docs/axi_ltc2387: Update doc

Signed-off-by: Stanca Pop <[email protected]>

Author: StancaPop

docs/library/axi_ltc2387/index.rst

@@ -7,8 +7,7 @@ AXI LTC2387
    :path: library/axi_ltc2387
 
 The :git-hdl:`AXI LTC2387 <library/axi_ltc2387>` IP core can be used to
-interface :adi:`LTC2387-18`, :adi:`LTC2386-18`, :adi:`LTC2385-18` and
-:adi:`ADAQ23878` devices.
+interface :adi:`LTC2387-18`, :adi:`LTC2387-16` and :adi:`ADAQ23878` devices.
 
 This documentation only covers the IP core and requires that one must be
 familiar with the device for a complete and better understanding.
@@ -74,15 +73,10 @@ From the HDL perspective, the selection between the 16-bit and the 18-bit
 version of the chip, is done by the `ADC_RES` and `OUT_RES` parameters of
 the modules.
 
-* For the 18-bit, ADC_RES=18 (=> OUT_RES=32; addresses should be on a nb. of
+* For the 18-bit, ADC_RES=18 (=> OUT_RES=32; addresses should be on a no. of
   bits power of 2)
 * For the 16-bit, ADC_RES=16 (=> OUT_RES=16)
 
-.. warning::
-
-   When using the ONE LANE configuration (TWOLANES=0), the only resolution
-   supported is 18 bits!
-
 Detailed Description
 --------------------------------------------------------------------------------
 
@@ -143,7 +137,8 @@ system level.
 The :ref:`axi_ltc2387 interface` must be connected directly to the top file of
 the design, as I/O primitives are part of the IP.
 
-The example design uses a DMA to move the data from the output of the IP to memory.
+The example design uses a DMA to move the data from the output of the IP to
+memory.
 
 If the data needs to be processed in HDL before moving to the memory, it can be
 done at the output of the IP (at the system level) or inside the ADC interface
@@ -169,8 +164,7 @@ References
 * HDL project at :git-hdl:`projects/cn0577`
 * HDL project documentation at :ref:`cn0577`
 * :adi:`LTC2387-18` 18-bit 15 MSPS
-* :adi:`LTC2386-18` 18-bit 10 MSPS
-* :adi:`LTC2385-18` 18-bit 5 MSPS
+* :adi:`LTC2387-16` 16-bit 15 MSPS
 * :adi:`ADAQ23878` 18-bit 15 MSPS
 * :xilinx:`Zynq-7000 SoC Overview <support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf>`.
 * :xilinx:`Zynq-7000 SoC Packaging and Pinout <support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf>`.