ad9084_ebz: vcu118: Add support for single-link mode

Signed-off-by: Filip Gherman <[email protected]>

Author: Filip.Gherman

projects/ad9084_ebz/common/ad9084_ebz_bd.tcl

@@ -491,7 +491,7 @@ ad_ip_parameter axi_apollo_rx_dma CONFIG.MAX_BYTES_PER_BURST 4096
 ad_ip_parameter axi_apollo_rx_dma CONFIG.CYCLIC 0
 ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_data_width
 if {$ADI_PHY_SEL} {
-  ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_data_width
+  ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(1024, $adc_data_width)]
 } else {
   # Versal limitation
   ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $adc_data_width)]
@@ -592,7 +592,7 @@ ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_2D_TRANSFER 0
 ad_ip_parameter axi_apollo_tx_dma CONFIG.CYCLIC 1
 ad_ip_parameter axi_apollo_tx_dma CONFIG.MAX_BYTES_PER_BURST 4096
 if {$ADI_PHY_SEL} {
-  ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_SRC $dac_data_width
+  ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(1024, $dac_data_width)]
 } else {
   # Versal limitation
   ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(512, $dac_data_width)]
@@ -797,16 +797,24 @@ if {$ASYMMETRIC_A_B_MODE} {
   }
 } else {
   set max_lane_map {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23}
-  # set lane_map {}
-
-  # for {set i 0}  {$i < $RX_NUM_LINKS} {incr i} {
-  #   for {set j 0}  {$j < $RX_JESD_L} {incr j} {
-  #     set cur_lane [expr $i*$MAX_RX_LANES_PER_LINK+$j]
-  #     lappend lane_map [lindex $max_lane_map $cur_lane]
-  #   }
-  # }
+  set lane_map {}
+
+  for {set i 0}  {$i < $RX_NUM_LINKS} {incr i} {
+    for {set j 0}  {$j < $RX_JESD_L} {incr j} {
+      set cur_lane [expr $i*$MAX_RX_LANES_PER_LINK+$j]
+      lappend lane_map [lindex $max_lane_map $cur_lane]
+    }
+  }
+
+  for {set i 0}  {$i < $RX_NUM_LINKS} {incr i} {
+    for {set j $RX_JESD_L}  {$j < $MAX_RX_LANES_PER_LINK} {incr j} {
+      set cur_lane [expr $i*$MAX_RX_LANES_PER_LINK+$j]
+      lappend lane_map [lindex $max_lane_map $cur_lane]
+    }
+  }
+
   if {$ADI_PHY_SEL} {
-    ad_xcvrcon  util_apollo_xcvr axi_apollo_rx_xcvr axi_apollo_rx_jesd $max_lane_map {} rx_device_clk $MAX_RX_LANES
+    ad_xcvrcon  util_apollo_xcvr axi_apollo_rx_xcvr axi_apollo_rx_jesd $lane_map {} rx_device_clk $MAX_RX_LANES
     create_bd_port -dir I rx_sysref_12
     create_bd_port -dir O rx_sync_12
   }
@@ -828,16 +836,34 @@ if {$ASYMMETRIC_A_B_MODE} {
   }
 } else {
   set max_lane_map {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23}
-  # set lane_map {}
-
-  # for {set i 0}  {$i < $TX_NUM_LINKS} {incr i} {
-  #   for {set j 0}  {$j < $TX_JESD_L} {incr j} {
-  #     set cur_lane [expr $i*$MAX_TX_LANES_PER_LINK+$j]
-  #     lappend lane_map [lindex $max_lane_map $cur_lane]
-  #   }
-  # }
+  set lane_map {}
+
+ for {set i 0}  {$i < $TX_NUM_LINKS} {incr i} {
+    for {set j 0}  {$j < $TX_JESD_L} {incr j} {
+      set cur_lane [expr $i*$MAX_TX_LANES_PER_LINK+$j]
+      lappend lane_map [lindex $max_lane_map $cur_lane]
+    }
+  }
+
+  for {set i 0}  {$i < $TX_NUM_LINKS} {incr i} {
+    for {set j $TX_JESD_L}  {$j < $MAX_TX_LANES_PER_LINK} {incr j} {
+      set cur_lane [expr $i*$MAX_TX_LANES_PER_LINK+$j]
+      lappend lane_map [lindex $max_lane_map $cur_lane]
+    }
+  }
+
   if {$ADI_PHY_SEL} {
-    ad_xcvrcon  util_apollo_xcvr axi_apollo_tx_xcvr axi_apollo_tx_jesd $max_lane_map {} tx_device_clk $MAX_TX_LANES
+    ad_xcvrcon  util_apollo_xcvr axi_apollo_tx_xcvr axi_apollo_tx_jesd $lane_map {} tx_device_clk $MAX_TX_LANES
+
+    if {$TX_JESD_L == 8} {
+      delete_bd_objs [get_bd_intf_nets axi_apollo_tx_xcvr_up_cm_8]
+      delete_bd_objs [get_bd_intf_nets axi_apollo_tx_xcvr_up_cm_12]
+      connect_bd_intf_net [get_bd_intf_pins axi_apollo_tx_xcvr/up_cm_8] [get_bd_intf_pins util_apollo_xcvr/up_cm_12]
+      connect_bd_intf_net [get_bd_intf_pins axi_apollo_tx_xcvr/up_cm_12] [get_bd_intf_pins util_apollo_xcvr/up_cm_16]
+    } elseif {$TX_JESD_L == 4} {
+      delete_bd_objs [get_bd_intf_nets axi_apollo_tx_xcvr_up_cm_4]
+      connect_bd_intf_net [get_bd_intf_pins axi_apollo_tx_xcvr/up_cm_4] [get_bd_intf_pins util_apollo_xcvr/up_cm_12]
+    }
     create_bd_port -dir I tx_sysref_12
     create_bd_port -dir I tx_sync_12
   }

projects/ad9084_ebz/vcu118/system_project.tcl

@@ -48,15 +48,15 @@ adi_project ad9084_ebz_vcu118 0 [list \
   RX_JESD_L           [get_env_param RX_JESD_L            8 ] \
   RX_JESD_S           [get_env_param RX_JESD_S            1 ] \
   RX_JESD_NP          [get_env_param RX_JESD_NP          16 ] \
-  RX_NUM_LINKS        [get_env_param RX_NUM_LINKS         1 ] \
+  RX_NUM_LINKS        [get_env_param RX_NUM_LINKS         2 ] \
   TX_JESD_M           [get_env_param TX_JESD_M            4 ] \
   TX_JESD_L           [get_env_param TX_JESD_L            8 ] \
   TX_JESD_S           [get_env_param TX_JESD_S            1 ] \
   TX_JESD_NP          [get_env_param TX_JESD_NP          16 ] \
-  TX_NUM_LINKS        [get_env_param TX_NUM_LINKS         1 ] \
+  TX_NUM_LINKS        [get_env_param TX_NUM_LINKS         2 ] \
   RX_KS_PER_CHANNEL   [get_env_param RX_KS_PER_CHANNEL   32 ] \
   TX_KS_PER_CHANNEL   [get_env_param TX_KS_PER_CHANNEL   32 ] \
-  ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE  1 ] \
+  ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE  0 ] \
   RX_B_LANE_RATE      [get_env_param RX_B_LANE_RATE  20.625 ] \
   TX_B_LANE_RATE      [get_env_param TX_B_LANE_RATE  20.625 ] \
   RX_B_JESD_M         [get_env_param RX_B_JESD_M          4 ] \

projects/ad9084_ebz/vcu118/system_top.v

@@ -36,9 +36,9 @@
 `timescale 1ns/100ps
 
 module system_top #(
-  parameter TX_NUM_LINKS = 1,
-  parameter RX_NUM_LINKS = 1,
-  parameter ASYMMETRIC_A_B_MODE = 1
+  parameter TX_NUM_LINKS = 2,
+  parameter RX_NUM_LINKS = 2,
+  parameter ASYMMETRIC_A_B_MODE = 0
 ) (
   input         sys_rst,
   input         sys_clk_p,