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Set M 2023b and V 2023.2
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9 files changed

+13
-14
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9 files changed

+13
-14
lines changed

+adi/Version.m

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
% Version
33
% BSP Version information
44
properties (Constant)
5-
Vivado = '2022.2'
6-
MATLAB = 'R2022a'
5+
Vivado = getenv('req_vivado_v')
6+
MATLAB = getenv('req_matlab_v')
77
Release = '21.2.1'
88
AppName = 'Analog Devices, Inc. Precision Toolbox'
99
ToolboxName = 'PrecisionToolbox'

CI/scripts_hdl/matlab_processors.tcl

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -47,9 +47,9 @@ proc preprocess_bd {project carrier rxtx} {
4747
}
4848
switch $carrier {
4949
zed {
50-
set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect]
51-
connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK] [get_bd_pins axi_clkgen/clk_0]
52-
connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
50+
set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_gp0_interconnect]
51+
connect_bd_net [get_bd_pins axi_gp0_interconnect/M20_ACLK] [get_bd_pins axi_clkgen/clk_0]
52+
connect_bd_net [get_bd_pins axi_gp0_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
5353
}
5454
}
5555
}

hdl/vendor/AnalogDevices/+AnalogDevices/get_memory_axi_interface_info.m

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
case 'cn0585'
66
switch fpga
77
case{'ZED'}
8-
InterfaceConnection = 'axi_cpu_interconnect/M20_AXI';
8+
InterfaceConnection = 'axi_gp0_interconnect/M20_AXI';
99
BaseAddress = '0x43C00000';
1010
MasterAddressSpace = 'sys_ps7/Data';
1111
otherwise

hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020
hRD.BoardName = sprintf('AnalogDevices %s %s', pname, upper(board));
2121

2222
% Tool information
23-
hRD.SupportedToolVersion = {'2022.2'};
23+
hRD.SupportedToolVersion = {'2023.2'};
2424

2525
% Get the root directory
2626
rootDir = fileparts(strtok(mfilename('fullpath'), '+'));

pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121
hRD.BoardName = sprintf('AnalogDevices CN0585 GPIO Control');
2222

2323
% Tool information
24-
hRD.SupportedToolVersion = {'2023.2'};
24+
hRD.SupportedToolVersion = {getenv('req_vivado_v')};
2525

2626
% Get the root directories
2727
rootDirExample = fileparts(strtok(mfilename('fullpath'), '+'));

pcx_examples/targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ function add_tx_io(hRD)
22

33
% add AXI4 and AXI4-Lite slave interfaces
44
hRD.addAXI4SlaveInterface( ...
5-
'InterfaceConnection', 'axi_cpu_interconnect/M20_AXI', ...
5+
'InterfaceConnection', 'axi_gp0_interconnect/M20_AXI', ...
66
'BaseAddress', '0x43C00000', ...
77
'MasterAddressSpace', 'sys_ps7/Data');
88

pcx_examples/targeting/cn0585/cn0585_hdl/build_bsp.sh

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,7 @@ fi
4444
VIVADO=${VER}
4545

4646
# Setup
47-
#source /opt/Xilinx/Vivado/$VIVADO/settings64.sh
48-
source /emea/mediadata/opt/Xilinx/Vivado/$VIVADO/settings64.sh
47+
source "$vivado_settings_path"
4948

5049
# Rename .prj files since MATLAB ignores then during packaging
5150
FILES=$(grep -lrn hdl/projects/common -e '.prj' | grep -v Makefile | grep -v .git)

test/BSPTestsBase.m

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,7 @@ function setVivadoPath(~,vivado)
160160
if ispc
161161
pathname = ['C:\Xilinx\Vivado\',vivado,'\bin\vivado.bat'];
162162
elseif isunix
163-
pathname = ['/emea/mediadata/opt/Xilinx/Vivado/',vivado,'/bin/vivado'];
163+
pathname = ['/opt/Xilinx/Vivado/',vivado,'/bin/vivado'];
164164
end
165165
end
166166
assert(exist(pathname,'file')>0,'Correct version of Vivado is unavailable or in a non-standard location');
@@ -203,4 +203,4 @@ function testMain(testCase, configs, SynthesizeDesign)
203203
end
204204
end
205205
end
206-
end
206+
end

test/build_design.m

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929

3030
% Specify the top level project directory
3131
hWC.ProjectFolder = folder;
32-
hWC.ReferenceDesignToolVersion = '2023.2';
32+
hWC.ReferenceDesignToolVersion = getenv('req_vivado_v');
3333
hWC.IgnoreToolVersionMismatch = true;
3434
hWC.AllowUnsupportedToolVersion = true;
3535

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