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Description
The following input code
from amaranth import *
from amaranth.back import rtlil
m = Module()
a = Signal(name="a a")
rtlil.convert(m, ports=[a])
Generates the output
module \top
wire width 1 input 0 \a a
end
which is invalid, according to https://yosyshq.readthedocs.io/projects/yosys/en/v0.48/yosys_internals/formats/rtlil_rep.html#rtlil-identifiers.
Furthermore yosys cannot read this output, generating the following error:
Input filename: /tmp/.il
ERROR: Parser error in line 2: syntax error