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edecouxwhitequark
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add redpitaya board definition
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amaranth_boards/redpitaya_125_14.py

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import os
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import subprocess
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from amaranth.build import *
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from amaranth.vendor import XilinxPlatform
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from .resources import *
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__all__ = ["RedPitaya14Platform"]
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class RedPitaya14Platform(XilinxPlatform):
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device = "xc7z010"
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package = "clg400"
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speed = "1"
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default_clk = "clk125"
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resources = [
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Resource("clk125", 0,
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DiffPairs("U18", "U19", dir="i"), Clock(125e6), Attrs(IOSTANDARD="TMDS_33")),
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*LEDResources(
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pins="F16 F17 G15 H15 K14 G14 J15 J14",
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attrs=Attrs(IOSTANDARD="LVCMOS33")),
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Resource("daisy_io", 0,
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DiffPairs("T12", "U12", dir="i"), Attrs(IOSTANDARD="TMDS_33")),
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Resource("daisy_io", 1,
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DiffPairs("U14", "U15", dir="i"), Attrs(IOSTANDARD="TMDS_33")),
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Resource("daisy_io", 2,
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DiffPairs("P14", "R14", dir="i"), Attrs(IOSTANDARD="TMDS_33")),
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Resource("daisy_io", 3,
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DiffPairs("N18", "P19", dir="i"), Attrs(IOSTANDARD="TMDS_33")),
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]
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connectors = [
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Connector("E1", 0, {
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# Outer Analog Header
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"dio0_p": "G17",
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"dio0_n": "G18",
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"dio1_p": "H16",
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"dio1_n": "H17",
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"dio2_p": "J18",
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"dio2_n": "H18",
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"dio3_p": "K17",
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"dio3_n": "K18",
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"dio4_p": "L14",
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"dio4_n": "L15",
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"dio5_p": "L16",
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"dio5_n": "L17",
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"dio6_p": "K16",
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"dio6_n": "J16",
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"dio7_p": "M14",
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"dio7_n": "M15",
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})
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]
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def toolchain_program(self, products, name, **kwargs):
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with products.extract("{}.bit".format(name)) as bitstream_filename:
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subprocess.check_call(["openFPGALoader", "-c", "digilent_hs2", bitstream_filename])
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if __name__ == "__main__":
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from .test.blinky import *
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RedPitaya14Platform().build(Blinky(), do_program=True)

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