-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathNWI_108A1.qsf
85 lines (83 loc) · 4.26 KB
/
NWI_108A1.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
# Date created = 12:14:19 November 18, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# NWI_108A1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY NWI_108A1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:14:19 NOVEMBER 18, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_FILE NWI_108A1.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE ALU.vhd
set_global_assignment -name VHDL_FILE CPU.vhd
set_global_assignment -name VHDL_FILE MEMORY.vhd
set_global_assignment -name VHDL_FILE INSTRUCTS.vhd
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_FILE INTERRUPT.vhd
set_global_assignment -name VHDL_FILE TIMER.vhd
set_global_assignment -name VHDL_FILE UART.vhd
set_global_assignment -name VHDL_FILE CLK_GEN.vhd
set_global_assignment -name VHDL_FILE BUS_MASTER.vhd
set_global_assignment -name QIP_FILE ROM.qip
set_global_assignment -name QIP_FILE RAM.qip
set_global_assignment -name VHDL_FILE BUS_SLAVE.vhd
set_global_assignment -name VHDL_FILE IO_PORT.vhd
set_location_assignment PIN_A15 -to pins[0]
set_location_assignment PIN_A13 -to pins[1]
set_location_assignment PIN_B13 -to pins[2]
set_location_assignment PIN_A11 -to pins[3]
set_location_assignment PIN_D1 -to pins[4]
set_location_assignment PIN_F3 -to pins[5]
set_location_assignment PIN_B1 -to pins[6]
set_location_assignment PIN_L3 -to pins[7]
set_location_assignment PIN_J15 -to rst
set_location_assignment PIN_R8 -to clk
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top