Write a System Verilog code to implement wallace tree reduction for a 5x5 multiplier

[cuber2116]

A structure for the 5x5 wallace tree multiplier has been provided in diagram.md in Wallace5x5 folder.
Write a code for wallace_tree_reduction.sv in Wallace5x5 folder.
Implementing adder+Working Test bench = 350 points

[gaganbrwj]

can you please assign me this

[Web-dev-learner1]

Can you assign this to me?

[cuber2116]

!assign @gaganbrwj 60m

[cuber2116]

!assign @gaganbrwj 90

[gaganbrwj]

okay i am done with the code of .sv files i should code the testbench files now

module wallace_tree_reduction (
input logic [4:0] a, // 5-bit input a
input logic [4:0] b, // 5-bit input b
output logic [9:0] product // 10-bit product
);

logic [4:0][4:0] partial_products; // 5 partial products (5x5)

// Step 1: Generate partial products
genvar i, j;
generate
    for (i = 0; i < 5; i++) begin
        for (j = 0; j < 5; j++) begin
            assign partial_products[i][j] = a[i] & b[j];
        end
    end
endgenerate

// Step 2: Wallace tree reduction using full and half adders
logic [9:0] sum_stage1, carry_stage1;
logic [9:0] sum_stage2, carry_stage2;
logic [9:0] final_sum, final_carry;

// First stage of reduction
// (Add intermediate logic for full adders and half adders, summing the partial products)
// This is the core of Wallace tree logic where you will reduce the rows using adders.
// Use full_adder and half_adder for different bits.

// Stage 1 reduction (example logic, expand for the full multiplier)
half_adder ha1(partial_products[0][1], partial_products[1][0], sum_stage1[1], carry_stage1[1]);
full_adder fa1(partial_products[0][2], partial_products[1][1], partial_products[2][0], sum_stage1[2], carry_stage1[2]);

// Stage 2 and so on for the entire tree...

// Step 3: Final addition of sums and carry
assign product = final_sum + (final_carry << 1);

endmodule

// Full adder module
module full_adder(
input logic a, b, cin,
output logic sum, cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (cin & a);
endmodule

// Half adder module
module half_adder(
input logic a, b,
output logic sum, cout
);
assign sum = a ^ b;
assign cout = a & b;
endmodule

[cuber2116]

!assign @gaganbrwj

[cuber2116]

@gaganbrwj open a PR

[gaganbrwj]

huh? this is the code to implement wallace tree reduction for a 5x5 multiplier
and thts wht i was assigned

[gaganbrwj]

i have now written testbench files also to it

[cuber2116]

@gaganbrwj the bot didn't assign it to you because you were assigned some other issue initially

[cuber2116]

!assign @gaganbrwj

[cuber2116]

Now it's been assigned @gaganbrwj please open PR, don't submit the code here

[gaganbrwj]

okay am i assigned to this issue now ?

[cuber2116]

Yes

[bunsamosa-bot]

Hey @cuber2116! The timer for the @gaganbrwj to work on the issue has finished, deassign and assign a new contributor or extend the current timer. Contact maintainer leads if inactive @DedLad @polarhive @achyuthcodes30

[gaganbrwj]

Now it's been assigned @gaganbrwj please open PR, don't submit the code here

okay got it

[cuber2116]

@gaganbrwj did you finish?

[gaganbrwj]

the codes are ready but there are errors and i am pulling the request now

[cuber2116]

!assign @gaganbrwj 30

[cuber2116]

@gaganbrwj you have 30 more mins

[gaganbrwj]

i am so sorry theres problem in pulling request
give me 15 more min maybe ill be able to do it

[cuber2116]

!assign @gaganbrwj 20

[gaganbrwj]

assign me some more time please

[cuber2116]

!assign @gaganbrwj 60

[kavin81]

@cuber2116 can you assign me ?

[cuber2116]

!assign @kavin81 90

[cuber2116]

@kavin81 I think you've been assigned to a different issue so please make sure that they deassign you first so that I can assign this to you