UNRATIFIED RISC-V: Add 'Zcmop' extension

[DO NOT MERGE]
Until the 'Zcmop' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream. This commit uses
version 0.1 as a placeholder.

This commit adds support for the compressed "May Be Operations (MOP)"
(Zcmop) extension which adds 8 compressed MOP instructions.
By default, they are the same as NOP.  However, if certain feature is
supported (and optionally enabled), it is allowed to alter
architectural state unlike HINT instructions.

This commit is based on the TENTATIVE specification:
<riscv/riscv-cfi#131>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zcmop' -> 'Zca'
	implication.  (riscv_supported_std_z_ext): Add 'Zcmop'.
	(riscv_multi_subset_supports): Support new instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zcmop.s: New test for 'Zcmop'.
	* testsuite/gas/riscv/zcmop.d: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (
	MATCH_C_MOP_0, MASK_C_MOP_0, MATCH_C_MOP_1, MASK_C_MOP_1,
	MATCH_C_MOP_2, MASK_C_MOP_2, MATCH_C_MOP_3, MASK_C_MOP_3,
	MATCH_C_MOP_4, MASK_C_MOP_4, MATCH_C_MOP_5, MASK_C_MOP_5,
	MATCH_C_MOP_6, MASK_C_MOP_6, MATCH_C_MOP_7, MASK_C_MOP_7): New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	class INSN_CLASS_ZCMOP.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add new "may be" operations from
	the 'Zcmop' extension near the bottom.

Author: a4lg

bfd/elfxx-riscv.c

@@ -1182,6 +1182,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zcf", "zca",	check_implicit_always},
   {"zcd", "zca",	check_implicit_always},
   {"zcb", "zca",	check_implicit_always},
+  {"zcmop", "zca",	check_implicit_always},
   {"smaia", "ssaia",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
@@ -1322,6 +1323,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zcb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zcf",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zcd",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zcmop",		ISA_SPEC_CLASS_DRAFT,		0, 1,  0 },
   {NULL, 0, 0, 0, 0}
 };
 
@@ -2527,6 +2529,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_ZCB_AND_ZMMUL:
       return (riscv_subset_supports (rps, "zcb")
 	      && riscv_subset_supports (rps, "zmmul"));
+    case INSN_CLASS_ZCMOP:
+      return riscv_subset_supports (rps, "zcmop");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2745,6 +2749,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zcb' and `zbb");
     case INSN_CLASS_ZCB_AND_ZMMUL:
       return _("zcb' and `zmmul', or `zcb' and `m");
+    case INSN_CLASS_ZCMOP:
+      return "zcmop";
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:

gas/testsuite/gas/riscv/zcmop.d

@@ -0,0 +1,16 @@
+#as: -march=rv32i_zcmop
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+c\.mop\.0
+[ 	]+[0-9a-f]+:[ 	]+6181[ 	]+c\.mop\.1
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+c\.mop\.2
+[ 	]+[0-9a-f]+:[ 	]+6381[ 	]+c\.mop\.3
+[ 	]+[0-9a-f]+:[ 	]+6481[ 	]+c\.mop\.4
+[ 	]+[0-9a-f]+:[ 	]+6581[ 	]+c\.mop\.5
+[ 	]+[0-9a-f]+:[ 	]+6681[ 	]+c\.mop\.6
+[ 	]+[0-9a-f]+:[ 	]+6781[ 	]+c\.mop\.7

gas/testsuite/gas/riscv/zcmop.s

@@ -0,0 +1,9 @@
+target:
+	c.mop.0
+	c.mop.1
+	c.mop.2
+	c.mop.3
+	c.mop.4
+	c.mop.5
+	c.mop.6
+	c.mop.7

include/opcode/riscv-opc.h

@@ -2384,6 +2384,23 @@
 #define MASK_WRS_NTO 0xffffffff
 #define MATCH_WRS_STO 0x01d00073
 #define MASK_WRS_STO 0xffffffff
+/* Zcmop "may be" operations.  */
+#define MATCH_C_MOP_0 0x6081
+#define MASK_C_MOP_0 0xffff
+#define MATCH_C_MOP_1 0x6181
+#define MASK_C_MOP_1 0xffff
+#define MATCH_C_MOP_2 0x6281
+#define MASK_C_MOP_2 0xffff
+#define MATCH_C_MOP_3 0x6381
+#define MASK_C_MOP_3 0xffff
+#define MATCH_C_MOP_4 0x6481
+#define MASK_C_MOP_4 0xffff
+#define MATCH_C_MOP_5 0x6581
+#define MASK_C_MOP_5 0xffff
+#define MATCH_C_MOP_6 0x6681
+#define MASK_C_MOP_6 0xffff
+#define MATCH_C_MOP_7 0x6781
+#define MASK_C_MOP_7 0xffff
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 #define MATCH_TH_ADDSL 0x0000100b
 #define MASK_TH_ADDSL 0xf800707f
@@ -3527,6 +3544,15 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU)
 DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH)
 DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB)
 DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH)
+/* Zcmop "may be" operations.  */
+DECLARE_INSN(c_mop_0, MATCH_C_MOP_0, MASK_C_MOP_0)
+DECLARE_INSN(c_mop_1, MATCH_C_MOP_1, MASK_C_MOP_1)
+DECLARE_INSN(c_mop_2, MATCH_C_MOP_2, MASK_C_MOP_2)
+DECLARE_INSN(c_mop_3, MATCH_C_MOP_3, MASK_C_MOP_3)
+DECLARE_INSN(c_mop_4, MATCH_C_MOP_4, MASK_C_MOP_4)
+DECLARE_INSN(c_mop_5, MATCH_C_MOP_5, MASK_C_MOP_5)
+DECLARE_INSN(c_mop_6, MATCH_C_MOP_6, MASK_C_MOP_6)
+DECLARE_INSN(c_mop_7, MATCH_C_MOP_7, MASK_C_MOP_7)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */

include/opcode/riscv.h

@@ -436,6 +436,7 @@ enum riscv_insn_class
   INSN_CLASS_ZCB_AND_ZBA,
   INSN_CLASS_ZCB_AND_ZBB,
   INSN_CLASS_ZCB_AND_ZMMUL,
+  INSN_CLASS_ZCMOP,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,

opcodes/riscv-opc.c

@@ -2009,6 +2009,16 @@ const struct riscv_opcode riscv_opcodes[] =
 {"mop.rr.6",  0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_6, MASK_MOP_RR_6, match_opcode, 0 },
 {"mop.rr.7",  0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_7, MASK_MOP_RR_7, match_opcode, 0 },
 
+/* Zcmop "may be" operations.  */
+{"c.mop.0",   0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_0, MASK_C_MOP_0, match_opcode, 0 },
+{"c.mop.1",   0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_1, MASK_C_MOP_1, match_opcode, 0 },
+{"c.mop.2",   0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_2, MASK_C_MOP_2, match_opcode, 0 },
+{"c.mop.3",   0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_3, MASK_C_MOP_3, match_opcode, 0 },
+{"c.mop.4",   0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_4, MASK_C_MOP_4, match_opcode, 0 },
+{"c.mop.5",   0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_5, MASK_C_MOP_5, match_opcode, 0 },
+{"c.mop.6",   0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_6, MASK_C_MOP_6, match_opcode, 0 },
+{"c.mop.7",   0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_7, MASK_C_MOP_7, match_opcode, 0 },
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },