From f40410c7fb52da13f1798e022367fb70f4e14b9d Mon Sep 17 00:00:00 2001 From: Taylor Hillegeist Date: Tue, 4 Feb 2025 10:48:07 -0600 Subject: [PATCH] Add Support for non-constant stride field arrays. (STM32) (#377) Co-authored-by: Matt Knight --- port/stmicro/stm32/src/chips/all.zig | 1301 +++++++++++++++++++++----- port/stmicro/stm32/src/generate.zig | 36 +- 2 files changed, 1105 insertions(+), 232 deletions(-) diff --git a/port/stmicro/stm32/src/chips/all.zig b/port/stmicro/stm32/src/chips/all.zig index d4079d02..8664091b 100644 --- a/port/stmicro/stm32/src/chips/all.zig +++ b/port/stmicro/stm32/src/chips/all.zig @@ -314342,14 +314342,21 @@ pub const types = struct { /// FDCAN Interrupt Register IR: mmio.Mmio(packed struct(u32) { /// Rx FIFO X New Message - RFN: u1, + @"RFN[0]": u1, /// Rx FIFO X Watermark Reached - RFW: u1, + @"RFW[0]": u1, /// Rx FIFO X Full - RFF: u1, + @"RFF[0]": u1, /// Rx FIFO X Message Lost - RFL: u1, - reserved8: u4, + @"RFL[0]": u1, + /// Rx FIFO X New Message + @"RFN[1]": u1, + /// Rx FIFO X Watermark Reached + @"RFW[1]": u1, + /// Rx FIFO X Full + @"RFF[1]": u1, + /// Rx FIFO X Message Lost + @"RFL[1]": u1, /// High Priority Message HPM: u1, /// Transmission Completed @@ -314396,14 +314403,21 @@ pub const types = struct { /// FDCAN Interrupt Enable Register IE: mmio.Mmio(packed struct(u32) { /// Rx FIFO X New Message Enable - RFNE: u1, + @"RFNE[0]": u1, /// Rx FIFO X Watermark Reached Enable - RFWE: u1, + @"RFWE[0]": u1, /// Rx FIFO X Full Enable - RFFE: u1, + @"RFFE[0]": u1, /// Rx FIFO X Message Lost Enable - RFLE: u1, - reserved8: u4, + @"RFLE[0]": u1, + /// Rx FIFO X New Message Enable + @"RFNE[1]": u1, + /// Rx FIFO X Watermark Reached Enable + @"RFWE[1]": u1, + /// Rx FIFO X Full Enable + @"RFFE[1]": u1, + /// Rx FIFO X Message Lost Enable + @"RFLE[1]": u1, /// High Priority Message Enable HPME: u1, /// Transmission Completed Enable @@ -314453,14 +314467,21 @@ pub const types = struct { /// FDCAN Interrupt Line Select Register ILS: mmio.Mmio(packed struct(u32) { /// Rx FIFO X New Message Interrupt Line - RFNL: u1, + @"RFNL[0]": u1, /// Rx FIFO X Watermark Reached Interrupt Line - RFWL: u1, + @"RFWL[0]": u1, /// Rx FIFO X Full Interrupt Line - RFFL: u1, + @"RFFL[0]": u1, /// Rx FIFO X Message Lost Interrupt Line - RFLL: u1, - reserved8: u4, + @"RFLL[0]": u1, + /// Rx FIFO X New Message Interrupt Line + @"RFNL[1]": u1, + /// Rx FIFO X Watermark Reached Interrupt Line + @"RFWL[1]": u1, + /// Rx FIFO X Full Interrupt Line + @"RFFL[1]": u1, + /// Rx FIFO X Message Lost Interrupt Line + @"RFLL[1]": u1, /// High Priority Message Interrupt Line HPML: u1, /// Transmission Completed Interrupt Line @@ -314622,8 +314643,11 @@ pub const types = struct { /// FDCAN Rx Buffer Element Size Configuration Register RXESC: mmio.Mmio(packed struct(u32) { /// Rx FIFO X Data Field Size - FDS: u3, - reserved8: u5, + @"FDS[0]": u3, + reserved4: u1, + /// Rx FIFO X Data Field Size + @"FDS[1]": u3, + reserved8: u1, /// Rx Buffer Data Field Size RBDS: u3, padding: u21, @@ -315812,12 +315836,17 @@ pub const types = struct { /// FDCAN interrupt register IR: mmio.Mmio(packed struct(u32) { /// Rx FIFO X new message - RFN: u1, + @"RFN[0]": u1, /// Rx FIFO X full - RFF: u1, + @"RFF[0]": u1, /// Rx FIFO X message lost - RFL: u1, - reserved6: u3, + @"RFL[0]": u1, + /// Rx FIFO X new message + @"RFN[1]": u1, + /// Rx FIFO X full + @"RFF[1]": u1, + /// Rx FIFO X message lost + @"RFL[1]": u1, /// High-priority message HPM: u1, /// Transmission completed @@ -315859,12 +315888,17 @@ pub const types = struct { /// FDCAN interrupt enable register IE: mmio.Mmio(packed struct(u32) { /// Rx FIFO X new message interrupt enable - RFNE: u1, + @"RFNE[0]": u1, /// Rx FIFO X full interrupt enable - RFFE: u1, + @"RFFE[0]": u1, /// Rx FIFO X message lost interrupt enable - RFLE: u1, - reserved6: u3, + @"RFLE[0]": u1, + /// Rx FIFO X new message interrupt enable + @"RFNE[1]": u1, + /// Rx FIFO X full interrupt enable + @"RFFE[1]": u1, + /// Rx FIFO X message lost interrupt enable + @"RFLE[1]": u1, /// High-priority message interrupt enable HPME: u1, /// Transmission completed interrupt enable @@ -322433,32 +322467,100 @@ pub const types = struct { /// low interrupt status register ISR: [2]mmio.Mmio(packed struct(u32) { /// Stream x FIFO error interrupt flag (x=3..0) - FEIF: u1, + @"FEIF[0]": u1, reserved2: u1, /// Stream x direct mode error interrupt flag (x=3..0) - DMEIF: u1, + @"DMEIF[0]": u1, /// Stream x transfer error interrupt flag (x=3..0) - TEIF: u1, + @"TEIF[0]": u1, /// Stream x half transfer interrupt flag (x=3..0) - HTIF: u1, + @"HTIF[0]": u1, /// Stream x transfer complete interrupt flag (x = 3..0) - TCIF: u1, - padding: u26, + @"TCIF[0]": u1, + /// Stream x FIFO error interrupt flag (x=3..0) + @"FEIF[1]": u1, + reserved8: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + @"DMEIF[1]": u1, + /// Stream x transfer error interrupt flag (x=3..0) + @"TEIF[1]": u1, + /// Stream x half transfer interrupt flag (x=3..0) + @"HTIF[1]": u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + @"TCIF[1]": u1, + reserved16: u4, + /// Stream x FIFO error interrupt flag (x=3..0) + @"FEIF[2]": u1, + reserved18: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + @"DMEIF[2]": u1, + /// Stream x transfer error interrupt flag (x=3..0) + @"TEIF[2]": u1, + /// Stream x half transfer interrupt flag (x=3..0) + @"HTIF[2]": u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + @"TCIF[2]": u1, + /// Stream x FIFO error interrupt flag (x=3..0) + @"FEIF[3]": u1, + reserved24: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + @"DMEIF[3]": u1, + /// Stream x transfer error interrupt flag (x=3..0) + @"TEIF[3]": u1, + /// Stream x half transfer interrupt flag (x=3..0) + @"HTIF[3]": u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + @"TCIF[3]": u1, + padding: u4, }), /// low interrupt flag clear register IFCR: [2]mmio.Mmio(packed struct(u32) { /// Stream x FIFO error interrupt flag (x=3..0) - FEIF: u1, + @"FEIF[0]": u1, reserved2: u1, /// Stream x direct mode error interrupt flag (x=3..0) - DMEIF: u1, + @"DMEIF[0]": u1, /// Stream x transfer error interrupt flag (x=3..0) - TEIF: u1, + @"TEIF[0]": u1, + /// Stream x half transfer interrupt flag (x=3..0) + @"HTIF[0]": u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + @"TCIF[0]": u1, + /// Stream x FIFO error interrupt flag (x=3..0) + @"FEIF[1]": u1, + reserved8: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + @"DMEIF[1]": u1, + /// Stream x transfer error interrupt flag (x=3..0) + @"TEIF[1]": u1, /// Stream x half transfer interrupt flag (x=3..0) - HTIF: u1, + @"HTIF[1]": u1, /// Stream x transfer complete interrupt flag (x = 3..0) - TCIF: u1, - padding: u26, + @"TCIF[1]": u1, + reserved16: u4, + /// Stream x FIFO error interrupt flag (x=3..0) + @"FEIF[2]": u1, + reserved18: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + @"DMEIF[2]": u1, + /// Stream x transfer error interrupt flag (x=3..0) + @"TEIF[2]": u1, + /// Stream x half transfer interrupt flag (x=3..0) + @"HTIF[2]": u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + @"TCIF[2]": u1, + /// Stream x FIFO error interrupt flag (x=3..0) + @"FEIF[3]": u1, + reserved24: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + @"DMEIF[3]": u1, + /// Stream x transfer error interrupt flag (x=3..0) + @"TEIF[3]": u1, + /// Stream x half transfer interrupt flag (x=3..0) + @"HTIF[3]": u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + @"TCIF[3]": u1, + padding: u4, }), /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers ST: u32, @@ -322639,32 +322741,100 @@ pub const types = struct { /// low interrupt status register ISR: [2]mmio.Mmio(packed struct(u32) { /// Stream x FIFO error interrupt flag (x=3..0) - FEIF: u1, + @"FEIF[0]": u1, reserved2: u1, /// Stream x direct mode error interrupt flag (x=3..0) - DMEIF: u1, + @"DMEIF[0]": u1, /// Stream x transfer error interrupt flag (x=3..0) - TEIF: u1, + @"TEIF[0]": u1, /// Stream x half transfer interrupt flag (x=3..0) - HTIF: u1, + @"HTIF[0]": u1, /// Stream x transfer complete interrupt flag (x = 3..0) - TCIF: u1, - padding: u26, + @"TCIF[0]": u1, + /// Stream x FIFO error interrupt flag (x=3..0) + @"FEIF[1]": u1, + reserved8: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + @"DMEIF[1]": u1, + /// Stream x transfer error interrupt flag (x=3..0) + @"TEIF[1]": u1, + /// Stream x half transfer interrupt flag (x=3..0) + @"HTIF[1]": u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + @"TCIF[1]": u1, + reserved16: u4, + /// Stream x FIFO error interrupt flag (x=3..0) + @"FEIF[2]": u1, + reserved18: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + @"DMEIF[2]": u1, + /// Stream x transfer error interrupt flag (x=3..0) + @"TEIF[2]": u1, + /// Stream x half transfer interrupt flag (x=3..0) + @"HTIF[2]": u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + @"TCIF[2]": u1, + /// Stream x FIFO error interrupt flag (x=3..0) + @"FEIF[3]": u1, + reserved24: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + @"DMEIF[3]": u1, + /// Stream x transfer error interrupt flag (x=3..0) + @"TEIF[3]": u1, + /// Stream x half transfer interrupt flag (x=3..0) + @"HTIF[3]": u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + @"TCIF[3]": u1, + padding: u4, }), /// low interrupt flag clear register IFCR: [2]mmio.Mmio(packed struct(u32) { /// Stream x FIFO error interrupt flag (x=3..0) - FEIF: u1, + @"FEIF[0]": u1, reserved2: u1, /// Stream x direct mode error interrupt flag (x=3..0) - DMEIF: u1, + @"DMEIF[0]": u1, /// Stream x transfer error interrupt flag (x=3..0) - TEIF: u1, + @"TEIF[0]": u1, /// Stream x half transfer interrupt flag (x=3..0) - HTIF: u1, + @"HTIF[0]": u1, /// Stream x transfer complete interrupt flag (x = 3..0) - TCIF: u1, - padding: u26, + @"TCIF[0]": u1, + /// Stream x FIFO error interrupt flag (x=3..0) + @"FEIF[1]": u1, + reserved8: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + @"DMEIF[1]": u1, + /// Stream x transfer error interrupt flag (x=3..0) + @"TEIF[1]": u1, + /// Stream x half transfer interrupt flag (x=3..0) + @"HTIF[1]": u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + @"TCIF[1]": u1, + reserved16: u4, + /// Stream x FIFO error interrupt flag (x=3..0) + @"FEIF[2]": u1, + reserved18: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + @"DMEIF[2]": u1, + /// Stream x transfer error interrupt flag (x=3..0) + @"TEIF[2]": u1, + /// Stream x half transfer interrupt flag (x=3..0) + @"HTIF[2]": u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + @"TCIF[2]": u1, + /// Stream x FIFO error interrupt flag (x=3..0) + @"FEIF[3]": u1, + reserved24: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + @"DMEIF[3]": u1, + /// Stream x transfer error interrupt flag (x=3..0) + @"TEIF[3]": u1, + /// Stream x half transfer interrupt flag (x=3..0) + @"HTIF[3]": u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + @"TCIF[3]": u1, + padding: u4, }), /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers ST: u32, @@ -350770,26 +350940,74 @@ pub const types = struct { /// High Resolution Timer: Output Enable Register OENR: mmio.Mmio(packed struct(u32) { /// Timer X Output Enable - T1OEN: u1, + @"T1OEN[0]": u1, /// Timer X Complementary Output Enable - T2OEN: u1, - padding: u30, + @"T2OEN[0]": u1, + /// Timer X Output Enable + @"T1OEN[1]": u1, + /// Timer X Complementary Output Enable + @"T2OEN[1]": u1, + /// Timer X Output Enable + @"T1OEN[2]": u1, + /// Timer X Complementary Output Enable + @"T2OEN[2]": u1, + /// Timer X Output Enable + @"T1OEN[3]": u1, + /// Timer X Complementary Output Enable + @"T2OEN[3]": u1, + /// Timer X Output Enable + @"T1OEN[4]": u1, + /// Timer X Complementary Output Enable + @"T2OEN[4]": u1, + padding: u22, }), /// High Resolution Timer: Output Disable Register ODISR: mmio.Mmio(packed struct(u32) { /// Timer X Output Disable - T1ODIS: u1, + @"T1ODIS[0]": u1, /// Timer X Complementary Output Disable - T2ODIS: u1, - padding: u30, + @"T2ODIS[0]": u1, + /// Timer X Output Disable + @"T1ODIS[1]": u1, + /// Timer X Complementary Output Disable + @"T2ODIS[1]": u1, + /// Timer X Output Disable + @"T1ODIS[2]": u1, + /// Timer X Complementary Output Disable + @"T2ODIS[2]": u1, + /// Timer X Output Disable + @"T1ODIS[3]": u1, + /// Timer X Complementary Output Disable + @"T2ODIS[3]": u1, + /// Timer X Output Disable + @"T1ODIS[4]": u1, + /// Timer X Complementary Output Disable + @"T2ODIS[4]": u1, + padding: u22, }), /// High Resolution Timer: Output Disable Status Register ODSR: mmio.Mmio(packed struct(u32) { /// Timer X Output Disable Status - T1ODIS: u1, + @"T1ODIS[0]": u1, /// Timer X Complementary Output Disable Status - T2ODIS: u1, - padding: u30, + @"T2ODIS[0]": u1, + /// Timer X Output Disable Status + @"T1ODIS[1]": u1, + /// Timer X Complementary Output Disable Status + @"T2ODIS[1]": u1, + /// Timer X Output Disable Status + @"T1ODIS[2]": u1, + /// Timer X Complementary Output Disable Status + @"T2ODIS[2]": u1, + /// Timer X Output Disable Status + @"T1ODIS[3]": u1, + /// Timer X Complementary Output Disable Status + @"T2ODIS[3]": u1, + /// Timer X Output Disable Status + @"T1ODIS[4]": u1, + /// Timer X Complementary Output Disable Status + @"T2ODIS[4]": u1, + padding: u22, }), /// High Resolution Timer: Burst Mode Control Register BMCR: mmio.Mmio(packed struct(u32) { @@ -350838,14 +351056,46 @@ pub const types = struct { /// (4/4 of MSTCMP) Master Compare X @"MSTCMP[3]": u1, /// Timer X reset or roll-over - TRST: u1, + @"TRST[0]": u1, /// Timer X repetition - TREP: u1, + @"TREP[0]": u1, /// Timer X compare 1 event - TCMP1: u1, + @"TCMP1[0]": u1, /// Timer X compare 2 event - TCMP2: u1, - padding: u21, + @"TCMP2[0]": u1, + /// Timer X reset or roll-over + @"TRST[1]": u1, + /// Timer X repetition + @"TREP[1]": u1, + /// Timer X compare 1 event + @"TCMP1[1]": u1, + /// Timer X compare 2 event + @"TCMP2[1]": u1, + /// Timer X reset or roll-over + @"TRST[2]": u1, + /// Timer X repetition + @"TREP[2]": u1, + /// Timer X compare 1 event + @"TCMP1[2]": u1, + /// Timer X compare 2 event + @"TCMP2[2]": u1, + /// Timer X reset or roll-over + @"TRST[3]": u1, + /// Timer X repetition + @"TREP[3]": u1, + /// Timer X compare 1 event + @"TCMP1[3]": u1, + /// Timer X compare 2 event + @"TCMP2[3]": u1, + /// Timer X reset or roll-over + @"TRST[4]": u1, + /// Timer X repetition + @"TREP[4]": u1, + /// Timer X compare 1 event + @"TCMP1[4]": u1, + /// Timer X compare 2 event + @"TCMP2[4]": u1, + padding: u5, }), /// High Resolution Timer: Burst Mode Compare Register BMCMPR: mmio.Mmio(packed struct(u32) { @@ -350862,30 +351112,102 @@ pub const types = struct { /// High Resolution Timer: External Event Control Register 1 EECR1: mmio.Mmio(packed struct(u32) { /// External Event X Source - EESRC: u2, + @"EESRC[0]": u2, /// External Event X Polarity - EEPOL: u1, + @"EEPOL[0]": u1, /// External Event X Sensitivity - EESNS: u2, + @"EESNS[0]": u2, /// External Event X Fast Mode - EEFAST: u2, - padding: u25, + @"EEFAST[0]": u2, + // skipped overlapping field EESRC[1] at offset 6 bits + reserved8: u1, + /// External Event X Polarity + @"EEPOL[1]": u1, + /// External Event X Sensitivity + @"EESNS[1]": u2, + /// External Event X Fast Mode + @"EEFAST[1]": u2, + // skipped overlapping field EESRC[2] at offset 12 bits + reserved14: u1, + /// External Event X Polarity + @"EEPOL[2]": u1, + /// External Event X Sensitivity + @"EESNS[2]": u2, + /// External Event X Fast Mode + @"EEFAST[2]": u2, + // skipped overlapping field EESRC[3] at offset 18 bits + reserved20: u1, + /// External Event X Polarity + @"EEPOL[3]": u1, + /// External Event X Sensitivity + @"EESNS[3]": u2, + /// External Event X Fast Mode + @"EEFAST[3]": u2, + // skipped overlapping field EESRC[4] at offset 24 bits + reserved26: u1, + /// External Event X Polarity + @"EEPOL[4]": u1, + /// External Event X Sensitivity + @"EESNS[4]": u2, + /// External Event X Fast Mode + @"EEFAST[4]": u2, + padding: u1, }), /// High Resolution Timer: External Event Control Register 2 EECR2: mmio.Mmio(packed struct(u32) { /// External Event X Source - EESRC: u2, + @"EESRC[0]": u2, /// External Event X Polarity - EEPOL: u1, + @"EEPOL[0]": u1, /// External Event X Sensitivity - EESNS: u2, - padding: u27, + @"EESNS[0]": u2, + reserved6: u1, + /// External Event X Source + @"EESRC[1]": u2, + /// External Event X Polarity + @"EEPOL[1]": u1, + /// External Event X Sensitivity + @"EESNS[1]": u2, + reserved12: u1, + /// External Event X Source + @"EESRC[2]": u2, + /// External Event X Polarity + @"EEPOL[2]": u1, + /// External Event X Sensitivity + @"EESNS[2]": u2, + reserved18: u1, + /// External Event X Source + @"EESRC[3]": u2, + /// External Event X Polarity + @"EEPOL[3]": u1, + /// External Event X Sensitivity + @"EESNS[3]": u2, + reserved24: u1, + /// External Event X Source + @"EESRC[4]": u2, + /// External Event X Polarity + @"EEPOL[4]": u1, + /// External Event X Sensitivity + @"EESNS[4]": u2, + padding: u3, }), /// High Resolution Timer: External Event Control Register 3 EECR3: mmio.Mmio(packed struct(u32) { /// External Event X filter - EEF: u3, - reserved30: u27, + @"EEF[0]": u3, + reserved6: u3, + /// External Event X filter + @"EEF[1]": u3, + reserved12: u3, + /// External Event X filter + @"EEF[2]": u3, + reserved18: u3, + /// External Event X filter + @"EEF[3]": u3, + reserved24: u3, + /// External Event X filter + @"EEF[4]": u3, + reserved30: u3, /// External Event Sampling Clock Division EEVSD: u2, }), @@ -350912,16 +351234,49 @@ pub const types = struct { /// (5/5 of ADCEEV) ADC trigger X on External Event Y @"ADCEEV[4]": u1, /// ADC trigger X on Timer Y Compare 2 - ADCTC2: u1, + @"ADCTC2[0]": u1, /// ADC trigger X on Timer Y Compare 3 - ADCTC3: u1, + @"ADCTC3[0]": u1, /// ADC trigger X on Timer Y Compare 3 - ADCTC4: u1, + @"ADCTC4[0]": u1, /// ADC trigger X on Timer Y Period - ADCTPER: u1, + @"ADCTPER[0]": u1, /// ADC trigger X on Timer Y Reset - ADCTRST: u1, - padding: u17, + @"ADCTRST[0]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[1]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[1]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[1]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[1]": u1, + /// ADC trigger X on Timer Y Reset + @"ADCTRST[1]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[2]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[2]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[2]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[2]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[3]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[3]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[3]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[3]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[4]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[4]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[4]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[4]": u1, }), /// High Resolution Timer: ADC Trigger [2, 4] Register ADC2R: mmio.Mmio(packed struct(u32) { @@ -350946,17 +351301,49 @@ pub const types = struct { /// (5/5 of ADCEEV) ADC trigger X on External Event Y @"ADCEEV[4]": u1, /// ADC trigger X on Timer Y Compare 2 - ADCTC2: u1, + @"ADCTC2[0]": u1, /// ADC trigger X on Timer Y Compare 3 - ADCTC3: u1, + @"ADCTC3[0]": u1, /// ADC trigger X on Timer Y Compare 3 - ADCTC4: u1, + @"ADCTC4[0]": u1, /// ADC trigger X on Timer Y Period - ADCTPER: u1, - reserved22: u8, + @"ADCTPER[0]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[1]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[1]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[1]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[1]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[2]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[2]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[2]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[2]": u1, /// ADC trigger X on Timer Y Reset - ADCTRST: u1, - padding: u9, + @"ADCTRST[0]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[3]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[3]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[3]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[3]": u1, + /// ADC trigger X on Timer Y Reset + @"ADCTRST[1]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[4]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[4]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[4]": u1, + /// ADC trigger X on Timer Y Reset + @"ADCTRST[2]": u1, }), reserved972: [8]u8, /// High Resolution Timer: DLL Control Register @@ -350972,16 +351359,45 @@ pub const types = struct { /// High Resolution Timer: Fault Input Register 1 FLTINR1: mmio.Mmio(packed struct(u32) { /// Fault X enable - FLTE: u1, + @"FLTE[0]": u1, /// Fault X polarity - FLTP: u1, + @"FLTP[0]": u1, /// Fault X source - FLTSRC: u1, + @"FLTSRC[0]": u1, /// Fault X filter - FLTF: u4, + @"FLTF[0]": u4, /// Fault X Lock - FLTLCK: u1, - padding: u24, + @"FLTLCK[0]": u1, + /// Fault X enable + @"FLTE[1]": u1, + /// Fault X polarity + @"FLTP[1]": u1, + /// Fault X source + @"FLTSRC[1]": u1, + /// Fault X filter + @"FLTF[1]": u4, + /// Fault X Lock + @"FLTLCK[1]": u1, + /// Fault X enable + @"FLTE[2]": u1, + /// Fault X polarity + @"FLTP[2]": u1, + /// Fault X source + @"FLTSRC[2]": u1, + /// Fault X filter + @"FLTF[2]": u4, + /// Fault X Lock + @"FLTLCK[2]": u1, + /// Fault X enable + @"FLTE[3]": u1, + /// Fault X polarity + @"FLTP[3]": u1, + /// Fault X source + @"FLTSRC[3]": u1, + /// Fault X filter + @"FLTF[3]": u4, + /// Fault X Lock + @"FLTLCK[3]": u1, }), reserved984: [4]u8, /// High Resolution Timer: Burst DMA Master timer update Register @@ -351107,10 +351523,13 @@ pub const types = struct { /// (2/2 of CPT) Capture X Interrupt Flag @"CPT[1]": u1, /// Output X Set Interrupt Flag - SETR: u1, + @"SETR[0]": u1, /// Output X Reset Interrupt Flag - RSTR: u1, - reserved13: u2, + @"RSTR[0]": u1, + /// Output X Set Interrupt Flag + @"SETR[1]": u1, + /// Output X Reset Interrupt Flag + @"RSTR[1]": u1, /// Reset Interrupt Flag RST: u1, /// Delayed Protection Flag @@ -351150,10 +351569,13 @@ pub const types = struct { /// (2/2 of CPTC) Capture X Interrupt flag Clear @"CPTC[1]": u1, /// Output X Set flag Clear - SETRC: u1, + @"SETRC[0]": u1, /// Output X Reset flag Clear - RSTRC: u1, - reserved13: u2, + @"RSTRC[0]": u1, + /// Output X Set flag Clear + @"SETRC[1]": u1, + /// Output X Reset flag Clear + @"RSTRC[1]": u1, /// Reset Interrupt flag Clear RSTC: u1, /// Delayed Protection Flag Clear @@ -351180,10 +351602,13 @@ pub const types = struct { /// (2/2 of CPTIE) Capture Interrupt Enable @"CPTIE[1]": u1, /// Output X Set Interrupt Enable - SETRIE: u1, + @"SETRIE[0]": u1, /// Output X Reset Interrupt Enable - RSTRIE: u1, - reserved13: u2, + @"RSTRIE[0]": u1, + /// Output X Set Interrupt Enable + @"SETRIE[1]": u1, + /// Output X Reset Interrupt Enable + @"RSTRIE[1]": u1, /// Reset/roll-over Interrupt Enable RSTIE: u1, /// Delayed Protection Interrupt Enable @@ -351207,10 +351632,13 @@ pub const types = struct { /// (2/2 of CPTDE) Capture X DMA request Enable @"CPTDE[1]": u1, /// Output X Set DMA request Enable - SETRDE: u1, + @"SETRDE[0]": u1, /// Output X Reset DMA request Enable - RSTRDE: u1, - reserved29: u2, + @"RSTRDE[0]": u1, + /// Output X Set DMA request Enable + @"SETRDE[1]": u1, + /// Output X Reset DMA request Enable + @"RSTRDE[1]": u1, /// Reset/roll-over DMA request Enable RSTDE: u1, /// Delayed Protection DMA request Enable @@ -351483,12 +351911,30 @@ pub const types = struct { /// (10/10 of EXTEVNT) External Event X @"EXTEVNT[9]": RESETEFFECT, /// Timer X compare 1 event - TCMP1: RESETEFFECT, + @"TCMP1[0]": RESETEFFECT, /// Timer X compare 2 event - TCMP2: RESETEFFECT, + @"TCMP2[0]": RESETEFFECT, /// Timer X compare 4 event - TCMP4: RESETEFFECT, - padding: u10, + @"TCMP4[0]": RESETEFFECT, + /// Timer X compare 1 event + @"TCMP1[1]": RESETEFFECT, + /// Timer X compare 2 event + @"TCMP2[1]": RESETEFFECT, + /// Timer X compare 4 event + @"TCMP4[1]": RESETEFFECT, + /// Timer X compare 1 event + @"TCMP1[2]": RESETEFFECT, + /// Timer X compare 2 event + @"TCMP2[2]": RESETEFFECT, + /// Timer X compare 4 event + @"TCMP4[2]": RESETEFFECT, + /// Timer X compare 1 event + @"TCMP1[3]": RESETEFFECT, + /// Timer X compare 2 event + @"TCMP2[3]": RESETEFFECT, + /// Timer X compare 4 event + @"TCMP4[3]": RESETEFFECT, + padding: u1, }), /// Timer X Chopper Register CHP: mmio.Mmio(packed struct(u32) { @@ -351565,24 +352011,37 @@ pub const types = struct { OUTR: mmio.Mmio(packed struct(u32) { reserved1: u1, /// Output 1 polarity - POL: POL, + @"POL[0]": POL, /// Output X Idle mode - IDLEM: u1, + @"IDLEM[0]": u1, /// Output X Idle State - IDLES: u1, + @"IDLES[0]": u1, /// Output X Fault state - FAULTX: FAULT, + @"FAULTX[0]": FAULT, /// Output X Chopper enable - CHP: u1, + @"CHP[0]": u1, /// Output X Deadtime upon burst mode Idle entry - DIDL: u1, + @"DIDL[0]": u1, /// Deadtime enable DTEN: u1, /// Delayed Protection Enable DLYPRTEN: u1, /// Delayed Protection DLYPRT: DLYPRT, - padding: u19, + reserved17: u4, + /// Output 1 polarity + @"POL[1]": POL, + /// Output X Idle mode + @"IDLEM[1]": u1, + /// Output X Idle State + @"IDLES[1]": u1, + /// Output X Fault state + @"FAULTX[1]": FAULT, + /// Output X Chopper enable + @"CHP[1]": u1, + /// Output X Deadtime upon burst mode Idle entry + @"DIDL[1]": u1, + padding: u8, }), /// Timer X Fault Register FLT: mmio.Mmio(packed struct(u32) { @@ -352115,26 +352574,74 @@ pub const types = struct { /// High Resolution Timer: Output Enable Register OENR: mmio.Mmio(packed struct(u32) { /// Timer X Output Enable - T1OEN: u1, + @"T1OEN[0]": u1, /// Timer X Complementary Output Enable - T2OEN: u1, - padding: u30, + @"T2OEN[0]": u1, + /// Timer X Output Enable + @"T1OEN[1]": u1, + /// Timer X Complementary Output Enable + @"T2OEN[1]": u1, + /// Timer X Output Enable + @"T1OEN[2]": u1, + /// Timer X Complementary Output Enable + @"T2OEN[2]": u1, + /// Timer X Output Enable + @"T1OEN[3]": u1, + /// Timer X Complementary Output Enable + @"T2OEN[3]": u1, + /// Timer X Output Enable + @"T1OEN[4]": u1, + /// Timer X Complementary Output Enable + @"T2OEN[4]": u1, + padding: u22, }), /// High Resolution Timer: Output Disable Register ODISR: mmio.Mmio(packed struct(u32) { /// Timer X Output Disable - T1ODIS: u1, + @"T1ODIS[0]": u1, /// Timer X Complementary Output Disable - T2ODIS: u1, - padding: u30, + @"T2ODIS[0]": u1, + /// Timer X Output Disable + @"T1ODIS[1]": u1, + /// Timer X Complementary Output Disable + @"T2ODIS[1]": u1, + /// Timer X Output Disable + @"T1ODIS[2]": u1, + /// Timer X Complementary Output Disable + @"T2ODIS[2]": u1, + /// Timer X Output Disable + @"T1ODIS[3]": u1, + /// Timer X Complementary Output Disable + @"T2ODIS[3]": u1, + /// Timer X Output Disable + @"T1ODIS[4]": u1, + /// Timer X Complementary Output Disable + @"T2ODIS[4]": u1, + padding: u22, }), /// High Resolution Timer: Output Disable Status Register ODSR: mmio.Mmio(packed struct(u32) { /// Timer X Output Disable Status - T1ODIS: u1, + @"T1ODIS[0]": u1, /// Timer X Complementary Output Disable Status - T2ODIS: u1, - padding: u30, + @"T2ODIS[0]": u1, + /// Timer X Output Disable Status + @"T1ODIS[1]": u1, + /// Timer X Complementary Output Disable Status + @"T2ODIS[1]": u1, + /// Timer X Output Disable Status + @"T1ODIS[2]": u1, + /// Timer X Complementary Output Disable Status + @"T2ODIS[2]": u1, + /// Timer X Output Disable Status + @"T1ODIS[3]": u1, + /// Timer X Complementary Output Disable Status + @"T2ODIS[3]": u1, + /// Timer X Output Disable Status + @"T1ODIS[4]": u1, + /// Timer X Complementary Output Disable Status + @"T2ODIS[4]": u1, + padding: u22, }), /// High Resolution Timer: Burst Mode Control Register BMCR: mmio.Mmio(packed struct(u32) { @@ -352183,14 +352690,46 @@ pub const types = struct { /// (4/4 of MSTCMP) Master Compare X @"MSTCMP[3]": u1, /// Timer X reset or roll-over - TRST: u1, + @"TRST[0]": u1, /// Timer X repetition - TREP: u1, + @"TREP[0]": u1, /// Timer X compare 1 event - TCMP1: u1, + @"TCMP1[0]": u1, /// Timer X compare 2 event - TCMP2: u1, - padding: u21, + @"TCMP2[0]": u1, + /// Timer X reset or roll-over + @"TRST[1]": u1, + /// Timer X repetition + @"TREP[1]": u1, + /// Timer X compare 1 event + @"TCMP1[1]": u1, + /// Timer X compare 2 event + @"TCMP2[1]": u1, + /// Timer X reset or roll-over + @"TRST[2]": u1, + /// Timer X repetition + @"TREP[2]": u1, + /// Timer X compare 1 event + @"TCMP1[2]": u1, + /// Timer X compare 2 event + @"TCMP2[2]": u1, + /// Timer X reset or roll-over + @"TRST[3]": u1, + /// Timer X repetition + @"TREP[3]": u1, + /// Timer X compare 1 event + @"TCMP1[3]": u1, + /// Timer X compare 2 event + @"TCMP2[3]": u1, + /// Timer X reset or roll-over + @"TRST[4]": u1, + /// Timer X repetition + @"TREP[4]": u1, + /// Timer X compare 1 event + @"TCMP1[4]": u1, + /// Timer X compare 2 event + @"TCMP2[4]": u1, + padding: u5, }), /// High Resolution Timer: Burst Mode Compare Register BMCMPR: mmio.Mmio(packed struct(u32) { @@ -352207,30 +352746,102 @@ pub const types = struct { /// High Resolution Timer: External Event Control Register 1 EECR1: mmio.Mmio(packed struct(u32) { /// External Event X Source - EESRC: u2, + @"EESRC[0]": u2, /// External Event X Polarity - EEPOL: u1, + @"EEPOL[0]": u1, /// External Event X Sensitivity - EESNS: u2, + @"EESNS[0]": u2, /// External Event X Fast Mode - EEFAST: u2, - padding: u25, + @"EEFAST[0]": u2, + // skipped overlapping field EESRC[1] at offset 6 bits + reserved8: u1, + /// External Event X Polarity + @"EEPOL[1]": u1, + /// External Event X Sensitivity + @"EESNS[1]": u2, + /// External Event X Fast Mode + @"EEFAST[1]": u2, + // skipped overlapping field EESRC[2] at offset 12 bits + reserved14: u1, + /// External Event X Polarity + @"EEPOL[2]": u1, + /// External Event X Sensitivity + @"EESNS[2]": u2, + /// External Event X Fast Mode + @"EEFAST[2]": u2, + // skipped overlapping field EESRC[3] at offset 18 bits + reserved20: u1, + /// External Event X Polarity + @"EEPOL[3]": u1, + /// External Event X Sensitivity + @"EESNS[3]": u2, + /// External Event X Fast Mode + @"EEFAST[3]": u2, + // skipped overlapping field EESRC[4] at offset 24 bits + reserved26: u1, + /// External Event X Polarity + @"EEPOL[4]": u1, + /// External Event X Sensitivity + @"EESNS[4]": u2, + /// External Event X Fast Mode + @"EEFAST[4]": u2, + padding: u1, }), /// High Resolution Timer: External Event Control Register 2 EECR2: mmio.Mmio(packed struct(u32) { /// External Event X Source - EESRC: u2, + @"EESRC[0]": u2, /// External Event X Polarity - EEPOL: u1, + @"EEPOL[0]": u1, /// External Event X Sensitivity - EESNS: u2, - padding: u27, + @"EESNS[0]": u2, + reserved6: u1, + /// External Event X Source + @"EESRC[1]": u2, + /// External Event X Polarity + @"EEPOL[1]": u1, + /// External Event X Sensitivity + @"EESNS[1]": u2, + reserved12: u1, + /// External Event X Source + @"EESRC[2]": u2, + /// External Event X Polarity + @"EEPOL[2]": u1, + /// External Event X Sensitivity + @"EESNS[2]": u2, + reserved18: u1, + /// External Event X Source + @"EESRC[3]": u2, + /// External Event X Polarity + @"EEPOL[3]": u1, + /// External Event X Sensitivity + @"EESNS[3]": u2, + reserved24: u1, + /// External Event X Source + @"EESRC[4]": u2, + /// External Event X Polarity + @"EEPOL[4]": u1, + /// External Event X Sensitivity + @"EESNS[4]": u2, + padding: u3, }), /// High Resolution Timer: External Event Control Register 3 EECR3: mmio.Mmio(packed struct(u32) { /// External Event X filter - EEF: u3, - reserved30: u27, + @"EEF[0]": u3, + reserved6: u3, + /// External Event X filter + @"EEF[1]": u3, + reserved12: u3, + /// External Event X filter + @"EEF[2]": u3, + reserved18: u3, + /// External Event X filter + @"EEF[3]": u3, + reserved24: u3, + /// External Event X filter + @"EEF[4]": u3, + reserved30: u3, /// External Event Sampling Clock Division EEVSD: u2, }), @@ -352257,16 +352868,47 @@ pub const types = struct { /// (5/5 of ADCEEV) ADC trigger X on External Event Y @"ADCEEV[4]": u1, /// ADC trigger X on Timer Y Compare 2 - ADCTC2: u1, + @"ADCTC2[0]": u1, /// ADC trigger X on Timer Y Compare 3 - ADCTC3: u1, + @"ADCTC3[0]": u1, /// ADC trigger X on Timer Y Compare 3 - ADCTC4: u1, + @"ADCTC4[0]": u1, /// ADC trigger X on Timer Y Period - ADCTPER: u1, + @"ADCTPER[0]": u1, /// ADC trigger X on Timer Y Reset - ADCTRST: u1, - padding: u17, + @"ADCTRST[0]": u1, + reserved16: u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[1]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[1]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[1]": u1, + /// ADC trigger X on Timer Y Reset + @"ADCTRST[1]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[5]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[2]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[2]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[2]": u1, + reserved25: u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[3]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[3]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[3]": u1, + /// ADC trigger X on Timer Y Reset + @"ADCTRST[2]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[4]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[4]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[4]": u1, }), /// High Resolution Timer: ADC Trigger [2, 4] Register ADC2R: mmio.Mmio(packed struct(u32) { @@ -352291,19 +352933,48 @@ pub const types = struct { /// (5/5 of ADCEEV) ADC trigger X on External Event Y @"ADCEEV[4]": u1, /// ADC trigger X on Timer Y Compare 2 - ADCTC2: u1, - reserved12: u1, + @"ADCTC2[0]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[5]": u1, /// ADC trigger X on Timer Y Compare 3 - ADCTC4: u1, + @"ADCTC4[0]": u1, /// ADC trigger X on Timer Y Period - ADCTPER: u1, - reserved15: u1, + @"ADCTPER[0]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[1]": u1, /// ADC trigger X on Timer Y Compare 3 - ADCTC3: u1, - reserved22: u6, + @"ADCTC3[1]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[1]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[1]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[2]": u1, + reserved20: u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[2]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[2]": u1, /// ADC trigger X on Timer Y Reset - ADCTRST: u1, - padding: u9, + @"ADCTRST[0]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[3]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[4]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[3]": u1, + /// ADC trigger X on Timer Y Period + @"ADCTPER[3]": u1, + /// ADC trigger X on Timer Y Reset + @"ADCTRST[1]": u1, + /// ADC trigger X on Timer Y Compare 2 + @"ADCTC2[4]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC3[0]": u1, + /// ADC trigger X on Timer Y Compare 3 + @"ADCTC4[4]": u1, + /// ADC trigger X on Timer Y Reset + @"ADCTRST[2]": u1, }), reserved972: [8]u8, /// High Resolution Timer: DLL Control Register @@ -352319,16 +352990,45 @@ pub const types = struct { /// High Resolution Timer: Fault Input Register 1 FLTINR1: mmio.Mmio(packed struct(u32) { /// Fault X enable - FLTE: u1, + @"FLTE[0]": u1, /// Fault X polarity - FLTP: u1, + @"FLTP[0]": u1, /// Fault X source - FLTSRC: u1, + @"FLTSRC[0]": u1, /// Fault X filter - FLTF: u4, + @"FLTF[0]": u4, /// Fault X Lock - FLTLCK: u1, - padding: u24, + @"FLTLCK[0]": u1, + /// Fault X enable + @"FLTE[1]": u1, + /// Fault X polarity + @"FLTP[1]": u1, + /// Fault X source + @"FLTSRC[1]": u1, + /// Fault X filter + @"FLTF[1]": u4, + /// Fault X Lock + @"FLTLCK[1]": u1, + /// Fault X enable + @"FLTE[2]": u1, + /// Fault X polarity + @"FLTP[2]": u1, + /// Fault X source + @"FLTSRC[2]": u1, + /// Fault X filter + @"FLTF[2]": u4, + /// Fault X Lock + @"FLTLCK[2]": u1, + /// Fault X enable + @"FLTE[3]": u1, + /// Fault X polarity + @"FLTP[3]": u1, + /// Fault X source + @"FLTSRC[3]": u1, + /// Fault X filter + @"FLTF[3]": u4, + /// Fault X Lock + @"FLTLCK[3]": u1, }), reserved984: [4]u8, /// High Resolution Timer: Burst DMA Master timer update Register @@ -352454,10 +353154,13 @@ pub const types = struct { /// (2/2 of CPT) Capture X Interrupt Flag @"CPT[1]": u1, /// Output X Set Interrupt Flag - SETR: u1, + @"SETR[0]": u1, /// Output X Reset Interrupt Flag - RSTR: u1, - reserved13: u2, + @"RSTR[0]": u1, + /// Output X Set Interrupt Flag + @"SETR[1]": u1, + /// Output X Reset Interrupt Flag + @"RSTR[1]": u1, /// Reset Interrupt Flag RST: u1, /// Delayed Protection Flag @@ -352497,10 +353200,13 @@ pub const types = struct { /// (2/2 of CPTC) Capture X Interrupt flag Clear @"CPTC[1]": u1, /// Output X Set flag Clear - SETRC: u1, + @"SETRC[0]": u1, /// Output X Reset flag Clear - RSTRC: u1, - reserved13: u2, + @"RSTRC[0]": u1, + /// Output X Set flag Clear + @"SETRC[1]": u1, + /// Output X Reset flag Clear + @"RSTRC[1]": u1, /// Reset Interrupt flag Clear RSTC: u1, /// Delayed Protection Flag Clear @@ -352527,10 +353233,13 @@ pub const types = struct { /// (2/2 of CPTIE) Capture Interrupt Enable @"CPTIE[1]": u1, /// Output X Set Interrupt Enable - SETRIE: u1, + @"SETRIE[0]": u1, /// Output X Reset Interrupt Enable - RSTRIE: u1, - reserved13: u2, + @"RSTRIE[0]": u1, + /// Output X Set Interrupt Enable + @"SETRIE[1]": u1, + /// Output X Reset Interrupt Enable + @"RSTRIE[1]": u1, /// Reset/roll-over Interrupt Enable RSTIE: u1, /// Delayed Protection Interrupt Enable @@ -352554,10 +353263,13 @@ pub const types = struct { /// (2/2 of CPTDE) Capture X DMA request Enable @"CPTDE[1]": u1, /// Output X Set DMA request Enable - SETRDE: u1, + @"SETRDE[0]": u1, /// Output X Reset DMA request Enable - RSTRDE: u1, - reserved29: u2, + @"RSTRDE[0]": u1, + /// Output X Set DMA request Enable + @"SETRDE[1]": u1, + /// Output X Reset DMA request Enable + @"RSTRDE[1]": u1, /// Reset/roll-over DMA request Enable RSTDE: u1, /// Delayed Protection DMA request Enable @@ -352793,7 +353505,7 @@ pub const types = struct { /// Timer X Reset Register RST: mmio.Mmio(packed struct(u32) { /// Timer X compare 1 event - TCMP1: RESETEFFECT, + @"TCMP1[4]": RESETEFFECT, /// Timer X Update reset UPDT: RESETEFFECT, /// (1/2 of CMP) Timer X compare X reset @@ -352830,12 +353542,32 @@ pub const types = struct { @"EXTEVNT[8]": RESETEFFECT, /// (10/10 of EXTEVNT) External Event X @"EXTEVNT[9]": RESETEFFECT, - reserved20: u1, + /// Timer X compare 1 event + @"TCMP1[0]": RESETEFFECT, /// Timer X compare 2 event - TCMP2: RESETEFFECT, + @"TCMP2[0]": RESETEFFECT, /// Timer X compare 4 event - TCMP4: RESETEFFECT, - padding: u10, + @"TCMP4[0]": RESETEFFECT, + /// Timer X compare 1 event + @"TCMP1[1]": RESETEFFECT, + /// Timer X compare 2 event + @"TCMP2[1]": RESETEFFECT, + /// Timer X compare 4 event + @"TCMP4[1]": RESETEFFECT, + /// Timer X compare 1 event + @"TCMP1[2]": RESETEFFECT, + /// Timer X compare 2 event + @"TCMP2[2]": RESETEFFECT, + /// Timer X compare 4 event + @"TCMP4[2]": RESETEFFECT, + /// Timer X compare 1 event + @"TCMP1[3]": RESETEFFECT, + /// Timer X compare 2 event + @"TCMP2[3]": RESETEFFECT, + /// Timer X compare 4 event + @"TCMP4[3]": RESETEFFECT, + /// Timer X compare 2 event + @"TCMP2[4]": RESETEFFECT, }), /// Timer X Chopper Register CHP: mmio.Mmio(packed struct(u32) { @@ -352912,24 +353644,37 @@ pub const types = struct { OUTR: mmio.Mmio(packed struct(u32) { reserved1: u1, /// Output 1 polarity - POL: POL, + @"POL[0]": POL, /// Output X Idle mode - IDLEM: u1, + @"IDLEM[0]": u1, /// Output X Idle State - IDLES: u1, + @"IDLES[0]": u1, /// Output X Fault state - FAULTX: FAULT, + @"FAULTX[0]": FAULT, /// Output X Chopper enable - CHP: u1, + @"CHP[0]": u1, /// Output X Deadtime upon burst mode Idle entry - DIDL: u1, + @"DIDL[0]": u1, /// Deadtime enable DTEN: u1, /// Delayed Protection Enable DLYPRTEN: u1, /// Delayed Protection DLYPRT: DLYPRT, - padding: u19, + reserved17: u4, + /// Output 1 polarity + @"POL[1]": POL, + /// Output X Idle mode + @"IDLEM[1]": u1, + /// Output X Idle State + @"IDLES[1]": u1, + /// Output X Fault state + @"FAULTX[1]": FAULT, + /// Output X Chopper enable + @"CHP[1]": u1, + /// Output X Deadtime upon burst mode Idle entry + @"DIDL[1]": u1, + padding: u8, }), /// Timer X Fault Register FLT: mmio.Mmio(packed struct(u32) { @@ -360988,13 +361733,13 @@ pub const types = struct { /// LPTIM interrupt and status register. ISR: mmio.Mmio(packed struct(u32) { /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, + @"CCIF[0]": u1, /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. ARRM: u1, /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. EXTTRIG: u1, /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, + @"CMPOK[0]": u1, /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. ARROK: u1, /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -361005,7 +361750,12 @@ pub const types = struct { UE: u1, /// Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. REPOK: u1, - reserved12: u3, + /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[1]": u1, + /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[2]": u1, + /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[3]": u1, /// (1/4 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. @"CCOF[0]": u1, /// (2/4 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. @@ -361014,7 +361764,14 @@ pub const types = struct { @"CCOF[2]": u1, /// (4/4 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. @"CCOF[3]": u1, - reserved24: u8, + reserved19: u3, + /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[1]": u1, + /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[2]": u1, + /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[3]": u1, + reserved24: u2, /// Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. DIEROK: u1, padding: u7, @@ -361022,13 +361779,13 @@ pub const types = struct { /// LPTIM interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, + @"CCCF[0]": u1, /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. ARRMCF: u1, /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. EXTTRIGCF: u1, /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, + @"CMPOKCF[0]": u1, /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. ARROKCF: u1, /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -361039,7 +361796,12 @@ pub const types = struct { UECF: u1, /// Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. REPOKCF: u1, - reserved12: u3, + /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[1]": u1, + /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[2]": u1, + /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[3]": u1, /// (1/4 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. @"CCOCF[0]": u1, /// (2/4 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. @@ -361048,7 +361810,14 @@ pub const types = struct { @"CCOCF[2]": u1, /// (4/4 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. @"CCOCF[3]": u1, - reserved24: u8, + reserved19: u3, + /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[1]": u1, + /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[2]": u1, + /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[3]": u1, + reserved24: u2, /// Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. DIEROKCF: u1, padding: u7, @@ -361056,13 +361825,13 @@ pub const types = struct { /// LPTIM interrupt enable register. DIER: mmio.Mmio(packed struct(u32) { /// Capture/compare 1 interrupt enable. - CCIE: u1, + @"CCIE[0]": u1, /// Autoreload match Interrupt Enable. ARRMIE: u1, /// External trigger valid edge Interrupt Enable. EXTTRIGIE: u1, /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, + @"CMPOKIE[0]": u1, /// Autoreload register update OK Interrupt Enable. ARROKIE: u1, /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -361073,7 +361842,12 @@ pub const types = struct { UEIE: u1, /// Repetition register update OK interrupt Enable. REPOKIE: u1, - reserved12: u3, + /// Capture/compare 1 interrupt enable. + @"CCIE[1]": u1, + /// Capture/compare 1 interrupt enable. + @"CCIE[2]": u1, + /// Capture/compare 1 interrupt enable. + @"CCIE[3]": u1, /// (1/4 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. @"CCOIE[0]": u1, /// (2/4 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. @@ -361083,8 +361857,22 @@ pub const types = struct { /// (4/4 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. @"CCOIE[3]": u1, /// Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCDE: u1, - padding: u15, + @"CCDE[0]": u1, + reserved19: u2, + /// Compare register 1 update OK interrupt enable. + @"CMPOKIE[1]": u1, + /// Compare register 1 update OK interrupt enable. + @"CMPOKIE[2]": u1, + /// Compare register 1 update OK interrupt enable. + @"CMPOKIE[3]": u1, + reserved25: u3, + /// Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCDE[1]": u1, + /// Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCDE[2]": u1, + /// Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCDE[3]": u1, + padding: u4, }), /// LPTIM configuration register. CFGR: mmio.Mmio(packed struct(u32) { @@ -419330,12 +420118,19 @@ pub const types = struct { /// Tamper and alternate function configuration register TAFCR: mmio.Mmio(packed struct(u32) { /// Tamper detection enable - TAMPE: u1, + @"TAMPE[0]": u1, /// Active level for tamper - TAMPTRG: TAMPTRG, + @"TAMPTRG[0]": TAMPTRG, /// Tamper interrupt enable TAMPIE: u1, - reserved7: u4, + /// Tamper detection enable + @"TAMPE[1]": u1, + /// Active level for tamper + @"TAMPTRG[1]": TAMPTRG, + /// Tamper detection enable + @"TAMPE[2]": u1, + /// Active level for tamper + @"TAMPTRG[2]": TAMPTRG, /// Activate timestamp on tamper detection event TAMPTS: u1, /// Tamper sampling frequency @@ -419673,9 +420468,9 @@ pub const types = struct { /// Tamper and alternate function configuration register TAFCR: mmio.Mmio(packed struct(u32) { /// Tamper detection enable - TAMPE: u1, + @"TAMPE[0]": u1, /// Active level for tamper - TAMPTRG: TAMPTRG, + @"TAMPTRG[0]": TAMPTRG, /// Tamper interrupt enable TAMPIE: u1, reserved16: u13, @@ -420122,12 +420917,16 @@ pub const types = struct { /// Tamper and alternate function configuration register TAFCR: mmio.Mmio(packed struct(u32) { /// Tamper detection enable - TAMPE: u1, + @"TAMPE[0]": u1, /// Active level for tamper - TAMPTRG: TAMPTRG, + @"TAMPTRG[0]": TAMPTRG, /// Tamper interrupt enable TAMPIE: u1, - reserved7: u4, + /// Tamper detection enable + @"TAMPE[1]": u1, + /// Active level for tamper + @"TAMPTRG[1]": TAMPTRG, + reserved7: u2, /// Activate timestamp on tamper detection event TAMPTS: u1, /// Tamper sampling frequency @@ -420592,12 +421391,16 @@ pub const types = struct { /// Tamper and alternate function configuration register TAFCR: mmio.Mmio(packed struct(u32) { /// Tamper detection enable - TAMPE: u1, + @"TAMPE[0]": u1, /// Active level for tamper - TAMPTRG: TAMPTRG, + @"TAMPTRG[0]": TAMPTRG, /// Tamper interrupt enable TAMPIE: u1, - reserved7: u4, + /// Tamper detection enable + @"TAMPE[1]": u1, + /// Active level for tamper + @"TAMPTRG[1]": TAMPTRG, + reserved7: u2, /// Activate timestamp on tamper detection event TAMPTS: u1, /// Tamper sampling frequency @@ -421050,12 +421853,19 @@ pub const types = struct { /// Tamper configuration register TAMPCR: mmio.Mmio(packed struct(u32) { /// Tamper detection enable - TAMPE: u1, + @"TAMPE[0]": u1, /// Active level for tamper - TAMPTRG: TAMPTRG, + @"TAMPTRG[0]": TAMPTRG, /// Tamper interrupt enable TAMPIE: u1, - reserved7: u4, + /// Tamper detection enable + @"TAMPE[1]": u1, + /// Active level for tamper + @"TAMPTRG[1]": TAMPTRG, + /// Tamper detection enable + @"TAMPE[2]": u1, + /// Active level for tamper + @"TAMPTRG[2]": TAMPTRG, /// Activate timestamp on tamper detection event TAMPTS: u1, /// Tamper sampling frequency @@ -421528,12 +422338,19 @@ pub const types = struct { /// Tamper configuration register TAMPCR: mmio.Mmio(packed struct(u32) { /// Tamper detection enable - TAMPE: u1, + @"TAMPE[0]": u1, /// Active level for tamper - TAMPTRG: TAMPTRG, + @"TAMPTRG[0]": TAMPTRG, /// Tamper interrupt enable TAMPIE: u1, - reserved7: u4, + /// Tamper detection enable + @"TAMPE[1]": u1, + /// Active level for tamper + @"TAMPTRG[1]": TAMPTRG, + /// Tamper detection enable + @"TAMPE[2]": u1, + /// Active level for tamper + @"TAMPTRG[2]": TAMPTRG, /// Activate timestamp on tamper detection event TAMPTS: u1, /// Tamper sampling frequency @@ -422001,12 +422818,19 @@ pub const types = struct { /// Tamper configuration register TAMPCR: mmio.Mmio(packed struct(u32) { /// Tamper detection enable - TAMPE: u1, + @"TAMPE[0]": u1, /// Active level for tamper - TAMPTRG: TAMPTRG, + @"TAMPTRG[0]": TAMPTRG, /// Tamper interrupt enable TAMPIE: u1, - reserved7: u4, + /// Tamper detection enable + @"TAMPE[1]": u1, + /// Active level for tamper + @"TAMPTRG[1]": TAMPTRG, + /// Tamper detection enable + @"TAMPE[2]": u1, + /// Active level for tamper + @"TAMPTRG[2]": TAMPTRG, /// Activate timestamp on tamper detection event TAMPTS: u1, /// Tamper sampling frequency @@ -422483,12 +423307,19 @@ pub const types = struct { /// Tamper and alternate function configuration register TAFCR: mmio.Mmio(packed struct(u32) { /// Tamper detection enable - TAMPE: u1, + @"TAMPE[0]": u1, /// Active level for tamper - TAMPTRG: TAMPTRG, + @"TAMPTRG[0]": TAMPTRG, /// Tamper interrupt enable TAMPIE: u1, - reserved7: u4, + /// Tamper detection enable + @"TAMPE[1]": u1, + /// Active level for tamper + @"TAMPTRG[1]": TAMPTRG, + /// Tamper detection enable + @"TAMPE[2]": u1, + /// Active level for tamper + @"TAMPTRG[2]": TAMPTRG, /// Activate timestamp on tamper detection event TAMPTS: u1, /// Tamper sampling frequency @@ -422936,12 +423767,19 @@ pub const types = struct { /// Tamper configuration register TAMPCR: mmio.Mmio(packed struct(u32) { /// Tamper detection enable - TAMPE: u1, + @"TAMPE[0]": u1, /// Active level for tamper - TAMPTRG: TAMPTRG, + @"TAMPTRG[0]": TAMPTRG, /// Tamper interrupt enable TAMPIE: u1, - reserved7: u4, + /// Tamper detection enable + @"TAMPE[1]": u1, + /// Active level for tamper + @"TAMPTRG[1]": TAMPTRG, + /// Tamper detection enable + @"TAMPE[2]": u1, + /// Active level for tamper + @"TAMPTRG[2]": TAMPTRG, /// Activate timestamp on tamper detection event TAMPTS: u1, /// Tamper sampling frequency @@ -423413,12 +424251,19 @@ pub const types = struct { /// Tamper configuration register TAMPCR: mmio.Mmio(packed struct(u32) { /// Tamper detection enable - TAMPE: u1, + @"TAMPE[0]": u1, /// Active level for tamper - TAMPTRG: TAMPTRG, + @"TAMPTRG[0]": TAMPTRG, /// Tamper interrupt enable TAMPIE: u1, - reserved7: u4, + /// Tamper detection enable + @"TAMPE[1]": u1, + /// Active level for tamper + @"TAMPTRG[1]": TAMPTRG, + /// Tamper detection enable + @"TAMPE[2]": u1, + /// Active level for tamper + @"TAMPTRG[2]": TAMPTRG, /// Activate timestamp on tamper detection event TAMPTS: u1, /// Tamper sampling frequency diff --git a/port/stmicro/stm32/src/generate.zig b/port/stmicro/stm32/src/generate.zig index 9d5af883..46f7f18d 100644 --- a/port/stmicro/stm32/src/generate.zig +++ b/port/stmicro/stm32/src/generate.zig @@ -331,11 +331,12 @@ pub fn main() !void { if (item.object.get("fieldset")) |fieldset| blk: { const fieldset_key = try std.fmt.allocPrint(allocator, "fieldset/{s}", .{fieldset.string}); const fieldset_value = (register_file.value.object.get(fieldset_key) orelse break :blk).object; - for (fieldset_value.get("fields").?.array.items) |field| { + next_field: for (fieldset_value.get("fields").?.array.items) |field| { const field_name = field.object.get("name").?.string; const field_description: ?[]const u8 = if (field.object.get("description")) |desc| desc.string else null; switch (field.object.get("bit_offset").?) { .integer => |int| { + // This is the standard bit offset case most items will be in this catigory const bit_offset = int; const bit_size = field.object.get("bit_size").?.integer; const enum_id: ?regz.Database.EnumID = if (field.object.get("enum")) |enum_name| @@ -344,9 +345,34 @@ pub fn main() !void { null; var array_count: ?u16 = null; var array_stride: ?u8 = null; - if (field.object.get("array")) |array| { - array_count = if (array.object.get("len")) |len| @intCast(len.integer) else null; - array_stride = if (array.object.get("stride")) |stride| @intCast(stride.integer) else null; + if (field.object.get("array")) |array_obj| { + const object_map = array_obj.object; + // This is the typical case for array objects e.g., @"A[0]", @"A[1]" registers + // these are evenly spaced and much nicer to work with. + + array_count = if (object_map.get("len")) |len| @intCast(len.integer) else null; + array_stride = if (object_map.get("stride")) |stride| @intCast(stride.integer) else null; + + // This category where there is an array of items, but it is given by + // individual offsets as opposed to a count + stride. This is used when strides are + // inconsistent between elements + + if (object_map.get("offsets")) |positions| { + for (positions.array.items, 0..) |position, idx| { + const field_name_irregular_stride = try std.fmt.allocPrint(allocator, "{s}[{}]", .{ field_name, idx }); + + try db.add_register_field(register_id, .{ + .name = field_name_irregular_stride, + .description = field_description, + .offset_bits = @intCast(position.integer + bit_offset), + .size_bits = @intCast(bit_size), + .enum_id = enum_id, + .count = null, + .stride = null, + }); + } + continue :next_field; + } } try db.add_register_field(register_id, .{ @@ -360,6 +386,8 @@ pub fn main() !void { }); }, .array => |arr| { + // This case is for discontinuous fields where the first few bits are + // separated from the rest of the field by padding or other fields if (arr.items.len != 2) { //This should never happen, because the input data as of yet doesn't contain this. std.log.warn("skipping {s}, it's an non-consecutive field with more than two parts", .{field_name});