From e08f948a2961970a62fed653d9a96af1f8bf603f Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Mon, 20 Jan 2025 08:51:51 -0800 Subject: [PATCH] update to master --- build-internals/build.zig | 2 +- build.zig | 16 ++-- core/src/core/usb.zig | 83 ++++++++----------- core/src/cpus/avr5.zig | 6 +- core/src/cpus/cortex_m.zig | 4 +- core/src/cpus/cortex_m/m3.zig | 20 ++--- core/src/cpus/cortex_m/m33.zig | 20 ++--- core/src/cpus/cortex_m/m4.zig | 20 ++--- core/src/cpus/cortex_m/m7.zig | 20 ++--- core/src/cpus/riscv32.zig | 2 +- core/src/microzig.zig | 57 +++++++++++++ core/src/mmio.zig | 4 +- core/src/start.zig | 76 ++--------------- core/src/utilities.zig | 24 +++--- drivers/build.zig | 2 +- .../rp2xxx/src/rp2040_only/adc.zig | 2 +- .../rp2xxx/src/rp2040_only/flash_program.zig | 2 +- .../rp2xxx/src/rp2040_only/i2c_bus_scan.zig | 2 +- .../rp2xxx/src/rp2040_only/random.zig | 2 +- .../rp2xxx/src/rp2040_only/rtc.zig | 2 +- .../rp2xxx/src/rp2040_only/tiles.zig | 2 +- .../rp2xxx/src/rp2040_only/uart_log.zig | 2 +- .../rp2xxx/src/rp2040_only/usb_cdc.zig | 2 +- .../rp2xxx/src/rp2040_only/usb_hid.zig | 2 +- .../raspberrypi/rp2xxx/src/squarewave.zig | 2 +- .../esp/src/cpus/espressif-riscv.zig | 2 +- .../gd32/src/hals/GD32VF103/pins.zig | 30 +++---- port/nxp/lpc/build.zig | 2 +- port/raspberrypi/rp2xxx/patches/rp2040.zig | 5 +- port/raspberrypi/rp2xxx/src/cpus/hazard3.zig | 6 +- .../rp2xxx/src/hal/clocks/common.zig | 2 +- port/raspberrypi/rp2xxx/src/hal/image_def.zig | 2 +- port/raspberrypi/rp2xxx/src/hal/pins.zig | 24 +++--- .../raspberrypi/rp2xxx/src/hal/pio/rp2040.zig | 2 +- .../raspberrypi/rp2xxx/src/hal/pio/rp2350.zig | 2 +- port/raspberrypi/rp2xxx/src/hal/rom.zig | 16 ++-- .../stmicro/stm32/src/hals/STM32F103/pins.zig | 30 +++---- port/wch/ch32v/build.zig | 6 +- port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig | 4 +- port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig | 4 +- port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig | 4 +- port/wch/ch32v/src/hals/ch32v003/pins.zig | 32 +++---- port/wch/ch32v/src/hals/pins.zig | 32 +++---- tools/regz/src/mmio.zig | 6 +- 44 files changed, 287 insertions(+), 300 deletions(-) diff --git a/build-internals/build.zig b/build-internals/build.zig index 3fcda4d1b..24bdb3eee 100644 --- a/build-internals/build.zig +++ b/build-internals/build.zig @@ -4,7 +4,7 @@ const LazyPath = Build.LazyPath; const Module = Build.Module; const regz = @import("regz"); -const Patch = regz.patch.Patch; +pub const Patch = regz.patch.Patch; const uf2 = @import("uf2"); const FamilyId = uf2.FamilyId; diff --git a/build.zig b/build.zig index 13c79422d..e751dc99f 100644 --- a/build.zig +++ b/build.zig @@ -116,13 +116,13 @@ pub const PortSelect = blk: { fields = fields ++ [_]std.builtin.Type.StructField{.{ .name = port.name, .type = bool, - .default_value = @as(*const anyopaque, @ptrCast(&false)), + .default_value_ptr = @as(*const anyopaque, @ptrCast(&false)), .is_comptime = false, .alignment = @alignOf(bool), }}; } break :blk @Type(.{ - .Struct = .{ + .@"struct" = .{ .layout = .auto, .fields = fields, .decls = &.{}, @@ -140,13 +140,13 @@ pub const PortCache = blk: { fields = fields ++ [_]std.builtin.Type.StructField{.{ .name = port.name, .type = typ, - .default_value = @as(*const anyopaque, @ptrCast(&@as(typ, null))), + .default_value_ptr = @as(*const anyopaque, @ptrCast(&@as(typ, null))), .is_comptime = false, .alignment = @alignOf(typ), }}; } break :blk @Type(.{ - .Struct = .{ + .@"struct" = .{ .layout = .auto, .fields = fields, .decls = &.{}, @@ -194,7 +194,7 @@ pub fn MicroBuild(port_select: PortSelect) type { fields = fields ++ [_]std.builtin.Type.StructField{.{ .name = port.name, .type = typ, - .default_value = null, + .default_value_ptr = null, .is_comptime = false, .alignment = @alignOf(typ), }}; @@ -202,7 +202,7 @@ pub fn MicroBuild(port_select: PortSelect) type { } break :blk @Type(.{ - .Struct = .{ + .@"struct" = .{ .layout = .auto, .fields = fields, .decls = &.{}, @@ -711,7 +711,7 @@ pub inline fn custom_lazy_import( const deps = build_runner.dependencies; const pkg_hash = custom_find_import_pkg_hash_or_fatal(dep_name); - inline for (@typeInfo(deps.packages).Struct.decls) |decl| { + inline for (@typeInfo(deps.packages).@"struct".decls) |decl| { if (comptime std.mem.eql(u8, decl.name, pkg_hash)) { const pkg = @field(deps.packages, decl.name); const available = !@hasDecl(pkg, "available") or pkg.available; @@ -733,7 +733,7 @@ inline fn custom_find_import_pkg_hash_or_fatal(comptime dep_name: []const u8) [] const build_runner = @import("root"); const deps = build_runner.dependencies; - const pkg_deps = comptime for (@typeInfo(deps.packages).Struct.decls) |decl| { + const pkg_deps = comptime for (@typeInfo(deps.packages).@"struct".decls) |decl| { const pkg_hash = decl.name; const pkg = @field(deps.packages, pkg_hash); if (@hasDecl(pkg, "build_zig") and pkg.build_zig == @This()) break pkg.deps; diff --git a/core/src/core/usb.zig b/core/src/core/usb.zig index 5cae2c0a5..f9bc76720 100644 --- a/core/src/core/usb.zig +++ b/core/src/core/usb.zig @@ -22,7 +22,6 @@ pub const vendor = @import("usb/vendor.zig"); pub const utils = @import("usb/utils.zig"); pub const templates = @import("usb/templates.zig"); - const DescType = types.DescType; const Dir = types.Dir; const Endpoint = types.Endpoint; @@ -55,7 +54,7 @@ pub fn Usb(comptime f: anytype) type { var clk_init: bool = false; var itf_to_drv: [f.cfg_max_interfaces_count]u8 = .{0} ** f.cfg_max_interfaces_count; var ep_to_drv: [f.cfg_max_endpoints_count][2]u8 = .{.{0} ** 2} ** f.cfg_max_endpoints_count; - pub const max_packet_size = if(f.high_speed) 512 else 64; + pub const max_packet_size = if (f.high_speed) 512 else 64; const drvid_invalid = 0xff; /// The callbacks passed provided by the caller @@ -80,7 +79,7 @@ pub fn Usb(comptime f: anytype) type { // descriptors for transmission. var tmp: [128]u8 = .{0} ** 128; // Keeps track of sent data from tmp buffer - var buffer_reader = BufferReader { .buffer = &.{} }; + var buffer_reader = BufferReader{ .buffer = &.{} }; // Last setup packet request var setup_packet: types.SetupPacket = undefined; // Class driver associated with last setup request if any @@ -89,10 +88,9 @@ pub fn Usb(comptime f: anytype) type { // Command endpoint utilities const CmdEndpoint = struct { - /// Command response utility function that can split long data in multiple packets fn send_cmd_response(data: []const u8, expected_max_length: u16) void { - S.buffer_reader = BufferReader { .buffer = data[0..@min(data.len, expected_max_length)] }; + S.buffer_reader = BufferReader{ .buffer = data[0..@min(data.len, expected_max_length)] }; const data_chunk = S.buffer_reader.try_peek(64); if (data_chunk.len > 0) { @@ -127,13 +125,7 @@ pub fn Usb(comptime f: anytype) type { } fn device() types.UsbDevice { - return .{ - .fn_ready = device_ready, - .fn_control_transfer = device_control_transfer, - .fn_control_ack = device_control_ack, - .fn_endpoint_open = device_endpoint_open, - .fn_endpoint_transfer = device_endpoint_transfer - }; + return .{ .fn_ready = device_ready, .fn_control_transfer = device_control_transfer, .fn_control_ack = device_control_ack, .fn_endpoint_open = device_endpoint_open, .fn_endpoint_transfer = device_endpoint_transfer }; } fn device_ready() bool { @@ -180,7 +172,7 @@ pub fn Usb(comptime f: anytype) type { fn configuration_reset() void { @memset(&itf_to_drv, drvid_invalid); - @memset(&ep_to_drv, .{drvid_invalid, drvid_invalid}); + @memset(&ep_to_drv, .{ drvid_invalid, drvid_invalid }); } /// Usb task function meant to be executed in regular intervals after @@ -194,7 +186,6 @@ pub fn Usb(comptime f: anytype) type { // Device Specific Request const DeviceRequestProcessor = struct { - fn process_setup_request(setup: *const types.SetupPacket) !void { switch (setup.request_type.type) { .Class => { @@ -221,7 +212,7 @@ pub fn Usb(comptime f: anytype) type { if (cfg_num > 0) { try process_set_config(cfg_num - 1); // TODO: call mount callback if any - } else { + } else { // TODO: call umount callback if any } } @@ -234,10 +225,10 @@ pub fn Usb(comptime f: anytype) type { if (descriptor_type) |dt| { try process_get_descriptor(setup, dt); } - } + }, } }, - else => {} + else => {}, } } @@ -246,15 +237,15 @@ pub fn Usb(comptime f: anytype) type { .Device => { if (S.debug_mode) std.log.info(" Device", .{}); - var bw = BufferWriter { .buffer = &S.tmp }; + var bw = BufferWriter{ .buffer = &S.tmp }; try bw.write(&usb_config.?.device_descriptor.serialize()); CmdEndpoint.send_cmd_response(bw.get_written_slice(), setup.length); }, .Config => { if (S.debug_mode) std.log.info(" Config", .{}); - - var bw = BufferWriter { .buffer = &S.tmp }; + + var bw = BufferWriter{ .buffer = &S.tmp }; try bw.write(usb_config.?.config_descriptor); CmdEndpoint.send_cmd_response(bw.get_written_slice(), setup.length); @@ -274,7 +265,7 @@ pub fn Usb(comptime f: anytype) type { const s = usb_config.?.descriptor_strings[i - 1]; const len = 2 + s.len; - var wb = BufferWriter { .buffer = &S.tmp }; + var wb = BufferWriter{ .buffer = &S.tmp }; try wb.write_int(u8, @intCast(len)); try wb.write_int(u8, 0x03); try wb.write(s); @@ -282,7 +273,7 @@ pub fn Usb(comptime f: anytype) type { break :StringBlk wb.get_written_slice(); } }; - + CmdEndpoint.send_cmd_response(bytes, setup.length); }, .Interface => { @@ -304,12 +295,12 @@ pub fn Usb(comptime f: anytype) type { .num_configurations = usb_config.?.device_descriptor.num_configurations, }; - var bw = BufferWriter { .buffer = &S.tmp }; + var bw = BufferWriter{ .buffer = &S.tmp }; try bw.write(&dqd.serialize()); CmdEndpoint.send_cmd_response(bw.get_written_slice(), setup.length); }, - else => {} + else => {}, } } @@ -359,7 +350,9 @@ pub fn Usb(comptime f: anytype) type { fn bind_endpoints_to_driver(drv_bos_cfg: []const u8, drv_idx: u8) void { var curr_bos_cfg = drv_bos_cfg; - while (curr_bos_cfg.len > 0) : ({curr_bos_cfg = BosConfig.get_desc_next(curr_bos_cfg);}) { + while (curr_bos_cfg.len > 0) : ({ + curr_bos_cfg = BosConfig.get_desc_next(curr_bos_cfg); + }) { if (BosConfig.try_get_desc_as(types.EndpointDescriptor, curr_bos_cfg)) |desc_ep| { const ep_addr = desc_ep.endpoint_address; ep_to_drv[Endpoint.num_from_address(ep_addr)][Endpoint.dir_from_address(ep_addr).as_number()] = drv_idx; @@ -384,8 +377,7 @@ pub fn Usb(comptime f: anytype) type { // Endpoint Specific Request const EndpointRequestProcessor = struct { - fn process_setup_request(_: *const types.SetupPacket) !void { - } + fn process_setup_request(_: *const types.SetupPacket) !void {} }; // Check which interrupt flags are set. @@ -407,9 +399,8 @@ pub fn Usb(comptime f: anytype) type { .Device => try DeviceRequestProcessor.process_setup_request(&setup), .Interface => try InterfaceRequestProcessor.process_setup_request(&setup), .Endpoint => try EndpointRequestProcessor.process_setup_request(&setup), - else => {} + else => {}, } - } // Events on one or more buffers? (In practice, always one.) @@ -426,24 +417,24 @@ pub fn Usb(comptime f: anytype) type { switch (epb.endpoint_address) { Endpoint.EP0_IN_ADDR => { if (debug) std.log.info(" EP0_IN_ADDR", .{}); - + const buffer_reader = &S.buffer_reader; - + // We use this opportunity to finish the delayed // SetAddress request, if there is one: if (S.new_address) |addr| { // Change our address: f.set_address(@intCast(addr)); } - + if (epb.buffer.len > 0 and buffer_reader.get_remaining_bytes_count() > 0) { _ = buffer_reader.try_advance(epb.buffer.len); const next_data_chunk = buffer_reader.try_peek(64); if (next_data_chunk.len > 0) { f.usb_start_tx( - Endpoint.EP0_IN_ADDR, - next_data_chunk, - ); + Endpoint.EP0_IN_ADDR, + next_data_chunk, + ); } else { f.usb_start_rx( Endpoint.EP0_OUT_ADDR, @@ -497,7 +488,7 @@ pub fn Usb(comptime f: anytype) type { S.new_address = null; S.configured = false; S.started = false; - S.buffer_reader = BufferReader { .buffer = &.{} }; + S.buffer_reader = BufferReader{ .buffer = &.{} }; } // If we have been configured but haven't reached this point yet, set up @@ -513,13 +504,7 @@ pub fn Usb(comptime f: anytype) type { // Driver support stuctures // +++++++++++++++++++++++++++++++++++++++++++++++++ -pub const DeviceConfiguration = struct { - device_descriptor: *const types.DeviceDescriptor, - config_descriptor: []const u8, - lang_descriptor: []const u8, - descriptor_strings: []const []const u8, - drivers: []types.UsbClassDriver -}; +pub const DeviceConfiguration = struct { device_descriptor: *const types.DeviceDescriptor, config_descriptor: []const u8, lang_descriptor: []const u8, descriptor_strings: []const []const u8, drivers: []types.UsbClassDriver }; /// USB interrupt status /// @@ -571,7 +556,7 @@ const BufferWriter = struct { pos: usize = 0, endian: std.builtin.Endian = builtin.cpu.arch.endian(), - pub const Error = error{ EndOfBuffer }; + pub const Error = error{EndOfBuffer}; /// Moves forward write cursor by the provided number of bytes. pub fn advance(self: *@This(), bytes: usize) Error!void { @@ -583,12 +568,12 @@ const BufferWriter = struct { pub fn write(self: *@This(), data: []const u8) Error!void { try self.bound_check(data.len); defer self.advance_unsafe(data.len); - @memcpy(self.buffer[self.pos..self.pos + data.len], data); + @memcpy(self.buffer[self.pos .. self.pos + data.len], data); } /// Writes an int with respect to the buffer's endianness and moves write cursor forward by int size. pub fn write_int(self: *@This(), comptime T: type, value: T) Error!void { - const size = @divExact(@typeInfo(T).Int.bits, 8); + const size = @divExact(@typeInfo(T).int.bits, 8); try self.bound_check(size); defer self.advance_unsafe(size); std.mem.writeInt(T, self.buffer[self.pos..][0..size], value, self.endian); @@ -597,7 +582,7 @@ const BufferWriter = struct { /// Writes an int with respect to the buffer's endianness but skip bound check. /// Useful in cases where the bound can be checked once for batch of ints. pub fn write_int_unsafe(self: *@This(), comptime T: type, value: T) void { - const size = @divExact(@typeInfo(T).Int.bits, 8); + const size = @divExact(@typeInfo(T).int.bits, 8); defer self.advance_unsafe(size); std.mem.writeInt(T, self.buffer[self.pos..][0..size], value, self.endian); } @@ -634,13 +619,13 @@ const BufferReader = struct { pub fn try_read(self: *@This(), bytes: usize) []const u8 { const size = @min(bytes, self.buffer.len - self.pos); defer self.advance_unsafe(size); - return self.buffer[self.pos..self.pos + size]; + return self.buffer[self.pos .. self.pos + size]; } /// Attempts to read the given amount of bytes (or less if close to buffer end) without advancing the read cursor. pub fn try_peek(self: *@This(), bytes: usize) []const u8 { const size = @min(bytes, self.buffer.len - self.pos); - return self.buffer[self.pos..self.pos + size]; + return self.buffer[self.pos .. self.pos + size]; } /// Returns the number of bytes remaining from the current read cursor position to the end of the underlying buffer. diff --git a/core/src/cpus/avr5.zig b/core/src/cpus/avr5.zig index bb84bb24a..6421d1158 100644 --- a/core/src/cpus/avr5.zig +++ b/core/src/cpus/avr5.zig @@ -31,7 +31,7 @@ pub const vector_table_asm = blk: { const asm_str: []const u8 = "jmp microzig_start\n"; //const has_interrupts = @hasDecl(root, "microzig_options"); - //for (@typeInfo(root.VectorTableOptions).Struct.fields) |field| { + //for (@typeInfo(root.VectorTableOptions).@"struct".fields) |field| { // const new_insn = if (has_interrupts) overload: { // const interrupts = root.microzig_options.interrupts; // if (@hasDecl(interrupts, field.name)) { @@ -62,7 +62,7 @@ export fn abort() noreturn { pub fn export_startup_logic() void { _ = startup_logic; - @export(vector_table, .{ + @export(&vector_table, .{ .name = "_start", }); } @@ -87,7 +87,7 @@ fn make_isr_handler(comptime name: []const u8, comptime func: anytype) type { comptime { const options = .{ .name = exported_name, .linkage = .Strong }; - @export(isr_vector, options); + @export(&isr_vector, options); } }; } diff --git a/core/src/cpus/cortex_m.zig b/core/src/cpus/cortex_m.zig index 14dae0296..5c02ff732 100644 --- a/core/src/cpus/cortex_m.zig +++ b/core/src/cpus/cortex_m.zig @@ -85,7 +85,7 @@ pub const startup_logic = struct { }; pub fn export_startup_logic() void { - @export(startup_logic._start, .{ + @export(&startup_logic._start, .{ .name = "_start", }); } @@ -106,7 +106,7 @@ pub const vector_table: VectorTable = blk: { }; if (@hasDecl(root, "microzig_options")) { - for (@typeInfo(root.VectorTableOptions).Struct.fields) |field| + for (@typeInfo(microzig.VectorTableOptions).@"struct".fields) |field| @field(tmp, field.name) = @field(root.microzig_options.interrupts, field.name); } diff --git a/core/src/cpus/cortex_m/m3.zig b/core/src/cpus/cortex_m/m3.zig index c0fc782dc..ac326a137 100644 --- a/core/src/cpus/cortex_m/m3.zig +++ b/core/src/cpus/cortex_m/m3.zig @@ -131,23 +131,23 @@ pub const MemoryProtectionUnit = extern struct { reserved0: u24, }), /// MPU Region Base Address Register - RBAR: RBAR, + RBAR: RBAR_Register, /// MPU Region Attribute and Size Register - RASR: RASR, + RASR: RASR_Register, /// MPU Alias 1 Region Base Address Register - RBAR_A1: RBAR, + RBAR_A1: RBAR_Register, /// MPU Alias 1 Region Attribute and Size Register - RASR_A1: RASR, + RASR_A1: RASR_Register, /// MPU Alias 2 Region Base Address Register - RBAR_A2: RBAR, + RBAR_A2: RBAR_Register, /// MPU Alias 2 Region Attribute and Size Register - RASR_A2: RASR, + RASR_A2: RASR_Register, /// MPU Alias 3 Region Base Address Register - RBAR_A3: RBAR, + RBAR_A3: RBAR_Register, /// MPU Alias 3 Region Attribute and Size Register - RASR_A3: RASR, + RASR_A3: RASR_Register, - pub const RBAR = mmio.Mmio(packed struct(u32) { + pub const RBAR_Register = mmio.Mmio(packed struct(u32) { /// MPU region field. REGION: u4, /// MPU region number valid bit. @@ -156,7 +156,7 @@ pub const MemoryProtectionUnit = extern struct { ADDR: u27, }); - pub const RASR = mmio.Mmio(packed struct(u32) { + pub const RASR_Register = mmio.Mmio(packed struct(u32) { /// Region enable bit. ENABLE: u1, /// Specifies the size of the MPU protection region. diff --git a/core/src/cpus/cortex_m/m33.zig b/core/src/cpus/cortex_m/m33.zig index f1955b85d..9deb1100c 100644 --- a/core/src/cpus/cortex_m/m33.zig +++ b/core/src/cpus/cortex_m/m33.zig @@ -138,21 +138,21 @@ pub const MemoryProtectionUnit = extern struct { reserved0: u24, }), /// MPU Region Base Address Register. - RBAR: RBAR, + RBAR: RBAR_Register, /// MPU Region Limit Address Register. - RLAR: RLAR, + RLAR: RLAR_Register, /// MPU Region Base Address Register Alias 1. - RBAR_A1: RBAR, + RBAR_A1: RBAR_Register, /// MPU Region Base Address Register Alias 2. - RBAR_A2: RBAR, + RBAR_A2: RBAR_Register, /// MPU Region Base Address Register Alias 3. - RBAR_A3: RBAR, + RBAR_A3: RBAR_Register, /// MPU Region Limit Address Register Alias 1. - RLAR_A1: RLAR, + RLAR_A1: RLAR_Register, /// MPU Region Base Address Register Alias 2. - RLAR_A2: RLAR, + RLAR_A2: RLAR_Register, /// MPU Region Base Address Register Alias 3. - RLAR_A3: RLAR, + RLAR_A3: RLAR_Register, reserved0: [20]u8, /// MPU Memory Addribute Indirection Register 0. MPU_MAIR0: u32, @@ -160,7 +160,7 @@ pub const MemoryProtectionUnit = extern struct { MPU_MAIR1: u32, /// MPU Region Address Register format. - pub const RBAR = mmio.Mmio(packed struct(u32) { + pub const RBAR_Register = mmio.Mmio(packed struct(u32) { /// Execute Never defines if code can be executed from this region. XN: u1, /// Access permissions. @@ -173,7 +173,7 @@ pub const MemoryProtectionUnit = extern struct { }); /// MPU Region Limit Address Register format. - pub const RLAR = mmio.Mmio(packed struct(u32) { + pub const RLAR_Register = mmio.Mmio(packed struct(u32) { /// Enable the region. EN: u1, /// Attribue Index associates a set of attributes in the MPU MAIR0 and MPU MAIR1 fields. diff --git a/core/src/cpus/cortex_m/m4.zig b/core/src/cpus/cortex_m/m4.zig index 9f64d71ec..345bd72de 100644 --- a/core/src/cpus/cortex_m/m4.zig +++ b/core/src/cpus/cortex_m/m4.zig @@ -132,23 +132,23 @@ pub const MemoryProtectionUnit = extern struct { reserved0: u24, }), /// MPU Region Base Address Register. - RBAR: RBAR, + RBAR: RBAR_Register, /// MPU Region Attribute and Size Register. - RASR: RASR, + RASR: RASR_Register, /// MPU Alias 1 Region Base Address Register. - RBAR_A1: RBAR, + RBAR_A1: RBAR_Register, /// MPU Alias 1 Region Attribute and Size Register. - RASR_A1: RASR, + RASR_A1: RASR_Register, /// MPU Alias 2 Region Base Address Register. - RBAR_A2: RBAR, + RBAR_A2: RBAR_Register, /// MPU Alias 2 Region Attribute and Size Register. - RASR_A2: RASR, + RASR_A2: RASR_Register, /// MPU Alias 3 Region Base Address Register. - RBAR_A3: RBAR, + RBAR_A3: RBAR_Register, /// MPU Alias 3 Region Attribute and Size Register. - RASR_A3: RASR, + RASR_A3: RASR_Register, - pub const RBAR = mmio.Mmio(packed struct(u32) { + pub const RBAR_Register = mmio.Mmio(packed struct(u32) { /// MPU region field. REGION: u4, /// MPU region number valid bit. @@ -157,7 +157,7 @@ pub const MemoryProtectionUnit = extern struct { ADDR: u27, }); - pub const RASR = mmio.Mmio(packed struct(u32) { + pub const RASR_Register = mmio.Mmio(packed struct(u32) { /// Region enable bit. ENABLE: u1, /// Specifies the size of the MPU protection region. diff --git a/core/src/cpus/cortex_m/m7.zig b/core/src/cpus/cortex_m/m7.zig index 24ecb72e4..e5cd57229 100644 --- a/core/src/cpus/cortex_m/m7.zig +++ b/core/src/cpus/cortex_m/m7.zig @@ -120,29 +120,29 @@ pub const MemoryProtectionUnit = extern struct { padding: u24, }), /// MPU Region Base Address Register - RBAR: RBAR, + RBAR: RBAR_Register, /// MPU Region Attribute and Size Register - RASR: RASR, + RASR: RASR_Register, /// MPU Alias 1 Region Base Address Register - RBAR_A1: RBAR, + RBAR_A1: RBAR_Register, /// MPU Alias 1 Region Attribute and Size Register - RASR_A1: RASR, + RASR_A1: RASR_Register, /// MPU Alias 2 Region Base Address Register - RBAR_A2: RBAR, + RBAR_A2: RBAR_Register, /// MPU Alias 2 Region Attribute and Size Register - RASR_A2: RASR, + RASR_A2: RASR_Register, /// MPU Alias 3 Region Base Address Register - RBAR_A3: RBAR, + RBAR_A3: RBAR_Register, /// MPU Alias 3 Region Attribute and Size Register - RASR_A3: RASR, + RASR_A3: RASR_Register, - pub const RBAR = mmio.Mmio(packed struct(u32) { + pub const RBAR_Register = mmio.Mmio(packed struct(u32) { REGION: u4, VALID: u1, ADDR: u27, }); - pub const RASR = mmio.Mmio(packed struct(u32) { + pub const RASR_Register = mmio.Mmio(packed struct(u32) { /// Region enable bit ENABLE: u1, /// Region Size diff --git a/core/src/cpus/riscv32.zig b/core/src/cpus/riscv32.zig index 5b58f6693..8f896977e 100644 --- a/core/src/cpus/riscv32.zig +++ b/core/src/cpus/riscv32.zig @@ -82,7 +82,7 @@ pub const startup_logic = struct { }; pub fn export_startup_logic() void { - @export(startup_logic._start, .{ + @export(&startup_logic._start, .{ .name = "_start", }); } diff --git a/core/src/microzig.zig b/core/src/microzig.zig index 2b85c2925..01713545c 100644 --- a/core/src/microzig.zig +++ b/core/src/microzig.zig @@ -64,6 +64,63 @@ pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noretu hang(); } +pub const VectorTableOptions = if (@hasDecl(chip, "VectorTable")) +blk: { + const VectorTable = chip.VectorTable; + const fields_with_default = fields_with_default: { + var count = 0; + for (@typeInfo(VectorTable).@"struct".fields) |field| { + if (field.default_value_ptr != null) + count += 1; + } + + break :fields_with_default count; + }; + + var fields: [fields_with_default]std.builtin.Type.StructField = undefined; + var idx = 0; + for (@typeInfo(VectorTable).@"struct".fields) |field| { + if (field.default_value_ptr == null) + continue; + + fields[idx] = field; + idx += 1; + } + + break :blk @Type(.{ + .@"struct" = .{ + .fields = &fields, + .layout = .auto, + .decls = &.{}, + .is_tuple = false, + }, + }); +} else struct {}; + +pub const Options = struct { + interrupts: VectorTableOptions = .{}, + log_level: std.log.Level = std.log.default_level, + log_scope_levels: []const std.log.ScopeLevel = &.{}, + logFn: fn ( + comptime message_level: std.log.Level, + comptime scope: @TypeOf(.enum_literal), + comptime format: []const u8, + args: anytype, + ) void = struct { + fn log( + comptime message_level: std.log.Level, + comptime scope: @Type(.enum_literal), + comptime format: []const u8, + args: anytype, + ) void { + _ = message_level; + _ = scope; + _ = format; + _ = args; + } + }.log, +}; + /// Hangs the processor and will stop doing anything useful. Use with caution! pub fn hang() noreturn { cpu.disable_interrupts(); diff --git a/core/src/mmio.zig b/core/src/mmio.zig index c27df1f59..87f7f899e 100644 --- a/core/src/mmio.zig +++ b/core/src/mmio.zig @@ -38,7 +38,7 @@ pub fn Mmio(comptime PackedT: type) type { pub inline fn modify(addr: *volatile Self, fields: anytype) void { var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + inline for (@typeInfo(@TypeOf(fields)).@"struct".fields) |field| { @field(val, field.name) = @field(fields, field.name); } write(addr, val); @@ -46,7 +46,7 @@ pub fn Mmio(comptime PackedT: type) type { pub inline fn toggle(addr: *volatile Self, fields: anytype) void { var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + inline for (@typeInfo(@TypeOf(fields)).@"struct".fields) |field| { @field(val, field.name) = @field(val, field.name) ^ @field(fields, field.name); } write(addr, val); diff --git a/core/src/start.zig b/core/src/start.zig index 988f65b06..727eca4e1 100644 --- a/core/src/start.zig +++ b/core/src/start.zig @@ -5,63 +5,7 @@ const app = @import("app"); // Use microzig panic handler if not defined by an application pub const panic = if (!@hasDecl(app, "panic")) microzig.panic else app.panic; -pub const VectorTableOptions = if (@hasDecl(microzig.chip, "VectorTable")) blk: { - const VectorTable = microzig.chip.VectorTable; - const fields_with_default = fields_with_default: { - var count = 0; - for (@typeInfo(VectorTable).Struct.fields) |field| { - if (field.default_value != null) - count += 1; - } - - break :fields_with_default count; - }; - - var fields: [fields_with_default]std.builtin.Type.StructField = undefined; - var idx = 0; - for (@typeInfo(VectorTable).Struct.fields) |field| { - if (field.default_value == null) - continue; - - fields[idx] = field; - idx += 1; - } - - break :blk @Type(.{ - .Struct = .{ - .fields = &fields, - .layout = .auto, - .decls = &.{}, - .is_tuple = false, - }, - }); -} else struct {}; - -pub const Options = struct { - interrupts: VectorTableOptions = .{}, - log_level: std.log.Level = std.log.default_level, - log_scope_levels: []const std.log.ScopeLevel = &.{}, - logFn: fn ( - comptime message_level: std.log.Level, - comptime scope: @TypeOf(.enum_literal), - comptime format: []const u8, - args: anytype, - ) void = struct { - fn log( - comptime message_level: std.log.Level, - comptime scope: @Type(.EnumLiteral), - comptime format: []const u8, - args: anytype, - ) void { - _ = message_level; - _ = scope; - _ = format; - _ = args; - } - }.log, -}; - -pub const microzig_options: Options = if (@hasDecl(app, "microzig_options")) app.microzig_options else .{}; +pub const microzig_options: microzig.Options = if (@hasDecl(app, "microzig_options")) app.microzig_options else .{}; // Conditionally provide a default no-op logFn if app does not have one // defined. Parts of microzig use the stdlib logging facility and @@ -88,18 +32,18 @@ comptime { // that is either called (Cortex-M) or executed (AVR) when initalized. // Allow board and chip to override CPU vector table. - const export_opts = .{ + const export_opts = std.builtin.ExportOptions{ .name = "vector_table", .section = "microzig_flash_start", .linkage = .strong, }; if ((microzig.board != void and @hasDecl(microzig.board, "vector_table"))) - @export(microzig.board.vector_table, export_opts) + @export(µzig.board.vector_table, export_opts) else if (@hasDecl(microzig.chip, "vector_table")) - @export(microzig.chip.vector_table, export_opts) + @export(µzig.chip.vector_table, export_opts) else if (@hasDecl(microzig.cpu, "vector_table")) - @export(microzig.cpu.vector_table, export_opts) + @export(µzig.cpu.vector_table, export_opts) else if (@hasDecl(app, "interrupts")) @compileError("interrupts not configured"); } @@ -121,12 +65,12 @@ export fn microzig_main() noreturn { const info: std.builtin.Type = @typeInfo(@TypeOf(main)); const invalid_main_msg = "main must be either 'pub fn main() void' or 'pub fn main() !void'."; - if (info != .Fn or info.Fn.params.len > 0) + if (info != .@"fn" or info.@"fn".params.len > 0) @compileError(invalid_main_msg); - const return_type = info.Fn.return_type orelse @compileError(invalid_main_msg); + const return_type = info.@"fn".return_type orelse @compileError(invalid_main_msg); - if (info.Fn.calling_convention == .Async) + if (info.@"fn".calling_convention == .@"async") @compileError("TODO: Embedded event loop not supported yet. Please try again later."); // A hal can export a default init function that runs before main for @@ -138,7 +82,7 @@ export fn microzig_main() noreturn { else if (microzig.hal != void and @hasDecl(microzig.hal, "init")) microzig.hal.init(); - if (@typeInfo(return_type) == .ErrorUnion) { + if (@typeInfo(return_type) == .error_union) { main() catch |err| { // TODO: // - Compute maximum size on the type of "err" @@ -168,8 +112,6 @@ pub const sections = struct { }; pub fn initialize_system_memories() void { - @setCold(true); - // fill .bss with zeroes { const bss_start: [*]u8 = @ptrCast(§ions.microzig_bss_start); diff --git a/core/src/utilities.zig b/core/src/utilities.zig index f3ba89908..146e6e7d1 100644 --- a/core/src/utilities.zig +++ b/core/src/utilities.zig @@ -4,28 +4,28 @@ const std = @import("std"); /// with similar operations to those of a slice. pub fn Slice_Vector(comptime Slice: type) type { const type_info = @typeInfo(Slice); - if (type_info != .Pointer) + if (type_info != .pointer) @compileError("Slice must have a slice type!"); - if (type_info.Pointer.size != .Slice) + if (type_info.pointer.size != .slice) @compileError("Slice must have a slice type!"); const item_ptr_info: std.builtin.Type = .{ - .Pointer = .{ - .alignment = @min(type_info.Pointer.alignment, @alignOf(type_info.Pointer.child)), - .size = .One, - .child = type_info.Pointer.child, - .address_space = type_info.Pointer.address_space, - .is_const = type_info.Pointer.is_const, - .is_volatile = type_info.Pointer.is_volatile, - .is_allowzero = type_info.Pointer.is_allowzero, - .sentinel = null, + .pointer = .{ + .alignment = @min(type_info.pointer.alignment, @alignOf(type_info.pointer.child)), + .size = .one, + .child = type_info.pointer.child, + .address_space = type_info.pointer.address_space, + .is_const = type_info.pointer.is_const, + .is_volatile = type_info.pointer.is_volatile, + .is_allowzero = type_info.pointer.is_allowzero, + .sentinel_ptr = null, }, }; return struct { const Vector = @This(); - pub const Item = type_info.Pointer.child; + pub const Item = type_info.pointer.child; pub const ItemPtr = @Type(item_ptr_info); /// The slice of slices. The first and the last slice of this slice must diff --git a/drivers/build.zig b/drivers/build.zig index e14185d52..36474cf85 100644 --- a/drivers/build.zig +++ b/drivers/build.zig @@ -9,7 +9,7 @@ pub fn build(b: *std.Build) void { const test_suite = b.addTest(.{ .root_source_file = b.path("framework.zig"), - .target = b.host, + .target = b.graph.host, .optimize = .Debug, }); diff --git a/examples/raspberrypi/rp2xxx/src/rp2040_only/adc.zig b/examples/raspberrypi/rp2xxx/src/rp2040_only/adc.zig index 728ef66ad..77228e8e0 100644 --- a/examples/raspberrypi/rp2xxx/src/rp2040_only/adc.zig +++ b/examples/raspberrypi/rp2xxx/src/rp2040_only/adc.zig @@ -13,7 +13,7 @@ const baud_rate = 115200; const uart_tx_pin = gpio.num(0); const uart_rx_pin = gpio.num(1); -pub const microzig_options = .{ +pub const microzig_options = microzig.Options{ .logFn = rp2xxx.uart.logFn, }; diff --git a/examples/raspberrypi/rp2xxx/src/rp2040_only/flash_program.zig b/examples/raspberrypi/rp2xxx/src/rp2040_only/flash_program.zig index f78c4368e..361244b35 100644 --- a/examples/raspberrypi/rp2xxx/src/rp2040_only/flash_program.zig +++ b/examples/raspberrypi/rp2xxx/src/rp2040_only/flash_program.zig @@ -23,7 +23,7 @@ pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noretu while (true) {} } -pub const microzig_options = .{ +pub const microzig_options = microzig.Options{ .log_level = .debug, .logFn = rp2xxx.uart.logFn, }; diff --git a/examples/raspberrypi/rp2xxx/src/rp2040_only/i2c_bus_scan.zig b/examples/raspberrypi/rp2xxx/src/rp2040_only/i2c_bus_scan.zig index ba9af3283..54ef1412b 100644 --- a/examples/raspberrypi/rp2xxx/src/rp2040_only/i2c_bus_scan.zig +++ b/examples/raspberrypi/rp2xxx/src/rp2040_only/i2c_bus_scan.zig @@ -7,7 +7,7 @@ const gpio = rp2xxx.gpio; const peripherals = microzig.chip.peripherals; const chip = rp2xxx.compatibility.chip; -pub const microzig_options = .{ +pub const microzig_options = microzig.Options{ .log_level = .info, .logFn = rp2xxx.uart.logFn, }; diff --git a/examples/raspberrypi/rp2xxx/src/rp2040_only/random.zig b/examples/raspberrypi/rp2xxx/src/rp2040_only/random.zig index eb946595e..0506a1f18 100644 --- a/examples/raspberrypi/rp2xxx/src/rp2040_only/random.zig +++ b/examples/raspberrypi/rp2xxx/src/rp2040_only/random.zig @@ -23,7 +23,7 @@ pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noretu while (true) {} } -pub const microzig_options = .{ +pub const microzig_options = microzig.Options{ .log_level = .debug, .logFn = rp2xxx.uart.logFn, }; diff --git a/examples/raspberrypi/rp2xxx/src/rp2040_only/rtc.zig b/examples/raspberrypi/rp2xxx/src/rp2040_only/rtc.zig index da44cc381..bcd389b6b 100644 --- a/examples/raspberrypi/rp2xxx/src/rp2040_only/rtc.zig +++ b/examples/raspberrypi/rp2xxx/src/rp2040_only/rtc.zig @@ -10,7 +10,7 @@ const pin_config = rp2xxx.pins.GlobalConfiguration{ }, }; -pub const microzig_options = .{ +pub const microzig_options = microzig.Options{ .interrupts = .{ .RTC_IRQ = .{ .C = &rtc_isr }, }, diff --git a/examples/raspberrypi/rp2xxx/src/rp2040_only/tiles.zig b/examples/raspberrypi/rp2xxx/src/rp2040_only/tiles.zig index bc5e4ef2f..4a8bb86df 100644 --- a/examples/raspberrypi/rp2xxx/src/rp2040_only/tiles.zig +++ b/examples/raspberrypi/rp2xxx/src/rp2040_only/tiles.zig @@ -37,7 +37,7 @@ const sm: StateMachine = .sm0; const led_pin = gpio.num(16); const brightness: [256]u8 = blk: { - @setEvalBranchQuota(10_000); + @setEvalBranchQuota(25_000); const gamma = 2.2; diff --git a/examples/raspberrypi/rp2xxx/src/rp2040_only/uart_log.zig b/examples/raspberrypi/rp2xxx/src/rp2040_only/uart_log.zig index d8dbcc30c..b5181adbf 100644 --- a/examples/raspberrypi/rp2xxx/src/rp2040_only/uart_log.zig +++ b/examples/raspberrypi/rp2xxx/src/rp2040_only/uart_log.zig @@ -19,7 +19,7 @@ pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noretu while (true) {} } -pub const microzig_options = .{ +pub const microzig_options = microzig.Options{ .log_level = .debug, .logFn = rp2xxx.uart.logFn, }; diff --git a/examples/raspberrypi/rp2xxx/src/rp2040_only/usb_cdc.zig b/examples/raspberrypi/rp2xxx/src/rp2040_only/usb_cdc.zig index 984aa14f8..ab509ab06 100644 --- a/examples/raspberrypi/rp2xxx/src/rp2040_only/usb_cdc.zig +++ b/examples/raspberrypi/rp2xxx/src/rp2040_only/usb_cdc.zig @@ -59,7 +59,7 @@ pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noretu while (true) {} } -pub const microzig_options = .{ +pub const microzig_options = microzig.Options{ .log_level = .debug, .logFn = rp2xxx.uart.logFn, }; diff --git a/examples/raspberrypi/rp2xxx/src/rp2040_only/usb_hid.zig b/examples/raspberrypi/rp2xxx/src/rp2040_only/usb_hid.zig index df78f9321..be28470e5 100644 --- a/examples/raspberrypi/rp2xxx/src/rp2040_only/usb_hid.zig +++ b/examples/raspberrypi/rp2xxx/src/rp2040_only/usb_hid.zig @@ -61,7 +61,7 @@ pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noretu while (true) {} } -pub const microzig_options = .{ +pub const microzig_options = microzig.Options{ .log_level = .debug, .logFn = rp2xxx.uart.logFn, }; diff --git a/examples/raspberrypi/rp2xxx/src/squarewave.zig b/examples/raspberrypi/rp2xxx/src/squarewave.zig index ff521037b..2769e41dd 100644 --- a/examples/raspberrypi/rp2xxx/src/squarewave.zig +++ b/examples/raspberrypi/rp2xxx/src/squarewave.zig @@ -7,7 +7,7 @@ const Pio = rp2xxx.pio.Pio; const StateMachine = rp2xxx.pio.StateMachine; const squarewave_program = blk: { - @setEvalBranchQuota(2000); + @setEvalBranchQuota(3000); break :blk rp2xxx.pio.assemble( \\; \\; Copyright (c) 2020 Raspberry Pi (Trading) Ltd. diff --git a/port/espressif/esp/src/cpus/espressif-riscv.zig b/port/espressif/esp/src/cpus/espressif-riscv.zig index cb8a760bd..5b4706800 100644 --- a/port/espressif/esp/src/cpus/espressif-riscv.zig +++ b/port/espressif/esp/src/cpus/espressif-riscv.zig @@ -108,7 +108,7 @@ pub const startup_logic = struct { }; pub fn export_startup_logic() void { - @export(startup_logic._start, .{ + @export(&startup_logic._start, .{ .name = "_start", }); } diff --git a/port/gigadevice/gd32/src/hals/GD32VF103/pins.zig b/port/gigadevice/gd32/src/hals/GD32VF103/pins.zig index 60adf83ac..8964e952e 100644 --- a/port/gigadevice/gd32/src/hals/GD32VF103/pins.zig +++ b/port/gigadevice/gd32/src/hals/GD32VF103/pins.zig @@ -85,13 +85,13 @@ pub fn GPIO(comptime port: u3, comptime num: u4, comptime mode: gpio.Mode) type pub fn Pins(comptime config: GlobalConfiguration) type { comptime { var fields: []const StructField = &.{}; - for (@typeInfo(GlobalConfiguration).Struct.fields) |port_field| { + for (@typeInfo(GlobalConfiguration).@"struct".fields) |port_field| { if (@field(config, port_field.name)) |port_config| { - for (@typeInfo(Port.Configuration).Struct.fields) |field| { + for (@typeInfo(Port.Configuration).@"struct".fields) |field| { if (@field(port_config, field.name)) |pin_config| { var pin_field = StructField{ .is_comptime = false, - .default_value = null, + .default_value_ptr = null, // initialized below: .name = undefined, @@ -110,7 +110,7 @@ pub fn Pins(comptime config: GlobalConfiguration) type { } return @Type(.{ - .Struct = .{ + .@"struct" = .{ .layout = .auto, .is_tuple = false, .fields = fields, @@ -145,8 +145,8 @@ pub const Port = enum { PIN15: ?Pin.Configuration = null, comptime { - const pin_field_count = @typeInfo(Pin).Enum.fields.len; - const config_field_count = @typeInfo(Configuration).Struct.fields.len; + const pin_field_count = @typeInfo(Pin).@"enum".fields.len; + const config_field_count = @typeInfo(Configuration).@"struct".fields.len; if (pin_field_count != config_field_count) @compileError(comptimePrint("{} {}", .{ pin_field_count, config_field_count })); } @@ -161,19 +161,19 @@ pub const GlobalConfiguration = struct { GPIOE: ?Port.Configuration = null, comptime { - const port_field_count = @typeInfo(Port).Enum.fields.len; - const config_field_count = @typeInfo(GlobalConfiguration).Struct.fields.len; + const port_field_count = @typeInfo(Port).@"enum".fields.len; + const config_field_count = @typeInfo(GlobalConfiguration).@"struct".fields.len; if (port_field_count != config_field_count) @compileError(comptimePrint("{} {}", .{ port_field_count, config_field_count })); } pub fn apply(comptime config: GlobalConfiguration) Pins(config) { - inline for (@typeInfo(GlobalConfiguration).Struct.fields) |port_field| { + inline for (@typeInfo(GlobalConfiguration).@"struct".fields) |port_field| { if (@field(config, port_field.name)) |port_config| { comptime var input_gpios: u16 = 0; comptime var output_gpios: u16 = 0; comptime { - for (@typeInfo(Port.Configuration).Struct.fields) |field| + for (@typeInfo(Port.Configuration).@"struct".fields) |field| if (@field(port_config, field.name)) |pin_config| { const gpio_num = @intFromEnum(@field(Pin, field.name)); @@ -195,7 +195,7 @@ pub const GlobalConfiguration = struct { _ = RCU.APB2EN.raw & bit; } - inline for (@typeInfo(Port.Configuration).Struct.fields) |field| { + inline for (@typeInfo(Port.Configuration).@"struct".fields) |field| { if (@field(port_config, field.name)) |pin_config| { var pin = gpio.Pin.init(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name))); pin.set_mode(pin_config.mode.?); @@ -203,7 +203,7 @@ pub const GlobalConfiguration = struct { } if (input_gpios != 0) { - inline for (@typeInfo(Port.Configuration).Struct.fields) |field| + inline for (@typeInfo(Port.Configuration).@"struct".fields) |field| if (@field(port_config, field.name)) |pin_config| { var pin = gpio.Pin.init(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name))); const pull = pin_config.pull orelse continue; @@ -220,9 +220,9 @@ pub const GlobalConfiguration = struct { // default build them all (wasn't sure how to do that cleanly in // `Pins()` var ret: Pins(config) = undefined; - inline for (@typeInfo(Pins(config)).Struct.fields) |field| { - if (field.default_value) |default_value| { - @field(ret, field.name) = @as(*const field.field_type, @ptrCast(default_value)).*; + inline for (@typeInfo(Pins(config)).@"struct".fields) |field| { + if (field.default_value_ptr) |default_value_ptr| { + @field(ret, field.name) = @as(*const field.field_type, @ptrCast(default_value_ptr)).*; } else { @field(ret, field.name) = .{}; } diff --git a/port/nxp/lpc/build.zig b/port/nxp/lpc/build.zig index 40970b054..f4dd60427 100644 --- a/port/nxp/lpc/build.zig +++ b/port/nxp/lpc/build.zig @@ -63,7 +63,7 @@ pub fn build(b: *std.Build) void { const lpc176x5x_patch_elf_exe = b.addExecutable(.{ .name = "lpc176x5x-patchelf", .root_source_file = b.path("src/tools/patchelf.zig"), - .target = b.host, + .target = b.graph.host, }); b.installArtifact(lpc176x5x_patch_elf_exe); } diff --git a/port/raspberrypi/rp2xxx/patches/rp2040.zig b/port/raspberrypi/rp2xxx/patches/rp2040.zig index ae3f66efa..6d68279f8 100644 --- a/port/raspberrypi/rp2xxx/patches/rp2040.zig +++ b/port/raspberrypi/rp2xxx/patches/rp2040.zig @@ -1,4 +1,7 @@ -pub const patches = &.{ +const microzig = @import("microzig/build-internals"); +const Patch = microzig.Patch; + +pub const patches: []const Patch = &.{ .{ .add_enum = .{ .parent = "types.peripherals.USB_DPRAM", diff --git a/port/raspberrypi/rp2xxx/src/cpus/hazard3.zig b/port/raspberrypi/rp2xxx/src/cpus/hazard3.zig index 92c198d27..db22cda05 100644 --- a/port/raspberrypi/rp2xxx/src/cpus/hazard3.zig +++ b/port/raspberrypi/rp2xxx/src/cpus/hazard3.zig @@ -66,11 +66,11 @@ pub const startup_logic = struct { pub const vector_table = wrap_trap_handler(startup_logic.trap_handler); pub fn export_startup_logic() void { - @export(startup_logic._start, .{ + @export(&startup_logic._start, .{ .name = "_start", }); - @export(startup_logic._start_c, .{ + @export(&startup_logic._start_c, .{ .name = "_start_c", }); } @@ -80,7 +80,7 @@ pub inline fn wrap_trap_handler(inner: fn () callconv(.C) void) fn () callconv(. const unique_call_inner_export_name = @typeName(@This()) ++ "_call_inner"; comptime { - @export(call_inner, .{ + @export(&call_inner, .{ .name = unique_call_inner_export_name, }); } diff --git a/port/raspberrypi/rp2xxx/src/hal/clocks/common.zig b/port/raspberrypi/rp2xxx/src/hal/clocks/common.zig index 81b665903..f1598129b 100644 --- a/port/raspberrypi/rp2xxx/src/hal/clocks/common.zig +++ b/port/raspberrypi/rp2xxx/src/hal/clocks/common.zig @@ -100,7 +100,7 @@ pub fn GeneratorImpl(Generator: type, Source: type, IntegerDivisorType: type) ty assert(24 == @sizeOf([2]Regs)); } - const generators = @as(*volatile [@typeInfo(Generator).Enum.fields.len]Regs, @ptrCast(CLOCKS)); + const generators = @as(*volatile [@typeInfo(Generator).@"enum".fields.len]Regs, @ptrCast(CLOCKS)); const CTRL_ENABLE_MASK = @as(u32, 1 << 11); const CTRL_SRC_MASK = @as(u32, 0x3); diff --git a/port/raspberrypi/rp2xxx/src/hal/image_def.zig b/port/raspberrypi/rp2xxx/src/hal/image_def.zig index edb7a9337..eafad5e85 100644 --- a/port/raspberrypi/rp2xxx/src/hal/image_def.zig +++ b/port/raspberrypi/rp2xxx/src/hal/image_def.zig @@ -19,7 +19,7 @@ const cpu: Cpu = std.meta.stringToEnum(Cpu, @tagName(arch)).?; const image_def = init(); comptime { - @export(image_def, .{ + @export(&image_def, .{ .name = "_image_def", .section = ".bootmeta", .linkage = .strong, diff --git a/port/raspberrypi/rp2xxx/src/hal/pins.zig b/port/raspberrypi/rp2xxx/src/hal/pins.zig index 8850e3bf1..d1d8193de 100644 --- a/port/raspberrypi/rp2xxx/src/hal/pins.zig +++ b/port/raspberrypi/rp2xxx/src/hal/pins.zig @@ -283,7 +283,7 @@ fn single(gpio_num: u5) [30]u1 { return ret; } -const function_table = [@typeInfo(Function).Enum.fields.len][30]u1{ +const function_table = [@typeInfo(Function).@"enum".fields.len][30]u1{ all(), // SIO all(), // PIO0 all(), // PIO1 @@ -371,19 +371,19 @@ pub const GlobalConfiguration = struct { GPIO29: ?Pin.Configuration = null, comptime { - const pin_field_count = @typeInfo(Pin).Enum.fields.len; - const config_field_count = @typeInfo(GlobalConfiguration).Struct.fields.len; + const pin_field_count = @typeInfo(Pin).@"enum".fields.len; + const config_field_count = @typeInfo(GlobalConfiguration).@"struct".fields.len; if (pin_field_count != config_field_count) @compileError(comptimePrint("{} {}", .{ pin_field_count, config_field_count })); } pub fn PinsType(self: GlobalConfiguration) type { var fields: []const StructField = &.{}; - for (@typeInfo(GlobalConfiguration).Struct.fields) |field| { + for (@typeInfo(GlobalConfiguration).@"struct".fields) |field| { if (@field(self, field.name)) |pin_config| { var pin_field = StructField{ .is_comptime = false, - .default_value = null, + .default_value_ptr = null, // initialized below: .name = undefined, @@ -409,7 +409,7 @@ pub const GlobalConfiguration = struct { } return @Type(.{ - .Struct = .{ + .@"struct" = .{ .layout = .auto, .is_tuple = false, .fields = fields, @@ -421,17 +421,17 @@ pub const GlobalConfiguration = struct { // Can be called at comptime or runtime pub fn pins(comptime self: GlobalConfiguration) self.PinsType() { var ret: self.PinsType() = undefined; - inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| { + inline for (@typeInfo(GlobalConfiguration).@"struct".fields) |field| { if (@field(self, field.name)) |pin_config| { if (pin_config.function == .SIO) { @field(ret, pin_config.name orelse field.name) = gpio.num(@intFromEnum(@field(Pin, field.name))); } else if (pin_config.function.is_pwm()) { - @field(ret, pin_config.name orelse field.name) = pwm.Pwm { + @field(ret, pin_config.name orelse field.name) = pwm.Pwm{ .slice_number = pin_config.function.pwm_slice(), .channel = pin_config.function.pwm_channel(), }; } else if (pin_config.function.is_adc()) { - @field(ret, pin_config.name orelse field.name) = @as(adc.Input, @enumFromInt(switch(pin_config.function) { + @field(ret, pin_config.name orelse field.name) = @as(adc.Input, @enumFromInt(switch (pin_config.function) { .ADC0 => 0, .ADC1 => 1, .ADC2 => 2, @@ -453,7 +453,7 @@ pub const GlobalConfiguration = struct { // validate selected function comptime { - for (@typeInfo(GlobalConfiguration).Struct.fields) |field| + for (@typeInfo(GlobalConfiguration).@"struct".fields) |field| if (@field(config, field.name)) |pin_config| { const gpio_num = @intFromEnum(@field(Pin, field.name)); if (0 == function_table[@intFromEnum(pin_config.function)][gpio_num]) @@ -484,7 +484,7 @@ pub const GlobalConfiguration = struct { SIO.GPIO_OUT_CLR.raw = used_gpios; } - inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| { + inline for (@typeInfo(GlobalConfiguration).@"struct".fields) |field| { if (@field(config, field.name)) |pin_config| { const pin = gpio.num(@intFromEnum(@field(Pin, field.name))); const func = pin_config.function; @@ -527,7 +527,7 @@ pub const GlobalConfiguration = struct { SIO.GPIO_OE_SET.raw = output_gpios; if (input_gpios != 0) { - inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| + inline for (@typeInfo(GlobalConfiguration).@"struct".fields) |field| if (@field(config, field.name)) |pin_config| { const gpio_num = @intFromEnum(@field(Pin, field.name)); const pull = pin_config.pull orelse continue; diff --git a/port/raspberrypi/rp2xxx/src/hal/pio/rp2040.zig b/port/raspberrypi/rp2xxx/src/hal/pio/rp2040.zig index 61187890c..0cf3b4961 100644 --- a/port/raspberrypi/rp2xxx/src/hal/pio/rp2040.zig +++ b/port/raspberrypi/rp2xxx/src/hal/pio/rp2040.zig @@ -76,7 +76,7 @@ pub const Pio = enum(u1) { pub fn sm_clear_fifos(self: Pio, sm: common.StateMachine) void { const sm_regs = self.get_sm_regs(sm); const xor_shiftctrl = hw.xor_alias(&sm_regs.shiftctrl); - const mask = .{ + const mask = @TypeOf(common.PIO0.SM0_SHIFTCTRL).underlying_type{ .FJOIN_TX = 1, .FJOIN_RX = 1, diff --git a/port/raspberrypi/rp2xxx/src/hal/pio/rp2350.zig b/port/raspberrypi/rp2xxx/src/hal/pio/rp2350.zig index 21ff49576..ec182f9b8 100644 --- a/port/raspberrypi/rp2xxx/src/hal/pio/rp2350.zig +++ b/port/raspberrypi/rp2xxx/src/hal/pio/rp2350.zig @@ -86,7 +86,7 @@ pub const Pio = enum(u2) { pub fn sm_clear_fifos(self: Pio, sm: common.StateMachine) void { const sm_regs = self.get_sm_regs(sm); const xor_shiftctrl = hw.xor_alias(&sm_regs.shiftctrl); - const mask = .{ + const mask = @TypeOf(common.PIO0.SM0_SHIFTCTRL).underlying_type{ .FJOIN_TX = 1, .FJOIN_RX = 1, diff --git a/port/raspberrypi/rp2xxx/src/hal/rom.zig b/port/raspberrypi/rp2xxx/src/hal/rom.zig index a3980741c..2d810939d 100644 --- a/port/raspberrypi/rp2xxx/src/hal/rom.zig +++ b/port/raspberrypi/rp2xxx/src/hal/rom.zig @@ -113,7 +113,7 @@ pub inline fn rom_hword_as_ptr(rom_addr: u32) *anyopaque { /// /// A anyopaque pointer to the function; must be cast by the caller pub inline fn _rom_func_lookup(code: Code) *anyopaque { - const rom_table_lookup = @as(*signatures.rom_table_lookup, @ptrCast(rom_hword_as_ptr(0x18))); + const rom_table_lookup = @as(*signatures.rom_table_lookup, @alignCast(@ptrCast(rom_hword_as_ptr(0x18)))); const func_table = @as(*u16, @ptrCast(@alignCast(rom_hword_as_ptr(0x14)))); return rom_table_lookup(func_table, @intFromEnum(code)); } @@ -196,7 +196,7 @@ pub fn memcpy(dest: []u8, src: []const u8) []u8 { const n = if (dest.len <= src.len) dest.len else src.len; - if (S.f == null) S.f = @as(*signatures.memcpy, @ptrCast(_rom_func_lookup(Code.memcpy))); + if (S.f == null) S.f = @as(*signatures.memcpy, @alignCast(@ptrCast(_rom_func_lookup(Code.memcpy)))); return S.f.?(dest.ptr, src.ptr, n)[0..n]; } @@ -208,7 +208,7 @@ pub fn memcpy(dest: []u8, src: []const u8) []u8 { pub inline fn connect_internal_flash() *signatures.connect_internal_flash { return @as( *signatures.connect_internal_flash, - @ptrCast(_rom_func_lookup(Code.connect_internal_flash)), + @alignCast(@ptrCast(_rom_func_lookup(Code.connect_internal_flash))), ); } @@ -220,7 +220,7 @@ pub inline fn connect_internal_flash() *signatures.connect_internal_flash { pub inline fn flash_exit_xip() *signatures.flash_exit_xip { return @as( *signatures.flash_exit_xip, - @ptrCast(_rom_func_lookup(Code.flash_exit_xip)), + @alignCast(@ptrCast(_rom_func_lookup(Code.flash_exit_xip))), ); } @@ -232,7 +232,7 @@ pub inline fn flash_exit_xip() *signatures.flash_exit_xip { pub inline fn flash_range_erase() *signatures.flash_range_erase { return @as( *signatures.flash_range_erase, - @ptrCast(_rom_func_lookup(Code.flash_range_erase)), + @alignCast(@ptrCast(_rom_func_lookup(Code.flash_range_erase))), ); } @@ -242,7 +242,7 @@ pub inline fn flash_range_erase() *signatures.flash_range_erase { pub inline fn flash_range_program() *signatures.flash_range_program { return @as( *signatures.flash_range_program, - @ptrCast(_rom_func_lookup(Code.flash_range_program)), + @alignCast(@ptrCast(_rom_func_lookup(Code.flash_range_program))), ); } @@ -251,7 +251,7 @@ pub inline fn flash_range_program() *signatures.flash_range_program { pub inline fn flash_flush_cache() *signatures.flash_flush_cache { return @as( *signatures.flash_flush_cache, - @ptrCast(_rom_func_lookup(Code.flash_flush_cache)), + @alignCast(@ptrCast(_rom_func_lookup(Code.flash_flush_cache))), ); } @@ -264,6 +264,6 @@ pub inline fn flash_flush_cache() *signatures.flash_flush_cache { pub inline fn flash_enter_cmd_xip() *signatures.flash_enter_cmd_xip { return @as( *signatures.flash_enter_cmd_xip, - @ptrCast(_rom_func_lookup(Code.flash_enter_cmd_xip)), + @alignCast(@ptrCast(_rom_func_lookup(Code.flash_enter_cmd_xip))), ); } diff --git a/port/stmicro/stm32/src/hals/STM32F103/pins.zig b/port/stmicro/stm32/src/hals/STM32F103/pins.zig index d00b582d5..8e1b9245d 100644 --- a/port/stmicro/stm32/src/hals/STM32F103/pins.zig +++ b/port/stmicro/stm32/src/hals/STM32F103/pins.zig @@ -85,13 +85,13 @@ pub fn GPIO(comptime port: u3, comptime num: u4, comptime mode: gpio.Mode) type pub fn Pins(comptime config: GlobalConfiguration) type { comptime { var fields: []const StructField = &.{}; - for (@typeInfo(GlobalConfiguration).Struct.fields) |port_field| { + for (@typeInfo(GlobalConfiguration).@"struct".fields) |port_field| { if (@field(config, port_field.name)) |port_config| { - for (@typeInfo(Port.Configuration).Struct.fields) |field| { + for (@typeInfo(Port.Configuration).@"struct".fields) |field| { if (@field(port_config, field.name)) |pin_config| { var pin_field = StructField{ .is_comptime = false, - .default_value = null, + .default_value_ptr = null, // initialized below: .name = undefined, @@ -110,7 +110,7 @@ pub fn Pins(comptime config: GlobalConfiguration) type { } return @Type(.{ - .Struct = .{ + .@"struct" = .{ .layout = .auto, .is_tuple = false, .fields = fields, @@ -147,8 +147,8 @@ pub const Port = enum { PIN15: ?Pin.Configuration = null, comptime { - const pin_field_count = @typeInfo(Pin).Enum.fields.len; - const config_field_count = @typeInfo(Configuration).Struct.fields.len; + const pin_field_count = @typeInfo(Pin).@"enum".fields.len; + const config_field_count = @typeInfo(Configuration).@"struct".fields.len; if (pin_field_count != config_field_count) @compileError(comptimePrint("{} {}", .{ pin_field_count, config_field_count })); } @@ -165,19 +165,19 @@ pub const GlobalConfiguration = struct { GPIOG: ?Port.Configuration = null, comptime { - const port_field_count = @typeInfo(Port).Enum.fields.len; - const config_field_count = @typeInfo(GlobalConfiguration).Struct.fields.len; + const port_field_count = @typeInfo(Port).@"enum".fields.len; + const config_field_count = @typeInfo(GlobalConfiguration).@"struct".fields.len; if (port_field_count != config_field_count) @compileError(comptimePrint("{} {}", .{ port_field_count, config_field_count })); } pub fn apply(comptime config: GlobalConfiguration) Pins(config) { - inline for (@typeInfo(GlobalConfiguration).Struct.fields) |port_field| { + inline for (@typeInfo(GlobalConfiguration).@"struct".fields) |port_field| { if (@field(config, port_field.name)) |port_config| { comptime var input_gpios: u16 = 0; comptime var output_gpios: u16 = 0; comptime { - for (@typeInfo(Port.Configuration).Struct.fields) |field| + for (@typeInfo(Port.Configuration).@"struct".fields) |field| if (@field(port_config, field.name)) |pin_config| { const gpio_num = @intFromEnum(@field(Pin, field.name)); @@ -199,7 +199,7 @@ pub const GlobalConfiguration = struct { _ = RCC.APB2ENR.raw & bit; } - inline for (@typeInfo(Port.Configuration).Struct.fields) |field| { + inline for (@typeInfo(Port.Configuration).@"struct".fields) |field| { if (@field(port_config, field.name)) |pin_config| { var pin = gpio.Pin.init(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name))); pin.set_mode(pin_config.mode.?); @@ -207,7 +207,7 @@ pub const GlobalConfiguration = struct { } if (input_gpios != 0) { - inline for (@typeInfo(Port.Configuration).Struct.fields) |field| + inline for (@typeInfo(Port.Configuration).@"struct".fields) |field| if (@field(port_config, field.name)) |pin_config| { var pin = gpio.Pin.init(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name))); const pull = pin_config.pull orelse continue; @@ -224,9 +224,9 @@ pub const GlobalConfiguration = struct { // default build them all (wasn't sure how to do that cleanly in // `Pins()` var ret: Pins(config) = undefined; - inline for (@typeInfo(Pins(config)).Struct.fields) |field| { - if (field.default_value) |default_value| { - @field(ret, field.name) = @as(*const field.field_type, @ptrCast(default_value)).*; + inline for (@typeInfo(Pins(config)).@"struct".fields) |field| { + if (field.default_value_ptr) |default_value_ptr| { + @field(ret, field.name) = @as(*const field.field_type, @ptrCast(default_value_ptr)).*; } else { @field(ret, field.name) = .{}; } diff --git a/port/wch/ch32v/build.zig b/port/wch/ch32v/build.zig index 6e5cdd136..e109e7c9e 100644 --- a/port/wch/ch32v/build.zig +++ b/port/wch/ch32v/build.zig @@ -38,7 +38,7 @@ pub fn init(dep: *std.Build.Dependency) Self { .root_source_file = b.path("src/hals/hal_ch32v203.zig"), }; - const qingkev2a = .{ + const qingkev2a = std.Target.Query{ // QingKe V2C is RV32EC .cpu_arch = .riscv32, .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic }, @@ -51,7 +51,7 @@ pub fn init(dep: *std.Build.Dependency) Self { .abi = .eabi, }; - const qingkev3 = .{ + const qingkev3 = std.Target.Query{ .cpu_arch = .riscv32, .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 }, // generic_rv32 has feature I. @@ -64,7 +64,7 @@ pub fn init(dep: *std.Build.Dependency) Self { .abi = .eabi, }; - const qingkev4b = .{ + const qingkev4b = std.Target.Query{ .cpu_arch = .riscv32, .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 }, // generic_rv32 has feature I. diff --git a/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig b/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig index 951a173fd..d483ae6d6 100644 --- a/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig +++ b/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig @@ -55,7 +55,7 @@ pub const startup_logic = struct { }; pub fn export_startup_logic() void { - @export(startup_logic._start, .{ + @export(&startup_logic._start, .{ .name = "_start", }); } @@ -64,7 +64,7 @@ const VectorTable = microzig.chip.VectorTable; pub const vector_table: VectorTable = blk: { var tmp: VectorTable = .{}; if (@hasDecl(root, "microzig_options")) { - for (@typeInfo(root.VectorTableOptions).Struct.fields) |field| + for (@typeInfo(microzig.VectorTableOptions).@"struct".fields) |field| @field(tmp, field.name) = @field(root.microzig_options.interrupts, field.name); } diff --git a/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig b/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig index 5756de898..dce943649 100644 --- a/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig +++ b/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig @@ -61,7 +61,7 @@ pub const startup_logic = struct { }; pub fn export_startup_logic() void { - @export(startup_logic._start, .{ + @export(&startup_logic._start, .{ .name = "_start", }); } @@ -70,7 +70,7 @@ const VectorTable = microzig.chip.VectorTable; pub const vector_table: VectorTable = blk: { var tmp: VectorTable = .{}; if (@hasDecl(root, "microzig_options")) { - for (@typeInfo(root.VectorTableOptions).Struct.fields) |field| + for (@typeInfo(microzig.VectorTableOptions).@"struct".fields) |field| @field(tmp, field.name) = @field(root.microzig_options.interrupts, field.name); } diff --git a/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig b/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig index 7febcee3e..446fd6272 100644 --- a/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig +++ b/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig @@ -55,7 +55,7 @@ pub const startup_logic = struct { }; pub fn export_startup_logic() void { - @export(startup_logic._start, .{ + @export(&startup_logic._start, .{ .name = "_start", }); } @@ -64,7 +64,7 @@ const VectorTable = microzig.chip.VectorTable; pub const vector_table: VectorTable = blk: { var tmp: VectorTable = .{}; if (@hasDecl(root, "microzig_options")) { - for (@typeInfo(root.VectorTableOptions).Struct.fields) |field| + for (@typeInfo(microzig.VectorTableOptions).@"struct".fields) |field| @field(tmp, field.name) = @field(root.microzig_options.interrupts, field.name); } diff --git a/port/wch/ch32v/src/hals/ch32v003/pins.zig b/port/wch/ch32v/src/hals/ch32v003/pins.zig index e03122326..4fadc5310 100644 --- a/port/wch/ch32v/src/hals/ch32v003/pins.zig +++ b/port/wch/ch32v/src/hals/ch32v003/pins.zig @@ -78,7 +78,7 @@ pub fn GPIO(comptime port: u3, comptime num: u4, comptime mode: gpio.Mode) type } fn getTagNameByIndex(comptime T: type, comptime index: usize) []const u8 { - const fields = @typeInfo(T).Enum.fields; + const fields = @typeInfo(T).@"enum".fields; if (index >= fields.len) { @compileError("Index is out of enum members."); } @@ -88,13 +88,13 @@ fn getTagNameByIndex(comptime T: type, comptime index: usize) []const u8 { pub fn Pins(comptime config: GlobalConfiguration) type { comptime { var fields: []const StructField = &.{}; - for (@typeInfo(GlobalConfiguration).Struct.fields) |port_field| { + for (@typeInfo(GlobalConfiguration).@"struct".fields) |port_field| { if (@field(config, port_field.name)) |port_config| { - for (@typeInfo(Port.Configuration).Struct.fields) |field| { + for (@typeInfo(Port.Configuration).@"struct".fields) |field| { if (@field(port_config, field.name)) |pin_config| { var pin_field = StructField{ .is_comptime = false, - .default_value = null, + .default_value_ptr = null, // initialized below: .name = undefined, @@ -113,7 +113,7 @@ pub fn Pins(comptime config: GlobalConfiguration) type { } return @Type(.{ - .Struct = .{ + .@"struct" = .{ .layout = .auto, .is_tuple = false, .fields = fields, @@ -147,8 +147,8 @@ pub const Port = enum(u2) { PIN7: ?Pin.Configuration = null, comptime { - const pin_field_count = @typeInfo(Pin).Enum.fields.len; - const config_field_count = @typeInfo(Configuration).Struct.fields.len; + const pin_field_count = @typeInfo(Pin).@"enum".fields.len; + const config_field_count = @typeInfo(Configuration).@"struct".fields.len; if (pin_field_count != config_field_count) @compileError(comptimePrint("{} {}", .{ pin_field_count, config_field_count })); } @@ -161,19 +161,19 @@ pub const GlobalConfiguration = struct { GPIOD: ?Port.Configuration = null, comptime { - const port_field_count = @typeInfo(Port).Enum.fields.len; - const config_field_count = @typeInfo(GlobalConfiguration).Struct.fields.len; + const port_field_count = @typeInfo(Port).@"enum".fields.len; + const config_field_count = @typeInfo(GlobalConfiguration).@"struct".fields.len; if (port_field_count != config_field_count) @compileError(comptimePrint("{} {}", .{ port_field_count, config_field_count })); } pub fn apply(comptime config: GlobalConfiguration) Pins(config) { - inline for (@typeInfo(GlobalConfiguration).Struct.fields) |port_field| { + inline for (@typeInfo(GlobalConfiguration).@"struct".fields) |port_field| { if (@field(config, port_field.name)) |port_config| { comptime var input_gpios: u16 = 0; comptime var output_gpios: u16 = 0; comptime { - for (@typeInfo(Port.Configuration).Struct.fields) |field| + for (@typeInfo(Port.Configuration).@"struct".fields) |field| if (@field(port_config, field.name)) |pin_config| { const gpio_num = @intFromEnum(@field(Pin, field.name)); @@ -197,7 +197,7 @@ pub const GlobalConfiguration = struct { // comptime var port_cfg_value: u32 = 0; // comptime var port_cfg_default: u32 = 0; // Configure port mode. - inline for (@typeInfo(Port.Configuration).Struct.fields) |field| { + inline for (@typeInfo(Port.Configuration).@"struct".fields) |field| { // TODO: GPIOD has only 3 ports. Check this. if (@field(port_config, field.name)) |pin_config| { var pin = gpio.Pin.init(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name))); @@ -208,7 +208,7 @@ pub const GlobalConfiguration = struct { // Set upll-up and pull-down. if (input_gpios != 0) { - inline for (@typeInfo(Port.Configuration).Struct.fields) |field| + inline for (@typeInfo(Port.Configuration).@"struct".fields) |field| if (@field(port_config, field.name)) |pin_config| { var pin = gpio.Pin.init(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name))); const pull = pin_config.pull orelse continue; @@ -231,9 +231,9 @@ pub fn get_pins(comptime config: GlobalConfiguration) Pins(config) { // default build them all (wasn't sure how to do that cleanly in // `Pins()` var ret: Pins(config) = undefined; - inline for (@typeInfo(Pins(config)).Struct.fields) |field| { - if (field.default_value) |default_value| { - @field(ret, field.name) = @as(*const field.field_type, @ptrCast(default_value)).*; + inline for (@typeInfo(Pins(config)).@"struct".fields) |field| { + if (field.default_value_ptr) |default_value_ptr| { + @field(ret, field.name) = @as(*const field.field_type, @ptrCast(default_value_ptr)).*; } else { @field(ret, field.name) = .{}; } diff --git a/port/wch/ch32v/src/hals/pins.zig b/port/wch/ch32v/src/hals/pins.zig index 2eee8c956..e5291b28c 100644 --- a/port/wch/ch32v/src/hals/pins.zig +++ b/port/wch/ch32v/src/hals/pins.zig @@ -86,7 +86,7 @@ pub fn GPIO(comptime port: u3, comptime num: u4, comptime mode: gpio.Mode) type } fn getTagNameByIndex(comptime T: type, comptime index: usize) []const u8 { - const fields = @typeInfo(T).Enum.fields; + const fields = @typeInfo(T).@"enum".fields; if (index >= fields.len) { @compileError("Index is out of enum members."); } @@ -96,13 +96,13 @@ fn getTagNameByIndex(comptime T: type, comptime index: usize) []const u8 { pub fn Pins(comptime config: GlobalConfiguration) type { comptime { var fields: []const StructField = &.{}; - for (@typeInfo(GlobalConfiguration).Struct.fields) |port_field| { + for (@typeInfo(GlobalConfiguration).@"struct".fields) |port_field| { if (@field(config, port_field.name)) |port_config| { - for (@typeInfo(Port.Configuration).Struct.fields) |field| { + for (@typeInfo(Port.Configuration).@"struct".fields) |field| { if (@field(port_config, field.name)) |pin_config| { var pin_field = StructField{ .is_comptime = false, - .default_value = null, + .default_value_ptr = null, // initialized below: .name = undefined, @@ -121,7 +121,7 @@ pub fn Pins(comptime config: GlobalConfiguration) type { } return @Type(.{ - .Struct = .{ + .@"struct" = .{ .layout = .auto, .is_tuple = false, .fields = fields, @@ -163,8 +163,8 @@ pub const Port = enum { PIN15: ?Pin.Configuration = null, comptime { - const pin_field_count = @typeInfo(Pin).Enum.fields.len; - const config_field_count = @typeInfo(Configuration).Struct.fields.len; + const pin_field_count = @typeInfo(Pin).@"enum".fields.len; + const config_field_count = @typeInfo(Configuration).@"struct".fields.len; if (pin_field_count != config_field_count) @compileError(comptimePrint("{} {}", .{ pin_field_count, config_field_count })); } @@ -178,19 +178,19 @@ pub const GlobalConfiguration = struct { GPIOD: ?Port.Configuration = null, comptime { - const port_field_count = @typeInfo(Port).Enum.fields.len; - const config_field_count = @typeInfo(GlobalConfiguration).Struct.fields.len; + const port_field_count = @typeInfo(Port).@"enum".fields.len; + const config_field_count = @typeInfo(GlobalConfiguration).@"struct".fields.len; if (port_field_count != config_field_count) @compileError(comptimePrint("{} {}", .{ port_field_count, config_field_count })); } pub fn apply(comptime config: GlobalConfiguration) Pins(config) { - inline for (@typeInfo(GlobalConfiguration).Struct.fields) |port_field| { + inline for (@typeInfo(GlobalConfiguration).@"struct".fields) |port_field| { if (@field(config, port_field.name)) |port_config| { comptime var input_gpios: u16 = 0; comptime var output_gpios: u16 = 0; comptime { - for (@typeInfo(Port.Configuration).Struct.fields) |field| + for (@typeInfo(Port.Configuration).@"struct".fields) |field| if (@field(port_config, field.name)) |pin_config| { const gpio_num = @intFromEnum(@field(Pin, field.name)); @@ -214,7 +214,7 @@ pub const GlobalConfiguration = struct { // comptime var port_cfg_value: u32 = 0; // comptime var port_cfg_default: u32 = 0; // Configure port mode. - inline for (@typeInfo(Port.Configuration).Struct.fields) |field| { + inline for (@typeInfo(Port.Configuration).@"struct".fields) |field| { // TODO: GPIOD has only 3 ports. Check this. if (@field(port_config, field.name)) |pin_config| { var pin = gpio.Pin.init(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name))); @@ -225,7 +225,7 @@ pub const GlobalConfiguration = struct { // Set upll-up and pull-down. if (input_gpios != 0) { - inline for (@typeInfo(Port.Configuration).Struct.fields) |field| + inline for (@typeInfo(Port.Configuration).@"struct".fields) |field| if (@field(port_config, field.name)) |pin_config| { var pin = gpio.Pin.init(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name))); const pull = pin_config.pull orelse continue; @@ -248,9 +248,9 @@ pub fn get_pins(comptime config: GlobalConfiguration) Pins(config) { // default build them all (wasn't sure how to do that cleanly in // `Pins()` var ret: Pins(config) = undefined; - inline for (@typeInfo(Pins(config)).Struct.fields) |field| { - if (field.default_value) |default_value| { - @field(ret, field.name) = @as(*const field.field_type, @ptrCast(default_value)).*; + inline for (@typeInfo(Pins(config)).@"struct".fields) |field| { + if (field.default_value_ptr) |default_value_ptr| { + @field(ret, field.name) = @as(*const field.field_type, @ptrCast(default_value_ptr)).*; } else { @field(ret, field.name) = .{}; } diff --git a/tools/regz/src/mmio.zig b/tools/regz/src/mmio.zig index e1c86f3b4..22714cfbb 100644 --- a/tools/regz/src/mmio.zig +++ b/tools/regz/src/mmio.zig @@ -26,13 +26,13 @@ pub fn Mmio(comptime size: u8, comptime PackedT: type) type { pub inline fn write(addr: *volatile Self, val: PackedT) void { // This is a workaround for a compiler bug related to miscompilation // If the tmp var is not used, result location will fuck things up - var tmp = @as(IntT, @bitCast(val)); + const tmp = @as(IntT, @bitCast(val)); addr.raw = tmp; } pub inline fn modify(addr: *volatile Self, fields: anytype) void { var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + inline for (@typeInfo(@TypeOf(fields)).@"struct".fields) |field| { @field(val, field.name) = @field(fields, field.name); } write(addr, val); @@ -40,7 +40,7 @@ pub fn Mmio(comptime size: u8, comptime PackedT: type) type { pub inline fn toggle(addr: *volatile Self, fields: anytype) void { var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + inline for (@typeInfo(@TypeOf(fields)).@"struct".fields) |field| { @field(val, field.name) = @field(val, field.name) ^ @field(fields, field.name); } write(addr, val);