From d6ba2ebf5402e7418a97cef9e40397fc410c02a1 Mon Sep 17 00:00:00 2001
From: Ethan Frei <ethan.frei@gmail.com>
Date: Fri, 17 Jan 2025 16:22:59 -0600
Subject: [PATCH] fixing register so there is 32 bits (#349)

---
 core/src/cpus/cortex_m/m0plus.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/core/src/cpus/cortex_m/m0plus.zig b/core/src/cpus/cortex_m/m0plus.zig
index 95ed125a8..73366708b 100644
--- a/core/src/cpus/cortex_m/m0plus.zig
+++ b/core/src/cpus/cortex_m/m0plus.zig
@@ -124,7 +124,7 @@ pub const SystemControlBlock = extern struct {
         ///
         /// The processor also wakes up on execution of an SEV instruction or an external event.
         SEVONPEND: u1,
-        reserved2: u17,
+        reserved2: u27,
     }),
     /// Configuration Control Register.
     CCR: mmio.Mmio(packed struct(u32) {