From d436cad4b29ab83c67acde469ce35a1c4f4ccaf5 Mon Sep 17 00:00:00 2001 From: Norio Suzuki Date: Tue, 3 Dec 2024 16:57:59 +0900 Subject: [PATCH] Updated PR #223 for current HEAD and extended it for other WCH's CH32V series. (#302) * Updated PR #223 for current head. The modifications for tools by @akiroz was imported without modification. SVD files are merged to be tha same name as its datasheet. Merged startup codes. Imported rcc_init_hsi_pll() into HAL module. The empty.zig example was almost replaced. However, blinky.zig is not merged because the example by @akiroz is accessing peripheral registers in main function. * Extended PR #223 to the other CH32V series chips. No description about ABI for CH32V103 and CH32V202 but assumed it is EABI. Names of the vector table (Interrupt names) are fixed to be the same name for that of the datasheet. --------- Co-authored-by: nosuz --- examples/wch/ch32v/src/empty.zig | 10 +- port/wch/ch32v/README.md | 4 +- port/wch/ch32v/build.zig | 30 +- port/wch/ch32v/src/chips/ch32v003.svd | 677 +++++------------- port/wch/ch32v/src/chips/ch32v103.svd | 97 +-- port/wch/ch32v/src/chips/ch32v20x.svd | 404 ++++++----- port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig | 83 +-- port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig | 95 +-- port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig | 85 +-- port/wch/ch32v/src/hals/hal_ch32v003.zig | 24 + port/wch/ch32v/test/programs/minimal.zig | 2 +- tools/regz/src/Database.zig | 14 + tools/regz/src/arch/riscv.zig | 134 ++++ tools/regz/src/gen.zig | 3 + tools/regz/src/svd.zig | 6 + 15 files changed, 735 insertions(+), 933 deletions(-) create mode 100644 tools/regz/src/arch/riscv.zig diff --git a/examples/wch/ch32v/src/empty.zig b/examples/wch/ch32v/src/empty.zig index fa1c8a1d..79359fc5 100644 --- a/examples/wch/ch32v/src/empty.zig +++ b/examples/wch/ch32v/src/empty.zig @@ -1,8 +1,8 @@ const microzig = @import("microzig"); -pub fn main() void { - while (true) { - asm volatile ("" ::: "memory"); - // asm volatile ("nop"); - } +pub fn main() !void { + asm volatile ("nop"); + // while (true) { + // asm volatile ("" ::: "memory"); + // } } diff --git a/port/wch/ch32v/README.md b/port/wch/ch32v/README.md index d4d70881..cd2aab92 100644 --- a/port/wch/ch32v/README.md +++ b/port/wch/ch32v/README.md @@ -1,3 +1,5 @@ # WCH CH32Vx03 Package -SVD is copied from [ch32-rs/ch32-rs](https://github.com/ch32-rs/ch32-rs) +SVD is derived from [ch32-rs/ch32-rs](https://github.com/ch32-rs/ch32-rs). + +However, the names of registers and interrupts are fixed to match the same names in the datasheet. diff --git a/port/wch/ch32v/build.zig b/port/wch/ch32v/build.zig index 814a398a..6e5cdd13 100644 --- a/port/wch/ch32v/build.zig +++ b/port/wch/ch32v/build.zig @@ -3,6 +3,8 @@ const microzig = @import("microzig/build-internals"); const Self = @This(); +const KiB = 1024; + chips: struct { ch32v003x4: *const microzig.Target, ch32v103x6: *const microzig.Target, @@ -46,7 +48,7 @@ pub fn init(dep: *std.Build.Dependency) Self { std.Target.riscv.Feature.c, }), .os_tag = .freestanding, - .abi = .none, + .abi = .eabi, }; const qingkev3 = .{ @@ -59,7 +61,7 @@ pub fn init(dep: *std.Build.Dependency) Self { std.Target.riscv.Feature.m, }), .os_tag = .freestanding, - .abi = .none, + .abi = .eabi, }; const qingkev4b = .{ @@ -72,7 +74,7 @@ pub fn init(dep: *std.Build.Dependency) Self { std.Target.riscv.Feature.m, }), .os_tag = .freestanding, - .abi = .none, + .abi = .eabi, }; const chip_ch32v003x4: microzig.Target = .{ @@ -86,8 +88,8 @@ pub fn init(dep: *std.Build.Dependency) Self { .svd = b.path("src/chips/ch32v003.svd"), }, .memory_regions = &.{ - .{ .offset = 0x08000000, .length = 16 * 1024, .kind = .flash }, - .{ .offset = 0x20000000, .length = 2 * 1024, .kind = .ram }, + .{ .offset = 0x08000000, .length = 16 * KiB, .kind = .flash }, + .{ .offset = 0x20000000, .length = 2 * KiB, .kind = .ram }, }, }, .hal = hal_ch32v003, @@ -99,11 +101,10 @@ pub fn init(dep: *std.Build.Dependency) Self { .chip = .{ .name = "CH32V103xx", // from SVD .cpu = qingkev3, - // .cpu = microzig.cpus.riscv32_imac, .cpu_module_file = b.path("src/cpus/qingkev3-rv32imac.zig"), .memory_regions = &.{ - .{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash }, - .{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram }, + .{ .offset = 0x08000000, .length = 64 * KiB, .kind = .flash }, + .{ .offset = 0x20000000, .length = 20 * KiB, .kind = .ram }, }, .register_definition = .{ .svd = b.path("src/chips/ch32v103.svd"), @@ -118,11 +119,10 @@ pub fn init(dep: *std.Build.Dependency) Self { .chip = .{ .name = "CH32V103xx", // from SVD .cpu = qingkev3, - // .cpu = microzig.cpus.riscv32_imac, .cpu_module_file = b.path("src/cpus/qingkev3-rv32imac.zig"), .memory_regions = &.{ - .{ .offset = 0x08000000, .length = 32 * 1024, .kind = .flash }, - .{ .offset = 0x20000000, .length = 10 * 1024, .kind = .ram }, + .{ .offset = 0x08000000, .length = 32 * KiB, .kind = .flash }, + .{ .offset = 0x20000000, .length = 10 * KiB, .kind = .ram }, }, .register_definition = .{ .svd = b.path("src/chips/ch32v103.svd"), @@ -140,8 +140,8 @@ pub fn init(dep: *std.Build.Dependency) Self { .cpu = qingkev4b, .cpu_module_file = b.path("src/cpus/qingkev4-rv32imac.zig"), .memory_regions = &.{ - .{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash }, - .{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram }, + .{ .offset = 0x08000000, .length = 64 * KiB, .kind = .flash }, + .{ .offset = 0x20000000, .length = 20 * KiB, .kind = .ram }, }, .register_definition = .{ .svd = b.path("src/chips/ch32v20x.svd"), @@ -158,8 +158,8 @@ pub fn init(dep: *std.Build.Dependency) Self { .cpu = qingkev4b, .cpu_module_file = b.path("src/cpus/qingkev4-rv32imac.zig"), .memory_regions = &.{ - .{ .offset = 0x08000000, .length = 32 * 1024, .kind = .flash }, - .{ .offset = 0x20000000, .length = 10 * 1024, .kind = .ram }, + .{ .offset = 0x08000000, .length = 32 * KiB, .kind = .flash }, + .{ .offset = 0x20000000, .length = 10 * KiB, .kind = .ram }, }, .register_definition = .{ .svd = b.path("src/chips/ch32v20x.svd"), diff --git a/port/wch/ch32v/src/chips/ch32v003.svd b/port/wch/ch32v/src/chips/ch32v003.svd index fa19581a..5fc2e665 100644 --- a/port/wch/ch32v/src/chips/ch32v003.svd +++ b/port/wch/ch32v/src/chips/ch32v003.svd @@ -6,6 +6,14 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio CH32V00xxx 1.0 CH32V00xxx View File + + QINGKEV2 + r0p0 + little + false + false + 2 + @@ -108,16 +116,16 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - AWUAPR - AWUAPR + AWUWR + AWUWR Automatic wake window comparison value register - (PWR_AWUAPR) + (PWR_AWUWR) 0x0C 0x20 0x0000003F - AWUAPR + AWUWR AWU window value 0 6 @@ -279,27 +287,11 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 4 read-write - - PPRE1 - APB Low speed prescaler - (APB1) - 8 - 3 - read-write - - - PPRE2 - APB High speed prescaler - (APB2) - 11 - 3 - read-write - ADCPRE ADC prescaler - 14 - 2 + 11 + 5 read-write @@ -501,6 +493,12 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 + + TIM2RST + TIM2 reset + 0 + 1 + WWDGRST Window watchdog reset @@ -742,24 +740,17 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio Configure the extended control register 0x00 0x20 - 0x00000040 + 0x00000A00 - PLL_CFG - Configure the PLL clock delay time - 0 - 4 - read-write - - - LOCKUP_EN + LKUPEN LOCKUP_Enable 6 1 read-write - LOCKUP_RESET + LKUPRST LOCKUP RESET 7 1 @@ -769,27 +760,6 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio LDO_TRIM LDO_TRIM 10 - 1 - read-write - - - FLASH_CLK_TRIM - FLASH clock trimming - 11 - 3 - read-write - - - WR_EN - Control Register write enable - 14 - 1 - read-write - - - WR_LOCK - Control Register write lock - 15 1 read-write @@ -813,23 +783,6 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 18 1 read-write - - - - - EXTEND_KR - EXTEND - Configure the extended key register - 0x04 - 0x20 - 0x00000000 - - - KEY - Write key value - 0 - 32 - write-only @@ -1338,10 +1291,10 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - PCFR - PCFR + PCFR1 + PCFR1 AF remap and debug I/O configuration - register (AFIO_PCFR) + register (AFIO_PCFR1) 0x4 0x20 0x00000000 @@ -1361,7 +1314,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - USART1RM + USART1_RM USART1 remapping 2 1 @@ -1382,7 +1335,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - PA12RM + PA12_RM Port A1/Port A2 mapping on OSCIN/OSCOUT 15 @@ -1911,61 +1864,61 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x00000000 - PR0 + IF0 Pending bit 0 0 1 - PR1 + IF1 Pending bit 1 1 1 - PR2 + IF2 Pending bit 2 2 1 - PR3 + IF3 Pending bit 3 3 1 - PR4 + IF4 Pending bit 4 4 1 - PR5 + IF5 Pending bit 5 5 1 - PR6 + IF6 Pending bit 6 6 1 - PR7 + IF7 Pending bit 7 7 1 - PR8 + IF8 Pending bit 8 8 1 - PR9 + IF9 Pending bit 9 9 1 @@ -1985,37 +1938,37 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio registers - DMA1_Channel1 + DMA1_CH1 DMA1 Channel1 global interrupt 22 - DMA1_Channel2 + DMA1_CH2 DMA1 Channel2 global interrupt 23 - DMA1_Channel3 + DMA1_CH3 DMA1 Channel3 global interrupt 24 - DMA1_Channel4 + DMA1_CH4 DMA1 Channel4 global interrupt 25 - DMA1_Channel5 + DMA1_CH5 DMA1 Channel5 global interrupt 26 - DMA1_Channel6 + DMA1_CH6 DMA1 Channel6 global interrupt 27 - DMA1_Channel7 + DMA1_CH7 DMA1 Channel7 global interrupt 28 @@ -3604,7 +3557,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x0000 - WEIF + EWIF Early Wakeup Interrupt Flag 0 1 @@ -3625,24 +3578,24 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio registers - TIM1_BRK + TIM1BRK TIM1 Break interrupt 34 - TIM1_UP + TIM1UP TIM1 Update interrupt 35 - TIM1_TRG_COM + TIM1TRG TIM1 Trigger and Commutation interrupts 36 - TIM1_CC + TIM1CC TIM1 Capture Compare interrupt 37 @@ -3657,7 +3610,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x0000 - TMR_CAP_LVL_EN + CAPLVL Timer capture level indication enable 15 @@ -4404,7 +4357,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio CC4P - Capture/Compare 3 output + Capture/Compare 4 output Polarity 13 1 @@ -4732,7 +4685,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x0000 - DMAADR + DMAB DMA register for burst accesses 0 @@ -4768,14 +4721,14 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x0000 - TMR_CAP_LVL_EN + CAPLVL Timer capture level indication enable 15 1 - TMR_CAP_OV_EN + CAPOV Timer capture value configuration enable 14 @@ -5714,12 +5667,6 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 5 1 - - ENARP - ARP enable - 4 - 1 - PE Peripheral enable @@ -6233,20 +6180,19 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - CHSID - Channel side - 2 + UDR + Underrun flag + 3 1 read-only - UDR - Underrun flag - 3 + CHSID + Channel side + 2 1 read-only - TXE Transmit buffer empty @@ -6824,7 +6770,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x00000000 - ADC_CAL_VOL + CALVOL ADC Calibration voltage selection 25 2 @@ -7003,8 +6949,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - SAMPTR1_CHARGE1 - SAMPTR1_CHARGE1 + SAMPTR1 + SAMPTR1 sample time register 1 0xC 0x20 @@ -7012,42 +6958,42 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x00000000 - SMP10_TKCG10 + SMP10 Channel 10 sample time selection 0 3 - SMP11_TKCG11 + SMP11 Channel 11 sample time selection 3 3 - SMP12_TKCG12 + SMP12 Channel 12 sample time selection 6 3 - SMP13_TKCG13 + SMP13 Channel 13 sample time selection 9 3 - SMP14_TKCG14 + SMP14 Channel 14 sample time selection 12 3 - SMP15_TKCG15 + SMP15 Channel 15 sample time selection 15 @@ -7056,8 +7002,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - SAMPTR2_CHARGE2 - SAMPTR2_CHARGE2 + SAMPTR2 + SAMPTR2 sample time register 2 0x10 0x20 @@ -7065,70 +7011,70 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x00000000 - SMP0_TKCG0 + SMP0 Channel 0 sample time selection 0 3 - SMP1_TKCG1 + SMP1 Channel 1 sample time selection 3 3 - SMP2_TKCG2 + SMP2 Channel 2 sample time selection 6 3 - SMP3_TKCG3 + SMP3 Channel 3 sample time selection 9 3 - SMP4_TKCG4 - Channel 4 sample time + SMP4 + Channample time selection 12 3 - SMP5_TKCG5 + SMP5 Channel 5 sample time selection 15 3 - SMP6_TKCG6 + SMP6 Channel 6 sample time selection 18 3 - SMP7_TKCG7 + SMP7 Channel 7 sample time selection 21 3 - SMP8_TKCG8 + SMP8 Channel 8 sample time selection 24 3 - SMP9_TKCG9 + SMP9 Channel 9 sample time selection 27 @@ -7578,66 +7524,31 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x0 - DEG_IWDG + IWDG_STOP DEG_IWDG 0 1 - DEG_WWDG + WWDG_STOP DEG_WWDG 1 1 - DEG_I2C1 - DEG_I2C1 - 2 - 1 - - - DEG_TIM1 + TIM1_STOP DEG_TIM1 4 1 - DEG_TIM2 + TIM2_STOP DEG_TIM2 5 1 - - CFGR2 - CFGR2 - DBGMCU_CFGR2 - 0x4 - 0x20 - read-write - 0x0 - - - DBG_SLEEP - DBG_SLEEP - 0 - 1 - - - DBG_STOP - DBG_STOP - 1 - 1 - - - DBG_STANDBY - DBG_STANDBY - 2 - 1 - - - @@ -7661,7 +7572,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x0000 - FLASHSIZE + F_SIZE Flash size 0 16 @@ -7749,7 +7660,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio LATENCY Number of FLASH wait states 0 - 1 + 2 read-write @@ -7910,13 +7821,13 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 1 - PAGE_PG + FTPG Fast programming 16 1 - PAGE_ER + FTER Fast erase 17 1 @@ -7979,12 +7890,6 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 2 1 - - STOP_RST - STOP_RST - 3 - 1 - STANDY_RST STANDY_RST @@ -7992,8 +7897,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 1 - CFG_RST_MODE - CFG_RST_MODE + CFGRSTT + CFGRSTT 5 2 @@ -8093,55 +7998,31 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 2 - INTENSTA12_31 + INTENSTA12 Interrupt ID Status 12 - 20 + 1 - - - - ISR2 - ISR2 - Interrupt Status - Register - 0x04 - 0x20 - read-only - 0x00000000 - - INTENSTA + INTENSTA14 Interrupt ID Status - 0 - 32 + 14 + 1 - - - - ISR3 - ISR3 - Interrupt Status - Register - 0x08 - 0x20 - read-only - 0x00000000 - - INTENSTA + INTENSTA16_31 Interrupt ID Status - 0 - 32 + 16 + 16 - ISR4 - ISR4 + ISR2 + ISR2 Interrupt Status Register - 0x0C + 0x04 0x20 read-only 0x00000000 @@ -8150,7 +8031,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio INTENSTA Interrupt ID Status 0 - 8 + 7 @@ -8170,61 +8051,39 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 2 - PENDSTA12_31 + PENDSTA12 PENDSTA 12 - 20 + 1 - - - - IPR2 - IPR2 - Interrupt Pending Register - 0x24 - 0x20 - read-only - 0x00000000 - - PENDSTA + PENDSTA14 PENDSTA - 0 - 32 + 14 + 1 - - - - IPR3 - IPR3 - Interrupt Pending Register - 0x28 - 0x20 - read-only - 0x00000000 - - PENDSTA + PENDSTA16_31 PENDSTA - 0 - 32 + 16 + 16 - IPR4 - IPR4 + IPR2 + IPR2 Interrupt Pending Register - 0x2C + 0x24 0x20 read-only 0x00000000 - PENDSTA + PENDSTA32_38 PENDSTA 0 - 8 + 7 @@ -8319,18 +8178,6 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio VTFID1 8 8 - - - VTFID2 - VTFID2 - 16 - 8 - - - VTFID3 - VTFID3 - 24 - 8 @@ -8381,54 +8228,6 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 31 - - - VTFADDRR2 - VTFADDRR2 - Interrupt 2 address - Register - 0x68 - 0x20 - read-write - 0x00000000 - - - VTF2EN - VTF2EN - 0 - 1 - - - ADDR2 - ADDR2 - 1 - 31 - - - - - VTFADDRR3 - VTFADDRR3 - Interrupt 3 address - Register - 0x6C - 0x20 - read-write - 0x00000000 - - - VTF3EN - VTF3EN - 0 - 1 - - - ADDR3 - ADDR3 - 1 - 31 - - IENR1 @@ -8440,61 +8239,39 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x00000000 - INTEN + INTEN12 INTEN 12 - 20 + 1 - - - - IENR2 - IENR2 - Interrupt Setting Register - 0x104 - 0x20 - write-only - 0x00000000 - - INTEN + INTEN14 INTEN - 0 - 32 + 14 + 1 - - - - IENR3 - IENR3 - Interrupt Setting Register - 0x108 - 0x20 - write-only - 0x00000000 - - INTEN + INTEN16_31 INTEN - 0 - 32 + 16 + 16 - IENR4 - IENR4 + IENR2 + IENR2 Interrupt Setting Register - 0x10C + 0x104 0x20 write-only 0x00000000 INTEN - INTEN + INTEN32_38 0 - 8 + 7 @@ -8508,61 +8285,39 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x00000000 - INTRSET + INTRSET12 INTRSET 12 - 20 + 1 - - - - IRER2 - IRER2 - Interrupt Clear Register - 0x184 - 0x20 - write-only - 0x00000000 - - INTRSET + INTRSET14 INTRSET - 0 - 32 + 14 + 1 - - - - IRER3 - IRER3 - Interrupt Clear Register - 0x188 - 0x20 - write-only - 0x00000000 - - INTRSET + INTRSET16_31 INTRSET - 0 - 32 + 16 + 16 - IRER4 - IRER4 + IRER2 + IRER2 Interrupt Clear Register - 0x18C + 0x184 0x20 write-only 0x00000000 - INTRSET + INTRSET32_38 INTRSET 0 - 8 + 7 @@ -8582,61 +8337,39 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 2 - PENDSET12_31 + PENDSET12 PENDSET 12 - 20 + 1 - - - - IPSR2 - IPSR2 - Interrupt Pending Register - 0x204 - 0x20 - write-only - 0x00000000 - - PENDSET + PENDSET14 PENDSET - 0 - 32 + 14 + 1 - - - - IPSR3 - IPSR3 - Interrupt Pending Register - 0x208 - 0x20 - write-only - 0x00000000 - - PENDSET + PENDSET16_31 PENDSET - 0 - 32 + 16 + 16 - IPSR4 - IPSR4 + IPSR2 + IPSR2 Interrupt Pending Register - 0x20C + 0x204 0x20 write-only 0x00000000 - PENDSET + PENDSET32_38 PENDSET 0 - 8 + 7 @@ -8656,61 +8389,39 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 2 - PENDRESET12_31 + PENDRESET12 PENDRESET 12 - 20 + 1 - - - - IPRR2 - IPRR2 - Interrupt Pending Clear Register - 0x284 - 0x20 - write-only - 0x00000000 - - PENDRESET + PENDRESET14 PENDRESET - 0 - 32 + 14 + 1 - - - - IPRR3 - IPRR3 - Interrupt Pending Clear Register - 0x288 - 0x20 - write-only - 0x00000000 - - PENDRESET + PENDRESET16_31 PENDRESET - 0 - 32 + 16 + 16 - IPRR4 - IPRR4 + IPRR2 + IPRR2 Interrupt Pending Clear Register - 0x28C + 0x284 0x20 write-only 0x00000000 - PENDRESET + PENDRESET32_38 PENDRESET 0 - 8 + 7 @@ -8730,61 +8441,39 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 2 - IACTS12_31 + IACTS12 IACTS 12 - 20 + 1 - - - - IACTR2 - IACTR2 - Interrupt ACTIVE Register - 0x304 - 0x20 - write-only - 0x00000000 - - IACTS + IACTS14 IACTS - 0 - 32 + 14 + 1 - - - - IACTR3 - IACTR3 - Interrupt ACTIVE Register - 0x308 - 0x20 - write-only - 0x00000000 - - IACTS + IACTS16_31 IACTS - 0 - 32 + 16 + 16 - IACTR4 - IACTR4 + IACTR2 + IACTR2 Interrupt ACTIVE Register - 0x30C + 0x304 0x20 write-only 0x00000000 - IACTS + IACTS32_38 IACTS 0 - 8 + 7 diff --git a/port/wch/ch32v/src/chips/ch32v103.svd b/port/wch/ch32v/src/chips/ch32v103.svd index 513df0e9..ef9ccefc 100644 --- a/port/wch/ch32v/src/chips/ch32v103.svd +++ b/port/wch/ch32v/src/chips/ch32v103.svd @@ -6,6 +6,15 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio CH32V103xx 1.0 CH32V103xx View File + + QINGKEV3 + r0p0 + little + false + false + 2 + + @@ -16,7 +25,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x20 0x0 0xFFFFFFFF - + PWR @@ -132,7 +141,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + RCC Reset and clock control @@ -713,7 +722,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio USART1 clock enable 14 1 - + @@ -743,7 +752,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio Timer 4 clock enable 2 1 - + WWDGEN Window watchdog clock @@ -955,12 +964,12 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 12 1 read-write - + - + - + EXTEND extension configuration @@ -986,14 +995,14 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0 1 read-write - + USBDPU USBD pullup Enable 1 1 read-write - + USBHDIO USBHD IO(PB6/PB7) Enable @@ -1007,7 +1016,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 3 1 read-write - + HSIPRE Whether HSI is divided @@ -1021,35 +1030,35 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 6 1 read-write - + LKUPRESET LOCKUP RESET 7 1 read-write - + ULLDOTRIM ULLDOTRIM 8 2 read-write - + LDOTRIM LDOTRIM 10 1 read-write - + - - - + + + GPIOA General purpose I/O @@ -1940,7 +1949,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio GPIOD 0x40011400 - + AFIO Alternate function I/O @@ -3116,7 +3125,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + DMA DMA controller @@ -3128,37 +3137,37 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio registers - DMA1_Channel1 + DMA1_CH1 DMA1 Channel1 global interrupt 27 - DMA1_Channel2 + DMA1_CH2 DMA1 Channel2 global interrupt 28 - DMA1_Channel3 + DMA1_CH3 DMA1 Channel3 global interrupt 29 - DMA1_Channel4 + DMA1_CH4 DMA1 Channel4 global interrupt 30 - DMA1_Channel5 + DMA1_CH5 DMA1 Channel5 global interrupt 31 - DMA1_Channel6 + DMA1_CH6 DMA1 Channel6 global interrupt 32 - DMA1_Channel7 + DMA1_CH7 DMA1 Channel7 global interrupt 33 @@ -5300,19 +5309,19 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio registers - TIM1_BRK_TIM9 + TIM1_BRK TIM1 Break interrupt and TIM9 global interrupt 40 - TIM1_UP_TIM10 + TIM1_UP TIM1 Update interrupt and TIM10 global interrupt 41 - TIM1_TRG_COM_TIM11 + TIM1_TRG_COM TIM1 Trigger and Commutation interrupts and TIM11 global interrupt 42 @@ -6516,7 +6525,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio control 0 1 - + @@ -7316,8 +7325,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 46 - - + + I2C1 Inter integrated circuit @@ -8194,7 +8203,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + USART1 Universal synchronous asynchronous receiver @@ -9432,7 +9441,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + DAC1 Digital to analog converter @@ -9851,7 +9860,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + USBHD USB register @@ -9878,7 +9887,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio RB_UC_DMA_EN DMA enable and DMA interrupt enable for USB - [0:0] + [0:0] RB_UC_CLR_ALL @@ -10943,7 +10952,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x20 read-only 0x00000000 - + INTENSTA2_3 Interrupt ID Status @@ -11056,7 +11065,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio CFGR Interrupt Config Register 0x48 - 0x20 + 0x20 0x00000000 @@ -11488,7 +11497,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 28 - + @@ -11503,7 +11512,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio registers - USB_FS_WKUP + USBWakeUp USB Device FS Wakeup through EXTI line interrupt 58 @@ -11522,7 +11531,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio EA Endpoint address 0 - 4 + 4 STAT_TX @@ -12382,8 +12391,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - - + + - + diff --git a/port/wch/ch32v/src/chips/ch32v20x.svd b/port/wch/ch32v/src/chips/ch32v20x.svd index 4345c6f8..ff6e7137 100644 --- a/port/wch/ch32v/src/chips/ch32v20x.svd +++ b/port/wch/ch32v/src/chips/ch32v20x.svd @@ -6,6 +6,14 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio CH32V20xxx 1.0 CH32V20xxx View File + + QINGKEV4 + r0p0 + little + false + false + 2 + @@ -1346,7 +1354,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio SLKIE - Sleep interrupt + Sleep interrupt enable 17 1 @@ -1354,7 +1362,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio WKUIE - Wakeup interrupt + Wakeup interrupt enable 16 1 @@ -1362,7 +1370,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio ERRIE - Error interrupt + Error interrupt enable 15 1 @@ -1370,7 +1378,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio LECIE - Last error code interrupt + Last error code interrupt enable 11 1 @@ -1378,7 +1386,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio BOFIE - Bus-off interrupt + Bus-off interrupt enable 10 1 @@ -1386,7 +1394,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio EPVIE - Error passive interrupt + Error passive interrupt enable 9 1 @@ -1394,7 +1402,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio EWGIE - Error warning interrupt + Error warning interrupt enable 8 1 @@ -1402,7 +1410,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio FOVIE1 - FIFO overrun interrupt + FIFO overrun interrupt enable 6 1 @@ -1410,7 +1418,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio FFIE1 - FIFO full interrupt + FIFO full interrupt enable 5 1 @@ -1418,7 +1426,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio FMPIE1 - FIFO message pending interrupt + FIFO message pending interrupt enable 4 1 @@ -1426,7 +1434,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio FOVIE0 - FIFO overrun interrupt + FIFO overrun interrupt enable 3 1 @@ -1434,7 +1442,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio FFIE0 - FIFO full interrupt + FIFO full interrupt enable 2 1 @@ -1442,7 +1450,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio FMPIE0 - FIFO message pending interrupt + FIFO message pending interrupt enable 1 1 @@ -1450,7 +1458,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio TMEIE - Transmit mailbox empty interrupt + Transmit mailbox empty interrupt enable 0 1 @@ -1490,7 +1498,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio BOFF - Bus-off + Bus-off flag 2 1 @@ -1498,7 +1506,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio EPVF - Error passive + Error passive flag 1 1 @@ -1506,7 +1514,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio EWGF - Error warning + Error warning flag 0 1 @@ -2077,7 +2085,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio RXMDTR0 RXMDTR0 - CAN receive FIFO mailbox data length control and time stamp + CAN receive FIFO mailbox data length control and time stamp register 0x1B4 0x20 @@ -2227,7 +2235,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio RXMDTR1 RXMDTR1 - CAN receive FIFO mailbox data length control and time stamp + CAN receive FIFO mailbox data length control and time stamp register 0x1C4 0x20 @@ -14172,7 +14180,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + ETHERNET_MAC Ethernet: media access control @@ -14308,7 +14316,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 21 1 - + JD Jabber disable @@ -14321,7 +14329,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 23 1 - + TCD SEND clock delay @@ -16094,9 +16102,9 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - - - + + + DAC Digital to analog converter @@ -16470,7 +16478,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + PWR Power control @@ -16614,7 +16622,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + RCC Reset and clock control @@ -17393,7 +17401,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio USART1 clock enable 14 1 - + TIM9_EN TIM9 Timer clock enable @@ -17405,7 +17413,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio TIM10 Timer clock enable 20 1 - + @@ -17465,13 +17473,13 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio USART 7 clock enable 7 1 - + USART8_EN USART 8 clock enable 8 1 - + WWDGEN Window watchdog clock @@ -17716,7 +17724,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 12 1 read-write - + DVPRST DVP reset @@ -17730,7 +17738,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 14 1 read-write - + @@ -17862,14 +17870,14 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0 1 read-write - + USBDPU USBD pullup Enable 1 1 read-write - + ETH_10M_EN ETH 10M Enable @@ -17883,7 +17891,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 3 1 read-write - + PLL_HSI_PRE Whether HSI is divided @@ -17897,21 +17905,21 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 6 1 read-write - + LOCKUP_RSTF LOCKUP RESET 7 1 read-write - + ULLDO_TRIM ULLDO_TRIM 8 2 read-write - + LDO_TRIM LDO_TRIM @@ -17925,11 +17933,11 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 12 1 read-write - + - + OPA OPA configuration @@ -17955,14 +17963,14 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0 1 read-write - + MODE1 OPA MODE1 1 1 read-write - + NSEL1 OPA NSEL1 @@ -17976,7 +17984,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 3 1 read-write - + EN2 OPA Enable2 @@ -17997,21 +18005,21 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 6 1 read-write - + PSEL2 OPA PSEL2 7 1 read-write - + EN3 OPA Eable3 8 1 read-write - + MODE3 OPA MODE3 @@ -18025,46 +18033,46 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 10 1 read-write - + PSEL3 OPA PSEL3 11 1 read-write - + EN4 OPA Enable4 12 1 read-write - + MODE4 OPA MODE4 13 1 read-write - + NSEL4 OPA NSEL4 14 1 read-write - + PSEL4 OPA PSEL4 15 1 read-write - + - + GPIOA General purpose I/O @@ -20324,37 +20332,37 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio registers - DMA1_Channel1 + DMA1_CH1 DMA1 Channel1 global interrupt 27 - DMA1_Channel2 + DMA1_CH2 DMA1 Channel2 global interrupt 28 - DMA1_Channel3 + DMA1_CH3 DMA1 Channel3 global interrupt 29 - DMA1_Channel4 + DMA1_CH4 DMA1 Channel4 global interrupt 30 - DMA1_Channel5 + DMA1_CH5 DMA1 Channel5 global interrupt 31 - DMA1_Channel6 + DMA1_CH6 DMA1 Channel6 global interrupt 32 - DMA1_Channel7 + DMA1_CH7 DMA1 Channel7 global interrupt 33 @@ -23056,7 +23064,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x0 0x400 registers - + CTLR @@ -23077,7 +23085,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - PSCR + PSCR PSCR Prescaler register (IWDG_PSCR) 0x4 @@ -23253,8 +23261,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 40 - TIM1_UP_ - TIM1 Update + TIM1_UP + TIM1 Update interrupt 41 @@ -24355,7 +24363,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio TIM8_UP_ - TIM8 Update + TIM8 Update interrupt 60 @@ -24381,7 +24389,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio TIM9_UP_ - TIM9 Update + TIM9 Update interrupt 91 @@ -24407,7 +24415,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio TIM10_UP_ - TIM10 Update + TIM10 Update interrupt 95 @@ -25352,7 +25360,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio TIM5 global interrupt 66 - + I2C1 Inter integrated circuit @@ -26055,7 +26063,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 1 read-only - + TXE Transmit buffer empty @@ -26620,7 +26628,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio SPI3 global interrupt 67 - + USART1 Universal synchronous asynchronous receiver @@ -27099,7 +27107,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio registers - ADC + ADC1_2 ADC global interrupt 34 @@ -28808,7 +28816,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio DEG_TIM1 4 1 - + DEG_TIM2 DEG_TIM2 @@ -28826,7 +28834,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio DEG_TIM4 7 1 - + @@ -28892,7 +28900,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio RB_UC_DMA_EN DMA enable and DMA interrupt enable for USB - [0:0] + [0:0] RB_UC_CLR_ALL @@ -29059,7 +29067,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio USB_FRAME_NO [15:0] - + @@ -29102,7 +29110,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + USB_MIS_ST USB miscellaneous status @@ -29158,7 +29166,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio USB interrupt flag 0x0A 0x08 - + 0x20 @@ -29783,7 +29791,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP0_MAX_LEN endpoint 0 max acceptable length @@ -30024,8 +30032,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - - + + UEP0_T_LEN endpoint 0 send the length @@ -30040,7 +30048,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP0_T_CTRL endpoint 0 send control @@ -30067,7 +30075,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP0_R_CTRL endpoint 0 send control @@ -30094,8 +30102,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP1_T_LEN endpoint 1 send the length @@ -30110,7 +30118,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP1_T_CTRL endpoint 1 send control @@ -30137,7 +30145,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP1_R_CTRL endpoint 1 send control @@ -30164,8 +30172,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP2_T_LEN__UH_EP_PID endpoint 2 send the length @@ -30180,7 +30188,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP2_T_CTRL endpoint 2 send control @@ -30207,7 +30215,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP2_R_CTRL__UH_RX_CTRL endpoint 2 send control @@ -30246,8 +30254,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - - + + UEP3_T_LEN___UH_TX_LEN_H endpoint 3 send the length @@ -30262,7 +30270,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP3_T_CTRL___UH_TX_CTRL endpoint 3 send control @@ -30294,7 +30302,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio [5:5] read-write - + bUH_T_DATA_NO bUH_T_DATA_NO @@ -30302,7 +30310,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP3_R_CTRL endpoint 3 send control @@ -30329,8 +30337,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP4_T_LEN endpoint 4 send the length @@ -30345,7 +30353,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP4_T_CTRL endpoint 4 send control @@ -30372,7 +30380,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP4_R_CTRL endpoint 4 send control @@ -30399,8 +30407,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP5_T_LEN endpoint 5 send the length @@ -30415,7 +30423,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP5_T_CTRL endpoint 5 send control @@ -30442,7 +30450,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP5_R_CTRL endpoint 5 send control @@ -30469,8 +30477,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP6_T_LEN endpoint 6 send the length @@ -30485,7 +30493,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP6_T_CTRL endpoint 6 send control @@ -30512,7 +30520,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP6_R_CTRL endpoint 6 send control @@ -30539,8 +30547,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP7_T_LEN endpoint 7 send the length @@ -30555,7 +30563,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP7_T_CTRL endpoint 7 send control @@ -30582,7 +30590,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP7_R_CTRL endpoint 7 send control @@ -30609,8 +30617,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP8_T_LEN endpoint 8 send the length @@ -30625,7 +30633,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP8_T_CTRL endpoint 8 send control @@ -30652,7 +30660,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP8_R_CTRL endpoint 8 send control @@ -30679,8 +30687,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP9_T_LEN endpoint9 send the length @@ -30695,7 +30703,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP9_T_CTRL endpoint 9 send control @@ -30722,7 +30730,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP9_R_CTRL endpoint 9 send control @@ -30749,8 +30757,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP10_T_LEN endpoint 10 send the length @@ -30765,7 +30773,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP10_T_CTRL endpoint 10 send control @@ -30792,7 +30800,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP10_R_CTRL endpoint 10 send control @@ -30819,8 +30827,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP11_T_LEN endpoint 11 send the length @@ -30835,7 +30843,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP11_T_CTRL endpoint 11 send control @@ -30862,7 +30870,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP11_R_CTRL endpoint 11 send control @@ -30889,8 +30897,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP12_T_LEN endpoint 12 send the length @@ -30905,7 +30913,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP12_T_CTRL endpoint 12 send control @@ -30932,7 +30940,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP12_R_CTRL endpoint 12 send control @@ -30959,8 +30967,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP13_T_LEN endpoint 13 send the length @@ -30975,7 +30983,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP13_T_CTRL endpoint 13 send control @@ -31002,7 +31010,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP13_R_CTRL endpoint 13 send control @@ -31029,8 +31037,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP14_T_LEN endpoint 14 send the length @@ -31045,7 +31053,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP14_T_CTRL endpoint 14 send control @@ -31072,7 +31080,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP14_R_CTRL endpoint 14 send control @@ -31099,8 +31107,8 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - - + + UEP15_T_LEN endpoint 15 send the length @@ -31115,7 +31123,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP15_T_CTRL endpoint 15 send control @@ -31142,7 +31150,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write - + UEP15_R_CTRL endpoint 15 send control @@ -31169,7 +31177,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-only - + @@ -31593,7 +31601,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio USBHD_UC_DMA_EN DMA enable and DMA interrupt enable for USB - [0:0] + [0:0] USBHD_UC_CLR_ALL @@ -31638,7 +31646,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio USBHD_UH_PORT_EN__USBHD_UD_PORT_EN enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached - [0:0] + [0:0] USBHD_UH_BUS_RESET__USBHD_UD_GP_BIT @@ -31680,31 +31688,31 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio USBHD_UIE_BUS_RST__USBHD_UIE_DETECT enable interrupt for USB bus reset event for USB device mode [0:0] - + USBHD_UIE_TRANSFER enable interrupt for USB transfer completion [1:1] - + USBHD_UIE_SUSPEND enable interrupt for USB suspend or resume event [2:2] - + USBHD_UIE_HST_SOF enable interrupt for host SOF timer action for USB host mode [3:3] - + USBHD_UIE_FIFO_OV enable interrupt for FIFO overflow [4:4] - + USBHD_UIE_DEV_NAK @@ -31715,7 +31723,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio USBHD_UIE_DEV_SOF enable interrupt for SOF received for USB device mode [7:7] - + @@ -31949,7 +31957,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + R8_UEP5_6_MOD endpoint 5/6 mode 0x0e @@ -31989,7 +31997,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + R8_UEP7_MOD endpoint 7 mode 0x0f @@ -32055,21 +32063,21 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x24 0x20 read-write - + R32_UEP6_DMA endpoint 6 DMA buffer address 0x28 0x20 read-write - + R32_UEP7_DMA endpoint 7 DMA buffer address 0x2c 0x20 read-write - + R8_UEP0_T_LEN endpoint 0 transmittal length @@ -32126,7 +32134,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio [3:3] - + R8_UEP1_T_LEN endpoint 1 transmittal length @@ -32320,7 +32328,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + R8_UEP4_T_LEN endpoint 4 transmittal length @@ -32378,7 +32386,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + R8_UEP5_T_LEN endpoint 5 transmittal length @@ -32436,7 +32444,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio - + R8_UEP6_T_LEN endpoint 6 transmittal length @@ -32493,7 +32501,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio [3:3] - + R8_UEP7_T_LEN endpoint 7 transmittal length @@ -32550,7 +32558,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio [3:3] - + USB_OTG_CR usb otg control @@ -32620,7 +32628,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio [3:3] - + @@ -32631,7 +32639,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0xE000E000 0x00 - 0x1100 + 0x1100 registers @@ -32810,7 +32818,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio CFGR Interrupt Config Register 0x48 - 0x20 + 0x20 0x00000000 @@ -33446,7 +33454,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR11 IPRIOR11 @@ -33537,7 +33545,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR21 IPRIOR21 @@ -33619,7 +33627,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR30 IPRIOR30 @@ -33710,7 +33718,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR40 IPRIOR40 @@ -33801,7 +33809,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR50 IPRIOR50 @@ -33983,7 +33991,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR70 IPRIOR70 @@ -34074,7 +34082,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR80 IPRIOR80 @@ -34165,7 +34173,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR90 IPRIOR90 @@ -34255,7 +34263,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x8 read-write 0x00000000 - + IPRIOR100 IPRIOR100 @@ -34355,7 +34363,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR111 IPRIOR111 @@ -34446,7 +34454,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR121 IPRIOR121 @@ -34528,7 +34536,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR130 IPRIOR130 @@ -34619,7 +34627,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR140 IPRIOR140 @@ -34710,7 +34718,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR150 IPRIOR150 @@ -34892,7 +34900,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR170 IPRIOR170 @@ -34983,7 +34991,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR180 IPRIOR180 @@ -35074,7 +35082,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR190 IPRIOR190 @@ -35164,7 +35172,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 0x8 read-write 0x00000000 - + IPRIOR200 IPRIOR200 @@ -35174,7 +35182,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR201 IPRIOR201 @@ -35265,7 +35273,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR211 IPRIOR211 @@ -35356,7 +35364,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR221 IPRIOR221 @@ -35438,7 +35446,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR230 IPRIOR230 @@ -35529,7 +35537,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR240 IPRIOR240 @@ -35620,7 +35628,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + IPRIOR250 IPRIOR250 @@ -35675,7 +35683,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio read-write 0x00000000 - + SCTLR SCTLR @@ -35781,7 +35789,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 1 - + STK_SR System START @@ -35797,7 +35805,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 1 - + STK_CNTL System counter low register @@ -35813,7 +35821,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 32 - + STK_CNTH System counter high register @@ -35829,7 +35837,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 32 - + STK_CMPLR System compare low register @@ -35845,7 +35853,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 32 - + STK_CMPHR System compare high register @@ -35861,7 +35869,7 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocatio 32 - + diff --git a/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig b/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig index f2ebb0fd..951a173f 100644 --- a/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig +++ b/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig @@ -1,15 +1,14 @@ -// const std = @import("std"); const microzig = @import("microzig"); const root = @import("root"); pub const cpu_frequency = 24_000_000; // 24 MHz pub inline fn enable_interrupts() void { - asm volatile ("csrrs zero, mstatus, 0x8"); + asm volatile ("csrsi mstatus, 0b1000"); } pub inline fn disable_interrupts() void { - asm volatile ("csrrc zero, mstatus, 0x8"); + asm volatile ("csrci mstatus, 0b1000"); } pub inline fn wfi() void { @@ -17,29 +16,16 @@ pub inline fn wfi() void { } pub inline fn wfe() void { - // TODO: impliment wfe() - @compileError("wfe() is not implimented."); - // set WFITOWFE on PFIC_SCTLR followed by - // asm volatile ("wfi"); + const PFIC = microzig.chip.peripherals.PFIC; + // Treats the subsequent wfi instruction as wfe + PFIC.SCTLR.modify(.{ .WFITOWFE = 1 }); + asm volatile ("wfi"); } pub const startup_logic = struct { - comptime { - // Program codes are written from 0x800_0000. - // The PC pointer after reset is 0x0000_0000 and reads codes from alias of flash memory. - // This is not expected PC pointer on init.S. Thus jump to _abs_start is mandatory. - asm ( - \\.section microzig_flash_start - \\lui ra, %hi(_start) - \\jr %lo(_start)(ra) - ); - } - extern fn microzig_main() noreturn; pub fn _start() callconv(.C) noreturn { - microzig.cpu.disable_interrupts(); // Power-on reset makes interrupts disbaled. - // set global pointer asm volatile ( \\.option push @@ -52,11 +38,20 @@ pub const startup_logic = struct { : : [eos] "r" (@as(u32, microzig.config.end_of_stack)), ); - // root.initialize_system_memories(); - // smaller than initialize_system_memories() in start.zig - initialize_system_memories(); + root.initialize_system_memories(); + + // Vendor-defined CSRs + // 3.2 Interrupt-related CSR Registers + asm volatile ("csrsi 0x804, 0b111"); // INTSYSCR: enable EABI + Interrupt nesting + HPE + asm volatile ("csrsi mtvec, 0b11"); // mtvec: absolute address + vector table mode + microzig.cpu.enable_interrupts(); + microzig_main(); } + + export fn _reset_vector() linksection("microzig_flash_start") callconv(.Naked) void { + asm volatile ("j _start"); + } }; pub fn export_startup_logic() void { @@ -65,37 +60,13 @@ pub fn export_startup_logic() void { }); } -inline fn initialize_system_memories() void { - // clear .bss - asm volatile ( - \\clear_bss_section: - \\ la t0, microzig_bss_start - \\ la t1, microzig_bss_end - // \\ beq t0, t1, clear_bss_done - \\ j clear_bss_loop_end - \\clear_bss_loop: - \\ sw zero, 0(t0) - \\ addi t0, t0, 4 - \\clear_bss_loop_end: - \\ bltu t0, t1, clear_bss_loop - \\clear_bss_done: - ); +const VectorTable = microzig.chip.VectorTable; +pub const vector_table: VectorTable = blk: { + var tmp: VectorTable = .{}; + if (@hasDecl(root, "microzig_options")) { + for (@typeInfo(root.VectorTableOptions).Struct.fields) |field| + @field(tmp, field.name) = @field(root.microzig_options.interrupts, field.name); + } - // copy .data section to RAM - asm volatile ( - \\copy_data_section: - \\ la a0, microzig_data_load_start - \\ la a1, microzig_data_start - \\ la a2, microzig_data_end - // \\ beq a1, a2, copy_data_done - \\ j copy_data_loop_end - \\copy_data_loop: - \\ lw t0, 0(a0) - \\ sw t0, 0(a1) - \\ addi a0, a0, 4 - \\ addi a1, a1, 4 - \\copy_data_loop_end: - \\ bltu a1, a2, copy_data_loop - \\copy_data_done: - ); -} + break :blk tmp; +}; diff --git a/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig b/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig index a56bb3ed..5756de89 100644 --- a/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig +++ b/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig @@ -1,15 +1,14 @@ -// const std = @import("std"); const root = @import("root"); const microzig = @import("microzig"); pub const cpu_frequency = 8_000_000; // 8 MHz pub inline fn enable_interrupts() void { - asm volatile ("csrrs zero, mstatus, 0x8"); + asm volatile ("csrsi mstatus, 0b1000"); } pub inline fn disable_interrupts() void { - asm volatile ("csrrc zero, mstatus, 0x8"); + asm volatile ("csrci mstatus, 0b1000"); } pub inline fn wfi() void { @@ -17,35 +16,16 @@ pub inline fn wfi() void { } pub inline fn wfe() void { - // TODO: impliment wfe() - @compileError("wfe() is not implimented."); - // set WFITOWFE on PFIC_SCTLR followed by - // asm volatile ("wfi"); + const PFIC = microzig.chip.peripherals.PFIC; + // Treats the subsequent wfi instruction as wfe + PFIC.SCTLR.modify(.{ .WFITOWFE = 1 }); + asm volatile ("wfi"); } pub const startup_logic = struct { - comptime { - // CH32V103 starts from 0x800_0004 but CH32V203 starts from 0x800_0000. - // Two nops are required to make 4 bytes padding. The nop in RV32C is two bytes. - asm ( - \\.section microzig_flash_start - \\nop - \\nop - ); - // Program codes are written from 0x800_0000. - // The PC pointer after reset is 0x0000_0004 and reads codes from alias of flash memory. Refer 3.2.1 Power Reset on Datasheet. - // This is not expected PC pointer on init.S. Thus jump to _abs_start is mandatory. - asm ( - \\lui ra, %hi(_start) - \\jr %lo(_start)(ra) - ); - } - extern fn microzig_main() noreturn; pub fn _start() callconv(.C) noreturn { - microzig.cpu.disable_interrupts(); // Power-on reset makes interrupts disbaled. - // set global pointer asm volatile ( \\.option push @@ -58,11 +38,26 @@ pub const startup_logic = struct { : : [eos] "r" (@as(u32, microzig.config.end_of_stack)), ); - // root.initialize_system_memories(); - // smaller than initialize_system_memories() in start.zig - initialize_system_memories(); + root.initialize_system_memories(); + + // // Vendor-defined CSRs + // // 3.2 Interrupt-related CSR Registers + // asm volatile ("csrsi 0x804, 0b111"); // INTSYSCR: enable EABI + Interrupt nesting + HPE + asm volatile ("csrsi mtvec, 0b1"); // mtvec: vector table mode + microzig.cpu.enable_interrupts(); + microzig_main(); } + + export fn _reset_vector() linksection("microzig_flash_start") callconv(.Naked) void { + // CH32V103 starts from 0x000_0004 but the top of the microzig_flash_start is 0x000_0000. + // So, two nops are required to make 4 bytes padding. The nop in RV32C is two bytes. + asm volatile ( + \\nop + \\nop + \\j _start + ); + } }; pub fn export_startup_logic() void { @@ -71,37 +66,13 @@ pub fn export_startup_logic() void { }); } -inline fn initialize_system_memories() void { - // clear .bss - asm volatile ( - \\clear_bss_section: - \\ la t0, microzig_bss_start - \\ la t1, microzig_bss_end - // \\ beq t0, t1, clear_bss_done - \\ j clear_bss_loop_end - \\clear_bss_loop: - \\ sw zero, 0(t0) - \\ addi t0, t0, 4 - \\clear_bss_loop_end: - \\ bltu t0, t1, clear_bss_loop - \\clear_bss_done: - ); +const VectorTable = microzig.chip.VectorTable; +pub const vector_table: VectorTable = blk: { + var tmp: VectorTable = .{}; + if (@hasDecl(root, "microzig_options")) { + for (@typeInfo(root.VectorTableOptions).Struct.fields) |field| + @field(tmp, field.name) = @field(root.microzig_options.interrupts, field.name); + } - // copy .data section to RAM - asm volatile ( - \\copy_data_section: - \\ la a0, microzig_data_load_start - \\ la a1, microzig_data_start - \\ la a2, microzig_data_end - // \\ beq a1, a2, copy_data_done - \\ j copy_data_loop_end - \\copy_data_loop: - \\ lw t0, 0(a0) - \\ sw t0, 0(a1) - \\ addi a0, a0, 4 - \\ addi a1, a1, 4 - \\copy_data_loop_end: - \\ bltu a1, a2, copy_data_loop - \\copy_data_done: - ); -} + break :blk tmp; +}; diff --git a/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig b/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig index a7ca345e..7febcee3 100644 --- a/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig +++ b/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig @@ -1,15 +1,14 @@ -// const std = @import("std"); -const root = @import("root"); const microzig = @import("microzig"); +const root = @import("root"); pub const cpu_frequency = 8_000_000; // 8 MHz pub inline fn enable_interrupts() void { - asm volatile ("csrrs zero, mstatus, 0x8"); + asm volatile ("csrsi mstatus, 0b1000"); } pub inline fn disable_interrupts() void { - asm volatile ("csrrc zero, mstatus, 0x8"); + asm volatile ("csrci mstatus, 0b1000"); } pub inline fn wfi() void { @@ -17,29 +16,16 @@ pub inline fn wfi() void { } pub inline fn wfe() void { - // TODO: impliment wfe() - @compileError("wfe() is not implimented."); - // set WFITOWFE on PFIC_SCTLR followed by - // asm volatile ("wfi"); + const PFIC = microzig.chip.peripherals.PFIC; + // Treats the subsequent wfi instruction as wfe + PFIC.SCTLR.modify(.{ .WFITOWFE = 1 }); + asm volatile ("wfi"); } pub const startup_logic = struct { - comptime { - // Program codes are written from 0x800_0000. - // The PC pointer after reset is 0x0000_0000 and reads codes from alias of flash memory. - // This is not expected PC pointer on init.S. Thus jump to _abs_start is mandatory. - asm ( - \\.section microzig_flash_start - \\lui ra, %hi(_start) - \\jr %lo(_start)(ra) - ); - } - extern fn microzig_main() noreturn; pub fn _start() callconv(.C) noreturn { - microzig.cpu.disable_interrupts(); // Power-on reset makes interrupts disbaled. - // set global pointer asm volatile ( \\.option push @@ -52,11 +38,20 @@ pub const startup_logic = struct { : : [eos] "r" (@as(u32, microzig.config.end_of_stack)), ); - // root.initialize_system_memories(); - // smaller than initialize_system_memories() in start.zig - initialize_system_memories(); + root.initialize_system_memories(); + + // Vendor-defined CSRs + // 3.2 Interrupt-related CSR Registers + asm volatile ("csrsi 0x804, 0b0111"); // INTSYSCR: enable Interrupt nesting + HPE and the configured interrupt nesting depth is 2. + asm volatile ("csrsi mtvec, 0b11"); // mtvec: absolute address + vector table mode + microzig.cpu.enable_interrupts(); + microzig_main(); } + + export fn _reset_vector() linksection("microzig_flash_start") callconv(.Naked) void { + asm volatile ("j _start"); + } }; pub fn export_startup_logic() void { @@ -65,37 +60,13 @@ pub fn export_startup_logic() void { }); } -inline fn initialize_system_memories() void { - // clear .bss - asm volatile ( - \\clear_bss_section: - \\ la t0, microzig_bss_start - \\ la t1, microzig_bss_end - // \\ beq t0, t1, clear_bss_done - \\ j clear_bss_loop_end - \\clear_bss_loop: - \\ sw zero, 0(t0) - \\ addi t0, t0, 4 - \\clear_bss_loop_end: - \\ bltu t0, t1, clear_bss_loop - \\clear_bss_done: - ); +const VectorTable = microzig.chip.VectorTable; +pub const vector_table: VectorTable = blk: { + var tmp: VectorTable = .{}; + if (@hasDecl(root, "microzig_options")) { + for (@typeInfo(root.VectorTableOptions).Struct.fields) |field| + @field(tmp, field.name) = @field(root.microzig_options.interrupts, field.name); + } - // copy .data section to RAM - asm volatile ( - \\copy_data_section: - \\ la a0, microzig_data_load_start - \\ la a1, microzig_data_start - \\ la a2, microzig_data_end - // \\ beq a1, a2, copy_data_done - \\ j copy_data_loop_end - \\copy_data_loop: - \\ lw t0, 0(a0) - \\ sw t0, 0(a1) - \\ addi a0, a0, 4 - \\ addi a1, a1, 4 - \\copy_data_loop_end: - \\ bltu a1, a2, copy_data_loop - \\copy_data_done: - ); -} + break :blk tmp; +}; diff --git a/port/wch/ch32v/src/hals/hal_ch32v003.zig b/port/wch/ch32v/src/hals/hal_ch32v003.zig index cbdbd542..06dacd51 100644 --- a/port/wch/ch32v/src/hals/hal_ch32v003.zig +++ b/port/wch/ch32v/src/hals/hal_ch32v003.zig @@ -1,4 +1,28 @@ +const microzig = @import("microzig"); +pub const peripherals = microzig.chip.peripherals; + pub const pins = @import("ch32v003/pins.zig"); pub const gpio = @import("ch32v003/gpio.zig"); // pub fn init() void {} + +const RCC = peripherals.RCC; +const FLASH = peripherals.FLASH; + +pub fn rcc_init_hsi_pll() void { + const CFG0_PLL_TRIM: *u8 = @ptrFromInt(0x1FFFF7D4); // Factory HSI clock trim value + if (CFG0_PLL_TRIM.* != 0xFF) { + RCC.CTLR.modify(.{ .HSITRIM = @as(u5, @truncate(CFG0_PLL_TRIM.*)) }); + } + + FLASH.ACTLR.modify(.{ .LATENCY = 1 }); // Flash wait state 1 for 48MHz clock + + RCC.CFGR0.modify(.{ + .PLLSRC = 0, // HSI + .HPRE = 0, // Prescaler off + }); + RCC.CTLR.modify(.{ .PLLON = 1 }); + while (RCC.CTLR.read().PLLRDY != 1) {} + RCC.CFGR0.modify(.{ .SW = 0b10 }); // Select PLL clock source + while (RCC.CFGR0.read().SWS != 0b10) {} // Spin until PLL selected +} diff --git a/port/wch/ch32v/test/programs/minimal.zig b/port/wch/ch32v/test/programs/minimal.zig index 5258ce31..fb1377c0 100644 --- a/port/wch/ch32v/test/programs/minimal.zig +++ b/port/wch/ch32v/test/programs/minimal.zig @@ -1,5 +1,5 @@ const micro = @import("microzig"); -pub fn main() void { +pub fn main() !void { // This function will contain the application logic. } diff --git a/tools/regz/src/Database.zig b/tools/regz/src/Database.zig index 7ffe496d..709055e0 100644 --- a/tools/regz/src/Database.zig +++ b/tools/regz/src/Database.zig @@ -122,6 +122,11 @@ pub const Arch = enum { // mips mips, + // riscv + qingke_v2, + qingke_v3, + qingke_v4, + pub fn to_string(arch: Arch) []const u8 { return inline for (@typeInfo(Arch).Enum.fields) |field| { if (@field(Arch, field.name) == arch) @@ -178,6 +183,15 @@ pub const Arch = enum { else => false, }; } + + pub fn is_riscv(arch: Arch) bool { + return switch (arch) { + .qingke_v2 => true, + .qingke_v3 => true, + .qingke_v4 => true, + else => false, + }; + } }; // not sure how to communicate the *_once values in generated code diff --git a/tools/regz/src/arch/riscv.zig b/tools/regz/src/arch/riscv.zig new file mode 100644 index 00000000..5d434c40 --- /dev/null +++ b/tools/regz/src/arch/riscv.zig @@ -0,0 +1,134 @@ +//! codegen specific to riscv +const std = @import("std"); +const assert = std.debug.assert; + +const Database = @import("../Database.zig"); +const Arch = Database.Arch; +const EntityId = Database.EntityId; + +const gen = @import("../gen.zig"); +const InterruptWithIndexAndName = @import("InterruptWithIndexAndName.zig"); + +const log = std.log.scoped(.@"gen.riscv"); + +pub fn write_interrupt_vector( + db: Database, + device_id: EntityId, + writer: anytype, +) !void { + assert(db.entity_is("instance.device", device_id)); + const arch = db.instances.devices.get(device_id).?.arch; + assert(arch.is_riscv()); + + try writer.writeAll( + \\pub const VectorTable = extern struct { + \\ const Handler = micro.interrupt.Handler; + \\ const unhandled = micro.interrupt.unhandled; + \\ + ); + + var index: i32 = 0; + + // CPU specific vectors + switch (arch) { + .qingke_v2 => { + // start from No. 1 + try writer.writeAll( + \\ reserved1: [1]u32 = undefined, + \\ NMI: Handler = unhandled, + \\ EXC: Handler = unhandled, + \\ reserved4: [8]u32 = undefined, + \\ SysTick: Handler = unhandled, + \\ reserved13: [1]u32 = undefined, + \\ SW: Handler = unhandled, + \\ reserved15: [1]u32 = undefined, + \\ + ); + index = 16; + }, + .qingke_v3 => { + // start from No. 2 + try writer.writeAll( + \\ NMI: Handler = unhandled, + \\ EXC: Handler = unhandled, + \\ reserved4: [8]u32 = undefined, + \\ SysTick: Handler = unhandled, + \\ reserved13: [1]u32 = undefined, + \\ SWI: Handler = unhandled, + \\ reserved15: [1]u32 = undefined, + \\ + ); + index = 16; + }, + .qingke_v4 => { + // start from No. 1 + try writer.writeAll( + \\ reserved1: [1]u32 = undefined, + \\ NMI: Handler = unhandled, + \\ HardFault: Handler = unhandled, + \\ reserved4: [1]u32 = undefined, + \\ Ecall_M: Handler = unhandled, + \\ reserved6: [2]u32 = undefined, + \\ Ecall_U: Handler = unhandled, + \\ BreakPoint: Handler = unhandled, + \\ reserved10: [2]u32 = undefined, + \\ SysTick: Handler = unhandled, + \\ reserved13: [1]u32 = undefined, + \\ SW: Handler = unhandled, + \\ reserved15: [1]u32 = undefined, + \\ + ); + index = 16; + }, + else => {}, + } + + if (db.children.interrupts.get(device_id)) |interrupt_set| { + var interrupts = std.ArrayList(InterruptWithIndexAndName).init(db.gpa); + defer interrupts.deinit(); + + var it = interrupt_set.iterator(); + while (it.next()) |entry| { + const interrupt_id = entry.key_ptr.*; + const interrupt_index = db.instances.interrupts.get(interrupt_id).?; + const name = db.attrs.name.get(interrupt_id) orelse continue; + + try interrupts.append(.{ + .id = interrupt_id, + .name = name, + .index = interrupt_index, + }); + } + + std.sort.insertion( + InterruptWithIndexAndName, + interrupts.items, + {}, + InterruptWithIndexAndName.less_than, + ); + + for (interrupts.items) |interrupt| { + if (index < interrupt.index) { + try writer.print("reserved{}: [{}]u32 = undefined,\n", .{ + index, + interrupt.index - index, + }); + index = interrupt.index; + } else if (index > interrupt.index) { + log.warn("skipping interrupt: {s}", .{interrupt.name}); + continue; + } + + if (db.attrs.description.get(interrupt.id)) |description| + try gen.write_comment(db.gpa, description, writer); + + try writer.print("{}: Handler = unhandled,\n", .{ + std.zig.fmtId(interrupt.name), + }); + + index += 1; + } + } + + try writer.writeAll("};\n\n"); +} diff --git a/tools/regz/src/gen.zig b/tools/regz/src/gen.zig index d03883c8..d4f6b428 100644 --- a/tools/regz/src/gen.zig +++ b/tools/regz/src/gen.zig @@ -9,6 +9,7 @@ const EntitySet = Database.EntitySet; const arm = @import("arch/arm.zig"); const avr = @import("arch/avr.zig"); +const riscv = @import("arch/riscv.zig"); const log = std.log.scoped(.gen); @@ -245,6 +246,8 @@ fn write_vector_table( try arm.write_interrupt_vector(db, device_id, writer) else if (arch.is_avr()) try avr.write_interrupt_vector(db, device_id, writer) + else if (arch.is_riscv()) + try riscv.write_interrupt_vector(db, device_id, writer) else if (arch == .unknown) return else diff --git a/tools/regz/src/svd.zig b/tools/regz/src/svd.zig index d03fc7ee..3ac0a651 100644 --- a/tools/regz/src/svd.zig +++ b/tools/regz/src/svd.zig @@ -215,6 +215,12 @@ fn arch_from_str(str: []const u8) Database.Arch { .cortex_a57 else if (std.mem.eql(u8, "CA72", str)) .cortex_a72 + else if (std.mem.eql(u8, "QINGKEV2", str)) + .qingke_v2 + else if (std.mem.eql(u8, "QINGKEV3", str)) + .qingke_v3 + else if (std.mem.eql(u8, "QINGKEV4", str)) + .qingke_v4 else .unknown; }