From ae1d2e1f4ddff9b8bf52a89ae402e5c4d297f27c Mon Sep 17 00:00:00 2001 From: Taylor Hillegeist Date: Tue, 21 Jan 2025 01:03:37 -0600 Subject: [PATCH] Supporting non-contiguous registers (#357) This commit adds support for items with multiple start-end points inside of the bit_offset field of the json data. (its for the STM32). --- port/stmicro/stm32/src/chips/all.zig | 378 ++++++++++++++++++++++++--- port/stmicro/stm32/src/generate.zig | 83 ++++-- 2 files changed, 403 insertions(+), 58 deletions(-) diff --git a/port/stmicro/stm32/src/chips/all.zig b/port/stmicro/stm32/src/chips/all.zig index dabfac76..d4079d02 100644 --- a/port/stmicro/stm32/src/chips/all.zig +++ b/port/stmicro/stm32/src/chips/all.zig @@ -312580,7 +312580,29 @@ pub const types = struct { DATATYPE: DATATYPE, /// Operating mode MODE: MODE, - padding: u27, + /// Chaining mode selection + CHMOD: u2, + reserved11: u4, + /// Enable DMA management of data input phase + DMAINEN: u1, + /// Enable DMA management of data output phase + DMAOUTEN: u1, + /// GCM or CCM phase selection + GCMPH: GCMPH, + reserved16: u1, + /// Chaining mode selection + CHMOD_CONT: u1, + reserved18: u1, + /// Key size selection + KEYSIZE: u1, + reserved20: u1, + /// Number of padding bytes in last block of payload + NPBLB: u4, + /// Key mode selection + KMOD: u2, + reserved31: u5, + /// AES peripheral software reset + IPRST: u1, }), /// Status register SR: mmio.Mmio(packed struct(u32) { @@ -312700,7 +312722,29 @@ pub const types = struct { DATATYPE: DATATYPE, /// Operating mode MODE: MODE, - padding: u27, + /// Chaining mode selection + CHMOD: u2, + reserved11: u4, + /// Enable DMA management of data input phase + DMAINEN: u1, + /// Enable DMA management of data output phase + DMAOUTEN: u1, + /// GCM or CCM phase selection + GCMPH: GCMPH, + reserved16: u1, + /// Chaining mode selection + CHMOD_CONT: u1, + reserved18: u1, + /// Key size selection + KEYSIZE: u1, + reserved20: u1, + /// Number of padding bytes in last block of payload + NPBLB: u4, + /// Key mode selection + KMOD: u2, + reserved31: u5, + /// AES peripheral software reset + IPRST: u1, }), /// Status register SR: mmio.Mmio(packed struct(u32) { @@ -359955,7 +359999,28 @@ pub const types = struct { reserved9: u1, /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. PRESC: PRESC, - padding: u20, + reserved13: u1, + /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. + TRIGSEL: u3, + reserved17: u1, + /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + TRIGEN: TRIGEN, + /// Timeout enable The TIMOUT bit controls the Timeout feature. + TIMOUT: u1, + /// Waveform shape The WAVE bit controls the output shape. + WAVE: u1, + /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. + WAVPOL: WAVPOL, + /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + PRELOAD: u1, + /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + COUNTMODE: ClockSource, + /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + ENC: u1, + reserved29: u4, + /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. + TRIGSEL_CONT: u1, + padding: u2, }), /// LPTIM control register. CR: mmio.Mmio(packed struct(u32) { @@ -425251,7 +425316,34 @@ pub const types = struct { DATATYPE: DATATYPE, /// SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. MODE: MODE, - padding: u27, + /// Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + CHMOD: u2, + reserved11: u4, + /// DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by SAES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). + DMAINEN: u1, + /// DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). + DMAOUTEN: u1, + /// GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield). + GCMPH: GCMPH, + reserved16: u1, + /// Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + CHMOD_CONT: u1, + reserved18: u1, + /// Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD[1:0]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + KEYSIZE: KEYSIZE, + /// Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + KEYPROT: u1, + /// Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ... + NPBLB: u4, + /// Key mode selection The bitfield defines how the SAES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0] bitfield. This sharing is valid only while KMOD[1:0]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With KMOD[1:0] other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (secure or non-secure) results in automatic key erasure and setting of the KEIF flag. + ///Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + KMOD: KMOD, + /// Key share identification This bitfield defines, at the end of a decryption process with KMOD[1:0]=10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. Others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + KSHAREID: KSHAREID, + /// Key selection The bitfield defines the source of the key information to use in the AES cryptographic core. Others: Reserved (if used, unfreeze SAES with IPRST) When KEYSEL is different from zero, selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the SAES_SR register. Otherwise, the key error flag KEIF is set. Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID = 0. When the application software changes the key selection by writing the KEYSEL[2:0] bitfield, the key registers are immediately erased and the KEYVALID flag cleared. At the end of the decryption process, if KMOD[1:0] is other than zero, KEYSEL[2:0] is cleared. With the bitfield value other than zero and KEYVALID set, the application cannot transfer the ownership of SAES with a loaded key to an application running in another security context (such as secure, non-secure). More specifically, when security of an access to any register does not match the information recorded by SAES, the KEIF flag is set. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + KEYSEL: KEYSEL, + /// SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers. + IPRST: u1, }), /// SAES status register. SR: mmio.Mmio(packed struct(u32) { @@ -425398,7 +425490,31 @@ pub const types = struct { DATATYPE: DATATYPE, /// SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. MODE: MODE, - padding: u27, + /// Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + CHMOD: u2, + reserved11: u4, + /// DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by SAES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). + DMAINEN: u1, + /// DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). + DMAOUTEN: u1, + reserved16: u3, + /// Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + CHMOD_CONT: u1, + reserved18: u1, + /// Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD[1:0]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + KEYSIZE: KEYSIZE, + /// Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + KEYPROT: u1, + reserved24: u4, + /// Key mode selection The bitfield defines how the SAES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0] bitfield. This sharing is valid only while KMOD[1:0]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With KMOD[1:0] other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (secure or non-secure) results in automatic key erasure and setting of the KEIF flag. + ///Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + KMOD: KMOD, + /// Key share identification This bitfield defines, at the end of a decryption process with KMOD[1:0]=10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. Others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + KSHAREID: KSHAREID, + /// Key selection The bitfield defines the source of the key information to use in the AES cryptographic core. Others: Reserved (if used, unfreeze SAES with IPRST) When KEYSEL is different from zero, selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the SAES_SR register. Otherwise, the key error flag KEIF is set. Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID = 0. When the application software changes the key selection by writing the KEYSEL[2:0] bitfield, the key registers are immediately erased and the KEYVALID flag cleared. At the end of the decryption process, if KMOD[1:0] is other than zero, KEYSEL[2:0] is cleared. With the bitfield value other than zero and KEYVALID set, the application cannot transfer the ownership of SAES with a loaded key to an application running in another security context (such as secure, non-secure). More specifically, when security of an access to any register does not match the information recorded by SAES, the KEIF flag is set. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + KEYSEL: KEYSEL, + /// SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers. + IPRST: u1, }), /// SAES status register. SR: mmio.Mmio(packed struct(u32) { @@ -439181,7 +439297,22 @@ pub const types = struct { padding: u24, }), /// slave mode control register - SMCR: u32, + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: MSM, + reserved16: u8, + /// Slave mode selection + SMS_CONT: u1, + reserved20: u3, + /// Trigger selection + TS_CONT: u2, + padding: u10, + }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { /// Update interrupt enable @@ -439343,7 +439474,22 @@ pub const types = struct { padding: u21, }), /// slave mode control register - SMCR: u32, + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: MSM, + reserved16: u8, + /// Slave mode selection + SMS_CONT: u1, + reserved20: u3, + /// Trigger selection + TS_CONT: u2, + padding: u10, + }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { /// Update interrupt enable @@ -439602,7 +439748,13 @@ pub const types = struct { }), /// slave mode control register SMCR: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: MSM, /// External trigger filter ETF: FilterValue, /// External trigger prescaler @@ -439611,7 +439763,12 @@ pub const types = struct { ECE: u1, /// External trigger polarity ETP: ETP, - padding: u16, + /// Slave mode selection + SMS_CONT: u1, + reserved20: u3, + /// Trigger selection + TS_CONT: u2, + padding: u10, }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { @@ -440156,7 +440313,13 @@ pub const types = struct { }), /// slave mode control register SMCR: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: MSM, /// External trigger filter ETF: FilterValue, /// External trigger prescaler @@ -440165,7 +440328,12 @@ pub const types = struct { ECE: u1, /// External trigger polarity ETP: ETP, - padding: u16, + /// Slave mode selection + SMS_CONT: u1, + reserved20: u3, + /// Trigger selection + TS_CONT: u2, + padding: u10, }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { @@ -440394,7 +440562,13 @@ pub const types = struct { }), /// slave mode control register SMCR: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: MSM, /// External trigger filter ETF: FilterValue, /// External trigger prescaler @@ -440403,7 +440577,12 @@ pub const types = struct { ECE: u1, /// External trigger polarity ETP: ETP, - padding: u16, + /// Slave mode selection + SMS_CONT: u1, + reserved20: u3, + /// Trigger selection + TS_CONT: u2, + padding: u10, }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { @@ -441385,9 +441564,34 @@ pub const types = struct { padding: u19, }), /// control register 2 - CR2: u32, + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: TI1S, + reserved25: u17, + /// Master mode selection + MMS_CONT: u1, + padding: u6, + }), /// slave mode control register - SMCR: u32, + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: MSM, + reserved16: u8, + /// Slave mode selection + SMS_CONT: u1, + reserved20: u3, + /// Trigger selection + TS_CONT: u2, + padding: u10, + }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { /// Update interrupt enable @@ -441530,10 +441734,45 @@ pub const types = struct { padding: u19, }), /// control register 2 - CR2: u32, + CR2: mmio.Mmio(packed struct(u32) { + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: CCDS, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: TI1S, + /// (1/2 of OIS) Output Idle state x (x=1,2) + @"OIS[0]": u1, + /// (1/1 of OISN) Output Idle state x (x=1) + @"OISN[0]": u1, + /// (2/2 of OIS) Output Idle state x (x=1,2) + @"OIS[1]": u1, + reserved25: u14, + /// Master mode selection + MMS_CONT: u1, + padding: u6, + }), /// slave mode control register SMCR: mmio.Mmio(packed struct(u32) { - reserved24: u24, + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: MSM, + reserved16: u8, + /// Slave mode selection + SMS_CONT: u1, + reserved20: u3, + /// Trigger selection + TS_CONT: u2, + reserved24: u2, /// SMS preload enable SMSPE: u1, padding: u7, @@ -441796,7 +442035,17 @@ pub const types = struct { }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: CCDS, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: TI1S, /// (1/6 of OIS) Output Idle state x (x=1-6) @"OIS[0]": u1, /// (1/4 of OISN) Output Idle state x N x (x=1-4) @@ -441821,14 +442070,21 @@ pub const types = struct { reserved20: u1, /// Master mode selection 2 MMS2: MMS2, - padding: u8, + reserved25: u1, + /// Master mode selection + MMS_CONT: u1, + padding: u6, }), /// slave mode control register SMCR: mmio.Mmio(packed struct(u32) { - reserved3: u3, + /// Slave mode selection + SMS: u3, /// OCREF clear selection OCCS: OCCS, - reserved8: u4, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: MSM, /// External trigger filter ETF: FilterValue, /// External trigger prescaler @@ -441837,7 +442093,12 @@ pub const types = struct { ECE: u1, /// External trigger polarity ETP: ETP, - reserved24: u8, + /// Slave mode selection + SMS_CONT: u1, + reserved20: u3, + /// Trigger selection + TS_CONT: u2, + reserved24: u2, /// SMS preload enable SMSPE: u1, /// SMS preload source @@ -442108,12 +442369,25 @@ pub const types = struct { @"OCFE[0]": u1, /// (1/2 of OCPE) Output compare x (x=5,6) preload enable @"OCPE[0]": u1, - reserved10: u6, + /// (1/2 of OCM) Output compare x (x=5,6) mode + @"OCM[0]": u3, + /// (1/2 of OCCE) Output compare x (x=5,6) clear enable + @"OCCE[0]": u1, + reserved10: u2, /// (2/2 of OCFE) Output compare x (x=5,6) fast enable @"OCFE[1]": u1, /// (2/2 of OCPE) Output compare x (x=5,6) preload enable @"OCPE[1]": u1, - padding: u20, + /// (2/2 of OCM) Output compare x (x=5,6) mode + @"OCM[1]": u3, + /// (2/2 of OCCE) Output compare x (x=5,6) clear enable + @"OCCE[1]": u1, + /// (1/2 of OCM_CONT) Output compare x (x=5,6) mode + @"OCM_CONT[0]": u1, + reserved24: u7, + /// (2/2 of OCM_CONT) Output compare x (x=5,6) mode + @"OCM_CONT[1]": u1, + padding: u7, }), /// break and dead-time register DTR2: mmio.Mmio(packed struct(u32) { @@ -442271,7 +442545,15 @@ pub const types = struct { padding: u19, }), /// control register 2 - CR2: u32, + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: u3, + reserved25: u18, + /// Master mode selection + MMS_CONT: u1, + padding: u6, + }), reserved12: [4]u8, /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { @@ -442468,14 +442750,24 @@ pub const types = struct { reserved3: u3, /// Capture/compare DMA selection CCDS: CCDS, - reserved7: u3, + /// Master mode selection + MMS: u3, /// TI1 selection TI1S: TI1S, - padding: u24, + reserved25: u17, + /// Master mode selection + MMS_CONT: u1, + padding: u6, }), /// slave mode control register SMCR: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: MSM, /// External trigger filter ETF: FilterValue, /// External trigger prescaler @@ -442484,7 +442776,12 @@ pub const types = struct { ECE: u1, /// External trigger polarity ETP: ETP, - reserved24: u8, + /// Slave mode selection + SMS_CONT: u1, + reserved20: u3, + /// Trigger selection + TS_CONT: u2, + reserved24: u2, /// SMS preload enable SMSPE: u1, /// SMS preload source @@ -442754,14 +443051,24 @@ pub const types = struct { reserved3: u3, /// Capture/compare DMA selection CCDS: CCDS, - reserved7: u3, + /// Master mode selection + MMS: u3, /// TI1 selection TI1S: TI1S, - padding: u24, + reserved25: u17, + /// Master mode selection + MMS_CONT: u1, + padding: u6, }), /// slave mode control register SMCR: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: MSM, /// External trigger filter ETF: FilterValue, /// External trigger prescaler @@ -442770,7 +443077,12 @@ pub const types = struct { ECE: u1, /// External trigger polarity ETP: ETP, - reserved24: u8, + /// Slave mode selection + SMS_CONT: u1, + reserved20: u3, + /// Trigger selection + TS_CONT: u2, + reserved24: u2, /// SMS preload enable SMSPE: u1, /// SMS preload source diff --git a/port/stmicro/stm32/src/generate.zig b/port/stmicro/stm32/src/generate.zig index b1a4623f..9d5af883 100644 --- a/port/stmicro/stm32/src/generate.zig +++ b/port/stmicro/stm32/src/generate.zig @@ -334,35 +334,68 @@ pub fn main() !void { for (fieldset_value.get("fields").?.array.items) |field| { const field_name = field.object.get("name").?.string; const field_description: ?[]const u8 = if (field.object.get("description")) |desc| desc.string else null; - const bit_offset = switch (field.object.get("bit_offset").?) { - .integer => |int| int, + switch (field.object.get("bit_offset").?) { + .integer => |int| { + const bit_offset = int; + const bit_size = field.object.get("bit_size").?.integer; + const enum_id: ?regz.Database.EnumID = if (field.object.get("enum")) |enum_name| + if (enums.get(enum_name.string)) |enum_id| enum_id else null + else + null; + var array_count: ?u16 = null; + var array_stride: ?u8 = null; + if (field.object.get("array")) |array| { + array_count = if (array.object.get("len")) |len| @intCast(len.integer) else null; + array_stride = if (array.object.get("stride")) |stride| @intCast(stride.integer) else null; + } + + try db.add_register_field(register_id, .{ + .name = field_name, + .description = field_description, + .offset_bits = @intCast(bit_offset), + .size_bits = @intCast(bit_size), + .enum_id = enum_id, + .count = array_count, + .stride = array_stride, + }); + }, + .array => |arr| { + if (arr.items.len != 2) { + //This should never happen, because the input data as of yet doesn't contain this. + std.log.warn("skipping {s}, it's an non-consecutive field with more than two parts", .{field_name}); + continue; + } + const cont_field = try std.fmt.allocPrint(allocator, "{s}_CONT", .{field_name}); + const field_names = [2][]const u8{ field_name, cont_field }; + + for (arr.items, field_names) |non_contiguous_offset, non_contiguous_field_name| { + const bit_offset = non_contiguous_offset.object.get("start").?.integer; + const bit_size = non_contiguous_offset.object.get("end").?.integer - bit_offset + 1; + + const enum_id = null; //These can't handle the ENUM size but it will still be avaiable to use. + + var array_count: ?u16 = null; + var array_stride: ?u8 = null; + if (field.object.get("array")) |array| { + array_count = if (array.object.get("len")) |len| @intCast(len.integer) else null; + array_stride = if (array.object.get("stride")) |stride| @intCast(stride.integer) else null; + } + + try db.add_register_field(register_id, .{ + .name = non_contiguous_field_name, + .description = field_description, + .offset_bits = @intCast(bit_offset), + .size_bits = @intCast(bit_size), + .enum_id = enum_id, + .count = array_count, + .stride = array_stride, + }); + } + }, else => |val| { std.log.warn("skipping {s}, it's a {}", .{ field_name, val }); - break :blk; }, - }; - - const bit_size = field.object.get("bit_size").?.integer; - const enum_id: ?regz.Database.EnumID = if (field.object.get("enum")) |enum_name| - if (enums.get(enum_name.string)) |enum_id| enum_id else null - else - null; - var array_count: ?u16 = null; - var array_stride: ?u8 = null; - if (field.object.get("array")) |array| { - array_count = if (array.object.get("len")) |len| @intCast(len.integer) else null; - array_stride = if (array.object.get("stride")) |stride| @intCast(stride.integer) else null; } - - try db.add_register_field(register_id, .{ - .name = field_name, - .description = field_description, - .offset_bits = @intCast(bit_offset), - .size_bits = @intCast(bit_size), - .enum_id = enum_id, - .count = array_count, - .stride = array_stride, - }); } } }