From 86df0aab712cf79b52c0b991c751078595370019 Mon Sep 17 00:00:00 2001 From: Junhui Liu <80765805+pigmoral@users.noreply.github.com> Date: Thu, 13 Feb 2025 05:00:46 +0800 Subject: [PATCH] WCH: Add support for CH32V307 chip and CH32V307V-R1-1v0 board (#383) --- examples/wch/ch32v/build.zig | 5 + port/wch/ch32v/build.zig | 57 + .../wch/ch32v/src/boards/CH32V307V-R1-1v0.zig | 6 + port/wch/ch32v/src/chips/ch32v30x.svd | 40051 ++++++++++++++++ port/wch/ch32v/src/hals/hal_ch32v307.zig | 4 + 5 files changed, 40123 insertions(+) create mode 100644 port/wch/ch32v/src/boards/CH32V307V-R1-1v0.zig create mode 100644 port/wch/ch32v/src/chips/ch32v30x.svd create mode 100644 port/wch/ch32v/src/hals/hal_ch32v307.zig diff --git a/examples/wch/ch32v/build.zig b/examples/wch/ch32v/build.zig index 5e64e96b..70554029 100644 --- a/examples/wch/ch32v/build.zig +++ b/examples/wch/ch32v/build.zig @@ -28,6 +28,11 @@ pub fn build(b: *std.Build) void { .{ .target = mb.ports.ch32v.chips.ch32v203x8, .name = "empty_ch32v203", .file = "src/empty.zig" }, .{ .target = mb.ports.ch32v.chips.ch32v203x8, .name = "blinky_ch32v203", .file = "src/blinky.zig" }, .{ .target = mb.ports.ch32v.boards.ch32v203.suzuduino_uno_v1b, .name = "suzuduino_blinky", .file = "src/board_blinky.zig" }, + + // CH32V307 + .{ .target = mb.ports.ch32v.chips.ch32v307xc, .name = "empty_ch32v307", .file = "src/empty.zig" }, + .{ .target = mb.ports.ch32v.chips.ch32v307xc, .name = "blinky_ch32v307", .file = "src/blinky.zig" }, + .{ .target = mb.ports.ch32v.boards.ch32v307.ch32v307v_r1_1v0, .name = "ch32v307v_r1_1v0_blinky", .file = "src/blinky.zig" }, }; for (available_examples) |example| { diff --git a/port/wch/ch32v/build.zig b/port/wch/ch32v/build.zig index 6e5cdd13..be4f9707 100644 --- a/port/wch/ch32v/build.zig +++ b/port/wch/ch32v/build.zig @@ -11,6 +11,7 @@ chips: struct { ch32v103x8: *const microzig.Target, ch32v203x6: *const microzig.Target, ch32v203x8: *const microzig.Target, + ch32v307xc: *const microzig.Target, }, boards: struct { @@ -23,6 +24,9 @@ boards: struct { ch32v203: struct { suzuduino_uno_v1b: *const microzig.Target, }, + ch32v307: struct { + ch32v307v_r1_1v0: *const microzig.Target, + }, }, pub fn init(dep: *std.Build.Dependency) Self { @@ -37,6 +41,9 @@ pub fn init(dep: *std.Build.Dependency) Self { const hal_ch32v203: microzig.HardwareAbstractionLayer = .{ .root_source_file = b.path("src/hals/hal_ch32v203.zig"), }; + const hal_ch32v307: microzig.HardwareAbstractionLayer = .{ + .root_source_file = b.path("src/hals/hal_ch32v307.zig"), + }; const qingkev2a = .{ // QingKe V2C is RV32EC @@ -77,6 +84,20 @@ pub fn init(dep: *std.Build.Dependency) Self { .abi = .eabi, }; + const qingkev4f = .{ + .cpu_arch = .riscv32, + .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 }, + // generic_rv32 has feature I. + .cpu_features_add = std.Target.riscv.featureSet(&.{ + std.Target.riscv.Feature.c, + std.Target.riscv.Feature.a, + std.Target.riscv.Feature.m, + std.Target.riscv.Feature.f, + }), + .os_tag = .freestanding, + .abi = .eabi, + }; + const chip_ch32v003x4: microzig.Target = .{ .dep = dep, .preferred_binary_format = .bin, @@ -168,6 +189,30 @@ pub fn init(dep: *std.Build.Dependency) Self { .hal = hal_ch32v203, }; + const chip_ch32v307xc = microzig.Target{ + .dep = dep, + .preferred_binary_format = .bin, + .chip = .{ + .name = "CH32V30xxx", // from SVD + .cpu = qingkev4f, + .cpu_module_file = b.path("src/cpus/qingkev4-rv32imac.zig"), + .memory_regions = &.{ + // FLASH + RAM supports the following configuration + // FLASH-192K + RAM-128K + // FLASH-224K + RAM-96K + // FLASH-256K + RAM-64K + // FLASH-288K + RAM-32K + // FLASH-128K + RAM-192K + .{ .offset = 0x08000000, .length = 128 * KiB, .kind = .flash }, + .{ .offset = 0x20000000, .length = 32 * KiB, .kind = .ram }, + }, + .register_definition = .{ + .svd = b.path("src/chips/ch32v30x.svd"), + }, + }, + .hal = hal_ch32v307, + }; + const board_ch32v003f4p6_r0_1v1 = chip_ch32v003x4.derive(.{ .board = .{ .name = "WCH CH32V003F4P6-R0-1v1", @@ -192,6 +237,14 @@ pub fn init(dep: *std.Build.Dependency) Self { }, }); + const board_ch32v307v_r1_1v0 = chip_ch32v307xc.derive(.{ + .board = .{ + .name = "WCH CH32V307V-R1-1V0", + .url = "https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0", + .root_source_file = b.path("src/boards/CH32V307V-R1-1v0.zig"), + }, + }); + return .{ .chips = .{ .ch32v003x4 = chip_ch32v003x4.derive(.{}), @@ -199,6 +252,7 @@ pub fn init(dep: *std.Build.Dependency) Self { .ch32v103x8 = chip_ch32v103x8.derive(.{}), .ch32v203x6 = chip_ch32v203x6.derive(.{}), .ch32v203x8 = chip_ch32v203x8.derive(.{}), + .ch32v307xc = chip_ch32v307xc.derive(.{}), }, .boards = .{ @@ -211,6 +265,9 @@ pub fn init(dep: *std.Build.Dependency) Self { .ch32v203 = .{ .suzuduino_uno_v1b = board_suzuduino_uno_v1b, }, + .ch32v307 = .{ + .ch32v307v_r1_1v0 = board_ch32v307v_r1_1v0, + }, }, }; } diff --git a/port/wch/ch32v/src/boards/CH32V307V-R1-1v0.zig b/port/wch/ch32v/src/boards/CH32V307V-R1-1v0.zig new file mode 100644 index 00000000..406d4e3a --- /dev/null +++ b/port/wch/ch32v/src/boards/CH32V307V-R1-1v0.zig @@ -0,0 +1,6 @@ +// CH32V307V_MINI +// CH32V307 +pub const chip = @import("chip"); +pub const micro = @import("microzig"); + +pub const cpu_frequency = 8_000_000; // 8 MHz diff --git a/port/wch/ch32v/src/chips/ch32v30x.svd b/port/wch/ch32v/src/chips/ch32v30x.svd new file mode 100644 index 00000000..37388af5 --- /dev/null +++ b/port/wch/ch32v/src/chips/ch32v30x.svd @@ -0,0 +1,40051 @@ + + + WCH Ltd. + WCH + CH32V30xxx + 1.0 + CH32V30xxx View File + + QINGKEV4 + r0p0 + little + false + false + 2 + + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + RNG + Random number generator + RNG + 0x40023C00 + + 0x0 + 0x400 + registers + + + RNG + RNG interrupt + 63 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator + enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt + status + 6 + 1 + read-write + + + CEIS + Clock error interrupt + status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + USB + Universal serial bus full-speed device + interface + USB + 0x40005C00 + + 0x0 + 0x400 + registers + + + USBWakeUp + USB Device WakeUp from suspend through EXTI Line Interrupt + 58 + + + + EP0R + EP0R + endpoint 0 register + 0x0 + 0x10 + read-write + 0x0000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP1R + EP1R + endpoint 1 register + 0x4 + 0x10 + read-write + 0x0000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP2R + EP2R + endpoint 2 register + 0x8 + 0x10 + read-write + 0x0000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP3R + EP3R + endpoint 3 register + 0xC + 0x10 + read-write + 0x0000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP4R + EP4R + endpoint 4 register + 0x10 + 0x10 + read-write + 0x0000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP5R + EP5R + endpoint 5 register + 0x14 + 0x10 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP6R + EP6R + endpoint 6 register + 0x18 + 0x10 + read-write + 0x0000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP7R + EP7R + endpoint 7 register + 0x1C + 0x10 + read-write + 0x0000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + CNTR + USB_CNTR + control register + 0x40 + 0x10 + read-write + 0x0003 + + + FRES + Force USB Reset + 0 + 1 + + + PDWN + Power down + 1 + 1 + + + LPMODE + Low-power mode + 2 + 1 + + + FSUSP + Force suspend + 3 + 1 + + + RESUME + Resume request + 4 + 1 + + + ESOFM + Expected start of frame interrupt + mask + 8 + 1 + + + SOFM + Start of frame interrupt + mask + 9 + 1 + + + RESETM + USB reset interrupt mask + 10 + 1 + + + SUSPM + Suspend mode interrupt + mask + 11 + 1 + + + WKUPM + Wakeup interrupt mask + 12 + 1 + + + ERRM + Error interrupt mask + 13 + 1 + + + PMAOVRM + Packet memory area over / underrun + interrupt mask + 14 + 1 + + + CTRM + Correct transfer interrupt + mask + 15 + 1 + + + + + ISTR + ISTR + interrupt status register + 0x44 + 0x10 + read-write + 0x0000 + + + EP_ID + Endpoint Identifier + 0 + 4 + + + DIR + Direction of transaction + 4 + 1 + + + ESOF + Expected start frame + 8 + 1 + + + SOF + start of frame + 9 + 1 + + + RESET + reset request + 10 + 1 + + + SUSP + Suspend mode request + 11 + 1 + + + WKUP + Wakeup + 12 + 1 + + + ERR + Error + 13 + 1 + + + PMAOVR + Packet memory area over / + underrun + 14 + 1 + + + CTR + Correct transfer + 15 + 1 + + + + + FNR + FNR + frame number register + 0x48 + 0x10 + read-only + 0x0000 + + + FN + Frame number + 0 + 11 + + + LSOF + Lost SOF + 11 + 2 + + + LCK + Locked + 13 + 1 + + + RXDM + Receive data - line status + 14 + 1 + + + RXDP + Receive data + line status + 15 + 1 + + + + + DADDR + DADDR + device address + 0x4C + 0x10 + read-write + 0x0000 + + + ADD + Device address + 0 + 7 + + + EF + Enable function + 7 + 1 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTABLE + Buffer table + 3 + 13 + + + + + + + CAN1 + Controller area network + CAN1 + 0x40006400 + + 0x0 + 0x400 + registers + + + USB_HP_CAN1_TX + CAN1 TX interrupts + 35 + + + USB_LP_CAN1_RX0 + CAN1 RX0 interrupts + 36 + + + CAN1_RX1 + CAN1 RX1 interrupt + 37 + + + CAN1_SCE + CAN1 SCE interrupt + 38 + + + + CTLR + CTLR + CAN Master control register + 0x0 + 0x20 + read-write + 0x00010002 + + + DBF + Debug freeze + 16 + 1 + read-write + + + RESET + Software master reset + 15 + 1 + read-write + + + TTCM + Time triggered communication mode + 7 + 1 + read-write + + + ABOM + Automatic bus-off management + 6 + 1 + read-write + + + AWUM + Automatic wakeup mode + 5 + 1 + read-write + + + NART + No automatic retransmission + 4 + 1 + read-write + + + RFLM + Receive FIFO locked mode + 3 + 1 + read-write + + + TXFP + Transmit FIFO priority + 2 + 1 + read-write + + + SLEEP + Sleep mode request + 1 + 1 + read-write + + + INRQ + Initialization request + 0 + 1 + read-write + + + + + STATR + STATR + CAN master status register + 0x4 + 0x20 + 0x00000C02 + + + RX + Rx signal + 11 + 1 + read-only + + + SAMP + Last sample point + 10 + 1 + read-only + + + RXM + Receive mode + 9 + 1 + read-only + + + TXM + Transmit mode + 8 + 1 + read-only + + + SLAKI + Sleep acknowledge interrupt + 4 + 1 + read-write + + + WKUI + Wakeup interrupt + 3 + 1 + read-write + + + ERRI + Error interrupt + 2 + 1 + read-write + + + SLAK + Sleep acknowledge + 1 + 1 + read-only + + + INAK + Initialization acknowledge + 0 + 1 + read-only + + + + + TSTATR + TSTATR + CAN transmit status register + 0x8 + 0x20 + 0x1C000000 + + + LOW2 + Lowest priority flag for mailbox + 2 + 31 + 1 + read-only + + + LOW1 + Lowest priority flag for mailbox + 1 + 30 + 1 + read-only + + + LOW0 + Lowest priority flag for mailbox + 0 + 29 + 1 + read-only + + + TME2 + Transmit mailbox 2 empty + 28 + 1 + read-only + + + TME1 + Transmit mailbox 1 empty + 27 + 1 + read-only + + + TME0 + Transmit mailbox 0 empty + 26 + 1 + read-only + + + CODE + Mailbox code + 24 + 2 + read-only + + + ABRQ2 + Abort request for mailbox 2 + 23 + 1 + read-write + + + TERR2 + Transmission error of mailbox 2 + 19 + 1 + read-write + + + ALST2 + Arbitration lost for mailbox 2 + 18 + 1 + read-write + + + TXOK2 + Transmission OK of mailbox 2 + 17 + 1 + read-write + + + RQCP2 + Request completed mailbox2 + 16 + 1 + read-write + + + ABRQ1 + Abort request for mailbox 1 + 15 + 1 + read-write + + + TERR1 + Transmission error of mailbox1 + 11 + 1 + read-write + + + ALST1 + Arbitration lost for mailbox1 + 10 + 1 + read-write + + + TXOK1 + Transmission OK of mailbox1 + 9 + 1 + read-write + + + RQCP1 + Request completed mailbox1 + 8 + 1 + read-write + + + ABRQ0 + Abort request for mailbox0 + 7 + 1 + read-write + + + TERR0 + Transmission error of mailbox0 + 3 + 1 + read-write + + + ALST0 + Arbitration lost for mailbox0 + 2 + 1 + read-write + + + TXOK0 + Transmission OK of mailbox0 + 1 + 1 + read-write + + + RQCP0 + Request completed mailbox0 + 0 + 1 + read-write + + + + + RFIFO0 + RFIFO0 + CAN receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RFOM0 + Release FIFO 0 output mailbox + 5 + 1 + read-write + + + FOVR0 + FIFO 0 overrun + 4 + 1 + read-write + + + FULL0 + FIFO 0 full + 3 + 1 + read-write + + + FMP0 + FIFO 0 message pending + 0 + 2 + read-only + + + + + RFIFO1 + RFIFO1 + CAN receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RFOM1 + Release FIFO 1 output mailbox + 5 + 1 + read-write + + + FOVR1 + FIFO 1 overrun + 4 + 1 + read-write + + + FULL1 + FIFO 1 full + 3 + 1 + read-write + + + FMP1 + FIFO 1 message pending + 0 + 2 + read-only + + + + + INTENR + INTENR + CAN interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLKIE + Sleep interrupt + enable + 17 + 1 + read-write + + + WKUIE + Wakeup interrupt + enable + 16 + 1 + read-write + + + ERRIE + Error interrupt + enable + 15 + 1 + read-write + + + LECIE + Last error code interrupt + enable + 11 + 1 + read-write + + + BOFIE + Bus-off interrupt + enable + 10 + 1 + read-write + + + EPVIE + Error passive interrupt + enable + 9 + 1 + read-write + + + EWGIE + Error warning interrupt + enable + 8 + 1 + read-write + + + FOVIE1 + FIFO overrun interrupt + enable + 6 + 1 + read-write + + + FFIE1 + FIFO full interrupt + enable + 5 + 1 + read-write + + + FMPIE1 + FIFO message pending interrupt + enable + 4 + 1 + read-write + + + FOVIE0 + FIFO overrun interrupt + enable + 3 + 1 + read-write + + + FFIE0 + FIFO full interrupt + enable + 2 + 1 + read-write + + + FMPIE0 + FIFO message pending interrupt + enable + 1 + 1 + read-write + + + TMEIE + Transmit mailbox empty interrupt + enable + 0 + 1 + read-write + + + + + ERRSR + ERRSR + CAN error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Least significant byte of the 9-bit + transmit error counter + 16 + 8 + read-only + + + LEC + Last error code + 4 + 3 + read-write + + + BOFF + Bus-off + flag + 2 + 1 + read-only + + + EPVF + Error passive + flag + 1 + 1 + read-only + + + EWGF + Error warning + flag + 0 + 1 + read-only + + + + + BTIMR + BTIMR + CAN bit timing register + 0x1C + 0x20 + read-write + 0x01230000 + + + SILM + Silent mode (debug) + 31 + 1 + read-write + + + LBKM + Loop back mode (debug) + 30 + 1 + read-write + + + SJW + Resynchronization jump width + 24 + 2 + read-write + + + TS2 + Time segment 2 + 20 + 3 + read-write + + + TS1 + Time segment 1 + 16 + 4 + read-write + + + BRP + Baud rate prescaler + 0 + 10 + read-write + + + + + TXMIR0 + TXMIR0 + CAN TX mailbox identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + STID + Standard identifier + 21 + 11 + read-write + + + EXID + extended identifier + 3 + 18 + read-write + + + IDE + Identifier extension + 2 + 1 + read-write + + + RTR + Remote transmission request + 1 + 1 + read-write + + + TXRQ + Transmit mailbox request + 0 + 1 + read-write + + + + + TXMDTR0 + TXMDTR0 + CAN mailbox data length control and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-write + + + TGT + Transmit global time + 8 + 1 + read-write + + + DLC + Data length code + 0 + 4 + read-write + + + + + TXMDLR0 + TXMDLR0 + CAN mailbox data low register + 0x188 + 0x20 + read-write + 0x00000000 + + + DATA3 + Data byte 3 + 24 + 8 + read-write + + + DATA2 + Data byte 2 + 16 + 8 + read-write + + + DATA1 + Data byte 1 + 8 + 8 + read-write + + + DATA0 + Data byte 0 + 0 + 8 + read-write + + + + + TXMDHR0 + TXMDHR0 + CAN mailbox data high register + 0x18C + 0x20 + read-write + 0x00000000 + + + DATA7 + Data byte 7 + 24 + 8 + read-write + + + DATA6 + Data byte 6 + 16 + 8 + read-write + + + DATA5 + Data byte 5 + 8 + 8 + read-write + + + DATA4 + Data byte 4 + 0 + 8 + read-write + + + + + TXMIR1 + TXMIR1 + CAN TX mailbox identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + STID + Standard identifier + 21 + 11 + read-write + + + EXID + extended identifier + 3 + 18 + read-write + + + IDE + Identifier extension + 2 + 1 + read-write + + + RTR + Remote transmission request + 1 + 1 + read-write + + + TXRQ + Transmit mailbox request + 0 + 1 + read-write + + + + + TXMDTR1 + TXMDTR1 + CAN mailbox data length control and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-write + + + TGT + Transmit global time + 8 + 1 + read-write + + + DLC + Data length code + 0 + 4 + read-write + + + + + TXMDLR1 + TXMDLR1 + CAN mailbox data low register + 0x198 + 0x20 + read-write + 0x00000000 + + + DATA3 + Data byte 3 + 24 + 8 + read-write + + + DATA2 + Data byte 2 + 16 + 8 + read-write + + + DATA1 + Data byte 1 + 8 + 8 + read-write + + + DATA0 + Data byte 0 + 0 + 8 + read-write + + + + + TXMDHR1 + TXMDHR1 + CAN mailbox data high register + 0x19C + 0x20 + read-write + 0x00000000 + + + DATA7 + Data byte 7 + 24 + 8 + read-write + + + DATA6 + Data byte 6 + 16 + 8 + read-write + + + DATA5 + Data byte 5 + 8 + 8 + read-write + + + DATA4 + Data byte 4 + 0 + 8 + read-write + + + + + TXMIR2 + TXMIR2 + CAN TX mailbox identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + STID + Standard identifier + 21 + 11 + read-write + + + EXID + extended identifier + 3 + 18 + read-write + + + IDE + Identifier extension + 2 + 1 + read-write + + + RTR + Remote transmission request + 1 + 1 + read-write + + + TXRQ + Transmit mailbox request + 0 + 1 + read-write + + + + + TXMDTR2 + TXMDTR2 + CAN mailbox data length control and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-write + + + TGT + Transmit global time + 8 + 1 + read-write + + + DLC + Data length code + 0 + 4 + read-write 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+ MMCTGFCR + Ethernet MMC transmitted good frames counter + register + 0x68 + 0x20 + read-only + 0x00000000 + + + TGFC + Transmitted good frames + counter + 0 + 32 + + + + + MMCRFCECR + MMCRFCECR + Ethernet MMC received frames with CRC error + counter register + 0x94 + 0x20 + read-only + 0x00000000 + + + RFCFC + Received frames with CRC error + counter + 0 + 32 + + + + + MMCRFAECR + MMCRFAECR + Ethernet MMC received frames with alignment + error counter register + 0x98 + 0x20 + read-only + 0x00000000 + + + RFAEC + Received frames with alignment error + counter + 0 + 32 + + + + + MMCRGUFCR + MMCRGUFCR + MMC received good unicast frames counter + register + 0xC4 + 0x20 + read-only + 0x00000000 + + + RGUFC + Received good unicast frames + counter + 0 + 32 + + + + + + + ETHERNET_PTP + Ethernet: Precision time protocol + ETHERNET + 0x40028700 + + 0x0 + 0x400 + registers + + + + PTPTSCR + PTPTSCR + Ethernet PTP time stamp control register + (ETH_PTPTSCR) + 0x0 + 0x20 + read-write + 0x00000000 + + + TSE + Time stamp enable + 0 + 1 + + + TSFCU + Time stamp fine or coarse + update + 1 + 1 + + + TSSTI + Time stamp system time + initialize + 2 + 1 + + + TSSTU + Time stamp system time + update + 3 + 1 + + + TSITE + Time stamp interrupt trigger + enable + 4 + 1 + + + TSARU + Time stamp addend register + update + 5 + 1 + + + + + PTPSSIR + PTPSSIR + Ethernet PTP subsecond increment + register + 0x4 + 0x20 + read-write + 0x00000000 + + + STSSI + System time subsecond + increment + 0 + 8 + + + + + PTPTSHR + PTPTSHR + Ethernet PTP time stamp high + register + 0x8 + 0x20 + read-only + 0x00000000 + + + STS + System time second + 0 + 32 + + + + + PTPTSLR + PTPTSLR + Ethernet PTP time stamp low register + (ETH_PTPTSLR) + 0xC + 0x20 + read-only + 0x00000000 + + + STSS + System time subseconds + 0 + 31 + + + STPNS + System time positive or negative + sign + 31 + 1 + + + + + PTPTSHUR + PTPTSHUR + Ethernet PTP time stamp high update + register + 0x10 + 0x20 + read-write + 0x00000000 + + + TSUS + Time stamp update second + 0 + 32 + + + + + PTPTSLUR + PTPTSLUR + Ethernet PTP time stamp low update register + (ETH_PTPTSLUR) + 0x14 + 0x20 + read-write + 0x00000000 + + + TSUSS + Time stamp update + subseconds + 0 + 31 + + + TSUPNS + Time stamp update positive or negative + sign + 31 + 1 + + + + + PTPTSAR + PTPTSAR + Ethernet PTP time stamp addend + register + 0x18 + 0x20 + read-write + 0x00000000 + + + TSA + Time stamp addend + 0 + 32 + + + + + PTPTTHR + PTPTTHR + Ethernet PTP target time high + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TTSH + Target time stamp high + 0 + 32 + + + + + PTPTTLR + PTPTTLR + Ethernet PTP target time low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + TTSL + Target time stamp low + 0 + 32 + + + + + + + ETHERNET_DMA + Ethernet: DMA controller operation + ETHERNET + 0x40029000 + + 0x0 + 0x400 + registers + + + + DMABMR + DMABMR + Ethernet DMA bus mode register + 0x0 + 0x20 + read-write + 0x00002101 + + + SR + Software reset + 0 + 1 + + + DA + DMA Arbitration + 1 + 1 + + + DSL + Descriptor skip length + 2 + 5 + + + PBL + Programmable burst length + 8 + 6 + + + RTPR + Rx Tx priority ratio + 14 + 2 + + + FB + Fixed burst + 16 + 1 + + + RDP + Rx DMA PBL + 17 + 6 + + + USP + Use separate PBL + 23 + 1 + + + FPM + 4xPBL mode + 24 + 1 + + + AAB + Address-aligned beats + 25 + 1 + + + + + DMATPDR + DMATPDR + Ethernet DMA transmit poll demand + register + 0x4 + 0x20 + read-write + 0x00000000 + + + TPD + Transmit poll demand + 0 + 32 + + + + + DMARPDR + DMARPDR + EHERNET DMA receive poll demand + register + 0x8 + 0x20 + read-write + 0x00000000 + + + RPD + Receive poll demand + 0 + 32 + + + + + DMARDLAR + DMARDLAR + Ethernet DMA receive descriptor list address + register + 0xC + 0x20 + read-write + 0x00000000 + + + SRL + Start of receive list + 0 + 32 + + + + + DMATDLAR + DMATDLAR + Ethernet DMA transmit descriptor list + address register + 0x10 + 0x20 + read-write + 0x00000000 + + + STL + Start of transmit list + 0 + 32 + + + + + DMASR + DMASR + Ethernet DMA status register + 0x14 + 0x20 + 0x00000000 + + + TS + Transmit status + 0 + 1 + read-write + + + TPSS + Transmit process stopped + status + 1 + 1 + read-write + + + TBUS + Transmit buffer unavailable + status + 2 + 1 + read-write + + + TJTS + Transmit jabber timeout + status + 3 + 1 + read-write + + + ROS + Receive overflow status + 4 + 1 + read-write + + + TUS + Transmit underflow status + 5 + 1 + read-write + + + RS + Receive status + 6 + 1 + read-write + + + RBUS + Receive buffer unavailable + status + 7 + 1 + read-write + + + RPSS + Receive process stopped + status + 8 + 1 + read-write + + + PWTS + Receive watchdog timeout + status + 9 + 1 + read-write + + + ETS + Early transmit status + 10 + 1 + read-write + + + FBES + Fatal bus error status + 13 + 1 + read-write + + + ERS + Early receive status + 14 + 1 + read-write + + + AIS + Abnormal interrupt summary + 15 + 1 + read-write + + + NIS + Normal interrupt summary + 16 + 1 + read-write + + + RPS + Receive process state + 17 + 3 + read-only + + + TPS + Transmit process state + 20 + 3 + read-only + + + EBS + Error bits status + 23 + 3 + read-only + + + MMCS + MMC status + 27 + 1 + read-only + + + PMTS + PMT status + 28 + 1 + read-only + + + TSTS + Time stamp trigger status + 29 + 1 + read-only + + + IPLS + 10MPHY Physical layer variation + 31 + 1 + read-only + + + + + DMAOMR + DMAOMR + Ethernet DMA operation mode + register + 0x18 + 0x20 + read-write + 0x00000000 + + + SR + SR + 1 + 1 + + + OSF + OSF + 2 + 1 + + + RTC + RTC + 3 + 2 + + + FUGF + FUGF + 6 + 1 + + + FEF + FEF + 7 + 1 + + + ST + ST + 13 + 1 + + + TTC + TTC + 14 + 3 + + + FTF + FTF + 20 + 1 + + + TSF + TSF + 21 + 1 + + + DFRF + DFRF + 24 + 1 + + + RSF + RSF + 25 + 1 + + + DTCEFD + DTCEFD + 26 + 1 + + + + + DMAIER + DMAIER + Ethernet DMA interrupt enable + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + Transmit interrupt enable + 0 + 1 + + + TPSIE + Transmit process stopped interrupt + enable + 1 + 1 + + + TBUIE + Transmit buffer unavailable interrupt + enable + 2 + 1 + + + TJTIE + Transmit jabber timeout interrupt + enable + 3 + 1 + + + ROIE + Overflow interrupt enable + 4 + 1 + + + TUIE + Underflow interrupt enable + 5 + 1 + + + RIE + Receive interrupt enable + 6 + 1 + + + RBUIE + Receive buffer unavailable interrupt + enable + 7 + 1 + + + RPSIE + Receive process stopped interrupt + enable + 8 + 1 + + + RWTIE + receive watchdog timeout interrupt + enable + 9 + 1 + + + ETIE + Early transmit interrupt + enable + 10 + 1 + + + FBEIE + Fatal bus error interrupt + enable + 13 + 1 + + + ERIE + Early receive interrupt + enable + 14 + 1 + + + AISE + Abnormal interrupt summary + enable + 15 + 1 + + + NISE + Normal interrupt summary + enable + 16 + 1 + + + IPLE + 10M Physical layer connection + 31 + 1 + + + + + DMAMFBOCR + DMAMFBOCR + Ethernet DMA missed frame and buffer + overflow counter register + 0x20 + 0x20 + read-only + 0x00000000 + + + MFC + Missed frames by the + controller + 0 + 16 + + + OMFC + Overflow bit for missed frame + counter + 16 + 1 + + + MFA + Missed frames by the + application + 17 + 11 + + + OFOC + Overflow bit for FIFO overflow + counter + 28 + 1 + + + + + DMACHTDR + DMACHTDR + Ethernet DMA current host transmit + descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + Host transmit descriptor address + pointer + 0 + 32 + + + + + DMACHRDR + DMACHRDR + Ethernet DMA current host receive descriptor + register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + Host receive descriptor address + pointer + 0 + 32 + + + + + DMACHTBAR + DMACHTBAR + Ethernet DMA current host transmit buffer + address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + Host transmit buffer address + pointer + 0 + 32 + + + + + DMACHRBAR + DMACHRBAR + Ethernet DMA current host receive buffer + address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + Host receive buffer address + pointer + 0 + 32 + + + + + + + SDIO + Secure digital input/output + interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO + SDIO global interrupt + 65 + + + + POWER + POWER + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + Power supply control bits + 0 + 2 + + + + + CLKCR + CLKCR + SDI clock control register + (SDIO_CLKCR) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock divide factor + 0 + 8 + + + CLKEN + Clock enable bit + 8 + 1 + + + PWRSAV + Power saving configuration + bit + 9 + 1 + + + BYPASS + Clock divider bypass enable + bit + 10 + 1 + + + WIDBUS + Wide bus mode enable bit + 11 + 2 + + + NEGEDGE + SDIO_CK dephasing selection + bit + 13 + 1 + + + HWFC_EN + HW Flow Control enable + 14 + 1 + + + + + ARG + ARG + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + + + CMD + CMD + SDIO command register + (SDIO_CMD) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDINDEX + Command index + 0 + 6 + + + WAITRESP + Wait for response bits + 6 + 2 + + + WAITINT + CPSM waits for interrupt request + 8 + 1 + + + WAITPEND + CPSM Waits for ends of data transfer (CmdPend internal signal) + 9 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable bit + 10 + 1 + + + SDIOSuspend + SD I/O suspend command + 11 + 1 + + + ENCMDcompl + Enable CMD completion + 12 + 1 + + + nIEN + not Interrupt Enable + 13 + 1 + + + CE_ATACMD + CE-ATA command + 14 + 1 + + + + + RESPCMD + RESPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + Response command index + 0 + 6 + + + + + RESP1 + RESP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + Card status 1 + 0 + 32 + + + + + RESP2 + RESP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + Card status 2 + 0 + 32 + + + + + RESP3 + RESP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + Card status 3 + 0 + 32 + + + + + RESP4 + RESP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + Card status 4 + 0 + 32 + + + + + DTIMER + DTIMER + Bits 31:0 = DATATIME: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data timeout period + 0 + 32 + + + + + DLEN + DLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + + + DCTRL + DCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + DTEN + Data transfer enabled bit + 0 + 1 + + + DTDIR + Data transfer direction selection + 1 + 1 + + + DTMODE + Data transfer mode selection 1: Stream or + SDIO multibyte data transfer + 2 + 1 + + + DMAEN + DMA enable bit + 3 + 1 + + + DBLOCKSIZE + Data block size + 4 + 4 + + + PWSTART + Read wait start + 8 + 1 + + + PWSTOP + Read wait stop + 9 + 1 + + + RWMOD + Read wait mode + 10 + 1 + + + SDIOEN + SD I/O enable functions + 11 + 1 + + + + + DCOUNT + DCOUNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + + + STA + STA + SDIO status register + (SDIO_STA) + 0x34 + 0x20 + read-only + 0x00000000 + + + CCRCFAIL + Command response received (CRC check failed) + 0 + 1 + + + DCRCFAIL + Data block sent/received (CRC check failed) + 1 + 1 + + + CTIMEOUT + Command response timeout + 2 + 1 + + + DTIMEOUT + Data timeout + 3 + 1 + + + TXUNDERR + Transmit FIFO underrun error + 4 + 1 + + + RXOVERR + Received FIFO overrun error + 5 + 1 + + + CMDREND + Command response received (CRC check passed) + 6 + 1 + + + CMDSENT + Command sent (no response required) + 7 + 1 + + + DATAEND + Data end (data counter, SDIDCOUNT, is zero) + 8 + 1 + + + STBITERR + Start bit not detected on all data signals in wide bus mode + 9 + 1 + + + DBCKEND + Data block sent/received (CRC check passed) + 10 + 1 + + + CMDACT + Command transfer in progress + 11 + 1 + + + TXACT + Data transmit in progress + 12 + 1 + + + RXACT + Data receive in progress + 13 + 1 + + + TXFIFOHE + Transmit FIFO half empty: at least 8 words can be written into the + FIFO + 14 + 1 + + + RXFIFOHF + Receive FIFO half full: there are at least 8 words in the + FIFO + 15 + 1 + + + TXFIFOF + Transmit FIFO full + 16 + 1 + + + RXFIFOF + Receive FIFO full + 17 + 1 + + + TXFIFOE + Transmit FIFO empty + 18 + 1 + + + RXFIFOE + Receive FIFO empty + 19 + 1 + + + TXDAVL + Data available in transmit FIFO + 20 + 1 + + + RXDAVL + Data available in receive FIFO + 21 + 1 + + + SDIOIT + SDIO interrupt received + 22 + 1 + + + CEATAEND + CE-ATA command completion signal received for CMD61 + 23 + 1 + + + + + ICR + ICR + SDIO interrupt clear register + (SDIO_ICR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CCRCFAILC + CCRCFAIL flag clear bit + 0 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit + 1 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit + 2 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit + 3 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit + 4 + 1 + + + RXOVERRC + RXOVERR flag clear bit + 5 + 1 + + + CMDRENDC + CMDREND flag clear bit + 6 + 1 + + + CMDSENTC + CMDSENT flag clear bit + 7 + 1 + + + DATAENDC + DATAEND flag clear bit + 8 + 1 + + + STBITERRC + STBITERR flag clear bit + 9 + 1 + + + DBCKENDC + DBCKEND flag clear bit + 10 + 1 + + + SDIOITC + SDIOIT flag clear bit + 22 + 1 + + + CEATAENDC + CEATAEND flag clear bit + 23 + 1 + + + + + MASK + MASK + SDIO mask register (SDIO_MASK) + 0x3C + 0x20 + read-write + 0x00000000 + + + CCRCFAILIE + Command CRC fail interrupt + enable + 0 + 1 + + + DCRCFAILIE + Data CRC fail interrupt + enable + 1 + 1 + + + CTIMEOUTIE + Command timeout interrupt + enable + 2 + 1 + + + DTIMEOUTIE + Data timeout interrupt + enable + 3 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt + enable + 4 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt + enable + 5 + 1 + + + CMDRENDIE + Command response received interrupt + enable + 6 + 1 + + + CMDSENTIE + Command sent interrupt + enable + 7 + 1 + + + DATAENDIE + Data end interrupt + enable + 8 + 1 + + + STBITERRIE + Start bit error interrupt + enable + 9 + 1 + + + DBACKENDIE + Data block end interrupt + enable + 10 + 1 + + + CMDACTIE + Command acting interrupt + enable + 11 + 1 + + + TXACTIE + Data transmit acting interrupt + enable + 12 + 1 + + + RXACTIE + Data receive acting interrupt + enable + 13 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt + enable + 14 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt + enable + 15 + 1 + + + TXFIFOFIE + Tx FIFO full interrupt + enable + 16 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt + enable + 17 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt + enable + 18 + 1 + + + RXFIFOEIE + Rx FIFO empty interrupt + enable + 19 + 1 + + + TXDAVLIE + Data available in Tx FIFO interrupt + enable + 20 + 1 + + + RXDAVLIE + Data available in Rx FIFO interrupt + enable + 21 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt + enable + 22 + 1 + + + CEATENDIE + CE-ATA command completion signal received interrupt + enable + 23 + 1 + + + + + FIFOCNT + FIFOCNT + Bits 23:0 = FIFOCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + FIF0COUNT + Remaining number of words to be written to or read from the + FIFO + 0 + 32 + + + + + FIFO + FIFO + bits 31:0 = FIFOData: Receive and transmit + FIFO data + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFOData + Receive and transmit FIFO data + 0 + 32 + + + + + + + FSMC + Flexible static memory controller + FSMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + FSMC + FSMC global interrupt + 64 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + Write burst enable + 19 + 1 + read-write + + + ASYNCWAIT + Wait signal during asynchronous transfers + 15 + 1 + read-write + + + EXTMOD + Extended mode enable + 14 + 1 + read-write + + + WAITEN + Wait enable bit + 13 + 1 + read-write + + + WREN + Write enable bit + 12 + 1 + read-write + + + WAITCFG + Wait timing configuration + 11 + 1 + read-write + + + WRAPMOD + Wrapped burst mode support + 10 + 1 + read-write + + + WAITPOL + Wait signal polarity bit + 9 + 1 + read-write + + + BURSTEN + Burst enable bit + 8 + 1 + read-write + + + FACCEN + Flash access enable + 6 + 1 + read-write + + + MWID + Memory databus width + 4 + 2 + read-write + + + MTYP + Memory type + 2 + 2 + read-write + + + MUXEN + Address/data multiplexing enable bit + 1 + 1 + read-write + + + MBKEN + Memory bank enable bit + 0 + 1 + read-write + + + + + BTR1 + BTR1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + Access mode + 28 + 2 + read-write + + + DATLAT + Data latency for synchronous NOR Flash memory + 24 + 4 + read-write + + + CLKDIV + Clock divide ratio (for FSMC_CLK signal) + 20 + 4 + read-write + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + read-write + + + DATAST + Data-phase duration + 8 + 8 + read-write + + + ADDHLD + Address-hold phase duration + 4 + 4 + read-write + + + ADDSET + Address setup phase duration + 0 + 4 + read-write + + + + + PCR2 + PCR2 + PC Card/NAND Flash control register + 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECC page size + 17 + 3 + + + TAR + ALE to RE delay + 13 + 4 + + + TCLR + CLE to RE delay + 9 + 4 + + + ECCEN + ECC computation logic enable bit + 6 + 1 + + + PWID + Databus width + 4 + 2 + + + PTYP + Memory type + 3 + 1 + + + PBKEN + PC Card/NAND Flash memory bank enable bit + 2 + 1 + + + PWAITEN + Wait feature enable bit + 1 + 1 + + + + + SR2 + SR2 + FIFO status and interrupt register + 2 + 0x64 + 0x20 + 0x00000040 + + + FEMPT + FIFO empty + 6 + 1 + read-only + + + IFEN + Interrupt falling edge detection enable bit + 5 + 1 + read-write + + + ILEN + Interrupt high-level detection enable bit + 4 + 1 + read-write + + + IREN + Interrupt rising edge detection enable bit + 3 + 1 + read-write + + + IFS + Interrupt falling edge status + 2 + 1 + read-write + + + ILS + Interrupt high-level status + 1 + 1 + read-write + + + IRS + Interrupt rising edge status + 0 + 1 + read-write + + + + + PMEM2 + PMEM2 + Common memory space timing register + 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + Common memory x databus HiZ + time + 24 + 8 + + + MEMHOLDx + Common memory x hold + time + 16 + 8 + + + MEMWAITx + Common memory x wait + time + 8 + 8 + + + MEMSETx + Common memory x setup + time + 0 + 8 + + + + + PATT2 + PATT2 + Attribute memory space timing register + 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + Attribute memory x databus HiZ + time + 24 + 8 + + + ATTHOLDx + Attribute memory x hold + time + 16 + 8 + + + ATTWAITx + Attribute memory x wait + time + 8 + 8 + + + ATTSETx + Attribute memory x setup + time + 0 + 8 + + + + + ECCR2 + ECCR2 + ECC result register 2 + 0x74 + 0x20 + read-only + 0x00000000 + + + ECCx + ECC result + 0 + 32 + + + + + BWTR1 + BWTR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + Access mode + 28 + 2 + + + DATLAT + Data latency for synchronous NOR Flash memory + 24 + 4 + + + CLKDIV + Clock divide ratio (for FSMC_CLK signal) + 20 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + ADDSET + Address setup phase duration + 0 + 4 + + + + + + + DVP + Digital Video Port + DVP + 0x50050000 + + 0x0 + 0x400 + registers + + + DVP + DVP global Interrupt + interrupt + 86 + + + + CR0 + CR0 + Digital Video control register + (DVP_CR0) + 0x00 + 0x08 + read-write + 0x00 + + + RB_DVP_ENABLE + DVP enable + 0 + 1 + read-write + + + RB_DVP_V_POLAR + DVP VSYNC polarity control + 1 + 1 + read-write + + + RB_DVP_H_POLAR + DVP HSYNC polarity control + 2 + 1 + read-write + + + RB_DVP_P_POLAR + DVP PCLK polarity control + 3 + 1 + read-write + + + RB_DVP_MSK_DAT_MOD + DVP data mode + 4 + 2 + + + RB_DVP_JPEG + DVP JPEG mode + 6 + 1 + read-write + + + + + CR1 + CR1 + Digital Video control register + (DVP_CR1) + 0x01 + 0x08 + read-write + 0x06 + + + RB_DVP_DMA_EN + DVP dma enable + 0 + 1 + read-write + + + RB_DVP_ALL_CLR + DVP all clear + 1 + 1 + read-write + + + RB_DVP_RCV_CLR + DVP receive logic clear + 2 + 1 + read-write + + + RB_DVP_BUF_TOG + DVP bug toggle by software + 3 + 1 + read-write + + + RB_DVP_CM + DVP capture mode + 4 + 1 + read-write + + + RB_DVP_CROP + DVP Crop feature enable + 5 + 1 + read-write + + + RB_DVP_FCRC + DVP frame capture rate control + 6 + 2 + read-write + + + + + IER + IER + Digital Video Interrupt register + (DVP_IER) + 0x02 + 0x08 + read-write + 0x00 + + + RB_DVP_IE_STR_FRM + DVP frame start interrupt enable + 0 + 1 + read-write + + + RB_DVP_IE_ROW_DONE + DVP row received done interrupt enable + 1 + 1 + read-write + + + RB_DVP_IE_FRM_DONE + DVP frame received done interrupt enable + 2 + 1 + read-write + + + RB_DVP_IE_FIFO_OV + DVP receive fifo overflow interrupt enable + 3 + 1 + read-write + + + RB_DVP_IE_STP_FRM + DVP frame stop interrupt enable + 4 + 1 + read-write + + + + + ROW_NUM + ROW_NUM + Image line count configuration register + (DVP_ROW_NUM) + 0x04 + 0x10 + read-write + 0x0000 + + + RB_DVP_ROW_NUM + The number of rows of frame image data + 0 + 16 + read-write + + + + + COL_NUM + COL_NUM + Image column number configuration register + (DVP_COL_NUM) + 0x06 + 0x10 + read-write + 0x0000 + + + RB_DVP_COL_NUM + Number of PCLK cycles for row data + 0 + 16 + read-write + + + + + DMA_BUF0 + DMA_BUF0 + Digital Video DMA address register + (DVP_DMA_BUF0) + 0x08 + 0x20 + read-write + 0x00000000 + + + RB_DVP_DMA_BUF0 + DMA receive address 0 + 0 + 17 + read-write + + + + + DMA_BUF1 + DMA_BUF1 + Digital Video DMA address register + (DVP_DMA_BUF1) + 0x0C + 0x20 + read-write + 0x00000000 + + + RB_DVP_DMA_BUF1 + DMA receive address 1 + 0 + 17 + read-write + + + + + IFR + IFR + Digital Video Flag register + (DVP_IFR) + 0x10 + 0x08 + read-write + 0x00 + + + RB_DVP_IF_STR_FRM + DVP frame start interrupt enable + 0 + 1 + read-write + + + RB_DVP_IF_ROW_DONE + DVP row received done interrupt enable + 1 + 1 + read-write + + + RB_DVP_IF_FRM_DONE + DVP frame received done interrupt enable + 2 + 1 + read-write + + + RB_DVP_IF_FIFO_OV + DVP receive fifo overflow interrupt enable + 3 + 1 + read-write + + + RB_DVP_IF_STP_FRM + DVP frame stop interrupt enable + 4 + 1 + read-write + + + + + STATUS + STATUS + Digital Video STATUS register + (DVP_STATUS) + 0x11 + 0x08 + read-only + 0x00 + + + RB_DVP_FIFO_RDY + DVP frame start interrupt enable + 0 + 1 + read-only + + + RB_DVP_FIFO_FULL + DVP row received done interrupt enable + 1 + 1 + read-only + + + RB_DVP_FIFO_OV + DVP frame received done interrupt enable + 2 + 1 + read-only + + + RB_DVP_MSK_FIFO_CNT + DVP receive fifo overflow interrupt enable + 4 + 3 + read-only + + + + + ROW_CNT + ROW_CNT + Digital Video line counter register + (DVP_ROW_CNT) + 0x14 + 0x10 + read-only + 0x0000 + + + RB_DVP_ROW_CNT + The number of rows of frame image data + 0 + 16 + read-only + + + + + HOFFCNT + HOFFCNT + Digital Video horizontal displacement register + (DVP_HOFFCNT) + 0x18 + 0x10 + read-write + 0x0000 + + + RB_DVP_HOFFCNT + Number of PCLK cycles for row data + 0 + 16 + read-write + + + + + VST + VST + Digital Video line number register + (DVP_VST) + 0x1A + 0x10 + read-write + 0x0000 + + + RB_DVP_VST + The number of lines captured by the image + 0 + 16 + read-write + + + + + CAPCNT + CAPCNT + Digital Video Capture count register + (DVP_CAPCNT) + 0x1C + 0x10 + read-write + 0x0000 + + + RB_DVP_CAPCNT + Number of PCLK cycles captured by clipping window + 0 + 16 + read-write + + + + + VLINE + VLINE + Digital Video Vertical line count register + (DVP_VLINE) + 0x1E + 0x10 + read-write + 0x0000 + + + RB_DVP_VLINE + Crop the number of rows captured by window + 0 + 16 + read-write + + + + + DR + DR + Digital Video Data register + (DVP_DR) + 0x20 + 0x20 + read-only + 0x00000000 + + + RB_DVP_DR + Prevent DMA overflow + 0 + 32 + + + + + + + DAC + Digital to analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CTLR + CTLR + Control register (DAC_CR) + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable + 0 + 1 + + + BOFF1 + DAC channel1 output buffer + disable + 1 + 1 + + + TEN1 + DAC channel1 trigger + enable + 2 + 1 + + + TSEL1 + DAC channel1 trigger + selection + 3 + 3 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude + selector + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + EN2 + DAC channel2 enable + 16 + 1 + + + BOFF2 + DAC channel2 output buffer + disable + 17 + 1 + + + TEN2 + DAC channel2 trigger + enable + 18 + 1 + + + TSEL2 + DAC channel2 trigger + selection + 19 + 3 + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude + selector + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + + + SWTR + SWTR + DAC software trigger register + (DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + + SWTRIG2 + DAC channel2 software + trigger + 1 + 1 + + + + + R12BDHR1 + R12BDHR1 + DAC channel1 12-bit right-aligned data + holding register(DAC_DHR12R1) + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + L12BDHR1 + L12BDHR1 + DAC channel1 12-bit left aligned data + holding register (DAC_DHR12L1) + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + R8BDHR1 + R8BDHR1 + DAC channel1 8-bit right aligned data + holding register (DAC_DHR8R1) + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + R12BDHR2 + R12BDHR2 + DAC channel2 12-bit right aligned data + holding register (DAC_DHR12R2) + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + + + L12BDHR2 + L12BDHR2 + DAC channel2 12-bit left aligned data + holding register (DAC_DHR12L2) + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + + + R8BDHR2 + R8BDHR2 + DAC channel2 8-bit right-aligned data + holding register (DAC_DHR8R2) + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + + + RD12BDHR + RD12BDHR + Dual DAC 12-bit right-aligned data holding + register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 + Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + + + LD12BDHR + LD12BDHR + DUAL DAC 12-bit left aligned data holding + register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 + Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 20 + 12 + + + + + RD8BDHR + RD8BDHR + DUAL DAC 8-bit right aligned data holding + register (DAC_DHR8RD), Bits 31:16 Reserved + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + + + DOR1 + DOR1 + DAC channel1 data output register + (DAC_DOR1) + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + DAC channel2 data output register + (DAC_DOR2) + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection + interrupt + 17 + + + + CTLR + CTLR + Power control register + (PWR_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + LPDS + Low Power Deep Sleep + 0 + 1 + + + PDDS + Power Down Deep Sleep + 1 + 1 + + + CWUF + Clear Wake-up Flag + 2 + 1 + + + CSBF + Clear STANDBY Flag + 3 + 1 + + + PVDE + Power Voltage Detector + Enable + 4 + 1 + + + PLS + PVD Level Selection + 5 + 3 + + + DBP + Disable Backup Domain write + protection + 8 + 1 + + + R2K_STYEN + standby 2k ram enable + 16 + 1 + + + R30K_STYEN + standby 30k ram enable + 17 + 1 + + + R2K_VBATEN + VBAT 30k ram enable + 18 + 1 + + + R30K_VBATEN + VBAT 30k ram enable + 19 + 1 + + + RAM_LVEN + Ram LV Enable + 20 + 1 + + + + + CSR + CSR + Power control register + (PWR_CSR) + 0x04 + 0x20 + 0x00000000 + + + WUF + Wake-Up Flag + 0 + 1 + read-only + + + SBF + STANDBY Flag + 1 + 1 + read-only + + + PVDO + PVD Output + 2 + 1 + read-only + + + EWUP + Enable WKUP pin + 8 + 1 + read-write + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x00 + 0x400 + registers + + + RCC + RCC global interrupt + 21 + + + + CTLR + CTLR + Clock control register + 0x00 + 0x20 + 0x00000083 + + + HSION + Internal High Speed clock + enable + 0 + 1 + read-write + + + HSIRDY + Internal High Speed clock ready + flag + 1 + 1 + read-only + + + HSITRIM + Internal High Speed clock + trimming + 3 + 5 + read-write + + + HSICAL + Internal High Speed clock + Calibration + 8 + 8 + read-only + + + HSEON + External High Speed clock + enable + 16 + 1 + read-write + + + HSERDY + External High Speed clock ready + flag + 17 + 1 + read-only + + + HSEBYP + External High Speed clock + Bypass + 18 + 1 + read-write + + + CSSON + Clock Security System + enable + 19 + 1 + read-write + + + PLLON + PLL enable + 24 + 1 + read-write + + + PLLRDY + PLL clock ready flag + 25 + 1 + read-only + + + PLL2ON + PLL2 enable + 26 + 1 + read-write + + + PLL2RDY + PLL2 clock ready flag + 27 + 1 + read-only + + + PLL3ON + PLL3 enable + 28 + 1 + read-write + + + PLL3RDY + PLL3 clock ready flag + 29 + 1 + read-only + + + + + CFGR0 + CFGR0 + Clock configuration register + (RCC_CFGR0) + 0x04 + 0x20 + 0x00000000 + + + SW + System clock Switch + 0 + 2 + read-write + + + SWS + System Clock Switch Status + 2 + 2 + read-only + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + PPRE1 + APB Low speed prescaler + (APB1) + 8 + 3 + read-write + + + PPRE2 + APB High speed prescaler + (APB2) + 11 + 3 + read-write + + + ADCPRE + ADC prescaler + 14 + 2 + read-write + + + PLLSRC + PLL entry clock source + 16 + 1 + read-write + + + PLLXTPRE + HSE divider for PLL entry + 17 + 1 + read-write + + + PLLMUL + PLL Multiplication Factor + 18 + 4 + read-write + + + USBPRE + USB prescaler + 22 + 2 + read-write + + + MCO + Microcontroller clock + output + 24 + 4 + read-write + + + ADC_CLK_ADJ + ADC clock ADJ + 31 + 1 + read-write + + + + + INTR + INTR + Clock interrupt register + (RCC_INTR) + 0x08 + 0x20 + 0x00000000 + + + LSIRDYF + LSI Ready Interrupt flag + 0 + 1 + read-only + + + LSERDYF + LSE Ready Interrupt flag + 1 + 1 + read-only + + + HSIRDYF + HSI Ready Interrupt flag + 2 + 1 + read-only + + + HSERDYF + HSE Ready Interrupt flag + 3 + 1 + read-only + + + PLLRDYF + PLL Ready Interrupt flag + 4 + 1 + read-only + + + PLL2RDYF + PLL2 Ready Interrupt flag + 5 + 1 + read-only + + + PLL3RDYF + PLL3 Ready Interrupt flag + 6 + 1 + read-only + + + CSSF + Clock Security System Interrupt + flag + 7 + 1 + read-only + + + LSIRDYIE + LSI Ready Interrupt Enable + 8 + 1 + read-write + + + LSERDYIE + LSE Ready Interrupt Enable + 9 + 1 + read-write + + + HSIRDYIE + HSI Ready Interrupt Enable + 10 + 1 + read-write + + + HSERDYIE + HSE Ready Interrupt Enable + 11 + 1 + read-write + + + PLLRDYIE + PLL Ready Interrupt Enable + 12 + 1 + read-write + + + PLL2RDYIE + PLL2 Ready Interrupt Enable + 13 + 1 + read-write + + + PLL3RDYIE + PLL3 Ready Interrupt Enable + 14 + 1 + read-write + + + LSIRDYC + LSI Ready Interrupt Clear + 16 + 1 + write-only + + + LSERDYC + LSE Ready Interrupt Clear + 17 + 1 + write-only + + + HSIRDYC + HSI Ready Interrupt Clear + 18 + 1 + write-only + + + HSERDYC + HSE Ready Interrupt Clear + 19 + 1 + write-only + + + PLLRDYC + PLL Ready Interrupt Clear + 20 + 1 + write-only + + + PLL2RDYC + PLL2 Ready Interrupt Clear + 21 + 1 + write-only + + + PLL3RDYC + PLL3 Ready Interrupt Clear + 22 + 1 + write-only + + + CSSC + Clock security system interrupt + clear + 23 + 1 + write-only + + + + + APB2PRSTR + APB2PRSTR + APB2 peripheral reset register + (RCC_APB2PRSTR) + 0x0C + 0x20 + read-write + 0x00000000 + + + AFIORST + Alternate function I/O + reset + 0 + 1 + + + IOPARST + IO port A reset + 2 + 1 + + + IOPBRST + IO port B reset + 3 + 1 + + + IOPCRST + IO port C reset + 4 + 1 + + + IOPDRST + IO port D reset + 5 + 1 + + + IOPERST + IO port E reset + 6 + 1 + + + ADC1RST + ADC 1 interface reset + 9 + 1 + + + ADC2RST + ADC 2 interface reset + 10 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + TIM8RST + TIM8 timer reset + 13 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TIM9RST + TIM9 timer reset + 19 + 1 + + + TIM10RST + TIM10 timer reset + 20 + 1 + + + + + APB1PRSTR + APB1PRSTR + APB1 peripheral reset register + (RCC_APB1PRSTR) + 0x10 + 0x20 + read-write + 0x00000000 + + + TIM2RST + Timer 2 reset + 0 + 1 + + + TIM3RST + Timer 3 reset + 1 + 1 + + + TIM4RST + Timer 4 reset + 2 + 1 + + + TIM5RST + Timer 5 reset + 3 + 1 + + + TIM6RST + Timer 6 reset + 4 + 1 + + + TIM7RST + Timer 7 reset + 5 + 1 + + + UART6RST + UART 6 reset + 6 + 1 + + + UART7RST + UART 7 reset + 7 + 1 + + + UART8RST + UART 8 reset + 8 + 1 + + + WWDGRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + USART4RST + USART 4 reset + 19 + 1 + + + USART5RST + USART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + USBDRST + USBD reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + BKPRST + Backup interface reset + 27 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + DACRST + DAC interface reset + 29 + 1 + + + + + AHBPCENR + AHBPCENR + AHB Peripheral Clock enable register + (RCC_AHBPCENR) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLITFEN + FLITF clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + FSMCEN + FSMC clock enable + 8 + 1 + + + TRNG_EN + TRNG clock enable + 9 + 1 + + + SDIOEN + SDIO clock enable + 10 + 1 + + + USBHS_EN + USBHS clock enable + 11 + 1 + + + OTG_EN + OTG clock enable + 12 + 1 + + + DVP_EN + DVP clock enable + 13 + 1 + + + ETHMACEN + Ethernet MAC clock enable + 14 + 1 + + + ETHMACTXEN + Ethernet MAC TX clock + enable + 15 + 1 + + + ETHMACRXEN + Ethernet MAC RX clock + enable + 16 + 1 + + + + + APB2PCENR + APB2PCENR + APB2 peripheral clock enable register + (RCC_APB2PCENR) + 0x18 + 0x20 + read-write + 0x00000000 + + + AFIOEN + Alternate function I/O clock + enable + 0 + 1 + + + IOPAEN + I/O port A clock enable + 2 + 1 + + + IOPBEN + I/O port B clock enable + 3 + 1 + + + IOPCEN + I/O port C clock enable + 4 + 1 + + + IOPDEN + I/O port D clock enable + 5 + 1 + + + IOPEEN + I/O port E clock enable + 6 + 1 + + + ADC1EN + ADC1 interface clock + enable + 9 + 1 + + + ADC2EN + ADC 2 interface clock + enable + 10 + 1 + + + TIM1EN + TIM1 Timer clock enable + 11 + 1 + + + SPI1EN + SPI 1 clock enable + 12 + 1 + + + TIM8EN + TIM8 Timer clock enable + 13 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + TIM9_EN + TIM9 Timer clock enable + 19 + 1 + + + TIM10_EN + TIM10 Timer clock enable + 20 + 1 + + + + + APB1PCENR + APB1PCENR + APB1 peripheral clock enable register + (RCC_APB1PCENR) + 0x1C + 0x20 + read-write + 0x00000000 + + + TIM2EN + Timer 2 clock enable + 0 + 1 + + + TIM3EN + Timer 3 clock enable + 1 + 1 + + + TIM4EN + Timer 4 clock enable + 2 + 1 + + + TIM5EN + Timer 5 clock enable + 3 + 1 + + + TIM6EN + Timer 6 clock enable + 4 + 1 + + + TIM7EN + Timer 7 clock enable + 5 + 1 + + + USART6_EN + USART 6 clock enable + 6 + 1 + + + USART7_EN + USART 7 clock enable + 7 + 1 + + + USART8_EN + USART 8 clock enable + 8 + 1 + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + SPI2EN + SPI 2 clock enable + 14 + 1 + + + SPI3EN + SPI 3 clock enable + 15 + 1 + + + USART2EN + USART 2 clock enable + 17 + 1 + + + USART3EN + USART 3 clock enable + 18 + 1 + + + UART4EN + UART 4 clock enable + 19 + 1 + + + UART5EN + UART 5 clock enable + 20 + 1 + + + I2C1EN + I2C 1 clock enable + 21 + 1 + + + I2C2EN + I2C 2 clock enable + 22 + 1 + + + USBDEN + USBD clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + BKPEN + Backup interface clock + enable + 27 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + DACEN + DAC interface clock enable + 29 + 1 + + + + + BDCTLR + BDCTLR + Backup domain control register + (RCC_BDCTLR) + 0x20 + 0x20 + 0x00000000 + + + LSEON + External Low Speed oscillator + enable + 0 + 1 + read-write + + + LSERDY + External Low Speed oscillator + ready + 1 + 1 + read-only + + + LSEBYP + External Low Speed oscillator + bypass + 2 + 1 + read-write + + + RTCSEL + RTC clock source selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + + + + RSTSCKR + RSTSCKR + Control/status register + (RCC_RSTSCKR) + 0x24 + 0x20 + 0x0C000000 + + + LSION + Internal low speed oscillator + enable + 0 + 1 + read-write + + + LSIRDY + Internal low speed oscillator + ready + 1 + 1 + read-only + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + PINRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + IWDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRSTR + AHBRSTR + AHB reset register + (RCC_APHBRSTR) + 0x28 + 0x20 + 0x00000000 + + + USBHDRST + USBHD reset + 12 + 1 + read-write + + + DVPRST + DVP reset + 13 + 1 + read-only + + + ETHMACRST + Ethernet MAC reset + 14 + 1 + read-write + + + + + CFGR2 + CFGR2 + Clock configuration register2 + (RCC_CFGR2) + 0x2C + 0x20 + read-write + 0x00000000 + + + PREDIV1 + PREDIV1 division factor + 0 + 4 + + + PREDIV2 + PREDIV2 division factor + 4 + 4 + + + PLL2MUL + PLL2 Multiplication Factor + 8 + 4 + + + PLL3MUL + PLL3 Multiplication Factor + 12 + 4 + + + PREDIV1SRC + PREDIV1 entry clock source + 16 + 1 + + + I2S2SRC + I2S2 clock source + 17 + 1 + + + I2S3SRC + I2S3 clock source + 18 + 1 + + + TRNG_SRC + TRNG clock source + 19 + 1 + + + ETH1G_SRC + ETH1G clock source + 20 + 2 + + + ETH1G_125M_EN + ETH1G _125M clock enable + 22 + 1 + + + USBHS_PREDIY + USB HS PREDIV division factor + 24 + 3 + + + USBHS_PLL_SRC + USB HS Multiplication Factor clock source + 27 + 1 + + + USBHS_CKPEF_SEL + USB HS Peference Clock source + 28 + 2 + + + USBHS_PLLALIVE + USB HS Multiplication control + 30 + 1 + + + USBHS_CLK_SRC + USB HS clock source + 31 + 1 + + + + + + + EXTEND + Extend configuration + EXTEND + 0x40023800 + + 0x00 + 0x400 + registers + + + + EXTEND_CTR + EXTEND + EXTEND register + 0x00 + 0x20 + 0x00000A00 + + + USBDLS + USBD Lowspeed Enable + 0 + 1 + read-write + + + USBDPU + USBD pullup Enable + 1 + 1 + read-write + + + ETH_10M_EN + ETH 10M Enable + 2 + 1 + read-write + + + ETH_RGMII_EN + ETH RGMII Enable + 3 + 1 + read-write + + + PLL_HSI_PRE + Whether HSI is divided + 4 + 1 + read-write + + + LOCKUP_EN + LOCKUP_Eable + 6 + 1 + read-write + + + LOCKUP_RSTF + LOCKUP RESET + 7 + 1 + read-write + + + ULLDO_TRIM + ULLDO_TRIM + 8 + 2 + read-write + + + LDO_TRIM + LDO_TRIM + 10 + 2 + read-write + + + HSE_KEEP_LP + HSE_KEEP_LP + 12 + 1 + read-write + + + + + + + OPA + OPA configuration + OPA + 0x40023804 + + 0x0 + 0x200 + registers + + + + CR + CR + Control register + 0x0 + 0x20 + 0x00000000 + + + EN1 + OPA Enable1 + 0 + 1 + read-write + + + MODE1 + OPA MODE1 + 1 + 1 + read-write + + + NSEL1 + OPA NSEL1 + 2 + 1 + read-write + + + PSEL1 + OPA PSEL1 + 3 + 1 + read-write + + + EN2 + OPA Enable2 + 4 + 1 + read-write + + + MODE2 + OPA MODE2 + 5 + 1 + read-write + + + NSEL2 + OPA NSEL2 + 6 + 1 + read-write + + + PSEL2 + OPA PSEL2 + 7 + 1 + read-write + + + EN3 + OPA Eable3 + 8 + 1 + read-write + + + MODE3 + OPA MODE3 + 9 + 1 + read-write + + + NSEL3 + OPA NSEL3 + 10 + 1 + read-write + + + PSEL3 + OPA PSEL3 + 11 + 1 + read-write + + + EN4 + OPA Enable4 + 12 + 1 + read-write + + + MODE4 + OPA MODE4 + 13 + 1 + read-write + + + NSEL4 + OPA NSEL4 + 14 + 1 + read-write + + + PSEL4 + OPA PSEL4 + 15 + 1 + read-write + + + + + + + GPIOA + General purpose I/O + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CFGLR + CFGLR + Port configuration register low + (GPIOn_CFGLR) + 0x0 + 0x20 + read-write + 0x44444444 + + + MODE0 + Port n.0 mode bits + 0 + 2 + + + CNF0 + Port n.0 configuration + bits + 2 + 2 + + + MODE1 + Port n.1 mode bits + 4 + 2 + + + CNF1 + Port n.1 configuration + bits + 6 + 2 + + + MODE2 + Port n.2 mode bits + 8 + 2 + + + CNF2 + Port n.2 configuration + bits + 10 + 2 + + + MODE3 + Port n.3 mode bits + 12 + 2 + + + CNF3 + Port n.3 configuration + bits + 14 + 2 + + + MODE4 + Port n.4 mode bits + 16 + 2 + + + CNF4 + Port n.4 configuration + bits + 18 + 2 + + + MODE5 + Port n.5 mode bits + 20 + 2 + + + CNF5 + Port n.5 configuration + bits + 22 + 2 + + + MODE6 + Port n.6 mode bits + 24 + 2 + + + CNF6 + Port n.6 configuration + bits + 26 + 2 + + + MODE7 + Port n.7 mode bits + 28 + 2 + + + CNF7 + Port n.7 configuration + bits + 30 + 2 + + + + + CFGHR + CFGHR + Port configuration register high + (GPIOn_CFGHR) + 0x4 + 0x20 + read-write + 0x44444444 + + + MODE8 + Port n.8 mode bits + 0 + 2 + + + CNF8 + Port n.8 configuration + bits + 2 + 2 + + + MODE9 + Port n.9 mode bits + 4 + 2 + + + CNF9 + Port n.9 configuration + bits + 6 + 2 + + + MODE10 + Port n.10 mode bits + 8 + 2 + + + CNF10 + Port n.10 configuration + bits + 10 + 2 + + + MODE11 + Port n.11 mode bits + 12 + 2 + + + CNF11 + Port n.11 configuration + bits + 14 + 2 + + + MODE12 + Port n.12 mode bits + 16 + 2 + + + CNF12 + Port n.12 configuration + bits + 18 + 2 + + + MODE13 + Port n.13 mode bits + 20 + 2 + + + CNF13 + Port n.13 configuration + bits + 22 + 2 + + + MODE14 + Port n.14 mode bits + 24 + 2 + + + CNF14 + Port n.14 configuration + bits + 26 + 2 + + + MODE15 + Port n.15 mode bits + 28 + 2 + + + CNF15 + Port n.15 configuration + bits + 30 + 2 + + + + + INDR + INDR + Port input data register + (GPIOn_INDR) + 0x8 + 0x20 + read-only + 0x00000000 + + + IDR0 + Port input data + 0 + 1 + + + IDR1 + Port input data + 1 + 1 + + + IDR2 + Port input data + 2 + 1 + + + IDR3 + Port input data + 3 + 1 + + + IDR4 + Port input data + 4 + 1 + + + IDR5 + Port input data + 5 + 1 + + + IDR6 + Port input data + 6 + 1 + + + IDR7 + Port input data + 7 + 1 + + + IDR8 + Port input data + 8 + 1 + + + IDR9 + Port input data + 9 + 1 + + + IDR10 + Port input data + 10 + 1 + + + IDR11 + Port input data + 11 + 1 + + + IDR12 + Port input data + 12 + 1 + + + IDR13 + Port input data + 13 + 1 + + + IDR14 + Port input data + 14 + 1 + + + IDR15 + Port input data + 15 + 1 + + + + + OUTDR + OUTDR + Port output data register + (GPIOn_OUTDR) + 0xC + 0x20 + read-write + 0x00000000 + + + ODR0 + Port output data + 0 + 1 + + + ODR1 + Port output data + 1 + 1 + + + ODR2 + Port output data + 2 + 1 + + + ODR3 + Port output data + 3 + 1 + + + ODR4 + Port output data + 4 + 1 + + + ODR5 + Port output data + 5 + 1 + + + ODR6 + Port output data + 6 + 1 + + + ODR7 + Port output data + 7 + 1 + + + ODR8 + Port output data + 8 + 1 + + + ODR9 + Port output data + 9 + 1 + + + ODR10 + Port output data + 10 + 1 + + + ODR11 + Port output data + 11 + 1 + + + ODR12 + Port output data + 12 + 1 + + + ODR13 + Port output data + 13 + 1 + + + ODR14 + Port output data + 14 + 1 + + + ODR15 + Port output data + 15 + 1 + + + + + BSHR + BSHR + Port bit set/reset register + (GPIOn_BSHR) + 0x10 + 0x20 + write-only + 0x00000000 + + + BS0 + Set bit 0 + 0 + 1 + + + BS1 + Set bit 1 + 1 + 1 + + + BS2 + Set bit 1 + 2 + 1 + + + BS3 + Set bit 3 + 3 + 1 + + + BS4 + Set bit 4 + 4 + 1 + + + BS5 + Set bit 5 + 5 + 1 + + + BS6 + Set bit 6 + 6 + 1 + + + BS7 + Set bit 7 + 7 + 1 + + + BS8 + Set bit 8 + 8 + 1 + + + BS9 + Set bit 9 + 9 + 1 + + + BS10 + Set bit 10 + 10 + 1 + + + BS11 + Set bit 11 + 11 + 1 + + + BS12 + Set bit 12 + 12 + 1 + + + BS13 + Set bit 13 + 13 + 1 + + + BS14 + Set bit 14 + 14 + 1 + + + BS15 + Set bit 15 + 15 + 1 + + + BR0 + Reset bit 0 + 16 + 1 + + + BR1 + Reset bit 1 + 17 + 1 + + + BR2 + Reset bit 2 + 18 + 1 + + + BR3 + Reset bit 3 + 19 + 1 + + + BR4 + Reset bit 4 + 20 + 1 + + + BR5 + Reset bit 5 + 21 + 1 + + + BR6 + Reset bit 6 + 22 + 1 + + + BR7 + Reset bit 7 + 23 + 1 + + + BR8 + Reset bit 8 + 24 + 1 + + + BR9 + Reset bit 9 + 25 + 1 + + + BR10 + Reset bit 10 + 26 + 1 + + + BR11 + Reset bit 11 + 27 + 1 + + + BR12 + Reset bit 12 + 28 + 1 + + + BR13 + Reset bit 13 + 29 + 1 + + + BR14 + Reset bit 14 + 30 + 1 + + + BR15 + Reset bit 15 + 31 + 1 + + + + + BCR + BCR + Port bit reset register + (GPIOn_BCR) + 0x14 + 0x20 + write-only + 0x00000000 + + + BR0 + Reset bit 0 + 0 + 1 + + + BR1 + Reset bit 1 + 1 + 1 + + + BR2 + Reset bit 1 + 2 + 1 + + + BR3 + Reset bit 3 + 3 + 1 + + + BR4 + Reset bit 4 + 4 + 1 + + + BR5 + Reset bit 5 + 5 + 1 + + + BR6 + Reset bit 6 + 6 + 1 + + + BR7 + Reset bit 7 + 7 + 1 + + + BR8 + Reset bit 8 + 8 + 1 + + + BR9 + Reset bit 9 + 9 + 1 + + + BR10 + Reset bit 10 + 10 + 1 + + + BR11 + Reset bit 11 + 11 + 1 + + + BR12 + Reset bit 12 + 12 + 1 + + + BR13 + Reset bit 13 + 13 + 1 + + + BR14 + Reset bit 14 + 14 + 1 + + + BR15 + Reset bit 15 + 15 + 1 + + + + + LCKR + LCKR + Port configuration lock + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LCK0 + Port A Lock bit 0 + 0 + 1 + + + LCK1 + Port A Lock bit 1 + 1 + 1 + + + LCK2 + Port A Lock bit 2 + 2 + 1 + + + LCK3 + Port A Lock bit 3 + 3 + 1 + + + LCK4 + Port A Lock bit 4 + 4 + 1 + + + LCK5 + Port A Lock bit 5 + 5 + 1 + + + LCK6 + Port A Lock bit 6 + 6 + 1 + + + LCK7 + Port A Lock bit 7 + 7 + 1 + + + LCK8 + Port A Lock bit 8 + 8 + 1 + + + LCK9 + Port A Lock bit 9 + 9 + 1 + + + LCK10 + Port A Lock bit 10 + 10 + 1 + + + LCK11 + Port A Lock bit 11 + 11 + 1 + + + LCK12 + Port A Lock bit 12 + 12 + 1 + + + LCK13 + Port A Lock bit 13 + 13 + 1 + + + LCK14 + Port A Lock bit 14 + 14 + 1 + + + LCK15 + Port A Lock bit 15 + 15 + 1 + + + LCKK + Lock key + 16 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOE + 0x40011800 + + + AFIO + Alternate function I/O + AFIO + 0x40010000 + + 0x0 + 0x400 + registers + + + + ECR + ECR + Event Control Register + (AFIO_ECR) + 0x0 + 0x20 + read-write + 0x00000000 + + + PIN + Pin selection + 0 + 4 + + + PORT + Port selection + 4 + 3 + + + EVOE + Event Output Enable + 7 + 1 + + + + + PCFR + PCFR + AF remap and debug I/O configuration + register (AFIO_PCFR) + 0x4 + 0x20 + 0x00000000 + + + SPI1RM + SPI1 remapping + 0 + 1 + read-write + + + I2C1RM + I2C1 remapping + 1 + 1 + read-write + + + USART1RM + USART1 remapping + 2 + 1 + read-write + + + USART2RM + USART2 remapping + 3 + 1 + read-write + + + USART3RM + USART3 remapping + 4 + 2 + read-write + + + TIM1RM + TIM1 remapping + 6 + 2 + read-write + + + TIM2RM + TIM2 remapping + 8 + 2 + read-write + + + TIM3RM + TIM3 remapping + 10 + 2 + read-write + + + TIM4RM + TIM4 remapping + 12 + 1 + read-write + + + CAN1RM + CAN1 remapping + 13 + 2 + read-write + + + PD01RM + Port D0/Port D1 mapping on + OSCIN/OSCOUT + 15 + 1 + read-write + + + TIM5CH4RM + TIM5 channel4 internal remap + 16 + 1 + read-write + + + ADC1_ETRGINJ_RM + ADC 1 External trigger injected conversion remapping + 17 + 1 + read-write + + + ADC1_ETRGREG_RM + ADC 1 external trigger regular conversion remapping + 18 + 1 + read-write + + + ADC2_ETRGINJ_RM + ADC 2 External trigger injected conversion remapping + 19 + 1 + read-write + + + ADC2_ETRGREG_RM + ADC 2 external trigger regular conversion remapping + 20 + 1 + read-write + + + ETHRM + Ethernet remapping + 21 + 1 + read-write + + + CAN2RM + CAN2 remapping + 22 + 1 + read-write + + + MII_RMII_SEL + MII_RMII_SEL + 23 + 1 + read-write + + + SWCFG + Serial wire JTAG + configuration + 24 + 3 + write-only + + + SPI3_RM + SPI3 remapping + 28 + 1 + read-write + + + TIM2ITRA_RM + TIM2 internally triggers 1 remapping + 29 + 1 + read-write + + + PTP_PPSP_RM + Ethernet PTP_PPS remapping + 30 + 1 + read-write + + + + + EXTICR1 + EXTICR1 + External interrupt configuration register 1 + (AFIO_EXTICR1) + 0x08 + 0x20 + read-write + 0x00000000 + + + EXTI0 + EXTI0 configuration + 0 + 4 + + + EXTI1 + EXTI1 configuration + 4 + 4 + + + EXTI2 + EXTI2 configuration + 8 + 4 + + + EXTI3 + EXTI3 configuration + 12 + 4 + + + + + EXTICR2 + EXTICR2 + External interrupt configuration register 2 + (AFIO_EXTICR2) + 0xC + 0x20 + read-write + 0x00000000 + + + EXTI4 + EXTI4 configuration + 0 + 4 + + + EXTI5 + EXTI5 configuration + 4 + 4 + + + EXTI6 + EXTI6 configuration + 8 + 4 + + + EXTI7 + EXTI7 configuration + 12 + 4 + + + + + EXTICR3 + EXTICR3 + External interrupt configuration register 3 + (AFIO_EXTICR3) + 0x10 + 0x20 + read-write + 0x00000000 + + + EXTI8 + EXTI8 configuration + 0 + 4 + + + EXTI9 + EXTI9 configuration + 4 + 4 + + + EXTI10 + EXTI10 configuration + 8 + 4 + + + EXTI11 + EXTI11 configuration + 12 + 4 + + + + + EXTICR4 + EXTICR4 + External interrupt configuration register 4 + (AFIO_EXTICR4) + 0x14 + 0x20 + read-write + 0x00000000 + + + EXTI12 + EXTI12 configuration + 0 + 4 + + + EXTI13 + EXTI13 configuration + 4 + 4 + + + EXTI14 + EXTI14 configuration + 8 + 4 + + + EXTI15 + EXTI15 configuration + 12 + 4 + + + + + PCFR2 + PCFR2 + AF remap and debug I/O configuration + register (AFIO_PCFR2) + 0x1C + 0x20 + 0x00000000 + + + TIM8_REMAP + TIM8 remapping + 2 + 1 + read-write + + + TIM9_REMAP + TIM9 remapping + 3 + 2 + read-write + + + TIM10_REMAP + TIM10 remapping + 5 + 2 + read-write + + + FSMC_NADV + FSMC_NADV + 10 + 1 + read-write + + + UART4_REMAP + UART4 remapping + 16 + 2 + read-write + + + UART5_REMAP + UART5 remapping + 18 + 2 + read-write + + + UART6_REMAP + UART6 remapping + 20 + 2 + read-write + + + UART7_REMAP + UART7 remapping + 22 + 2 + read-write + + + UART8_REMAP + UART8 remapping + 24 + 2 + read-write + + + UART1_REMAP2 + UART1 remapping + 26 + 1 + read-write + + + + + + + EXTI + EXTI + EXTI + 0x40010400 + + 0x00 + 0x400 + registers + + + TAMPER + Tamper interrupt + 18 + + + EXTI0 + EXTI Line0 interrupt + 22 + + + EXTI1 + EXTI Line1 interrupt + 23 + + + EXTI2 + EXTI Line2 interrupt + 24 + + + EXTI3 + EXTI Line3 interrupt + 25 + + + EXTI4 + EXTI Line4 interrupt + 26 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 39 + + + EXTI15_10 + EXTI Line[15:10] interrupts + 56 + + + + INTENR + INTENR + Interrupt mask register + (EXTI_INTENR) + 0x00 + 0x20 + read-write + 0x00000000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + MR10 + Interrupt Mask on line 10 + 10 + 1 + + + MR11 + Interrupt Mask on line 11 + 11 + 1 + + + MR12 + Interrupt Mask on line 12 + 12 + 1 + + + MR13 + Interrupt Mask on line 13 + 13 + 1 + + + MR14 + Interrupt Mask on line 14 + 14 + 1 + + + MR15 + Interrupt Mask on line 15 + 15 + 1 + + + MR16 + Interrupt Mask on line 16 + 16 + 1 + + + MR17 + Interrupt Mask on line 17 + 17 + 1 + + + MR18 + Interrupt Mask on line 18 + 18 + 1 + + + MR19 + Interrupt Mask on line 19 + 19 + 1 + + + + + EVENR + EVENR + Event mask register (EXTI_EVENR) + 0x04 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + + MR1 + Event Mask on line 1 + 1 + 1 + + + MR2 + Event Mask on line 2 + 2 + 1 + + + MR3 + Event Mask on line 3 + 3 + 1 + + + MR4 + Event Mask on line 4 + 4 + 1 + + + MR5 + Event Mask on line 5 + 5 + 1 + + + MR6 + Event Mask on line 6 + 6 + 1 + + + MR7 + Event Mask on line 7 + 7 + 1 + + + MR8 + Event Mask on line 8 + 8 + 1 + + + MR9 + Event Mask on line 9 + 9 + 1 + + + MR10 + Event Mask on line 10 + 10 + 1 + + + MR11 + Event Mask on line 11 + 11 + 1 + + + MR12 + Event Mask on line 12 + 12 + 1 + + + MR13 + Event Mask on line 13 + 13 + 1 + + + MR14 + Event Mask on line 14 + 14 + 1 + + + MR15 + Event Mask on line 15 + 15 + 1 + + + MR16 + Event Mask on line 16 + 16 + 1 + + + MR17 + Event Mask on line 17 + 17 + 1 + + + MR18 + Event Mask on line 18 + 18 + 1 + + + MR19 + Event Mask on line 19 + 19 + 1 + + + + + RTENR + RTENR + Rising Trigger selection register + (EXTI_RTENR) + 0x08 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Rising trigger event configuration of + line 18 + 18 + 1 + + + TR19 + Rising trigger event configuration of + line 19 + 19 + 1 + + + + + FTENR + FTENR + Falling Trigger selection register + (EXTI_FTENR) + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Falling trigger event configuration of + line 18 + 18 + 1 + + + TR19 + Falling trigger event configuration of + line 19 + 19 + 1 + + + + + SWIEVR + SWIEVR + Software interrupt event register + (EXTI_SWIEVR) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Software Interrupt on line + 0 + 0 + 1 + + + SWIER1 + Software Interrupt on line + 1 + 1 + 1 + + + SWIER2 + Software Interrupt on line + 2 + 2 + 1 + + + SWIER3 + Software Interrupt on line + 3 + 3 + 1 + + + SWIER4 + Software Interrupt on line + 4 + 4 + 1 + + + SWIER5 + Software Interrupt on line + 5 + 5 + 1 + + + SWIER6 + Software Interrupt on line + 6 + 6 + 1 + + + SWIER7 + Software Interrupt on line + 7 + 7 + 1 + + + SWIER8 + Software Interrupt on line + 8 + 8 + 1 + + + SWIER9 + Software Interrupt on line + 9 + 9 + 1 + + + SWIER10 + Software Interrupt on line + 10 + 10 + 1 + + + SWIER11 + Software Interrupt on line + 11 + 11 + 1 + + + SWIER12 + Software Interrupt on line + 12 + 12 + 1 + + + SWIER13 + Software Interrupt on line + 13 + 13 + 1 + + + SWIER14 + Software Interrupt on line + 14 + 14 + 1 + + + SWIER15 + Software Interrupt on line + 15 + 15 + 1 + + + SWIER16 + Software Interrupt on line + 16 + 16 + 1 + + + SWIER17 + Software Interrupt on line + 17 + 17 + 1 + + + SWIER18 + Software Interrupt on line + 18 + 18 + 1 + + + SWIER19 + Software Interrupt on line + 19 + 19 + 1 + + + + + INTFR + INTFR + Pending register (EXTI_INTFR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PR0 + Pending bit 0 + 0 + 1 + + + PR1 + Pending bit 1 + 1 + 1 + + + PR2 + Pending bit 2 + 2 + 1 + + + PR3 + Pending bit 3 + 3 + 1 + + + PR4 + Pending bit 4 + 4 + 1 + + + PR5 + Pending bit 5 + 5 + 1 + + + PR6 + Pending bit 6 + 6 + 1 + + + PR7 + Pending bit 7 + 7 + 1 + + + PR8 + Pending bit 8 + 8 + 1 + + + PR9 + Pending bit 9 + 9 + 1 + + + PR10 + Pending bit 10 + 10 + 1 + + + PR11 + Pending bit 11 + 11 + 1 + + + PR12 + Pending bit 12 + 12 + 1 + + + PR13 + Pending bit 13 + 13 + 1 + + + PR14 + Pending bit 14 + 14 + 1 + + + PR15 + Pending bit 15 + 15 + 1 + + + PR16 + Pending bit 16 + 16 + 1 + + + PR17 + Pending bit 17 + 17 + 1 + + + PR18 + Pending bit 18 + 18 + 1 + + + PR19 + Pending bit 19 + 19 + 1 + + + + + + + DMA1 + DMA1 controller + DMA1 + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 27 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 28 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 29 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 30 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 31 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 32 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 33 + + + + INTFR + INTFR + DMA interrupt status register + (DMA_INTFR) + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + TCIF1 + Channel 1 Transfer Complete + flag + 1 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete + flag + 2 + 1 + + + TEIF1 + Channel 1 Transfer Error + flag + 3 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 4 + 1 + + + TCIF2 + Channel 2 Transfer Complete + flag + 5 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete + flag + 6 + 1 + + + TEIF2 + Channel 2 Transfer Error + flag + 7 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 8 + 1 + + + TCIF3 + Channel 3 Transfer Complete + flag + 9 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete + flag + 10 + 1 + + + TEIF3 + Channel 3 Transfer Error + flag + 11 + 1 + + + GIF4 + Channel 4 Global interrupt + flag + 12 + 1 + + + TCIF4 + Channel 4 Transfer Complete + flag + 13 + 1 + + + HTIF4 + Channel 4 Half Transfer Complete + flag + 14 + 1 + + + TEIF4 + Channel 4 Transfer Error + flag + 15 + 1 + + + GIF5 + Channel 5 Global interrupt + flag + 16 + 1 + + + TCIF5 + Channel 5 Transfer Complete + flag + 17 + 1 + + + HTIF5 + Channel 5 Half Transfer Complete + flag + 18 + 1 + + + TEIF5 + Channel 5 Transfer Error + flag + 19 + 1 + + + GIF6 + Channel 6 Global interrupt + flag + 20 + 1 + + + TCIF6 + Channel 6 Transfer Complete + flag + 21 + 1 + + + HTIF6 + Channel 6 Half Transfer Complete + flag + 22 + 1 + + + TEIF6 + Channel 6 Transfer Error + flag + 23 + 1 + + + GIF7 + Channel 7 Global interrupt + flag + 24 + 1 + + + TCIF7 + Channel 7 Transfer Complete + flag + 25 + 1 + + + HTIF7 + Channel 7 Half Transfer Complete + flag + 26 + 1 + + + TEIF7 + Channel 7 Transfer Error + flag + 27 + 1 + + + + + INTFCR + INTFCR + DMA interrupt flag clear register + (DMA_INTFCR) + 0x4 + 0x20 + write-only + 0x00000000 + + + CGIF1 + Channel 1 Global interrupt + clear + 0 + 1 + + + CGIF2 + Channel 2 Global interrupt + clear + 4 + 1 + + + CGIF3 + Channel 3 Global interrupt + clear + 8 + 1 + + + CGIF4 + Channel 4 Global interrupt + clear + 12 + 1 + + + CGIF5 + Channel 5 Global interrupt + clear + 16 + 1 + + + CGIF6 + Channel 6 Global interrupt + clear + 20 + 1 + + + CGIF7 + Channel 7 Global interrupt + clear + 24 + 1 + + + CTCIF1 + Channel 1 Transfer Complete + clear + 1 + 1 + + + CTCIF2 + Channel 2 Transfer Complete + clear + 5 + 1 + + + CTCIF3 + Channel 3 Transfer Complete + clear + 9 + 1 + + + CTCIF4 + Channel 4 Transfer Complete + clear + 13 + 1 + + + CTCIF5 + Channel 5 Transfer Complete + clear + 17 + 1 + + + CTCIF6 + Channel 6 Transfer Complete + clear + 21 + 1 + + + CTCIF7 + Channel 7 Transfer Complete + clear + 25 + 1 + + + CHTIF1 + Channel 1 Half Transfer + clear + 2 + 1 + + + CHTIF2 + Channel 2 Half Transfer + clear + 6 + 1 + + + CHTIF3 + Channel 3 Half Transfer + clear + 10 + 1 + + + CHTIF4 + Channel 4 Half Transfer + clear + 14 + 1 + + + CHTIF5 + Channel 5 Half Transfer + clear + 18 + 1 + + + CHTIF6 + Channel 6 Half Transfer + clear + 22 + 1 + + + CHTIF7 + Channel 7 Half Transfer + clear + 26 + 1 + + + CTEIF1 + Channel 1 Transfer Error + clear + 3 + 1 + + + CTEIF2 + Channel 2 Transfer Error + clear + 7 + 1 + + + CTEIF3 + Channel 3 Transfer Error + clear + 11 + 1 + + + CTEIF4 + Channel 4 Transfer Error + clear + 15 + 1 + + + CTEIF5 + Channel 5 Transfer Error + clear + 19 + 1 + + + CTEIF6 + Channel 6 Transfer Error + clear + 23 + 1 + + + CTEIF7 + Channel 7 Transfer Error + clear + 27 + 1 + + + + + CFGR1 + CFGR + DMA channel configuration register + (DMA_CFGR) + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR1 + CNTR + DMA channel 1 number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR1 + PADDR1 + DMA channel 1 peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR1 + MADDR1 + DMA channel 1 memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR2 + CFGR2 + DMA channel configuration register + (DMA_CFGR) + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR2 + CNTR2 + DMA channel 2 number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR2 + PADDR2 + DMA channel 2 peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR2 + MADDR2 + DMA channel 2 memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR3 + CFGR3 + DMA channel configuration register + (DMA_CFGR) + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR3 + CNTR3 + DMA channel 3 number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR3 + PADDR3 + DMA channel 3 peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR3 + MADDR3 + DMA channel 3 memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR4 + CFGR4 + DMA channel configuration register + (DMA_CFGR) + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR4 + CNTR4 + DMA channel 4 number of data + register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR4 + PADDR4 + DMA channel 4 peripheral address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR4 + MADDR4 + DMA channel 4 memory address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR5 + CFGR5 + DMA channel configuration register + (DMA_CFGR) + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR5 + CNTR5 + DMA channel 5 number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR5 + PADDR5 + DMA channel 5 peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR5 + MADDR5 + DMA channel 5 memory address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR6 + CFGR6 + DMA channel configuration register + (DMA_CFGR) + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR6 + CNTR6 + DMA channel 6 number of data + register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR6 + PADDR6 + DMA channel 6 peripheral address + register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR6 + MADDR6 + DMA channel 6 memory address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR7 + CFGR7 + DMA channel configuration register + (DMA_CFGR) + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR7 + CNTR7 + DMA channel 7 number of data + register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR7 + PADDR7 + DMA channel 7 peripheral address + register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR7 + MADDR7 + DMA channel 7 memory address + register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + + DMA2 + DMA2 controller + DMA2 + 0x40020400 + + 0x0 + 0x400 + registers + + + DMA2_Channel1 + DMA2 Channel1 global interrupt + 72 + + + DMA2_Channel2 + DMA2 Channel2 global interrupt + 73 + + + DMA2_Channel3 + DMA2 Channel3 global interrupt + 74 + + + DMA2_Channel4 + DMA2 Channel4 global interrupt + 75 + + + DMA2_Channel5 + DMA2 Channel5 global interrupt + 76 + + + DMA2_Channel6 + DMA2 Channel6 global interrupt + 98 + + + DMA2_Channel7 + DMA2 Channel7 global interrupt + 99 + + + DMA2_Channel8 + DMA2 Channel8 global interrupt + 100 + + + DMA2_Channel9 + DMA2 Channel9 global interrupt + 101 + + + DMA2_Channel10 + DMA2 Channel10 global interrupt + 102 + + + DMA2_Channel11 + DMA2 Channel11 global interrupt + 103 + + + + INTFR + INTFR + DMA interrupt status register + (DMA_INTFR) + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + TCIF1 + Channel 1 Transfer Complete + flag + 1 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete + flag + 2 + 1 + + + TEIF1 + Channel 1 Transfer Error + flag + 3 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 4 + 1 + + + TCIF2 + Channel 2 Transfer Complete + flag + 5 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete + flag + 6 + 1 + + + TEIF2 + Channel 2 Transfer Error + flag + 7 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 8 + 1 + + + TCIF3 + Channel 3 Transfer Complete + flag + 9 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete + flag + 10 + 1 + + + TEIF3 + Channel 3 Transfer Error + flag + 11 + 1 + + + GIF4 + Channel 4 Global interrupt + flag + 12 + 1 + + + TCIF4 + Channel 4 Transfer Complete + flag + 13 + 1 + + + HTIF4 + Channel 4 Half Transfer Complete + flag + 14 + 1 + + + TEIF4 + Channel 4 Transfer Error + flag + 15 + 1 + + + GIF5 + Channel 5 Global interrupt + flag + 16 + 1 + + + TCIF5 + Channel 5 Transfer Complete + flag + 17 + 1 + + + HTIF5 + Channel 5 Half Transfer Complete + flag + 18 + 1 + + + TEIF5 + Channel 5 Transfer Error + flag + 19 + 1 + + + GIF6 + Channel 6 Global interrupt + flag + 20 + 1 + + + TCIF6 + Channel 6 Transfer Complete + flag + 21 + 1 + + + HTIF6 + Channel 6 Half Transfer Complete + flag + 22 + 1 + + + TEIF6 + Channel 6 Transfer Error + flag + 23 + 1 + + + GIF7 + Channel 7 Global interrupt + flag + 24 + 1 + + + TCIF7 + Channel 7 Transfer Complete + flag + 25 + 1 + + + HTIF7 + Channel 7 Half Transfer Complete + flag + 26 + 1 + + + TEIF7 + Channel 7 Transfer Error + flag + 27 + 1 + + + + + INTFCR + INTFCR + DMA interrupt flag clear register + (DMA_INTFCR) + 0x4 + 0x20 + write-only + 0x00000000 + + + CGIF1 + Channel 1 Global interrupt + clear + 0 + 1 + + + CGIF2 + Channel 2 Global interrupt + clear + 4 + 1 + + + CGIF3 + Channel 3 Global interrupt + clear + 8 + 1 + + + CGIF4 + Channel 4 Global interrupt + clear + 12 + 1 + + + CGIF5 + Channel 5 Global interrupt + clear + 16 + 1 + + + CGIF6 + Channel 6 Global interrupt + clear + 20 + 1 + + + CGIF7 + Channel 7 Global interrupt + clear + 24 + 1 + + + CTCIF1 + Channel 1 Transfer Complete + clear + 1 + 1 + + + CTCIF2 + Channel 2 Transfer Complete + clear + 5 + 1 + + + CTCIF3 + Channel 3 Transfer Complete + clear + 9 + 1 + + + CTCIF4 + Channel 4 Transfer Complete + clear + 13 + 1 + + + CTCIF5 + Channel 5 Transfer Complete + clear + 17 + 1 + + + CTCIF6 + Channel 6 Transfer Complete + clear + 21 + 1 + + + CTCIF7 + Channel 7 Transfer Complete + clear + 25 + 1 + + + CHTIF1 + Channel 1 Half Transfer + clear + 2 + 1 + + + CHTIF2 + Channel 2 Half Transfer + clear + 6 + 1 + + + CHTIF3 + Channel 3 Half Transfer + clear + 10 + 1 + + + CHTIF4 + Channel 4 Half Transfer + clear + 14 + 1 + + + CHTIF5 + Channel 5 Half Transfer + clear + 18 + 1 + + + CHTIF6 + Channel 6 Half Transfer + clear + 22 + 1 + + + CHTIF7 + Channel 7 Half Transfer + clear + 26 + 1 + + + CTEIF1 + Channel 1 Transfer Error + clear + 3 + 1 + + + CTEIF2 + Channel 2 Transfer Error + clear + 7 + 1 + + + CTEIF3 + Channel 3 Transfer Error + clear + 11 + 1 + + + CTEIF4 + Channel 4 Transfer Error + clear + 15 + 1 + + + CTEIF5 + Channel 5 Transfer Error + clear + 19 + 1 + + + CTEIF6 + Channel 6 Transfer Error + clear + 23 + 1 + + + CTEIF7 + Channel 7 Transfer Error + clear + 27 + 1 + + + + + CFGR1 + CFGR1 + DMA channel configuration register + (DMA_CFGR) + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR1 + CNTR1 + DMA channel 1 number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR1 + PADDR1 + DMA channel 1 peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR1 + MADDR1 + DMA channel 1 memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR2 + CFGR2 + DMA channel configuration register + (DMA_CFGR) + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR2 + CNTR2 + DMA channel 2 number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR2 + PADDR2 + DMA channel 2 peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR2 + MADDR2 + DMA channel 2 memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR3 + CFGR3 + DMA channel configuration register + (DMA_CFGR) + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR3 + CNTR3 + DMA channel 3 number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR3 + PADDR3 + DMA channel 3 peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR3 + MADDR3 + DMA channel 3 memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR4 + CFGR4 + DMA channel configuration register + (DMA_CFGR) + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR4 + CNTR4 + DMA channel 4 number of data + register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR4 + PADDR4 + DMA channel 4 peripheral address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR4 + MADDR4 + DMA channel 4 memory address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR5 + CFGR5 + DMA channel configuration register + (DMA_CFGR) + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR5 + CNTR5 + DMA channel 5 number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR5 + PADDR5 + DMA channel 5 peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR5 + MADDR5 + DMA channel 5 memory address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR6 + CFGR6 + DMA channel configuration register + (DMA_CFGR) + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR6 + CNTR6 + DMA channel 6 number of data + register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR6 + PADDR6 + DMA channel 6 peripheral address + register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR6 + MADDR6 + DMA channel 6 memory address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR7 + CFGR7 + DMA channel configuration register + (DMA_CFGR) + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR7 + CNTR7 + DMA channel 7 number of data + register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR7 + PADDR7 + DMA channel 7 peripheral address + register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR7 + MADDR7 + DMA channel 7 memory address + register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR8 + CFGR8 + DMA channel configuration register + (DMA_CFGR) used in ch32v30x_D8/D8C + 0x90 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR8 + CNTR8 + DMA channel 8 number of data + register used in ch32v30x_D8/D8C + 0x94 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR8 + PADDR8 + DMA channel 8 peripheral address + register used in ch32v30x_D8/D8C + 0x98 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR8 + MADDR8 + DMA channel 8 memory address + register used in ch32v30x_D8/D8C + 0x9C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR9 + CFGR9 + DMA channel configuration register + (DMA_CFGR) used in ch32v30x_D8/D8C + 0xA0 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR9 + CNTR9 + DMA channel 9 number of data + register used in ch32v30x_D8/D8C + 0xA4 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR9 + PADDR7 + DMA channel 7 peripheral address + register used in ch32v30x_D8/D8C + 0xA8 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR9 + MADDR9 + DMA channel 9 memory address + register used in ch32v30x_D8/D8C + 0xAC + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR10 + CFGR10 + DMA channel configuration register + (DMA_CFGR) used in ch32v30x_D8/D8C + 0xB0 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR10 + CNTR10 + DMA channel 10 number of data + register used in ch32v30x_D8/D8C + 0xB4 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR10 + PADDR10 + DMA channel 10 peripheral address + register used in ch32v30x_D8/D8C + 0xB8 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR10 + MADDR10 + DMA channel 10 memory address + register used in ch32v30x_D8/D8C + 0xBC + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CFGR11 + CFGR11 + DMA channel configuration register + (DMA_CFGR) used in ch32v30x_D8/D8C + 0xC0 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNTR11 + CNTR11 + DMA channel 11 number of data + register used in ch32v30x_D8/D8C + 0xC4 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + PADDR11 + PADDR11 + DMA channel 11 peripheral address + register used in ch32v30x_D8/D8C + 0xC8 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + MADDR11 + MADDR11 + DMA channel 11 memory address + register used in ch32v30x_D8/D8C + 0xCC + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + EXTEN_INTFR + INTFR + DMA2 EXTEN interrupt status register + (DMA_INTFR)used in ch32v30x_D8/D8C + 0xD0 + 0x20 + read-only + 0x00000000 + + + GIF8 + Channel 8 Global interrupt + flag + 0 + 1 + + + TCIF8 + Channel 8 Transfer Complete + flag + 1 + 1 + + + HTIF8 + Channel 8 Half Transfer Complete + flag + 2 + 1 + + + TEIF8 + Channel 8 Transfer Error + flag + 3 + 1 + + + GIF9 + Channel 9 Global interrupt + flag + 4 + 1 + + + TCIF9 + Channel 9 Transfer Complete + flag + 5 + 1 + + + HTIF9 + Channel 9 Half Transfer Complete + flag + 6 + 1 + + + TEIF9 + Channel 9 Transfer Error + flag + 7 + 1 + + + GIF10 + Channel 10 Global interrupt + flag + 8 + 1 + + + TCIF10 + Channel 10 Transfer Complete + flag + 9 + 1 + + + HTIF10 + Channel 10 Half Transfer Complete + flag + 10 + 1 + + + TEIF10 + Channel 10 Transfer Error + flag + 11 + 1 + + + GIF11 + Channel 11 Global interrupt + flag + 12 + 1 + + + TCIF11 + Channel 11 Transfer Complete + flag + 13 + 1 + + + HTIF11 + Channel 11 Half Transfer Complete + flag + 14 + 1 + + + TEIF11 + Channel 11 Transfer Error + flag + 15 + 1 + + + + + EXTEN_INTFCR + INTFCR + DMA2 EXTEN interrupt flag clear register + (DMA_INTFCR)used in ch32v30x_D8/D8C + 0xD4 + 0x20 + read-write + 0x00000000 + + + CGIF8 + Channel 8 Global interrupt + clear + 0 + 1 + + + CGIF9 + Channel 9 Global interrupt + clear + 4 + 1 + + + CGIF10 + Channel 10 Global interrupt + clear + 8 + 1 + + + CGIF11 + Channel 11 Global interrupt + clear + 12 + 1 + + + CTCIF8 + Channel 8 Global interrupt + clear + 1 + 1 + + + CTCIF9 + Channel 9 Global interrupt + clear + 5 + 1 + + + CTCIF10 + Channel 10 Global interrupt + clear + 9 + 1 + + + CTCIF11 + Channel 11 Global interrupt + clear + 13 + 1 + + + CHTIF8 + Channel 8 Global interrupt + clear + 2 + 1 + + + CHTIF9 + Channel 9 Global interrupt + clear + 6 + 1 + + + CHTIF10 + Channel 10 Global interrupt + clear + 10 + 1 + + + CHTIF11 + Channel 11 Global interrupt + clear + 14 + 1 + + + CTEIF8 + Channel 8 Global interrupt + clear + 3 + 1 + + + CTEIF9 + Channel 9 Global interrupt + clear + 7 + 1 + + + CTEIF10 + Channel 10 Global interrupt + clear + 11 + 1 + + + CTEIF11 + Channel 11 Global interrupt + clear + 15 + 1 + + + + + + + RTC + Real time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC global interrupt + 19 + + + RTCAlarm + RTC Alarms through EXTI line + interrupt + 57 + + + + CTLRH + CTLRH + RTC Control Register High + 0x0 + 0x20 + read-write + 0x00000000 + + + SECIE + Second interrupt Enable + 0 + 1 + + + ALRIE + Alarm interrupt Enable + 1 + 1 + + + OWIE + Overflow interrupt Enable + 2 + 1 + + + + + CTLRL + CTLRL + RTC Control Register Low + 0x4 + 0x20 + 0x00000020 + + + SECF + Second Flag + 0 + 1 + read-write + + + ALRF + Alarm Flag + 1 + 1 + read-write + + + OWF + Overflow Flag + 2 + 1 + read-write + + + RSF + Registers Synchronized + Flag + 3 + 1 + read-write + + + CNF + Configuration Flag + 4 + 1 + read-write + + + RTOFF + RTC operation OFF + 5 + 1 + read-only + + + + + PSCRH + PSCRH + RTC Prescaler Load Register + High + 0x8 + 0x20 + write-only + 0x00000000 + + + PRLH + RTC Prescaler Load Register + High + 0 + 4 + + + + + PSCRL + PSCRL + RTC Prescaler Load Register + Low + 0xC + 0x20 + write-only + 0x8000 + + + PRLL + RTC Prescaler Divider Register + Low + 0 + 16 + + + + + DIVH + DIVH + RTC Prescaler Divider Register + High + 0x10 + 0x20 + read-only + 0x00000000 + + + DIVH + RTC prescaler divider register + high + 0 + 4 + + + + + DIVL + DIVL + RTC Prescaler Divider Register + Low + 0x14 + 0x20 + read-only + 0x8000 + + + DIVL + RTC prescaler divider register + Low + 0 + 16 + + + + + CNTH + CNTH + RTC Counter Register High + 0x18 + 0x20 + read-write + 0x00000000 + + + CNTH + RTC counter register high + 0 + 16 + + + + + CNTL + CNTL + RTC Counter Register Low + 0x1C + 0x20 + read-write + 0x00000000 + + + CNTL + RTC counter register Low + 0 + 16 + + + + + ALRMH + ALRMH + RTC Alarm Register High + 0x20 + 0x20 + write-only + 0xFFFF + + + ALRH + RTC alarm register high + 0 + 16 + + + + + ALRML + ALRML + RTC Alarm Register Low + 0x24 + 0x20 + write-only + 0xFFFF + + + ALRL + RTC alarm register low + 0 + 16 + + + + + + + BKP + Backup registers + BKP + 0x40006C00 + + 0x0 + 0x400 + registers + + + + DATAR1 + DATAR1 + Backup data register (BKP_DR) + 0x4 + 0x20 + read-write + 0x00000000 + + + D1 + Backup data + 0 + 16 + + + + + DATAR2 + DATAR2 + Backup data register (BKP_DR) + 0x8 + 0x20 + read-write + 0x00000000 + + + D2 + Backup data + 0 + 16 + + + + + DATAR3 + DATAR3 + Backup data register (BKP_DR) + 0xC + 0x20 + read-write + 0x00000000 + + + D3 + Backup data + 0 + 16 + + + + + DATAR4 + DATAR4 + Backup data register (BKP_DR) + 0x10 + 0x20 + read-write + 0x00000000 + + + D4 + Backup data + 0 + 16 + + + + + DATAR5 + DATAR5 + Backup data register (BKP_DR) + 0x14 + 0x20 + read-write + 0x00000000 + + + D5 + Backup data + 0 + 16 + + + + + DATAR6 + DATAR6 + Backup data register (BKP_DR) + 0x18 + 0x20 + read-write + 0x00000000 + + + D6 + Backup data + 0 + 16 + + + + + DATAR7 + DATAR7 + Backup data register (BKP_DR) + 0x1C + 0x20 + read-write + 0x00000000 + + + D7 + Backup data + 0 + 16 + + + + + DATAR8 + DATAR8 + Backup data register (BKP_DR) + 0x20 + 0x20 + read-write + 0x00000000 + + + D8 + Backup data + 0 + 16 + + + + + DATAR9 + DATAR9 + Backup data register (BKP_DR) + 0x24 + 0x20 + read-write + 0x00000000 + + + D9 + Backup data + 0 + 16 + + + + + DATAR10 + DATAR10 + Backup data register (BKP_DR) + 0x28 + 0x20 + read-write + 0x00000000 + + + D10 + Backup data + 0 + 16 + + + + + DATAR11 + DATAR11 + Backup data register (BKP_DR) + 0x40 + 0x20 + read-write + 0x00000000 + + + DR11 + Backup data + 0 + 16 + + + + + DATAR12 + DATAR12 + Backup data register (BKP_DR) + 0x44 + 0x20 + read-write + 0x00000000 + + + DR12 + Backup data + 0 + 16 + + + + + DATAR13 + DATAR13 + Backup data register (BKP_DR) + 0x48 + 0x20 + read-write + 0x00000000 + + + DR13 + Backup data + 0 + 16 + + + + + DATAR14 + DATAR14 + Backup data register (BKP_DR) + 0x4C + 0x20 + read-write + 0x00000000 + + + D14 + Backup data + 0 + 16 + + + + + DATAR15 + DATAR15 + Backup data register (BKP_DR) + 0x50 + 0x20 + read-write + 0x00000000 + + + D15 + Backup data + 0 + 16 + + + + + DATAR16 + DATAR16 + Backup data register (BKP_DR) + 0x54 + 0x20 + read-write + 0x00000000 + + + D16 + Backup data + 0 + 16 + + + + + DATAR17 + DATAR17 + Backup data register (BKP_DR) + 0x58 + 0x20 + read-write + 0x00000000 + + + D17 + Backup data + 0 + 16 + + + + + DATAR18 + DATAR18 + Backup data register (BKP_DR) + 0x5C + 0x20 + read-write + 0x00000000 + + + D18 + Backup data + 0 + 16 + + + + + DATAR19 + DATAR19 + Backup data register (BKP_DR) + 0x60 + 0x20 + read-write + 0x00000000 + + + D19 + Backup data + 0 + 16 + + + + + DATAR20 + DATAR20 + Backup data register (BKP_DR) + 0x64 + 0x20 + read-write + 0x00000000 + + + D20 + Backup data + 0 + 16 + + + + + DATAR21 + DATAR21 + Backup data register (BKP_DR) + 0x68 + 0x20 + read-write + 0x00000000 + + + D21 + Backup data + 0 + 16 + + + + + DATAR22 + DATAR22 + Backup data register (BKP_DR) + 0x6C + 0x20 + read-write + 0x00000000 + + + D22 + Backup data + 0 + 16 + + + + + DATAR23 + DATAR23 + Backup data register (BKP_DR) + 0x70 + 0x20 + read-write + 0x00000000 + + + D23 + Backup data + 0 + 16 + + + + + DATAR24 + DATAR24 + Backup data register (BKP_DR) + 0x74 + 0x20 + read-write + 0x00000000 + + + D24 + Backup data + 0 + 16 + + + + + DATAR25 + DATAR25 + Backup data register (BKP_DR) + 0x78 + 0x20 + read-write + 0x00000000 + + + D25 + Backup data + 0 + 16 + + + + + DATAR26 + DATAR26 + Backup data register (BKP_DR) + 0x7C + 0x20 + read-write + 0x00000000 + + + D26 + Backup data + 0 + 16 + + + + + DATAR27 + DATAR27 + Backup data register (BKP_DR) + 0x80 + 0x20 + read-write + 0x00000000 + + + D27 + Backup data + 0 + 16 + + + + + DATAR28 + DATAR28 + Backup data register (BKP_DR) + 0x84 + 0x20 + read-write + 0x00000000 + + + D28 + Backup data + 0 + 16 + + + + + DATAR29 + DATAR29 + Backup data register (BKP_DR) + 0x88 + 0x20 + read-write + 0x00000000 + + + D29 + Backup data + 0 + 16 + + + + + DATAR30 + DATAR30 + Backup data register (BKP_DR) + 0x8C + 0x20 + read-write + 0x00000000 + + + D30 + Backup data + 0 + 16 + + + + + DATAR31 + DATAR31 + Backup data register (BKP_DR) + 0x90 + 0x20 + read-write + 0x00000000 + + + D31 + Backup data + 0 + 16 + + + + + DATAR32 + DATAR32 + Backup data register (BKP_DR) + 0x94 + 0x20 + read-write + 0x00000000 + + + D32 + Backup data + 0 + 16 + + + + + DATAR33 + DATAR33 + Backup data register (BKP_DR) + 0x98 + 0x20 + read-write + 0x00000000 + + + D33 + Backup data + 0 + 16 + + + + + DATAR34 + DATAR34 + Backup data register (BKP_DR) + 0x9C + 0x20 + read-write + 0x00000000 + + + D34 + Backup data + 0 + 16 + + + + + DATAR35 + DATAR35 + Backup data register (BKP_DR) + 0xA0 + 0x20 + read-write + 0x00000000 + + + D35 + Backup data + 0 + 16 + + + + + DATAR36 + DATAR36 + Backup data register (BKP_DR) + 0xA4 + 0x20 + read-write + 0x00000000 + + + D36 + Backup data + 0 + 16 + + + + + DATAR37 + DATAR37 + Backup data register (BKP_DR) + 0xA8 + 0x20 + read-write + 0x00000000 + + + D37 + Backup data + 0 + 16 + + + + + DATAR38 + DATAR38 + Backup data register (BKP_DR) + 0xAC + 0x20 + read-write + 0x00000000 + + + D38 + Backup data + 0 + 16 + + + + + DATAR39 + DATAR39 + Backup data register (BKP_DR) + 0xB0 + 0x20 + read-write + 0x00000000 + + + D39 + Backup data + 0 + 16 + + + + + DATAR40 + DATAR40 + Backup data register (BKP_DR) + 0xB4 + 0x20 + read-write + 0x00000000 + + + D40 + Backup data + 0 + 16 + + + + + DATAR41 + DATAR41 + Backup data register (BKP_DR) + 0xB8 + 0x20 + read-write + 0x00000000 + + + D41 + Backup data + 0 + 16 + + + + + DATAR42 + DATAR42 + Backup data register (BKP_DR) + 0xBC + 0x20 + read-write + 0x00000000 + + + D42 + Backup data + 0 + 16 + + + + + OCTLR + OCTLR + RTC clock calibration register + (BKP_OCTLR) + 0x2C + 0x20 + read-write + 0x00000000 + + + CAL + Calibration value + 0 + 7 + + + CCO + Calibration Clock Output + 7 + 1 + + + ASOE + Alarm or second output + enable + 8 + 1 + + + ASOS + Alarm or second output + selection + 9 + 1 + + + + + TPCTLR + TPCTLR + Backup control register + (BKP_TPCTLR) + 0x30 + 0x20 + read-write + 0x00000000 + + + TPE + Tamper pin enable + 0 + 1 + + + TPAL + Tamper pin active level + 1 + 1 + + + + + TPCSR + TPCSR + BKP_TPCSR control/status register + (BKP_CSR) + 0x34 + 0x20 + 0x00000000 + + + CTE + Clear Tamper event + 0 + 1 + write-only + + + CTI + Clear Tamper Interrupt + 1 + 1 + write-only + + + TPIE + Tamper Pin interrupt + enable + 2 + 1 + read-write + + + TEF + Tamper Event Flag + 8 + 1 + read-only + + + TIF + Tamper Interrupt Flag + 9 + 1 + read-only + + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + CTLR + CTLR + Key register (IWDG_CTLR) + 0x0 + 0x20 + write-only + 0x0000 + + + KEY + Key value + 0 + 16 + write-only + + + + + PSCR + PSCR + Prescaler register (IWDG_PSCR) + 0x4 + 0x20 + read-write + 0x0000 + + + PR + Prescaler divider + 0 + 3 + read-write + + + + + RLDR + RLDR + Reload register (IWDG_RLDR) + 0x8 + 0x20 + read-write + 0x0FFF + + + RL + Watchdog counter reload + value + 0 + 12 + read-write + + + + + STATR + STATR + Status register (IWDG_SR) + 0xC + 0x20 + read-only + 0x0000 + + + PVU + Watchdog prescaler value + update + 0 + 1 + read-only + + + RVU + Watchdog counter reload value + update + 1 + 1 + read-only + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 16 + + + + CTLR + CTLR + Control register (WWDG_CR) + 0x0 + 0x20 + read-write + 0x007F + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + read-write + + + WDGA + Activation bit + 7 + 1 + read-write + + + + + CFGR + CFGR + Configuration register + (WWDG_CFR) + 0x4 + 0x20 + read-write + 0x007F + + + W + 7-bit window value + 0 + 7 + read-write + + + WDGTB + Timer Base + 7 + 2 + read-write + + + EWI + Early Wakeup Interrupt + 9 + 1 + read-write + + + + + STATR + STATR + Status register (WWDG_SR) + 0x8 + 0x20 + read-write + 0x0000 + + + WEIF + Early Wakeup Interrupt Flag + 0 + 1 + read-write + + + + + + + TIM1 + Advanced timer + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK + TIM1 Break + interrupt + 40 + + + TIM1_UP_ + TIM1 Update + interrupt + 41 + + + TIM1_TRG_COM + TIM1 Trigger and Commutation interrupts + 42 + + + TIM1_CC + TIM1 Capture Compare interrupt + 43 + + + + CTLR1 + CTLR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTLR2 + CTLR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCFGR + SMCFGR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DMAINTENR + DMAINTENR + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + INTFR + INTFR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + SWEVGR + SWEVGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CHCTLR1_Output + CHCTLR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CHCTLR1_Input + CHCTLR1_Input + capture/compare mode register 1 (input + mode) + CHCTLR1_Output + 0x18 + 0x20 + read-write + 0x0000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CHCTLR2_Output + CHCTLR2_Output + capture/compare mode register (output + mode) + 0x1C + 0x20 + read-write + 0x0000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CHCTLR2_Input + CHCTLR2_Input + capture/compare mode register 2 (input + mode) + CHCTLR2_Output + 0x1C + 0x20 + read-write + 0x0000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x0000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ATRLR + ATRLR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000 + + + ATRLR + Auto-reload value + 0 + 16 + + + + + RPTCR + RPTCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + RPTCR + Repetition counter value + 0 + 8 + + + + + CH1CVR + CH1CVR + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x0000 + + + CH1CVR + Capture/Compare 1 value + 0 + 16 + + + + + CH2CVR + CH2CVR + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x0000 + + + CH2CVR + Capture/Compare 2 value + 0 + 16 + + + + + CH3CVR + CH3CVR + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x0000 + + + CH3CVR + Capture/Compare value + 0 + 16 + + + + + CH4CVR + CH4CVR + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x0000 + + + CH4CVR + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + DMACFGR + DMACFGR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAADR + DMAADR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAADR + DMA register for burst + accesses + 0 + 16 + + + + + + + TIM8 + 0x40013400 + + TIM8_BRK + TIM8 Break + interrupt + 59 + + + TIM8_UP_ + TIM8 Update + interrupt + 60 + + + TIM8_TRG_COM + TIM8 Trigger and Commutation interrupts + 61 + + + TIM8_CC + TIM8 Capture Compare interrupt + 62 + + + + TIM9 + 0x40014C00 + + TIM9_BRK + TIM9 Break + interrupt + 90 + + + TIM9_UP_ + TIM9 Update + interrupt + 91 + + + TIM9_TRG_COM + TIM9 Trigger and Commutation interrupts + 92 + + + TIM9_CC + TIM9 Capture Compare interrupt + 93 + + + + TIM10 + 0x40015000 + + TIM10_BRK + TIM10 Break + interrupt + 94 + + + TIM10_UP_ + TIM10 Update + interrupt + 95 + + + TIM10_TRG_COM + TIM10 Trigger and Commutation interrupts + 96 + + + TIM10_CC + TIM10 Capture Compare interrupt + 97 + + + + TIM2 + General purpose timer + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 44 + + + + CTLR1 + CTLR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTLR2 + CTLR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Update selection + 2 + 1 + + + CCPC + Compare selection + 0 + 1 + + + + + SMCFGR + SMCFGR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DMAINTENR + DMAINTENR + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request + enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + INTFR + INTFR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + SWEVGR + SWEVGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Brake generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/compare + generation + 5 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CHCTLR1_Output + CHCTLR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x0000 + + + OC2CE + Output compare 2 clear + enable + 15 + 1 + + + OC2M + Output compare 2 mode + 12 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Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CHCTLR2_Input + CHCTLR2_Input + capture/compare mode register 2 (input + mode) + CHCTLR2_Output + 0x1C + 0x20 + read-write + 0x0000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x0000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ATRLR + ATRLR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000 + + + ATRLR + Auto-reload value + 0 + 16 + + + + + CH1CVR + CH1CVR + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x0000 + + + CH1CVR + Capture/Compare 1 value + 0 + 16 + + + + + CH2CVR + CH2CVR + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x0000 + + + CH2CVR + Capture/Compare 2 value + 0 + 16 + + + + + CH3CVR + CH3CVR + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x0000 + + + CH3CVR + Capture/Compare value + 0 + 16 + + + + + CH4CVR + CH4CVR + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x0000 + + + CH4CVR + Capture/Compare value + 0 + 16 + + + + + DMACFGR + DMACFGR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAADR + DMAADR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAADR + DMA register for burst + accesses + 0 + 16 + + + + + + + TIM3 + 0x40000400 + + TIM3 + TIM3 global interrupt + 45 + + + + TIM4 + 0x40000800 + + TIM4 + TIM4 global interrupt + 46 + + + + TIM5 + 0x40000C00 + + TIM5 + TIM5 global interrupt + 66 + + + +TIM6 +Basic timer +TIM +0x40001000 + + 0x0 + 0x400 + registers + + + TIM6 + TIM6 Basic + interrupt + 70 + + + + CTLR1 + CTLR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTLR2 + CTLR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + DMAINTENR + DMAINTENR + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + INTFR + INTFR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + SWEVGR + SWEVGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x0000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ATRLR + ATRLR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000 + + + ATRLR + Auto-reload value + 0 + 16 + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM8 Basic + interrupt + 71 + + + + I2C1 + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1 event interrupt + 47 + + + I2C1_ER + I2C1 error interrupt + 48 + + + + CTLR1 + CTLR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SWRST + Software reset + 15 + 1 + + + ALERT + SMBus alert + 13 + 1 + + + PEC + Packet error checking + 12 + 1 + + + POS + Acknowledge/PEC Position (for data + reception) + 11 + 1 + + + ACK + Acknowledge enable + 10 + 1 + + + STOP + Stop generation + 9 + 1 + + + START + Start generation + 8 + 1 + + + NOSTRETCH + Clock stretching disable (Slave + mode) + 7 + 1 + + + ENGC + General call enable + 6 + 1 + + + ENPEC + PEC enable + 5 + 1 + + + ENARP + ARP enable + 4 + 1 + + + SMBTYPE + SMBus type + 3 + 1 + + + SMBUS + SMBus mode + 1 + 1 + + + PE + Peripheral enable + 0 + 1 + + + + + CTLR2 + CTLR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + LAST + DMA last transfer + 12 + 1 + + + DMAEN + DMA requests enable + 11 + 1 + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + + ITEVTEN + Event interrupt enable + 9 + 1 + + + ITERREN + Error interrupt enable + 8 + 1 + + + FREQ + Peripheral clock frequency + 0 + 6 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADDMODE + Addressing mode (slave + mode) + 15 + 1 + + + MUST1 + Must be 1 + 14 + 1 + + + ADD9_8 + Interface address + 8 + 2 + + + ADD7_1 + Interface address + 1 + 7 + + + ADD0 + Interface address + 0 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x0000 + + + ADD2 + Interface address + 1 + 7 + + + ENDUAL + Dual addressing mode + enable + 0 + 1 + + + + + DATAR + DATAR + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DATAR + 8-bit data register + 0 + 8 + + + + + STAR1 + STAR1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + SMBALERT + SMBus alert + 15 + 1 + read-write + + + TIMEOUT + Timeout or Tlow error + 14 + 1 + read-write + + + PECERR + PEC Error in reception + 12 + 1 + read-write + + + OVR + Overrun/Underrun + 11 + 1 + read-write + + + AF + Acknowledge failure + 10 + 1 + read-write + + + ARLO + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TxE + Data register empty + (transmitters) + 7 + 1 + read-only + + + RxNE + Data register not empty + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADD10 + 10-bit header sent (Master + mode) + 3 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + + ADDR + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + + + + STAR2 + STAR2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PEC + acket error checking + register + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + SMBHOST + SMBus host header (Slave + mode) + 6 + 1 + + + SMBDEFAULT + SMBus device default address (Slave + mode) + 5 + 1 + + + GENCALL + General call address (Slave + mode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CKCFGR + CKCFGR + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + F_S + I2C master mode selection + 15 + 1 + + + DUTY + Fast mode duty cycle + 14 + 1 + + + CCR + Clock control register in Fast/Standard + mode (Master mode) + 0 + 12 + + + + + RTR + RTR + Raise time register + 0x20 + 0x20 + read-write + 0x0002 + + + TRISE + Maximum rise time in Fast/Standard mode + (Master mode) + 0 + 6 + + + + + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2 event interrupt + 49 + + + I2C2_ER + I2C2 error interrupt + 50 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 51 + + + + CTLR1 + CTLR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CTLR2 + CTLR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + STATR + STATR + status register + 0x8 + 0x20 + 0x0002 + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + UDR + Underrun flag + 3 + 1 + read-only + + + CHSID + Channel side + 2 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DATAR + DATAR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DATAR + Data register + 0 + 16 + + + + + CRCR + CRCR + CRCR polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RCRCR + RCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RXCRC + Rx CRC register + 0 + 16 + + + + + TCRCR + TCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TXCRC + Tx CRC register + 0 + 16 + + + + + SPI_I2S_CFGR + SPI_I2S_CFGR + SPI_I2S configure register + 0x1C + 0x20 + read-write + 0x0000 + + + CHLEN + Channel length (number of bits per audio channel) + 0 + 1 + + + DATLEN + DATLEN[1:0] bits (Data length to be transferred) + 1 + 2 + + + CKPOL + steady state clock polarity + 3 + 1 + + + I2SSTD + I2SSTD[1:0] bits (I2S standard selection) + 4 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SCFG + I2SCFG[1:0] bits (I2S configuration mode) + 8 + 2 + + + I2SE + I2S Enable + 10 + 1 + + + I2SMOD + I2S mode selection + 11 + 1 + + + + + HSCR + HSCR + high speed control register + 0x24 + 0x20 + read-write + 0x0000 + + + HSRXEN + High speed mode read enable + 0 + 1 + + + + + + + SPI2 + Serial peripheral interface + SPI + 0x40003800 + + 0x0 + 0x400 + registers + + + SPI2 + SPI2 global interrupt + 52 + + + + CTLR1 + CTLR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CTLR2 + CTLR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + STATR + STATR + status register + 0x8 + 0x20 + 0x0002 + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DATAR + DATAR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DATAR + Data register + 0 + 16 + + + + + CRCR + CRCR + CRCR polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RCRCR + RCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RXCRC + Rx CRC register + 0 + 16 + + + + + TCRCR + TCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TXCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + I2S configuration register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMOD + I2S mode selection + 11 + 1 + + + I2SE + I2S Enable + 10 + 1 + + + I2SCFG + I2S configuration mode + 8 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPOL + Steady state clock + polarity + 3 + 1 + + + DATLEN + Data length to be + transferred + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x20 + read-write + 00000010 + + + MCKOE + Master clock output enable + 9 + 1 + + + ODD + Odd factor for the + prescaler + 8 + 1 + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + + + HSCR + HSCR + high speed control register + 0x24 + 0x20 + read-write + 0x0000 + + + HSRXEN + High speed mode read enable + 0 + 1 + + + + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 67 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 53 + + + + STATR + STATR + Status register + 0x0 + 0x20 + 0x000000C0 + + + CTS + CTS flag + 9 + 1 + read-write + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NE + Noise error flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DATAR + DATAR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CTLR1 + CTLR1 + Control register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CTLR2 + CTLR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + lin break detection length + 5 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CTLR3 + CTLR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x00000000 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + GPR + GPR + Guard time and prescaler + register + 0x18 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 54 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 55 + + + + UART4 + 0x40004C00 + + UART4 + UART4 global interrupt + 68 + + + + UART5 + 0x40005000 + + UART5 + UART5 global interrupt + 69 + + + + UART6 + 0x40001800 + + UART6 + UART6 global interrupt + 87 + + + + UART7 + 0x40001C00 + + UART7 + UART7 global interrupt + 88 + + + + UART8 + 0x40002000 + + UART8 + UART8 global interrupt + 89 + + + + ADC1 + Analog to digital converter + ADC1 + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC + ADC global interrupt + 34 + + + + STATR + STATR + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + STRT + Regular channel start flag + 4 + 1 + + + JSTRT + Injected channel start + flag + 3 + 1 + + + JEOC + Injected channel end of + conversion + 2 + 1 + + + EOC + Regular channel end of + conversion + 1 + 1 + + + AWD + Analog watchdog flag + 0 + 1 + + + + + CTLR1 + CTLR1 + control register 1/TKEY_V_CTLR + 0x4 + 0x20 + read-write + 0x00000000 + + + PGA + ADC_PGA + 27 + 2 + + + BUFEN + TKEY_BUF_Enable + 26 + 1 + + + TKITUNE + TKEY_I enable + 25 + 1 + + + TKEYEN + TKEY enable, including TKEY_F and + TKEY_V + 24 + 1 + + + AWDEN + Analog watchdog enable on regular + channels + 23 + 1 + + + JAWDEN + Analog watchdog enable on injected + channels + 22 + 1 + + + DUALMOD + Dual mode selection + 16 + 4 + + + DISCNUM + Discontinuous mode channel + count + 13 + 3 + + + JDISCEN + Discontinuous mode on injected + channels + 12 + 1 + + + DISCEN + Discontinuous mode on regular + channels + 11 + 1 + + + JAUTO + Automatic injected group + conversion + 10 + 1 + + + AWDSGL + Enable the watchdog on a single channel + in scan mode + 9 + 1 + + + SCAN + Scan mode enable + 8 + 1 + + + JEOCIE + Interrupt enable for injected + channels + 7 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + AWDCH + Analog watchdog channel select + bits + 0 + 5 + + + + + CTLR2 + CTLR2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + TSVREFE + Temperature sensor and VREFINT + enable + 23 + 1 + + + SWSTART + Start conversion of regular + channels + 22 + 1 + + + JSWSTART + Start conversion of injected + channels + 21 + 1 + + + EXTTRIG + External trigger conversion mode for + regular channels + 20 + 1 + + + EXTSEL + External event select for regular + group + 17 + 3 + + + JEXTTRIG + External trigger conversion mode for + injected channels + 15 + 1 + + + JEXTSEL + External event select for injected + group + 12 + 3 + + + ALIGN + Data alignment + 11 + 1 + + + DMA + Direct memory access mode + 8 + 1 + + + RSTCAL + Reset calibration + 3 + 1 + + + CAL + A/D calibration + 2 + 1 + + + CONT + Continuous conversion + 1 + 1 + + + ADON + A/D converter ON / OFF + 0 + 1 + + + + + SAMPTR1_CHARGE1 + SAMPTR1_CHARGE1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SMP10_TKCG10 + Channel 10 sample time + selection + 0 + 3 + + + SMP11_TKCG11 + Channel 11 sample time + selection + 3 + 3 + + + SMP12_TKCG12 + Channel 12 sample time + selection + 6 + 3 + + + SMP13_TKCG13 + Channel 13 sample time + selection + 9 + 3 + + + SMP14_TKCG14 + Channel 14 sample time + selection + 12 + 3 + + + SMP15_TKCG15 + Channel 15 sample time + selection + 15 + 3 + + + SMP16_TKCG16 + Channel 16 sample time + selection + 18 + 3 + + + SMP17_TKCG17 + Channel 17 sample time + selection + 21 + 3 + + + + + SAMPTR2_CHARGE2 + SAMPTR2_CHARGE2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + SMP0_TKCG0 + Channel 0 sample time + selection + 0 + 3 + + + SMP1_TKCG1 + Channel 1 sample time + selection + 3 + 3 + + + SMP2_TKCG2 + Channel 2 sample time + selection + 6 + 3 + + + SMP3_TKCG3 + Channel 3 sample time + selection + 9 + 3 + + + SMP4_TKCG4 + Channel 4 sample time + selection + 12 + 3 + + + SMP5_TKCG5 + Channel 5 sample time + selection + 15 + 3 + + + SMP6_TKCG6 + Channel 6 sample time + selection + 18 + 3 + + + SMP7_TKCG7 + Channel 7 sample time + selection + 21 + 3 + + + SMP8_TKCG8 + Channel 8 sample time + selection + 24 + 3 + + + SMP9_TKCG9 + Channel 9 sample time + selection + 27 + 3 + + + + + IOFR1 + IOFR1 + injected channel data offset register + x + 0x14 + 0x20 + read-write + 0x00000000 + + + JOFFSET1 + Data offset for injected channel + x + 0 + 12 + + + + + IOFR2 + IOFR2 + injected channel data offset register + x + 0x18 + 0x20 + read-write + 0x00000000 + + + JOFFSET2 + Data offset for injected channel + x + 0 + 12 + + + + + IOFR3 + IOFR3 + injected channel data offset register + x + 0x1C + 0x20 + read-write + 0x00000000 + + + JOFFSET3 + Data offset for injected channel + x + 0 + 12 + + + + + IOFR4 + IOFR4 + injected channel data offset register + x + 0x20 + 0x20 + read-write + 0x00000000 + + + JOFFSET4 + Data offset for injected channel + x + 0 + 12 + + + + + WDHTR + WDHTR + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000000 + + + HT + Analog watchdog higher + threshold + 0 + 12 + + + + + WDLTR + WDLTR + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + LT + Analog watchdog lower + threshold + 0 + 12 + + + + + RSQR1 + RSQR1 + regular sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + L + Regular channel sequence + length + 20 + 4 + + + SQ16 + 16th conversion in regular + sequence + 15 + 5 + + + SQ15 + 15th conversion in regular + sequence + 10 + 5 + + + SQ14 + 14th conversion in regular + sequence + 5 + 5 + + + SQ13 + 13th conversion in regular + sequence + 0 + 5 + + + + + RSQR2 + RSQR2 + regular sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ12 + 12th conversion in regular + sequence + 25 + 5 + + + SQ11 + 11th conversion in regular + sequence + 20 + 5 + + + SQ10 + 10th conversion in regular + sequence + 15 + 5 + + + SQ9 + 9th conversion in regular + sequence + 10 + 5 + + + SQ8 + 8th conversion in regular + sequence + 5 + 5 + + + SQ7 + 7th conversion in regular + sequence + 0 + 5 + + + + + RSQR3__CHANNEL + RSQR3__CHANNEL + regular sequence register 3;TKEY_V_CHANNEL + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ6 + 6th conversion in regular + sequence + 25 + 5 + + + SQ5 + 5th conversion in regular + sequence + 20 + 5 + + + SQ4 + 4th conversion in regular + sequence + 15 + 5 + + + SQ3 + 3rd conversion in regular + sequence + 10 + 5 + + + SQ2 + 2nd conversion in regular + sequence + 5 + 5 + + + SQ1__CHSEL + 1st conversion in regular + sequence;TKDY_V channel select + 0 + 5 + + + + + ISQR + ISQR + injected sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + JL + Injected sequence length + 20 + 2 + + + JSQ4 + 4th conversion in injected + sequence + 15 + 5 + + + JSQ3 + 3rd conversion in injected + sequence + 10 + 5 + + + JSQ2 + 2nd conversion in injected + sequence + 5 + 5 + + + JSQ1 + 1st conversion in injected + sequence + 0 + 5 + + + + + IDATAR1_CHGOFFSET + IDATAR1_CHGOFFSET + injected data register x_Charge data offset for injected channel x + 0x3C + 0x20 + read-only + 0x00000000 + + + IDATA0_7_TKCGOFFSET + Injected data_Touch key charge data offset for injected channel x + 0 + 8 + + + IDATA8_15 + Injected data + 8 + 8 + + + + + IDATAR2 + IDATAR2 + injected data register x + 0x40 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + IDATAR3 + IDATAR3 + injected data register x + 0x44 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + IDATAR4 + IDATAR4 + injected data register x + 0x48 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + RDATAR_DR_ACT_DCG + RDATAR_DR_ACT_DCG + regular data register_start and discharge time register + 0x4C + 0x20 + read-write + 0x00000000 + + + DATA0_7_TKACT_DCG + Regular data_Touch key start and discharge time register + 0 + 8 + + + DATA8_15 + Regular data + 8 + 8 + + + + + + + ADC2 + Analog to digital converter + ADC + 0x40012800 + + 0x0 + 0x400 + registers + + + + STATR + STATR + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + STRT + Regular channel start flag + 4 + 1 + + + JSTRT + Injected channel start + flag + 3 + 1 + + + JEOC + Injected channel end of + conversion + 2 + 1 + + + EOC + Regular channel end of + conversion + 1 + 1 + + + AWD + Analog watchdog flag + 0 + 1 + + + + + CTLR1 + CTLR1 + control register 1/TKEY_V_CTLR + 0x4 + 0x20 + read-write + 0x00000000 + + + PGA + ADC_PGA + 27 + 2 + + + BUFEN + TKEY_BUF_Enable + 26 + 1 + + + TKITUNE + TKEY_I enable + 25 + 1 + + + TKEYEN + TKEY enable, including TKEY_F and + TKEY_V + 24 + 1 + + + AWDEN + Analog watchdog enable on regular + channels + 23 + 1 + + + JAWDEN + Analog watchdog enable on injected + channels + 22 + 1 + + + DUALMOD + Dual mode selection + 16 + 4 + + + DISCNUM + Discontinuous mode channel + count + 13 + 3 + + + JDISCEN + Discontinuous mode on injected + channels + 12 + 1 + + + DISCEN + Discontinuous mode on regular + channels + 11 + 1 + + + JAUTO + Automatic injected group + conversion + 10 + 1 + + + AWDSGL + Enable the watchdog on a single channel + in scan mode + 9 + 1 + + + SCAN + Scan mode enable + 8 + 1 + + + JEOCIE + Interrupt enable for injected + channels + 7 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + AWDCH + Analog watchdog channel select + bits + 0 + 5 + + + + + CTLR2 + CTLR2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + TSVREFE + Temperature sensor and VREFINT + enable + 23 + 1 + + + SWSTART + Start conversion of regular + channels + 22 + 1 + + + JSWSTART + Start conversion of injected + channels + 21 + 1 + + + EXTTRIG + External trigger conversion mode for + regular channels + 20 + 1 + + + EXTSEL + External event select for regular + group + 17 + 3 + + + JEXTTRIG + External trigger conversion mode for + injected channels + 15 + 1 + + + JEXTSEL + External event select for injected + group + 12 + 3 + + + ALIGN + Data alignment + 11 + 1 + + + DMA + Direct memory access mode + 8 + 1 + + + RSTCAL + Reset calibration + 3 + 1 + + + CAL + A/D calibration + 2 + 1 + + + CONT + Continuous conversion + 1 + 1 + + + ADON + A/D converter ON / OFF + 0 + 1 + + + + + SAMPTR1_CHARGE1 + SAMPTR1_CHARGE1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SMP10_TKCG10 + Channel 10 sample time + selection + 0 + 3 + + + SMP11_TKCG11 + Channel 11 sample time + selection + 3 + 3 + + + SMP12_TKCG12 + Channel 12 sample time + selection + 6 + 3 + + + SMP13_TKCG13 + Channel 13 sample time + selection + 9 + 3 + + + SMP14_TKCG14 + Channel 14 sample time + selection + 12 + 3 + + + SMP15_TKCG15 + Channel 15 sample time + selection + 15 + 3 + + + SMP16_TKCG16 + Channel 16 sample time + selection + 18 + 3 + + + SMP17_TKCG17 + Channel 17 sample time + selection + 21 + 3 + + + + + SAMPTR2_CHARGE2 + SAMPTR2_CHARGE2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + SMP0_TKCG0 + Channel 0 sample time + selection + 0 + 3 + + + SMP1_TKCG1 + Channel 1 sample time + selection + 3 + 3 + + + SMP2_TKCG2 + Channel 2 sample time + selection + 6 + 3 + + + SMP3_TKCG3 + Channel 3 sample time + selection + 9 + 3 + + + SMP4_TKCG4 + Channel 4 sample time + selection + 12 + 3 + + + SMP5_TKCG5 + Channel 5 sample time + selection + 15 + 3 + + + SMP6_TKCG6 + Channel 6 sample time + selection + 18 + 3 + + + SMP7_TKCG7 + Channel 7 sample time + selection + 21 + 3 + + + SMP8_TKCG8 + Channel 8 sample time + selection + 24 + 3 + + + SMP9_TKCG9 + Channel 9 sample time + selection + 27 + 3 + + + + + IOFR1 + IOFR1 + injected channel data offset register + x + 0x14 + 0x20 + read-write + 0x00000000 + + + JOFFSET1 + Data offset for injected channel + x + 0 + 12 + + + + + IOFR2 + IOFR2 + injected channel data offset register + x + 0x18 + 0x20 + read-write + 0x00000000 + + + JOFFSET2 + Data offset for injected channel + x + 0 + 12 + + + + + IOFR3 + IOFR3 + injected channel data offset register + x + 0x1C + 0x20 + read-write + 0x00000000 + + + JOFFSET3 + Data offset for injected channel + x + 0 + 12 + + + + + IOFR4 + IOFR4 + injected channel data offset register + x + 0x20 + 0x20 + read-write + 0x00000000 + + + JOFFSET4 + Data offset for injected channel + x + 0 + 12 + + + + + WDHTR + WDHTR + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000000 + + + HT + Analog watchdog higher + threshold + 0 + 12 + + + + + WDLTR + WDLTR + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + LT + Analog watchdog lower + threshold + 0 + 12 + + + + + RSQR1 + RSQR1 + regular sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + L + Regular channel sequence + length + 20 + 4 + + + SQ16 + 16th conversion in regular + sequence + 15 + 5 + + + SQ15 + 15th conversion in regular + sequence + 10 + 5 + + + SQ14 + 14th conversion in regular + sequence + 5 + 5 + + + SQ13 + 13th conversion in regular + sequence + 0 + 5 + + + + + RSQR2 + RSQR2 + regular sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ12 + 12th conversion in regular + sequence + 25 + 5 + + + SQ11 + 11th conversion in regular + sequence + 20 + 5 + + + SQ10 + 10th conversion in regular + sequence + 15 + 5 + + + SQ9 + 9th conversion in regular + sequence + 10 + 5 + + + SQ8 + 8th conversion in regular + sequence + 5 + 5 + + + SQ7 + 7th conversion in regular + sequence + 0 + 5 + + + + + RSQR3__CHANNEL + RSQR3__CHANNEL + regular sequence register 3;TKEY_V_CHANNEL + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ6 + 6th conversion in regular + sequence + 25 + 5 + + + SQ5 + 5th conversion in regular + sequence + 20 + 5 + + + SQ4 + 4th conversion in regular + sequence + 15 + 5 + + + SQ3 + 3rd conversion in regular + sequence + 10 + 5 + + + SQ2 + 2nd conversion in regular + sequence + 5 + 5 + + + SQ1__CHSEL + 1st conversion in regular + sequence;TKDY_V channel select + 0 + 5 + + + + + ISQR + ISQR + injected sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + JL + Injected sequence length + 20 + 2 + + + JSQ4 + 4th conversion in injected + sequence + 15 + 5 + + + JSQ3 + 3rd conversion in injected + sequence + 10 + 5 + + + JSQ2 + 2nd conversion in injected + sequence + 5 + 5 + + + JSQ1 + 1st conversion in injected + sequence + 0 + 5 + + + + + IDATAR1_CHGOFFSET + IDATAR1_CHGOFFSET + injected data register x_Charge data offset for injected channel x + 0x3C + 0x20 + read-only + 0x00000000 + + + IDATA0_7_TKCGOFFSET + Injected data_Touch key charge data offset for injected channel x + 0 + 8 + + + IDATA8_15 + Injected data + 8 + 8 + + + + + IDATAR2 + IDATAR2 + injected data register x + 0x40 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + IDATAR3 + IDATAR3 + injected data register x + 0x44 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + IDATAR4 + IDATAR4 + injected data register x + 0x48 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + RDATAR_DR_ACT_DCG + RDATAR_DR_ACT_DCG + regular data register_start and discharge time register + 0x4C + 0x20 + read-write + 0x00000000 + + + DATA0_7_TKACT_DCG + Regular data_Touch key start and discharge time register + 0 + 8 + + + DATA8_15 + Regular data + 8 + 8 + + + + + + + DBG + Debug support + DBG + 0xE000D000 + + 0x0 + 0x400 + registers + + + + CFGR1 + CFGR1 + DBGMCU_CFGR1 + 0x0 + 0x20 + read-write + 0x0 + + + DEG_IWDG + DEG_IWDG + 0 + 1 + + + DEG_WWDG + DEG_WWDG + 1 + 1 + + + DEG_I2C1 + DEG_I2C1 + 2 + 1 + + + DEG_I2C2 + DEG_I2C2 + 3 + 1 + + + DEG_TIM1 + DEG_TIM1 + 4 + 1 + + + DEG_TIM2 + DEG_TIM2 + 5 + 1 + + + DEG_TIM3 + DEG_TIM3 + 6 + 1 + + + DEG_TIM4 + DEG_TIM4 + 7 + 1 + + + + + CFGR2 + CFGR2 + DBGMCU_CFGR2 + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + DBG_SLEEP + 0 + 1 + + + DBG_STOP + DBG_STOP + 1 + 1 + + + DBG_STANDBY + DBG_STANDBY + 2 + 1 + + + + + + + USBHD + USB register + USBHD + 0x40023400 + + 0x00 + 0x400 + registers + + + USBHSWakeup + USBHSWakeup + 84 + + + USBHS + USBHS + 85 + + + + USB_CTRL + USB base control + 0x00 + 0x08 + read-write + 0x06 + + + RB_UC_DMA_EN + DMA enable and DMA interrupt enable for USB + [0:0] + + + RB_UC_CLR_ALL + force clear FIFO and count of USB + [1:1] + + + RB_UC_RESET_SIE + force reset USB SIE, need software clear + [2:2] + + + RB_UC_INT_BUSY + enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid + [3:3] + + + RB_UC_DEV_PU_EN + USB device enable and internal pullup resistance enable + [4:4] + + + RB_UC_SPEED_TYPE + enable USB low speed: 00=full speed, 01=high speed, 10 =low speed + [6:5] + + + RB_UC_HOST_MODE + enable USB host mode: 0=device mode, 1=host mode + [7:7] + + + + + UHOST_CTRL + USB HOST control + 0x01 + 0x08 + + + bUH_TX_BUS_RESET + USB host bus reset status + [0:0] + read-write + + + bUH_TX_BUS_SUSPEND + the host sends hang sigal + [1:1] + read-write + + + bUH_TX_BUS_RESUME + host wake up device + [2:2] + read-write + + + bUH_REMOTE_WKUP + the remoke wake-up + [3:3] + read-write + + + bUH_PHY_SUSPENDM + USB-PHY thesuspended state the internal USB-PLL is turned off + [4:4] + read-write + + + bUH_SOF_FREE + the bus is idle + [6:6] + read-only + + + bUH_SOF_EN + automatically generate the SOF packet enabling control bit + [7:7] + read-write + + + + + USB_INT_EN + USB interrupt enable + 0x02 + 0x08 + read-write + 0x00 + + + RB_UIE_BUS_RST__RB_UIE_DETECT + enable interrupt for USB bus reset event for USB device mode;enable interrupt for USB device detected event for USB host mode + [0:0] + + + RB_UIE_TRANSFER + enable interrupt for USB transfer completion + [1:1] + + + RB_UIE_SUSPEND + enable interrupt for USB suspend or resume event + [2:2] + + + RB_UIE_SOF_ACT + indicate host SOF timer action status for USB host + [3:3] + + + RB_UIE_FIFO_OV + enable interrupt for FIFO overflow + [4:4] + + + RB_UIE_SETUP_ACT + indicate host SETUP timer action status for USB host + [5:5] + + + RB_UIE_ISO_ACT + enable interrupt for NAK responded for USB device mode + [6:6] + + + RB_UIE_DEV_NAK + enable interrupt for NAK responded for USB device mode + [7:7] + + + + + USB_DEV_AD + USB device address + 0x03 + 0x08 + read-write + 0x00 + + + MASK_USB_ADDR + bit mask for USB device address + [6:0] + + + RB_UDA_GP_BIT + general purpose bit + [7:7] + + + + + USB_FRAME_NO + USB_FRAME_NO + 0x04 + 0x10 + read-only + 0x0000 + + + USB_FRAME_NO + USB_FRAME_NO + [15:0] + + + + + USB_USB_SUSPEND + indicate USB suspend status + 0x06 + 0x08 + read-write + 0x00 + + + USB_SYS_MOD + USB_SYS_MOD + [1:0] + + + USB_WAKEUP + remote resume + [2:2] + + + USB_LINESTATE + USB_LINESTATE + [5:4] + + + + + USB_SPEED_TYPE + USB_SPEED_TYPE + 0x08 + 0x08 + read-only + 0x00 + + + USB_SPEED_TYPE + USB_SPEED_TYPE + [1:0] + + + + + USB_MIS_ST + USB miscellaneous status + 0x09 + 0x08 + read-only + 0x00 + + + RB_UMS_SPLIT_CAN + RO, indicate device attached status on USB host + [0:0] + + + RB_UMS_ATTACH + RO, indicate UDM level saved at device attached to USB host + [1:1] + + + RB_UMS_SUSPEND + RO, indicate USB suspend status + [2:2] + + + RB_UMS_BUS_RESET + RO, indicate USB bus reset status + [3:3] + + + RB_UMS_R_FIFO_RDY + RO, indicate USB receiving FIFO ready status (not empty) + [4:4] + + + RB_UMS_SIE_FREE + RO, indicate USB SIE free status + [5:5] + + + RB_UMS_SOF_ACT + RO, indicate host SOF timer action status for USB host + [6:6] + + + RB_UMS_SOF_PRES + RO, indicate host SOF timer presage status + [7:7] + + + + + USB_INT_FG + USB interrupt flag + 0x0A + 0x08 + 0x20 + + + RB_UIF_BUS_RST + RB_UIF_BUS_RST + [0:0] + read-write + + + RB_UIF_TRANSFER + USB transfer completion interrupt flag, direct bit address clear or write 1 to clear + [1:1] + read-write + + + RB_UIF_SUSPEND + USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear + [2:2] + read-write + + + RB_UIF_HST_SOF + host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear + [3:3] + read-write + + + RB_UIF_FIFO_OV + FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear + [4:4] + read-write + + + RB_U_SETUP_ACT + USB_SETUP_ACT + [5:5] + read-only + + + UIF_ISO_ACT + UIF_ISO_ACT + [6:6] + read-only + + + RB_U_IS_NAK + RO, indicate current USB transfer is NAK received + [7:7] + read-only + + + + + USB_INT_ST + USB interrupt status + 0x0B + 0x08 + read-only + + + MASK_UIS_H_RES__MASK_UIS_ENDP + RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received;RO, bit mask of current transfer endpoint number for USB device mode + [3:0] + + + MASK_UIS_TOKEN + RO, bit mask of current token PID code received for USB device mode + [5:4] + + + RB_UIS_TOG_OK + RO, indicate current USB transfer toggle is OK + [6:6] + + + RB_UIS_IS_NAK + RO, indicate current USB transfer is NAK received for USB device mode + [7:7] + + + + + USB_RX_LEN + USB receiving length + 0x0C + 0x10 + read-only + + + R16_USB_RX_LEN + length of received bytes + [15:0] + + + + + UEP_CONFIG + USB endpoint configuration + 0x10 + 0X20 + read-write + + + bUEP_R_EN__UH_EP_MOD + endpoint RX enable/bUH_TX_EN + [31:17] + read-write + + + bUEP_T_EN_bUH_TX_EN + endpoint TX enable/bUH_TX_EN + [15:1] + read-write + + + + + UEP_TYPE + USB endpoint type + 0x14 + 0X20 + read-write + + + bUEP_R_TYPE + endpoint RX type + [31:17] + read-write + + + bUEP_T_TYPE + endpoint TX type + [15:1] + read-write + + + + + UEP_BUF_MOD + USB endpoint buffer mode + 0x18 + 0X20 + read-write + + + bUEP_ISO_BUF_MOD + buffer mode of USB endpoint + [31:16] + read-write + + + bUEP_BUF_MOD + buffer mode of USB endpoint + [15:0] + read-write + + + + + UEP0_DMA + B endpoint 0 DMA buffer address + 0x1C + 0x10 + read-write + + + UEP0_DMA + endpoint 0 DMA buffer address + [15:0] + read-write + + + + + UEP1_RX_DMA + endpoint 1 DMA RX buffer address + 0x20 + 0x10 + read-write + + + UEP1_RX_DMA + endpoint 1 DMA buffer address + [15:0] + read-write + + + + + UEP2_RX_DMA__UH_RX_DMA + endpoint 2 DMA RX buffer address/UH_RX_DMA + 0x24 + 0x10 + read-write + + + UEP2_RX_DMA__UH_RX_DMA + endpoint 2 DMA buffer address + [15:0] + read-write + + + + + UEP3_RX_DMA + endpoint 3 DMA RX buffer address + 0x28 + 0x10 + read-write + + + UEP3_RX_DMA + endpoint 3 DMA buffer address + [15:0] + read-write + + + + + UEP4_RX_DMA + endpoint 4 DMA RX buffer address + 0x2C + 0x10 + read-write + + + UEP4_RX_DMA + endpoint 4 DMA buffer address + [15:0] + read-write + + + + + UEP5_RX_DMA + endpoint 5 DMA RX buffer address + 0x30 + 0x10 + read-write + + + UEP5_DMA + endpoint 5 DMA buffer address + [15:0] + read-write + + + + + UEP6_RX_DMA + endpoint 6 DMA RX buffer address + 0x34 + 0x10 + read-write + + + UEP6_RX_DMA + endpoint 6 DMA buffer address + [15:0] + read-write + + + + + UEP7_RX_DMA + endpoint 7 DMA RX buffer address + 0x38 + 0x10 + read-write + + + UEP7_RX_DMA + endpoint 7 DMA buffer address + [15:0] + read-write + + + + + UEP8_RX_DMA + endpoint 8 DMA RX buffer address + 0x3C + 0x10 + read-write + + + UEP8_RX_DMA + endpoint 8 DMA buffer address + [15:0] + read-write + + + + + UEP9_RX_DMA + endpoint 9 DMA RX buffer address + 0x40 + 0x10 + read-write + + + UEP9_RX_DMA + endpoint 9 DMA buffer address + [15:0] + read-write + + + + + UEP10_RX_DMA + endpoint 10 DMA RX buffer address + 0x44 + 0x10 + read-write + + + UEP10_RX_DMA + endpoint 10 DMA buffer address + [15:0] + read-write + + + + + UEP11_RX_DMA + endpoint 11 DMA RX buffer address + 0x48 + 0x10 + read-write + + + UEP11_RX_DMA + endpoint 11 DMA buffer address + [15:0] + read-write + + + + + UEP12_RX_DMA + endpoint 12 DMA RX buffer address + 0x4C + 0x10 + read-write + + + UEP12_RX_DMA + endpoint 12 DMA buffer address + [15:0] + read-write + + + + + UEP13_RX_DMA + endpoint 13 DMA RX buffer address + 0x50 + 0x10 + read-write + + + UEP13_RX_DMA + endpoint 13 DMA buffer address + [15:0] + read-write + + + + + UEP14_RX_DMA + endpoint 14 DMA RX buffer address + 0x54 + 0x10 + read-write + + + UEP14_RX_DMA + endpoint 14 DMA buffer address + [15:0] + read-write + + + + + UEP15_RX_DMA + endpoint 15 DMA RX buffer address + 0x58 + 0x10 + read-write + + + UEP15_RX_DMA + endpoint 15 DMA buffer address + [15:0] + read-write + + + + + UEP1_TX_DMA + endpoint 1 DMA TX buffer address + 0X5C + 0x10 + read-write + + + UEP1_TX_DMA + endpoint 1 DMA buffer address + [15:0] + read-write + + + + + UEP2_TX_DMA + endpoint 2 DMA TX buffer address + 0x60 + 0x10 + read-write + + + UEP2_TX_DMA + endpoint 2 DMA buffer address + [15:0] + read-write + + + + + UEP3_TX_DMA__UH_TX_DMA + endpoint 3 DMA TX buffer address + 0x64 + 0x10 + read-write + + + UEP3_TX_DMA__UH_TX_DMA + endpoint 3 DMA buffer address + [15:0] + read-write + + + + + UEP4_TX_DMA + endpoint 4 DMA TX buffer address + 0x68 + 0x10 + read-write + + + UEP4_TX_DMA + endpoint 4 DMA buffer address + [15:0] + read-write + + + + + UEP5_TX_DMA + endpoint 5 DMA TX buffer address + 0x6C + 0x10 + read-write + + + UEP5_TX_DMA + endpoint 5 DMA buffer address + [15:0] + read-write + + + + + UEP6_TX_DMA + endpoint 6 DMA TX buffer address + 0x70 + 0x10 + read-write + + + UEP6_TX_DMA + endpoint 6 DMA buffer address + [15:0] + read-write + + + + + UEP7_TX_DMA + endpoint 7 DMA TX buffer address + 0x74 + 0x10 + read-write + + + UEP7_TX_DMA + endpoint 7 DMA buffer address + [15:0] + read-write + + + + + UEP8_TX_DMA + endpoint 8 DMA TX buffer address + 0x78 + 0x10 + read-write + + + UEP8_TX_DMA + endpoint 8 DMA buffer address + [15:0] + read-write + + + + + UEP9_TX_DMA + endpoint 9 DMA TX buffer address + 0x7C + 0x10 + read-write + + + UEP9_TX_DMA + endpoint 9 DMA buffer address + [15:0] + read-write + + + + + UEP10_TX_DMA + endpoint 10 DMA TX buffer address + 0x80 + 0x10 + read-write + + + UEP10_TX_DMA + endpoint 10 DMA buffer address + [15:0] + read-write + + + + + UEP11_TX_DMA + endpoint 11 DMA TX buffer address + 0x84 + 0x10 + read-write + + + UEP11_TX_DMA + endpoint 11 DMA buffer address + [15:0] + read-write + + + + + UEP12_TX_DMA____UH_SPLIT_DATA + endpoint 12 DMA TX buffer address + 0x88 + 0x10 + read-write + + + UEP12_TX_DMA___UH_SPLIT_DATA + endpoint 12 DMA buffer address + [15:0] + read-write + + + + + UEP13_TX_DMA + endpoint 13 DMA TX buffer address + 0x8C + 0x10 + read-write + + + UEP13_TX_DMA + endpoint 13 DMA buffer address + [15:0] + read-write + + + + + UEP14_TX_DMA + endpoint 14 DMA TX buffer address + 0x90 + 0x10 + read-write + + + UEP14_TX_DMA + endpoint 14 DMA buffer address + [15:0] + read-write + + + + + UEP15_TX_DMA + endpoint 15 DMA TX buffer address + 0x94 + 0x10 + read-write + + + UEP15_TX_DMA + endpoint 15 DMA buffer address + [15:0] + read-write + + + + + UEP0_MAX_LEN + endpoint 0 max acceptable length + 0X98 + 0x10 + read-write + + + UEP0_MAX_LEN + endpoint 0 max acceptable length + [10:0] + read-write + + + + + UEP1_MAX_LEN + endpoint 1 max acceptable length + 0X9C + 0x10 + read-write + + + UEP1_MAX_LEN + endpoint 1 max acceptable length + [10:0] + read-write + + + + + UEP2_MAX_LEN__UH_RX_MAX_LEN + endpoint 2 max acceptable length + 0xA0 + 0x10 + read-write + + + UEP2_MAX_LEN__UH_RX_MAX_LEN + endpoint 2 max acceptable length + [10:0] + read-write + + + + + UEP3_MAX_LEN + endpoint 3 MAX_LEN TX + 0xA4 + 0x10 + read-write + + + UEP3_MAX_LEN + endpoint 3 max acceptable length + [10:0] + read-write + + + + + UEP4_MAX_LEN + endpoint 4 max acceptable length + 0xA8 + 0x10 + read-write + + + UEP4_MAX_LEN + endpoint 4 max acceptable length + [10:0] + read-write + + + + + UEP5_MAX_LEN + endpoint 5 max acceptable length + 0xAC + 0x10 + read-write + + + UEP5_MAX_LEN + endpoint 5 max acceptable length + [10:0] + read-write + + + + + UEP6_MAX_LEN + endpoint 6 max acceptable length + 0xB0 + 0x10 + read-write + + + UEP6_MAX_LEN + endpoint 6 max acceptable length + [10:0] + read-write + + + + + UEP7_MAX_LEN + endpoint 7 max acceptable length + 0xB4 + 0x10 + read-write + + + UEP7_MAX_LEN + endpoint 7 max acceptable length + [10:0] + read-write + + + + + UEP8_MAX_LEN + endpoint 8 max acceptable length + 0xB8 + 0x10 + read-write + + + UEP8_MAX_LEN + endpoint 8 max acceptable length + [10:0] + read-write + + + + + UEP9_MAX_LEN + endpoint 9 max acceptable length + 0xBC + 0x10 + read-write + + + UEP9_MAX_LEN + endpoint 9 max acceptable length + [10:0] + read-write + + + + + UEP10_MAX_LEN + endpoint 10 max acceptable length + 0xC0 + 0x10 + read-write + + + UEP10_MAX_LEN + endpoint 10 max acceptable length + [10:0] + read-write + + + + + UEP11_MAX_LEN + endpoint 11 max acceptable length + 0xC4 + 0x10 + read-write + + + UEP11_MAX_LEN + endpoint 11 max acceptable length + [10:0] + read-write + + + + + UEP12_MAX_LEN + endpoint 12 max acceptable length + 0xC8 + 0x10 + read-write + + + UEP12_MAX_LEN + endpoint 12 max acceptable length + [10:0] + read-write + + + + + UEP13_MAX_LEN + endpoint 13 max acceptable length + 0xCC + 0x10 + read-write + + + UEP13_MAX_LEN + endpoint 13 max acceptable length + [10:0] + read-write + + + + + UEP14_MAX_LEN + endpoint 14 max acceptable length + 0xD0 + 0x10 + read-write + + + UEP14_MAX_LEN + endpoint 14 max acceptable length + [10:0] + read-write + + + + + UEP15_MAX_LEN + endpoint 15 max acceptable length + 0xD4 + 0x10 + read-write + + + UEP15_MAX_LEN + endpoint 15 max acceptable length + [10:0] + read-write + + + + + UEP0_T_LEN + endpoint 0 send the length + 0xD8 + 0x10 + read-write + + + UEP0_T_LEN + endpoint 0 send the length + [10:0] + read-write + + + + + UEP0_T_CTRL + endpoint 0 send control + 0xDA + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 0 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 0 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 0 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP0_R_CTRL + endpoint 0 send control + 0xDB + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 0 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 0 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 0 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP1_T_LEN + endpoint 1 send the length + 0xDC + 0x10 + read-write + + + UEP1_T_LEN + endpoint 1 send the length + [10:0] + read-write + + + + + UEP1_T_CTRL + endpoint 1 send control + 0xDE + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 1 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 1 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 1 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP1_R_CTRL + endpoint 1 send control + 0xDF + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 1 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 1 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 1 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP2_T_LEN__UH_EP_PID + endpoint 2 send the length + 0xE0 + 0x10 + read-write + + + UEP2_T_LEN__MASK_UH_ENDP__MASK_UH_TOKEN + endpoint 2 send the length + [10:0] + read-write + + + + + UEP2_T_CTRL + endpoint 2 send control + 0xE2 + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 2 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 2 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 2 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP2_R_CTRL__UH_RX_CTRL + endpoint 2 send control + 0xE3 + 0x08 + read-write + + + MASK_UEP_R_RES__MASK_UH_R_RES + endpoint 2 control of the accept response to OUT transactions + [1:0] + read-write + + + bUH_R_RES_NO + bUH_R_RES_NO + [2:2] + read-write + + + MASK_UEP_R_TOG__MASK_UH_R_TOG + endpoint 2 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO__bUH_R_AUTO_TOG + endpoint 2 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + bUH_R_DATA_NO + bUH_R_DATA_NO + [6:6] + read-write + + + + + UEP3_T_LEN___UH_TX_LEN_H + endpoint 3 send the length + 0xE4 + 0x10 + read-write + + + UEP3_T_LEN___UH_TX_LEN_H + endpoint 3 send the length + [10:0] + read-write + + + + + UEP3_T_CTRL___UH_TX_CTRL + endpoint 3 send control + 0xE6 + 0x08 + read-write + + + MASK_UEP_T_RES_____MASK_UH_T_RES + endpoint 3 control of the send response to IN transactions + [1:0] + read-write + + + bUH_T_RES_NO + bUH_T_RES_NO + [2:2] + read-write + + + MASK_UEP_T_TOG____MASK_UH_T_TOG + endpoint 3 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO____bUH_T_AUTO_TOG + endpoint 3 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + bUH_T_DATA_NO + bUH_T_DATA_NO + [6:6] + read-write + + + + + UEP3_R_CTRL + endpoint 3 send control + 0xE7 + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 3 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 3 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 3 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP4_T_LEN + endpoint 4 send the length + 0xE8 + 0x10 + read-write + + + UEP4_T_LEN + endpoint 0 send the length + [10:0] + read-write + + + + + UEP4_T_CTRL + endpoint 4 send control + 0xEA + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 4 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 4 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 4 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP4_R_CTRL + endpoint 4 send control + 0xEB + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 4 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 4 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 4 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP5_T_LEN + endpoint 5 send the length + 0xEC + 0x10 + read-write + + + UEP5_T_LEN + endpoint 5 send the length + [10:0] + read-write + + + + + UEP5_T_CTRL + endpoint 5 send control + 0xEE + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 5 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 5 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 5 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP5_R_CTRL + endpoint 5 send control + 0xEF + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 5 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 5 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 5 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP6_T_LEN + endpoint 6 send the length + 0xF0 + 0x10 + read-write + + + UEP6_T_LEN + endpoint 6 send the length + [10:0] + read-write + + + + + UEP6_T_CTRL + endpoint 6 send control + 0xF2 + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 6 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 6 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 6 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP6_R_CTRL + endpoint 6 send control + 0xF3 + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 6 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 6 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 6 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP7_T_LEN + endpoint 7 send the length + 0xF4 + 0x10 + read-write + + + UEP7_T_LEN + endpoint 7 send the length + [10:0] + read-write + + + + + UEP7_T_CTRL + endpoint 7 send control + 0xF6 + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 7 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 7 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 7 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP7_R_CTRL + endpoint 7 send control + 0xF7 + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 7 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 7 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 7 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP8_T_LEN + endpoint 8 send the length + 0xF8 + 0x10 + read-write + + + UEP8_T_LEN + endpoint 8 send the length + [10:0] + read-write + + + + + UEP8_T_CTRL + endpoint 8 send control + 0xFA + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 8 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 8 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 8 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP8_R_CTRL + endpoint 8 send control + 0xFB + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 8 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 8 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 8 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP9_T_LEN + endpoint9 send the length + 0xFC + 0x10 + read-write + + + UEP9_T_LEN + endpoint 9 send the length + [10:0] + read-write + + + + + UEP9_T_CTRL + endpoint 9 send control + 0xFE + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 9 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 9 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 9 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP9_R_CTRL + endpoint 9 send control + 0xFF + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 9 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 9 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 9 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP10_T_LEN + endpoint 10 send the length + 0x100 + 0x10 + read-write + + + UEP10_T_LEN + endpoint 10 send the length + [10:0] + read-write + + + + + UEP10_T_CTRL + endpoint 10 send control + 0x102 + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 10 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 10 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 10 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP10_R_CTRL + endpoint 10 send control + 0x103 + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 10 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 10 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 10 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP11_T_LEN + endpoint 11 send the length + 0x104 + 0x10 + read-write + + + UEP0_T_LEN + endpoint 11 send the length + [10:0] + read-write + + + + + UEP11_T_CTRL + endpoint 11 send control + 0x106 + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 11 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 11 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 11 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP11_R_CTRL + endpoint 11 send control + 0x107 + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 11 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 11 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 11 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP12_T_LEN + endpoint 12 send the length + 0x108 + 0x10 + read-write + + + UEP0_T_LEN + endpoint 12 send the length + [10:0] + read-write + + + + + UEP12_T_CTRL + endpoint 12 send control + 0x10A + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 12 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 12 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 12 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP12_R_CTRL + endpoint 12 send control + 0x10B + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 12 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 12 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 12 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP13_T_LEN + endpoint 13 send the length + 0x10C + 0x10 + read-write + + + UEP13_T_LEN + endpoint 13 send the length + [10:0] + read-write + + + + + UEP13_T_CTRL + endpoint 13 send control + 0x10E + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 13 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 13 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 13 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP13_R_CTRL + endpoint 13 send control + 0x10F + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 13 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 13 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 13 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP14_T_LEN + endpoint 14 send the length + 0x110 + 0x10 + read-write + + + UEP14_T_LEN + endpoint 14 send the length + [10:0] + read-write + + + + + UEP14_T_CTRL + endpoint 14 send control + 0x112 + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 14 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 14 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 14 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP14_R_CTRL + endpoint 14 send control + 0x113 + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 14 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 14 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 14 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + UEP15_T_LEN + endpoint 15 send the length + 0x114 + 0x10 + read-write + + + UEP0_T_LEN + endpoint 15 send the length + [10:0] + read-write + + + + + UEP15_T_CTRL + endpoint 15 send control + 0x116 + 0x08 + read-write + + + MASK_UEP_T_RES + endpoint 15 control of the send response to IN transactions + [1:0] + read-write + + + MASK_UEP_T_TOG + endpoint 15 synchronous trigger bit for the sender to prepare + [4:3] + read-write + + + bUEP_T_TOG_AUTO + endpoint 15 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-write + + + + + UEP15_R_CTRL + endpoint 15 send control + 0x117 + 0x08 + read-write + + + MASK_UEP_R_RES + endpoint 15 control of the accept response to OUT transactions + [1:0] + read-write + + + MASK_UEP_R_TOG + endpoint 15 synchronous trigger bit for the accept to prepare + [4:3] + read-write + + + bUEP_R_TOG_AUTO + endpoint 15 synchronous trigger bit automatic filp enables the control bit + [5:5] + read-only + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DATAR + DATAR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDATAR + IDATAR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CTLR + CTLR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Reset bit + 0 + 1 + + + + + + + FLASH + FLASH + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 20 + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + KEYR + FPEC key + 0 + 32 + + + + + OBKEYR + OBKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + STATR + STATR + Status register + 0xC + 0x20 + 0x00000000 + + + ENHANCE_MOD_STA + Enhance mode start + 7 + 1 + read-only + + + EOP + End of operation + 5 + 1 + read-write + + + WRPRTERR + Write protection error + 4 + 1 + read-write + + + WR_BSY + Quick page programming + 1 + 1 + read-only + + + BSY + Busy + 0 + 1 + read-only + + + + + CTLR + CTLR + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + PG + Programming + 0 + 1 + + + PER + Page Erase + 1 + 1 + + + MER + Mass Erase + 2 + 1 + + + OBPG + Option byte programming + 4 + 1 + + + OBER + Option byte erase + 5 + 1 + + + STRT + Start + 6 + 1 + + + LOCK + Lock + 7 + 1 + + + OBWRE + Option bytes write enable + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + EOPIE + End of operation interrupt + enable + 12 + 1 + + + FLOCK + Fast programmable lock + 15 + 1 + + + PAGE_PG + Fast programming + 16 + 1 + + + PAGE_ER + Fast erase + 17 + 1 + + + BER32 + Block Erase 32K + 18 + 1 + + + BER64 + Block Erase 64K + 19 + 1 + + + PGSTART + Page Programming Start + 21 + 1 + + + RSENACT + Reset Flash Enhance read mode + 22 + 1 + + + ENHANCEMODE + Flash Enhance read mode + 24 + 1 + + + SCKMODE + Flash SCK mode + 25 + 1 + + + + + ADDR + ADDR + Flash address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FAR + Flash Address + 0 + 32 + + + + + OBR + OBR + Option byte register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + OBERR + Option byte error + 0 + 1 + + + RDPRT + Read protection + 1 + 1 + + + IWDG_SW + IWDG_SW + 2 + 1 + + + STOP_RST + STOP_RST + 3 + 1 + + + STANDY_RST + STANDY_RST + 4 + 1 + + + SRAM_CODE_MODE + SRAM_CODE_MODE + 8 + 2 + + + + + WPR + WPR + Write protection register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + WRP + Write protect + 0 + 32 + + + + + MODEKEYR + MODEKEYR + Mode select register + 0x24 + 0x20 + write-only + 0x00000000 + + + MODEKEYR + Mode select + 0 + 32 + + + + + + + USB_OTG_FS + USB FS OTG register + USB_OTG_FS + 0x50000000 + + 0x00 + 0x40000 + registers + + + USBHSWakeup + USBHSWakeup + 84 + + + USBHS + USBHS + 85 + + + OTG_FS + OTG_FS + 83 + + + + USBHD_BASE_CTRL + USB base control + 0x00 + 8 + read-write + + + USBHD_UC_DMA_EN + DMA enable and DMA interrupt enable for USB + [0:0] + + + USBHD_UC_CLR_ALL + force clear FIFO and count of USB + [1:1] + + + USBHD_UC_RESET_SIE + force reset USB SIE, need software clear + [2:2] + + + USBHD_UC_INT_BUSY + enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid + [3:3] + + + USBHD_UC_SYS_CTRL_MASK + USB device enable and internal pullup resistance enable + [5:4] + + + USBHD_UC_LOW_SPEED + enable USB low speed: 0=12Mbps, 1=1.5Mbps + [6:6] + + + RB_UC_HOST_MODE + enable USB host mode: 0=device mode, 1=host mode + [7:7] + + + + + USBHD_UDEV_CTRL__USBHD_UHOST_CTRL + USB device/host physical prot control + 0x01 + 8 + read-write + 0x00 + + + USBHD_UH_PORT_EN__USBHD_UD_PORT_EN + enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + [0:0] + + + USBHD_UH_BUS_RESET__USBHD_UD_GP_BIT + force clear FIFO and count of USB + [1:1] + + + USBHD_UH_LOW_SPEED__USBHD_UD_LOW_SPEED + enable USB port low speed: 0=full speed, 1=low speed + [2:2] + + + USBHD_UH_DM_PIN__USBHD_UD_DM_PIN + ReadOnly: indicate current UDM pin level + [4:4] + read-only + + + USBHD_UH_DP_PIN__USBHD_UD_DP_PIN + USB device enable and internal pullup resistance enable + [5:5] + read-only + + + USBHD_UH_PD_DIS__USBHD_UD_PD_DIS + disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable + [7:7] + + + + + R8_USB_INT_EN + USB interrupt enable + 0x02 + 8 + read-write + + + USBHD_UIE_BUS_RST__USBHD_UIE_DETECT + enable interrupt for USB bus reset event for USB device mode + [0:0] + + + USBHD_UIE_TRANSFER + enable interrupt for USB transfer completion + [1:1] + + + USBHD_UIE_SUSPEND + enable interrupt for USB suspend or resume event + [2:2] + + + USBHD_UIE_HST_SOF + enable interrupt for host SOF timer action for USB host mode + [3:3] + + + USBHD_UIE_FIFO_OV + enable interrupt for FIFO overflow + [4:4] + + + USBHD_UIE_DEV_NAK + enable interrupt for NAK responded for USB device mode + [6:6] + + + USBHD_UIE_DEV_SOF + enable interrupt for SOF received for USB device mode + [7:7] + + + + + R8_USB_DEV_AD + USB device address + 0x03 + 8 + read-write + + + MASK_USB_ADDR + bit mask for USB device address + [6:0] + read-write + + + RB_UDA_GP_BIT + general purpose bit + [7:7] + + + + + R8_USB_MIS_ST + USB miscellaneous status + 0x05 + 8 + read-only + + + RB_UMS_DEV_ATTACH + RO, indicate device attached status on USB host + [0:0] + + + RB_UMS_DM_LEVEL + RO, indicate UDM level saved at device attached to USB host + [1:1] + + + RB_UMS_SUSPEND + RO, indicate USB suspend status + [2:2] + + + RB_UMS_BUS_RESET + RO, indicate USB bus reset status + [3:3] + + + RB_UMS_R_FIFO_RDY + RO, indicate USB receiving FIFO ready status (not empty) + [4:4] + + + RB_UMS_SIE_FREE + RO, indicate USB SIE free status + [5:5] + + + RB_UMS_SOF_ACT + RO, indicate host SOF timer action status for USB host + [6:6] + + + RB_UMS_SOF_PRES + RO, indicate host SOF timer presage status + [7:7] + + + + + R8_USB_INT_FG + USB interrupt flag + 0x06 + 8 + read-write + + + RB_UIF_BUS_RST__RB_UIF_DETECT + bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear + [0:0] + + + RB_UIF_TRANSFER + USB transfer completion interrupt flag, direct bit address clear or write 1 to clear + [1:1] + + + RB_UIF_SUSPEND + USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear + [2:2] + + + RB_UIF_HST_SOF + host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear + [3:3] + + + RB_UIF_FIFO_OV + FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear + [4:4] + + + RB_U_SIE_FREE + RO, indicate USB SIE free status + [5:5] + read-only + + + RB_U_TOG_OK + RO, indicate current USB transfer toggle is OK + [6:6] + read-only + + + RB_U_IS_NAK + RO, indicate current USB transfer is NAK received + [7:7] + read-only + + + + + R8_USB_INT_ST + USB interrupt status + 0x07 + 8 + read-only + + + MASK_UIS_H_RES__MASK_UIS_ENDP + RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received;RO, bit mask of current transfer endpoint number for USB device mode + [3:0] + + + MASK_UIS_TOKEN + RO, bit mask of current token PID code received for USB device mode + [5:4] + + + RB_UIS_TOG_OK + RO, indicate current USB transfer toggle is OK + [6:6] + + + RB_UIS_IS_NAK + RO, indicate current USB transfer is NAK received for USB device mode + [7:7] + + + + + R16_USB_RX_LEN + USB receiving length + 0x08 + 16 + read-only + + + R8_UEP4_1_MOD + endpoint 4/1 mode + 0x0C + 8 + read-write + + + RB_UEP4_TX_EN + enable USB endpoint 4 transmittal (IN) + [2:2] + + + RB_UEP4_RX_EN + enable USB endpoint 4 receiving (OUT) + [3:3] + + + RB_UEP1_BUF_MOD + buffer mode of USB endpoint 1 + [4:4] + + + RB_UEP1_TX_EN + enable USB endpoint 1 transmittal (IN) + [6:6] + + + RB_UEP1_RX_EN + enable USB endpoint 1 receiving (OUT) + [7:7] + + + + + R8_UEP2_3_MOD__R8_UH_EP_MOD + endpoint 2/3 mode;host endpoint mode + 0x0D + 8 + read-write + + + RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD + buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint + [0:0] + + + RB_UEP2_TX_EN + enable USB endpoint 2 transmittal (IN) + [2:2] + + + RB_UEP2_RX_EN__RB_UH_EP_RX_EN + enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving + [3:3] + + + RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD + buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint + [4:4] + + + RB_UEP3_TX_EN__RB_UH_EP_TX_EN + enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal + [6:6] + + + RB_UEP3_RX_EN + enable USB endpoint 3 receiving (OUT) + [7:7] + + + + + R8_UEP5_6_MOD + endpoint 5/6 mode + 0x0e + 8 + read-write + 0x00 + + + RB_UEP5_BUF_MOD + buffer mode of USB endpoint 5 + [0:0] + + + RB_UEP5_TX_EN + enable USB endpoint 5 transmittal (IN) + [2:2] + + + RB_UEP5_RX_EN + enable USB endpoint 5 receiving (OUT) + [3:3] + + + RB_UEP6_BUF_MOD + buffer mode of USB endpoint 6 + [4:4] + + + RB_UEP6_TX_EN + enable USB endpoint 6 transmittal (IN) + [6:6] + + + RB_UEP3_RX_EN + enable USB endpoint 6 receiving (OUT) + [7:7] + + + + + R8_UEP7_MOD + endpoint 7 mode + 0x0f + 8 + read-write + 0x00 + + + RB_UEP7_BUF_MOD + buffer mode of USB endpoint 7 + [0:0] + + + RB_UEP7_TX_EN + enable USB endpoint 7 transmittal (IN) + [2:2] + + + RB_UEP7_RX_EN + enable USB endpoint 7 receiving (OUT) + [3:3] + + + + + R32_UEP0_DMA + endpoint 0 DMA buffer address + 0x10 + 0x20 + read-write + + + R32_UEP1_DMA + endpoint 1 DMA buffer address + 0x14 + 0x20 + read-write + + + R32_UEP2_DMA__R32_UH_RX_DMA + endpoint 2 DMA buffer address;host rx endpoint buffer high address + 0x18 + 0x20 + read-write + + + R32_UEP3_DMA__R32_UH_TX_DMA + endpoint 3 DMA buffer address;host tx endpoint buffer high address + 0x1C + 0x20 + read-write + + + R32_UEP4_DMA + endpoint 4 DMA buffer address + 0x20 + 0x20 + read-write + + + R32_UEP5_DMA + endpoint 5 DMA buffer address + 0x24 + 0x20 + read-write + + + R32_UEP6_DMA + endpoint 6 DMA buffer address + 0x28 + 0x20 + read-write + + + R32_UEP7_DMA + endpoint 7 DMA buffer address + 0x2c + 0x20 + read-write + + + R8_UEP0_T_LEN + endpoint 0 transmittal length + 0x30 + 8 + read-write + + + R8_UEP0_T_CTRL + endpoint 0 control + 0x32 + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + USBHD_UEP_T_TOG + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP0_R_CTRL + endpoint 0 control + 0x33 + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + USBHD_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP1_T_LEN + endpoint 1 transmittal length + 0x34 + 8 + read-write + + + R8_UEP1_T_CTRL___USBHD_UH_SETUP + endpoint 1 control + 0x36 + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + USBHD_UEP_T_TOG_ + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + USBHD_UH_SOF_EN + USB host automatic SOF enable + [6:6] + + + USBHD_UH_PRE_PID_EN + USB host PRE PID enable for low speed device via hub + [7:7] + + + + + R8_UEP1_R_CTRL + endpoint 1 control + 0x37 + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + USBHD_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP2_T_LEN__USBHD_UH_EP_PID + endpoint 2 transmittal length + 0x38 + 8 + read-write + + + USBHD_UH_ENDP_MASK + bit mask of endpoint number for USB host transfer + [3:0] + + + USBHD_UH_TOKEN_MASK + bit mask of token PID for USB host transfer + [7:4] + + + + + R8_UEP2_T_CTRL + endpoint 2 control + 0x3a + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + USBHD_UEP_T_TOG_ + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP2_R_CTRL__USBHD_UH_RX_CTRL + endpoint 2 control + 0x3b + 8 + read-write + 0x00 + + + MASK_UEP_R_RES___USBHD_UH_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + USBHD_UEP_R_TOG___USBHD_UH_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG___USBHD_UH_R_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP3_T_LEN__USBHD_UH_TX_LEN + endpoint 3 transmittal length + 0x3c + 8 + read-write + + + R8_UEP3_T_CTRL__USBHD_UH_TX_CTRL + endpoint 3 control + 0x3e + 8 + read-write + 0x00 + + + MASK_UEP_T_RES___USBHD_UH_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + USBHD_UEP_T_TOG___USBHD_UH_T_TOG + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG__USBHD_UH_T_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP3_R_CTRL_ + endpoint 3 control + 0x3f + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + USBHD_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP4_T_LEN + endpoint 4 transmittal length + 0x40 + 8 + read-write + + + R8_UEP4_T_CTRL + endpoint 4 control + 0x42 + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + USBHD_UEP_T_TOG___USBHD_UH_T_TOG + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG__USBHD_UH_T_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP4_R_CTRL_ + endpoint 4 control + 0x43 + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + USBHD_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP5_T_LEN + endpoint 5 transmittal length + 0x44 + 8 + read-write + + + R8_UEP5_T_CTRL + endpoint 5 control + 0x46 + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + USBHD_UEP_T_TOG___USBHD_UH_T_TOG + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG__USBHD_UH_T_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP5_R_CTRL_ + endpoint 5 control + 0x47 + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + USBHD_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP6_T_LEN + endpoint 6 transmittal length + 0x48 + 8 + read-write + + + R8_UEP6_T_CTRL + endpoint 6 control + 0x4a + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + USBHD_UEP_T_TOG___USBHD_UH_T_TOG + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG__USBHD_UH_T_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP6_R_CTRL_ + endpoint 6 control + 0x4b + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + USBHD_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP7_T_LEN + endpoint 7 transmittal length + 0x4c + 8 + read-write + + + R8_UEP7_T_CTRL + endpoint 7 control + 0x4e + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + USBHD_UEP_T_TOG___USBHD_UH_T_TOG + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG__USBHD_UH_T_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP7_R_CTRL_ + endpoint 7 control + 0x4f + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + USBHD_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + USBHD_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + USB_OTG_CR + usb otg control + 0x54 + 0x20 + read-write + 0x00 + + + USB_OTG_CR_DISCHARGEVBUS + usb otg control + [0:0] + + + USB_OTG_CR_CHARGEVBUS + usb otg control + [1:1] + + + USB_OTG_CR_IDPU + usb otg control + [2:2] + + + USB_OTG_CR_OTG_EN + usb otg control + [3:3] + + + USB_OTG_CR_VBUS + usb otg control + [4:4] + + + USB_OTG_CR_SESS + usb otg control + [5:5] + + + + + USB_OTG_SR + usb otg status + 0x58 + 0x20 + read-write + 0x00 + + + USB_OTG_SR_VBUS_VLD + usb otg status + [0:0] + + + USB_OTG_SR_SESS_VLD + usb otg status + [1:1] + + + USB_OTG_SR_SESS_END + usb otg status + [2:2] + + + USB_OTG_SR_ID_DIG + usb otg status + [3:3] + + + + + + + PFIC + Programmable Fast Interrupt + Controller + PFIC + 0xE000E000 + + 0x00 + 0x1100 + registers + + + + ISR1 + ISR1 + Interrupt Status + Register + 0x00 + 0x20 + read-only + 0x0000000C + + + INTENSTA2_3 + Interrupt ID Status + 2 + 2 + + + INTENSTA12_31 + Interrupt ID Status + 12 + 20 + + + + + ISR2 + ISR2 + Interrupt Status + Register + 0x04 + 0x20 + read-only + 0x00000000 + + + INTENSTA + Interrupt ID Status + 0 + 32 + + + + + ISR3 + ISR3 + Interrupt Status + Register + 0x08 + 0x20 + read-only + 0x00000000 + + + INTENSTA + Interrupt ID Status + 0 + 32 + + + + + ISR4 + ISR4 + Interrupt Status + Register + 0x0C + 0x20 + read-only + 0x00000000 + + + INTENSTA + Interrupt ID Status + 0 + 8 + + + + + IPR1 + IPR1 + Interrupt Pending Register + 0x20 + 0x20 + read-only + 0x00000000 + + + PENDSTA2_3 + PENDSTA + 2 + 2 + + + PENDSTA12_31 + PENDSTA + 12 + 20 + + + + + IPR2 + IPR2 + Interrupt Pending Register + 0x24 + 0x20 + read-only + 0x00000000 + + + PENDSTA + PENDSTA + 0 + 32 + + + + + IPR3 + IPR3 + Interrupt Pending Register + 0x28 + 0x20 + read-only + 0x00000000 + + + PENDSTA + PENDSTA + 0 + 32 + + + + + IPR4 + IPR4 + Interrupt Pending Register + 0x2C + 0x20 + read-only + 0x00000000 + + + PENDSTA + PENDSTA + 0 + 8 + + + + + ITHRESDR + ITHRESDR + Interrupt Priority + Register + 0x40 + 0x20 + read-write + 0x00000000 + + + THRESHOLD + THRESHOLD + 0 + 8 + + + + + CFGR + CFGR + Interrupt Config Register + 0x48 + 0x20 + 0x00000000 + + + RESETSYS + RESETSYS + write-only + 7 + 1 + + + KEYCODE + KEYCODE + write-only + 16 + 16 + + + + + GISR + GISR + Interrupt Global Register + 0x4C + 0x20 + read-only + 0x00000000 + + + NESTSTA + NESTSTA + 0 + 8 + + + GACTSTA + GACTSTA + 8 + 1 + + + GPENDSTA + GPENDSTA + 9 + 1 + + + + + VTFIDR + VTFIDR + ID Config Register + 0x50 + 0x20 + read-write + 0x00000000 + + + VTFID0 + VTFID0 + 0 + 8 + + + VTFID1 + VTFID1 + 8 + 8 + + + VTFID2 + VTFID2 + 16 + 8 + + + VTFID3 + VTFID3 + 24 + 8 + + + + + VTFADDRR0 + VTFADDRR0 + Interrupt 0 address + Register + 0x60 + 0x20 + read-write + 0x00000000 + + + VTF0EN + VTF0EN + 0 + 1 + + + ADDR0 + ADDR0 + 1 + 31 + + + + + VTFADDRR1 + VTFADDRR1 + Interrupt 1 address + Register + 0x64 + 0x20 + read-write + 0x00000000 + + + VTF1EN + VTF1EN + 0 + 1 + + + ADDR1 + ADDR1 + 1 + 31 + + + + + VTFADDRR2 + VTFADDRR2 + Interrupt 2 address + Register + 0x68 + 0x20 + read-write + 0x00000000 + + + VTF2EN + VTF2EN + 0 + 1 + + + ADDR2 + ADDR2 + 1 + 31 + + + + + VTFADDRR3 + VTFADDRR3 + Interrupt 3 address + Register + 0x6C + 0x20 + read-write + 0x00000000 + + + VTF3EN + VTF3EN + 0 + 1 + + + ADDR3 + ADDR3 + 1 + 31 + + + + + IENR1 + IENR1 + Interrupt Setting Register + 0x100 + 0x20 + write-only + 0x00000000 + + + INTEN + INTEN + 12 + 20 + + + + + IENR2 + IENR2 + Interrupt Setting Register + 0x104 + 0x20 + write-only + 0x00000000 + + + INTEN + INTEN + 0 + 32 + + + + + IENR3 + IENR3 + Interrupt Setting Register + 0x108 + 0x20 + write-only + 0x00000000 + + + INTEN + INTEN + 0 + 32 + + + + + IENR4 + IENR4 + Interrupt Setting Register + 0x10C + 0x20 + write-only + 0x00000000 + + + INTEN + INTEN + 0 + 8 + + + + + IRER1 + IRER1 + Interrupt Clear Register + 0x180 + 0x20 + write-only + 0x00000000 + + + INTRSET + INTRSET + 12 + 20 + + + + + IRER2 + IRER2 + Interrupt Clear Register + 0x184 + 0x20 + write-only + 0x00000000 + + + INTRSET + INTRSET + 0 + 32 + + + + + IRER3 + IRER3 + Interrupt Clear Register + 0x188 + 0x20 + write-only + 0x00000000 + + + INTRSET + INTRSET + 0 + 32 + + + + + IRER4 + IRER4 + Interrupt Clear Register + 0x18C + 0x20 + write-only + 0x00000000 + + + INTRSET + INTRSET + 0 + 8 + + + + + IPSR1 + IPSR1 + Interrupt Pending Register + 0x200 + 0x20 + write-only + 0x00000000 + + + PENDSET2_3 + PENDSET + 2 + 2 + + + PENDSET12_31 + PENDSET + 12 + 20 + + + + + IPSR2 + IPSR2 + Interrupt Pending Register + 0x204 + 0x20 + write-only + 0x00000000 + + + PENDSET + PENDSET + 0 + 32 + + + + + IPSR3 + IPSR3 + Interrupt Pending Register + 0x208 + 0x20 + write-only + 0x00000000 + + + PENDSET + PENDSET + 0 + 32 + + + + + IPSR4 + IPSR4 + Interrupt Pending Register + 0x20C + 0x20 + write-only + 0x00000000 + + + PENDSET + PENDSET + 0 + 8 + + + + + IPRR1 + IPRR1 + Interrupt Pending Clear Register + 0x280 + 0x20 + write-only + 0x00000000 + + + PENDRESET2_3 + PENDRESET + 2 + 2 + + + PENDRESET12_31 + PENDRESET + 12 + 20 + + + + + IPRR2 + IPRR2 + Interrupt Pending Clear Register + 0x284 + 0x20 + write-only + 0x00000000 + + + PENDRESET + PENDRESET + 0 + 32 + + + + + IPRR3 + IPRR3 + Interrupt Pending Clear Register + 0x288 + 0x20 + write-only + 0x00000000 + + + PENDRESET + PENDRESET + 0 + 32 + + + + + IPRR4 + IPRR4 + Interrupt Pending Clear Register + 0x28C + 0x20 + write-only + 0x00000000 + + + PENDRESET + PENDRESET + 0 + 8 + + + + + IACTR1 + IACTR1 + Interrupt ACTIVE Register + 0x300 + 0x20 + write-only + 0x00000000 + + + IACTS2_3 + IACTS + 2 + 2 + + + IACTS12_31 + IACTS + 12 + 20 + + + + + IACTR2 + IACTR2 + Interrupt ACTIVE Register + 0x304 + 0x20 + write-only + 0x00000000 + + + IACTS + IACTS + 0 + 32 + + + + + IACTR3 + IACTR3 + Interrupt ACTIVE Register + 0x308 + 0x20 + write-only + 0x00000000 + + + IACTS + IACTS + 0 + 32 + + + + + IACTR4 + IACTR4 + Interrupt ACTIVE Register + 0x30C + 0x20 + write-only + 0x00000000 + + + IACTS + IACTS + 0 + 8 + + + + + IPRIOR0 + IPRIOR0 + Interrupt Priority Register + 0x400 + 0x8 + read-write + 0x00000000 + + + IPRIOR1 + IPRIOR1 + Interrupt Priority Register + 0x401 + 0x8 + read-write + 0x00000000 + + + IPRIOR2 + IPRIOR2 + Interrupt Priority Register + 0x402 + 0x8 + read-write + 0x00000000 + + + IPRIOR3 + IPRIOR3 + Interrupt Priority Register + 0x403 + 0x8 + read-write + 0x00000000 + + + IPRIOR4 + IPRIOR4 + Interrupt Priority Register + 0x404 + 0x8 + read-write + 0x00000000 + + + IPRIOR5 + IPRIOR5 + Interrupt Priority Register + 0x405 + 0x8 + read-write + 0x00000000 + + + IPRIOR6 + IPRIOR6 + Interrupt Priority Register + 0x406 + 0x8 + read-write + 0x00000000 + + + IPRIOR7 + IPRIOR7 + Interrupt Priority Register + 0x407 + 0x8 + read-write + 0x00000000 + + + IPRIOR8 + IPRIOR8 + Interrupt Priority Register + 0x408 + 0x8 + read-write + 0x00000000 + + + IPRIOR9 + IPRIOR9 + Interrupt Priority Register + 0x409 + 0x8 + read-write + 0x00000000 + + + IPRIOR10 + IPRIOR10 + Interrupt Priority Register + 0x40A + 0x8 + read-write + 0x00000000 + + + IPRIOR11 + IPRIOR11 + Interrupt Priority Register + 0x40B + 0x8 + read-write + 0x00000000 + + + IPRIOR12 + IPRIOR12 + Interrupt Priority Register + 0x40C + 0x8 + read-write + 0x00000000 + + + IPRIOR13 + IPRIOR13 + Interrupt Priority Register + 0x40D + 0x8 + read-write + 0x00000000 + + + IPRIOR14 + IPRIOR14 + Interrupt Priority Register + 0x40E + 0x8 + read-write + 0x00000000 + + + IPRIOR15 + IPRIOR15 + Interrupt Priority Register + 0x40F + 0x8 + read-write + 0x00000000 + + + IPRIOR16 + IPRIOR6 + Interrupt Priority Register + 0x410 + 0x8 + read-write + 0x00000000 + + + IPRIOR17 + IPRIOR7 + Interrupt Priority Register + 0x411 + 0x8 + read-write + 0x00000000 + + + IPRIOR18 + IPRIOR8 + Interrupt Priority Register + 0x412 + 0x8 + read-write + 0x00000000 + + + IPRIOR19 + IPRIOR9 + Interrupt Priority Register + 0x413 + 0x8 + read-write + 0x00000000 + + + IPRIOR20 + IPRIOR20 + Interrupt Priority Register + 0x414 + 0x8 + read-write + 0x00000000 + + + IPRIOR21 + IPRIOR21 + Interrupt Priority Register + 0x415 + 0x8 + read-write + 0x00000000 + + + IPRIOR22 + IPRIOR22 + Interrupt Priority Register + 0x416 + 0x8 + read-write + 0x00000000 + + + IPRIOR23 + IPRIOR23 + Interrupt Priority Register + 0x417 + 0x8 + read-write + 0x00000000 + + + IPRIOR24 + IPRIOR24 + Interrupt Priority Register + 0x418 + 0x8 + read-write + 0x00000000 + + + IPRIOR25 + IPRIOR25 + Interrupt Priority Register + 0x419 + 0x8 + read-write + 0x00000000 + + + IPRIOR26 + IPRIOR26 + Interrupt Priority Register + 0x41A + 0x8 + read-write + 0x00000000 + + + IPRIOR27 + IPRIOR27 + Interrupt Priority Register + 0x41B + 0x8 + read-write + 0x00000000 + + + IPRIOR28 + IPRIOR28 + Interrupt Priority Register + 0x41C + 0x8 + read-write + 0x00000000 + + + IPRIOR29 + IPRIOR29 + Interrupt Priority Register + 0x41D + 0x8 + read-write + 0x00000000 + + + IPRIOR30 + IPRIOR30 + Interrupt Priority Register + 0x41E + 0x8 + read-write + 0x00000000 + + + IPRIOR31 + IPRIOR31 + Interrupt Priority Register + 0x41F + 0x8 + read-write + 0x00000000 + + + IPRIOR32 + IPRIOR32 + Interrupt Priority Register + 0x420 + 0x8 + read-write + 0x00000000 + + + IPRIOR33 + IPRIOR33 + Interrupt Priority Register + 0x421 + 0x8 + read-write + 0x00000000 + + + IPRIOR34 + IPRIOR34 + Interrupt Priority Register + 0x422 + 0x8 + read-write + 0x00000000 + + + IPRIOR35 + IPRIOR35 + Interrupt Priority Register + 0x423 + 0x8 + read-write + 0x00000000 + + + IPRIOR36 + IPRIOR36 + Interrupt Priority Register + 0x424 + 0x8 + read-write + 0x00000000 + + + IPRIOR37 + IPRIOR37 + Interrupt Priority Register + 0x425 + 0x8 + read-write + 0x00000000 + + + IPRIOR38 + IPRIOR38 + Interrupt Priority Register + 0x426 + 0x8 + read-write + 0x00000000 + + + IPRIOR39 + IPRIOR39 + Interrupt Priority Register + 0x427 + 0x8 + read-write + 0x00000000 + + + IPRIOR40 + IPRIOR40 + Interrupt Priority Register + 0x428 + 0x8 + read-write + 0x00000000 + + + IPRIOR41 + IPRIOR41 + Interrupt Priority Register + 0x429 + 0x8 + read-write + 0x00000000 + + + IPRIOR42 + IPRIOR42 + Interrupt Priority Register + 0x42A + 0x8 + read-write + 0x00000000 + + + IPRIOR43 + IPRIOR43 + Interrupt Priority Register + 0x42B + 0x8 + read-write + 0x00000000 + + + IPRIOR44 + IPRIOR44 + Interrupt Priority Register + 0x42C + 0x8 + read-write + 0x00000000 + + + IPRIOR45 + IPRIOR45 + Interrupt Priority Register + 0x42D + 0x8 + read-write + 0x00000000 + + + IPRIOR46 + IPRIOR46 + Interrupt Priority Register + 0x42E + 0x8 + read-write + 0x00000000 + + + IPRIOR47 + IPRIOR47 + Interrupt Priority Register + 0x42F + 0x8 + read-write + 0x00000000 + + + IPRIOR48 + IPRIOR48 + Interrupt Priority Register + 0x430 + 0x8 + read-write + 0x00000000 + + + IPRIOR49 + IPRIOR49 + Interrupt Priority Register + 0x431 + 0x8 + read-write + 0x00000000 + + + IPRIOR50 + IPRIOR50 + Interrupt Priority Register + 0x432 + 0x8 + read-write + 0x00000000 + + + IPRIOR51 + IPRIOR51 + Interrupt Priority Register + 0x433 + 0x8 + read-write + 0x00000000 + + + IPRIOR52 + IPRIOR52 + Interrupt Priority Register + 0x434 + 0x8 + read-write + 0x00000000 + + + IPRIOR53 + IPRIOR53 + Interrupt Priority Register + 0x435 + 0x8 + read-write + 0x00000000 + + + IPRIOR54 + IPRIOR54 + Interrupt Priority Register + 0x436 + 0x8 + read-write + 0x00000000 + + + IPRIOR55 + IPRIOR55 + Interrupt Priority Register + 0x437 + 0x8 + read-write + 0x00000000 + + + IPRIOR56 + IPRIOR56 + Interrupt Priority Register + 0x438 + 0x8 + read-write + 0x00000000 + + + IPRIOR57 + IPRIOR57 + Interrupt Priority Register + 0x439 + 0x8 + read-write + 0x00000000 + + + IPRIOR58 + IPRIOR58 + Interrupt Priority Register + 0x43A + 0x8 + read-write + 0x00000000 + + + IPRIOR59 + IPRIOR59 + Interrupt Priority Register + 0x43B + 0x8 + read-write + 0x00000000 + + + IPRIOR60 + IPRIOR60 + Interrupt Priority Register + 0x43C + 0x8 + read-write + 0x00000000 + + + IPRIOR61 + IPRIOR61 + Interrupt Priority Register + 0x43D + 0x8 + read-write + 0x00000000 + + + IPRIOR62 + IPRIOR62 + Interrupt Priority Register + 0x43E + 0x8 + read-write + 0x00000000 + + + IPRIOR63 + IPRIOR63 + Interrupt Priority Register + 0x43F + 0x8 + read-write + 0x00000000 + + + IPRIOR64 + IPRIOR64 + Interrupt Priority Register + 0x440 + 0x8 + read-write + 0x00000000 + + + IPRIOR65 + IPRIOR65 + Interrupt Priority Register + 0x441 + 0x8 + read-write + 0x00000000 + + + IPRIOR66 + IPRIOR66 + Interrupt Priority Register + 0x442 + 0x8 + read-write + 0x00000000 + + + IPRIOR67 + IPRIOR67 + Interrupt Priority Register + 0x443 + 0x8 + read-write + 0x00000000 + + + IPRIOR68 + IPRIOR68 + Interrupt Priority Register + 0x444 + 0x8 + read-write + 0x00000000 + + + IPRIOR69 + IPRIOR69 + Interrupt Priority Register + 0x445 + 0x8 + read-write + 0x00000000 + + + IPRIOR70 + IPRIOR70 + Interrupt Priority Register + 0x446 + 0x8 + read-write + 0x00000000 + + + IPRIOR71 + IPRIOR71 + Interrupt Priority Register + 0x447 + 0x8 + read-write + 0x00000000 + + + IPRIOR72 + IPRIOR72 + Interrupt Priority Register + 0x448 + 0x8 + read-write + 0x00000000 + + + IPRIOR73 + IPRIOR73 + Interrupt Priority Register + 0x449 + 0x8 + read-write + 0x00000000 + + + IPRIOR74 + IPRIOR74 + Interrupt Priority Register + 0x44A + 0x8 + read-write + 0x00000000 + + + IPRIOR75 + IPRIOR75 + Interrupt Priority Register + 0x44B + 0x8 + read-write + 0x00000000 + + + IPRIOR76 + IPRIOR76 + Interrupt Priority Register + 0x44C + 0x8 + read-write + 0x00000000 + + + IPRIOR77 + IPRIOR77 + Interrupt Priority Register + 0x44D + 0x8 + read-write + 0x00000000 + + + IPRIOR78 + IPRIOR78 + Interrupt Priority Register + 0x44E + 0x8 + read-write + 0x00000000 + + + IPRIOR79 + IPRIOR79 + Interrupt Priority Register + 0x44F + 0x8 + read-write + 0x00000000 + + + IPRIOR80 + IPRIOR80 + Interrupt Priority Register + 0x450 + 0x8 + read-write + 0x00000000 + + + IPRIOR81 + IPRIOR81 + Interrupt Priority Register + 0x451 + 0x8 + read-write + 0x00000000 + + + IPRIOR82 + IPRIOR82 + Interrupt Priority Register + 0x452 + 0x8 + read-write + 0x00000000 + + + IPRIOR83 + IPRIOR83 + Interrupt Priority Register + 0x453 + 0x8 + read-write + 0x00000000 + + + IPRIOR84 + IPRIOR84 + Interrupt Priority Register + 0x454 + 0x8 + read-write + 0x00000000 + + + IPRIOR85 + IPRIOR85 + Interrupt Priority Register + 0x455 + 0x8 + read-write + 0x00000000 + + + IPRIOR86 + IPRIOR86 + Interrupt Priority Register + 0x456 + 0x8 + read-write + 0x00000000 + + + IPRIOR87 + IPRIOR87 + Interrupt Priority Register + 0x457 + 0x8 + read-write + 0x00000000 + + + IPRIOR88 + IPRIOR88 + Interrupt Priority Register + 0x458 + 0x8 + read-write + 0x00000000 + + + IPRIOR89 + IPRIOR89 + Interrupt Priority Register + 0x459 + 0x8 + read-write + 0x00000000 + + + IPRIOR90 + IPRIOR90 + Interrupt Priority Register + 0x45A + 0x8 + read-write + 0x00000000 + + + IPRIOR91 + IPRIOR91 + Interrupt Priority Register + 0x45B + 0x8 + read-write + 0x00000000 + + + IPRIOR92 + IPRIOR92 + Interrupt Priority Register + 0x45C + 0x8 + read-write + 0x00000000 + + + IPRIOR93 + IPRIOR93 + Interrupt Priority Register + 0x45D + 0x8 + read-write + 0x00000000 + + + IPRIOR94 + IPRIOR94 + Interrupt Priority Register + 0x45E + 0x8 + read-write + 0x00000000 + + + IPRIOR95 + IPRIOR95 + Interrupt Priority Register + 0x45F + 0x8 + read-write + 0x00000000 + + + IPRIOR96 + IPRIOR96 + Interrupt Priority Register + 0x460 + 0x8 + read-write + 0x00000000 + + + IPRIOR97 + IPRIOR97 + Interrupt Priority Register + 0x461 + 0x8 + read-write + 0x00000000 + + + IPRIOR98 + IPRIOR98 + Interrupt Priority Register + 0x462 + 0x8 + read-write + 0x00000000 + + + IPRIOR99 + IPRIOR99 + Interrupt Priority Register + 0x463 + 0x8 + read-write + 0x00000000 + + + IPRIOR100 + IPRIOR100 + Interrupt Priority Register + 0x464 + 0x8 + read-write + 0x00000000 + + + IPRIOR101 + IPRIOR101 + Interrupt Priority Register + 0x465 + 0x8 + read-write + 0x00000000 + + + IPRIOR102 + IPRIOR102 + Interrupt Priority Register + 0x466 + 0x8 + read-write + 0x00000000 + + + IPRIOR103 + IPRIOR103 + Interrupt Priority Register + 0x467 + 0x8 + read-write + 0x00000000 + + + IPRIOR104 + IPRIOR104 + Interrupt Priority Register + 0x468 + 0x8 + read-write + 0x00000000 + + + IPRIOR105 + IPRIOR105 + Interrupt Priority Register + 0x469 + 0x8 + read-write + 0x00000000 + + + IPRIOR106 + IPRIOR106 + Interrupt Priority Register + 0x46A + 0x8 + read-write + 0x00000000 + + + IPRIOR107 + IPRIOR107 + Interrupt Priority Register + 0x46B + 0x8 + read-write + 0x00000000 + + + IPRIOR108 + IPRIOR108 + Interrupt Priority Register + 0x46C + 0x8 + read-write + 0x00000000 + + + IPRIOR109 + IPRIOR109 + Interrupt Priority Register + 0x46D + 0x8 + read-write + 0x00000000 + + + IPRIOR110 + IPRIOR110 + Interrupt Priority Register + 0x46E + 0x8 + read-write + 0x00000000 + + + IPRIOR111 + IPRIOR111 + Interrupt Priority Register + 0x46F + 0x8 + read-write + 0x00000000 + + + IPRIOR112 + IPRIOR112 + Interrupt Priority Register + 0x470 + 0x8 + read-write + 0x00000000 + + + IPRIOR113 + IPRIOR113 + Interrupt Priority Register + 0x471 + 0x8 + read-write + 0x00000000 + + + IPRIOR114 + IPRIOR114 + Interrupt Priority Register + 0x472 + 0x8 + read-write + 0x00000000 + + + IPRIOR115 + IPRIOR115 + Interrupt Priority Register + 0x473 + 0x8 + read-write + 0x00000000 + + + IPRIOR116 + IPRIOR16 + Interrupt Priority Register + 0x474 + 0x8 + read-write + 0x00000000 + + + IPRIOR117 + IPRIOR17 + Interrupt Priority Register + 0x475 + 0x8 + read-write + 0x00000000 + + + IPRIOR118 + IPRIOR18 + Interrupt Priority Register + 0x476 + 0x8 + read-write + 0x00000000 + + + IPRIOR119 + IPRIOR19 + Interrupt Priority Register + 0x477 + 0x8 + read-write + 0x00000000 + + + IPRIOR120 + IPRIOR120 + Interrupt Priority Register + 0x478 + 0x8 + read-write + 0x00000000 + + + IPRIOR121 + IPRIOR121 + Interrupt Priority Register + 0x479 + 0x8 + read-write + 0x00000000 + + + IPRIOR122 + IPRIOR122 + Interrupt Priority Register + 0x47A + 0x8 + read-write + 0x00000000 + + + IPRIOR123 + IPRIOR123 + Interrupt Priority Register + 0x47B + 0x8 + read-write + 0x00000000 + + + IPRIOR124 + IPRIOR124 + Interrupt Priority Register + 0x47C + 0x8 + read-write + 0x00000000 + + + IPRIOR125 + IPRIOR125 + Interrupt Priority Register + 0x47D + 0x8 + read-write + 0x00000000 + + + IPRIOR126 + IPRIOR126 + Interrupt Priority Register + 0x47E + 0x8 + read-write + 0x00000000 + + + IPRIOR127 + IPRIOR127 + Interrupt Priority Register + 0x47F + 0x8 + read-write + 0x00000000 + + + IPRIOR128 + IPRIOR128 + Interrupt Priority Register + 0x480 + 0x8 + read-write + 0x00000000 + + + IPRIOR129 + IPRIOR129 + Interrupt Priority Register + 0x481 + 0x8 + read-write + 0x00000000 + + + IPRIOR130 + IPRIOR130 + Interrupt Priority Register + 0x482 + 0x8 + read-write + 0x00000000 + + + IPRIOR131 + IPRIOR131 + Interrupt Priority Register + 0x483 + 0x8 + read-write + 0x00000000 + + + IPRIOR132 + IPRIOR132 + Interrupt Priority Register + 0x484 + 0x8 + read-write + 0x00000000 + + + IPRIOR133 + IPRIOR133 + Interrupt Priority Register + 0x485 + 0x8 + read-write + 0x00000000 + + + IPRIOR134 + IPRIOR134 + Interrupt Priority Register + 0x486 + 0x8 + read-write + 0x00000000 + + + IPRIOR135 + IPRIOR135 + Interrupt Priority Register + 0x487 + 0x8 + read-write + 0x00000000 + + + IPRIOR136 + IPRIOR136 + Interrupt Priority Register + 0x488 + 0x8 + read-write + 0x00000000 + + + IPRIOR137 + IPRIOR137 + Interrupt Priority Register + 0x489 + 0x8 + read-write + 0x00000000 + + + IPRIOR138 + IPRIOR138 + Interrupt Priority Register + 0x48A + 0x8 + read-write + 0x00000000 + + + IPRIOR139 + IPRIOR139 + Interrupt Priority Register + 0x48B + 0x8 + read-write + 0x00000000 + + + IPRIOR140 + IPRIOR140 + Interrupt Priority Register + 0x48C + 0x8 + read-write + 0x00000000 + + + IPRIOR141 + IPRIOR141 + Interrupt Priority Register + 0x48D + 0x8 + read-write + 0x00000000 + + + IPRIOR142 + IPRIOR142 + Interrupt Priority Register + 0x48E + 0x8 + read-write + 0x00000000 + + + IPRIOR143 + IPRIOR143 + Interrupt Priority Register + 0x48F + 0x8 + read-write + 0x00000000 + + + IPRIOR144 + IPRIOR144 + Interrupt Priority Register + 0x490 + 0x8 + read-write + 0x00000000 + + + IPRIOR145 + IPRIOR145 + Interrupt Priority Register + 0x491 + 0x8 + read-write + 0x00000000 + + + IPRIOR146 + IPRIOR146 + Interrupt Priority Register + 0x492 + 0x8 + read-write + 0x00000000 + + + IPRIOR147 + IPRIOR147 + Interrupt Priority Register + 0x493 + 0x8 + read-write + 0x00000000 + + + IPRIOR148 + IPRIOR148 + Interrupt Priority Register + 0x494 + 0x8 + read-write + 0x00000000 + + + IPRIOR149 + IPRIOR149 + Interrupt Priority Register + 0x495 + 0x8 + read-write + 0x00000000 + + + IPRIOR150 + IPRIOR150 + Interrupt Priority Register + 0x496 + 0x8 + read-write + 0x00000000 + + + IPRIOR151 + IPRIOR151 + Interrupt Priority Register + 0x497 + 0x8 + read-write + 0x00000000 + + + IPRIOR152 + IPRIOR152 + Interrupt Priority Register + 0x498 + 0x8 + read-write + 0x00000000 + + + IPRIOR153 + IPRIOR153 + Interrupt Priority Register + 0x499 + 0x8 + read-write + 0x00000000 + + + IPRIOR154 + IPRIOR154 + Interrupt Priority Register + 0x49A + 0x8 + read-write + 0x00000000 + + + IPRIOR155 + IPRIOR155 + Interrupt Priority Register + 0x49B + 0x8 + read-write + 0x00000000 + + + IPRIOR156 + IPRIOR156 + Interrupt Priority Register + 0x49C + 0x8 + read-write + 0x00000000 + + + IPRIOR157 + IPRIOR157 + Interrupt Priority Register + 0x49D + 0x8 + read-write + 0x00000000 + + + IPRIOR158 + IPRIOR158 + Interrupt Priority Register + 0x49E + 0x8 + read-write + 0x00000000 + + + IPRIOR159 + IPRIOR159 + Interrupt Priority Register + 0x49F + 0x8 + read-write + 0x00000000 + + + IPRIOR160 + IPRIOR160 + Interrupt Priority Register + 0x4A0 + 0x8 + read-write + 0x00000000 + + + IPRIOR161 + IPRIOR161 + Interrupt Priority Register + 0x4A1 + 0x8 + read-write + 0x00000000 + + + IPRIOR162 + IPRIOR162 + Interrupt Priority Register + 0x4A2 + 0x8 + read-write + 0x00000000 + + + IPRIOR163 + IPRIOR163 + Interrupt Priority Register + 0x4A3 + 0x8 + read-write + 0x00000000 + + + IPRIOR164 + IPRIOR164 + Interrupt Priority Register + 0x4A4 + 0x8 + read-write + 0x00000000 + + + IPRIOR165 + IPRIOR165 + Interrupt Priority Register + 0x4A5 + 0x8 + read-write + 0x00000000 + + + IPRIOR166 + IPRIOR166 + Interrupt Priority Register + 0x4A6 + 0x8 + read-write + 0x00000000 + + + IPRIOR167 + IPRIOR167 + Interrupt Priority Register + 0x4A7 + 0x8 + read-write + 0x00000000 + + + IPRIOR168 + IPRIOR168 + Interrupt Priority Register + 0x4A8 + 0x8 + read-write + 0x00000000 + + + IPRIOR169 + IPRIOR169 + Interrupt Priority Register + 0x4A9 + 0x8 + read-write + 0x00000000 + + + IPRIOR170 + IPRIOR170 + Interrupt Priority Register + 0x4AA + 0x8 + read-write + 0x00000000 + + + IPRIOR171 + IPRIOR171 + Interrupt Priority Register + 0x4AB + 0x8 + read-write + 0x00000000 + + + IPRIOR172 + IPRIOR172 + Interrupt Priority Register + 0x4AC + 0x8 + read-write + 0x00000000 + + + IPRIOR173 + IPRIOR173 + Interrupt Priority Register + 0x4AD + 0x8 + read-write + 0x00000000 + + + IPRIOR174 + IPRIOR174 + Interrupt Priority Register + 0x4AE + 0x8 + read-write + 0x00000000 + + + IPRIOR175 + IPRIOR175 + Interrupt Priority Register + 0x4AF + 0x8 + read-write + 0x00000000 + + + IPRIOR176 + IPRIOR176 + Interrupt Priority Register + 0x4B0 + 0x8 + read-write + 0x00000000 + + + IPRIOR177 + IPRIOR177 + Interrupt Priority Register + 0x4B1 + 0x8 + read-write + 0x00000000 + + + IPRIOR178 + IPRIOR178 + Interrupt Priority Register + 0x4B2 + 0x8 + read-write + 0x00000000 + + + IPRIOR179 + IPRIOR179 + Interrupt Priority Register + 0x4B3 + 0x8 + read-write + 0x00000000 + + + IPRIOR180 + IPRIOR180 + Interrupt Priority Register + 0x4B4 + 0x8 + read-write + 0x00000000 + + + IPRIOR181 + IPRIOR181 + Interrupt Priority Register + 0x4B5 + 0x8 + read-write + 0x00000000 + + + IPRIOR182 + IPRIOR182 + Interrupt Priority Register + 0x4B6 + 0x8 + read-write + 0x00000000 + + + IPRIOR183 + IPRIOR183 + Interrupt Priority Register + 0x4B7 + 0x8 + read-write + 0x00000000 + + + IPRIOR184 + IPRIOR184 + Interrupt Priority Register + 0x4B8 + 0x8 + read-write + 0x00000000 + + + IPRIOR185 + IPRIOR185 + Interrupt Priority Register + 0x4B9 + 0x8 + read-write + 0x00000000 + + + IPRIOR186 + IPRIOR186 + Interrupt Priority Register + 0x4BA + 0x8 + read-write + 0x00000000 + + + IPRIOR187 + IPRIOR187 + Interrupt Priority Register + 0x4BB + 0x8 + read-write + 0x00000000 + + + IPRIOR188 + IPRIOR188 + Interrupt Priority Register + 0x4BC + 0x8 + read-write + 0x00000000 + + + IPRIOR189 + IPRIOR189 + Interrupt Priority Register + 0x4BD + 0x8 + read-write + 0x00000000 + + + IPRIOR190 + IPRIOR190 + Interrupt Priority Register + 0x4BE + 0x8 + read-write + 0x00000000 + + + IPRIOR191 + IPRIOR191 + Interrupt Priority Register + 0x4BF + 0x8 + read-write + 0x00000000 + + + IPRIOR192 + IPRIOR192 + Interrupt Priority Register + 0x4C0 + 0x8 + read-write + 0x00000000 + + + IPRIOR193 + IPRIOR193 + Interrupt Priority Register + 0x4C1 + 0x8 + read-write + 0x00000000 + + + IPRIOR194 + IPRIOR194 + Interrupt Priority Register + 0x4C2 + 0x8 + read-write + 0x00000000 + + + IPRIOR195 + IPRIOR195 + Interrupt Priority Register + 0x4C3 + 0x8 + read-write + 0x00000000 + + + IPRIOR196 + IPRIOR196 + Interrupt Priority Register + 0x4C4 + 0x8 + read-write + 0x00000000 + + + IPRIOR197 + IPRIOR197 + Interrupt Priority Register + 0x4C5 + 0x8 + read-write + 0x00000000 + + + IPRIOR198 + IPRIOR198 + Interrupt Priority Register + 0x4C6 + 0x8 + read-write + 0x00000000 + + + IPRIOR199 + IPRIOR199 + Interrupt Priority Register + 0x4C7 + 0x8 + read-write + 0x00000000 + + + IPRIOR200 + IPRIOR200 + Interrupt Priority Register + 0x4C8 + 0x8 + read-write + 0x00000000 + + + IPRIOR201 + IPRIOR201 + Interrupt Priority Register + 0x4C9 + 0x8 + read-write + 0x00000000 + + + IPRIOR202 + IPRIOR202 + Interrupt Priority Register + 0x4CA + 0x8 + read-write + 0x00000000 + + + IPRIOR203 + IPRIOR203 + Interrupt Priority Register + 0x4CB + 0x8 + read-write + 0x00000000 + + + IPRIOR204 + IPRIOR204 + Interrupt Priority Register + 0x4CC + 0x8 + read-write + 0x00000000 + + + IPRIOR205 + IPRIOR205 + Interrupt Priority Register + 0x4CD + 0x8 + read-write + 0x00000000 + + + IPRIOR206 + IPRIOR206 + Interrupt Priority Register + 0x4CE + 0x8 + read-write + 0x00000000 + + + IPRIOR207 + IPRIOR207 + Interrupt Priority Register + 0x4CF + 0x8 + read-write + 0x00000000 + + + IPRIOR208 + IPRIOR208 + Interrupt Priority Register + 0x4D0 + 0x8 + read-write + 0x00000000 + + + IPRIOR209 + IPRIOR209 + Interrupt Priority Register + 0x4D1 + 0x8 + read-write + 0x00000000 + + + IPRIOR210 + IPRIOR210 + Interrupt Priority Register + 0x4D2 + 0x8 + read-write + 0x00000000 + + + IPRIOR211 + IPRIOR211 + Interrupt Priority Register + 0x4D3 + 0x8 + read-write + 0x00000000 + + + IPRIOR212 + IPRIOR212 + Interrupt Priority Register + 0x4D4 + 0x8 + read-write + 0x00000000 + + + IPRIOR213 + IPRIOR213 + Interrupt Priority Register + 0x4D5 + 0x8 + read-write + 0x00000000 + + + IPRIOR214 + IPRIOR214 + Interrupt Priority Register + 0x4D6 + 0x8 + read-write + 0x00000000 + + + IPRIOR215 + IPRIOR215 + Interrupt Priority Register + 0x4D7 + 0x8 + read-write + 0x00000000 + + + IPRIOR216 + IPRIOR26 + Interrupt Priority Register + 0x4D8 + 0x8 + read-write + 0x00000000 + + + IPRIOR217 + IPRIOR27 + Interrupt Priority Register + 0x4D9 + 0x8 + read-write + 0x00000000 + + + IPRIOR218 + IPRIOR28 + Interrupt Priority Register + 0x4DA + 0x8 + read-write + 0x00000000 + + + IPRIOR219 + IPRIOR29 + Interrupt Priority Register + 0x4DB + 0x8 + read-write + 0x00000000 + + + IPRIOR220 + IPRIOR220 + Interrupt Priority Register + 0x4DC + 0x8 + read-write + 0x00000000 + + + IPRIOR221 + IPRIOR221 + Interrupt Priority Register + 0x4DD + 0x8 + read-write + 0x00000000 + + + IPRIOR222 + IPRIOR222 + Interrupt Priority Register + 0x4DE + 0x8 + read-write + 0x00000000 + + + IPRIOR223 + IPRIOR223 + Interrupt Priority Register + 0x4DF + 0x8 + read-write + 0x00000000 + + + IPRIOR224 + IPRIOR224 + Interrupt Priority Register + 0x4E0 + 0x8 + read-write + 0x00000000 + + + IPRIOR225 + IPRIOR225 + Interrupt Priority Register + 0x4E1 + 0x8 + read-write + 0x00000000 + + + IPRIOR226 + IPRIOR226 + Interrupt Priority Register + 0x4E2 + 0x8 + read-write + 0x00000000 + + + IPRIOR227 + IPRIOR227 + Interrupt Priority Register + 0x4E3 + 0x8 + read-write + 0x00000000 + + + IPRIOR228 + IPRIOR228 + Interrupt Priority Register + 0x4E4 + 0x8 + read-write + 0x00000000 + + + IPRIOR229 + IPRIOR229 + Interrupt Priority Register + 0x4E5 + 0x8 + read-write + 0x00000000 + + + IPRIOR230 + IPRIOR230 + Interrupt Priority Register + 0x4E6 + 0x8 + read-write + 0x00000000 + + + IPRIOR231 + IPRIOR231 + Interrupt Priority Register + 0x4E7 + 0x8 + read-write + 0x00000000 + + + IPRIOR232 + IPRIOR232 + Interrupt Priority Register + 0x4E8 + 0x8 + read-write + 0x00000000 + + + IPRIOR233 + IPRIOR233 + Interrupt Priority Register + 0x4E9 + 0x8 + read-write + 0x00000000 + + + IPRIOR234 + IPRIOR234 + Interrupt Priority Register + 0x4EA + 0x8 + read-write + 0x00000000 + + + IPRIOR235 + IPRIOR235 + Interrupt Priority Register + 0x4EB + 0x8 + read-write + 0x00000000 + + + IPRIOR236 + IPRIOR236 + Interrupt Priority Register + 0x4EC + 0x8 + read-write + 0x00000000 + + + IPRIOR237 + IPRIOR237 + Interrupt Priority Register + 0x4ED + 0x8 + read-write + 0x00000000 + + + IPRIOR238 + IPRIOR238 + Interrupt Priority Register + 0x4EE + 0x8 + read-write + 0x00000000 + + + IPRIOR239 + IPRIOR239 + Interrupt Priority Register + 0x4EF + 0x8 + read-write + 0x00000000 + + + IPRIOR240 + IPRIOR240 + Interrupt Priority Register + 0x4F0 + 0x8 + read-write + 0x00000000 + + + IPRIOR241 + IPRIOR241 + Interrupt Priority Register + 0x4F1 + 0x8 + read-write + 0x00000000 + + + IPRIOR242 + IPRIOR242 + Interrupt Priority Register + 0x4F2 + 0x8 + read-write + 0x00000000 + + + IPRIOR243 + IPRIOR243 + Interrupt Priority Register + 0x4F3 + 0x8 + read-write + 0x00000000 + + + IPRIOR244 + IPRIOR244 + Interrupt Priority Register + 0x4F4 + 0x8 + read-write + 0x00000000 + + + IPRIOR245 + IPRIOR245 + Interrupt Priority Register + 0x4F5 + 0x8 + read-write + 0x00000000 + + + IPRIOR246 + IPRIOR246 + Interrupt Priority Register + 0x4F6 + 0x8 + read-write + 0x00000000 + + + IPRIOR247 + IPRIOR247 + Interrupt Priority Register + 0x4F7 + 0x8 + read-write + 0x00000000 + + + IPRIOR248 + IPRIOR248 + Interrupt Priority Register + 0x4F8 + 0x8 + read-write + 0x00000000 + + + IPRIOR249 + IPRIOR249 + Interrupt Priority Register + 0x4F9 + 0x8 + read-write + 0x00000000 + + + IPRIOR250 + IPRIOR250 + Interrupt Priority Register + 0x4FA + 0x8 + read-write + 0x00000000 + + + IPRIOR251 + IPRIOR251 + Interrupt Priority Register + 0x4FB + 0x8 + read-write + 0x00000000 + + + IPRIOR252 + IPRIOR252 + Interrupt Priority Register + 0x4FC + 0x8 + read-write + 0x00000000 + + + IPRIOR253 + IPRIOR253 + Interrupt Priority Register + 0x4FD + 0x8 + read-write + 0x00000000 + + + IPRIOR254 + IPRIOR254 + Interrupt Priority Register + 0x4FE + 0x8 + read-write + 0x00000000 + + + IPRIOR255 + IPRIOR255 + Interrupt Priority Register + 0x4FF + 0x8 + read-write + 0x00000000 + + + SCTLR + SCTLR + System Control Register + 0xd10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + WFITOWFE + WFITOWFE + 3 + 1 + + + SEVONPEND + SEVONPEND + 4 + 1 + + + SETEVENT + SETEVENT + 5 + 1 + + + SYSRESET + SYSRESET + 31 + 1 + + + + + STK_CTLR + STK_CTLR + System counter control register + 0x1000 + 0x20 + 0x00000000 + + + STE + System counter enable + read-write + 0 + 1 + + + STIE + System counter interrupt enable + read-write + 1 + 1 + + + STCLK + System selects the clock source + read-write + 2 + 1 + + + STRE + System reload register + read-write + 3 + 1 + + + MODE + System Mode + read-write + 4 + 1 + + + INIT + System Initialization update + read-write + 5 + 1 + + + SWIE + System software triggered interrupts enable + read-write + 31 + 1 + + + + + STK_SR + System START + 0x1004 + 0x20 + read-write + 0x00000000 + + + CNTIF + CNTIF + 0 + 1 + + + + + STK_CNTL + System counter low register + 0x1008 + 0x20 + read-write + 0x00000000 + + + CNTL + CNTL + 0 + 32 + + + + + STK_CNTH + System counter high register + 0x100C + 0x20 + read-write + 0x00000000 + + + CNTH + CNTH + 0 + 32 + + + + + STK_CMPLR + System compare low register + 0x1010 + 0x20 + read-write + 0x00000000 + + + CMPL + CMPL + 0 + 32 + + + + + STK_CMPHR + System compare high register + 0x1014 + 0x20 + read-write + 0x00000000 + + + CMPH + CMPH + 0 + 32 + + + + + + + diff --git a/port/wch/ch32v/src/hals/hal_ch32v307.zig b/port/wch/ch32v/src/hals/hal_ch32v307.zig new file mode 100644 index 00000000..9368f3d4 --- /dev/null +++ b/port/wch/ch32v/src/hals/hal_ch32v307.zig @@ -0,0 +1,4 @@ +pub const pins = @import("pins.zig"); +pub const gpio = @import("gpio.zig"); + +// pub fn init() void {}