diff --git a/build-internals/build.zig b/build-internals/build.zig
index 057b252e..3cd30f4c 100644
--- a/build-internals/build.zig
+++ b/build-internals/build.zig
@@ -92,6 +92,9 @@ pub const Chip = struct {
/// The cpu target this controller uses.
cpu: std.Target.Query,
+ /// The cpu specific module file, which contains its startup_logic.
+ cpu_module_file: ?LazyPath = null,
+
/// The provider for register definitions.
register_definition: union(enum) {
/// Use `regz` to create a zig file from a JSON schema.
diff --git a/build.zig b/build.zig
index 4ffedb6a..137ca61c 100644
--- a/build.zig
+++ b/build.zig
@@ -12,6 +12,8 @@ pub const MemoryRegion = internals.MemoryRegion;
const regz = @import("tools/regz");
+// If more ports are available, the error "error: evaluation exceeded 1000 backwards branches" may occur.
+// In such cases, consider increasing the argument value for @setEvalBranchQuota().
const port_list: []const struct {
name: [:0]const u8,
dep_name: [:0]const u8,
@@ -24,7 +26,7 @@ const port_list: []const struct {
.{ .name = "lpc", .dep_name = "port/nxp/lpc" },
.{ .name = "rp2xxx", .dep_name = "port/raspberrypi/rp2xxx" },
.{ .name = "stm32", .dep_name = "port/stmicro/stm32" },
- //.{ .name = "ch32v", .dep_name = "port/wch/ch32v" },
+ .{ .name = "ch32v", .dep_name = "port/wch/ch32v" },
};
pub fn build(b: *Build) void {
@@ -315,7 +317,12 @@ pub fn MicroBuild(port_select: PortSelect) type {
},
});
- const cpu_mod = cpu.create_module(b, mb.core_dep);
+ const cpu_mod = if (target.chip.cpu_module_file) |root_source_file|
+ b.createModule(.{
+ .root_source_file = root_source_file,
+ })
+ else
+ cpu.create_module(b, mb.core_dep);
cpu_mod.addImport("microzig", core_mod);
core_mod.addImport("cpu", cpu_mod);
@@ -660,6 +667,7 @@ pub inline fn custom_lazy_import(
}
inline fn custom_find_import_pkg_hash_or_fatal(comptime dep_name: []const u8) []const u8 {
+ @setEvalBranchQuota(2000);
const build_runner = @import("root");
const deps = build_runner.dependencies;
diff --git a/build.zig.zon b/build.zig.zon
index 769caadf..7af42e59 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -20,7 +20,7 @@
.@"port/nxp/lpc" = .{ .path = "port/nxp/lpc", .lazy = true },
.@"port/raspberrypi/rp2xxx" = .{ .path = "port/raspberrypi/rp2xxx", .lazy = true },
.@"port/stmicro/stm32" = .{ .path = "port/stmicro/stm32", .lazy = true },
- //.@"port/wch/ch32v" = .{ .path = "port/wch/ch32v", .lazy = true },
+ .@"port/wch/ch32v" = .{ .path = "port/wch/ch32v", .lazy = true },
// used for creating package tarballs
.boxzer = .{
diff --git a/examples/build.zig b/examples/build.zig
index fa9b5d95..cea00ae3 100644
--- a/examples/build.zig
+++ b/examples/build.zig
@@ -9,7 +9,7 @@ const example_dep_names: []const []const u8 = &.{
"nxp/lpc",
"raspberrypi/rp2xxx",
"stmicro/stm32",
- // "wch/ch32",
+ "wch/ch32v",
};
pub fn build(b: *std.Build) void {
diff --git a/examples/build.zig.zon b/examples/build.zig.zon
index b7251f1d..6103e3f3 100644
--- a/examples/build.zig.zon
+++ b/examples/build.zig.zon
@@ -11,6 +11,7 @@
.@"nxp/lpc" = .{ .path = "nxp/lpc" },
.@"raspberrypi/rp2xxx" = .{ .path = "raspberrypi/rp2xxx" },
.@"stmicro/stm32" = .{ .path = "stmicro/stm32" },
+ .@"wch/ch32v" = .{ .path = "wch/ch32v" },
},
.paths = .{
"build.zig",
diff --git a/examples/wch/ch32v/LICENSE b/examples/wch/ch32v/LICENSE
new file mode 100644
index 00000000..33640972
--- /dev/null
+++ b/examples/wch/ch32v/LICENSE
@@ -0,0 +1,19 @@
+Copyright (c) Zig Embedded Group contributors
+
+This software is provided 'as-is', without any express or implied warranty. In
+no event will the authors be held liable for any damages arising from the use
+of this software.
+
+Permission is granted to anyone to use this software for any purpose, including
+commercial applications, and to alter it and redistribute it freely, subject to
+the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must not claim
+ that you wrote the original software. If you use this software in a product,
+ an acknowledgment in the product documentation would be appreciated but is
+ not required.
+
+2. Altered source versions must be plainly marked as such, and must not be
+ misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source distribution.
diff --git a/examples/wch/ch32v/build.zig b/examples/wch/ch32v/build.zig
index 376c77f4..5e64e96b 100644
--- a/examples/wch/ch32v/build.zig
+++ b/examples/wch/ch32v/build.zig
@@ -1,41 +1,45 @@
const std = @import("std");
-const MicroZig = @import("microzig/build");
-const wch = @import("microzig/port/wch/ch32v");
-
-const available_examples = [_]Example{
- // CH32V003
- .{ .target = wch.chips.ch32v003x4, .name = "empty_ch32v003", .file = "src/empty.zig" },
- .{ .target = wch.chips.ch32v003x4, .name = "blinky_ch32v003", .file = "src/blinky_ch32v003.zig" },
- // .{ .target = wch.boards.ch32v003.ch32v003f4p6_r0_1v1, .name = "ch32v003f4p6_r0_1v1_empty", .file = "src/empty.zig" },
- // .{ .target = wch.boards.ch32v003.ch32v003f4p6_r0_1v1, .name = "ch32v003f4p6_r0_1v1_blinky", .file = "src/blinky.zig" },
-
- // CH32V103
- .{ .target = wch.chips.ch32v103x8, .name = "empty_ch32v103", .file = "src/empty.zig" },
- .{ .target = wch.chips.ch32v103x8, .name = "blinky_ch32v103", .file = "src/blinky.zig" },
- // .{ .target = wch.boards.ch32v103.ch32v103r_r1_1v1, .name = "ch32v103r_r1_1v1_empty", .file = "src/empty.zig" },
- // .{ .target = wch.boards.ch32v103.ch32v103r_r1_1v1, .name = "ch32v103r_r1_1v1_blinky", .file = "src/blinky.zig" },
-
- // CH32V203
- .{ .target = wch.chips.ch32v203x8, .name = "empty_ch32v203", .file = "src/empty.zig" },
- .{ .target = wch.chips.ch32v203x8, .name = "blinky_ch32v203", .file = "src/blinky.zig" },
- .{ .target = wch.boards.ch32v203.suzuduino_uno_v1b, .name = "suzuduino_blinky", .file = "src/board_blinky.zig" },
-};
+const microzig = @import("microzig");
+
+const MicroBuild = microzig.MicroBuild(.{
+ .ch32v = true,
+});
pub fn build(b: *std.Build) void {
- const microzig = MicroZig.init(b, .{});
const optimize = b.standardOptimizeOption(.{});
+ const mz_dep = b.dependency("microzig", .{});
+ const mb = MicroBuild.init(b, mz_dep) orelse return;
+
+ const available_examples = [_]Example{
+ // CH32V003
+ .{ .target = mb.ports.ch32v.chips.ch32v003x4, .name = "empty_ch32v003", .file = "src/empty.zig" },
+ .{ .target = mb.ports.ch32v.chips.ch32v003x4, .name = "blinky_ch32v003", .file = "src/blinky_ch32v003.zig" },
+ .{ .target = mb.ports.ch32v.boards.ch32v003.ch32v003f4p6_r0_1v1, .name = "ch32v003f4p6_r0_1v1_empty", .file = "src/empty.zig" },
+ .{ .target = mb.ports.ch32v.boards.ch32v003.ch32v003f4p6_r0_1v1, .name = "ch32v003f4p6_r0_1v1_blinky", .file = "src/blinky.zig" },
+
+ // CH32V103
+ .{ .target = mb.ports.ch32v.chips.ch32v103x8, .name = "empty_ch32v103", .file = "src/empty.zig" },
+ .{ .target = mb.ports.ch32v.chips.ch32v103x8, .name = "blinky_ch32v103", .file = "src/blinky.zig" },
+ .{ .target = mb.ports.ch32v.boards.ch32v103.ch32v103r_r1_1v1, .name = "ch32v103r_r1_1v1_blinky", .file = "src/blinky.zig" },
+ .{ .target = mb.ports.ch32v.boards.ch32v103.ch32v103r_r1_1v1, .name = "ch32v103r_r1_1v1_empty", .file = "src/empty.zig" },
+
+ // CH32V203
+ .{ .target = mb.ports.ch32v.chips.ch32v203x8, .name = "empty_ch32v203", .file = "src/empty.zig" },
+ .{ .target = mb.ports.ch32v.chips.ch32v203x8, .name = "blinky_ch32v203", .file = "src/blinky.zig" },
+ .{ .target = mb.ports.ch32v.boards.ch32v203.suzuduino_uno_v1b, .name = "suzuduino_blinky", .file = "src/board_blinky.zig" },
+ };
+
for (available_examples) |example| {
// `add_firmware` basically works like addExecutable, but takes a
// `microzig.Target` for target instead of a `std.zig.CrossTarget`.
//
// The target will convey all necessary information on the chip,
// cpu and potentially the board as well.
- const firmware = microzig.add_firmware(b, .{
+ const fw = mb.add_firmware(.{
.name = example.name,
.target = example.target,
.optimize = optimize,
- // .optimize = .ReleaseSmall, // not work -Doptimize=ReleaseSmall
.root_source_file = b.path(example.file),
});
@@ -43,16 +47,15 @@ pub fn build(b: *std.Build) void {
// and allows installing the firmware as a typical firmware file.
//
// This will also install into `$prefix/firmware` instead of `$prefix/bin`.
- microzig.install_firmware(b, firmware, .{ .format = .bin });
+ mb.install_firmware(fw, .{});
// For debugging, we also always install the firmware as an ELF file
- // microzig.install_firmware(b, firmware, .{}); // default format is ELF
- microzig.install_firmware(b, firmware, .{ .format = .elf });
+ mb.install_firmware(fw, .{ .format = .elf });
}
}
const Example = struct {
- target: MicroZig.Target,
+ target: *const microzig.Target,
name: []const u8,
file: []const u8,
};
diff --git a/examples/wch/ch32v/build.zig.zon b/examples/wch/ch32v/build.zig.zon
index 231b652f..c4afd1c8 100644
--- a/examples/wch/ch32v/build.zig.zon
+++ b/examples/wch/ch32v/build.zig.zon
@@ -2,8 +2,7 @@
.name = "examples/wch/ch32v",
.version = "0.0.0",
.dependencies = .{
- .@"microzig/build" = .{ .path = "../../../build" },
- .@"microzig/port/wch/ch32v" = .{ .path = "../../../port/wch/ch32v" },
+ .microzig = .{ .path = "../../.." },
},
.paths = .{
diff --git a/port/wch/ch32v/LICENSE b/port/wch/ch32v/LICENSE
new file mode 100644
index 00000000..33640972
--- /dev/null
+++ b/port/wch/ch32v/LICENSE
@@ -0,0 +1,19 @@
+Copyright (c) Zig Embedded Group contributors
+
+This software is provided 'as-is', without any express or implied warranty. In
+no event will the authors be held liable for any damages arising from the use
+of this software.
+
+Permission is granted to anyone to use this software for any purpose, including
+commercial applications, and to alter it and redistribute it freely, subject to
+the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must not claim
+ that you wrote the original software. If you use this software in a product,
+ an acknowledgment in the product documentation would be appreciated but is
+ not required.
+
+2. Altered source versions must be plainly marked as such, and must not be
+ misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source distribution.
diff --git a/port/wch/ch32v/build.zig b/port/wch/ch32v/build.zig
index c792f530..814a398a 100644
--- a/port/wch/ch32v/build.zig
+++ b/port/wch/ch32v/build.zig
@@ -1,28 +1,43 @@
const std = @import("std");
-const Build = std.Build;
-const MicroZig = @import("microzig/build");
+const microzig = @import("microzig/build-internals");
-fn path(comptime suffix: []const u8) std.Build.LazyPath {
- return .{
- .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix),
+const Self = @This();
+
+chips: struct {
+ ch32v003x4: *const microzig.Target,
+ ch32v103x6: *const microzig.Target,
+ ch32v103x8: *const microzig.Target,
+ ch32v203x6: *const microzig.Target,
+ ch32v203x8: *const microzig.Target,
+},
+
+boards: struct {
+ ch32v003: struct {
+ ch32v003f4p6_r0_1v1: *const microzig.Target,
+ },
+ ch32v103: struct {
+ ch32v103r_r1_1v1: *const microzig.Target,
+ },
+ ch32v203: struct {
+ suzuduino_uno_v1b: *const microzig.Target,
+ },
+},
+
+pub fn init(dep: *std.Build.Dependency) Self {
+ const b = dep.builder;
+
+ const hal_ch32v003: microzig.HardwareAbstractionLayer = .{
+ .root_source_file = b.path("src/hals/hal_ch32v003.zig"),
+ };
+ const hal_ch32v103: microzig.HardwareAbstractionLayer = .{
+ .root_source_file = b.path("src/hals/hal_ch32v103.zig"),
+ };
+ const hal_ch32v203: microzig.HardwareAbstractionLayer = .{
+ .root_source_file = b.path("src/hals/hal_ch32v203.zig"),
};
-}
-const hal_ch32v003 = .{
- .root_source_file = path("/src/hals/hal_ch32v003.zig"),
-};
-const hal_ch32v103 = .{
- .root_source_file = path("/src/hals/hal_ch32v103.zig"),
-};
-const hal_ch32v203 = .{
- .root_source_file = path("/src/hals/hal_ch32v203.zig"),
-};
-
-const qingkev2a = .{
- // QingKe V2C is RV32EmC
- .name = "QingKeV2A",
- .root_source_file = path("/src/cpus/qingkev2-rv32ec.zig"),
- .target = std.Target.Query{
+ const qingkev2a = .{
+ // QingKe V2C is RV32EC
.cpu_arch = .riscv32,
.cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic },
.cpu_features_add = std.Target.riscv.featureSet(&.{
@@ -32,13 +47,9 @@ const qingkev2a = .{
}),
.os_tag = .freestanding,
.abi = .none,
- },
-};
+ };
-const qingkev3 = .{
- .name = "QingKeV3",
- .root_source_file = path("/src/cpus/qingkev3-rv32imac.zig"),
- .target = std.Target.Query{
+ const qingkev3 = .{
.cpu_arch = .riscv32,
.cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
// generic_rv32 has feature I.
@@ -49,13 +60,9 @@ const qingkev3 = .{
}),
.os_tag = .freestanding,
.abi = .none,
- },
-};
+ };
-const qingkev4b = .{
- .name = "QingKeV4B",
- .root_source_file = path("/src/cpus/qingkev4-rv32imac.zig"),
- .target = std.Target.Query{
+ const qingkev4b = .{
.cpu_arch = .riscv32,
.cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
// generic_rv32 has feature I.
@@ -66,136 +73,148 @@ const qingkev4b = .{
}),
.os_tag = .freestanding,
.abi = .none,
- },
-};
+ };
-pub const chips = struct {
- pub const ch32v003x4 = MicroZig.Target{
- .preferred_format = .elf,
+ const chip_ch32v003x4: microzig.Target = .{
+ .dep = dep,
+ .preferred_binary_format = .bin,
.chip = .{
.name = "CH32V00xxx", // from SVD
.cpu = qingkev2a,
+ .cpu_module_file = b.path("src/cpus/qingkev2-rv32ec.zig"),
+ .register_definition = .{
+ .svd = b.path("src/chips/ch32v003.svd"),
+ },
.memory_regions = &.{
.{ .offset = 0x08000000, .length = 16 * 1024, .kind = .flash },
.{ .offset = 0x20000000, .length = 2 * 1024, .kind = .ram },
},
- .register_definition = .{
- .svd = path("/src/chips/ch32v003.svd"),
- },
},
.hal = hal_ch32v003,
};
- pub const ch32v103x8 = MicroZig.Target{
- .preferred_format = .bin,
+ const chip_ch32v103x8 = microzig.Target{
+ .dep = dep,
+ .preferred_binary_format = .bin,
.chip = .{
.name = "CH32V103xx", // from SVD
.cpu = qingkev3,
- // .cpu = MicroZig.cpus.riscv32_imac,
+ // .cpu = microzig.cpus.riscv32_imac,
+ .cpu_module_file = b.path("src/cpus/qingkev3-rv32imac.zig"),
.memory_regions = &.{
.{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash },
.{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram },
},
.register_definition = .{
- .svd = path("/src/chips/ch32v103.svd"),
+ .svd = b.path("src/chips/ch32v103.svd"),
},
},
.hal = hal_ch32v103,
};
- pub const ch32v103x6 = MicroZig.Target{
- .preferred_format = .bin,
+ const chip_ch32v103x6 = microzig.Target{
+ .dep = dep,
+ .preferred_binary_format = .bin,
.chip = .{
.name = "CH32V103xx", // from SVD
.cpu = qingkev3,
- // .cpu = MicroZig.cpus.riscv32_imac,
+ // .cpu = microzig.cpus.riscv32_imac,
+ .cpu_module_file = b.path("src/cpus/qingkev3-rv32imac.zig"),
.memory_regions = &.{
.{ .offset = 0x08000000, .length = 32 * 1024, .kind = .flash },
.{ .offset = 0x20000000, .length = 10 * 1024, .kind = .ram },
},
.register_definition = .{
- .svd = path("/src/chips/ch32v103.svd"),
+ .svd = b.path("src/chips/ch32v103.svd"),
},
},
.hal = hal_ch32v103,
};
- pub const ch32v203x8 = MicroZig.Target{
- .preferred_format = .bin,
+ const chip_ch32v203x8 = microzig.Target{
+ .dep = dep,
+
+ .preferred_binary_format = .bin,
.chip = .{
.name = "CH32V20xxx", // from SVD
.cpu = qingkev4b,
- // .cpu = MicroZig.cpus.riscv32_imac,
+ .cpu_module_file = b.path("src/cpus/qingkev4-rv32imac.zig"),
.memory_regions = &.{
.{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash },
.{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram },
},
.register_definition = .{
- .svd = path("/src/chips/ch32v20x.svd"),
+ .svd = b.path("src/chips/ch32v20x.svd"),
},
},
.hal = hal_ch32v203,
};
- pub const ch32v203x6 = MicroZig.Target{
- .preferred_format = .bin,
+ const chip_ch32v203x6 = microzig.Target{
+ .dep = dep,
+ .preferred_binary_format = .bin,
.chip = .{
.name = "CH32V20xxx", // from SVD
.cpu = qingkev4b,
- // .cpu = MicroZig.cpus.riscv32_imac,
+ .cpu_module_file = b.path("src/cpus/qingkev4-rv32imac.zig"),
.memory_regions = &.{
.{ .offset = 0x08000000, .length = 32 * 1024, .kind = .flash },
.{ .offset = 0x20000000, .length = 10 * 1024, .kind = .ram },
},
.register_definition = .{
- .svd = path("/src/chips/ch32v20x.svd"),
+ .svd = b.path("src/chips/ch32v20x.svd"),
},
},
.hal = hal_ch32v203,
};
-};
-
-pub const boards = struct {
- pub const ch32v003 = struct {
- pub const ch32v003f4p6_r0_1v1 = MicroZig.Target{
- .preferred_format = .elf,
- .chip = chips.ch32v003.chip,
- .hal = hal_ch32v003,
- .board = .{
- .name = "WCH CH32V003F4P6-R0-1v1",
- .url = "https://www.wch-ic.com/products/CH32V003.html",
- .root_source_file = path("/src/boards/CH32V003F4P6-R0-1v1.zig"),
- },
- };
- };
- pub const ch32v103 = struct {
- pub const ch32v103r_r1_1v1 = MicroZig.Target{
- .preferred_format = .bin,
- .chip = chips.ch32v103x8.chip,
- .hal = hal_ch32v103,
- .board = .{
- .name = "WCH CH32V103R-R1-1v1",
- .url = "https://github.com/openwch/ch32v103/tree/main/SCHPCB/CH32V103R-R1-1v1",
- .root_source_file = path("/src/boards/CH32V103-R1-1v1.zig"),
- },
- };
- };
+ const board_ch32v003f4p6_r0_1v1 = chip_ch32v003x4.derive(.{
+ .board = .{
+ .name = "WCH CH32V003F4P6-R0-1v1",
+ .url = "https://www.wch-ic.com/products/CH32V003.html",
+ .root_source_file = b.path("src/boards/CH32V003F4P6-R0-1v1.zig"),
+ },
+ });
+
+ const board_ch32v103r_r1_1v1 = chip_ch32v103x8.derive(.{
+ .board = .{
+ .name = "WCH CH32V103R-R1-1v1",
+ .url = "https://github.com/openwch/ch32v103/tree/main/SCHPCB/CH32V103R-R1-1v1",
+ .root_source_file = b.path("src/boards/CH32V103-R1-1v1.zig"),
+ },
+ });
- pub const ch32v203 = struct {
- pub const suzuduino_uno_v1b = MicroZig.Target{
- .preferred_format = .bin,
- .chip = chips.ch32v203x8.chip,
- .hal = hal_ch32v203,
- .board = .{
- .name = "WCH Suzuduino Uno V1b",
- .url = "https://github.com/verylowfreq/suzuduino-uno-v1",
- .root_source_file = path("/src/boards/Suzuduino_Uno_V1b.zig"),
+ const board_suzuduino_uno_v1b = chip_ch32v203x8.derive(.{
+ .board = .{
+ .name = "WCH Suzuduino Uno V1b",
+ .url = "https://github.com/verylowfreq/suzuduino-uno-v1",
+ .root_source_file = b.path("src/boards/Suzuduino_Uno_V1b.zig"),
+ },
+ });
+
+ return .{
+ .chips = .{
+ .ch32v003x4 = chip_ch32v003x4.derive(.{}),
+ .ch32v103x6 = chip_ch32v103x6.derive(.{}),
+ .ch32v103x8 = chip_ch32v103x8.derive(.{}),
+ .ch32v203x6 = chip_ch32v203x6.derive(.{}),
+ .ch32v203x8 = chip_ch32v203x8.derive(.{}),
+ },
+
+ .boards = .{
+ .ch32v003 = .{
+ .ch32v003f4p6_r0_1v1 = board_ch32v003f4p6_r0_1v1,
},
- };
+ .ch32v103 = .{
+ .ch32v103r_r1_1v1 = board_ch32v103r_r1_1v1,
+ },
+ .ch32v203 = .{
+ .suzuduino_uno_v1b = board_suzuduino_uno_v1b,
+ },
+ },
};
-};
+}
-pub fn build(b: *Build) void {
+pub fn build(b: *std.Build) void {
_ = b.step("test", "Run platform agnostic unit tests");
}
diff --git a/port/wch/ch32v/build.zig.zon b/port/wch/ch32v/build.zig.zon
index 19626dae..0853d582 100644
--- a/port/wch/ch32v/build.zig.zon
+++ b/port/wch/ch32v/build.zig.zon
@@ -2,7 +2,7 @@
.name = "port/wch/ch32v",
.version = "0.0.0",
.dependencies = .{
- .@"microzig/build" = .{ .path = "../../../build" },
+ .@"microzig/build-internals" = .{ .path = "../../../build-internals" },
},
.paths = .{
"LICENSE",
diff --git a/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig b/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig
index c960ddb8..f2ebb0fd 100644
--- a/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig
+++ b/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig
@@ -37,7 +37,7 @@ pub const startup_logic = struct {
extern fn microzig_main() noreturn;
- pub fn _start() linksection("microzig_flash_start") callconv(.C) noreturn {
+ pub fn _start() callconv(.C) noreturn {
microzig.cpu.disable_interrupts(); // Power-on reset makes interrupts disbaled.
// set global pointer
diff --git a/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig b/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig
index 6c3e56f4..a56bb3ed 100644
--- a/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig
+++ b/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig
@@ -43,7 +43,7 @@ pub const startup_logic = struct {
extern fn microzig_main() noreturn;
- pub fn _start() linksection("microzig_flash_start") callconv(.C) noreturn {
+ pub fn _start() callconv(.C) noreturn {
microzig.cpu.disable_interrupts(); // Power-on reset makes interrupts disbaled.
// set global pointer
diff --git a/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig b/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig
index 0b627334..a7ca345e 100644
--- a/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig
+++ b/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig
@@ -37,7 +37,7 @@ pub const startup_logic = struct {
extern fn microzig_main() noreturn;
- pub fn _start() linksection("microzig_flash_start") callconv(.C) noreturn {
+ pub fn _start() callconv(.C) noreturn {
microzig.cpu.disable_interrupts(); // Power-on reset makes interrupts disbaled.
// set global pointer