diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index a5306bcd..5007abaf 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -32,7 +32,9 @@ jobs: run: zig build -Doptimize=ReleaseSmall - name: Unit Test Ports - run: zig build run-port-tests -Doptimize=ReleaseSmall + run: | + cd port/raspberrypi/rp2xxx + zig build test - name: Build Website run: zig build diff --git a/build/LICENSE b/build-internals/LICENSE similarity index 100% rename from build/LICENSE rename to build-internals/LICENSE diff --git a/build-internals/README.md b/build-internals/README.md new file mode 100644 index 00000000..00d4cd59 --- /dev/null +++ b/build-internals/README.md @@ -0,0 +1,4 @@ +# build-internals + +This package is meant to provide build related type definitions for +internal use in the repo (avoiding circular dependencies). diff --git a/build-internals/build.zig b/build-internals/build.zig new file mode 100644 index 00000000..e1692381 --- /dev/null +++ b/build-internals/build.zig @@ -0,0 +1,285 @@ +const std = @import("std"); +const Build = std.Build; +const LazyPath = Build.LazyPath; +const Module = Build.Module; + +pub fn build(b: *Build) void { + _ = b.addModule("build-internals", .{ + .root_source_file = b.path("build.zig"), + }); +} + +/// A compilation target for MicroZig. Provides information about the chip, +/// hal, board and so on. +/// +/// This is used instead of `std.Target.Query` to define a MicroZig Firmware. +pub const Target = struct { + /// The `*std.Build.Dependency` belonging of the port that created this target. + dep: *Build.Dependency, + + /// The preferred binary format of this MicroZig target, if it has one. + preferred_binary_format: ?BinaryFormat = null, + + /// The chip this target uses. + chip: Chip, + + /// Usually, embedded projects are single-threaded and single-core applications. Platforms that + /// support multiple CPUs should set this to `false`. + single_threaded: bool = true, + + /// Determines whether the compiler_rt package is bundled with the application or not. + /// This should always be true except for platforms where compiler_rt cannot be built right now. + bundle_compiler_rt: bool = true, + + /// (optional) Provides a default hardware abstraction layer that is used. + /// If `null`, no `microzig.hal` will be available. + hal: ?HardwareAbstractionLayer = null, + + /// (optional) Provides description of external hardware and connected devices + /// like oscillators and such. + /// + /// This structure isn't used by MicroZig itself, but can be utilized from the HAL + /// if present. + board: ?Board = null, + + /// (optional) Provide a custom linker script for the hardware or define a custom generation. + linker_script: ?LazyPath = null, + + /// (optional) Post processing step that will patch up and modify the elf file if necessary. + patch_elf: ?*const fn (*Build.Dependency, LazyPath) LazyPath = null, + + /// Things you can change by deriving from an already existing target. + pub const DeriveOptions = struct { + preferred_binary_format: ?BinaryFormat = null, + chip: ?Chip = null, + single_threaded: ?bool = null, + bundle_compiler_rt: ?bool = null, + hal: ?HardwareAbstractionLayer = null, + board: ?Board = null, + linker_script: ?LazyPath = null, + patch_elf: ?*const fn (*Build.Dependency, LazyPath) LazyPath = null, + }; + + /// Creates a new target from an existing one. + pub fn derive(from: *const Target, options: DeriveOptions) *Target { + const ret = from.dep.builder.allocator.create(Target) catch @panic("out of memory"); + ret.* = .{ + .dep = from.dep, + .preferred_binary_format = options.preferred_binary_format orelse from.preferred_binary_format, + .chip = options.chip orelse from.chip, + .single_threaded = options.single_threaded orelse from.single_threaded, + .bundle_compiler_rt = options.bundle_compiler_rt orelse from.bundle_compiler_rt, + .hal = options.hal orelse from.hal, + .board = options.board orelse from.board, + .linker_script = options.linker_script orelse from.linker_script, + .patch_elf = options.patch_elf orelse from.patch_elf, + }; + return ret; + } +}; + +/// Defines a chip. +pub const Chip = struct { + /// The display name of the controller. + name: []const u8, + + /// (optional) link to the documentation/vendor page of the controller. + url: ?[]const u8 = null, + + /// The cpu target this controller uses. + cpu: std.Target.Query, + + /// The provider for register definitions. + register_definition: union(enum) { + /// Use `regz` to create a zig file from a JSON schema. + json: LazyPath, + + /// Use `regz` to create a json file from a SVD schema. + svd: LazyPath, + + /// Use `regz` to create a zig file from an ATDF schema. + atdf: LazyPath, + + /// Use the provided file directly as the chip file. + zig: LazyPath, + }, + + /// The memory regions that are present in this chip. + memory_regions: []const MemoryRegion, +}; + +/// Defines a hardware abstraction layer. +pub const HardwareAbstractionLayer = struct { + /// Provides the root source file for the HAL. + root_source_file: LazyPath, + + /// Provides imports for the HAL. **Need to be heap allocated.** + imports: []const Module.Import = &.{}, +}; + +/// Provides a description of a board. +/// +/// Boards provide additional information to a chip and HAL package. +/// For example, they can list attached peripherials, external crystal frequencies, +/// flash sizes, ... +pub const Board = struct { + /// Display name of the board. + name: []const u8, + + /// (optional) link to the documentation/vendor page of the board. + url: ?[]const u8 = null, + + /// Provides the root source file for the board definition. + root_source_file: LazyPath, + + /// (optional) Provides imports for the board definition. **Need to be heap allocated.** + imports: []const Module.Import = &.{}, +}; + +/// Convenience struct for heap allocated imports. +pub const ModuleImports = struct { + /// List of imports. + list: []const Module.Import = &.{}, + + /// Initializes module imports on the heap. + pub fn init(allocator: std.mem.Allocator, imports: []const Module.Import) ModuleImports { + return .{ + .list = allocator.dupe(imports) catch @panic("out of memory"), + }; + } +}; + +/// The resulting binary format for the firmware file. +/// A lot of embedded systems don't use plain ELF files, thus we provide means +/// to convert the resulting ELF into other common formats. +pub const BinaryFormat = union(enum) { + /// [Executable and Linkable Format](https://en.wikipedia.org/wiki/Executable_and_Linkable_Format), the standard output from the compiler. + elf, + + /// A flat binary, contains only the loaded portions of the firmware with an unspecified base offset. + bin, + + /// The [Intel HEX](https://en.wikipedia.org/wiki/Intel_HEX) format, contains + /// an ASCII description of what memory to load where. + hex, + + /// A [Device Firmware Upgrade](https://www.usb.org/sites/default/files/DFU_1.1.pdf) file. + dfu, + + /// The [USB Flashing Format (UF2)](https://github.com/microsoft/uf2) designed by Microsoft. + uf2: enum { + ATMEGA32, + SAML21, + NRF52, + ESP32, + STM32L1, + STM32L0, + STM32WL, + LPC55, + STM32G0, + GD32F350, + STM32L5, + STM32G4, + MIMXRT10XX, + STM32F7, + SAMD51, + STM32F4, + FX2, + STM32F2, + STM32F1, + NRF52833, + STM32F0, + SAMD21, + STM32F3, + STM32F407, + STM32H7, + STM32WB, + ESP8266, + KL32L2, + STM32F407VG, + NRF52840, + ESP32S2, + ESP32S3, + ESP32C3, + ESP32C2, + ESP32H2, + RP2040, + RP2XXX_ABSOLUTE, + RP2XXX_DATA, + RP2350_ARM_S, + RP2350_RISC_V, + RP2350_ARM_NS, + STM32L4, + GD32VF103, + CSK4, + CSK6, + M0SENSE, + }, + + /// The [firmware format](https://docs.espressif.com/projects/esptool/en/latest/esp32/advanced-topics/firmware-image-format.html) used by the [esptool](https://github.com/espressif/esptool) bootloader. + esp, + + /// Custom option for non-standard formats. + custom: *Custom, + + /// Returns the standard extension for the resulting binary file. + pub fn get_extension(format: BinaryFormat) []const u8 { + return switch (format) { + .elf => ".elf", + .bin => ".bin", + .hex => ".hex", + .dfu => ".dfu", + .uf2 => ".uf2", + .esp => ".bin", + + .custom => |c| c.extension, + }; + } + + pub const Custom = struct { + /// The standard extension of the format. + extension: []const u8, + + /// A function that will convert a given `elf` file into the custom output format. + convert: *const fn (*Build.Dependency, elf: Build.LazyPath) Build.LazyPath, + }; +}; + +/// A descriptor for memory regions in a microcontroller. +pub const MemoryRegion = struct { + /// The type of the memory region for generating a proper linker script. + kind: Kind, + offset: u64, + length: u64, + + pub const Kind = union(enum) { + /// This is a (normally) immutable memory region where the code is stored. + flash, + + /// This is a mutable memory region for data storage. + ram, + + /// This is a memory region that maps MMIO devices. + io, + + /// This is a memory region that exists, but is reserved and must not be used. + reserved, + + /// This is a memory region used for internal linking tasks required by the board support package. + private: PrivateRegion, + }; + + pub const PrivateRegion = struct { + /// The name of the memory region. Will not have an automatic numeric counter and must be unique. + name: []const u8, + + /// Is the memory region executable? + executable: bool, + + /// Is the memory region readable? + readable: bool, + + /// Is the memory region writable? + writeable: bool, + }; +}; diff --git a/build/definitions/build.zig.zon b/build-internals/build.zig.zon similarity index 78% rename from build/definitions/build.zig.zon rename to build-internals/build.zig.zon index aa88dfd8..cbe11ee8 100644 --- a/build/definitions/build.zig.zon +++ b/build-internals/build.zig.zon @@ -1,5 +1,5 @@ .{ - .name = "build/definitions", + .name = "build-internals", .version = "0.0.0", .paths = .{ "LICENSE", diff --git a/build.zig b/build.zig index da0b3ee5..faba2ecb 100644 --- a/build.zig +++ b/build.zig @@ -1,42 +1,45 @@ const std = @import("std"); const Build = std.Build; +const LazyPath = Build.LazyPath; -const MicroZig = @import("build/definitions"); - -const example_dep_names: []const []const u8 = &.{ - "examples/nordic/nrf5x", - "examples/nxp/lpc", - "examples/microchip/atsam", - "examples/microchip/avr", - "examples/gigadevice/gd32", - "examples/stmicro/stm32", - //"examples/espressif/esp", - "examples/raspberrypi/rp2xxx", -}; +const internals = @import("build-internals"); +pub const Target = internals.Target; +pub const Chip = internals.Chip; +pub const HardwareAbstractionLayer = internals.HardwareAbstractionLayer; +pub const Board = internals.Board; +pub const BinaryFormat = internals.BinaryFormat; +pub const MemoryRegion = internals.MemoryRegion; -const ports = .{ - .{ "port/nordic/nrf5x", @import("port/nordic/nrf5x") }, - .{ "port/nxp/lpc", @import("port/nxp/lpc") }, - .{ "port/microchip/atsam", @import("port/microchip/atsam") }, - .{ "port/microchip/avr", @import("port/microchip/avr") }, - .{ "port/gigadevice/gd32", @import("port/gigadevice/gd32") }, - .{ "port/stmicro/stm32", @import("port/stmicro/stm32") }, - .{ "port/espressif/esp", @import("port/espressif/esp") }, - .{ "port/raspberrypi/rp2xxx", @import("port/raspberrypi/rp2xxx") }, +const port_list: []const struct { + name: [:0]const u8, + dep_name: [:0]const u8, +} = &.{ + // .{ .name = "esp", .dep_name = "port/espressif/esp" }, + .{ .name = "gd32", .dep_name = "port/gigadevice/gd32" }, + .{ .name = "atsam", .dep_name = "port/microchip/atsam" }, + .{ .name = "avr", .dep_name = "port/microchip/avr" }, + .{ .name = "nrf5x", .dep_name = "port/nordic/nrf5x" }, + .{ .name = "lpc", .dep_name = "port/nxp/lpc" }, + .{ .name = "rp2xxx", .dep_name = "port/raspberrypi/rp2xxx" }, + .{ .name = "stm32", .dep_name = "port/stmicro/stm32" }, }; pub fn build(b: *Build) void { const optimize = b.standardOptimizeOption(.{}); - // Build all examples - for (example_dep_names) |example_dep_name| { - const example_dep = b.dependency(example_dep_name, .{ - .optimize = optimize, - }); + const generate_linker_script_exe = b.addExecutable(.{ + .name = "generate_linker_script", + .root_source_file = b.path("tools/generate_linker_script.zig"), + .target = b.host, + .optimize = optimize, + }); - const example_dep_install_step = example_dep.builder.getInstallStep(); - b.getInstallStep().dependOn(example_dep_install_step); - } + generate_linker_script_exe.root_module.addImport( + "build-internals", + b.dependency("build-internals", .{}).module("build-internals"), + ); + + b.installArtifact(generate_linker_script_exe); const boxzer_dep = b.dependency("boxzer", .{}); const boxzer_exe = boxzer_dep.artifact("boxzer"); @@ -46,12 +49,565 @@ pub fn build(b: *Build) void { const package_step = b.step("package", "Package monorepo using boxzer"); package_step.dependOn(&boxzer_run.step); +} + +pub const PortSelect = blk: { + var fields: []const std.builtin.Type.StructField = &.{}; + for (port_list) |port| { + fields = fields ++ [_]std.builtin.Type.StructField{.{ + .name = port.name, + .type = bool, + .default_value = @as(*const anyopaque, @ptrCast(&false)), + .is_comptime = false, + .alignment = @alignOf(bool), + }}; + } + break :blk @Type(.{ + .Struct = .{ + .layout = .auto, + .fields = fields, + .decls = &.{}, + .is_tuple = false, + }, + }); +}; + +// Don't know if this is required but it doesn't hurt either. +// Helps in case there are multiple microzig instances including the same ports (eg: examples). +pub const PortCache = blk: { + var fields: []const std.builtin.Type.StructField = &.{}; + for (port_list) |port| { + const typ = ?(custom_lazy_import(port.dep_name) orelse struct {}); + fields = fields ++ [_]std.builtin.Type.StructField{.{ + .name = port.name, + .type = typ, + .default_value = @as(*const anyopaque, @ptrCast(&@as(typ, null))), + .is_comptime = false, + .alignment = @alignOf(typ), + }}; + } + break :blk @Type(.{ + .Struct = .{ + .layout = .auto, + .fields = fields, + .decls = &.{}, + .is_tuple = false, + }, + }); +}; + +var port_cache: PortCache = .{}; + +/// The MicroZig build system. +pub fn MicroBuild(port_select: PortSelect) type { + return struct { + const SelectedPorts = blk: { + var fields: []const std.builtin.Type.StructField = &.{}; + + for (port_list) |port| { + if (@field(port_select, port.name)) { + const typ = custom_lazy_import(port.dep_name) orelse struct {}; + fields = fields ++ [_]std.builtin.Type.StructField{.{ + .name = port.name, + .type = typ, + .default_value = null, + .is_comptime = false, + .alignment = @alignOf(typ), + }}; + } + } + + break :blk @Type(.{ + .Struct = .{ + .layout = .auto, + .fields = fields, + .decls = &.{}, + .is_tuple = false, + }, + }); + }; - const test_ports_step = b.step("run-port-tests", "Run all platform agnostic tests for Ports"); - inline for (ports) |port| { - const port_dep = b.dependency(port[0], .{}); - if (port_dep.builder.top_level_steps.get("test")) |test_step| { - test_ports_step.dependOn(&test_step.step); + const Self = @This(); + + builder: *Build, + dep: *Build.Dependency, + core_dep: *Build.Dependency, + drivers_dep: *Build.Dependency, + + /// Contains all the ports you selected. + ports: SelectedPorts, + + const InitReturnType = blk: { + var ok = true; + for (port_list) |port| { + if (@field(port_select, port.name)) { + ok = ok and custom_lazy_import(port.dep_name) != null; + } + } + if (ok) { + break :blk *Self; + } else { + break :blk noreturn; + } + }; + + /// Initializes the microzig build system. + // TODO: should we call this `create`? + pub fn init(b: *Build, dep: *Build.Dependency) InitReturnType { + if (InitReturnType == noreturn) { + inline for (port_list) |port| { + if (@field(port_select, port.name)) { + _ = dep.builder.lazyDependency(port.dep_name, .{}); + } + } + std.process.exit(0); + } + + var ports: SelectedPorts = undefined; + inline for (port_list) |port| { + if (@field(port_select, port.name)) { + @field(ports, port.name) = if (@field(port_cache, port.name)) |cached_port| cached_port else blk: { + const port_dep = dep.builder.lazyDependency(port.dep_name, .{}).?; + const instance = custom_lazy_import(port.dep_name).?.init(port_dep); + @field(port_cache, port.name) = instance; + break :blk instance; + }; + } + } + + const mb = b.allocator.create(Self) catch @panic("out of memory"); + mb.* = .{ + .builder = b, + .dep = dep, + .core_dep = dep.builder.dependency("core", .{}), + .drivers_dep = dep.builder.dependency("drivers", .{}), + .ports = ports, + }; + return mb; } + + /// Configuration options for the `add_firmware` function. + pub const CreateFirmwareOptions = struct { + /// The name of the firmware file. + name: []const u8, + + /// The MicroZig target that the firmware is built for. Either a board or a chip. + target: *const Target, + + /// The optimization level that should be used. Usually `ReleaseSmall` or `Debug` is a good choice. + /// Also using `std.Build.standardOptimizeOption` is a good idea. + optimize: std.builtin.OptimizeMode, + + /// The root source file for the application. This is your `src/main.zig` file. + root_source_file: LazyPath, + + /// Imports for the application. + imports: []const Build.Module.Import = &.{}, + + /// If set, overrides the `single_threaded` property of the target. + single_threaded: ?bool = null, + + /// If set, overrides the `bundle_compiler_rt` property of the target. + bundle_compiler_rt: ?bool = null, + + /// If set, overrides the `hal` module. + hal: ?*Build.Module = null, + + /// If set, overrides the `board` module. + board: ?*Build.Module = null, + + /// If set, overrides the `linker_script` property of the target. + linker_script: ?LazyPath = null, + + /// Strips stack trace info from final executable. + strip: bool = false, + + /// Enables the following build options for the firmware executable + /// to support stripping unused symbols in all modes (not just Release): + /// exe.link_gc_sections = true; + /// exe.link_data_sections = true; + /// exe.link_function_sections = true; + strip_unused_symbols: bool = true, + }; + + /// Creates a new firmware for a given target. + pub fn add_firmware(mb: *Self, options: CreateFirmwareOptions) *Firmware { + const b = mb.dep.builder; + + const target = options.target; + const zig_target = mb.dep.builder.resolveTargetQuery(target.chip.cpu); + const cpu = Cpu.init(zig_target.result); + + // TODO: let the user override which ram section to use the stack on, + // for now just using the first ram section in the memory region list + const first_ram = blk: { + for (target.chip.memory_regions) |region| { + if (region.kind == .ram) + break :blk region; + } else @panic("no ram memory region found for setting the end-of-stack address"); + }; + + const config = mb.dep.builder.addOptions(); + config.addOption(bool, "has_hal", options.hal != null or target.hal != null); + config.addOption(bool, "has_board", options.board != null or target.board != null); + + config.addOption([]const u8, "cpu_name", zig_target.result.cpu.model.name); + config.addOption([]const u8, "chip_name", target.chip.name); + config.addOption(usize, "end_of_stack", first_ram.offset + first_ram.length); + + const core_mod = b.createModule(.{ + .root_source_file = mb.core_dep.path("src/microzig.zig"), + .imports = &.{ + .{ + .name = "config", + .module = config.createModule(), + }, + .{ + .name = "drivers", + .module = mb.drivers_dep.module("drivers"), + }, + }, + }); + + const cpu_mod = cpu.create_module(b, mb.core_dep); + cpu_mod.addImport("microzig", core_mod); + core_mod.addImport("cpu", cpu_mod); + + const regz_exe = b.dependency("tools/regz", .{}).artifact("regz"); + const chip_source = switch (target.chip.register_definition) { + .json, .atdf, .svd => |file| blk: { + const regz_run = b.addRunArtifact(regz_exe); + + regz_run.addArg("--schema"); // Explicitly set schema type, one of: svd, atdf, json + regz_run.addArg(@tagName(target.chip.register_definition)); + + regz_run.addArg("--output_path"); // Write to a file + const zig_file = regz_run.addOutputFileArg("chip.zig"); + + regz_run.addFileArg(file); + + break :blk zig_file; + }, + + .zig => |src| src, + }; + const chip_mod = b.createModule(.{ + .root_source_file = chip_source, + }); + + chip_mod.addImport("microzig", core_mod); + core_mod.addImport("chip", chip_mod); + + if (target.hal) |hal| { + const hal_mod = options.hal orelse b.createModule(.{ + .root_source_file = hal.root_source_file, + .imports = hal.imports, + }); + hal_mod.addImport("microzig", core_mod); + core_mod.addImport("hal", hal_mod); + } + + if (target.board) |board| { + const board_mod = options.board orelse b.createModule(.{ + .root_source_file = board.root_source_file, + .imports = board.imports, + }); + board_mod.addImport("microzig", core_mod); + core_mod.addImport("board", board_mod); + } + + const app_mod = mb.builder.createModule(.{ + .root_source_file = options.root_source_file, + .imports = options.imports, + }); + app_mod.addImport("microzig", core_mod); + + const fw = mb.builder.allocator.create(Firmware) catch @panic("out of memory"); + fw.* = .{ + .mb = mb, + .artifact = mb.builder.addExecutable(.{ + .name = options.name, + .optimize = options.optimize, + .target = zig_target, + .linkage = .static, + .root_source_file = mb.core_dep.path("src/start.zig"), + .strip = options.strip, + }), + .app_mod = app_mod, + .target = target, + .emitted_files = Firmware.EmittedFiles.init(mb.builder.allocator), + }; + + fw.artifact.bundle_compiler_rt = options.bundle_compiler_rt orelse fw.target.bundle_compiler_rt; + + fw.artifact.link_gc_sections = options.strip_unused_symbols; + fw.artifact.link_function_sections = options.strip_unused_symbols; + fw.artifact.link_data_sections = options.strip_unused_symbols; + + fw.artifact.root_module.addImport("microzig", core_mod); + fw.artifact.root_module.addImport("app", app_mod); + + // If not specified then generate the linker script + const linker_script = options.linker_script orelse target.linker_script orelse blk: { + const GenerateLinkerScriptArgs = @import("tools/generate_linker_script.zig").Args; + + const generate_linker_script_exe = mb.dep.artifact("generate_linker_script"); + + const generate_linker_script_args: GenerateLinkerScriptArgs = .{ + .cpu_name = zig_target.result.cpu.model.name, + .cpu_arch = zig_target.result.cpu.arch, + .chip_name = target.chip.name, + .memory_regions = target.chip.memory_regions, + }; + + const args_str = std.json.stringifyAlloc( + b.allocator, + generate_linker_script_args, + .{}, + ) catch @panic("out of memory"); + + const generate_linker_script_run = b.addRunArtifact(generate_linker_script_exe); + generate_linker_script_run.addArg(args_str); + break :blk generate_linker_script_run.addOutputFileArg("linker.ld"); + }; + fw.artifact.setLinkerScript(linker_script); + + return fw; + } + + /// Configuration options for firmware installation. + pub const InstallFirmwareOptions = struct { + format: ?BinaryFormat = null, + }; + + /// Adds a new dependency to the `install` step that will install the `firmware` into the folder `$prefix/firmware`. + pub fn install_firmware(mb: *Self, fw: *Firmware, options: InstallFirmwareOptions) void { + std.debug.assert(mb == fw.mb); + + const install_step = add_install_firmware(mb, fw, options); + mb.builder.getInstallStep().dependOn(&install_step.step); + } + + /// Creates a new `std.Build.Step.InstallFile` instance that will install the given firmware to `$prefix/firmware`. + /// + /// **NOTE:** This does not actually install the firmware yet. You have to add the returned step as a dependency to another step. + /// If you want to just install the firmware, use `installFirmware` instead! + pub fn add_install_firmware(mb: *Self, fw: *Firmware, options: InstallFirmwareOptions) *Build.Step.InstallFile { + std.debug.assert(mb == fw.mb); + + const format = options.format orelse fw.target.preferred_binary_format orelse .elf; + + const basename = mb.builder.fmt("{s}{s}", .{ + fw.artifact.name, + format.get_extension(), + }); + + return mb.builder.addInstallFileWithDir(fw.get_emitted_bin(format), .{ .custom = "firmware" }, basename); + } + + /// Declaration of a firmware build. + pub const Firmware = struct { + pub const EmittedFiles = std.AutoHashMap(BinaryFormat, LazyPath); + + mb: *Self, + + /// The artifact that is built by MicroZig. + artifact: *Build.Step.Compile, + + /// The app module that is built by Zig. + app_mod: *Build.Module, + + /// The target to which the firmware is built. + target: *const Target, + + emitted_elf: ?LazyPath = null, + emitted_files: EmittedFiles, + + /// Returns the emitted ELF file for this firmware. This is useful if you need debug information + /// or want to use a debugger like Segger, ST-Link or similar. + /// + /// **NOTE:** This is similar, but not equivalent to `std.Build.Step.Compile.getEmittedBin`. The call on the compile step does + /// not include post processing of the ELF files necessary by certain targets. + pub fn get_emitted_elf(fw: *Firmware) LazyPath { + if (fw.emitted_elf == null) { + const raw_elf = fw.artifact.getEmittedBin(); + fw.emitted_elf = if (fw.target.patch_elf) |patch_elf| + patch_elf(fw.target.dep, raw_elf) + else + raw_elf; + } + return fw.emitted_elf.?; + } + + /// Returns the emitted binary for this firmware. The file is either in the preferred file format for + /// the target or in `format` if not null. + /// + /// **NOTE:** The file returned here is the same file that will be installed. + pub fn get_emitted_bin(fw: *Firmware, format: ?BinaryFormat) LazyPath { + const resolved_format = format orelse fw.target.preferred_binary_format orelse .elf; + + const result = fw.emitted_files.getOrPut(resolved_format) catch @panic("out of memory"); + if (!result.found_existing) { + const elf_file = fw.get_emitted_elf(); + + const basename = fw.mb.builder.fmt("{s}{s}", .{ + fw.artifact.name, + resolved_format.get_extension(), + }); + + result.value_ptr.* = switch (resolved_format) { + .elf => elf_file, + + .bin => blk: { + const objcopy = fw.mb.builder.addObjCopy(elf_file, .{ + .basename = basename, + .format = .bin, + }); + + break :blk objcopy.getOutput(); + }, + + .hex => blk: { + const objcopy = fw.mb.builder.addObjCopy(elf_file, .{ + .basename = basename, + .format = .hex, + }); + + break :blk objcopy.getOutput(); + }, + + .uf2 => |family_id| blk: { + const uf2_exe = fw.mb.dep.builder.dependency("tools/uf2", .{ .optimize = .ReleaseSafe }).artifact("elf2uf2"); + + const convert = fw.mb.builder.addRunArtifact(uf2_exe); + + convert.addArg("--family-id"); + convert.addArg(@tagName(family_id)); + + convert.addArg("--elf-path"); + convert.addFileArg(elf_file); + + convert.addArg("--output-path"); + break :blk convert.addOutputFileArg(basename); + }, + + .dfu => @panic("DFU is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/145 for more details!"), + .esp => @panic("ESP firmware image is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/146 for more details!"), + + .custom => |generator| generator.convert(fw.target.dep, elf_file), + }; + } + + return result.value_ptr.*; + } + + /// Configuration options for the `add_app_import` function. + pub const AppDependencyOptions = struct { + depend_on_microzig: bool = false, + }; + + /// Adds an import to your application. + pub fn add_app_import(fw: *Firmware, name: []const u8, module: *Build.Module, options: AppDependencyOptions) void { + if (options.depend_on_microzig) { + module.addImport("microzig", fw.modules.microzig); + } + fw.app_mod.addImport(name, module); + } + + /// Adds an include path to the firmware. + pub fn add_include_path(fw: *Firmware, path: LazyPath) void { + fw.artifact.addIncludePath(path); + } + + /// Adds a system include path to the firmware. + pub fn add_system_include_path(fw: *Firmware, path: LazyPath) void { + fw.artifact.addSystemIncludePath(path); + } + + /// Adds a c source file to the firmware. + pub fn add_c_source_file(fw: *Firmware, source: Build.Module.CSourceFile) void { + fw.artifact.addCSourceFile(source); + } + + /// Adds options to your application. + pub fn add_options(fw: *Firmware, module_name: []const u8, options: *Build.Step.Options) void { + fw.app_mod.addOptions(module_name, options); + } + + /// Adds an object file to the firmware. + pub fn add_object_file(fw: *Firmware, source: LazyPath) void { + fw.artifact.addObjectFile(source); + } + }; + }; +} + +const Cpu = enum { + avr5, + cortex_m, + riscv32, + + // TODO: to be verified + pub fn init(target: std.Target) Cpu { + if (std.mem.eql(u8, target.cpu.model.name, "avr5")) { + return .avr5; + } else if (std.mem.startsWith(u8, target.cpu.model.name, "cortex_m")) { + return .cortex_m; + } else if (target.cpu.arch.isRISCV() and target.ptrBitWidth() == 32) { + return .riscv32; + } + + @panic("unrecognized cpu configuration"); } + + pub fn create_module(cpu: Cpu, b: *Build, core_dep: *Build.Dependency) *Build.Module { + return b.createModule(.{ + .root_source_file = switch (cpu) { + .avr5 => core_dep.path("src/cpus/avr5.zig"), + .cortex_m => core_dep.path("src/cpus/cortex_m.zig"), + .riscv32 => core_dep.path("src/cpus/riscv32.zig"), + }, + }); + } +}; + +pub inline fn custom_lazy_import( + comptime dep_name: []const u8, +) ?type { + const build_runner = @import("root"); + const deps = build_runner.dependencies; + const pkg_hash = custom_find_import_pkg_hash_or_fatal(dep_name); + + inline for (@typeInfo(deps.packages).Struct.decls) |decl| { + if (comptime std.mem.eql(u8, decl.name, pkg_hash)) { + const pkg = @field(deps.packages, decl.name); + const available = !@hasDecl(pkg, "available") or pkg.available; + if (!available) { + return null; + } + return if (@hasDecl(pkg, "build_zig")) + pkg.build_zig + else + @compileError("dependency '" ++ dep_name ++ "' does not have a build.zig"); + } + } + + comptime unreachable; // Bad @dependencies source +} + +inline fn custom_find_import_pkg_hash_or_fatal(comptime dep_name: []const u8) []const u8 { + const build_runner = @import("root"); + const deps = build_runner.dependencies; + + const pkg_deps = comptime for (@typeInfo(deps.packages).Struct.decls) |decl| { + const pkg_hash = decl.name; + const pkg = @field(deps.packages, pkg_hash); + if (@hasDecl(pkg, "build_zig") and pkg.build_zig == @This()) break pkg.deps; + } else deps.root_deps; + + comptime for (pkg_deps) |dep| { + if (std.mem.eql(u8, dep[0], dep_name)) return dep[1]; + }; + + @panic("dependency not found"); } diff --git a/build.zig.zon b/build.zig.zon index 829c3387..a60bdf6d 100644 --- a/build.zig.zon +++ b/build.zig.zon @@ -3,30 +3,23 @@ .version = "0.13.0", .minimum_zig_version = "0.13.0", .dependencies = .{ - // packages within the monorepo so that others can reach them - .build = .{ .path = "build" }, - .@"build/definitions" = .{ .path = "build/definitions" }, + .@"build-internals" = .{ .path = "build-internals" }, .core = .{ .path = "core" }, + .drivers = .{ .path = "drivers" }, + + // tools .@"tools/regz" = .{ .path = "tools/regz" }, .@"tools/uf2" = .{ .path = "tools/uf2" }, - .@"port/nordic/nrf5x" = .{ .path = "port/nordic/nrf5x" }, - .@"port/nxp/lpc" = .{ .path = "port/nxp/lpc" }, - .@"port/microchip/atsam" = .{ .path = "port/microchip/atsam" }, - .@"port/microchip/avr" = .{ .path = "port/microchip/avr" }, - .@"port/gigadevice/gd32" = .{ .path = "port/gigadevice/gd32" }, - .@"port/stmicro/stm32" = .{ .path = "port/stmicro/stm32" }, - .@"port/espressif/esp" = .{ .path = "port/espressif/esp" }, - .@"port/raspberrypi/rp2xxx" = .{ .path = "port/raspberrypi/rp2xxx" }, - // examples so that we can build them all in one go - .@"examples/nordic/nrf5x" = .{ .path = "examples/nordic/nrf5x" }, - .@"examples/nxp/lpc" = .{ .path = "examples/nxp/lpc" }, - .@"examples/microchip/atsam" = .{ .path = "examples/microchip/atsam" }, - .@"examples/microchip/avr" = .{ .path = "examples/microchip/avr" }, - .@"examples/gigadevice/gd32" = .{ .path = "examples/gigadevice/gd32" }, - .@"examples/stmicro/stm32" = .{ .path = "examples/stmicro/stm32" }, - .@"examples/espressif/esp" = .{ .path = "examples/espressif/esp" }, - .@"examples/raspberrypi/rp2xxx" = .{ .path = "examples/raspberrypi/rp2xxx" }, + // ports + // .@"port/espressif/esp" = .{ .path = "port/espressif/esp", .lazy = true }, + .@"port/gigadevice/gd32" = .{ .path = "port/gigadevice/gd32", .lazy = true }, + .@"port/microchip/atsam" = .{ .path = "port/microchip/atsam", .lazy = true }, + .@"port/microchip/avr" = .{ .path = "port/microchip/avr", .lazy = true }, + .@"port/nordic/nrf5x" = .{ .path = "port/nordic/nrf5x", .lazy = true }, + .@"port/nxp/lpc" = .{ .path = "port/nxp/lpc", .lazy = true }, + .@"port/raspberrypi/rp2xxx" = .{ .path = "port/raspberrypi/rp2xxx", .lazy = true }, + .@"port/stmicro/stm32" = .{ .path = "port/stmicro/stm32", .lazy = true }, // used for creating package tarballs .boxzer = .{ @@ -34,7 +27,6 @@ .hash = "12202157366306cd7fb005defe138bf8aeccfa903850d234b1c1edc1ca8071e4a931", }, }, - .paths = .{ "README.md", "build.zig", @@ -42,5 +34,6 @@ "LICENSE", "design", "docs", + "tools/generate_linker_script.zig", }, } diff --git a/build/README.md b/build/README.md deleted file mode 100644 index 0f1955c0..00000000 --- a/build/README.md +++ /dev/null @@ -1,4 +0,0 @@ -# MicroZig Build Support - -This package is meant to provide build utilities to create embedded firmware easily. - diff --git a/build/build.zig b/build/build.zig deleted file mode 100644 index b64cf05b..00000000 --- a/build/build.zig +++ /dev/null @@ -1,642 +0,0 @@ -//! MicroZig Build Interface -host_build: *Build, -self: *Build.Dependency, -microzig_core: *Build.Dependency, -drivers_dep: *Build.Dependency, -generate_linkerscript: *Build.Step.Compile, - -const std = @import("std"); -const Build = std.Build; -const LazyPath = Build.LazyPath; - -const uf2 = @import("microzig/tools/uf2"); -const core = @import("microzig/core"); -const defs = @import("microzig/build/definitions"); -pub const Chip = defs.Chip; -pub const Cpu = defs.Cpu; -pub const HardwareAbstractionLayer = defs.HardwareAbstractionLayer; -pub const BoardDefinition = defs.BoardDefinition; - -const MicroZig = @This(); - -/// This build script validates usage patterns we expect from MicroZig -pub fn build(b: *Build) !void { - const uf2_dep = b.dependency("microzig/tools/uf2", .{}); - - const build_test = b.addTest(.{ - .root_source_file = b.path("build.zig"), - }); - - build_test.root_module.addAnonymousImport("uf2", .{ - .root_source_file = .{ .cwd_relative = uf2_dep.builder.pathFromRoot("build.zig") }, - }); - - const install_docs = b.addInstallDirectory(.{ - .source_dir = build_test.getEmittedDocs(), - .install_dir = .prefix, - .install_subdir = "docs", - }); - - b.getInstallStep().dependOn(&install_docs.step); -} - -fn root() []const u8 { - return comptime (std.fs.path.dirname(@src().file) orelse "."); -} -/// Creates a new MicroZig build environment that can be used to create new firmware. -pub fn init(b: *Build, opts: struct { - dependency_name: []const u8 = "microzig/build", -}) *MicroZig { - const mz_dep = b.dependency(opts.dependency_name, .{}); - const core_dep = mz_dep.builder.dependency("microzig/core", .{}); - const drivers_dep = mz_dep.builder.dependency("microzig/drivers", .{}); - const ret = b.allocator.create(MicroZig) catch @panic("OOM"); - ret.* = - MicroZig{ - .host_build = b, - .self = mz_dep, - .microzig_core = core_dep, - .drivers_dep = drivers_dep, - .generate_linkerscript = mz_dep.builder.addExecutable(.{ - .name = "generate-linkerscript", - .root_source_file = .{ .cwd_relative = comptime root() ++ "/src/generate_linkerscript.zig" }, - .target = mz_dep.builder.host, - }), - }; - - const defs_dep = mz_dep.builder.dependency("microzig/build/definitions", .{}); - ret.generate_linkerscript.root_module.addImport("microzig/build/definitions", defs_dep.module("definitions")); - - return ret; -} - -pub fn add_firmware( - /// The MicroZig instance that should be used to create the firmware. - mz: *MicroZig, - /// The instance of the `build.zig` that is calling this function. - host_build: *Build, - /// Options that define how the firmware is built. - options: FirmwareOptions, -) *Firmware { - const micro_build = mz.self.builder; - - const chip = &options.target.chip; - const maybe_hal = options.hal orelse options.target.hal; - const maybe_board = options.board orelse options.target.board; - - const linker_script = options.linker_script orelse options.target.linker_script; - - // TODO: let the user override which ram section to use the stack on, - // for now just using the first ram section in the memory region list - const first_ram = blk: { - for (chip.memory_regions) |region| { - if (region.kind == .ram) - break :blk region; - } else @panic("no ram memory region found for setting the end-of-stack address"); - }; - - // On demand, generate chip definitions via regz: - const chip_source = switch (chip.register_definition) { - .json, .atdf, .svd => |file| blk: { - const regz_exe = mz.dependency("microzig/tools/regz", .{ .optimize = .ReleaseSafe }).artifact("regz"); - - const regz_gen = host_build.addRunArtifact(regz_exe); - - regz_gen.addArg("--schema"); // Explicitly set schema type, one of: svd, atdf, json - regz_gen.addArg(@tagName(chip.register_definition)); - - regz_gen.addArg("--output_path"); // Write to a file - const zig_file = regz_gen.addOutputFileArg("chip.zig"); - - regz_gen.addFileArg(file); - - break :blk zig_file; - }, - - .zig => |src| src, - }; - - const config = host_build.addOptions(); - config.addOption(bool, "has_hal", (maybe_hal != null)); - config.addOption(bool, "has_board", (maybe_board != null)); - - config.addOption(?[]const u8, "board_name", if (maybe_board) |brd| brd.name else null); - - config.addOption([]const u8, "chip_name", chip.name); - config.addOption([]const u8, "cpu_name", chip.cpu.name); - config.addOption(usize, "end_of_stack", first_ram.offset + first_ram.length); - - const fw: *Firmware = host_build.allocator.create(Firmware) catch @panic("out of memory"); - fw.* = Firmware{ - .mz = mz, - .host_build = host_build, - .artifact = host_build.addExecutable(.{ - .name = options.name, - .optimize = options.optimize, - .target = mz.host_build.resolveTargetQuery(chip.cpu.target), - .linkage = .static, - .root_source_file = .{ .cwd_relative = mz.microzig_core.builder.pathFromRoot("src/start.zig") }, - .strip = options.strip, - }), - .target = options.target, - .output_files = Firmware.OutputFileMap.init(host_build.allocator), - .config = config, - .modules = .{ - .microzig = micro_build.createModule(.{ - .root_source_file = .{ .cwd_relative = mz.microzig_core.builder.pathFromRoot("src/microzig.zig") }, - .imports = &.{ - .{ - .name = "config", - .module = micro_build.createModule(.{ .root_source_file = config.getSource() }), - }, - .{ - .name = "drivers", - .module = mz.drivers_dep.module("drivers"), - }, - }, - }), - .cpu = undefined, - .chip = undefined, - .board = null, - .hal = null, - .app = undefined, - }, - }; - errdefer fw.output_files.deinit(); - - fw.artifact.link_gc_sections = options.strip_unused_symbols; - fw.artifact.link_function_sections = options.strip_unused_symbols; - fw.artifact.link_data_sections = options.strip_unused_symbols; - - fw.modules.chip = micro_build.createModule(.{ - .root_source_file = chip_source, - .imports = &.{ - .{ .name = "microzig", .module = fw.modules.microzig }, - }, - }); - fw.modules.microzig.addImport("chip", fw.modules.chip); - - fw.modules.cpu = micro_build.createModule(.{ - .root_source_file = chip.cpu.root_source_file, - .imports = &.{ - .{ .name = "microzig", .module = fw.modules.microzig }, - }, - }); - fw.modules.microzig.addImport("cpu", fw.modules.cpu); - - if (maybe_hal) |hal| { - fw.modules.hal = micro_build.createModule(.{ - .root_source_file = hal.root_source_file, - .imports = &.{ - .{ .name = "microzig", .module = fw.modules.microzig }, - }, - }); - fw.modules.microzig.addImport("hal", fw.modules.hal.?); - } - - if (maybe_board) |brd| { - fw.modules.board = micro_build.createModule(.{ - .root_source_file = brd.root_source_file, - .imports = &.{ - .{ .name = "microzig", .module = fw.modules.microzig }, - }, - }); - fw.modules.microzig.addImport("board", fw.modules.board.?); - } - - fw.modules.app = host_build.createModule(.{ - .root_source_file = options.root_source_file, - .imports = &.{ - .{ .name = "microzig", .module = fw.modules.microzig }, - }, - }); - - //const umm = mz.microzig_core.builder.dependency("umm-zig", .{}).module("umm"); - //fw.modules.microzig.addImport("umm", umm); - - fw.artifact.root_module.addImport("app", fw.modules.app); - fw.artifact.root_module.addImport("microzig", fw.modules.microzig); - - fw.artifact.bundle_compiler_rt = options.bundle_compiler_rt orelse fw.target.bundle_compiler_rt; - - if (linker_script) |ls| { - fw.artifact.setLinkerScriptPath(ls); - } else { - const target = mz.host_build.resolveTargetQuery(chip.cpu.target); - const generate_linkerscript_args = GenerateLinkerscriptArgs{ - .cpu_name = target.result.cpu.model.name, - .cpu_arch = target.result.cpu.arch, - .chip_name = chip.name, - .memory_regions = chip.memory_regions, - }; - - const args_str = std.json.stringifyAlloc( - mz.microzig_core.builder.allocator, - generate_linkerscript_args, - .{}, - ) catch @panic("OOM"); - - const generate_linkerscript_run = mz.microzig_core.builder.addRunArtifact(mz.generate_linkerscript); - generate_linkerscript_run.addArg(args_str); - const linkerscript = generate_linkerscript_run.addOutputFileArg("linker.ld"); - - // If not specified then generate the linker script - fw.artifact.setLinkerScript(linkerscript); - } - - if (options.target.configure) |configure| { - configure(fw.mz, fw); - } - - return fw; -} - -const GenerateLinkerscriptArgs = @import("src/generate_linkerscript.zig").Args; - -/// Adds a new dependency to the `install` step that will install the `firmware` into the folder `$prefix/firmware`. -pub fn install_firmware( - /// The MicroZig instance that was used to create the firmware. - mz: *MicroZig, - /// The instance of the `build.zig` that should perform installation. - b: *Build, - /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`. - firmware: *Firmware, - /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here. - options: InstallFirmwareOptions, -) void { - std.debug.assert(mz == firmware.mz); - const install_step = add_install_firmware(mz, b, firmware, options); - b.getInstallStep().dependOn(&install_step.step); -} - -/// Creates a new `std.Build.Step.InstallFile` instance that will install the given firmware to `$prefix/firmware`. -/// -/// **NOTE:** This does not actually install the firmware yet. You have to add the returned step as a dependency to another step. -/// If you want to just install the firmware, use `installFirmware` instead! -pub fn add_install_firmware( - /// The MicroZig instance that was used to create the firmware. - mz: *MicroZig, - /// The instance of the `build.zig` that should perform installation. - b: *Build, - /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`. - firmware: *Firmware, - /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here. - options: InstallFirmwareOptions, -) *Build.Step.InstallFile { - _ = mz; - const format = firmware.resolve_format(options.format); - - const basename = b.fmt("{s}{s}", .{ - firmware.artifact.name, - format.get_extension(), - }); - - return b.addInstallFileWithDir(firmware.get_emitted_bin(format), .{ .custom = "firmware" }, basename); -} - -fn dependency(env: *MicroZig, name: []const u8, args: anytype) *Build.Dependency { - return env.self.builder.dependency(name, args); -} - -pub const cpus = core.cpus; - -/// A compilation target for MicroZig. Provides information about the chip, -/// hal, board and so on. -/// -/// This is used instead of `std.zig.CrossTarget` to define a MicroZig Firmware. -pub const Target = struct { - /// The preferred binary format of this MicroZig target. If `null`, the user must - /// explicitly give the `.format` field during a call to `getEmittedBin()` or installation steps. - preferred_format: ?BinaryFormat, - - /// The chip this target uses, - chip: Chip, - - /// Usually, embedded projects are single-threaded and single-core applications. Platforms that - /// support multiple CPUs should set this to `false`. - single_threaded: bool = true, - - /// Determines whether the compiler_rt package is bundled with the application or not. - /// This should always be true except for platforms where compiler_rt cannot be built right now. - bundle_compiler_rt: bool = true, - - /// (optional) Provides a default hardware abstraction layer that is used. - /// If `null`, no `microzig.hal` will be available. - hal: ?HardwareAbstractionLayer = null, - - /// (optional) Provides description of external hardware and connected devices - /// like oscillators and such. - /// - /// This structure isn't used by MicroZig itself, but can be utilized from the HAL - /// if present. - board: ?BoardDefinition = null, - - /// (optional) Provide a custom linker script for the hardware or define a custom generation. - linker_script: ?LazyPath = null, - - /// (optional) Further configures the created firmware depending on the chip and/or board settings. - /// This can be used to set/change additional properties on the created `*Firmware` object. - configure: ?*const fn (env: *MicroZig, *Firmware) void = null, - - /// (optional) Post processing step that will patch up and modify the elf file if necessary. - binary_post_process: ?*const fn (host_build: *std.Build, LazyPath) std.Build.LazyPath = null, -}; - -/// Options to the `add_firmware` function. -pub const FirmwareOptions = struct { - /// The name of the firmware file. - name: []const u8, - - /// The MicroZig target that the firmware is built for. Either a board or a chip. - target: Target, - - /// The optimization level that should be used. Usually `ReleaseSmall` or `Debug` is a good choice. - /// Also using `std.Build.standardOptimizeOption` is a good idea. - optimize: std.builtin.OptimizeMode, - - /// The root source file for the application. This is your `src/main.zig` file. - root_source_file: LazyPath, - - // Overrides: - - /// If set, overrides the `single_threaded` property of the target. - single_threaded: ?bool = null, - - /// If set, overrides the `bundle_compiler_rt` property of the target. - bundle_compiler_rt: ?bool = null, - - /// If set, overrides the `hal` property of the target. - hal: ?HardwareAbstractionLayer = null, - - /// If set, overrides the `board` property of the target. - board: ?BoardDefinition = null, - - /// If set, overrides the `linker_script` property of the target. - linker_script: ?LazyPath = null, - - /// Strips stack trace info from final executable. - strip: bool = false, - - /// Enables the following build options for the firmware executable - /// to support stripping unused symbols in all modes (not just Release): - /// exe.link_gc_sections = true; - /// exe.link_data_sections = true; - /// exe.link_function_sections = true; - strip_unused_symbols: bool = true, -}; - -/// Configuration options for firmware installation. -pub const InstallFirmwareOptions = struct { - /// Overrides the output format for the binary. If not set, the standard preferred file format for the firmware target is used. - format: ?BinaryFormat = null, -}; - -/// Declaration of a firmware build. -pub const Firmware = struct { - const OutputFileMap = std.ArrayHashMap(BinaryFormat, LazyPath, BinaryFormat.Context, false); - - const Modules = struct { - app: *std.Build.Module, - cpu: *std.Build.Module, - chip: *std.Build.Module, - board: ?*std.Build.Module, - hal: ?*std.Build.Module, - microzig: *std.Build.Module, - }; - - // privates: - mz: *MicroZig, - host_build: *std.Build, - target: Target, - output_files: OutputFileMap, - - // publics: - - /// The artifact that is built by Zig. - artifact: *std.Build.Step.Compile, - - /// The options step that provides `microzig.config`. If you need custom configuration, you can add this here. - config: *std.Build.Step.Options, - - /// Declaration of the MicroZig modules used by this firmware. - modules: Modules, - - /// Path to the emitted elf file, if any. - emitted_elf: ?LazyPath = null, - - /// Returns the emitted ELF file for this firmware. This is useful if you need debug information - /// or want to use a debugger like Segger, ST-Link or similar. - /// - /// **NOTE:** This is similar, but not equivalent to `std.Build.Step.Compile.getEmittedBin`. The call on the compile step does - /// not include post processing of the ELF files necessary by certain targets. - pub fn get_emitted_elf(firmware: *Firmware) LazyPath { - if (firmware.emitted_elf == null) { - const raw_elf = firmware.artifact.getEmittedBin(); - firmware.emitted_elf = if (firmware.target.binary_post_process) |binary_post_process| - binary_post_process(firmware.host_build, raw_elf) - else - raw_elf; - } - return firmware.emitted_elf.?; - } - - /// Returns the emitted binary for this firmware. The file is either in the preferred file format for - /// the target or in `format` if not null. - /// - /// **NOTE:** The file returned here is the same file that will be installed. - pub fn get_emitted_bin(firmware: *Firmware, format: ?BinaryFormat) LazyPath { - const actual_format = firmware.resolve_format(format); - - const gop = firmware.output_files.getOrPut(actual_format) catch @panic("out of memory"); - if (!gop.found_existing) { - const elf_file = firmware.get_emitted_elf(); - - const basename = firmware.host_build.fmt("{s}{s}", .{ - firmware.artifact.name, - actual_format.get_extension(), - }); - - gop.value_ptr.* = switch (actual_format) { - .elf => elf_file, - - .bin => blk: { - const objcopy = firmware.host_build.addObjCopy(elf_file, .{ - .basename = basename, - .format = .bin, - }); - - break :blk objcopy.getOutput(); - }, - - .hex => blk: { - const objcopy = firmware.host_build.addObjCopy(elf_file, .{ - .basename = basename, - .format = .hex, - }); - - break :blk objcopy.getOutput(); - }, - - .uf2 => |family_id| blk: { - const uf2_exe = firmware.mz.dependency("microzig/tools/uf2", .{ .optimize = .ReleaseSafe }).artifact("elf2uf2"); - - const convert = firmware.host_build.addRunArtifact(uf2_exe); - - convert.addArg("--family-id"); - convert.addArg(firmware.host_build.fmt("0x{X:0>4}", .{@intFromEnum(family_id)})); - - convert.addArg("--elf-path"); - convert.addFileArg(elf_file); - - convert.addArg("--output-path"); - break :blk convert.addOutputFileArg(basename); - }, - - .dfu => build_config_error(firmware.host_build, "DFU is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/145 for more details!", .{}), - .esp => build_config_error(firmware.host_build, "ESP firmware image is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/146 for more details!", .{}), - - .custom => |generator| generator.convert(generator, elf_file), - }; - } - return gop.value_ptr.*; - } - - pub const AppDependencyOptions = struct { - depend_on_microzig: bool = false, - }; - - /// Adds a regular dependency to your application. - pub fn add_app_import(fw: *Firmware, name: []const u8, module: *std.Build.Module, options: AppDependencyOptions) void { - if (options.depend_on_microzig) { - module.addImport("microzig", fw.modules.microzig); - } - fw.modules.app.addImport(name, module); - } - - pub fn add_include_path(fw: *Firmware, path: LazyPath) void { - fw.artifact.addIncludePath(path); - } - - pub fn add_system_include_path(fw: *Firmware, path: LazyPath) void { - fw.artifact.addSystemIncludePath(path); - } - - pub fn add_c_source_file(fw: *Firmware, source: std.Build.Step.Compile.CSourceFile) void { - fw.artifact.addCSourceFile(source); - } - - pub fn add_options(fw: *Firmware, module_name: []const u8, options: *std.Build.Step.Options) void { - fw.modules.app.addOptions(module_name, options); - } - - pub fn add_object_file(fw: *Firmware, source: LazyPath) void { - fw.artifact.addObjectFile(source); - } - - fn resolve_format(firmware: *Firmware, format: ?BinaryFormat) BinaryFormat { - if (format) |fmt| return fmt; - - if (firmware.target.preferred_format) |fmt| return fmt; - - build_config_error(firmware.host_build, "{s} has no preferred output format, please provide one in the `format` option.", .{ - firmware.target.chip.name, - }); - } -}; - -fn build_config_error(b: *std.Build, comptime fmt: []const u8, args: anytype) noreturn { - const msg = b.fmt(fmt, args); - @panic(msg); -} - -/// The resulting binary format for the firmware file. -/// A lot of embedded systems don't use plain ELF files, thus we provide means -/// to convert the resulting ELF into other common formats. -pub const BinaryFormat = union(enum) { - /// [Executable and Linkable Format](https://en.wikipedia.org/wiki/Executable_and_Linkable_Format), the standard output from the compiler. - elf, - - /// A flat binary, contains only the loaded portions of the firmware with an unspecified base offset. - bin, - - /// The [Intel HEX](https://en.wikipedia.org/wiki/Intel_HEX) format, contains - /// an ASCII description of what memory to load where. - hex, - - /// A [Device Firmware Upgrade](https://www.usb.org/sites/default/files/DFU_1.1.pdf) file. - dfu, - - /// The [USB Flashing Format (UF2)](https://github.com/microsoft/uf2) designed by Microsoft. - uf2: uf2.FamilyId, - - /// The [firmware format](https://docs.espressif.com/projects/esptool/en/latest/esp32/advanced-topics/firmware-image-format.html) used by the [esptool](https://github.com/espressif/esptool) bootloader. - esp, - - /// Custom option for non-standard formats. - custom: *Custom, - - /// Returns the standard extension for the resulting binary file. - pub fn get_extension(format: BinaryFormat) []const u8 { - return switch (format) { - .elf => ".elf", - .bin => ".bin", - .hex => ".hex", - .dfu => ".dfu", - .uf2 => ".uf2", - .esp => ".bin", - - .custom => |c| c.extension, - }; - } - - pub const Custom = struct { - /// The standard extension of the format. - extension: []const u8, - - /// A function that will convert a given `elf` file into the custom output format. - /// - /// The `*Custom` format is passed so contextual information can be obtained by using - /// `@fieldParentPtr` to provide access to tooling. - convert: *const fn (*Custom, elf: Build.LazyPath) Build.LazyPath, - }; - - const Enum = std.meta.Tag(BinaryFormat); - - pub const Context = struct { - pub fn hash(self: @This(), fmt: BinaryFormat) u32 { - _ = self; - - var hasher = std.hash.XxHash32.init(0x1337_42_21); - - hasher.update(@tagName(fmt)); - - switch (fmt) { - .elf, .bin, .hex, .dfu, .esp => |val| { - if (@TypeOf(val) != void) @compileError("Missing update: Context.hash now requires special care!"); - }, - - .uf2 => |family_id| hasher.update(@tagName(family_id)), - .custom => |custom| hasher.update(std.mem.asBytes(custom)), - } - - return hasher.final(); - } - - pub fn eql(self: @This(), fmt_a: BinaryFormat, fmt_b: BinaryFormat, index: usize) bool { - _ = self; - _ = index; - if (@as(BinaryFormat.Enum, fmt_a) != @as(BinaryFormat.Enum, fmt_b)) - return false; - - return switch (fmt_a) { - .elf, .bin, .hex, .dfu, .esp => |val| { - if (@TypeOf(val) != void) @compileError("Missing update: Context.eql now requires special care!"); - return true; - }, - - .uf2 => |a| (a == fmt_b.uf2), - .custom => |a| (a == fmt_b.custom), - }; - } - }; -}; diff --git a/build/build.zig.zon b/build/build.zig.zon deleted file mode 100644 index b5fb1740..00000000 --- a/build/build.zig.zon +++ /dev/null @@ -1,29 +0,0 @@ -.{ - .name = "build", - .version = "0.0.1", - .dependencies = .{ - .@"microzig/tools/uf2" = .{ - .path = "../tools/uf2", - }, - .@"microzig/tools/regz" = .{ - .path = "../tools/regz", - }, - .@"microzig/core" = .{ - .path = "../core", - }, - .@"microzig/build/definitions" = .{ - .path = "definitions", - }, - .@"microzig/drivers" = .{ - .path = "../drivers", - }, - }, - - .paths = .{ - "README.md", - "build.zig", - "build.zig.zon", - "LICENSE", - "src", - }, -} diff --git a/build/definitions/LICENSE b/build/definitions/LICENSE deleted file mode 100644 index 33640972..00000000 --- a/build/definitions/LICENSE +++ /dev/null @@ -1,19 +0,0 @@ -Copyright (c) Zig Embedded Group contributors - -This software is provided 'as-is', without any express or implied warranty. In -no event will the authors be held liable for any damages arising from the use -of this software. - -Permission is granted to anyone to use this software for any purpose, including -commercial applications, and to alter it and redistribute it freely, subject to -the following restrictions: - -1. The origin of this software must not be misrepresented; you must not claim - that you wrote the original software. If you use this software in a product, - an acknowledgment in the product documentation would be appreciated but is - not required. - -2. Altered source versions must be plainly marked as such, and must not be - misrepresented as being the original software. - -3. This notice may not be removed or altered from any source distribution. diff --git a/build/definitions/build.zig b/build/definitions/build.zig deleted file mode 100644 index deee1cbe..00000000 --- a/build/definitions/build.zig +++ /dev/null @@ -1,112 +0,0 @@ -const std = @import("std"); -const Build = std.Build; -const LazyPath = Build.LazyPath; - -pub fn build(b: *Build) void { - _ = b.addModule("definitions", .{ - .root_source_file = b.path("build.zig"), - }); -} - -/// A cpu descriptor. -pub const Cpu = struct { - /// Display name of the CPU. - name: []const u8, - - /// Source file providing startup code and memory initialization routines. - root_source_file: LazyPath, - - /// The compiler target we use to compile all the code. - target: std.Target.Query, -}; - -/// Defines a custom microcontroller. -pub const Chip = struct { - /// The display name of the controller. - name: []const u8, - - /// (optional) link to the documentation/vendor page of the controller. - url: ?[]const u8 = null, - - /// The cpu model this controller uses. - cpu: Cpu, - - /// The provider for register definitions. - register_definition: union(enum) { - /// Use `regz` to create a zig file from a JSON schema. - json: LazyPath, - - /// Use `regz` to create a json file from a SVD schema. - svd: LazyPath, - - /// Use `regz` to create a zig file from an ATDF schema. - atdf: LazyPath, - - /// Use the provided file directly as the chip file. - zig: LazyPath, - }, - - /// The memory regions that are present in this chip. - memory_regions: []const MemoryRegion, -}; - -/// Defines a hardware abstraction layer. -pub const HardwareAbstractionLayer = struct { - /// Root source file for this HAL. - root_source_file: LazyPath, -}; - -/// Provides a description of a board. -/// -/// Boards provide additional information to a chip and HAL package. -/// For example, they can list attached peripherials, external crystal frequencies, -/// flash sizes, ... -pub const BoardDefinition = struct { - /// Display name of the board - name: []const u8, - - /// (optional) link to the documentation/vendor page of the board. - url: ?[]const u8 = null, - - /// Provides the root file for the board definition. - root_source_file: LazyPath, -}; - -/// A descriptor for memory regions in a microcontroller. -pub const MemoryRegion = struct { - /// The type of the memory region for generating a proper linker script. - kind: Kind, - offset: u64, - length: u64, - - pub const Kind = union(enum) { - /// This is a (normally) immutable memory region where the code is stored. - flash, - - /// This is a mutable memory region for data storage. - ram, - - /// This is a memory region that maps MMIO devices. - io, - - /// This is a memory region that exists, but is reserved and must not be used. - reserved, - - /// This is a memory region used for internal linking tasks required by the board support package. - private: PrivateRegion, - }; - - pub const PrivateRegion = struct { - /// The name of the memory region. Will not have an automatic numeric counter and must be unique. - name: []const u8, - - /// Is the memory region executable? - executable: bool, - - /// Is the memory region readable? - readable: bool, - - /// Is the memory region writable? - writeable: bool, - }; -}; diff --git a/core/build.zig b/core/build.zig index 31ce44a9..b611db41 100644 --- a/core/build.zig +++ b/core/build.zig @@ -3,12 +3,6 @@ //! This means we need to use addExecutable() instead of using const std = @import("std"); -const MicroZig = @import("microzig/build/definitions"); - -fn root() []const u8 { - return comptime (std.fs.path.dirname(@src().file) orelse "."); -} -const build_root = root(); /// This build script validates usage patterns we expect from MicroZig pub fn build(b: *std.Build) !void { @@ -22,127 +16,3 @@ pub fn build(b: *std.Build) !void { b.getInstallStep().dependOn(&run_unit_tests.step); } - -pub const cpus = struct { - pub const avr5 = MicroZig.Cpu{ - .name = "AVR5", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/cpus/avr5.zig" }, - .target = std.Target.Query{ - .cpu_arch = .avr, - .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 }, - .os_tag = .freestanding, - .abi = .eabi, - }, - }; - - pub const cortex_m0 = MicroZig.Cpu{ - .name = "ARM Cortex-M0", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/cpus/cortex_m.zig" }, - .target = std.Target.Query{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, - .os_tag = .freestanding, - .abi = .eabi, - }, - }; - - pub const cortex_m0plus = MicroZig.Cpu{ - .name = "ARM Cortex-M0+", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/cpus/cortex_m.zig" }, - .target = std.Target.Query{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, - .os_tag = .freestanding, - .abi = .eabi, - }, - }; - - pub const cortex_m3 = MicroZig.Cpu{ - .name = "ARM Cortex-M3", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/cpus/cortex_m.zig" }, - .target = std.Target.Query{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, - .os_tag = .freestanding, - .abi = .eabi, - }, - }; - - pub const cortex_m33 = MicroZig.Cpu{ - .name = "ARM Cortex-M33", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/cpus/cortex_m.zig" }, - .target = std.Target.Query{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, - .os_tag = .freestanding, - .abi = .eabi, - }, - }; - - pub const cortex_m33f = MicroZig.Cpu{ - .name = "ARM Cortex-M33F", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/cpus/cortex_m.zig" }, - .target = std.Target.Query{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, - .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), - .os_tag = .freestanding, - .abi = .eabihf, - }, - }; - - pub const cortex_m4 = MicroZig.Cpu{ - .name = "ARM Cortex-M4", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/cpus/cortex_m.zig" }, - .target = std.Target.Query{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, - .os_tag = .freestanding, - .abi = .eabi, - }, - }; - - pub const cortex_m4f = MicroZig.Cpu{ - .name = "ARM Cortex-M4F", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/cpus/cortex_m.zig" }, - .target = std.zig.CrossTarget{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, - .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), - .os_tag = .freestanding, - .abi = .eabihf, - }, - }; - - pub const cortex_m7 = MicroZig.Cpu{ - .name = "ARM Cortex-M7", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/cpus/cortex_m.zig" }, - .target = std.zig.CrossTarget{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, - .os_tag = .freestanding, - .abi = .eabi, - }, - }; - pub const cortex_m7f = MicroZig.Cpu{ - .name = "ARM Cortex-M7F", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/cpus/cortex_m.zig" }, - .target = std.zig.CrossTarget{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, - .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), - .os_tag = .freestanding, - .abi = .eabihf, - }, - }; - pub const riscv32_imac = MicroZig.Cpu{ - .name = "RISC-V 32-bit", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/cpus/riscv32.zig" }, - .target = std.Target.Query{ - .cpu_arch = .riscv32, - .cpu_model = .{ .explicit = &std.Target.riscv.cpu.sifive_e21 }, - .os_tag = .freestanding, - .abi = .none, - }, - }; -}; diff --git a/core/build.zig.zon b/core/build.zig.zon index 8c594798..a9cff3fa 100644 --- a/core/build.zig.zon +++ b/core/build.zig.zon @@ -1,9 +1,7 @@ .{ .name = "core", .version = "0.0.1", - .dependencies = .{ - .@"microzig/build/definitions" = .{ .path = "../build/definitions" }, - }, + .dependencies = .{}, .paths = .{ "LICENSE", "thoughts.md", diff --git a/examples/build.zig b/examples/build.zig new file mode 100644 index 00000000..09050449 --- /dev/null +++ b/examples/build.zig @@ -0,0 +1,27 @@ +const std = @import("std"); + +const example_dep_names: []const []const u8 = &.{ + //"espressif/esp", + "gigadevice/gd32", + "microchip/atsam", + "microchip/avr", + "nordic/nrf5x", + "nxp/lpc", + "raspberrypi/rp2xxx", + "stmicro/stm32", +}; + +pub fn build(b: *std.Build) void { + const optimize = b.standardOptimizeOption(.{}); + + // Build all examples + for (example_dep_names) |example_dep_name| { + const example_dep = b.dependency(example_dep_name, .{ + .optimize = optimize, + }); + + const example_dep_install_step = example_dep.builder.getInstallStep(); + example_dep.builder.install_path = b.install_path; // HACK: install in the current directory + b.getInstallStep().dependOn(example_dep_install_step); + } +} diff --git a/examples/build.zig.zon b/examples/build.zig.zon new file mode 100644 index 00000000..b7251f1d --- /dev/null +++ b/examples/build.zig.zon @@ -0,0 +1,19 @@ +.{ + .name = "examples", + .version = "0.0.0", + .dependencies = .{ + // examples + // .@"espressif/esp" = .{ .path = "espressif/esp" }, + .@"gigadevice/gd32" = .{ .path = "gigadevice/gd32" }, + .@"microchip/atsam" = .{ .path = "microchip/atsam" }, + .@"microchip/avr" = .{ .path = "microchip/avr" }, + .@"nordic/nrf5x" = .{ .path = "nordic/nrf5x" }, + .@"nxp/lpc" = .{ .path = "nxp/lpc" }, + .@"raspberrypi/rp2xxx" = .{ .path = "raspberrypi/rp2xxx" }, + .@"stmicro/stm32" = .{ .path = "stmicro/stm32" }, + }, + .paths = .{ + "build.zig", + "build.zig.zon", + }, +} diff --git a/examples/gigadevice/gd32/build.zig b/examples/gigadevice/gd32/build.zig index 9620196f..f1b359cf 100644 --- a/examples/gigadevice/gd32/build.zig +++ b/examples/gigadevice/gd32/build.zig @@ -1,25 +1,30 @@ const std = @import("std"); -const MicroZig = @import("microzig/build"); -const gd32 = @import("microzig/port/gigadevice/gd32"); - -const available_examples = [_]Example{ - .{ .target = gd32.chips.gd32vf103xb, .name = "gd32vf103xb", .file = "src/empty.zig" }, - .{ .target = gd32.chips.gd32vf103x8, .name = "gd32vf103x8", .file = "src/empty.zig" }, - .{ .target = gd32.boards.sipeed.longan_nano, .name = "sipeed-longan_nano", .file = "src/empty.zig" }, - .{ .target = gd32.boards.sipeed.longan_nano, .name = "sipeed-longan_nano_blinky", .file = "src/blinky.zig" }, -}; +const microzig = @import("microzig"); + +const MicroBuild = microzig.MicroBuild(.{ + .gd32 = true, +}); pub fn build(b: *std.Build) void { - const microzig = MicroZig.init(b, .{}); const optimize = b.standardOptimizeOption(.{}); + const mz_dep = b.dependency("microzig", .{}); + const mb = MicroBuild.init(b, mz_dep); + + const available_examples = [_]Example{ + .{ .target = mb.ports.gd32.chips.gd32vf103xb, .name = "gd32vf103xb", .file = "src/empty.zig" }, + .{ .target = mb.ports.gd32.chips.gd32vf103x8, .name = "gd32vf103x8", .file = "src/empty.zig" }, + .{ .target = mb.ports.gd32.boards.sipeed.longan_nano, .name = "sipeed-longan_nano", .file = "src/empty.zig" }, + .{ .target = mb.ports.gd32.boards.sipeed.longan_nano, .name = "sipeed-longan_nano_blinky", .file = "src/blinky.zig" }, + }; + for (available_examples) |example| { // `add_firmware` basically works like addExecutable, but takes a // `microzig.Target` for target instead of a `std.zig.CrossTarget`. // // The target will convey all necessary information on the chip, // cpu and potentially the board as well. - const firmware = microzig.add_firmware(b, .{ + const fw = mb.add_firmware(.{ .name = example.name, .target = example.target, .optimize = optimize, @@ -30,15 +35,15 @@ pub fn build(b: *std.Build) void { // and allows installing the firmware as a typical firmware file. // // This will also install into `$prefix/firmware` instead of `$prefix/bin`. - microzig.install_firmware(b, firmware, .{ .format = .bin }); + mb.install_firmware(fw, .{ .format = .bin }); // For debugging, we also always install the firmware as an ELF file - microzig.install_firmware(b, firmware, .{}); + mb.install_firmware(fw, .{}); } } const Example = struct { - target: MicroZig.Target, + target: *const microzig.Target, name: []const u8, file: []const u8, }; diff --git a/examples/gigadevice/gd32/build.zig.zon b/examples/gigadevice/gd32/build.zig.zon index 7cbc7348..c6e27529 100644 --- a/examples/gigadevice/gd32/build.zig.zon +++ b/examples/gigadevice/gd32/build.zig.zon @@ -2,8 +2,7 @@ .name = "examples/gigadevice/gd32", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, - .@"microzig/port/gigadevice/gd32" = .{ .path = "../../../port/gigadevice/gd32" }, + .microzig = .{ .path = "../../.." }, }, .paths = .{ diff --git a/examples/microchip/atsam/build.zig b/examples/microchip/atsam/build.zig index 522e68ef..836af1f6 100644 --- a/examples/microchip/atsam/build.zig +++ b/examples/microchip/atsam/build.zig @@ -1,22 +1,27 @@ const std = @import("std"); -const MicroZig = @import("microzig/build"); -const atsam = @import("microzig/port/microchip/atsam"); +const microzig = @import("microzig"); -const available_examples = [_]Example{ - .{ .target = atsam.chips.atsamd51j19, .name = "atsamd51j19-blinky", .file = "src/blinky.zig" }, -}; +const MicroBuild = microzig.MicroBuild(.{ + .atsam = true, +}); pub fn build(b: *std.Build) void { - const microzig = MicroZig.init(b, .{}); const optimize = b.standardOptimizeOption(.{}); + const mz_dep = b.dependency("microzig", .{}); + const mb = MicroBuild.init(b, mz_dep); + + const available_examples = [_]Example{ + .{ .target = mb.ports.atsam.chips.atsamd51j19, .name = "atsamd51j19-blinky", .file = "src/blinky.zig" }, + }; + for (available_examples) |example| { // `add_firmware` basically works like addExecutable, but takes a // `microzig.Target` for target instead of a `std.zig.CrossTarget`. // // The target will convey all necessary information on the chip, // cpu and potentially the board as well. - const firmware = microzig.add_firmware(b, .{ + const fw = mb.add_firmware(.{ .name = example.name, .target = example.target, .optimize = optimize, @@ -27,15 +32,15 @@ pub fn build(b: *std.Build) void { // and allows installing the firmware as a typical firmware file. // // This will also install into `$prefix/firmware` instead of `$prefix/bin`. - microzig.install_firmware(b, firmware, .{}); + mb.install_firmware(fw, .{}); // For debugging, we also always install the firmware as an ELF file - microzig.install_firmware(b, firmware, .{ .format = .elf }); + mb.install_firmware(fw, .{ .format = .elf }); } } const Example = struct { - target: MicroZig.Target, + target: *const microzig.Target, name: []const u8, file: []const u8, }; diff --git a/examples/microchip/atsam/build.zig.zon b/examples/microchip/atsam/build.zig.zon index 903e029a..8561c1f9 100644 --- a/examples/microchip/atsam/build.zig.zon +++ b/examples/microchip/atsam/build.zig.zon @@ -2,8 +2,7 @@ .name = "examples/microchip/atsam", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, - .@"microzig/port/microchip/atsam" = .{ .path = "../../../port/microchip/atsam" }, + .microzig = .{ .path = "../../.." }, }, .paths = .{ diff --git a/examples/microchip/avr/build.zig b/examples/microchip/avr/build.zig index efcfafb0..10688d61 100644 --- a/examples/microchip/avr/build.zig +++ b/examples/microchip/avr/build.zig @@ -1,23 +1,28 @@ const std = @import("std"); -const MicroZig = @import("microzig/build"); -const avr = @import("microzig/port/microchip/avr"); +const microzig = @import("microzig"); -const available_examples = [_]Example{ - .{ .target = avr.boards.arduino.nano, .name = "arduino-nano_blinky", .file = "src/blinky.zig" }, - .{ .target = avr.boards.arduino.uno_rev3, .name = "arduino-nano_blinky", .file = "src/blinky.zig" }, -}; +const MicroBuild = microzig.MicroBuild(.{ + .avr = true, +}); pub fn build(b: *std.Build) void { - const microzig = MicroZig.init(b, .{}); const optimize = b.standardOptimizeOption(.{}); + const mz_dep = b.dependency("microzig", .{}); + const mb = MicroBuild.init(b, mz_dep); + + const available_examples = [_]Example{ + .{ .target = mb.ports.avr.boards.arduino.nano, .name = "arduino-nano_blinky", .file = "src/blinky.zig" }, + .{ .target = mb.ports.avr.boards.arduino.uno_rev3, .name = "arduino-nano_blinky", .file = "src/blinky.zig" }, + }; + for (available_examples) |example| { // `add_firmware` basically works like addExecutable, but takes a // `microzig.Target` for target instead of a `std.zig.CrossTarget`. // // The target will convey all necessary information on the chip, // cpu and potentially the board as well. - const firmware = microzig.add_firmware(b, .{ + const fw = mb.add_firmware(.{ .name = example.name, .target = example.target, .optimize = optimize, @@ -28,15 +33,15 @@ pub fn build(b: *std.Build) void { // and allows installing the firmware as a typical firmware file. // // This will also install into `$prefix/firmware` instead of `$prefix/bin`. - microzig.install_firmware(b, firmware, .{}); + mb.install_firmware(fw, .{}); // For debugging, we also always install the firmware as an ELF file - microzig.install_firmware(b, firmware, .{ .format = .elf }); + mb.install_firmware(fw, .{ .format = .elf }); } } const Example = struct { - target: MicroZig.Target, + target: *const microzig.Target, name: []const u8, file: []const u8, }; diff --git a/examples/microchip/avr/build.zig.zon b/examples/microchip/avr/build.zig.zon index 61412d39..cdcc79d2 100644 --- a/examples/microchip/avr/build.zig.zon +++ b/examples/microchip/avr/build.zig.zon @@ -2,8 +2,7 @@ .name = "examples/microchip/avr", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, - .@"microzig/port/microchip/avr" = .{ .path = "../../../port/microchip/avr" }, + .microzig = .{ .path = "../../.." }, }, .paths = .{ diff --git a/examples/nordic/nrf5x/build.zig b/examples/nordic/nrf5x/build.zig index 9e7f4fab..afb557c8 100644 --- a/examples/nordic/nrf5x/build.zig +++ b/examples/nordic/nrf5x/build.zig @@ -1,23 +1,27 @@ const std = @import("std"); -const Build = std.Build; -const MicroZig = @import("microzig/build"); -const nrf5x = @import("microzig/port/nordic/nrf5x"); +const microzig = @import("microzig"); -const available_examples = [_]Example{ - .{ .target = nrf5x.boards.nordic_nRF52840_Dongle, .name = "nrf52480-dongle_blinky", .file = "src/blinky.zig" }, -}; +const MicroBuild = microzig.MicroBuild(.{ + .nrf5x = true, +}); -pub fn build(b: *Build) void { - const microzig = MicroZig.init(b, .{}); +pub fn build(b: *std.Build) void { const optimize = b.standardOptimizeOption(.{}); + const mz_dep = b.dependency("microzig", .{}); + const mb = MicroBuild.init(b, mz_dep); + + const available_examples = [_]Example{ + .{ .target = mb.ports.nrf5x.boards.nordic.nrf52840_dongle, .name = "nrf52480-dongle_blinky", .file = "src/blinky.zig" }, + }; + for (available_examples) |example| { // `add_firmware` basically works like addExecutable, but takes a // `microzig.Target` for target instead of a `std.zig.CrossTarget`. // // The target will convey all necessary information on the chip, // cpu and potentially the board as well. - const firmware = microzig.add_firmware(b, .{ + const fw = mb.add_firmware(.{ .name = example.name, .target = example.target, .optimize = optimize, @@ -28,15 +32,15 @@ pub fn build(b: *Build) void { // and allows installing the firmware as a typical firmware file. // // This will also install into `$prefix/firmware` instead of `$prefix/bin`. - microzig.install_firmware(b, firmware, .{}); + mb.install_firmware(fw, .{}); // For debugging, we also always install the firmware as an ELF file - microzig.install_firmware(b, firmware, .{ .format = .elf }); + mb.install_firmware(fw, .{ .format = .elf }); } } const Example = struct { - target: MicroZig.Target, + target: *const microzig.Target, name: []const u8, file: []const u8, }; diff --git a/examples/nordic/nrf5x/build.zig.zon b/examples/nordic/nrf5x/build.zig.zon index 57e7ac71..67f95f26 100644 --- a/examples/nordic/nrf5x/build.zig.zon +++ b/examples/nordic/nrf5x/build.zig.zon @@ -2,8 +2,7 @@ .name = "examples/nordic/nrf5x", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, - .@"microzig/port/nordic/nrf5x" = .{ .path = "../../../port/nordic/nrf5x" }, + .microzig = .{ .path = "../../.." }, }, .paths = .{ diff --git a/examples/nxp/lpc/build.zig b/examples/nxp/lpc/build.zig index ae38f1ed..963b87e6 100644 --- a/examples/nxp/lpc/build.zig +++ b/examples/nxp/lpc/build.zig @@ -1,22 +1,27 @@ const std = @import("std"); -const MicroZig = @import("microzig/build"); -const lpc = @import("microzig/port/nxp/lpc"); +const microzig = @import("microzig"); -const available_examples = [_]ExampleDesc{ - .{ .target = lpc.boards.mbed.lpc1768, .name = "mbed-lpc1768_blinky", .file = "src/blinky.zig" }, -}; +const MicroBuild = microzig.MicroBuild(.{ + .lpc = true, +}); pub fn build(b: *std.Build) void { - const microzig = MicroZig.init(b, .{}); const optimize = b.standardOptimizeOption(.{}); + const mz_dep = b.dependency("microzig", .{}); + const mb = MicroBuild.init(b, mz_dep); + + const available_examples = [_]Example{ + .{ .target = mb.ports.lpc.boards.mbed.lpc1768, .name = "mbed-lpc1768_blinky", .file = "src/blinky.zig" }, + }; + for (available_examples) |example| { // `add_firmware` basically works like addExecutable, but takes a // `microzig.Target` for target instead of a `std.zig.CrossTarget`. // // The target will convey all necessary information on the chip, // cpu and potentially the board as well. - const firmware = microzig.add_firmware(b, .{ + const fw = mb.add_firmware(.{ .name = example.name, .target = example.target, .optimize = optimize, @@ -27,15 +32,15 @@ pub fn build(b: *std.Build) void { // and allows installing the firmware as a typical firmware file. // // This will also install into `$prefix/firmware` instead of `$prefix/bin`. - microzig.install_firmware(b, firmware, .{}); + mb.install_firmware(fw, .{}); // For debugging, we also always install the firmware as an ELF file - microzig.install_firmware(b, firmware, .{ .format = .elf }); + mb.install_firmware(fw, .{ .format = .elf }); } } -const ExampleDesc = struct { - target: MicroZig.Target, +const Example = struct { + target: *const microzig.Target, name: []const u8, file: []const u8, }; diff --git a/examples/nxp/lpc/build.zig.zon b/examples/nxp/lpc/build.zig.zon index 6e0ea0cb..1e0dc557 100644 --- a/examples/nxp/lpc/build.zig.zon +++ b/examples/nxp/lpc/build.zig.zon @@ -2,10 +2,8 @@ .name = "examples/nxp/lpc", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, - .@"microzig/port/nxp/lpc" = .{ .path = "../../../port/nxp/lpc" }, + .microzig = .{ .path = "../../.." }, }, - .paths = .{ "LICENSE", "README.md", diff --git a/examples/raspberrypi/rp2xxx/build.zig b/examples/raspberrypi/rp2xxx/build.zig index 82591b9e..ccb7d52c 100644 --- a/examples/raspberrypi/rp2xxx/build.zig +++ b/examples/raspberrypi/rp2xxx/build.zig @@ -1,79 +1,75 @@ const std = @import("std"); -const MicroZig = @import("microzig/build"); -const rp2xxx = @import("microzig/port/raspberrypi/rp2xxx"); +const microzig = @import("microzig"); -const rp2040_only_examples = [_]Example{ - // RaspberryPi Boards: - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_adc", .file = "src/rp2040_only/adc.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_flash-program", .file = "src/rp2040_only/flash_program.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_flash-id", .file = "src/rp2040_only/flash_id.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_i2c-bus-scan", .file = "src/rp2040_only/i2c_bus_scan.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_pwm", .file = "src/rp2040_only/pwm.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_random", .file = "src/rp2040_only/random.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_spi-host", .file = "src/rp2040_only/spi_host.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_squarewave", .file = "src/rp2040_only/squarewave.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_uart_echo", .file = "src/rp2040_only/uart_echo.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_uart_log", .file = "src/rp2040_only/uart_log.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_usb-hid", .file = "src/rp2040_only/usb_hid.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_usb-cdc", .file = "src/rp2040_only/usb_cdc.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_ws2812", .file = "src/rp2040_only/ws2812.zig" }, - .{ .target = rp2xxx.boards.raspberrypi.pico, .name = "pico_multicore", .file = "src/rp2040_only/blinky_core1.zig" }, +const MicroBuild = microzig.MicroBuild(.{ + .rp2xxx = true, +}); - // WaveShare Boards: - .{ .target = rp2xxx.boards.waveshare.rp2040_matrix, .name = "rp2040-matrix_tiles", .file = "src/rp2040_only/tiles.zig" }, - // .{ .target = "board:waveshare/rp2040_eth", .name = "rp2040-eth" }, - // .{ .target = "board:waveshare/rp2040_plus_4m", .name = "rp2040-plus-4m" }, - // .{ .target = "board:waveshare/rp2040_plus_16m", .name = "rp2040-plus-16m" }, -}; +pub fn build(b: *std.Build) void { + const optimize = b.standardOptimizeOption(.{}); -const rp2350_only_examples = [_]Example{ - // TODO: No RP2350 feature specific examples to show off yet -}; + const mz_dep = b.dependency("microzig", .{}); + const mb = MicroBuild.init(b, mz_dep); -const chip_agnostic_examples = [_]ChipAgnosticExample{ - .{ .name = "blinky", .file = "src/blinky.zig" }, - .{ .name = "gpio-clock-output", .file = "src/gpio_clock_output.zig" }, - .{ .name = "changing-system-clocks", .file = "src/changing_system_clocks.zig" }, - .{ .name = "custom-clock-config", .file = "src/custom_clock_config.zig" }, -}; + const rp2040_only_examples: []const Example = &.{ + // RaspberryPi Boards: + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_adc", .file = "src/rp2040_only/adc.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_flash-program", .file = "src/rp2040_only/flash_program.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_flash-id", .file = "src/rp2040_only/flash_id.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_i2c-bus-scan", .file = "src/rp2040_only/i2c_bus_scan.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_pwm", .file = "src/rp2040_only/pwm.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_random", .file = "src/rp2040_only/random.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_spi-host", .file = "src/rp2040_only/spi_host.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_squarewave", .file = "src/rp2040_only/squarewave.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_uart-echo", .file = "src/rp2040_only/uart_echo.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_uart-log", .file = "src/rp2040_only/uart_log.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_usb-hid", .file = "src/rp2040_only/usb_hid.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_usb-cdc", .file = "src/rp2040_only/usb_cdc.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_ws2812", .file = "src/rp2040_only/ws2812.zig" }, + .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_multicore", .file = "src/rp2040_only/blinky_core1.zig" }, -const available_examples = val: { - var examples: [rp2040_only_examples.len + rp2350_only_examples.len + chip_agnostic_examples.len * 2]Example = rp2040_only_examples ++ - rp2350_only_examples ++ - [_]Example{undefined} ** (chip_agnostic_examples.len * 2); + // WaveShare Boards: + .{ .target = mb.ports.rp2xxx.boards.waveshare.rp2040_matrix, .name = "rp2040-matrix_tiles", .file = "src/rp2040_only/tiles.zig" }, + // .{ .target = "board:waveshare/rp2040_eth", .name = "rp2040-eth" }, + // .{ .target = "board:waveshare/rp2040_plus_4m", .name = "rp2040-plus-4m" }, + // .{ .target = "board:waveshare/rp2040_plus_16m", .name = "rp2040-plus-16m" }, + }; - var i: usize = rp2040_only_examples.len + rp2350_only_examples.len; + const rp2350_only_examples: []const Example = &.{ + // TODO: No RP2350 feature specific examples to show off yet + }; - for (chip_agnostic_examples) |ex| { - examples[i] = .{ - .target = rp2xxx.boards.raspberrypi.pico, - .name = "pico_" ++ ex.name, - .file = ex.file, - }; - i += 1; - examples[i] = .{ - .target = rp2xxx.boards.raspberrypi.pico2, - .name = "pico2_" ++ ex.name, - .file = ex.file, - }; - i += 1; - } + const chip_agnostic_examples: []const ChipAgnosticExample = &.{ + .{ .name = "blinky", .file = "src/blinky.zig" }, + .{ .name = "gpio-clock-output", .file = "src/gpio_clock_output.zig" }, + .{ .name = "changing-system-clocks", .file = "src/changing_system_clocks.zig" }, + .{ .name = "custom-clock-config", .file = "src/custom_clock_config.zig" }, + }; - break :val examples; -}; + var available_examples = std.ArrayList(Example).init(b.allocator); + available_examples.appendSlice(rp2040_only_examples) catch @panic("out of memory"); + available_examples.appendSlice(rp2350_only_examples) catch @panic("out of memory"); + for (chip_agnostic_examples) |example| { + available_examples.append(.{ + .target = mb.ports.rp2xxx.boards.raspberrypi.pico, + .name = b.fmt("pico_{s}", .{example.name}), + .file = example.file, + }) catch @panic("out of memory"); -pub fn build(b: *std.Build) void { - const mz = MicroZig.init(b, .{}); - const optimize = b.standardOptimizeOption(.{}); - - for (available_examples) |example| { + available_examples.append(.{ + .target = mb.ports.rp2xxx.boards.raspberrypi.pico2_arm, + .name = b.fmt("pico2_{s}", .{example.name}), + .file = example.file, + }) catch @panic("out of memory"); + } + for (available_examples.items) |example| { // `add_firmware` basically works like addExecutable, but takes a // `microzig.Target` for target instead of a `std.zig.CrossTarget`. // // The target will convey all necessary information on the chip, // cpu and potentially the board as well. - const firmware = mz.add_firmware(b, .{ + const firmware = mb.add_firmware(.{ .name = example.name, .target = example.target, .optimize = optimize, @@ -84,15 +80,15 @@ pub fn build(b: *std.Build) void { // and allows installing the firmware as a typical firmware file. // // This will also install into `$prefix/firmware` instead of `$prefix/bin`. - mz.install_firmware(b, firmware, .{}); + mb.install_firmware(firmware, .{}); // For debugging, we also always install the firmware as an ELF file - mz.install_firmware(b, firmware, .{ .format = .elf }); + mb.install_firmware(firmware, .{ .format = .elf }); } } const Example = struct { - target: MicroZig.Target, + target: *const microzig.Target, name: []const u8, file: []const u8, }; diff --git a/examples/raspberrypi/rp2xxx/build.zig.zon b/examples/raspberrypi/rp2xxx/build.zig.zon index 3028b107..3a5dc453 100644 --- a/examples/raspberrypi/rp2xxx/build.zig.zon +++ b/examples/raspberrypi/rp2xxx/build.zig.zon @@ -2,10 +2,8 @@ .name = "examples/raspberrypi/rp2xxx", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, - .@"microzig/port/raspberrypi/rp2xxx" = .{ .path = "../../../port/raspberrypi/rp2xxx" }, + .microzig = .{ .path = "../../.." }, }, - .paths = .{ "LICENSE", "README.md", diff --git a/examples/stmicro/stm32/build.zig b/examples/stmicro/stm32/build.zig index 8d04df85..48a80a93 100644 --- a/examples/stmicro/stm32/build.zig +++ b/examples/stmicro/stm32/build.zig @@ -1,30 +1,35 @@ const std = @import("std"); -const MicroZig = @import("microzig/build"); -const stm32 = @import("microzig/port/stmicro/stm32"); - -const available_examples = [_]Example{ - .{ .target = stm32.chips.STM32F103C8, .name = "STM32F103C8", .file = "src/blinky.zig" }, - // TODO: stm32.pins.GlobalConfiguration is not available on those targets - // .{ .target = stm32.chips.stm32f303vc, .name = "stm32f303vc", .file = "src/blinky.zig" }, - // .{ .target = stm32.chips.stm32f407vg, .name = "stm32f407vg", .file = "src/blinky.zig" }, - // .{ .target = stm32.chips.stm32f429zit6u, .name = "stm32f429zit6u", .file = "src/blinky.zig" }, - // .{ .target = stm32.boards.stm32f3discovery, .name = "stm32f3discovery", .file = "src/blinky.zig" }, - // .{ .target = stm32.boards.stm32f4discovery, .name = "stm32f4discovery", .file = "src/blinky.zig" }, - // .{ .target = stm32.boards.stm3240geval, .name = "stm3240geval", .file = "src/blinky.zig" }, - // .{ .target = stm32.boards.stm32f429idiscovery, .name = "stm32f429idiscovery", .file = "src/blinky.zig" }, -}; +const microzig = @import("microzig"); + +const MicroBuild = microzig.MicroBuild(.{ + .stm32 = true, +}); pub fn build(b: *std.Build) void { - const microzig = MicroZig.init(b, .{}); const optimize = b.standardOptimizeOption(.{}); + const mz_dep = b.dependency("microzig", .{}); + const mb = MicroBuild.init(b, mz_dep); + + const available_examples = [_]Example{ + .{ .target = mb.ports.stm32.chips.STM32F103C8, .name = "STM32F103C8", .file = "src/blinky.zig" }, + // TODO: stm32.pins.GlobalConfiguration is not available on those targets + // .{ .target = stm32.chips.stm32f303vc, .name = "stm32f303vc", .file = "src/blinky.zig" }, + // .{ .target = stm32.chips.stm32f407vg, .name = "stm32f407vg", .file = "src/blinky.zig" }, + // .{ .target = stm32.chips.stm32f429zit6u, .name = "stm32f429zit6u", .file = "src/blinky.zig" }, + // .{ .target = stm32.boards.stm32f3discovery, .name = "stm32f3discovery", .file = "src/blinky.zig" }, + // .{ .target = stm32.boards.stm32f4discovery, .name = "stm32f4discovery", .file = "src/blinky.zig" }, + // .{ .target = stm32.boards.stm3240geval, .name = "stm3240geval", .file = "src/blinky.zig" }, + // .{ .target = stm32.boards.stm32f429idiscovery, .name = "stm32f429idiscovery", .file = "src/blinky.zig" }, + }; + for (available_examples) |example| { // `add_firmware` basically works like addExecutable, but takes a // `microzig.Target` for target instead of a `std.zig.CrossTarget`. // // The target will convey all necessary information on the chip, // cpu and potentially the board as well. - const firmware = microzig.add_firmware(b, .{ + const fw = mb.add_firmware(.{ .name = example.name, .target = example.target, .optimize = optimize, @@ -35,15 +40,15 @@ pub fn build(b: *std.Build) void { // and allows installing the firmware as a typical firmware file. // // This will also install into `$prefix/firmware` instead of `$prefix/bin`. - microzig.install_firmware(b, firmware, .{}); + mb.install_firmware(fw, .{}); // For debugging, we also always install the firmware as an ELF file - microzig.install_firmware(b, firmware, .{ .format = .elf }); + mb.install_firmware(fw, .{ .format = .elf }); } } const Example = struct { - target: MicroZig.Target, + target: *const microzig.Target, name: []const u8, file: []const u8, }; diff --git a/examples/stmicro/stm32/build.zig.zon b/examples/stmicro/stm32/build.zig.zon index d5ff918b..6be82150 100644 --- a/examples/stmicro/stm32/build.zig.zon +++ b/examples/stmicro/stm32/build.zig.zon @@ -2,8 +2,7 @@ .name = "examples/stmicro/stm32", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, - .@"microzig/port/stmicro/stm32" = .{ .path = "../../../port/stmicro/stm32" }, + .microzig = .{ .path = "../../.." }, }, .paths = .{ diff --git a/port/gigadevice/gd32/build.zig b/port/gigadevice/gd32/build.zig index ec39c870..c448af65 100644 --- a/port/gigadevice/gd32/build.zig +++ b/port/gigadevice/gd32/build.zig @@ -1,66 +1,89 @@ const std = @import("std"); -const Build = std.Build; -const MicroZig = @import("microzig/build"); +const microzig = @import("microzig/build-internals"); -fn path(comptime suffix: []const u8) std.Build.LazyPath { - return .{ - .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix), - }; -} +const Self = @This(); -const hal = .{ - .root_source_file = path("/src/hals/GD32VF103/hal.zig"), -}; +chips: struct { + gd32vf103xb: *const microzig.Target, + gd32vf103x8: *const microzig.Target, +}, -pub const chips = struct { - pub const gd32vf103xb = MicroZig.Target{ - .preferred_format = .elf, +boards: struct { + sipeed: struct { + longan_nano: *const microzig.Target, + }, +}, + +pub fn init(dep: *std.Build.Dependency) Self { + const b = dep.builder; + + const hal_f103: microzig.HardwareAbstractionLayer = .{ + .root_source_file = b.path("src/hals/GD32VF103/hal.zig"), + }; + + const chip_gd32vf103xb: microzig.Target = .{ + .dep = dep, + .preferred_binary_format = .elf, .chip = .{ .name = "GD32VF103", - .cpu = MicroZig.cpus.riscv32_imac, + .cpu = .{ + .cpu_arch = .riscv32, + .cpu_model = .{ .explicit = &std.Target.riscv.cpu.sifive_e21 }, + .os_tag = .freestanding, + .abi = .none, + }, + .register_definition = .{ + .json = b.path("src/chips/GD32VF103.json"), + }, .memory_regions = &.{ .{ .offset = 0x08000000, .length = 128 * 1024, .kind = .flash }, .{ .offset = 0x20000000, .length = 32 * 1024, .kind = .ram }, }, - .register_definition = .{ - .json = path("/src/chips/GD32VF103.json"), - }, }, - .hal = hal, + .hal = hal_f103, }; - pub const gd32vf103x8 = MicroZig.Target{ - .preferred_format = .elf, + const chip_gd32vf103x8: microzig.Target = .{ + .dep = dep, + .preferred_binary_format = .elf, .chip = .{ .name = "GD32VF103", - .cpu = MicroZig.cpus.riscv32_imac, + .cpu = .{ + .cpu_arch = .riscv32, + .cpu_model = .{ .explicit = &std.Target.riscv.cpu.sifive_e21 }, + .os_tag = .freestanding, + .abi = .none, + }, + .register_definition = .{ + .json = b.path("src/chips/GD32VF103.json"), + }, .memory_regions = &.{ .{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash }, .{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram }, }, - .register_definition = .{ - .json = path("/src/chips/GD32VF103.json"), - }, }, - .hal = hal, + .hal = hal_f103, }; -}; -pub const boards = struct { - pub const sipeed = struct { - pub const longan_nano = MicroZig.Target{ - .preferred_format = .elf, - .chip = chips.gd32vf103xb.chip, - .hal = hal, - .board = .{ - .name = "Longan Nano", - .url = "https://longan.sipeed.com/en/", - .root_source_file = path("/src/boards/longan_nano.zig"), + return .{ + .chips = .{ + .gd32vf103xb = chip_gd32vf103xb.derive(.{}), + .gd32vf103x8 = chip_gd32vf103x8.derive(.{}), + }, + .boards = .{ + .sipeed = .{ + .longan_nano = chip_gd32vf103xb.derive(.{ + .board = .{ + .name = "Longan Nano", + .url = "https://longan.sipeed.com/en/", + .root_source_file = b.path("src/boards/longan_nano.zig"), + }, + }), }, - }; + }, }; -}; +} -pub fn build(b: *Build) void { +pub fn build(b: *std.Build) void { _ = b.step("test", "Run platform agnostic unit tests"); } diff --git a/port/gigadevice/gd32/build.zig.zon b/port/gigadevice/gd32/build.zig.zon index 22aad072..edf31d71 100644 --- a/port/gigadevice/gd32/build.zig.zon +++ b/port/gigadevice/gd32/build.zig.zon @@ -2,7 +2,7 @@ .name = "port/gigadevice/gd32", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, + .@"microzig/build-internals" = .{ .path = "../../../build-internals" }, }, .paths = .{ "LICENSE", diff --git a/port/microchip/atsam/build.zig b/port/microchip/atsam/build.zig index 8c739360..c57120b2 100644 --- a/port/microchip/atsam/build.zig +++ b/port/microchip/atsam/build.zig @@ -1,25 +1,32 @@ const std = @import("std"); -const MicroZig = @import("microzig/build"); +const microzig = @import("microzig/build-internals"); -pub fn build(b: *std.Build) void { - _ = b.step("test", "Run platform agnostic unit tests"); -} +const Self = @This(); -fn root() []const u8 { - return comptime (std.fs.path.dirname(@src().file) orelse "."); -} +chips: struct { + atsamd51j19: *const microzig.Target, +}, -const build_root = root(); +boards: struct {}, -pub const chips = struct { - pub const atsamd51j19 = MicroZig.Target{ - .preferred_format = .elf, +pub fn init(dep: *std.Build.Dependency) Self { + const b = dep.builder; + + const chip_atsamd51j19: microzig.Target = .{ + .dep = dep, + .preferred_binary_format = .elf, .chip = .{ .name = "ATSAMD51J19A", .url = "https://www.microchip.com/en-us/product/ATSAMD51J19A", - .cpu = MicroZig.cpus.cortex_m4f, + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .os_tag = .freestanding, + .abi = .eabihf, + }, .register_definition = .{ - .atdf = .{ .cwd_relative = build_root ++ "/src/chips/ATSAMD51J19A.atdf" }, + .atdf = b.path("src/chips/ATSAMD51J19A.atdf"), }, .memory_regions = &.{ .{ .kind = .flash, .offset = 0x00000000, .length = 512 * 1024 }, // Embedded Flash @@ -29,8 +36,15 @@ pub const chips = struct { }, }, }; -}; -pub const boards = struct { - // empty right now -}; + return .{ + .chips = .{ + .atsamd51j19 = chip_atsamd51j19.derive(.{}), + }, + .boards = .{}, + }; +} + +pub fn build(b: *std.Build) void { + _ = b.step("test", "Run platform agnostic unit tests"); +} diff --git a/port/microchip/atsam/build.zig.zon b/port/microchip/atsam/build.zig.zon index 12c1cd6c..1e7e0712 100644 --- a/port/microchip/atsam/build.zig.zon +++ b/port/microchip/atsam/build.zig.zon @@ -2,7 +2,7 @@ .name = "port/microchip/atsam", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, + .@"microzig/build-internals" = .{ .path = "../../../build-internals" }, }, .paths = .{ "LICENSE", diff --git a/port/microchip/avr/build.zig b/port/microchip/avr/build.zig index c87415cd..74846603 100644 --- a/port/microchip/avr/build.zig +++ b/port/microchip/avr/build.zig @@ -1,93 +1,111 @@ const std = @import("std"); -const Build = std.Build; -const MicroZig = @import("microzig/build"); +const microzig = @import("microzig/build-internals"); -fn path(comptime suffix: []const u8) Build.LazyPath { - return .{ - .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix), - }; -} +const Self = @This(); + +chips: struct { + atmega328p: *const microzig.Target, + atmega32u4: *const microzig.Target, +}, + +boards: struct { + arduino: struct { + nano: *const microzig.Target, + uno_rev3: *const microzig.Target, + }, + adafruit: struct { + itsybitsy_32u4: *const microzig.Target, + }, +}, -const hal = .{ - .root_source_file = path("/src/hals/ATmega328P.zig"), -}; -const hal32u4 = .{ - .root_source_file = path("/src/hals/ATmega32U4.zig"), -}; +pub fn init(dep: *std.Build.Dependency) Self { + const b = dep.builder; -pub const chips = struct { - pub const atmega328p = MicroZig.Target{ - .preferred_format = .hex, + const chip_atmega328p: microzig.Target = .{ + .dep = dep, + .preferred_binary_format = .hex, .chip = .{ .name = "ATmega328P", .url = "https://www.microchip.com/en-us/product/atmega328p", - .cpu = MicroZig.cpus.avr5, + .cpu = .{ + .cpu_arch = .avr, + .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 }, + .os_tag = .freestanding, + .abi = .eabi, + }, .register_definition = .{ - .json = path("/src/chips/ATmega328P.json"), + .json = b.path("src/chips/ATmega328P.json"), }, .memory_regions = &.{ .{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash }, .{ .offset = 0x800100, .length = 2048, .kind = .ram }, }, }, - .hal = hal, + .hal = .{ + .root_source_file = b.path("src/hals/ATmega328P.zig"), + }, }; - pub const atmega32u4 = MicroZig.Target{ - .preferred_format = .hex, + + const chip_atmega32u4: microzig.Target = .{ + .dep = dep, + .preferred_binary_format = .hex, .chip = .{ .name = "ATmega32U4", .url = "https://www.microchip.com/en-us/product/ATmega32U4", - .cpu = MicroZig.cpus.avr5, + .cpu = .{ + .cpu_arch = .avr, + .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 }, + .os_tag = .freestanding, + .abi = .eabi, + }, .register_definition = .{ - .json = path("/src/chips/ATmega32U4.json"), + .json = b.path("src/chips/ATmega32U4.json"), }, .memory_regions = &.{ .{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash }, .{ .offset = 0x800100, .length = 2560, .kind = .ram }, }, }, - .hal = hal32u4, + .hal = .{ + .root_source_file = b.path("src/hals/ATmega32U4.zig"), + }, }; -}; - -pub const boards = struct { - pub const arduino = struct { - pub const nano = MicroZig.Target{ - .preferred_format = .hex, - .chip = chips.atmega328p.chip, - .hal = hal, - .board = .{ - .name = "Arduino Nano", - .url = "https://docs.arduino.cc/hardware/nano", - .root_source_file = path("/src/boards/arduino_nano.zig"), - }, - }; - pub const uno_rev3 = MicroZig.Target{ - .preferred_format = .hex, - .chip = chips.atmega328p.chip, - .hal = hal, - .board = .{ - .name = "Arduino Uno", - .url = "https://docs.arduino.cc/hardware/uno-rev3", - .root_source_file = path("/src/boards/arduino_uno.zig"), + return .{ + .chips = .{ + .atmega328p = chip_atmega328p.derive(.{}), + .atmega32u4 = chip_atmega32u4.derive(.{}), + }, + .boards = .{ + .arduino = .{ + .nano = chip_atmega328p.derive(.{ + .board = .{ + .name = "Arduino Nano", + .url = "https://docs.arduino.cc/hardware/nano", + .root_source_file = b.path("src/boards/arduino_nano.zig"), + }, + }), + .uno_rev3 = chip_atmega328p.derive(.{ + .board = .{ + .name = "Arduino Nano", + .url = "https://docs.arduino.cc/hardware/nano", + .root_source_file = b.path("src/boards/arduino_uno.zig"), + }, + }), }, - }; - }; - pub const adafruit = struct { - pub const itsybitsy_32u4 = MicroZig.Target{ - .preferred_format = .hex, - .chip = chips.atmega32u4.chip, - .hal = hal32u4, - .board = .{ - .name = "Adafruit ItsyBitsy 32u4", - .url = "https://cdn-learn.adafruit.com/downloads/pdf/introducting-itsy-bitsy-32u4.pdf", - .root_source_file = path("/src/boards/itsybitsy_32u4.zig"), + .adafruit = .{ + .itsybitsy_32u4 = chip_atmega32u4.derive(.{ + .board = .{ + .name = "Arduino Nano", + .url = "https://docs.arduino.cc/hardware/nano", + .root_source_file = b.path("src/boards/itsybitsy_32u4.zig"), + }, + }), }, - }; + }, }; -}; +} -pub fn build(b: *Build) void { +pub fn build(b: *std.Build) void { _ = b.step("test", "Run platform agnostic unit tests"); } diff --git a/port/microchip/avr/build.zig.zon b/port/microchip/avr/build.zig.zon index 4093199d..ec313d31 100644 --- a/port/microchip/avr/build.zig.zon +++ b/port/microchip/avr/build.zig.zon @@ -2,7 +2,7 @@ .name = "port/microchip/avr", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, + .@"microzig/build-internals" = .{ .path = "../../../build-internals" }, }, .paths = .{ "LICENSE", diff --git a/port/nordic/nrf5x/build.zig b/port/nordic/nrf5x/build.zig index 595e0951..64c72f01 100644 --- a/port/nordic/nrf5x/build.zig +++ b/port/nordic/nrf5x/build.zig @@ -1,22 +1,36 @@ const std = @import("std"); -const Build = std.Build; -const MicroZig = @import("microzig/build"); +const microzig = @import("microzig/build-internals"); -fn path(comptime suffix: []const u8) std.Build.LazyPath { - return .{ - .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix), - }; -} +const Self = @This(); + +chips: struct { + nrf52840: *const microzig.Target, + nrf52832: *const microzig.Target, +}, + +boards: struct { + nordic: struct { + nrf52840_dongle: *const microzig.Target, + }, +}, + +pub fn init(dep: *std.Build.Dependency) Self { + const b = dep.builder; -pub const chips = struct { - pub const nrf52840 = MicroZig.Target{ - .preferred_format = .elf, + const chip_nrf52840: microzig.Target = .{ + .dep = dep, + .preferred_binary_format = .elf, .chip = .{ .name = "nrf52840", .url = "https://www.nordicsemi.com/products/nrf52840", - .cpu = MicroZig.cpus.cortex_m4, + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, .register_definition = .{ - .json = path("/src/chips/nrf52840.json"), + .json = b.path("src/chips/nrf52840.json"), }, .memory_regions = &.{ .{ .offset = 0x00000000, .length = 0x100000, .kind = .flash }, @@ -31,14 +45,20 @@ pub const chips = struct { }, }; - pub const nrf52832 = MicroZig.Target{ - .preferred_format = .elf, + const chip_nrf52832: microzig.Target = .{ + .dep = dep, + .preferred_binary_format = .elf, .chip = .{ .name = "nrf52", .url = "https://www.nordicsemi.com/products/nrf52832", - .cpu = MicroZig.cpus.cortex_m4, + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, .register_definition = .{ - .json = path("/src/chips/nrf52.json"), + .json = b.path("src/chips/nrf52.json"), }, .memory_regions = &.{ .{ .offset = 0x00000000, .length = 0x80000, .kind = .flash }, @@ -46,20 +66,26 @@ pub const chips = struct { }, }, }; -}; -pub const boards = struct { - pub const nordic_nRF52840_Dongle = MicroZig.Target{ - .preferred_format = .elf, - .chip = chips.nrf52840.chip, - .board = .{ - .name = "nRF52840 Dongle", - .url = "https://www.nordicsemi.com/Products/Development-hardware/nrf52840-dongle", - .root_source_file = path("/src/boards/nrf52840-dongle.zig"), + return .{ + .chips = .{ + .nrf52840 = chip_nrf52840.derive(.{}), + .nrf52832 = chip_nrf52832.derive(.{}), + }, + .boards = .{ + .nordic = .{ + .nrf52840_dongle = chip_nrf52840.derive(.{ + .board = .{ + .name = "nRF52840 Dongle", + .url = "https://www.nordicsemi.com/Products/Development-hardware/nrf52840-dongle", + .root_source_file = b.path("src/boards/nrf52840-dongle.zig"), + }, + }), + }, }, }; -}; +} -pub fn build(b: *Build) void { +pub fn build(b: *std.Build) void { _ = b.step("test", "Run platform agnostic unit tests"); } diff --git a/port/nordic/nrf5x/build.zig.zon b/port/nordic/nrf5x/build.zig.zon index 5809e7cf..4cbe5e11 100644 --- a/port/nordic/nrf5x/build.zig.zon +++ b/port/nordic/nrf5x/build.zig.zon @@ -2,7 +2,7 @@ .name = "port/nordic/nrf5x", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, + .@"microzig/build-internals" = .{ .path = "../../../build-internals" }, }, .paths = .{ "LICENSE", diff --git a/port/nxp/lpc/build.zig b/port/nxp/lpc/build.zig index e353cede..e16d8ca4 100644 --- a/port/nxp/lpc/build.zig +++ b/port/nxp/lpc/build.zig @@ -1,67 +1,77 @@ const std = @import("std"); -const MicroZig = @import("microzig/build"); +const microzig = @import("microzig/build-internals"); -fn path(comptime suffix: []const u8) std.Build.LazyPath { - return .{ - .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix), - }; -} +const Self = @This(); + +chips: struct { + lpc176x5x: *const microzig.Target, +}, + +boards: struct { + mbed: struct { + lpc1768: *const microzig.Target, + }, +}, -const hal = .{ - .root_source_file = path("/src/hals/LPC176x5x.zig"), -}; +pub fn init(dep: *std.Build.Dependency) Self { + const b = dep.builder; -pub const chips = struct { - pub const lpc176x5x = MicroZig.Target{ - .preferred_format = .elf, + const chip_lpc176x5x: microzig.Target = .{ + .dep = dep, + .preferred_binary_format = .elf, .chip = .{ - // TODO: Separate over those chips, this is not generic! .name = "LPC176x5x", - .cpu = MicroZig.cpus.cortex_m3, + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ .json = b.path("src/chips/LPC176x5x.json") }, .memory_regions = &.{ .{ .offset = 0x00000000, .length = 512 * 1024, .kind = .flash }, .{ .offset = 0x10000000, .length = 32 * 1024, .kind = .ram }, .{ .offset = 0x2007C000, .length = 32 * 1024, .kind = .ram }, }, - .register_definition = .{ - .json = path("/src/chips/LPC176x5x.json"), - }, }, - .hal = hal, - .binary_post_process = postprocess, + .hal = .{ + .root_source_file = b.path("src/hals/LPC176x5x.zig"), + }, + .patch_elf = lpc176x5x_patch_elf, }; -}; -pub const boards = struct { - pub const mbed = struct { - pub const lpc1768 = MicroZig.Target{ - .preferred_format = .hex, - .chip = chips.lpc176x5x.chip, - .hal = hal, - .board = .{ - .name = "mbed LPC1768", - .url = "https://os.mbed.com/platforms/mbed-LPC1768/", - .root_source_file = path("/src/boards/mbed_LPC1768.zig"), + return .{ + .chips = .{ + .lpc176x5x = chip_lpc176x5x.derive(.{}), + }, + .boards = .{ + .mbed = .{ + .lpc1768 = chip_lpc176x5x.derive(.{ + .board = .{ + .name = "mbed LPC1768", + .url = "https://os.mbed.com/platforms/mbed-LPC1768/", + .root_source_file = b.path("src/boards/mbed_LPC1768.zig"), + }, + }), }, - .binary_post_process = postprocess, - }; + }, }; -}; +} -/// Post-processes an ELF file to add a checksum over the first 8 words so the -/// cpu will properly boot. -fn postprocess(b: *std.Build, input: std.Build.LazyPath) std.Build.LazyPath { - const patchelf = b.addExecutable(.{ +pub fn build(b: *std.Build) void { + const lpc176x5x_patch_elf_exe = b.addExecutable(.{ .name = "lpc176x5x-patchelf", - .root_source_file = path("/src/tools/patchelf.zig"), + .root_source_file = b.path("src/tools/patchelf.zig"), .target = b.host, }); - - const patch = b.addRunArtifact(patchelf); - patch.addFileArg(input); - return patch.addOutputFileArg("firmware.elf"); + b.installArtifact(lpc176x5x_patch_elf_exe); } -pub fn build(b: *std.Build) void { - _ = b.step("test", "Run platform agnostic unit tests"); +/// Patch an ELF file to add a checksum over the first 8 words so the +/// cpu will properly boot. +fn lpc176x5x_patch_elf(dep: *std.Build.Dependency, input: std.Build.LazyPath) std.Build.LazyPath { + const patch_elf_exe = dep.artifact("lpc176x5x-patchelf"); + const run = dep.builder.addRunArtifact(patch_elf_exe); + run.addFileArg(input); + return run.addOutputFileArg("output.elf"); } diff --git a/port/nxp/lpc/build.zig.zon b/port/nxp/lpc/build.zig.zon index e4e0a32a..72e68c85 100644 --- a/port/nxp/lpc/build.zig.zon +++ b/port/nxp/lpc/build.zig.zon @@ -2,7 +2,7 @@ .name = "port/nxp/lpc", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, + .@"microzig/build-internals" = .{ .path = "../../../build-internals" }, }, .paths = .{ "LICENSE", diff --git a/port/raspberrypi/rp2xxx/build.zig b/port/raspberrypi/rp2xxx/build.zig index e069f65a..0404ad5f 100644 --- a/port/raspberrypi/rp2xxx/build.zig +++ b/port/raspberrypi/rp2xxx/build.zig @@ -1,146 +1,160 @@ const std = @import("std"); -const Build = std.Build; +const microzig = @import("microzig/build-internals"); -const MicroZig = @import("microzig/build"); -const Chip = MicroZig.Chip; -const Target = MicroZig.Target; -const Firmware = MicroZig.Firmware; +const Self = @This(); -fn root() []const u8 { - return comptime (std.fs.path.dirname(@src().file) orelse "."); -} -const build_root = root(); +chips: struct { + rp2040: *const microzig.Target, + rp2350_arm: *const microzig.Target, +}, -pub fn build(b: *Build) !void { - const unit_tests = b.addTest(.{ - .root_source_file = b.path("src/hal.zig"), - }); - unit_tests.addIncludePath(b.path("src/hal/pio/assembler")); +boards: struct { + raspberrypi: struct { + pico: *const microzig.Target, + pico2_arm: *const microzig.Target, + }, + waveshare: struct { + rp2040_plus_4m: *const microzig.Target, + rp2040_plus_16m: *const microzig.Target, + rp2040_eth: *const microzig.Target, + rp2040_matrix: *const microzig.Target, + }, +}, - const unit_tests_run = b.addRunArtifact(unit_tests); - const test_step = b.step("test", "Run platform agnostic unit tests"); - test_step.dependOn(&unit_tests_run.step); -} +pub fn init(dep: *std.Build.Dependency) Self { + const b = dep.builder; -pub const chips = struct { - // Note: This chip has no flash support defined and requires additional configuration! - pub const rp2040 = Target{ - .preferred_format = .{ .uf2 = .RP2040 }, - .chip = chip_rp2040, - .hal = hal, - .board = null, - .linker_script = linker_script_ld2040, + const hal: microzig.HardwareAbstractionLayer = .{ + .root_source_file = b.path("src/hal.zig"), }; - // Note: This chip has no flash support defined and requires additional configuration! - pub const rp2350_arm = Target{ - .preferred_format = .{ .uf2 = .RP2350_ARM_S }, - .chip = chip_rp2350_arm, + const chip_rp2040: microzig.Target = .{ + .dep = dep, + .preferred_binary_format = .{ .uf2 = .RP2040 }, + .chip = .{ + .name = "RP2040", + .cpu = std.Target.Query{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ .svd = b.path("src/chips/rp2040.svd") }, + .memory_regions = &.{ + .{ .kind = .flash, .offset = 0x10000100, .length = (2048 * 1024) - 256 }, + .{ .kind = .flash, .offset = 0x10000000, .length = 256 }, + .{ .kind = .ram, .offset = 0x20000000, .length = 256 * 1024 }, + }, + }, .hal = hal, - .board = null, - .linker_script = linker_script_ld2350, + .linker_script = b.path("rp2040.ld"), }; - // TODO: Not supporting the RISCV cores yet - // Note: This chip has no flash support defined and requires additional configuration! - // pub const rp2350_riscv = Target{ - // .preferred_format = .{ .uf2 = .RP2350_RISC_V }, - // .chip = chip_rp235X_riscv, - // .hal = hal_riscv, - // .board = null, - // .linker_script = linker_script_ld2350, - // }; -}; - -pub const boards = struct { - pub const raspberrypi = struct { - pub const pico = Target{ - .preferred_format = .{ .uf2 = .RP2040 }, - .chip = chip_rp2040, - .hal = hal, - .linker_script = linker_script_ld2040, - .board = .{ - .name = "RaspberryPi Pico", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/boards/raspberry_pi_pico.zig" }, - .url = "https://www.raspberrypi.com/products/raspberry-pi-pico/", + const chip_rp2350: microzig.Target = .{ + .dep = dep, + .preferred_binary_format = .{ .uf2 = .RP2350_ARM_S }, + .chip = .{ + .name = "RP2350", + .cpu = std.Target.Query{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .abi = .eabi, }, - .configure = rp2_configure(chip_rp2040, .w25q080), - }; - - pub const pico2 = Target{ - .preferred_format = .{ .uf2 = .RP2350_ARM_S }, - .chip = chip_rp2350_arm, - .hal = hal, - .linker_script = linker_script_ld2350, - .board = .{ - .name = "RaspberryPi Pico 2", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/boards/raspberry_pi_pico2.zig" }, - .url = "https://www.raspberrypi.com/products/raspberry-pi-pico2/", + .register_definition = .{ .svd = b.path("src/chips/rp2350.svd") }, + .memory_regions = &.{ + .{ .kind = .flash, .offset = 0x10000100, .length = (2048 * 1024) - 256 }, + .{ .kind = .flash, .offset = 0x10000000, .length = 256 }, + .{ .kind = .ram, .offset = 0x20000000, .length = 256 * 1024 }, }, - .configure = null, - }; + }, + .hal = hal, + .linker_script = b.path("rp2350.ld"), }; - pub const waveshare = struct { - pub const rp2040_plus_4m = Target{ - .preferred_format = .{ .uf2 = .RP2040 }, - .chip = chip_rp2040, - .hal = hal, - .linker_script = linker_script_ld2040, - .board = .{ - .name = "Waveshare RP2040-Plus (4M Flash)", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/boards/waveshare_rp2040_plus_4m.zig" }, - .url = "https://www.waveshare.com/rp2040-plus.htm", - }, - .configure = rp2_configure(chip_rp2040, .w25q080), - }; + const bootrom_rp2040 = get_bootrom(b, chip_rp2040.chip, .w25q080); + const rp2040_bootrom_imports = b.allocator.dupe(std.Build.Module.Import, &.{ + .{ .name = "bootloader", .module = b.createModule(.{ .root_source_file = bootrom_rp2040 }) }, + }) catch @panic("out of memory"); - pub const rp2040_plus_16m = Target{ - .preferred_format = .{ .uf2 = .RP2040 }, - .chip = chip_rp2040, - .hal = hal, - .linker_script = linker_script_ld2040, - .board = .{ - .name = "Waveshare RP2040-Plus (16M Flash)", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/boards/waveshare_rp2040_plus_16m.zig" }, - .url = "https://www.waveshare.com/rp2040-plus.htm", - }, - .configure = rp2_configure(chip_rp2040, .w25q080), - }; - - pub const rp2040_eth = Target{ - .preferred_format = .{ .uf2 = .RP2040 }, - .chip = chip_rp2040, - .hal = hal, - .linker_script = linker_script_ld2040, - .board = .{ - .name = "Waveshare RP2040-ETH Mini", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/boards/waveshare_rp2040_eth.zig" }, - .url = "https://www.waveshare.com/rp2040-eth.htm", + return .{ + .chips = .{ + .rp2040 = chip_rp2040.derive(.{}), + .rp2350_arm = chip_rp2350.derive(.{}), + }, + .boards = .{ + .raspberrypi = .{ + .pico = chip_rp2040.derive(.{ + .board = .{ + .name = "RaspberryPi Pico", + .url = "https://www.raspberrypi.com/products/raspberry-pi-pico/", + .root_source_file = b.path("src/boards/raspberry_pi_pico.zig"), + .imports = rp2040_bootrom_imports, + }, + }), + .pico2_arm = chip_rp2350.derive(.{ + .board = .{ + .name = "RaspberryPi Pico 2", + .url = "https://www.raspberrypi.com/products/raspberry-pi-pico2/", + .root_source_file = b.path("src/boards/raspberry_pi_pico2.zig"), + }, + }), }, - .configure = rp2_configure(chip_rp2040, .w25q080), - }; - - pub const rp2040_matrix = Target{ - .preferred_format = .{ .uf2 = .RP2040 }, - .chip = chip_rp2040, - .hal = hal, - .linker_script = linker_script_ld2040, - .board = .{ - .name = "Waveshare RP2040-Matrix", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/boards/waveshare_rp2040_matrix.zig" }, - .url = "https://www.waveshare.com/rp2040-matrix.htm", + .waveshare = .{ + .rp2040_plus_4m = chip_rp2040.derive(.{ + .board = .{ + .name = "Waveshare RP2040-Plus (4M Flash)", + .url = "https://www.waveshare.com/rp2040-plus.htm", + .root_source_file = b.path("src/boards/waveshare_rp2040_plus_4m.zig"), + .imports = rp2040_bootrom_imports, + }, + }), + .rp2040_plus_16m = chip_rp2040.derive(.{ + .board = .{ + .name = "Waveshare RP2040-Plus (16M Flash)", + .url = "https://www.waveshare.com/rp2040-plus.htm", + .root_source_file = b.path("src/boards/waveshare_rp2040_plus_16m.zig"), + .imports = rp2040_bootrom_imports, + }, + }), + .rp2040_eth = chip_rp2040.derive(.{ + .board = .{ + .name = "Waveshare RP2040-ETH Mini", + .url = "https://www.waveshare.com/rp2040-eth.htm", + .root_source_file = b.path("src/boards/waveshare_rp2040_eth.zig"), + .imports = rp2040_bootrom_imports, + }, + }), + .rp2040_matrix = chip_rp2040.derive(.{ + .board = .{ + .name = "Waveshare RP2040-Matrix", + .url = "https://www.waveshare.com/rp2040-matrix.htm", + .root_source_file = b.path("src/boards/waveshare_rp2040_matrix.zig"), + .imports = rp2040_bootrom_imports, + }, + }), }, - .configure = rp2_configure(chip_rp2040, .w25q080), - }; + }, }; -}; +} -pub const BootROM = union(enum) { - artifact: *Build.Step.Compile, // provide a custom startup code - blob: Build.LazyPath, // just include a binary blob +pub fn build(b: *std.Build) !void { + // TODO: construct all bootroms here and expose them via lazy paths: requires zig 0.14 - // Pre-shipped ones: + const optimize = b.standardOptimizeOption(.{}); + + const unit_tests = b.addTest(.{ + .root_source_file = b.path("src/hal.zig"), + .optimize = optimize, + }); + unit_tests.addIncludePath(b.path("src/hal/pio/assembler")); + + const unit_tests_run = b.addRunArtifact(unit_tests); + const test_step = b.step("test", "Run platform agnostic unit tests"); + test_step.dependOn(&unit_tests_run.step); +} + +const BootROM = union(enum) { at25sf128a, generic_03h, is25lp080, @@ -151,124 +165,26 @@ pub const BootROM = union(enum) { legacy, }; -const linker_script_ld2040 = .{ - .cwd_relative = build_root ++ "/rp2040.ld", -}; -const linker_script_ld2350 = .{ - .cwd_relative = build_root ++ "/rp2350.ld", -}; - -const hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/src/hal.zig" }, -}; - -const chip_rp2040 = .{ - .name = "RP2040", - .url = "https://www.raspberrypi.com/products/rp2040/", - .cpu = MicroZig.cpus.cortex_m0plus, - .register_definition = .{ - .svd = .{ .cwd_relative = build_root ++ "/src/chips/rp2040.svd" }, - }, - .memory_regions = &.{ - .{ .kind = .flash, .offset = 0x10000100, .length = (2048 * 1024) - 256 }, - .{ .kind = .flash, .offset = 0x10000000, .length = 256 }, - .{ .kind = .ram, .offset = 0x20000000, .length = 256 * 1024 }, - }, -}; -const chip_rp2350_arm = .{ - .name = "RP2350", - .url = "https://www.raspberrypi.com/products/rp2350/", - .cpu = MicroZig.cpus.cortex_m33, - .register_definition = .{ - .svd = .{ .cwd_relative = build_root ++ "/src/chips/rp2350.svd" }, - }, - .memory_regions = &.{ - .{ .kind = .flash, .offset = 0x10000100, .length = (4096 * 1024) - 256 }, - .{ .kind = .flash, .offset = 0x10000000, .length = 256 }, - .{ .kind = .ram, .offset = 0x20000000, .length = 520 * 1024 }, - }, -}; -const chip_rp2350_riscv = .{ - .name = "RP2350", - .url = "https://www.raspberrypi.com/products/rp2350/", - .cpu = MicroZig.cpus.riscv32, - .register_definition = .{ - .svd = .{ .cwd_relative = build_root ++ "/src/chips/rp2350.svd" }, - }, - .memory_regions = &.{ - .{ .kind = .flash, .offset = 0x10000100, .length = (4096 * 1024) - 256 }, - .{ .kind = .flash, .offset = 0x10000000, .length = 256 }, - .{ .kind = .ram, .offset = 0x20000000, .length = 520 * 1024 }, - }, -}; - -/// Returns a configuration function that will add the provided `BootROM` to the firmware. -pub fn rp2_configure(comptime chip: Chip, comptime bootrom: BootROM) *const fn (mz: *MicroZig, *Firmware) void { - const T = struct { - fn configure(mz: *MicroZig, fw: *Firmware) void { - const bootrom_file = get_bootrom(mz, chip, bootrom); - - // HACK: Inject the file as a dependency to MicroZig.board - fw.modules.board.?.addImport( - "bootloader", - mz.host_build.createModule(.{ - .root_source_file = bootrom_file.bin, - }), - ); - - // TODO: is this required? - bootrom_file.bin.addStepDependencies(&fw.artifact.step); - } - }; +fn get_bootrom(b: *std.Build, chip: microzig.Chip, rom: BootROM) std.Build.LazyPath { + var target = chip.cpu; + target.abi = .eabi; - return T.configure; -} - -pub const Stage2Bootloader = struct { - bin: Build.LazyPath, - elf: ?Build.LazyPath, -}; - -pub fn get_bootrom(mz: *MicroZig, chip: Chip, rom: BootROM) Stage2Bootloader { - const rom_exe = switch (rom) { - .artifact => |artifact| artifact, - .blob => |blob| return Stage2Bootloader{ - .bin = blob, - .elf = null, - }, - - else => blk: { - var target = chip.cpu.target; - target.abi = .eabi; - - const rom_path = mz.host_build.pathFromRoot( - mz.host_build.fmt("{s}/src/bootroms/{s}/{s}.S", .{ build_root, chip.name, @tagName(rom) }), - ); - - const rom_exe = mz.host_build.addExecutable(.{ - .name = mz.host_build.fmt("stage2-{s}", .{@tagName(rom)}), - .optimize = .ReleaseSmall, - .target = mz.host_build.resolveTargetQuery(target), - .root_source_file = null, - }); - //rom_exe.linkage = .static; - rom_exe.setLinkerScript(.{ - .cwd_relative = mz.host_build.fmt("{s}/src/bootroms/{s}/shared/stage2.ld", .{ build_root, chip.name }), - }); - rom_exe.addAssemblyFile(.{ .cwd_relative = rom_path }); - rom_exe.entry = .{ .symbol_name = "_stage2_boot" }; + const rom_exe = b.addExecutable(.{ + .name = b.fmt("stage2-{s}", .{@tagName(rom)}), + .optimize = .ReleaseSmall, + .target = b.resolveTargetQuery(target), + .root_source_file = null, + }); - break :blk rom_exe; - }, - }; + //rom_exe.linkage = .static; + rom_exe.setLinkerScript(b.path(b.fmt("src/bootroms/{s}/shared/stage2.ld", .{chip.name}))); + rom_exe.addAssemblyFile(b.path(b.fmt("src/bootroms/{s}/{s}.S", .{ chip.name, @tagName(rom) }))); + rom_exe.entry = .{ .symbol_name = "_stage2_boot" }; - const rom_objcopy = mz.host_build.addObjCopy(rom_exe.getEmittedBin(), .{ - .basename = mz.host_build.fmt("{s}.bin", .{@tagName(rom)}), + const rom_objcopy = b.addObjCopy(rom_exe.getEmittedBin(), .{ + .basename = b.fmt("{s}.bin", .{@tagName(rom)}), .format = .bin, }); - return Stage2Bootloader{ - .bin = rom_objcopy.getOutput(), - .elf = rom_exe.getEmittedBin(), - }; + return rom_objcopy.getOutput(); } diff --git a/port/raspberrypi/rp2xxx/build.zig.zon b/port/raspberrypi/rp2xxx/build.zig.zon index 018c5057..3a58b8a7 100644 --- a/port/raspberrypi/rp2xxx/build.zig.zon +++ b/port/raspberrypi/rp2xxx/build.zig.zon @@ -2,9 +2,7 @@ .name = "port/raspberrypi/rp2xxx", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ - .path = "../../../build", - }, + .@"microzig/build-internals" = .{ .path = "../../../build-internals" }, }, .paths = .{ "LICENSE", diff --git a/port/stmicro/stm32/build.zig b/port/stmicro/stm32/build.zig index 1d2eea6a..15260283 100644 --- a/port/stmicro/stm32/build.zig +++ b/port/stmicro/stm32/build.zig @@ -1,14 +1,51 @@ const std = @import("std"); -const MicroZig = @import("microzig/build"); - -fn root() []const u8 { - return comptime (std.fs.path.dirname(@src().file) orelse "."); +const microzig = @import("microzig/build-internals"); +const Chips = @import("src/Chips.zig"); + +const Self = @This(); + +chips: Chips, +boards: struct { + stm32f3discovery: *const microzig.Target, + stm32f4discovery: *const microzig.Target, + stm3240geval: *const microzig.Target, + stm32f429idiscovery: *const microzig.Target, +}, + +pub fn init(dep: *std.Build.Dependency) Self { + const b = dep.builder; + const chips = Chips.init(dep); + + return .{ + .chips = chips, + .boards = .{ + .stm32f3discovery = chips.STM32F303VC.derive(.{ + .board = .{ + .name = "STM32F3DISCOVERY", + .root_source_file = b.path("src/boards/STM32F3DISCOVERY.zig"), + }, + }), + .stm32f4discovery = chips.STM32F407VG.derive(.{ + .board = .{ + .name = "STM32F4DISCOVERY", + .root_source_file = b.path("src/boards/STM32F4DISCOVERY.zig"), + }, + }), + .stm3240geval = chips.STM32F407VG.derive(.{ + .board = .{ + .name = "STM3240G_EVAL", + .root_source_file = b.path("src/boards/STM3240G_EVAL.zig"), + }, + }), + .stm32f429idiscovery = chips.STM32F429ZI.derive(.{ + .board = .{ + .name = "STM32F429IDISCOVERY", + .root_source_file = b.path("src/boards/STM32F429IDISCOVERY.zig"), + }, + }), + }, + }; } -const build_root = root(); - -const KiB = 1024; - -pub const chips = @import("src/chips.zig"); pub fn build(b: *std.Build) !void { const update = b.step("update", "Update chip definitions from embassy-rs/stm32-data-generated"); @@ -33,75 +70,3 @@ pub fn build(b: *std.Build) !void { _ = b.step("test", "Run platform agnostic unit tests"); } - -pub const boards = struct { - pub const stm32f3discovery = MicroZig.Target{ - .preferred_format = .elf, - .chip = chips.STM32F303VC.chip, - .board = .{ - .name = "STM32F3DISCOVERY", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/boards/STM32F3DISCOVERY.zig" }, - }, - }; - - pub const stm32f4discovery = MicroZig.Target{ - .preferred_format = .elf, - .chip = chips.STM32F407VG.chip, - .board = .{ - .name = "STM32F4DISCOVERY", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/boards/STM32F4DISCOVERY.zig" }, - }, - }; - - pub const stm3240geval = MicroZig.Target{ - .preferred_format = .elf, - .chip = chips.STM32F407VG.chip, - .board = .{ - .name = "STM3240G_EVAL", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/boards/STM3240G_EVAL.zig" }, - }, - }; - - pub const stm32f429idiscovery = MicroZig.Target{ - .preferred_format = .elf, - .chip = chips.STM32F429ZI.chip, - .board = .{ - .name = "STM32F429IDISCOVERY", - .root_source_file = .{ .cwd_relative = build_root ++ "/src/boards/STM32F429IDISCOVERY.zig" }, - }, - }; -}; - -// pub fn build(b: *std.build.Builder) void { -// _ = b; -// const optimize = b.standardOptimizeOption(.{}); -// inline for (@typeInfo(boards).Struct.decls) |decl| { -// if (!decl.is_pub) -// continue; - -// const exe = microzig.addEmbeddedExecutable(b, .{ -// .name = @field(boards, decl.name).name ++ ".minimal", -// .root_source_file = .{ -// .path = "test/programs/minimal.zig", -// }, -// .backing = .{ .board = @field(boards, decl.name) }, -// .optimize = optimize, -// }); -// exe.installArtifact(b); -// } - -// inline for (@typeInfo(chips).Struct.decls) |decl| { -// if (!decl.is_pub) -// continue; - -// const exe = microzig.addEmbeddedExecutable(b, .{ -// .name = @field(chips, decl.name).name ++ ".minimal", -// .root_source_file = .{ -// .path = "test/programs/minimal.zig", -// }, -// .backing = .{ .chip = @field(chips, decl.name) }, -// .optimize = optimize, -// }); -// exe.installArtifact(b); -// } -// } diff --git a/port/stmicro/stm32/build.zig.zon b/port/stmicro/stm32/build.zig.zon index 73805954..5b0457f5 100644 --- a/port/stmicro/stm32/build.zig.zon +++ b/port/stmicro/stm32/build.zig.zon @@ -2,7 +2,7 @@ .name = "port/stmicro/stm32", .version = "0.0.0", .dependencies = .{ - .@"microzig/build" = .{ .path = "../../../build" }, + .@"microzig/build-internals" = .{ .path = "../../../build-internals" }, .@"microzig/tools/regz" = .{ .path = "../../../tools/regz" }, .@"stm32-data-generated" = .{ .url = "git+https://github.com/embassy-rs/stm32-data-generated.git#5198a6e36b24f6d79c4ac91af5e61e8d54667d88", diff --git a/port/stmicro/stm32/src/Chips.zig b/port/stmicro/stm32/src/Chips.zig new file mode 100644 index 00000000..f8f847cf --- /dev/null +++ b/port/stmicro/stm32/src/Chips.zig @@ -0,0 +1,35666 @@ +const std = @import("std"); +const microzig = @import("microzig/build-internals"); + +const Self = @This(); + +STM32C011D6: *microzig.Target, +STM32C011F4: *microzig.Target, +STM32C011F6: *microzig.Target, +STM32C011J4: *microzig.Target, +STM32C011J6: *microzig.Target, +STM32C031C4: *microzig.Target, +STM32C031C6: *microzig.Target, +STM32C031F4: *microzig.Target, +STM32C031F6: *microzig.Target, +STM32C031G4: *microzig.Target, +STM32C031G6: *microzig.Target, +STM32C031K4: *microzig.Target, +STM32C031K6: *microzig.Target, +STM32F030C6: *microzig.Target, +STM32F030C8: *microzig.Target, +STM32F030CC: *microzig.Target, +STM32F030F4: *microzig.Target, +STM32F030K6: *microzig.Target, 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*microzig.Target, +@"STM32L151C8-A": *microzig.Target, +STM32L151CB: *microzig.Target, +@"STM32L151CB-A": *microzig.Target, +STM32L151CC: *microzig.Target, +STM32L151QC: *microzig.Target, +STM32L151QD: *microzig.Target, +STM32L151QE: *microzig.Target, +STM32L151R6: *microzig.Target, +@"STM32L151R6-A": *microzig.Target, +STM32L151R8: *microzig.Target, +@"STM32L151R8-A": *microzig.Target, +STM32L151RB: *microzig.Target, +@"STM32L151RB-A": *microzig.Target, +STM32L151RC: *microzig.Target, +@"STM32L151RC-A": *microzig.Target, +STM32L151RD: *microzig.Target, +STM32L151RE: *microzig.Target, +STM32L151UC: *microzig.Target, +STM32L151V8: *microzig.Target, +@"STM32L151V8-A": *microzig.Target, +STM32L151VB: *microzig.Target, +@"STM32L151VB-A": *microzig.Target, +STM32L151VC: *microzig.Target, +@"STM32L151VC-A": *microzig.Target, +STM32L151VD: *microzig.Target, +@"STM32L151VD-X": *microzig.Target, +STM32L151VE: *microzig.Target, +STM32L151ZC: *microzig.Target, +STM32L151ZD: *microzig.Target, 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*microzig.Target, +STM32L152VE: *microzig.Target, +STM32L152ZC: *microzig.Target, +STM32L152ZD: *microzig.Target, +STM32L152ZE: *microzig.Target, +STM32L162QC: *microzig.Target, +STM32L162QD: *microzig.Target, +STM32L162RC: *microzig.Target, +@"STM32L162RC-A": *microzig.Target, +STM32L162RD: *microzig.Target, +STM32L162RE: *microzig.Target, +STM32L162VC: *microzig.Target, +@"STM32L162VC-A": *microzig.Target, +STM32L162VD: *microzig.Target, +@"STM32L162VD-X": *microzig.Target, +STM32L162VE: *microzig.Target, +STM32L162ZC: *microzig.Target, +STM32L162ZD: *microzig.Target, +STM32L162ZE: *microzig.Target, +STM32L412C8: *microzig.Target, +STM32L412CB: *microzig.Target, +STM32L412K8: *microzig.Target, +STM32L412KB: *microzig.Target, +STM32L412R8: *microzig.Target, +STM32L412RB: *microzig.Target, +STM32L412T8: *microzig.Target, +STM32L412TB: *microzig.Target, +STM32L422CB: *microzig.Target, +STM32L422KB: *microzig.Target, +STM32L422RB: *microzig.Target, +STM32L422TB: *microzig.Target, +STM32L431CB: *microzig.Target, +STM32L431CC: *microzig.Target, +STM32L431KB: *microzig.Target, +STM32L431KC: *microzig.Target, +STM32L431RB: *microzig.Target, +STM32L431RC: *microzig.Target, +STM32L431VC: *microzig.Target, +STM32L432KB: *microzig.Target, +STM32L432KC: *microzig.Target, +STM32L433CB: *microzig.Target, +STM32L433CC: *microzig.Target, +STM32L433RB: *microzig.Target, +STM32L433RC: *microzig.Target, +STM32L433VC: *microzig.Target, +STM32L442KC: *microzig.Target, +STM32L443CC: *microzig.Target, +STM32L443RC: *microzig.Target, +STM32L443VC: *microzig.Target, +STM32L451CC: *microzig.Target, +STM32L451CE: *microzig.Target, +STM32L451RC: *microzig.Target, +STM32L451RE: *microzig.Target, +STM32L451VC: *microzig.Target, +STM32L451VE: *microzig.Target, +STM32L452CC: *microzig.Target, +STM32L452CE: *microzig.Target, +STM32L452RC: *microzig.Target, +STM32L452RE: *microzig.Target, +STM32L452VC: *microzig.Target, +STM32L452VE: *microzig.Target, +STM32L462CE: *microzig.Target, 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+STM32U5G7VJ: *microzig.Target, +STM32U5G9BJ: *microzig.Target, +STM32U5G9NJ: *microzig.Target, +STM32U5G9VJ: *microzig.Target, +STM32U5G9ZJ: *microzig.Target, +STM32WB10CC: *microzig.Target, +STM32WB15CC: *microzig.Target, +STM32WB30CE: *microzig.Target, +STM32WB35CC: *microzig.Target, +STM32WB35CE: *microzig.Target, +STM32WB50CG: *microzig.Target, +STM32WB55CC: *microzig.Target, +STM32WB55CE: *microzig.Target, +STM32WB55CG: *microzig.Target, +STM32WB55RC: *microzig.Target, +STM32WB55RE: *microzig.Target, +STM32WB55RG: *microzig.Target, +STM32WB55VC: *microzig.Target, +STM32WB55VE: *microzig.Target, +STM32WB55VG: *microzig.Target, +STM32WB55VY: *microzig.Target, +STM32WBA50KE: *microzig.Target, +STM32WBA50KG: *microzig.Target, +STM32WBA52CE: *microzig.Target, +STM32WBA52CG: *microzig.Target, +STM32WBA52KE: *microzig.Target, +STM32WBA52KG: *microzig.Target, +STM32WBA54CE: *microzig.Target, +STM32WBA54CG: *microzig.Target, +STM32WBA54KE: *microzig.Target, +STM32WBA54KG: *microzig.Target, +STM32WBA55CE: *microzig.Target, +STM32WBA55CG: *microzig.Target, +STM32WBA55HE: *microzig.Target, +STM32WBA55HG: *microzig.Target, +STM32WBA55UE: *microzig.Target, +STM32WBA55UG: *microzig.Target, +STM32WL54CC: *microzig.Target, +STM32WL54JC: *microzig.Target, +STM32WL55CC: *microzig.Target, +STM32WL55JC: *microzig.Target, +STM32WLE4C8: *microzig.Target, +STM32WLE4CB: *microzig.Target, +STM32WLE4CC: *microzig.Target, +STM32WLE4J8: *microzig.Target, +STM32WLE4JB: *microzig.Target, +STM32WLE4JC: *microzig.Target, +STM32WLE5C8: *microzig.Target, +STM32WLE5CB: *microzig.Target, +STM32WLE5CC: *microzig.Target, +STM32WLE5J8: *microzig.Target, +STM32WLE5JB: *microzig.Target, +STM32WLE5JC: *microzig.Target, + +pub fn init(dep: *std.Build.Dependency) Self { + const b = dep.builder; + const register_definition_path = b.path("src/chips/all.zig"); + + var ret: Self = undefined; + + ret.STM32C011D6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C011D6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C011D6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32C011F4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C011F4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C011F4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32C011F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C011F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C011F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32C011J4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C011J4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C011J4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32C011J6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C011J6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C011J6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32C031C4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C031C4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C031C4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32C031C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C031C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C031C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32C031F4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C031F4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C031F4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32C031F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C031F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C031F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32C031G4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C031G4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C031G4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32C031G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C031G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C031G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32C031K4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C031K4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C031K4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32C031K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32C031K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32C031K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F030C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F030C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F030C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F030C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F030C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F030C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F030CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F030CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F030CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F030F4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F030F4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F030F4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F030K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F030K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F030K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F030R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F030R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F030R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F030RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F030RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F030RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F031C4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F031C4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F031C4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F031C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F031C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F031C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F031E6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F031E6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F031E6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F031F4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F031F4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F031F4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F031F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F031F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F031F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F031G4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F031G4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F031G4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F031G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F031G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F031G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F031K4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F031K4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F031K4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F031K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F031K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F031K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F038C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F038C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F038C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F038E6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F038E6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F038E6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F038F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F038F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F038F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F038G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F038G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F038G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F038K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F038K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F038K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F042C4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F042C4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F042C4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F042C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F042C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F042C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F042F4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F042F4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F042F4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F042F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F042F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F042F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F042G4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F042G4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F042G4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F042G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F042G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F042G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F042K4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F042K4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F042K4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F042K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F042K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F042K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F042T6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F042T6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F042T6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F048C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F048C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F048C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F048G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F048G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F048G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F048T6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F048T6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F048T6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F051C4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F051C4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F051C4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F051C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F051C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F051C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F051C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F051C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F051C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F051K4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F051K4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F051K4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F051K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F051K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F051K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F051K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F051K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F051K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F051R4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F051R4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F051R4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F051R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F051R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F051R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F051R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F051R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F051R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F051T8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F051T8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F051T8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F058C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F058C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F058C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F058R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F058R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F058R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F058T8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F058T8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F058T8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F070C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F070C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F070C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F070CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F070CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F070CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F070F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F070F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F070F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F070RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F070RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F070RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F071C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F071C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F071C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F071CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F071CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F071CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F071RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F071RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F071RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F071V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F071V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F071V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F071VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F071VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F071VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F072C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F072C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F072C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F072CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F072CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F072CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F072R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F072R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F072R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F072RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F072RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F072RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F072V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F072V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F072V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F072VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F072VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F072VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F078CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F078CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F078CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F078RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F078RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F078RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F078VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F078VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F078VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F091CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F091CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F091CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F091CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F091CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F091CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F091RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F091RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F091RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F091RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F091RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F091RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F091VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F091VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F091VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F091VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F091VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F091VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F098CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F098CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F098CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F098RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F098RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F098RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F098VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F098VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F098VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100C4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100C4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100C4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100R4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100R4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100R4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100RD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100RD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100RD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100VD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100VD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100VD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100ZD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100ZD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100ZD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F100ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F100ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F100ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101C4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101C4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101C4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F101C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32F101CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101R4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101R4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101R4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F101R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32F101RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101RD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101RD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101RD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101RF = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101RF.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101RF", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101T4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101T4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101T4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101T6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101T6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101T6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F101T8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101T8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101T8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32F101TB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101TB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101TB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32F101VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101VD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101VD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101VD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101VF = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101VF.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101VF", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101ZD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101ZD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101ZD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101ZF = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101ZF.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101ZF", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32F101ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F101ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F101ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32F102C4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F102C4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F102C4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F102C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F102C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F102C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F102C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F102C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F102C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32F102CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F102CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F102CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F102R4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F102R4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F102R4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32F102R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F102R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F102R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + }; + + ret.STM32F102R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F102R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F102R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32F102RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F102RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F102RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F103C4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103C4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103C4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103R4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103R4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103R4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103RD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103RD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103RD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103RF = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103RF.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103RF", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103T4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103T4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103T4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103T6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103T6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103T6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103T8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103T8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103T8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103TB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103TB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103TB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103VD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103VD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103VD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103VF = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103VF.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103VF", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103ZD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103ZD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103ZD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103ZF = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103ZF.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103ZF", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F103ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F103ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F103ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + .hal = .{ + .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + }, + }; + + ret.STM32F105R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F105R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F105R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F105RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F105RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F105RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F105RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F105RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F105RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F105V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F105V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F105V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F105VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F105VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F105VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F105VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F105VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F105VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F107RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F107RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F107RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F107RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F107RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F107RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F107VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F107VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F107VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F107VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F107VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F107VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205RF = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205RF.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205RF", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xA0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205VF = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205VF.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205VF", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xA0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205ZF = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205ZF.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205ZF", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xA0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F205ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F205ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F205ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F207IC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F207IC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F207IC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F207IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F207IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F207IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F207IF = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F207IF.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F207IF", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xA0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F207IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F207IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F207IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F207VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F207VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F207VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F207VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F207VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F207VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F207VF = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F207VF.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F207VF", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xA0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F207VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F207VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F207VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F207ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F207ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F207ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F207ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F207ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F207ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F207ZF = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F207ZF.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F207ZF", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xA0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F207ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F207ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F207ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F215RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F215RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F215RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F215RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F215RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F215RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F215VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F215VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F215VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F215VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F215VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F215VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F215ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F215ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F215ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F215ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F215ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F215ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F217IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F217IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F217IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F217IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F217IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F217IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F217VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F217VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F217VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F217VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F217VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F217VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F217ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F217ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F217ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F217ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F217ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F217ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F301C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F301C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F301C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F301C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F301C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F301C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F301K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F301K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F301K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F301K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F301K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F301K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F301R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F301R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F301R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F301R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F301R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F301R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302RD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302RD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302RD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302VD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302VD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302VD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302ZD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302ZD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302ZD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F302ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F302ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F302ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303RD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303RD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303RD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303VD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303VD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303VD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303ZD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303ZD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303ZD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F303ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F303ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F303ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F318C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F318C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F318C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F318K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F318K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F318K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F328C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F328C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F328C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F334C4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F334C4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F334C4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F334C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F334C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F334C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F334C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F334C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F334C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F334K4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F334K4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F334K4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F334K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F334K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F334K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F334K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F334K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F334K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F334R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F334R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F334R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F334R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F334R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F334R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32F358CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F358CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F358CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32F358RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F358RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F358RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32F358VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F358VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F358VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32F373C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F373C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F373C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F373CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F373CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F373CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, + }, + }, + }; + + ret.STM32F373CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F373CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F373CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F373R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F373R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F373R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F373RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F373RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F373RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, + }, + }, + }; + + ret.STM32F373RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F373RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F373RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F373V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F373V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F373V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F373VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F373VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F373VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, + }, + }, + }; + + ret.STM32F373VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F373VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F373VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F378CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F378CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F378CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F378RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F378RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F378RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F378VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F378VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F378VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F398VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F398VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F398VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F401CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F401CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F401CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F401CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F401CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F401CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F401CD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F401CD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F401CD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32F401CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F401CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F401CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32F401RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F401RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F401RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F401RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F401RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F401RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F401RD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F401RD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F401RD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32F401RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F401RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F401RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32F401VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F401VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F401VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F401VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F401VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F401VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32F401VD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F401VD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F401VD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32F401VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F401VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F401VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32F405OE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F405OE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F405OE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F405OG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F405OG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F405OG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F405RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F405RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F405RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F405VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F405VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F405VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F405ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F405ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F405ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F407IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F407IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F407IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F407IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F407IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F407IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F407VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F407VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F407VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F407VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F407VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F407VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F407ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F407ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F407ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F407ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F407ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F407ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, + .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32F410C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F410C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F410C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F410CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F410CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F410CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F410R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F410R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F410R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F410RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F410RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F410RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F410T8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F410T8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F410T8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F410TB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F410TB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F410TB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32F411CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F411CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F411CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F411CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F411CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F411CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F411RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F411RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F411RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F411RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F411RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F411RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F411VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F411VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F411VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F411VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F411VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F411VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F412CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F412CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F412CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F412CG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F412CG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F412CG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F412RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F412RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F412RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F412RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F412RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F412RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F412VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F412VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F412VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F412VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F412VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F412VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F412ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F412ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F412ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F412ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F412ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F412ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F413CG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F413CG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F413CG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F413CH = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F413CH.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F413CH", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F413MG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F413MG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F413MG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F413MH = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F413MH.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F413MH", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F413RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F413RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F413RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F413RH = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F413RH.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F413RH", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F413VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F413VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F413VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F413VH = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F413VH.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F413VH", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F413ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F413ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F413ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F413ZH = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F413ZH.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F413ZH", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F415OG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F415OG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F415OG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F415RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F415RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F415RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F415VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F415VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F415VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F415ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F415ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F415ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F417IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F417IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F417IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F417IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F417IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F417IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F417VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F417VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F417VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F417VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F417VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F417VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F417ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F417ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F417ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F417ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F417ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F417ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F423CH = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F423CH.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F423CH", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F423MH = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F423MH.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F423MH", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F423RH = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F423RH.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F423RH", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F423VH = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F423VH.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F423VH", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F423ZH = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F423ZH.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F423ZH", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F427AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F427AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F427AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F427AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F427AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F427AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F427IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F427IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F427IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F427II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F427II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F427II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F427VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F427VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F427VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F427VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F427VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F427VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F427ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F427ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F427ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F427ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F427ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F427ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429BE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429BE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429BE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429NE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429NE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429NE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429NG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429NG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429NG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429NI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429NI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429NI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F429ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F429ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F429ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F437AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F437AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F437AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F437IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F437IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F437IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F437II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F437II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F437II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F437VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F437VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F437VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F437VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F437VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F437VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F437ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F437ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F437ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F437ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F437ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F437ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F439AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F439AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F439AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F439BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F439BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F439BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F439BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F439BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F439BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F439IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F439IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F439IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F439II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F439II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F439II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F439NG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F439NG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F439NG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F439NI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F439NI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F439NI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F439VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F439VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F439VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F439VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F439VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F439VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F439ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F439ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F439ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F439ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F439ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F439ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F446MC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F446MC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F446MC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F446ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F446ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F446ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F446RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F446RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F446RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F446RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F446RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F446RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F446VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F446VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F446VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F446VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F446VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F446VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F446ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F446ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F446ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F446ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F446ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F446ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469AE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469AE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469AE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469BE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469BE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469BE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469NE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469NE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469NE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469NG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469NG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469NG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469NI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469NI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469NI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F469ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F469ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F469ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F479AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F479AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F479AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F479AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F479AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F479AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F479BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F479BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F479BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F479BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F479BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F479BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F479IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F479IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F479IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F479II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F479II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F479II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F479NG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F479NG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F479NG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F479NI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F479NI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F479NI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F479VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F479VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F479VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F479VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F479VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F479VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F479ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F479ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F479ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F479ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F479ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F479ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32F722IC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F722IC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F722IC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F722IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F722IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F722IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F722RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F722RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F722RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F722RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F722RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F722RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F722VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F722VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F722VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F722VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F722VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F722VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F722ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F722ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F722ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F722ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F722ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F722ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F723IC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F723IC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F723IC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F723IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F723IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F723IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F723VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F723VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F723VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F723VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F723VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F723VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F723ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F723ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F723ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F723ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F723ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F723ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F730I8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F730I8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F730I8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F730R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F730R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F730R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F730V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F730V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F730V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F730Z8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F730Z8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F730Z8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F732IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F732IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F732IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F732RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F732RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F732RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F732VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F732VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F732VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F732ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F732ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F732ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F733IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F733IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F733IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F733VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F733VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F733VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F733ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F733ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F733ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, + }, + }, + }; + + ret.STM32F745IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F745IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F745IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F745IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F745IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F745IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F745VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F745VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F745VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F745VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F745VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F745VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F745ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F745ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F745ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F745ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F745ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F745ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F746BE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F746BE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F746BE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F746BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F746BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F746BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F746IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F746IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F746IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F746IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F746IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F746IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F746NE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F746NE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F746NE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F746NG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F746NG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F746NG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F746VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F746VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F746VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F746VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F746VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F746VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F746ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F746ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F746ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F746ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F746ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F746ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F750N8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F750N8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F750N8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F750V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F750V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F750V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F750Z8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F750Z8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F750Z8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F756BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F756BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F756BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F756IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F756IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F756IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F756NG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F756NG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F756NG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F756VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F756VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F756VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F756ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F756ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F756ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32F765BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F765BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F765BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F765BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F765BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F765BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F765IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F765IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F765IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F765II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F765II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F765II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F765NG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F765NG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F765NG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F765NI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F765NI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F765NI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F765VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F765VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F765VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F765VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F765VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F765VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F765ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F765ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F765ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F765ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F765ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F765ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F767BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F767BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F767BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F767BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F767BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F767BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F767IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F767IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F767IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F767II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F767II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F767II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F767NG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F767NG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F767NG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F767NI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F767NI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F767NI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F767VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F767VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F767VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F767VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F767VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F767VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F767ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F767ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F767ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F767ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F767ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F767ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F768AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F768AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F768AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F769AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F769AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F769AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F769AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F769AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F769AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F769BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F769BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F769BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F769BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F769BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F769BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F769IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F769IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F769IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F769II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F769II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F769II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F769NG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F769NG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F769NG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F769NI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F769NI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F769NI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F777BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F777BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F777BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F777II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F777II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F777II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F777NI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F777NI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F777NI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F777VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F777VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F777VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F777ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F777ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F777ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F778AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F778AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F778AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F779AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F779AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F779AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F779BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F779BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F779BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F779II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F779II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F779II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32F779NI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32F779NI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32F779NI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, + }, + }, + }; + + ret.STM32G030C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G030C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G030C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G030C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G030C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G030C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G030F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G030F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G030F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G030J6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G030J6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G030J6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G030K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G030K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G030K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G030K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G030K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G030K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031C4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031C4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031C4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031F4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031F4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031F4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031F8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031F8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031F8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031G4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031G4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031G4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031G8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031G8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031G8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031J4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031J4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031J4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031J6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031J6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031J6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031K4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031K4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031K4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G031Y8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G031Y8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G031Y8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G041C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G041C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G041C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G041C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G041C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G041C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G041F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G041F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G041F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G041F8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G041F8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G041F8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G041G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G041G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G041G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G041G8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G041G8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G041G8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G041J6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G041J6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G041J6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G041K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G041K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G041K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G041K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G041K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G041K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G041Y8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G041Y8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G041Y8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32G050C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G050C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G050C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G050C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G050C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G050C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G050F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G050F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G050F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G050K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G050K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G050K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G050K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G050K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G050K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G051C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G051C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G051C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G051C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G051C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G051C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G051F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G051F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G051F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G051F8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G051F8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G051F8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G051G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G051G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G051G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G051G8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G051G8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G051G8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G051K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G051K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G051K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G051K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G051K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G051K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G061C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G061C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G061C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G061C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G061C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G061C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G061F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G061F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G061F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G061F8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G061F8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G061F8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G061G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G061G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G061G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G061G8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G061G8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G061G8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G061K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G061K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G061K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G061K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G061K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G061K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, + }, + }, + }; + + ret.STM32G070CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G070CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G070CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G070KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G070KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G070KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G070RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G070RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G070RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071EB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071EB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071EB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071G8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071G8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071G8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071GB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071GB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071GB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G071RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G071RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G071RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G081CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G081CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G081CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G081EB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G081EB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G081EB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G081GB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G081GB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G081GB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G081KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G081KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G081KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G081RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G081RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G081RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B0CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B0CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B0CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B0KE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B0KE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B0KE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B0RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B0RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B0RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B0VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B0VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B0VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1KC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1KC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1KC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1KE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1KE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1KE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1MB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1MB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1MB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1MC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1MC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1MC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1NE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1NE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1NE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0B1VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0B1VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0B1VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0C1CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0C1CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0C1CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0C1CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0C1CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0C1CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0C1KC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0C1KC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0C1KC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0C1KE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0C1KE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0C1KE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0C1MC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0C1MC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0C1MC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0C1ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0C1ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0C1ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0C1NE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0C1NE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0C1NE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0C1RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0C1RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0C1RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0C1RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0C1RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0C1RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0C1VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0C1VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0C1VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G0C1VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G0C1VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G0C1VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, + }, + }, + }; + + ret.STM32G431C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431M6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431M6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431M6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431M8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431M8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431M8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431MB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431MB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431MB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431V6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431V6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431V6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G431VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G431VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G431VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G441CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G441CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G441CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G441KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G441KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G441KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G441MB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G441MB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G441MB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G441RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G441RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G441RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G441VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G441VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G441VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, + .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32G471CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G471CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G471CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G471CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G471CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G471CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G471MC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G471MC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G471MC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G471ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G471ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G471ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G471QC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G471QC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G471QC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G471QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G471QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G471QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G471RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G471RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G471RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G471RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G471RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G471RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G471VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G471VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G471VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G471VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G471VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G471VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473MB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473MB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473MB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473MC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473MC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473MC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473PB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473PB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473PB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473PC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473PC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473PC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473PE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473PE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473PE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473QB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473QB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473QB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473QC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473QC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473QC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G473VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G473VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G473VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474MB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474MB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474MB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474MC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474MC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474MC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474PB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474PB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474PB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474PC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474PC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474PC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474PE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474PE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474PE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474QB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474QB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474QB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474QC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474QC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474QC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G474VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G474VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G474VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G483CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G483CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G483CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G483ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G483ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G483ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G483PE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G483PE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G483PE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G483QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G483QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G483QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G483RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G483RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G483RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G483VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G483VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G483VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G484CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G484CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G484CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G484ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G484ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G484ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G484PE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G484PE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G484PE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G484QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G484QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G484QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G484RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G484RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G484RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G484VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G484VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G484VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32G491CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G491CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G491CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G491CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G491CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G491CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G491KC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G491KC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G491KC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G491KE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G491KE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G491KE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G491MC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G491MC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G491MC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G491ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G491ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G491ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G491RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G491RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G491RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G491RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G491RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G491RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G491VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G491VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G491VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G491VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G491VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G491VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G4A1CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G4A1CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G4A1CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G4A1KE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G4A1KE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G4A1KE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G4A1ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G4A1ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G4A1ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G4A1RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G4A1RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G4A1RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32G4A1VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32G4A1VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32G4A1VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H503CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H503CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H503CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H503EB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H503EB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H503EB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H503KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H503KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H503KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H503RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H503RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H503RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H523CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H523CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H523CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H523CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H523CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H523CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H523HE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H523HE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H523HE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H523RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H523RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H523RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H523RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H523RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H523RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H523VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H523VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H523VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H523VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H523VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H523VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H523ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H523ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H523ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H523ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H523ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H523ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H533CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H533CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H533CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H533HE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H533HE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H533HE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H533RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H533RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H533RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H533VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H533VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H533VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H533ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H533ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H533ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, + .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H562AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H562AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H562AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H562AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H562AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H562AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H562IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H562IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H562IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H562II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H562II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H562II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H562RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H562RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H562RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H562RI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H562RI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H562RI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H562VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H562VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H562VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H562VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H562VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H562VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H562ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H562ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H562ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H562ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H562ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H562ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H563AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H563AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H563AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H563AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H563AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H563AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H563IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H563IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H563IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H563II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H563II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H563II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H563MI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H563MI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H563MI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H563RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H563RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H563RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H563RI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H563RI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H563RI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H563VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H563VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H563VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H563VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H563VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H563VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H563ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H563ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H563ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H563ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H563ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H563ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H573AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H573AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H573AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H573II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H573II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H573II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H573MI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H573MI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H573MI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H573RI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H573RI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H573RI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H573VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H573VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H573VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H573ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H573ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H573ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32H723VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H723VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H723VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H723VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H723VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H723VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H723ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H723ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H723ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H723ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H723ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H723ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H725AE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H725AE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H725AE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H725AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H725AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H725AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H725IE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H725IE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H725IE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H725IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H725IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H725IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H725RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H725RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H725RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H725RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H725RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H725RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H725VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H725VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H725VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H725VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H725VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H725VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H725ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H725ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H725ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H725ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H725ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H725ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H730AB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H730AB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H730AB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H730IB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H730IB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H730IB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H730VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H730VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H730VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H730ZB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H730ZB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H730ZB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H733VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H733VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H733VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H733ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H733ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H733ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H735AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H735AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H735AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H735IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H735IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H735IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H735RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H735RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H735RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H735VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H735VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H735VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H735ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H735ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H735ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H742AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H742AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H742AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H742AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H742AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H742AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H742BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H742BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H742BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H742BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H742BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H742BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H742IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H742IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H742IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H742II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H742II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H742II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H742VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H742VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H742VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H742VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H742VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H742VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H742XG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H742XG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H742XG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H742XI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H742XI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H742XI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H742ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H742ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H742ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H742ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H742ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H742ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H743AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H743AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H743AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H743AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H743AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H743AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H743BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H743BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H743BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H743BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H743BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H743BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H743IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H743IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H743IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H743II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H743II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H743II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H743VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H743VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H743VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H743VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H743VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H743VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H743XG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H743XG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H743XG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H743XI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H743XI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H743XI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H743ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H743ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H743ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H743ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H743ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H743ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H745BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H745BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H745BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H745BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H745BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H745BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H745IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H745IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H745IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H745II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H745II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H745II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H745XG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H745XG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H745XG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H745XI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H745XI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H745XI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H745ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H745ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H745ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H745ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H745ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H745ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H747AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H747AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H747AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H747AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H747AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H747AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H747BG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H747BG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H747BG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H747BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H747BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H747BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H747IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H747IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H747IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H747II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H747II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H747II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H747XG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H747XG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H747XG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H747XI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H747XI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H747XI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H747ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H747ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H747ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H750IB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H750IB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H750IB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H750VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H750VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H750VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H750XB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H750XB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H750XB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H750ZB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H750ZB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H750ZB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H753AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H753AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H753AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H753BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H753BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H753BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H753II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H753II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H753II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H753VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H753VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H753VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H753XI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H753XI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H753XI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H753ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H753ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H753ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32H755BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H755BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H755BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H755II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H755II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H755II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H755XI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H755XI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H755XI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H755ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H755ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H755ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H757AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H757AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H757AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H757BI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H757BI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H757BI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H757II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H757II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H757II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H757XI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H757XI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H757XI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H757ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H757ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H757ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, + .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3IG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3IG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3IG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3LG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3LG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3LG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3LI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3LI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3LI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3NG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3NG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3NG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3NI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3NI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3NI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3QI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3QI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3QI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3RI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3RI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3RI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7A3ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7A3ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7A3ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B0AB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B0AB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B0AB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B0IB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B0IB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B0IB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B0RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B0RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B0RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B0VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B0VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B0VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B0ZB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B0ZB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B0ZB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B3AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B3AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B3AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B3II = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B3II.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B3II", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B3LI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B3LI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B3LI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B3NI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B3NI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B3NI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B3QI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B3QI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B3QI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B3RI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B3RI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B3RI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B3VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B3VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B3VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7B3ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7B3ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7B3ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7R3A8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7R3A8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7R3A8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7R3I8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7R3I8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7R3I8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7R3L8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7R3L8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7R3L8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7R3R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7R3R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7R3R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7R3V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7R3V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7R3V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7R3Z8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7R3Z8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7R3Z8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7R7A8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7R7A8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7R7A8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7R7I8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7R7I8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7R7I8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7R7L8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7R7L8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7R7L8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7R7Z8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7R7Z8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7R7Z8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7S3A8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7S3A8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7S3A8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7S3I8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7S3I8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7S3I8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7S3L8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7S3L8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7S3L8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7S3R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7S3R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7S3R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7S3V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7S3V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7S3V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7S3Z8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7S3Z8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7S3Z8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7S7A8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7S7A8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7S7A8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7S7I8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7S7I8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7S7I8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7S7L8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7S7L8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7S7L8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32H7S7Z8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32H7S7Z8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32H7S7Z8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m7 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.fp_armv8d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, + .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L010C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L010C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L010C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L010F4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L010F4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L010F4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L010K4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L010K4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L010K4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L010K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L010K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L010K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L010R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L010R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L010R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L010RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L010RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L010RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L011D3 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L011D3.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L011D3", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x2000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L011D4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L011D4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L011D4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L011E3 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L011E3.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L011E3", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x2000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L011E4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L011E4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L011E4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L011F3 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L011F3.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L011F3", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x2000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L011F4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L011F4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L011F4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L011G3 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L011G3.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L011G3", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x2000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L011G4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L011G4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L011G4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L011K3 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L011K3.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L011K3", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x2000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L011K4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L011K4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L011K4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L021D4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L021D4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L021D4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L021F4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L021F4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L021F4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L021G4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L021G4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L021G4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L021K4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L021K4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L021K4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, + }, + }, + }; + + ret.STM32L031C4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L031C4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L031C4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L031C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L031C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L031C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L031E4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L031E4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L031E4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L031E6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L031E6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L031E6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L031F4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L031F4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L031F4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L031F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L031F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L031F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L031G4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L031G4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L031G4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L031G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L031G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L031G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L031K4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L031K4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L031K4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L031K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L031K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L031K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L041C4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L041C4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L041C4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L041C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L041C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L041C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L041E6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L041E6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L041E6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L041F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L041F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L041F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L041G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L041G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L041G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L041K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L041K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L041K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L051C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L051C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L051C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L051C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L051C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L051C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L051K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L051K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L051K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L051K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L051K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L051K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L051R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L051R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L051R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L051R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L051R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L051R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L051T6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L051T6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L051T6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L051T8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L051T8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L051T8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L052C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L052C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L052C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L052C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L052C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L052C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L052K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L052K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L052K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L052K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L052K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L052K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L052R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L052R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L052R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L052R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L052R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L052R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L052T6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L052T6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L052T6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L052T8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L052T8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L052T8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L053C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L053C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L053C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L053C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L053C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L053C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L053R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L053R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L053R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L053R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L053R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L053R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L062C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L062C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L062C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L062K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L062K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L062K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L063C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L063C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L063C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L063R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L063R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L063R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L071C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L071C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L071C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L071CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L071CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L071CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L071CZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L071CZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L071CZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L071K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L071K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L071K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L071KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L071KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L071KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L071KZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L071KZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L071KZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L071RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L071RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L071RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L071RZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L071RZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L071RZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L071V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L071V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L071V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L071VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L071VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L071VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L071VZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L071VZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L071VZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L072CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L072CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L072CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L072CZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L072CZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L072CZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L072KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L072KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L072KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L072KZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L072KZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L072KZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L072RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L072RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L072RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L072RZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L072RZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L072RZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L072V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L072V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L072V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L072VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L072VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L072VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L072VZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L072VZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L072VZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L073CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L073CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L073CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L073CZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L073CZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L073CZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L073RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L073RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L073RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L073RZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L073RZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L073RZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L073V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L073V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L073V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L073VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L073VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L073VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L073VZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L073VZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L073VZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L081CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L081CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L081CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L081CZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L081CZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L081CZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L081KZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L081KZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L081KZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L082CZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L082CZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L082CZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L082KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L082KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L082KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L082KZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L082KZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L082KZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L083CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L083CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L083CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L083CZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L083CZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L083CZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L083RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L083RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L083RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L083RZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L083RZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L083RZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L083V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L083V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L083V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L083VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L083VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L083VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L083VZ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L083VZ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L083VZ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, + }, + }, + }; + + ret.STM32L100C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L100C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L100C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L100C6-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L100C6-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L100C6-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32L100R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L100R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L100R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L100R8-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L100R8-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L100R8-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L100RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L100RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L100RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L100RB-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L100RB-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L100RB-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L100RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L100RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L100RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L151C6-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L151C6-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151C6-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L151C8-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L151C8-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151C8-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L151CB-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L151CB-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151CB-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151QC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151QC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151QC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151QD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151QD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151QD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L151R6-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L151R6-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151R6-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L151R8-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L151R8-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151R8-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L151RB-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L151RB-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151RB-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L151RC-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L151RC-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151RC-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151RD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151RD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151RD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151UC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151UC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151UC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L151V8-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L151V8-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151V8-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L151VB-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L151VB-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151VB-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L151VC-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L151VC-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151VC-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151VD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151VD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151VD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L151VD-X" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L151VD-X".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151VD-X", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151ZD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151ZD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151ZD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32L151ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L151ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L151ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L152C6-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L152C6-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152C6-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L152C8-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L152C8-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152C8-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L152CB-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L152CB-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152CB-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152QC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152QC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152QC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152QD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152QD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152QD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L152R6-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L152R6-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152R6-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L152R8-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L152R8-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152R8-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L152RB-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L152RB-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152RB-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L152RC-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L152RC-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152RC-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152RD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152RD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152RD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152UC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152UC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152UC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152V8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152V8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152V8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L152V8-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L152V8-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152V8-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152VB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152VB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152VB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L152VB-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L152VB-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152VB-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L152VC-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L152VC-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152VC-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152VD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152VD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152VD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L152VD-X" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L152VD-X".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152VD-X", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152ZD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152ZD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152ZD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32L152ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L152ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L152ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L162QC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L162QC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162QC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L162QD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L162QD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162QD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32L162RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L162RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L162RC-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L162RC-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162RC-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L162RD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L162RD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162RD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32L162RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L162RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L162VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L162VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L162VC-A" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L162VC-A".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162VC-A", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L162VD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L162VD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162VD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.@"STM32L162VD-X" = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.@"STM32L162VD-X".* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162VD-X", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L162VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L162VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L162ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L162ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L162ZD = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L162ZD.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162ZD", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + }, + }, + }; + + ret.STM32L162ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L162ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L162ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, + }, + }, + }; + + ret.STM32L412C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L412C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L412C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L412CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L412CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L412CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L412K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L412K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L412K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L412KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L412KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L412KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L412R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L412R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L412R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L412RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L412RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L412RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L412T8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L412T8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L412T8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L412TB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L412TB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L412TB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L422CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L422CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L422CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L422KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L422KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L422KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L422RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L422RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L422RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L422TB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L422TB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L422TB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, + }, + }, + }; + + ret.STM32L431CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L431CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L431CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L431CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L431CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L431CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L431KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L431KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L431KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L431KC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L431KC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L431KC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L431RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L431RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L431RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L431RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L431RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L431RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L431VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L431VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L431VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L432KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L432KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L432KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L432KC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L432KC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L432KC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L433CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L433CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L433CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L433CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L433CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L433CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L433RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L433RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L433RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L433RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L433RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L433RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L433VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L433VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L433VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L442KC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L442KC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L442KC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L443CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L443CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L443CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L443RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L443RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L443RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L443VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L443VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L443VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, + .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, + }, + }, + }; + + ret.STM32L451CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L451CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L451CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L451CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L451CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L451CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L451RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L451RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L451RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L451RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L451RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L451RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L451VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L451VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L451VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L451VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L451VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L451VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L452CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L452CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L452CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L452CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L452CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L452CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L452RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L452RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L452RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L452RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L452RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L452RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L452VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L452VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L452VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L452VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L452VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L452VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L462CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L462CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L462CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L462RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L462RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L462RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L462VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L462VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L462VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32L471QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L471QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L471QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L471QG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L471QG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L471QG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L471RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L471RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L471RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L471RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L471RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L471RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L471VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L471VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L471VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L471VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L471VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L471VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L471ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L471ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L471ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L471ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L471ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L471ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L475RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L475RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L475RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L475RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L475RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L475RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L475RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L475RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L475RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L475VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L475VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L475VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L475VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L475VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L475VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L475VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L475VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L475VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476JE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476JE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476JE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476JG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476JG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476JG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476MG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476MG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476MG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476QG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476QG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476QG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L476ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L476ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L476ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L486JG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L486JG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L486JG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L486QG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L486QG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L486QG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L486RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L486RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L486RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L486VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L486VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L486VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L486ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L486ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L486ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32L496AE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L496AE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L496AE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L496AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L496AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L496AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L496QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L496QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L496QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L496QG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L496QG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L496QG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L496RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L496RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L496RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L496RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L496RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L496RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L496VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L496VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L496VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L496VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L496VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L496VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L496WG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L496WG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L496WG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L496ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L496ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L496ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L496ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L496ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L496ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4A6AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4A6AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4A6AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4A6QG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4A6QG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4A6QG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4A6RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4A6RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4A6RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4A6VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4A6VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4A6VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4A6ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4A6ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4A6ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4P5AE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4P5AE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4P5AE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4P5AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4P5AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4P5AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4P5CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4P5CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4P5CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4P5CG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4P5CG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4P5CG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4P5QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4P5QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4P5QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4P5QG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4P5QG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4P5QG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4P5RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4P5RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4P5RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4P5RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4P5RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4P5RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4P5VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4P5VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4P5VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4P5VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4P5VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4P5VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4P5ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4P5ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4P5ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4P5ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4P5ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4P5ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4Q5AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4Q5AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4Q5AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4Q5CG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4Q5CG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4Q5CG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4Q5QG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4Q5QG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4Q5QG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4Q5RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4Q5RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4Q5RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4Q5VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4Q5VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4Q5VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4Q5ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4Q5ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4Q5ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R5AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R5AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R5AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R5AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R5AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R5AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R5QG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R5QG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R5QG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R5QI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R5QI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R5QI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R5VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R5VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R5VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R5VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R5VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R5VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R5ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R5ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R5ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R5ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R5ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R5ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R7AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R7AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R7AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R7VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R7VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R7VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R7ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R7ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R7ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R9AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R9AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R9AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R9AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R9AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R9AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R9VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R9VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R9VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R9VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R9VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R9VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R9ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R9ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R9ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4R9ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4R9ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4R9ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4S5AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4S5AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4S5AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4S5QI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4S5QI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4S5QI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4S5VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4S5VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4S5VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4S5ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4S5ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4S5ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4S7AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4S7AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4S7AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4S7VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4S7VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4S7VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4S7ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4S7ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4S7ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4S9AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4S9AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4S9AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4S9VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4S9VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4S9VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L4S9ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L4S9ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L4S9ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, + }, + }, + }; + + ret.STM32L552CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L552CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L552CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L552CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L552CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L552CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L552ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L552ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L552ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L552QC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L552QC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L552QC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L552QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L552QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L552QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L552RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L552RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L552RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L552RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L552RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L552RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L552VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L552VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L552VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L552VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L552VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L552VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L552ZC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L552ZC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L552ZC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L552ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L552ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L552ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L562CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L562CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L562CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L562ME = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L562ME.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L562ME", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L562QE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L562QE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L562QE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L562RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L562RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L562RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L562VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L562VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L562VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32L562ZE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32L562ZE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32L562ZE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, + }, + }, + }; + + ret.STM32U031C6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U031C6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U031C6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32U031C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U031C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U031C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32U031F4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U031F4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U031F4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32U031F6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U031F6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U031F6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32U031F8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U031F8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U031F8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32U031G6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U031G6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U031G6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32U031G8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U031G8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U031G8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32U031K4 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U031K4.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U031K4", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32U031K6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U031K6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U031K6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32U031K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U031K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U031K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32U031R6 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U031R6.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U031R6", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32U031R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U031R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U031R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073H8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073H8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073H8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073HB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073HB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073HB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073HC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073HC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073HC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073K8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073K8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073K8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073KB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073KB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073KB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073KC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073KC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073KC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073M8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073M8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073M8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073MB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073MB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073MB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073MC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073MC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073MC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073R8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073R8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073R8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U073RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U073RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U073RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U083CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U083CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U083CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U083HC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U083HC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U083HC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U083KC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U083KC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U083KC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U083MC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U083MC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U083MC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U083RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U083RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U083RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, + }, + }, + }; + + ret.STM32U535CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U535CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U535CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U535CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U535CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U535CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U535CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U535CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U535CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U535JE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U535JE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U535JE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U535NC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U535NC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U535NC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U535NE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U535NE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U535NE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U535RB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U535RB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U535RB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U535RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U535RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U535RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U535RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U535RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U535RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U535VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U535VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U535VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U535VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U535VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U535VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U545CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U545CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U545CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U545JE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U545JE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U545JE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U545NE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U545NE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U545NE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U545RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U545RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U545RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U545VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U545VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U545VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575AG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575AG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575AG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575CG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575CG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575CG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575CI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575CI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575CI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575OG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575OG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575OG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575OI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575OI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575OI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575QG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575QG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575QG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575QI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575QI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575QI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575RI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575RI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575RI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575ZG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575ZG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575ZG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U575ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U575ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U575ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U585AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U585AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U585AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U585CI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U585CI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U585CI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U585OI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U585OI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U585OI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U585QI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U585QI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U585QI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U585RI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U585RI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U585RI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U585VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U585VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U585VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U585ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U585ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U585ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U595AI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U595AI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U595AI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U595AJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U595AJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U595AJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U595QI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U595QI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U595QI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U595QJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U595QJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U595QJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U595RI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U595RI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U595RI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U595RJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U595RJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U595RJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U595VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U595VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U595VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U595VJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U595VJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U595VJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U595ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U595ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U595ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U595ZJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U595ZJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U595ZJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U599BJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U599BJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U599BJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U599NI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U599NI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U599NI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U599NJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U599NJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U599NJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U599VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U599VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U599VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U599VJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U599VJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U599VJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U599ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U599ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U599ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U599ZJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U599ZJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U599ZJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5A5AJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5A5AJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5A5AJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5A5QI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5A5QI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5A5QI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5A5QJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5A5QJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5A5QJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5A5RJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5A5RJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5A5RJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5A5VJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5A5VJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5A5VJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5A5ZJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5A5ZJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5A5ZJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5A9BJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5A9BJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5A9BJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5A9NJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5A9NJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5A9NJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5A9VJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5A9VJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5A9VJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5A9ZJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5A9ZJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5A9ZJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5F7VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5F7VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5F7VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5F7VJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5F7VJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5F7VJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5F9BJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5F9BJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5F9BJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5F9NJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5F9NJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5F9NJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5F9VI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5F9VI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5F9VI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5F9VJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5F9VJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5F9VJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5F9ZI = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5F9ZI.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5F9ZI", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5F9ZJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5F9ZJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5F9ZJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5G7VJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5G7VJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5G7VJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5G9BJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5G9BJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5G9BJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5G9NJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5G9NJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5G9NJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5G9VJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5G9VJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5G9VJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32U5G9ZJ = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32U5G9ZJ.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32U5G9ZJ", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, + .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, + .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB10CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB10CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB10CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x50000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB15CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB15CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB15CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x50000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x1000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x1000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB30CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB30CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB30CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB35CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB35CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB35CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB35CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB35CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB35CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB50CG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB50CG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB50CG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB55CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB55CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB55CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB55CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB55CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB55CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB55CG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB55CG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB55CG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB55RC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB55RC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB55RC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB55RE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB55RE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB55RE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB55RG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB55RG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB55RG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB55VC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB55VC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB55VC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB55VE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB55VE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB55VE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB55VG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB55VG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB55VG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WB55VY = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WB55VY.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WB55VY", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0xA0000, .kind = .flash }, + .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, + .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA50KE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA50KE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA50KE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA50KG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA50KG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA50KG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA52CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA52CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA52CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA52CG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA52CG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA52CG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA52KE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA52KE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA52KE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA52KG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA52KG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA52KG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA54CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA54CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA54CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA54CG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA54CG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA54CG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA54KE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA54KE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA54KE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA54KG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA54KG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA54KG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA55CE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA55CE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA55CE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA55CG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA55CG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA55CG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA55HE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA55HE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA55HE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA55HG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA55HG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA55HG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA55UE = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA55UE.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA55UE", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, + }, + }, + }; + + ret.STM32WBA55UG = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WBA55UG.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WBA55UG", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 }, + .os_tag = .freestanding, + .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}), + .abi = .eabihf, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, + }, + }, + }; + + ret.STM32WL54CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WL54CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WL54CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WL54JC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WL54JC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WL54JC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WL55CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WL55CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WL55CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WL55JC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WL55JC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WL55JC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WLE4C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WLE4C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WLE4C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20002800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32WLE4CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WLE4CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WLE4CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, + .{ .offset = 0x20006000, .length = 0x6000, .kind = .ram }, + }, + }, + }; + + ret.STM32WLE4CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WLE4CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WLE4CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WLE4J8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WLE4J8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WLE4J8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20002800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32WLE4JB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WLE4JB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WLE4JB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, + .{ .offset = 0x20006000, .length = 0x6000, .kind = .ram }, + }, + }, + }; + + ret.STM32WLE4JC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WLE4JC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WLE4JC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WLE5C8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WLE5C8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WLE5C8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20002800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32WLE5CB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WLE5CB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WLE5CB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, + .{ .offset = 0x20006000, .length = 0x6000, .kind = .ram }, + }, + }, + }; + + ret.STM32WLE5CC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WLE5CC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WLE5CC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + ret.STM32WLE5J8 = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WLE5J8.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WLE5J8", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, + .{ .offset = 0x20002800, .length = 0x2800, .kind = .ram }, + }, + }, + }; + + ret.STM32WLE5JB = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WLE5JB.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WLE5JB", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, + .{ .offset = 0x20006000, .length = 0x6000, .kind = .ram }, + }, + }, + }; + + ret.STM32WLE5JC = b.allocator.create(microzig.Target) catch @panic("out of memory"); + ret.STM32WLE5JC.* = .{ + .dep = dep, + .preferred_binary_format = .elf, + .chip = .{ + .name = "STM32WLE5JC", + .cpu = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .register_definition = .{ + .zig = register_definition_path, + }, + .memory_regions = &.{ + .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, + .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, + .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, + }, + }, + }; + + return ret; +} diff --git a/port/stmicro/stm32/src/chips.zig b/port/stmicro/stm32/src/chips.zig deleted file mode 100644 index 3295aea0..00000000 --- a/port/stmicro/stm32/src/chips.zig +++ /dev/null @@ -1,23618 +0,0 @@ -const std = @import("std"); -const MicroZig = @import("microzig/build"); - -fn root() []const u8 { - return comptime (std.fs.path.dirname(@src().file) orelse "."); -} -const build_root = root(); -pub const register_definition_path = build_root ++ "/chips/all.zig"; - -pub const STM32C011D6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C011D6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32C011F4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C011F4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32C011F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C011F6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32C011J4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C011J4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32C011J6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C011J6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32C031C4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C031C4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32C031C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C031C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32C031F4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C031F4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32C031F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C031F6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32C031G4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C031G4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32C031G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C031G6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32C031K4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C031K4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32C031K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32C031K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F030C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F030C6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F030C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F030C8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F030CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F030CC", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F030F4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F030F4", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F030K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F030K6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F030R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F030R8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F030RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F030RC", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F031C4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F031C4", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F031C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F031C6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F031E6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F031E6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F031F4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F031F4", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F031F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F031F6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F031G4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F031G4", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F031G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F031G6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F031K4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F031K4", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F031K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F031K6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F038C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F038C6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F038E6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F038E6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F038F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F038F6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F038G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F038G6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F038K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F038K6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F042C4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F042C4", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F042C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F042C6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F042F4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F042F4", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F042F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F042F6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F042G4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F042G4", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F042G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F042G6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F042K4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F042K4", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F042K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F042K6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F042T6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F042T6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F048C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F048C6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F048G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F048G6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F048T6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F048T6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F051C4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F051C4", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F051C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F051C6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F051C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F051C8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F051K4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F051K4", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F051K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F051K6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F051K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F051K8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F051R4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F051R4", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F051R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F051R6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F051R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F051R8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F051T8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F051T8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F058C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F058C8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F058R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F058R8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F058T8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F058T8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F070C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F070C6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F070CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F070CB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F070F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F070F6", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F070RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F070RB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F071C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F071C8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F071CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F071CB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F071RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F071RB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F071V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F071V8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F071VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F071VB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F072C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F072C8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F072CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F072CB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F072R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F072R8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F072RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F072RB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F072V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F072V8", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F072VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F072VB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F078CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F078CB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F078RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F078RB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F078VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F078VB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F091CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F091CB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F091CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F091CC", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F091RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F091RB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F091RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F091RC", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F091VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F091VB", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F091VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F091VC", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F098CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F098CC", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F098RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F098RC", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F098VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F098VC", - .cpu = MicroZig.cpus.cortex_m0, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100C4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100C4", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100C6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100C8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100CB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100R4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100R4", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100R6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100R8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100RB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100RC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100RD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100RD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100RE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100V8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100VB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100VC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100VD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100VD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100VE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100ZC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100ZD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100ZD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F100ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F100ZE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101C4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101C4", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101C6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101C8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101CB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101R4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101R4", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101R6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101R8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101RB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101RC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101RD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101RD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101RE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101RF = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101RF", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101RG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101T4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101T4", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101T6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101T6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101T8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101T8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101TB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101TB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101V8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101VB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101VC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101VD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101VD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101VE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101VF = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101VF", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101VG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101ZC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101ZD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101ZD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101ZE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101ZF = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101ZF", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F101ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F101ZG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F102C4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F102C4", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F102C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F102C6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F102C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F102C8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F102CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F102CB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F102R4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F102R4", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F102R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F102R6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F102R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F102R8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F102RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F102RB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F103C4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103C4", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103C6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103C8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103CB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103R4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103R4", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103R6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103R8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103RB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103RC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103RD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103RD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103RE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103RF = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103RF", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103RG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103T4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103T4", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103T6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103T6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103T8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103T8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103TB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103TB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103V8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103VB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103VC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103VD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103VD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103VE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103VF = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103VF", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103VG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103ZC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103ZD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103ZD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103ZE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103ZF = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103ZF", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F103ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F103ZG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, - .hal = .{ - .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - }, -}; - -pub const STM32F105R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F105R8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F105RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F105RB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F105RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F105RC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F105V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F105V8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F105VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F105VB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F105VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F105VC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F107RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F107RB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F107RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F107RC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F107VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F107VB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F107VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F107VC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205RB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205RC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205RE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205RF = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205RF", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xA0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205RG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205VB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205VC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205VE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205VF = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205VF", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xA0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205VG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205ZC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205ZE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205ZF = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205ZF", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xA0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F205ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F205ZG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F207IC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F207IC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F207IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F207IE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F207IF = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F207IF", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xA0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F207IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F207IG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F207VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F207VC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F207VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F207VE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F207VF = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F207VF", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xA0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F207VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F207VG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F207ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F207ZC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F207ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F207ZE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F207ZF = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F207ZF", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xA0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F207ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F207ZG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F215RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F215RE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F215RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F215RG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F215VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F215VE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F215VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F215VG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F215ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F215ZE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F215ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F215ZG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F217IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F217IE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F217IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F217IG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F217VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F217VE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F217VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F217VG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F217ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F217ZE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F217ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F217ZG", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F301C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F301C6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F301C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F301C8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F301K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F301K6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F301K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F301K8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F301R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F301R6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F301R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F301R8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302C6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302C8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302K6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302K8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302R6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302R8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302RD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302RD", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302VB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302VD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302VD", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302ZD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302ZD", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F302ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F302ZE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303C6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303C8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303K6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303K8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303R6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303R8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303RD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303RD", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303VB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303VD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303VD", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303ZD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303ZD", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F303ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F303ZE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F318C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F318C8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F318K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F318K8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F328C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F328C8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F334C4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F334C4", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F334C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F334C6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F334C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F334C8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F334K4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F334K4", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F334K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F334K6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F334K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F334K8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F334R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F334R6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F334R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F334R8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F358CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F358CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F358RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F358RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F358VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F358VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F373C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F373C8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F373CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F373CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F373CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F373CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F373R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F373R8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F373RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F373RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F373RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F373RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F373V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F373V8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F373VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F373VB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F373VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F373VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F378CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F378CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F378RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F378RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F378VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F378VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F398VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F398VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F401CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F401CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F401CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F401CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F401CD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F401CD", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F401CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F401CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F401RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F401RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F401RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F401RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F401RD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F401RD", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F401RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F401RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F401VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F401VB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F401VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F401VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F401VD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F401VD", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F401VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F401VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F405OE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F405OE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F405OG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F405OG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F405RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F405RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F405VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F405VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F405ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F405ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F407IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F407IE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F407IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F407IG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F407VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F407VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F407VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F407VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F407ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F407ZE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F407ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F407ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x1C000, .kind = .ram }, - .{ .offset = 0x2001C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F410C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F410C8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F410CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F410CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F410R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F410R8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F410RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F410RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F410T8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F410T8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F410TB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F410TB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F411CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F411CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F411CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F411CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F411RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F411RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F411RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F411RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F411VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F411VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F411VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F411VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F412CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F412CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F412CG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F412CG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F412RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F412RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F412RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F412RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F412VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F412VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F412VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F412VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F412ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F412ZE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F412ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F412ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F413CG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F413CG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F413CH = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F413CH", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F413MG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F413MG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F413MH = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F413MH", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F413RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F413RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F413RH = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F413RH", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F413VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F413VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F413VH = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F413VH", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F413ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F413ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F413ZH = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F413ZH", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F415OG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F415OG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F415RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F415RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F415VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F415VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F415ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F415ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F417IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F417IE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F417IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F417IG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F417VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F417VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F417VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F417VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F417ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F417ZE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F417ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F417ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F423CH = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F423CH", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F423MH = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F423MH", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F423RH = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F423RH", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F423VH = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F423VH", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F423ZH = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F423ZH", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x160000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F427AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F427AG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F427AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F427AI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F427IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F427IG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F427II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F427II", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F427VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F427VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F427VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F427VI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F427ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F427ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F427ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F427ZI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429AG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429AI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429BE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429BE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429BG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429BI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429IE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429IG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429II", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429NE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429NE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429NG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429NG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429NI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429NI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429VI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429ZE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F429ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F429ZI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F437AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F437AI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F437IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F437IG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F437II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F437II", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F437VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F437VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F437VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F437VI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F437ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F437ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F437ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F437ZI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F439AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F439AI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F439BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F439BG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F439BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F439BI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F439IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F439IG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F439II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F439II", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F439NG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F439NG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F439NI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F439NI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F439VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F439VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F439VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F439VI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F439ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F439ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F439ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F439ZI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F446MC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F446MC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F446ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F446ME", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F446RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F446RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F446RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F446RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F446VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F446VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F446VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F446VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F446ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F446ZC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F446ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F446ZE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469AE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469AE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469AG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469AI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469BE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469BE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469BG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469BI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469IE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469IG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469II", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469NE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469NE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469NG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469NG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469NI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469NI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469VI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469ZE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F469ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F469ZI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F479AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F479AG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F479AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F479AI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F479BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F479BG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F479BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F479BI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F479IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F479IG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F479II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F479II", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F479NG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F479NG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F479NI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F479NI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F479VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F479VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F479VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F479VI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F479ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F479ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F479ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F479ZI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8110000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8120000, .length = 0xE0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F722IC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F722IC", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F722IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F722IE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F722RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F722RC", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F722RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F722RE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F722VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F722VC", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F722VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F722VE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F722ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F722ZC", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F722ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F722ZE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F723IC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F723IC", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F723IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F723IE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F723VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F723VC", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F723VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F723VE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F723ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F723ZC", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F723ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F723ZE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F730I8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F730I8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F730R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F730R8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F730V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F730V8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F730Z8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F730Z8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F732IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F732IE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F732RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F732RE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F732VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F732VE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F732ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F732ZE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F733IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F733IE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F733VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F733VE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F733ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F733ZE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x60000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x30000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F745IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F745IE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F745IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F745IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F745VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F745VE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F745VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F745VG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F745ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F745ZE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F745ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F745ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F746BE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F746BE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F746BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F746BG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F746IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F746IE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F746IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F746IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F746NE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F746NE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F746NG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F746NG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F746VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F746VE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F746VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F746VG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F746ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F746ZE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F746ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F746ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F750N8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F750N8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F750V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F750V8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F750Z8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F750Z8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F756BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F756BG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F756IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F756IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F756NG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F756NG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F756VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F756VG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F756ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F756ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20010000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F765BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F765BG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F765BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F765BI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F765IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F765IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F765II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F765II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F765NG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F765NG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F765NI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F765NI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F765VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F765VG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F765VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F765VI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F765ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F765ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F765ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F765ZI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F767BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F767BG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F767BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F767BI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F767IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F767IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F767II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F767II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F767NG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F767NG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F767NI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F767NI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F767VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F767VG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F767VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F767VI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F767ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F767ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F767ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F767ZI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F768AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F768AI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F769AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F769AG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F769AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F769AI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F769BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F769BG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F769BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F769BI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F769IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F769IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F769II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F769II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F769NG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F769NG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0xC0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F769NI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F769NI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F777BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F777BI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F777II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F777II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F777NI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F777NI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F777VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F777VI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F777ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F777ZI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F778AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F778AI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F779AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F779AI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F779BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F779BI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F779II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F779II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32F779NI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32F779NI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x1C0000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x60000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G030C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G030C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G030C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G030C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G030F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G030F6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G030J6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G030J6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G030K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G030K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G030K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G030K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031C4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031C4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031F4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031F4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031F6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031F8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031F8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031G4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031G4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031G6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031G8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031G8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031J4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031J4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031J6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031J6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031K4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031K4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G031Y8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G031Y8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G041C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G041C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G041C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G041C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G041F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G041F6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G041F8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G041F8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G041G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G041G6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G041G8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G041G8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G041J6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G041J6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G041K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G041K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G041K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G041K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G041Y8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G041Y8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G050C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G050C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G050C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G050C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G050F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G050F6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G050K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G050K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G050K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G050K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G051C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G051C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G051C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G051C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G051F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G051F6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G051F8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G051F8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G051G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G051G6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G051G8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G051G8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G051K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G051K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G051K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G051K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G061C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G061C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G061C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G061C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G061F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G061F6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G061F8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G061F8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G061G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G061G6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G061G8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G061G8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G061K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G061K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G061K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G061K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G070CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G070CB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G070KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G070KB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G070RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G070RB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071CB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071EB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071EB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071G6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071G8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071G8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071GB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071GB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071KB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071R6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071R8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G071RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G071RB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G081CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G081CB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G081EB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G081EB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G081GB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G081GB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G081KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G081KB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G081RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G081RB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x9000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B0CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B0CE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B0KE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B0KE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B0RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B0RE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B0VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B0VE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1CB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1CC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1CE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1KB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1KC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1KC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1KE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1KE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1MB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1MB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1MC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1MC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1ME", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1NE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1NE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1RB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1RC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1RE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1VB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1VC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0B1VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0B1VE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0C1CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0C1CC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0C1CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0C1CE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0C1KC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0C1KC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0C1KE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0C1KE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0C1MC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0C1MC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0C1ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0C1ME", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0C1NE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0C1NE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0C1RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0C1RC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0C1RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0C1RE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0C1VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0C1VC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G0C1VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G0C1VE", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x24000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431C6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431C8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431K6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431K8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431KB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431M6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431M6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431M8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431M8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431MB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431MB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431R6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431R8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431V6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431V6", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431V8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G431VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G431VB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G441CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G441CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G441KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G441KB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G441MB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G441MB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G441RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G441RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G441VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G441VB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x1800, .kind = .ram }, - .{ .offset = 0x20005800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G471CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G471CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G471CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G471CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G471MC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G471MC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G471ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G471ME", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G471QC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G471QC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G471QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G471QE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G471RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G471RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G471RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G471RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G471VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G471VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G471VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G471VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473MB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473MB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473MC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473MC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473ME", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473PB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473PB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473PC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473PC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473PE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473PE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473QB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473QB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473QC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473QC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473QE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473VB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G473VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G473VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474MB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474MB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474MC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474MC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474ME", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474PB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474PB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474PC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474PC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474PE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474PE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474QB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474QB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474QC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474QC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474QE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474VB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G474VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G474VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G483CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G483CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G483ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G483ME", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G483PE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G483PE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G483QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G483QE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G483RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G483RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G483VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G483VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G484CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G484CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G484ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G484ME", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G484PE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G484PE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G484QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G484QE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G484RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G484RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G484VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G484VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G491CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G491CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G491CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G491CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G491KC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G491KC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G491KE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G491KE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G491MC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G491MC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G491ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G491ME", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G491RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G491RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G491RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G491RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G491VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G491VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G491VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G491VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G4A1CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G4A1CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G4A1KE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G4A1KE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G4A1ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G4A1ME", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G4A1RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G4A1RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32G4A1VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32G4A1VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20014000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20018000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H503CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H503CB", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H503EB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H503EB", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H503KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H503KB", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H503RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H503RB", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H523CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H523CC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H523CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H523CE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H523HE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H523HE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H523RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H523RC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H523RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H523RE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H523VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H523VC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H523VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H523VE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H523ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H523ZC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H523ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H523ZE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H533CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H533CE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H533HE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H533HE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H533RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H533RE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H533VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H533VE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H533ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H533ZE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x14000, .kind = .ram }, - .{ .offset = 0x20034000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H562AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H562AG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H562AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H562AI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H562IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H562IG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H562II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H562II", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H562RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H562RG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H562RI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H562RI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H562VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H562VG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H562VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H562VI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H562ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H562ZG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H562ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H562ZI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H563AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H563AG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H563AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H563AI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H563IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H563IG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H563II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H563II", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H563MI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H563MI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H563RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H563RG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H563RI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H563RI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H563VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H563VG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H563VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H563VI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H563ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H563ZG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H563ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H563ZI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H573AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H573AI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H573II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H573II", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H573MI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H573MI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H573RI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H573RI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H573VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H573VI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H573ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H573ZI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20050000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H723VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H723VE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H723VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H723VG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H723ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H723ZE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H723ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H723ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H725AE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H725AE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H725AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H725AG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H725IE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H725IE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H725IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H725IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H725RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H725RE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H725RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H725RG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H725VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H725VE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H725VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H725VG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H725ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H725ZE", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H725ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H725ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H730AB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H730AB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H730IB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H730IB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H730VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H730VB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H730ZB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H730ZB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H733VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H733VG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H733ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H733ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H735AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H735AG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H735IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H735IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H735RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H735RG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H735VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H735VG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H735ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H735ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x50000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H742AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H742AG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H742AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H742AI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H742BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H742BG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H742BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H742BI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H742IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H742IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H742II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H742II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H742VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H742VG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H742VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H742VI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H742XG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H742XG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H742XI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H742XI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H742ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H742ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H742ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H742ZI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x60000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x30020000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H743AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H743AG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H743AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H743AI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H743BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H743BG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H743BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H743BI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H743IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H743IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H743II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H743II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H743VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H743VG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H743VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H743VI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H743XG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H743XG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H743XI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H743XI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H743ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H743ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H743ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H743ZI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H745BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H745BG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H745BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H745BI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H745IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H745IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H745II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H745II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H745XG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H745XG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H745XI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H745XI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H745ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H745ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H745ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H745ZI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H747AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H747AG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H747AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H747AI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H747BG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H747BG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H747BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H747BI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H747IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H747IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H747II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H747II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H747XG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H747XG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H747XI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H747XI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H747ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H747ZI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H750IB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H750IB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H750VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H750VB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H750XB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H750XB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H750ZB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H750ZB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H753AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H753AI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H753BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H753BI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H753II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H753II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H753VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H753VI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H753XI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H753XI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H753ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H753ZI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x38000000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H755BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H755BI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H755II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H755II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H755XI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H755XI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H755ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H755ZI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H757AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H757AI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H757BI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H757BI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H757II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H757II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H757XI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H757XI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H757ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H757ZI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x48000, .kind = .ram }, - .{ .offset = 0x18000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3AG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3AI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3IG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3IG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3LG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3LG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3LI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3LI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3NG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3NG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3NI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3NI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3QI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3QI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3RG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3RI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3RI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3VG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3VI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3ZG", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7A3ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7A3ZI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B0AB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B0AB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B0IB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B0IB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B0RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B0RB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B0VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B0VB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B0ZB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B0ZB", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B3AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B3AI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B3II = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B3II", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B3LI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B3LI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B3NI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B3NI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B3QI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B3QI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B3RI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B3RI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B3VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B3VI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7B3ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7B3ZI", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x100000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7R3A8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7R3A8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7R3I8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7R3I8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7R3L8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7R3L8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7R3R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7R3R8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7R3V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7R3V8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7R3Z8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7R3Z8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7R7A8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7R7A8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7R7I8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7R7I8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7R7L8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7R7L8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7R7Z8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7R7Z8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7S3A8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7S3A8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7S3I8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7S3I8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7S3L8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7S3L8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7S3R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7S3R8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7S3V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7S3V8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7S3Z8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7S3Z8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7S7A8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7S7A8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7S7I8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7S7I8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7S7L8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7S7L8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32H7S7Z8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32H7S7Z8", - .cpu = MicroZig.cpus.cortex_m7f, - .memory_regions = &.{ - .{ .offset = 0x0, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x24000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24020000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24040000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x24060000, .length = 0x12000, .kind = .ram }, - .{ .offset = 0x30000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x30004000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L010C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L010C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L010F4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L010F4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L010K4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L010K4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L010K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L010K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L010R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L010R8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L010RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L010RB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L011D3 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L011D3", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x2000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L011D4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L011D4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L011E3 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L011E3", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x2000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L011E4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L011E4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L011F3 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L011F3", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x2000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L011F4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L011F4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L011G3 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L011G3", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x2000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L011G4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L011G4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L011K3 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L011K3", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x2000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L011K4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L011K4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L021D4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L021D4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L021F4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L021F4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L021G4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L021G4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L021K4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L021K4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L031C4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L031C4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L031C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L031C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L031E4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L031E4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L031E6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L031E6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L031F4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L031F4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L031F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L031F6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L031G4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L031G4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L031G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L031G6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L031K4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L031K4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L031K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L031K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L041C4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L041C4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L041C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L041C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L041E6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L041E6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L041F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L041F6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L041G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L041G6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L041K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L041K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L051C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L051C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L051C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L051C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L051K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L051K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L051K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L051K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L051R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L051R6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L051R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L051R8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L051T6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L051T6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L051T8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L051T8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L052C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L052C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L052C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L052C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L052K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L052K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L052K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L052K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L052R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L052R6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L052R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L052R8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L052T6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L052T6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L052T8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L052T8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L053C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L053C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L053C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L053C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L053R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L053R6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L053R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L053R8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L062C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L062C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L062K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L062K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L063C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L063C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L063R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L063R8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L071C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L071C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L071CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L071CB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L071CZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L071CZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L071K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L071K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L071KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L071KB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L071KZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L071KZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L071RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L071RB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L071RZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L071RZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L071V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L071V8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L071VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L071VB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L071VZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L071VZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L072CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L072CB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L072CZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L072CZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L072KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L072KB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L072KZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L072KZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L072RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L072RB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L072RZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L072RZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L072V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L072V8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L072VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L072VB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L072VZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L072VZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L073CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L073CB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L073CZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L073CZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L073RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L073RB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L073RZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L073RZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L073V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L073V8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L073VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L073VB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L073VZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L073VZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L081CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L081CB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L081CZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L081CZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L081KZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L081KZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L082CZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L082CZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L082KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L082KB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L082KZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L082KZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L083CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L083CB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L083CZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L083CZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L083RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L083RB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L083RZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L083RZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L083V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L083V8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L083VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L083VB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L083VZ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L083VZ", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x5000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L100C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L100C6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L100C6-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L100C6-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L100R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L100R8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L100R8-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L100R8-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L100RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L100RB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L100RB-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L100RB-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L100RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L100RC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151C6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L151C6-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151C6-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151C8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L151C8-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151C8-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151CB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L151CB-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151CB-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151CC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151QC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151QC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151QD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151QD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151QE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151R6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L151R6-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151R6-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151R8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L151R8-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151R8-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151RB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L151RB-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151RB-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151RC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L151RC-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151RC-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151RD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151RD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151RE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151UC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151UC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151V8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L151V8-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151V8-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151VB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L151VB-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151VB-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151VC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L151VC-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151VC-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151VD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151VD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L151VD-X" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151VD-X", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151VE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151ZC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151ZD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151ZD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L151ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L151ZE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152C6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L152C6-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152C6-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152C8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L152C8-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152C8-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152CB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L152CB-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152CB-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152CC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152QC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152QC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152QD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152QD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152QE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152R6", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L152R6-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152R6-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152R8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L152R8-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152R8-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152RB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L152RB-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152RB-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152RC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L152RC-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152RC-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152RD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152RD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152RE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152UC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152UC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152V8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152V8", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L152V8-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152V8-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152VB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152VB", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L152VB-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152VB-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152VC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L152VC-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152VC-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152VD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152VD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L152VD-X" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152VD-X", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152VE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152ZC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152ZD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152ZD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L152ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L152ZE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L162QC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162QC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L162QD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162QD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L162RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162RC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L162RC-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162RC-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L162RD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162RD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L162RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162RE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L162VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162VC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L162VC-A" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162VC-A", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L162VD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162VD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const @"STM32L162VD-X" = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162VD-X", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L162VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162VE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L162ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162ZC", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L162ZD = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162ZD", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x8030000, .length = 0x30000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L162ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L162ZE", - .cpu = MicroZig.cpus.cortex_m3, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x14000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L412C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L412C8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L412CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L412CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L412K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L412K8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L412KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L412KB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L412R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L412R8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L412RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L412RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L412T8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L412T8", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L412TB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L412TB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L422CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L422CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L422KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L422KB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L422RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L422RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L422TB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L422TB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x2000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x2000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L431CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L431CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L431CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L431CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L431KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L431KB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L431KC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L431KC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L431RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L431RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L431RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L431RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L431VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L431VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L432KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L432KB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L432KC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L432KC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L433CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L433CB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L433CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L433CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L433RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L433RB", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L433RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L433RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L433VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L433VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L442KC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L442KC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L443CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L443CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L443RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L443RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L443VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L443VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x4000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0xC000, .kind = .ram }, - .{ .offset = 0x2000C000, .length = 0x4000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L451CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L451CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L451CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L451CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L451RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L451RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L451RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L451RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L451VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L451VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L451VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L451VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L452CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L452CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L452CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L452CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L452RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L452RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L452RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L452RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L452VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L452VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L452VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L452VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L462CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L462CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L462RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L462RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L462VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L462VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - .{ .offset = 0x20020000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L471QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L471QE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L471QG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L471QG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L471RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L471RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L471RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L471RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L471VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L471VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L471VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L471VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L471ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L471ZE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L471ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L471ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L475RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L475RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L475RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L475RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L475RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L475RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L475VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L475VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L475VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L475VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L475VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L475VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476JE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476JE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476JG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476JG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476ME", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476MG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476MG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476QE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476QG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476QG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476ZE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L476ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L476ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L486JG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L486JG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L486QG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L486QG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L486RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L486RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L486VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L486VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L486ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L486ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L496AE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L496AE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L496AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L496AG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L496QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L496QE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L496QG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L496QG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L496RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L496RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L496RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L496RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L496VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L496VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L496VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L496VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L496WG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L496WG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L496ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L496ZE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L496ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L496ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4A6AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4A6AG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4A6QG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4A6QG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4A6RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4A6RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4A6VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4A6VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4A6ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4A6ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4P5AE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4P5AE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4P5AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4P5AG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4P5CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4P5CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4P5CG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4P5CG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4P5QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4P5QE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4P5QG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4P5QG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4P5RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4P5RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4P5RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4P5RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4P5VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4P5VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4P5VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4P5VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4P5ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4P5ZE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4P5ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4P5ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4Q5AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4Q5AG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4Q5CG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4Q5CG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4Q5QG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4Q5QG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4Q5RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4Q5RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4Q5VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4Q5VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4Q5ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4Q5ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x50000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R5AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R5AG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R5AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R5AI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R5QG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R5QG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R5QI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R5QI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R5VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R5VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R5VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R5VI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R5ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R5ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R5ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R5ZI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R7AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R7AI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R7VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R7VI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R7ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R7ZI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R9AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R9AG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R9AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R9AI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R9VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R9VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R9VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R9VI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R9ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R9ZG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4R9ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4R9ZI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4S5AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4S5AI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4S5QI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4S5QI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4S5VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4S5VI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4S5ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4S5ZI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4S7AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4S7AI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4S7VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4S7VI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4S7ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4S7ZI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4S9AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4S9AI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4S9VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4S9VI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L4S9ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L4S9ZI", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L552CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L552CC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L552CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L552CE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L552ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L552ME", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L552QC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L552QC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L552QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L552QE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L552RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L552RC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L552RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L552RE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L552VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L552VC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L552VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L552VE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L552ZC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L552ZC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L552ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L552ZE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L562CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L562CE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L562ME = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L562ME", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L562QE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L562QE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L562RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L562RE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L562VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L562VE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32L562ZE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32L562ZE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U031C6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U031C6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U031C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U031C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U031F4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U031F4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U031F6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U031F6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U031F8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U031F8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U031G6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U031G6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U031G8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U031G8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U031K4 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U031K4", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x4000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U031K6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U031K6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U031K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U031K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U031R6 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U031R6", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x8000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U031R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U031R8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073C8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073CB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073CC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073H8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073H8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073HB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073HB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073HC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073HC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073K8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073K8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073KB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073KB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073KC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073KC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073M8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073M8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073MB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073MB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073MC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073MC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073R8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073R8", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073RB", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U073RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U073RC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U083CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U083CC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U083HC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U083HC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U083KC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U083KC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U083MC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U083MC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U083RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U083RC", - .cpu = MicroZig.cpus.cortex_m0plus, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xA000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U535CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U535CB", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U535CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U535CC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U535CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U535CE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U535JE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U535JE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U535NC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U535NC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U535NE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U535NE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U535RB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U535RB", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x8010000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U535RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U535RC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U535RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U535RE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U535VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U535VC", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x8020000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U535VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U535VE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U545CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U545CE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U545JE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U545JE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U545NE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U545NE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U545RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U545RE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U545VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U545VE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x8040000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575AG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575AG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575AI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575CG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575CG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575CI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575CI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575OG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575OG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575OI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575OI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575QG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575QG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575QI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575QI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575RG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575RI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575RI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575VG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575VI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575ZG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575ZG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x8080000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U575ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U575ZI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U585AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U585AI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U585CI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U585CI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U585OI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U585OI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U585QI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U585QI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U585RI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U585RI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U585VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U585VI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U585ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U585ZI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20040000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U595AI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U595AI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U595AJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U595AJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U595QI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U595QI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U595QJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U595QJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U595RI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U595RI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U595RJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U595RJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U595VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U595VI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U595VJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U595VJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U595ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U595ZI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U595ZJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U595ZJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U599BJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U599BJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U599NI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U599NI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U599NJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U599NJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U599VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U599VI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U599VJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U599VJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U599ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U599ZI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U599ZJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U599ZJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5A5AJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5A5AJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5A5QI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5A5QI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8100000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5A5QJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5A5QJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5A5RJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5A5RJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5A5VJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5A5VJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5A5ZJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5A5ZJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5A9BJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5A9BJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5A9NJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5A9NJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5A9VJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5A9VJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5A9ZJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5A9ZJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5F7VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5F7VI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5F7VJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5F7VJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5F9BJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5F9BJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5F9NJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5F9NJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5F9VI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5F9VI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5F9VJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5F9VJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5F9ZI = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5F9ZI", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5F9ZJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5F9ZJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5G7VJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5G7VJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5G9BJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5G9BJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5G9NJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5G9NJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5G9VJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5G9VJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32U5G9ZJ = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32U5G9ZJ", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x8200000, .length = 0x200000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0xC0000, .kind = .ram }, - .{ .offset = 0x200C0000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x200D0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x201A0000, .length = 0xD0000, .kind = .ram }, - .{ .offset = 0x20270000, .length = 0x80000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB10CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB10CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x50000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB15CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB15CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x50000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x1000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x3000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x1000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB30CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB30CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB35CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB35CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB35CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB35CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB50CG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB50CG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB55CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB55CC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB55CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB55CE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB55CG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB55CG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB55RC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB55RC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB55RE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB55RE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB55RG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB55RG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB55VC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB55VC", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB55VE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB55VE", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB55VG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB55VG", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WB55VY = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WB55VY", - .cpu = MicroZig.cpus.cortex_m4f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0xA0000, .kind = .flash }, - .{ .offset = 0x10000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x10008000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20000000, .length = 0x30000, .kind = .ram }, - .{ .offset = 0x20030000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20038000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA50KE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA50KE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA50KG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA50KG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA52CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA52CE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA52CG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA52CG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA52KE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA52KE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA52KG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA52KG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA54CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA54CE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA54CG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA54CG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA54KE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA54KE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA54KG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA54KG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA55CE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA55CE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA55CG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA55CG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA55HE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA55HE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA55HG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA55HG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA55UE = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA55UE", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x80000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x18000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WBA55UG = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WBA55UG", - .cpu = MicroZig.cpus.cortex_m33f, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x100000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x20000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WL54CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WL54CC", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WL54JC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WL54JC", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WL55CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WL55CC", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WL55JC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WL55JC", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WLE4C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WLE4C8", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20002800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WLE4CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WLE4CB", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, - .{ .offset = 0x20006000, .length = 0x6000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WLE4CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WLE4CC", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WLE4J8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WLE4J8", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20002800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WLE4JB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WLE4JB", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, - .{ .offset = 0x20006000, .length = 0x6000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WLE4JC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WLE4JC", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WLE5C8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WLE5C8", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20002800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WLE5CB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WLE5CB", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, - .{ .offset = 0x20006000, .length = 0x6000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WLE5CC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WLE5CC", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WLE5J8 = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WLE5J8", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x10000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x2800, .kind = .ram }, - .{ .offset = 0x20002800, .length = 0x2800, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WLE5JB = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WLE5JB", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x20000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x6000, .kind = .ram }, - .{ .offset = 0x20006000, .length = 0x6000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; - -pub const STM32WLE5JC = MicroZig.Target{ - .preferred_format = .elf, - .chip = .{ - .name = "STM32WLE5JC", - .cpu = MicroZig.cpus.cortex_m4, - .memory_regions = &.{ - .{ .offset = 0x8000000, .length = 0x40000, .kind = .flash }, - .{ .offset = 0x20000000, .length = 0x8000, .kind = .ram }, - .{ .offset = 0x20008000, .length = 0x8000, .kind = .ram }, - }, - .register_definition = .{ - .zig = .{ .cwd_relative = register_definition_path }, - }, - }, -}; diff --git a/port/stmicro/stm32/src/chips/all.zig b/port/stmicro/stm32/src/chips/all.zig index f75542c2..d5219cd8 100644 --- a/port/stmicro/stm32/src/chips/all.zig +++ b/port/stmicro/stm32/src/chips/all.zig @@ -305212,2059 +305212,2338 @@ pub const devices = struct { pub const types = struct { pub const peripherals = struct { - pub const rcc_f0v2 = struct { - pub const CECSW = enum(u1) { - /// HSI clock divided by 244 selected as CEC clock source - HSI_DIV_244 = 0x0, - /// LSE clock selected as CEC clock source - LSE = 0x1, - }; - - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, + pub const adc_f1 = struct { + pub const DUALMOD = enum(u4) { + /// Independent mode. + Independent = 0x0, + /// Combined regular simultaneous + injected simultaneous mode + RegularInjected = 0x1, + /// Combined regular simultaneous + alternate trigger mode + RegularAlternateTrigger = 0x2, + /// Combined injected simultaneous + fast interleaved mode + InjectedFastInterleaved = 0x3, + /// Combined injected simultaneous + slow Interleaved mode + InjectedSlowInterleaved = 0x4, + /// Injected simultaneous mode only + Injected = 0x5, + /// Regular simultaneous mode only + Regular = 0x6, + /// Fast interleaved mode only + FastInterleaved = 0x7, + /// Slow interleaved mode only + SlowInterleaved = 0x8, + /// Alternate trigger mode only + AlternateTrigger = 0x9, _, }; - pub const ICSW = enum(u1) { - /// HSI clock selected as I2C clock source - HSI = 0x0, - /// SYSCLK clock selected as I2C clock source - SYS = 0x1, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium high driving capability - MediumHigh = 0x1, - /// Medium low driving capability - MediumLow = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCOPRE = enum(u3) { - /// MCO is divided by 1 - Div1 = 0x0, - /// MCO is divided by 2 - Div2 = 0x1, - /// MCO is divided by 4 - Div4 = 0x2, - /// MCO is divided by 8 - Div8 = 0x3, - /// MCO is divided by 16 - Div16 = 0x4, - /// MCO is divided by 32 - Div32 = 0x5, - /// MCO is divided by 64 - Div64 = 0x6, - /// MCO is divided by 128 - Div128 = 0x7, - }; - - pub const MCOSEL = enum(u4) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// Internal RC 14 MHz (HSI14) oscillator clock selected - HSI14 = 0x1, - /// Internal low speed (LSI) oscillator clock selected - LSI = 0x2, - /// External low speed (LSE) oscillator clock selected - LSE = 0x3, - /// System clock selected - SYS = 0x4, - /// Internal RC 8 MHz (HSI) oscillator clock selected - HSI = 0x5, - /// External 4-32 MHz (HSE) oscillator clock selected - HSE = 0x6, - /// PLL clock selected (divided by 1 or 2, depending en PLLMCODIV) - PLL = 0x7, - _, + pub const SAMPLE_TIME = enum(u3) { + /// 1.5 cycles + Cycles1_5 = 0x0, + /// 7.5 cycles + Cycles7_5 = 0x1, + /// 13.5 cycles + Cycles13_5 = 0x2, + /// 28.5 cycles + Cycles28_5 = 0x3, + /// 41.5 cycles + Cycles41_5 = 0x4, + /// 55.5 cycles + Cycles55_5 = 0x5, + /// 71.5 cycles + Cycles71_5 = 0x6, + /// 239.5 cycles + Cycles239_5 = 0x7, }; - pub const PLLMCODIV = enum(u1) { - /// PLL is divided by 2 for MCO - Div2 = 0x0, - /// PLL is not divided for MCO - Div1 = 0x1, + /// Analog-to-digital converter + pub const ADC = extern struct { + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of conversion + EOC: u1, + /// Injected channel end of conversion + JEOC: u1, + /// Injected channel start flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + padding: u27, + }), + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Analog watchdog channel select bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt enable + AWDIE: u1, + /// Interrupt enable for injected channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: u1, + /// Automatic injected group conversion + JAUTO: u1, + /// Discontinuous mode on regular channels + DISCEN: u1, + /// Discontinuous mode on injected channels + JDISCEN: u1, + /// Discontinuous mode channel count + DISCNUM: u3, + /// Dual mode selection + DUALMOD: packed union { + raw: u4, + value: DUALMOD, + }, + reserved22: u2, + /// Analog watchdog enable on injected channels + JAWDEN: u1, + /// Analog watchdog enable on regular channels + AWDEN: u1, + padding: u8, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + /// A/D Calibration + CAL: u1, + /// Reset calibration + RSTCAL: u1, + reserved8: u4, + /// Direct memory access mode (for single ADC mode) + DMA: u1, + reserved11: u2, + /// Data alignment + ALIGN: u1, + /// External event select for injected group + JEXTSEL: u3, + /// External trigger conversion mode for injected channels + JEXTTRIG: u1, + reserved17: u1, + /// External event select for regular group + EXTSEL: u3, + /// External trigger conversion mode for regular channels + EXTTRIG: u1, + /// Start conversion of injected channels + JSWSTART: u1, + /// Start conversion of regular channels + SWSTART: u1, + /// Temperature sensor and VREFINT enable + TSVREFE: u1, + padding: u8, + }), + /// sample time register 1 + SMPR1: mmio.Mmio(packed struct(u32) { + /// Channel x sample time selection + SMP: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + padding: u29, + }), + /// sample time register 2 + SMPR2: mmio.Mmio(packed struct(u32) { + /// Channel 0 sampling time selection + SMP: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + padding: u29, + }), + /// injected channel data offset register x + JOFR: [4]mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET: u12, + padding: u20, + }), + /// watchdog higher threshold register + HTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog higher threshold + HT: u12, + padding: u20, + }), + /// watchdog lower threshold register + LTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog lower threshold + LT: u12, + padding: u20, + }), + /// regular sequence register 1 + SQR1: mmio.Mmio(packed struct(u32) { + /// 13th to 16th conversion in regular sequence + SQ: u5, + reserved20: u15, + /// Regular channel sequence length + L: u4, + padding: u8, + }), + /// regular sequence register 2 + SQR2: mmio.Mmio(packed struct(u32) { + /// 7th to 12th conversion in regular sequence + SQ: u5, + padding: u27, + }), + /// regular sequence register 3 + SQR3: mmio.Mmio(packed struct(u32) { + /// 1st to 6th conversion in regular sequence + SQ: u5, + padding: u27, + }), + /// injected sequence register + JSQR: mmio.Mmio(packed struct(u32) { + /// 1st conversion in injected sequence + JSQ: u5, + reserved20: u15, + /// Injected sequence length + JL: u2, + padding: u10, + }), + /// injected data register x + JDR: [4]mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// regular data register + DR: mmio.Mmio(packed struct(u32) { + /// Regular data + DATA: u16, + /// ADC2 data + ADC2DATA: u16, + }), }; + }; - pub const PLLMUL = enum(u4) { - /// PLL input clock x2 - Mul2 = 0x0, - /// PLL input clock x3 - Mul3 = 0x1, - /// PLL input clock x4 - Mul4 = 0x2, - /// PLL input clock x5 - Mul5 = 0x3, - /// PLL input clock x6 - Mul6 = 0x4, - /// PLL input clock x7 - Mul7 = 0x5, - /// PLL input clock x8 - Mul8 = 0x6, - /// PLL input clock x9 - Mul9 = 0x7, - /// PLL input clock x10 - Mul10 = 0x8, - /// PLL input clock x11 - Mul11 = 0x9, - /// PLL input clock x12 - Mul12 = 0xa, - /// PLL input clock x13 - Mul13 = 0xb, - /// PLL input clock x14 - Mul14 = 0xc, - /// PLL input clock x15 - Mul15 = 0xd, - /// PLL input clock x16 - Mul16 = 0xe, + pub const adc_f3 = struct { + pub const ADVREGEN = enum(u2) { + /// Intermediate state required when moving the ADC voltage regulator between states + Intermediate = 0x0, + /// ADC voltage regulator enabled + Enabled = 0x1, + /// ADC voltage regulator disabled + Disabled = 0x2, _, }; - pub const PLLSRC = enum(u1) { - /// HSI divided by 2 selected as PLL input clock - HSI_Div2 = 0x0, - /// HSE divided by PREDIV selected as PLL input clock - HSE_Div_PREDIV = 0x1, + pub const ALIGN = enum(u1) { + /// Right alignment + Right = 0x0, + /// Left alignment + Left = 0x1, }; - pub const PLLXTPRE = enum(u1) { - /// HSE clock not divided - Div1 = 0x0, - /// HSE clock divided by 2 - Div2 = 0x1, + pub const AWD1SGL = enum(u1) { + /// Analog watchdog 1 enabled on all channels + All = 0x0, + /// Analog watchdog 1 enabled on single channel selected in AWD1CH + Single = 0x1, }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, + pub const DIFSEL_10 = enum(u1) { + /// Input channel is configured in single-ended mode + SingleEnded = 0x0, + /// Input channel is configured in differential mode + Differential = 0x1, }; - pub const PREDIV = enum(u4) { - /// PREDIV input clock not divided - Div1 = 0x0, - /// PREDIV input clock divided by 2 - Div2 = 0x1, - /// PREDIV input clock divided by 3 - Div3 = 0x2, - /// PREDIV input clock divided by 4 - Div4 = 0x3, - /// PREDIV input clock divided by 5 - Div5 = 0x4, - /// PREDIV input clock divided by 6 - Div6 = 0x5, - /// PREDIV input clock divided by 7 - Div7 = 0x6, - /// PREDIV input clock divided by 8 - Div8 = 0x7, - /// PREDIV input clock divided by 9 - Div9 = 0x8, - /// PREDIV input clock divided by 10 - Div10 = 0x9, - /// PREDIV input clock divided by 11 - Div11 = 0xa, - /// PREDIV input clock divided by 12 - Div12 = 0xb, - /// PREDIV input clock divided by 13 - Div13 = 0xc, - /// PREDIV input clock divided by 14 - Div14 = 0xd, - /// PREDIV input clock divided by 15 - Div15 = 0xe, - /// PREDIV input clock divided by 16 - Div16 = 0xf, + pub const DMACFG = enum(u1) { + /// DMA One Shot mode selected + OneShot = 0x0, + /// DMA Circular mode selected + Circular = 0x1, }; - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, + pub const EXTEN = enum(u2) { + /// Trigger detection disabled + Disabled = 0x0, + /// Trigger detection on the rising edge + RisingEdge = 0x1, + /// Trigger detection on the falling edge + FallingEdge = 0x2, + /// Trigger detection on both the rising and falling edges + BothEdges = 0x3, }; - pub const SW = enum(u2) { - /// HSI oscillator used as system clock - HSI = 0x0, - /// HSE oscillator used as system clock - HSE = 0x1, - /// PLL used as system clock - PLL1_P = 0x2, - _, + pub const JEXTEN = enum(u2) { + /// Trigger detection disabled + Disabled = 0x0, + /// Trigger detection on the rising edge + RisingEdge = 0x1, + /// Trigger detection on the falling edge + FallingEdge = 0x2, + /// Trigger detection on both the rising and falling edges + BothEdges = 0x3, }; - pub const USART1SW = enum(u2) { - /// PCLK selected as USART clock source - PCLK2 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, + pub const JQM = enum(u1) { + /// JSQR Mode 0: Queue maintains the last written configuration into JSQR + Mode0 = 0x0, + /// JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence + Mode1 = 0x1, }; - pub const USARTSW = enum(u2) { - /// PCLK selected as USART clock source - PCLK1 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, + pub const RES = enum(u2) { + /// 12-bit resolution + Bits12 = 0x0, + /// 10-bit resolution + Bits10 = 0x1, + /// 8-bit resolution + Bits8 = 0x2, + /// 6-bit resolution + Bits6 = 0x3, }; - pub const USBSW = enum(u1) { - /// PLL clock selected as USB clock source - PLL1_P = 0x1, - _, + pub const SAMPLE_TIME = enum(u3) { + /// 1.5 ADC clock cycles + Cycles1_5 = 0x0, + /// 2.5 ADC clock cycles + Cycles2_5 = 0x1, + /// 4.5 ADC clock cycles + Cycles4_5 = 0x2, + /// 7.5 ADC clock cycles + Cycles7_5 = 0x3, + /// 19.5 ADC clock cycles + Cycles19_5 = 0x4, + /// 61.5 ADC clock cycles + Cycles61_5 = 0x5, + /// 181.5 ADC clock cycles + Cycles181_5 = 0x6, + /// 601.5 ADC clock cycles + Cycles601_5 = 0x7, }; - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register + /// Analog-to-Digital Converter + pub const ADC = extern struct { + /// interrupt and status register + ISR: mmio.Mmio(packed struct(u32) { + /// ADC Ready + ADRDY: u1, + /// End of sampling flag + EOSMP: u1, + /// End of conversion flag + EOC: u1, + /// End of regular sequence flag + EOS: u1, + /// ADC overrun + OVR: u1, + /// Injected channel end of conversion flag + JEOC: u1, + /// Injected channel end of sequence flag + JEOS: u1, + /// Analog watchdog flag + AWD: u1, + reserved10: u2, + /// Injected context queue overflow + JQOVF: u1, + padding: u21, + }), + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// ADC ready interrupt enable + ADRDYIE: u1, + /// End of sampling flag interrupt enable for regular conversions + EOSMPIE: u1, + /// End of regular conversion interrupt enable + EOCIE: u1, + /// End of regular sequence of conversions interrupt enable + EOSIE: u1, + /// Overrun interrupt enable + OVRIE: u1, + /// End of injected conversion interrupt enable + JEOCIE: u1, + /// End of injected sequence of conversions interrupt enable + JEOSIE: u1, + /// Analog watchdog X interrupt enable + AWDIE: u1, + reserved10: u2, + /// Injected context queue overflow interrupt enable + JQOVFIE: u1, + padding: u21, + }), + /// control register CR: mmio.Mmio(packed struct(u32) { - /// Internal High Speed clock enable - HSION: u1, - /// Internal High Speed clock ready flag - HSIRDY: u1, - reserved3: u1, - /// Internal High Speed clock trimming - HSITRIM: u5, - /// Internal High Speed clock Calibration - HSICAL: u8, - /// External High Speed clock enable - HSEON: u1, - /// External High Speed clock ready flag - HSERDY: u1, - /// External High Speed clock Bypass - HSEBYP: u1, - /// Clock Security System enable - CSSON: u1, - reserved24: u4, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding: u6, + /// ADC enable control + ADEN: u1, + /// ADC disable command + ADDIS: u1, + /// ADC start of regular conversion + ADSTART: u1, + /// ADC start of injected conversion + JADSTART: u1, + /// ADC stop of regular conversion command + ADSTP: u1, + /// ADC stop of injected conversion command + JADSTP: u1, + reserved28: u22, + /// ADC voltage regulator enable + ADVREGEN: packed union { + raw: u2, + value: ADVREGEN, + }, + /// Differential mode for calibration + ADCALDIF: u1, + /// ADC calibration + ADCAL: u1, }), - /// Clock configuration register (RCC_CFGR) + /// configuration register CFGR: mmio.Mmio(packed struct(u32) { - /// System clock Switch - SW: packed union { - raw: u2, - value: SW, + /// Direct memory access enable + DMAEN: u1, + /// Direct memory access configuration + DMACFG: packed union { + raw: u1, + value: DMACFG, }, - /// System Clock Switch Status - SWS: packed union { + reserved3: u1, + /// Data resolution + RES: packed union { raw: u2, - value: SW, + value: RES, }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, + /// Data alignment + ALIGN: packed union { + raw: u1, + value: ALIGN, }, - /// APB Low speed prescaler (APB1) - PPRE: packed union { - raw: u3, - value: PPRE, + /// External trigger selection for regular group + EXTSEL: u4, + /// External trigger enable and polarity selection for regular channels + EXTEN: packed union { + raw: u2, + value: EXTEN, }, - reserved14: u3, - /// APCPRE is deprecated. See ADC field in CFGR2 register. - ADCPRE: u1, + /// Overrun Mode + OVRMOD: u1, + /// Continuous conversion + CONT: u1, + /// Delayed conversion mode + AUTDLY: u1, reserved16: u1, - /// PLL input clock source - PLLSRC: packed union { + /// Discontinuous mode for regular channels + DISCEN: u1, + /// Discontinuous mode channel count + DISCNUM: u3, + /// Discontinuous mode on injected channels + JDISCEN: u1, + /// JSQR queue mode + JQM: packed union { raw: u1, - value: PLLSRC, + value: JQM, }, - /// HSE divider for PLL entry. Same bit as PREDIV[0] from CFGR2 register. Refer to it for its meaning - PLLXTPRE: packed union { + /// Enable the watchdog 1 on a single channel or on all channels + AWD1SGL: packed union { raw: u1, - value: PLLXTPRE, - }, - /// PLL Multiplication Factor - PLLMUL: packed union { - raw: u4, - value: PLLMUL, - }, - reserved24: u2, - /// Microcontroller clock output - MCOSEL: packed union { - raw: u4, - value: MCOSEL, + value: AWD1SGL, }, - /// Microcontroller Clock Output Prescaler - MCOPRE: packed union { + /// Analog watchdog 1 enable on regular channels + AWD1EN: u1, + /// Analog watchdog 1 enable on injected channels + JAWD1EN: u1, + /// Automatic injected group conversion + JAUTO: u1, + /// Analog watchdog 1 channel selection + AWD1CH: u5, + padding: u1, + }), + reserved20: [4]u8, + /// sample time register 1 + SMPR1: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Channel x sampling time selection + SMP: packed union { raw: u3, - value: MCOPRE, + value: SAMPLE_TIME, }, - /// PLL clock not divided for MCO - PLLMCODIV: packed union { - raw: u1, - value: PLLMCODIV, + padding: u26, + }), + /// sample time register 2 + SMPR2: mmio.Mmio(packed struct(u32) { + /// Channel x sampling time selection + SMP: packed union { + raw: u3, + value: SAMPLE_TIME, }, + padding: u29, }), - /// Clock interrupt register (RCC_CIR) - CIR: mmio.Mmio(packed struct(u32) { - /// LSI Ready Interrupt flag - LSIRDYF: u1, - /// LSE Ready Interrupt flag - LSERDYF: u1, - /// HSI Ready Interrupt flag - HSIRDYF: u1, - /// HSE Ready Interrupt flag - HSERDYF: u1, - /// PLL Ready Interrupt flag - PLLRDYF: u1, - /// HSI14 ready interrupt flag - HSI14RDYF: u1, - reserved7: u1, - /// Clock Security System Interrupt flag - CSSF: u1, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1, - /// LSE Ready Interrupt Enable - LSERDYIE: u1, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1, - /// HSE Ready Interrupt Enable - HSERDYIE: u1, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1, - /// HSI14 ready interrupt enable - HSI14RDYIE: u1, - reserved16: u2, - /// LSI Ready Interrupt Clear - LSIRDYC: u1, - /// LSE Ready Interrupt Clear - LSERDYC: u1, - /// HSI Ready Interrupt Clear - HSIRDYC: u1, - /// HSE Ready Interrupt Clear - HSERDYC: u1, - /// PLL Ready Interrupt Clear - PLLRDYC: u1, - /// HSI 14 MHz Ready Interrupt Clear - HSI14RDYC: u1, - reserved23: u1, - /// Clock security system interrupt clear - CSSC: u1, + reserved32: [4]u8, + /// watchdog threshold register 1 + TR1: mmio.Mmio(packed struct(u32) { + /// LT1 + LT1: u12, + reserved16: u4, + /// HT1 + HT1: u12, + padding: u4, + }), + /// watchdog threshold register + TR2: mmio.Mmio(packed struct(u32) { + /// LT2 + LT2: u8, + reserved16: u8, + /// HT2 + HT2: u8, padding: u8, }), - /// APB2 peripheral reset register (RCC_APB2RSTR) - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// SYSCFG and COMP reset - SYSCFGRST: u1, - reserved5: u4, - /// USART6 reset - USART6RST: u1, - /// USART7 reset - USART7RST: u1, - /// USART8 reset - USART8RST: u1, - reserved9: u1, - /// ADC interface reset - ADCRST: u1, - reserved11: u1, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI 1 reset - SPI1RST: u1, - reserved14: u1, - /// USART1 reset - USART1RST: u1, - reserved16: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - reserved22: u3, - /// Debug MCU reset - DBGMCURST: u1, - padding: u9, + /// watchdog threshold register 3 + TR3: mmio.Mmio(packed struct(u32) { + /// LT3 + LT3: u8, + reserved16: u8, + /// HT3 + HT3: u8, + padding: u8, }), - /// APB1 peripheral reset register (RCC_APB1RSTR) - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - reserved4: u2, - /// Timer 6 reset - TIM6RST: u1, - /// TIM7 timer reset - TIM7RST: u1, - reserved8: u2, - /// Timer 14 reset - TIM14RST: u1, - reserved11: u2, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI2 reset - SPI2RST: u1, - reserved17: u2, - /// USART 2 reset - USART2RST: u1, - /// USART3 reset - USART3RST: u1, - /// USART4 reset - USART4RST: u1, - /// USART5 reset - USART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// USB interface reset - USBRST: u1, - reserved25: u1, - /// CAN interface reset - CANRST: u1, - reserved27: u1, - /// Clock Recovery System interface reset - CRSRST: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - /// HDMI CEC reset - CECRST: u1, - padding: u1, + reserved48: [4]u8, + /// regular sequence register 1 + SQR1: mmio.Mmio(packed struct(u32) { + /// Regular channel sequence length + L: u4, + reserved6: u2, + /// X conversion in regular sequence + SQ: u5, + padding: u21, }), - /// AHB Peripheral Clock enable register (RCC_AHBENR) - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA clock enable - DMAEN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// SRAM interface clock enable - SRAMEN: u1, - reserved4: u1, - /// FLASH clock enable - FLASHEN: u1, - reserved6: u1, - /// CRC clock enable - CRCEN: u1, - reserved17: u10, - /// I/O port A clock enable - GPIOAEN: u1, - /// I/O port B clock enable - GPIOBEN: u1, - /// I/O port C clock enable - GPIOCEN: u1, - /// I/O port D clock enable - GPIODEN: u1, - /// I/O port E clock enable - GPIOEEN: u1, - /// I/O port F clock enable - GPIOFEN: u1, - reserved24: u1, - /// Touch sensing controller clock enable - TSCEN: u1, - padding: u7, + /// regular sequence register 2 + SQR2: mmio.Mmio(packed struct(u32) { + /// X conversion in regular sequence + SQ: u5, + padding: u27, }), - /// APB2 peripheral clock enable register (RCC_APB2ENR) - APB2ENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved5: u4, - /// USART6 clock enable - USART6EN: u1, - /// USART7 clock enable - USART7EN: u1, - /// USART8 clock enable - USART8EN: u1, - reserved9: u1, - /// ADC 1 interface clock enable - ADCEN: u1, - reserved11: u1, - /// TIM1 Timer clock enable - TIM1EN: u1, - /// SPI 1 clock enable - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable - USART1EN: u1, - reserved16: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - reserved22: u3, - /// MCU debug module clock enable - DBGMCUEN: u1, - padding: u9, + /// regular sequence register 3 + SQR3: mmio.Mmio(packed struct(u32) { + /// X conversion in regular sequence + SQ: u5, + padding: u27, }), - /// APB1 peripheral clock enable register (RCC_APB1ENR) - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer 2 clock enable - TIM2EN: u1, - /// Timer 3 clock enable - TIM3EN: u1, - reserved4: u2, - /// Timer 6 clock enable - TIM6EN: u1, - /// TIM7 timer clock enable - TIM7EN: u1, - reserved8: u2, - /// Timer 14 clock enable - TIM14EN: u1, - reserved11: u2, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI 2 clock enable - SPI2EN: u1, - reserved17: u2, - /// USART 2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// USART4 clock enable - USART4EN: u1, - /// USART5 clock enable - USART5EN: u1, - /// I2C 1 clock enable - I2C1EN: u1, - /// I2C 2 clock enable - I2C2EN: u1, - /// USB interface clock enable - USBEN: u1, - reserved25: u1, - /// CAN interface clock enable - CANEN: u1, - reserved27: u1, - /// Clock Recovery System interface clock enable - CRSEN: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - /// HDMI CEC interface clock enable - CECEN: u1, - padding: u1, + /// regular sequence register 4 + SQR4: mmio.Mmio(packed struct(u32) { + /// X conversion in regular sequence + SQ: u5, + padding: u27, }), - /// Backup domain control register (RCC_BDCR) - BDCR: mmio.Mmio(packed struct(u32) { - /// External Low Speed oscillator enable - LSEON: u1, - /// External Low Speed oscillator ready - LSERDY: u1, - /// External Low Speed oscillator bypass - LSEBYP: u1, - /// LSE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - reserved8: u3, - /// RTC clock source selection - RTCSEL: packed union { + /// regular Data Register + DR: mmio.Mmio(packed struct(u32) { + /// Regular data + RDATA: u16, + padding: u16, + }), + reserved76: [8]u8, + /// injected sequence register + JSQR: mmio.Mmio(packed struct(u32) { + /// Injected channel sequence length + JL: u2, + /// External Trigger Selection for injected group + JEXTSEL: u4, + /// External Trigger Enable and Polarity Selection for injected channels + JEXTEN: packed union { raw: u2, - value: RTCSEL, + value: JEXTEN, }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - padding: u15, - }), - /// Control/status register (RCC_CSR) - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low speed oscillator enable - LSION: u1, - /// Internal low speed oscillator ready - LSIRDY: u1, - reserved23: u21, - /// 1.8 V domain reset flag - V18PWRRSTF: u1, - /// Remove reset flag - RMVF: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// X conversion in the injected sequence + JSQ: u5, + padding: u19, }), - /// AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - reserved17: u17, - /// I/O port A reset - GPIOARST: u1, - /// I/O port B reset - GPIOBRST: u1, - /// I/O port C reset - GPIOCRST: u1, - /// I/O port D reset - GPIODRST: u1, - /// I/O port E reset - GPIOERST: u1, - /// I/O port F reset - GPIOFRST: u1, - reserved24: u1, - /// Touch sensing controller reset - TSCRST: u1, - padding: u7, + reserved96: [16]u8, + /// offset register X + OFR: [4]mmio.Mmio(packed struct(u32) { + /// Data offset y for the channel programmed into bits OFFSETy_CH + OFFSET: u12, + reserved26: u14, + /// Data offset y for the channel programmed into bits OFFSETy_CH + CH: u5, + /// Offset y Enable + EN: u1, }), - /// Clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// PREDIV division factor - PREDIV: packed union { - raw: u4, - value: PREDIV, - }, - padding: u28, + reserved128: [16]u8, + /// injected data register X + JDR: [4]mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, }), - /// Clock configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SW: packed union { - raw: u2, - value: USART1SW, + reserved160: [16]u8, + /// Analog Watchdog X Configuration Register + AWDCR: [2]mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// AWD2CH + AWD2CH0: u1, + padding: u30, + }), + reserved176: [8]u8, + /// Differential Mode Selection Register 2 + DIFSEL: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Differential mode for channels 15 to 1 + DIFSEL_10: packed union { + raw: u1, + value: DIFSEL_10, }, - reserved4: u2, - /// I2C1 clock source selection - I2C1SW: packed union { + /// Differential mode for channels 15 to 1 + DIFSEL_11: packed union { raw: u1, - value: ICSW, + value: DIFSEL_10, }, - reserved6: u1, - /// HDMI CEC clock source selection - CECSW: packed union { + /// Differential mode for channels 15 to 1 + DIFSEL_12: packed union { raw: u1, - value: CECSW, + value: DIFSEL_10, }, - /// USB clock source selection - USBSW: packed union { + /// Differential mode for channels 15 to 1 + DIFSEL_13: packed union { raw: u1, - value: USBSW, + value: DIFSEL_10, }, - /// ADCSW is deprecated. See ADC field in CFGR2 register. - ADCSW: u1, - reserved16: u7, - /// USART2 clock source selection - USART2SW: packed union { - raw: u2, - value: USARTSW, + /// Differential mode for channels 15 to 1 + DIFSEL_14: packed union { + raw: u1, + value: DIFSEL_10, }, - /// USART3 clock source - USART3SW: packed union { - raw: u2, - value: USARTSW, + /// Differential mode for channels 15 to 1 + DIFSEL_15: packed union { + raw: u1, + value: DIFSEL_10, }, - padding: u12, + /// Differential mode for channels 15 to 1 + DIFSEL_16: packed union { + raw: u1, + value: DIFSEL_10, + }, + /// Differential mode for channels 15 to 1 + DIFSEL_17: packed union { + raw: u1, + value: DIFSEL_10, + }, + /// Differential mode for channels 15 to 1 + DIFSEL_18: packed union { + raw: u1, + value: DIFSEL_10, + }, + /// Differential mode for channels 15 to 1 + DIFSEL_19: packed union { + raw: u1, + value: DIFSEL_10, + }, + /// Differential mode for channels 15 to 1 + DIFSEL_110: packed union { + raw: u1, + value: DIFSEL_10, + }, + /// Differential mode for channels 15 to 1 + DIFSEL_111: packed union { + raw: u1, + value: DIFSEL_10, + }, + /// Differential mode for channels 15 to 1 + DIFSEL_112: packed union { + raw: u1, + value: DIFSEL_10, + }, + /// Differential mode for channels 15 to 1 + DIFSEL_113: packed union { + raw: u1, + value: DIFSEL_10, + }, + /// Differential mode for channels 15 to 1 + DIFSEL_114: packed union { + raw: u1, + value: DIFSEL_10, + }, + /// Differential mode for channels 15 to 1 + DIFSEL_115: packed union { + raw: u1, + value: DIFSEL_10, + }, + /// Differential mode for channels 15 to 1 + DIFSEL_116: packed union { + raw: u1, + value: DIFSEL_10, + }, + /// Differential mode for channels 15 to 1 + DIFSEL_117: packed union { + raw: u1, + value: DIFSEL_10, + }, + padding: u13, }), - /// Clock control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// HSI14 clock enable - HSI14ON: u1, - /// HR14 clock ready flag - HSI14RDY: u1, - /// HSI14 clock request from ADC disable - HSI14DIS: u1, - /// HSI14 clock trimming - HSI14TRIM: u5, - /// HSI14 clock calibration - HSI14CAL: u8, - padding: u16, + /// Calibration Factors + CALFACT: mmio.Mmio(packed struct(u32) { + /// CALFACT_S + CALFACT_S: u7, + reserved16: u9, + /// CALFACT_D + CALFACT_D: u7, + padding: u9, }), }; }; - pub const sai_v1 = struct { - pub const CKSTR = enum(u1) { - /// Data strobing edge is falling edge of SCK - FallingEdge = 0x0, - /// Data strobing edge is rising edge of SCK - RisingEdge = 0x1, - }; - - pub const CNRDY = enum(u1) { - /// External AC’97 Codec is ready - Ready = 0x0, - /// External AC’97 Codec is not ready - NotReady = 0x1, - }; - - pub const COMP = enum(u2) { - /// No companding algorithm - NoCompanding = 0x0, - /// μ-Law algorithm - MuLaw = 0x2, - /// A-Law algorithm - ALaw = 0x3, - _, - }; - - pub const CPL = enum(u1) { - /// 1’s complement representation - OnesComplement = 0x0, - /// 2’s complement representation - TwosComplement = 0x1, - }; - - pub const DS = enum(u3) { - /// 8 bits - Bit8 = 0x2, - /// 10 bits - Bit10 = 0x3, - /// 16 bits - Bit16 = 0x4, - /// 20 bits - Bit20 = 0x5, - /// 24 bits - Bit24 = 0x6, - /// 32 bits - Bit32 = 0x7, - _, - }; - - pub const FLVL = enum(u3) { - /// FIFO empty - Empty = 0x0, - /// FIFO <= 1⁄4 but not empty - Quarter1 = 0x1, - /// 1⁄4 < FIFO <= 1⁄2 - Quarter2 = 0x2, - /// 1⁄2 < FIFO <= 3⁄4 - Quarter3 = 0x3, - /// 3⁄4 < FIFO but not full - Quarter4 = 0x4, - /// FIFO full - Full = 0x5, - _, - }; - - pub const FSOFF = enum(u1) { - /// FS is asserted on the first bit of the slot 0 - OnFirst = 0x0, - /// FS is asserted one bit before the first bit of the slot 0 - BeforeFirst = 0x1, - }; - - pub const FSPOL = enum(u1) { - /// FS is active low (falling edge) - FallingEdge = 0x0, - /// FS is active high (rising edge) - RisingEdge = 0x1, - }; - - pub const FTH = enum(u3) { - /// FIFO empty - Empty = 0x0, - /// 1⁄4 FIFO - Quarter1 = 0x1, - /// 1⁄2 FIFO - Quarter2 = 0x2, - /// 3⁄4 FIFO - Quarter3 = 0x3, - /// FIFO full - Full = 0x4, - _, - }; - - pub const LSBFIRST = enum(u1) { - /// Data are transferred with MSB first - MsbFirst = 0x0, - /// Data are transferred with LSB first - LsbFirst = 0x1, - }; - - pub const MODE = enum(u2) { - /// Master transmitter - MasterTx = 0x0, - /// Master receiver - MasterRx = 0x1, - /// Slave transmitter - SlaveTx = 0x2, - /// Slave receiver - SlaveRx = 0x3, - }; - - pub const MONO = enum(u1) { - /// Stereo mode - Stereo = 0x0, - /// Mono mode - Mono = 0x1, - }; - - pub const MUTEVAL = enum(u1) { - /// Bit value 0 is sent during the mute mode - SendZero = 0x0, - /// Last values are sent during the mute mode - SendLast = 0x1, + pub const adc_f3_v1_1 = struct { + pub const ADC_CFG = enum(u1) { + /// Bank A selected for channels ADC_IN0..31 + BANK_A = 0x0, + /// Bank B selected for channels ADC_IN0..31b + BANK_B = 0x1, }; - pub const NODIV = enum(u1) { - /// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value - MasterClock = 0x0, - /// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. - NoDiv = 0x1, + pub const DELS = enum(u3) { + /// No Delay + NO_DELAY = 0x0, + /// Until the converted data have been read + AFTER_READ = 0x1, + /// Delay 7 APB clock cycles after the conversion + DELAY_7_CLK = 0x2, + /// Delay 16 APB clock cycles after the conversion + DELAY_15_CLK = 0x3, + /// Delay 31 APB clock cycles after the conversion + DELAY_31_CLK = 0x4, + /// Delay 63 APB clock cycles after the conversion + DELAY_63_CLK = 0x5, + /// Delay 127 APB clock cycles after the conversion + DELAY_127_CLK = 0x6, + /// Delay 255 APB clock cycles after the conversion + DELAY_255_CLK = 0x7, }; - pub const OUTDRIV = enum(u1) { - /// Audio block output driven when SAIEN is set - OnStart = 0x0, - /// Audio block output driven immediately after the setting of this bit - Immediately = 0x1, + pub const DISCNUM = enum(u3) { + /// 1 conversions are discontinued and the conversion is carried out on one channel + DISCNUM_1 = 0x0, + /// 2 conversion is discontinued and the conversions are carried out on 2 channels + DISCNUM_2 = 0x1, + /// 3 conversions are discontinued and the conversions are carried out on 3 channels + DISCNUM_3 = 0x2, + /// 4 conversions are discontinued and the conversions are carried out on 4 channels + DISCNUM_4 = 0x3, + /// 5 conversions are discontinued and the conversions are carried out on 5 channels + DISCNUM_5 = 0x4, + /// 6 conversions are discontinued and the conversions are carried out on 6 channels + DISCNUM_6 = 0x5, + /// 7 conversions are discontinued and the conversions are carried out on 7 channels + DISCNUM_7 = 0x6, + /// 8 conversions are discontinued and the conversions are carried out on 8 channels + DISCNUM_8 = 0x7, }; - pub const PRTCFG = enum(u2) { - /// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol - Free = 0x0, - /// SPDIF protocol - Spdif = 0x1, - /// AC’97 protocol - Ac97 = 0x2, - _, + pub const EXTEN = enum(u2) { + /// Trigger detection disabled + DISABLED = 0x0, + /// Trigger detection on the rising edge + RISING = 0x1, + /// Trigger detection on the falling edge + FALLING = 0x2, + /// Trigger detection on both edges + BOTH = 0x3, }; - pub const SLOTEN = enum(u16) { - /// Inactive slot - Inactive = 0x0, - /// Active slot - Active = 0x1, + pub const EXTSEL = enum(u4) { + /// Timer 9 CC2 event + TIM9_CC2 = 0x0, + /// Timer 9 TRGO event + TIM9_TRGO = 0x1, + /// Timer 2 CC3 event + TIM2_CC3 = 0x2, + /// Timer 2 CC2 event + TIM2_CC2 = 0x3, + /// Timer 3 TRGO event + TIM3_TRGO = 0x4, + /// Timer 4 CC4 event + TIM4_CC4 = 0x5, + /// Timer 2 TRGO event + TIM2_TRGO = 0x6, + /// Timer 3 CC1 event + TIM3_CC1 = 0x7, + /// Timer 3 CC3 event + TIM3_CC3 = 0x8, + /// Timer 4 TRGO event + TIM4_TRGO = 0x9, + /// Timer 6 TRGO event + TIM6_TRGO = 0xa, + /// External interrupt line 11 + EXTI_LINE11 = 0xf, _, }; - pub const SLOTSZ = enum(u2) { - /// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) - DataSize = 0x0, - /// 16-bit - Bit16 = 0x1, - /// 32-bit - Bit32 = 0x2, + pub const JEXTSEL = enum(u4) { + /// Timer 9 CC1 event + TIM9_CC1 = 0x0, + /// Timer 9 TRGO event + TIM9_TRGO = 0x1, + /// Timer 2 TRGO event + TIM2_TRGO = 0x2, + /// Timer 2 CC1 event + TIM2_CC1 = 0x3, + /// Timer 3 CC4 event + TIM3_CC4 = 0x4, + /// Timer 4 TRGO event + TIM4_TRGO = 0x5, + /// Timer 4 CC1 event + TIM4_CC1 = 0x6, + /// Timer 4 CC2 event + TIM4_CC2 = 0x7, + /// Timer 4 CC3 event + TIM4_CC3 = 0x8, + /// Timer 4 CC3 event + TIM10_CC1 = 0x9, + /// Timer 7 TRGO event + TIM7_TRGO = 0xa, + /// External interrupt line 15 + EXTI_LINE15 = 0xf, _, }; - pub const SYNCEN = enum(u2) { - /// audio sub-block in asynchronous mode - Asynchronous = 0x0, - /// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode - Internal = 0x1, - /// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode - External = 0x2, - _, + pub const RES = enum(u2) { + /// 12-bit resolution + Bits12 = 0x0, + /// 10-bit resolution + Bits10 = 0x1, + /// 8-bit resolution + Bits8 = 0x2, + /// 6-bit resolution + Bits6 = 0x3, }; - pub const WCKCFG = enum(u1) { - /// Clock configuration is correct - Correct = 0x0, - /// Clock configuration does not respect the rule concerning the frame length specification - Wrong = 0x1, + pub const SAMPLE_TIME = enum(u3) { + /// 4 ADC clock cycles + Cycles4 = 0x0, + /// 9 ADC clock cycles + Cycles9 = 0x1, + /// 16 ADC clock cycles + Cycles16 = 0x2, + /// 24 ADC clock cycles + Cycles24 = 0x3, + /// 48 ADC clock cycles + Cycles48 = 0x4, + /// 96 ADC clock cycles + Cycles96 = 0x5, + /// 192 ADC clock cycles + Cycles192 = 0x6, + /// 384 ADC clock cycles + Cycles384 = 0x7, }; - /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - pub const CH = extern struct { - /// Configuration register 1 + /// Analog-to-digital converter + pub const ADC = extern struct { + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of conversion + EOC: u1, + /// Injected channel end of conversion + JEOC: u1, + /// Injected channel start flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + /// Overrun + OVR: u1, + /// ADC ON status + ADONS: u1, + reserved8: u1, + /// Regular channel not ready + RCNR: u1, + /// Injected channel not ready + JCNR: u1, + padding: u22, + }), + /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - /// SAIx audio block mode immediately - MODE: packed union { - raw: u2, - value: MODE, + /// Analog watchdog channel select bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt enable + AWDIE: u1, + /// Interrupt enable for injected channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: u1, + /// Automatic injected group conversion + JAUTO: u1, + /// Discontinuous mode on regular channels + DISCEN: u1, + /// Discontinuous mode on injected channels + JDISCEN: u1, + /// Discontinuous mode channel count + DISCNUM: packed union { + raw: u3, + value: DISCNUM, }, - /// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. - PRTCFG: packed union { + /// Power down during the delay phase + PDD: u1, + /// Power down during the idle phase + PDI: u1, + reserved22: u4, + /// Analog watchdog enable on injected channels + JAWDEN: u1, + /// Analog watchdog enable on regular channels + AWDEN: u1, + /// Resolution + RES: packed union { raw: u2, - value: PRTCFG, - }, - reserved5: u1, - /// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. - DS: packed union { - raw: u3, - value: DS, + value: RES, }, - /// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. - LSBFIRST: packed union { + /// Overrun interrupt enable + OVRIE: u1, + padding: u5, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + /// ADC configuration + ADC_CFG: packed union { raw: u1, - value: LSBFIRST, + value: ADC_CFG, }, - /// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. - CKSTR: packed union { - raw: u1, - value: CKSTR, + reserved4: u1, + /// Delay selection + DELS: packed union { + raw: u3, + value: DELS, }, - /// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. - SYNCEN: packed union { - raw: u2, - value: SYNCEN, + reserved8: u1, + /// Direct memory access mode + DMA: u1, + /// DMA disable selection + DDS: u1, + /// End of conversion selection + EOCS: u1, + /// Data alignment + ALIGN: u1, + reserved16: u4, + /// External event select for injected group + JEXTSEL: packed union { + raw: u4, + value: JEXTSEL, }, - /// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. - MONO: packed union { - raw: u1, - value: MONO, + /// External trigger enable for injected channels + JEXTEN: packed union { + raw: u2, + value: EXTEN, }, - /// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. - OUTDRIV: packed union { - raw: u1, - value: OUTDRIV, + /// Start conversion of injected channels + JSWSTART: u1, + reserved24: u1, + /// External event select for regular group + EXTSEL: packed union { + raw: u4, + value: EXTSEL, }, - reserved16: u2, - /// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. - SAIEN: u1, - /// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. - DMAEN: u1, - reserved19: u1, - /// No fixed divider between MCLK and FS - NODIV: packed union { - raw: u1, - value: NODIV, + /// External trigger enable for regular channels + EXTEN: packed union { + raw: u2, + value: EXTEN, }, - /// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: - MCKDIV: u4, - padding: u8, + /// Start conversion of regular channels + SWSTART: u1, + padding: u1, }), - /// Configuration register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// FIFO threshold. This bit is set and cleared by software. - FTH: packed union { + /// sample time register 1 + SMPR1: mmio.Mmio(packed struct(u32) { + /// channel 20-29 sampling time selection + SMP: packed union { raw: u3, - value: FTH, - }, - /// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. - FFLUSH: u1, - /// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. - TRIS: u1, - /// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. - MUTE: u1, - /// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. - MUTEVAL: packed union { - raw: u1, - value: MUTEVAL, + value: SAMPLE_TIME, }, - /// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. - MUTECNT: u6, - /// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. - CPL: packed union { - raw: u1, - value: CPL, + padding: u29, + }), + /// sample time register 2 + SMPR2: mmio.Mmio(packed struct(u32) { + /// channel 10-19 sampling time selection + SMP: packed union { + raw: u3, + value: SAMPLE_TIME, }, - /// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. - COMP: packed union { - raw: u2, - value: COMP, + padding: u29, + }), + /// sample time register 3 + SMPR3: mmio.Mmio(packed struct(u32) { + /// channel 0-9 sampling time selection + SMP: packed union { + raw: u3, + value: SAMPLE_TIME, }, + padding: u29, + }), + /// injected channel data offset register 1 + JOFR1: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET1: u12, + padding: u20, + }), + /// injected channel data offset register 2 + JOFR2: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET2: u12, + padding: u20, + }), + /// injected channel data offset register 3 + JOFR3: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET3: u12, + padding: u20, + }), + /// injected channel data offset register 4 + JOFR4: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET4: u12, + padding: u20, + }), + /// watchdog higher threshold register + HTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog higher threshold + HT: u12, + padding: u20, + }), + /// watchdog lower threshold register + LTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog lower threshold + LT: u12, + padding: u20, + }), + /// regular sequence register 1 + SQR1: mmio.Mmio(packed struct(u32) { + /// 25th-29th conversion in regular sequence + SQ: u5, + reserved20: u15, + /// Regular channel sequence length + L: u4, + padding: u8, + }), + /// regular sequence register 2 + SQR2: mmio.Mmio(packed struct(u32) { + /// 19th-24th conversion in regular sequence + SQ: u5, + padding: u27, + }), + /// regular sequence register 3 + SQR3: mmio.Mmio(packed struct(u32) { + /// 13th-18th conversion in regular sequence + SQ: u5, + padding: u27, + }), + /// regular sequence register 4 + SQR4: mmio.Mmio(packed struct(u32) { + /// 7th-12th conversion in regular sequence + SQ: u5, + padding: u27, + }), + /// regular sequence register 5 + SQR5: mmio.Mmio(packed struct(u32) { + /// 1st-6th conversion in regular sequence + SQ: u5, + padding: u27, + }), + /// injected sequence register + JSQR: mmio.Mmio(packed struct(u32) { + /// 1st conversion in injected sequence + JSQ1: u5, + /// 2nd conversion in injected sequence + JSQ2: u5, + /// 3rd conversion in injected sequence + JSQ3: u5, + /// 4th conversion in injected sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding: u10, + }), + /// injected data register x1 + JDR1: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, padding: u16, }), - /// This register has no meaning in AC97 and SPDIF audio protocol - FRCR: mmio.Mmio(packed struct(u32) { - /// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. - FRL: u8, - /// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. - FSALL: u7, - reserved16: u1, - /// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. - FSDEF: u1, - /// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - FSPOL: packed union { - raw: u1, - value: FSPOL, - }, - /// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - FSOFF: packed union { - raw: u1, - value: FSOFF, - }, - padding: u13, + /// injected data register 2 + JDR2: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, }), - /// This register has no meaning in AC97 and SPDIF audio protocol - SLOTR: mmio.Mmio(packed struct(u32) { - /// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - FBOFF: u5, - reserved6: u1, - /// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - SLOTSZ: packed union { - raw: u2, - value: SLOTSZ, - }, - /// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - NBSLOT: u4, - reserved16: u4, - /// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - SLOTEN: packed union { - raw: u16, - value: SLOTEN, - }, + /// injected data register 3 + JDR3: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, }), - /// Interrupt mask register 2 - IM: mmio.Mmio(packed struct(u32) { - /// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. - OVRUDRIE: u1, - /// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. - MUTEDETIE: u1, - /// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. - WCKCFGIE: u1, - /// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, - FREQIE: u1, - /// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. - CNRDYIE: u1, - /// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. - AFSDETIE: u1, - /// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. - LFSDETIE: u1, - padding: u25, + /// injected data register 4 + JDR4: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. - OVRUDR: u1, - /// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. - MUTEDET: u1, - /// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. - WCKCFG: packed union { - raw: u1, - value: WCKCFG, - }, - /// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. - FREQ: u1, - /// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. - CNRDY: packed union { - raw: u1, - value: CNRDY, - }, - /// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. - AFSDET: u1, - /// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register - LFSDET: u1, - reserved16: u9, - /// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: - FLVL: packed union { + /// regular data register + DR: mmio.Mmio(packed struct(u32) { + /// Regular data + rdata: u16, + padding: u16, + }), + /// sample time register 0 + SMPR0: mmio.Mmio(packed struct(u32) { + /// channel 30-31 sampling time selection + SMP: packed union { raw: u3, - value: FLVL, + value: SAMPLE_TIME, }, - padding: u13, + padding: u29, }), - /// Clear flag register - CLRFR: mmio.Mmio(packed struct(u32) { - /// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. - COVRUDR: u1, - /// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. - CMUTEDET: u1, - /// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. - CWCKCFG: u1, - reserved4: u1, - /// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. - CCNRDY: u1, - /// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. - CAFSDET: u1, - /// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. - CLFSDET: u1, + reserved768: [672]u8, + /// ADC common status register + CSR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog flag of the ADC + AWD1: u1, + /// End of conversion of the ADC + EOC1: u1, + /// Injected channel end of conversion of the ADC + JEOC1: u1, + /// Injected channel Start flag of the ADC + JSTRT1: u1, + /// Regular channel Start flag of the ADC + STRT1: u1, + /// Overrun flag of the ADC + OVR1: u1, + /// ADON Status of ADC1 + ADONS1: u1, padding: u25, }), - /// Data register - DR: mmio.Mmio(packed struct(u32) { - /// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. - DATA: u32, + /// ADC common control register + CCR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// ADC prescaler + ADCPRE: u2, + reserved23: u5, + /// Temperature sensor and VREFINT enable + TSVREFE: u1, + padding: u8, }), }; - - /// Serial audio interface - pub const SAI = extern struct { - reserved4: [4]u8, - /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - CH: u32, - }; }; - pub const pwr_f7 = struct { - pub const PDDS = enum(u1) { - /// Enter Stop mode when the CPU enters deepsleep - STOP_MODE = 0x0, - /// Enter Standby mode when the CPU enters deepsleep - STANDBY_MODE = 0x1, + pub const adc_f3_v2 = struct { + pub const DISCNUM = enum(u3) { + /// 1 conversions are discontinued and the conversion is carried out on one channel + DISCNUM_1 = 0x0, + /// 2 conversion is discontinued and the conversions are carried out on 2 channels + DISCNUM_2 = 0x1, + /// 3 conversions are discontinued and the conversions are carried out on 3 channels + DISCNUM_3 = 0x2, + /// 4 conversions are discontinued and the conversions are carried out on 4 channels + DISCNUM_4 = 0x3, + /// 5 conversions are discontinued and the conversions are carried out on 5 channels + DISCNUM_5 = 0x4, + /// 6 conversions are discontinued and the conversions are carried out on 6 channels + DISCNUM_6 = 0x5, + /// 7 conversions are discontinued and the conversions are carried out on 7 channels + DISCNUM_7 = 0x6, + /// 8 conversions are discontinued and the conversions are carried out on 8 channels + DISCNUM_8 = 0x7, }; - pub const VOS = enum(u2) { - /// Scale 3 mode - SCALE3 = 0x1, - /// Scale 2 mode - SCALE2 = 0x2, - /// Scale 1 mode (reset value) - SCALE1 = 0x3, - _, + pub const SAMPLE_TIME = enum(u3) { + /// 1.5 ADC clock cycles + Cycles1_5 = 0x0, + /// 7.5 ADC clock cycles + Cycles7_5 = 0x1, + /// 13.5 ADC clock cycles + Cycles13_5 = 0x2, + /// 28.5 ADC clock cycles + Cycles28_5 = 0x3, + /// 41.5 ADC clock cycles + Cycles41_5 = 0x4, + /// 55.5 ADC clock cycles + Cycles55_5 = 0x5, + /// 71.5 ADC clock cycles + Cycles71_5 = 0x6, + /// 239.5 ADC clock cycles + Cycles239_5 = 0x7, }; - /// Power control - pub const PWR = extern struct { - /// power control register - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power deep sleep - LPDS: u1, - /// Power down deepsleep - PDDS: packed union { - raw: u1, - value: PDDS, - }, - reserved3: u1, - /// Clear standby flag - CSBF: u1, - /// Power voltage detector enable - PVDE: u1, - /// PVD level selection - PLS: u3, - /// Disable backup domain write protection - DBP: u1, - /// Flash power down in Stop mode - FPDS: u1, - /// Low-power regulator in deepsleep under-drive mode - LPUDS: u1, - /// Main regulator in deepsleep under-drive mode - MRUDS: u1, - reserved13: u1, - /// ADCDC1 - ADCDC1: u1, - /// Regulator voltage scaling output selection - VOS: packed union { - raw: u2, - value: VOS, + /// Analog-to-Digital Converter + pub const ADC = extern struct { + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// analog watchdog flag + AWD: u1, + /// end of conversion + EOC: u1, + /// injected channel end of conversion + JEOC: u1, + /// injected channel start flag + JSTRT: u1, + /// regular channel start flag + STRT: u1, + /// overrun + OVR: u1, + padding: u26, + }), + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// analog watchdog channel select bits + AWDCH: u5, + /// interrupt enable for EOC + EOCIE: u1, + /// analog watchdog interrupt enable + AWDIE: u1, + /// interrupt enable for injected channels + JEOCIE: u1, + /// scan mode + SCAN: u1, + /// enable the watchdog on a single channel in scan mode + AWDSGL: u1, + /// automatic injected group conversion + JAUTO: u1, + /// discontinuous mode on regular channels + DISCEN: u1, + /// discontinuous mode on injected channels + JDISCEN: u1, + /// discontinuous mode channel count + DISCNUM: packed union { + raw: u3, + value: DISCNUM, }, - /// Over-drive enable - ODEN: u1, - /// Over-drive switching enabled - ODSWEN: u1, - /// Under-drive enable in stop mode - UDEN: u2, - padding: u12, + reserved22: u6, + /// analog watchdog enable on injected channels + JAWDEN: u1, + /// analog watchdog enable on regular channels + AWDEN: u1, + padding: u8, }), - /// power control/status register - CSR1: mmio.Mmio(packed struct(u32) { - /// Wakeup internal flag - WUIF: u1, - /// Standby flag - SBF: u1, - /// PVD output - PVDO: u1, - /// Backup regulator ready - BRR: u1, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// A/D converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + /// A/D calibration + CAL: u1, + /// reset calibration + RSTCAL: u1, reserved8: u4, - /// Enable internal wakeup - EIWUP: u1, - /// Backup regulator enable - BRE: u1, - reserved14: u4, - /// Regulator voltage scaling output selection ready bit - VOSRDY: u1, - reserved16: u1, - /// Over-drive mode ready - ODRDY: u1, - /// Over-drive mode switching ready - ODSWRDY: u1, - /// Under-drive ready flag - UDRDY: u2, - padding: u12, + /// DMA disable selection (for single ADC mode) + DMA: u1, + reserved11: u2, + /// data alignment + ALIGN: u1, + /// external event select for injected group + JEXTSEL: u3, + /// external trigger conversion mode for injected channels + JEXTTRIG: u1, + reserved17: u1, + /// external event select for regular group + EXTSEL: u3, + /// external trigger conversion mode for regular channels + EXTTRIG: u1, + /// start conversion of injected channels + JSWSTART: u1, + /// start conversion of regular channels + SWSTART: u1, + /// temperature sensor and VREFINT enable + TSVREFE: u1, + padding: u8, }), - /// power control register - CR2: mmio.Mmio(packed struct(u32) { - /// Clear Wakeup Pin flag for PA0 - CWUPF: u1, - reserved8: u7, - /// Wakeup pin polarity bit for PA0 - WUPP: u1, - padding: u23, + /// sample time register 1 + SMPR1: mmio.Mmio(packed struct(u32) { + /// channel 10 sampling time selection + SMP10: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 11 sampling time selection + SMP11: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 12 sampling time selection + SMP12: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 13 sampling time selection + SMP13: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 14 sampling time selection + SMP14: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 15 sampling time selection + SMP15: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 16 sampling time selection + SMP16: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 17 sampling time selection + SMP17: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 18 sampling time selection + SMP18: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + padding: u5, }), - /// power control/status register - CSR2: mmio.Mmio(packed struct(u32) { - /// Wakeup Pin flag for PA0 - WUPF: u1, - reserved8: u7, - /// Enable Wakeup pin for PA0 - EWUP: u1, - padding: u23, + /// sample time register 2 + SMPR2: mmio.Mmio(packed struct(u32) { + /// channel 0 sampling time selection + SMP0: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 1 sampling time selection + SMP1: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 2 sampling time selection + SMP2: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 3 sampling time selection + SMP3: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 4 sampling time selection + SMP4: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 5 sampling time selection + SMP5: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 6 sampling time selection + SMP6: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 7 sampling time selection + SMP7: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 8 sampling time selection + SMP8: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + /// channel 9 sampling time selection + SMP9: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + padding: u2, + }), + /// injected channel data offset register 1 + JOFR1: mmio.Mmio(packed struct(u32) { + /// data offset for injected channel 1 + JOFFSET1: u12, + padding: u20, + }), + /// injected channel data offset register 2 + JOFR2: mmio.Mmio(packed struct(u32) { + /// data offset for injected channel 2 + JOFFSET2: u12, + padding: u20, + }), + /// injected channel data offset register 3 + JOFR3: mmio.Mmio(packed struct(u32) { + /// data offset for injected channel 3 + JOFFSET3: u12, + padding: u20, + }), + /// injected channel data offset register 4 + JOFR4: mmio.Mmio(packed struct(u32) { + /// data offset for injected channel 4 + JOFFSET4: u12, + padding: u20, + }), + /// watchdog higher threshold register + HTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog high threshold + HT: u12, + padding: u20, + }), + /// watchdog lower threshold register + LTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog low threshold + LT: u12, + padding: u20, + }), + /// regular sequence register 1 + SQR1: mmio.Mmio(packed struct(u32) { + /// 13th conversion in regular sequence + SQ13: u5, + /// 14th conversion in regular sequence + SQ14: u5, + /// 15th conversion in regular sequence + SQ15: u5, + /// 16th conversion in regular sequence + SQ16: u5, + /// regular channel sequence length + L: u4, + padding: u8, + }), + /// regular sequence register 2 + SQR2: mmio.Mmio(packed struct(u32) { + /// 7th conversion in regular sequence + SQ7: u5, + /// 8th conversion in regular sequence + SQ8: u5, + /// 9th conversion in regular sequence + SQ9: u5, + /// 10th conversion in regular sequence + SQ10: u5, + /// 11th conversion in regular sequence + SQ11: u5, + /// 12th conversion in regular sequence + SQ12: u5, + padding: u2, + }), + /// regular sequence register 3 + SQR3: mmio.Mmio(packed struct(u32) { + /// 1st conversion in regular sequence + SQ1: u5, + /// 2nd conversion in regular sequence + SQ2: u5, + /// 3rd conversion in regular sequence + SQ3: u5, + /// 4th conversion in regular sequence + SQ4: u5, + /// 5th conversion in regular sequence + SQ5: u5, + /// 6th conversion in regular sequence + SQ6: u5, + padding: u2, + }), + /// injected sequence register + JSQR: mmio.Mmio(packed struct(u32) { + /// 1st conversion in injected sequence + JSQ1: u5, + /// 2nd conversion in injected sequence + JSQ2: u5, + /// 3rd conversion in injected sequence + JSQ3: u5, + /// 4th conversion in injected sequence + JSQ4: u5, + /// injected sequence length + JL: u2, + padding: u10, + }), + /// injected data register 1 + JDR1: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA1: u16, + padding: u16, + }), + /// injected data register 2 + JDR2: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA2: u16, + padding: u16, + }), + /// injected data register 3 + JDR3: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA3: u16, + padding: u16, + }), + /// injected data register 4 + JDR4: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA4: u16, + padding: u16, + }), + /// regular data register + DR: mmio.Mmio(packed struct(u32) { + /// Regular data + DATA: u16, + padding: u16, }), }; }; - pub const comp_v1 = struct { - pub const BLANKSEL = enum(u5) { - None = 0x0, - /// TIM1 OC4 - Tim1Oc4 = 0x1, - /// TIM1 OC5 - Tim1Oc5 = 0x2, - /// TIM2 OC3 - Tim2Oc3 = 0x4, - /// TIM3 OC3 - Tim3Oc3 = 0x8, - /// TIM15 OC2 - Tim15Oc2 = 0x10, - _, - }; - - pub const HYST = enum(u2) { - None = 0x0, - Low = 0x1, - Medium = 0x2, - High = 0x3, + pub const adc_g0 = struct { + pub const DMACFG = enum(u1) { + /// DMA One Shot mode selected + OneShot = 0x0, + /// DMA Circular mode selected + Circular = 0x1, }; - pub const POLARITY = enum(u1) { - NonInverted = 0x0, - Inverted = 0x1, + pub const RES = enum(u2) { + /// 12-bit resolution + Bits12 = 0x0, + /// 10-bit resolution + Bits10 = 0x1, + /// 8-bit resolution + Bits8 = 0x2, + /// 6-bit resolution + Bits6 = 0x3, }; - pub const PWRMODE = enum(u2) { - HighSpeed = 0x0, - MediumSpeed = 0x1, - _, + pub const SAMPLE_TIME = enum(u3) { + /// 1.5 ADC cycles + Cycles1_5 = 0x0, + /// 3.5 ADC cycles + Cycles3_5 = 0x1, + /// 7.5 ADC cycles + Cycles7_5 = 0x2, + /// 12.5 ADC cycles + Cycles12_5 = 0x3, + /// 19.5 ADC cycles + Cycles19_5 = 0x4, + /// 39.5 ADC cycles + Cycles39_5 = 0x5, + /// 79.5 ADC cycles + Cycles79_5 = 0x6, + /// 160.5 ADC cycles + Cycles160_5 = 0x7, }; - /// Comparator v1. (RM0444 18) - pub const COMP = extern struct { - /// Comparator control and status register. - CSR: mmio.Mmio(packed struct(u32) { - /// COMP enable bit. - EN: u1, - reserved4: u3, - /// Comparator signal selector for inverting input INM. - INMSEL: u4, - /// Comparator signal selector for non-inverting input INP. - INPSEL: u2, + /// Analog to Digital Converter + pub const ADC = extern struct { + /// ADC interrupt and status register + ISR: mmio.Mmio(packed struct(u32) { + /// ADC ready flag + ADRDY: u1, + /// ADC group regular end of sampling flag + EOSMP: u1, + /// ADC group regular end of unitary conversion flag + EOC: u1, + /// ADC group regular end of sequence conversions flag + EOS: u1, + /// ADC group regular overrun flag + OVR: u1, + reserved7: u2, + /// ADC analog watchdog 1 flag + AWD1: u1, + /// ADC analog watchdog 2 flag + AWD2: u1, + /// ADC analog watchdog 3 flag + AWD3: u1, reserved11: u1, - /// Comparator non-inverting input selector for window mode. - WINMODE: u1, - reserved14: u2, - /// Comparator output selector. - WINOUT: u1, - /// Comparator polarity selector. - POLARITY: packed union { + /// End Of Calibration flag + EOCAL: u1, + reserved13: u1, + /// Channel Configuration Ready flag + CCRDY: u1, + padding: u18, + }), + /// ADC interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// ADC ready interrupt + ADRDYIE: u1, + /// ADC group regular end of sampling interrupt + EOSMPIE: u1, + /// ADC group regular end of unitary conversion interrupt + EOCIE: u1, + /// ADC group regular end of sequence conversions interrupt + EOSIE: u1, + /// ADC group regular overrun interrupt + OVRIE: u1, + reserved7: u2, + /// ADC analog watchdog 1 interrupt + AWD1IE: u1, + /// ADC analog watchdog 2 interrupt + AWD2IE: u1, + /// ADC analog watchdog 3 interrupt + AWD3IE: u1, + reserved11: u1, + /// End of calibration interrupt enable + EOCALIE: u1, + reserved13: u1, + /// Channel Configuration Ready Interrupt enable + CCRDYIE: u1, + padding: u18, + }), + /// ADC control register + CR: mmio.Mmio(packed struct(u32) { + /// ADC enable + ADEN: u1, + /// ADC disable + ADDIS: u1, + /// ADC group regular conversion start + ADSTART: u1, + reserved4: u1, + /// ADC group regular conversion stop + ADSTP: u1, + reserved28: u23, + /// ADC voltage regulator enable + ADVREGEN: u1, + reserved31: u2, + /// ADC calibration + ADCAL: u1, + }), + /// ADC configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// ADC DMA transfer enable + DMAEN: u1, + /// Direct memory access configuration + DMACFG: packed union { raw: u1, - value: POLARITY, + value: DMACFG, }, - /// Comparator hysteresis selector. - HYST: packed union { + /// Scan sequence direction + SCANDIR: u1, + /// ADC data resolution + RES: packed union { raw: u2, - value: HYST, + value: RES, }, - /// Comparator power mode selector. - PWRMODE: packed union { - raw: u2, - value: PWRMODE, + /// ADC data alignement + ALIGN: u1, + /// ADC group regular external trigger source + EXTSEL: u3, + reserved10: u1, + /// ADC group regular external trigger polarity + EXTEN: u2, + /// ADC group regular overrun configuration + OVRMOD: u1, + /// Continuous conversion + CONT: u1, + /// Wait conversion mode + WAIT: u1, + /// Auto-off mode + AUTOFF: u1, + /// ADC group regular sequencer discontinuous mode + DISCEN: u1, + reserved21: u4, + /// Mode selection of the ADC_CHSELR register + CHSELRMOD: u1, + /// ADC analog watchdog 1 monitoring a single channel or all channels + AWD1SGL: u1, + /// ADC analog watchdog 1 enable on scope ADC group regular + AWD1EN: u1, + reserved26: u2, + /// ADC analog watchdog 1 monitored channel selection + AWDCH1CH: u5, + padding: u1, + }), + /// ADC configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// ADC oversampler enable on scope ADC group regular + OVSE: u1, + reserved2: u1, + /// ADC oversampling ratio + OVSR: u3, + /// ADC oversampling shift + OVSS: u4, + /// ADC oversampling discontinuous mode (triggered mode) for ADC group regular + TOVS: u1, + reserved29: u19, + /// Low frequency trigger mode enable + LFTRIG: u1, + /// ADC clock mode + CKMODE: u2, + }), + /// ADC sampling time register + SMPR: mmio.Mmio(packed struct(u32) { + /// Sampling time selection + SMP1: packed union { + raw: u3, + value: SAMPLE_TIME, }, - /// Comparator blanking source selector. - BLANKSEL: packed union { - raw: u5, - value: BLANKSEL, + reserved4: u1, + /// Sampling time selection + SMP2: packed union { + raw: u3, + value: SAMPLE_TIME, }, - reserved30: u5, - /// Comparator output status. (READ ONLY) - VALUE_DO_NOT_SET: u1, - /// CSR register lock. - LOCK: u1, + reserved8: u1, + /// Channel sampling time selection + SMPSEL: u1, + padding: u23, + }), + reserved32: [8]u8, + /// watchdog threshold register + AWD1TR: mmio.Mmio(packed struct(u32) { + /// ADC analog watchdog 1 threshold low + LT1: u12, + reserved16: u4, + /// ADC analog watchdog 1 threshold high + HT1: u12, + padding: u4, + }), + /// watchdog threshold register + AWD2TR: mmio.Mmio(packed struct(u32) { + /// ADC analog watchdog 2 threshold low + LT2: u12, + reserved16: u4, + /// ADC analog watchdog 2 threshold high + HT2: u12, + padding: u4, + }), + /// channel selection register + CHSELR: mmio.Mmio(packed struct(u32) { + /// Channel-x selection + CHSEL: u19, + padding: u13, + }), + /// watchdog threshold register + AWD3TR: mmio.Mmio(packed struct(u32) { + /// ADC analog watchdog 3 threshold high + LT3: u12, + reserved16: u4, + /// ADC analog watchdog 3 threshold high + HT3: u12, + padding: u4, + }), + reserved64: [16]u8, + /// ADC group regular conversion data register + DR: mmio.Mmio(packed struct(u32) { + /// ADC group regular conversion data + regularDATA: u16, + padding: u16, + }), + reserved160: [92]u8, + /// ADC analog watchdog 2 configuration register + AWD2CR: mmio.Mmio(packed struct(u32) { + /// ADC analog watchdog 2 monitored channel selection + AWD2CH: u19, + padding: u13, + }), + /// ADC analog watchdog 3 configuration register + AWD3CR: mmio.Mmio(packed struct(u32) { + /// ADC analog watchdog 3 monitored channel selection + AWD3CH: u19, + padding: u13, + }), + reserved180: [12]u8, + /// ADC calibration factors register + CALFACT: mmio.Mmio(packed struct(u32) { + /// ADC calibration factor in single-ended mode + CALFACT: u7, + padding: u25, + }), + reserved776: [592]u8, + /// ADC common control register + CCR: mmio.Mmio(packed struct(u32) { + reserved18: u18, + /// ADC prescaler + PRESC: u4, + /// VREFINT enable + VREFEN: u1, + /// Temperature sensor enable + TSEN: u1, + /// VBAT enable + VBATEN: u1, + padding: u7, + }), + reserved984: [204]u8, + /// Hardware Configuration Register + HWCFGR6: mmio.Mmio(packed struct(u32) { + /// Input channel mapping + CHMAP20: u5, + reserved8: u3, + /// Input channel mapping + CHMAP21: u5, + reserved16: u3, + /// Input channel mapping + CHMAP22: u5, + reserved24: u3, + /// Input channel mapping + CHMAP23: u5, + padding: u3, + }), + /// Hardware Configuration Register + HWCFGR5: mmio.Mmio(packed struct(u32) { + /// Input channel mapping + CHMAP19: u5, + reserved8: u3, + /// Input channel mapping + CHMAP18: u5, + reserved16: u3, + /// Input channel mapping + CHMAP17: u5, + reserved24: u3, + /// Input channel mapping + CHMAP16: u5, + padding: u3, + }), + /// Hardware Configuration Register + HWCFGR4: mmio.Mmio(packed struct(u32) { + /// Input channel mapping + CHMAP15: u5, + reserved8: u3, + /// Input channel mapping + CHMAP14: u5, + reserved16: u3, + /// Input channel mapping + CHMAP13: u5, + reserved24: u3, + /// Input channel mapping + CHMAP12: u5, + padding: u3, + }), + /// Hardware Configuration Register + HWCFGR3: mmio.Mmio(packed struct(u32) { + /// Input channel mapping + CHMAP11: u5, + reserved8: u3, + /// Input channel mapping + CHMAP10: u5, + reserved16: u3, + /// Input channel mapping + CHMAP9: u5, + reserved24: u3, + /// Input channel mapping + CHMAP8: u5, + padding: u3, + }), + /// Hardware Configuration Register + HWCFGR2: mmio.Mmio(packed struct(u32) { + /// Input channel mapping + CHMAP7: u5, + reserved8: u3, + /// Input channel mapping + CHMAP6: u5, + reserved16: u3, + /// Input channel mapping + CHMAP5: u5, + reserved24: u3, + /// Input channel mapping + CHMAP4: u5, + padding: u3, + }), + /// Hardware Configuration Register + HWCFGR1: mmio.Mmio(packed struct(u32) { + /// Input channel mapping + CHMAP3: u5, + reserved8: u3, + /// Input channel mapping + CHMAP2: u5, + reserved16: u3, + /// Input channel mapping + CHMAP1: u5, + reserved24: u3, + /// Input channel mapping + CHMAP0: u5, + padding: u3, + }), + /// Hardware Configuration Register + HWCFGR0: mmio.Mmio(packed struct(u32) { + /// NUM_CHAN_24 + NUM_CHAN_24: u4, + /// Extra analog watchdog + EXTRA_AWDS: u4, + /// Oversampling + OVS: u4, + padding: u20, + }), + /// EXTI IP Version register + VERR: mmio.Mmio(packed struct(u32) { + /// Minor Revision number + MINREV: u4, + /// Major Revision number + MAJREV: u4, + padding: u24, + }), + /// EXTI Identification register + IPIDR: mmio.Mmio(packed struct(u32) { + /// IP Identification + IPID: u32, + }), + /// EXTI Size ID register + SIDR: mmio.Mmio(packed struct(u32) { + /// Size Identification + SID: u32, }), }; }; - pub const rtc_v2f0 = struct { - pub const ALRMR_MSK = enum(u1) { - /// Alarm set if the date/day match - ToMatch = 0x0, - /// Date/day don’t care in Alarm comparison - NotMatch = 0x1, - }; - - pub const ALRMR_PM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, - }; - - pub const ALRMR_WDSEL = enum(u1) { - /// DU[3:0] represents the date units - DateUnits = 0x0, - /// DU[3:0] represents the week day. DT[1:0] is don’t care - WeekDay = 0x1, - }; - - pub const AMPM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, - }; - - pub const CALP = enum(u1) { - /// No RTCCLK pulses are added - NoChange = 0x0, - /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - IncreaseFreq = 0x1, + pub const adc_g4 = struct { + pub const ADCALDIF = enum(u1) { + /// Calibration for single-ended mode + SingleEnded = 0x0, + /// Calibration for differential mode + Differential = 0x1, }; - pub const CALW16 = enum(u1) { - /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 - Sixteen_Second = 0x1, + pub const ADSTP = enum(u1) { + /// Stop conversion of channel + Stop = 0x1, _, }; - pub const CALW8 = enum(u1) { - /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected - Eight_Second = 0x1, - _, + pub const AWD1SGL = enum(u1) { + /// Analog watchdog 1 enabled on all channels + All = 0x0, + /// Analog watchdog 1 enabled on single channel selected in AWD1CH + Single = 0x1, }; - pub const COSEL = enum(u1) { - /// Calibration output is 512 Hz (with default prescaler setting) - CalFreq_512Hz = 0x0, - /// Calibration output is 1 Hz (with default prescaler setting) - CalFreq_1Hz = 0x1, + pub const DIFSEL = enum(u1) { + /// Input channel is configured in single-ended mode + SingleEnded = 0x0, + /// Input channel is configured in differential mode + Differential = 0x1, }; - pub const FMT = enum(u1) { - /// 24 hour/day format - Twenty_Four_Hour = 0x0, - /// AM/PM hour format - AM_PM = 0x1, + pub const DMACFG = enum(u1) { + /// DMA One Shot mode selected + OneShot = 0x0, + /// DMA Circular mode selected + Circular = 0x1, }; - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Wakeup output enabled - Wakeup = 0x3, - _, + pub const DMAEN = enum(u1) { + /// DMA disable + Disable = 0x0, + /// DMA enable + Enable = 0x1, }; - pub const PCMODE = enum(u1) { - /// PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode - Floating = 0x0, - /// PCx is forced to push-pull output if LSE is disabled - PushPull = 0x1, + pub const EXTEN = enum(u2) { + /// Trigger detection disabled + Disabled = 0x0, + /// Trigger detection on the rising edge + RisingEdge = 0x1, + /// Trigger detection on the falling edge + FallingEdge = 0x2, + /// Trigger detection on both the rising and falling edges + BothEdges = 0x3, }; - pub const PCVALUE = enum(u1) { - /// If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low - Low = 0x0, - /// If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high - High = 0x1, + pub const JEXTEN = enum(u2) { + /// Trigger detection disabled + Disabled = 0x0, + /// Trigger detection on the rising edge + RisingEdge = 0x1, + /// Trigger detection on the falling edge + FallingEdge = 0x2, + /// Trigger detection on both the rising and falling edges + BothEdges = 0x3, }; - pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - Low = 0x1, + pub const JQM = enum(u1) { + /// JSQR Mode 0: Queue maintains the last written configuration into JSQR + Mode0 = 0x0, + /// JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence + Mode1 = 0x1, }; - pub const TAMPFLT = enum(u2) { - /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - Immediate = 0x0, - /// Tamper event is activated after 2 consecutive samples at the active level - Samples2 = 0x1, - /// Tamper event is activated after 4 consecutive samples at the active level - Samples4 = 0x2, - /// Tamper event is activated after 8 consecutive samples at the active level - Samples8 = 0x3, + pub const OVRMOD = enum(u1) { + /// Preserve DR register when an overrun is detected + Preserve = 0x0, + /// Overwrite DR register when an overrun is detected + Overwrite = 0x1, }; - pub const TAMPFREQ = enum(u3) { - /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - Div32768 = 0x0, - /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - Div16384 = 0x1, - /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - Div8192 = 0x2, - /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - Div4096 = 0x3, - /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - Div2048 = 0x4, - /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - Div1024 = 0x5, - /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - Div512 = 0x6, - /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - Div256 = 0x7, + pub const RES = enum(u2) { + /// 12-bit resolution + Bits12 = 0x0, + /// 10-bit resolution + Bits10 = 0x1, + /// 8-bit resolution + Bits8 = 0x2, + /// 6-bit resolution + Bits6 = 0x3, }; - pub const TAMPPRCH = enum(u2) { - /// 1 RTCCLK cycle - Cycles1 = 0x0, - /// 2 RTCCLK cycles - Cycles2 = 0x1, - /// 4 RTCCLK cycles - Cycles4 = 0x2, - /// 8 RTCCLK cycles - Cycles8 = 0x3, + pub const ROVSM = enum(u1) { + /// Oversampling is temporary stopped and continued after injection sequence + Continued = 0x0, + /// Oversampling is aborted and resumed from start after injection sequence + Resumed = 0x1, }; - pub const TAMPPUDIS = enum(u1) { - /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - Enabled = 0x0, - /// Disable precharge of RTC_TAMPx pins - Disabled = 0x1, + pub const SAMPLE_TIME = enum(u3) { + /// 2.5 clock cycles + Cycles2_5 = 0x0, + /// 6.5 clock cycles + Cycles6_5 = 0x1, + /// 12.5 clock cycles + Cycles12_5 = 0x2, + /// 24.5 clock cycles + Cycles24_5 = 0x3, + /// 47.5 clock cycles + Cycles47_5 = 0x4, + /// 92.5 clock cycles + Cycles92_5 = 0x5, + /// 247.5 clock cycles + Cycles247_5 = 0x6, + /// 640.5 clock cycles + Cycles640_5 = 0x7, }; - pub const TAMPTRG = enum(u1) { - /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. - RisingEdge = 0x0, - /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event - FallingEdge = 0x1, + pub const TROVS = enum(u1) { + /// All oversampled conversions for a channel are done consecutively following a trigger + Automatic = 0x0, + /// Each oversampled conversion for a channel needs a new trigger + Triggered = 0x1, }; - pub const TSEDGE = enum(u1) { - /// RTC_TS input rising edge generates a time-stamp event - RisingEdge = 0x0, - /// RTC_TS input falling edge generates a time-stamp event - FallingEdge = 0x1, - }; - - pub const WUCKSEL = enum(u3) { - /// RTC/16 clock is selected - Div16 = 0x0, - /// RTC/8 clock is selected - Div8 = 0x1, - /// RTC/4 clock is selected - Div4 = 0x2, - /// RTC/2 clock is selected - Div2 = 0x3, - /// ck_spre (usually 1 Hz) clock is selected - ClockSpare = 0x4, - /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - ClockSpareWithOffset = 0x6, - _, - }; - - /// Real-time clock - pub const RTC = extern struct { - /// Time register - TR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, + /// Analog to Digital Converter + pub const ADC = extern struct { + /// interrupt and status register + ISR: mmio.Mmio(packed struct(u32) { + /// ready flag + ADRDY: u1, + /// group regular end of sampling flag + EOSMP: u1, + /// group regular end of unitary conversion flag + EOC: u1, + /// group regular end of sequence conversions flag + EOS: u1, + /// group regular overrun flag + OVR: u1, + /// group injected end of unitary conversion flag + JEOC: u1, + /// group injected end of sequence conversions flag + JEOS: u1, + /// analog watchdog 1 flag + AWD1: u1, + /// analog watchdog 2 flag + AWD2: u1, + /// analog watchdog 3 flag + AWD3: u1, + /// group injected contexts queue overflow flag + JQOVF: u1, + padding: u21, }), - /// Date register - DR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding: u8, + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// ready interrupt + ADRDYIE: u1, + /// group regular end of sampling interrupt + EOSMPIE: u1, + /// group regular end of unitary conversion interrupt + EOCIE: u1, + /// group regular end of sequence conversions interrupt + EOSIE: u1, + /// group regular overrun interrupt + OVRIE: u1, + /// group injected end of unitary conversion interrupt + JEOCIE: u1, + /// group injected end of sequence conversions interrupt + JEOSIE: u1, + /// analog watchdog 1 interrupt + AWD1IE: u1, + /// analog watchdog 2 interrupt + AWD2IE: u1, + /// analog watchdog 3 interrupt + AWD3IE: u1, + /// group injected contexts queue overflow interrupt + JQOVFIE: u1, + padding: u21, }), - /// Control register + /// control register CR: mmio.Mmio(packed struct(u32) { - /// Wakeup clock selection - WUCKSEL: packed union { - raw: u3, - value: WUCKSEL, - }, - /// Timestamp event active edge - TSEDGE: packed union { - raw: u1, - value: TSEDGE, - }, - /// Reference clock detection enable (50 or 60 Hz) - REFCKON: u1, - /// Bypass the shadow registers - BYPSHAD: u1, - /// Hour format - FMT: packed union { + /// enable + ADEN: u1, + /// disable + ADDIS: u1, + /// group regular conversion start + ADSTART: u1, + /// group injected conversion start + JADSTART: u1, + /// group regular conversion stop + ADSTP: packed union { raw: u1, - value: FMT, + value: ADSTP, }, - reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, - /// Wakeup timer enable - WUTE: u1, - /// Timestamp enable - TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, - /// Wakeup timer interrupt enable - WUTIE: u1, - /// Timestamp interrupt enable - TSIE: u1, - /// Add 1 hour (summer time change) - ADD1H: u1, - /// Subtract 1 hour (winter time change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output selection - COSEL: packed union { + /// group injected conversion stop + JADSTP: packed union { raw: u1, - value: COSEL, + value: ADSTP, }, - /// Output polarity - POL: packed union { + reserved28: u22, + /// voltage regulator enable + ADVREGEN: u1, + /// deep power down enable + DEEPPWD: u1, + /// differential mode for calibration + ADCALDIF: packed union { raw: u1, - value: POL, - }, - /// Output selection - OSEL: packed union { - raw: u2, - value: OSEL, + value: ADCALDIF, }, - /// Calibration output enable - COE: u1, - padding: u8, - }), - /// Initialization and status register - ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, - /// Wakeup timer write enabled - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Enter Initialization mode - INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, - /// Wakeup timer flag - WUTF: u1, - /// Timestamp flag - TSF: u1, - /// Timestamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, - /// Recalibration pending flag - RECALPF: u1, - padding: u15, - }), - /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, - padding: u9, - }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, - padding: u16, + /// calibration + ADCAL: u1, }), - reserved28: [4]u8, - /// Alarm register - ALRMR: [1]mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm seconds mask - MSK1: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm minutes mask - MSK2: packed union { + /// configuration register 1 + CFGR: mmio.Mmio(packed struct(u32) { + /// Direct memory access configuration + DMACFG: packed union { raw: u1, - value: ALRMR_MSK, + value: DMACFG, }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: ALRMR_PM, + reserved3: u2, + /// data resolution + RES: packed union { + raw: u2, + value: RES, }, - /// Alarm hours mask - MSK3: packed union { - raw: u1, - value: ALRMR_MSK, + /// external trigger selection for regular group + EXTSEL: u5, + /// external trigger enable and polarity selection for regular channels + EXTEN: packed union { + raw: u2, + value: EXTEN, }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { + /// overrun mode + OVRMOD: packed union { raw: u1, - value: ALRMR_WDSEL, + value: OVRMOD, }, - /// Alarm date mask - MSK4: packed union { + /// Continuous conversion + CONT: u1, + /// delayed conversion mode + AUTDLY: u1, + /// data alignment + ALIGN: u1, + /// discontinuous mode for regular channels + DISCEN: u1, + /// discontinuous mode channel count + DISCNUM: u3, + /// discontinuous mode on injected channels + JDISCEN: u1, + /// JSQR queue mode + JQM: packed union { raw: u1, - value: ALRMR_MSK, + value: JQM, }, - }), - reserved36: [4]u8, - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: u8, - padding: u24, - }), - /// Sub second register - SSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, - }), - /// Shift control register - SHIFTR: mmio.Mmio(packed struct(u32) { - /// Subtract a fraction of a second - SUBFS: u15, - reserved31: u16, - /// Add one second - ADD1S: u1, - }), - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { + /// enable the watchdog 1 on a single channel or on all channels + AWD1SGL: packed union { raw: u1, - value: AMPM, + value: AWD1SGL, }, - padding: u9, - }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding: u16, - }), - /// Timestamp sub second register - TSSSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, + /// analog watchdog 1 enable on regular channels + AWD1EN: u1, + /// analog watchdog 1 enable on injected channels + JAWD1EN: u1, + /// automatic injected group conversion + JAUTO: u1, + /// analog watchdog 1 channel selection + AWD1CH: u5, + /// injected queue disable + JQDIS: u1, }), - /// Calibration register - CALR: mmio.Mmio(packed struct(u32) { - /// Calibration minus - CALM: u9, - reserved13: u4, - /// Use a 16-second calibration cycle period - CALW16: packed union { - raw: u1, - value: CALW16, - }, - /// Use an 8-second calibration cycle period - CALW8: packed union { + /// configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Regular Oversampling Enable + ROVSE: u1, + /// Injected Oversampling Enable + JOVSE: u1, + /// Oversampling ratio + OVSR: u3, + /// Oversampling shift + OVSS: u4, + /// Triggered Regular Oversampling + TROVS: packed union { raw: u1, - value: CALW8, + value: TROVS, }, - /// Increase frequency of RTC by 488.5 ppm - CALP: packed union { + /// Regular Oversampling mode + ROVSM: packed union { raw: u1, - value: CALP, + value: ROVSM, }, - padding: u16, + reserved16: u5, + /// Gain compensation mode + GCOMP: u1, + reserved25: u8, + /// Software trigger bit for sampling time control trigger mode + SWTRIG: u1, + /// Bulb sampling mode + BULB: u1, + /// Sampling time control trigger mode + SMPTRIG: u1, + padding: u4, }), - /// Tamper and alternate function configuration register - TAFCR: mmio.Mmio(packed struct(u32) { - /// Tamper detection enable - TAMPE: u1, - /// Active level for tamper - TAMPTRG: packed union { - raw: u1, - value: TAMPTRG, - }, - /// Tamper interrupt enable - TAMPIE: u1, - reserved7: u4, - /// Activate timestamp on tamper detection event - TAMPTS: u1, - /// Tamper sampling frequency - TAMPFREQ: packed union { + /// sampling time register 1 + SMPR: mmio.Mmio(packed struct(u32) { + /// channel n * 10 + x sampling time + SMP: packed union { raw: u3, - value: TAMPFREQ, - }, - /// Tamper filter count - TAMPFLT: packed union { - raw: u2, - value: TAMPFLT, - }, - /// Tamper precharge duration - TAMPPRCH: packed union { - raw: u2, - value: TAMPPRCH, - }, - /// Tamper pull-up disable - TAMPPUDIS: packed union { - raw: u1, - value: TAMPPUDIS, - }, - reserved18: u2, - /// PC13 value - PC13VALUE: packed union { - raw: u1, - value: PCVALUE, - }, - /// PC13 mode - PC13MODE: packed union { - raw: u1, - value: PCMODE, - }, - /// PC14 value - PC14VALUE: packed union { - raw: u1, - value: PCVALUE, - }, - /// PC14 mode - PC14MODE: packed union { - raw: u1, - value: PCMODE, - }, - /// PC15 value - PC15VALUE: packed union { - raw: u1, - value: PCVALUE, + value: SAMPLE_TIME, }, - /// PC15 mode - PC15MODE: packed union { - raw: u1, - value: PCMODE, + reserved31: u28, + /// Addition of one clock cycle to the sampling time + SMPPLUS: u1, + }), + /// sampling time register 2 + SMPR2: mmio.Mmio(packed struct(u32) { + /// channel n * 10 + x sampling time + SMP: packed union { + raw: u3, + value: SAMPLE_TIME, }, - padding: u8, + padding: u29, }), - /// Alarm sub second register - ALRMSSR: [1]mmio.Mmio(packed struct(u32) { - /// Sub seconds value - SS: u15, - reserved24: u9, - /// Mask the most-significant bits starting at this bit - MASKSS: u4, + reserved32: [4]u8, + /// analog watchdog threshold register 1 + TR1: mmio.Mmio(packed struct(u32) { + /// analog watchdog 1 lower threshold + LT1: u12, + /// analog watchdog filtering parameter + AWDFILT: u3, + reserved16: u1, + /// analog watchdog 1 higher threshold + HT1: u12, padding: u4, }), - reserved80: [8]u8, - /// Backup register - BKPR: [5]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, + /// analog watchdog threshold register 2 + TR2: mmio.Mmio(packed struct(u32) { + /// analog watchdog 2 lower threshold + LT2: u8, + reserved16: u8, + /// analog watchdog 2 higher threshold + HT2: u8, + padding: u8, }), - }; - }; - - pub const hash_v2 = struct { - /// Hash processor. - pub const HASH = extern struct { - /// control register. - CR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Initialize message digest calculation. - INIT: u1, - /// DMA enable. - DMAE: u1, - /// Data type selection. - DATATYPE: u2, - /// Mode selection. - MODE: u1, - /// Algorithm selection. - ALGO0: u1, - /// Number of words already pushed. - NBW: u4, - /// DIN not empty. - DINNE: u1, - /// Multiple DMA Transfers. - MDMAT: u1, - reserved16: u2, - /// Long key selection. - LKEY: u1, - reserved18: u1, - /// ALGO. - ALGO1: u1, - padding: u13, + /// analog watchdog threshold register 3 + TR3: mmio.Mmio(packed struct(u32) { + /// analog watchdog 3 lower threshold + LT3: u8, + reserved16: u8, + /// analog watchdog 3 higher threshold + HT3: u8, + padding: u8, }), - /// data input register. - DIN: u32, - /// start register. - STR: mmio.Mmio(packed struct(u32) { - /// Number of valid bits in the last word of the message. - NBLW: u5, - reserved8: u3, - /// Digest calculation. - DCAL: u1, - padding: u23, + reserved48: [4]u8, + /// group regular sequencer ranks register 1 + SQR1: mmio.Mmio(packed struct(u32) { + /// L + L: u4, + reserved6: u2, + /// group regular sequencer rank 1-4 + SQ: u5, + padding: u21, }), - /// digest registers. - HRA: [5]u32, - /// interrupt enable register. - IMR: mmio.Mmio(packed struct(u32) { - /// Data input interrupt enable. - DINIE: u1, - /// Digest calculation completion interrupt enable. - DCIE: u1, - padding: u30, + /// group regular sequencer ranks register 2 + SQR2: mmio.Mmio(packed struct(u32) { + /// group regular sequencer rank 5-9 + SQ: u5, + padding: u27, }), - /// status register. - SR: mmio.Mmio(packed struct(u32) { - /// Data input interrupt status. - DINIS: u1, - /// Digest calculation completion interrupt status. - DCIS: u1, - /// DMA Status. - DMAS: u1, - /// Busy bit. - BUSY: u1, - padding: u28, + /// group regular sequencer ranks register 3 + SQR3: mmio.Mmio(packed struct(u32) { + /// group regular sequencer rank 10-14 + SQ: u5, + padding: u27, }), - reserved248: [208]u8, - /// context swap registers. - CSR: [54]u32, - reserved784: [320]u8, - /// HASH digest register. - HR: [8]u32, - }; - }; - - pub const pwr_c0 = struct { - /// PWR address block description - pub const PWR = extern struct { - /// PWR control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection These bits select the low-power mode entered when CPU enters deepsleep mode. 1XX: Shutdown mode - LPMS: u3, - /// Flash memory powered down during Stop mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode. - FPD_STOP: u1, - reserved5: u1, - /// Flash memory powered down during Sleep mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Sleep mode. - FPD_SLP: u1, - padding: u26, + /// group regular sequencer ranks register 4 + SQR4: mmio.Mmio(packed struct(u32) { + /// group regular sequencer rank 15-16 + SQ: u5, + padding: u27, }), - reserved8: [4]u8, - /// PWR control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin - EWUP: u1, - reserved10: u9, - /// Apply pull-up and pull-down configuration This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. - APC: u1, - reserved15: u4, - /// Enable internal wakeup line When set, a rising edge on the internal wakeup line triggers a wakeup event. - EIWUL: u1, + /// group regular conversion data register + DR: mmio.Mmio(packed struct(u32) { + /// group regular conversion data + RDATA: u16, padding: u16, }), - /// PWR control register 4 - CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity - WP: u1, - padding: u31, + reserved76: [8]u8, + /// group injected sequencer register + JSQR: mmio.Mmio(packed struct(u32) { + /// group injected sequencer scan length + JL: u2, + /// group injected external trigger source + JEXTSEL: u5, + /// group injected external trigger polarity + JEXTEN: packed union { + raw: u2, + value: JEXTEN, + }, + /// group injected sequencer rank 1-4 + JSQ: u5, + padding: u18, }), - /// PWR status register 1 - SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag - WUF: u1, - reserved8: u7, - /// Standby/Shutdown flag This bit is set by hardware when the device enters Standby or Shutdown mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. - SBF: u1, - reserved15: u6, - /// Wakeup flag internal This bit is set when a wakeup condition is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. - WUFI: u1, + reserved96: [16]u8, + /// offset number 1-4 register + OFR: [4]mmio.Mmio(packed struct(u32) { + /// data offset + OFFSET: u12, + reserved24: u12, + /// Positive offset + OFFSETPOS: u1, + /// Saturation enable + SATEN: u1, + /// Channel selection for the data offset + OFFSET1_CH: u5, + /// Offset enable + OFFSET_EN: u1, + }), + reserved128: [16]u8, + /// group injected sequencer rank 1-4 register + JDR: [4]mmio.Mmio(packed struct(u32) { + /// group injected sequencer rank conversion data + JDATA: u16, padding: u16, }), - /// PWR status register 2 - SR2: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// Flash ready flag This bit is set by hardware to indicate when the Flash memory is ready to be accessed after wakeup from power-down. To place the Flash memory in power-down, set either FPD_SLP or FPD_STP bit. Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to Flash memory. - FLASH_RDY: u1, - padding: u24, + reserved160: [16]u8, + /// analog watchdog 2 configuration register + AWD2CR: mmio.Mmio(packed struct(u32) { + /// analog watchdog 2 channel selection + AWD2CH: u19, + padding: u13, }), - /// PWR status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear Wakeup flag - CWUF: u1, - reserved8: u7, - /// Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register. - CSBF: u1, - padding: u23, + /// analog watchdog 3 configuration register + AWD3CR: mmio.Mmio(packed struct(u32) { + /// analog watchdog 3 channel selection + AWD3CH: u19, + padding: u13, }), - reserved32: [4]u8, - /// PWR Port pull-up control register - PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, + reserved176: [8]u8, + /// channel differential or single-ended mode selection register + DIFSEL: mmio.Mmio(packed struct(u32) { + /// channel differential or single-ended mode for channel + DIFSEL: packed union { + raw: u1, + value: DIFSEL, + }, padding: u31, }), - /// PWR Port pull-down control register - PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// calibration factors register + CALFACT: mmio.Mmio(packed struct(u32) { + /// calibration factor in single-ended mode + CALFACT_S: u7, + reserved16: u9, + /// calibration factor in differential mode + CALFACT_D: u7, + padding: u9, + }), + reserved192: [8]u8, + /// Gain compensation register + GCOMP: mmio.Mmio(packed struct(u32) { + /// Gain compensation coefficient + GCOMPCOEFF: u14, + padding: u18, }), }; }; - pub const hsem_v2 = struct { - /// HSEM. - pub const HSEM = extern struct { - /// HSEM register HSEM_R%s HSEM_R31. - R: [32]mmio.Mmio(packed struct(u32) { - /// Semaphore ProcessID. - PROCID: u8, - /// Semaphore COREID. - COREID: u4, - reserved31: u19, - /// Lock indication. - LOCK: u1, - }), - /// HSEM Read lock register. - RLR: [32]mmio.Mmio(packed struct(u32) { - /// Semaphore ProcessID. - PROCID: u8, - /// Semaphore COREID. - COREID: u4, - reserved31: u19, - /// Lock indication. - LOCK: u1, - }), - /// HSEM Interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x enable bit. - ISE: u1, - padding: u31, - }), - /// HSEM Interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x clear bit. - ISC: u1, - padding: u31, - }), - /// HSEM Interrupt status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x status bit before enable (mask). - ISF: u1, - padding: u31, - }), - /// HSEM Masked interrupt status register. - MISR: mmio.Mmio(packed struct(u32) { - /// masked interrupt semaphore x status bit after enable (mask). - MISF: u1, - padding: u31, - }), - reserved320: [48]u8, - /// HSEM Clear register. - CR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// COREID of semaphores to be cleared. - COREID: u4, - reserved16: u4, - /// Semaphore clear Key. - KEY: u16, - }), - /// HSEM Interrupt clear register. - KEYR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Semaphore Clear Key. - KEY: u16, - }), + pub const adc_h5 = struct { + pub const ADCALDIF = enum(u1) { + /// Calibration for single-ended mode + SingleEnded = 0x0, + /// Calibration for differential mode + Differential = 0x1, }; - }; - pub const adc_v2 = struct { pub const ALIGN = enum(u1) { /// Right alignment Right = 0x0, @@ -307272,2190 +307551,1674 @@ pub const types = struct { Left = 0x1, }; - pub const AWDSGL = enum(u1) { - /// Analog watchdog enabled on all channels - AllChannels = 0x0, - /// Analog watchdog enabled on a single channel - SingleChannel = 0x1, - }; - - pub const DDS = enum(u1) { - /// No new DMA request is issued after the last transfer - Single = 0x0, - /// DMA requests are issued as long as data are converted and DMA=1 - Continuous = 0x1, + pub const AWD1SGL = enum(u1) { + /// Analog watchdog 1 enabled on all channels + All = 0x0, + /// Analog watchdog 1 enabled on single channel selected in AWD1CH + Single = 0x1, }; - pub const EOCS = enum(u1) { - /// The EOC bit is set at the end of each sequence of regular conversions - EachSequence = 0x0, - /// The EOC bit is set at the end of each regular conversion - EachConversion = 0x1, + pub const DMACFG = enum(u1) { + /// DMA One Shot mode selected + OneShot = 0x0, + /// DMA Circular mode selected + Circular = 0x1, }; pub const EXTEN = enum(u2) { - /// Trigger detection disabled + /// Hardware trigger detection disabled (conversions can be launched by software) Disabled = 0x0, - /// Trigger detection on the rising edge + /// Hardware trigger detection on the rising edge RisingEdge = 0x1, - /// Trigger detection on the falling edge + /// Hardware trigger detection on the falling edge FallingEdge = 0x2, - /// Trigger detection on both the rising and falling edges + /// Hardware trigger detection on both the rising and falling edge BothEdges = 0x3, }; - pub const JEXTEN = enum(u2) { - /// Trigger detection disabled - Disabled = 0x0, - /// Trigger detection on the rising edge - RisingEdge = 0x1, - /// Trigger detection on the falling edge - FallingEdge = 0x2, - /// Trigger detection on both the rising and falling edges - BothEdges = 0x3, + pub const JQM = enum(u1) { + /// JSQR Mode 0: Queue maintains the last written configuration into JSQR + Mode0 = 0x0, + /// JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence + Mode1 = 0x1, + }; + + pub const OFFSETPOS = enum(u1) { + /// Negative offset + Negative = 0x0, + /// Positive offset + Positive = 0x1, + }; + + pub const OVRMOD = enum(u1) { + /// Preserve DR register when an overrun is detected + Preserve = 0x0, + /// Overwrite DR register when an overrun is detected + Overwrite = 0x1, + }; + + pub const OVSR = enum(u3) { + x2 = 0x0, + x4 = 0x1, + x8 = 0x2, + x16 = 0x3, + x32 = 0x4, + x64 = 0x5, + x128 = 0x6, + x256 = 0x7, }; pub const RES = enum(u2) { - /// 12-bit (15 ADCCLK cycles) + /// 12-bit resolution Bits12 = 0x0, - /// 10-bit (13 ADCCLK cycles) + /// 10-bit resolution Bits10 = 0x1, - /// 8-bit (11 ADCCLK cycles) + /// 8-bit resolution Bits8 = 0x2, - /// 6-bit (9 ADCCLK cycles) + /// 6-bit resolution Bits6 = 0x3, }; + pub const ROVSM = enum(u1) { + /// Oversampling is temporary stopped and continued after injection sequence + Continued = 0x0, + /// Oversampling is aborted and resumed from start after injection sequence + Resumed = 0x1, + }; + pub const SAMPLE_TIME = enum(u3) { - /// 3 cycles - Cycles3 = 0x0, - /// 15 cycles - Cycles15 = 0x1, - /// 28 cycles - Cycles28 = 0x2, - /// 56 cycles - Cycles56 = 0x3, - /// 84 cycles - Cycles84 = 0x4, - /// 112 cycles - Cycles112 = 0x5, - /// 144 cycles - Cycles144 = 0x6, - /// 480 cycles - Cycles480 = 0x7, + /// 2.5 ADC clock cycles + Cycles2_5 = 0x0, + /// 6.5 ADC clock cycles + Cycles6_5 = 0x1, + /// 12.5 ADC clock cycles + Cycles12_5 = 0x2, + /// 24.5 ADC clock cycles + Cycles24_5 = 0x3, + /// 47.5 ADC clock cycles + Cycles47_5 = 0x4, + /// 92.5 ADC clock cycles + Cycles92_5 = 0x5, + /// 247.5 ADC clock cycles + Cycles247_5 = 0x6, + /// 640.5 ADC clock cycles + Cycles640_5 = 0x7, }; - pub const SMPR_SMPx_x = enum(u32) { - /// 3 cycles - Cycles3 = 0x0, - /// 15 cycles - Cycles15 = 0x1, - /// 28 cycles - Cycles28 = 0x2, - /// 56 cycles - Cycles56 = 0x3, - /// 84 cycles - Cycles84 = 0x4, - /// 112 cycles - Cycles112 = 0x5, - /// 144 cycles - Cycles144 = 0x6, - /// 480 cycles - Cycles480 = 0x7, - _, + pub const SMPPLUS = enum(u1) { + /// The sampling time remains set to 2.5 ADC clock cycles remains + Cycles2_5 = 0x0, + /// 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers. + Cycles3_5 = 0x1, }; - /// Analog-to-digital converter + pub const SWTRIG = enum(u1) { + /// Software trigger starts the conversion for sampling time control trigger mode + Conversion = 0x0, + /// Software trigger starts the sampling for sampling time control trigger mode + Sampling = 0x1, + }; + + pub const TROVS = enum(u1) { + /// All oversampled conversions for a channel are run following a trigger + Automatic = 0x0, + /// Each oversampled conversion for a channel needs a new trigger + Triggered = 0x1, + }; + + /// Analog to digital converter pub const ADC = extern struct { - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog event occurred - AWD: u1, - /// Regular channel end of conversion + /// interrupt and status register + ISR: mmio.Mmio(packed struct(u32) { + /// ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it + ADRDY: u1, + /// End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase + EOSMP: u1, + /// End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register EOC: u1, - /// Injected channel end of conversion - JEOC: u1, - /// Injected channel conversion has started - JSTRT: u1, - /// Regular channel conversion has started - STRT: u1, - /// Overrun occurred + /// End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it + EOS: u1, + /// overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it OVR: u1, - padding: u26, + /// Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register + JEOC: u1, + /// Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it + JEOS: u1, + /// Analog watchdog 1-3 flags. Set by hardware when the converted voltage crosses the values programmed in the corresponding fields LT and HT fields of the relevant TR register. It is cleared by software. + AWD: u1, + reserved10: u2, + /// Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information + JQOVF: u1, + padding: u21, }), - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Analog watchdog channel select bits - AWDCH: u5, - /// Interrupt enable for EOC + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + ADRDYIE: u1, + /// End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + EOSMPIE: u1, + /// End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). EOCIE: u1, - /// Analog watchdog interrupt enable - AWDIE: u1, - /// Interrupt enable for injected channels + /// End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + EOSIE: u1, + /// Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + OVRIE: u1, + /// End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). JEOCIE: u1, - /// Scan mode - SCAN: u1, - /// Enable the watchdog on a single channel in scan mode - AWDSGL: packed union { + /// End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + JEOSIE: u1, + /// Analog watchdog 1-3 interrupt enable. This bit is set and cleared by software to enable/disable the analog watchdog 1-3 interrupts. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + AWDIE: u1, + reserved10: u2, + /// Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + JQOVFIE: u1, + padding: u21, + }), + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator). + ADEN: u1, + /// ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + ADDIS: u1, + /// ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion immediately starts (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (EXTSEL = 0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC) In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared). + ADSTART: u1, + /// ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion immediately starts (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared). + JADSTART: u1, + /// ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). + ADSTP: u1, + /// ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC) In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). + JADSTP: u1, + reserved28: u22, + /// voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) + ADVREGEN: u1, + /// Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + DEEPPWD: u1, + /// Differential mode for calibration This bit is set and cleared by software to configure the Single-ended or Differential inputs mode for the calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + ADCALDIF: packed union { raw: u1, - value: AWDSGL, + value: ADCALDIF, }, - /// Automatic injected group conversion - JAUTO: u1, - /// Discontinuous mode on regular channels - DISCEN: u1, - /// Discontinuous mode on injected channels - JDISCEN: u1, - /// Discontinuous mode channel count - DISCNUM: u3, - reserved22: u6, - /// Analog watchdog enable on injected channels - JAWDEN: u1, - /// Analog watchdog enable on regular channels - AWDEN: u1, - /// Resolution + /// ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for Single-ended or Differential inputs mode. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0. The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing). + ADCAL: u1, + }), + /// configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to conversions using the DMA. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + DMAEN: u1, + /// Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + DMACFG: packed union { + raw: u1, + value: DMACFG, + }, + reserved3: u1, + /// Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). RES: packed union { raw: u2, value: RES, }, - /// Overrun interrupt enable - OVRIE: u1, - padding: u5, - }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// A/D Converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - reserved8: u6, - /// Direct memory access mode (for single ADC mode) - DMA: u1, - /// DMA disable selection (for single ADC mode) - DDS: packed union { - raw: u1, - value: DDS, + /// External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + EXTSEL: u1, + reserved10: u4, + /// External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + EXTEN: packed union { + raw: u2, + value: EXTEN, }, - /// End of conversion selection - EOCS: packed union { + /// Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + OVRMOD: packed union { raw: u1, - value: EOCS, + value: OVRMOD, }, - /// Data alignment + /// Single / Continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + CONT: u1, + /// Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + AUTDLY: u1, + /// Data alignment This bit is set and cleared by software to select right or left alignment. Refer to register, data alignment and offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN). Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). ALIGN: packed union { raw: u1, value: ALIGN, }, - reserved16: u4, - /// External event select for injected group - JEXTSEL: u4, - /// External trigger enable for injected channels - JEXTEN: packed union { - raw: u2, - value: JEXTEN, + /// Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + DISCEN: u1, + /// Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in Discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + DISCNUM: u3, + /// Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable Discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. + JDISCEN: u1, + /// JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to for more information. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + JQM: packed union { + raw: u1, + value: JQM, }, - /// Start conversion of injected channels - JSWSTART: u1, - reserved24: u1, - /// External event select for regular group - EXTSEL: u4, - /// External trigger enable for regular channels - EXTEN: packed union { - raw: u2, - value: EXTEN, + /// Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + AWD1SGL: packed union { + raw: u1, + value: AWD1SGL, }, - /// Start conversion of regular channels - SWSTART: u1, - padding: u1, + /// Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + AWD1EN: u1, + /// Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + JAWD1EN: u1, + /// Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). + JAUTO: u1, + /// Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... others: reserved, must not be used Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value. The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + AWD1CH: u5, + /// Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared. + JQDIS: u1, + }), + /// configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + ROVSE: u1, + /// Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + JOVSE: u1, + /// Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). + OVSR: packed union { + raw: u3, + value: OVSR, + }, + /// Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). + OVSS: u4, + /// Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + TROVS: packed union { + raw: u1, + value: TROVS, + }, + /// Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + ROVSM: packed union { + raw: u1, + value: ROVSM, + }, + reserved25: u14, + /// Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + SWTRIG: packed union { + raw: u1, + value: SWTRIG, + }, + /// Bulb sampling mode This bit is set and cleared by software to enable the bulb sampling mode. SAMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + BULB: u1, + /// Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN bit should be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN bit is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + SMPTRIG: u1, + padding: u4, }), /// sample time register 1 SMPR1: mmio.Mmio(packed struct(u32) { - /// Channel 10 sampling time selection + /// Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. SMP: packed union { raw: u3, value: SAMPLE_TIME, }, - padding: u29, + reserved31: u28, + /// Addition of one clock cycle to the sampling time. To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 + SMPPLUS: packed union { + raw: u1, + value: SMPPLUS, + }, }), /// sample time register 2 SMPR2: mmio.Mmio(packed struct(u32) { - /// Channel 0 sampling time selection + /// Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. SMP: packed union { raw: u3, value: SAMPLE_TIME, }, padding: u29, }), - /// injected channel data offset register x - JOFR: [4]mmio.Mmio(packed struct(u32) { - /// Data offset for injected channel x - JOFFSET: u12, - padding: u20, + reserved32: [4]u8, + /// watchdog threshold register 1 + TR1: mmio.Mmio(packed struct(u32) { + /// Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + LT1: u12, + /// Analog watchdog filtering parameter This bit is set and cleared by software. ... Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + AWDFILT: u3, + reserved16: u1, + /// Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + HT1: u12, + padding: u4, }), - /// watchdog higher threshold register - HTR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog higher threshold - HT: u12, - padding: u20, + /// watchdog threshold register 2 + TR2: mmio.Mmio(packed struct(u32) { + /// Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + LT2: u8, + reserved16: u8, + /// Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + HT2: u8, + padding: u8, }), - /// watchdog lower threshold register - LTR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog lower threshold - LT: u12, - padding: u20, + /// watchdog threshold register 3 + TR3: mmio.Mmio(packed struct(u32) { + /// Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + LT3: u8, + reserved16: u8, + /// Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + HT3: u8, + padding: u8, }), + reserved48: [4]u8, /// regular sequence register 1 SQR1: mmio.Mmio(packed struct(u32) { - /// 13th conversion in regular sequence - SQ: u5, - reserved20: u15, - /// Regular channel sequence length + /// Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). L: u4, - padding: u8, + reserved6: u2, + /// 1st-4th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + SQ: u5, + padding: u21, }), /// regular sequence register 2 SQR2: mmio.Mmio(packed struct(u32) { - /// 7th conversion in regular sequence + /// 5th-9th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 5th-9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). SQ: u5, padding: u27, }), /// regular sequence register 3 SQR3: mmio.Mmio(packed struct(u32) { - /// 1st conversion in regular sequence + /// 10th-14th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 10th-14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + SQ: u5, + padding: u27, + }), + /// regular sequence register 4 + SQR4: mmio.Mmio(packed struct(u32) { + /// 15th-16th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 15th-16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). SQ: u5, padding: u27, }), + /// regular data register + DR: mmio.Mmio(packed struct(u32) { + /// Regular data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in + RDATA: u16, + padding: u16, + }), + reserved76: [8]u8, /// injected sequence register JSQR: mmio.Mmio(packed struct(u32) { - /// 1st conversion in injected sequence - JSQ: u5, - reserved20: u15, - /// Injected sequence length + /// Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). JL: u2, - padding: u10, + /// External Trigger Selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + JEXTSEL: u5, + /// External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). If JQM = 1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Queue of context for injected conversions). + JEXTEN: packed union { + raw: u2, + value: EXTEN, + }, + /// 1st-4th conversions in the injected sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + JSQ: u5, + padding: u18, }), - /// injected data register x + reserved96: [16]u8, + /// offset 1-4 register + OFR: [4]mmio.Mmio(packed struct(u32) { + /// Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4. + OFFSET: u12, + reserved24: u12, + /// Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + OFFSETPOS: packed union { + raw: u1, + value: OFFSETPOS, + }, + /// Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + SATEN: u1, + /// Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the data offset y. If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers. + OFFSET_CH: u5, + /// Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + OFFSET_EN: u1, + }), + reserved128: [16]u8, + /// injected channel 1-4 register JDR: [4]mmio.Mmio(packed struct(u32) { - /// Injected data + /// Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in JDATA: u16, padding: u16, }), - /// regular data register - DR: mmio.Mmio(packed struct(u32) { - /// Regular data - DATA: u16, - padding: u16, + reserved160: [16]u8, + /// Analog Watchdog 2 Configuration Register + AWD2CR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: analog input channel i is monitored by AWD2 When AWD2CH[19:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the analog watchdog. + AWD2CH: u20, + padding: u12, + }), + /// Analog Watchdog 3 Configuration Register + AWD3CR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: analog input channel i is monitored by AWD3 When AWD3CH[19:0] = 000..0, the analog Watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the analog watchdog. + AWD3CH: u20, + padding: u12, + }), + reserved176: [8]u8, + /// Differential mode Selection Register + DIFSEL: mmio.Mmio(packed struct(u32) { + /// Differential mode for channels 19 to 0. These bits are set and cleared by software. They allow to select if a channel is configured as Single-ended or Differential mode. DIFSEL[i] = 0: analog input channel is configured in Single-ended mode DIFSEL[i] = 1: analog input channel i is configured in Differential mode Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port or to an internal channel must be kept their reset value (Single-ended input mode). The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + DIFSEL: u20, + padding: u12, + }), + /// Calibration Factors + CALFACT: mmio.Mmio(packed struct(u32) { + /// Calibration Factors In Single-ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new single-ended calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). + CALFACT_S: u7, + reserved16: u9, + /// Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new differential calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). + CALFACT_D: u7, + padding: u9, + }), + reserved200: [16]u8, + /// option register + OR: mmio.Mmio(packed struct(u32) { + /// Option bit 0 + OP0: u1, + /// Option bit 1. Note - not documented for H562/H563/H573 + OP1: u1, + padding: u30, }), }; }; - pub const flash_u5 = struct { - pub const BKPSRAM_ECC = enum(u1) { - /// Backup RAM ECC check enabled - B_0x0 = 0x0, - /// Backup RAM ECC check disabled - B_0x1 = 0x1, - }; - - pub const BK_ECC = enum(u1) { - /// Bank 1 - B_0x0 = 0x0, - /// Bank 2 - B_0x1 = 0x1, - }; - - pub const BK_OP = enum(u1) { - /// Bank 1 - B_0x0 = 0x0, - /// Bank 2 - B_0x1 = 0x1, - }; - - pub const BOR_LEV = enum(u3) { - /// BOR level 0 (reset level threshold around 1.7 V) - B_0x0 = 0x0, - /// BOR level 1 (reset level threshold around 2.0 V) - B_0x1 = 0x1, - /// BOR level 2 (reset level threshold around 2.2 V) - B_0x2 = 0x2, - /// BOR level 3 (reset level threshold around 2.5 V) - B_0x3 = 0x3, - /// BOR level 4 (reset level threshold around 2.8 V) - B_0x4 = 0x4, - _, - }; - - pub const CODE_OP = enum(u3) { - /// No Flash operation interrupted by previous reset - B_0x0 = 0x0, - /// Single write operation interrupted - B_0x1 = 0x1, - /// Burst write operation interrupted - B_0x2 = 0x2, - /// Page erase operation interrupted - B_0x3 = 0x3, - /// Bank erase operation interrupted - B_0x4 = 0x4, - /// Mass erase operation interrupted - B_0x5 = 0x5, - /// Option change operation interrupted - B_0x6 = 0x6, - _, - }; - - pub const DUALBANK = enum(u1) { - /// Single bank Flash with contiguous address in bank 1 - B_0x0 = 0x0, - /// Dual-bank Flash with contiguous addresses - B_0x1 = 0x1, - }; - - pub const ECCIE = enum(u1) { - /// ECCC interrupt disabled - B_0x0 = 0x0, - /// ECCC interrupt enabled. - B_0x1 = 0x1, - }; - - pub const HDP_ACCDIS = enum(u1) { - /// Access to HDP2 area granted - B_0x0 = 0x0, - /// Access to HDP2 area denied (SECWM2Ry option bytes modification bocked -refer to ) - B_0x1 = 0x1, - }; - - pub const IO_VDDIO_HSLV = enum(u1) { - /// High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) - B_0x0 = 0x0, - /// High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - B_0x1 = 0x1, - }; - - pub const IO_VDD_HSLV = enum(u1) { - /// High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) - B_0x0 = 0x0, - /// High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) - B_0x1 = 0x1, - }; - - pub const IWDG_STDBY = enum(u1) { - /// Independent watchdog counter frozen in Standby mode - B_0x0 = 0x0, - /// Independent watchdog counter running in Standby mode - B_0x1 = 0x1, - }; - - pub const IWDG_STOP = enum(u1) { - /// Independent watchdog counter frozen in Stop mode - B_0x0 = 0x0, - /// Independent watchdog counter running in Stop mode - B_0x1 = 0x1, - }; - - pub const IWDG_SW = enum(u1) { - /// Hardware independent watchdog selected - B_0x0 = 0x0, - /// Software independent watchdog selected - B_0x1 = 0x1, - }; - - pub const LPM = enum(u1) { - /// Flash not in low-power read mode - B_0x0 = 0x0, - /// Flash in low-power read mode - B_0x1 = 0x1, - }; - - pub const NSCR_BKER = enum(u1) { - /// Bank 1 selected for non-secure page erase - B_0x0 = 0x0, - /// Bank 2 selected for non-secure page erase - B_0x1 = 0x1, - }; - - pub const NSCR_EOPIE = enum(u1) { - /// Non-secure EOP Interrupt disabled - B_0x0 = 0x0, - /// Non-secure EOP Interrupt enabled - B_0x1 = 0x1, - }; - - pub const NSCR_ERRIE = enum(u1) { - /// Non-secure OPERR error interrupt disabled - B_0x0 = 0x0, - /// Non-secure OPERR error interrupt enabled - B_0x1 = 0x1, + pub const adc_l0 = struct { + pub const ALIGN = enum(u1) { + /// Right alignment + Right = 0x0, + /// Left alignment + Left = 0x1, }; - pub const NSCR_PER = enum(u1) { - /// Non-secure page erase disabled - B_0x0 = 0x0, - /// Non-secure page erase enabled - B_0x1 = 0x1, + pub const AWDSGL = enum(u1) { + /// Analog watchdog enabled on all channels + AllChannels = 0x0, + /// Analog watchdog enabled on a single channel + SingleChannel = 0x1, }; - pub const NSCR_PG = enum(u1) { - /// Non-secure Flash programming disabled - B_0x0 = 0x0, - /// Non-secure Flash programming enabled - B_0x1 = 0x1, + pub const CKMODE = enum(u2) { + /// Asynchronous clock mode + ADCCLK = 0x0, + /// Synchronous clock mode (PCLK/2) + PCLK_Div2 = 0x1, + /// Sychronous clock mode (PCLK/4) + PCLK_Div4 = 0x2, + /// Synchronous clock mode (PCLK) + PCLK = 0x3, }; - pub const NSPRIV = enum(u1) { - /// Non-secure Flash registers can be read and written by privileged or unprivileged access. - B_0x0 = 0x0, - /// Non-secure Flash registers can be read and written by privileged access only. - B_0x1 = 0x1, + pub const DMACFG = enum(u1) { + /// DMA One Shot mode selected + OneShot = 0x0, + /// DMA Circular mode selected + Circular = 0x1, }; - pub const OBL_LAUNCH = enum(u1) { - /// Option byte loading complete - B_0x0 = 0x0, - /// Option byte loading requested - B_0x1 = 0x1, + pub const EXTEN = enum(u2) { + /// Trigger detection disabled + Disabled = 0x0, + /// Trigger detection on the rising edge + RisingEdge = 0x1, + /// Trigger detection on the falling edge + FallingEdge = 0x2, + /// Trigger detection on both the rising and falling edges + BothEdges = 0x3, }; - pub const PDREQ = enum(u1) { - /// No request for bank 2 to enter power-down mode - B_0x0 = 0x0, - /// Bank 2 requested to enter power-down mode - B_0x1 = 0x1, + pub const OVRMOD = enum(u1) { + /// ADC_DR register is preserved with the old data when an overrun is detected + Preserved = 0x0, + /// ADC_DR register is overwritten with the last conversion result when an overrun is detected + Overwritten = 0x1, }; - pub const RDP = enum(u8) { - /// Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1) - B_0x55 = 0x55, - /// Level 0 (readout protection not active) - B_0xAA = 0xaa, - /// Level 2 (chip readout protection active) - B_0xCC = 0xcc, + pub const PRESC = enum(u4) { + /// Input ADC clock not divided. + Div1 = 0x0, + /// Input ADC clock divided by 2. + Div2 = 0x1, + /// Input ADC clock divided by 4. + Div4 = 0x2, + /// Input ADC clock divided by 6. + Div6 = 0x3, + /// Input ADC clock divided by 8. + Div8 = 0x4, + /// Input ADC clock divided by 10. + Div10 = 0x5, + /// Input ADC clock divided by 12. + Div12 = 0x6, + /// Input ADC clock divided by 16. + Div16 = 0x7, + /// Input ADC clock divided by 32. + Div32 = 0x8, + /// Input ADC clock divided by 64. + Div64 = 0x9, + /// Input ADC clock divided by 128. + Div128 = 0xa, + /// Input ADC clock divided by 256. + Div256 = 0xb, _, }; - pub const SECCR_BKER = enum(u1) { - /// Bank 1 selected for secure page erase - B_0x0 = 0x0, - /// Bank 2 selected for secure page erase - B_0x1 = 0x1, - }; - - pub const SECCR_EOPIE = enum(u1) { - /// Secure EOP Interrupt disabled - B_0x0 = 0x0, - /// Secure EOP Interrupt enabled - B_0x1 = 0x1, - }; - - pub const SECCR_ERRIE = enum(u1) { - /// Secure OPERR error interrupt disabled - B_0x0 = 0x0, - /// Secure OPERR error interrupt enabled - B_0x1 = 0x1, - }; - - pub const SECCR_PER = enum(u1) { - /// Secure page erase disabled - B_0x0 = 0x0, - /// Secure page erase enabled - B_0x1 = 0x1, - }; - - pub const SECCR_PG = enum(u1) { - /// Secure Flash programming disabled - B_0x0 = 0x0, - /// Secure Flash programming enabled - B_0x1 = 0x1, - }; - - pub const SLEEP_PD = enum(u1) { - /// Flash in Idle mode during Sleep mode - B_0x0 = 0x0, - /// Flash in power-down mode during Sleep mode - B_0x1 = 0x1, - }; - - pub const SPRIV = enum(u1) { - /// Secure Flash registers can be read and written by privileged or unprivileged access. - B_0x0 = 0x0, - /// Secure Flash registers can be read and written by privileged access only. - B_0x1 = 0x1, - }; - - pub const SRAM_ECC = enum(u1) { - /// SRAM3 ECC check enabled - B_0x0 = 0x0, - /// SRAM3 ECC check disabled - B_0x1 = 0x1, - }; - - pub const SWAP_BANK = enum(u1) { - /// Bank 1 and bank 2 addresses not swapped - B_0x0 = 0x0, - /// Bank 1 and bank 2 addresses swapped - B_0x1 = 0x1, - }; - - pub const WRPAR_UNLOCK = enum(u1) { - /// WRP2A start and end pages locked - B_0x0 = 0x0, - /// WRP2A start and end pages unlocked - B_0x1 = 0x1, - }; - - pub const WRPBR_UNLOCK = enum(u1) { - /// WRP2B start and end pages locked - B_0x0 = 0x0, - /// WRP2B start and end pages unlocked - B_0x1 = 0x1, - }; - - pub const WWDG_SW = enum(u1) { - /// Hardware window watchdog selected - B_0x0 = 0x0, - /// Software window watchdog selected - B_0x1 = 0x1, - }; - - pub const nBOOT = enum(u1) { - /// nBOOT0 = 0 - B_0x0 = 0x0, - /// nBOOT0 = 1 - B_0x1 = 0x1, - }; - - pub const nRST_SHDW = enum(u1) { - /// Reset generated when entering the Shutdown mode - B_0x0 = 0x0, - /// No reset generated when entering the Shutdown mode - B_0x1 = 0x1, - }; - - pub const nRST_STDBY = enum(u1) { - /// Reset generated when entering the Standby mode - B_0x0 = 0x0, - /// No reset generate when entering the Standby mode - B_0x1 = 0x1, + pub const RES = enum(u2) { + /// 12-bit (14 ADCCLK cycles) + Bits12 = 0x0, + /// 10-bit (13 ADCCLK cycles) + Bits10 = 0x1, + /// 8-bit (11 ADCCLK cycles) + Bits8 = 0x2, + /// 6-bit (9 ADCCLK cycles) + Bits6 = 0x3, }; - pub const nRST_STOP = enum(u1) { - /// Reset generated when entering the Stop mode - B_0x0 = 0x0, - /// No reset generated when entering the Stop mode - B_0x1 = 0x1, + pub const SAMPLE_TIME = enum(u3) { + /// 1.5 cycles + Cycles1_5 = 0x0, + /// 3.5 cycles + Cycles3_5 = 0x1, + /// 7.5 cycles + Cycles7_5 = 0x2, + /// 12.5 cycles + Cycles12_5 = 0x3, + /// 19.5 cycles + Cycles19_5 = 0x4, + /// 39.5 cycles + Cycles39_5 = 0x5, + /// 79.5 cycles + Cycles79_5 = 0x6, + /// 160.5 cycles + Cycles160_5 = 0x7, }; - pub const nSWBOOT = enum(u1) { - /// BOOT0 taken from the option bit nBOOT0 - B_0x0 = 0x0, - /// BOOT0 taken from PH3/BOOT0 pin - B_0x1 = 0x1, + pub const SCANDIR = enum(u1) { + /// Upward scan (from CHSEL0 to CHSEL18) + Upward = 0x0, + /// Backward scan (from CHSEL18 to CHSEL0) + Backward = 0x1, }; - /// Flash - pub const FLASH = extern struct { - /// FLASH access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time. ... - LATENCY: u4, - reserved8: u4, - /// Prefetch enable This bit enables the prefetch buffer in the embedded Flash memory. - PRFTEN: u1, - reserved11: u2, - /// Low-power read mode This bit puts the Flash memory in low-power read mode. - LPM: packed union { - raw: u1, - value: LPM, - }, - /// Bank 1 power-down mode request This bit is write-protected with FLASH_PDKEY1R. This bit requests bank 1 to enter power-down mode. When bank 1 enters power-down mode, this bit is cleared by hardware and the PDKEY1R is locked. - PDREQ1: packed union { - raw: u1, - value: PDREQ, - }, - /// Bank 2 power-down mode request This bit is write-protected with FLASH_PDKEY2R. This bit requests bank 2 to enter power-down mode. When bank 2 enters power-down mode, this bit is cleared by hardware and the PDKEY2R is locked. - PDREQ2: packed union { - raw: u1, - value: PDREQ, - }, - /// Flash memory power-down mode during Sleep mode This bit determines whether the Flash memory is in power-down mode or Idle mode when the device is in Sleep mode. The Flash must not be put in power-down while a program or an erase operation is on-going. - SLEEP_PD: packed union { - raw: u1, - value: SLEEP_PD, - }, - padding: u17, - }), - reserved8: [4]u8, - /// FLASH non-secure key register - NSKEYR: u32, - /// FLASH secure key register - SECKEYR: u32, - /// FLASH option key register - OPTKEYR: u32, - reserved24: [4]u8, - /// FLASH bank 1 power-down key register - PDKEY1R: mmio.Mmio(packed struct(u32) { - /// Bank 1 power-down key - PDKEY1: u32, - }), - /// FLASH bank 2 power-down key register - PDKEY2R: mmio.Mmio(packed struct(u32) { - /// Bank 2 power-down key - PDKEY2: u32, + /// Analog-to-digital converter + pub const ADC = extern struct { + /// interrupt and status register + ISR: mmio.Mmio(packed struct(u32) { + /// ADC ready + ADRDY: u1, + /// End of sampling flag + EOSMP: u1, + /// End of conversion flag + EOC: u1, + /// End of sequence flag + EOS: u1, + /// ADC overrun + OVR: u1, + reserved7: u2, + /// Analog watchdog flag + AWD: u1, + reserved11: u3, + /// End Of Calibration flag + EOCAL: u1, + padding: u20, }), - /// FLASH non-secure status register - NSSR: mmio.Mmio(packed struct(u32) { - /// Non-secure end of operation - EOP: u1, - /// Non-secure operation error - OPERR: u1, - reserved3: u1, - /// Non-secure programming error This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1. - PROGERR: u1, - /// Non-secure write protection error This bit is set by hardware when an non-secure address to be erased/programmed belongs to a write-protected part (by WRP, HDP or RDP level 1) of the Flash memory. This bit is cleared by writing 1. Refer to for full conditions of error flag setting. - WRPERR: u1, - /// Non-secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1. - PGAERR: u1, - /// Non-secure size error This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1. - SIZERR: u1, - /// Non-secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to for full conditions of error flag setting. - PGSERR: u1, - reserved13: u5, - /// Option write error This bit is set by hardware when the options bytes are written with an invalid configuration. It is cleared by writing 1. Refer to for full conditions of error flag setting. - OPTWERR: u1, - reserved16: u2, - /// Non-secure busy This indicates that a Flash memory secure or non-secure operation is in progress. This bit is set at the beginning of a Flash operation and reset when the operation finishes or when an error occurs. - BSY: u1, - /// Non-secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory. - WDW: u1, - /// OEM1 lock This bit indicates that the OEM1 RDP key read during the OBL is not virgin. When set, the OEM1 RDP lock mechanism is active. - OEM1LOCK: u1, - /// OEM2 lock This bit indicates that the OEM2 RDP key read during the OBL is not virgin. When set, the OEM2 RDP lock mechanism is active. - OEM2LOCK: u1, - /// Bank 1 in power-down mode This bit indicates that the Flash memory bank 1 is in power-down state. It is reset when bank 1 is in normal mode or being awaken. - PD1: u1, - /// Bank 2 in power-down mode This bit indicates that the Flash memory bank 2 is in power-down state. It is reset when bank 2 is in normal mode or being awaken. - PD2: u1, - padding: u10, + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// ADC ready interrupt enable + ADRDYIE: u1, + /// End of sampling flag interrupt enable + EOSMPIE: u1, + /// End of conversion interrupt enable + EOCIE: u1, + /// End of conversion sequence interrupt enable + EOSIE: u1, + /// Overrun interrupt enable + OVRIE: u1, + reserved7: u2, + /// Analog watchdog interrupt enable + AWDIE: u1, + reserved11: u3, + /// End of calibration interrupt enable. + EOCALIE: u1, + padding: u20, }), - /// FLASH secure status register - SECSR: mmio.Mmio(packed struct(u32) { - /// Secure end of operation This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writing 1. - EOP: u1, - /// Secure operation error This bit is set by hardware when a Flash memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1. - OPERR: u1, - reserved3: u1, - /// Secure programming error This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1. - PROGERR: u1, - /// Secure write protection error This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory.This bit is cleared by writing 1. Refer to for full conditions of error flag setting. - WRPERR: u1, - /// Secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1. - PGAERR: u1, - /// Secure size error This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1. - SIZERR: u1, - /// Secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to for full conditions of error flag setting. - PGSERR: u1, - reserved16: u8, - /// Secure busy This bit indicates that a Flash memory secure or non-secure operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs. - BSY: u1, - /// Secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory. - WDW: u1, - padding: u14, + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// ADC enable command + ADEN: u1, + /// ADC disable command + ADDIS: u1, + /// ADC start conversion command + ADSTART: u1, + reserved4: u1, + /// ADC stop conversion command + ADSTP: u1, + reserved28: u23, + /// ADC Voltage Regulator Enable. + ADVREGEN: u1, + reserved31: u2, + /// ADC calibration + ADCAL: u1, }), - /// FLASH non-secure control register - NSCR: mmio.Mmio(packed struct(u32) { - /// Non-secure programming - PG: packed union { - raw: u1, - value: NSCR_PG, - }, - /// Non-secure page erase - PER: packed union { - raw: u1, - value: NSCR_PER, - }, - /// Non-secure bank 1 mass erase This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set. - MER1: u1, - /// Non-secure page number selection These bits select the page to erase. ... - PNB: u7, - reserved11: u1, - /// Non-secure bank selection for page erase - BKER: packed union { + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// Direct memory access enable + DMAEN: u1, + /// Direct memory access configuration + DMACFG: packed union { raw: u1, - value: NSCR_BKER, + value: DMACFG, }, - reserved14: u2, - /// Non-secure burst write programming mode When set, this bit selects the burst write programming mode. - BWR: u1, - /// Non-secure bank 2 mass erase This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set. - MER2: u1, - /// Non-secure start This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR. - STRT: u1, - /// Options modification start This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR. - OPTSTRT: u1, - reserved24: u6, - /// Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1. - EOPIE: packed union { + /// Scan sequence direction + SCANDIR: packed union { raw: u1, - value: NSCR_EOPIE, + value: SCANDIR, }, - /// Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1. - ERRIE: packed union { - raw: u1, - value: NSCR_ERRIE, + /// Data resolution + RES: packed union { + raw: u2, + value: RES, }, - reserved27: u1, - /// Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set. - OBL_LAUNCH: packed union { + /// Data alignment + ALIGN: packed union { raw: u1, - value: OBL_LAUNCH, + value: ALIGN, }, - reserved30: u2, - /// Option lock This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset. - OPTLOCK: u1, - /// Non-secure lock This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. - LOCK: u1, - }), - /// FLASH secure control register - SECCR: mmio.Mmio(packed struct(u32) { - /// Secure programming - PG: packed union { - raw: u1, - value: SECCR_PG, + /// External trigger selection + EXTSEL: u3, + reserved10: u1, + /// External trigger enable and polarity selection + EXTEN: packed union { + raw: u2, + value: EXTEN, }, - /// Secure page erase - PER: packed union { + /// Overrun management mode + OVRMOD: packed union { raw: u1, - value: SECCR_PER, + value: OVRMOD, }, - /// Secure bank 1 mass erase This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set. - MER1: u1, - /// Secure page number selection These bits select the page to erase: ... - PNB: u7, - reserved11: u1, - /// Secure bank selection for page erase - BKER: packed union { + /// Continuous conversion + CONT: u1, + /// Wait conversion mode + WAIT: u1, + /// Auto-off mode + AUTOFF: u1, + /// Discontinuous mode + DISCEN: u1, + reserved22: u5, + /// Enable the watchdog on a single channel or on all channels + AWDSGL: packed union { raw: u1, - value: SECCR_BKER, + value: AWDSGL, }, - reserved14: u2, - /// Secure burst write programming mode When set, this bit selects the burst write programming mode. - BWR: u1, - /// Secure bank 2 mass erase This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set. - MER2: u1, - /// Secure start This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR. - STRT: u1, - reserved24: u7, - /// Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1. - EOPIE: packed union { - raw: u1, - value: SECCR_EOPIE, - }, - /// Secure error interrupt enable - ERRIE: packed union { - raw: u1, - value: SECCR_ERRIE, - }, - /// Secure PCROP read error interrupt enable - RDERRIE: u1, - reserved29: u2, - /// Flash memory security state invert This bit inverts the Flash memory security state. - INV: u1, - reserved31: u1, - /// Secure lock This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. - LOCK: u1, + /// Analog watchdog enable + AWDEN: u1, + reserved26: u2, + /// Analog watchdog channel selection + AWDCH: u5, + padding: u1, }), - /// FLASH ECC register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC fail address - ADDR_ECC: u20, - reserved21: u1, - /// ECC fail bank - BK_ECC: packed union { - raw: u1, - value: BK_ECC, - }, - /// System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory. - SYSF_ECC: u1, - reserved24: u1, - /// ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set. - ECCIE: packed union { - raw: u1, - value: ECCIE, + /// configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Oversampler Enable. + OVSE: u1, + reserved2: u1, + /// Oversampling ratio. + OVSR: u3, + /// Oversampling shift. + OVSS: u4, + /// Triggered Oversampling. + TOVS: u1, + reserved30: u20, + /// ADC clock mode + CKMODE: packed union { + raw: u2, + value: CKMODE, }, - reserved30: u5, - /// ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1. - ECCC: u1, - /// ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1. - ECCD: u1, }), - /// FLASH operation status register - OPSR: mmio.Mmio(packed struct(u32) { - /// Interrupted operation address This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0 0000 to 0xF FFF0. - ADDR_OP: u20, - reserved21: u1, - /// Interrupted operation bank This bit indicates which Flash memory bank was accessed when reset occurred - BK_OP: packed union { - raw: u1, - value: BK_OP, - }, - /// Operation in system Flash memory interrupted This bit indicates that the reset occurred during an operation in the system Flash memory. - SYSF_OP: u1, - reserved29: u6, - /// Flash memory operation code This field indicates which Flash memory operation has been interrupted by a system reset: - CODE_OP: packed union { + /// sampling time register + SMPR: mmio.Mmio(packed struct(u32) { + /// Sampling time selection + SMP: packed union { raw: u3, - value: CODE_OP, + value: SAMPLE_TIME, }, + padding: u29, }), - reserved64: [8]u8, - /// FLASH option register - OPTR: mmio.Mmio(packed struct(u32) { - /// Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to for more details. - RDP: packed union { - raw: u8, - value: RDP, - }, - /// BOR reset level These bits contain the VDD supply level threshold that activates/releases the reset. - BOR_LEV: packed union { - raw: u3, - value: BOR_LEV, - }, - reserved12: u1, - /// Reset generation in Stop mode - nRST_STOP: packed union { - raw: u1, - value: nRST_STOP, - }, - /// Reset generation in Standby mode - nRST_STDBY: packed union { - raw: u1, - value: nRST_STDBY, - }, - /// Reset generation in Shutdown mode - nRST_SHDW: packed union { - raw: u1, - value: nRST_SHDW, - }, - /// SRAM1, SRAM3 and SRAM4 erase upon system reset - SRAM1345_RST: u1, - /// Independent watchdog selection - IWDG_SW: packed union { - raw: u1, - value: IWDG_SW, - }, - /// Independent watchdog counter freeze in Stop mode - IWDG_STOP: packed union { - raw: u1, - value: IWDG_STOP, - }, - /// Independent watchdog counter freeze in Standby mode - IWDG_STDBY: packed union { - raw: u1, - value: IWDG_STDBY, - }, - /// Window watchdog selection - WWDG_SW: packed union { - raw: u1, - value: WWDG_SW, - }, - /// Swap banks - SWAP_BANK: packed union { - raw: u1, - value: SWAP_BANK, - }, - /// Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices - DUALBANK: packed union { - raw: u1, - value: DUALBANK, - }, - /// Backup RAM ECC detection and correction enable - BKPSRAM_ECC: packed union { - raw: u1, - value: BKPSRAM_ECC, - }, - /// SRAM3 ECC detection and correction enable - SRAM3_ECC: packed union { - raw: u1, - value: SRAM_ECC, - }, - /// SRAM2 ECC detection and correction enable - SRAM2_ECC: packed union { - raw: u1, - value: SRAM_ECC, + reserved32: [8]u8, + /// watchdog threshold register + TR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog lower threshold + LT: u12, + reserved16: u4, + /// Analog watchdog higher threshold + HT: u12, + padding: u4, + }), + reserved40: [4]u8, + /// channel selection register + CHSELR: mmio.Mmio(packed struct(u32) { + /// Channel-x selection + @"CHSEL x": u1, + padding: u31, + }), + reserved64: [20]u8, + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Converted data + DATA: u16, + padding: u16, + }), + reserved180: [112]u8, + /// ADC Calibration factor. + CALFACT: mmio.Mmio(packed struct(u32) { + /// Calibration factor. + CALFACT: u7, + padding: u25, + }), + reserved776: [592]u8, + /// common configuration register + CCR: mmio.Mmio(packed struct(u32) { + reserved18: u18, + /// ADC prescaler. + PRESC: packed union { + raw: u4, + value: PRESC, }, - /// SRAM2 erase when system reset - SRAM2_RST: u1, - /// Software BOOT0 - nSWBOOT0: packed union { + /// VREFINT enable + VREFEN: u1, + /// Temperature sensor enable + TSEN: u1, + reserved25: u1, + /// Low Frequency Mode enable + LFMEN: u1, + padding: u6, + }), + }; + }; + + pub const adc_u0 = struct { + pub const DMACFG = enum(u1) { + /// DMA One Shot mode selected + OneShot = 0x0, + /// DMA Circular mode selected + Circular = 0x1, + }; + + pub const RES = enum(u2) { + /// 12-bit resolution + Bits12 = 0x0, + /// 10-bit resolution + Bits10 = 0x1, + /// 8-bit resolution + Bits8 = 0x2, + /// 6-bit resolution + Bits6 = 0x3, + }; + + pub const SAMPLE_TIME = enum(u3) { + /// 1.5 ADC cycles + Cycles1_5 = 0x0, + /// 3.5 ADC cycles + Cycles3_5 = 0x1, + /// 7.5 ADC cycles + Cycles7_5 = 0x2, + /// 12.5 ADC cycles + Cycles12_5 = 0x3, + /// 19.5 ADC cycles + Cycles19_5 = 0x4, + /// 39.5 ADC cycles + Cycles39_5 = 0x5, + /// 79.5 ADC cycles + Cycles79_5 = 0x6, + /// 160.5 ADC cycles + Cycles160_5 = 0x7, + }; + + /// Analog to Digital Converter + pub const ADC = extern struct { + /// ADC interrupt and status register + ISR: mmio.Mmio(packed struct(u32) { + /// ADC ready flag + ADRDY: u1, + /// ADC group regular end of sampling flag + EOSMP: u1, + /// ADC group regular end of unitary conversion flag + EOC: u1, + /// ADC group regular end of sequence conversions flag + EOS: u1, + /// ADC group regular overrun flag + OVR: u1, + reserved7: u2, + /// ADC analog watchdog 1 flag + AWD1: u1, + /// ADC analog watchdog 2 flag + AWD2: u1, + /// ADC analog watchdog 3 flag + AWD3: u1, + reserved11: u1, + /// End Of Calibration flag + EOCAL: u1, + reserved13: u1, + /// Channel Configuration Ready flag + CCRDY: u1, + padding: u18, + }), + /// ADC interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// ADC ready interrupt + ADRDYIE: u1, + /// ADC group regular end of sampling interrupt + EOSMPIE: u1, + /// ADC group regular end of unitary conversion interrupt + EOCIE: u1, + /// ADC group regular end of sequence conversions interrupt + EOSIE: u1, + /// ADC group regular overrun interrupt + OVRIE: u1, + reserved7: u2, + /// ADC analog watchdog 1 interrupt + AWD1IE: u1, + /// ADC analog watchdog 2 interrupt + AWD2IE: u1, + /// ADC analog watchdog 3 interrupt + AWD3IE: u1, + reserved11: u1, + /// End of calibration interrupt enable + EOCALIE: u1, + reserved13: u1, + /// Channel Configuration Ready Interrupt enable + CCRDYIE: u1, + padding: u18, + }), + /// ADC control register + CR: mmio.Mmio(packed struct(u32) { + /// ADC enable + ADEN: u1, + /// ADC disable + ADDIS: u1, + /// ADC group regular conversion start + ADSTART: u1, + reserved4: u1, + /// ADC group regular conversion stop + ADSTP: u1, + reserved28: u23, + /// ADC voltage regulator enable + ADVREGEN: u1, + reserved31: u2, + /// ADC calibration + ADCAL: u1, + }), + /// ADC configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// ADC DMA transfer enable + DMAEN: u1, + /// Direct memory access configuration + DMACFG: packed union { raw: u1, - value: nSWBOOT, + value: DMACFG, }, - /// nBOOT0 option bit - nBOOT0: packed union { - raw: u1, - value: nBOOT, + /// Scan sequence direction + SCANDIR: u1, + /// ADC data resolution + RES: packed union { + raw: u2, + value: RES, }, - /// PA15 pull-up enable - PA15_PUPEN: u1, - /// High-speed IO at low VDD voltage configuration bit This bit can be set only with VDD below 2.5V - IO_VDD_HSLV: packed union { - raw: u1, - value: IO_VDD_HSLV, + /// ADC data alignement + ALIGN: u1, + /// ADC group regular external trigger source + EXTSEL: u3, + reserved10: u1, + /// ADC group regular external trigger polarity + EXTEN: u2, + /// ADC group regular overrun configuration + OVRMOD: u1, + /// Continuous conversion + CONT: u1, + /// Wait conversion mode + WAIT: u1, + /// Auto-off mode + AUTOFF: u1, + /// ADC group regular sequencer discontinuous mode + DISCEN: u1, + reserved21: u4, + /// Mode selection of the ADC_CHSELR register + CHSELRMOD: u1, + /// ADC analog watchdog 1 monitoring a single channel or all channels + AWD1SGL: u1, + /// ADC analog watchdog 1 enable on scope ADC group regular + AWD1EN: u1, + reserved26: u2, + /// ADC analog watchdog 1 monitored channel selection + AWDCH1CH: u5, + padding: u1, + }), + /// ADC configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// ADC oversampler enable on scope ADC group regular + OVSE: u1, + reserved2: u1, + /// ADC oversampling ratio + OVSR: u3, + /// ADC oversampling shift + OVSS: u4, + /// ADC oversampling discontinuous mode (triggered mode) for ADC group regular + TOVS: u1, + reserved29: u19, + /// Low frequency trigger mode enable + LFTRIG: u1, + /// ADC clock mode + CKMODE: u2, + }), + /// ADC sampling time register + SMPR: mmio.Mmio(packed struct(u32) { + /// Sampling time selection + SMP1: packed union { + raw: u3, + value: SAMPLE_TIME, }, - /// High-speed IO at low VDDIO2 voltage configuration bit This bit can be set only with VDDIO2 below 2.5 V. - IO_VDDIO2_HSLV: packed union { - raw: u1, - value: IO_VDDIO_HSLV, + reserved4: u1, + /// Sampling time selection + SMP2: packed union { + raw: u3, + value: SAMPLE_TIME, }, - /// Global TrustZone security enable - TZEN: u1, + reserved8: u1, + /// Channel sampling time selection + SMPSEL: u1, + padding: u23, }), - /// FLASH non-secure boot address 0 register - NSBOOTADD0R: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// Non-secure boot base address 0 The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000) - NSBOOTADD0: u25, + reserved32: [8]u8, + /// watchdog threshold register + AWD1TR: mmio.Mmio(packed struct(u32) { + /// ADC analog watchdog 1 threshold low + LT1: u12, + reserved16: u4, + /// ADC analog watchdog 1 threshold high + HT1: u12, + padding: u4, }), - /// FLASH non-secure boot address 1 register - NSBOOTADD1R: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// Non-secure boot address 1 The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000) - NSBOOTADD1: u25, + /// watchdog threshold register + AWD2TR: mmio.Mmio(packed struct(u32) { + /// ADC analog watchdog 2 threshold low + LT2: u12, + reserved16: u4, + /// ADC analog watchdog 2 threshold high + HT2: u12, + padding: u4, }), - /// FLASH secure boot address 0 register - SECBOOTADD0R: mmio.Mmio(packed struct(u32) { - /// Boot lock When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0. - BOOT_LOCK: u1, - reserved7: u6, - /// Secure boot base address 0 The secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: SECBOOTADD0[24:0] = 0x018 0000: Boot from secure Flash memory (0x0C00 0000) SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS (0x0FF8 0000) SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000) - SECBOOTADD0: u25, + /// channel selection register + CHSELR: mmio.Mmio(packed struct(u32) { + /// Channel-x selection + CHSEL: u19, + padding: u13, }), - /// FLASH secure watermark1 register 1 - SECWM1R1: mmio.Mmio(packed struct(u32) { - /// Start page of first secure area This field contains the first page of the secure area in bank 1. - SECWM1_PSTRT: u7, - reserved16: u9, - /// End page of first secure area This field contains the last page of the secure area in bank 1. - SECWM1_PEND: u7, - padding: u9, + /// watchdog threshold register + AWD3TR: mmio.Mmio(packed struct(u32) { + /// ADC analog watchdog 3 threshold high + LT3: u12, + reserved16: u4, + /// ADC analog watchdog 3 threshold high + HT3: u12, + padding: u4, }), - /// FLASH secure watermark1 register 2 - SECWM1R2: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// End page of first hide protection area This field contains the last page of the HDP area in bank 1. - HDP1_PEND: u7, - reserved31: u8, - /// Hide protection first area enable - HDP1EN: u1, + reserved64: [16]u8, + /// ADC group regular conversion data register + DR: mmio.Mmio(packed struct(u32) { + /// ADC group regular conversion data + regularDATA: u16, + padding: u16, }), - /// FLASH WRP1 area A address register - WRP1AR: mmio.Mmio(packed struct(u32) { - /// bank 1 WPR first area A start page This field contains the first page of the first WPR area for bank 1. - WRP1A_PSTRT: u7, - reserved16: u9, - /// Bank 1 WPR first area A end page This field contains the last page of the first WPR area in bank 1. - WRP1A_PEND: u7, - reserved31: u8, - /// Bank 1 WPR first area A unlock - UNLOCK: packed union { - raw: u1, - value: WRPAR_UNLOCK, - }, + reserved160: [92]u8, + /// ADC analog watchdog 2 configuration register + AWD2CR: mmio.Mmio(packed struct(u32) { + /// ADC analog watchdog 2 monitored channel selection + AWD2CH: u19, + padding: u13, }), - /// FLASH WRP1 area B address register - WRP1BR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP second area B start page This field contains the first page of the second WRP area for bank 1. - WRP1B_PSTRT: u7, - reserved16: u9, - /// Bank 1 WRP second area B end page This field contains the last page of the second WRP area in bank 1. - WRP1B_PEND: u7, - reserved31: u8, - /// Bank 1 WPR second area B unlock - UNLOCK: packed union { - raw: u1, - value: WRPBR_UNLOCK, - }, + /// ADC analog watchdog 3 configuration register + AWD3CR: mmio.Mmio(packed struct(u32) { + /// ADC analog watchdog 3 monitored channel selection + AWD3CH: u19, + padding: u13, }), - /// FLASH secure watermark2 register 1 - SECWM2R1: mmio.Mmio(packed struct(u32) { - /// Start page of second secure area This field contains the first page of the secure area in bank 2. - SECWM2_PSTRT: u7, - reserved16: u9, - /// End page of second secure area This field contains the last page of the secure area in bank 2. - SECWM2_PEND: u7, - padding: u9, + reserved180: [12]u8, + /// ADC calibration factors register + CALFACT: mmio.Mmio(packed struct(u32) { + /// ADC calibration factor in single-ended mode + CALFACT: u7, + padding: u25, }), - /// FLASH secure watermark2 register 2 - SECWM2R2: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// End page of hide protection second area HDP2_PEND contains the last page of the HDP area in bank 2. - HDP2_PEND: u7, - reserved31: u8, - /// Hide protection second area enable - HDP2EN: u1, + reserved776: [592]u8, + /// ADC common control register + CCR: mmio.Mmio(packed struct(u32) { + reserved18: u18, + /// ADC prescaler + PRESC: u4, + /// VREFINT enable + VREFEN: u1, + /// Temperature sensor enable + TSEN: u1, + /// VBAT enable + VBATEN: u1, + padding: u7, }), - /// FLASH WPR2 area A address register - WRP2AR: mmio.Mmio(packed struct(u32) { - /// Bank 2 WPR first area A start page This field contains the first page of the first WRP area for bank 2. - WRP2A_PSTRT: u7, - reserved16: u9, - /// Bank 2 WPR first area A end page This field contains the last page of the first WRP area in bank 2. - WRP2A_PEND: u7, - reserved31: u8, - /// Bank 2 WPR first area A unlock - UNLOCK: packed union { - raw: u1, - value: WRPAR_UNLOCK, - }, + }; + }; + + pub const adc_u5 = struct { + /// ADC. + pub const ADC = extern struct { + /// ADC interrupt and status register. + ISR: mmio.Mmio(packed struct(u32) { + /// ADRDY. + ADRDY: u1, + /// EOSMP. + EOSMP: u1, + /// EOC. + EOC: u1, + /// EOS. + EOS: u1, + /// OVR. + OVR: u1, + reserved7: u2, + /// AWD1. + AWD1: u1, + /// AWD2. + AWD2: u1, + /// AWD3. + AWD3: u1, + reserved11: u1, + /// EOCAL. + EOCAL: u1, + /// LDORDY. + LDORDY: u1, + padding: u19, }), - /// FLASH WPR2 area B address register - WRP2BR: mmio.Mmio(packed struct(u32) { - /// Bank 2 WPR second area B start page This field contains the first page of the second WRP area for bank 2. - WRP2B_PSTRT: u7, - reserved16: u9, - /// Bank 2 WPR second area B end page This field contains the last page of the second WRP area in bank 2. - WRP2B_PEND: u7, - reserved31: u8, - /// Bank 2 WPR second area B unlock - UNLOCK: packed union { - raw: u1, - value: WRPBR_UNLOCK, - }, + /// ADC interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// ADRDYIE. + ADRDYIE: u1, + /// EOSMPIE. + EOSMPIE: u1, + /// EOCIE. + EOCIE: u1, + /// EOSIE. + EOSIE: u1, + /// OVRIE. + OVRIE: u1, + reserved7: u2, + /// AWD1IE. + AWD1IE: u1, + /// AWD2IE. + AWD2IE: u1, + /// AWD3IE. + AWD3IE: u1, + reserved11: u1, + /// EOCALIE. + EOCALIE: u1, + /// LDORDYIE. + LDORDYIE: u1, + padding: u19, }), - /// FLASH OEM1 key register 1 - OEM1KEYR1: mmio.Mmio(packed struct(u32) { - /// OEM1 least significant bytes key - OEM1KEY: u32, + /// ADC control register. + CR: mmio.Mmio(packed struct(u32) { + /// ADEN. + ADEN: u1, + /// ADDIS. + ADDIS: u1, + /// ADSTART. + ADSTART: u1, + reserved4: u1, + /// ADSTP. + ADSTP: u1, + reserved28: u23, + /// ADVREGEN. + ADVREGEN: u1, + reserved31: u2, + /// ADCAL. + ADCAL: u1, }), - /// FLASH OEM1 key register 2 - OEM1KEYR2: mmio.Mmio(packed struct(u32) { - /// OEM1 most significant bytes key - OEM1KEY: u32, + /// ADC configuration register. + CFGR1: mmio.Mmio(packed struct(u32) { + /// DMAEN. + DMAEN: u1, + /// DMACFG. + DMACFG: u1, + /// RES. + RES: u2, + /// SCANDIR. + SCANDIR: u1, + /// ALIGN. + ALIGN: u1, + /// EXTSEL. + EXTSEL: u3, + reserved10: u1, + /// EXTEN. + EXTEN: u2, + /// OVRMOD. + OVRMOD: u1, + /// CONT. + CONT: u1, + /// WAIT. + WAIT: u1, + reserved16: u1, + /// DISCEN. + DISCEN: u1, + reserved21: u4, + /// CHSELRMOD. + CHSELRMOD: u1, + /// AWD1SGL. + AWD1SGL: u1, + /// AWD1EN. + AWD1EN: u1, + reserved26: u2, + /// AWD1CH. + AWD1CH: u5, + padding: u1, }), - /// FLASH OEM2 key register 1 - OEM2KEYR1: mmio.Mmio(packed struct(u32) { - /// OEM2 least significant bytes key - OEM2KEY: u32, + /// ADC configuration register 2. + CFGR2: mmio.Mmio(packed struct(u32) { + /// OVSE. + OVSE: u1, + reserved2: u1, + /// OVSR. + OVSR: u3, + /// OVSS. + OVSS: u4, + /// TOVS. + TOVS: u1, + reserved29: u19, + /// LFTRIG. + LFTRIG: u1, + padding: u2, }), - /// FLASH OEM2 key register 2 - OEM2KEYR2: mmio.Mmio(packed struct(u32) { - /// OEM2 most significant bytes key - OEM2KEY: u32, + /// ADC sample time register. + SMPR: mmio.Mmio(packed struct(u32) { + /// SMP1. + SMP1: u3, + reserved4: u1, + /// SMP2. + SMP2: u3, + reserved8: u1, + /// SMPSEL0. + SMPSEL0: u1, + /// SMPSEL1. + SMPSEL1: u1, + /// SMPSEL2. + SMPSEL2: u1, + /// SMPSEL3. + SMPSEL3: u1, + /// SMPSEL4. + SMPSEL4: u1, + /// SMPSEL5. + SMPSEL5: u1, + /// SMPSEL6. + SMPSEL6: u1, + /// SMPSEL7. + SMPSEL7: u1, + /// SMPSEL8. + SMPSEL8: u1, + /// SMPSEL9. + SMPSEL9: u1, + /// SMPSEL10. + SMPSEL10: u1, + /// SMPSEL11. + SMPSEL11: u1, + /// SMPSEL12. + SMPSEL12: u1, + /// SMPSEL13. + SMPSEL13: u1, + /// SMPSEL14. + SMPSEL14: u1, + /// SMPSEL15. + SMPSEL15: u1, + /// SMPSEL16. + SMPSEL16: u1, + /// SMPSEL17. + SMPSEL17: u1, + /// SMPSEL18. + SMPSEL18: u1, + /// SMPSEL19. + SMPSEL19: u1, + /// SMPSEL20. + SMPSEL20: u1, + /// SMPSEL21. + SMPSEL21: u1, + /// SMPSEL22. + SMPSEL22: u1, + /// SMPSEL23. + SMPSEL23: u1, }), - /// FLASH secure block based bank 1 register 1 - SEC1BBR1: mmio.Mmio(packed struct(u32) { - /// page secure/non-secure attribution - SEC1BB0: u1, - /// page secure/non-secure attribution - SEC1BB1: u1, - /// page secure/non-secure attribution - SEC1BB2: u1, - /// page secure/non-secure attribution - SEC1BB3: u1, - /// page secure/non-secure attribution - SEC1BB4: u1, - /// page secure/non-secure attribution - SEC1BB5: u1, - /// page secure/non-secure attribution - SEC1BB6: u1, - /// page secure/non-secure attribution - SEC1BB7: u1, - /// page secure/non-secure attribution - SEC1BB8: u1, - /// page secure/non-secure attribution - SEC1BB9: u1, - /// page secure/non-secure attribution - SEC1BB10: u1, - /// page secure/non-secure attribution - SEC1BB11: u1, - /// page secure/non-secure attribution - SEC1BB12: u1, - /// page secure/non-secure attribution - SEC1BB13: u1, - /// page secure/non-secure attribution - SEC1BB14: u1, - /// page secure/non-secure attribution - SEC1BB15: u1, - /// page secure/non-secure attribution - SEC1BB16: u1, - /// page secure/non-secure attribution - SEC1BB17: u1, - /// page secure/non-secure attribution - SEC1BB18: u1, - /// page secure/non-secure attribution - SEC1BB19: u1, - /// page secure/non-secure attribution - SEC1BB20: u1, - /// page secure/non-secure attribution - SEC1BB21: u1, - /// page secure/non-secure attribution - SEC1BB22: u1, - /// page secure/non-secure attribution - SEC1BB23: u1, - /// page secure/non-secure attribution - SEC1BB24: u1, - /// page secure/non-secure attribution - SEC1BB25: u1, - /// page secure/non-secure attribution - SEC1BB26: u1, - /// page secure/non-secure attribution - SEC1BB27: u1, - /// page secure/non-secure attribution - SEC1BB28: u1, - /// page secure/non-secure attribution - SEC1BB29: u1, - /// page secure/non-secure attribution - SEC1BB30: u1, - /// page secure/non-secure attribution - SEC1BB31: u1, + reserved32: [8]u8, + /// ADC watchdog threshold register. + AWD1TR: mmio.Mmio(packed struct(u32) { + /// LT1. + LT1: u12, + reserved16: u4, + /// HT1. + HT1: u12, + padding: u4, }), - /// FLASH secure block based bank 1 register 2 - SEC1BBR2: mmio.Mmio(packed struct(u32) { - /// page secure/non-secure attribution - SEC1BB0: u1, - /// page secure/non-secure attribution - SEC1BB1: u1, - /// page secure/non-secure attribution - SEC1BB2: u1, - /// page secure/non-secure attribution - SEC1BB3: u1, - /// page secure/non-secure attribution - SEC1BB4: u1, - /// page secure/non-secure attribution - SEC1BB5: u1, - /// page secure/non-secure attribution - SEC1BB6: u1, - /// page secure/non-secure attribution - SEC1BB7: u1, - /// page secure/non-secure attribution - SEC1BB8: u1, - /// page secure/non-secure attribution - SEC1BB9: u1, - /// page secure/non-secure attribution - SEC1BB10: u1, - /// page secure/non-secure attribution - SEC1BB11: u1, - /// page secure/non-secure attribution - SEC1BB12: u1, - /// page secure/non-secure attribution - SEC1BB13: u1, - /// page secure/non-secure attribution - SEC1BB14: u1, - /// page secure/non-secure attribution - SEC1BB15: u1, - /// page secure/non-secure attribution - SEC1BB16: u1, - /// page secure/non-secure attribution - SEC1BB17: u1, - /// page secure/non-secure attribution - SEC1BB18: u1, - /// page secure/non-secure attribution - SEC1BB19: u1, - /// page secure/non-secure attribution - SEC1BB20: u1, - /// page secure/non-secure attribution - SEC1BB21: u1, - /// page secure/non-secure attribution - SEC1BB22: u1, - /// page secure/non-secure attribution - SEC1BB23: u1, - /// page secure/non-secure attribution - SEC1BB24: u1, - /// page secure/non-secure attribution - SEC1BB25: u1, - /// page secure/non-secure attribution - SEC1BB26: u1, - /// page secure/non-secure attribution - SEC1BB27: u1, - /// page secure/non-secure attribution - SEC1BB28: u1, - /// page secure/non-secure attribution - SEC1BB29: u1, - /// page secure/non-secure attribution - SEC1BB30: u1, - /// page secure/non-secure attribution - SEC1BB31: u1, + /// ADC watchdog threshold register. + AWD2TR: mmio.Mmio(packed struct(u32) { + /// LT2. + LT2: u12, + reserved16: u4, + /// HT2. + HT2: u12, + padding: u4, }), - /// FLASH secure block based bank 1 register 3 - SEC1BBR3: mmio.Mmio(packed struct(u32) { - /// page secure/non-secure attribution - SEC1BB0: u1, - /// page secure/non-secure attribution - SEC1BB1: u1, - /// page secure/non-secure attribution - SEC1BB2: u1, - /// page secure/non-secure attribution - SEC1BB3: u1, - /// page secure/non-secure attribution - SEC1BB4: u1, - /// page secure/non-secure attribution - SEC1BB5: u1, - /// page secure/non-secure attribution - SEC1BB6: u1, - /// page secure/non-secure attribution - SEC1BB7: u1, - /// page secure/non-secure attribution - SEC1BB8: u1, - /// page secure/non-secure attribution - SEC1BB9: u1, - /// page secure/non-secure attribution - SEC1BB10: u1, - /// page secure/non-secure attribution - SEC1BB11: u1, - /// page secure/non-secure attribution - SEC1BB12: u1, - /// page secure/non-secure attribution - SEC1BB13: u1, - /// page secure/non-secure attribution - SEC1BB14: u1, - /// page secure/non-secure attribution - SEC1BB15: u1, - /// page secure/non-secure attribution - SEC1BB16: u1, - /// page secure/non-secure attribution - SEC1BB17: u1, - /// page secure/non-secure attribution - SEC1BB18: u1, - /// page secure/non-secure attribution - SEC1BB19: u1, - /// page secure/non-secure attribution - SEC1BB20: u1, - /// page secure/non-secure attribution - SEC1BB21: u1, - /// page secure/non-secure attribution - SEC1BB22: u1, - /// page secure/non-secure attribution - SEC1BB23: u1, - /// page secure/non-secure attribution - SEC1BB24: u1, - /// page secure/non-secure attribution - SEC1BB25: u1, - /// page secure/non-secure attribution - SEC1BB26: u1, - /// page secure/non-secure attribution - SEC1BB27: u1, - /// page secure/non-secure attribution - SEC1BB28: u1, - /// page secure/non-secure attribution - SEC1BB29: u1, - /// page secure/non-secure attribution - SEC1BB30: u1, - /// page secure/non-secure attribution - SEC1BB31: u1, + /// ADC channel selection register [alternate]. + CHSELRMOD0: mmio.Mmio(packed struct(u32) { + /// CHSEL. + CHSEL: u24, + padding: u8, }), - /// FLASH secure block based bank 1 register 4 - SEC1BBR4: mmio.Mmio(packed struct(u32) { - /// page secure/non-secure attribution - SEC1BB0: u1, - /// page secure/non-secure attribution - SEC1BB1: u1, - /// page secure/non-secure attribution - SEC1BB2: u1, - /// page secure/non-secure attribution - SEC1BB3: u1, - /// page secure/non-secure attribution - SEC1BB4: u1, - /// page secure/non-secure attribution - SEC1BB5: u1, - /// page secure/non-secure attribution - SEC1BB6: u1, - /// page secure/non-secure attribution - SEC1BB7: u1, - /// page secure/non-secure attribution - SEC1BB8: u1, - /// page secure/non-secure attribution - SEC1BB9: u1, - /// page secure/non-secure attribution - SEC1BB10: u1, - /// page secure/non-secure attribution - SEC1BB11: u1, - /// page secure/non-secure attribution - SEC1BB12: u1, - /// page secure/non-secure attribution - SEC1BB13: u1, - /// page secure/non-secure attribution - SEC1BB14: u1, - /// page secure/non-secure attribution - SEC1BB15: u1, - /// page secure/non-secure attribution - SEC1BB16: u1, - /// page secure/non-secure attribution - SEC1BB17: u1, - /// page secure/non-secure attribution - SEC1BB18: u1, - /// page secure/non-secure attribution - SEC1BB19: u1, - /// page secure/non-secure attribution - SEC1BB20: u1, - /// page secure/non-secure attribution - SEC1BB21: u1, - /// page secure/non-secure attribution - SEC1BB22: u1, - /// page secure/non-secure attribution - SEC1BB23: u1, - /// page secure/non-secure attribution - SEC1BB24: u1, - /// page secure/non-secure attribution - SEC1BB25: u1, - /// page secure/non-secure attribution - SEC1BB26: u1, - /// page secure/non-secure attribution - SEC1BB27: u1, - /// page secure/non-secure attribution - SEC1BB28: u1, - /// page secure/non-secure attribution - SEC1BB29: u1, - /// page secure/non-secure attribution - SEC1BB30: u1, - /// page secure/non-secure attribution - SEC1BB31: u1, + /// ADC watchdog threshold register. + AWD3TR: mmio.Mmio(packed struct(u32) { + /// LT3. + LT3: u12, + reserved16: u4, + /// HT3. + HT3: u12, + padding: u4, }), - reserved160: [16]u8, - /// FLASH secure block based bank 2 register 1 - SEC2BBR1: mmio.Mmio(packed struct(u32) { - /// page secure/non-secure attribution - SEC2BB0: u1, - /// page secure/non-secure attribution - SEC2BB1: u1, - /// page secure/non-secure attribution - SEC2BB2: u1, - /// page secure/non-secure attribution - SEC2BB3: u1, - /// page secure/non-secure attribution - SEC2BB4: u1, - /// page secure/non-secure attribution - SEC2BB5: u1, - /// page secure/non-secure attribution - SEC2BB6: u1, - /// page secure/non-secure attribution - SEC2BB7: u1, - /// page secure/non-secure attribution - SEC2BB8: u1, - /// page secure/non-secure attribution - SEC2BB9: u1, - /// page secure/non-secure attribution - SEC2BB10: u1, - /// page secure/non-secure attribution - SEC2BB11: u1, - /// page secure/non-secure attribution - SEC2BB12: u1, - /// page secure/non-secure attribution - SEC2BB13: u1, - /// page secure/non-secure attribution - SEC2BB14: u1, - /// page secure/non-secure attribution - SEC2BB15: u1, - /// page secure/non-secure attribution - SEC2BB16: u1, - /// page secure/non-secure attribution - SEC2BB17: u1, - /// page secure/non-secure attribution - SEC2BB18: u1, - /// page secure/non-secure attribution - SEC2BB19: u1, - /// page secure/non-secure attribution - SEC2BB20: u1, - /// page secure/non-secure attribution - SEC2BB21: u1, - /// page secure/non-secure attribution - SEC2BB22: u1, - /// page secure/non-secure attribution - SEC2BB23: u1, - /// page secure/non-secure attribution - SEC2BB24: u1, - /// page secure/non-secure attribution - SEC2BB25: u1, - /// page secure/non-secure attribution - SEC2BB26: u1, - /// page secure/non-secure attribution - SEC2BB27: u1, - /// page secure/non-secure attribution - SEC2BB28: u1, - /// page secure/non-secure attribution - SEC2BB29: u1, - /// page secure/non-secure attribution - SEC2BB30: u1, - /// page secure/non-secure attribution - SEC2BB31: u1, + reserved64: [16]u8, + /// ADC data register. + DR: mmio.Mmio(packed struct(u32) { + /// DATA. + DATA: u16, + padding: u16, }), - /// FLASH secure block based bank 2 register 2 - SEC2BBR2: mmio.Mmio(packed struct(u32) { - /// page secure/non-secure attribution - SEC2BB0: u1, - /// page secure/non-secure attribution - SEC2BB1: u1, - /// page secure/non-secure attribution - SEC2BB2: u1, - /// page secure/non-secure attribution - SEC2BB3: u1, - /// page secure/non-secure attribution - SEC2BB4: u1, - /// page secure/non-secure attribution - SEC2BB5: u1, - /// page secure/non-secure attribution - SEC2BB6: u1, - /// page secure/non-secure attribution - SEC2BB7: u1, - /// page secure/non-secure attribution - SEC2BB8: u1, - /// page secure/non-secure attribution - SEC2BB9: u1, - /// page secure/non-secure attribution - SEC2BB10: u1, - /// page secure/non-secure attribution - SEC2BB11: u1, - /// page secure/non-secure attribution - SEC2BB12: u1, - /// page secure/non-secure attribution - SEC2BB13: u1, - /// page secure/non-secure attribution - SEC2BB14: u1, - /// page secure/non-secure attribution - SEC2BB15: u1, - /// page secure/non-secure attribution - SEC2BB16: u1, - /// page secure/non-secure attribution - SEC2BB17: u1, - /// page secure/non-secure attribution - SEC2BB18: u1, - /// page secure/non-secure attribution - SEC2BB19: u1, - /// page secure/non-secure attribution - SEC2BB20: u1, - /// page secure/non-secure attribution - SEC2BB21: u1, - /// page secure/non-secure attribution - SEC2BB22: u1, - /// page secure/non-secure attribution - SEC2BB23: u1, - /// page secure/non-secure attribution - SEC2BB24: u1, - /// page secure/non-secure attribution - SEC2BB25: u1, - /// page secure/non-secure attribution - SEC2BB26: u1, - /// page secure/non-secure attribution - SEC2BB27: u1, - /// page secure/non-secure attribution - SEC2BB28: u1, - /// page secure/non-secure attribution - SEC2BB29: u1, - /// page secure/non-secure attribution - SEC2BB30: u1, - /// page secure/non-secure attribution - SEC2BB31: u1, + /// ADC data register. + PWRR: mmio.Mmio(packed struct(u32) { + /// AUTOFF. + AUTOFF: u1, + /// DPD. + DPD: u1, + /// VREFPROT. + VREFPROT: u1, + /// VREFSECSMP. + VREFSECSMP: u1, + padding: u28, }), - /// FLASH secure block based bank 2 register 3 - SEC2BBR3: mmio.Mmio(packed struct(u32) { - /// page secure/non-secure attribution - SEC2BB0: u1, - /// page secure/non-secure attribution - SEC2BB1: u1, - /// page secure/non-secure attribution - SEC2BB2: u1, - /// page secure/non-secure attribution - SEC2BB3: u1, - /// page secure/non-secure attribution - SEC2BB4: u1, - /// page secure/non-secure attribution - SEC2BB5: u1, - /// page secure/non-secure attribution - SEC2BB6: u1, - /// page secure/non-secure attribution - SEC2BB7: u1, - /// page secure/non-secure attribution - SEC2BB8: u1, - /// page secure/non-secure attribution - SEC2BB9: u1, - /// page secure/non-secure attribution - SEC2BB10: u1, - /// page secure/non-secure attribution - SEC2BB11: u1, - /// page secure/non-secure attribution - SEC2BB12: u1, - /// page secure/non-secure attribution - SEC2BB13: u1, - /// page secure/non-secure attribution - SEC2BB14: u1, - /// page secure/non-secure attribution - SEC2BB15: u1, - /// page secure/non-secure attribution - SEC2BB16: u1, - /// page secure/non-secure attribution - SEC2BB17: u1, - /// page secure/non-secure attribution - SEC2BB18: u1, - /// page secure/non-secure attribution - SEC2BB19: u1, - /// page secure/non-secure attribution - SEC2BB20: u1, - /// page secure/non-secure attribution - SEC2BB21: u1, - /// page secure/non-secure attribution - SEC2BB22: u1, - /// page secure/non-secure attribution - SEC2BB23: u1, - /// page secure/non-secure attribution - SEC2BB24: u1, - /// page secure/non-secure attribution - SEC2BB25: u1, - /// page secure/non-secure attribution - SEC2BB26: u1, - /// page secure/non-secure attribution - SEC2BB27: u1, - /// page secure/non-secure attribution - SEC2BB28: u1, - /// page secure/non-secure attribution - SEC2BB29: u1, - /// page secure/non-secure attribution - SEC2BB30: u1, - /// page secure/non-secure attribution - SEC2BB31: u1, + reserved160: [88]u8, + /// ADC Analog Watchdog 2 Configuration register. + AWD2CR: mmio.Mmio(packed struct(u32) { + /// AWD2CH0. + AWD2CH0: u1, + /// AWD2CH1. + AWD2CH1: u1, + /// AWD2CH2. + AWD2CH2: u1, + /// AWD2CH3. + AWD2CH3: u1, + /// AWD2CH4. + AWD2CH4: u1, + /// AWD2CH5. + AWD2CH5: u1, + /// AWD2CH6. + AWD2CH6: u1, + /// AWD2CH7. + AWD2CH7: u1, + /// AWD2CH8. + AWD2CH8: u1, + /// AWD2CH9. + AWD2CH9: u1, + /// AWD2CH10. + AWD2CH10: u1, + /// AWD2CH11. + AWD2CH11: u1, + /// AWD2CH12. + AWD2CH12: u1, + /// AWD2CH13. + AWD2CH13: u1, + /// AWD2CH14. + AWD2CH14: u1, + /// AWD2CH15. + AWD2CH15: u1, + /// AWD2CH16. + AWD2CH16: u1, + /// AWD2CH17. + AWD2CH17: u1, + /// AWD2CH18. + AWD2CH18: u1, + /// AWD2CH19. + AWD2CH19: u1, + /// AWD2CH20. + AWD2CH20: u1, + /// AWD2CH21. + AWD2CH21: u1, + /// AWD2CH22. + AWD2CH22: u1, + /// AWD2CH23. + AWD2CH23: u1, + padding: u8, }), - /// FLASH secure block based bank 2 register 4 - SEC2BBR4: mmio.Mmio(packed struct(u32) { - /// page secure/non-secure attribution - SEC2BB0: u1, - /// page secure/non-secure attribution - SEC2BB1: u1, - /// page secure/non-secure attribution - SEC2BB2: u1, - /// page secure/non-secure attribution - SEC2BB3: u1, - /// page secure/non-secure attribution - SEC2BB4: u1, - /// page secure/non-secure attribution - SEC2BB5: u1, - /// page secure/non-secure attribution - SEC2BB6: u1, - /// page secure/non-secure attribution - SEC2BB7: u1, - /// page secure/non-secure attribution - SEC2BB8: u1, - /// page secure/non-secure attribution - SEC2BB9: u1, - /// page secure/non-secure attribution - SEC2BB10: u1, - /// page secure/non-secure attribution - SEC2BB11: u1, - /// page secure/non-secure attribution - SEC2BB12: u1, - /// page secure/non-secure attribution - SEC2BB13: u1, - /// page secure/non-secure attribution - SEC2BB14: u1, - /// page secure/non-secure attribution - SEC2BB15: u1, - /// page secure/non-secure attribution - SEC2BB16: u1, - /// page secure/non-secure attribution - SEC2BB17: u1, - /// page secure/non-secure attribution - SEC2BB18: u1, - /// page secure/non-secure attribution - SEC2BB19: u1, - /// page secure/non-secure attribution - SEC2BB20: u1, - /// page secure/non-secure attribution - SEC2BB21: u1, - /// page secure/non-secure attribution - SEC2BB22: u1, - /// page secure/non-secure attribution - SEC2BB23: u1, - /// page secure/non-secure attribution - SEC2BB24: u1, - /// page secure/non-secure attribution - SEC2BB25: u1, - /// page secure/non-secure attribution - SEC2BB26: u1, - /// page secure/non-secure attribution - SEC2BB27: u1, - /// page secure/non-secure attribution - SEC2BB28: u1, - /// page secure/non-secure attribution - SEC2BB29: u1, - /// page secure/non-secure attribution - SEC2BB30: u1, - /// page secure/non-secure attribution - SEC2BB31: u1, + /// ADC Analog Watchdog 3 Configuration register. + AWD3CR: mmio.Mmio(packed struct(u32) { + /// AWD3CH0. + AWD3CH0: u1, + /// AWD3CH1. + AWD3CH1: u1, + /// AWD3CH2. + AWD3CH2: u1, + /// AWD3CH3. + AWD3CH3: u1, + /// AWD3CH4. + AWD3CH4: u1, + /// AWD3CH5. + AWD3CH5: u1, + /// AWD3CH6. + AWD3CH6: u1, + /// AWD3CH7. + AWD3CH7: u1, + /// AWD3CH8. + AWD3CH8: u1, + /// AWD3CH9. + AWD3CH9: u1, + /// AWD3CH10. + AWD3CH10: u1, + /// AWD3CH11. + AWD3CH11: u1, + /// AWD3CH12. + AWD3CH12: u1, + /// AWD3CH13. + AWD3CH13: u1, + /// AWD3CH14. + AWD3CH14: u1, + /// AWD3CH15. + AWD3CH15: u1, + /// AWD3CH16. + AWD3CH16: u1, + /// AWD3CH17. + AWD3CH17: u1, + /// AWD3CH18. + AWD3CH18: u1, + /// AWD3CH19. + AWD3CH19: u1, + /// AWD3CH20. + AWD3CH20: u1, + /// AWD3CH21. + AWD3CH21: u1, + /// AWD3CH22. + AWD3CH22: u1, + /// AWD3CH23. + AWD3CH23: u1, + padding: u8, }), - reserved192: [16]u8, - /// FLASH secure HDP control register - SECHDPCR: mmio.Mmio(packed struct(u32) { - /// HDP1 area access disable When set, this bit is only cleared by a system reset. - HDP1_ACCDIS: packed union { + reserved196: [28]u8, + /// ADC Calibration factor. + CALFACT: mmio.Mmio(packed struct(u32) { + /// CALFACT. + CALFACT: u7, + padding: u25, + }), + reserved208: [8]u8, + /// ADC option register. + OR: mmio.Mmio(packed struct(u32) { + /// CHN21SEL. + CHN21SEL: u1, + padding: u31, + }), + reserved776: [564]u8, + /// ADC common configuration register. + CCR: mmio.Mmio(packed struct(u32) { + reserved18: u18, + /// PRESC. + PRESC: u4, + /// VREFEN. + VREFEN: u1, + /// VSENSESEL. + VSENSESEL: u1, + /// VBATEN. + VBATEN: u1, + padding: u7, + }), + }; + }; + + pub const adc_v1 = struct { + pub const ALIGN = enum(u1) { + /// Right alignment + Right = 0x0, + /// Left alignment + Left = 0x1, + }; + + pub const AWDSGL = enum(u1) { + /// Analog watchdog enabled on all channels + AllChannels = 0x0, + /// Analog watchdog enabled on a single channel + SingleChannel = 0x1, + }; + + pub const CKMODE = enum(u2) { + /// Asynchronous clock mode + ADCCLK = 0x0, + /// Synchronous clock mode (PCLK/2) + PCLK_Div2 = 0x1, + /// Sychronous clock mode (PCLK/4) + PCLK_Div4 = 0x2, + _, + }; + + pub const DMACFG = enum(u1) { + /// DMA One Shot mode selected + OneShot = 0x0, + /// DMA Circular mode selected + Circular = 0x1, + }; + + pub const EXTEN = enum(u2) { + /// Trigger detection disabled + Disabled = 0x0, + /// Trigger detection on the rising edge + RisingEdge = 0x1, + /// Trigger detection on the falling edge + FallingEdge = 0x2, + /// Trigger detection on both the rising and falling edges + BothEdges = 0x3, + }; + + pub const OVRMOD = enum(u1) { + /// ADC_DR register is preserved with the old data when an overrun is detected + Preserved = 0x0, + /// ADC_DR register is overwritten with the last conversion result when an overrun is detected + Overwritten = 0x1, + }; + + pub const RES = enum(u2) { + /// 12-bit (14 ADCCLK cycles) + Bits12 = 0x0, + /// 10-bit (13 ADCCLK cycles) + Bits10 = 0x1, + /// 8-bit (11 ADCCLK cycles) + Bits8 = 0x2, + /// 6-bit (9 ADCCLK cycles) + Bits6 = 0x3, + }; + + pub const SAMPLE_TIME = enum(u3) { + /// 1.5 cycles + Cycles1_5 = 0x0, + /// 7.5 cycles + Cycles7_5 = 0x1, + /// 13.5 cycles + Cycles13_5 = 0x2, + /// 28.5 cycles + Cycles28_5 = 0x3, + /// 41.5 cycles + Cycles41_5 = 0x4, + /// 55.5 cycles + Cycles55_5 = 0x5, + /// 71.5 cycles + Cycles71_5 = 0x6, + /// 239.5 cycles + Cycles239_5 = 0x7, + }; + + pub const SCANDIR = enum(u1) { + /// Upward scan (from CHSEL0 to CHSEL18) + Upward = 0x0, + /// Backward scan (from CHSEL18 to CHSEL0) + Backward = 0x1, + }; + + /// Analog-to-digital converter + pub const ADC = extern struct { + /// interrupt and status register + ISR: mmio.Mmio(packed struct(u32) { + /// ADC ready + ADRDY: u1, + /// End of sampling flag + EOSMP: u1, + /// End of conversion flag + EOC: u1, + /// End of sequence flag + EOSEQ: u1, + /// ADC overrun + OVR: u1, + reserved7: u2, + /// Analog watchdog flag + AWD: u1, + padding: u24, + }), + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// ADC ready interrupt enable + ADRDYIE: u1, + /// End of sampling flag interrupt enable + EOSMPIE: u1, + /// End of conversion interrupt enable + EOCIE: u1, + /// End of conversion sequence interrupt enable + EOSEQIE: u1, + /// Overrun interrupt enable + OVRIE: u1, + reserved7: u2, + /// Analog watchdog interrupt enable + AWDIE: u1, + padding: u24, + }), + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// ADC enable command + ADEN: u1, + /// ADC disable command + ADDIS: u1, + /// ADC start conversion command + ADSTART: u1, + reserved4: u1, + /// ADC stop conversion command + ADSTP: u1, + reserved31: u26, + /// ADC calibration + ADCAL: u1, + }), + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// Direct memory access enable + DMAEN: u1, + /// Direct memory access configuration + DMACFG: packed union { raw: u1, - value: HDP_ACCDIS, + value: DMACFG, }, - /// HDP2 area access disable When set, this bit is only cleared by a system reset. - HDP2_ACCDIS: packed union { + /// Scan sequence direction + SCANDIR: packed union { raw: u1, - value: HDP_ACCDIS, + value: SCANDIR, }, - padding: u30, - }), - /// FLASH privilege configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// Privileged protection for secure registers This bit can be accessed only when TrustZone is enabled (TZEN = 1). This bit can be read by both privileged or unprivileged, secure and non-secure access. The SPRIV bit can be written only by a secure privileged access. A non-secure write access on SPRIV bit is ignored. A secure unprivileged write access on SPRIV bit is ignored. - SPRIV: packed union { + /// Data resolution + RES: packed union { + raw: u2, + value: RES, + }, + /// Data alignment + ALIGN: packed union { raw: u1, - value: SPRIV, + value: ALIGN, }, - /// Privileged protection for non-secure registers This bit can be read by both privileged or unprivileged, secure and non-secure access. The NSPRIV bit can be written by a secure or non-secure privileged access. A secure or non-secure unprivileged write access on NSPRIV bit is ignored. - NSPRIV: packed union { + /// External trigger selection + EXTSEL: u3, + reserved10: u1, + /// External trigger enable and polarity selection + EXTEN: packed union { + raw: u2, + value: EXTEN, + }, + /// Overrun management mode + OVRMOD: packed union { raw: u1, - value: NSPRIV, + value: OVRMOD, }, - padding: u30, + /// Continuous conversion + CONT: u1, + /// Wait conversion mode + WAIT: u1, + /// Auto-off mode + AUTOFF: u1, + /// Discontinuous mode + DISCEN: u1, + reserved22: u5, + /// Enable the watchdog on a single channel or on all channels + AWDSGL: packed union { + raw: u1, + value: AWDSGL, + }, + /// Analog watchdog enable + AWDEN: u1, + reserved26: u2, + /// Analog watchdog channel selection + AWDCH: u5, + padding: u1, }), - reserved208: [8]u8, - /// FLASH privilege block based bank 1 register 1 - PRIV1BBR1: mmio.Mmio(packed struct(u32) { - /// page privileged/unprivileged attribution - PRIV1BB0: u1, - /// page privileged/unprivileged attribution - PRIV1BB1: u1, - /// page privileged/unprivileged attribution - PRIV1BB2: u1, - /// page privileged/unprivileged attribution - PRIV1BB3: u1, - /// page privileged/unprivileged attribution - PRIV1BB4: u1, - /// page privileged/unprivileged attribution - PRIV1BB5: u1, - /// page privileged/unprivileged attribution - PRIV1BB6: u1, - /// page privileged/unprivileged attribution - PRIV1BB7: u1, - /// page privileged/unprivileged attribution - PRIV1BB8: u1, - /// page privileged/unprivileged attribution - PRIV1BB9: u1, - /// page privileged/unprivileged attribution - PRIV1BB10: u1, - /// page privileged/unprivileged attribution - PRIV1BB11: u1, - /// page privileged/unprivileged attribution - PRIV1BB12: u1, - /// page privileged/unprivileged attribution - PRIV1BB13: u1, - /// page privileged/unprivileged attribution - PRIV1BB14: u1, - /// page privileged/unprivileged attribution - PRIV1BB15: u1, - /// page privileged/unprivileged attribution - PRIV1BB16: u1, - /// page privileged/unprivileged attribution - PRIV1BB17: u1, - /// page privileged/unprivileged attribution - PRIV1BB18: u1, - /// page privileged/unprivileged attribution - PRIV1BB19: u1, - /// page privileged/unprivileged attribution - PRIV1BB20: u1, - /// page privileged/unprivileged attribution - PRIV1BB21: u1, - /// page privileged/unprivileged attribution - PRIV1BB22: u1, - /// page privileged/unprivileged attribution - PRIV1BB23: u1, - /// page privileged/unprivileged attribution - PRIV1BB24: u1, - /// page privileged/unprivileged attribution - PRIV1BB25: u1, - /// page privileged/unprivileged attribution - PRIV1BB26: u1, - /// page privileged/unprivileged attribution - PRIV1BB27: u1, - /// page privileged/unprivileged attribution - PRIV1BB28: u1, - /// page privileged/unprivileged attribution - PRIV1BB29: u1, - /// page privileged/unprivileged attribution - PRIV1BB30: u1, - /// page privileged/unprivileged attribution - PRIV1BB31: u1, + /// configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + reserved30: u30, + /// ADC clock mode + CKMODE: packed union { + raw: u2, + value: CKMODE, + }, }), - /// FLASH privilege block based bank 1 register 2 - PRIV1BBR2: mmio.Mmio(packed struct(u32) { - /// page privileged/unprivileged attribution - PRIV1BB0: u1, - /// page privileged/unprivileged attribution - PRIV1BB1: u1, - /// page privileged/unprivileged attribution - PRIV1BB2: u1, - /// page privileged/unprivileged attribution - PRIV1BB3: u1, - /// page privileged/unprivileged attribution - PRIV1BB4: u1, - /// page privileged/unprivileged attribution - PRIV1BB5: u1, - /// page privileged/unprivileged attribution - PRIV1BB6: u1, - /// page privileged/unprivileged attribution - PRIV1BB7: u1, - /// page privileged/unprivileged attribution - PRIV1BB8: u1, - /// page privileged/unprivileged attribution - PRIV1BB9: u1, - /// page privileged/unprivileged attribution - PRIV1BB10: u1, - /// page privileged/unprivileged attribution - PRIV1BB11: u1, - /// page privileged/unprivileged attribution - PRIV1BB12: u1, - /// page privileged/unprivileged attribution - PRIV1BB13: u1, - /// page privileged/unprivileged attribution - PRIV1BB14: u1, - /// page privileged/unprivileged attribution - PRIV1BB15: u1, - /// page privileged/unprivileged attribution - PRIV1BB16: u1, - /// page privileged/unprivileged attribution - PRIV1BB17: u1, - /// page privileged/unprivileged attribution - PRIV1BB18: u1, - /// page privileged/unprivileged attribution - PRIV1BB19: u1, - /// page privileged/unprivileged attribution - PRIV1BB20: u1, - /// page privileged/unprivileged attribution - PRIV1BB21: u1, - /// page privileged/unprivileged attribution - PRIV1BB22: u1, - /// page privileged/unprivileged attribution - PRIV1BB23: u1, - /// page privileged/unprivileged attribution - PRIV1BB24: u1, - /// page privileged/unprivileged attribution - PRIV1BB25: u1, - /// page privileged/unprivileged attribution - PRIV1BB26: u1, - /// page privileged/unprivileged attribution - PRIV1BB27: u1, - /// page privileged/unprivileged attribution - PRIV1BB28: u1, - /// page privileged/unprivileged attribution - PRIV1BB29: u1, - /// page privileged/unprivileged attribution - PRIV1BB30: u1, - /// page privileged/unprivileged attribution - PRIV1BB31: u1, + /// sampling time register + SMPR: mmio.Mmio(packed struct(u32) { + /// Sampling time selection + SMP: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + padding: u29, }), - /// FLASH privilege block based bank 1 register 3 - PRIV1BBR3: mmio.Mmio(packed struct(u32) { - /// page privileged/unprivileged attribution - PRIV1BB0: u1, - /// page privileged/unprivileged attribution - PRIV1BB1: u1, - /// page privileged/unprivileged attribution - PRIV1BB2: u1, - /// page privileged/unprivileged attribution - PRIV1BB3: u1, - /// page privileged/unprivileged attribution - PRIV1BB4: u1, - /// page privileged/unprivileged attribution - PRIV1BB5: u1, - /// page privileged/unprivileged attribution - PRIV1BB6: u1, - /// page privileged/unprivileged attribution - PRIV1BB7: u1, - /// page privileged/unprivileged attribution - PRIV1BB8: u1, - /// page privileged/unprivileged attribution - PRIV1BB9: u1, - /// page privileged/unprivileged attribution - PRIV1BB10: u1, - /// page privileged/unprivileged attribution - PRIV1BB11: u1, - /// page privileged/unprivileged attribution - PRIV1BB12: u1, - /// page privileged/unprivileged attribution - PRIV1BB13: u1, - /// page privileged/unprivileged attribution - PRIV1BB14: u1, - /// page privileged/unprivileged attribution - PRIV1BB15: u1, - /// page privileged/unprivileged attribution - PRIV1BB16: u1, - /// page privileged/unprivileged attribution - PRIV1BB17: u1, - /// page privileged/unprivileged attribution - PRIV1BB18: u1, - /// page privileged/unprivileged attribution - PRIV1BB19: u1, - /// page privileged/unprivileged attribution - PRIV1BB20: u1, - /// page privileged/unprivileged attribution - PRIV1BB21: u1, - /// page privileged/unprivileged attribution - PRIV1BB22: u1, - /// page privileged/unprivileged attribution - PRIV1BB23: u1, - /// page privileged/unprivileged attribution - PRIV1BB24: u1, - /// page privileged/unprivileged attribution - PRIV1BB25: u1, - /// page privileged/unprivileged attribution - PRIV1BB26: u1, - /// page privileged/unprivileged attribution - PRIV1BB27: u1, - /// page privileged/unprivileged attribution - PRIV1BB28: u1, - /// page privileged/unprivileged attribution - PRIV1BB29: u1, - /// page privileged/unprivileged attribution - PRIV1BB30: u1, - /// page privileged/unprivileged attribution - PRIV1BB31: u1, + reserved32: [8]u8, + /// watchdog threshold register + TR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog lower threshold + LT: u12, + reserved16: u4, + /// Analog watchdog higher threshold + HT: u12, + padding: u4, }), - /// FLASH privilege block based bank 1 register 4 - PRIV1BBR4: mmio.Mmio(packed struct(u32) { - /// page privileged/unprivileged attribution - PRIV1BB0: u1, - /// page privileged/unprivileged attribution - PRIV1BB1: u1, - /// page privileged/unprivileged attribution - PRIV1BB2: u1, - /// page privileged/unprivileged attribution - PRIV1BB3: u1, - /// page privileged/unprivileged attribution - PRIV1BB4: u1, - /// page privileged/unprivileged attribution - PRIV1BB5: u1, - /// page privileged/unprivileged attribution - PRIV1BB6: u1, - /// page privileged/unprivileged attribution - PRIV1BB7: u1, - /// page privileged/unprivileged attribution - PRIV1BB8: u1, - /// page privileged/unprivileged attribution - PRIV1BB9: u1, - /// page privileged/unprivileged attribution - PRIV1BB10: u1, - /// page privileged/unprivileged attribution - PRIV1BB11: u1, - /// page privileged/unprivileged attribution - PRIV1BB12: u1, - /// page privileged/unprivileged attribution - PRIV1BB13: u1, - /// page privileged/unprivileged attribution - PRIV1BB14: u1, - /// page privileged/unprivileged attribution - PRIV1BB15: u1, - /// page privileged/unprivileged attribution - PRIV1BB16: u1, - /// page privileged/unprivileged attribution - PRIV1BB17: u1, - /// page privileged/unprivileged attribution - PRIV1BB18: u1, - /// page privileged/unprivileged attribution - PRIV1BB19: u1, - /// page privileged/unprivileged attribution - PRIV1BB20: u1, - /// page privileged/unprivileged attribution - PRIV1BB21: u1, - /// page privileged/unprivileged attribution - PRIV1BB22: u1, - /// page privileged/unprivileged attribution - PRIV1BB23: u1, - /// page privileged/unprivileged attribution - PRIV1BB24: u1, - /// page privileged/unprivileged attribution - PRIV1BB25: u1, - /// page privileged/unprivileged attribution - PRIV1BB26: u1, - /// page privileged/unprivileged attribution - PRIV1BB27: u1, - /// page privileged/unprivileged attribution - PRIV1BB28: u1, - /// page privileged/unprivileged attribution - PRIV1BB29: u1, - /// page privileged/unprivileged attribution - PRIV1BB30: u1, - /// page privileged/unprivileged attribution - PRIV1BB31: u1, + reserved40: [4]u8, + /// channel selection register + CHSELR: mmio.Mmio(packed struct(u32) { + /// Channel-x selection + @"CHSEL x": u1, + padding: u31, }), - reserved240: [16]u8, - /// FLASH privilege block based bank 2 register 1 - PRIV2BBR1: mmio.Mmio(packed struct(u32) { - /// page privileged/unprivileged attribution - PRIV2BB0: u1, - /// page privileged/unprivileged attribution - PRIV2BB1: u1, - /// page privileged/unprivileged attribution - PRIV2BB2: u1, - /// page privileged/unprivileged attribution - PRIV2BB3: u1, - /// page privileged/unprivileged attribution - PRIV2BB4: u1, - /// page privileged/unprivileged attribution - PRIV2BB5: u1, - /// page privileged/unprivileged attribution - PRIV2BB6: u1, - /// page privileged/unprivileged attribution - PRIV2BB7: u1, - /// page privileged/unprivileged attribution - PRIV2BB8: u1, - /// page privileged/unprivileged attribution - PRIV2BB9: u1, - /// page privileged/unprivileged attribution - PRIV2BB10: u1, - /// page privileged/unprivileged attribution - PRIV2BB11: u1, - /// page privileged/unprivileged attribution - PRIV2BB12: u1, - /// page privileged/unprivileged attribution - PRIV2BB13: u1, - /// page privileged/unprivileged attribution - PRIV2BB14: u1, - /// page privileged/unprivileged attribution - PRIV2BB15: u1, - /// page privileged/unprivileged attribution - PRIV2BB16: u1, - /// page privileged/unprivileged attribution - PRIV2BB17: u1, - /// page privileged/unprivileged attribution - PRIV2BB18: u1, - /// page privileged/unprivileged attribution - PRIV2BB19: u1, - /// page privileged/unprivileged attribution - PRIV2BB20: u1, - /// page privileged/unprivileged attribution - PRIV2BB21: u1, - /// page privileged/unprivileged attribution - PRIV2BB22: u1, - /// page privileged/unprivileged attribution - PRIV2BB23: u1, - /// page privileged/unprivileged attribution - PRIV2BB24: u1, - /// page privileged/unprivileged attribution - PRIV2BB25: u1, - /// page privileged/unprivileged attribution - PRIV2BB26: u1, - /// page privileged/unprivileged attribution - PRIV2BB27: u1, - /// page privileged/unprivileged attribution - PRIV2BB28: u1, - /// page privileged/unprivileged attribution - PRIV2BB29: u1, - /// page privileged/unprivileged attribution - PRIV2BB30: u1, - /// page privileged/unprivileged attribution - PRIV2BB31: u1, - }), - /// FLASH privilege block based bank 2 register 2 - PRIV2BBR2: mmio.Mmio(packed struct(u32) { - /// page privileged/unprivileged attribution - PRIV2BB0: u1, - /// page privileged/unprivileged attribution - PRIV2BB1: u1, - /// page privileged/unprivileged attribution - PRIV2BB2: u1, - /// page privileged/unprivileged attribution - PRIV2BB3: u1, - /// page privileged/unprivileged attribution - PRIV2BB4: u1, - /// page privileged/unprivileged attribution - PRIV2BB5: u1, - /// page privileged/unprivileged attribution - PRIV2BB6: u1, - /// page privileged/unprivileged attribution - PRIV2BB7: u1, - /// page privileged/unprivileged attribution - PRIV2BB8: u1, - /// page privileged/unprivileged attribution - PRIV2BB9: u1, - /// page privileged/unprivileged attribution - PRIV2BB10: u1, - /// page privileged/unprivileged attribution - PRIV2BB11: u1, - /// page privileged/unprivileged attribution - PRIV2BB12: u1, - /// page privileged/unprivileged attribution - PRIV2BB13: u1, - /// page privileged/unprivileged attribution - PRIV2BB14: u1, - /// page privileged/unprivileged attribution - PRIV2BB15: u1, - /// page privileged/unprivileged attribution - PRIV2BB16: u1, - /// page privileged/unprivileged attribution - PRIV2BB17: u1, - /// page privileged/unprivileged attribution - PRIV2BB18: u1, - /// page privileged/unprivileged attribution - PRIV2BB19: u1, - /// page privileged/unprivileged attribution - PRIV2BB20: u1, - /// page privileged/unprivileged attribution - PRIV2BB21: u1, - /// page privileged/unprivileged attribution - PRIV2BB22: u1, - /// page privileged/unprivileged attribution - PRIV2BB23: u1, - /// page privileged/unprivileged attribution - PRIV2BB24: u1, - /// page privileged/unprivileged attribution - PRIV2BB25: u1, - /// page privileged/unprivileged attribution - PRIV2BB26: u1, - /// page privileged/unprivileged attribution - PRIV2BB27: u1, - /// page privileged/unprivileged attribution - PRIV2BB28: u1, - /// page privileged/unprivileged attribution - PRIV2BB29: u1, - /// page privileged/unprivileged attribution - PRIV2BB30: u1, - /// page privileged/unprivileged attribution - PRIV2BB31: u1, - }), - /// FLASH privilege block based bank 2 register 3 - PRIV2BBR3: mmio.Mmio(packed struct(u32) { - /// page privileged/unprivileged attribution - PRIV2BB0: u1, - /// page privileged/unprivileged attribution - PRIV2BB1: u1, - /// page privileged/unprivileged attribution - PRIV2BB2: u1, - /// page privileged/unprivileged attribution - PRIV2BB3: u1, - /// page privileged/unprivileged attribution - PRIV2BB4: u1, - /// page privileged/unprivileged attribution - PRIV2BB5: u1, - /// page privileged/unprivileged attribution - PRIV2BB6: u1, - /// page privileged/unprivileged attribution - PRIV2BB7: u1, - /// page privileged/unprivileged attribution - PRIV2BB8: u1, - /// page privileged/unprivileged attribution - PRIV2BB9: u1, - /// page privileged/unprivileged attribution - PRIV2BB10: u1, - /// page privileged/unprivileged attribution - PRIV2BB11: u1, - /// page privileged/unprivileged attribution - PRIV2BB12: u1, - /// page privileged/unprivileged attribution - PRIV2BB13: u1, - /// page privileged/unprivileged attribution - PRIV2BB14: u1, - /// page privileged/unprivileged attribution - PRIV2BB15: u1, - /// page privileged/unprivileged attribution - PRIV2BB16: u1, - /// page privileged/unprivileged attribution - PRIV2BB17: u1, - /// page privileged/unprivileged attribution - PRIV2BB18: u1, - /// page privileged/unprivileged attribution - PRIV2BB19: u1, - /// page privileged/unprivileged attribution - PRIV2BB20: u1, - /// page privileged/unprivileged attribution - PRIV2BB21: u1, - /// page privileged/unprivileged attribution - PRIV2BB22: u1, - /// page privileged/unprivileged attribution - PRIV2BB23: u1, - /// page privileged/unprivileged attribution - PRIV2BB24: u1, - /// page privileged/unprivileged attribution - PRIV2BB25: u1, - /// page privileged/unprivileged attribution - PRIV2BB26: u1, - /// page privileged/unprivileged attribution - PRIV2BB27: u1, - /// page privileged/unprivileged attribution - PRIV2BB28: u1, - /// page privileged/unprivileged attribution - PRIV2BB29: u1, - /// page privileged/unprivileged attribution - PRIV2BB30: u1, - /// page privileged/unprivileged attribution - PRIV2BB31: u1, + reserved64: [20]u8, + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Converted data + DATA: u16, + padding: u16, }), - /// FLASH privilege block based bank 2 register 4 - PRIV2BBR4: mmio.Mmio(packed struct(u32) { - /// page privileged/unprivileged attribution - PRIV2BB0: u1, - /// page privileged/unprivileged attribution - PRIV2BB1: u1, - /// page privileged/unprivileged attribution - PRIV2BB2: u1, - /// page privileged/unprivileged attribution - PRIV2BB3: u1, - /// page privileged/unprivileged attribution - PRIV2BB4: u1, - /// page privileged/unprivileged attribution - PRIV2BB5: u1, - /// page privileged/unprivileged attribution - PRIV2BB6: u1, - /// page privileged/unprivileged attribution - PRIV2BB7: u1, - /// page privileged/unprivileged attribution - PRIV2BB8: u1, - /// page privileged/unprivileged attribution - PRIV2BB9: u1, - /// page privileged/unprivileged attribution - PRIV2BB10: u1, - /// page privileged/unprivileged attribution - PRIV2BB11: u1, - /// page privileged/unprivileged attribution - PRIV2BB12: u1, - /// page privileged/unprivileged attribution - PRIV2BB13: u1, - /// page privileged/unprivileged attribution - PRIV2BB14: u1, - /// page privileged/unprivileged attribution - PRIV2BB15: u1, - /// page privileged/unprivileged attribution - PRIV2BB16: u1, - /// page privileged/unprivileged attribution - PRIV2BB17: u1, - /// page privileged/unprivileged attribution - PRIV2BB18: u1, - /// page privileged/unprivileged attribution - PRIV2BB19: u1, - /// page privileged/unprivileged attribution - PRIV2BB20: u1, - /// page privileged/unprivileged attribution - PRIV2BB21: u1, - /// page privileged/unprivileged attribution - PRIV2BB22: u1, - /// page privileged/unprivileged attribution - PRIV2BB23: u1, - /// page privileged/unprivileged attribution - PRIV2BB24: u1, - /// page privileged/unprivileged attribution - PRIV2BB25: u1, - /// page privileged/unprivileged attribution - PRIV2BB26: u1, - /// page privileged/unprivileged attribution - PRIV2BB27: u1, - /// page privileged/unprivileged attribution - PRIV2BB28: u1, - /// page privileged/unprivileged attribution - PRIV2BB29: u1, - /// page privileged/unprivileged attribution - PRIV2BB30: u1, - /// page privileged/unprivileged attribution - PRIV2BB31: u1, + reserved776: [708]u8, + /// common configuration register + CCR: mmio.Mmio(packed struct(u32) { + reserved22: u22, + /// Temperature sensor and VREFINT enable + VREFEN: u1, + /// Temperature sensor enable + TSEN: u1, + /// VBAT enable + VBATEN: u1, + padding: u7, }), }; }; - pub const adc_h5 = struct { - pub const ADCALDIF = enum(u1) { - /// Calibration for single-ended mode - SingleEnded = 0x0, - /// Calibration for differential mode - Differential = 0x1, - }; - + pub const adc_v2 = struct { pub const ALIGN = enum(u1) { /// Right alignment Right = 0x0, @@ -309463,61 +309226,289 @@ pub const types = struct { Left = 0x1, }; - pub const AWD1SGL = enum(u1) { - /// Analog watchdog 1 enabled on all channels - All = 0x0, - /// Analog watchdog 1 enabled on single channel selected in AWD1CH - Single = 0x1, + pub const AWDSGL = enum(u1) { + /// Analog watchdog enabled on all channels + AllChannels = 0x0, + /// Analog watchdog enabled on a single channel + SingleChannel = 0x1, }; - pub const DMACFG = enum(u1) { - /// DMA One Shot mode selected - OneShot = 0x0, - /// DMA Circular mode selected - Circular = 0x1, + pub const DDS = enum(u1) { + /// No new DMA request is issued after the last transfer + Single = 0x0, + /// DMA requests are issued as long as data are converted and DMA=1 + Continuous = 0x1, + }; + + pub const EOCS = enum(u1) { + /// The EOC bit is set at the end of each sequence of regular conversions + EachSequence = 0x0, + /// The EOC bit is set at the end of each regular conversion + EachConversion = 0x1, }; pub const EXTEN = enum(u2) { - /// Hardware trigger detection disabled (conversions can be launched by software) + /// Trigger detection disabled Disabled = 0x0, - /// Hardware trigger detection on the rising edge + /// Trigger detection on the rising edge RisingEdge = 0x1, - /// Hardware trigger detection on the falling edge + /// Trigger detection on the falling edge FallingEdge = 0x2, - /// Hardware trigger detection on both the rising and falling edge + /// Trigger detection on both the rising and falling edges BothEdges = 0x3, }; - pub const JQM = enum(u1) { - /// JSQR Mode 0: Queue maintains the last written configuration into JSQR - Mode0 = 0x0, - /// JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence - Mode1 = 0x1, + pub const JEXTEN = enum(u2) { + /// Trigger detection disabled + Disabled = 0x0, + /// Trigger detection on the rising edge + RisingEdge = 0x1, + /// Trigger detection on the falling edge + FallingEdge = 0x2, + /// Trigger detection on both the rising and falling edges + BothEdges = 0x3, }; - pub const OFFSETPOS = enum(u1) { - /// Negative offset - Negative = 0x0, - /// Positive offset - Positive = 0x1, + pub const RES = enum(u2) { + /// 12-bit (15 ADCCLK cycles) + Bits12 = 0x0, + /// 10-bit (13 ADCCLK cycles) + Bits10 = 0x1, + /// 8-bit (11 ADCCLK cycles) + Bits8 = 0x2, + /// 6-bit (9 ADCCLK cycles) + Bits6 = 0x3, }; - pub const OVRMOD = enum(u1) { - /// Preserve DR register when an overrun is detected - Preserve = 0x0, - /// Overwrite DR register when an overrun is detected - Overwrite = 0x1, + pub const SAMPLE_TIME = enum(u3) { + /// 3 cycles + Cycles3 = 0x0, + /// 15 cycles + Cycles15 = 0x1, + /// 28 cycles + Cycles28 = 0x2, + /// 56 cycles + Cycles56 = 0x3, + /// 84 cycles + Cycles84 = 0x4, + /// 112 cycles + Cycles112 = 0x5, + /// 144 cycles + Cycles144 = 0x6, + /// 480 cycles + Cycles480 = 0x7, }; - pub const OVSR = enum(u3) { - x2 = 0x0, - x4 = 0x1, - x8 = 0x2, - x16 = 0x3, - x32 = 0x4, - x64 = 0x5, - x128 = 0x6, - x256 = 0x7, + pub const SMPR_SMPx_x = enum(u32) { + /// 3 cycles + Cycles3 = 0x0, + /// 15 cycles + Cycles15 = 0x1, + /// 28 cycles + Cycles28 = 0x2, + /// 56 cycles + Cycles56 = 0x3, + /// 84 cycles + Cycles84 = 0x4, + /// 112 cycles + Cycles112 = 0x5, + /// 144 cycles + Cycles144 = 0x6, + /// 480 cycles + Cycles480 = 0x7, + _, + }; + + /// Analog-to-digital converter + pub const ADC = extern struct { + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog event occurred + AWD: u1, + /// Regular channel end of conversion + EOC: u1, + /// Injected channel end of conversion + JEOC: u1, + /// Injected channel conversion has started + JSTRT: u1, + /// Regular channel conversion has started + STRT: u1, + /// Overrun occurred + OVR: u1, + padding: u26, + }), + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Analog watchdog channel select bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt enable + AWDIE: u1, + /// Interrupt enable for injected channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: packed union { + raw: u1, + value: AWDSGL, + }, + /// Automatic injected group conversion + JAUTO: u1, + /// Discontinuous mode on regular channels + DISCEN: u1, + /// Discontinuous mode on injected channels + JDISCEN: u1, + /// Discontinuous mode channel count + DISCNUM: u3, + reserved22: u6, + /// Analog watchdog enable on injected channels + JAWDEN: u1, + /// Analog watchdog enable on regular channels + AWDEN: u1, + /// Resolution + RES: packed union { + raw: u2, + value: RES, + }, + /// Overrun interrupt enable + OVRIE: u1, + padding: u5, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + reserved8: u6, + /// Direct memory access mode (for single ADC mode) + DMA: u1, + /// DMA disable selection (for single ADC mode) + DDS: packed union { + raw: u1, + value: DDS, + }, + /// End of conversion selection + EOCS: packed union { + raw: u1, + value: EOCS, + }, + /// Data alignment + ALIGN: packed union { + raw: u1, + value: ALIGN, + }, + reserved16: u4, + /// External event select for injected group + JEXTSEL: u4, + /// External trigger enable for injected channels + JEXTEN: packed union { + raw: u2, + value: JEXTEN, + }, + /// Start conversion of injected channels + JSWSTART: u1, + reserved24: u1, + /// External event select for regular group + EXTSEL: u4, + /// External trigger enable for regular channels + EXTEN: packed union { + raw: u2, + value: EXTEN, + }, + /// Start conversion of regular channels + SWSTART: u1, + padding: u1, + }), + /// sample time register 1 + SMPR1: mmio.Mmio(packed struct(u32) { + /// Channel 10 sampling time selection + SMP: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + padding: u29, + }), + /// sample time register 2 + SMPR2: mmio.Mmio(packed struct(u32) { + /// Channel 0 sampling time selection + SMP: packed union { + raw: u3, + value: SAMPLE_TIME, + }, + padding: u29, + }), + /// injected channel data offset register x + JOFR: [4]mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET: u12, + padding: u20, + }), + /// watchdog higher threshold register + HTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog higher threshold + HT: u12, + padding: u20, + }), + /// watchdog lower threshold register + LTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog lower threshold + LT: u12, + padding: u20, + }), + /// regular sequence register 1 + SQR1: mmio.Mmio(packed struct(u32) { + /// 13th conversion in regular sequence + SQ: u5, + reserved20: u15, + /// Regular channel sequence length + L: u4, + padding: u8, + }), + /// regular sequence register 2 + SQR2: mmio.Mmio(packed struct(u32) { + /// 7th conversion in regular sequence + SQ: u5, + padding: u27, + }), + /// regular sequence register 3 + SQR3: mmio.Mmio(packed struct(u32) { + /// 1st conversion in regular sequence + SQ: u5, + padding: u27, + }), + /// injected sequence register + JSQR: mmio.Mmio(packed struct(u32) { + /// 1st conversion in injected sequence + JSQ: u5, + reserved20: u15, + /// Injected sequence length + JL: u2, + padding: u10, + }), + /// injected data register x + JDR: [4]mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// regular data register + DR: mmio.Mmio(packed struct(u32) { + /// Regular data + DATA: u16, + padding: u16, + }), + }; + }; + + pub const adc_v3 = struct { + pub const DMACFG = enum(u1) { + /// DMA One Shot mode selected + OneShot = 0x0, + /// DMA Circular mode selected + Circular = 0x1, }; pub const RES = enum(u2) { @@ -309531,244 +309522,168 @@ pub const types = struct { Bits6 = 0x3, }; - pub const ROVSM = enum(u1) { - /// Oversampling is temporary stopped and continued after injection sequence - Continued = 0x0, - /// Oversampling is aborted and resumed from start after injection sequence - Resumed = 0x1, - }; - pub const SAMPLE_TIME = enum(u3) { - /// 2.5 ADC clock cycles + /// 2.5 ADC cycles Cycles2_5 = 0x0, - /// 6.5 ADC clock cycles + /// 6.5 ADC cycles Cycles6_5 = 0x1, - /// 12.5 ADC clock cycles + /// 12.5 ADC cycles Cycles12_5 = 0x2, - /// 24.5 ADC clock cycles + /// 24.5 ADC cycles Cycles24_5 = 0x3, - /// 47.5 ADC clock cycles + /// 47.5 ADC cycles Cycles47_5 = 0x4, - /// 92.5 ADC clock cycles + /// 92.5 ADC cycles Cycles92_5 = 0x5, - /// 247.5 ADC clock cycles + /// 247.5 ADC cycles Cycles247_5 = 0x6, - /// 640.5 ADC clock cycles + /// 640.5 ADC cycles Cycles640_5 = 0x7, }; - pub const SMPPLUS = enum(u1) { - /// The sampling time remains set to 2.5 ADC clock cycles remains - Cycles2_5 = 0x0, - /// 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers. - Cycles3_5 = 0x1, - }; - - pub const SWTRIG = enum(u1) { - /// Software trigger starts the conversion for sampling time control trigger mode - Conversion = 0x0, - /// Software trigger starts the sampling for sampling time control trigger mode - Sampling = 0x1, - }; - - pub const TROVS = enum(u1) { - /// All oversampled conversions for a channel are run following a trigger - Automatic = 0x0, - /// Each oversampled conversion for a channel needs a new trigger - Triggered = 0x1, - }; - - /// Analog to digital converter + /// Analog-to-Digital Converter pub const ADC = extern struct { /// interrupt and status register ISR: mmio.Mmio(packed struct(u32) { - /// ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it + /// ADRDY ADRDY: u1, - /// End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase + /// EOSMP EOSMP: u1, - /// End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register + /// EOC EOC: u1, - /// End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it + /// EOS EOS: u1, - /// overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it + /// OVR OVR: u1, - /// Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register + /// JEOC JEOC: u1, - /// Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it + /// JEOS JEOS: u1, - /// Analog watchdog 1-3 flags. Set by hardware when the converted voltage crosses the values programmed in the corresponding fields LT and HT fields of the relevant TR register. It is cleared by software. + /// AWD1 AWD: u1, reserved10: u2, - /// Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information + /// JQOVF JQOVF: u1, padding: u21, }), /// interrupt enable register IER: mmio.Mmio(packed struct(u32) { - /// ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + /// ADRDYIE ADRDYIE: u1, - /// End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// EOSMPIE EOSMPIE: u1, - /// End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// EOCIE EOCIE: u1, - /// End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// EOSIE EOSIE: u1, - /// Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// OVRIE OVRIE: u1, - /// End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + /// JEOCIE JEOCIE: u1, - /// End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + /// JEOSIE JEOSIE: u1, - /// Analog watchdog 1-3 interrupt enable. This bit is set and cleared by software to enable/disable the analog watchdog 1-3 interrupts. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - AWDIE: u1, - reserved10: u2, - /// Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + /// AWD1IE + AWD1IE: u1, + /// AWD2IE + AWD2IE: u1, + /// AWD3IE + AWD3IE: u1, + /// JQOVFIE JQOVFIE: u1, padding: u21, }), /// control register CR: mmio.Mmio(packed struct(u32) { - /// ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator). + /// ADEN ADEN: u1, - /// ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + /// ADDIS ADDIS: u1, - /// ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion immediately starts (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (EXTSEL = 0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC) In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared). + /// ADSTART ADSTART: u1, - /// ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion immediately starts (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared). + /// JADSTART JADSTART: u1, - /// ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). + /// ADSTP ADSTP: u1, - /// ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC) In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). + /// JADSTP JADSTP: u1, reserved28: u22, - /// voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) + /// ADVREGEN ADVREGEN: u1, - /// Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + /// DEEPPWD DEEPPWD: u1, - /// Differential mode for calibration This bit is set and cleared by software to configure the Single-ended or Differential inputs mode for the calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). - ADCALDIF: packed union { - raw: u1, - value: ADCALDIF, - }, - /// ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for Single-ended or Differential inputs mode. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0. The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing). + /// ADCALDIF + ADCALDIF: u1, + /// ADCAL ADCAL: u1, }), /// configuration register CFGR: mmio.Mmio(packed struct(u32) { - /// Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to conversions using the DMA. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + /// DMAEN DMAEN: u1, - /// Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + /// Direct memory access configuration DMACFG: packed union { raw: u1, value: DMACFG, }, reserved3: u1, - /// Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + /// RES RES: packed union { raw: u2, value: RES, }, - /// External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - EXTSEL: u1, - reserved10: u4, - /// External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - EXTEN: packed union { - raw: u2, - value: EXTEN, - }, - /// Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - OVRMOD: packed union { - raw: u1, - value: OVRMOD, - }, - /// Single / Continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// ALIGN + ALIGN: u1, + /// EXTSEL + EXTSEL: u4, + /// EXTEN + EXTEN: u2, + /// OVRMOD + OVRMOD: u1, + /// CONT CONT: u1, - /// Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + /// AUTDLY AUTDLY: u1, - /// Data alignment This bit is set and cleared by software to select right or left alignment. Refer to register, data alignment and offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN). Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - ALIGN: packed union { - raw: u1, - value: ALIGN, - }, - /// Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// AUTOFF + AUTOFF: u1, + /// DISCEN DISCEN: u1, - /// Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in Discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// DISCNUM DISCNUM: u3, - /// Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable Discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. + /// JDISCEN JDISCEN: u1, - /// JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to for more information. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). - JQM: packed union { - raw: u1, - value: JQM, - }, - /// Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - AWD1SGL: packed union { - raw: u1, - value: AWD1SGL, - }, - /// Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// JQM + JQM: u1, + /// AWD1SGL + AWD1SGL: u1, + /// AWD1EN AWD1EN: u1, - /// Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + /// JAWD1EN JAWD1EN: u1, - /// Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). + /// JAUTO JAUTO: u1, - /// Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... others: reserved, must not be used Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value. The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - AWD1CH: u5, - /// Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared. - JQDIS: u1, + /// AWDCH1CH + AWDCH1CH: u5, + padding: u1, }), - /// configuration register 2 + /// configuration register CFGR2: mmio.Mmio(packed struct(u32) { - /// Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + /// DMAEN ROVSE: u1, - /// Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + /// DMACFG JOVSE: u1, - /// Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). - OVSR: packed union { - raw: u3, - value: OVSR, - }, - /// Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). + /// RES + OVSR: u3, + /// ALIGN OVSS: u4, - /// Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). - TROVS: packed union { - raw: u1, - value: TROVS, - }, - /// Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). - ROVSM: packed union { - raw: u1, - value: ROVSM, - }, - reserved25: u14, - /// Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). - SWTRIG: packed union { - raw: u1, - value: SWTRIG, - }, - /// Bulb sampling mode This bit is set and cleared by software to enable the bulb sampling mode. SAMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). - BULB: u1, - /// Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN bit should be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN bit is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). - SMPTRIG: u1, - padding: u4, + /// EXTSEL + TOVS: u1, + /// EXTEN + ROVSM: u1, + padding: u21, }), /// sample time register 1 - SMPR1: mmio.Mmio(packed struct(u32) { - /// Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - reserved31: u28, - /// Addition of one clock cycle to the sampling time. To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 - SMPPLUS: packed union { - raw: u1, - value: SMPPLUS, - }, - }), - /// sample time register 2 - SMPR2: mmio.Mmio(packed struct(u32) { - /// Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + SMPR: [2]mmio.Mmio(packed struct(u32) { + /// Channel 0 sampling time selection SMP: packed union { raw: u3, value: SAMPLE_TIME, @@ -309777,2080 +309692,2216 @@ pub const types = struct { }), reserved32: [4]u8, /// watchdog threshold register 1 - TR1: mmio.Mmio(packed struct(u32) { - /// Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - LT1: u12, - /// Analog watchdog filtering parameter This bit is set and cleared by software. ... Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). - AWDFILT: u3, - reserved16: u1, - /// Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - HT1: u12, + TR: [3]mmio.Mmio(packed struct(u32) { + /// LT1 + LT: u12, + reserved16: u4, + /// HT1 + HT: u12, padding: u4, }), - /// watchdog threshold register 2 - TR2: mmio.Mmio(packed struct(u32) { - /// Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - LT2: u8, - reserved16: u8, - /// Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - HT2: u8, - padding: u8, - }), - /// watchdog threshold register 3 - TR3: mmio.Mmio(packed struct(u32) { - /// Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - LT3: u8, - reserved16: u8, - /// Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - HT3: u8, - padding: u8, - }), reserved48: [4]u8, /// regular sequence register 1 SQR1: mmio.Mmio(packed struct(u32) { - /// Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// Regular channel sequence length L: u4, reserved6: u2, - /// 1st-4th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// SQ1 SQ: u5, padding: u21, }), /// regular sequence register 2 SQR2: mmio.Mmio(packed struct(u32) { - /// 5th-9th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 5th-9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// SQ5 SQ: u5, padding: u27, }), /// regular sequence register 3 SQR3: mmio.Mmio(packed struct(u32) { - /// 10th-14th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 10th-14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// SQ10 SQ: u5, padding: u27, }), /// regular sequence register 4 SQR4: mmio.Mmio(packed struct(u32) { - /// 15th-16th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 15th-16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + /// SQ15 SQ: u5, padding: u27, }), - /// regular data register + /// regular Data Register DR: mmio.Mmio(packed struct(u32) { - /// Regular data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in - RDATA: u16, + /// regularDATA + regularDATA: u16, padding: u16, }), reserved76: [8]u8, /// injected sequence register JSQR: mmio.Mmio(packed struct(u32) { - /// Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + /// JL JL: u2, - /// External Trigger Selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). - JEXTSEL: u5, - /// External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). If JQM = 1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Queue of context for injected conversions). - JEXTEN: packed union { - raw: u2, - value: EXTEN, - }, - /// 1st-4th conversions in the injected sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + /// JEXTSEL + JEXTSEL: u4, + /// JEXTEN + JEXTEN: u2, + /// JSQ1 JSQ: u5, - padding: u18, + padding: u19, }), reserved96: [16]u8, - /// offset 1-4 register + /// offset register 1 OFR: [4]mmio.Mmio(packed struct(u32) { - /// Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4. OFFSET: u12, - reserved24: u12, - /// Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - OFFSETPOS: packed union { - raw: u1, - value: OFFSETPOS, - }, - /// Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - SATEN: u1, - /// Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the data offset y. If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers. + reserved26: u14, OFFSET_CH: u5, - /// Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). OFFSET_EN: u1, }), reserved128: [16]u8, - /// injected channel 1-4 register + /// injected data registers JDR: [4]mmio.Mmio(packed struct(u32) { - /// Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in + /// JDATA1 JDATA: u16, padding: u16, }), reserved160: [16]u8, /// Analog Watchdog 2 Configuration Register AWD2CR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: analog input channel i is monitored by AWD2 When AWD2CH[19:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the analog watchdog. - AWD2CH: u20, - padding: u12, + reserved1: u1, + /// AWD2CH + AWD2CH: u18, + padding: u13, }), /// Analog Watchdog 3 Configuration Register AWD3CR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: analog input channel i is monitored by AWD3 When AWD3CH[19:0] = 000..0, the analog Watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the analog watchdog. - AWD3CH: u20, - padding: u12, + reserved1: u1, + /// AWD3CH + AWD3CH: u18, + padding: u13, }), reserved176: [8]u8, - /// Differential mode Selection Register + /// Differential Mode Selection Register 2 DIFSEL: mmio.Mmio(packed struct(u32) { - /// Differential mode for channels 19 to 0. These bits are set and cleared by software. They allow to select if a channel is configured as Single-ended or Differential mode. DIFSEL[i] = 0: analog input channel is configured in Single-ended mode DIFSEL[i] = 1: analog input channel i is configured in Differential mode Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port or to an internal channel must be kept their reset value (Single-ended input mode). The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). - DIFSEL: u20, - padding: u12, + reserved1: u1, + /// Differential mode for channels 15 to 1 + DIFSEL_1_15: u15, + /// Differential mode for channels 18 to 16 + DIFSEL_16_18: u3, + padding: u13, }), /// Calibration Factors CALFACT: mmio.Mmio(packed struct(u32) { - /// Calibration Factors In Single-ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new single-ended calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). + /// CALFACT_S CALFACT_S: u7, reserved16: u9, - /// Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new differential calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). + /// CALFACT_D CALFACT_D: u7, padding: u9, }), - reserved200: [16]u8, - /// option register - OR: mmio.Mmio(packed struct(u32) { - /// Option bit 0 - OP0: u1, - /// Option bit 1. Note - not documented for H562/H563/H573 - OP1: u1, - padding: u30, - }), }; }; - pub const usbram_16x2_1024 = struct { - /// USB Endpoint memory - pub const USBRAM = extern struct { - /// USB Endpoint memory - MEM: u32, + pub const adc_v4 = struct { + pub const ADCALDIF = enum(u1) { + /// Calibration for single-ended mode + SingleEnded = 0x0, + /// Calibration for differential mode + Differential = 0x1, }; - }; - pub const fsmc_v1x3 = struct { - pub const ACCMOD = enum(u2) { - /// Access mode A - A = 0x0, - /// Access mode B - B = 0x1, - /// Access mode C - C = 0x2, - /// Access mode D - D = 0x3, + pub const ADSTP = enum(u1) { + /// Stop conversion of channel + Stop = 0x1, + _, }; - pub const CPSIZE = enum(u3) { - /// No burst split when crossing page boundary - NoBurstSplit = 0x0, - /// 128 bytes CRAM page size - Bytes128 = 0x1, - /// 256 bytes CRAM page size - Bytes256 = 0x2, - /// 512 bytes CRAM page size - Bytes512 = 0x3, - /// 1024 bytes CRAM page size - Bytes1024 = 0x4, - _, + pub const AWD1SGL = enum(u1) { + /// Analog watchdog 1 enabled on all channels + All = 0x0, + /// Analog watchdog 1 enabled on single channel selected in AWD1CH + Single = 0x1, }; - pub const ECCPS = enum(u3) { - /// ECC page size 256 bytes - Bytes256 = 0x0, - /// ECC page size 512 bytes - Bytes512 = 0x1, - /// ECC page size 1024 bytes - Bytes1024 = 0x2, - /// ECC page size 2048 bytes - Bytes2048 = 0x3, - /// ECC page size 4096 bytes - Bytes4096 = 0x4, - /// ECC page size 8192 bytes - Bytes8192 = 0x5, - _, + pub const BOOST = enum(u2) { + /// Boost mode used when clock ≤ 6.25 MHz + LT6_25 = 0x0, + /// Boost mode used when 6.25 MHz < clock ≤ 12.5 MHz + LT12_5 = 0x1, + /// Boost mode used when 12.5 MHz < clock ≤ 25.0 MHz + LT25 = 0x2, + /// Boost mode used when 25.0 MHz < clock ≤ 50.0 MHz + LT50 = 0x3, }; - pub const MTYP = enum(u2) { - /// SRAM memory type - SRAM = 0x0, - /// PSRAM (CRAM) memory type - PSRAM = 0x1, - /// NOR Flash/OneNAND Flash - Flash = 0x2, - _, + pub const DIFSEL = enum(u1) { + /// Input channel is configured in single-ended mode + SingleEnded = 0x0, + /// Input channel is configured in differential mode + Differential = 0x1, }; - pub const MWID = enum(u2) { - /// Memory data bus width 8 bits - Bits8 = 0x0, - /// Memory data bus width 16 bits - Bits16 = 0x1, - /// Memory data bus width 32 bits - Bits32 = 0x2, - _, + pub const DMNGT = enum(u2) { + /// Store output data in DR only + DR = 0x0, + /// DMA One Shot Mode selected + DMA_OneShot = 0x1, + /// DFSDM mode selected + DFSDM = 0x2, + /// DMA Circular Mode selected + DMA_Circular = 0x3, }; - pub const PTYP = enum(u1) { - /// NAND Flash - NANDFlash = 0x1, - _, + pub const EXTEN = enum(u2) { + /// Trigger detection disabled + Disabled = 0x0, + /// Trigger detection on the rising edge + RisingEdge = 0x1, + /// Trigger detection on the falling edge + FallingEdge = 0x2, + /// Trigger detection on both the rising and falling edges + BothEdges = 0x3, }; - pub const PWID = enum(u2) { - /// External memory device width 8 bits - Bits8 = 0x0, - /// External memory device width 16 bits - Bits16 = 0x1, + pub const JEXTEN = enum(u2) { + /// Trigger detection disabled + Disabled = 0x0, + /// Trigger detection on the rising edge + RisingEdge = 0x1, + /// Trigger detection on the falling edge + FallingEdge = 0x2, + /// Trigger detection on both the rising and falling edges + BothEdges = 0x3, + }; + + pub const JQM = enum(u1) { + /// JSQR Mode 0: Queue maintains the last written configuration into JSQR + Mode0 = 0x0, + /// JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence + Mode1 = 0x1, + }; + + pub const OVRMOD = enum(u1) { + /// Preserve DR register when an overrun is detected + Preserve = 0x0, + /// Overwrite DR register when an overrun is detected + Overwrite = 0x1, + }; + + pub const PCSEL = enum(u1) { + /// Input channel x is not pre-selected + NotPreselected = 0x0, + /// Pre-select input channel x + Preselected = 0x1, + }; + + pub const RES = enum(u3) { + /// 16-bit resolution + Bits16 = 0x0, + /// 14-bit resolution in legacy mode (not optimized power consumption) + Bits14 = 0x1, + /// 12-bit resolution in legacy mode (not optimized power consumption) + Bits12 = 0x2, + /// 10-bit resolution + Bits10 = 0x3, + /// 14-bit resolution + Bits14V = 0x5, + /// 12-bit resolution + Bits12V = 0x6, + /// 8-bit resolution + Bits8 = 0x7, _, }; - pub const WAITCFG = enum(u1) { - /// NWAIT signal is active one data cycle before wait state - BeforeWaitState = 0x0, - /// NWAIT signal is active during wait state - DuringWaitState = 0x1, + pub const ROVSM = enum(u1) { + /// Oversampling is temporary stopped and continued after injection sequence + Continued = 0x0, + /// Oversampling is aborted and resumed from start after injection sequence + Resumed = 0x1, }; - pub const WAITPOL = enum(u1) { - /// NWAIT active low - ActiveLow = 0x0, - /// NWAIT active high - ActiveHigh = 0x1, + pub const SAMPLE_TIME = enum(u3) { + /// 1.5 clock cycles + Cycles1_5 = 0x0, + /// 2.5 clock cycles + Cycles2_5 = 0x1, + /// 8.5 clock cycles + Cycles8_5 = 0x2, + /// 16.5 clock cycles + Cycles16_5 = 0x3, + /// 32.5 clock cycles + Cycles32_5 = 0x4, + /// 64.5 clock cycles + Cycles64_5 = 0x5, + /// 387.5 clock cycles + Cycles387_5 = 0x6, + /// 810.5 clock cycles + Cycles810_5 = 0x7, }; - /// Flexible static memory controller - pub const FSMC = extern struct { - /// SRAM/NOR-Flash chip-select control register 1-4 - BCR: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { - raw: u2, - value: MTYP, + pub const TROVS = enum(u1) { + /// All oversampled conversions for a channel are run following a trigger + Automatic = 0x0, + /// Each oversampled conversion for a channel needs a new trigger + Triggered = 0x1, + }; + + /// Analog to Digital Converter + pub const ADC = extern struct { + /// interrupt and status register + ISR: mmio.Mmio(packed struct(u32) { + /// ready flag + ADRDY: u1, + /// group regular end of sampling flag + EOSMP: u1, + /// group regular end of unitary conversion flag + EOC: u1, + /// group regular end of sequence conversions flag + EOS: u1, + /// group regular overrun flag + OVR: u1, + /// group injected end of unitary conversion flag + JEOC: u1, + /// group injected end of sequence conversions flag + JEOS: u1, + /// analog watchdog 1 flag + AWD1: u1, + /// analog watchdog 2 flag + AWD2: u1, + /// analog watchdog 3 flag + AWD3: u1, + /// group injected contexts queue overflow flag + JQOVF: u1, + reserved12: u1, + /// ADC LDO output voltage ready (not always available) + LDORDY: u1, + padding: u19, + }), + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// ready interrupt + ADRDYIE: u1, + /// group regular end of sampling interrupt + EOSMPIE: u1, + /// group regular end of unitary conversion interrupt + EOCIE: u1, + /// group regular end of sequence conversions interrupt + EOSIE: u1, + /// group regular overrun interrupt + OVRIE: u1, + /// group injected end of unitary conversion interrupt + JEOCIE: u1, + /// group injected end of sequence conversions interrupt + JEOSIE: u1, + /// analog watchdog 1 interrupt + AWD1IE: u1, + /// analog watchdog 2 interrupt + AWD2IE: u1, + /// analog watchdog 3 interrupt + AWD3IE: u1, + /// group injected contexts queue overflow interrupt + JQOVFIE: u1, + padding: u21, + }), + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// enable + ADEN: u1, + /// disable + ADDIS: u1, + /// group regular conversion start + ADSTART: u1, + /// group injected conversion start + JADSTART: u1, + /// group regular conversion stop + ADSTP: packed union { + raw: u1, + value: ADSTP, }, - /// Memory data bus width - MWID: packed union { + /// group injected conversion stop + JADSTP: packed union { + raw: u1, + value: ADSTP, + }, + reserved8: u2, + /// Boost mode control + BOOST: packed union { raw: u2, - value: MWID, + value: BOOST, }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { + reserved16: u6, + /// Linearity calibration + ADCALLIN: u1, + reserved22: u5, + /// Linearity calibration ready Word 1 + LINCALRDYW1: u1, + /// Linearity calibration ready Word 2 + LINCALRDYW2: u1, + /// Linearity calibration ready Word 3 + LINCALRDYW3: u1, + /// Linearity calibration ready Word 4 + LINCALRDYW4: u1, + /// Linearity calibration ready Word 5 + LINCALRDYW5: u1, + /// Linearity calibration ready Word 6 + LINCALRDYW6: u1, + /// voltage regulator enable + ADVREGEN: u1, + /// deep power down enable + DEEPPWD: u1, + /// differential mode for calibration + ADCALDIF: packed union { raw: u1, - value: WAITPOL, + value: ADCALDIF, }, - /// WRAPMOD - WRAPMOD: u1, - /// Wait timing configuration - WAITCFG: packed union { - raw: u1, - value: WAITCFG, + /// calibration + ADCAL: u1, + }), + /// configuration register 1 + CFGR: mmio.Mmio(packed struct(u32) { + /// DMA transfer enable + DMNGT: packed union { + raw: u2, + value: DMNGT, }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - /// CRAM page size - CPSIZE: packed union { + /// data resolution + RES: packed union { raw: u3, - value: CPSIZE, + value: RES, }, - /// Write burst enable - CBURSTRW: u1, - padding: u12, - }), - /// SRAM/NOR-Flash chip-select timing register 1-4 - BTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - /// Clock divide ratio (for FMC_CLK signal) - CLKDIV: u4, - /// Data latency for synchronous memory - DATLAT: u4, - /// Access mode - ACCMOD: packed union { + /// group regular external trigger source + EXTSEL: u5, + /// group regular external trigger polarity + EXTEN: packed union { raw: u2, - value: ACCMOD, + value: EXTEN, }, - padding: u2, + /// group regular overrun configuration + OVRMOD: packed union { + raw: u1, + value: OVRMOD, + }, + /// Continuous conversion + CONT: u1, + /// low power auto wait + AUTDLY: u1, + reserved16: u1, + /// group regular sequencer discontinuous mode + DISCEN: u1, + /// group regular sequencer discontinuous number of ranks + DISCNUM: u3, + /// group injected sequencer discontinuous mode + JDISCEN: u1, + /// group injected contexts queue mode + JQM: packed union { + raw: u1, + value: JQM, + }, + /// analog watchdog 1 monitoring a single channel or all channels + AWD1SGL: packed union { + raw: u1, + value: AWD1SGL, + }, + /// analog watchdog 1 enable on scope group regular + AWD1EN: u1, + /// analog watchdog 1 enable on scope group injected + JAWD1EN: u1, + /// group injected automatic trigger mode + JAUTO: u1, + /// analog watchdog 1 monitored channel selection + AWD1CH: u5, + /// group injected contexts queue disable + JQDIS: u1, }), - reserved96: [88]u8, - /// PC Card/NAND Flash control register 2-4 - PCR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Wait feature enable bit - PWAITEN: u1, - /// NAND Flash memory bank enable bit - PBKEN: u1, - /// Memory type - PTYP: packed union { + /// configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// oversampler enable on scope group regular + ROVSE: u1, + /// oversampler enable on scope group injected + JOVSE: u1, + reserved5: u3, + /// oversampling shift + OVSS: u4, + /// oversampling discontinuous mode (triggered mode) for group regular + TROVS: packed union { raw: u1, - value: PTYP, + value: TROVS, }, - /// Data bus width - PWID: packed union { - raw: u2, - value: PWID, + /// Regular Oversampling mode + ROVSM: packed union { + raw: u1, + value: ROVSM, }, - /// ECC computation logic enable bit - ECCEN: u1, - reserved9: u2, - /// CLE to RE delay - TCLR: u4, - /// ALE to RE delay - TAR: u4, - /// ECC page size - ECCPS: packed union { + /// Right-shift data after Offset 1 correction + RSHIFT1: u1, + /// Right-shift data after Offset 2 correction + RSHIFT2: u1, + /// Right-shift data after Offset 3 correction + RSHIFT3: u1, + /// Right-shift data after Offset 4 correction + RSHIFT4: u1, + reserved16: u1, + /// Oversampling ratio + OSVR: u10, + reserved28: u2, + /// Left shift factor + LSHIFT: u4, + }), + /// sampling time register 1-2 + SMPR: [2]mmio.Mmio(packed struct(u32) { + /// channel n * 10 + x sampling time + SMP: packed union { raw: u3, - value: ECCPS, + value: SAMPLE_TIME, }, - padding: u12, + padding: u29, }), - /// FIFO status and interrupt register 2-4 - SR: mmio.Mmio(packed struct(u32) { - /// Interrupt rising edge status - IRS: u1, - /// Interrupt high-level status - ILS: u1, - /// Interrupt falling edge status - IFS: u1, - /// Interrupt rising edge detection enable bit - IREN: u1, - /// Interrupt high-level detection enable bit - ILEN: u1, - /// Interrupt falling edge detection enable bit - IFEN: u1, - /// FIFO empty status - FEMPT: u1, - padding: u25, + /// pre channel selection register + PCSEL: mmio.Mmio(packed struct(u32) { + /// Channel x (VINP[i]) pre selection + PCSEL: packed union { + raw: u1, + value: PCSEL, + }, + padding: u31, }), - /// Common memory space timing register 2-4 - PMEM: mmio.Mmio(packed struct(u32) { - /// Common memory x setup time - MEMSET: u8, - /// Common memory wait time - MEMWAIT: u8, - /// Common memory hold time - MEMHOLD: u8, - /// Common memory x data bus Hi-Z time - MEMHIZ: u8, + /// analog watchdog 1 threshold register + LTR1: mmio.Mmio(packed struct(u32) { + /// analog watchdog 1 threshold low + LTR1: u26, + padding: u6, }), - /// Attribute memory space timing register 2-4 - PATT: mmio.Mmio(packed struct(u32) { - /// Attribute memory setup time - ATTSET: u8, - /// Attribute memory wait time - ATTWAIT: u8, - /// Attribute memory hold time - ATTHOLD: u8, - /// Attribute memory data bus Hi-Z time - ATTHIZ: u8, + /// analog watchdog 2 threshold register + HTR1: mmio.Mmio(packed struct(u32) { + /// analog watchdog 2 threshold low + HTR1: u26, + padding: u6, }), - reserved116: [4]u8, - /// ECC result register 2-3 - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC computation result value - ECC: u32, + reserved48: [8]u8, + /// group regular sequencer ranks register 1 + SQR1: mmio.Mmio(packed struct(u32) { + /// L3 + L: u4, + reserved6: u2, + /// group regular sequencer rank 1-4 + SQ: u5, + padding: u21, }), - reserved176: [56]u8, - /// I/O space timing register 4 - PIO4: mmio.Mmio(packed struct(u32) { - /// IOSETx - IOSETx: u8, - /// IOWAITx - IOWAITx: u8, - /// IOHOLDx - IOHOLDx: u8, - /// IOHIZx - IOHIZx: u8, + /// group regular sequencer ranks register 2 + SQR2: mmio.Mmio(packed struct(u32) { + /// group regular sequencer rank 5-9 + SQ: u5, + padding: u27, }), - reserved260: [80]u8, - /// SRAM/NOR-Flash write timing registers 1-4 - BWTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - reserved28: u8, - /// Access mode - ACCMOD: packed union { + /// group regular sequencer ranks register 3 + SQR3: mmio.Mmio(packed struct(u32) { + /// group regular sequencer rank 10-14 + SQ: u5, + padding: u27, + }), + /// group regular sequencer ranks register 4 + SQR4: mmio.Mmio(packed struct(u32) { + /// group regular sequencer rank 15-16 + SQ: u5, + padding: u27, + }), + /// group regular conversion data register + DR: mmio.Mmio(packed struct(u32) { + /// group regular conversion data + RDATA: u16, + padding: u16, + }), + reserved76: [8]u8, + /// group injected sequencer register + JSQR: mmio.Mmio(packed struct(u32) { + /// group injected sequencer scan length + JL: u2, + /// group injected external trigger source + JEXTSEL: u5, + /// group injected external trigger polarity + JEXTEN: packed union { raw: u2, - value: ACCMOD, + value: JEXTEN, }, - padding: u2, + /// group injected sequencer rank 1-4 + JSQ1: u5, + padding: u18, }), - }; - }; - - pub const dbgmcu_wl = struct { - /// Microcontroller Debug Unit - pub const DBGMCU = extern struct { - /// Identity Code Register - IDCODER: mmio.Mmio(packed struct(u32) { - /// Device ID - DEV_ID: u12, - reserved16: u4, - /// Revision - REV_ID: u16, + reserved96: [16]u8, + /// offset number 1-4 register + OFR: [4]mmio.Mmio(packed struct(u32) { + /// offset number x offset level + OFFSET1: u26, + /// offset number x channel selection + OFFSET1_CH: u5, + /// Signed saturation enable + SSATE: u1, }), - /// Configuration Register - CR: mmio.Mmio(packed struct(u32) { - /// Allow debug in SLEEP mode - DBG_SLEEP: u1, - /// Allow debug in STOP mode - DBG_STOP: u1, - /// Allow debug in STANDBY mode - DBG_STANDBY: u1, - padding: u29, + reserved128: [16]u8, + /// group injected sequencer rank 1-4 register + JDR: [4]mmio.Mmio(packed struct(u32) { + /// group injected sequencer rank 1 conversion data + JDATA: u32, }), - reserved60: [52]u8, - /// CPU1 APB1 Peripheral Freeze Register 1 - APB1FZR1: mmio.Mmio(packed struct(u32) { - /// TIM2 stop in CPU1 debug - TIM2: u1, - reserved10: u9, - /// RTC stop in CPU1 debug - RTC: u1, - /// WWDG stop in CPU1 debug - WWDG: u1, - /// IWDG stop in CPU1 debug - IWDG: u1, - reserved21: u8, - /// I2C1 SMBUS timeout stop in CPU1 debug - I2C1: u1, - /// I2C2 SMBUS timeout stop in CPU1 debug - I2C2: u1, - /// I2C3 SMBUS timeout stop in CPU1 debug - I2C3: u1, - reserved31: u7, - /// LPTIM1 stop in CPU1 debug - LPTIM1: u1, + reserved160: [16]u8, + /// analog watchdog 2 configuration register + AWD2CR: mmio.Mmio(packed struct(u32) { + /// analog watchdog 2 monitored channel selection + AWD2CH: u1, + padding: u31, }), - /// CPU2 APB1 Peripheral Freeze Register 1 [dual core device - C2APB1FZR1: mmio.Mmio(packed struct(u32) { - /// TIM2 - TIM2: u1, - reserved10: u9, - /// RTC - RTC: u1, - reserved12: u1, - /// IWDG - IWDG: u1, - reserved21: u8, - /// I2C1 - I2C1: u1, - /// I2C2 - I2C2: u1, - /// I2C3 - I2C3: u1, - reserved31: u7, - /// LPTIM1 - LPTIM1: u1, + /// analog watchdog 3 configuration register + AWD3CR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// analog watchdog 3 monitored channel selection + AWD3CH: u1, + padding: u30, }), - /// CPU1 APB1 Peripheral Freeze Register 2 - APB1FZR2: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// LPTIM2 - LPTIM2: u1, - /// LPTIM3 - LPTIM3: u1, - padding: u25, + reserved176: [8]u8, + /// watchdog lower threshold register 2 + LTR2: mmio.Mmio(packed struct(u32) { + /// Analog watchdog 2 lower threshold + LTR2: u26, + padding: u6, }), - /// CPU2 APB1 Peripheral Freeze Register 2 [dual core device - C2APB1FZR2: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// LPTIM2 - LPTIM2: u1, - /// LPTIM3 - LPTIM3: u1, - padding: u25, + /// watchdog higher threshold register 2 + HTR2: mmio.Mmio(packed struct(u32) { + /// Analog watchdog 2 higher threshold + HTR2: u26, + padding: u6, }), - /// CPU1 APB2 Peripheral Freeze Register - APB2FZR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 - TIM1: u1, - reserved17: u5, - /// TIM16 - TIM16: u1, - /// TIM17 - TIM17: u1, - padding: u13, + /// watchdog lower threshold register 3 + LTR3: mmio.Mmio(packed struct(u32) { + /// Analog watchdog 3 lower threshold + LTR3: u26, + padding: u6, }), - /// CPU2 APB2 Peripheral Freeze Register [dual core device - C2APB2FZR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 - TIM1: u1, - reserved17: u5, - /// TIM16 - TIM16: u1, - /// TIM17 - TIM17: u1, - padding: u13, + /// watchdog higher threshold register 3 + HTR3: mmio.Mmio(packed struct(u32) { + /// Analog watchdog 3 higher threshold + HTR3: u26, + padding: u6, + }), + /// channel differential or single-ended mode selection register + DIFSEL: mmio.Mmio(packed struct(u32) { + /// channel differential or single-ended mode for channel + DIFSEL: packed union { + raw: u1, + value: DIFSEL, + }, + padding: u31, + }), + /// calibration factors register + CALFACT: mmio.Mmio(packed struct(u32) { + /// calibration factor in single-ended mode + CALFACT_S: u11, + reserved16: u5, + /// calibration factor in differential mode + CALFACT_D: u11, + padding: u5, + }), + /// Calibration Factor register 2 + CALFACT2: mmio.Mmio(packed struct(u32) { + /// Linearity Calibration Factor + LINCALFACT: u30, + padding: u2, }), }; }; - pub const timer_v1 = struct { - pub const BKINP = enum(u1) { - /// input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) - NotInverted = 0x0, - /// input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) - Inverted = 0x1, - }; - - pub const BKP = enum(u1) { - /// Break input tim_brk is active low - ActiveLow = 0x0, - /// Break input tim_brk is active high - ActiveHigh = 0x1, - }; - - pub const CCDS = enum(u1) { - /// CCx DMA request sent when CCx event occurs - OnCompare = 0x0, - /// CCx DMA request sent when update event occurs - OnUpdate = 0x1, + pub const adccommon_f3 = struct { + /// ADC clock mode + pub const CKMODE = enum(u2) { + /// Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous mode + Asynchronous = 0x0, + /// Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck. + SyncDiv1 = 0x1, + /// Use AHB clock rcc_hclk3 divided by 2. + SyncDiv2 = 0x2, + /// Use AHB clock rcc_hclk3 divided by 4. + SyncDiv4 = 0x3, }; - pub const CCMR_Input_CCS = enum(u2) { - /// CCx channel is configured as input, normal mapping: ICx mapped to TIx - TI4 = 0x1, - /// CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) - TI3 = 0x2, - /// CCx channel is configured as input, ICx is mapped on TRC - TRC = 0x3, - _, + pub const DMACFG = enum(u1) { + /// DMA One Shot mode selected + OneShot = 0x0, + /// DMA Circular mode selected + Circulator = 0x1, }; - pub const CCMR_Output_CCS = enum(u2) { - /// CCx channel is configured as output - Output = 0x0, + /// Dual ADC mode selection + pub const DUAL = enum(u5) { + /// Independent mode + Independent = 0x0, + /// Dual, combined regular simultaneous + injected simultaneous mode + DualRJ = 0x1, + /// Dual, combined regular simultaneous + alternate trigger mode + DualRA = 0x2, + /// Dual, combined injected simultaneous + fast interleaved mode + DualIJ = 0x3, + /// Dual, injected simultaneous mode only + DualJ = 0x5, + /// Dual, regular simultaneous mode only + DualR = 0x6, + /// dual, interleaved mode only + DualI = 0x7, + /// Dual, alternate trigger mode only + DualA = 0x9, _, }; - pub const CKD = enum(u2) { - /// t_DTS = t_CK_INT - Div1 = 0x0, - /// t_DTS = 2 × t_CK_INT - Div2 = 0x1, - /// t_DTS = 4 × t_CK_INT - Div4 = 0x2, + /// Direct memory access mode for multi ADC mode + pub const MDMA = enum(u2) { + /// MDMA mode disabled + Disabled = 0x0, + /// MDMA mode enabled for 12 and 10-bit resolution + Bits12_10 = 0x2, + /// MDMA mode enabled for 8 and 6-bit resolution + Bits8_6 = 0x3, _, }; - pub const CMS = enum(u2) { - /// The counter counts up or down depending on the direction bit - EdgeAligned = 0x0, - /// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. - CenterAligned1 = 0x1, - /// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. - CenterAligned2 = 0x2, - /// The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. - CenterAligned3 = 0x3, - }; - - pub const DIR = enum(u1) { - /// Counter used as upcounter - Up = 0x0, - /// Counter used as downcounter - Down = 0x1, + /// ADC common registers + pub const ADC_COMMON = extern struct { + /// ADC Common status register + CSR: mmio.Mmio(packed struct(u32) { + /// Master ADC ready + ADRDY_MST: u1, + /// End of sampling phase flag of the master ADC + EOSMP_MST: u1, + /// End of regular conversion of the master ADC + EOC_MST: u1, + /// End of regular sequence flag of the master ADC + EOS_MST: u1, + /// Overrun flag of the master ADC + OVR_MST: u1, + /// End of injected conversion of the master ADC + JEOC_MST: u1, + /// End of injected sequence flag of the master ADC + JEOS: u1, + /// Analog watchdog flag of the master ADC + AWD_MST: u1, + reserved10: u2, + /// Injected context queue overflow flag of the master ADC + JQOVF_MST: u1, + reserved16: u5, + /// Slave ADC ready + ADRDY_SLV: u1, + /// End of sampling phase flag of the slave ADC + EOSMP_SLV: u1, + /// End of regular conversion of the slave ADC + EOC_SLV: u1, + /// End of regular sequence flag of the slave ADC + EOS_SLV: u1, + /// Overrun flag of the slave ADC + OVR_SLV: u1, + /// End of injected conversion of the slave ADC + JEOC_SLV: u1, + /// End of injected sequence flag of the slave ADC + JEOS_SLV: u1, + /// Analog watchdog flag of the slave ADC + AWD_SLV: u1, + reserved26: u2, + /// Injected context queue overflow flag of the slave ADC + JQOVF_SLV: u1, + padding: u5, + }), + reserved8: [4]u8, + /// ADC common control register + CCR: mmio.Mmio(packed struct(u32) { + /// Dual ADC mode selection + DUAL: packed union { + raw: u5, + value: DUAL, + }, + reserved8: u3, + /// Delay between 2 sampling phases + DELAY: u4, + reserved13: u1, + /// Direct memory access configuration + DMACFG: packed union { + raw: u1, + value: DMACFG, + }, + /// Direct memory access mode for multi ADC mode + MDMA: packed union { + raw: u2, + value: MDMA, + }, + /// ADC clock mode + CKMODE: packed union { + raw: u2, + value: CKMODE, + }, + reserved22: u4, + /// VREFINT enable + VREFEN: u1, + /// Temperature sensor enable + TSEN: u1, + /// VBAT enable + VBATEN: u1, + padding: u7, + }), + /// ADC common regular data register for dual and triple modes + CDR: mmio.Mmio(packed struct(u32) { + /// Regular data of the master ADC + RDATA_MST: u16, + /// Regular data of the master ADC + RDATA_SLV: u16, + }), }; + }; - pub const ETP = enum(u1) { - /// ETR is noninverted, active at high level or rising edge - NotInverted = 0x0, - /// ETR is inverted, active at low level or falling edge - Inverted = 0x1, + pub const adccommon_h5 = struct { + pub const CKMODE = enum(u2) { + /// Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock + Asynchronous = 0x0, + /// Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck + SyncDiv1 = 0x1, + /// Use AHB clock rcc_hclk3 divided by 2 + SyncDiv2 = 0x2, + /// Use AHB clock rcc_hclk3 divided by 4 + SyncDiv4 = 0x3, }; - pub const ETPS = enum(u2) { - /// Prescaler OFF - Div1 = 0x0, - /// ETRP frequency divided by 2 - Div2 = 0x1, - /// ETRP frequency divided by 4 - Div4 = 0x2, - /// ETRP frequency divided by 8 - Div8 = 0x3, + pub const DMACFG = enum(u1) { + /// DMA One Shot mode selected + OneShot = 0x0, + /// DMA Circular mode selected + Circular = 0x1, }; - pub const FilterValue = enum(u4) { - /// No filter, sampling is done at fDTS - NoFilter = 0x0, - /// fSAMPLING=fCK_INT, N=2 - FCK_INT_N2 = 0x1, - /// fSAMPLING=fCK_INT, N=4 - FCK_INT_N4 = 0x2, - /// fSAMPLING=fCK_INT, N=8 - FCK_INT_N8 = 0x3, - /// fSAMPLING=fDTS/2, N=6 - FDTS_Div2_N6 = 0x4, - /// fSAMPLING=fDTS/2, N=8 - FDTS_Div2_N8 = 0x5, - /// fSAMPLING=fDTS/4, N=6 - FDTS_Div4_N6 = 0x6, - /// fSAMPLING=fDTS/4, N=8 - FDTS_Div4_N8 = 0x7, - /// fSAMPLING=fDTS/8, N=6 - FDTS_Div8_N6 = 0x8, - /// fSAMPLING=fDTS/8, N=8 - FDTS_Div8_N8 = 0x9, - /// fSAMPLING=fDTS/16, N=5 - FDTS_Div16_N5 = 0xa, - /// fSAMPLING=fDTS/16, N=6 - FDTS_Div16_N6 = 0xb, - /// fSAMPLING=fDTS/16, N=8 - FDTS_Div16_N8 = 0xc, - /// fSAMPLING=fDTS/32, N=5 - FDTS_Div32_N5 = 0xd, - /// fSAMPLING=fDTS/32, N=6 - FDTS_Div32_N6 = 0xe, - /// fSAMPLING=fDTS/32, N=8 - FDTS_Div32_N8 = 0xf, + pub const DUAL = enum(u5) { + /// Independent mode + Independent = 0x0, + /// Dual, combined regular simultaneous + injected simultaneous mode + DualRJ = 0x1, + /// Dual, combined regular simultaneous + alternate trigger mode + DualRA = 0x2, + /// Dual, combined interleaved mode + injected simultaneous mode + DualIJ = 0x3, + /// Dual, injected simultaneous mode only + DualJ = 0x5, + /// Dual, regular simultaneous mode only + DualR = 0x6, + /// Dual, interleaved mode only + DualI = 0x7, + /// Dual, alternate trigger mode only + DualA = 0x9, + _, }; - pub const GC5C = enum(u1) { - /// No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3) - NoEffect = 0x0, - /// TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF - LogicalAND = 0x1, + pub const IDLEVALUE = enum(u4) { + /// Dummy channel selection is 0x13 + H13 = 0x0, + /// Dummy channel selection is 0x1F + H1F = 0x1, + _, }; - pub const LOCK = enum(u2) { - /// No bit is write protected - Disabled = 0x0, - /// DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written - Level1 = 0x1, - /// LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. - Level2 = 0x2, - /// LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. - Level3 = 0x3, + pub const MDMA = enum(u2) { + /// Without data packing, CDR/CDR2 not used + NoPack = 0x0, + /// CDR formatted for 32-bit down to 10-bit resolution + Format32to10 = 0x2, + /// CDR formatted for 8-bit resolution + Format8 = 0x3, + _, }; - pub const MMS = enum(u3) { - /// The UG bit from the TIMx_EGR register is used as trigger output - Reset = 0x0, - /// The counter enable signal, CNT_EN, is used as trigger output - Enable = 0x1, - /// The update event is selected as trigger output - Update = 0x2, - /// The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - ComparePulse = 0x3, - /// OC1REF signal is used as trigger output - CompareOC1 = 0x4, - /// OC2REF signal is used as trigger output - CompareOC2 = 0x5, - /// OC3REF signal is used as trigger output - CompareOC3 = 0x6, - /// OC4REF signal is used as trigger output - CompareOC4 = 0x7, + pub const PRESC = enum(u4) { + /// adc_ker_ck_input not divided + Div1 = 0x0, + /// adc_ker_ck_input divided by 2 + Div2 = 0x1, + /// adc_ker_ck_input divided by 4 + Div4 = 0x2, + /// adc_ker_ck_input divided by 6 + Div6 = 0x3, + /// adc_ker_ck_input divided by 8 + Div8 = 0x4, + /// adc_ker_ck_input divided by 10 + Div10 = 0x5, + /// adc_ker_ck_input divided by 12 + Div12 = 0x6, + /// adc_ker_ck_input divided by 16 + Div16 = 0x7, + /// adc_ker_ck_input divided by 32 + Div32 = 0x8, + /// adc_ker_ck_input divided by 64 + Div64 = 0x9, + /// adc_ker_ck_input divided by 128 + Div128 = 0xa, + /// adc_ker_ck_input divided by 256 + Div256 = 0xb, + _, }; - pub const MMS2 = enum(u4) { - /// The UG bit from the TIMx_EGR register is used as TRGO2 - Reset = 0x0, - /// The counter enable signal, CNT_EN, is used as TRGO2 - Enable = 0x1, - /// The update event is selected as TRGO2 - Update = 0x2, - /// TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - ComparePulse = 0x3, - /// OC1REF signal is used as TRGO2 - CompareOC1 = 0x4, - /// OC2REF signal is used as TRGO2 - CompareOC2 = 0x5, - /// OC3REF signal is used as TRGO2 - CompareOC3 = 0x6, - /// OC4REF signal is used as TRGO2 - CompareOC4 = 0x7, - /// OC5REF signal is used as TRGO2 - CompareOC5 = 0x8, - /// OC6REF signal is used as TRGO2 - CompareOC6 = 0x9, - /// OC4REF rising or falling edges generate pulses on TRGO2 - ComparePulse_OC4 = 0xa, - /// OC6REF rising or falling edges generate pulses on TRGO2 - ComparePulse_OC6 = 0xb, - /// OC4REF or OC6REF rising edges generate pulses on TRGO2 - ComparePulse_OC4_Or_OC6_Rising = 0xc, - /// OC4REF rising or OC6REF falling edges generate pulses on TRGO2 - ComparePulse_OC4_Rising_Or_OC6_Falling = 0xd, - /// OC5REF or OC6REF rising edges generate pulses on TRGO2 - ComparePulse_OC5_Or_OC6_Rising = 0xe, - /// OC5REF rising or OC6REF falling edges generate pulses on TRGO2 - ComparePulse_OC5_Rising_Or_OC6_Falling = 0xf, - }; - - pub const MSM = enum(u1) { - /// No action - NoSync = 0x0, - /// The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - Sync = 0x1, - }; - - pub const OCM = enum(u3) { - /// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs - Frozen = 0x0, - /// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register - ActiveOnMatch = 0x1, - /// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register - InactiveOnMatch = 0x2, - /// OCyREF toggles when TIMx_CNT=TIMx_CCRy - Toggle = 0x3, - /// OCyREF is forced low - ForceInactive = 0x4, - /// OCyREF is forced high - ForceActive = 0x5, - /// In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active - PwmMode1 = 0x6, - /// Inversely to PwmMode1 - PwmMode2 = 0x7, - }; - - pub const OSSI = enum(u1) { - /// When inactive, OC/OCN outputs are disabled - Disabled = 0x0, - /// When inactive, OC/OCN outputs are forced to idle level - IdleLevel = 0x1, + /// ADC common registers + pub const ADC_COMMON = extern struct { + /// common status register + CSR: mmio.Mmio(packed struct(u32) { + /// Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register. + ADRDY_MST: u1, + /// End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register. + EOSMP_MST: u1, + /// End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register. + EOC_MST: u1, + /// End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register. + EOS_MST: u1, + /// Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register. + OVR_MST: u1, + /// End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register. + JEOC_MST: u1, + /// End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. + JEOS_MST: u1, + /// Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. + AWD_MST: u1, + reserved10: u2, + /// Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register. + JQOVF_MST: u1, + reserved16: u5, + /// Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register. + ADRDY_SLV: u1, + /// End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADC_ISR register. + EOSMP_SLV: u1, + /// End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register. + EOC_SLV: u1, + /// End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register. + EOS_SLV: u1, + /// Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register. + OVR_SLV: u1, + /// End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register. + JEOC_SLV: u1, + /// End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. + JEOS_SLV: u1, + /// Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. + AWD_SLV: u1, + reserved26: u2, + /// Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register. + JQOVF_SLV: u1, + padding: u5, + }), + reserved8: [4]u8, + /// common control register + CCR: mmio.Mmio(packed struct(u32) { + /// Dual ADC mode selection These bits are written by software to select the operating mode. 0 value means Independent Mode. Values 00001 to 01001 means Dual mode, master and slave ADCs are working together. All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + DUAL: packed union { + raw: u5, + value: DUAL, + }, + reserved8: u3, + /// Delay between 2 sampling phases These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + DELAY: u4, + reserved13: u1, + /// DMA configuration (for dual ADC mode) This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + DMACFG: packed union { + raw: u1, + value: DMACFG, + }, + /// Direct memory access mode for dual ADC mode This bitfield is set and cleared by software. Refer to the DMA controller section for more details. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + MDMA: packed union { + raw: u2, + value: MDMA, + }, + /// ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + CKMODE: packed union { + raw: u2, + value: CKMODE, + }, + /// ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00. + PRESC: packed union { + raw: u4, + value: PRESC, + }, + /// VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel + VREFEN: u1, + /// VSENSE enable This bit is set and cleared by software to control VSENSE + TSEN: u1, + /// VBAT enable This bit is set and cleared by software to control + VBATEN: u1, + padding: u7, + }), + /// common regular data register for dual mode + CDR: mmio.Mmio(packed struct(u32) { + /// Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)) In MDMA = 0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0]. + RDATA_MST: u16, + /// Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)). + RDATA_SLV: u16, + }), + reserved240: [224]u8, + /// hardware configuration register + HWCFGR0: mmio.Mmio(packed struct(u32) { + /// Number of ADCs implemented + ADCNUM: u4, + /// Number of pipeline stages + MULPIPE: u4, + /// Number of option bits 0002: 2 option bits implemented in the ADC option register (ADC_OR) at address offset 0xC8. + OPBITS: u4, + /// Idle value for non-selected channels + IDLEVALUE: packed union { + raw: u4, + value: IDLEVALUE, + }, + padding: u16, + }), + /// version register + VERR: mmio.Mmio(packed struct(u32) { + /// Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2. + MINREV: u4, + /// Major revision These bits returns the ADC IP major revision + MAJREV: u4, + padding: u24, + }), + /// identification register + IPDR: u32, + /// size identification register + SIDR: u32, }; + }; - pub const OSSR = enum(u1) { - /// When inactive, OC/OCN outputs are disabled - Disabled = 0x0, - /// When inactive, OC/OCN outputs are enabled with their inactive level - IdleLevel = 0x1, + pub const adccommon_h50 = struct { + pub const CKMODE = enum(u2) { + /// Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock + Asynchronous = 0x0, + /// Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck + SyncDiv1 = 0x1, + /// Use AHB clock rcc_hclk3 divided by 2 + SyncDiv2 = 0x2, + /// Use AHB clock rcc_hclk3 divided by 4 + SyncDiv4 = 0x3, }; - pub const SMS = enum(u4) { - /// Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock. - Disabled = 0x0, - /// Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - Encoder_Mode_1 = 0x1, - /// Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - Encoder_Mode_2 = 0x2, - /// Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - Encoder_Mode_3 = 0x3, - /// Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - Reset_Mode = 0x4, - /// Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - Gated_Mode = 0x5, - /// Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - Trigger_Mode = 0x6, - /// External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - Ext_Clock_Mode = 0x7, - /// Rising edge of the selected trigger input (tim_trgi) reinitializes the counter, generates an update of the registers and starts the counter. - Combined_Reset_Trigger = 0x8, + pub const IDLEVALUE = enum(u4) { + /// Dummy channel selection is 0x13 + H13 = 0x0, + /// Dummy channel selection is 0x1F + H1F = 0x1, _, }; - pub const TI1S = enum(u1) { - /// The TIMx_CH1 pin is connected to TI1 input - Normal = 0x0, - /// The TIMx_CH1, CH2, CH3 pins are connected to TI1 input - XOR = 0x1, - }; - - pub const TS = enum(u5) { - /// Internal Trigger 0 - ITR0 = 0x0, - /// Internal Trigger 1 - ITR1 = 0x1, - /// Internal Trigger 2 - ITR2 = 0x2, - /// Internal Trigger 3 - ITR3 = 0x3, - /// TI1 Edge Detector - TI1F_ED = 0x4, - /// Filtered Timer Input 1 - TI1FP1 = 0x5, - /// Filtered Timer Input 2 - TI2FP2 = 0x6, - /// External Trigger input - ETRF = 0x7, + pub const PRESC = enum(u4) { + /// adc_ker_ck_input not divided + Div1 = 0x0, + /// adc_ker_ck_input divided by 2 + Div2 = 0x1, + /// adc_ker_ck_input divided by 4 + Div4 = 0x2, + /// adc_ker_ck_input divided by 6 + Div6 = 0x3, + /// adc_ker_ck_input divided by 8 + Div8 = 0x4, + /// adc_ker_ck_input divided by 10 + Div10 = 0x5, + /// adc_ker_ck_input divided by 12 + Div12 = 0x6, + /// adc_ker_ck_input divided by 16 + Div16 = 0x7, + /// adc_ker_ck_input divided by 32 + Div32 = 0x8, + /// adc_ker_ck_input divided by 64 + Div64 = 0x9, + /// adc_ker_ck_input divided by 128 + Div128 = 0xa, + /// adc_ker_ck_input divided by 256 + Div256 = 0xb, _, }; - pub const URS = enum(u1) { - /// Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - AnyEvent = 0x0, - /// Only counter overflow/underflow generates an update interrupt or DMA request - CounterOnly = 0x1, - }; - - /// 1-channel timers - pub const TIM_1CH = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Clock division - CKD: packed union { - raw: u2, - value: CKD, - }, - padding: u22, - }), - reserved12: [8]u8, - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/Compare x (x=1) interrupt enable - CCIE: u1, - padding: u30, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1) interrupt flag - CCIF: u1, - reserved9: u7, - /// Capture/Compare x (x=1) overcapture flag - CCOF: u1, - padding: u22, - }), - /// event generation register - EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1) generation - CCG: u1, - padding: u30, - }), - /// capture/compare mode register 1 (input mode) - CCMR_Input: [1]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: packed union { + /// ADC common registers + pub const ADC_COMMON = extern struct { + reserved8: [8]u8, + /// common control register + CCR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + CKMODE: packed union { raw: u2, - value: CCMR_Input_CCS, + value: CKMODE, }, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: packed union { + /// ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00. + PRESC: packed union { raw: u4, - value: FilterValue, + value: PRESC, }, - padding: u24, - }), - reserved32: [4]u8, - /// capture/compare enable register - CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1) output enable - CCE: u1, - /// Capture/Compare x (x=1) output Polarity - CCP: u1, - reserved3: u1, - /// Capture/Compare x (x=1) output Polarity - CCNP: u1, - padding: u28, + /// VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel + VREFEN: u1, + /// VSENSE enable This bit is set and cleared by software to control VSENSE + TSEN: u1, + /// VBAT enable This bit is set and cleared by software to control + VBATEN: u1, + padding: u7, }), - reserved52: [16]u8, - /// capture/compare register x (x=1) - CCR: [1]mmio.Mmio(packed struct(u32) { - /// capture/compare x (x=1-4,6) value - CCR: u16, + reserved240: [228]u8, + /// hardware configuration register + HWCFGR0: mmio.Mmio(packed struct(u32) { + /// Number of ADCs implemented + ADCNUM: u4, + /// Number of pipeline stages + MULPIPE: u4, + /// Number of option bits 0002: 2 option bits implemented in the ADC option register (ADC_OR) at address offset 0xC8. + OPBITS: u4, + /// Idle value for non-selected channels + IDLEVALUE: packed union { + raw: u4, + value: IDLEVALUE, + }, padding: u16, }), - reserved80: [24]u8, - /// Option register 1 Note: Check Reference Manual to parse this register content - OR: u32, - reserved104: [20]u8, - /// input selection register - TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1) input - TISEL: u4, - padding: u28, + /// version register + VERR: mmio.Mmio(packed struct(u32) { + /// Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2. + MINREV: u4, + /// Major revision These bits returns the ADC IP major revision + MAJREV: u4, + padding: u24, }), + /// identification register + IPDR: u32, + /// size identification register + SIDR: u32, }; + }; - /// 1-channel with one complementary output timers - pub const TIM_1CH_CMP = extern struct { - reserved4: [4]u8, - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Capture/compare preloaded control - CCPC: u1, - reserved2: u1, - /// Capture/compare control update selection - CCUS: u1, - /// Capture/compare DMA selection - CCDS: packed union { - raw: u1, - value: CCDS, - }, - reserved8: u4, - /// Output Idle state x (x=1) - OIS: u1, - /// Output Idle state x (x=1) - OISN: u1, - padding: u22, - }), - reserved12: [4]u8, - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// COM interrupt enable - COMIE: u1, - reserved7: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare x (x=1) DMA request enable - CCDE: u1, - padding: u22, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// COM interrupt flag - COMIF: u1, - reserved7: u1, - /// Break x (x=1) interrupt flag - BIF: u1, - padding: u24, - }), - /// event generation register - EGR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// Capture/Compare control update generation - COMG: u1, - reserved7: u1, - /// Break x (x=1) generation - BG: u1, - padding: u24, - }), - reserved32: [8]u8, - /// capture/compare enable register - CCER: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Capture/Compare x (x=1) complementary output enable - CCNE: u1, - padding: u29, - }), - reserved48: [12]u8, - /// repetition counter register - RCR: mmio.Mmio(packed struct(u32) { - /// Repetition counter value - REP: u8, - padding: u24, + pub const adccommon_v2 = struct { + pub const ADCPRE = enum(u2) { + /// PCLK2 divided by 2 + Div2 = 0x0, + /// PCLK2 divided by 4 + Div4 = 0x1, + /// PCLK2 divided by 6 + Div6 = 0x2, + /// PCLK2 divided by 8 + Div8 = 0x3, + }; + + pub const DDS = enum(u1) { + /// No new DMA request is issued after the last transfer + Single = 0x0, + /// DMA requests are issued as long as data are converted and DMA=01, 10 or 11 + Continuous = 0x1, + }; + + pub const DMA = enum(u2) { + /// DMA mode disabled + Disabled = 0x0, + /// DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3) + Mode1 = 0x1, + /// DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) + Mode2 = 0x2, + /// DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) + Mode3 = 0x3, + }; + + pub const MULTI = enum(u5) { + /// All the ADCs independent: independent mode + Independent = 0x0, + /// Dual ADC1 and ADC2, combined regular and injected simultaneous mode + DualRJ = 0x1, + /// Dual ADC1 and ADC2, combined regular and alternate trigger mode + DualRA = 0x2, + /// Dual ADC1 and ADC2, injected simultaneous mode only + DualJ = 0x5, + /// Dual ADC1 and ADC2, regular simultaneous mode only + DualR = 0x6, + /// Dual ADC1 and ADC2, interleaved mode only + DualI = 0x7, + /// Dual ADC1 and ADC2, alternate trigger mode only + DualA = 0x9, + /// Triple ADC, regular and injected simultaneous mode + TripleRJ = 0x11, + /// Triple ADC, regular and alternate trigger mode + TripleRA = 0x12, + /// Triple ADC, injected simultaneous mode only + TripleJ = 0x15, + /// Triple ADC, regular simultaneous mode only + TripleR = 0x16, + /// Triple ADC, interleaved mode only + TripleI = 0x17, + /// Triple ADC, alternate trigger mode only + TripleA = 0x18, + _, + }; + + /// ADC common registers + pub const ADC_COMMON = extern struct { + /// ADC Common status register + CSR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog event occurred + AWD: u1, + /// End of conversion of ADC + EOC: u1, + /// Injected channel end of conversion of ADC + JEOC: u1, + /// Injected channel conversion started + JSTRT: u1, + /// regular channel conversion started + STRT: u1, + /// Overrun occurred + OVR: u1, + padding: u26, }), - reserved68: [16]u8, - /// break and dead-time register - BDTR: mmio.Mmio(packed struct(u32) { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: packed union { - raw: u2, - value: LOCK, - }, - /// Off-state selection for Idle mode - OSSI: packed union { - raw: u1, - value: OSSI, + /// ADC common control register + CCR: mmio.Mmio(packed struct(u32) { + /// Multi ADC mode selection + MULTI: packed union { + raw: u5, + value: MULTI, }, - /// Off-state selection for Run mode - OSSR: packed union { + reserved8: u3, + /// Delay between 2 sampling phases + DELAY: u4, + reserved13: u1, + /// DMA disable selection for multi-ADC mode + DDS: packed union { raw: u1, - value: OSSR, + value: DDS, }, - /// Break x (x=1) enable - BKE: u1, - /// Break x (x=1) polarity - BKP: packed union { - raw: u1, - value: BKP, + /// Direct memory access mode for multi ADC mode + DMA: packed union { + raw: u2, + value: DMA, }, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - /// Break x (x=1) filter - BKF: packed union { - raw: u4, - value: FilterValue, + /// ADC prescaler + ADCPRE: packed union { + raw: u2, + value: ADCPRE, }, - padding: u12, - }), - /// DMA control register - DCR: mmio.Mmio(packed struct(u32) { - /// DMA base address - DBA: u5, - reserved8: u3, - /// DMA burst length - DBL: u5, - padding: u19, + reserved22: u4, + /// VBAT enable + VBATE: u1, + /// Temperature sensor and VREFINT enable + TSVREFE: u1, + padding: u8, }), - /// DMA address for full transfer - DMAR: mmio.Mmio(packed struct(u32) { - /// DMA register for burst accesses - DMAB: u16, + /// ADC common regular data register for dual and triple modes + CDR: mmio.Mmio(packed struct(u32) { + /// 1st data item of a pair of regular conversions + DATA: u16, padding: u16, }), - reserved96: [16]u8, - /// alternate function register 1 - AF1: mmio.Mmio(packed struct(u32) { - /// TIMx_BKIN input enable - BKINE: u1, - /// TIM_BRK_CMPx (x=1-2) enable - BKCMPE: u1, - reserved8: u6, - /// BRK DFSDM1_BREAKx enable (x=0 if TIM15, x=1 if TIM16, x=2 if TIM17) - BKDF1BKE: u1, - /// TIMx_BKIN input polarity - BKINP: packed union { - raw: u1, - value: BKINP, - }, - /// TIM_BRK_CMPx (x=1-2) input polarity - BKCMPP: packed union { - raw: u1, - value: BKINP, - }, - padding: u21, - }), }; + }; - /// 2-channel timers - pub const TIM_2CH = extern struct { - reserved4: [4]u8, - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Master mode selection - MMS: packed union { - raw: u3, - value: MMS, - }, - /// TI1 selection - TI1S: packed union { + pub const adccommon_v3 = struct { + pub const DMACFG = enum(u1) { + /// DMA One Shot mode selected + OneShot = 0x0, + /// DMA Circular mode selected + Circular = 0x1, + }; + + /// Analog-to-Digital Converter + pub const ADC_COMMON = extern struct { + /// ADC Common status register + CSR: mmio.Mmio(packed struct(u32) { + /// ADDRDY_MST + ADDRDY_MST: u1, + /// EOSMP_MST + EOSMP_MST: u1, + /// EOC_MST + EOC_MST: u1, + /// EOS_MST + EOS_MST: u1, + /// OVR_MST + OVR_MST: u1, + /// JEOC_MST + JEOC_MST: u1, + /// JEOS_MST + JEOS_MST: u1, + /// Analog watchdog flag of the master ADC + AWD_MST: u1, + reserved10: u2, + /// JQOVF_MST + JQOVF_MST: u1, + reserved16: u5, + /// ADRDY_SLV + ADRDY_SLV: u1, + /// EOSMP_SLV + EOSMP_SLV: u1, + /// End of regular conversion of the slave ADC + EOC_SLV: u1, + /// End of regular sequence flag of the slave ADC + EOS_SLV: u1, + /// Overrun flag of the slave ADC + OVR_SLV: u1, + /// End of injected conversion flag of the slave ADC + JEOC_SLV: u1, + /// End of injected sequence flag of the slave ADC + JEOS_SLV: u1, + /// Analog watchdog 1 flag of the slave ADC + AWD_SLV: u1, + reserved26: u2, + /// Injected Context Queue Overflow flag of the slave ADC + JQOVF_SLV: u1, + padding: u5, + }), + reserved8: [4]u8, + /// ADC common control register + CCR: mmio.Mmio(packed struct(u32) { + /// Multi ADC mode selection + MULT: u5, + reserved8: u3, + /// Delay between 2 sampling phases + DELAY: u4, + reserved13: u1, + /// Direct memory access configuration + DMACFG: packed union { raw: u1, - value: TI1S, + value: DMACFG, }, - padding: u24, - }), - /// slave mode control register - SMCR: u32, - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/Compare x (x=1-2) interrupt enable - CCIE: u1, - reserved6: u4, - /// Trigger interrupt enable - TIE: u1, - padding: u25, + /// Direct memory access mode for multi ADC mode + MDMA: u2, + /// ADC clock mode + CKMODE: u2, + reserved22: u4, + /// VREFINT enable + VREFEN: u1, + /// CH18 selection (Vbat) + CH18SEL: u1, + /// CH17 selection (temperature) + CH17SEL: u1, + padding: u7, }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1-2) interrupt flag - CCIF: u1, - reserved6: u4, - /// Trigger interrupt flag - TIF: u1, - reserved9: u2, - /// Capture/Compare x (x=1-2) overcapture flag - CCOF: u1, - padding: u22, + /// ADC common regular data register for dual and triple modes + CDR: mmio.Mmio(packed struct(u32) { + /// Regular data of the master ADC + RDATA_MST: u16, + /// Regular data of the slave ADC + RDATA_SLV: u16, }), - /// event generation register - EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1-2) generation - CCG: u1, - reserved6: u4, - /// Trigger generation - TG: u1, - padding: u25, + }; + }; + + pub const adccommon_v4 = struct { + pub const CKMODE = enum(u2) { + /// Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock + Asynchronous = 0x0, + /// Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck + SyncDiv1 = 0x1, + /// Use AHB clock rcc_hclk3 divided by 2 + SyncDiv2 = 0x2, + /// Use AHB clock rcc_hclk3 divided by 4 + SyncDiv4 = 0x3, + }; + + pub const DAMDF = enum(u2) { + /// Without data packing, CDR/CDR2 not used + NoPack = 0x0, + /// CDR formatted for 32-bit down to 10-bit resolution + Format32to10 = 0x2, + /// CDR formatted for 8-bit resolution + Format8 = 0x3, + _, + }; + + pub const DUAL = enum(u5) { + /// Independent mode + Independent = 0x0, + /// Dual, combined regular simultaneous + injected simultaneous mode + DualRJ = 0x1, + /// Dual, combined regular simultaneous + alternate trigger mode + DualRA = 0x2, + /// Dual, combined interleaved mode + injected simultaneous mode + DualIJ = 0x3, + /// Dual, injected simultaneous mode only + DualJ = 0x5, + /// Dual, regular simultaneous mode only + DualR = 0x6, + /// Dual, interleaved mode only + DualI = 0x7, + /// Dual, alternate trigger mode only + DualA = 0x9, + _, + }; + + pub const PRESC = enum(u4) { + /// adc_ker_ck_input not divided + Div1 = 0x0, + /// adc_ker_ck_input divided by 2 + Div2 = 0x1, + /// adc_ker_ck_input divided by 4 + Div4 = 0x2, + /// adc_ker_ck_input divided by 6 + Div6 = 0x3, + /// adc_ker_ck_input divided by 8 + Div8 = 0x4, + /// adc_ker_ck_input divided by 10 + Div10 = 0x5, + /// adc_ker_ck_input divided by 12 + Div12 = 0x6, + /// adc_ker_ck_input divided by 16 + Div16 = 0x7, + /// adc_ker_ck_input divided by 32 + Div32 = 0x8, + /// adc_ker_ck_input divided by 64 + Div64 = 0x9, + /// adc_ker_ck_input divided by 128 + Div128 = 0xa, + /// adc_ker_ck_input divided by 256 + Div256 = 0xb, + _, + }; + + /// Analog-to-Digital Converter + pub const ADC_COMMON = extern struct { + /// ADC Common status register + CSR: mmio.Mmio(packed struct(u32) { + /// Master ADC ready + ADRDY_MST: u1, + /// End of Sampling phase flag of the master ADC + EOSMP_MST: u1, + /// End of regular conversion of the master ADC + EOC_MST: u1, + /// End of regular sequence flag of the master ADC + EOS_MST: u1, + /// Overrun flag of the master ADC + OVR_MST: u1, + /// End of injected conversion flag of the master ADC + JEOC_MST: u1, + /// End of injected sequence flag of the master ADC + JEOS_MST: u1, + /// Analog watchdog flag of the master ADC + AWD_MST: u1, + reserved10: u2, + /// Injected Context Queue Overflow flag of the master ADC + JQOVF_MST: u1, + reserved16: u5, + /// Slave ADC ready + ADRDY_SLV: u1, + /// End of Sampling phase flag of the slave ADC + EOSMP_SLV: u1, + /// End of regular conversion of the slave ADC + EOC_SLV: u1, + /// End of regular sequence flag of the slave ADC + EOS_SLV: u1, + /// Overrun flag of the slave ADC + OVR_SLV: u1, + /// End of injected conversion flag of the slave ADC + JEOC_SLV: u1, + /// End of injected sequence flag of the slave ADC + JEOS_SLV: u1, + /// Analog watchdog flag of the slave ADC + AWD_SLV: u1, + reserved26: u2, + /// Injected Context Queue Overflow flag of the slave ADC + JQOVF_SLV: u1, + padding: u5, }), - /// capture/compare mode register 1 (input mode) - CCMR_Input: [1]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: packed union { + reserved8: [4]u8, + /// ADC common control register + CCR: mmio.Mmio(packed struct(u32) { + /// Dual ADC mode selection + DUAL: packed union { + raw: u5, + value: DUAL, + }, + reserved8: u3, + /// Delay between 2 sampling phases + DELAY: u4, + reserved14: u2, + /// Dual ADC Mode Data Format + DAMDF: packed union { raw: u2, - value: CCMR_Input_CCS, + value: DAMDF, }, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: packed union { + /// ADC clock mode + CKMODE: packed union { + raw: u2, + value: CKMODE, + }, + /// ADC prescaler + PRESC: packed union { raw: u4, - value: FilterValue, + value: PRESC, }, - padding: u24, - }), - reserved32: [4]u8, - /// capture/compare enable register - CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-2) output enable - CCE: u1, - /// Capture/Compare x (x=1-2) output Polarity - CCP: u1, - reserved3: u1, - /// Capture/Compare x (x=1-2) output Polarity - CCNP: u1, - padding: u28, + /// VREFINT enable + VREFEN: u1, + /// Temperature sensor enable + VSENSEEN: u1, + /// VBAT enable + VBATEN: u1, + padding: u7, }), - reserved52: [16]u8, - /// capture/compare register x (x=1-2) - CCR: [2]mmio.Mmio(packed struct(u32) { - /// capture/compare x (x=1-4,6) value - CCR: u16, - padding: u16, + /// ADC common regular data register for dual and triple modes + CDR: mmio.Mmio(packed struct(u32) { + /// Regular data of the master ADC + RDATA_MST: u16, + /// Regular data of the slave ADC + RDATA_SLV: u16, }), - reserved104: [44]u8, - /// input selection register - TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1-2) input - TISEL: u4, - padding: u28, + /// ADC x common regular data register for 32-bit dual mode + CDR2: mmio.Mmio(packed struct(u32) { + /// Regular data of the master/slave alternated ADCs + RDATA_ALT: u32, }), }; + }; - /// 2-channel with one complementary output timers - pub const TIM_2CH_CMP = extern struct { - reserved4: [4]u8, - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Master mode selection - MMS: packed union { - raw: u3, - value: MMS, - }, - /// TI1 selection - TI1S: packed union { - raw: u1, - value: TI1S, - }, - /// Output Idle state x (x=1,2) - OIS: u1, - padding: u23, - }), - /// slave mode control register - SMCR: u32, - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - reserved6: u6, - /// Trigger interrupt enable - TIE: u1, - reserved13: u6, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding: u17, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1,2) interrupt flag - CCIF: u1, - reserved6: u4, - /// Trigger interrupt flag - TIF: u1, - reserved9: u2, - /// Capture/Compare x (x=1,2) overcapture flag - CCOF: u1, - padding: u22, - }), - /// event generation register - EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1,2) generation - CCG: u1, - reserved6: u4, - /// Trigger generation - TG: u1, - padding: u25, - }), - /// capture/compare mode register 1 (input mode) - CCMR_Input: [2]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: packed union { - raw: u2, - value: CCMR_Input_CCS, - }, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: packed union { - raw: u4, - value: FilterValue, - }, - padding: u24, - }), - /// capture/compare enable register - CCER: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Capture/Compare x (x=1) complementary output enable - CCNE: u1, - padding: u29, - }), - reserved52: [16]u8, - /// capture/compare register x (x=1-2) - CCR: [2]mmio.Mmio(packed struct(u32) { - /// capture/compare x (x=1-4,6) value - CCR: u16, - padding: u16, + pub const adf_v1 = struct { + /// DFLT trigger mode. This bitfield is set and cleared by software. It is used to select the trigger mode of the DFLT0. + pub const ACQMOD = enum(u3) { + /// Asynchronous continuous acquisition mode. + AsynchronousContinuous = 0x0, + /// Asynchronous single-shot acquisition mode + AsynchronousSingleShot = 0x1, + /// Synchronous continuous acquisition mode. + SyncronousContinuous = 0x2, + /// Synchronous single-shot acquisition mode. + SyncronousSingleShot = 0x3, + /// Window continuous acquisition mode. + WindowContinuous = 0x4, + _, + }; + + /// Bitstream selection. This bitfield is set and cleared by software. It is used to select the bitstream to be used by the DFLT0. + pub const BSSEL = enum(u5) { + /// bsx_r provided to DFLTy (and SCDy). + BS0_R = 0x0, + /// bsx_f provided to DFLTy (and SCDy). + BS0_F = 0x1, + /// bsx_r provided to DFLTy (and SCDy). + BS1_R = 0x2, + /// bsx_f provided to DFLTy (and SCDy). + BS1_F = 0x3, + /// bsx_r provided to DFLTy (and SCDy). + BS2_R = 0x4, + /// bsx_f provided to DFLTy (and SCDy). + BS2_F = 0x5, + /// bsx_r provided to DFLTy (and SCDy). + BS3_R = 0x6, + /// bsx_f provided to DFLTy (and SCDy). + BS3_F = 0x7, + /// bsx_r provided to DFLTy (and SCDy). + BS4_R = 0x8, + /// bsx_f provided to DFLTy (and SCDy). + BS4_F = 0x9, + /// bsx_r provided to DFLTy (and SCDy). + BS5_R = 0xa, + /// bsx_f provided to DFLTy (and SCDy). + BS5_F = 0xb, + /// bsx_r provided to DFLTy (and SCDy). + BS6_R = 0xc, + /// bsx_f provided to DFLTy (and SCDy). + BS6_F = 0xd, + /// bsx_r provided to DFLTy (and SCDy). + BS7_R = 0xe, + /// bsx_f provided to DFLTy (and SCDy). + BS7_F = 0xf, + /// bsx_r provided to DFLTy (and SCDy). + BS8_R = 0x10, + /// bsx_f provided to DFLTy (and SCDy). + BS8_F = 0x11, + /// bsx_r provided to DFLTy (and SCDy). + BS9_R = 0x12, + /// bsx_f provided to DFLTy (and SCDy). + BS9_F = 0x13, + /// bsx_r provided to DFLTy (and SCDy). + BS10_R = 0x14, + /// bsx_f provided to DFLTy (and SCDy). + BS10_F = 0x15, + /// bsx_r provided to DFLTy (and SCDy). + BS11_R = 0x16, + /// bsx_f provided to DFLTy (and SCDy). + BS11_F = 0x17, + /// bsx_r provided to DFLTy (and SCDy). + BS12_R = 0x18, + /// bsx_f provided to DFLTy (and SCDy). + BS12_F = 0x19, + /// bsx_r provided to DFLTy (and SCDy). + BS13_R = 0x1a, + /// bsx_f provided to DFLTy (and SCDy). + BS13_F = 0x1b, + /// bsx_r provided to DFLTy (and SCDy). + BS14_R = 0x1c, + /// bsx_f provided to DFLTy (and SCDy). + BS14_F = 0x1d, + /// bsx_r provided to DFLTy (and SCDy). + BS15_R = 0x1e, + /// bsx_f provided to DFLTy (and SCDy). + BS15_F = 0x1f, + }; + + /// CCK1 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin. + pub const CCKDIR = enum(u1) { + /// CCK is an input. + Input = 0x0, + /// CCK is an output. + Output = 0x1, + }; + + /// Divider to control the CCK clock. This bit is set and reset by software. It is used to control the frequency of the bitstream clock on the CCK pin. + pub const CCKDIV = enum(u4) { + /// The ADF_CCK clock is adf_proc_ck. + DIV1 = 0x0, + /// The ADF_CCK clock is adf_proc_ck divided by 2. + DIV2 = 0x1, + /// The ADF_CCK clock is adf_proc_ck divided by 3. + DIV3 = 0x2, + /// The ADF_CCK clock is adf_proc_ck divided by 4. + DIV4 = 0x3, + /// The ADF_CCK clock is adf_proc_ck divided by 5. + DIV5 = 0x4, + /// The ADF_CCK clock is adf_proc_ck divided by 6. + DIV6 = 0x5, + /// The ADF_CCK clock is adf_proc_ck divided by 7. + DIV7 = 0x6, + /// The ADF_CCK clock is adf_proc_ck divided by 8. + DIV8 = 0x7, + /// The ADF_CCK clock is adf_proc_ck divided by 9. + DIV9 = 0x8, + /// The ADF_CCK clock is adf_proc_ck divided by 10. + DIV10 = 0x9, + /// The ADF_CCK clock is adf_proc_ck divided by 11. + DIV11 = 0xa, + /// The ADF_CCK clock is adf_proc_ck divided by 12. + DIV12 = 0xb, + /// The ADF_CCK clock is adf_proc_ck divided by 13. + DIV13 = 0xc, + /// The ADF_CCK clock is adf_proc_ck divided by 14. + DIV14 = 0xd, + /// The ADF_CCK clock is adf_proc_ck divided by 15. + DIV15 = 0xe, + /// The ADF_CCK clock is adf_proc_ck divided by 16. + DIV16 = 0xf, + }; + + /// CCK clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin. + pub const CCKEN = enum(u1) { + /// Bitstream clock not generated. + NotGenerated = 0x0, + /// Bitstream clock generated on the CCK pin. + Generated = 0x1, + }; + + /// Select the CIC order. This bitfield is set and cleared by software. It is used to select the MCIC order. + pub const CICMOD = enum(u3) { + /// MCIC configured in single Sinc4 filter. + SINC4 = 0x4, + /// MCIC configured in single Sinc5 filter. + SINC5 = 0x5, + _, + }; + + /// Clock generator mode. This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1). + pub const CKGMOD = enum(u1) { + /// The kernel clock is provided to the dividers as soon as CKGDEN is set to 1. + Immediate = 0x0, + /// The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met. + Trigger = 0x1, + }; + + /// Data capture mode. This bitfield is set and cleared by software. It is used to define in which conditions, the samples provided by DLFT0 are stored into the memory. + pub const DATCAP = enum(u2) { + /// Samples from DFLT0 not transfered into the memory. + Disabled = 0x0, + /// Samples from DFLT0 transfered into the memory when SAD is in DETECT state. + OnDetected = 0x1, + /// Samples from DFLT0 transfered into memory when SAD and DFLT0 are enabled. + Enabled = 0x2, + _, + }; + + /// Source data for the digital filter. + pub const DATSRC = enum(u2) { + /// Stream coming from the BSMX selected + BSMX = 0x0, + /// Stream coming from the ADCITF1 selected + ADCITF1 = 0x2, + /// Stream coming from the ADCITF2 selected + ADCITF2 = 0x3, + _, + }; + + /// Sound trigger event configuration. This bit is set and cleared by software. It is used to define if the sddet_evt event is generated only when the SAD enters to MONITOR state or when the SAD enters or exits the DETECT state. + pub const DETCFG = enum(u1) { + /// sddet_evt generated when SAD enters the MONITOR state. + Monitor = 0x0, + /// sddet_evt generated when SAD enters or exits the DETECT state. + Detect = 0x1, + }; + + /// Frame size. This bitfield is set and cleared by software. it is used to define the size of one frame and also to define how many samples are taken into account to compute the short-term signal level. + pub const FRSIZE = enum(u3) { + /// 8 sample. + Samples8 = 0x0, + /// 16 samples. + Samples16 = 0x1, + /// 32 samples. + Samples32 = 0x2, + /// 64 samples. + Samples64 = 0x3, + /// 128 samples. + Samples128 = 0x4, + /// 256 samples. + Samples256 = 0x5, + /// 512 samples. + Samples512 = 0x6, + _, + }; + + /// Hangover time window. This bitfield is set and cleared by software. It is used to select the hangover time window. + pub const HGOVR = enum(u3) { + /// SAD back to MONITOR state if sound is below threshold for 4 frames. + @"Frames 4" = 0x0, + /// SAD back to MONITOR state if sound is below threshold for 4 frames. + @"Frames 8" = 0x1, + /// SAD back to MONITOR state if sound is below threshold for 4 frames. + @"Frames 16" = 0x2, + /// SAD back to MONITOR state if sound is below threshold for 4 frames. + @"Frames 32" = 0x3, + /// SAD back to MONITOR state if sound is below threshold for 4 frames. + @"Frames 64" = 0x4, + /// SAD back to MONITOR state if sound is below threshold for 4 frames. + @"Frames 128" = 0x5, + /// SAD back to MONITOR state if sound is below threshold for 4 frames. + @"Frames 256" = 0x6, + /// SAD back to MONITOR state if sound is below threshold for 4 frames. + @"Frames 512" = 0x7, + }; + + /// High-pass filter cut-off frequency. This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F PCM represents the sampling frequency at HPF input. + pub const HPFC = enum(u2) { + /// Cut-off frequency = 0.000625 x FPCM. + Low = 0x0, + /// Cut-off frequency = 0.00125 x FPCM. + Medium = 0x1, + /// Cut-off frequency = 0.00250 x FPCM + High = 0x2, + /// Cut-off frequency = 0.00950 x FPCM + Maximum = 0x3, + }; + + /// LFRNB. This bitfield is set and cleared by software. It is used to define the number of learning frames to perform the first estimate of the noise level. + pub const LFRNB = enum(u3) { + /// 2 samples. + @"Frames 2" = 0x0, + /// 4 samples. + @"Frames 4" = 0x1, + /// 8 samples. + @"Frames 8" = 0x2, + /// 16 samples. + @"Frames 16" = 0x3, + /// 32 samples. + @"Frames 32" = 0x4, + _, + }; + + /// Reshaper filter decimation ratio. This bitfield is set and cleared by software. It is used to select the decimation ratio of the reshaper filter. + pub const RSFLTD = enum(u1) { + /// Decimation ratio is 4 (default value). + Decimation4 = 0x0, + /// Decimation ratio is 1. + Decimation1 = 0x1, + }; + + /// RXFIFO threshold selection. This bitfield is set and cleared by software. It is used to select the RXFIFO threshold. + pub const RXFIFO = enum(u1) { + /// RXFIFO threshold event generated when the RXFIFO is not empty + NotEmpty = 0x0, + /// RXFIFO threshold event generated when the RXFIFO is half-full + HalfFull = 0x1, + }; + + /// SAD working mode. This bitfield is set and cleared by software. It is used to define the way the SAD works + pub const SADMOD = enum(u2) { + /// Threshold value computed according to the estimated ambient noise. The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a voice activity detector. + ThresholdEstimatedAmbientNoise = 0x0, + /// Threshold value equal to ANMIN[12:0], multiplied by the gain selected by SNTHR[3:0] The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a sound detector. + ThresholdMinimumNoiselevel = 0x1, + /// Threshold value given by 4 x ANMIN[12:0]. The SAD triggers when the estimated ambient noise (ANLVL), multiplied by the gain selected by SNTHR[3:0] is bigger than the defined threshold. In this mode, the SAD is working like an ambient noise estimator. Hysteresis function cannot be used in this mode. + ThresholdMinimumNoiselevelx4 = 0x2, + _, + }; + + /// SAD state. This bitfield is set and cleared by hardware. It indicates the SAD state and is meaningful only when SADEN = 1. + pub const SADST = enum(u2) { + /// SAD in LEARN state. + Learn = 0x0, + /// SAD in MONITOR state. + Monitor = 0x1, + /// SAD in DETECT state. + Detect = 0x2, + _, + }; + + /// Serial clock source. This bitfield is set and cleared by software. It is used to select the clock source of the serial interface. + pub const SCKSRC = enum(u2) { + /// Serial clock source is CCK0. + CCK0 = 0x0, + /// Serial clock source is CCK1. + CCK1 = 0x1, + /// Serial clock source is CCI0. + CKI0 = 0x2, + /// Serial clock source is CCI1. + CKI1 = 0x3, + }; + + /// Serial interface mode. This bitfield is set and cleared by software. It is used to select the serial interface mode. + pub const SITFMOD = enum(u2) { + /// LF_MASTER SPI mode. + MasterSPI = 0x0, + /// Normal SPI mode. + NormalSPI = 0x1, + /// Manchester mode rising edge = logic 0, falling edge = logic 1. + ManchesterFalling = 0x2, + /// Manchester mode rising edge = logic 1, falling edge = logic 0. + ManchesterRising = 0x3, + }; + + /// SNTHR. This bitfield is set and cleared by software. It is used to select the gain to be applied at CIC output. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this bitfield informs the application on the current gain value. + pub const SNTHR = enum(u4) { + /// Threshold is 3.5 dB higher than ANLVL + @"NOISE PLUS 3_5" = 0x0, + /// Threshold is 6.0 dB higher than ANLVL + @"NOISE PLUS 6_0" = 0x1, + /// Threshold is 9.5 dB higher than ANLVL + @"NOISE PLUS 9_5" = 0x2, + /// Threshold is 12 dB higher than ANLVL + @"NOISE PLUS 12" = 0x3, + /// Threshold is 15.6 dB higher than ANLVL + @"NOISE PLUS 15_6" = 0x4, + /// Threshold is 18 dB higher than ANLVL + @"NOISE PLUS 18" = 0x5, + /// Threshold is 21.6 dB higher than ANLVL + @"NOISE PLUS 21_6" = 0x6, + /// Threshold is 24.1 dB higher than ANLVL + @"NOISE PLUS 24_1" = 0x7, + /// Threshold is 27.6 dB higher than ANLVL + @"NOISE PLUS 27_6" = 0x8, + /// Threshold is 30.1 dB higher than ANLVL + @"NOISE PLUS 30_1" = 0x9, + _, + }; + + /// CKGEN trigger sensitivity selection. This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0. + pub const TRGSENS = enum(u1) { + /// A rising edge event triggers the activation of CKGEN dividers. + RisingEdge = 0x0, + /// A falling edge even triggers the activation of CKGEN dividers. + FallingEdge = 0x1, + }; + + /// Digital filter trigger signal selection. + pub const TRGSRC = enum(u4) { + /// TRGO Selected. + TRGO = 0x0, + /// adf_trg1 selected. + TRG1 = 0x2, + _, + }; + + /// ADF. + pub const ADF = extern struct { + /// ADF Global Control Register. + GCR: mmio.Mmio(packed struct(u32) { + /// Trigger output control Set by software and reset by. + TRGO: u1, + padding: u31, }), - reserved68: [8]u8, - /// break and dead-time register - BDTR: mmio.Mmio(packed struct(u32) { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: packed union { - raw: u2, - value: LOCK, - }, - /// Off-state selection for Idle mode - OSSI: packed union { + /// ADF clock generator control register. + CKGCR: mmio.Mmio(packed struct(u32) { + /// Clock generator dividers enable. + CKGDEN: u1, + /// CCK0 clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin. + CCK0EN: packed union { raw: u1, - value: OSSI, + value: CCKEN, }, - /// Off-state selection for Run mode - OSSR: packed union { + /// CCK1 clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin. + CCK1EN: packed union { raw: u1, - value: OSSR, + value: CCKEN, }, - /// Break x (x=1) enable - BKE: u1, - /// Break x (x=1) polarity - BKP: packed union { + reserved4: u1, + /// Clock generator mode. This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1). + CKGMOD: packed union { raw: u1, - value: BKP, - }, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - /// Break x (x=1) filter - BKF: packed union { - raw: u4, - value: FilterValue, + value: CKGMOD, }, - padding: u12, - }), - reserved104: [32]u8, - /// input selection register - TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1-2) input - TISEL: u4, - padding: u28, - }), - }; - - /// Advanced Control timers - pub const TIM_ADV = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Direction - DIR: packed union { + /// CCK0 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK0 pin. + CCK0DIR: packed union { raw: u1, - value: DIR, + value: CCKDIR, }, - /// Center-aligned mode selection - CMS: packed union { - raw: u2, - value: CMS, + /// CCK1 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin. + CCK1DIR: packed union { + raw: u1, + value: CCKDIR, }, reserved8: u1, - /// Clock division - CKD: packed union { - raw: u2, - value: CKD, + /// CKGEN trigger sensitivity selection. This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0. + TRGSENS: packed union { + raw: u1, + value: TRGSENS, }, - padding: u22, - }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Output Idle state x (x=1-6) - OIS: u1, - /// Output Idle state x N x (x=1-4) - OISN: u1, - reserved20: u10, - /// Master mode selection 2 - MMS2: packed union { + reserved12: u3, + /// Digital filter trigger signal selection. This bit is set and cleared by software. It is used to select the trigger signal for the digital filter. This bit is not significant if the CKGMOD = 0. + TRGSRC: packed union { raw: u4, - value: MMS2, + value: TRGSRC, }, - padding: u8, - }), - /// slave mode control register - SMCR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// External trigger filter - ETF: packed union { + /// Divider to control the CCK clock. + CCKDIV: packed union { raw: u4, - value: FilterValue, - }, - /// External trigger prescaler - ETPS: packed union { - raw: u2, - value: ETPS, - }, - /// External clock mode 2 enable - ECE: u1, - /// External trigger polarity - ETP: packed union { - raw: u1, - value: ETP, + value: CCKDIV, }, - padding: u16, - }), - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/Compare x (x=1-4) interrupt enable - CCIE: u1, - reserved9: u7, - /// Capture/Compare x (x=1-4) DMA request enable - CCDE: u1, - padding: u22, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1-4) interrupt flag - CCIF: u1, - reserved7: u5, - /// Break x (x=1,2) interrupt flag - BIF: u1, - reserved9: u1, - /// Capture/Compare x (x=1-4) overcapture flag - CCOF: u1, - reserved13: u3, - /// System break interrupt flag - SBIF: u1, - reserved16: u2, - /// Capture/compare 5 interrupt flag - CCIF5: u1, - /// Capture/compare 6 interrupt flag - CCIF6: u1, - padding: u14, - }), - /// event generation register - EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1-4) generation - CCG: u1, - reserved7: u5, - /// Break x (x=1-2) generation - BG: u1, - padding: u24, + reserved24: u4, + /// Divider to control the serial interface clock. + PROCDIV: u7, + /// Clock generator active flag. + CKGACTIVE: u1, }), - /// capture/compare mode register 1-2 (input mode) - CCMR_Input: [2]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: packed union { + reserved128: [120]u8, + /// ADF serial interface control register 0. + SITFCR: mmio.Mmio(packed struct(u32) { + SITFEN: u1, + SCKSRC: packed union { raw: u2, - value: CCMR_Input_CCS, + value: SCKSRC, }, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: packed union { - raw: u4, - value: FilterValue, + reserved4: u1, + SITFMOD: packed union { + raw: u2, + value: SITFMOD, }, - padding: u24, - }), - /// capture/compare enable register - CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-6) output enable - CCE: u1, - /// Capture/Compare x (x=1-6) output Polarity - CCP: u1, - /// Capture/Compare x (x=1-3) complementary output enable - CCNE: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCNP: u1, - padding: u28, - }), - reserved48: [12]u8, - /// repetition counter register - RCR: mmio.Mmio(packed struct(u32) { - /// Repetition counter value - REP: u16, - padding: u16, + reserved8: u2, + /// Manchester symbol threshold/SPI threshold. This bitfield is set and cleared by software. It is used for Manchester mode to define the expected symbol threshold levels (seer to Manchester mode for details on computation). In addition this bitfield is used to define the timeout value for the clock absence detection in Normal SPI mode. STH[4:0] values lower than four are invalid. + STH: u5, + reserved31: u18, + /// SITFACTIVE. + SITFACTIVE: u1, }), - /// capture/compare register x (x=1-4) - CCR: [4]mmio.Mmio(packed struct(u32) { - /// capture/compare x (x=1-4,6) value - CCR: u16, - padding: u16, + /// ADF bitstream matrix control register 0. + BSMXCR: mmio.Mmio(packed struct(u32) { + /// Bitstream selection. + BSSEL: packed union { + raw: u5, + value: BSSEL, + }, + reserved31: u26, + /// BSMX active flag. This bit is set and cleared by hardware. It is used by the application to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when BSMXACTIVE is set to 0. This BSMXACTIVE flag cannot go to 0 if DFLT0 is enabled. + BSMXACTIVE: u1, }), - /// break and dead-time register - BDTR: mmio.Mmio(packed struct(u32) { - reserved12: u12, - /// Break x (x=1,2) enable - BKE: u1, - /// Break x (x=1,2) polarity - BKP: packed union { + /// ADF digital filter control register 0. + DFLTCR: mmio.Mmio(packed struct(u32) { + /// DFLT enable. This bit is set and reset by software. It is used to enable the digital filter. + DFLTEN: u1, + /// DMA requests enable. This bit is set and reset by software. It is used to control the generation of DMA request to transfer the processed samples into the memory. + DMAEN: u1, + /// RXFIFO threshold selection. + FTH: packed union { raw: u1, - value: BKP, - }, - reserved16: u2, - /// Break x (x=1,2) filter - BKF: packed union { - raw: u4, - value: FilterValue, + value: RXFIFO, }, - padding: u12, - }), - reserved76: [4]u8, - /// DMA address for full transfer - DMAR: u32, - reserved84: [4]u8, - /// capture/compare mode register 3 - CCMR3: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Output compare x (x=5,6) fast enable - OCFE: u1, - /// Output compare x (x=5,6) preload enable - OCPE: u1, - /// Output compare x (x=5,6) mode - OCM: packed union { + reserved4: u1, + /// DFLT trigger mode. + ACQMOD: packed union { raw: u3, - value: OCM, - }, - /// Output compare x (x=5,6) clear enable - OCCE: u1, - padding: u24, - }), - /// capture/compare register 5 - CCR5: mmio.Mmio(packed struct(u32) { - reserved29: u29, - /// Group channel 5 and channel x (x=1-3) - GC5C: packed union { - raw: u1, - value: GC5C, + value: ACQMOD, }, - padding: u2, - }), - /// capture/compare register 6 - CCR6: mmio.Mmio(packed struct(u32) { - /// capture/compare x (x=1-4,6) value - CCR: u16, - padding: u16, - }), - /// alternate function register 1 - AF1: mmio.Mmio(packed struct(u32) { - reserved14: u14, - /// etr_in source selection - ETRSEL: u4, - padding: u14, + reserved12: u5, + /// DFLT trigger signal selection. + TRGSRC: u4, + reserved20: u4, + /// Number of samples to be discarded. + NBDIS: u8, + reserved30: u2, + /// DFLT run status flag. + DFLTRUN: u1, + /// DFLT active flag. + DFLTACTIVE: u1, }), - /// alternate function register 2 - AF2: mmio.Mmio(packed struct(u32) { - /// TIMx_BKIN2 input enable - BK2INE: u1, - /// TIM_BRK2_CMPx (x=1-8) enable - BK2CMPE: u1, - reserved8: u6, - /// BRK2 DFSDM1_BREAK1 enable - BK2DF1BK1E: u1, - /// TIMx_BK2IN input polarity - BK2INP: packed union { - raw: u1, - value: BKINP, - }, - /// TIM_BRK2_CMPx (x=1-4) input polarity - BK2CMPP: packed union { - raw: u1, - value: BKINP, + /// ADF digital filer configuration register 0. + DFLTCICR: mmio.Mmio(packed struct(u32) { + /// Source data for the digital filter. + DATSRC: packed union { + raw: u2, + value: DATSRC, }, - padding: u21, - }), - /// input selection register - TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1-4) input - TISEL: u4, - padding: u28, - }), - }; - - /// Basic timers - pub const TIM_BASIC = extern struct { - reserved4: [4]u8, - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Master mode selection - MMS: packed union { + reserved4: u2, + /// Select the CIC order. + CICMOD: packed union { raw: u3, - value: MMS, + value: CICMOD, }, - padding: u25, - }), - }; - - /// Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP - pub const TIM_BASIC_NO_CR2 = extern struct { - reserved12: [12]u8, - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Update DMA request enable - UDE: u1, - padding: u23, + reserved8: u1, + /// CIC decimation ratio selection. This bitfield is set and cleared by software.It is used to select the CIC decimation ratio. A decimation ratio smaller than two is not allowed. The decimation ratio is given by (CICDEC+1). + MCICD: u9, + reserved20: u3, + /// Scaling factor selection. This bitfield is set and cleared by software. It is used to select the gain to be applied at CIC output. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this bitfield informs the application on the current gain value. + SCALE: u6, + padding: u6, }), - }; - - /// Virtual timer for common part of TIM_BASIC and TIM_1CH - pub const TIM_CORE = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: packed union { + /// ADF reshape filter configuration register 0. + DFLTRSFR: mmio.Mmio(packed struct(u32) { + /// Reshaper filter bypass. + RSFLTBYP: u1, + reserved4: u3, + /// Reshaper filter decimation ratio. + RSFLTD: packed union { raw: u1, - value: URS, + value: RSFLTD, }, - /// One-pulse mode enbaled - OPM: u1, - reserved7: u3, - /// Auto-reload preload enable - ARPE: u1, - reserved11: u3, - /// UIF status bit remapping enable - UIFREMAP: u1, - padding: u20, - }), - reserved12: [8]u8, - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - /// Update interrupt enable - UIE: u1, - padding: u31, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Update interrupt flag - UIF: u1, - padding: u31, + reserved7: u2, + /// High-pass filter bypass. This bit is set and cleared by software. It is used to bypass the high-pass filter. + HPFBYP: u1, + /// High-pass filter cut-off frequency. This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F PCM represents the sampling frequency at HPF input. + HPFC: packed union { + raw: u2, + value: HPFC, + }, + padding: u22, }), - /// event generation register - EGR: mmio.Mmio(packed struct(u32) { - /// Update generation - UG: u1, - padding: u31, + reserved164: [16]u8, + /// ADF delay control register 0. + DLYCR: mmio.Mmio(packed struct(u32) { + /// Delay to apply to a bitstream. This bitfield is set and cleared by software. It defines the number of input samples that are skipped. Skipping is applied immediately after writing to this bitfield, if SKPBF = 0 and DFLTEN = 1. If SKPBF = 1, the value written into the register is ignored by the delay state machine. + SKPDLY: u7, + reserved31: u24, + /// Skip busy flag. + SKPBF: u1, }), - reserved36: [12]u8, - /// counter - CNT: mmio.Mmio(packed struct(u32) { - /// counter value - CNT: u16, - reserved31: u15, - /// UIF copy - UIFCPY: u1, + reserved172: [4]u8, + /// ADF DFLT0 interrupt enable register. + DFLTIER: mmio.Mmio(packed struct(u32) { + /// RXFIFO threshold interrupt enable. + FTHIE: u1, + /// Data overflow interrupt enable. + DOVRIE: u1, + reserved9: u7, + /// Saturation detection interrupt enable. + SATIE: u1, + /// Clock absence detection interrupt enable. + CKABIE: u1, + /// Reshape filter overrun interrupt enable. + RFOVRIE: u1, + /// Sound activity detection interrupt enable. + SDDETIE: u1, + /// SAD sound-level value ready enable. + SDLVLIE: u1, + padding: u18, }), - /// prescaler - PSC: u32, - /// auto-reload register - ARR: mmio.Mmio(packed struct(u32) { - /// Auto-reload value - ARR: u16, - padding: u16, + /// ADF DFLT0 interrupt status register 0. + DFLTISR: mmio.Mmio(packed struct(u32) { + /// RXFIFO threshold flag. + FTHF: u1, + /// Data overflow flag. + DOVRF: u1, + reserved3: u1, + /// RXFIFO not empty flag. + RXNEF: u1, + reserved9: u5, + /// Saturation detection flag. + SATF: u1, + /// Clock absence detection flag. + CKABF: u1, + /// Reshape filter overrun detection flag. + RFOVRF: u1, + /// Sound activity detection flag. + SDDETF: u1, + /// Sound level value ready flag. + SDLVLF: u1, + padding: u18, }), - }; - - /// General purpose 16-bit timers - pub const TIM_GP16 = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Direction - DIR: packed union { - raw: u1, - value: DIR, - }, - /// Center-aligned mode selection - CMS: packed union { + reserved184: [4]u8, + /// ADF SAD control register. + SADCR: mmio.Mmio(packed struct(u32) { + /// Sound activity detector enable. + SADEN: u1, + /// Data capture mode. + DATCAP: packed union { raw: u2, - value: CMS, + value: DATCAP, }, - reserved8: u1, - /// Clock division - CKD: packed union { + /// Sound trigger event configuration. + DETCFG: packed union { + raw: u1, + value: DETCFG, + }, + /// SAD state. + SADST: packed union { raw: u2, - value: CKD, + value: SADST, }, - padding: u22, - }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Capture/compare DMA selection - CCDS: packed union { - raw: u1, - value: CCDS, + reserved7: u1, + /// Hysteresis enable. + HYSTEN: u1, + /// Frame size. + FRSIZE: packed union { + raw: u3, + value: FRSIZE, }, - reserved7: u3, - /// TI1 selection - TI1S: packed union { - raw: u1, - value: TI1S, + reserved12: u1, + /// Sound activity detector working mode. + SADMOD: packed union { + raw: u2, + value: SADMOD, }, - padding: u24, + reserved31: u17, + /// SAD Active flag. + SADACTIVE: u1, }), - /// slave mode control register - SMCR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// External trigger filter - ETF: packed union { + /// ADF SAD configuration register. + SADCFGR: mmio.Mmio(packed struct(u32) { + /// SNTHR. + SNTHR: packed union { raw: u4, - value: FilterValue, + value: SNTHR, }, - /// External trigger prescaler - ETPS: packed union { - raw: u2, - value: ETPS, + /// ANSLP. + ANSLP: u3, + reserved8: u1, + /// LFRNB. + LFRNB: packed union { + raw: u3, + value: LFRNB, }, - /// External clock mode 2 enable - ECE: u1, - /// External trigger polarity - ETP: packed union { - raw: u1, - value: ETP, + reserved12: u1, + /// Hangover time window. + HGOVR: packed union { + raw: u3, + value: HGOVR, }, - padding: u16, + reserved16: u1, + /// ANMIN. + ANMIN: u13, + padding: u3, }), - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/Compare x (x=1-4) interrupt enable - CCIE: u1, - reserved6: u4, - /// Trigger interrupt enable - TIE: u1, - reserved9: u2, - /// Capture/Compare x (x=1-4) DMA request enable - CCDE: u1, - reserved14: u4, - /// Trigger DMA request enable - TDE: u1, + /// ADF SAD sound level register. + SADSDLVR: mmio.Mmio(packed struct(u32) { + /// Short term sound level. This bitfield is set by hardware. It contains the latest sound level computed by the SAD. To refresh this value, SDLVLF must be cleared. + SDLVL: u15, padding: u17, }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1-4) interrupt flag - CCIF: u1, - reserved6: u4, - /// Trigger interrupt flag - TIF: u1, - reserved9: u2, - /// Capture/Compare x (x=1-4) overcapture flag - CCOF: u1, - padding: u22, + /// ADF SAD ambient noise level register. + SADANLVR: mmio.Mmio(packed struct(u32) { + /// ANLVL. + ANLVL: u15, + padding: u17, }), - /// event generation register - EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1-4) generation - CCG: u1, - reserved6: u4, - /// Trigger generation - TG: u1, - padding: u25, - }), - /// capture/compare mode register 1-2 (input mode) - CCMR_Input: [2]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: packed union { - raw: u2, - value: CCMR_Input_CCS, - }, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: packed union { - raw: u4, - value: FilterValue, - }, - padding: u24, - }), - /// capture/compare enable register - CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-4) output enable - CCE: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCP: u1, - reserved3: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCNP: u1, - padding: u28, - }), - reserved52: [16]u8, - /// capture/compare register x (x=1-4) - CCR: [4]mmio.Mmio(packed struct(u32) { - /// capture/compare x (x=1-4,6) value - CCR: u16, - padding: u16, - }), - reserved72: [4]u8, - /// DMA control register - DCR: mmio.Mmio(packed struct(u32) { - /// DMA base address - DBA: u5, - reserved8: u3, - /// DMA burst length - DBL: u5, - padding: u19, - }), - /// DMA address for full transfer - DMAR: mmio.Mmio(packed struct(u32) { - /// DMA register for burst accesses - DMAB: u16, - padding: u16, - }), - reserved96: [16]u8, - /// alternate function register 1 - AF1: mmio.Mmio(packed struct(u32) { - reserved14: u14, - /// etr_in source selection - ETRSEL: u4, - padding: u14, - }), - reserved104: [4]u8, - /// input selection register - TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1-4) input - TISEL: u4, - padding: u28, + reserved240: [40]u8, + /// ADF digital filter data register 0. + DFLTDR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// DR. Data processed by DFT + DR: u24, }), }; + }; - /// General purpose 32-bit timers - pub const TIM_GP32 = extern struct { - reserved36: [36]u8, - /// counter - CNT: u32, - reserved44: [4]u8, - /// auto-reload register - ARR: u32, - reserved52: [4]u8, - /// capture/compare register x (x=1-4) - CCR: [4]u32, + pub const aes_f7 = struct { + pub const DATATYPE = enum(u2) { + /// Word + None = 0x0, + /// Half-word (16-bit) + HalfWord = 0x1, + /// Byte (8-bit) + Byte = 0x2, + /// Bit + Bit = 0x3, }; - }; - pub const pwr_wb = struct { - /// Power control - pub const PWR = extern struct { - /// Power control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection for CPU1 - LPMS: u3, - reserved4: u1, - /// Flash power down mode during LPRun for CPU1 - FPDR: u1, - /// Flash power down mode during LPsSleep for CPU1 - FPDS: u1, - reserved8: u2, - /// Disable backup domain write protection - DBP: u1, - reserved14: u5, - /// Low-power run - LPR: u1, - padding: u17, + pub const GCMPH = enum(u2) { + /// Init phase + @"Init phase" = 0x0, + /// Header phase + @"Header phase" = 0x1, + /// Payload phase + @"Payload phase" = 0x2, + /// Final phase + @"Final phase" = 0x3, + }; + + pub const MODE = enum(u2) { + /// Encryption + Mode1 = 0x0, + /// Key derivation (or key preparation for ECB/CBC decryption) + Mode2 = 0x1, + /// Decryption + Mode3 = 0x2, + /// Key derivation then single decryption + Mode4 = 0x3, + }; + + /// Advanced encryption standard hardware accelerator + pub const AES = extern struct { + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// AES enable + EN: u1, + /// Data type selection + DATATYPE: packed union { + raw: u2, + value: DATATYPE, + }, + /// Operating mode + MODE: packed union { + raw: u2, + value: MODE, + }, + /// Chaining mode bit1 bit0 + CHMOD10: u2, + /// Computation Complete Flag Clear + CCFC: u1, + /// Error clear + ERRC: u1, + /// CCF flag interrupt enable + CCFIE: u1, + /// Error interrupt enable + ERRIE: u1, + /// Enable DMA management of data input phase + DMAINEN: u1, + /// Enable DMA management of data output phase + DMAOUTEN: u1, + /// GCM or CCM phase selection + GCMPH: packed union { + raw: u2, + value: GCMPH, + }, + reserved16: u1, + /// Chaining mode bit2 + CHMOD2: u1, + reserved18: u1, + /// Key size selection + KEYSIZE: u1, + padding: u13, }), - /// Power control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Power voltage detector enable - PVDE: u1, - /// Power voltage detector level selection - PLS: u3, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Computation complete flag + CCF: u1, + /// Read error flag + RDERR: u1, + /// Write error flag + WRERR: u1, + /// Busy flag + BUSY: u1, padding: u28, }), - /// Power control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin - EWUP: u1, - reserved8: u7, - /// Enable BORH and Step Down counverter forced in Bypass interrups for CPU1 - EBORHSDFB: u1, - /// SRAM2a retention in Standby mode - RRS: u1, - /// Apply pull-up and pull-down configuration - APC: u1, - /// Enable BLE end of activity interrupt for CPU1 - EBLEA: u1, - /// Enable critical radio phase end of activity interrupt for CPU1 - ECRPE: u1, - /// Enable end of activity interrupt for CPU1 - E802A: u1, - /// Enable CPU2 Hold interrupt for CPU1 - EC2H: u1, - /// Enable internal wakeup line for CPU1 - EIWUL: u1, - padding: u16, - }), - /// Power control register 4 - CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity - WP1: u1, - reserved8: u7, - /// VBAT battery charging enable - VBE: u1, - /// VBAT battery charging resistor selection - VBRS: u1, - reserved15: u5, - /// BOOT CPU2 after reset or wakeup from Stop or Standby modes - C2BOOT: u1, - padding: u16, - }), - /// Power status register 1 - SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag 1 - CWUF: u1, - reserved7: u6, - /// Step Down converter forced in Bypass interrupt flag - SDFBF: u1, - /// BORH interrupt flag - BORHF: u1, - /// BLE wakeup interrupt flag - BLEWUF: u1, - /// 802.15.4 wakeup interrupt flag - _802WUF: u1, - /// Enable critical radio phase end of activity interrupt flag - CRPEF: u1, - /// BLE end of activity interrupt flag - BLEAF: u1, - /// 802.15.4 end of activity interrupt flag - AF802: u1, - /// CPU2 Hold interrupt flag - C2HF: u1, - /// Internal Wakeup interrupt flag - WUFI: u1, - padding: u16, - }), - /// Power status register 2 - SR2: mmio.Mmio(packed struct(u32) { - /// Step Down converter Bypass mode flag - SDBF: u1, - /// Step Down converter SMPS mode flag - SDSMPSF: u1, - reserved8: u6, - /// Low-power regulator started - REGLPS: u1, - /// Low-power regulator flag - REGLPF: u1, - /// Voltage scaling flag - VOSF: u1, - /// Power voltage detector output - PVDO: u1, - /// Peripheral voltage monitoring output: VDDUSB vs. 1.2 V - PVMO1: u1, - reserved14: u1, - /// Peripheral voltage monitoring output: VDDA vs. 1.62 V - PVMO3: u1, - padding: u17, - }), - /// Power status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag 1 - CWUF: u1, - reserved7: u6, - /// Clear SMPS Step Down converter forced in Bypass interrupt flag - CSMPSFBF: u1, - /// Clear BORH interrupt flag - CBORHF: u1, - /// Clear BLE wakeup interrupt flag - CBLEWUF: u1, - /// Clear 802.15.4 wakeup interrupt flag - C802WUF: u1, - /// Clear critical radio phase end of activity interrupt flag - CCRPEF: u1, - /// Clear BLE end of activity interrupt flag - CBLEAF: u1, - /// Clear 802.15.4 end of activity interrupt flag - C802AF: u1, - /// Clear CPU2 Hold interrupt flag - CC2HF: u1, - padding: u17, - }), - /// Power control register 5 - CR5: mmio.Mmio(packed struct(u32) { - /// Step Down converter voltage output scaling - SDVOS: u4, - /// Step Down converter supplt startup current selection - SDSC: u3, - reserved8: u1, - /// BORH configuration selection - BORHC: u1, - /// VOS configuration selection (non user) - SMPSCFG: u1, - reserved14: u4, - /// Enable Step Down converter Bypass mode enabled - SDBEN: u1, - /// Enable Step Down converter SMPS mode enabled - SDEB: u1, - padding: u16, - }), - /// Power Port A pull-up control register - PUCRA: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, - }), - /// Power Port A pull-down control register - PDCRA: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, - }), - /// Power Port B pull-up control register - PUCRB: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, - }), - /// Power Port B pull-down control register - PDCRB: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, - }), - /// Power Port C pull-up control register - PUCRC: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, - }), - /// Power Port C pull-down control register - PDCRC: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, - }), - /// Power Port D pull-up control register - PUCRD: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, - }), - /// Power Port D pull-down control register - PDCRD: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, - }), - /// Power Port E pull-up control register - PUCRE: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, - }), - /// Power Port E pull-down control register - PDCRE: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, - }), - reserved88: [16]u8, - /// Power Port H pull-up control register - PUCRH: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// Data input register + DINR: mmio.Mmio(packed struct(u32) { + /// Input data word + DIN: u32, }), - /// Power Port H pull-down control register - PDCRH: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// Data output register + DOUTR: mmio.Mmio(packed struct(u32) { + /// Output data word + DOUT: u32, }), - reserved128: [32]u8, - /// CPU2 Power control register 1 - C2CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection for CPU2 - LPMS: u3, - reserved4: u1, - /// Flash power down mode during LPRun for CPU2 - FPDR: u1, - /// Flash power down mode during LPSleep for CPU2 - FPDS: u1, - reserved14: u8, - /// BLE external wakeup signal - BLEEWKUP: u1, - /// 802.15.4 external wakeup signal - _802EWKUP: u1, - padding: u16, + /// Key register + KEYR: mmio.Mmio(packed struct(u32) { + /// Cryptographic key + KEY: u32, }), - /// CPU2 Power control register 3 - C2CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin - EWUP: u1, - reserved9: u8, - /// Enable BLE host wakeup interrupt for CPU2 - EBLEWUP: u1, - /// Enable 802.15.4 host wakeup interrupt for CPU2 - E802WUP: u1, - reserved12: u1, - /// Apply pull-up and pull-down configuration for CPU2 - APC: u1, - reserved15: u2, - /// Enable internal wakeup line for CPU2 - EIWUL: u1, - padding: u16, + reserved32: [12]u8, + /// Initialization vector register + IVR: [4]mmio.Mmio(packed struct(u32) { + /// Initialization vector input + IVI: u32, }), - /// Power status clear register - EXTSCR: mmio.Mmio(packed struct(u32) { - /// Clear CPU1 Stop Standby flags - C1CSSF: u1, - /// Clear CPU2 Stop Standby flags - C2CSSF: u1, - /// Clear Critical Radio system phase - CCRPF: u1, - reserved8: u5, - /// System Standby flag for CPU1 - C1SBF: u1, - /// System Stop flag for CPU1 - C1STOPF: u1, - /// System Standby flag for CPU2 - C2SBF: u1, - /// System Stop flag for CPU2 - C2STOPF: u1, - reserved13: u1, - /// Critical Radio system phase - CRPF: u1, - /// CPU1 deepsleep mode - C1DS: u1, - /// CPU2 deepsleep mode - C2DS: u1, - padding: u16, + reserved64: [16]u8, + /// Suspend register + SUSPR: [8]mmio.Mmio(packed struct(u32) { + /// AES suspend + SUSP: u32, }), }; }; @@ -311943,13398 +311994,12414 @@ pub const types = struct { }; }; - pub const rng_v1 = struct { - /// Random number generator - pub const RNG = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Random number generator enable - RNGEN: u1, - /// Interrupt enable - IE: u1, - reserved5: u1, - /// Clock error detection - CED: u1, - padding: u26, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Data ready - DRDY: u1, - /// Clock error current status - CECS: u1, - /// Seed error current status - SECS: u1, - reserved5: u2, - /// Clock error interrupt status - CEIS: u1, - /// Seed error interrupt status - SEIS: u1, - padding: u25, - }), - /// data register - DR: u32, + pub const aes_v2 = struct { + pub const DATATYPE = enum(u2) { + /// Word + None = 0x0, + /// Half-word (16-bit) + HalfWord = 0x1, + /// Byte (8-bit) + Byte = 0x2, + /// Bit + Bit = 0x3, }; - }; - pub const flash_wb = struct { - /// Flash - pub const FLASH = extern struct { - /// Access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: u3, - reserved8: u5, - /// Prefetch enable - PRFTEN: u1, - /// Instruction cache enable - ICEN: u1, - /// Data cache enable - DCEN: u1, - /// Instruction cache reset - ICRST: u1, - /// Data cache reset - DCRST: u1, - reserved15: u2, - /// CPU1 CortexM4 program erase suspend request - PES: u1, - /// Flash User area empty - EMPTY: u1, - padding: u15, - }), - reserved8: [4]u8, - /// Flash key register - KEYR: u32, - /// Option byte key register - OPTKEYR: u32, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved3: u1, - /// Programming error - PROGERR: u1, - /// Write protected error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Size error - SIZERR: u1, - /// Programming sequence error - PGSERR: u1, - /// Fast programming data miss error - MISERR: u1, - /// Fast programming error - FASTERR: u1, - reserved13: u3, - /// User Option OPTVAL indication - OPTNV: u1, - /// PCROP read error - RDERR: u1, - /// Option validity error - OPTVERR: u1, - /// Busy - BSY: u1, - reserved18: u1, - /// Programming or erase configuration busy - CFGBSY: u1, - /// Programming or erase operation suspended - PESD: u1, - padding: u12, - }), - /// Flash control register + pub const GCMPH = enum(u2) { + /// Init phase + @"Init phase" = 0x0, + /// Header phase + @"Header phase" = 0x1, + /// Payload phase + @"Payload phase" = 0x2, + /// Final phase + @"Final phase" = 0x3, + }; + + pub const MODE = enum(u2) { + /// Encryption + Mode1 = 0x0, + /// Key derivation (or key preparation for ECB/CBC decryption) + Mode2 = 0x1, + /// Decryption + Mode3 = 0x2, + /// Key derivation then single decryption + Mode4 = 0x3, + }; + + /// Advanced encryption standard hardware accelerator + pub const AES = extern struct { + /// Control register CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Page erase - PER: u1, - /// This bit triggers the mass erase (all user pages) when set - MER: u1, - /// Page number selection - PNB: u8, - reserved16: u5, - /// Start - STRT: u1, - /// Options modification start - OPTSTRT: u1, - /// Fast programming - FSTPG: u1, - reserved24: u5, - /// End of operation interrupt enable - EOPIE: u1, + /// AES enable + EN: u1, + /// Data type selection + DATATYPE: packed union { + raw: u2, + value: DATATYPE, + }, + /// Operating mode + MODE: packed union { + raw: u2, + value: MODE, + }, + /// Chaining mode bit1 bit0 + CHMOD10: u2, + /// Computation Complete Flag Clear + CCFC: u1, + /// Error clear + ERRC: u1, + /// CCF flag interrupt enable + CCFIE: u1, /// Error interrupt enable ERRIE: u1, - /// PCROP read error interrupt enable - RDERRIE: u1, - /// Force the option byte loading - OBL_LAUNCH: u1, - reserved30: u2, - /// Options Lock - OPTLOCK: u1, - /// FLASH_CR Lock - LOCK: u1, - }), - /// Flash ECC register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC fail address - ADDR_ECC: u17, - reserved20: u3, - /// System Flash ECC fail - SYSF_ECC: u1, - reserved24: u3, - /// ECC correction interrupt enable - ECCCIE: u1, - reserved26: u1, - /// CPU identification - CPUID: u3, - reserved30: u1, - /// ECC correction - ECCC: u1, - /// ECC detection - ECCD: u1, - }), - reserved32: [4]u8, - /// Flash option register - OPTR: mmio.Mmio(packed struct(u32) { - /// Read protection level - RDP: u8, - /// Security enabled - ESE: u1, - /// BOR reset Level - BOR_LEV: u3, - /// nRST_STOP - nRST_STOP: u1, - /// nRST_STDBY - nRST_STDBY: u1, - /// nRST_SHDW - nRST_SHDW: u1, + /// Enable DMA management of data input phase + DMAINEN: u1, + /// Enable DMA management of data output phase + DMAOUTEN: u1, + /// GCM or CCM phase selection + GCMPH: packed union { + raw: u2, + value: GCMPH, + }, reserved16: u1, - /// Independent watchdog selection - IDWG_SW: u1, - /// Independent watchdog counter freeze in Stop mode - IWDG_STOP: u1, - /// Independent watchdog counter freeze in Standby mode - IWDG_STDBY: u1, - /// Window watchdog selection - WWDG_SW: u1, - reserved23: u3, - /// Boot configuration - nBOOT1: u1, - /// SRAM2 parity check enable - SRAM2_PE: u1, - /// SRAM2 Erase when system reset - SRAM2_RST: u1, - /// Software Boot0 - nSWBOOT0: u1, - /// nBoot0 option bit - nBOOT0: u1, - reserved29: u1, - /// Radio Automatic Gain Control Trimming - AGC_TRIM: u3, - }), - /// Flash Bank 1 PCROP Start address zone A register - PCROP1ASR: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROPQ area start offset - PCROP1A_STRT: u9, - padding: u23, + /// Chaining mode bit2 + CHMOD2: u1, + reserved18: u1, + /// Key size selection + KEYSIZE: u1, + reserved20: u1, + /// Number of padding bytes in last block of payload + NPBLB: u4, + padding: u8, }), - /// Flash Bank 1 PCROP End address zone A register - PCROP1AER: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area end offset - PCROP1A_END: u9, - reserved31: u22, - /// PCROP area preserved when RDP level decreased - PCROP_RDP: u1, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Computation complete flag + CCF: u1, + /// Read error flag + RDERR: u1, + /// Write error flag + WRERR: u1, + /// Busy flag + BUSY: u1, + padding: u28, }), - /// Flash Bank 1 WRP area A address register - WRP1AR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP first area A start offset - WRP1A_STRT: u8, - reserved16: u8, - /// Bank 1 WRP first area A end offset - WRP1A_END: u8, - padding: u8, + /// Data input register + DINR: mmio.Mmio(packed struct(u32) { + /// Input data word + DIN: u32, }), - /// Flash Bank 1 WRP area B address register - WRP1BR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP second area B start offset - WRP1B_END: u8, - reserved16: u8, - /// Bank 1 WRP second area B end offset - WRP1B_STRT: u8, - padding: u8, + /// Data output register + DOUTR: mmio.Mmio(packed struct(u32) { + /// Output data word + DOUT: u32, }), - /// Flash Bank 1 PCROP Start address area B register - PCROP1BSR: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area B start offset - PCROP1B_STRT: u9, - padding: u23, + /// Key register + KEYR: mmio.Mmio(packed struct(u32) { + /// Cryptographic key + KEY: u32, }), - /// Flash Bank 1 PCROP End address area B register - PCROP1BER: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area end area B offset - PCROP1B_END: u9, - padding: u23, + reserved32: [12]u8, + /// Initialization vector register + IVR: [4]mmio.Mmio(packed struct(u32) { + /// Initialization vector input + IVI: u32, }), - /// IPCC mailbox data buffer address register - IPCCBR: mmio.Mmio(packed struct(u32) { - /// PCC mailbox data buffer base address - IPCCDBA: u14, - padding: u18, + reserved64: [16]u8, + /// Suspend register + SUSPR: [8]mmio.Mmio(packed struct(u32) { + /// AES suspend + SUSP: u32, }), - reserved92: [28]u8, - /// CPU2 cortex M0 access control register - C2ACR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// CPU2 cortex M0 prefetch enable - PRFTEN: u1, - /// CPU2 cortex M0 instruction cache enable - ICEN: u1, - reserved11: u1, - /// CPU2 cortex M0 instruction cache reset - ICRST: u1, - reserved15: u3, - /// CPU2 cortex M0 program erase suspend request - PES: u1, - padding: u16, + }; + }; + + pub const aes_v3a = struct { + pub const CHMOD = enum(u3) { + /// Electronic codebook + ECB = 0x0, + /// Cipher-block chaining + CBC = 0x1, + /// Counter mode + CTR = 0x2, + /// Galois counter mode and Galois message authentication code + GCM_GMAC = 0x3, + /// Counter with CBC-MAC + CCM = 0x4, + _, + }; + + pub const DATATYPE = enum(u2) { + /// Word + None = 0x0, + /// Half-word (16-bit) + HalfWord = 0x1, + /// Byte (8-bit) + Byte = 0x2, + /// Bit + Bit = 0x3, + }; + + pub const GCMPH = enum(u2) { + /// Init phase + @"Init phase" = 0x0, + /// Header phase + @"Header phase" = 0x1, + /// Payload phase + @"Payload phase" = 0x2, + /// Final phase + @"Final phase" = 0x3, + }; + + pub const MODE = enum(u2) { + /// Encryption + Mode1 = 0x0, + /// Key derivation (or key preparation for ECB/CBC decryption) + Mode2 = 0x1, + /// Decryption + Mode3 = 0x2, + _, + }; + + /// Advanced encryption standard hardware accelerator + pub const AES = extern struct { + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// AES enable + EN: u1, + /// Data type selection + DATATYPE: packed union { + raw: u2, + value: DATATYPE, + }, + /// Operating mode + MODE: packed union { + raw: u2, + value: MODE, + }, + padding: u27, }), - /// CPU2 cortex M0 status register - C2SR: mmio.Mmio(packed struct(u32) { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved3: u1, - /// Programming error - PROGERR: u1, - /// write protection error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Size error - SIZERR: u1, - /// Programming sequence error - PGSERR: u1, - /// Fast programming data miss error - MISSERR: u1, - /// Fast programming error - FASTERR: u1, - reserved14: u4, - /// PCROP read error + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Computation complete flag + CCF: u1, + /// Read error flag RDERR: u1, - reserved16: u1, - /// Busy - BSY: u1, - reserved18: u1, - /// Programming or erase configuration busy - CFGBSY: u1, - /// Programming or erase operation suspended - PESD: u1, - padding: u12, + /// Write error flag + WRERR: u1, + /// Busy flag + BUSY: u1, + reserved7: u3, + /// Key valid flag + KEYVALID: u1, + padding: u24, }), - /// CPU2 cortex M0 control register - C2CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Page erase - PER: u1, - /// Masse erase - MER: u1, - /// Page Number selection - PNB: u8, - reserved16: u5, - /// Start - STRT: u1, - reserved18: u1, - /// Fast programming - FSTPG: u1, - reserved24: u5, - /// End of operation interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// PCROP read error interrupt enable - RDERRIE: u1, - padding: u5, + /// Data input register + DINR: u32, + /// Data output register + DOUTR: u32, + /// Key register + KEYR: u32, + reserved32: [12]u8, + /// Initialization vector register + IVR: [4]u32, + reserved64: [16]u8, + /// Suspend register + SUSPR: [8]u32, + reserved768: [672]u8, + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// Computation complete flag interrupt enable + CCFIE: u1, + /// Read or write error interrupt enable + RWEIE: u1, + /// Key error interrupt enable + KEIE: u1, + padding: u29, }), - reserved128: [24]u8, - /// Secure flash start address register - SFR: mmio.Mmio(packed struct(u32) { - /// Secure flash start address - SFSA: u8, - /// Flash security disable - FSD: u1, - reserved12: u3, - /// Disable Cortex M0 debug access - DDS: u1, - padding: u19, + /// interrupt status register + ISR: mmio.Mmio(packed struct(u32) { + /// Computation complete flag + CCF: u1, + /// Read or write error interrupt flag + RWEIF: u1, + /// Key error interrupt flag + KEIF: u1, + padding: u29, }), - /// Secure SRAM2 start address and cortex M0 reset vector register - SRRVR: mmio.Mmio(packed struct(u32) { - /// cortex M0 access control register - SBRV: u18, - /// Secure backup SRAM2a start address - SBRSA: u5, - /// backup SRAM2a security disable - BRSD: u1, - reserved25: u1, - /// Secure non backup SRAM2a start address - SNBRSA: u5, - /// non-backup SRAM2b security disable - NBRSD: u1, - /// CPU2 cortex M0 boot reset vector memory selection - C2OPT: u1, + /// interrupt clear register + ICR: mmio.Mmio(packed struct(u32) { + /// Computation complete flag clear + CCF: u1, + /// Read or write error interrupt flag clear + RWEIF: u1, + /// Key error interrupt flag clear + KEIF: u1, + padding: u29, }), }; }; - pub const syscfg_l4 = struct { - /// System configuration controller - pub const SYSCFG = extern struct { - /// memory remap register - MEMRMP: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection - MEM_MODE: u3, - /// QUADSPI memory mapping swap - QFS: u1, - reserved8: u4, - /// Flash Bank mode selection - FB_MODE: u1, - padding: u23, - }), - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// Firewall disable - FWDIS: u1, - reserved8: u7, - /// I/O analog switch voltage booster enable - BOOSTEN: u1, - reserved16: u7, - /// Fast-mode Plus (Fm+) driving capability activation on PB6 - I2C_PB6_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB7 - I2C_PB7_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB8 - I2C_PB8_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB9 - I2C_PB9_FMP: u1, - /// I2C1 Fast-mode Plus driving capability activation - I2C1_FMP: u1, - /// I2C2 Fast-mode Plus driving capability activation - I2C2_FMP: u1, - /// I2C3 Fast-mode Plus driving capability activation - I2C3_FMP: u1, - reserved26: u3, - /// Floating Point Unit interrupts enable bits - FPU_IE: u6, + pub const aes_v3b = struct { + pub const CHMOD = enum(u3) { + /// Electronic codebook + ECB = 0x0, + /// Cipher-block chaining + CBC = 0x1, + /// Counter mode + CTR = 0x2, + /// Galois counter mode and Galois message authentication code + GCM_GMAC = 0x3, + /// Counter with CBC-MAC + CCM = 0x4, + _, + }; + + pub const DATATYPE = enum(u2) { + /// Word + None = 0x0, + /// Half-word (16-bit) + HalfWord = 0x1, + /// Byte (8-bit) + Byte = 0x2, + /// Bit + Bit = 0x3, + }; + + pub const GCMPH = enum(u2) { + /// Init phase + @"Init phase" = 0x0, + /// Header phase + @"Header phase" = 0x1, + /// Payload phase + @"Payload phase" = 0x2, + /// Final phase + @"Final phase" = 0x3, + }; + + pub const MODE = enum(u2) { + /// Encryption + Mode1 = 0x0, + /// Key derivation (or key preparation for ECB/CBC decryption) + Mode2 = 0x1, + /// Decryption + Mode3 = 0x2, + _, + }; + + /// Advanced encryption standard hardware accelerator + pub const AES = extern struct { + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// AES enable + EN: u1, + /// Data type selection + DATATYPE: packed union { + raw: u2, + value: DATATYPE, + }, + /// Operating mode + MODE: packed union { + raw: u2, + value: MODE, + }, + padding: u27, }), - /// external interrupt configuration register 1 - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI12 configuration bits - EXTI: u4, - padding: u28, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Computation complete flag + CCF: u1, + /// Read error flag + RDERR: u1, + /// Write error flag + WRERR: u1, + /// Busy flag + BUSY: u1, + reserved7: u3, + /// Key valid flag + KEYVALID: u1, + padding: u24, }), - /// SCSR - SCSR: mmio.Mmio(packed struct(u32) { - /// SRAM2 Erase - SRAM2ER: u1, - /// SRAM2 busy by erase operation - SRAM2BSY: u1, - padding: u30, + /// Data input register + DINR: u32, + /// Data output register + DOUTR: u32, + /// Key register + KEYR: u32, + reserved32: [12]u8, + /// Initialization vector register + IVR: [4]u32, + reserved64: [16]u8, + /// Suspend register + SUSPR: [8]u32, + reserved768: [672]u8, + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// Computation complete flag interrupt enable + CCFIE: u1, + /// Read or write error interrupt enable + RWEIE: u1, + /// Key error interrupt enable + KEIE: u1, + padding: u29, }), - /// CFGR2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// Cortex LOCKUP (Hardfault) output enable bit - CLL: u1, - /// SRAM2 parity lock bit - SPL: u1, - /// PVD lock enable bit - PVDL: u1, - /// ECC Lock - ECCL: u1, - reserved8: u4, - /// SRAM2 parity error flag - SPF: u1, - padding: u23, + /// interrupt status register + ISR: mmio.Mmio(packed struct(u32) { + /// Computation complete flag + CCF: u1, + /// Read or write error interrupt flag + RWEIF: u1, + /// Key error interrupt flag + KEIF: u1, + padding: u29, }), - /// SWPR - SWPR: mmio.Mmio(packed struct(u32) { - /// SRAWM2 write protection. - PWP: u1, - padding: u31, + /// interrupt clear register + ICR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Read or write error interrupt flag clear + RWEIF: u1, + /// Key error interrupt flag clear + KEIF: u1, + padding: u29, }), - /// SKR - SKR: mmio.Mmio(packed struct(u32) { - /// SRAM2 write protection key for software erase - KEY: u8, + }; + }; + + pub const afio_f1 = struct { + /// Alternate function I/O + pub const AFIO = extern struct { + /// Event Control Register (AFIO_EVCR) + EVCR: mmio.Mmio(packed struct(u32) { + /// Pin selection + PIN: u4, + /// Port selection + PORT: u3, + /// Event Output Enable + EVOE: u1, padding: u24, }), + /// AF remap and debug I/O configuration register (AFIO_MAPR) + MAPR: mmio.Mmio(packed struct(u32) { + /// SPI1 remapping + SPI1_REMAP: u1, + /// I2C1 remapping + I2C1_REMAP: u1, + /// USART1 remapping + USART1_REMAP: u1, + /// USART2 remapping + USART2_REMAP: u1, + /// USART3 remapping + USART3_REMAP: u2, + /// TIM1 remapping + TIM1_REMAP: u2, + /// TIM2 remapping + TIM2_REMAP: u2, + /// TIM3 remapping + TIM3_REMAP: u2, + /// TIM4 remapping + TIM4_REMAP: u1, + /// CAN1 remapping + CAN1_REMAP: u2, + /// Port D0/Port D1 mapping on OSCIN/OSCOUT + PD01_REMAP: u1, + /// Set and cleared by software + TIM5CH4_IREMAP: u1, + /// ADC 1 External trigger injected conversion remapping + ADC1_ETRGINJ_REMAP: u1, + /// ADC 1 external trigger regular conversion remapping + ADC1_ETRGREG_REMAP: u1, + /// ADC 2 external trigger injected conversion remapping + ADC2_ETRGINJ_REMAP: u1, + /// ADC 2 external trigger regular conversion remapping + ADC2_ETRGREG_REMAP: u1, + /// Ethernet MAC I/O remapping + ETH_REMAP: u1, + /// CAN2 I/O remapping + CAN2_REMAP: u1, + /// MII or RMII selection + MII_RMII_SEL: u1, + /// Serial wire JTAG configuration + SWJ_CFG: u3, + reserved28: u1, + /// SPI3/I2S3 remapping + SPI3_REMAP: u1, + /// TIM2 internal trigger 1 remapping + TIM2ITR1_IREMAP: u1, + /// Ethernet PTP PPS remapping + PTP_PPS_REMAP: u1, + padding: u1, + }), + /// External interrupt configuration register 1 (AFIO_EXTICR1) + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI12 configuration + EXTI: u4, + padding: u28, + }), + reserved28: [4]u8, + /// AF remap and debug I/O configuration register + MAPR2: mmio.Mmio(packed struct(u32) { + /// TIM15 remapping + TIM15_REMAP: u1, + /// TIM16 remapping + TIM16_REMAP: u1, + /// TIM17 remapping + TIM17_REMAP: u1, + /// CEC remapping + CEC_REMAP: u1, + /// TIM1 DMA remapping + TIM1_DMA_REMAP: u1, + /// TIM9 remapping + TIM9_REMAP: u1, + /// TIM10 remapping + TIM10_REMAP: u1, + /// TIM11 remapping + TIM11_REMAP: u1, + /// TIM13 remapping + TIM13_REMAP: u1, + /// TIM14 remapping + TIM14_REMAP: u1, + /// NADV connect/disconnect + FSMC_NADV: u1, + /// TIM67_DAC DMA remapping + TIM67_DAC_DMA_REMAP: u1, + /// TIM12 remapping + TIM12_REMAP: u1, + /// Miscellaneous features remapping + MISC_REMAP: u1, + padding: u18, + }), }; }; - pub const rcc_l0_v2 = struct { - pub const CLK48SEL = enum(u1) { - /// PLL VCO divided by 2 selected - PLL1_VCO_DIV_2 = 0x0, - /// HSI48 clock selected - HSI48 = 0x1, + pub const bdma_v1 = struct { + pub const DIR = enum(u1) { + /// Read from peripheral + FromPeripheral = 0x0, + /// Read from memory + FromMemory = 0x1, }; - pub const HPRE = enum(u4) { - /// system clock not divided - Div1 = 0x0, - /// system clock divided by 2 - Div2 = 0x8, - /// system clock divided by 4 - Div4 = 0x9, - /// system clock divided by 8 - Div8 = 0xa, - /// system clock divided by 16 - Div16 = 0xb, - /// system clock divided by 64 - Div64 = 0xc, - /// system clock divided by 128 - Div128 = 0xd, - /// system clock divided by 256 - Div256 = 0xe, - /// system clock divided by 512 - Div512 = 0xf, - _, + pub const PL = enum(u2) { + /// Low priority + Low = 0x0, + /// Medium priority + Medium = 0x1, + /// High priority + High = 0x2, + /// Very high priority + VeryHigh = 0x3, }; - pub const I2CSEL = enum(u2) { - /// APB clock selected as peripheral clock - PCLK1 = 0x0, - /// System clock selected as peripheral clock - SYS = 0x1, - /// HSI clock selected as peripheral clock - HSI = 0x2, + pub const SIZE = enum(u2) { + /// 8-bit size + Bits8 = 0x0, + /// 16-bit size + Bits16 = 0x1, + /// 32-bit size + Bits32 = 0x2, _, }; - pub const LPTIMSEL = enum(u2) { - /// APB clock selected as Timer clock - PCLK1 = 0x0, - /// LSI clock selected as Timer clock - LSI = 0x1, - /// HSI clock selected as Timer clock - HSI = 0x2, - /// LSE clock selected as Timer clock - LSE = 0x3, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, + /// Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers + pub const CH = extern struct { + /// DMA channel configuration register (DMA_CCR) + CR: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: packed union { + raw: u1, + value: DIR, + }, + /// Circular mode enabled + CIRC: u1, + /// Peripheral increment mode enabled + PINC: u1, + /// Memory increment mode enabled + MINC: u1, + /// Peripheral size + PSIZE: packed union { + raw: u2, + value: SIZE, + }, + /// Memory size + MSIZE: packed union { + raw: u2, + value: SIZE, + }, + /// Channel Priority level + PL: packed union { + raw: u2, + value: PL, + }, + /// Memory to memory mode enabled + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 1 number of data register + NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 1 peripheral address register + PAR: u32, + /// DMA channel 1 memory address register + MAR: u32, }; - pub const MCOPRE = enum(u3) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x1, - /// Division by 4 - Div4 = 0x2, - /// Division by 8 - Div8 = 0x3, - /// Division by 16 - Div16 = 0x4, - _, + /// DMA controller + pub const DMA = extern struct { + /// DMA interrupt status register (DMA_ISR) + ISR: mmio.Mmio(packed struct(u32) { + /// Channel 1 Global interrupt flag + GIF: u1, + /// Channel 1 Transfer Complete flag + TCIF: u1, + /// Channel 1 Half Transfer Complete flag + HTIF: u1, + /// Channel 1 Transfer Error flag + TEIF: u1, + padding: u28, + }), + /// DMA interrupt flag clear register (DMA_IFCR) + IFCR: mmio.Mmio(packed struct(u32) { + /// Channel 1 Global interrupt flag + GIF: u1, + /// Channel 1 Transfer Complete flag + TCIF: u1, + /// Channel 1 Half Transfer Complete flag + HTIF: u1, + /// Channel 1 Transfer Error flag + TEIF: u1, + padding: u28, + }), + /// Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers + CH: u32, }; + }; - pub const MCOSEL = enum(u4) { - /// No clock - DISABLE = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI oscillator clock selected - HSI = 0x2, - /// MSI oscillator clock selected - MSI = 0x3, - /// HSE oscillator clock selected - HSE = 0x4, - /// PLL clock selected - PLL = 0x5, - /// LSI oscillator clock selected - LSI = 0x6, - /// LSE oscillator clock selected - LSE = 0x7, - _, + pub const bdma_v2 = struct { + pub const DIR = enum(u1) { + /// Read from peripheral + FromPeripheral = 0x0, + /// Read from memory + FromMemory = 0x1, }; - pub const MSIRANGE = enum(u3) { - /// range 0 around 65.536 kHz - Range66K = 0x0, - /// range 1 around 131.072 kHz - Range131K = 0x1, - /// range 2 around 262.144 kHz - Range262K = 0x2, - /// range 3 around 524.288 kHz - Range524K = 0x3, - /// range 4 around 1.048 MHz - Range1M = 0x4, - /// range 5 around 2.097 MHz (reset value) - Range2M = 0x5, - /// range 6 around 4.194 MHz - Range4M = 0x6, - _, + pub const PL = enum(u2) { + /// Low priority + Low = 0x0, + /// Medium priority + Medium = 0x1, + /// High priority + High = 0x2, + /// Very high priority + VeryHigh = 0x3, }; - pub const PLLDIV = enum(u2) { - /// PLLVCO / 2 - Div2 = 0x1, - /// PLLVCO / 3 - Div3 = 0x2, - /// PLLVCO / 4 - Div4 = 0x3, + pub const SIZE = enum(u2) { + /// 8-bit size + Bits8 = 0x0, + /// 16-bit size + Bits16 = 0x1, + /// 32-bit size + Bits32 = 0x2, _, }; - pub const PLLMUL = enum(u4) { - /// PLL clock entry x 3 - Mul3 = 0x0, - /// PLL clock entry x 4 - Mul4 = 0x1, - /// PLL clock entry x 6 - Mul6 = 0x2, - /// PLL clock entry x 8 - Mul8 = 0x3, - /// PLL clock entry x 12 - Mul12 = 0x4, - /// PLL clock entry x 16 - Mul16 = 0x5, - /// PLL clock entry x 24 - Mul24 = 0x6, - /// PLL clock entry x 32 - Mul32 = 0x7, - /// PLL clock entry x 48 - Mul48 = 0x8, - _, + /// Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers + pub const CH = extern struct { + /// DMA channel configuration register (DMA_CCR) + CR: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: packed union { + raw: u1, + value: DIR, + }, + /// Circular mode enabled + CIRC: u1, + /// Peripheral increment mode enabled + PINC: u1, + /// Memory increment mode enabled + MINC: u1, + /// Peripheral size + PSIZE: packed union { + raw: u2, + value: SIZE, + }, + /// Memory size + MSIZE: packed union { + raw: u2, + value: SIZE, + }, + /// Channel Priority level + PL: packed union { + raw: u2, + value: PL, + }, + /// Memory to memory mode enabled + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 1 number of data register + NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 1 peripheral address register + PAR: u32, + /// DMA channel 1 memory address register + MAR: u32, }; - pub const PLLSRC = enum(u1) { - /// HSI selected as PLL input clock - HSI = 0x0, - /// HSE selected as PLL input clock - HSE = 0x1, + /// DMA controller + pub const DMA = extern struct { + /// DMA interrupt status register (DMA_ISR) + ISR: mmio.Mmio(packed struct(u32) { + /// Channel 1 Global interrupt flag + GIF: u1, + /// Channel 1 Transfer Complete flag + TCIF: u1, + /// Channel 1 Half Transfer Complete flag + HTIF: u1, + /// Channel 1 Transfer Error flag + TEIF: u1, + padding: u28, + }), + /// DMA interrupt flag clear register (DMA_IFCR) + IFCR: mmio.Mmio(packed struct(u32) { + /// Channel 1 Global interrupt flag + GIF: u1, + /// Channel 1 Transfer Complete flag + TCIF: u1, + /// Channel 1 Half Transfer Complete flag + HTIF: u1, + /// Channel 1 Transfer Error flag + TEIF: u1, + padding: u28, + }), + /// Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers + CH: u32, + reserved168: [156]u8, + /// channel selection register + CSELR: mmio.Mmio(packed struct(u32) { + /// DMA channel selection + CS: u4, + padding: u28, + }), }; + }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, + pub const bkp_v1 = struct { + pub const ASOS = enum(u1) { + /// RTC Alarm pulse output selected + Alarm = 0x0, + /// RTC Second pulse output selected + Second = 0x1, }; - pub const RTCPRE = enum(u2) { - /// HSE divided by 2 - Div2 = 0x0, - /// HSE divided by 4 - Div4 = 0x1, - /// HSE divided by 8 - Div8 = 0x2, - /// HSE divided by 16 - Div16 = 0x3, + pub const TPAL = enum(u1) { + /// A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) + High = 0x0, + /// A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) + Low = 0x1, }; - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock - HSE = 0x3, + /// Backup registers + pub const BKP = extern struct { + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Backup data + D: u16, + padding: u16, + }), + reserved44: [40]u8, + /// RTC clock calibration register + RTCCR: mmio.Mmio(packed struct(u32) { + /// Calibration value + CAL: u7, + /// Calibration Clock Output + CCO: u1, + /// Alarm or second output enable + ASOE: u1, + /// Alarm or second output selection + ASOS: packed union { + raw: u1, + value: ASOS, + }, + padding: u22, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Tamper pin enable + TPE: u1, + /// Tamper pin active level + TPAL: packed union { + raw: u1, + value: TPAL, + }, + padding: u30, + }), + /// Control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// Clear Tamper event + CTE: u1, + /// Clear Tamper Interrupt + CTI: u1, + /// Tamper Pin interrupt enable + TPIE: u1, + reserved8: u5, + /// Tamper Event Flag + TEF: u1, + /// Tamper Interrupt Flag + TIF: u1, + padding: u22, + }), }; + }; - pub const STOPWUCK = enum(u1) { - /// Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock - MSI = 0x0, - /// Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI/4 if HSIDIVEN=1) - HSI = 0x1, + pub const can_bxcan = struct { + pub const IDE = enum(u1) { + /// Standard identifier + Standard = 0x0, + /// Extended identifier + Extended = 0x1, }; - pub const SW = enum(u2) { - /// MSI oscillator used as system clock - MSI = 0x0, - /// HSI oscillator used as system clock - HSI = 0x1, - /// HSE oscillator used as system clock - HSE = 0x2, - /// PLL used as system clock - PLL1_R = 0x3, + pub const LEC = enum(u3) { + /// No Error + NoError = 0x0, + /// Stuff Error + Stuff = 0x1, + /// Form Error + Form = 0x2, + /// Acknowledgment Error + Ack = 0x3, + /// Bit recessive Error + BitRecessive = 0x4, + /// Bit dominant Error + BitDominant = 0x5, + /// CRC Error + Crc = 0x6, + /// Set by software + Custom = 0x7, }; - pub const UARTSEL = enum(u2) { - /// APB clock selected as peripheral clock - PCLK1 = 0x0, - /// System clock selected as peripheral clock - SYS = 0x1, - /// HSI clock selected as peripheral clock - HSI = 0x2, - /// LSE clock selected as peripheral clock - LSE = 0x3, + pub const RTR = enum(u1) { + /// Data frame + Data = 0x0, + /// Remote frame + Remote = 0x1, }; - pub const USART1SEL = enum(u2) { - /// APB clock selected as peripheral clock - PCLK2 = 0x0, - /// System clock selected as peripheral clock - SYS = 0x1, - /// HSI clock selected as peripheral clock - HSI = 0x2, - /// LSE clock selected as peripheral clock - LSE = 0x3, + pub const SILM = enum(u1) { + /// Normal operation + Normal = 0x0, + /// Silent Mode + Silent = 0x1, }; - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// 16 MHz high-speed internal clock enable - HSION: u1, - /// High-speed internal clock enable bit for some IP kernels - HSIKERON: u1, - /// Internal high-speed clock ready flag - HSIRDY: u1, - /// HSIDIVEN - HSIDIVEN: u1, - /// HSIDIVF - HSIDIVF: u1, - /// 16 MHz high-speed internal clock output enable - HSIOUTEN: u1, - reserved8: u2, - /// MSI clock enable - MSION: u1, - /// MSI clock ready flag - MSIRDY: u1, - reserved16: u6, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE clock bypass - HSEBYP: u1, - /// Clock security system on HSE enable - CSSHSEON: u1, - /// TC/LCD prescaler - RTCPRE: packed union { - raw: u2, - value: RTCPRE, - }, - reserved24: u2, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding: u6, + /// Controller area network + pub const CAN = extern struct { + /// master control register + MCR: mmio.Mmio(packed struct(u32) { + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved15: u7, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding: u15, }), - /// Internal clock sources calibration register - ICSCR: mmio.Mmio(packed struct(u32) { - /// nternal high speed clock calibration - HSICAL: u8, - /// High speed internal clock trimming - HSITRIM: u5, - /// MSI clock ranges - MSIRANGE: packed union { - raw: u3, - value: MSIRANGE, - }, - /// MSI clock calibration - MSICAL: u8, - /// MSI clock trimming - MSITRIM: u8, + /// master status register + MSR: mmio.Mmio(packed struct(u32) { + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved8: u3, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding: u20, }), - /// Clock recovery RC register - CRRCR: mmio.Mmio(packed struct(u32) { - /// 48MHz HSI clock enable - HSI48ON: u1, - /// 48MHz HSI clock ready flag - HSI48RDY: u1, - /// 48 MHz HSI clock divided by 6 output enable - HSI48DIV6EN: u1, - reserved8: u5, - /// 48 MHz HSI clock calibration - HSI48CAL: u8, - padding: u16, + /// transmit status register + TSR: mmio.Mmio(packed struct(u32) { + /// RQCP0 + RQCP: u1, + /// TXOK0 + TXOK: u1, + /// ALST0 + ALST: u1, + /// TERR0 + TERR: u1, + reserved7: u3, + /// ABRQ0 + ABRQ: u1, + reserved24: u16, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox 0 + TME: u1, + reserved29: u2, + /// Lowest priority flag for mailbox 0 + LOW: u1, + padding: u2, }), - /// Clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u2, - value: SW, - }, - /// System clock switch status - SWS: packed union { - raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// APB low-speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, - }, - /// APB high-speed prescaler (APB2) - PPRE2: packed union { + /// receive FIFO 0 register + RFR: [2]mmio.Mmio(packed struct(u32) { + /// FMP0 + FMP: u2, + reserved3: u1, + /// FULL0 + FULL: u1, + /// FOVR0 + FOVR: u1, + /// RFOM0 + RFOM: u1, + padding: u26, + }), + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE: u1, + /// FFIE0 + FFIE: u1, + /// FOVIE0 + FOVIE: u1, + reserved8: u4, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved15: u3, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding: u14, + }), + /// error status register + ESR: mmio.Mmio(packed struct(u32) { + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved4: u1, + /// LEC + LEC: packed union { raw: u3, - value: PPRE, - }, - reserved15: u1, - /// Wake-up from stop clock selection - STOPWUCK: packed union { - raw: u1, - value: STOPWUCK, - }, - /// PLL entry clock source - PLLSRC: packed union { - raw: u1, - value: PLLSRC, + value: LEC, }, - reserved18: u1, - /// PLL multiplication factor - PLLMUL: packed union { - raw: u4, - value: PLLMUL, - }, - /// PLL output division - PLLDIV: packed union { - raw: u2, - value: PLLDIV, - }, - /// Microcontroller clock output selection - MCOSEL: packed union { - raw: u4, - value: MCOSEL, - }, - /// Microcontroller clock output prescaler - MCOPRE: packed union { - raw: u3, - value: MCOPRE, - }, - padding: u1, - }), - /// Clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYIE: u1, - /// LSE ready interrupt flag - LSERDYIE: u1, - /// HSI ready interrupt flag - HSIRDYIE: u1, - /// HSE ready interrupt flag - HSERDYIE: u1, - /// PLL ready interrupt flag - PLLRDYIE: u1, - /// MSI ready interrupt flag - MSIRDYIE: u1, - /// HSI48 ready interrupt flag - HSI48RDYIE: u1, - /// LSE CSS interrupt flag - CSSLSE: u1, - padding: u24, - }), - /// Clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// PLL ready interrupt flag - PLLRDYF: u1, - /// MSI ready interrupt flag - MSIRDYF: u1, - /// HSI48 ready interrupt flag - HSI48RDYF: u1, - /// LSE Clock Security System Interrupt flag - CSSLSEF: u1, - /// Clock Security System Interrupt flag - CSSHSEF: u1, - padding: u23, - }), - /// Clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready Interrupt clear - LSIRDYC: u1, - /// LSE ready Interrupt clear - LSERDYC: u1, - /// HSI ready Interrupt clear - HSIRDYC: u1, - /// HSE ready Interrupt clear - HSERDYC: u1, - /// PLL ready Interrupt clear - PLLRDYC: u1, - /// MSI ready Interrupt clear - MSIRDYC: u1, - /// HSI48 ready Interrupt clear - HSI48RDYC: u1, - /// LSE Clock Security System Interrupt clear - CSSLSEC: u1, - /// Clock Security System Interrupt clear - CSSHSEC: u1, - padding: u23, + reserved16: u9, + /// TEC + TEC: u8, + /// REC + REC: u8, }), - /// GPIO reset register - GPIORSTR: mmio.Mmio(packed struct(u32) { - /// I/O port A reset - GPIOARST: u1, - /// I/O port B reset - GPIOBRST: u1, - /// I/O port A reset - GPIOCRST: u1, - /// I/O port D reset - GPIODRST: u1, - /// I/O port E reset - GPIOERST: u1, - reserved7: u2, - /// I/O port H reset - GPIOHRST: u1, - padding: u24, + /// bit timing register + BTR: mmio.Mmio(packed struct(u32) { + /// BRP + BRP: u10, + reserved16: u6, + /// TS1 + TS: u4, + reserved24: u4, + /// SJW + SJW: u2, + reserved30: u4, + /// Loop Back Mode enabled + LBKM: u1, + /// SILM + SILM: packed union { + raw: u1, + value: SILM, + }, }), - /// AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - /// DMA reset - DMA1RST: u1, + reserved384: [352]u8, + /// CAN Transmit cluster + TX: u32, + reserved432: [44]u8, + /// CAN Receive cluster + RX: u32, + reserved512: [76]u8, + /// filter master register + FMR: mmio.Mmio(packed struct(u32) { + /// FINIT + FINIT: u1, reserved8: u7, - /// Memory interface reset - MIFRST: u1, - reserved12: u3, - /// Test integration module reset - CRCRST: u1, - reserved16: u3, - /// Touch Sensing reset - TSCRST: u1, - reserved20: u3, - /// Random Number Generator module reset - RNGRST: u1, - reserved24: u3, - /// Crypto module reset - CRYPRST: u1, - padding: u7, + /// CAN2SB + CAN2SB: u6, + padding: u18, }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// System configuration controller reset - SYSCFGRST: u1, - reserved2: u1, - /// TIM21 timer reset - TIM21RST: u1, - reserved5: u2, - /// TIM22 timer reset - TIM22RST: u1, - reserved9: u3, - /// ADC interface reset - ADCRST: u1, - reserved12: u2, - /// SPI 1 reset - SPI1RST: u1, - reserved14: u1, - /// USART1 reset - USART1RST: u1, - reserved22: u7, - /// DBG reset - DBGRST: u1, - padding: u9, + /// filter mode register + FM1R: mmio.Mmio(packed struct(u32) { + /// Filter mode + FBM: u1, + padding: u31, }), - /// APB1 peripheral reset register - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - reserved4: u2, - /// Timer 6 reset - TIM6RST: u1, - /// Timer 7 reset - TIM7RST: u1, - reserved11: u5, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI2 reset - SPI2RST: u1, - reserved17: u2, - /// USART2 reset - USART2RST: u1, - /// LPUART1 reset - LPUART1RST: u1, - /// USART4 reset - USART4RST: u1, - /// USART5 reset - USART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// USB reset - USBRST: u1, - reserved27: u3, - /// Clock recovery system reset - CRSRST: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - /// I2C3 reset - I2C3RST: u1, - /// Low power timer reset - LPTIM1RST: u1, + reserved524: [4]u8, + /// filter scale register + FS1R: mmio.Mmio(packed struct(u32) { + /// Filter scale configuration + FSC: u1, + padding: u31, }), - /// GPIO clock enable register - GPIOENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port A clock enable - GPIOCEN: u1, - /// I/O port D clock enable - GPIODEN: u1, - /// IO port E clock enable - GPIOEEN: u1, - reserved7: u2, - /// I/O port H clock enable - GPIOHEN: u1, - padding: u24, + reserved532: [4]u8, + /// filter FIFO assignment register + FFA1R: mmio.Mmio(packed struct(u32) { + /// Filter FIFO assignment for filter 0 + FFA: u1, + padding: u31, }), - /// AHB peripheral clock enable register - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA clock enable - DMA1EN: u1, - reserved8: u7, - /// NVM interface clock enable - MIFEN: u1, - reserved12: u3, - /// CRC clock enable - CRCEN: u1, - reserved16: u3, - /// Touch Sensing clock enable - TSCEN: u1, - reserved20: u3, - /// Random Number Generator clock enable - RNGEN: u1, - reserved24: u3, - /// Crypto clock enable - CRYPEN: u1, - padding: u7, + reserved540: [4]u8, + /// filter activation register + FA1R: mmio.Mmio(packed struct(u32) { + /// Filter active + FACT: u1, + padding: u31, }), - /// APB2 peripheral clock enable register - APB2ENR: mmio.Mmio(packed struct(u32) { - /// System configuration controller clock enable - SYSCFGEN: u1, - reserved2: u1, - /// TIM21 timer clock enable - TIM21EN: u1, - reserved5: u2, - /// TIM22 timer clock enable - TIM22EN: u1, - reserved7: u1, - /// Firewall clock enable - FWEN: u1, - reserved9: u1, - /// ADC clock enable - ADCEN: u1, - reserved12: u2, - /// SPI1 clock enable - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable - USART1EN: u1, - reserved22: u7, - /// DBG clock enable - DBGEN: u1, - padding: u9, + reserved576: [32]u8, + /// CAN Filter Bank cluster + FB: u32, + }; + + /// CAN Filter Bank cluster + pub const FB = extern struct { + /// Filter bank 0 register 1 + FR1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB: u1, + padding: u31, }), - /// APB1 peripheral clock enable register - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer2 clock enable - TIM2EN: u1, - /// Timer 3 clock enbale - TIM3EN: u1, - reserved4: u2, - /// Timer 6 clock enable - TIM6EN: u1, - /// Timer 7 clock enable - TIM7EN: u1, - reserved11: u5, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI2 clock enable - SPI2EN: u1, - reserved17: u2, - /// UART2 clock enable - USART2EN: u1, - /// LPUART1 clock enable - LPUART1EN: u1, - /// USART4 clock enable - USART4EN: u1, - /// USART5 clock enable - USART5EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - /// I2C2 clock enable - I2C2EN: u1, - /// USB clock enable - USBEN: u1, - reserved27: u3, - /// Clock recovery system clock enable - CRSEN: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - /// I2C3 clock enable - I2C3EN: u1, - /// Low power timer clock enable - LPTIM1EN: u1, + /// Filter bank 0 register 2 + FR2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB: u1, + padding: u31, }), - /// GPIO clock enable in sleep mode register - GPIOSMEN: mmio.Mmio(packed struct(u32) { - /// Port A clock enable during Sleep mode - GPIOASMEN: u1, - /// Port B clock enable during Sleep mode - GPIOBSMEN: u1, - /// Port C clock enable during Sleep mode - GPIOCSMEN: u1, - /// Port D clock enable during Sleep mode - GPIODSMEN: u1, - /// Port E clock enable during Sleep mode - GPIOESMEN: u1, - reserved7: u2, - /// Port H clock enable during Sleep mode - GPIOHSMEN: u1, - padding: u24, + }; + + /// CAN Receive cluster + pub const RX = extern struct { + /// receive FIFO mailbox identifier register + RIR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// RTR + RTR: packed union { + raw: u1, + value: RTR, + }, + /// IDE + IDE: packed union { + raw: u1, + value: IDE, + }, + /// EXID + EXID: u18, + /// STID + STID: u11, }), - /// AHB peripheral clock enable in sleep mode register - AHBSMENR: mmio.Mmio(packed struct(u32) { - /// DMA clock enable during sleep mode - DMA1SMEN: u1, - reserved8: u7, - /// NVM interface clock enable during sleep mode - MIFSMEN: u1, - /// SRAM interface clock enable during sleep mode - SRAMSMEN: u1, - reserved12: u2, - /// CRC clock enable during sleep mode - CRCSMEN: u1, - reserved16: u3, - /// Touch Sensing clock enable during sleep mode - TSCSMEN: u1, - reserved20: u3, - /// Random Number Generator clock enable during sleep mode - RNGSMEN: u1, - reserved24: u3, - /// Crypto clock enable during sleep mode - CRYPSMEN: u1, - padding: u7, + /// mailbox data high register + RDTR: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// FMI + FMI: u8, + /// TIME + TIME: u16, }), - /// APB2 peripheral clock enable in sleep mode register - APB2SMENR: mmio.Mmio(packed struct(u32) { - /// System configuration controller clock enable during sleep mode - SYSCFGSMEN: u1, - reserved2: u1, - /// TIM21 timer clock enable during sleep mode - TIM21SMEN: u1, - reserved5: u2, - /// TIM22 timer clock enable during sleep mode - TIM22SMEN: u1, - reserved9: u3, - /// ADC clock enable during sleep mode - ADCSMEN: u1, - reserved12: u2, - /// SPI1 clock enable during sleep mode - SPI1SMEN: u1, - reserved14: u1, - /// USART1 clock enable during sleep mode - USART1SMEN: u1, - reserved22: u7, - /// DBG clock enable during sleep mode - DBGSMEN: u1, - padding: u9, + /// mailbox data high register + RDLR: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA: u8, + padding: u24, }), - /// APB1 peripheral clock enable in sleep mode register - APB1SMENR: mmio.Mmio(packed struct(u32) { - /// Timer2 clock enable during sleep mode - TIM2SMEN: u1, - /// Timer 3 clock enable during sleep mode - TIM3SMEN: u1, - reserved4: u2, - /// Timer 6 clock enable during sleep mode - TIM6SMEN: u1, - /// Timer 7 clock enable during sleep mode - TIM7SMEN: u1, - reserved11: u5, - /// Window watchdog clock enable during sleep mode - WWDGSMEN: u1, - reserved14: u2, - /// SPI2 clock enable during sleep mode - SPI2SMEN: u1, - reserved17: u2, - /// UART2 clock enable during sleep mode - USART2SMEN: u1, - /// LPUART1 clock enable during sleep mode - LPUART1SMEN: u1, - /// USART4 clock enabe during sleep mode - USART4SMEN: u1, - /// USART5 clock enable during sleep mode - USART5SMEN: u1, - /// I2C1 clock enable during sleep mode - I2C1SMEN: u1, - /// I2C2 clock enable during sleep mode - I2C2SMEN: u1, - /// USB clock enable during sleep mode - USBSMEN: u1, - reserved27: u3, - /// Clock recovery system clock enable during sleep mode - CRSSMEN: u1, - /// Power interface clock enable during sleep mode - PWRSMEN: u1, - /// DAC interface clock enable during sleep mode - DACSMEN: u1, - /// I2C3 clock enable during sleep mode - I2C3SMEN: u1, - /// Low power timer clock enable during sleep mode - LPTIM1SMEN: u1, + /// receive FIFO mailbox data high register + RDHR: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA: u8, + padding: u24, }), - /// Clock configuration register - CCIPR: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SEL: packed union { - raw: u2, - value: USART1SEL, - }, - /// USART2 clock source selection - USART2SEL: packed union { - raw: u2, - value: UARTSEL, - }, - reserved10: u6, - /// LPUART1 clock source selection - LPUART1SEL: packed union { - raw: u2, - value: UARTSEL, - }, - /// I2C1 clock source selection - I2C1SEL: packed union { - raw: u2, - value: I2CSEL, - }, - reserved16: u2, - /// I2C3 clock source selection - I2C3SEL: packed union { - raw: u2, - value: I2CSEL, - }, - /// Low Power Timer clock source selection - LPTIM1SEL: packed union { - raw: u2, - value: LPTIMSEL, + }; + + /// CAN Transmit cluster + pub const TX = extern struct { + /// TX mailbox identifier register + TIR: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: packed union { + raw: u1, + value: RTR, }, - reserved26: u6, - /// 48 MHz clock source selection - CLK48SEL: packed union { + /// IDE + IDE: packed union { raw: u1, - value: CLK48SEL, + value: IDE, }, - padding: u5, + /// EXID + EXID: u18, + /// STID + STID: u11, }), - /// Control and status register - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low-speed oscillator enable - LSION: u1, - /// Internal low-speed oscillator ready - LSIRDY: u1, - reserved8: u6, - /// External low-speed oscillator enable - LSEON: u1, - /// External low-speed oscillator ready - LSERDY: u1, - /// External low-speed oscillator bypass - LSEBYP: u1, - /// LSEDRV - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// CSSLSEON - CSSLSEON: u1, - /// CSS on LSE failure detection flag - CSSLSED: u1, - reserved16: u1, - /// RTC and LCD clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - /// RTC clock enable - RTCEN: u1, - /// RTC software reset - RTCRST: u1, - reserved23: u3, - /// Remove reset flag - RMVF: u1, - /// Firewall reset flag - FWRSTF: u1, - /// OBLRSTF - OBLRSTF: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// mailbox data length control and time stamp register + TDTR: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// mailbox data low register + TDLR: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA: u8, + padding: u24, + }), + /// mailbox data high register + TDHR: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA: u8, + padding: u24, }), }; }; - pub const comp_f3_v1 = struct { - pub const HYST = enum(u2) { - None = 0x0, - /// Low hysteresis - Low = 0x1, - /// Medium hysteresis - Medium = 0x2, - /// High hysteresis - High = 0x3, - }; - - pub const MODE = enum(u2) { - /// High Speed mode - HighSpeed = 0x0, - /// Medium Speed mode - MediumSpeed = 0x1, - /// Low Speed mode - LowSpeed = 0x2, - /// Very Low Speed mode - VeryLowSpeed = 0x3, + pub const can_fdcan_h7 = struct { + pub const TFQM = enum(u1) { + /// Tx FIFO operation + FIFO = 0x0, + /// Tx queue operation + QUEUE = 0x1, }; - /// General purpose comparators. - pub const COMP = extern struct { - /// control and status register. - CSR: mmio.Mmio(packed struct(u32) { - /// Comparator enable. - EN: u1, - /// Comparator 1 non inverting input connection to DAC output. Only available on COMP1 - INP_DAC: u1, - /// Comparator mode. - MODE: packed union { - raw: u2, - value: MODE, - }, - /// Comparator inverting input selection. - INSEL: u3, - /// Window mode enable. Only available on COMP2 - WNDWEN: u1, - /// Comparator output selection. - OUTSEL: u3, - /// Comparator output polarity. - POL: u1, - /// Comparator hysteresis. - HYST: packed union { - raw: u2, - value: HYST, - }, - /// Comparator output. - OUT: u1, - /// Comparator lock. - LOCK: u1, + /// Controller area network with flexible data rate (FD) + pub const FDCAN = extern struct { + /// FDCAN Core Release Register + CREL: mmio.Mmio(packed struct(u32) { + /// Timestamp Day + DAY: u8, + /// Timestamp Month + MON: u8, + /// Timestamp Year + YEAR: u4, + /// Sub-step of Core release + SUBSTEP: u4, + /// Step of Core release + STEP: u4, + /// Core release + REL: u4, + }), + /// FDCAN Core Release Register + ENDN: mmio.Mmio(packed struct(u32) { + /// Endiannes Test Value + ETV: u32, + }), + reserved12: [4]u8, + /// FDCAN Data Bit Timing and Prescaler Register + DBTP: mmio.Mmio(packed struct(u32) { + /// Synchronization Jump Width + DSJW: u4, + /// Data time segment after sample point + DTSEG2: u4, + /// Data time segment after sample point + DTSEG1: u5, + reserved16: u3, + /// Data BIt Rate Prescaler + DBRP: u5, + reserved23: u2, + /// Transceiver Delay Compensation + TDC: u1, + padding: u8, + }), + /// FDCAN Test Register + TEST: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Loop Back mode + LBCK: u1, + /// Loop Back mode + TX: u2, + /// Control of Transmit Pin + RX: u1, + padding: u24, + }), + /// FDCAN RAM Watchdog Register + RWD: mmio.Mmio(packed struct(u32) { + /// Watchdog configuration + WDC: u8, + /// Watchdog value + WDV: u8, padding: u16, }), - }; - }; - - pub const pwr_u5 = struct { - pub const ACTVOS = enum(u2) { - /// Range 4 (lowest power) - Range4 = 0x0, - /// Range 3 - Range3 = 0x1, - /// Range 2 - Range2 = 0x2, - /// Range 1 (highest frequency) - Range1 = 0x3, - }; - - pub const FLASHFWU = enum(u1) { - /// Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption). - LowPower = 0x0, - /// Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time). - Normal = 0x1, - }; - - pub const LPMS = enum(u3) { - /// Stop 0 mode - Stop0 = 0x0, - /// Stop 1 mode - Stop1 = 0x1, - /// Stop 2 mode - Stop2 = 0x2, - /// Stop 3 mode - Stop3 = 0x3, - _, - }; - - pub const PDS = enum(u1) { - /// Content retained in Stop modes - Retained = 0x0, - /// Content lost in Stop modes - Lost = 0x1, - }; - - pub const PVDLS = enum(u3) { - /// VPVD0 around 2.0 V - v20 = 0x0, - /// VPVD1 around 2.2 V - v22 = 0x1, - /// VPVD2 around 2.4 V - v24 = 0x2, - /// VPVD3 around 2.5 V - v25 = 0x3, - /// VPVD4 around 2.6 V - v26 = 0x4, - /// VPVD5 around 2.8 V - v28 = 0x5, - /// VPVD6 around 2.9 V - v29 = 0x6, - /// External input analog voltage PVD_IN (compared internally to VREFINT) - pvd_in = 0x7, - }; - - pub const PVDO = enum(u1) { - /// VDD is equal or above the PVD threshold selected by PVDLS[2:0]. - AboveOrEqual = 0x0, - /// VDD is below the PVD threshold selected by PVDLS[2:0]. - Below = 0x1, - }; - - pub const REGSEL = enum(u1) { - /// LDO selected - LDO = 0x0, - /// SMPS selected - SMPS = 0x1, - }; - - pub const SRAMFWU = enum(u1) { - /// SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption). - B_0x0 = 0x0, - /// SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time). - B_0x1 = 0x1, - }; - - pub const SRAMPD = enum(u1) { - /// SRAM1 powered on - PoweredOn = 0x0, - /// SRAM1 powered off - PoweredOff = 0x1, - }; - - pub const TEMPH = enum(u1) { - /// Temperature < high threshold - B_0x0 = 0x0, - /// Temperature ≥ high threshold - B_0x1 = 0x1, - }; - - pub const TEMPL = enum(u1) { - /// Temperature > low threshold - B_0x0 = 0x0, - /// Temperature ≤ low threshold - B_0x1 = 0x1, - }; - - pub const VBATH = enum(u1) { - /// Backup domain voltage level < high threshold - B_0x0 = 0x0, - /// Backup domain voltage level ≥ high threshold - B_0x1 = 0x1, - }; - - pub const VBE = enum(u1) { - /// VBAT battery charging disabled - B_0x0 = 0x0, - /// VBAT battery charging enabled - B_0x1 = 0x1, - }; - - pub const VBRS = enum(u1) { - /// Charge VBAT through a 5 kΩ resistor - B_0x0 = 0x0, - /// Charge VBAT through a 1.5 kΩ resistor - B_0x1 = 0x1, - }; - - pub const VOS = enum(u2) { - /// Range 4 (lowest power) - Range4 = 0x0, - /// Range 3 - Range3 = 0x1, - /// Range 2 - Range2 = 0x2, - /// Range 1 (highest frequency). This value cannot be written when VCOREMEN = 1 in TAMP_OR register. - Range1 = 0x3, - }; - - pub const WUPP = enum(u1) { - /// Detection on high level (rising edge) - High = 0x0, - /// Detection on low level (falling edge) - Low = 0x1, - }; - - pub const WUSEL = enum(u2) { - /// WKUP7_0 - B_0x0 = 0x0, - /// WKUP7_1 - B_0x1 = 0x1, - /// WKUP7_2 - B_0x2 = 0x2, - /// WKUP7_3 - B_0x3 = 0x3, - }; - - /// Power control - pub const PWR = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection These bits select the low-power mode entered when the CPU enters the Deepsleep mode. 10x: Standby mode (Standby mode also entered if LPMS=11X in CR1 with BREN=1 in BDCR1) 11x: Shutdown mode if BREN = 0 in BDCR1 - LPMS: packed union { - raw: u3, - value: LPMS, - }, - reserved5: u2, - /// SRAM2 page 1 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2 (from SRAM2 base address to SRAM2 base address + 0x1FFF). Note: This bit has no effect in Shutdown mode. - RRSB1: u1, - /// SRAM2 page 2 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2 (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF). Note: This bit has no effect in Shutdown mode. - RRSB2: u1, - /// BOR ultra-low power mode This bit is used to reduce the consumption by configuring the BOR in discontinuous mode. This bit must be set to reach the lowest power consumption in the low-power modes. - ULPMEN: u1, - /// SRAM1 power down This bit is used to reduce the consumption by powering off the SRAM1. - SRAM1PD: packed union { - raw: u1, - value: SRAMPD, - }, - /// SRAM2 power down This bit is used to reduce the consumption by powering off the SRAM2. - SRAM2PD: packed union { - raw: u1, - value: SRAMPD, - }, - /// SRAM3 power down This bit is used to reduce the consumption by powering off the SRAM3. - SRAM3PD: packed union { - raw: u1, - value: SRAMPD, - }, - /// SRAM4 power down This bit is used to reduce the consumption by powering off the SRAM4. - SRAM4PD: packed union { - raw: u1, - value: SRAMPD, - }, - padding: u20, + /// FDCAN CC Control Register + CCCR: mmio.Mmio(packed struct(u32) { + /// Initialization + INIT: u1, + /// Configuration Change Enable + CCE: u1, + /// ASM Restricted Operation Mode + ASM: u1, + /// Clock Stop Acknowledge + CSA: u1, + /// Clock Stop Request + CSR: u1, + /// Bus Monitoring Mode + MON: u1, + /// Disable Automatic Retransmission + DAR: u1, + /// Test Mode Enable + TEST: u1, + /// FD Operation Enable + FDOE: u1, + /// FDCAN Bit Rate Switching + BSE: u1, + reserved12: u2, + /// Protocol Exception Handling Disable + PXHD: u1, + /// Edge Filtering during Bus Integration + EFBI: u1, + /// TXP + TXP: u1, + /// Non ISO Operation + NISO: u1, + padding: u16, }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) - SRAM1PDS1: packed union { - raw: u1, - value: PDS, - }, - /// SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) - SRAM1PDS2: packed union { - raw: u1, - value: PDS, - }, - /// SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) - SRAM1PDS3: packed union { - raw: u1, - value: PDS, - }, - reserved4: u1, - /// SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in CR1. - SRAM2PDS1: packed union { - raw: u1, - value: PDS, - }, - /// SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in CR1. - SRAM2PDS2: packed union { - raw: u1, - value: PDS, - }, - /// SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3) - SRAM4PDS: packed union { - raw: u1, - value: PDS, - }, + /// FDCAN Nominal Bit Timing and Prescaler Register + NBTP: mmio.Mmio(packed struct(u32) { + /// Nominal Time segment after sample point + NTSEG2: u7, reserved8: u1, - /// ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3) - ICRAMPDS: packed union { - raw: u1, - value: PDS, - }, - /// DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3) - DC1RAMPDS: packed union { - raw: u1, - value: PDS, - }, - /// DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3) - DMA2DRAMPDS: packed union { - raw: u1, - value: PDS, - }, - /// FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop0,1,2,3) - PRAMPDS: packed union { - raw: u1, - value: PDS, - }, - /// PKA SRAM power-down - PKARAMPDS: packed union { - raw: u1, - value: PDS, - }, - /// SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes. - SRAM4FWU: packed union { - raw: u1, - value: SRAMFWU, - }, - /// Flash memory fast wakeup from Stop 0 and Stop 1 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption. - FLASHFWU: packed union { - raw: u1, - value: FLASHFWU, - }, - reserved16: u1, - /// SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) - SRAM3PDS1: packed union { - raw: u1, - value: PDS, - }, - /// SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) - SRAM3PDS2: packed union { - raw: u1, - value: PDS, - }, - /// SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) - SRAM3PDS3: packed union { - raw: u1, - value: PDS, - }, - /// SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) - SRAM3PDS4: packed union { - raw: u1, - value: PDS, - }, - /// SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) - SRAM3PDS5: packed union { - raw: u1, - value: PDS, - }, - /// SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) - SRAM3PDS6: packed union { - raw: u1, - value: PDS, - }, - /// SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) - SRAM3PDS7: packed union { - raw: u1, - value: PDS, - }, - /// SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) - SRAM3PDS8: packed union { - raw: u1, - value: PDS, - }, - reserved31: u7, - /// SmartRun domain in Run mode - SRDRUN: u1, + /// Nominal Time segment before sample point + NTSEG1: u8, + /// Bit Rate Prescaler + NBRP: u9, + /// NSJW: Nominal (Re)Synchronization Jump Width. + NSJW: u7, }), - /// control register 3 - CR3: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Regulator selection Note: REGSEL is reserved and must be kept at reset value in packages without SMPS. - REGSEL: packed union { - raw: u1, - value: REGSEL, - }, - /// Fast soft start - FSTEN: u1, - padding: u29, + /// FDCAN Timestamp Counter Configuration Register + TSCC: mmio.Mmio(packed struct(u32) { + /// Timestamp Select + TSS: u2, + reserved16: u14, + /// Timestamp Counter Prescaler + TCP: u4, + padding: u12, }), - /// voltage scaling register - VOSR: mmio.Mmio(packed struct(u32) { - reserved14: u14, - /// EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set. - BOOSTRDY: u1, - /// Ready bit for VCORE voltage scaling output selection - VOSRDY: u1, - /// Voltage scaling range selection This field is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1. - VOS: packed union { - raw: u2, - value: VOS, - }, - /// EPOD booster enable - BOOSTEN: u1, - padding: u13, + /// FDCAN Timestamp Counter Value Register + TSCV: mmio.Mmio(packed struct(u32) { + /// Timestamp Counter + TSC: u16, + padding: u16, }), - /// supply voltage monitoring control register - SVMCR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Power voltage detector enable - PVDE: u1, - /// Power voltage detector level selection These bits select the voltage threshold detected by the power voltage detector: - PVDLS: packed union { - raw: u3, - value: PVDLS, - }, - reserved24: u16, - /// VDDUSB independent USB voltage monitor enable - UVMEN: u1, - /// VDDIO2 independent I/Os voltage monitor enable - IO2VMEN: u1, - /// VDDA independent analog supply voltage monitor 1 enable (1.6V threshold) - AVM1EN: u1, - /// VDDA independent analog supply voltage monitor 2 enable (1.8V threshold) - AVM2EN: u1, - /// VDDUSB independent USB supply valid - USV: u1, - /// VDDIO2 independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not. - IO2SV: u1, - /// VDDA independent analog supply valid - ASV: u1, - padding: u1, + /// FDCAN Timeout Counter Configuration Register + TOCC: mmio.Mmio(packed struct(u32) { + /// Enable Timeout Counter + ETOC: u1, + /// Timeout Select + TOS: u2, + reserved16: u13, + /// Timeout Period + TOP: u16, }), - /// wakeup control register 1 - WUCR1: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 enable - WUPEN: u1, - padding: u31, + /// FDCAN Timeout Counter Value Register + TOCV: mmio.Mmio(packed struct(u32) { + /// Timeout Counter + TOC: u16, + padding: u16, }), - /// wakeup control register 2 - WUCR2: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. - WUPP: packed union { - raw: u1, - value: WUPP, - }, - padding: u31, + reserved64: [16]u8, + /// FDCAN Error Counter Register + ECR: mmio.Mmio(packed struct(u32) { + /// Transmit Error Counter + TEC: u8, + /// Receive Error Counter + REC: u7, + /// Receive Error Passive + RP: u1, + /// AN Error Logging + CEL: u8, + padding: u8, }), - /// wakeup control register 3 - WUCR3: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 selection This field must be configured when WUPEN1 = 0. - WUSEL1: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup pin WKUP2 selection This field must be configured when WUPEN2 = 0. - WUSEL2: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup pin WKUP3 selection This field must be configured when WUPEN3 = 0. - WUSEL3: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup pin WKUP4 selection This field must be configured when WUPEN4 = 0. - WUSEL4: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup pin WKUP5 selection This field must be configured when WUPEN5 = 0. - WUSEL5: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup pin WKUP6 selection This field must be configured when WUPEN6 = 0. - WUSEL6: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup pin WKUP7 selection This field must be configured when WUPEN7 = 0. - WUSEL7: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup pin WKUP8 selection This field must be configured when WUPEN8 = 0. - WUSEL8: packed union { - raw: u2, - value: WUSEL, - }, - padding: u16, + /// FDCAN Protocol Status Register + PSR: mmio.Mmio(packed struct(u32) { + /// Last Error Code + LEC: u3, + /// Activity + ACT: u2, + /// Error Passive + EP: u1, + /// Warning Status + EW: u1, + /// Bus_Off Status + BO: u1, + /// Data Last Error Code + DLEC: u3, + /// ESI flag of last received FDCAN Message + RESI: u1, + /// BRS flag of last received FDCAN Message + RBRS: u1, + /// Received FDCAN Message + REDL: u1, + /// Protocol Exception Event + PXE: u1, + reserved16: u1, + /// Transmitter Delay Compensation Value + TDCV: u7, + padding: u9, }), - /// Backup domain control register 1 - BDCR1: mmio.Mmio(packed struct(u32) { - /// Backup RAM retention in Standby and VBAT modes When this bit is set, the backup RAM content is kept in Standby and VBAT modes. If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS. Note: Backup RAM cannot be preserved in Shutdown mode. - BREN: u1, - reserved4: u3, - /// Backup domain voltage and temperature monitoring enable - MONEN: u1, - padding: u27, + /// FDCAN Transmitter Delay Compensation Register + TDCR: mmio.Mmio(packed struct(u32) { + /// Transmitter Delay Compensation Filter Window Length + TDCF: u7, + reserved8: u1, + /// Transmitter Delay Compensation Offset + TDCO: u7, + padding: u17, }), - /// Backup domain control register 2 - BDCR2: mmio.Mmio(packed struct(u32) { - /// VBAT charging enable - VBE: packed union { - raw: u1, - value: VBE, - }, - /// VBAT charging resistor selection - VBRS: packed union { - raw: u1, - value: VBRS, - }, - padding: u30, + reserved80: [4]u8, + /// FDCAN Interrupt Register + IR: mmio.Mmio(packed struct(u32) { + /// Rx FIFO X New Message + RFN: u1, + /// Rx FIFO X Watermark Reached + RFW: u1, + /// Rx FIFO X Full + RFF: u1, + /// Rx FIFO X Message Lost + RFL: u1, + reserved8: u4, + /// High Priority Message + HPM: u1, + /// Transmission Completed + TC: u1, + /// Transmission Cancellation Finished + TCF: u1, + /// Tx FIFO Empty + TEF: u1, + /// Tx Event FIFO New Entry + TEFN: u1, + /// Tx Event FIFO Watermark Reached + TEFW: u1, + /// Tx Event FIFO Full + TEFF: u1, + /// Tx Event FIFO Element Lost + TEFL: u1, + /// Timestamp Wraparound + TSW: u1, + /// Message RAM Access Failure + MRAF: u1, + /// Timeout Occurred + TOO: u1, + /// Message stored to Dedicated Rx Buffer + DRX: u1, + reserved22: u2, + /// Error Logging Overflow + ELO: u1, + /// Error Passive + EP: u1, + /// Warning Status + EW: u1, + /// Bus_Off Status + BO: u1, + /// Watchdog Interrupt + WDI: u1, + /// Protocol Error in Arbitration Phase (Nominal Bit Time is used) + PEA: u1, + /// Protocol Error in Data Phase (Data Bit Time is used) + PED: u1, + /// Access to Reserved Address + ARA: u1, + padding: u2, }), - /// disable Backup domain register - DBPCR: mmio.Mmio(packed struct(u32) { - /// Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers. - DBP: u1, - padding: u31, + /// FDCAN Interrupt Enable Register + IE: mmio.Mmio(packed struct(u32) { + /// Rx FIFO X New Message Enable + RFNE: u1, + /// Rx FIFO X Watermark Reached Enable + RFWE: u1, + /// Rx FIFO X Full Enable + RFFE: u1, + /// Rx FIFO X Message Lost Enable + RFLE: u1, + reserved8: u4, + /// High Priority Message Enable + HPME: u1, + /// Transmission Completed Enable + TCE: u1, + /// Transmission Cancellation Finished Enable + TCFE: u1, + /// Tx FIFO Empty Enable + TEFE: u1, + /// Tx Event FIFO New Entry Enable + TEFNE: u1, + /// Tx Event FIFO Watermark Reached Enable + TEFWE: u1, + /// Tx Event FIFO Full Enable + TEFFE: u1, + /// Tx Event FIFO Element Lost Enable + TEFLE: u1, + /// Timestamp Wraparound Enable + TSWE: u1, + /// Message RAM Access Failure Enable + MRAFE: u1, + /// Timeout Occurred Enable + TOOE: u1, + /// Message stored to Dedicated Rx Buffer Enable + DRXE: u1, + /// Bit Error Corrected Interrupt Enable + BECE: u1, + /// Bit Error Uncorrected Interrupt Enable + BEUE: u1, + /// Error Logging Overflow Enable + ELOE: u1, + /// Error Passive Enable + EPE: u1, + /// Warning Status Enable + EWE: u1, + /// Bus_Off Status Enable + BOE: u1, + /// Watchdog Interrupt Enable + WDIE: u1, + /// Protocol Error in Arbitration Phase Enable + PEAE: u1, + /// Protocol Error in Data Phase Enable + PEDE: u1, + /// Access to Reserved Address Enable + ARAE: u1, + padding: u2, }), - /// USB Type-C™ and Power Delivery register - UCPDR: mmio.Mmio(packed struct(u32) { - /// UCPD dead battery disable After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable). - UCPD_DBDIS: u1, - /// UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers. - UCPD_STBY: u1, + /// FDCAN Interrupt Line Select Register + ILS: mmio.Mmio(packed struct(u32) { + /// Rx FIFO X New Message Interrupt Line + RFNL: u1, + /// Rx FIFO X Watermark Reached Interrupt Line + RFWL: u1, + /// Rx FIFO X Full Interrupt Line + RFFL: u1, + /// Rx FIFO X Message Lost Interrupt Line + RFLL: u1, + reserved8: u4, + /// High Priority Message Interrupt Line + HPML: u1, + /// Transmission Completed Interrupt Line + TCL: u1, + /// Transmission Cancellation Finished Interrupt Line + TCFL: u1, + /// Tx FIFO Empty Interrupt Line + TEFL: u1, + /// Tx Event FIFO New Entry Interrupt Line + TEFNL: u1, + /// Tx Event FIFO Watermark Reached Interrupt Line + TEFWL: u1, + /// Tx Event FIFO Full Interrupt Line + TEFFL: u1, + /// Tx Event FIFO Element Lost Interrupt Line + TEFLL: u1, + /// Timestamp Wraparound Interrupt Line + TSWL: u1, + /// Message RAM Access Failure Interrupt Line + MRAFL: u1, + /// Timeout Occurred Interrupt Line + TOOL: u1, + /// Message stored to Dedicated Rx Buffer Interrupt Line + DRXL: u1, + /// Bit Error Corrected Interrupt Line + BECL: u1, + /// Bit Error Uncorrected Interrupt Line + BEUL: u1, + /// Error Logging Overflow Interrupt Line + ELOL: u1, + /// Error Passive Interrupt Line + EPL: u1, + /// Warning Status Interrupt Line + EWL: u1, + /// Bus_Off Status + BOL: u1, + /// Watchdog Interrupt Line + WDIL: u1, + /// Protocol Error in Arbitration Phase Line + PEAL: u1, + /// Protocol Error in Data Phase Line + PEDL: u1, + /// Access to Reserved Address Line + ARAL: u1, + padding: u2, + }), + /// FDCAN Interrupt Line Enable Register + ILE: mmio.Mmio(packed struct(u32) { + /// Enable Interrupt Line 0 + EINT0: u1, + /// Enable Interrupt Line 1 + EINT1: u1, padding: u30, }), - /// security configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// WUP1 secure protection - WUP1SEC: u1, - reserved12: u11, - /// Low-power modes secure protection - LPMSEC: u1, - /// Voltage detection and monitoring secure protection - VDMSEC: u1, - /// Backup domain secure protection - VBSEC: u1, - /// Pull-up/pull-down secure protection - APCSEC: u1, + reserved128: [32]u8, + /// FDCAN Global Filter Configuration Register + GFC: mmio.Mmio(packed struct(u32) { + /// Reject Remote Frames Extended + RRFE: u1, + /// Reject Remote Frames Standard + RRFS: u1, + /// Accept Non-matching Frames Extended + ANFE: u2, + /// Accept Non-matching Frames Standard + ANFS: u2, + padding: u26, + }), + /// FDCAN Standard ID Filter Configuration Register + SIDFC: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Filter List Standard Start Address + FLSSA: u14, + /// List Size Standard + LSS: u8, + padding: u8, + }), + /// FDCAN Extended ID Filter Configuration Register + XIDFC: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Filter List Standard Start Address + FLESA: u14, + /// List Size Extended + LSE: u8, + padding: u8, + }), + reserved144: [4]u8, + /// FDCAN Extended ID and Mask Register + XIDAM: mmio.Mmio(packed struct(u32) { + /// Extended ID Mask + EIDM: u29, + padding: u3, + }), + /// FDCAN High Priority Message Status Register + HPMS: mmio.Mmio(packed struct(u32) { + /// Buffer Index + BIDX: u6, + /// Message Storage Indicator + MSI: u2, + /// Filter Index + FIDX: u7, + /// Filter List + FLST: u1, padding: u16, }), - /// privilege control register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// secure functions privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access. - SPRIV: u1, - /// non-secure functions privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. - NSPRIV: u1, - padding: u30, + /// FDCAN New Data 1 Register + NDAT1: mmio.Mmio(packed struct(u32) { + /// New data (buffers 0 - 31) + ND: u32, }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Clear Stop and Standby flags This bit is protected against non-secure access when LPMSEC=1 in SECCFGR. This bit is protected against unprivileged access when LPMSEC=1 and SPRIV=1 in PRIVCFGR, or when LPMSEC=0 and NSPRIV=1. Writing 1 to this bit clears the STOPF and SBF flags. - CSSF: u1, - /// Stop flag This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit. - STOPF: u1, - /// Standby flag This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset. - SBF: u1, - padding: u29, + /// FDCAN New Data 2 Register + NDAT2: mmio.Mmio(packed struct(u32) { + /// New data (buffers 32 - 63) + ND: u32, }), - SVMSR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Regulator selection - REGS: packed union { - raw: u1, - value: REGSEL, - }, - reserved4: u2, - /// VDD voltage detector output - PVDO: packed union { - raw: u1, - value: PVDO, - }, - reserved15: u10, - /// Voltage level ready for currently used VOS - ACTVOSRDY: u1, - /// VOS currently applied to VCORE This field provides the last VOS value. - ACTVOS: packed union { - raw: u2, - value: ACTVOS, - }, - reserved24: u6, - /// VDDUSB ready - VDDUSBRDY: u1, - /// VDDIO2 ready - VDDIO2RDY: u1, - /// VDDA ready versus 1.6V voltage monitor - VDDA1RDY: u1, - /// VDDA ready versus 1.8V voltage monitor - VDDA2RDY: u1, - padding: u4, + /// FDCAN Rx FIFO X Configuration Register + RXFC: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Rx FIFO X Start Address + FSA: u14, + /// Rx FIFO X Size + FS: u7, + reserved24: u1, + /// FIFO X Watermark + FWM: u7, + /// FIFO X operation mode + FOM: u1, }), - /// Backup domain status register - BDSR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Backup domain voltage level monitoring versus high threshold - VBATH: packed union { - raw: u1, - value: VBATH, - }, - /// Temperature level monitoring versus low threshold - TEMPL: packed union { - raw: u1, - value: TEMPL, - }, - /// Temperature level monitoring versus high threshold - TEMPH: packed union { + /// FDCAN Rx FIFO X Status Register + RXFS: mmio.Mmio(packed struct(u32) { + /// Rx FIFO X Fill Level + FFL: u7, + reserved8: u1, + /// Rx FIFO X Get Index + FGI: u6, + reserved16: u2, + /// Rx FIFO X Put Index + FPI: u6, + reserved24: u2, + /// Rx FIFO X Full + FF: u1, + /// Rx FIFO X Message Lost + RFL: u1, + padding: u6, + }), + /// CAN Rx FIFO X Acknowledge Register + RXFA: mmio.Mmio(packed struct(u32) { + /// Rx FIFO X Acknowledge Index + FAI: u6, + padding: u26, + }), + /// FDCAN Rx Buffer Configuration Register + RXBC: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Rx Buffer Start Address + RBSA: u14, + padding: u16, + }), + reserved188: [12]u8, + /// FDCAN Rx Buffer Element Size Configuration Register + RXESC: mmio.Mmio(packed struct(u32) { + /// Rx FIFO X Data Field Size + FDS: u3, + reserved8: u5, + /// Rx Buffer Data Field Size + RBDS: u3, + padding: u21, + }), + /// FDCAN Tx Buffer Configuration Register + TXBC: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Tx Buffers Start Address + TBSA: u14, + /// Number of Dedicated Transmit Buffers + NDTB: u6, + reserved24: u2, + /// Transmit FIFO/Queue Size + TFQS: u6, + /// Tx FIFO/Queue Mode + TFQM: packed union { raw: u1, - value: TEMPH, + value: TFQM, }, - padding: u28, + padding: u1, }), - /// wakeup status register - WUSR: mmio.Mmio(packed struct(u32) { - /// Wakeup flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1=0. - WUF1: u1, - /// Wakeup flag 2 This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2=0. - WUF2: u1, - /// Wakeup flag 3 This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3=0. - WUF3: u1, - /// Wakeup flag 4 This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4=0. - WUF4: u1, - /// Wakeup flag 5 This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5=0. - WUF5: u1, - /// Wakeup flag 6 This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6=0. If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared. - WUF6: u1, - /// Wakeup flag 7 This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7=0. If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared. - WUF7: u1, - /// Wakeup flag 8 This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8=0. If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared. - WUF8: u1, - padding: u24, + /// FDCAN Tx FIFO/Queue Status Register + TXFQS: mmio.Mmio(packed struct(u32) { + /// Tx FIFO Free Level + TFFL: u6, + reserved8: u2, + /// TFGI + TFGI: u5, + reserved16: u3, + /// Tx FIFO/Queue Put Index + TFQPI: u5, + /// Tx FIFO/Queue Full + TFQF: u1, + padding: u10, }), - /// wakeup status clear register - WUSCR: mmio.Mmio(packed struct(u32) { - /// Wakeup flag 1 Writing 1 to this bit clears the WUF1 flag in WUSR. - CWUF1: u1, - /// Wakeup flag 2 Writing 1 to this bit clears the WUF2 flag in WUSR. - CWUF2: u1, - /// Wakeup flag 3 Writing 1 to this bit clears the WUF3 flag in WUSR. - CWUF3: u1, - /// Wakeup flag 4 Writing 1 to this bit clears the WUF4 flag in WUSR. - CWUF4: u1, - /// Wakeup flag 5 Writing 1 to this bit clears the WUF5 flag in WUSR. - CWUF5: u1, - /// Wakeup flag 6 Writing 1 to this bit clears the WUF6 flag in WUSR. - CWUF6: u1, - /// Wakeup flag 7 Writing 1 to this bit clears the WUF7 flag in WUSR. - CWUF7: u1, - /// Wakeup flag 8 Writing 1 to this bit clears the WUF8 flag in WUSR. - CWUF8: u1, - padding: u24, + /// FDCAN Tx Buffer Element Size Configuration Register + TXESC: mmio.Mmio(packed struct(u32) { + /// Tx Buffer Data Field Size + TBDS: u3, + padding: u29, }), - /// apply pull configuration register - APCR: mmio.Mmio(packed struct(u32) { - /// Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PUCRx and PDCRx are applied. When this bit is cleared, PUCRx and PDCRx are not applied to the I/Os. - APC: u1, + /// FDCAN Tx Buffer Request Pending Register + TXBRP: mmio.Mmio(packed struct(u32) { + /// Transmission Request Pending + TRP: u1, padding: u31, }), - /// Power Port pull-up control register - PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, + /// FDCAN Tx Buffer Add Request Register + TXBAR: mmio.Mmio(packed struct(u32) { + /// Add Request + AR: u1, padding: u31, }), - /// Power Port pull-down control register - PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, + /// FDCAN Tx Buffer Cancellation Request Register + TXBCR: mmio.Mmio(packed struct(u32) { + /// Cancellation Request + CR: u1, padding: u31, }), - }; - }; - - pub const syscfg_h50 = struct { - pub const CS = enum(u1) { - /// Code from the cell (available in SBS_CCVR) - Cell = 0x0, - /// Code from SBS_CCCR - Software = 0x1, - }; - - pub const DBGCFG_LOCK = enum(u8) { - /// Writes to SBS_DBGCR allowed (default) - B_0xB4 = 0xb4, - _, - }; - - pub const DBG_AUTH_HDPL = enum(u8) { - /// HDPL1 - B_0x51 = 0x51, - /// HDPL3 - B_0x6F = 0x6f, - /// HDPL2 - B_0x8A = 0x8a, - _, - }; - - pub const HDPL = enum(u8) { - /// HDPL1, iRoT - B_0x51 = 0x51, - /// HDPL3, application - B_0x6F = 0x6f, - /// HDPL2, uRoT - B_0x8A = 0x8a, - /// HDPL0, RSS - B_0xB4 = 0xb4, - _, - }; - - pub const INCR_HDPL = enum(u8) { - /// recommended value to increment HDPL level by one - B_0x6A = 0x6a, - /// no increment - B_0xB4 = 0xb4, - _, - }; - - /// System configuration, boot and security - pub const SYSCFG = extern struct { - reserved16: [16]u8, - /// SBS temporal isolation control register - HDPLCR: mmio.Mmio(packed struct(u32) { - /// increment HDPL value Other: all other values allow a HDPL level increment. - INCR_HDPL: packed union { - raw: u8, - value: INCR_HDPL, - }, - padding: u24, - }), - /// SBS temporal isolation status register - HDPLSR: mmio.Mmio(packed struct(u32) { - /// temporal isolation level This bitfield returns the current temporal isolation level. - HDPL: packed union { - raw: u8, - value: HDPL, - }, - padding: u24, - }), - reserved32: [8]u8, - /// SBS debug control register - DBGCR: mmio.Mmio(packed struct(u32) { - /// access port unlock Write 0xB4 to this bitfield to open the device access port. - AP_UNLOCK: u8, - /// debug unlock when DBG_AUTH_HDPL is reached Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register. - DBG_UNLOCK: u8, - /// authenticated debug temporal isolation level Writing to this bitfield defines at which HDPL the authenticated debug opens. Note: Writing any other values is ignored. Reading any other value means the debug never opens. - DBG_AUTH_HDPL: packed union { - raw: u8, - value: DBG_AUTH_HDPL, - }, - padding: u8, + /// FDCAN Tx Buffer Transmission Occurred Register + TXBTO: mmio.Mmio(packed struct(u32) { + /// Transmission Occurred + TO: u1, + padding: u31, }), - /// SBS debug lock register - DBGLOCKR: mmio.Mmio(packed struct(u32) { - /// debug configuration lock Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4. 0xC3 is the recommended value to lock the debug configuration using this bitfield. Other: Writes to SBS_DBGCR ignored - DBGCFG_LOCK: packed union { - raw: u8, - value: DBGCFG_LOCK, - }, - padding: u24, + /// FDCAN Tx Buffer Cancellation Finished Register + TXBCF: mmio.Mmio(packed struct(u32) { + /// Cancellation Finished + CF: u1, + padding: u31, }), - reserved256: [216]u8, - /// SBS product mode and configuration register - PMCR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// booster enable Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range. - BOOSTEN: u1, - /// booster VDD selection Note: Booster must not be used when VDDA < 2.7 V, but VDD > 2.7 V (add current consumption). Note: When both VDD < 2.7 V and VDDA < 2.7 V, booster is needed to get full AC performances from I/O analog switches. - BOOSTVDDSEL: u1, - reserved16: u6, - /// Fast-mode Plus command on PB(6) - PB6_FMPLUS: u1, - /// Fast-mode Plus command on PB(7) - PB7_FMPLUS: u1, - /// Fast-mode Plus command on PB(8) - PB8_FMPLUS: u1, - padding: u13, + /// FDCAN Tx Buffer Transmission Interrupt Enable Register + TXBTIE: mmio.Mmio(packed struct(u32) { + /// Transmission Interrupt Enable + TIE: u1, + padding: u31, }), - /// SBS FPU interrupt mask register - FPUIMR: mmio.Mmio(packed struct(u32) { - /// FPU interrupt enable Set and cleared by software to enable the Cortex-M33 FPU interrupts FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset) FPU_IE[4]: input abnormal interrupt enable FPU_IE[3]: overflow interrupt enable FPU_IE[2]: underflow interrupt enable FPU_IE[1]: divide-by-zero interrupt enable FPU_IE[0]: invalid operation interrupt enable - FPU_IE: u6, - padding: u26, + /// FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register + TXBCIE: mmio.Mmio(packed struct(u32) { + /// Cancellation Finished Interrupt Enable + CF: u1, + padding: u31, }), - /// SBS memory erase status register - MESR: mmio.Mmio(packed struct(u32) { - /// erase after reset status This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, ICACHE. It is set by hardware and reset by software - MCLR: u1, - reserved16: u15, - /// end-of-erase status for ICACHE This bit shows the status of the protection for ICACHE. It is set by hardware and reset by software. - IPMEE: u1, - padding: u15, + reserved240: [8]u8, + /// FDCAN Tx Event FIFO Configuration Register + TXEFC: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Event FIFO Start Address + EFSA: u14, + /// Event FIFO Size + EFS: u6, + reserved24: u2, + /// Event FIFO Watermark + EFWM: u6, + padding: u2, }), - reserved272: [4]u8, - /// SBS compensation cell for I/Os control and status register - CCCSR: mmio.Mmio(packed struct(u32) { - /// enable compensation cell for VDDIO power rail This bit enables the I/O compensation cell. - EN: u1, - /// code selection for VDDIO power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. - CS: packed union { - raw: u1, - value: CS, - }, - reserved8: u6, - /// VDDIO compensation cell ready flag This bit provides the status of the compensation cell. - RDY: u1, - padding: u23, + /// FDCAN Tx Event FIFO Status Register + TXEFS: mmio.Mmio(packed struct(u32) { + /// Event FIFO Fill Level + EFFL: u6, + reserved8: u2, + /// Event FIFO Get Index + EFGI: u5, + reserved16: u3, + /// Event FIFO put index + EFPI: u5, + reserved24: u3, + /// Event FIFO Full + EFF: u1, + /// Tx Event FIFO Element Lost + TEFL: u1, + padding: u6, }), - /// SBS compensation cell for I/Os value register - CCVALR: mmio.Mmio(packed struct(u32) { - /// compensation value for the NMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. - ANSRC1: u4, - /// compensation value for the PMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. - APSRC1: u4, - /// Compensation value for the NMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. - ANSRC2: u4, - /// compensation value for the PMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. - APSRC2: u4, - padding: u16, + /// FDCAN Tx Event FIFO Acknowledge Register + TXEFA: mmio.Mmio(packed struct(u32) { + /// Event FIFO Acknowledge Index + EFAI: u5, + padding: u27, }), - /// SBS compensation cell for I/Os software code register - CCSWCR: mmio.Mmio(packed struct(u32) { - /// NMOS compensation code for VDD power rails This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR. - SW_ANSRC1: u4, - /// PMOS compensation code for the VDD power rails This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR. - SW_APSRC1: u4, - /// NMOS compensation code for VDDIO power rails This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR. - SW_ANSRC2: u4, - /// PMOS compensation code for the VDDIO power rails This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR. - SW_APSRC2: u4, - padding: u16, + reserved256: [4]u8, + /// FDCAN TT Trigger Memory Configuration Register + TTTMC: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Trigger Memory Start Address + TMSA: u14, + /// Trigger Memory Elements + TME: u7, + padding: u9, }), - reserved288: [4]u8, - /// SBS Class B register - CFGR2: mmio.Mmio(packed struct(u32) { - /// core lockup lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1 break inputs. - CLL: u1, - /// SRAM ECC error lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1. - SEL: u1, - /// PVD lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1 break inputs. - PVDL: u1, - /// ECC lock This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1. - ECCL: u1, - padding: u28, + /// FDCAN TT Reference Message Configuration Register + TTRMC: mmio.Mmio(packed struct(u32) { + /// Reference Identifier + RID: u29, + reserved30: u1, + /// Extended Identifier + XTD: u1, + /// Reference Message Payload Select + RMPS: u1, }), - reserved324: [32]u8, - /// SBS CPU lock register - CNSLCKR: mmio.Mmio(packed struct(u32) { - /// VTOR_NS register lock This bit is set by software and cleared only by a system reset. - LOCKNSVTOR: u1, - /// MPU register lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers. - LOCKNSMPU: u1, - padding: u30, + /// FDCAN TT Operation Configuration Register + TTOCF: mmio.Mmio(packed struct(u32) { + /// Operation Mode + OM: u2, + reserved3: u1, + /// Gap Enable + GEN: u1, + /// Time Master + TM: u1, + /// LD of Synchronization Deviation Limit + LDSDL: u3, + /// Initial Reference Trigger Offset + IRTO: u7, + /// Enable External Clock Synchronization + EECS: u1, + /// Application Watchdog Limit + AWL: u8, + /// Enable Global Time Filtering + EGTF: u1, + /// Enable Clock Calibration + ECC: u1, + /// Event Trigger Polarity + EVTP: u1, + padding: u5, }), - reserved332: [4]u8, - /// SBS flift ECC NMI mask register - ECCNMIR: mmio.Mmio(packed struct(u32) { - /// NMI behavior setup when a double ECC error occurs on flitf data part - ECCNMI_MASK_EN: u1, - padding: u31, + /// FDCAN TT Matrix Limits Register + TTMLM: mmio.Mmio(packed struct(u32) { + /// Cycle Count Max + CCM: u6, + /// Cycle Start Synchronization + CSS: u2, + /// Tx Enable Window + TXEW: u4, + reserved16: u4, + /// Expected Number of Tx Triggers + ENTT: u12, + padding: u4, }), - }; - }; - - pub const flash_c0 = struct { - pub const BORF_LEV = enum(u2) { - /// BOR falling level 1 with threshold around 2.0V - FALLING_0 = 0x0, - /// BOR falling level 2 with threshold around 2.2V - FALLING_1 = 0x1, - /// BOR falling level 3 with threshold around 2.5V - FALLING_2 = 0x2, - /// BOR falling level 4 with threshold around 2.8V - FALLING_3 = 0x3, - }; - - pub const BORR_LEV = enum(u2) { - /// BOR rising level 1 with threshold around 2.1V - RISING_0 = 0x0, - /// BOR rising level 2 with threshold around 2.3V - RISING_1 = 0x1, - /// BOR rising level 3 with threshold around 2.6V - RISING_2 = 0x2, - /// BOR rising level 4 with threshold around 2.9V - RISING_3 = 0x3, - }; - - pub const LATENCY = enum(u3) { - /// Zero wait states - WS0 = 0x0, - /// One wait state - WS1 = 0x1, - _, - }; - - pub const NRST_MODE = enum(u2) { - /// Reset pin is in reset input mode only - INPUT_ONLY = 0x1, - /// Reset pin is in GPIO mode only - GPIO = 0x2, - /// Reset pin is in resety input and output mode - INPUT_OUTPUT = 0x3, - _, - }; - - pub const RDP = enum(u8) { - /// Read protection not active - LEVEL_0 = 0xaa, - /// Memories read protection active - LEVEL_1 = 0xbb, - /// Chip read protection active - LEVEL_2 = 0xcc, - _, - }; - - /// Flash - pub const FLASH = extern struct { - /// Access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: packed union { - raw: u3, - value: LATENCY, - }, - reserved8: u5, - /// Prefetch enable - PRFTEN: u1, - /// Instruction cache enable - ICEN: u1, - reserved11: u1, - /// Instruction cache reset - ICRST: u1, - reserved16: u4, - /// Flash User area empty - EMPTY: u1, - reserved18: u1, - /// Debug access software enable - DBG_SWEN: u1, + /// FDCAN TUR Configuration Register + TURCF: mmio.Mmio(packed struct(u32) { + /// Numerator Configuration Low + NCL: u16, + /// Denominator Configuration + DC: u14, + reserved31: u1, + /// Enable Local Time + ELT: u1, + }), + /// FDCAN TT Operation Control Register + TTOCN: mmio.Mmio(packed struct(u32) { + /// Set Global time + SGT: u1, + /// External Clock Synchronization + ECS: u1, + /// Stop Watch Polarity + SWP: u1, + /// Stop Watch Source + SWS: u2, + /// Register Time Mark Interrupt Pulse Enable + RTIE: u1, + /// Register Time Mark Compare + TMC: u2, + /// Trigger Time Mark Interrupt Pulse Enable + TTIE: u1, + /// Gap Control Select + GCS: u1, + /// Finish Gap + FGP: u1, + /// Time Mark Gap + TMG: u1, + /// Next is Gap + NIG: u1, + /// External Synchronization Control + ESCN: u1, + reserved15: u1, + /// TT Operation Control Register Locked + LCKC: u1, + padding: u16, + }), + /// FDCAN TT Global Time Preset Register + TTGTP: mmio.Mmio(packed struct(u32) { + /// Time Preset + NCL: u16, + /// Cycle Time Target Phase + CTP: u16, + }), + /// FDCAN TT Time Mark Register + TTTMK: mmio.Mmio(packed struct(u32) { + /// Time Mark + TM: u16, + /// Time Mark Cycle Code + TICC: u7, + reserved31: u8, + /// TT Time Mark Register Locked + LCKM: u1, + }), + /// FDCAN TT Interrupt Register + TTIR: mmio.Mmio(packed struct(u32) { + /// Start of Basic Cycle + SBC: u1, + /// Start of Matrix Cycle + SMC: u1, + /// Change of Synchronization Mode + CSM: u1, + /// Start of Gap + SOG: u1, + /// Register Time Mark Interrupt + RTMI: u1, + /// Trigger Time Mark Event Internal + TTMI: u1, + /// Stop Watch Event + SWE: u1, + /// Global Time Wrap + GTW: u1, + /// Global Time Discontinuity + GTD: u1, + /// Global Time Error + GTE: u1, + /// Tx Count Underflow + TXU: u1, + /// Tx Count Overflow + TXO: u1, + /// Scheduling Error 1 + SE1: u1, + /// Scheduling Error 2 + SE2: u1, + /// Error Level Changed + ELC: u1, + /// Initialization Watch Trigger + IWTG: u1, + /// Watch Trigger + WT: u1, + /// Application Watchdog + AW: u1, + /// Configuration Error + CER: u1, padding: u13, }), - reserved8: [4]u8, - /// Flash key register - KEYR: u32, - /// Option byte key register - OPTKEYR: u32, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved3: u1, - /// Programming error - PROGERR: u1, - /// Write protected error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Size error - SIZERR: u1, - /// Programming sequence error - PGSERR: u1, - /// Fast programming data miss error - MISERR: u1, - /// Fast programming error - FASTERR: u1, - reserved14: u4, - /// PCROP read error - RDERR: u1, - /// Option and Engineering bits loading validity error - OPTVERR: u1, - /// Busy - BSY: u1, - reserved18: u1, - /// Programming or erase configuration busy. - CFGBSY: u1, + /// FDCAN TT Interrupt Enable Register + TTIE: mmio.Mmio(packed struct(u32) { + /// Start of Basic Cycle Interrupt Enable + SBCE: u1, + /// Start of Matrix Cycle Interrupt Enable + SMCE: u1, + /// Change of Synchronization Mode Interrupt Enable + CSME: u1, + /// Start of Gap Interrupt Enable + SOGE: u1, + /// Register Time Mark Interrupt Enable + RTMIE: u1, + /// Trigger Time Mark Event Internal Interrupt Enable + TTMIE: u1, + /// Stop Watch Event Interrupt Enable + SWEE: u1, + /// Global Time Wrap Interrupt Enable + GTWE: u1, + /// Global Time Discontinuity Interrupt Enable + GTDE: u1, + /// Global Time Error Interrupt Enable + GTEE: u1, + /// Tx Count Underflow Interrupt Enable + TXUE: u1, + /// Tx Count Overflow Interrupt Enable + TXOE: u1, + /// Scheduling Error 1 Interrupt Enable + SE1E: u1, + /// Scheduling Error 2 Interrupt Enable + SE2E: u1, + /// Change Error Level Interrupt Enable + ELCE: u1, + /// Initialization Watch Trigger Interrupt Enable + IWTGE: u1, + /// Watch Trigger Interrupt Enable + WTE: u1, + /// Application Watchdog Interrupt Enable + AWE: u1, + /// Configuration Error Interrupt Enable + CERE: u1, padding: u13, }), - /// Flash control register - CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Page erase - PER: u1, - /// Mass erase - MER: u1, - /// Page number - PNB: u4, - reserved16: u9, - /// Start - STRT: u1, - /// Options modification start - OPTSTRT: u1, - /// Fast programming - FSTPG: u1, - reserved24: u5, - /// End of operation interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// PCROP read error interrupt enable - RDERRIE: u1, - /// Force the option byte loading - OBL_LAUNCH: u1, - /// Securable memory area protection enable - SEC_PROT: u1, - reserved30: u1, - /// Options Lock - OPTLOCK: u1, - /// FLASH_CR Lock - LOCK: u1, + /// FDCAN TT Interrupt Line Select Register + TTILS: mmio.Mmio(packed struct(u32) { + /// Start of Basic Cycle Interrupt Line + SBCL: u1, + /// Start of Matrix Cycle Interrupt Line + SMCL: u1, + /// Change of Synchronization Mode Interrupt Line + CSML: u1, + /// Start of Gap Interrupt Line + SOGL: u1, + /// Register Time Mark Interrupt Line + RTMIL: u1, + /// Trigger Time Mark Event Internal Interrupt Line + TTMIL: u1, + /// Stop Watch Event Interrupt Line + SWEL: u1, + /// Global Time Wrap Interrupt Line + GTWL: u1, + /// Global Time Discontinuity Interrupt Line + GTDL: u1, + /// Global Time Error Interrupt Line + GTEL: u1, + /// Tx Count Underflow Interrupt Line + TXUL: u1, + /// Tx Count Overflow Interrupt Line + TXOL: u1, + /// Scheduling Error 1 Interrupt Line + SE1L: u1, + /// Scheduling Error 2 Interrupt Line + SE2L: u1, + /// Change Error Level Interrupt Line + ELCL: u1, + /// Initialization Watch Trigger Interrupt Line + IWTGL: u1, + /// Watch Trigger Interrupt Line + WTL: u1, + /// Application Watchdog Interrupt Line + AWL: u1, + /// Configuration Error Interrupt Line + CERL: u1, + padding: u13, }), - reserved32: [8]u8, - /// Flash option register - OPTR: mmio.Mmio(packed struct(u32) { - /// Read protection level - RDP: packed union { - raw: u8, - value: RDP, - }, - /// BOR reset Level - BOREN: u1, - /// These bits contain the VDD supply level threshold that activates the reset - BORF_LEV: packed union { - raw: u2, - value: BORF_LEV, - }, - /// These bits contain the VDD supply level threshold that releases the reset. - BORR_LEV: packed union { - raw: u2, - value: BORR_LEV, - }, - /// nRST_STOP - nRST_STOP: u1, - /// nRST_STDBY - nRST_STDBY: u1, - /// nRSTS_HDW - nRSTS_HDW: u1, - /// Independent watchdog selection - IDWG_SW: u1, - /// Independent watchdog counter freeze in Stop mode - IWDG_STOP: u1, - /// Independent watchdog counter freeze in Standby mode - IWDG_STDBY: u1, - /// Window watchdog selection - WWDG_SW: u1, - reserved22: u2, - /// SRAM parity check control - RAM_PARITY_CHECK: u1, - reserved24: u1, - /// nBOOT_SEL - nBOOT_SEL: u1, - /// Boot configuration - nBOOT1: u1, - /// nBOOT0 option bit - nBOOT0: u1, - /// NRST_MODE - NRST_MODE: packed union { - raw: u2, - value: NRST_MODE, - }, - /// Internal reset holder enable bit - IRHEN: u1, - padding: u2, + /// FDCAN TT Operation Status Register + TTOST: mmio.Mmio(packed struct(u32) { + /// Error Level + EL: u2, + /// Master State + MS: u2, + /// Synchronization State + SYS: u2, + /// Quality of Global Time Phase + QGTP: u1, + /// Quality of Clock Speed + QCS: u1, + /// Reference Trigger Offset + RTO: u8, + reserved22: u6, + /// Wait for Global Time Discontinuity + WGTD: u1, + /// Gap Finished Indicator + GFI: u1, + /// Time Master Priority + TMP: u3, + /// Gap Started Indicator + GSI: u1, + /// Wait for Event + WFE: u1, + /// Application Watchdog Event + AWE: u1, + /// Wait for External Clock Synchronization + WECS: u1, + /// Schedule Phase Lock + SPL: u1, }), - /// Flash PCROP zone A Start address register - PCROP1ASR: mmio.Mmio(packed struct(u32) { - /// PCROP1A area start offset - PCROP1A_STRT: u6, - padding: u26, + /// FDCAN TUR Numerator Actual Register + TURNA: mmio.Mmio(packed struct(u32) { + /// Numerator Actual Value + NAV: u18, + padding: u14, }), - /// Flash PCROP zone A End address register - PCROP1AER: mmio.Mmio(packed struct(u32) { - /// PCROP1A area end offset - PCROP1A_END: u6, - reserved31: u25, - /// PCROP area preserved when RDP level decreased - PCROP_RDP: u1, + /// FDCAN TT Local and Global Time Register + TTLGT: mmio.Mmio(packed struct(u32) { + /// Local Time + LT: u16, + /// Global Time + GT: u16, }), - /// Flash WRP area A address register - WRP1AR: mmio.Mmio(packed struct(u32) { - /// WRP area A start offset - WRP1A_STRT: u6, - reserved16: u10, - /// WRP area A end offset - WRP1A_END: u6, + /// FDCAN TT Cycle Time and Count Register + TTCTC: mmio.Mmio(packed struct(u32) { + /// Cycle Time + CT: u16, + /// Cycle Count + CC: u6, padding: u10, }), - /// Flash WRP area B address register - WRP1BR: mmio.Mmio(packed struct(u32) { - /// WRP area B start offset - WRP1B_STRT: u6, + /// FDCAN TT Capture Time Register + TTCPT: mmio.Mmio(packed struct(u32) { + /// Cycle Count Value + CCV: u6, reserved16: u10, - /// WRP area B end offset - WRP1B_END: u6, - padding: u10, + /// Stop Watch Value + SWV: u16, }), - /// Flash PCROP zone B Start address register - PCROP1BSR: mmio.Mmio(packed struct(u32) { - /// PCROP1B area start offset - PCROP1B_STRT: u6, - padding: u26, + /// FDCAN TT Cycle Sync Mark Register + TTCSM: mmio.Mmio(packed struct(u32) { + /// Cycle Sync Mark + CSM: u16, + padding: u16, }), - /// Flash PCROP zone B End address register - PCROP1BER: mmio.Mmio(packed struct(u32) { - /// PCROP1B area end offset - PCROP1B_END: u6, + reserved768: [444]u8, + /// FDCAN TT Trigger Select Register + TTTS: mmio.Mmio(packed struct(u32) { + /// Stop watch trigger input selection + SWTDEL: u2, + reserved4: u2, + /// Event trigger input selection + EVTSEL: u2, padding: u26, }), - reserved128: [68]u8, - /// Flash Security register - SECR: mmio.Mmio(packed struct(u32) { - /// Securable memory area size - SEC_SIZE: u5, - reserved16: u11, - /// used to force boot from user area - BOOT_LOCK: u1, - padding: u15, - }), }; }; - pub const spi_v2 = struct { - pub const BIDIMODE = enum(u1) { - /// 2-line unidirectional data mode selected - Unidirectional = 0x0, - /// 1-line bidirectional data mode selected - Bidirectional = 0x1, - }; - - pub const BIDIOE = enum(u1) { - /// Output disabled (receive-only mode) - Receive = 0x0, - /// Output enabled (transmit-only mode) - Transmit = 0x1, - }; - - pub const BR = enum(u3) { - /// f_PCLK / 2 - Div2 = 0x0, - /// f_PCLK / 4 - Div4 = 0x1, - /// f_PCLK / 8 - Div8 = 0x2, - /// f_PCLK / 16 - Div16 = 0x3, - /// f_PCLK / 32 - Div32 = 0x4, - /// f_PCLK / 64 - Div64 = 0x5, - /// f_PCLK / 128 - Div128 = 0x6, - /// f_PCLK / 256 - Div256 = 0x7, - }; - - pub const CHLEN = enum(u1) { - /// 16-bit wide - Bits16 = 0x0, - /// 32-bit wide - Bits32 = 0x1, - }; - - pub const CHSIDE = enum(u1) { - /// Channel left has to be transmitted or has been received - Left = 0x0, - /// Channel right has to be transmitted or has been received - Right = 0x1, - }; - - pub const CKPOL = enum(u1) { - /// I2S clock inactive state is low level - IdleLow = 0x0, - /// I2S clock inactive state is high level - IdleHigh = 0x1, - }; - - pub const CPHA = enum(u1) { - /// The first clock transition is the first data capture edge - FirstEdge = 0x0, - /// The second clock transition is the first data capture edge - SecondEdge = 0x1, - }; - - pub const CPOL = enum(u1) { - /// CK to 0 when idle - IdleLow = 0x0, - /// CK to 1 when idle - IdleHigh = 0x1, - }; - - pub const CRCL = enum(u1) { - /// 8-bit CRC length - Bits8 = 0x0, - /// 16-bit CRC length - Bits16 = 0x1, - }; - - pub const CRCNEXT = enum(u1) { - /// Next transmit value is from Tx buffer - TxBuffer = 0x0, - /// Next transmit value is from Tx CRC register - CRC = 0x1, + pub const can_fdcan_v1 = struct { + pub const ACT = enum(u2) { + /// Synchronizing: node is synchronizing on CAN communication. + SYNC = 0x0, + /// Idle: node is neither receiver nor transmitter. + IDLE = 0x1, + /// Receiver: node is operating as receiver. + RX = 0x2, + /// Transmitter: node is operating as transmitter. + TX = 0x3, }; - pub const DATLEN = enum(u2) { - /// 16-bit data length - Bits16 = 0x0, - /// 24-bit data length - Bits24 = 0x1, - /// 32-bit data length - Bits32 = 0x2, + pub const ANFE = enum(u2) { + /// Accept in Rx FIFO 0 + ACCEPT_FIFO_0 = 0x0, + /// Accept in Rx FIFO 1 + ACCEPT_FIFO_1 = 0x1, + /// Reject + REJECT = 0x2, _, }; - pub const DS = enum(u4) { - /// 4-bit - Bits4 = 0x3, - /// 5-bit - Bits5 = 0x4, - /// 6-bit - Bits6 = 0x5, - /// 7-bit - Bits7 = 0x6, - /// 8-bit - Bits8 = 0x7, - /// 9-bit - Bits9 = 0x8, - /// 10-bit - Bits10 = 0x9, - /// 11-bit - Bits11 = 0xa, - /// 12-bit - Bits12 = 0xb, - /// 13-bit - Bits13 = 0xc, - /// 14-bit - Bits14 = 0xd, - /// 15-bit - Bits15 = 0xe, - /// 16-bit - Bits16 = 0xf, + pub const ANFS = enum(u2) { + /// Accept in Rx FIFO 0 + ACCEPT_FIFO_0 = 0x0, + /// Accept in Rx FIFO 1 + ACCEPT_FIFO_1 = 0x1, + /// Reject + REJECT = 0x2, _, }; - pub const FRF = enum(u1) { - /// SPI Motorola mode - Motorola = 0x0, - /// SPI TI mode - TI = 0x1, - }; - - pub const FRLVL = enum(u2) { - /// Rx FIFO Empty - Empty = 0x0, - /// Rx 1/4 FIFO - Quarter = 0x1, - /// Rx 1/2 FIFO - Half = 0x2, - /// Rx FIFO full - Full = 0x3, - }; - - pub const FRXTH = enum(u1) { - /// RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) - Half = 0x0, - /// RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) - Quarter = 0x1, - }; - - pub const FTLVL = enum(u2) { - /// Tx FIFO Empty - Empty = 0x0, - /// Tx 1/4 FIFO - Quarter = 0x1, - /// Tx 1/2 FIFO - Half = 0x2, - /// Tx FIFO full - Full = 0x3, - }; - - pub const ISCFG = enum(u2) { - /// Slave - transmit - SlaveTx = 0x0, - /// Slave - receive - SlaveRx = 0x1, - /// Master - transmit - MasterTx = 0x2, - /// Master - receive - MasterRx = 0x3, - }; - - pub const ISMOD = enum(u1) { - /// SPI mode is selected - SPIMode = 0x0, - /// I2S mode is selected - I2SMode = 0x1, - }; - - pub const ISSTD = enum(u2) { - /// I2S Philips standard - Philips = 0x0, - /// MSB justified standard - MSB = 0x1, - /// LSB justified standard - LSB = 0x2, - /// PCM standard - PCM = 0x3, - }; - - pub const LDMA_RX = enum(u1) { - /// Number of data to transfer for receive is even - Even = 0x0, - /// Number of data to transfer for receive is odd - Odd = 0x1, + pub const LEC = enum(u3) { + /// No Error: No error occurred since LEC has been reset by successful reception or transmission. + NO_ERROR = 0x0, + /// Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. + STUFF = 0x1, + /// Form Error: A fixed format part of a received frame has the wrong format. + FORM = 0x2, + /// AckError: The message transmitted by the FDCAN was not acknowledged by another node. + ACK = 0x3, + /// Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant. + BIT_1 = 0x4, + /// Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). + BIT_0 = 0x5, + /// CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. + CRC = 0x6, + /// NoChange: Any read access to the Protocol status register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol status register. + NO_CHANGE = 0x7, }; - pub const LDMA_TX = enum(u1) { - /// Number of data to transfer for transmit is even - Even = 0x0, - /// Number of data to transfer for transmit is odd - Odd = 0x1, + pub const MSI = enum(u2) { + /// No FIFO selected + NO_FIFO = 0x0, + /// FIFO overrun + OVERRUN = 0x1, + /// Message stored in FIFO 0 + FIFO_0 = 0x2, + /// Message stored in FIFO 1 + FIFO_1 = 0x3, }; - pub const LSBFIRST = enum(u1) { - /// Data is transmitted/received with the MSB first - MSBFirst = 0x0, - /// Data is transmitted/received with the LSB first - LSBFirst = 0x1, + pub const PDIV = enum(u4) { + /// Divide by 1 + DIV_1 = 0x0, + /// Divide by 2 + DIV_2 = 0x1, + /// Divide by 4 + DIV_4 = 0x2, + /// Divide by 6 + DIV_6 = 0x3, + /// Divide by 8 + DIV_8 = 0x4, + /// Divide by 10 + DIV_10 = 0x5, + /// Divide by 12 + DIV_12 = 0x6, + /// Divide by 14 + DIV_14 = 0x7, + /// Divide by 16 + DIV_16 = 0x8, + /// Divide by 18 + DIV_18 = 0x9, + /// Divide by 20 + DIV_20 = 0xa, + /// Divide by 22 + DIV_22 = 0xb, + /// Divide by 24 + DIV_24 = 0xc, + /// Divide by 26 + DIV_26 = 0xd, + /// Divide by 28 + DIV_28 = 0xe, + /// Divide by 30 + DIV_30 = 0xf, }; - pub const MSTR = enum(u1) { - /// Slave configuration - Slave = 0x0, - /// Master configuration - Master = 0x1, + pub const TFQM = enum(u1) { + /// Tx FIFO operation + FIFO = 0x0, + /// Tx queue operation + QUEUE = 0x1, }; - pub const ODD = enum(u1) { - /// Real divider value is I2SDIV * 2 - Even = 0x0, - /// Real divider value is (I2SDIV * 2) + 1 - Odd = 0x1, + pub const TOS = enum(u2) { + /// Continuous operation + CONTINUOUS = 0x0, + /// Timeout controlled by Tx event FIFO + TX_EVENT_FIFO = 0x1, + /// Timeout controlled by Rx FIFO 0 + RX_FIFO_0 = 0x2, + /// Timeout controlled by Rx FIFO 1 + RX_FIFO_1 = 0x3, }; - pub const PCMSYNC = enum(u1) { - /// Short frame synchronisation - Short = 0x0, - /// Long frame synchronisation - Long = 0x1, + pub const TSS = enum(u2) { + /// Timestamp counter value always 0x0000 + ZERO = 0x0, + /// Timestamp counter value incremented according to TCP + INCREMENT = 0x1, + /// External timestamp counter from TIM3 value (tim3_cnt[0:15]) + EXTERNAL = 0x2, + _, }; - pub const RXONLY = enum(u1) { - /// Full duplex (Transmit and receive) - FullDuplex = 0x0, - /// Output disabled (Receive-only mode) - OutputDisabled = 0x1, + pub const TX = enum(u2) { + /// Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time + RESET = 0x0, + /// Sample point can be monitored at pin FDCANx_TX + SAMPLE_POINT = 0x1, + /// Dominant (0) level at pin FDCANx_TX + DOMINANT = 0x2, + /// Recessive (1) at pin FDCANx_TX + RECESSIVE = 0x3, }; - /// Serial peripheral interface - pub const SPI = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Clock phase - CPHA: packed union { - raw: u1, - value: CPHA, - }, - /// Clock polarity - CPOL: packed union { - raw: u1, - value: CPOL, - }, - /// Master selection - MSTR: packed union { - raw: u1, - value: MSTR, - }, - /// Baud rate control - BR: packed union { - raw: u3, - value: BR, - }, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: packed union { - raw: u1, - value: LSBFIRST, - }, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: packed union { - raw: u1, - value: RXONLY, - }, - /// CRC length - CRCL: packed union { - raw: u1, - value: CRCL, - }, - /// CRC transfer next - CRCNEXT: packed union { - raw: u1, - value: CRCNEXT, - }, - /// Hardware CRC calculation enable - CRCEN: u1, - /// Select the direction of transfer in bidirectional mode - BIDIOE: packed union { - raw: u1, - value: BIDIOE, - }, - /// Bidirectional data mode enable - BIDIMODE: packed union { - raw: u1, - value: BIDIMODE, - }, - padding: u16, + /// Controller area network with flexible data rate (FD) + pub const FDCAN = extern struct { + /// FDCAN core release register + CREL: mmio.Mmio(packed struct(u32) { + /// DAY + DAY: u8, + /// MON + MON: u8, + /// YEAR + YEAR: u4, + /// SUBSTEP + SUBSTEP: u4, + /// STEP + STEP: u4, + /// REL + REL: u4, }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - /// NSS pulse management - NSSP: u1, - /// Frame format - FRF: packed union { - raw: u1, - value: FRF, - }, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt enable - RXNEIE: u1, - /// Tx buffer empty interrupt enable - TXEIE: u1, - /// Data size - DS: packed union { - raw: u4, - value: DS, - }, - /// FIFO reception threshold - FRXTH: packed union { - raw: u1, - value: FRXTH, - }, - /// Last DMA transfer for reception - LDMA_RX: packed union { - raw: u1, - value: LDMA_RX, - }, - /// Last DMA transfer for transmission - LDMA_TX: packed union { - raw: u1, - value: LDMA_TX, - }, - padding: u17, + /// FDCAN endian register + ENDN: mmio.Mmio(packed struct(u32) { + /// Endianness test value. The endianness test value is 0x8765 4321 + ETV: u32, }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: packed union { - raw: u1, - value: CHSIDE, - }, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// frame format error - FRE: u1, - /// FIFO reception level - FRLVL: packed union { - raw: u2, - value: FRLVL, - }, - /// FIFO Transmission Level - FTLVL: packed union { + reserved12: [4]u8, + /// FDCAN data bit timing and prescaler register + DBTP: mmio.Mmio(packed struct(u32) { + /// Synchronization jump width. Must always be smaller than DTSEG2, valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1: tSJW = (DSJW + 1) x tq. + DSJW: u4, + /// Data time segment after sample point. Valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS2 = (DTSEG2 + 1) x tq + DTSEG2: u4, + /// Data time segment before sample point. Valid values are 0 to 31. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS1 = (DTSEG1 + 1) x tq + DTSEG1: u5, + reserved16: u3, + /// Data bit rate prescaler. The value by which the oscillator frequency is divided to generate the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31. The hardware interpreters this value as the value programmed plus 1 + DBRP: u5, + reserved23: u2, + /// Transceiver delay compensation + TDC: u1, + padding: u8, + }), + /// FDCAN test register + TEST: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Loop back mode + LBCK: u1, + /// Control of transmit pin + TX: packed union { raw: u2, - value: FTLVL, + value: TX, }, - padding: u19, - }), - /// data register - half-word sized - DR16: u32, - /// CRC polynomial register - CRCPR: mmio.Mmio(packed struct(u32) { - /// CRC polynomial register - CRCPOLY: u16, - padding: u16, + /// Receive pin. Monitors the actual value of pin FDCANx_RX + RX: u1, + padding: u24, }), - /// RX CRC register - RXCRCR: mmio.Mmio(packed struct(u32) { - /// Rx CRC register - RxCRC: u16, + /// FDCAN RAM watchdog register + RWD: mmio.Mmio(packed struct(u32) { + /// Watchdog configuration. Start value of the message RAM watchdog counter. With the reset value of 00, the counter is disabled. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of FDCAN_CCCR register are set to 1 + WDC: u8, + /// Watchdog value. Actual message RAM watchdog counter value + WDV: u8, padding: u16, }), - /// TX CRC register - TXCRCR: mmio.Mmio(packed struct(u32) { - /// Tx CRC register - TxCRC: u16, + /// FDCAN CC control register + CCCR: mmio.Mmio(packed struct(u32) { + /// Initialization + INIT: u1, + /// Configuration change enable + CCE: u1, + /// ASM restricted operation mode. The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted operation Mode after it has received a valid frame. In the optional Restricted operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time + ASM: u1, + /// Clock stop acknowledge + CSA: u1, + /// Clock stop request + CSR: u1, + /// Bus monitoring mode. Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time + MON: u1, + /// Disable automatic retransmission + DAR: u1, + /// Test mode enable + TEST: u1, + /// FD operation enable + FDOE: u1, + /// FDCAN bit rate switching + BRSE: u1, + reserved12: u2, + /// Protocol exception handling disable + PXHD: u1, + /// Edge filtering during bus integration + EFBI: u1, + /// If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame + TXP: u1, + /// Non ISO operation. If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0 + NISO: u1, padding: u16, }), - /// I2S configuration register - I2SCFGR: mmio.Mmio(packed struct(u32) { - /// Channel length (number of bits per audio channel) - CHLEN: packed union { - raw: u1, - value: CHLEN, + /// FDCAN nominal bit timing and prescaler register + NBTP: mmio.Mmio(packed struct(u32) { + /// Nominal time segment after sample point. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used + NTSEG2: u7, + reserved8: u1, + /// Nominal time segment before sample point. Valid values are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + NTSEG1: u8, + /// Bit rate prescaler. Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + NBRP: u9, + /// Nominal (re)synchronization jump width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + NSJW: u7, + }), + /// FDCAN timestamp counter configuration register + TSCC: mmio.Mmio(packed struct(u32) { + /// Timestamp select. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + TSS: packed union { + raw: u2, + value: TSS, }, - /// Data length to be transferred - DATLEN: packed union { + reserved16: u14, + /// Timestamp counter prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1 … 16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. In CAN FD mode the internal timestamp counter TCP does not provide a constant time base due to the different CAN bit times between arbitration phase and data phase. Thus CAN FD requires an external counter for timestamp generation (TSS = 10). These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + TCP: u4, + padding: u12, + }), + /// FDCAN timestamp counter value register + TSCV: mmio.Mmio(packed struct(u32) { + /// Timestamp counter. The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). When TSCC[TSS] = 01, the timestamp counter is incremented in multiples of CAN bit times [1 … 16] depending on the configuration of TSCC[TCP]. A wrap around sets interrupt flag IR[TSW]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access has no impact + TSC: u16, + padding: u16, + }), + /// FDCAN timeout counter configuration register + TOCC: mmio.Mmio(packed struct(u32) { + /// Timeout counter enable. This is a protected write (P) bit, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + ETOC: u1, + /// Timeout select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + TOS: packed union { raw: u2, - value: DATLEN, + value: TOS, }, - /// Steady state clock polarity - CKPOL: packed union { - raw: u1, - value: CKPOL, + reserved16: u13, + /// Timeout period. Start value of the timeout counter (down-counter). Configures the timeout period + TOP: u16, + }), + /// FDCAN timeout counter value register + TOCV: mmio.Mmio(packed struct(u32) { + /// Timeout counter. The timeout counter is decremented in multiples of CAN bit times [1 … 16] depending on the configuration of TSCC.TCP. When decremented to 0, interrupt flag IR.TOO is set and the timeout counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS + TOC: u16, + padding: u16, + }), + reserved64: [16]u8, + /// FDCAN error counter register + ECR: mmio.Mmio(packed struct(u32) { + /// Transmit error counter. Actual state of the transmit error counter, values between 0 and 255. When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented + TEC: u8, + /// Receive error counter. Actual state of the receive error counter, values between 0 and 127 + REC: u7, + /// Receive error passive + RP: u1, + /// CAN error logging. The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. Access type is RX: reset on read. + CEL: u8, + padding: u8, + }), + /// FDCAN protocol status register + PSR: mmio.Mmio(packed struct(u32) { + /// Last error code. The LEC indicates the type of the last error to occur on the CAN bus. This field is cleared to 0 when a message has been transferred (reception or transmission) without error. Access type is RS: set on read. + LEC: packed union { + raw: u3, + value: LEC, }, - /// I2S standard selection - I2SSTD: packed union { + /// Activity. Monitors the module’s CAN communication state + ACT: packed union { raw: u2, - value: ISSTD, + value: ACT, }, - reserved7: u1, - /// PCM frame synchronization - PCMSYNC: packed union { - raw: u1, - value: PCMSYNC, + /// Error passive + EP: u1, + /// Warning Sstatus + EW: u1, + /// Bus_Off status + BO: u1, + /// Data last error code. Type of last error that occurred in the data phase of a FDCAN format frame with its BRS flag set. Coding is the same as for LEC. This field is cleared to 0 when a FDCAN format frame with its BRS flag set has been transferred (reception or transmission) without error. Access type is RS: set on read. + DLEC: u3, + /// ESI flag of last received FDCAN message. This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read. + RESI: u1, + /// BRS flag of last received FDCAN message. This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read. + RBRS: u1, + /// Received FDCAN message. This bit is set independent of acceptance filtering. Access type is RX: reset on read. + REDL: u1, + /// Protocol exception event + PXE: u1, + reserved16: u1, + /// Transmitter delay compensation value. Position of the secondary sample point, defined by the sum of the measured delay from FDCAN_TX to FDCAN_RX and TDCR.TDCO. The SSP position is, in the data phase, the number of minimum time quanta (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq + TDCV: u7, + padding: u9, + }), + /// FDCAN transmitter delay compensation register + TDCR: mmio.Mmio(packed struct(u32) { + /// Transmitter delay compensation filter window length. Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would result in an earlier SSP position are ignored for transmitter delay measurements. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + TDCF: u7, + reserved8: u1, + /// Transmitter delay compensation offset. Offset value defining the distance between the measured delay from FDCAN_TX to FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + TDCO: u7, + padding: u17, + }), + reserved80: [4]u8, + /// FDCAN interrupt register + IR: mmio.Mmio(packed struct(u32) { + /// Rx FIFO X new message + RFN: u1, + /// Rx FIFO X full + RFF: u1, + /// Rx FIFO X message lost + RFL: u1, + reserved6: u3, + /// High-priority message + HPM: u1, + /// Transmission completed + TC: u1, + /// Transmission cancellation finished + TCF: u1, + /// Tx FIFO empty + TFE: u1, + /// Tx event FIFO New Entry + TEFN: u1, + /// Tx event FIFO full + TEFF: u1, + /// Tx event FIFO element lost + TEFL: u1, + /// Timestamp wraparound + TSW: u1, + /// Message RAM access failure. The flag is set when the Rx handler: has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx handler starts processing of the following message. was unable to write a message to the message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated. The partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the FDCAN is switched into Restricted operation Mode (see mode). To leave Restricted operation Mode, the Host CPU has to reset CCCR.ASM. + MRAF: u1, + /// Timeout occurred + TOO: u1, + /// Error logging overflow + ELO: u1, + /// Error passive + EP: u1, + /// Warning status + EW: u1, + /// Bus_Off status + BO: u1, + /// Watchdog interrupt + WDI: u1, + /// Protocol error in arbitration phase (nominal bit time is used) + PEA: u1, + /// Protocol error in data phase (data bit time is used) + PED: u1, + /// Access to reserved address + ARA: u1, + padding: u8, + }), + /// FDCAN interrupt enable register + IE: mmio.Mmio(packed struct(u32) { + /// Rx FIFO X new message interrupt enable + RFNE: u1, + /// Rx FIFO X full interrupt enable + RFFE: u1, + /// Rx FIFO X message lost interrupt enable + RFLE: u1, + reserved6: u3, + /// High-priority message interrupt enable + HPME: u1, + /// Transmission completed interrupt enable + TCE: u1, + /// Transmission cancellation finished interrupt enable + TCFE: u1, + /// Tx FIFO empty interrupt enable + TFEE: u1, + /// Tx event FIFO new entry interrupt enable + TEFNE: u1, + /// Tx event FIFO full interrupt enable + TEFFE: u1, + /// Tx event FIFO element lost interrupt enable + TEFLE: u1, + /// Timestamp wraparound interrupt enable + TSWE: u1, + /// Message RAM access failure interrupt enable + MRAFE: u1, + /// Timeout occurred interrupt enable + TOOE: u1, + /// Error logging overflow interrupt enable + ELOE: u1, + /// Error passive interrupt enable + EPE: u1, + /// Warning status interrupt enable + EWE: u1, + /// Bus_Off status enable + BOE: u1, + /// Watchdog interrupt enable + WDIE: u1, + /// Protocol error in arbitration phase enable + PEAE: u1, + /// Protocol error in data phase enable + PEDE: u1, + /// Access to reserved address enable + ARAE: u1, + padding: u8, + }), + /// FDCAN interrupt line select register + ILS: mmio.Mmio(packed struct(u32) { + /// RX FIFO bit grouping the following interruption. RFLL: Rx FIFO X message lost interrupt line RFFL: Rx FIFO X full interrupt line RFNL: Rx FIFO X new message interrupt line. + RXFIFO: u1, + reserved2: u1, + /// Status message bit grouping the following interruption. TCFL: Transmission cancellation finished interrupt line TCL: Transmission completed interrupt line HPML: High-priority message interrupt line. + SMSG: u1, + /// Tx FIFO ERROR grouping the following interruption. TEFLL: Tx event FIFO element lost interrupt line TEFFL: Tx event FIFO full interrupt line TEFNL: Tx event FIFO new entry interrupt line TFEL: Tx FIFO empty interrupt line. + TFERR: u1, + /// Interrupt regrouping the following interruption. TOOL: Timeout occurred interrupt line MRAFL: Message RAM access failure interrupt line TSWL: Timestamp wraparound interrupt line. + MISC: u1, + /// Bit and line error grouping the following interruption. EPL Error passive interrupt line ELOL: Error logging overflow interrupt line. + BERR: u1, + /// Protocol error grouping the following interruption. ARAL: Access to reserved address line PEDL: Protocol error in data phase line PEAL: Protocol error in arbitration phase line WDIL: Watchdog interrupt line BOL: Bus_Off status EWL: Warning status interrupt line. + PERR: u1, + padding: u25, + }), + /// FDCAN interrupt line enable register + ILE: mmio.Mmio(packed struct(u32) { + /// Enable interrupt line 0 + EINT0: u1, + /// Enable interrupt line 1 + EINT1: u1, + padding: u30, + }), + reserved128: [32]u8, + /// FDCAN global filter configuration register + RXGFC: mmio.Mmio(packed struct(u32) { + /// Reject remote frames extended. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + RRFE: u1, + /// Reject remote frames standard. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + RRFS: u1, + /// Accept non-matching frames extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + ANFE: packed union { + raw: u2, + value: ANFE, }, - /// I2S configuration mode - I2SCFG: packed union { + /// Accept Non-matching frames standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + ANFS: packed union { raw: u2, - value: ISCFG, + value: ANFS, }, - /// I2S Enabled - I2SE: u1, - /// I2S mode selection - I2SMOD: packed union { - raw: u1, - value: ISMOD, + reserved8: u2, + /// FIFO 1 operation mode (overwrite or blocking). This is a protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + F1OM: u1, + /// FIFO 0 operation mode (overwrite or blocking). This is protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + F0OM: u1, + reserved16: u6, + /// List size standard. >28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + LSS: u5, + reserved24: u3, + /// List size extended. >8: Values greater than 8 are interpreted as 8. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + LSE: u4, + padding: u4, + }), + /// FDCAN extended ID and mask register + XIDAM: mmio.Mmio(packed struct(u32) { + /// Extended ID mask. For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + EIDM: u29, + padding: u3, + }), + /// FDCAN high-priority message status register + HPMS: mmio.Mmio(packed struct(u32) { + /// Buffer index. Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = 1 + BIDX: u3, + reserved6: u3, + /// Message storage indicator + MSI: packed union { + raw: u2, + value: MSI, }, - /// Asynchronous start enable - ASTRTEN: u1, - padding: u19, + /// Filter index. Index of matching filter element. Range is 0 to RXGFC[LSS] - 1 or RXGFC[LSE] - 1 + FIDX: u5, + reserved15: u2, + /// Filter list. Indicates the filter list of the matching filter element + FLST: u1, + padding: u16, }), - /// I2S prescaler register - I2SPR: mmio.Mmio(packed struct(u32) { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the prescaler - ODD: packed union { + reserved144: [4]u8, + /// FDCAN Rx FIFO X status register + RXFS: mmio.Mmio(packed struct(u32) { + /// Rx FIFO X fill level. Number of elements stored in Rx FIFO X, range 0 to 3 + FFL: u4, + reserved8: u4, + /// Rx FIFO X get index. Rx FIFO X read index pointer, range 0 to 2 + FGI: u2, + reserved16: u6, + /// Rx FIFO X put index. Rx FIFO X write index pointer, range 0 to 2 + FPI: u2, + reserved24: u6, + /// Rx FIFO X full + FF: u1, + /// Rx FIFO X message lost. This bit is a copy of interrupt flag IR[RFL]. When IR[RFL] is reset, this bit is also reset + RFL: u1, + padding: u6, + }), + /// CAN Rx FIFO X acknowledge register + RXFA: mmio.Mmio(packed struct(u32) { + /// Rx FIFO X acknowledge index. After the Host has read a message or a sequence of messages from Rx FIFO X it has to write the buffer index of the last element read from Rx FIFO X to FAI. This sets the Rx FIFO X get index RXFS[FGI] to FAI + 1 and update the FIFO X fill level RXFS[FFL] + FAI: u3, + padding: u29, + }), + reserved192: [40]u8, + /// FDCAN Tx buffer configuration register + TXBC: mmio.Mmio(packed struct(u32) { + reserved24: u24, + /// Tx FIFO/queue mode. This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + TFQM: packed union { raw: u1, - value: ODD, + value: TFQM, }, - /// Master clock output enable - MCKOE: u1, - padding: u22, + padding: u7, + }), + /// FDCAN Tx FIFO/queue status register + TXFQS: mmio.Mmio(packed struct(u32) { + /// Tx FIFO free level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC[TFQM] = 1) + TFFL: u3, + reserved8: u5, + /// Tx FIFO get index. Tx FIFO read index pointer, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC.TFQM = 1) + TFGI: u2, + reserved16: u6, + /// Tx FIFO/queue put index. Tx FIFO/queue write index pointer, range 0 to 3 + TFQPI: u2, + reserved21: u3, + /// Tx FIFO/queue full + TFQF: u1, + padding: u10, + }), + /// FDCAN Tx buffer request pending register + TXBRP: mmio.Mmio(packed struct(u32) { + /// Transmission request pending. Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions + TRP: u1, + padding: u31, + }), + /// FDCAN Tx buffer add request register + TXBAR: mmio.Mmio(packed struct(u32) { + /// Add request. Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed + AR: u1, + padding: u31, + }), + /// FDCAN Tx buffer cancellation request register + TXBCR: mmio.Mmio(packed struct(u32) { + /// Cancellation request. Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset + CR: u1, + padding: u31, + }), + /// FDCAN Tx buffer transmission occurred register + TXBTO: mmio.Mmio(packed struct(u32) { + /// Transmission occurred.. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR + TO: u1, + padding: u31, + }), + /// FDCAN Tx buffer cancellation finished register + TXBCF: mmio.Mmio(packed struct(u32) { + /// Cancellation finished. Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR + CF: u1, + padding: u31, + }), + /// FDCAN Tx buffer transmission interrupt enable register + TXBTIE: mmio.Mmio(packed struct(u32) { + /// Transmission interrupt enable. Each Tx buffer has its own TIE bit + TIE: u1, + padding: u31, + }), + /// FDCAN Tx buffer cancellation finished interrupt enable register + TXBCIE: mmio.Mmio(packed struct(u32) { + /// Cancellation finished interrupt enable.. Each Tx buffer has its own CFIE bit + CFIE: u1, + padding: u31, + }), + /// FDCAN Tx event FIFO status register + TXEFS: mmio.Mmio(packed struct(u32) { + /// Event FIFO fill level. Number of elements stored in Tx event FIFO, range 0 to 3 + EFFL: u3, + reserved8: u5, + /// Event FIFO get index. Tx event FIFO read index pointer, range 0 to 3 + EFGI: u2, + reserved16: u6, + /// Event FIFO put index. Tx event FIFO write index pointer, range 0 to 3 + EFPI: u2, + reserved24: u6, + /// Event FIFO full + EFF: u1, + /// Tx event FIFO element lost. This bit is a copy of interrupt flag IR[TEFL]. When IR[TEFL] is reset, this bit is also reset. 0 No Tx event FIFO element lost 1 Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0 + TEFL: u1, + padding: u6, + }), + /// FDCAN Tx event FIFO acknowledge register + TXEFA: mmio.Mmio(packed struct(u32) { + /// Event FIFO acknowledge index. After the Host has read an element or a sequence of elements from the Tx event FIFO, it has to write the index of the last element read from Tx event FIFO to EFAI. This sets the Tx event FIFO get index TXEFS[EFGI] to EFAI + 1 and updates the FIFO 0 fill level TXEFS[EFFL] + EFAI: u2, + padding: u30, + }), + reserved256: [20]u8, + /// FDCAN CFG clock divider register + CKDIV: mmio.Mmio(packed struct(u32) { + /// input clock divider. The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 + PDIV: packed union { + raw: u4, + value: PDIV, + }, + padding: u28, }), }; }; - pub const adf_v1 = struct { - /// DFLT trigger mode. This bitfield is set and cleared by software. It is used to select the trigger mode of the DFLT0. - pub const ACQMOD = enum(u3) { - /// Asynchronous continuous acquisition mode. - AsynchronousContinuous = 0x0, - /// Asynchronous single-shot acquisition mode - AsynchronousSingleShot = 0x1, - /// Synchronous continuous acquisition mode. - SyncronousContinuous = 0x2, - /// Synchronous single-shot acquisition mode. - SyncronousSingleShot = 0x3, - /// Window continuous acquisition mode. - WindowContinuous = 0x4, - _, + pub const cec_v1 = struct { + /// HDMI-CEC controller. + pub const CEC = extern struct { + /// configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// Peripheral enable. + PE: u1, + /// Interrupt enable. + IE: u1, + /// Bit timing error mode. + BTEM: u1, + /// Bit period error mode. + BPEM: u1, + padding: u28, + }), + /// CEC own address register. + OAR: mmio.Mmio(packed struct(u32) { + /// Own address. + OA: u4, + padding: u28, + }), + /// Rx Data Register. + PRES: mmio.Mmio(packed struct(u32) { + /// CEC Rx Data Register. + PRESC: u14, + padding: u18, + }), + /// CEC error status register. + ESR: mmio.Mmio(packed struct(u32) { + /// Bit timing error. + BTE: u1, + /// Bit period error. + BPE: u1, + /// Rx block transfer finished error. + RBTFE: u1, + /// Start bit error. + SBE: u1, + /// Block acknowledge error. + ACKE: u1, + /// Line error. + LINE: u1, + /// Tx block transfer finished error. + TBTFE: u1, + padding: u25, + }), + /// CEC control and status register. + CSR: mmio.Mmio(packed struct(u32) { + /// Tx start of message. + TSOM: u1, + /// Tx end of message. + TEOM: u1, + /// Tx error. + TERR: u1, + /// Tx byte transfer request or block transfer finished. + TBTRF: u1, + /// Rx start of message. + RSOM: u1, + /// Rx end of message. + REOM: u1, + /// Rx error. + RERR: u1, + /// Rx byte/block transfer finished. + RBTF: u1, + padding: u24, + }), + /// CEC Tx data register. + TXD: mmio.Mmio(packed struct(u32) { + /// Tx Data register. + TXD: u8, + padding: u24, + }), + /// CEC Rx data register. + RXD: mmio.Mmio(packed struct(u32) { + /// Rx data. + RXD: u8, + padding: u24, + }), }; + }; - /// Bitstream selection. This bitfield is set and cleared by software. It is used to select the bitstream to be used by the DFLT0. - pub const BSSEL = enum(u5) { - /// bsx_r provided to DFLTy (and SCDy). - BS0_R = 0x0, - /// bsx_f provided to DFLTy (and SCDy). - BS0_F = 0x1, - /// bsx_r provided to DFLTy (and SCDy). - BS1_R = 0x2, - /// bsx_f provided to DFLTy (and SCDy). - BS1_F = 0x3, - /// bsx_r provided to DFLTy (and SCDy). - BS2_R = 0x4, - /// bsx_f provided to DFLTy (and SCDy). - BS2_F = 0x5, - /// bsx_r provided to DFLTy (and SCDy). - BS3_R = 0x6, - /// bsx_f provided to DFLTy (and SCDy). - BS3_F = 0x7, - /// bsx_r provided to DFLTy (and SCDy). - BS4_R = 0x8, - /// bsx_f provided to DFLTy (and SCDy). - BS4_F = 0x9, - /// bsx_r provided to DFLTy (and SCDy). - BS5_R = 0xa, - /// bsx_f provided to DFLTy (and SCDy). - BS5_F = 0xb, - /// bsx_r provided to DFLTy (and SCDy). - BS6_R = 0xc, - /// bsx_f provided to DFLTy (and SCDy). - BS6_F = 0xd, - /// bsx_r provided to DFLTy (and SCDy). - BS7_R = 0xe, - /// bsx_f provided to DFLTy (and SCDy). - BS7_F = 0xf, - /// bsx_r provided to DFLTy (and SCDy). - BS8_R = 0x10, - /// bsx_f provided to DFLTy (and SCDy). - BS8_F = 0x11, - /// bsx_r provided to DFLTy (and SCDy). - BS9_R = 0x12, - /// bsx_f provided to DFLTy (and SCDy). - BS9_F = 0x13, - /// bsx_r provided to DFLTy (and SCDy). - BS10_R = 0x14, - /// bsx_f provided to DFLTy (and SCDy). - BS10_F = 0x15, - /// bsx_r provided to DFLTy (and SCDy). - BS11_R = 0x16, - /// bsx_f provided to DFLTy (and SCDy). - BS11_F = 0x17, - /// bsx_r provided to DFLTy (and SCDy). - BS12_R = 0x18, - /// bsx_f provided to DFLTy (and SCDy). - BS12_F = 0x19, - /// bsx_r provided to DFLTy (and SCDy). - BS13_R = 0x1a, - /// bsx_f provided to DFLTy (and SCDy). - BS13_F = 0x1b, - /// bsx_r provided to DFLTy (and SCDy). - BS14_R = 0x1c, - /// bsx_f provided to DFLTy (and SCDy). - BS14_F = 0x1d, - /// bsx_r provided to DFLTy (and SCDy). - BS15_R = 0x1e, - /// bsx_f provided to DFLTy (and SCDy). - BS15_F = 0x1f, + pub const cec_v2 = struct { + /// CEC. + pub const CEC = extern struct { + /// CEC control register. + CR: mmio.Mmio(packed struct(u32) { + /// CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission. + CECEN: u1, + /// Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception. + TXSOM: u1, + /// Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message). + TXEOM: u1, + padding: u29, + }), + /// This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0. + CFGR: mmio.Mmio(packed struct(u32) { + /// Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods. + SFT: u3, + /// Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall. + RXTOL: u1, + /// Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software. + BRESTP: u1, + /// Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0. + BREGEN: u1, + /// Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0. + LBPEGEN: u1, + /// Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software. + BRDNOGEN: u1, + /// SFT Option Bit The SFTOPT bit is set and cleared by software. + SFTOPT: u1, + reserved16: u7, + /// Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received. + OAR: u15, + /// Listen mode LSTN bit is set and cleared by software. + LSTN: u1, + }), + /// CEC Tx data register. + TXDR: mmio.Mmio(packed struct(u32) { + /// Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1. + TXD: u8, + padding: u24, + }), + /// CEC Rx Data Register. + RXDR: mmio.Mmio(packed struct(u32) { + /// Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line. + RXD: u8, + padding: u24, + }), + /// CEC Interrupt and Status Register. + ISR: mmio.Mmio(packed struct(u32) { + /// Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1. + RXBR: u1, + /// End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1. + RXEND: u1, + /// Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1. + RXOVR: u1, + /// Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1. + BRE: u1, + /// Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1. + SBPE: u1, + /// Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1. + LBPE: u1, + /// Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1. + RXACKE: u1, + /// Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1. + ARBLST: u1, + /// Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1. + TXBR: u1, + /// End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1. + TXEND: u1, + /// Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1. + TXUDR: u1, + /// Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1. + TXERR: u1, + /// Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1. + TXACKE: u1, + padding: u19, + }), + /// CEC interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software. + RXBRIE: u1, + /// End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software. + RXENDIE: u1, + /// Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software. + RXOVRIE: u1, + /// Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software. + BREIE: u1, + /// Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software. + SBPEIE: u1, + /// Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software. + LBPEIE: u1, + /// Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software. + RXACKIE: u1, + /// Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software. + ARBLSTIE: u1, + /// Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software. + TXBRIE: u1, + /// Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software. + TXENDIE: u1, + /// Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software. + TXUDRIE: u1, + /// Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software. + TXERRIE: u1, + /// Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software. + TXACKIE: u1, + padding: u19, + }), }; + }; - /// CCK1 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin. - pub const CCKDIR = enum(u1) { - /// CCK is an input. - Input = 0x0, - /// CCK is an output. - Output = 0x1, + pub const comp_f3_v1 = struct { + pub const HYST = enum(u2) { + None = 0x0, + /// Low hysteresis + Low = 0x1, + /// Medium hysteresis + Medium = 0x2, + /// High hysteresis + High = 0x3, }; - /// Divider to control the CCK clock. This bit is set and reset by software. It is used to control the frequency of the bitstream clock on the CCK pin. - pub const CCKDIV = enum(u4) { - /// The ADF_CCK clock is adf_proc_ck. - DIV1 = 0x0, - /// The ADF_CCK clock is adf_proc_ck divided by 2. - DIV2 = 0x1, - /// The ADF_CCK clock is adf_proc_ck divided by 3. - DIV3 = 0x2, - /// The ADF_CCK clock is adf_proc_ck divided by 4. - DIV4 = 0x3, - /// The ADF_CCK clock is adf_proc_ck divided by 5. - DIV5 = 0x4, - /// The ADF_CCK clock is adf_proc_ck divided by 6. - DIV6 = 0x5, - /// The ADF_CCK clock is adf_proc_ck divided by 7. - DIV7 = 0x6, - /// The ADF_CCK clock is adf_proc_ck divided by 8. - DIV8 = 0x7, - /// The ADF_CCK clock is adf_proc_ck divided by 9. - DIV9 = 0x8, - /// The ADF_CCK clock is adf_proc_ck divided by 10. - DIV10 = 0x9, - /// The ADF_CCK clock is adf_proc_ck divided by 11. - DIV11 = 0xa, - /// The ADF_CCK clock is adf_proc_ck divided by 12. - DIV12 = 0xb, - /// The ADF_CCK clock is adf_proc_ck divided by 13. - DIV13 = 0xc, - /// The ADF_CCK clock is adf_proc_ck divided by 14. - DIV14 = 0xd, - /// The ADF_CCK clock is adf_proc_ck divided by 15. - DIV15 = 0xe, - /// The ADF_CCK clock is adf_proc_ck divided by 16. - DIV16 = 0xf, + pub const MODE = enum(u2) { + /// High Speed mode + HighSpeed = 0x0, + /// Medium Speed mode + MediumSpeed = 0x1, + /// Low Speed mode + LowSpeed = 0x2, + /// Very Low Speed mode + VeryLowSpeed = 0x3, }; - /// CCK clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin. - pub const CCKEN = enum(u1) { - /// Bitstream clock not generated. - NotGenerated = 0x0, - /// Bitstream clock generated on the CCK pin. - Generated = 0x1, + /// General purpose comparators. + pub const COMP = extern struct { + /// control and status register. + CSR: mmio.Mmio(packed struct(u32) { + /// Comparator enable. + EN: u1, + /// Comparator 1 non inverting input connection to DAC output. Only available on COMP1 + INP_DAC: u1, + /// Comparator mode. + MODE: packed union { + raw: u2, + value: MODE, + }, + /// Comparator inverting input selection. + INSEL: u3, + /// Window mode enable. Only available on COMP2 + WNDWEN: u1, + /// Comparator output selection. + OUTSEL: u3, + /// Comparator output polarity. + POL: u1, + /// Comparator hysteresis. + HYST: packed union { + raw: u2, + value: HYST, + }, + /// Comparator output. + OUT: u1, + /// Comparator lock. + LOCK: u1, + padding: u16, + }), }; + }; - /// Select the CIC order. This bitfield is set and cleared by software. It is used to select the MCIC order. - pub const CICMOD = enum(u3) { - /// MCIC configured in single Sinc4 filter. - SINC4 = 0x4, - /// MCIC configured in single Sinc5 filter. - SINC5 = 0x5, + pub const comp_h5 = struct { + pub const BLANKING = enum(u4) { + NoBlanking = 0x0, + Tim1Oc5 = 0x1, + Tim2Oc3 = 0x2, + Tim3Oc3 = 0x3, + Tim3Oc4 = 0x4, + Lptim1Ch2 = 0x5, + Lptim2Ch2 = 0x6, _, }; - /// Clock generator mode. This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1). - pub const CKGMOD = enum(u1) { - /// The kernel clock is provided to the dividers as soon as CKGDEN is set to 1. - Immediate = 0x0, - /// The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met. - Trigger = 0x1, + pub const HYST = enum(u2) { + None = 0x0, + Low = 0x1, + Medium = 0x2, + High = 0x3, }; - /// Data capture mode. This bitfield is set and cleared by software. It is used to define in which conditions, the samples provided by DLFT0 are stored into the memory. - pub const DATCAP = enum(u2) { - /// Samples from DFLT0 not transfered into the memory. - Disabled = 0x0, - /// Samples from DFLT0 transfered into the memory when SAD is in DETECT state. - OnDetected = 0x1, - /// Samples from DFLT0 transfered into memory when SAD and DFLT0 are enabled. - Enabled = 0x2, + pub const INMSEL = enum(u4) { + VRef_1over4 = 0x0, + VRef_1over2 = 0x1, + VRef_3over4 = 0x2, + VRef = 0x3, + Dac1Out1 = 0x4, + Inm1 = 0x5, + Inm2 = 0x6, + Inm3 = 0x7, + VSense = 0x8, + VBat_1over4 = 0x9, _, }; - /// Source data for the digital filter. - pub const DATSRC = enum(u2) { - /// Stream coming from the BSMX selected - BSMX = 0x0, - /// Stream coming from the ADCITF1 selected - ADCITF1 = 0x2, - /// Stream coming from the ADCITF2 selected - ADCITF2 = 0x3, - _, + pub const PWRMODE = enum(u2) { + /// High speed / full power + High = 0x0, + /// Medium speed / medium power + Medium = 0x1, + /// Medium speed / medium power + MediumEither = 0x2, + /// Ultra low power / ultra-low-power + Low = 0x3, }; - /// Sound trigger event configuration. This bit is set and cleared by software. It is used to define if the sddet_evt event is generated only when the SAD enters to MONITOR state or when the SAD enters or exits the DETECT state. - pub const DETCFG = enum(u1) { - /// sddet_evt generated when SAD enters the MONITOR state. - Monitor = 0x0, - /// sddet_evt generated when SAD enters or exits the DETECT state. - Detect = 0x1, + /// Comparator. + pub const COMP = extern struct { + /// Comparator status register. + SR: mmio.Mmio(packed struct(u32) { + /// COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect. + CVAL: u1, + reserved16: u15, + /// COMP Channel1 interrupt flag This bit is set by hardware when the COMP Channel1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register. + CIF: u1, + padding: u15, + }), + /// Comparator interrupt clear flag register. + ICFR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Clear COMP Channel1 interrupt flag Writing 1 clears the C1IF flag in the COMP_SR register. + CCIF: u1, + padding: u15, + }), + reserved12: [4]u8, + /// Comparator configuration register 1. + CFGR1: mmio.Mmio(packed struct(u32) { + /// COMP Channel1 enable This bit is set and cleared by software (only if LOCK not set). It enables the COMP-Channel1. + EN: u1, + /// Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler. If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level VREF_COMP (similar to VREFINT). If SCALEN and BRGEN are set, the four scaler outputs provide VREF_COMP, 3/4-VREF_COMP, 1/2-VREF_COMP and 1/4-VREF_COMP levels, respectively. + BRGEN: u1, + /// Voltage scaler enable This bit is set and cleared by software (only if LOCK not set). This bit enables the VREFINT scaler for the COMP channels. + SCALEN: u1, + /// COMP channel1 polarity selection This bit is set and cleared by software (only if LOCK not set). It inverts COMP channel1 polarity. + POLARITY: u1, + reserved6: u2, + /// COMP channel1 interrupt enable This bit is set and cleared by software (only if LOCK not set). This bit enable the interrupt generation of the COMP channel1. + ITEN: u1, + reserved8: u1, + /// COMP channel1 hysteresis selection These bits are set and cleared by software (only if LOCK not set). They select the hysteresis voltage of the COMP channel1. + HYST: packed union { + raw: u2, + value: HYST, + }, + reserved12: u2, + /// Power mode of the COMP channel1 These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the COMP channel1. + PWRMODE: packed union { + raw: u2, + value: PWRMODE, + }, + reserved16: u2, + /// COMP channel1 inverting input selection These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of the COMP channel. Note: See Table-146: COMP1 inverting input assignment for more details. + INMSEL: packed union { + raw: u4, + value: INMSEL, + }, + /// COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. Note: See Table-145: COMP1 noninverting input assignment for more details. + INPSEL1: u1, + reserved22: u1, + /// COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of the COMP channel. See Table-145: COMP1 noninverting input assignment for more details. + INPSEL2: u1, + reserved24: u1, + /// COMP Channel1 blanking source selection Bits of this field are set and cleared by software (only if LOCK not set). The field selects the input source for COMP Channel1 output blanking: All other values: reserved. + BLANKING: packed union { + raw: u4, + value: BLANKING, + }, + reserved31: u3, + /// Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR1[31:0]. + LOCK: u1, + }), + /// Comparator configuration register 2. + CFGR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// COMP non-inverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. See Table-145: COMP1 noninverting input assignment for more details. + INPSEL0: u1, + reserved31: u26, + /// Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR2[31:0]. + LOCK: u1, + }), }; + }; - /// Frame size. This bitfield is set and cleared by software. it is used to define the size of one frame and also to define how many samples are taken into account to compute the short-term signal level. - pub const FRSIZE = enum(u3) { - /// 8 sample. - Samples8 = 0x0, - /// 16 samples. - Samples16 = 0x1, - /// 32 samples. - Samples32 = 0x2, - /// 64 samples. - Samples64 = 0x3, - /// 128 samples. - Samples128 = 0x4, - /// 256 samples. - Samples256 = 0x5, - /// 512 samples. - Samples512 = 0x6, + pub const comp_h7_a = struct { + pub const BLANKING = enum(u4) { + NoBlanking = 0x0, + Tim1Oc5 = 0x1, + Tim2Oc3 = 0x2, + Tim3Oc3 = 0x3, + Tim3Oc4 = 0x4, + Tim8Oc5 = 0x5, + Tim15Oc1 = 0x6, _, }; - /// Hangover time window. This bitfield is set and cleared by software. It is used to select the hangover time window. - pub const HGOVR = enum(u3) { - /// SAD back to MONITOR state if sound is below threshold for 4 frames. - @"Frames 4" = 0x0, - /// SAD back to MONITOR state if sound is below threshold for 4 frames. - @"Frames 8" = 0x1, - /// SAD back to MONITOR state if sound is below threshold for 4 frames. - @"Frames 16" = 0x2, - /// SAD back to MONITOR state if sound is below threshold for 4 frames. - @"Frames 32" = 0x3, - /// SAD back to MONITOR state if sound is below threshold for 4 frames. - @"Frames 64" = 0x4, - /// SAD back to MONITOR state if sound is below threshold for 4 frames. - @"Frames 128" = 0x5, - /// SAD back to MONITOR state if sound is below threshold for 4 frames. - @"Frames 256" = 0x6, - /// SAD back to MONITOR state if sound is below threshold for 4 frames. - @"Frames 512" = 0x7, + pub const HYST = enum(u2) { + None = 0x0, + Low = 0x1, + Medium = 0x2, + High = 0x3, }; - /// High-pass filter cut-off frequency. This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F PCM represents the sampling frequency at HPF input. - pub const HPFC = enum(u2) { - /// Cut-off frequency = 0.000625 x FPCM. - Low = 0x0, - /// Cut-off frequency = 0.00125 x FPCM. - Medium = 0x1, - /// Cut-off frequency = 0.00250 x FPCM - High = 0x2, - /// Cut-off frequency = 0.00950 x FPCM - Maximum = 0x3, - }; - - /// LFRNB. This bitfield is set and cleared by software. It is used to define the number of learning frames to perform the first estimate of the noise level. - pub const LFRNB = enum(u3) { - /// 2 samples. - @"Frames 2" = 0x0, - /// 4 samples. - @"Frames 4" = 0x1, - /// 8 samples. - @"Frames 8" = 0x2, - /// 16 samples. - @"Frames 16" = 0x3, - /// 32 samples. - @"Frames 32" = 0x4, + pub const INMSEL = enum(u4) { + VRef_1over4 = 0x0, + VRef_1over2 = 0x1, + VRef_3over4 = 0x2, + VRef = 0x3, + Inm4 = 0x4, + Inm5 = 0x5, + Inm6 = 0x6, + Inm7 = 0x7, + Inm8 = 0x8, + Inm9 = 0x9, _, }; - /// Reshaper filter decimation ratio. This bitfield is set and cleared by software. It is used to select the decimation ratio of the reshaper filter. - pub const RSFLTD = enum(u1) { - /// Decimation ratio is 4 (default value). - Decimation4 = 0x0, - /// Decimation ratio is 1. - Decimation1 = 0x1, + pub const INPSEL = enum(u1) { + INP1 = 0x0, + INP2 = 0x1, }; - /// RXFIFO threshold selection. This bitfield is set and cleared by software. It is used to select the RXFIFO threshold. - pub const RXFIFO = enum(u1) { - /// RXFIFO threshold event generated when the RXFIFO is not empty - NotEmpty = 0x0, - /// RXFIFO threshold event generated when the RXFIFO is half-full - HalfFull = 0x1, + pub const PWRMODE = enum(u2) { + /// High speed / full power + High = 0x0, + /// Medium speed / medium power + Medium = 0x1, + /// Medium speed / medium power + MediumEither = 0x2, + /// Ultra low power / ultra-low-power + Low = 0x3, }; - /// SAD working mode. This bitfield is set and cleared by software. It is used to define the way the SAD works - pub const SADMOD = enum(u2) { - /// Threshold value computed according to the estimated ambient noise. The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a voice activity detector. - ThresholdEstimatedAmbientNoise = 0x0, - /// Threshold value equal to ANMIN[12:0], multiplied by the gain selected by SNTHR[3:0] The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a sound detector. - ThresholdMinimumNoiselevel = 0x1, - /// Threshold value given by 4 x ANMIN[12:0]. The SAD triggers when the estimated ambient noise (ANLVL), multiplied by the gain selected by SNTHR[3:0] is bigger than the defined threshold. In this mode, the SAD is working like an ambient noise estimator. Hysteresis function cannot be used in this mode. - ThresholdMinimumNoiselevelx4 = 0x2, - _, + /// COMP1. + pub const COMP = extern struct { + /// Comparator status register. + SR: mmio.Mmio(packed struct(u32) { + /// COMP channel 1 output status bit. + CVAL: u1, + reserved16: u15, + /// COMP channel 1 Interrupt Flag. + CIF: u1, + padding: u15, + }), + /// Comparator interrupt clear flag register. + ICFR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Clear COMP channel 1 Interrupt Flag. + CCIF: u1, + padding: u15, + }), + /// Comparator option register. + OR: mmio.Mmio(packed struct(u32) { + /// Selection of source for alternate function of output ports. + AFOP: u11, + padding: u21, + }), + /// Comparator configuration register 1. + CFGR1: mmio.Mmio(packed struct(u32) { + /// COMP channel 1 enable bit. + EN: u1, + /// Scaler bridge enable. + BRGEN: u1, + /// Voltage scaler enable bit. + SCALEN: u1, + /// COMP channel 1 polarity selection bit. + POLARITY: u1, + reserved6: u2, + /// COMP channel 1 interrupt enable. + ITEN: u1, + reserved8: u1, + /// COMP channel 1 hysteresis selection bits. + HYST: packed union { + raw: u2, + value: HYST, + }, + reserved12: u2, + /// Power Mode of the COMP channel 1. + PWRMODE: packed union { + raw: u2, + value: PWRMODE, + }, + reserved16: u2, + /// COMP channel 1 inverting input selection field. + INMSEL: packed union { + raw: u4, + value: INMSEL, + }, + /// COMP channel 1 non-inverting input selection bit. + INPSEL: packed union { + raw: u1, + value: INPSEL, + }, + reserved24: u3, + /// COMP channel 1 blanking source selection bits. + BLANKING: packed union { + raw: u4, + value: BLANKING, + }, + reserved31: u3, + /// Lock bit. + LOCK: u1, + }), + /// Comparator configuration register 2. + CFGR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Window comparator mode selection bit. + WINMODE: u1, + padding: u27, + }), }; + }; - /// SAD state. This bitfield is set and cleared by hardware. It indicates the SAD state and is meaningful only when SADEN = 1. - pub const SADST = enum(u2) { - /// SAD in LEARN state. - Learn = 0x0, - /// SAD in MONITOR state. - Monitor = 0x1, - /// SAD in DETECT state. - Detect = 0x2, + pub const comp_h7_b = struct { + pub const BLANKING = enum(u4) { + NoBlanking = 0x0, + Tim1Oc5 = 0x1, + Tim2Oc3 = 0x2, + Tim3Oc3 = 0x3, + Tim3Oc4 = 0x4, + Tim8Oc5 = 0x5, + Tim15Oc1 = 0x6, _, }; - /// Serial clock source. This bitfield is set and cleared by software. It is used to select the clock source of the serial interface. - pub const SCKSRC = enum(u2) { - /// Serial clock source is CCK0. - CCK0 = 0x0, - /// Serial clock source is CCK1. - CCK1 = 0x1, - /// Serial clock source is CCI0. - CKI0 = 0x2, - /// Serial clock source is CCI1. - CKI1 = 0x3, - }; - - /// Serial interface mode. This bitfield is set and cleared by software. It is used to select the serial interface mode. - pub const SITFMOD = enum(u2) { - /// LF_MASTER SPI mode. - MasterSPI = 0x0, - /// Normal SPI mode. - NormalSPI = 0x1, - /// Manchester mode rising edge = logic 0, falling edge = logic 1. - ManchesterFalling = 0x2, - /// Manchester mode rising edge = logic 1, falling edge = logic 0. - ManchesterRising = 0x3, + pub const HYST = enum(u2) { + None = 0x0, + Low = 0x1, + Medium = 0x2, + High = 0x3, }; - /// SNTHR. This bitfield is set and cleared by software. It is used to select the gain to be applied at CIC output. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this bitfield informs the application on the current gain value. - pub const SNTHR = enum(u4) { - /// Threshold is 3.5 dB higher than ANLVL - @"NOISE PLUS 3_5" = 0x0, - /// Threshold is 6.0 dB higher than ANLVL - @"NOISE PLUS 6_0" = 0x1, - /// Threshold is 9.5 dB higher than ANLVL - @"NOISE PLUS 9_5" = 0x2, - /// Threshold is 12 dB higher than ANLVL - @"NOISE PLUS 12" = 0x3, - /// Threshold is 15.6 dB higher than ANLVL - @"NOISE PLUS 15_6" = 0x4, - /// Threshold is 18 dB higher than ANLVL - @"NOISE PLUS 18" = 0x5, - /// Threshold is 21.6 dB higher than ANLVL - @"NOISE PLUS 21_6" = 0x6, - /// Threshold is 24.1 dB higher than ANLVL - @"NOISE PLUS 24_1" = 0x7, - /// Threshold is 27.6 dB higher than ANLVL - @"NOISE PLUS 27_6" = 0x8, - /// Threshold is 30.1 dB higher than ANLVL - @"NOISE PLUS 30_1" = 0x9, - _, + pub const INMSEL = enum(u3) { + VRef_1over4 = 0x0, + VRef_1over2 = 0x1, + VRef_3over4 = 0x2, + VRef = 0x3, + Inm1 = 0x4, + Inm2 = 0x5, + COMPx_Inm1 = 0x6, + COMPx_Inm2 = 0x7, }; - /// CKGEN trigger sensitivity selection. This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0. - pub const TRGSENS = enum(u1) { - /// A rising edge event triggers the activation of CKGEN dividers. - RisingEdge = 0x0, - /// A falling edge even triggers the activation of CKGEN dividers. - FallingEdge = 0x1, + pub const INPSEL = enum(u1) { + INP1 = 0x0, + INP2 = 0x1, }; - /// Digital filter trigger signal selection. - pub const TRGSRC = enum(u4) { - /// TRGO Selected. - TRGO = 0x0, - /// adf_trg1 selected. - TRG1 = 0x2, - _, + pub const PWRMODE = enum(u2) { + /// High speed / full power + High = 0x0, + /// Medium speed / medium power + Medium = 0x1, + /// Medium speed / medium power + MediumEither = 0x2, + /// Ultra low power / ultra-low-power + Low = 0x3, }; - /// ADF. - pub const ADF = extern struct { - /// ADF Global Control Register. - GCR: mmio.Mmio(packed struct(u32) { - /// Trigger output control Set by software and reset by. - TRGO: u1, - padding: u31, + /// COMP1. + pub const COMP = extern struct { + /// Comparator status register. + SR: mmio.Mmio(packed struct(u32) { + /// COMP channel 1 output status bit. + CVAL: u1, + reserved16: u15, + /// COMP channel 1 Interrupt Flag. + CIF: u1, + padding: u15, }), - /// ADF clock generator control register. - CKGCR: mmio.Mmio(packed struct(u32) { - /// Clock generator dividers enable. - CKGDEN: u1, - /// CCK0 clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin. - CCK0EN: packed union { - raw: u1, - value: CCKEN, - }, - /// CCK1 clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin. - CCK1EN: packed union { - raw: u1, - value: CCKEN, - }, - reserved4: u1, - /// Clock generator mode. This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1). - CKGMOD: packed union { - raw: u1, - value: CKGMOD, - }, - /// CCK0 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK0 pin. - CCK0DIR: packed union { - raw: u1, - value: CCKDIR, - }, - /// CCK1 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin. - CCK1DIR: packed union { - raw: u1, - value: CCKDIR, - }, - reserved8: u1, - /// CKGEN trigger sensitivity selection. This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0. - TRGSENS: packed union { - raw: u1, - value: TRGSENS, - }, - reserved12: u3, - /// Digital filter trigger signal selection. This bit is set and cleared by software. It is used to select the trigger signal for the digital filter. This bit is not significant if the CKGMOD = 0. - TRGSRC: packed union { - raw: u4, - value: TRGSRC, - }, - /// Divider to control the CCK clock. - CCKDIV: packed union { - raw: u4, - value: CCKDIV, - }, - reserved24: u4, - /// Divider to control the serial interface clock. - PROCDIV: u7, - /// Clock generator active flag. - CKGACTIVE: u1, + /// Comparator interrupt clear flag register. + ICFR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Clear COMP channel 1 Interrupt Flag. + CCIF: u1, + padding: u15, }), - reserved128: [120]u8, - /// ADF serial interface control register 0. - SITFCR: mmio.Mmio(packed struct(u32) { - SITFEN: u1, - SCKSRC: packed union { + /// Comparator option register. + OR: mmio.Mmio(packed struct(u32) { + /// Selection of source for alternate function of output ports. + AFOP: u11, + padding: u21, + }), + /// Comparator configuration register 1. + CFGR1: mmio.Mmio(packed struct(u32) { + /// COMP channel 1 enable bit. + EN: u1, + /// Scaler bridge enable. + BRGEN: u1, + /// Voltage scaler enable bit. + SCALEN: u1, + /// COMP channel 1 polarity selection bit. + POLARITY: u1, + reserved6: u2, + /// COMP channel 1 interrupt enable. + ITEN: u1, + reserved8: u1, + /// COMP channel 1 hysteresis selection bits. + HYST: packed union { raw: u2, - value: SCKSRC, + value: HYST, }, - reserved4: u1, - SITFMOD: packed union { + reserved12: u2, + /// Power Mode of the COMP channel 1. + PWRMODE: packed union { raw: u2, - value: SITFMOD, + value: PWRMODE, }, - reserved8: u2, - /// Manchester symbol threshold/SPI threshold. This bitfield is set and cleared by software. It is used for Manchester mode to define the expected symbol threshold levels (seer to Manchester mode for details on computation). In addition this bitfield is used to define the timeout value for the clock absence detection in Normal SPI mode. STH[4:0] values lower than four are invalid. - STH: u5, - reserved31: u18, - /// SITFACTIVE. - SITFACTIVE: u1, - }), - /// ADF bitstream matrix control register 0. - BSMXCR: mmio.Mmio(packed struct(u32) { - /// Bitstream selection. - BSSEL: packed union { - raw: u5, - value: BSSEL, + reserved16: u2, + /// COMP channel 1 inverting input selection field. + INMSEL: packed union { + raw: u3, + value: INMSEL, }, - reserved31: u26, - /// BSMX active flag. This bit is set and cleared by hardware. It is used by the application to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when BSMXACTIVE is set to 0. This BSMXACTIVE flag cannot go to 0 if DFLT0 is enabled. - BSMXACTIVE: u1, - }), - /// ADF digital filter control register 0. - DFLTCR: mmio.Mmio(packed struct(u32) { - /// DFLT enable. This bit is set and reset by software. It is used to enable the digital filter. - DFLTEN: u1, - /// DMA requests enable. This bit is set and reset by software. It is used to control the generation of DMA request to transfer the processed samples into the memory. - DMAEN: u1, - /// RXFIFO threshold selection. - FTH: packed union { + reserved20: u1, + /// COMP channel 1 non-inverting input selection bit. + INPSEL: packed union { raw: u1, - value: RXFIFO, + value: INPSEL, }, - reserved4: u1, - /// DFLT trigger mode. - ACQMOD: packed union { - raw: u3, - value: ACQMOD, + reserved24: u3, + /// COMP channel 1 blanking source selection bits. + BLANKING: packed union { + raw: u4, + value: BLANKING, }, - reserved12: u5, - /// DFLT trigger signal selection. - TRGSRC: u4, - reserved20: u4, - /// Number of samples to be discarded. - NBDIS: u8, - reserved30: u2, - /// DFLT run status flag. - DFLTRUN: u1, - /// DFLT active flag. - DFLTACTIVE: u1, + reserved31: u3, + /// Lock bit. + LOCK: u1, }), - /// ADF digital filer configuration register 0. - DFLTCICR: mmio.Mmio(packed struct(u32) { - /// Source data for the digital filter. - DATSRC: packed union { - raw: u2, - value: DATSRC, - }, - reserved4: u2, - /// Select the CIC order. - CICMOD: packed union { - raw: u3, - value: CICMOD, - }, - reserved8: u1, - /// CIC decimation ratio selection. This bitfield is set and cleared by software.It is used to select the CIC decimation ratio. A decimation ratio smaller than two is not allowed. The decimation ratio is given by (CICDEC+1). - MCICD: u9, - reserved20: u3, - /// Scaling factor selection. This bitfield is set and cleared by software. It is used to select the gain to be applied at CIC output. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this bitfield informs the application on the current gain value. - SCALE: u6, - padding: u6, + /// Comparator configuration register 2. + CFGR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Window comparator mode selection bit. + WINMODE: u1, + padding: u27, }), - /// ADF reshape filter configuration register 0. - DFLTRSFR: mmio.Mmio(packed struct(u32) { - /// Reshaper filter bypass. - RSFLTBYP: u1, + }; + }; + + pub const comp_u0 = struct { + pub const BLANKING = enum(u5) { + /// No blanking. + NoBlanking = 0x0, + /// TIM1 OC4 enabled as blanking source + TIM1OC4 = 0x1, + /// TIM1 OC5 enabled as blanking source + TIM1OC5 = 0x2, + /// TIM5 OC3 enabled as blanking source + TIM2OC3 = 0x4, + /// TIM3 OC3 enabled as blanking source + TIM3OC3 = 0x8, + /// TIM15 OC2 enabled as blanking source + TIM15OC2 = 0x10, + _, + }; + + pub const HYST = enum(u2) { + None = 0x0, + Low = 0x1, + Medium = 0x2, + High = 0x3, + }; + + pub const PWRMODE = enum(u2) { + /// High speed / full power. + HighSpeed = 0x0, + /// Medium speed / medium power. + MediumSpeed = 0x1, + /// Very-low speed / ultra-low power. + LowSpeed = 0x3, + _, + }; + + pub const Polarity = enum(u1) { + /// Output is not inverted. + NotInverted = 0x0, + /// Output is inverted. + Inverted = 0x1, + }; + + pub const WindowMode = enum(u1) { + /// Signal selected with INPSEL[2:0] bitfield of this register. + ThisInpsel = 0x0, + /// Signal selected with INPSEL[2:0] bitfield of the other register (required for window mode). + OtherInpsel = 0x1, + }; + + pub const WindowOut = enum(u1) { + /// Comparator 1 value. + COMP1_VALUE = 0x0, + /// Comparator 1 value XOR comparator 2 value (required for window mode). + @"COMP1_VALUE XOR COMP2_VALUE" = 0x1, + }; + + /// Comparator. + pub const COMP = extern struct { + /// Comparator control and status register. + CSR: mmio.Mmio(packed struct(u32) { + /// Enable + EN: u1, reserved4: u3, - /// Reshaper filter decimation ratio. - RSFLTD: packed union { + /// Input minus selection bits. + INMSEL: u4, + /// Input plus selection bit. + INPSEL: u3, + /// Comparator 1 noninverting input selector for window mode. + WINMODE: packed union { raw: u1, - value: RSFLTD, - }, - reserved7: u2, - /// High-pass filter bypass. This bit is set and cleared by software. It is used to bypass the high-pass filter. - HPFBYP: u1, - /// High-pass filter cut-off frequency. This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F PCM represents the sampling frequency at HPF input. - HPFC: packed union { - raw: u2, - value: HPFC, + value: WindowMode, }, - padding: u22, - }), - reserved164: [16]u8, - /// ADF delay control register 0. - DLYCR: mmio.Mmio(packed struct(u32) { - /// Delay to apply to a bitstream. This bitfield is set and cleared by software. It defines the number of input samples that are skipped. Skipping is applied immediately after writing to this bitfield, if SKPBF = 0 and DFLTEN = 1. If SKPBF = 1, the value written into the register is ignored by the delay state machine. - SKPDLY: u7, - reserved31: u24, - /// Skip busy flag. - SKPBF: u1, - }), - reserved172: [4]u8, - /// ADF DFLT0 interrupt enable register. - DFLTIER: mmio.Mmio(packed struct(u32) { - /// RXFIFO threshold interrupt enable. - FTHIE: u1, - /// Data overflow interrupt enable. - DOVRIE: u1, - reserved9: u7, - /// Saturation detection interrupt enable. - SATIE: u1, - /// Clock absence detection interrupt enable. - CKABIE: u1, - /// Reshape filter overrun interrupt enable. - RFOVRIE: u1, - /// Sound activity detection interrupt enable. - SDDETIE: u1, - /// SAD sound-level value ready enable. - SDLVLIE: u1, - padding: u18, - }), - /// ADF DFLT0 interrupt status register 0. - DFLTISR: mmio.Mmio(packed struct(u32) { - /// RXFIFO threshold flag. - FTHF: u1, - /// Data overflow flag. - DOVRF: u1, - reserved3: u1, - /// RXFIFO not empty flag. - RXNEF: u1, - reserved9: u5, - /// Saturation detection flag. - SATF: u1, - /// Clock absence detection flag. - CKABF: u1, - /// Reshape filter overrun detection flag. - RFOVRF: u1, - /// Sound activity detection flag. - SDDETF: u1, - /// Sound level value ready flag. - SDLVLF: u1, - padding: u18, - }), - reserved184: [4]u8, - /// ADF SAD control register. - SADCR: mmio.Mmio(packed struct(u32) { - /// Sound activity detector enable. - SADEN: u1, - /// Data capture mode. - DATCAP: packed union { - raw: u2, - value: DATCAP, + reserved14: u2, + /// Comparator 1 output selector. + WINOUT: packed union { + raw: u1, + value: WindowOut, }, - /// Sound trigger event configuration. - DETCFG: packed union { + /// Polarity selection bit. + POLARITY: packed union { raw: u1, - value: DETCFG, + value: Polarity, }, - /// SAD state. - SADST: packed union { + /// Hysteresis selection bits. + HYST: packed union { raw: u2, - value: SADST, - }, - reserved7: u1, - /// Hysteresis enable. - HYSTEN: u1, - /// Frame size. - FRSIZE: packed union { - raw: u3, - value: FRSIZE, + value: HYST, }, - reserved12: u1, - /// Sound activity detector working mode. - SADMOD: packed union { + /// Power Mode. + PWRMODE: packed union { raw: u2, - value: SADMOD, - }, - reserved31: u17, - /// SAD Active flag. - SADACTIVE: u1, - }), - /// ADF SAD configuration register. - SADCFGR: mmio.Mmio(packed struct(u32) { - /// SNTHR. - SNTHR: packed union { - raw: u4, - value: SNTHR, - }, - /// ANSLP. - ANSLP: u3, - reserved8: u1, - /// LFRNB. - LFRNB: packed union { - raw: u3, - value: LFRNB, + value: PWRMODE, }, - reserved12: u1, - /// Hangover time window. - HGOVR: packed union { - raw: u3, - value: HGOVR, + /// Blanking source selection bits. + BLANKSEL: packed union { + raw: u5, + value: BLANKING, }, - reserved16: u1, - /// ANMIN. - ANMIN: u13, - padding: u3, - }), - /// ADF SAD sound level register. - SADSDLVR: mmio.Mmio(packed struct(u32) { - /// Short term sound level. This bitfield is set by hardware. It contains the latest sound level computed by the SAD. To refresh this value, SDLVLF must be cleared. - SDLVL: u15, - padding: u17, - }), - /// ADF SAD ambient noise level register. - SADANLVR: mmio.Mmio(packed struct(u32) { - /// ANLVL. - ANLVL: u15, - padding: u17, - }), - reserved240: [40]u8, - /// ADF digital filter data register 0. - DFLTDR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// DR. Data processed by DFT - DR: u24, + reserved30: u5, + /// Output status bit. + VALUE: u1, + /// Register lock bit. + LOCK: u1, }), }; }; - pub const syscfg_h5 = struct { - pub const CS = enum(u1) { - /// Code from the cell (available in the SBS_CCVR) - Cell = 0x0, - /// Code from SBS_CCCR - Software = 0x1, - }; - - pub const DBGCFG_LOCK = enum(u8) { - /// Writes to SBS_DBGCR allowed (default) - B_0xB4 = 0xb4, + pub const comp_u5 = struct { + pub const Blanking = enum(u5) { + /// No blanking. + NoBlanking = 0x0, + /// Check data sheet for blanking options + Blank1 = 0x1, + /// Check data sheet for blanking options + Blank2 = 0x2, + /// Check data sheet for blanking options + Blank3 = 0x4, _, }; - pub const DBG_AUTH_HDPL = enum(u8) { - /// HDPL1 - B_0x51 = 0x51, - /// HDPL3 - B_0x6F = 0x6f, - /// HDPL2 - B_0x8A = 0x8a, - _, + pub const Hysteresis = enum(u2) { + None = 0x0, + Low = 0x1, + Medium = 0x2, + High = 0x3, }; - pub const EPOCH_SEL = enum(u2) { - /// SEC_EPOCH counter input selected - B_0x0 = 0x0, - /// NS_EPOCH (non-secure) input selected - B_0x1 = 0x1, + pub const INM = enum(u4) { + /// Inverting input set to 1/4 VRef + QuarterVRef = 0x0, + /// Inverting input set to 1/2 VRef + HalfVRef = 0x1, + /// Inverting input set to 3/4 VRef + ThreeQuarterVRef = 0x2, + /// Inverting input set to VRef + VRef = 0x3, + /// Inverting input set to DAC1 output + DAC1 = 0x4, + /// Inverting input set to DAC2 output + DAC2 = 0x5, + /// Inverting input set to IO1 (PB7) + INM1 = 0x6, + /// Inverting input set to IO2 (PB3) + INM2 = 0x7, _, }; - pub const ETH_SEL_PHY = enum(u3) { - /// GMII or MII - MII_GMII = 0x0, - /// reserved (RGMII) - ReservedRGMII = 0x1, - /// RMII - RMII = 0x4, - _, + pub const Polarity = enum(u1) { + /// Output is not inverted. + NotInverted = 0x0, + /// Output is inverted. + Inverted = 0x1, }; - pub const HDPL = enum(u8) { - /// HDPL1, iRoT - B_0x51 = 0x51, - /// HDPL3, application (secure/non-secure) - B_0x6F = 0x6f, - /// HDPL2, uRoT - B_0x8A = 0x8a, - /// HDPL0, RSS - B_0xB4 = 0xb4, + pub const PowerMode = enum(u2) { + /// High speed / full power. + HighSpeed = 0x0, + /// Medium speed / medium power. + MediumSpeed = 0x1, + /// Very-low speed / ultra-low power. + UltraLow = 0x3, _, }; - pub const INCR_HDPL = enum(u8) { - /// recommended value to increment HDPL level by one - B_0x6A = 0x6a, - /// no increment - B_0xB4 = 0xb4, - _, + pub const WindowMode = enum(u1) { + /// Signal selected with INPSEL[2:0] bitfield of this register. + ThisInpsel = 0x0, + /// Signal selected with INPSEL[2:0] bitfield of the other register (required for window mode). + OtherInpsel = 0x1, }; - pub const SEC = enum(u1) { - /// SBS_CFGR2 register accessible through secure or non-secure transaction - B_0x0 = 0x0, - /// SBS_CFGR2 register only accessible through secure transaction - B_0x1 = 0x1, + pub const WindowOut = enum(u1) { + /// Comparator 1 value. + COMP1_VALUE = 0x0, + /// Comparator 1 value XOR comparator 2 value (required for window mode). + @"COMP1_VALUE XOR COMP2_VALUE" = 0x1, }; - /// SBS register block - pub const SYSCFG = extern struct { - reserved16: [16]u8, - /// SBS temporal isolation control register - HDPLCR: mmio.Mmio(packed struct(u32) { - /// increment HDPL value Other: all other values allow a HDPL level increment. - INCR_HDPL: packed union { - raw: u8, - value: INCR_HDPL, - }, - padding: u24, - }), - /// SBS temporal isolation status register - HDPLSR: mmio.Mmio(packed struct(u32) { - /// temporal isolation level This bitfield returns the current temporal isolation level. - HDPL: packed union { - raw: u8, - value: HDPL, - }, - padding: u24, - }), - /// SBS next HDPL control register - NEXTHDPLCR: mmio.Mmio(packed struct(u32) { - /// index to point to a higher HDPL than the current one Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas (OBK-HDPL = HDPL + NEXTHDPL). See for more details. - NEXTHDPL: u2, - padding: u30, - }), - reserved32: [4]u8, - /// SBS debug control register - DBGCR: mmio.Mmio(packed struct(u32) { - /// access port unlock Write 0xB4 to this bitfield to open the device access port. - AP_UNLOCK: u8, - /// debug unlock when DBG_AUTH_HDPL is reached Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register. - DBG_UNLOCK: u8, - /// authenticated debug temporal isolation level Writing to this bitfield defines at which HDPL the authenticated debug opens. Note: Writing any other values is ignored. Reading any other value means the debug never opens. - DBG_AUTH_HDPL: packed union { - raw: u8, - value: DBG_AUTH_HDPL, - }, - /// control debug opening secure/non-secure Write 0xB4 to this bitfield to open debug for secure and non-secure. Writing any other values only open non-secure. - DBG_AUTH_SEC: u8, - }), - /// SBS debug lock register - DBGLOCKR: mmio.Mmio(packed struct(u32) { - /// debug configuration lock Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4. 0xC3 is the recommended value to lock the debug configuration using this bitfield. Other: Writes to SBS_DBGCR ignored - DBGCFG_LOCK: packed union { - raw: u8, - value: DBGCFG_LOCK, - }, - padding: u24, - }), - reserved52: [12]u8, - /// SBS RSS command register - RSSCMDR: mmio.Mmio(packed struct(u32) { - /// RSS command The application can use this bitfield to pass on a command to the RSS, executed at the next reset. When RSSCMD ≠ 0 and PRODUCT_STATE is in Open, then the system always boots on RSS whatever is the boot pin value. - RSSCMD: u16, - padding: u16, - }), - reserved160: [104]u8, - /// SBS EPOCH selection control register - EPOCHSELCR: mmio.Mmio(packed struct(u32) { - /// select EPOCH value to be sent to the SAES 1x: EPOCH forced to zero (value used to retrieve PUF reference value at boot time) - EPOCH_SEL: packed union { - raw: u2, - value: EPOCH_SEL, + /// Comparator. + pub const COMP = extern struct { + /// Comparator control and status register. + CSR: mmio.Mmio(packed struct(u32) { + /// Enable + EN: u1, + reserved4: u3, + /// Input minus selection bits. + INMSEL: packed union { + raw: u4, + value: INM, }, - padding: u30, - }), - reserved192: [28]u8, - /// SBS security mode configuration control register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// SBS clock control, memory-erase status register and compensation cell register security enable - SBSSEC: packed union { + /// Input plus selection bit. + INPSEL: u3, + /// Comparator 1 noninverting input selector for window mode. + WINMODE: packed union { raw: u1, - value: SEC, + value: WindowMode, }, - /// ClassB security enable - CLASSBSEC: packed union { + reserved14: u2, + /// Comparator 1 output selector. + WINOUT: packed union { raw: u1, - value: SEC, + value: WindowOut, }, - reserved3: u1, - /// FPU security enable Note: This bit can only be written through privilege transaction. - FPUSEC: packed union { + /// Polarity selection bit. + POLARITY: packed union { raw: u1, - value: SEC, + value: Polarity, }, - reserved31: u27, - /// control accessibility of SMPS_DIV_CLOCK _EN in SBS_PMCR - SDCE_SEC_EN: u1, - }), - reserved256: [60]u8, - /// SBS product mode and configuration register - PMCR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// booster enable Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range. - BOOSTEN: u1, - /// booster VDD selection Note: Booster must not be used when VDDA < 2.7 V, but VDD > 2.7 V (add current consumption). When both VDD < 2.7 V and VDDA < 2.7 V, booster is needed to get full AC performances from I/O analog switches. - BOOSTVDDSEL: u1, - reserved16: u6, - /// Fast-mode Plus command on PB(6) - PB6_FMPLUS: u1, - /// Fast-mode Plus command on PB(7) - PB7_FMPLUS: u1, - /// Fast-mode Plus command on PB(8) - PB8_FMPLUS: u1, - /// Fast-mode Plus command on PB(9) - PB9_FMPLUS: u1, - reserved21: u1, - /// Ethernet PHY interface selection Other: reserved - ETH_SEL_PHY: packed union { - raw: u3, - value: ETH_SEL_PHY, + /// Hysteresis selection bits. + HYST: packed union { + raw: u2, + value: Hysteresis, }, - padding: u8, - }), - /// SBS FPU interrupt mask register - FPUIMR: mmio.Mmio(packed struct(u32) { - /// FPU interrupt enable Set and cleared by software to enable the Cortex-M33 FPU interrupts FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset) FPU_IE[4]: input abnormal interrupt enable FPU_IE[3]: overflow interrupt enable FPU_IE[2]: underflow interrupt enable FPU_IE[1]: divide-by-zero interrupt enable FPU_IE[0]: invalid operation interrupt enable - FPU_IE: u6, - padding: u26, - }), - /// SBS memory erase status register - MESR: mmio.Mmio(packed struct(u32) { - /// erase after reset status This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, DCACHE, ICACHE and PKA. It is set by hardware and reset by software - MCLR: u1, - reserved16: u15, - /// end-of-erase status for ICACHE and PKA RAM This bit shows the status of the protection for ICACHE and PKA. It is set by hardware and reset by software. - IPMEE: u1, - padding: u15, - }), - reserved272: [4]u8, - /// SBS compensation cell for I/Os control and status register - CCCSR: mmio.Mmio(packed struct(u32) { - /// enable compensation cell for VDDIO power rail This bit enables the I/O compensation cell. - EN: u1, - /// code selection for VDDIO power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. - CS: packed union { - raw: u1, - value: CS, + /// Power Mode. + PWRMODE: packed union { + raw: u2, + value: PowerMode, }, - reserved8: u6, - /// VDDIO compensation cell ready flag This bit provides the status of the compensation cell. - RDY: u1, - padding: u23, - }), - /// SBS compensation cell for I/Os value register - CCVALR: mmio.Mmio(packed struct(u32) { - /// compensation value for the NMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. - ANSRC1: u4, - /// compensation value for the PMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. - APSRC1: u4, - /// Compensation value for the NMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. - ANSRC2: u4, - /// compensation value for the PMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. - APSRC2: u4, - padding: u16, - }), - /// SBS compensation cell for I/Os software code register - CCSWCR: mmio.Mmio(packed struct(u32) { - /// NMOS compensation code for VDD power rails This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR. - SW_ANSRC1: u4, - /// PMOS compensation code for the VDD power rails This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR. - SW_APSRC1: u4, - /// NMOS compensation code for VDDIO power rails This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR. - SW_ANSRC2: u4, - /// PMOS compensation code for the VDDIO power rails This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR. - SW_APSRC2: u4, - padding: u16, - }), - reserved288: [4]u8, - /// SBS Class B register - CFGR2: mmio.Mmio(packed struct(u32) { - /// core lockup lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1/8/15/16/17 break inputs. - CLL: u1, - /// SRAM ECC error lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1/8/15/16/17. - SEL: u1, - /// PVD lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1/8/15/16/17 break inputs. - PVDL: u1, - /// ECC lock This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1/8/15/6/17. - ECCL: u1, - padding: u28, - }), - reserved324: [32]u8, - /// SBS CPU non-secure lock register - CNSLCKR: mmio.Mmio(packed struct(u32) { - /// VTOR_NS register lock This bit is set by software and cleared only by a system reset. - LOCKNSVTOR: u1, - /// non-secure MPU register lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers. - LOCKNSMPU: u1, - padding: u30, - }), - /// SBS CPU secure lock register - CSLCKR: mmio.Mmio(packed struct(u32) { - /// VTOR_S and AIRCR register lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register. - LOCKSVTAIRCR: u1, - /// secure MPU registers lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers. - LOCKSMPU: u1, - /// SAU registers lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers. - LOCKSAU: u1, - padding: u29, - }), - /// SBS flift ECC NMI mask register - ECCNMIR: mmio.Mmio(packed struct(u32) { - /// NMI behavior setup when a double ECC error occurs on flitf data part - ECCNMI_MASK_EN: u1, - padding: u31, + /// Blanking source selection bits. + BLANKSEL: packed union { + raw: u5, + value: Blanking, + }, + reserved30: u5, + /// Output status bit. + VALUE: u1, + /// Register lock bit. + LOCK: u1, }), }; }; - pub const exti_g0 = struct { - /// External interrupt/event controller - pub const EXTI = extern struct { - /// Rising Trigger selection register - RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Falling Trigger selection register - FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Software interrupt event register - SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Rising pending register - RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Falling pending register - FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - reserved96: [76]u8, - /// Configuration register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u8, - padding: u24, - }), - reserved128: [16]u8, - /// Interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Event mask register - EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), + pub const comp_v1 = struct { + pub const BLANKSEL = enum(u5) { + None = 0x0, + /// TIM1 OC4 + Tim1Oc4 = 0x1, + /// TIM1 OC5 + Tim1Oc5 = 0x2, + /// TIM2 OC3 + Tim2Oc3 = 0x4, + /// TIM3 OC3 + Tim3Oc3 = 0x8, + /// TIM15 OC2 + Tim15Oc2 = 0x10, + _, }; - }; - pub const flash_f7 = struct { - pub const LATENCY = enum(u4) { - /// 0 wait states - WS0 = 0x0, - /// 1 wait states - WS1 = 0x1, - /// 2 wait states - WS2 = 0x2, - /// 3 wait states - WS3 = 0x3, - /// 4 wait states - WS4 = 0x4, - /// 5 wait states - WS5 = 0x5, - /// 6 wait states - WS6 = 0x6, - /// 7 wait states - WS7 = 0x7, - /// 8 wait states - WS8 = 0x8, - /// 9 wait states - WS9 = 0x9, - /// 10 wait states - WS10 = 0xa, - /// 11 wait states - WS11 = 0xb, - /// 12 wait states - WS12 = 0xc, - /// 13 wait states - WS13 = 0xd, - /// 14 wait states - WS14 = 0xe, - /// 15 wait states - WS15 = 0xf, + pub const HYST = enum(u2) { + None = 0x0, + Low = 0x1, + Medium = 0x2, + High = 0x3, }; - pub const PSIZE = enum(u2) { - /// Program x8 - PSIZE8 = 0x0, - /// Program x16 - PSIZE16 = 0x1, - /// Program x32 - PSIZE32 = 0x2, - /// Program x64 - PSIZE64 = 0x3, + pub const POLARITY = enum(u1) { + NonInverted = 0x0, + Inverted = 0x1, }; - /// FLASH - pub const FLASH = extern struct { - /// Flash access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: packed union { - raw: u4, - value: LATENCY, - }, - reserved8: u4, - /// Prefetch enable - PRFTEN: u1, - /// ART Accelerator Enable - ARTEN: u1, + pub const PWRMODE = enum(u2) { + HighSpeed = 0x0, + MediumSpeed = 0x1, + _, + }; + + /// Comparator v1. (RM0444 18) + pub const COMP = extern struct { + /// Comparator control and status register. + CSR: mmio.Mmio(packed struct(u32) { + /// COMP enable bit. + EN: u1, + reserved4: u3, + /// Comparator signal selector for inverting input INM. + INMSEL: u4, + /// Comparator signal selector for non-inverting input INP. + INPSEL: u2, reserved11: u1, - /// ART Accelerator reset - ARTRST: u1, - padding: u20, - }), - /// Flash key register - KEYR: u32, - /// Flash option key register - OPTKEYR: u32, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved4: u2, - /// Write protection error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Programming parallelism error - PGPERR: u1, - /// Erase Sequence Error - ERSERR: u1, - /// RDERR - RDERR: u1, - reserved16: u7, - /// Busy - BSY: u1, - padding: u15, - }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Sector Erase - SER: u1, - /// Mass Erase of sectors 0 to 11 - MER: u1, - /// Sector number - SNB: u4, - reserved8: u1, - /// Program size - PSIZE: packed union { + /// Comparator non-inverting input selector for window mode. + WINMODE: u1, + reserved14: u2, + /// Comparator output selector. + WINOUT: u1, + /// Comparator polarity selector. + POLARITY: packed union { + raw: u1, + value: POLARITY, + }, + /// Comparator hysteresis selector. + HYST: packed union { raw: u2, - value: PSIZE, + value: HYST, }, - reserved16: u6, - /// Start - STRT: u1, - reserved24: u7, - /// End of operation interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// PCROP error interrupt enable - RDERRIE: u1, - reserved31: u4, - /// Lock + /// Comparator power mode selector. + PWRMODE: packed union { + raw: u2, + value: PWRMODE, + }, + /// Comparator blanking source selector. + BLANKSEL: packed union { + raw: u5, + value: BLANKSEL, + }, + reserved30: u5, + /// Comparator output status. (READ ONLY) + VALUE_DO_NOT_SET: u1, + /// CSR register lock. LOCK: u1, }), - /// Flash option control register - OPTCR: mmio.Mmio(packed struct(u32) { - /// Option lock - OPTLOCK: u1, - /// Option start - OPTSTRT: u1, - /// BOR reset Level - BOR_LEV: u2, - /// User option bytes - WWDG_SW: u1, - /// WDG_SW User option bytes - IWDG_SW: u1, - /// nRST_STOP User option bytes - nRST_STOP: u1, - /// nRST_STDBY User option bytes - nRST_STDBY: u1, - /// Read protect - RDP: u8, - /// Not write protect - nWRP: u8, - reserved28: u4, - /// Dual Boot mode (valid only when nDBANK=0) - nDBOOT: u1, - /// Not dual bank mode - nDBANK: u1, - /// Independent watchdog counter freeze in standby mode - IWDG_STDBY: u1, - /// Independent watchdog counter freeze in Stop mode - IWDG_STOP: u1, - }), - /// Flash option control register 1 - OPTCR1: mmio.Mmio(packed struct(u32) { - /// Boot base address when Boot pin =0 - BOOT_ADD0: u16, - /// Boot base address when Boot pin =1 - BOOT_ADD1: u16, - }), - /// Flash option control register - OPTCR2: mmio.Mmio(packed struct(u32) { - /// PCROP option byte - PCROPi: u8, - reserved31: u23, - /// PCROP zone preserved when RDP level decreased - PCROP_RDP: u1, - }), }; }; - pub const dac_v3 = struct { - pub const MODE = enum(u3) { - /// Normal mode, external pin only, buffer enabled - NORMAL_EXT_BUFEN = 0x0, - /// Normal mode, external pin and internal peripherals, buffer enabled - NORMAL_EXT_INT_BUFEN = 0x1, - /// Normal mode, external pin only, buffer disabled - NORMAL_EXT_BUFDIS = 0x2, - /// Normal mode, internal peripherals only, buffer disabled - NORMAL_INT_BUFDIS = 0x3, - /// Sample and hold mode, external pin only, buffer enabled - SAMPHOLD_EXT_BUFEN = 0x4, - /// Sample and hold mode, external pin and internal peripherals, buffer enabled - SAMPHOLD_EXT_INT_BUFEN = 0x5, - /// Sample and hold mode, external pin and internal peripherals, buffer disabled - SAMPHOLD_EXT_INT_BUFDIS = 0x6, - /// Sample and hold mode, internal peripherals only, buffer disabled - SAMPHOLD_INT_BUFDIS = 0x7, + pub const comp_v2 = struct { + pub const HYST = enum(u3) { + None = 0x0, + /// 10mV hysteresis + Hyst10m = 0x1, + /// 20mV hysteresis + Hyst20m = 0x2, + /// 30mV hysteresis + Hyst30m = 0x3, + /// 40mV hysteresis + Hyst40m = 0x4, + /// 50mV hysteresis + Hyst50m = 0x5, + /// 60mV hysteresis + Hyst60m = 0x6, + /// 70mV hysteresis + Hyst70m = 0x7, }; - pub const WAVE = enum(u2) { - /// Wave generation disabled - Disabled = 0x0, - /// Noise wave generation enabled - Noise = 0x1, - /// Triangle wave generation enabled - Triangle = 0x2, + pub const POLARITY = enum(u1) { + /// Non-inverted polarity + NonInverted = 0x0, + /// Inverted polarity + Inverted = 0x1, + }; + + /// Comparator v2. (RM0440 24) + pub const COMP = extern struct { + /// Comparator control and status register. + CSR: mmio.Mmio(packed struct(u32) { + /// COMP enable bit. + EN: u1, + reserved4: u3, + /// Comparator signal selector for inverting input INM. (RM0440 24.3.2 Table 197) + INMSEL: u3, + reserved8: u1, + /// Comparator signal selector for non-inverting input INP. (RM0440 24.3.2 Table 196) + INPSEL: u1, + reserved15: u6, + /// Comparator polarity selector. + POLARITY: packed union { + raw: u1, + value: POLARITY, + }, + /// Comparator hysteresis selector. + HYST: packed union { + raw: u3, + value: HYST, + }, + /// Comparator blanking source selector. (RM0440 24.3.6 Table 198) + BLANKSEL: u3, + /// Vrefint resistor bridge enable. (RM0440 24.6) + BRGEN: u1, + /// Vrefint scaled input enable. (RM0440 24.6) + SCALEN: u1, + reserved30: u6, + /// Comparator output status. (READ ONLY) + VALUE_DO_NOT_SET: u1, + /// CSR register lock. + LOCK: u1, + }), + }; + }; + + pub const comp_v3 = struct { + pub const BLANKING = enum(u3) { + /// No blanking. + NoBlanking = 0x0, + /// TIM1 OC5 selected as blanking source. + TIM1OC5 = 0x1, + /// TIM2 OC3 selected as blanking source. + TIM2OC3 = 0x2, _, }; - /// Digital-to-analog converter - pub const DAC = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// channel enable + pub const HYST = enum(u2) { + None = 0x0, + Low = 0x1, + Medium = 0x2, + High = 0x3, + }; + + pub const POLARITY = enum(u1) { + /// Output is not inverted. + NotInverted = 0x0, + /// Output is inverted. + Inverted = 0x1, + }; + + pub const PWRMODE = enum(u2) { + /// High speed / full power. + HighSpeed = 0x0, + /// Medium speed / medium power. + MediumSpeed = 0x1, + /// Low speed / low power. + LowSpeed = 0x2, + /// Very-low speed / ultra-low power. + VeryLowSpeed = 0x3, + }; + + /// Comparator. + pub const COMP = extern struct { + /// Comparator control and status register. + CSR: mmio.Mmio(packed struct(u32) { + /// Enable EN: u1, reserved2: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u3, - /// channel noise/triangle wave generation enable - WAVE: packed union { + /// Power Mode. + PWRMODE: packed union { raw: u2, - value: WAVE, + value: PWRMODE, }, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - /// channel DMA Underrun Interrupt enable - DMAUDRIE: u1, - /// DAC channel calibration enable - CEN: u1, - padding: u17, - }), - /// software trigger register - SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - padding: u31, - }), - /// channel 12-bit right-aligned data holding register - DHR12R: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, - }), - /// channel 12-bit left-aligned data holding register - DHR12L: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, - }), - /// channel 8-bit right-aligned data holding register - DHR8R: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, - }), - reserved32: [12]u8, - /// dual 12-bit right-aligned data holding register - DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, - }), - /// dual 12-bit left aligned data holding register - DHR12LD: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, - }), - /// dual 8-bit right aligned data holding register - DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, - }), - /// channel data output register - DOR: [2]mmio.Mmio(packed struct(u32) { - /// channel data output - DOR: u12, - padding: u20, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved13: u13, - /// channel DMA underrun flag - DMAUDR: u1, - /// channel calibration offset status - CAL_FLAG: u1, - /// channel busy writing sample time flag - BWST: u1, - padding: u16, - }), - /// calibration control register - CCR: mmio.Mmio(packed struct(u32) { - /// channel offset trimming value - OTRIM: u5, - padding: u27, - }), - /// mode control register - MCR: mmio.Mmio(packed struct(u32) { - /// DAC channel mode - MODE: packed union { + /// Input minus selection bits. + INMSEL: u3, + /// Input plus selection bit. + INPSEL: u2, + reserved15: u6, + /// Polarity selection bit. + POLARITY: packed union { + raw: u1, + value: POLARITY, + }, + /// Hysteresis selection bits. + HYST: packed union { + raw: u2, + value: HYST, + }, + /// Blanking source selection bits. + BLANKING: packed union { raw: u3, - value: MODE, + value: BLANKING, }, - padding: u29, - }), - /// sample and hold sample time register - SHSR: [2]mmio.Mmio(packed struct(u32) { - /// channel sample time - TSAMPLE: u10, - padding: u22, - }), - /// sample and hold hold time register - SHHR: mmio.Mmio(packed struct(u32) { - /// channel hold time - THOLD: u10, - padding: u22, - }), - /// sample and hold refresh time register - SHRR: mmio.Mmio(packed struct(u32) { - /// channel refresh time - TREFRESH: u8, - padding: u24, + reserved22: u1, + /// Scaler bridge enable. + BRGEN: u1, + /// Voltage scaler enable bit. + SCALEN: u1, + reserved25: u1, + /// Input minus extended selection bits. + INMESEL: u2, + reserved30: u3, + /// Output status bit. + VALUE: u1, + /// Register lock bit. + LOCK: u1, }), }; }; - pub const lptim_v1b_h7 = struct { - pub const CKPOL = enum(u2) { - /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. - Rising = 0x0, - /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. - Falling = 0x1, - /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. - Both = 0x2, + pub const cordic_v1 = struct { + pub const FUNC = enum(u4) { + /// Cosine function. + Cosine = 0x0, + /// Sine function. + Sine = 0x1, + /// Phase function. + Phase = 0x2, + /// Modulus function. + Modulus = 0x3, + /// Arctangent function. + Arctangent = 0x4, + /// Hyperbolic Cosine function. + HyperbolicCosine = 0x5, + /// Hyperbolic Sine function. + HyperbolicSine = 0x6, + /// Arctanh function. + Arctanh = 0x7, + /// Natural Logarithm function. + NaturalLogarithm = 0x8, + /// Square Root function. + SquareRoot = 0x9, _, }; - pub const ClockSource = enum(u1) { - /// clocked by internal clock source (APB clock or any of the embedded oscillators) - Internal = 0x0, - /// clocked by an external clock source through the LPTIM external Input1 - External = 0x1, - }; - - pub const Filter = enum(u2) { - Count1 = 0x0, - Count2 = 0x1, - Count4 = 0x2, - Count8 = 0x3, + pub const Num = enum(u1) { + /// 1 input/output + Num1 = 0x0, + /// 2 input/output + Num2 = 0x1, }; - pub const PRESC = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div4 = 0x2, - Div8 = 0x3, - Div16 = 0x4, - Div32 = 0x5, - Div64 = 0x6, - Div128 = 0x7, + pub const PRECISION = enum(u4) { + /// 4 iterations. + Iters4 = 0x1, + /// 8 iterations. + Iters8 = 0x2, + /// 12 iterations. + Iters12 = 0x3, + /// 16 iterations. + Iters16 = 0x4, + /// 20 iterations. + Iters20 = 0x5, + /// 24 iterations. + Iters24 = 0x6, + /// 28 iterations. + Iters28 = 0x7, + /// 32 iterations. + Iters32 = 0x8, + /// 36 iterations. + Iters36 = 0x9, + /// 40 iterations. + Iters40 = 0xa, + /// 44 iterations. + Iters44 = 0xb, + /// 48 iterations. + Iters48 = 0xc, + /// 52 iterations. + Iters52 = 0xd, + /// 56 iterations. + Iters56 = 0xe, + /// 60 iterations. + Iters60 = 0xf, + _, }; - pub const TRIGEN = enum(u2) { - /// software trigger (counting start is initiated by software) - Software = 0x0, - /// rising edge is the active edge - RisingEdge = 0x1, - /// falling edge is the active edge - FallingEdge = 0x2, - /// both edges are active edges - BothEdge = 0x3, + pub const Scale = enum(u3) { + /// Argument multiplied by 1, result multiplied by 1 + A1_R1 = 0x0, + /// Argument multiplied by 1/2, result multiplied by 2 + A1o2_R2 = 0x1, + /// Argument multiplied by 1/4, result multiplied by 4 + A1o4_R4 = 0x2, + /// Argument multiplied by 1/8, result multiplied by 8 + A1o8_R8 = 0x3, + /// Argument multiplied by 1/16, result multiplied by 16 + A1o16_R16 = 0x4, + /// Argument multiplied by 1/32, result multiplied by 32 + A1o32_R32 = 0x5, + /// Argument multiplied by 1/64, result multiplied by 64 + A1o64_R64 = 0x6, + /// Argument multiplied by 1/128, result multiplied by 128 + A1o128_R128 = 0x7, }; - pub const WAVPOL = enum(u1) { - /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. - Positive = 0x0, - /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. - Negative = 0x1, + pub const Size = enum(u1) { + /// Use 32 bit input/output values. + Bits32 = 0x0, + /// Use 16 bit input/output values. + Bits16 = 0x1, }; - /// Low power timer with Output Compare - pub const LPTIM = extern struct { - /// LPTIM interrupt and status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, - /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. - ARRM: u1, - /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. - EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, - /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. - ARROK: u1, - /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UP: u1, - /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWN: u1, - padding: u25, - }), - /// LPTIM interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, - /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. - ARRMCF: u1, - /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. - EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, - /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. - ARROKCF: u1, - /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPCF: u1, - /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNCF: u1, - padding: u25, - }), - /// LPTIM interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, - /// Autoreload match Interrupt Enable. - ARRMIE: u1, - /// External trigger valid edge Interrupt Enable. - EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, - /// Autoreload register update OK Interrupt Enable. - ARROKIE: u1, - /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPIE: u1, - /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNIE: u1, - padding: u25, - }), - /// LPTIM configuration register. - CFGR: mmio.Mmio(packed struct(u32) { - /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. - CKSEL: packed union { - raw: u1, - value: ClockSource, - }, - /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. - CKPOL: packed union { - raw: u2, - value: CKPOL, - }, - /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - CKFLT: packed union { - raw: u2, - value: Filter, + /// CORDIC co-processor. + pub const CORDIC = extern struct { + /// Control and status register. + CSR: mmio.Mmio(packed struct(u32) { + /// Function. + FUNC: packed union { + raw: u4, + value: FUNC, }, - reserved6: u1, - /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. - TRGFLT: packed union { - raw: u2, - value: Filter, + /// Precision required (number of iterations/cycles), where PRECISION = (number of iterations/4). + PRECISION: packed union { + raw: u4, + value: PRECISION, }, - reserved9: u1, - /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. - PRESC: packed union { + /// Scaling factor. Input value has been multiplied by 2^(-n) before for argument. Output value will need to be multiplied by 2^n later for results. + SCALE: packed union { raw: u3, - value: PRESC, + value: Scale, }, - reserved13: u1, - /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. - TRIGSEL: u3, - reserved17: u1, - /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. - TRIGEN: packed union { - raw: u2, - value: TRIGEN, + reserved16: u5, + /// Enable interrupt. + IEN: u1, + /// Enable DMA wread channel. + DMAREN: u1, + /// Enable DMA write channel. + DMAWEN: u1, + /// Number of results in the RDATA register. + NRES: packed union { + raw: u1, + value: Num, }, - /// Timeout enable The TIMOUT bit controls the Timeout feature. - TIMOUT: u1, - /// Waveform shape The WAVE bit controls the output shape. - WAVE: u1, - /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. - WAVPOL: packed union { + /// Number of arguments expected by the WDATA register. + NARGS: packed union { raw: u1, - value: WAVPOL, + value: Num, }, - /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. - PRELOAD: u1, - /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. - COUNTMODE: packed union { + /// Width of output data. + RESSIZE: packed union { raw: u1, - value: ClockSource, + value: Size, }, - /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - ENC: u1, - padding: u7, + /// Width of input data. + ARGSIZE: packed union { + raw: u1, + value: Size, + }, + reserved31: u8, + /// Result ready flag. + RRDY: u1, }), - /// LPTIM control register. + /// Argument register. + WDATA: u32, + /// Result register. + RDATA: u32, + }; + }; + + pub const crc_v1 = struct { + /// Cyclic Redundancy Check calculation unit + pub const CRC = extern struct { + /// Data register + DR: u32, + /// Independent Data register + IDR: u32, + /// Control register CR: mmio.Mmio(packed struct(u32) { - /// LPTIM enable The ENABLE bit is set and cleared by software. - ENABLE: u1, - /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. - SNGSTRT: u1, - /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. - CNTSTRT: u1, - /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. - COUNTRST: u1, - /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. - RSTARE: u1, - padding: u27, - }), - /// LPTIM compare register 1. - CMP: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. - CMP: u16, - padding: u16, - }), - /// LPTIM autoreload register. - ARR: mmio.Mmio(packed struct(u32) { - /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. - ARR: u16, - padding: u16, - }), - /// LPTIM counter register. - CNT: mmio.Mmio(packed struct(u32) { - /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. - CNT: u16, - padding: u16, - }), - reserved36: [4]u8, - /// LPTIM configuration register 2. - CFGR2: mmio.Mmio(packed struct(u32) { - /// LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. - INSEL: u2, - padding: u30, + /// RESET bit + RESET: u1, + padding: u31, }), }; }; - pub const rcc_h50 = struct { - pub const ADCDACSEL = enum(u3) { - /// rcc_hclk selected as kernel clock (default after reset) - HCLK2 = 0x0, - /// sys_ck selected as kernel clock - SYS = 0x1, - /// pll2_r_ck selected as kernel clock - PLL2_R = 0x2, - /// hse_ck selected as kernel clock - HSE = 0x3, - /// hsi_ker_ck selected as kernel clock - HSI = 0x4, - /// csi_ker_ck selected as kernel clock - CSI = 0x5, - _, + pub const crc_v2 = struct { + pub const POLYSIZE = enum(u2) { + /// 32-bit polynomial + Polysize32 = 0x0, + /// 16-bit polynomial + Polysize16 = 0x1, + /// 8-bit polynomial + Polysize8 = 0x2, + /// 7-bit polynomial + Polysize7 = 0x3, }; - pub const DACHOLDSEL = enum(u1) { - /// dac_hold_ck selected as kernel clock (default after reset) - DAC_HOLD = 0x0, - /// dac_hold_ck selected as kernel clock - DAC_HOLD_2 = 0x1, + pub const REV_IN = enum(u2) { + /// Bit order not affected + Normal = 0x0, + /// Bit reversal done by byte + Byte = 0x1, + /// Bit reversal done by half-word + HalfWord = 0x2, + /// Bit reversal done by word + Word = 0x3, }; - pub const FDCANSEL = enum(u2) { - /// hse_ck selected as kernel clock (default after reset) - HSE = 0x0, - /// pll1_q_ck selected as kernel clock - PLL1_Q = 0x1, - /// pll2_q_ck selected as kernel clock - PLL2_Q = 0x2, - _, + pub const REV_OUT = enum(u1) { + /// Bit order not affected + Normal = 0x0, + /// Bit reversed output + Reversed = 0x1, }; - pub const HPRE = enum(u4) { - /// sys_ck not divided - Div1 = 0x0, - /// sys_ck divided by 2 - Div2 = 0x8, - /// sys_ck divided by 4 - Div4 = 0x9, - /// sys_ck divided by 8 - Div8 = 0xa, - /// sys_ck divided by 16 - Div16 = 0xb, - /// sys_ck divided by 64 - Div64 = 0xc, - /// sys_ck divided by 128 - Div128 = 0xd, - /// sys_ck divided by 256 - Div256 = 0xe, - /// sys_ck divided by 512 - Div512 = 0xf, - _, + /// Cyclic Redundancy Check calculation unit + pub const CRC = extern struct { + /// Data register - half-word sized + DR16: u32, + /// Independent Data register + IDR: u32, + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// RESET bit + RESET: u1, + reserved3: u2, + /// Polynomial size + POLYSIZE: packed union { + raw: u2, + value: POLYSIZE, + }, + /// Reverse input data + REV_IN: packed union { + raw: u2, + value: REV_IN, + }, + /// Reverse output data + REV_OUT: packed union { + raw: u1, + value: REV_OUT, + }, + padding: u24, + }), + reserved16: [4]u8, + /// Initial CRC value + INIT: u32, }; + }; - pub const HSEEXT = enum(u1) { - /// HSE in analog mode (default after reset) - Analog = 0x0, - /// HSE in digital mode - Digital = 0x1, + pub const crc_v3 = struct { + pub const POLYSIZE = enum(u2) { + /// 32-bit polynomial + Polysize32 = 0x0, + /// 16-bit polynomial + Polysize16 = 0x1, + /// 8-bit polynomial + Polysize8 = 0x2, + /// 7-bit polynomial + Polysize7 = 0x3, }; - pub const HSIDIV = enum(u2) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x1, - /// Division by 4 - Div4 = 0x2, - /// Division by 8 - Div8 = 0x3, + pub const REV_IN = enum(u2) { + /// Bit order not affected + Normal = 0x0, + /// Bit reversal done by byte + Byte = 0x1, + /// Bit reversal done by half-word + HalfWord = 0x2, + /// Bit reversal done by word + Word = 0x3, }; - pub const I2CSEL = enum(u2) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// hsi_ker selected as peripheral clock - HSI = 0x2, - /// csi_ker selected as peripheral clock - CSI = 0x3, + pub const REV_OUT = enum(u1) { + /// Bit order not affected + Normal = 0x0, + /// Bit reversed output + Reversed = 0x1, }; - pub const I3C2SEL = enum(u2) { - /// rcc_pclk3 selected as peripheral clock - PCLK3 = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// hsi_ker selected as peripheral clock - HSI = 0x2, - /// csi_ker selected as peripheral clock - CSI = 0x3, + /// Cyclic Redundancy Check calculation unit + pub const CRC = extern struct { + /// Data register - half-word sized + DR16: u32, + /// Independent Data register + IDR: u32, + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// RESET bit + RESET: u1, + reserved3: u2, + /// Polynomial size + POLYSIZE: packed union { + raw: u2, + value: POLYSIZE, + }, + /// Reverse input data + REV_IN: packed union { + raw: u2, + value: REV_IN, + }, + /// Reverse output data + REV_OUT: packed union { + raw: u1, + value: REV_OUT, + }, + padding: u24, + }), + reserved16: [4]u8, + /// Initial CRC value + INIT: u32, + /// CRC polynomial + POL: u32, }; + }; - pub const LPTIM1SEL = enum(u3) { - /// rcc_pclk3 selected as peripheral clock - PCLK3 = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// LSE selected as peripheral clock - LSE = 0x3, - /// LSI selected as peripheral clock - LSI = 0x4, - /// PER selected as peripheral clock - PER = 0x5, + pub const crs_v1 = struct { + pub const SYNCSRC = enum(u2) { + /// GPIO selected as SYNC signal source + GPIO = 0x0, + /// LSE selected as SYNC signal source + LSE = 0x1, + /// USB SOF selected as SYNC signal source + USB = 0x2, _, }; - pub const LPTIM2SEL = enum(u3) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// LSE selected as peripheral clock - LSE = 0x3, - /// LSI selected as peripheral clock - LSI = 0x4, - /// PER selected as peripheral clock - PER = 0x5, - _, + /// Clock recovery system + pub const CRS = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// SYNC event OK interrupt enable + SYNCOKIE: u1, + /// SYNC warning interrupt enable + SYNCWARNIE: u1, + /// Synchronization or trimming error interrupt enable + ERRIE: u1, + /// Expected SYNC interrupt enable + ESYNCIE: u1, + reserved5: u1, + /// Frequency error counter enable + CEN: u1, + /// Automatic trimming enable + AUTOTRIMEN: u1, + /// Generate software SYNC event + SWSYNC: u1, + /// HSI48 oscillator smooth trimming + TRIM: u6, + padding: u18, + }), + /// configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// Counter reload value + RELOAD: u16, + /// Frequency error limit + FELIM: u8, + /// SYNC divider + SYNCDIV: u3, + reserved28: u1, + /// SYNC signal source selection + SYNCSRC: packed union { + raw: u2, + value: SYNCSRC, + }, + reserved31: u1, + /// SYNC polarity selection + SYNCPOL: u1, + }), + /// interrupt and status register + ISR: mmio.Mmio(packed struct(u32) { + /// SYNC event OK flag + SYNCOKF: u1, + /// SYNC warning flag + SYNCWARNF: u1, + /// Error flag + ERRF: u1, + /// Expected SYNC flag + ESYNCF: u1, + reserved8: u4, + /// SYNC error + SYNCERR: u1, + /// SYNC missed + SYNCMISS: u1, + /// Trimming overflow or underflow + TRIMOVF: u1, + reserved15: u4, + /// Frequency error direction + FEDIR: u1, + /// Frequency error capture + FECAP: u16, + }), + /// interrupt flag clear register + ICR: mmio.Mmio(packed struct(u32) { + /// SYNC event OK clear flag + SYNCOKC: u1, + /// SYNC warning clear flag + SYNCWARNC: u1, + /// Error clear flag + ERRC: u1, + /// Expected SYNC clear flag + ESYNCC: u1, + padding: u28, + }), }; + }; - pub const LPUARTSEL = enum(u3) { - /// rcc_pclk3 selected as kernel clock (default after reset) - PCLK3 = 0x0, - /// pll2_q_ck selected as kernel clock - PLL2_Q = 0x1, - /// hsi_ker_ck selected as kernel clock - HSI = 0x3, - /// csi_ker_ck selected as kernel clock - CSI = 0x4, - /// lse_ck selected as kernel clock - LSE = 0x5, - _, + pub const cryp_v1 = struct { + /// Cryptographic processor. + pub const CRYP = extern struct { + /// control register. + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Algorithm direction. + ALGODIR: u1, + /// Algorithm mode. + ALGOMODE: u3, + /// Data type selection. + DATATYPE: u2, + /// Key size selection (AES mode only). + KEYSIZE: u2, + reserved14: u4, + /// FIFO flush. + FFLUSH: u1, + /// Cryptographic processor enable. + CRYPEN: u1, + padding: u16, + }), + /// status register. + SR: mmio.Mmio(packed struct(u32) { + /// Input FIFO empty. + IFEM: u1, + /// Input FIFO not full. + IFNF: u1, + /// Output FIFO not empty. + OFNE: u1, + /// Output FIFO full. + OFFU: u1, + /// Busy bit. + BUSY: u1, + padding: u27, + }), + /// data input register. + DIN: u32, + /// data output register. + DOUT: u32, + /// DMA control register. + DMACR: mmio.Mmio(packed struct(u32) { + /// DMA input enable. + DIEN: u1, + /// DMA output enable. + DOEN: u1, + padding: u30, + }), + /// interrupt mask set/clear register. + IMSCR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service interrupt mask. + INIM: u1, + /// Output FIFO service interrupt mask. + OUTIM: u1, + padding: u30, + }), + /// raw interrupt status register. + RISR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service raw interrupt status. + INRIS: u1, + /// Output FIFO service raw interrupt status. + OUTRIS: u1, + padding: u30, + }), + /// masked interrupt status register. + MISR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service masked interrupt status. + INMIS: u1, + /// Output FIFO service masked interrupt status. + OUTMIS: u1, + padding: u30, + }), + /// Cluster KEY%s, containing K?LR, K?RR. + KEY: u32, + reserved64: [28]u8, + /// Cluster INIT%s, containing IV?LR, IV?RR. + INIT: u32, }; - pub const LSCOSEL = enum(u1) { - /// LSI clock selected - LSI = 0x0, - /// LSE clock selected - LSE = 0x1, + /// Cluster INIT%s, containing IV?LR, IV?RR. + pub const INIT = extern struct { + /// initialization vector registers. + IVLR: u32, + /// initialization vector registers. + IVRR: u32, }; - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, + /// Cluster KEY%s, containing K?LR, K?RR. + pub const KEY = extern struct { + /// key registers. + KLR: u32, + /// key registers. + KRR: u32, }; + }; - pub const LSEEXT = enum(u1) { - /// LSE in analog mode (default after Backup domain reset) - Analog = 0x0, - /// LSE in digital mode (do not use if RTC is active). - Digital = 0x1, + pub const cryp_v2 = struct { + /// Cryptographic processor. + pub const CRYP = extern struct { + /// control register. + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Algorithm direction. + ALGODIR: u1, + /// Algorithm mode. + ALGOMODE0: u3, + /// Data type selection. + DATATYPE: u2, + /// Key size selection (AES mode only). + KEYSIZE: u2, + reserved14: u4, + /// FIFO flush. + FFLUSH: u1, + /// Cryptographic processor enable. + CRYPEN: u1, + /// GCM_CCMPH. + GCM_CCMPH: u2, + reserved19: u1, + /// ALGOMODE. + ALGOMODE3: u1, + padding: u12, + }), + /// status register. + SR: mmio.Mmio(packed struct(u32) { + /// Input FIFO empty. + IFEM: u1, + /// Input FIFO not full. + IFNF: u1, + /// Output FIFO not empty. + OFNE: u1, + /// Output FIFO full. + OFFU: u1, + /// Busy bit. + BUSY: u1, + padding: u27, + }), + /// data input register. + DIN: u32, + /// data output register. + DOUT: u32, + /// DMA control register. + DMACR: mmio.Mmio(packed struct(u32) { + /// DMA input enable. + DIEN: u1, + /// DMA output enable. + DOEN: u1, + padding: u30, + }), + /// interrupt mask set/clear register. + IMSCR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service interrupt mask. + INIM: u1, + /// Output FIFO service interrupt mask. + OUTIM: u1, + padding: u30, + }), + /// raw interrupt status register. + RISR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service raw interrupt status. + INRIS: u1, + /// Output FIFO service raw interrupt status. + OUTRIS: u1, + padding: u30, + }), + /// masked interrupt status register. + MISR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service masked interrupt status. + INMIS: u1, + /// Output FIFO service masked interrupt status. + OUTMIS: u1, + padding: u30, + }), + /// Cluster KEY%s, containing K?LR, K?RR. + KEY: u32, + reserved64: [28]u8, + /// Cluster INIT%s, containing IV?LR, IV?RR. + INIT: u32, + reserved80: [12]u8, + /// context swap register. + CSGCMCCMR: [8]u32, + /// context swap register. + CSGCMR: [8]u32, }; - pub const MCO1SEL = enum(u3) { - /// HSI selected for micro-controller clock output - HSI = 0x0, - /// LSE selected for micro-controller clock output - LSE = 0x1, - /// HSE selected for micro-controller clock output - HSE = 0x2, - /// pll1_q selected for micro-controller clock output - PLL1_Q = 0x3, - /// HSI48 selected for micro-controller clock output - HSI48 = 0x4, - _, + /// Cluster INIT%s, containing IV?LR, IV?RR. + pub const INIT = extern struct { + /// initialization vector registers. + IVLR: u32, + /// initialization vector registers. + IVRR: u32, }; - pub const MCO2SEL = enum(u3) { - /// System clock selected for micro-controller clock output - SYS = 0x0, - /// pll2_p selected for micro-controller clock output - PLL2_P = 0x1, - /// HSE selected for micro-controller clock output - HSE = 0x2, - /// pll1_p selected for micro-controller clock output - PLL1_P = 0x3, - /// CSI selected for micro-controller clock output - CSI = 0x4, - /// LSI selected for micro-controller clock output - LSI = 0x5, - _, + /// Cluster KEY%s, containing K?LR, K?RR. + pub const KEY = extern struct { + /// key registers. + KLR: u32, + /// key registers. + KRR: u32, }; + }; - pub const MCOPRE = enum(u4) { - /// Divide by 1 - Div1 = 0x1, - /// Divide by 2 - Div2 = 0x2, - /// Divide by 3 - Div3 = 0x3, - /// Divide by 4 - Div4 = 0x4, - /// Divide by 5 - Div5 = 0x5, - /// Divide by 6 - Div6 = 0x6, - /// Divide by 7 - Div7 = 0x7, - /// Divide by 8 - Div8 = 0x8, - /// Divide by 9 - Div9 = 0x9, - /// Divide by 10 - Div10 = 0xa, - /// Divide by 11 - Div11 = 0xb, - /// Divide by 12 - Div12 = 0xc, - /// Divide by 13 - Div13 = 0xd, - /// Divide by 14 - Div14 = 0xe, - /// Divide by 15 - Div15 = 0xf, + pub const cryp_v3 = struct { + /// Cryptographic processor. + pub const CRYP = extern struct { + /// control register. + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Algorithm direction. + ALGODIR: u1, + /// Algorithm mode. + ALGOMODE0: u3, + /// Data type selection. + DATATYPE: u2, + /// Key size selection (AES mode only). + KEYSIZE: u2, + reserved14: u4, + /// FIFO flush. + FFLUSH: u1, + /// Cryptographic processor enable. + CRYPEN: u1, + /// GCM_CCMPH. + GCM_CCMPH: u2, + reserved19: u1, + /// ALGOMODE. + ALGOMODE3: u1, + /// Number of Padding Bytes in Last Block of payload. + NPBLB: u4, + padding: u8, + }), + /// status register. + SR: mmio.Mmio(packed struct(u32) { + /// Input FIFO empty. + IFEM: u1, + /// Input FIFO not full. + IFNF: u1, + /// Output FIFO not empty. + OFNE: u1, + /// Output FIFO full. + OFFU: u1, + /// Busy bit. + BUSY: u1, + padding: u27, + }), + /// data input register. + DIN: u32, + /// data output register. + DOUT: u32, + /// DMA control register. + DMACR: mmio.Mmio(packed struct(u32) { + /// DMA input enable. + DIEN: u1, + /// DMA output enable. + DOEN: u1, + padding: u30, + }), + /// interrupt mask set/clear register. + IMSCR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service interrupt mask. + INIM: u1, + /// Output FIFO service interrupt mask. + OUTIM: u1, + padding: u30, + }), + /// raw interrupt status register. + RISR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service raw interrupt status. + INRIS: u1, + /// Output FIFO service raw interrupt status. + OUTRIS: u1, + padding: u30, + }), + /// masked interrupt status register. + MISR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service masked interrupt status. + INMIS: u1, + /// Output FIFO service masked interrupt status. + OUTMIS: u1, + padding: u30, + }), + /// Cluster KEY%s, containing K?LR, K?RR. + KEY: u32, + reserved64: [28]u8, + /// Cluster INIT%s, containing IV?LR, IV?RR. + INIT: u32, + reserved80: [12]u8, + /// context swap register. + CSGCMCCMR: [8]u32, + /// context swap register. + CSGCMR: [8]u32, + }; + + /// Cluster INIT%s, containing IV?LR, IV?RR. + pub const INIT = extern struct { + /// initialization vector registers. + IVLR: u32, + /// initialization vector registers. + IVRR: u32, + }; + + /// Cluster KEY%s, containing K?LR, K?RR. + pub const KEY = extern struct { + /// key registers. + KLR: u32, + /// key registers. + KRR: u32, + }; + }; + + pub const cryp_v4 = struct { + pub const KMOD = enum(u2) { + /// Normal-key mode. Key registers are freely usable. + Normal = 0x0, + /// Shared-key mode. If shared-key mode is properly initialized in SAES peripheral, the CRYP peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in CRYP key registers when BUSY bit is cleared and KEYVALID is set in the CRYP_SR register. Key error flag KERF is set otherwise in the CRYP_SR register. + Shared = 0x2, _, }; - pub const PERSEL = enum(u2) { - /// hsi_ker_ck selected as kernel clock (default after reset) - HSI = 0x0, - /// csi_ker_ck selected as kernel clock - CSI = 0x1, - /// hse_ck selected as kernel clock - HSE = 0x2, + /// Cryptographic processor. + pub const CRYP = extern struct { + /// control register. + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Algorithm direction. + ALGODIR: u1, + /// Algorithm mode. + ALGOMODE0: u3, + /// Data type selection. + DATATYPE: u2, + /// Key size selection (AES mode only). + KEYSIZE: u2, + reserved14: u4, + /// FIFO flush. + FFLUSH: u1, + /// Cryptographic processor enable. + CRYPEN: u1, + /// GCM_CCMPH. + GCM_CCMPH: u2, + reserved19: u1, + /// ALGOMODE. + ALGOMODE3: u1, + /// Number of Padding Bytes in Last Block of payload. + NPBLB: u4, + /// Key mode selection This bitfield defines how the CRYP key can be used by the application. KEYSIZE must be correctly initialized when setting KMOD[1:0] different from zero. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set. + KMOD: packed union { + raw: u2, + value: KMOD, + }, + reserved31: u5, + /// CRYP peripheral software reset Setting the bit resets the CRYP peripheral, putting all registers to their default values, except the IPRST bit itself. This bit must be kept cleared while writing any configuration registers. + IPRST: u1, + }), + /// status register. + SR: mmio.Mmio(packed struct(u32) { + /// Input FIFO empty. + IFEM: u1, + /// Input FIFO not full. + IFNF: u1, + /// Output FIFO not empty. + OFNE: u1, + /// Output FIFO full. + OFFU: u1, + /// Busy bit. + BUSY: u1, + reserved6: u1, + /// Key error flag This read-only bit is set by hardware when key information failed to load into key registers. KERF is triggered upon any of the following errors: CRYP_KxR/LR register write does not respect the correct order (refer to Section 60.4.16: CRYP key registers for details). CRYP fails to load the key shared by SAES peripheral (KMOD = 0x2). KERF must be cleared by the application software, otherwise KEYVALID cannot be set. It can be done through IPRST bit of CRYP_CR, or when a correct key writing sequence starts. + KERF: u1, + /// Key valid flag This read-only bit is set by hardware when the key of size defined by KEYSIZE is loaded in CRYP_KxR/LR key registers. The CRYPEN bit can only be set when KEYVALID is set. In normal mode when KMOD[1:0] is at zero, the key must be written in the key registers in the correct sequence, otherwise the KERF flag is set and KEYVALID remains cleared. When KMOD[1:0] is different from zero, the BUSY flag is automatically set by CRYP. When the key is loaded successfully, BUSY is cleared and KEYVALID set. Upon an error, KERF is set, BUSY cleared and KEYVALID remains cleared. If set, KERF must be cleared, otherwise KEYVALID cannot be set. For further information on key loading, refer to Section 60.4.16: CRYP key registers. + KEYVALID: u1, + padding: u24, + }), + /// data input register. + DIN: u32, + /// data output register. + DOUT: u32, + /// DMA control register. + DMACR: mmio.Mmio(packed struct(u32) { + /// DMA input enable. + DIEN: u1, + /// DMA output enable. + DOEN: u1, + padding: u30, + }), + /// interrupt mask set/clear register. + IMSCR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service interrupt mask. + INIM: u1, + /// Output FIFO service interrupt mask. + OUTIM: u1, + padding: u30, + }), + /// raw interrupt status register. + RISR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service raw interrupt status. + INRIS: u1, + /// Output FIFO service raw interrupt status. + OUTRIS: u1, + padding: u30, + }), + /// masked interrupt status register. + MISR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service masked interrupt status. + INMIS: u1, + /// Output FIFO service masked interrupt status. + OUTMIS: u1, + padding: u30, + }), + /// Cluster KEY%s, containing K?LR, K?RR. + KEY: u32, + reserved64: [28]u8, + /// Cluster INIT%s, containing IV?LR, IV?RR. + INIT: u32, + reserved80: [12]u8, + /// context swap register. + CSGCMCCMR: [8]u32, + /// context swap register. + CSGCMR: [8]u32, + }; + + /// Cluster INIT%s, containing IV?LR, IV?RR. + pub const INIT = extern struct { + /// initialization vector registers. + IVLR: u32, + /// initialization vector registers. + IVRR: u32, + }; + + /// Cluster KEY%s, containing K?LR, K?RR. + pub const KEY = extern struct { + /// key registers. + KLR: u32, + /// key registers. + KRR: u32, + }; + }; + + pub const dac_v1 = struct { + pub const WAVE = enum(u2) { + /// Wave generation disabled + Disabled = 0x0, + /// Noise wave generation enabled + Noise = 0x1, + /// Triangle wave generation enabled + Triangle = 0x2, _, }; - pub const PLLDIV = enum(u7) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, - Div17 = 0x10, - Div18 = 0x11, - Div19 = 0x12, - Div20 = 0x13, - Div21 = 0x14, - Div22 = 0x15, - Div23 = 0x16, - Div24 = 0x17, - Div25 = 0x18, - Div26 = 0x19, - Div27 = 0x1a, - Div28 = 0x1b, - Div29 = 0x1c, - Div30 = 0x1d, - Div31 = 0x1e, - Div32 = 0x1f, - Div33 = 0x20, - Div34 = 0x21, - Div35 = 0x22, - Div36 = 0x23, - Div37 = 0x24, - Div38 = 0x25, - Div39 = 0x26, - Div40 = 0x27, - Div41 = 0x28, - Div42 = 0x29, - Div43 = 0x2a, - Div44 = 0x2b, - Div45 = 0x2c, - Div46 = 0x2d, - Div47 = 0x2e, - Div48 = 0x2f, - Div49 = 0x30, - Div50 = 0x31, - Div51 = 0x32, - Div52 = 0x33, - Div53 = 0x34, - Div54 = 0x35, - Div55 = 0x36, - Div56 = 0x37, - Div57 = 0x38, - Div58 = 0x39, - Div59 = 0x3a, - Div60 = 0x3b, - Div61 = 0x3c, - Div62 = 0x3d, - Div63 = 0x3e, - Div64 = 0x3f, - Div65 = 0x40, - Div66 = 0x41, - Div67 = 0x42, - Div68 = 0x43, - Div69 = 0x44, - Div70 = 0x45, - Div71 = 0x46, - Div72 = 0x47, - Div73 = 0x48, - Div74 = 0x49, - Div75 = 0x4a, - Div76 = 0x4b, - Div77 = 0x4c, - Div78 = 0x4d, - Div79 = 0x4e, - Div80 = 0x4f, - Div81 = 0x50, - Div82 = 0x51, - Div83 = 0x52, - Div84 = 0x53, - Div85 = 0x54, - Div86 = 0x55, - Div87 = 0x56, - Div88 = 0x57, - Div89 = 0x58, - Div90 = 0x59, - Div91 = 0x5a, - Div92 = 0x5b, - Div93 = 0x5c, - Div94 = 0x5d, - Div95 = 0x5e, - Div96 = 0x5f, - Div97 = 0x60, - Div98 = 0x61, - Div99 = 0x62, - Div100 = 0x63, - Div101 = 0x64, - Div102 = 0x65, - Div103 = 0x66, - Div104 = 0x67, - Div105 = 0x68, - Div106 = 0x69, - Div107 = 0x6a, - Div108 = 0x6b, - Div109 = 0x6c, - Div110 = 0x6d, - Div111 = 0x6e, - Div112 = 0x6f, - Div113 = 0x70, - Div114 = 0x71, - Div115 = 0x72, - Div116 = 0x73, - Div117 = 0x74, - Div118 = 0x75, - Div119 = 0x76, - Div120 = 0x77, - Div121 = 0x78, - Div122 = 0x79, - Div123 = 0x7a, - Div124 = 0x7b, - Div125 = 0x7c, - Div126 = 0x7d, - Div127 = 0x7e, - Div128 = 0x7f, + /// Digital-to-analog converter + pub const DAC = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// channel enable + EN: u1, + /// channel output buffer disable + BOFF: u1, + /// channel trigger enable + TEN: u1, + /// channel trigger selection + TSEL: u3, + /// channel noise/triangle wave generation enable + WAVE: packed union { + raw: u2, + value: WAVE, + }, + /// channel mask/amplitude selector + MAMP: u4, + /// channel DMA enable + DMAEN: u1, + padding: u19, + }), + /// software trigger register + SWTRIGR: mmio.Mmio(packed struct(u32) { + /// channel software trigger + SWTRIG: u1, + padding: u31, + }), + /// channel 12-bit right-aligned data holding register + DHR12R: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + padding: u20, + }), + /// channel 12-bit left-aligned data holding register + DHR12L: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + padding: u16, + }), + /// channel 8-bit right-aligned data holding register + DHR8R: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + padding: u24, + }), + reserved32: [12]u8, + /// dual 12-bit right-aligned data holding register + DHR12RD: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + padding: u20, + }), + /// dual 12-bit left aligned data holding register + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + padding: u16, + }), + /// dual 8-bit right aligned data holding register + DHR8RD: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + padding: u24, + }), + /// channel data output register + DOR: [2]mmio.Mmio(packed struct(u32) { + /// channel data output + DOR: u12, + padding: u20, + }), }; + }; - pub const PLLM = enum(u6) { - Div1 = 0x1, - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - Div16 = 0x10, - Div17 = 0x11, - Div18 = 0x12, - Div19 = 0x13, - Div20 = 0x14, - Div21 = 0x15, - Div22 = 0x16, - Div23 = 0x17, - Div24 = 0x18, - Div25 = 0x19, - Div26 = 0x1a, - Div27 = 0x1b, - Div28 = 0x1c, - Div29 = 0x1d, - Div30 = 0x1e, - Div31 = 0x1f, - Div32 = 0x20, - Div33 = 0x21, - Div34 = 0x22, - Div35 = 0x23, - Div36 = 0x24, - Div37 = 0x25, - Div38 = 0x26, - Div39 = 0x27, - Div40 = 0x28, - Div41 = 0x29, - Div42 = 0x2a, - Div43 = 0x2b, - Div44 = 0x2c, - Div45 = 0x2d, - Div46 = 0x2e, - Div47 = 0x2f, - Div48 = 0x30, - Div49 = 0x31, - Div50 = 0x32, - Div51 = 0x33, - Div52 = 0x34, - Div53 = 0x35, - Div54 = 0x36, - Div55 = 0x37, - Div56 = 0x38, - Div57 = 0x39, - Div58 = 0x3a, - Div59 = 0x3b, - Div60 = 0x3c, - Div61 = 0x3d, - Div62 = 0x3e, + pub const dac_v2 = struct { + pub const WAVE = enum(u2) { + /// Wave generation disabled + Disabled = 0x0, + /// Noise wave generation enabled + Noise = 0x1, + /// Triangle wave generation enabled + Triangle = 0x2, _, }; - pub const PLLN = enum(u9) { - Mul4 = 0x3, - Mul5 = 0x4, - Mul6 = 0x5, - Mul7 = 0x6, - Mul8 = 0x7, - Mul9 = 0x8, - Mul10 = 0x9, - Mul11 = 0xa, - Mul12 = 0xb, - Mul13 = 0xc, - Mul14 = 0xd, - Mul15 = 0xe, - Mul16 = 0xf, - Mul17 = 0x10, - Mul18 = 0x11, - Mul19 = 0x12, - Mul20 = 0x13, - Mul21 = 0x14, - Mul22 = 0x15, - Mul23 = 0x16, - Mul24 = 0x17, - Mul25 = 0x18, - Mul26 = 0x19, - Mul27 = 0x1a, - Mul28 = 0x1b, - Mul29 = 0x1c, - Mul30 = 0x1d, - Mul31 = 0x1e, - Mul32 = 0x1f, - Mul33 = 0x20, - Mul34 = 0x21, - Mul35 = 0x22, - Mul36 = 0x23, - Mul37 = 0x24, - Mul38 = 0x25, - Mul39 = 0x26, - Mul40 = 0x27, - Mul41 = 0x28, - Mul42 = 0x29, - Mul43 = 0x2a, - Mul44 = 0x2b, - Mul45 = 0x2c, - Mul46 = 0x2d, - Mul47 = 0x2e, - Mul48 = 0x2f, - Mul49 = 0x30, - Mul50 = 0x31, - Mul51 = 0x32, - Mul52 = 0x33, - Mul53 = 0x34, - Mul54 = 0x35, - Mul55 = 0x36, - Mul56 = 0x37, - Mul57 = 0x38, - Mul58 = 0x39, - Mul59 = 0x3a, - Mul60 = 0x3b, - Mul61 = 0x3c, - Mul62 = 0x3d, - Mul63 = 0x3e, - Mul64 = 0x3f, - Mul65 = 0x40, - Mul66 = 0x41, - Mul67 = 0x42, - Mul68 = 0x43, - Mul69 = 0x44, - Mul70 = 0x45, - Mul71 = 0x46, - Mul72 = 0x47, - Mul73 = 0x48, - Mul74 = 0x49, - Mul75 = 0x4a, - Mul76 = 0x4b, - Mul77 = 0x4c, - Mul78 = 0x4d, - Mul79 = 0x4e, - Mul80 = 0x4f, - Mul81 = 0x50, - Mul82 = 0x51, - Mul83 = 0x52, - Mul84 = 0x53, - Mul85 = 0x54, - Mul86 = 0x55, - Mul87 = 0x56, - Mul88 = 0x57, - Mul89 = 0x58, - Mul90 = 0x59, - Mul91 = 0x5a, - Mul92 = 0x5b, - Mul93 = 0x5c, - Mul94 = 0x5d, - Mul95 = 0x5e, - Mul96 = 0x5f, - Mul97 = 0x60, - Mul98 = 0x61, - Mul99 = 0x62, - Mul100 = 0x63, - Mul101 = 0x64, - Mul102 = 0x65, - Mul103 = 0x66, - Mul104 = 0x67, - Mul105 = 0x68, - Mul106 = 0x69, - Mul107 = 0x6a, - Mul108 = 0x6b, - Mul109 = 0x6c, - Mul110 = 0x6d, - Mul111 = 0x6e, - Mul112 = 0x6f, - Mul113 = 0x70, - Mul114 = 0x71, - Mul115 = 0x72, - Mul116 = 0x73, - Mul117 = 0x74, - Mul118 = 0x75, - Mul119 = 0x76, - Mul120 = 0x77, - Mul121 = 0x78, - Mul122 = 0x79, - Mul123 = 0x7a, - Mul124 = 0x7b, - Mul125 = 0x7c, - Mul126 = 0x7d, - Mul127 = 0x7e, - Mul128 = 0x7f, - Mul129 = 0x80, - Mul130 = 0x81, - Mul131 = 0x82, - Mul132 = 0x83, - Mul133 = 0x84, - Mul134 = 0x85, - Mul135 = 0x86, - Mul136 = 0x87, - Mul137 = 0x88, - Mul138 = 0x89, - Mul139 = 0x8a, - Mul140 = 0x8b, - Mul141 = 0x8c, - Mul142 = 0x8d, - Mul143 = 0x8e, - Mul144 = 0x8f, - Mul145 = 0x90, - Mul146 = 0x91, - Mul147 = 0x92, - Mul148 = 0x93, - Mul149 = 0x94, - Mul150 = 0x95, - Mul151 = 0x96, - Mul152 = 0x97, - Mul153 = 0x98, - Mul154 = 0x99, - Mul155 = 0x9a, - Mul156 = 0x9b, - Mul157 = 0x9c, - Mul158 = 0x9d, - Mul159 = 0x9e, - Mul160 = 0x9f, - Mul161 = 0xa0, - Mul162 = 0xa1, - Mul163 = 0xa2, - Mul164 = 0xa3, - Mul165 = 0xa4, - Mul166 = 0xa5, - Mul167 = 0xa6, - Mul168 = 0xa7, - Mul169 = 0xa8, - Mul170 = 0xa9, - Mul171 = 0xaa, - Mul172 = 0xab, - Mul173 = 0xac, - Mul174 = 0xad, - Mul175 = 0xae, - Mul176 = 0xaf, - Mul177 = 0xb0, - Mul178 = 0xb1, - Mul179 = 0xb2, - Mul180 = 0xb3, - Mul181 = 0xb4, - Mul182 = 0xb5, - Mul183 = 0xb6, - Mul184 = 0xb7, - Mul185 = 0xb8, - Mul186 = 0xb9, - Mul187 = 0xba, - Mul188 = 0xbb, - Mul189 = 0xbc, - Mul190 = 0xbd, - Mul191 = 0xbe, - Mul192 = 0xbf, - Mul193 = 0xc0, - Mul194 = 0xc1, - Mul195 = 0xc2, - Mul196 = 0xc3, - Mul197 = 0xc4, - Mul198 = 0xc5, - Mul199 = 0xc6, - Mul200 = 0xc7, - Mul201 = 0xc8, - Mul202 = 0xc9, - Mul203 = 0xca, - Mul204 = 0xcb, - Mul205 = 0xcc, - Mul206 = 0xcd, - Mul207 = 0xce, - Mul208 = 0xcf, - Mul209 = 0xd0, - Mul210 = 0xd1, - Mul211 = 0xd2, - Mul212 = 0xd3, - Mul213 = 0xd4, - Mul214 = 0xd5, - Mul215 = 0xd6, - Mul216 = 0xd7, - Mul217 = 0xd8, - Mul218 = 0xd9, - Mul219 = 0xda, - Mul220 = 0xdb, - Mul221 = 0xdc, - Mul222 = 0xdd, - Mul223 = 0xde, - Mul224 = 0xdf, - Mul225 = 0xe0, - Mul226 = 0xe1, - Mul227 = 0xe2, - Mul228 = 0xe3, - Mul229 = 0xe4, - Mul230 = 0xe5, - Mul231 = 0xe6, - Mul232 = 0xe7, - Mul233 = 0xe8, - Mul234 = 0xe9, - Mul235 = 0xea, - Mul236 = 0xeb, - Mul237 = 0xec, - Mul238 = 0xed, - Mul239 = 0xee, - Mul240 = 0xef, - Mul241 = 0xf0, - Mul242 = 0xf1, - Mul243 = 0xf2, - Mul244 = 0xf3, - Mul245 = 0xf4, - Mul246 = 0xf5, - Mul247 = 0xf6, - Mul248 = 0xf7, - Mul249 = 0xf8, - Mul250 = 0xf9, - Mul251 = 0xfa, - Mul252 = 0xfb, - Mul253 = 0xfc, - Mul254 = 0xfd, - Mul255 = 0xfe, - Mul256 = 0xff, - Mul257 = 0x100, - Mul258 = 0x101, - Mul259 = 0x102, - Mul260 = 0x103, - Mul261 = 0x104, - Mul262 = 0x105, - Mul263 = 0x106, - Mul264 = 0x107, - Mul265 = 0x108, - Mul266 = 0x109, - Mul267 = 0x10a, - Mul268 = 0x10b, - Mul269 = 0x10c, - Mul270 = 0x10d, - Mul271 = 0x10e, - Mul272 = 0x10f, - Mul273 = 0x110, - Mul274 = 0x111, - Mul275 = 0x112, - Mul276 = 0x113, - Mul277 = 0x114, - Mul278 = 0x115, - Mul279 = 0x116, - Mul280 = 0x117, - Mul281 = 0x118, - Mul282 = 0x119, - Mul283 = 0x11a, - Mul284 = 0x11b, - Mul285 = 0x11c, - Mul286 = 0x11d, - Mul287 = 0x11e, - Mul288 = 0x11f, - Mul289 = 0x120, - Mul290 = 0x121, - Mul291 = 0x122, - Mul292 = 0x123, - Mul293 = 0x124, - Mul294 = 0x125, - Mul295 = 0x126, - Mul296 = 0x127, - Mul297 = 0x128, - Mul298 = 0x129, - Mul299 = 0x12a, - Mul300 = 0x12b, - Mul301 = 0x12c, - Mul302 = 0x12d, - Mul303 = 0x12e, - Mul304 = 0x12f, - Mul305 = 0x130, - Mul306 = 0x131, - Mul307 = 0x132, - Mul308 = 0x133, - Mul309 = 0x134, - Mul310 = 0x135, - Mul311 = 0x136, - Mul312 = 0x137, - Mul313 = 0x138, - Mul314 = 0x139, - Mul315 = 0x13a, - Mul316 = 0x13b, - Mul317 = 0x13c, - Mul318 = 0x13d, - Mul319 = 0x13e, - Mul320 = 0x13f, - Mul321 = 0x140, - Mul322 = 0x141, - Mul323 = 0x142, - Mul324 = 0x143, - Mul325 = 0x144, - Mul326 = 0x145, - Mul327 = 0x146, - Mul328 = 0x147, - Mul329 = 0x148, - Mul330 = 0x149, - Mul331 = 0x14a, - Mul332 = 0x14b, - Mul333 = 0x14c, - Mul334 = 0x14d, - Mul335 = 0x14e, - Mul336 = 0x14f, - Mul337 = 0x150, - Mul338 = 0x151, - Mul339 = 0x152, - Mul340 = 0x153, - Mul341 = 0x154, - Mul342 = 0x155, - Mul343 = 0x156, - Mul344 = 0x157, - Mul345 = 0x158, - Mul346 = 0x159, - Mul347 = 0x15a, - Mul348 = 0x15b, - Mul349 = 0x15c, - Mul350 = 0x15d, - Mul351 = 0x15e, - Mul352 = 0x15f, - Mul353 = 0x160, - Mul354 = 0x161, - Mul355 = 0x162, - Mul356 = 0x163, - Mul357 = 0x164, - Mul358 = 0x165, - Mul359 = 0x166, - Mul360 = 0x167, - Mul361 = 0x168, - Mul362 = 0x169, - Mul363 = 0x16a, - Mul364 = 0x16b, - Mul365 = 0x16c, - Mul366 = 0x16d, - Mul367 = 0x16e, - Mul368 = 0x16f, - Mul369 = 0x170, - Mul370 = 0x171, - Mul371 = 0x172, - Mul372 = 0x173, - Mul373 = 0x174, - Mul374 = 0x175, - Mul375 = 0x176, - Mul376 = 0x177, - Mul377 = 0x178, - Mul378 = 0x179, - Mul379 = 0x17a, - Mul380 = 0x17b, - Mul381 = 0x17c, - Mul382 = 0x17d, - Mul383 = 0x17e, - Mul384 = 0x17f, - Mul385 = 0x180, - Mul386 = 0x181, - Mul387 = 0x182, - Mul388 = 0x183, - Mul389 = 0x184, - Mul390 = 0x185, - Mul391 = 0x186, - Mul392 = 0x187, - Mul393 = 0x188, - Mul394 = 0x189, - Mul395 = 0x18a, - Mul396 = 0x18b, - Mul397 = 0x18c, - Mul398 = 0x18d, - Mul399 = 0x18e, - Mul400 = 0x18f, - Mul401 = 0x190, - Mul402 = 0x191, - Mul403 = 0x192, - Mul404 = 0x193, - Mul405 = 0x194, - Mul406 = 0x195, - Mul407 = 0x196, - Mul408 = 0x197, - Mul409 = 0x198, - Mul410 = 0x199, - Mul411 = 0x19a, - Mul412 = 0x19b, - Mul413 = 0x19c, - Mul414 = 0x19d, - Mul415 = 0x19e, - Mul416 = 0x19f, - Mul417 = 0x1a0, - Mul418 = 0x1a1, - Mul419 = 0x1a2, - Mul420 = 0x1a3, - Mul421 = 0x1a4, - Mul422 = 0x1a5, - Mul423 = 0x1a6, - Mul424 = 0x1a7, - Mul425 = 0x1a8, - Mul426 = 0x1a9, - Mul427 = 0x1aa, - Mul428 = 0x1ab, - Mul429 = 0x1ac, - Mul430 = 0x1ad, - Mul431 = 0x1ae, - Mul432 = 0x1af, - Mul433 = 0x1b0, - Mul434 = 0x1b1, - Mul435 = 0x1b2, - Mul436 = 0x1b3, - Mul437 = 0x1b4, - Mul438 = 0x1b5, - Mul439 = 0x1b6, - Mul440 = 0x1b7, - Mul441 = 0x1b8, - Mul442 = 0x1b9, - Mul443 = 0x1ba, - Mul444 = 0x1bb, - Mul445 = 0x1bc, - Mul446 = 0x1bd, - Mul447 = 0x1be, - Mul448 = 0x1bf, - Mul449 = 0x1c0, - Mul450 = 0x1c1, - Mul451 = 0x1c2, - Mul452 = 0x1c3, - Mul453 = 0x1c4, - Mul454 = 0x1c5, - Mul455 = 0x1c6, - Mul456 = 0x1c7, - Mul457 = 0x1c8, - Mul458 = 0x1c9, - Mul459 = 0x1ca, - Mul460 = 0x1cb, - Mul461 = 0x1cc, - Mul462 = 0x1cd, - Mul463 = 0x1ce, - Mul464 = 0x1cf, - Mul465 = 0x1d0, - Mul466 = 0x1d1, - Mul467 = 0x1d2, - Mul468 = 0x1d3, - Mul469 = 0x1d4, - Mul470 = 0x1d5, - Mul471 = 0x1d6, - Mul472 = 0x1d7, - Mul473 = 0x1d8, - Mul474 = 0x1d9, - Mul475 = 0x1da, - Mul476 = 0x1db, - Mul477 = 0x1dc, - Mul478 = 0x1dd, - Mul479 = 0x1de, - Mul480 = 0x1df, - Mul481 = 0x1e0, - Mul482 = 0x1e1, - Mul483 = 0x1e2, - Mul484 = 0x1e3, - Mul485 = 0x1e4, - Mul486 = 0x1e5, - Mul487 = 0x1e6, - Mul488 = 0x1e7, - Mul489 = 0x1e8, - Mul490 = 0x1e9, - Mul491 = 0x1ea, - Mul492 = 0x1eb, - Mul493 = 0x1ec, - Mul494 = 0x1ed, - Mul495 = 0x1ee, - Mul496 = 0x1ef, - Mul497 = 0x1f0, - Mul498 = 0x1f1, - Mul499 = 0x1f2, - Mul500 = 0x1f3, - Mul501 = 0x1f4, - Mul502 = 0x1f5, - Mul503 = 0x1f6, - Mul504 = 0x1f7, - Mul505 = 0x1f8, - Mul506 = 0x1f9, - Mul507 = 0x1fa, - Mul508 = 0x1fb, - Mul509 = 0x1fc, - Mul510 = 0x1fd, - Mul511 = 0x1fe, - Mul512 = 0x1ff, - _, - }; - - pub const PLLRGE = enum(u2) { - /// Frequency is between 1 and 2 MHz - Range1 = 0x0, - /// Frequency is between 2 and 4 MHz - Range2 = 0x1, - /// Frequency is between 4 and 8 MHz - Range4 = 0x2, - /// Frequency is between 8 and 16 MHz - Range8 = 0x3, - }; - - pub const PLLSRC = enum(u2) { - /// no clock send to DIVMx divider and PLLs (default after reset) - DISABLE = 0x0, - /// HSI selected as PLL clock (hsi_ck) - HSI = 0x1, - /// CSI selected as PLL clock (csi_ck) - CSI = 0x2, - /// HSE selected as PLL clock (hse_ck) - HSE = 0x3, - }; - - pub const PLLVCOSEL = enum(u1) { - /// VCO frequency range 192 to 836 MHz - WideVCO = 0x0, - /// VCO frequency range 150 to 420 MHz - MediumVCO = 0x1, - }; - - pub const PPRE = enum(u3) { - /// rcc_pclk3 = rcc_hclk1 / 1 - Div1 = 0x0, - /// rcc_pclk3 = rcc_hclk1 / 2 - Div2 = 0x4, - /// rcc_pclk3 = rcc_hclk1 / 4 - Div4 = 0x5, - /// rcc_pclk3 = rcc_hclk1 / 8 - Div8 = 0x6, - /// rcc_pclk3 = rcc_hclk1 / 16 - Div16 = 0x7, - _, - }; - - pub const RNGSEL = enum(u2) { - /// hsi48_ker_ck selected as kernel clock (default after reset) - HSI48 = 0x0, - /// pll1_q_ck selected as kernel clock - PLL1_Q = 0x1, - /// lse_ck selected as kernel clock - LSE = 0x2, - /// lsi_ker_ck selected as kernel clock - LSI = 0x3, + /// Digital-to-analog converter + pub const DAC = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// channel enable + EN: u1, + /// channel output buffer disable + BOFF: u1, + /// channel trigger enable + TEN: u1, + /// channel trigger selection + TSEL: u3, + /// channel noise/triangle wave generation enable + WAVE: packed union { + raw: u2, + value: WAVE, + }, + /// channel mask/amplitude selector + MAMP: u4, + /// channel DMA enable + DMAEN: u1, + /// channel DMA Underrun Interrupt enable + DMAUDRIE: u1, + padding: u18, + }), + /// software trigger register + SWTRIGR: mmio.Mmio(packed struct(u32) { + /// channel software trigger + SWTRIG: u1, + padding: u31, + }), + /// channel 12-bit right-aligned data holding register + DHR12R: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + padding: u20, + }), + /// channel 12-bit left-aligned data holding register + DHR12L: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + padding: u16, + }), + /// channel 8-bit right-aligned data holding register + DHR8R: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + padding: u24, + }), + reserved32: [12]u8, + /// dual 12-bit right-aligned data holding register + DHR12RD: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + padding: u20, + }), + /// dual 12-bit left aligned data holding register + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + padding: u16, + }), + /// dual 8-bit right aligned data holding register + DHR8RD: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + padding: u24, + }), + /// channel data output register + DOR: [2]mmio.Mmio(packed struct(u32) { + /// channel data output + DOR: u12, + padding: u20, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// channel DMA underrun flag + DMAUDR: u1, + padding: u18, + }), }; + }; - pub const RTCSEL = enum(u2) { - /// no clock (default after Backup domain reset) - DISABLE = 0x0, - /// LSE selected as RTC clock - LSE = 0x1, - /// LSI selected as RTC clock - LSI = 0x2, - /// HSE divided by RTCPRE value selected as RTC clock - HSE_DIV_RTCPRE = 0x3, + pub const dac_v3 = struct { + pub const MODE = enum(u3) { + /// Normal mode, external pin only, buffer enabled + NORMAL_EXT_BUFEN = 0x0, + /// Normal mode, external pin and internal peripherals, buffer enabled + NORMAL_EXT_INT_BUFEN = 0x1, + /// Normal mode, external pin only, buffer disabled + NORMAL_EXT_BUFDIS = 0x2, + /// Normal mode, internal peripherals only, buffer disabled + NORMAL_INT_BUFDIS = 0x3, + /// Sample and hold mode, external pin only, buffer enabled + SAMPHOLD_EXT_BUFEN = 0x4, + /// Sample and hold mode, external pin and internal peripherals, buffer enabled + SAMPHOLD_EXT_INT_BUFEN = 0x5, + /// Sample and hold mode, external pin and internal peripherals, buffer disabled + SAMPHOLD_EXT_INT_BUFDIS = 0x6, + /// Sample and hold mode, internal peripherals only, buffer disabled + SAMPHOLD_INT_BUFDIS = 0x7, }; - pub const SPISEL = enum(u3) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// hsi_ker selected as peripheral clock - AUDIOCLK = 0x3, - /// csi_ker selected as peripheral clock - PER = 0x4, + pub const WAVE = enum(u2) { + /// Wave generation disabled + Disabled = 0x0, + /// Noise wave generation enabled + Noise = 0x1, + /// Triangle wave generation enabled + Triangle = 0x2, _, }; - pub const STOPKERWUCK = enum(u1) { - /// HSI selected as wakeup clock from system Stop (default after reset) - HSI = 0x0, - /// CSI selected as wakeup clock from system Stop - CSI = 0x1, - }; - - pub const STOPWUCK = enum(u1) { - /// CSI selected as wakeup clock from system Stop - CSI = 0x1, - _, + /// Digital-to-analog converter + pub const DAC = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// channel enable + EN: u1, + reserved2: u1, + /// channel trigger enable + TEN: u1, + /// channel trigger selection + TSEL: u3, + /// channel noise/triangle wave generation enable + WAVE: packed union { + raw: u2, + value: WAVE, + }, + /// channel mask/amplitude selector + MAMP: u4, + /// channel DMA enable + DMAEN: u1, + /// channel DMA Underrun Interrupt enable + DMAUDRIE: u1, + /// DAC channel calibration enable + CEN: u1, + padding: u17, + }), + /// software trigger register + SWTRIGR: mmio.Mmio(packed struct(u32) { + /// channel software trigger + SWTRIG: u1, + padding: u31, + }), + /// channel 12-bit right-aligned data holding register + DHR12R: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + padding: u20, + }), + /// channel 12-bit left-aligned data holding register + DHR12L: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + padding: u16, + }), + /// channel 8-bit right-aligned data holding register + DHR8R: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + padding: u24, + }), + reserved32: [12]u8, + /// dual 12-bit right-aligned data holding register + DHR12RD: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + padding: u20, + }), + /// dual 12-bit left aligned data holding register + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + padding: u16, + }), + /// dual 8-bit right aligned data holding register + DHR8RD: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + padding: u24, + }), + /// channel data output register + DOR: [2]mmio.Mmio(packed struct(u32) { + /// channel data output + DOR: u12, + padding: u20, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// channel DMA underrun flag + DMAUDR: u1, + /// channel calibration offset status + CAL_FLAG: u1, + /// channel busy writing sample time flag + BWST: u1, + padding: u16, + }), + /// calibration control register + CCR: mmio.Mmio(packed struct(u32) { + /// channel offset trimming value + OTRIM: u5, + padding: u27, + }), + /// mode control register + MCR: mmio.Mmio(packed struct(u32) { + /// DAC channel mode + MODE: packed union { + raw: u3, + value: MODE, + }, + padding: u29, + }), + /// sample and hold sample time register + SHSR: [2]mmio.Mmio(packed struct(u32) { + /// channel sample time + TSAMPLE: u10, + padding: u22, + }), + /// sample and hold hold time register + SHHR: mmio.Mmio(packed struct(u32) { + /// channel hold time + THOLD: u10, + padding: u22, + }), + /// sample and hold refresh time register + SHRR: mmio.Mmio(packed struct(u32) { + /// channel refresh time + TREFRESH: u8, + padding: u24, + }), }; + }; - pub const SW = enum(u3) { - /// HSI selected as system clock - HSI = 0x0, - /// CSI selected as system clock - CSI = 0x1, - /// HSE selected as system clock - HSE = 0x2, - /// PLL1 selected as system clock - PLL1_P = 0x3, - _, + pub const dac_v4 = struct { + pub const MODE = enum(u3) { + /// Normal mode, external pin only, buffer enabled + NORMAL_EXT_BUFEN = 0x0, + /// Normal mode, external pin and internal peripherals, buffer enabled + NORMAL_EXT_INT_BUFEN = 0x1, + /// Normal mode, external pin only, buffer disabled + NORMAL_EXT_BUFDIS = 0x2, + /// Normal mode, internal peripherals only, buffer disabled + NORMAL_INT_BUFDIS = 0x3, + /// Sample and hold mode, external pin only, buffer enabled + SAMPHOLD_EXT_BUFEN = 0x4, + /// Sample and hold mode, external pin and internal peripherals, buffer enabled + SAMPHOLD_EXT_INT_BUFEN = 0x5, + /// Sample and hold mode, external pin and internal peripherals, buffer disabled + SAMPHOLD_EXT_INT_BUFDIS = 0x6, + /// Sample and hold mode, internal peripherals only, buffer disabled + SAMPHOLD_INT_BUFDIS = 0x7, }; - pub const SYSTICKSEL = enum(u2) { - /// rcc_hclk/8 selected as clock source (default after reset) - HCLK1_DIV_8 = 0x0, - /// lsi_ker_ck[1] selected as clock source - LSI = 0x1, - /// lse_ck[1] selected as clock source - LSE = 0x2, + pub const WAVE = enum(u2) { + /// Wave generation disabled + Disabled = 0x0, + /// Noise wave generation enabled + Noise = 0x1, + /// Triangle wave generation enabled + Triangle = 0x2, _, }; - pub const TIMICSEL = enum(u1) { - /// No internal clock available for timers input capture (default after reset) - B_0x0 = 0x0, - /// hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture - B_0x1 = 0x1, - }; - - pub const TIMPRE = enum(u1) { - /// The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset) - DefaultX2 = 0x0, - /// The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2 - DefaultX4 = 0x1, - }; - - pub const USART1SEL = enum(u3) { - /// rcc_pclk2 selected as peripheral clock - PCLK2 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, - _, + /// Digital-to-analog converter + pub const DAC = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// channel enable + EN: u1, + /// channel trigger enable + TEN: u1, + /// channel trigger selection + TSEL: u4, + /// channel noise/triangle wave generation enable + WAVE: packed union { + raw: u2, + value: WAVE, + }, + /// channel mask/amplitude selector + MAMP: u4, + /// channel DMA enable + DMAEN: u1, + /// channel DMA Underrun Interrupt enable + DMAUDRIE: u1, + /// DAC channel calibration enable + CEN: u1, + padding: u17, + }), + /// software trigger register + SWTRIGR: mmio.Mmio(packed struct(u32) { + /// channel software trigger + SWTRIG: u1, + padding: u31, + }), + /// channel 12-bit right-aligned data holding register + DHR12R: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + padding: u20, + }), + /// channel 12-bit left-aligned data holding register + DHR12L: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + padding: u16, + }), + /// channel 8-bit right-aligned data holding register + DHR8R: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + padding: u24, + }), + reserved32: [12]u8, + /// dual 12-bit right-aligned data holding register + DHR12RD: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + padding: u20, + }), + /// dual 12-bit left aligned data holding register + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + padding: u16, + }), + /// dual 8-bit right aligned data holding register + DHR8RD: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + padding: u24, + }), + /// channel data output register + DOR: [2]mmio.Mmio(packed struct(u32) { + /// channel data output + DOR: u12, + padding: u20, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// channel DMA underrun flag + DMAUDR: u1, + /// channel calibration offset status + CAL_FLAG: u1, + /// channel busy writing sample time flag + BWST: u1, + padding: u16, + }), + /// calibration control register + CCR: mmio.Mmio(packed struct(u32) { + /// channel offset trimming value + OTRIM: u5, + padding: u27, + }), + /// mode control register + MCR: mmio.Mmio(packed struct(u32) { + /// DAC channel mode + MODE: packed union { + raw: u3, + value: MODE, + }, + padding: u29, + }), + /// sample and hold sample time register + SHSR: [2]mmio.Mmio(packed struct(u32) { + /// channel sample time + TSAMPLE: u10, + padding: u22, + }), + /// sample and hold hold time register + SHHR: mmio.Mmio(packed struct(u32) { + /// channel hold time + THOLD: u10, + padding: u22, + }), + /// sample and hold refresh time register + SHRR: mmio.Mmio(packed struct(u32) { + /// channel refresh time + TREFRESH: u8, + padding: u24, + }), }; + }; - pub const USARTSEL = enum(u3) { - /// rcc_pclk2 selected as peripheral clock - PCLK1 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, - _, + pub const dac_v5 = struct { + pub const MODE = enum(u3) { + /// Normal mode, external pin only, buffer enabled + NORMAL_EXT_BUFEN = 0x0, + /// Normal mode, external pin and internal peripherals, buffer enabled + NORMAL_EXT_INT_BUFEN = 0x1, + /// Normal mode, external pin only, buffer disabled + NORMAL_EXT_BUFDIS = 0x2, + /// Normal mode, internal peripherals only, buffer disabled + NORMAL_INT_BUFDIS = 0x3, + /// Sample and hold mode, external pin only, buffer enabled + SAMPHOLD_EXT_BUFEN = 0x4, + /// Sample and hold mode, external pin and internal peripherals, buffer enabled + SAMPHOLD_EXT_INT_BUFEN = 0x5, + /// Sample and hold mode, external pin and internal peripherals, buffer disabled + SAMPHOLD_EXT_INT_BUFDIS = 0x6, + /// Sample and hold mode, internal peripherals only, buffer disabled + SAMPHOLD_INT_BUFDIS = 0x7, }; - pub const USBSEL = enum(u2) { - /// Disable the kernel clock - DISABLE = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// HSI48 selected as peripheral clock - HSI48 = 0x3, + pub const WAVE = enum(u2) { + /// Wave generation disabled + Disabled = 0x0, + /// Noise wave generation enabled + Noise = 0x1, + /// Triangle wave generation enabled + Triangle = 0x2, _, }; - /// Reset and clock controller - pub const RCC = extern struct { - /// RCC clock control register + /// Digital-to-analog converter + pub const DAC = extern struct { + /// control register CR: mmio.Mmio(packed struct(u32) { - /// HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). - HSION: u1, - /// HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable. - HSIRDY: u1, - /// HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION. - HSIKERON: u1, - /// HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored. - HSIDIV: packed union { + /// channel enable + EN: u1, + /// channel trigger enable + TEN: u1, + /// channel trigger selection + TSEL: u4, + /// channel noise/triangle wave generation enable + WAVE: packed union { raw: u2, - value: HSIDIV, + value: WAVE, }, - /// HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. - HSIDIVF: u1, - reserved8: u2, - /// CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). - CSION: u1, - /// CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request). - CSIRDY: u1, - /// CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION. - CSIKERON: u1, - reserved12: u1, - /// HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode. - HSI48ON: u1, - /// HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable. - HSI48RDY: u1, - reserved16: u2, - /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). - HSEON: u1, - /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. - HSERDY: u1, - /// HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. - HSEBYP: u1, - /// HSE clock security system enable Set by software to enable clock security system on HSE. This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected. - HSECSSON: u1, - /// external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled. - HSEEXT: packed union { - raw: u1, - value: HSEEXT, - }, - reserved24: u3, - /// PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock. - PLLON: u1, - /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. - PLLRDY: u1, - padding: u6, - }), - reserved16: [12]u8, - /// RCC HSI calibration register - HSICFGR: mmio.Mmio(packed struct(u32) { - /// HSI clock calibration Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value. - HSICAL: u12, - reserved16: u4, - /// HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_OPT. After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated Note: The reset value of the field is 0x40. - HSITRIM: u7, - padding: u9, - }), - /// RCC clock recovery RC register - CRRCR: mmio.Mmio(packed struct(u32) { - /// Internal RC 48 MHz clock calibration Set by hardware by option-byte loading during system reset NRESET. Read-only. - HSI48CAL: u10, - padding: u22, + /// channel mask/amplitude selector + MAMP: u4, + /// channel DMA enable + DMAEN: u1, + /// channel DMA Underrun Interrupt enable + DMAUDRIE: u1, + /// DAC channel calibration enable + CEN: u1, + /// high frequency interface mode enable + HFSEL: u1, + padding: u16, }), - /// RCC CSI calibration register - CSICFGR: mmio.Mmio(packed struct(u32) { - /// CSI clock calibration Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value. - CSICAL: u8, - reserved16: u8, - /// CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_OPT. Note: The reset value of the field is 0x20. - CSITRIM: u6, - padding: u10, + /// software trigger register + SWTRIGR: mmio.Mmio(packed struct(u32) { + /// channel software trigger + SWTRIG: u1, + padding: u31, }), - /// RCC clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// system clock and trace clock switch Set and reset by software to select system clock and trace clock sources (sys_ck). Set by hardware in order to: - force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode - force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock others: reserved - SW: packed union { - raw: u3, - value: SW, - }, - /// system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset). others: reserved - SWS: packed union { - raw: u3, - value: SW, - }, - /// system clock selection after a wakeup from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset) STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10). - STOPWUCK: packed union { - raw: u1, - value: STOPWUCK, - }, - /// kernel clock selection after a wakeup from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. - STOPKERWUCK: packed union { - raw: u1, - value: STOPKERWUCK, - }, - /// HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ... - RTCPRE: u6, - reserved15: u1, - /// timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. - TIMPRE: packed union { - raw: u1, - value: TIMPRE, - }, - reserved18: u2, - /// MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... - MCO1PRE: packed union { - raw: u4, - value: MCOPRE, - }, - /// Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved - MCO1SEL: packed union { - raw: u3, - value: MCO1SEL, - }, - /// MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... - MCO2PRE: packed union { - raw: u4, - value: MCOPRE, - }, - /// microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved - MCO2SEL: packed union { - raw: u3, - value: MCO2SEL, - }, + /// channel 12-bit right-aligned data holding register + DHR12R: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + padding: u20, }), - /// RCC CPU domain clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// AHB prescaler Set and reset by software to control the division factor of rcc_hclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks 0xxx: rcc_hclk = sys_ck (default after reset) - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// APB low-speed prescaler (APB1) Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write. 0xx: rcc_pclk1 = rcc_hclk1 (default after reset) - PPRE1: packed union { - raw: u3, - value: PPRE, - }, - reserved8: u1, - /// APB high-speed prescaler (APB2) Set and reset by software to control APB high-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write. 0xx: rcc_pclk2 = rcc_hclk1 - PPRE2: packed union { - raw: u3, - value: PPRE, - }, - reserved12: u1, - /// APB low-speed prescaler (APB3) Set and reset by software to control APB low-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write. 0xx: rcc_pclk3 = rcc_hclk1 - PPRE3: packed union { - raw: u3, - value: PPRE, - }, - reserved16: u1, - /// AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals from RCC_AHB1ENR are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from RCC_AHB1ENR are off. enable control bits - AHB1DIS: u1, - /// AHB2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR are used and when their clocks are disabled in RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR are off. enable control bits - AHB2DIS: u1, - reserved19: u1, - /// AHB4 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB4 peripherals from RCC_AHB4ENR are used and when their clocks are disabled in RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from RCC_AHB4ENR are off. enable control bits - AHB4DIS: u1, - /// APB1 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. control bits - APB1DIS: u1, - /// APB2 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off. control bits - APB2DIS: u1, - /// APB3 clock disable value.Set and cleared by software This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. control bits - APB3DIS: u1, - padding: u9, + /// channel 12-bit left-aligned data holding register + DHR12L: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + padding: u16, }), - reserved40: [4]u8, - /// RCC PLL clock source selection register - PLLCFGR: [2]mmio.Mmio(packed struct(u32) { - /// DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset). - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - /// PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. - PLLRGE: packed union { - raw: u2, - value: PLLRGE, - }, - /// PLL1 fractional latch enable Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator. In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator. - PLLFRACEN: u1, - /// PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. - PLLVCOSEL: packed union { - raw: u1, - value: PLLVCOSEL, - }, - reserved8: u2, - /// prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... - DIVM: packed union { - raw: u6, - value: PLLM, - }, - reserved16: u2, - /// PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. - PLLPEN: u1, - /// PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). - PLLQEN: u1, - /// PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). - PLLREN: u1, - padding: u13, + /// channel 8-bit right-aligned data holding register + DHR8R: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + padding: u24, }), - reserved52: [4]u8, - /// RCC PLL1 dividers register - PLLDIVR: mmio.Mmio(packed struct(u32) { - /// Multiplication factor for PLL1VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved - PLLN: packed union { - raw: u9, - value: PLLN, - }, - /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... - PLLP: packed union { - raw: u7, - value: PLLDIV, - }, - /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLQ: packed union { - raw: u7, - value: PLLDIV, - }, - reserved24: u1, - /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLR: packed union { - raw: u7, - value: PLLDIV, - }, - padding: u1, + reserved32: [12]u8, + /// dual 12-bit right-aligned data holding register + DHR12RD: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + padding: u20, }), - /// RCC PLL1 fractional divider register - PLLFRACR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: * 128 to 560 MHz if PLL1VCOSEL = 0 * 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with * PLL1N between 8 and 420 * PLL1FRACN can be between 0 and 213- 1 * The input frequency Fref1_ck must be between 1 and 16 MHz. To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: * Set the bit PLL1FRACEN to 0 * Write the new fractional value into PLL1FRACN * Set the bit PLL1FRACEN to 1 - PLLFRACN: u13, + /// dual 12-bit left aligned data holding register + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, padding: u16, }), - reserved80: [20]u8, - /// RCC clock source interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization. - LSIRDYIE: u1, - /// LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization. - LSERDYIE: u1, - /// CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization. - CSIRDYIE: u1, - /// HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization. - HSIRDYIE: u1, - /// HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization. - HSERDYIE: u1, - /// HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. - HSI48RDYIE: u1, - /// PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. - PLLRDYIE: u1, - padding: u25, - }), - /// RCC clock source interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. - LSIRDYF: u1, - /// LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set. - LSERDYF: u1, - /// CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set. - CSIRDYF: u1, - /// HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set. - HSIRDYF: u1, - /// HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. - HSERDYF: u1, - /// HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. - HSI48RDYF: u1, - /// PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. - PLLRDYF: u1, - reserved10: u3, - /// HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. - HSECSSF: u1, - padding: u21, + /// dual 8-bit right aligned data holding register + DHR8RD: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + padding: u24, }), - /// RCC clock source interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done. - LSIRDYC: u1, - /// LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done. - LSERDYC: u1, - /// HSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done. - CSIRDYC: u1, - /// HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done. - HSIRDYC: u1, - /// HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done. - HSERDYC: u1, - /// HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. - HSI48RDYC: u1, - /// PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. - PLLRDYC: u1, - reserved10: u3, - /// HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done. - HSECSSC: u1, - padding: u21, + /// channel data output register + DOR: [2]mmio.Mmio(packed struct(u32) { + /// channel data output + DOR: u12, + padding: u20, }), - reserved96: [4]u8, - /// RCC AHB1 reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 block reset Set and reset by software. - GPDMA1RST: u1, - /// GPDMA2 block reset Set and reset by software. - GPDMA2RST: u1, - reserved12: u10, - /// CRC block reset Set and reset by software. - CRCRST: u1, - reserved17: u4, - /// RAMCFG block reset Set and reset by software. - RAMCFGRST: u1, - padding: u14, + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// channel DMA underrun flag + DMAUDR: u1, + /// channel calibration offset status + CAL_FLAG: u1, + /// channel busy writing sample time flag + BWST: u1, + padding: u16, }), - /// RCC AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// GPIOA block reset Set and reset by software. - GPIOARST: u1, - /// GPIOB block reset Set and reset by software. - GPIOBRST: u1, - /// GPIOC block reset Set and reset by software. - GPIOCRST: u1, - /// GPIOD block reset Set and reset by software. - GPIODRST: u1, - reserved7: u3, - /// GPIOH block reset Set and reset by software. - GPIOHRST: u1, - reserved10: u2, - /// ADC1 block reset Set and reset by software. - ADC1RST: u1, - /// DAC block reset Set and reset by software. - DAC1RST: u1, - reserved17: u5, - /// HASH block reset Set and reset by software. - HASHRST: u1, - /// RNG block reset Set and reset by software. - RNGRST: u1, - padding: u13, + /// calibration control register + CCR: mmio.Mmio(packed struct(u32) { + /// channel offset trimming value + OTRIM: u5, + padding: u27, }), - reserved116: [12]u8, - /// RCC APB1 peripheral low reset register - APB1LRSTR: mmio.Mmio(packed struct(u32) { - /// TIM2 block reset Set and reset by software. - TIM2RST: u1, - /// TIM3 block reset Set and reset by software. - TIM3RST: u1, - reserved4: u2, - /// TIM6 block reset Set and reset by software. - TIM6RST: u1, - /// TIM7 block reset Set and reset by software. - TIM7RST: u1, - reserved13: u7, - /// OPAMP block reset Set and reset by software. - OPAMPRST: u1, - /// SPI2 block reset Set and reset by software. - SPI2RST: u1, - /// SPI3 block reset Set and reset by software. - SPI3RST: u1, - /// COMP block reset Set and reset by software. - COMPRST: u1, - /// USART2 block reset Set and reset by software. - USART2RST: u1, - /// USART3 block reset Set and reset by software. - USART3RST: u1, - reserved21: u2, - /// I2C1 block reset Set and reset by software. - I2C1RST: u1, - /// I2C2 block reset Set and reset by software. - I2C2RST: u1, - /// I3C1 block reset Set and reset by software. - I3C1RST: u1, - /// CRS block reset Set and reset by software. - CRSRST: u1, - padding: u7, + /// mode control register + MCR: mmio.Mmio(packed struct(u32) { + /// DAC channel mode + MODE: packed union { + raw: u3, + value: MODE, + }, + padding: u29, }), - /// RCC APB1 peripheral high reset register - APB1HRSTR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// DTS block reset Set and reset by software. - DTSRST: u1, - reserved5: u1, - /// LPTIM2 block reset Set and reset by software. - LPTIM2RST: u1, - reserved9: u3, - /// FDCAN1 block reset Set and reset by software. - FDCAN12RST: u1, + /// sample and hold sample time register + SHSR: [2]mmio.Mmio(packed struct(u32) { + /// channel sample time + TSAMPLE: u10, padding: u22, }), - /// RCC APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 block reset Set and reset by software. - TIM1RST: u1, - /// SPI1 block reset Set and reset by software. - SPI1RST: u1, - reserved14: u1, - /// USART1 block reset Set and reset by software. - USART1RST: u1, - reserved24: u9, - /// USB block reset Set and reset by software. - USBRST: u1, - padding: u7, - }), - /// RCC APB3 peripheral reset register - APB3RSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SBS block reset Set and reset by software. - SYSCFGRST: u1, - reserved6: u4, - /// LPUART1 block reset Set and reset by software. - LPUART1RST: u1, - reserved9: u2, - /// I3C2RST block reset Set and reset by software. - I3C2RST: u1, - reserved11: u1, - /// LPTIM1 block reset Set and reset by software. - LPTIM1RST: u1, - reserved20: u8, - /// VREF block reset Set and reset by software. - VREFRST: u1, - padding: u11, + /// sample and hold hold time register + SHHR: mmio.Mmio(packed struct(u32) { + /// channel hold time + THOLD: u10, + padding: u22, }), - reserved136: [4]u8, - /// RCC AHB1 peripherals clock register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 clock enable Set and reset by software. - GPDMA1EN: u1, - /// GPDMA2 clock enable Set and reset by software. - GPDMA2EN: u1, - reserved8: u6, - /// Flash interface clock enable Set and reset by software. - FLITFEN: u1, - reserved12: u3, - /// CRC clock enable Set and reset by software. - CRCEN: u1, - reserved17: u4, - /// RAMCFG clock enable Set and reset by software. - RAMCFGEN: u1, - reserved28: u10, - /// BKPRAM clock enable Set and reset by software - BKPRAMEN: u1, - reserved31: u2, - /// SRAM1 clock enable Set and reset by software. - SRAM1EN: u1, + /// sample and hold refresh time register + SHRR: mmio.Mmio(packed struct(u32) { + /// channel refresh time + TREFRESH: u8, + padding: u24, }), - /// RCC AHB2 peripheral clock register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// GPIOA clock enable Set and reset by software. - GPIOAEN: u1, - /// GPIOB clock enable Set and reset by software. - GPIOBEN: u1, - /// GPIOC clock enable Set and reset by software. - GPIOCEN: u1, - /// GPIOD clock enable Set and reset by software. - GPIODEN: u1, - reserved7: u3, - /// GPIOH clock enable Set and reset by software. - GPIOHEN: u1, - reserved10: u2, - /// ADC1 peripherals clock enabled Set and reset by software. - ADC1EN: u1, - /// DAC clock enable Set and reset by software. - DAC1EN: u1, - reserved17: u5, - /// HASH clock enable Set and reset by software. - HASHEN: u1, - /// RNG clock enable Set and reset by software. - RNGEN: u1, - reserved30: u11, - /// SRAM2 clock enable Set and reset by software. - SRAM2EN: u1, - padding: u1, + }; + }; + + pub const dac_v6 = struct { + pub const MODE = enum(u3) { + /// Normal mode, external pin only, buffer enabled + NORMAL_EXT_BUFEN = 0x0, + /// Normal mode, external pin and internal peripherals, buffer enabled + NORMAL_EXT_INT_BUFEN = 0x1, + /// Normal mode, external pin only, buffer disabled + NORMAL_EXT_BUFDIS = 0x2, + /// Normal mode, internal peripherals only, buffer disabled + NORMAL_INT_BUFDIS = 0x3, + /// Sample and hold mode, external pin only, buffer enabled + SAMPHOLD_EXT_BUFEN = 0x4, + /// Sample and hold mode, external pin and internal peripherals, buffer enabled + SAMPHOLD_EXT_INT_BUFEN = 0x5, + /// Sample and hold mode, external pin and internal peripherals, buffer disabled + SAMPHOLD_EXT_INT_BUFDIS = 0x6, + /// Sample and hold mode, internal peripherals only, buffer disabled + SAMPHOLD_INT_BUFDIS = 0x7, + }; + + pub const WAVE = enum(u2) { + /// Wave generation disabled + Disabled = 0x0, + /// Noise wave generation enabled + Noise = 0x1, + /// Triangle wave generation enabled + Triangle = 0x2, + _, + }; + + /// Digital-to-analog converter + pub const DAC = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// channel enable + EN: u1, + /// channel trigger enable + TEN: u1, + /// channel trigger selection + TSEL: u4, + /// channel noise/triangle wave generation enable + WAVE: packed union { + raw: u2, + value: WAVE, + }, + /// channel mask/amplitude selector + MAMP: u4, + /// channel DMA enable + DMAEN: u1, + /// channel DMA Underrun Interrupt enable + DMAUDRIE: u1, + /// DAC channel calibration enable + CEN: u1, + padding: u17, }), - reserved156: [12]u8, - /// RCC APB1 peripheral clock register - APB1LENR: mmio.Mmio(packed struct(u32) { - /// TIM2 clock enable Set and reset by software. - TIM2EN: u1, - /// TIM3 clock enable Set and reset by software. - TIM3EN: u1, - reserved4: u2, - /// TIM6 clock enable Set and reset by software. - TIM6EN: u1, - /// TIM7 clock enable Set and reset by software. - TIM7EN: u1, - reserved11: u5, - /// WWDG clock enable Set and reset by software. - WWDGEN: u1, - reserved13: u1, - /// OPAMP clock enable Set and reset by software. - OPAMPEN: u1, - /// SPI2 clock enable Set and reset by software. - SPI2EN: u1, - /// SPI3 clock enable Set and reset by software. - SPI3EN: u1, - /// COMP clock enable Set and reset by software. - COMPEN: u1, - /// USART2 clock enable Set and reset by software. - USART2EN: u1, - /// USART3 clock enable Set and reset by software. - USART3EN: u1, - reserved21: u2, - /// I2C1 clock enable Set and reset by software. - I2C1EN: u1, - /// I2C2 clock enable Set and reset by software. - I2C2EN: u1, - /// I3C1 clock enable Set and reset by software. - I3C1EN: u1, - /// CRS clock enable Set and reset by software. - CRSEN: u1, - padding: u7, + /// software trigger register + SWTRIGR: mmio.Mmio(packed struct(u32) { + /// channel software trigger + SWTRIG: u1, + reserved16: u15, + /// channel software trigger B + SWTRIGB: u1, + padding: u15, }), - /// RCC APB1 peripheral clock register - APB1HENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// DTS clock enable Set and reset by software. - DTSEN: u1, - reserved5: u1, - /// LPTIM2 clock enable Set and reset by software. - LPTIM2EN: u1, - reserved9: u3, - /// FDCAN1 peripheral clock enable Set and reset by software. - FDCAN12EN: u1, - padding: u22, + /// channel 12-bit right-aligned data holding register + DHR12R: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + reserved16: u4, + /// channel 12-bit right-aligned data B + DHRB: u12, + padding: u4, }), - /// RCC APB2 peripheral clock register - APB2ENR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 clock enable Set and reset by software. - TIM1EN: u1, - /// SPI1 clock enable Set and reset by software. - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable Set and reset by software. - USART1EN: u1, - reserved24: u9, - /// USB clock enable Set and reset by software. - USBEN: u1, - padding: u7, + /// channel 12-bit left-aligned data holding register + DHR12L: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + reserved20: u4, + /// channel 12-bit left-aligned data B + DHRB: u12, }), - /// RCC APB3 peripheral clock register - APB3ENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SBS clock enable Set and reset by software. - SYSCFGEN: u1, - reserved6: u4, - /// LPUART1 clock enable Set and reset by software. - LPUART1EN: u1, - reserved9: u2, - /// I3C2EN clock enable Set and reset by software. - I3C2EN: u1, - reserved11: u1, - /// LPTIM1 clock enable Set and reset by software. - LPTIM1EN: u1, - reserved20: u8, - /// VREF clock enable Set and reset by software. - VREFEN: u1, - /// RTC APB interface clock enable Set and reset by software. - RTCAPBEN: u1, - padding: u10, + /// channel 8-bit right-aligned data holding register + DHR8R: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + /// channel 8-bit right-aligned data B + DHRB: u8, + padding: u16, }), - reserved176: [4]u8, - /// RCC AHB1 sleep clock register - AHB1LPENR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 clock enable during sleep mode Set and reset by software. - GPDMA1LPEN: u1, - /// GPDMA2 clock enable during sleep mode Set and reset by software. - GPDMA2LPEN: u1, - reserved8: u6, - /// Flash interface (FLITF) clock enable during sleep mode Set and reset by software. - FLITFLPEN: u1, - reserved12: u3, - /// CRC clock enable during sleep mode Set and reset by software. - CRCLPEN: u1, - reserved17: u4, - /// RAMCFG clock enable during sleep mode Set and reset by software. - RAMCFGLPEN: u1, - reserved28: u10, - /// BKPRAM clock enable during sleep mode Set and reset by software - BKPRAMLPEN: u1, - /// ICACHE clock enable during sleep mode Set and reset by software - ICACHELPEN: u1, - reserved31: u1, - /// SRAM1 clock enable during sleep mode Set and reset by software - SRAM1LPEN: u1, + reserved32: [12]u8, + /// dual 12-bit right-aligned data holding register + DHR12RD: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + padding: u20, }), - /// RCC AHB2 sleep clock register - AHB2LPENR: mmio.Mmio(packed struct(u32) { - /// GPIOA clock enable during sleep mode Set and reset by software. - GPIOALPEN: u1, - /// GPIOB clock enable during sleep mode Set and reset by software. - GPIOBLPEN: u1, - /// GPIOC clock enable during sleep mode Set and reset by software. - GPIOCLPEN: u1, - /// GPIOD clock enable during sleep mode Set and reset by software. - GPIODLPEN: u1, - reserved7: u3, - /// GPIOH clock enable during sleep mode Set and reset by software. - GPIOHLPEN: u1, - reserved10: u2, - /// ADC1 peripherals clock enable during sleep mode Set and reset by software. - ADC1LPEN: u1, - /// DAC clock enable during sleep mode Set and reset by software. - DAC1LPEN: u1, - reserved17: u5, - /// HASH clock enable during sleep mode Set and reset by software. - HASHLPEN: u1, - /// RNG clock enable during sleep mode Set and reset by software. - RNGLPEN: u1, - reserved30: u11, - /// SRAM2 clock enable during sleep mode Set and reset by software. - SRAM2LPEN: u1, - padding: u1, + /// dual 12-bit left aligned data holding register + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + padding: u16, }), - reserved196: [12]u8, - /// RCC APB1 sleep clock register - APB1LLPENR: mmio.Mmio(packed struct(u32) { - /// TIM2 clock enable during sleep mode Set and reset by software. - TIM2LPEN: u1, - /// TIM3 clock enable during sleep mode Set and reset by software. - TIM3LPEN: u1, - reserved4: u2, - /// TIM6 clock enable during sleep mode Set and reset by software. - TIM6LPEN: u1, - /// TIM7 clock enable during sleep mode Set and reset by software. - TIM7LPEN: u1, - reserved11: u5, - /// WWDG clock enable during sleep mode Set and reset by software. - WWDGLPEN: u1, - reserved13: u1, - /// OPAMP clock enable during sleep mode Set and reset by software. - OPAMPLPEN: u1, - /// SPI2 clock enable during sleep mode Set and reset by software. - SPI2LPEN: u1, - /// SPI3 clock enable during sleep mode Set and reset by software. - SPI3LPEN: u1, - /// COMP clock enable during sleep mode Set and reset by software. - COMPLPEN: u1, - /// USART2 clock enable during sleep mode Set and reset by software. - USART2LPEN: u1, - /// USART3 clock enable during sleep mode Set and reset by software. - USART3LPEN: u1, - reserved21: u2, - /// I2C1 clock enable during sleep mode Set and reset by software. - I2C1LPEN: u1, - /// I2C2 clock enable during sleep mode Set and reset by software. - I2C2LPEN: u1, - /// I3C1 clock enable during sleep mode Set and reset by software. - I3C1LPEN: u1, - /// CRS clock enable during sleep mode Set and reset by software. - CRSLPEN: u1, - padding: u7, + /// dual 8-bit right aligned data holding register + DHR8RD: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + padding: u24, }), - /// RCC APB1 sleep clock register - APB1HLPENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// DTS clock enable during sleep mode Set and reset by software. - DTSLPEN: u1, - reserved5: u1, - /// LPTIM2 clock enable during sleep mode Set and reset by software. - LPTIM2LPEN: u1, - reserved9: u3, - /// FDCAN1 peripheral clock enable during sleep mode Set and reset by software. - FDCAN12LPEN: u1, - padding: u22, + /// channel data output register + DOR: [2]mmio.Mmio(packed struct(u32) { + /// channel data output + DOR: u12, + reserved16: u4, + /// channel data output B + DORB: u12, + padding: u4, }), - /// RCC APB2 sleep clock register - APB2LPENR: mmio.Mmio(packed struct(u32) { + /// status register + SR: mmio.Mmio(packed struct(u32) { reserved11: u11, - /// TIM1 clock enable during sleep mode Set and reset by software. - TIM1LPEN: u1, - /// SPI1 clock enable during sleep mode Set and reset by software. - SPI1LPEN: u1, - reserved14: u1, - /// USART1 clock enable during sleep mode Set and reset by software. - USART1LPEN: u1, - reserved24: u9, - /// USB clock enable during sleep mode Set and reset by software. - USBLPEN: u1, - padding: u7, + /// channel ready status bit + DACRDY: u1, + /// channel output register status bit + DORSTAT: u1, + /// channel DMA underrun flag + DMAUDR: u1, + /// channel calibration offset status + CAL_FLAG: u1, + /// channel busy writing sample time flag + BWST: u1, + padding: u16, }), - /// RCC APB3 sleep clock register - APB3LPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SBS clock enable during sleep mode Set and reset by software. - SYSCFGLPEN: u1, - reserved6: u4, - /// LPUART1 clock enable during sleep mode Set and reset by software. - LPUART1LPEN: u1, - reserved9: u2, - /// I3C2 clock enable during sleep mode Set and reset by software. - I3C2LPEN: u1, - reserved11: u1, - /// LPTIM1 clock enable during sleep mode Set and reset by software. - LPTIM1LPEN: u1, - reserved20: u8, - /// VREF clock enable during sleep mode Set and reset by software. - VREFLPEN: u1, - /// RTC APB interface clock enable during sleep mode Set and reset by software. - RTCAPBLPEN: u1, - padding: u10, + /// calibration control register + CCR: mmio.Mmio(packed struct(u32) { + /// channel offset trimming value + OTRIM: u5, + padding: u27, }), - reserved216: [4]u8, - /// RCC kernel clock configuration register - CCIPR1: mmio.Mmio(packed struct(u32) { - /// USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - USART1SEL: packed union { - raw: u3, - value: USART1SEL, - }, - /// USART2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - USART2SEL: packed union { - raw: u3, - value: USARTSEL, - }, - /// USART3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - USART3SEL: packed union { + /// mode control register + MCR: mmio.Mmio(packed struct(u32) { + /// DAC channel mode + MODE: packed union { raw: u3, - value: USARTSEL, - }, - reserved31: u22, - /// TIM2, TIM3 and LPTIM2 input capture source selection Set and reset by software. - TIMICSEL: packed union { - raw: u1, - value: TIMICSEL, + value: MODE, }, + reserved8: u5, + /// channel DMA double data mode. + DMADOUBLE: u1, + /// enable signed format for DAC channel + SINFORMAT: u1, + reserved14: u4, + /// high frequency interface mode selection + HFSEL: u2, + padding: u16, }), - /// RCC kernel clock configuration register - CCIPR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// LPTIM1 kernel clock source selection others: reserved, the kernel clock is disabled - LPTIM1SEL: packed union { - raw: u3, - value: LPTIM1SEL, - }, - reserved12: u1, - /// LPTIM2 kernel clock source selection others: reserved, the kernel clock is disabled - LPTIM2SEL: packed union { - raw: u3, - value: LPTIM2SEL, - }, - padding: u17, + /// sample and hold sample time register + SHSR: [2]mmio.Mmio(packed struct(u32) { + /// channel sample time + TSAMPLE: u10, + padding: u22, }), - /// RCC kernel clock configuration register - CCIPR3: mmio.Mmio(packed struct(u32) { - /// SPI1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - SPI1SEL: packed union { - raw: u3, - value: SPISEL, - }, - /// SPI2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - SPI2SEL: packed union { - raw: u3, - value: SPISEL, - }, - /// SPI3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - SPI3SEL: packed union { - raw: u3, - value: SPISEL, - }, - reserved24: u15, - /// LPUART1 kernel clock source selection others: reserved, the kernel clock is disabled - LPUART1SEL: packed union { - raw: u3, - value: LPUARTSEL, - }, - padding: u5, + /// sample and hold hold time register + SHHR: mmio.Mmio(packed struct(u32) { + /// channel hold time + THOLD: u10, + padding: u22, }), - /// RCC kernel clock configuration register - CCIPR4: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// SYSTICK clock source selection Note: rcc_hclk frequency must be four times higher than lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK). - SYSTICKSEL: packed union { - raw: u2, - value: SYSTICKSEL, - }, - /// USB kernel clock source selection - USBSEL: packed union { - raw: u2, - value: USBSEL, - }, - reserved16: u10, - /// I2C1 kernel clock source selection - I2C1SEL: packed union { - raw: u2, - value: I2CSEL, - }, - /// I2C2 kernel clock source selection - I2C2SEL: packed union { - raw: u2, - value: I2CSEL, - }, - reserved24: u4, - /// I3C1 kernel clock source selection - I3C1SEL: packed union { - raw: u2, - value: I2CSEL, - }, - /// I3C2 kernel clock source selection - I3C2SEL: packed union { + /// sample and hold refresh time register + SHRR: mmio.Mmio(packed struct(u32) { + /// channel refresh time + TREFRESH: u8, + padding: u24, + }), + }; + }; + + pub const dac_v7 = struct { + pub const MODE = enum(u3) { + /// Normal mode, external pin only, buffer enabled + NORMAL_EXT_BUFEN = 0x0, + /// Normal mode, external pin and internal peripherals, buffer enabled + NORMAL_EXT_INT_BUFEN = 0x1, + /// Normal mode, external pin only, buffer disabled + NORMAL_EXT_BUFDIS = 0x2, + /// Normal mode, internal peripherals only, buffer disabled + NORMAL_INT_BUFDIS = 0x3, + /// Sample and hold mode, external pin only, buffer enabled + SAMPHOLD_EXT_BUFEN = 0x4, + /// Sample and hold mode, external pin and internal peripherals, buffer enabled + SAMPHOLD_EXT_INT_BUFEN = 0x5, + /// Sample and hold mode, external pin and internal peripherals, buffer disabled + SAMPHOLD_EXT_INT_BUFDIS = 0x6, + /// Sample and hold mode, internal peripherals only, buffer disabled + SAMPHOLD_INT_BUFDIS = 0x7, + }; + + pub const WAVE = enum(u2) { + /// Wave generation disabled + Disabled = 0x0, + /// Noise wave generation enabled + Noise = 0x1, + /// Triangle wave generation enabled + Triangle = 0x2, + /// Sawtooth wave generation enabled + Sawtooth = 0x3, + }; + + /// Digital-to-analog converter + pub const DAC = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// channel enable + EN: u1, + /// channel trigger enable + TEN: u1, + /// channel trigger selection + TSEL: u4, + /// channel noise/triangle wave generation enable + WAVE: packed union { raw: u2, - value: I3C2SEL, + value: WAVE, }, + /// channel mask/amplitude selector + MAMP: u4, + /// channel DMA enable + DMAEN: u1, + /// channel DMA Underrun Interrupt enable + DMAUDRIE: u1, + /// DAC channel calibration enable + CEN: u1, + padding: u17, + }), + /// software trigger register + SWTRIGR: mmio.Mmio(packed struct(u32) { + /// channel software trigger + SWTRIG: u1, + reserved16: u15, + /// channel software trigger B + SWTRIGB: u1, + padding: u15, + }), + /// channel 12-bit right-aligned data holding register + DHR12R: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + reserved16: u4, + /// channel 12-bit right-aligned data B + DHRB: u12, padding: u4, }), - /// RCC kernel clock configuration register - CCIPR5: mmio.Mmio(packed struct(u32) { - /// ADC and DAC kernel clock source selection others: reserved, the kernel clock is disabled - ADCDACSEL: packed union { + /// channel 12-bit left-aligned data holding register + DHR12L: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + reserved20: u4, + /// channel 12-bit left-aligned data B + DHRB: u12, + }), + /// channel 8-bit right-aligned data holding register + DHR8R: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + /// channel 8-bit right-aligned data B + DHRB: u8, + padding: u16, + }), + reserved32: [12]u8, + /// dual 12-bit right-aligned data holding register + DHR12RD: mmio.Mmio(packed struct(u32) { + /// channel 12-bit right-aligned data + DHR: u12, + padding: u20, + }), + /// dual 12-bit left aligned data holding register + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// channel 12-bit left-aligned data + DHR: u12, + padding: u16, + }), + /// dual 8-bit right aligned data holding register + DHR8RD: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data + DHR: u8, + padding: u24, + }), + /// channel data output register + DOR: [2]mmio.Mmio(packed struct(u32) { + /// channel data output + DOR: u12, + reserved16: u4, + /// channel data output B + DORB: u12, + padding: u4, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// channel ready status bit + DACRDY: u1, + /// channel output register status bit + DORSTAT: u1, + /// channel DMA underrun flag + DMAUDR: u1, + /// channel calibration offset status + CAL_FLAG: u1, + /// channel busy writing sample time flag + BWST: u1, + padding: u16, + }), + /// calibration control register + CCR: mmio.Mmio(packed struct(u32) { + /// channel offset trimming value + OTRIM: u5, + padding: u27, + }), + /// mode control register + MCR: mmio.Mmio(packed struct(u32) { + /// DAC channel mode + MODE: packed union { raw: u3, - value: ADCDACSEL, - }, - /// DAC hold clock - DACHOLDSEL: packed union { - raw: u1, - value: DACHOLDSEL, - }, - /// RNG kernel clock source selection - RNGSEL: packed union { - raw: u2, - value: RNGSEL, - }, - reserved8: u2, - /// FDCAN1 kernel clock source selection - FDCAN12SEL: packed union { - raw: u2, - value: FDCANSEL, - }, - reserved30: u20, - /// per_ck clock source selection - PERSEL: packed union { - raw: u2, - value: PERSEL, + value: MODE, }, + reserved8: u5, + /// channel DMA double data mode. + DMADOUBLE: u1, + /// enable signed format for DAC channel + SINFORMAT: u1, + reserved14: u4, + /// high frequency interface mode selection + HFSEL: u2, + padding: u16, }), - reserved240: [4]u8, - /// RCC Backup domain control register - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enabled Set and reset by software. - LSEON: u1, - /// LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0. - LSERDY: u1, - /// LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1) - LSEBYP: u1, - /// LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0). - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON. - LSECSSON: u1, - /// LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator. - LSECSSD: u1, - /// low-speed external clock type in bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled. - LSEEXT: packed union { - raw: u1, - value: LSEEXT, - }, - /// RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST). - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable Set and reset by software. - RTCEN: u1, - /// VSwitch domain software reset Set and reset by software. - VSWRST: u1, - reserved24: u7, - /// Low-speed clock output (LSCO) enable Set and cleared by software. - LSCOEN: u1, - /// Low-speed clock output selection Set and cleared by software. - LSCOSEL: packed union { - raw: u1, - value: LSCOSEL, - }, - /// LSI oscillator enable Set and cleared by software. - LSION: u1, - /// LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0. - LSIRDY: u1, - padding: u4, + /// sample and hold sample time register + SHSR: [2]mmio.Mmio(packed struct(u32) { + /// channel sample time + TSAMPLE: u10, + padding: u22, }), - /// RCC reset status register - RSR: mmio.Mmio(packed struct(u32) { - reserved23: u23, - /// remove reset flag Set and reset by software to reset the value of the reset flags. - RMVF: u1, - reserved26: u2, - /// pin reset flag (NRST) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. - PINRSTF: u1, - /// BOR reset flag Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). - BORRSTF: u1, - /// system reset from CPU reset flag Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33. - SFTRSTF: u1, - /// independent watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. - IWDGRSTF: u1, - /// window watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. - WWDGRSTF: u1, - /// Low-power reset flag Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared. Cleared by writing to the RMVF bit. - LPWRRSTF: u1, + /// sample and hold hold time register + SHHR: mmio.Mmio(packed struct(u32) { + /// channel hold time + THOLD: u10, + padding: u22, + }), + /// sample and hold refresh time register + SHRR: mmio.Mmio(packed struct(u32) { + /// channel refresh time + TREFRESH: u8, + padding: u24, + }), + reserved88: [8]u8, + /// Sawtooth register + STR: [2]mmio.Mmio(packed struct(u32) { + /// channel sawtooth reset value. + RSTDATA: u12, + /// channel sawtooth direction setting + DIR: u1, + reserved16: u3, + /// channel sawtooth increment value (12.4 bit format) + INCDATA: u16, + }), + /// Sawtooth Mode register + STMODR: mmio.Mmio(packed struct(u32) { + /// channel sawtooth reset trigger selection + STRSTTRIGSEL: u4, + reserved8: u4, + /// channel sawtooth increment trigger selection + STINCTRIGSEL: u4, + padding: u20, }), }; }; - pub const opamp_u0 = struct { - pub const CALON = enum(u1) { - /// Normal mode. - Normal = 0x0, - /// Calibration mode (all switches opened by HW). - Calibration = 0x1, - }; - - pub const CALSEL = enum(u1) { - /// NMOS calibration (200mV applied on OPAMP inputs). - NMOS = 0x0, - /// PMOS calibration (VDDA-200mV applied on OPAMP inputs). - PMOS = 0x1, - }; - - pub const OPALPM = enum(u1) { - /// operational amplifier in normal mode. - Normal = 0x0, - /// operational amplifier in low-power mode. - LowPower = 0x1, - }; - - pub const OPAMODE = enum(u2) { - /// internal PGA disable. - Disable = 0x0, - /// internal PGA disable. (Duplicate) - Disable2 = 0x1, - /// internal PGA enable, gain programmed in PGA_GAIN. - Enable = 0x2, - /// internal follower. - Follower = 0x3, - }; - - pub const OPA_RANGE = enum(u1) { - /// Low range (VDDA < 2.4V). - Low = 0x0, - /// High range (VDDA > 2.4V). - High = 0x1, - }; - - pub const PGA_GAIN = enum(u2) { - /// internal PGA Gain 2. - Gain2 = 0x0, - /// internal PGA Gain 4. - Gain4 = 0x1, - /// internal PGA Gain 8. - Gain8 = 0x2, - /// internal PGA Gain 16. - Gain16 = 0x3, - }; - - pub const USERTRIM = enum(u1) { - /// Factory trim code used. - Factory = 0x0, - /// User trim code used. - User = 0x1, - }; - - pub const VM_SEL = enum(u2) { - /// GPIO connected to VINM (valid also in PGA mode for filtering). - VINM = 0x0, - /// Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode) - NotConnected = 0x2, - _, - }; - - pub const VP_SEL = enum(u1) { - /// GPIO connected to VINP. - VINP = 0x0, - /// DAC connected to VINP. - DAC = 0x1, - }; - - /// OPAMP address block description. - pub const OPAMP = extern struct { - /// OPAMP control/status register. - CSR: mmio.Mmio(packed struct(u32) { - /// Operational amplifier Enable. - OPAMPEN: u1, - /// Operational amplifier Low Power Mode. The operational amplifier must be disable to change this configuration. - OPALPM: packed union { - raw: u1, - value: OPALPM, - }, - /// Operational amplifier PGA mode. - OPAMODE: packed union { - raw: u2, - value: OPAMODE, - }, - /// Operational amplifier Programmable amplifier gain value. - PGA_GAIN: packed union { - raw: u2, - value: PGA_GAIN, - }, - reserved8: u2, - /// Inverting input selection. These bits are used only when OPAMODE = 00, 01 or 10. 1x: Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode). - VM_SEL: packed union { - raw: u2, - value: VM_SEL, - }, - /// Non inverted input selection. - VP_SEL: packed union { - raw: u1, - value: VP_SEL, - }, - reserved12: u1, - /// Calibration mode enabled. - CALON: packed union { - raw: u1, - value: CALON, - }, - /// Calibration selection. - CALSEL: packed union { - raw: u1, - value: CALSEL, - }, - /// allows to switch from factory AOP offset trimmed values to AOP offset user trimmed values This bit is active for both mode normal and low-power. - USERTRIM: packed union { - raw: u1, - value: USERTRIM, - }, - /// Operational amplifier calibration output During calibration mode offset is trimmed when this signal toggle. - CALOUT: u1, - reserved31: u15, - /// Operational amplifier power supply range for stability All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP embedded in the product. - OPA_RANGE: packed union { - raw: u1, - value: OPA_RANGE, - }, + pub const dbgmcu_c0 = struct { + /// Debug support + pub const DBGMCU = extern struct { + /// MCU Device ID Code Register + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device Identifier + DEV_ID: u16, + /// Revision Identifier + REV_ID: u16, }), - /// OPAMP offset trimming register in normal mode. - OTR: mmio.Mmio(packed struct(u32) { - /// Trim for NMOS differential pairs. - TRIMOFFSETN: u5, - reserved8: u3, - /// Trim for PMOS differential pairs. - TRIMOFFSETP: u5, - padding: u19, + /// Debug MCU Configuration Register + CR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Debug Stop Mode + DBG_STOP: u1, + /// Debug Standby Mode + DBG_STANDBY: u1, + padding: u29, }), - /// OPAMP offset trimming register in low-power mode. - LPOTR: mmio.Mmio(packed struct(u32) { - /// Low-power mode trim for NMOS differential pairs. - TRIMLPOFFSETN: u5, - reserved8: u3, - /// Low-power mode trim for PMOS differential pairs. - TRIMLPOFFSETP: u5, - padding: u19, + /// DBG APB freeze register 1 + APB1FZR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// TIM3 counter stopped when core is halted + TIM3: u1, + reserved10: u8, + /// Debug RTC stopped when Core is halted + RTC: u1, + /// Debug Window Wachdog stopped when Core is halted + WWDG: u1, + /// Debug Independent Wachdog stopped when Core is halted + IWDG: u1, + reserved21: u8, + /// I2C1 SMBUS timeout mode stopped when core is halted + I2C1: u1, + padding: u10, + }), + /// DBG APB freeze register 2 + APB2FZR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 + TIM1: u1, + reserved15: u3, + /// TIM14 + TIM14: u1, + reserved17: u1, + /// TIM16 + TIM16: u1, + /// TIM17 + TIM17: u1, + padding: u13, }), }; }; - pub const exti_wle = struct { - /// External interrupt/event controller - pub const EXTI = extern struct { - /// Rising Trigger selection register - RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + pub const dbgmcu_f0 = struct { + /// Debug support + pub const DBGMCU = extern struct { + /// MCU Device ID Code Register + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device Identifier + DEV_ID: u12, + /// Division Identifier + DIV_ID: u4, + /// Revision Identifier + REV_ID: u16, }), - /// Falling Trigger selection register - FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// Debug MCU Configuration Register + CR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Debug Stop Mode + DBG_STOP: u1, + /// Debug Standby Mode + DBG_STANDBY: u1, + padding: u29, }), - /// Software interrupt event register - SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// Debug MCU APB1 freeze register + APB1_FZ: mmio.Mmio(packed struct(u32) { + /// TIM2 counter stopped when core is halted + TIM2: u1, + /// TIM3 counter stopped when core is halted + TIM3: u1, + reserved4: u2, + /// TIM6 counter stopped when core is halted + TIM6: u1, + /// TIM7 counter stopped when core is halted + TIM7: u1, + reserved8: u2, + /// TIM14 counter stopped when core is halted + TIM14: u1, + reserved10: u1, + /// Debug RTC stopped when core is halted + RTC: u1, + /// Debug window watchdog stopped when core is halted + WWDG: u1, + /// Debug independent watchdog stopped when core is halted + IWDG: u1, + reserved21: u8, + /// SMBUS timeout mode stopped when core is halted + DBG_I2C1_SMBUS_TIMEOUT: u1, + reserved25: u3, + /// CAN stopped when core is halted + CAN: u1, + padding: u6, }), - /// Pending register - PR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// Debug MCU APB2 freeze register + APB2_FZ: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 counter stopped when core is halted + TIM1: u1, + reserved16: u4, + /// TIM15 counter stopped when core is halted + TIM15: u1, + /// TIM16 counter stopped when core is halted + TIM16: u1, + /// TIM17 counter stopped when core is halted + TIM17: u1, + padding: u13, }), - reserved128: [112]u8, - /// Interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + }; + }; + + pub const dbgmcu_f1 = struct { + /// Debug support + pub const DBGMCU = extern struct { + /// DBGMCU_IDCODE + IDCODE: mmio.Mmio(packed struct(u32) { + /// DEV_ID + DEV_ID: u12, + reserved16: u4, + /// REV_ID + REV_ID: u16, }), - /// Event mask register - EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DBGMCU_CR + CR: mmio.Mmio(packed struct(u32) { + /// DBG_SLEEP + DBG_SLEEP: u1, + /// DBG_STOP + DBG_STOP: u1, + /// DBG_STANDBY + DBG_STANDBY: u1, + reserved5: u2, + /// TRACE_IOEN + TRACE_IOEN: u1, + /// TRACE_MODE + TRACE_MODE: u2, + /// IWDG + IWDG: u1, + /// WWDG + WWDG: u1, + /// TIM1 + TIM1: u1, + /// TIM2 + TIM2: u1, + /// TIM3 + TIM3: u1, + /// TIM4 + TIM4: u1, + /// CAN1 + CAN1: u1, + /// DBG_I2C1_SMBUS_TIMEOUT + DBG_I2C1_SMBUS_TIMEOUT: u1, + /// DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT: u1, + /// TIM8 + TIM8: u1, + /// TIM5 + TIM5: u1, + /// TIM6 + TIM6: u1, + /// TIM7 + TIM7: u1, + /// CAN2 + CAN2: u1, + /// TIM15 + TIM15: u1, + /// TIM16 + TIM16: u1, + /// TIM17 + TIM17: u1, + /// TIM12 + TIM12: u1, + /// TIM13 + TIM13: u1, + /// TIM14 + TIM14: u1, + padding: u4, }), }; }; - pub const dts_v1 = struct { - /// Digital temperature sensor. - pub const DTS = extern struct { - /// Temperature sensor configuration register 1. - CFGR1: mmio.Mmio(packed struct(u32) { - /// Temperature sensor 1 enable bit This bit is set and cleared by software. Note: Once enabled, the temperature sensor is active after a specific delay time. The TS1_RDY flag will be set when the sensor is ready. - EN: u1, - reserved4: u3, - /// Start frequency measurement on temperature sensor 1 This bit is set and cleared by software. - START: u1, - reserved8: u3, - /// Input trigger selection bit for temperature sensor 1 These bits are set and cleared by software. They select which input triggers a temperature measurement. Refer to Section 19.3.10: Trigger input. - INTRIG_SEL: u4, + pub const dbgmcu_f2 = struct { + /// Debug support + pub const DBGMCU = extern struct { + /// IDCODE + IDCODE: mmio.Mmio(packed struct(u32) { + /// DEV_ID + DEV_ID: u12, reserved16: u4, - /// Sampling time for temperature sensor 1 These bits allow increasing the sampling time to improve measurement precision. When the PCLK clock is selected as reference clock (REFCLK_SEL = 0), the measurement will be performed at TS1_SMP_TIME period of CLK_PTAT. When the LSE is selected as reference clock (REFCLK_SEL =1), the measurement will be performed at TS1_SMP_TIME period of LSE. - SMP_TIME: u4, - /// Reference clock selection bit This bit is set and cleared by software. It indicates whether the reference clock is the high speed clock (PCLK) or the low speed clock (LSE). - REFCLK_SEL: u1, - /// Quick measurement option bit This bit is set and cleared by software. It is used to increase the measurement speed by suppressing the calibration step. It is effective only when the LSE clock is used as reference clock (REFCLK_SEL=1). - Q_MEAS_OPT: u1, - reserved24: u2, - /// High speed clock division ratio These bits are set and cleared by software. They can be used to define the division ratio for the main clock in order to obtain the internal frequency lower than 1 MHz required for the calibration. They are applicable only for calibration when PCLK is selected as reference clock (REFCLK_SEL=0). ... - HSREF_CLK_DIV: u7, - padding: u1, - }), - reserved8: [4]u8, - /// Temperature sensor T0 value register 1. - T0VALR1: mmio.Mmio(packed struct(u32) { - /// Engineering value of the frequency measured at T0 for. temperature sensor 1 This value is expressed in 0.1 kHz. - FMT0: u16, - /// Engineering value of the T0 temperature for temperature sensor 1. Others: Reserved, must not be used. - T0: u2, - padding: u14, + /// REV_ID + REV_ID: u16, }), - reserved16: [4]u8, - /// Temperature sensor ramp value register. - RAMPVALR: mmio.Mmio(packed struct(u32) { - /// Engineering value of the ramp coefficient for the temperature sensor 1. This value is expressed in Hz/�C. - RAMP_COEFF: u16, - padding: u16, + /// Control Register + CR: mmio.Mmio(packed struct(u32) { + /// DBG_SLEEP + DBG_SLEEP: u1, + /// DBG_STOP + DBG_STOP: u1, + /// DBG_STANDBY + DBG_STANDBY: u1, + reserved5: u2, + /// TRACE_IOEN + TRACE_IOEN: u1, + /// TRACE_MODE + TRACE_MODE: u2, + padding: u24, }), - /// Temperature sensor interrupt threshold register 1. - ITR1: mmio.Mmio(packed struct(u32) { - /// Low interrupt threshold for temperature sensor 1 These bits are set and cleared by software. They indicate the lowest value than can be reached before raising an interrupt signal. - LITTHD: u16, - /// High interrupt threshold for temperature sensor 1 These bits are set and cleared by software. They indicate the highest value than can be reached before raising an interrupt signal. - HITTHD: u16, + /// Debug MCU APB1 Freeze registe + APB1_FZ: mmio.Mmio(packed struct(u32) { + /// TIM2 + TIM2: u1, + /// TIM3 + TIM3: u1, + /// TIM4 + TIM4: u1, + /// TIM5 + TIM5: u1, + /// TIM6 + TIM6: u1, + /// TIM7 + TIM7: u1, + /// TIM12 + TIM12: u1, + /// TIM13 + TIM13: u1, + /// TIM14 + TIM14: u1, + reserved10: u1, + /// RTC + RTC: u1, + /// WWDG + WWDG: u1, + /// IWDEG + IWDG: u1, + reserved21: u8, + /// I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT: u1, + /// I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT: u1, + /// I2C3_SMBUS_TIMEOUT + I2C3_SMBUS_TIMEOUT: u1, + reserved25: u1, + /// CAN1 + CAN1: u1, + /// CAN2 + CAN2: u1, + padding: u5, }), - reserved28: [4]u8, - /// Temperature sensor data register. - DR: mmio.Mmio(packed struct(u32) { - /// Value of the counter output value for temperature sensor 1. - MFREQ: u16, - padding: u16, + /// Debug MCU APB2 Freeze registe + APB2_FZ: mmio.Mmio(packed struct(u32) { + /// TIM1 counter stopped when core is halted + TIM1: u1, + /// TIM8 counter stopped when core is halted + TIM8: u1, + reserved16: u14, + /// TIM9 counter stopped when core is halted + TIM9: u1, + /// TIM10 counter stopped when core is halted + TIM10: u1, + /// TIM11 counter stopped when core is halted + TIM11: u1, + padding: u13, }), - /// Temperature sensor status register. - SR: mmio.Mmio(packed struct(u32) { - /// Interrupt flag for end of measurement on temperature sensor 1, synchronized on PCLK. This bit is set by hardware when a temperature measure is done. It is cleared by software by writing 1 to the TS2_CITEF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITEFEN bit is set. - ITEF: u1, - /// Interrupt flag for low threshold on temperature sensor 1, synchronized on PCLK. This bit is set by hardware when the low threshold is set and reached. It is cleared by software by writing 1 to the TS1_CITLF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITLFEN bit is set. - ITLF: u1, - /// Interrupt flag for high threshold on temperature sensor 1, synchronized on PCLK This bit is set by hardware when the high threshold is set and reached. It is cleared by software by writing 1 to the TS1_CITHF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITHFEN bit is set. - ITHF: u1, - reserved4: u1, - /// Asynchronous interrupt flag for end of measure on temperature sensor 1 This bit is set by hardware when a temperature measure is done. It is cleared by software by writing 1 to the TS1_CAITEF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITEFEN bit is set. - AITEF: u1, - /// Asynchronous interrupt flag for low threshold on temperature sensor 1 This bit is set by hardware when the low threshold is reached. It is cleared by software by writing 1 to the TS1_CAITLF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITLFEN bit is set. - AITLF: u1, - /// Asynchronous interrupt flag for high threshold on temperature sensor 1 This bit is set by hardware when the high threshold is reached. It is cleared by software by writing 1 to the TS1_CAITHF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITHFEN bit is set. - AITHF: u1, - reserved15: u8, - /// Temperature sensor 1 ready flag This bit is set and reset by hardware. It indicates that a measurement is ongoing. - RDY: u1, - padding: u16, + }; + }; + + pub const dbgmcu_f3 = struct { + /// Debug support + pub const DBGMCU = extern struct { + /// MCU Device ID Code Register + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device Identifier + DEV_ID: u12, + reserved16: u4, + /// Revision Identifier + REV_ID: u16, }), - /// Temperature sensor interrupt enable register. - ITENR: mmio.Mmio(packed struct(u32) { - /// Interrupt enable flag for end of measurement on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the synchronous interrupt for end of measurement. - ITEEN: u1, - /// Interrupt enable flag for low threshold on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the synchronous interrupt when the measure reaches or is below the low threshold. - ITLEN: u1, - /// Interrupt enable flag for high threshold on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the interrupt when the measure reaches or is above the high threshold. - ITHEN: u1, - reserved4: u1, - /// Asynchronous interrupt enable flag for end of measurement on temperature sensor 1 This bit are set and cleared by software. It enables the asynchronous interrupt for end of measurement (only when REFCLK_SEL = 1). - AITEEN: u1, - /// Asynchronous interrupt enable flag for low threshold on temperature sensor 1. This bit are set and cleared by software. It enables the asynchronous interrupt when the temperature is below the low threshold (only when REFCLK_SEL= 1). - AITLEN: u1, - /// Asynchronous interrupt enable flag on high threshold for temperature sensor 1. This bit are set and cleared by software. It enables the asynchronous interrupt when the temperature is above the high threshold (only when REFCLK_SEL= 1’’). - AITHEN: u1, - padding: u25, + /// Debug MCU Configuration Register + CR: mmio.Mmio(packed struct(u32) { + /// Debug Sleep mode + DBG_SLEEP: u1, + /// Debug Stop Mode + DBG_STOP: u1, + /// Debug Standby Mode + DBG_STANDBY: u1, + reserved5: u2, + /// Trace pin assignment control + TRACE_IOEN: u1, + /// Trace pin assignment control + TRACE_MODE: u2, + padding: u24, }), - /// Temperature sensor clear interrupt flag register. - ICIFR: mmio.Mmio(packed struct(u32) { - /// Interrupt clear flag for end of measurement on temperature sensor 1 Writing 1 to this bit clears the TS1_ITEF flag in the DTS_SR register. - CITEF: u1, - /// Interrupt clear flag for low threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_ITLF flag in the DTS_SR register. - CITLF: u1, - /// Interrupt clear flag for high threshold on temperature sensor 1 Writing this bit to 1 clears the TS1_ITHF flag in the DTS_SR register. - CITHF: u1, - reserved4: u1, - /// Write once bit. Clear the asynchronous IT flag for End Of Measure for thermal sensor 1. Writing 1 clears the TS1_AITEF flag of the DTS_SR register. - CAITEF: u1, - /// Asynchronous interrupt clear flag for low threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_AITLF flag in the DTS_SR register. - CAITLF: u1, - /// Asynchronous interrupt clear flag for high threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_AITHF flag in the DTS_SR register. - CAITHF: u1, - padding: u25, + /// APB Low Freeze Register + APB1FZR: mmio.Mmio(packed struct(u32) { + /// Debug Timer 2 stopped when Core is halted + TIM2: u1, + /// Debug Timer 3 stopped when Core is halted + TIM3: u1, + /// Debug Timer 4 stopped when Core is halted + TIM4: u1, + /// Debug Timer 5 stopped when Core is halted + TIM5: u1, + /// Debug Timer 6 stopped when Core is halted + TIM6: u1, + /// Debug Timer 7 stopped when Core is halted + TIM7: u1, + /// Debug Timer 12 stopped when Core is halted + TIM12: u1, + /// Debug Timer 13 stopped when Core is halted + TIM13: u1, + /// Debug Timer 14 stopped when Core is halted + TIM14: u1, + /// Debug Timer 18 stopped when Core is halted + TIM18: u1, + /// Debug RTC stopped when Core is halted + RTC: u1, + /// Debug Window Wachdog stopped when Core is halted + WWDG: u1, + /// Debug Independent Wachdog stopped when Core is halted + IWDG: u1, + reserved21: u8, + /// SMBUS timeout mode stopped when Core is halted + I2C1_SMBUS_TIMEOUT: u1, + /// SMBUS timeout mode stopped when Core is halted + I2C2_SMBUS_TIMEOUT: u1, + reserved25: u2, + /// Debug CAN stopped when core is halted + CAN: u1, + padding: u6, }), - /// Temperature sensor option register. - OR: mmio.Mmio(packed struct(u32) { - /// general purpose option bits. - OP: u1, - padding: u31, + /// APB High Freeze Register + APB2FZR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Debug Timer 15 stopped when Core is halted + TIM15: u1, + /// Debug Timer 16 stopped when Core is halted + TIM16: u1, + /// Debug Timer 17 stopped when Core is halted + TIM17: u1, + /// Debug Timer 19 stopped when Core is halted + TIM19: u1, + padding: u26, }), }; }; - pub const crc_v2 = struct { - pub const POLYSIZE = enum(u2) { - /// 32-bit polynomial - Polysize32 = 0x0, - /// 16-bit polynomial - Polysize16 = 0x1, - /// 8-bit polynomial - Polysize8 = 0x2, - /// 7-bit polynomial - Polysize7 = 0x3, - }; - - pub const REV_IN = enum(u2) { - /// Bit order not affected - Normal = 0x0, - /// Bit reversal done by byte - Byte = 0x1, - /// Bit reversal done by half-word - HalfWord = 0x2, - /// Bit reversal done by word - Word = 0x3, - }; - - pub const REV_OUT = enum(u1) { - /// Bit order not affected - Normal = 0x0, - /// Bit reversed output - Reversed = 0x1, - }; - - /// Cyclic Redundancy Check calculation unit - pub const CRC = extern struct { - /// Data register - half-word sized - DR16: u32, - /// Independent Data register - IDR: u32, - /// Control register + pub const dbgmcu_f4 = struct { + /// Debug support + pub const DBGMCU = extern struct { + /// IDCODE + IDCODE: mmio.Mmio(packed struct(u32) { + /// DEV_ID + DEV_ID: u12, + reserved16: u4, + /// REV_ID + REV_ID: u16, + }), + /// Control Register CR: mmio.Mmio(packed struct(u32) { - /// RESET bit - RESET: u1, - reserved3: u2, - /// Polynomial size - POLYSIZE: packed union { - raw: u2, - value: POLYSIZE, - }, - /// Reverse input data - REV_IN: packed union { - raw: u2, - value: REV_IN, - }, - /// Reverse output data - REV_OUT: packed union { - raw: u1, - value: REV_OUT, - }, + /// DBG_SLEEP + DBG_SLEEP: u1, + /// DBG_STOP + DBG_STOP: u1, + /// DBG_STANDBY + DBG_STANDBY: u1, + reserved5: u2, + /// TRACE_IOEN + TRACE_IOEN: u1, + /// TRACE_MODE + TRACE_MODE: u2, padding: u24, }), - reserved16: [4]u8, - /// Initial CRC value - INIT: u32, + /// Debug MCU APB1 Freeze registe + APB1FZR: mmio.Mmio(packed struct(u32) { + /// TIM2 + TIM2: u1, + /// TIM3 + TIM3: u1, + /// TIM4 + TIM4: u1, + /// TIM5 + TIM5: u1, + /// TIM6 + TIM6: u1, + /// TIM7 + TIM7: u1, + /// TIM12 + TIM12: u1, + /// TIM13 + TIM13: u1, + /// TIM14 + TIM14: u1, + reserved10: u1, + /// RTC stopped when Core is halted + RTC: u1, + /// WWDG + WWDG: u1, + /// IWDEG + IWDG: u1, + reserved21: u8, + /// I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT: u1, + /// I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT: u1, + /// I2C3SMBUS_TIMEOUT + I2C3_SMBUS_TIMEOUT: u1, + /// SMBUS timeout mode stopped when Core is halted + I2CFMP_SMBUS_TIMEOUT: u1, + /// CAN1 + CAN1: u1, + /// CAN2 + CAN2: u1, + padding: u5, + }), + /// Debug MCU APB2 Freeze registe + APB2FZR: mmio.Mmio(packed struct(u32) { + /// TIM1 counter stopped when core is halted + TIM1: u1, + /// TIM8 counter stopped when core is halted + TIM8: u1, + reserved16: u14, + /// TIM9 counter stopped when core is halted + TIM9: u1, + /// TIM10 counter stopped when core is halted + TIM10: u1, + /// TIM11 counter stopped when core is halted + TIM11: u1, + padding: u13, + }), }; }; - pub const adc_g0 = struct { - pub const DMACFG = enum(u1) { - /// DMA One Shot mode selected - OneShot = 0x0, - /// DMA Circular mode selected - Circular = 0x1, - }; - - pub const RES = enum(u2) { - /// 12-bit resolution - Bits12 = 0x0, - /// 10-bit resolution - Bits10 = 0x1, - /// 8-bit resolution - Bits8 = 0x2, - /// 6-bit resolution - Bits6 = 0x3, - }; - - pub const SAMPLE_TIME = enum(u3) { - /// 1.5 ADC cycles - Cycles1_5 = 0x0, - /// 3.5 ADC cycles - Cycles3_5 = 0x1, - /// 7.5 ADC cycles - Cycles7_5 = 0x2, - /// 12.5 ADC cycles - Cycles12_5 = 0x3, - /// 19.5 ADC cycles - Cycles19_5 = 0x4, - /// 39.5 ADC cycles - Cycles39_5 = 0x5, - /// 79.5 ADC cycles - Cycles79_5 = 0x6, - /// 160.5 ADC cycles - Cycles160_5 = 0x7, - }; - - /// Analog to Digital Converter - pub const ADC = extern struct { - /// ADC interrupt and status register - ISR: mmio.Mmio(packed struct(u32) { - /// ADC ready flag - ADRDY: u1, - /// ADC group regular end of sampling flag - EOSMP: u1, - /// ADC group regular end of unitary conversion flag - EOC: u1, - /// ADC group regular end of sequence conversions flag - EOS: u1, - /// ADC group regular overrun flag - OVR: u1, - reserved7: u2, - /// ADC analog watchdog 1 flag - AWD1: u1, - /// ADC analog watchdog 2 flag - AWD2: u1, - /// ADC analog watchdog 3 flag - AWD3: u1, - reserved11: u1, - /// End Of Calibration flag - EOCAL: u1, - reserved13: u1, - /// Channel Configuration Ready flag - CCRDY: u1, - padding: u18, - }), - /// ADC interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// ADC ready interrupt - ADRDYIE: u1, - /// ADC group regular end of sampling interrupt - EOSMPIE: u1, - /// ADC group regular end of unitary conversion interrupt - EOCIE: u1, - /// ADC group regular end of sequence conversions interrupt - EOSIE: u1, - /// ADC group regular overrun interrupt - OVRIE: u1, - reserved7: u2, - /// ADC analog watchdog 1 interrupt - AWD1IE: u1, - /// ADC analog watchdog 2 interrupt - AWD2IE: u1, - /// ADC analog watchdog 3 interrupt - AWD3IE: u1, - reserved11: u1, - /// End of calibration interrupt enable - EOCALIE: u1, - reserved13: u1, - /// Channel Configuration Ready Interrupt enable - CCRDYIE: u1, - padding: u18, + pub const dbgmcu_f7 = struct { + /// Debug support + pub const DBGMCU = extern struct { + /// IDCODE + IDCODE: mmio.Mmio(packed struct(u32) { + /// DEV_ID + DEV_ID: u12, + reserved16: u4, + /// REV_ID + REV_ID: u16, }), - /// ADC control register + /// Control Register CR: mmio.Mmio(packed struct(u32) { - /// ADC enable - ADEN: u1, - /// ADC disable - ADDIS: u1, - /// ADC group regular conversion start - ADSTART: u1, - reserved4: u1, - /// ADC group regular conversion stop - ADSTP: u1, - reserved28: u23, - /// ADC voltage regulator enable - ADVREGEN: u1, - reserved31: u2, - /// ADC calibration - ADCAL: u1, + /// DBG_SLEEP + DBG_SLEEP: u1, + /// DBG_STOP + DBG_STOP: u1, + /// DBG_STANDBY + DBG_STANDBY: u1, + reserved5: u2, + /// TRACE_IOEN + TRACE_IOEN: u1, + /// TRACE_MODE + TRACE_MODE: u2, + padding: u24, }), - /// ADC configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// ADC DMA transfer enable - DMAEN: u1, - /// Direct memory access configuration - DMACFG: packed union { - raw: u1, - value: DMACFG, - }, - /// Scan sequence direction - SCANDIR: u1, - /// ADC data resolution - RES: packed union { - raw: u2, - value: RES, - }, - /// ADC data alignement - ALIGN: u1, - /// ADC group regular external trigger source - EXTSEL: u3, - reserved10: u1, - /// ADC group regular external trigger polarity - EXTEN: u2, - /// ADC group regular overrun configuration - OVRMOD: u1, - /// Continuous conversion - CONT: u1, - /// Wait conversion mode - WAIT: u1, - /// Auto-off mode - AUTOFF: u1, - /// ADC group regular sequencer discontinuous mode - DISCEN: u1, - reserved21: u4, - /// Mode selection of the ADC_CHSELR register - CHSELRMOD: u1, - /// ADC analog watchdog 1 monitoring a single channel or all channels - AWD1SGL: u1, - /// ADC analog watchdog 1 enable on scope ADC group regular - AWD1EN: u1, - reserved26: u2, - /// ADC analog watchdog 1 monitored channel selection - AWDCH1CH: u5, - padding: u1, + /// Debug MCU APB1 Freeze register + APB1FZR: mmio.Mmio(packed struct(u32) { + /// TIM2 + TIM2: u1, + /// TIM3 + TIM3: u1, + /// TIM4 + TIM4: u1, + /// TIM5 + TIM5: u1, + /// TIM6 + TIM6: u1, + /// TIM7 + TIM7: u1, + /// TIM12 + TIM12: u1, + /// TIM13 + TIM13: u1, + /// TIM14 + TIM14: u1, + /// LPTIM1 + LPTIM1: u1, + /// RTC + RTC: u1, + /// WWDG + WWDG: u1, + /// IWDG + IWDG: u1, + /// CAN3 + CAN3: u1, + reserved21: u7, + /// DBG_I2C1_SMBUS_TIMEOUT + DBG_I2C1_SMBUS_TIMEOUT: u1, + /// DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT: u1, + /// DBG_I2C3_SMBUS_TIMEOUT + DBG_I2C3_SMBUS_TIMEOUT: u1, + /// DBG_I2C4SMBUS_TIMEOUT + DBG_I2C4_SMBUS_TIMEOUT: u1, + /// CAN1 + CAN1: u1, + /// CAN2 + CAN2: u1, + padding: u5, }), - /// ADC configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// ADC oversampler enable on scope ADC group regular - OVSE: u1, - reserved2: u1, - /// ADC oversampling ratio - OVSR: u3, - /// ADC oversampling shift - OVSS: u4, - /// ADC oversampling discontinuous mode (triggered mode) for ADC group regular - TOVS: u1, - reserved29: u19, - /// Low frequency trigger mode enable - LFTRIG: u1, - /// ADC clock mode - CKMODE: u2, + /// Debug MCU APB2 Freeze register + APB2FZR: mmio.Mmio(packed struct(u32) { + /// TIM1 counter stopped when core is halted + TIM1: u1, + /// TIM8 counter stopped when core is halted + TIM8: u1, + reserved16: u14, + /// TIM9 counter stopped when core is halted + TIM9: u1, + /// TIM10 counter stopped when core is halted + TIM10: u1, + /// TIM11 counter stopped when core is halted + TIM11: u1, + padding: u13, }), - /// ADC sampling time register - SMPR: mmio.Mmio(packed struct(u32) { - /// Sampling time selection - SMP1: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - reserved4: u1, - /// Sampling time selection - SMP2: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - reserved8: u1, - /// Channel sampling time selection - SMPSEL: u1, - padding: u23, + }; + }; + + pub const dbgmcu_g0 = struct { + /// Debug support + pub const DBGMCU = extern struct { + /// MCU Device ID Code Register + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device Identifier + DEV_ID: u16, + /// Revision Identifier + REV_ID: u16, }), - reserved32: [8]u8, - /// watchdog threshold register - AWD1TR: mmio.Mmio(packed struct(u32) { - /// ADC analog watchdog 1 threshold low - LT1: u12, - reserved16: u4, - /// ADC analog watchdog 1 threshold high - HT1: u12, - padding: u4, + /// Debug MCU Configuration Register + CR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Debug Stop Mode + DBG_STOP: u1, + /// Debug Standby Mode + DBG_STANDBY: u1, + padding: u29, }), - /// watchdog threshold register - AWD2TR: mmio.Mmio(packed struct(u32) { - /// ADC analog watchdog 2 threshold low - LT2: u12, - reserved16: u4, - /// ADC analog watchdog 2 threshold high - HT2: u12, - padding: u4, + /// DBG APB freeze register 1 + APB1FZR: mmio.Mmio(packed struct(u32) { + /// Debug Timer 2 stopped when Core is halted + TIM2: u1, + /// TIM3 counter stopped when core is halted + TIM3: u1, + reserved4: u2, + /// Debug Timer 6 stopped when Core is halted + TIM6: u1, + /// TIM7 counter stopped when core is halted + TIM7: u1, + reserved10: u4, + /// Debug RTC stopped when Core is halted + RTC: u1, + /// Debug Window Wachdog stopped when Core is halted + WWDG: u1, + /// Debug Independent Wachdog stopped when Core is halted + IWDG: u1, + reserved21: u8, + /// I2C1 SMBUS timeout mode stopped when core is halted + I2C1: u1, + reserved30: u8, + /// Clocking of LPTIMER2 counter when the core is halted + LPTIM2: u1, + /// Clocking of LPTIMER1 counter when the core is halted + LPTIM1: u1, }), - /// channel selection register - CHSELR: mmio.Mmio(packed struct(u32) { - /// Channel-x selection - CHSEL: u19, + /// DBG APB freeze register 2 + APB2FZR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 + TIM1: u1, + reserved15: u3, + /// TIM14 + TIM14: u1, + /// TIM15 + TIM15: u1, + /// TIM16 + TIM16: u1, + /// TIM17 + TIM17: u1, padding: u13, }), - /// watchdog threshold register - AWD3TR: mmio.Mmio(packed struct(u32) { - /// ADC analog watchdog 3 threshold high - LT3: u12, - reserved16: u4, - /// ADC analog watchdog 3 threshold high - HT3: u12, - padding: u4, + }; + }; + + pub const dbgmcu_g4 = struct { + /// Debug support + pub const DBGMCU = extern struct { + /// MCU Device ID Code Register + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device Identifier + DEV_ID: u16, + /// Revision Identifier + REV_ID: u16, }), - reserved64: [16]u8, - /// ADC group regular conversion data register - DR: mmio.Mmio(packed struct(u32) { - /// ADC group regular conversion data - regularDATA: u16, - padding: u16, + /// Debug MCU Configuration Register + CR: mmio.Mmio(packed struct(u32) { + /// Debug Sleep Mode + DBG_SLEEP: u1, + /// Debug Stop Mode + DBG_STOP: u1, + /// Debug Standby Mode + DBG_STANDBY: u1, + reserved5: u2, + /// Trace pin assignment control + TRACE_IOEN: u1, + /// Trace pin assignment control + TRACE_MODE: u2, + padding: u24, }), - reserved160: [92]u8, - /// ADC analog watchdog 2 configuration register - AWD2CR: mmio.Mmio(packed struct(u32) { - /// ADC analog watchdog 2 monitored channel selection - AWD2CH: u19, - padding: u13, + /// APB Low Freeze Register 1 + APB1LFZR: mmio.Mmio(packed struct(u32) { + /// Debug Timer 2 stopped when Core is halted + TIM2: u1, + /// TIM3 counter stopped when core is halted + TIM3: u1, + /// TIM4 counter stopped when core is halted + TIM4: u1, + /// TIM5 counter stopped when core is halted + TIM5: u1, + /// Debug Timer 6 stopped when Core is halted + TIM6: u1, + /// TIM7 counter stopped when core is halted + TIM7: u1, + reserved10: u4, + /// Debug RTC stopped when Core is halted + RTC: u1, + /// Debug Window Wachdog stopped when Core is halted + WWDG: u1, + /// Debug Independent Wachdog stopped when Core is halted + IWDG: u1, + reserved21: u8, + /// I2C1 SMBUS timeout mode stopped when core is halted + I2C1: u1, + /// I2C2 SMBUS timeout mode stopped when core is halted + I2C2: u1, + reserved30: u7, + /// I2C3 SMBUS timeout mode stopped when core is halted + I2C3: u1, + /// LPTIM1 counter stopped when core is halted + LPTIMER: u1, }), - /// ADC analog watchdog 3 configuration register - AWD3CR: mmio.Mmio(packed struct(u32) { - /// ADC analog watchdog 3 monitored channel selection - AWD3CH: u19, - padding: u13, + /// APB Low Freeze Register 2 + APB1HFZR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// I2C4 + I2C4: u1, + padding: u30, }), - reserved180: [12]u8, - /// ADC calibration factors register - CALFACT: mmio.Mmio(packed struct(u32) { - /// ADC calibration factor in single-ended mode - CALFACT: u7, - padding: u25, + /// APB High Freeze Register + APB2FZR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 counter stopped when core is halted + TIM1: u1, + reserved13: u1, + /// TIM8 counter stopped when core is halted + TIM8: u1, + reserved16: u2, + /// TIM15 counter stopped when core is halted + TIM15: u1, + /// TIM16 counter stopped when core is halted + TIM16: u1, + /// TIM17 counter stopped when core is halted + TIM17: u1, + reserved20: u1, + /// TIM20counter stopped when core is halted + TIM20: u1, + reserved26: u5, + /// HRTIM0 + HRTIM0: u1, + /// HRTIM0 + HRTIM1: u1, + /// HRTIM0 + HRTIM2: u1, + /// HRTIM0 + HRTIM3: u1, + padding: u2, }), - reserved776: [592]u8, - /// ADC common control register - CCR: mmio.Mmio(packed struct(u32) { - reserved18: u18, - /// ADC prescaler - PRESC: u4, - /// VREFINT enable - VREFEN: u1, - /// Temperature sensor enable - TSEN: u1, - /// VBAT enable - VBATEN: u1, - padding: u7, + }; + }; + + pub const dbgmcu_h5 = struct { + /// Microcontroller debug unit. + pub const DBGMCU = extern struct { + /// DBGMCU identity code register. + IDCODE: mmio.Mmio(packed struct(u32) { + /// device identification. + DEV_ID: u12, + reserved16: u4, + /// revision. + REV_ID: u16, }), - reserved984: [204]u8, - /// Hardware Configuration Register - HWCFGR6: mmio.Mmio(packed struct(u32) { - /// Input channel mapping - CHMAP20: u5, - reserved8: u3, - /// Input channel mapping - CHMAP21: u5, - reserved16: u3, - /// Input channel mapping - CHMAP22: u5, - reserved24: u3, - /// Input channel mapping - CHMAP23: u5, - padding: u3, + /// DBGMCU configuration register. + CR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Allows debug in Stop mode All clocks are disabled automatically in Stop mode. All active clocks and oscillators continue to run during Stop mode, allowing full debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state. + STOP: u1, + /// Allows debug in Standby mode All clocks are disabled and the core powered down automatically in Standby mode. All active clocks and oscillators continue to run during Standby mode, and the core supply is maintained, allowing full debug capability. On exit from Standby mode, a system reset is performed. + STANDBY: u1, + reserved4: u1, + /// trace pin enable. + TRACE_IOEN: u1, + /// trace port and clock enable. This bit enables the trace port clock, TRACECK. + TRACE_EN: u1, + /// trace pin assignment. + TRACE_MODE: u2, + reserved16: u8, + /// Debug credentials reset type This bit selects which type of reset is used to revoke the debug authentication credentials. + DCRT: u1, + padding: u15, }), - /// Hardware Configuration Register - HWCFGR5: mmio.Mmio(packed struct(u32) { - /// Input channel mapping - CHMAP19: u5, - reserved8: u3, - /// Input channel mapping - CHMAP18: u5, - reserved16: u3, - /// Input channel mapping - CHMAP17: u5, - reserved24: u3, - /// Input channel mapping - CHMAP16: u5, - padding: u3, + /// DBGMCU APB1L peripheral freeze register. + APB1LFZR: mmio.Mmio(packed struct(u32) { + /// TIM2 stop in debug. + TIM2_STOP: u1, + /// TIM3 stop in debug. + TIM3_STOP: u1, + /// TIM4 stop in debug. + TIM4_STOP: u1, + /// TIM5 stop in debug. + TIM5_STOP: u1, + /// TIM6 stop in debug. + TIM6_STOP: u1, + /// TIM7 stop in debug. + TIM7_STOP: u1, + /// TIM12 stop in debug. + TIM12_STOP: u1, + /// TIM13 stop in debug. + TIM13_STOP: u1, + /// TIM14 stop in debug. + TIM14_STOP: u1, + reserved11: u2, + /// WWDG stop in debug. + WWDG_STOP: u1, + /// IWDG stop in debug. + IWDG_STOP: u1, + reserved21: u8, + /// I2C1 SMBUS timeout stop in debug. + I2C1_STOP: u1, + /// I2C2 SMBUS timeout stop in debug. + I2C2_STOP: u1, + /// I3C1 SCL stall counter stop in debug. + I3C1_STOP: u1, + padding: u8, }), - /// Hardware Configuration Register - HWCFGR4: mmio.Mmio(packed struct(u32) { - /// Input channel mapping - CHMAP15: u5, - reserved8: u3, - /// Input channel mapping - CHMAP14: u5, - reserved16: u3, - /// Input channel mapping - CHMAP13: u5, - reserved24: u3, - /// Input channel mapping - CHMAP12: u5, - padding: u3, + /// DBGMCU APB1H peripheral freeze register. + APB1HFZR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// LPTIM2 stop in debug. + LPTIM2_STOP: u1, + padding: u26, }), - /// Hardware Configuration Register - HWCFGR3: mmio.Mmio(packed struct(u32) { - /// Input channel mapping - CHMAP11: u5, - reserved8: u3, - /// Input channel mapping - CHMAP10: u5, - reserved16: u3, - /// Input channel mapping - CHMAP9: u5, - reserved24: u3, - /// Input channel mapping - CHMAP8: u5, - padding: u3, + /// DBGMCU APB2 peripheral freeze register. + APB2FZR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 stop in debug. + TIM1_STOP: u1, + reserved13: u1, + /// TIM8 stop in debug. + TIM8_STOP: u1, + reserved16: u2, + /// TIM15 stop in debug. + TIM15_STOP: u1, + /// TIM16 stop in debug. + TIM16_STOP: u1, + /// TIM17 stop in debug. + TIM17_STOP: u1, + padding: u13, }), - /// Hardware Configuration Register - HWCFGR2: mmio.Mmio(packed struct(u32) { - /// Input channel mapping - CHMAP7: u5, - reserved8: u3, - /// Input channel mapping - CHMAP6: u5, - reserved16: u3, - /// Input channel mapping - CHMAP5: u5, - reserved24: u3, - /// Input channel mapping - CHMAP4: u5, - padding: u3, + /// DBGMCU APB3 peripheral freeze register. + APB3FZR: mmio.Mmio(packed struct(u32) { + reserved10: u10, + /// I2C3 SMBUS timeout stop in debug. + I2C3_STOP: u1, + /// I2C4 SMBUS timeout stop in debug. + I2C4_STOP: u1, + reserved17: u5, + /// LPTIM1 stop in debug. + LPTIM1_STOP: u1, + /// LPTIM3 stop in debug. + LPTIM3_STOP: u1, + /// LPTIM4 stop in debug. + LPTIM4_STOP: u1, + /// LPTIM5 stop in debug. + LPTIM5_STOP: u1, + /// LPTIM6 stop in debug. + LPTIM6_STOP: u1, + reserved30: u8, + /// RTC stop in debug. + RTC_STOP: u1, + padding: u1, }), - /// Hardware Configuration Register - HWCFGR1: mmio.Mmio(packed struct(u32) { - /// Input channel mapping - CHMAP3: u5, - reserved8: u3, - /// Input channel mapping - CHMAP2: u5, - reserved16: u3, - /// Input channel mapping - CHMAP1: u5, - reserved24: u3, - /// Input channel mapping - CHMAP0: u5, - padding: u3, + reserved32: [8]u8, + /// DBGMCU AHB1 peripheral freeze register. + AHB1FZR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 channel 0 stop in debug. + GPDMA1_STOP: u1, + reserved16: u15, + /// GPDMA2 channel 0 stop in debug. + GPDMA2_STOP: u1, + padding: u15, }), - /// Hardware Configuration Register - HWCFGR0: mmio.Mmio(packed struct(u32) { - /// NUM_CHAN_24 - NUM_CHAN_24: u4, - /// Extra analog watchdog - EXTRA_AWDS: u4, - /// Oversampling - OVS: u4, - padding: u20, + reserved252: [216]u8, + /// DBGMCU status register. + SR: mmio.Mmio(packed struct(u32) { + /// Bit n identifies whether access port AP n is present in device Bit n = 0: APn absent Bit n = 1: APn present. + AP_PRESENT: u16, + /// Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) Bit n = 0: APn locked Bit n = 1: APn enabled. + AP_ENABLED: u16, }), - /// EXTI IP Version register - VERR: mmio.Mmio(packed struct(u32) { - /// Minor Revision number - MINREV: u4, - /// Major Revision number - MAJREV: u4, + /// DBGMCU debug authentication mailbox host register. + AUTH_HOST: u32, + /// DBGMCU debug authentication mailbox device register. + AUTH_DEVICE: u32, + /// DBGMCU debug authentication mailbox acknowledge register. + AUTH_ACK: mmio.Mmio(packed struct(u32) { + /// Host to device acknowledge. The device sets this bit to indicate that it has placed a message in the DBGMCU_DBG_AUTH_DEVICE register. It should be reset by the host after reading the message. + HOST_ACK: u1, + /// Device to device acknowledge. The host sets this bit to indicate that it has placed a message in the DBGMCU_DBG_AUTH_HOST register. It is reset by the device after reading the message. + DEV_ACK: u1, + padding: u30, + }), + reserved4048: [3780]u8, + /// DBGMCU CoreSight peripheral identity register 4. + PIDR4: mmio.Mmio(packed struct(u32) { + /// JEP106 continuation code. + JEP106CON: u4, + /// register file size. + SIZE: u4, padding: u24, }), - /// EXTI Identification register - IPIDR: mmio.Mmio(packed struct(u32) { - /// IP Identification - IPID: u32, + reserved4064: [12]u8, + /// DBGMCU CoreSight peripheral identity register 0. + PIDR0: mmio.Mmio(packed struct(u32) { + /// part number bits [7:0]. + PARTNUM: u8, + padding: u24, }), - /// EXTI Size ID register - SIDR: mmio.Mmio(packed struct(u32) { - /// Size Identification - SID: u32, + /// DBGMCU CoreSight peripheral identity register 1. + PIDR1: mmio.Mmio(packed struct(u32) { + /// part number bits [11:8]. + PARTNUM: u4, + /// JEP106 identity code bits [3:0]. + JEP106ID: u4, + padding: u24, }), - }; - }; - - pub const adccommon_v4 = struct { - pub const CKMODE = enum(u2) { - /// Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock - Asynchronous = 0x0, - /// Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck - SyncDiv1 = 0x1, - /// Use AHB clock rcc_hclk3 divided by 2 - SyncDiv2 = 0x2, - /// Use AHB clock rcc_hclk3 divided by 4 - SyncDiv4 = 0x3, - }; - - pub const DAMDF = enum(u2) { - /// Without data packing, CDR/CDR2 not used - NoPack = 0x0, - /// CDR formatted for 32-bit down to 10-bit resolution - Format32to10 = 0x2, - /// CDR formatted for 8-bit resolution - Format8 = 0x3, - _, - }; - - pub const DUAL = enum(u5) { - /// Independent mode - Independent = 0x0, - /// Dual, combined regular simultaneous + injected simultaneous mode - DualRJ = 0x1, - /// Dual, combined regular simultaneous + alternate trigger mode - DualRA = 0x2, - /// Dual, combined interleaved mode + injected simultaneous mode - DualIJ = 0x3, - /// Dual, injected simultaneous mode only - DualJ = 0x5, - /// Dual, regular simultaneous mode only - DualR = 0x6, - /// Dual, interleaved mode only - DualI = 0x7, - /// Dual, alternate trigger mode only - DualA = 0x9, - _, - }; - - pub const PRESC = enum(u4) { - /// adc_ker_ck_input not divided - Div1 = 0x0, - /// adc_ker_ck_input divided by 2 - Div2 = 0x1, - /// adc_ker_ck_input divided by 4 - Div4 = 0x2, - /// adc_ker_ck_input divided by 6 - Div6 = 0x3, - /// adc_ker_ck_input divided by 8 - Div8 = 0x4, - /// adc_ker_ck_input divided by 10 - Div10 = 0x5, - /// adc_ker_ck_input divided by 12 - Div12 = 0x6, - /// adc_ker_ck_input divided by 16 - Div16 = 0x7, - /// adc_ker_ck_input divided by 32 - Div32 = 0x8, - /// adc_ker_ck_input divided by 64 - Div64 = 0x9, - /// adc_ker_ck_input divided by 128 - Div128 = 0xa, - /// adc_ker_ck_input divided by 256 - Div256 = 0xb, - _, - }; - - /// Analog-to-Digital Converter - pub const ADC_COMMON = extern struct { - /// ADC Common status register - CSR: mmio.Mmio(packed struct(u32) { - /// Master ADC ready - ADRDY_MST: u1, - /// End of Sampling phase flag of the master ADC - EOSMP_MST: u1, - /// End of regular conversion of the master ADC - EOC_MST: u1, - /// End of regular sequence flag of the master ADC - EOS_MST: u1, - /// Overrun flag of the master ADC - OVR_MST: u1, - /// End of injected conversion flag of the master ADC - JEOC_MST: u1, - /// End of injected sequence flag of the master ADC - JEOS_MST: u1, - /// Analog watchdog flag of the master ADC - AWD_MST: u1, - reserved10: u2, - /// Injected Context Queue Overflow flag of the master ADC - JQOVF_MST: u1, - reserved16: u5, - /// Slave ADC ready - ADRDY_SLV: u1, - /// End of Sampling phase flag of the slave ADC - EOSMP_SLV: u1, - /// End of regular conversion of the slave ADC - EOC_SLV: u1, - /// End of regular sequence flag of the slave ADC - EOS_SLV: u1, - /// Overrun flag of the slave ADC - OVR_SLV: u1, - /// End of injected conversion flag of the slave ADC - JEOC_SLV: u1, - /// End of injected sequence flag of the slave ADC - JEOS_SLV: u1, - /// Analog watchdog flag of the slave ADC - AWD_SLV: u1, - reserved26: u2, - /// Injected Context Queue Overflow flag of the slave ADC - JQOVF_SLV: u1, - padding: u5, + /// DBGMCU CoreSight peripheral identity register 2. + PIDR2: mmio.Mmio(packed struct(u32) { + /// JEP106 identity code bits [6:4]. + JEP106ID: u3, + /// JEDEC assigned value. + JEDEC: u1, + /// component revision number. + REVISION: u4, + padding: u24, }), - reserved8: [4]u8, - /// ADC common control register - CCR: mmio.Mmio(packed struct(u32) { - /// Dual ADC mode selection - DUAL: packed union { - raw: u5, - value: DUAL, - }, - reserved8: u3, - /// Delay between 2 sampling phases - DELAY: u4, - reserved14: u2, - /// Dual ADC Mode Data Format - DAMDF: packed union { - raw: u2, - value: DAMDF, - }, - /// ADC clock mode - CKMODE: packed union { - raw: u2, - value: CKMODE, - }, - /// ADC prescaler - PRESC: packed union { - raw: u4, - value: PRESC, - }, - /// VREFINT enable - VREFEN: u1, - /// Temperature sensor enable - VSENSEEN: u1, - /// VBAT enable - VBATEN: u1, - padding: u7, + /// DBGMCU CoreSight peripheral identity register 3. + PIDR3: mmio.Mmio(packed struct(u32) { + /// customer modified. + CMOD: u4, + /// metal fix version. + REVAND: u4, + padding: u24, }), - /// ADC common regular data register for dual and triple modes - CDR: mmio.Mmio(packed struct(u32) { - /// Regular data of the master ADC - RDATA_MST: u16, - /// Regular data of the slave ADC - RDATA_SLV: u16, + /// DBGMCU CoreSight component identity register 0. + CIDR0: mmio.Mmio(packed struct(u32) { + /// component identification bits [7:0]. + PREAMBLE: u8, + padding: u24, }), - /// ADC x common regular data register for 32-bit dual mode - CDR2: mmio.Mmio(packed struct(u32) { - /// Regular data of the master/slave alternated ADCs - RDATA_ALT: u32, + /// DBGMCU CoreSight component identity register 1. + CIDR1: mmio.Mmio(packed struct(u32) { + /// component identification bits [11:8]. + PREAMBLE: u4, + /// component identification bits [15:12] - component class. + CLASS: u4, + padding: u24, + }), + /// DBGMCU CoreSight component identity register 2. + CIDR2: mmio.Mmio(packed struct(u32) { + /// component identification bits [23:16]. + PREAMBLE: u8, + padding: u24, + }), + /// DBGMCU CoreSight component identity register 3. + CIDR3: mmio.Mmio(packed struct(u32) { + /// component identification bits [31:24]. + PREAMBLE: u8, + padding: u24, }), }; }; - pub const dsihost_u5 = struct { - /// DSI Host. - pub const DSIHOST = extern struct { - /// DSI Host version register. - VR: mmio.Mmio(packed struct(u32) { - /// Version of the DSI Host This read-only register contains the version of the DSI Host. - VERSION: u32, + pub const dbgmcu_h7 = struct { + /// Debug support + pub const DBGMCU = extern struct { + /// Identity code + IDC: mmio.Mmio(packed struct(u32) { + /// Device ID + DEV_ID: u12, + reserved16: u4, + /// Revision ID + REV_ID: u16, }), - /// DSI Host control register. + /// Configuration register CR: mmio.Mmio(packed struct(u32) { - /// Enable This bit configures the DSI Host in either power-up mode or to reset. - EN: u1, - padding: u31, - }), - /// DSI Host clock control register. - CCR: mmio.Mmio(packed struct(u32) { - /// TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation. - TXECKDIV: u8, - /// Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error. - TOCKDIV: u8, - padding: u16, - }), - /// DSI Host LTDC VCID register. - LVCIDR: mmio.Mmio(packed struct(u32) { - /// Virtual channel ID These bits configure the virtual channel ID for the LTDC interface traffic. - VCID: u2, - padding: u30, - }), - /// DSI Host LTDC color coding register. - LCOLCR: mmio.Mmio(packed struct(u32) { - /// Color coding This field configures the DPI color coding. Others: Reserved. - COLC: u4, - reserved8: u4, - /// Loosely packet enable This bit enables the loosely packed variant to 18-bit configuration. - LPE: u1, - padding: u23, + /// Allow debug in D1 Sleep mode + DBGSLEEP_D1: u1, + /// Allow debug in D1 Stop mode + DBGSTOP_D1: u1, + /// Allow debug in D1 Standby mode + DBGSTBY_D1: u1, + reserved20: u17, + /// Trace clock enable enable + TRACECLKEN: u1, + /// D1 debug clock enable enable + D1DBGCKEN: u1, + /// D3 debug clock enable enable + D3DBGCKEN: u1, + reserved28: u5, + /// External trigger output enable + TRGOEN: u1, + padding: u3, }), - /// DSI Host LTDC polarity configuration register. - LPCR: mmio.Mmio(packed struct(u32) { - /// Data enable polarity This bit configures the polarity of data enable pin. - DEP: u1, - /// VSYNC polarity This bit configures the polarity of VSYNC pin. - VSP: u1, - /// HSYNC polarity This bit configures the polarity of HSYNC pin. - HSP: u1, - padding: u29, + reserved52: [44]u8, + /// APB3 peripheral freeze register + APB3FZR1: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// WWDG1 stop in debug mode + WWDG1: u1, + padding: u25, }), - /// DSI Host low-power mode configuration register. - LPMCR: mmio.Mmio(packed struct(u32) { - /// VACT largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VACT regions. - VLPSIZE: u8, - reserved16: u8, - /// Largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions. - LPSIZE: u8, + reserved60: [4]u8, + /// APB1L peripheral freeze register + APB1LFZR1: mmio.Mmio(packed struct(u32) { + /// TIM2 stop in debug mode + TIM2: u1, + /// TIM3 stop in debug mode + TIM3: u1, + /// TIM4 stop in debug mode + TIM4: u1, + /// TIM5 stop in debug mode + TIM5: u1, + /// TIM6 stop in debug mode + TIM6: u1, + /// TIM7 stop in debug mode + TIM7: u1, + /// TIM12 stop in debug mode + TIM12: u1, + /// TIM13 stop in debug mode + TIM13: u1, + /// TIM14 stop in debug mode + TIM14: u1, + /// LPTIM1 stop in debug mode + LPTIM1: u1, + reserved21: u11, + /// I2C1 SMBUS timeout stop in debug mode + I2C1: u1, + /// I2C2 SMBUS timeout stop in debug mode + I2C2: u1, + /// I2C3 SMBUS timeout stop in debug mode + I2C3: u1, padding: u8, }), - reserved44: [16]u8, - /// DSI Host protocol configuration register. - PCR: mmio.Mmio(packed struct(u32) { - /// EoTp transmission enable This bit enables the EoTP transmission. - ETTXE: u1, - /// EoTp reception enable This bit enables the EoTp reception. - ETRXE: u1, - /// Bus-turn-around enable This bit enables the bus-turn-around (BTA) request. - BTAE: u1, - /// ECC reception enable This bit enables the ECC reception, error correction and reporting. - ECCRXE: u1, - /// CRC reception enable This bit enables the CRC reception and error reporting. - CRCRXE: u1, - /// EoTp transmission in low-power enable This bit enables the EoTP transmission in low-power. - ETTXLPE: u1, - padding: u26, - }), - /// DSI Host generic VCID register. - GVCIDR: mmio.Mmio(packed struct(u32) { - /// Virtual channel ID for reception This field indicates the generic interface read-back virtual channel identification. - VCIDRX: u2, + reserved76: [12]u8, + /// APB2 peripheral freeze register + APB2FZR1: mmio.Mmio(packed struct(u32) { + /// TIM1 stop in debug mode + TIM1: u1, + /// TIM8 stop in debug mode + TIM8: u1, reserved16: u14, - /// Virtual channel ID for transmission This field indicates the generic interface virtual channel identification where the generic packet is automatically generated and transmitted. - VCIDTX: u2, - padding: u14, + /// TIM15 stop in debug mode + TIM15: u1, + /// TIM16 stop in debug mode + TIM16: u1, + /// TIM17 stop in debug mode + TIM17: u1, + reserved29: u10, + /// HRTIM stop in debug mode + HRTIM: u1, + padding: u2, }), - /// DSI Host mode configuration register. - MCR: mmio.Mmio(packed struct(u32) { - /// Command mode This bit configures the DSI Host in either video or command mode. - CMDM: u1, - padding: u31, + reserved84: [4]u8, + /// APB4 peripheral freeze register + APB4FZR1: mmio.Mmio(packed struct(u32) { + reserved7: u7, + /// I2C4 SMBUS timeout stop in debug mode + I2C4: u1, + reserved9: u1, + /// LPTIM2 stop in debug mode + LPTIM2: u1, + /// LPTIM3 stop in debug mode + LPTIM3: u1, + /// LPTIM4 stop in debug mode + LPTIM4: u1, + /// LPTIM5 stop in debug mode + LPTIM5: u1, + reserved16: u3, + /// RTC stop in debug mode + RTC: u1, + reserved18: u1, + /// Independent watchdog for D1 stop in debug mode + IWDG1: u1, + padding: u13, }), - /// DSI Host video mode configuration register. - VMCR: mmio.Mmio(packed struct(u32) { - /// Video mode type This field configures the video mode transmission type : 1x: Burst mode. - VMT: u2, - reserved8: u6, - /// Low-power vertical sync active enable This bit enables to return to low-power inside the vertical sync time (VSA) period when timing allows. - LPVSAE: u1, - /// Low-power vertical back-porch enable This bit enables to return to low-power inside the vertical back-porch (VBP) period when timing allows. - LPVBPE: u1, - /// Low-power vertical front-porch enable This bit enables to return to low-power inside the vertical front-porch (VFP) period when timing allows. - LPVFPE: u1, - /// Low-power vertical active enable This bit enables to return to low-power inside the vertical active (VACT) period when timing allows. - LPVAE: u1, - /// Low-power horizontal back-porch enable This bit enables the return to low-power inside the horizontal back-porch (HBP) period when timing allows. - LPHBPE: u1, - /// Low-power horizontal front-porch enable This bit enables the return to low-power inside the horizontal front-porch (HFP) period when timing allows. - LPHFPE: u1, - /// Frame bus-turn-around acknowledge enable This bit enables the request for an acknowledge response at the end of a frame. - FBTAAE: u1, - /// Low-power command enable This bit enables the command transmission only in low-power mode. - LPCE: u1, - /// Pattern generator enable This bit enables the video mode pattern generator. - PGE: u1, - reserved20: u3, - /// Pattern generator mode This bit configures the pattern generator mode. - PGM: u1, - reserved24: u3, - /// Pattern generator orientation This bit configures the color bar orientation. - PGO: u1, - padding: u7, + }; + }; + + pub const dbgmcu_l0 = struct { + /// Debug support + pub const DBGMCU = extern struct { + /// MCU Device ID Code Register + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device Identifier + DEV_ID: u12, + reserved16: u4, + /// Revision Identifier + REV_ID: u16, }), - /// DSI Host video packet configuration register. - VPCR: mmio.Mmio(packed struct(u32) { - /// Video packet size This field configures the number of pixels in a single video packet. For 18-bit not loosely packed data types, this number must be a multiple of 4. For YCbCr data types, it must be a multiple of 2 as described in the DSI specification. - VPSIZE: u14, - padding: u18, + /// Debug MCU Configuration Register + CR: mmio.Mmio(packed struct(u32) { + /// Debug Sleep Mode + DBG_SLEEP: u1, + /// Debug Stop Mode + DBG_STOP: u1, + /// Debug Standby Mode + DBG_STANDBY: u1, + padding: u29, }), - /// DSI Host video chunks configuration register. - VCCR: mmio.Mmio(packed struct(u32) { - /// Number of chunks This register configures the number of chunks to be transmitted during a line period (a chunk consists of a video packet and a null packet). If set to 0 or 1, the video line is transmitted in a single packet. If set to 1, the packet is part of a chunk, so a null packet follows it if NPSIZE > 0. Otherwise, multiple chunks are used to transmit each video line. - NUMC: u13, - padding: u19, + /// APB Low Freeze Register + APB1FZR: mmio.Mmio(packed struct(u32) { + /// Debug Timer 2 stopped when Core is halted + TIM2: u1, + reserved4: u3, + /// Debug Timer 6 stopped when Core is halted + TIM6: u1, + reserved10: u5, + /// Debug RTC stopped when Core is halted + RTC: u1, + /// Debug Window Wachdog stopped when Core is halted + WWDG: u1, + /// Debug Independent Wachdog stopped when Core is halted + IWDG: u1, + reserved21: u8, + /// I2C1 SMBUS timeout mode stopped when core is halted + I2C1: u1, + /// I2C2 SMBUS timeout mode stopped when core is halted + I2C2: u1, + reserved31: u8, + /// LPTIM1 counter stopped when core is halted + LPTIM: u1, }), - /// DSI Host video null packet configuration register. - VNPCR: mmio.Mmio(packed struct(u32) { - /// Null packet size This field configures the number of bytes inside a null packet. Setting to 0 disables the null packets. - NPSIZE: u13, - padding: u19, + /// APB High Freeze Register + APB2FZR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Debug Timer 21 stopped when Core is halted + TIM21: u1, + reserved6: u3, + /// Debug Timer 22 stopped when Core is halted + TIM22: u1, + padding: u25, }), - /// DSI Host video HSA configuration register. - VHSACR: mmio.Mmio(packed struct(u32) { - /// Horizontal synchronism active duration This fields configures the horizontal synchronism active period in lane byte clock cycles. - HSA: u12, - padding: u20, + }; + }; + + pub const dbgmcu_l1 = struct { + /// debug support + pub const DBGMCU = extern struct { + /// DBGMCU_IDCODE + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device identifier + DEV_ID: u12, + reserved16: u4, + /// Revision identifie + REV_ID: u16, }), - /// DSI Host video HBP configuration register. - VHBPCR: mmio.Mmio(packed struct(u32) { - /// Horizontal back-porch duration This fields configures the horizontal back-porch period in lane byte clock cycles. - HBP: u12, - padding: u20, + /// Debug MCU configuration register + CR: mmio.Mmio(packed struct(u32) { + /// Debug Sleep mode + DBG_SLEEP: u1, + /// Debug Stop mode + DBG_STOP: u1, + /// Debug Standby mode + DBG_STANDBY: u1, + reserved5: u2, + /// Trace pin assignment control + TRACE_IOEN: u1, + /// Trace pin assignment control + TRACE_MODE: u2, + padding: u24, }), - /// DSI Host video line configuration register. - VLCR: mmio.Mmio(packed struct(u32) { - /// Horizontal line duration This fields configures the total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles. - HLINE: u15, - padding: u17, + /// Debug MCU APB1 freeze register1 + APB1_FZ: mmio.Mmio(packed struct(u32) { + /// TIM2 counter stopped when core is halted + DBG_TIM2_STOP: u1, + /// TIM3 counter stopped when core is halted + DBG_TIM3_STOP: u1, + /// TIM4 counter stopped when core is halted + DBG_TIM4_STOP: u1, + /// TIM5 counter stopped when core is halted + DBG_TIM5_STOP: u1, + /// TIM6 counter stopped when core is halted + DBG_TIM6_STOP: u1, + /// TIM7 counter stopped when core is halted + DBG_TIM7_STOP: u1, + reserved10: u4, + /// Debug RTC stopped when core is halted + DBG_RTC_STOP: u1, + /// Debug window watchdog stopped when core is halted + DBG_WWDG_STOP: u1, + /// Debug independent watchdog stopped when core is halted + DBG_IWDG_STOP: u1, + reserved21: u8, + /// SMBUS timeout mode stopped when core is halted + DBG_I2C1_SMBUS_TIMEOUT: u1, + /// SMBUS timeout mode stopped when core is halted + DBG_I2C2_SMBUS_TIMEOUT: u1, + padding: u9, }), - /// DSI Host video VSA configuration register. - VVSACR: mmio.Mmio(packed struct(u32) { - /// Vertical synchronism active duration This fields configures the vertical synchronism active period measured in number of horizontal lines. - VSA: u10, - padding: u22, + /// Debug MCU APB1 freeze register 2 + APB2_FZ: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// TIM counter stopped when core is halted + DBG_TIM9_STOP: u1, + /// TIM counter stopped when core is halted + DBG_TIM10_STOP: u1, + /// TIM counter stopped when core is halted + DBG_TIM11_STOP: u1, + padding: u27, }), - /// DSI Host video VBP configuration register. - VVBPCR: mmio.Mmio(packed struct(u32) { - /// Vertical back-porch duration This fields configures the vertical back-porch period measured in number of horizontal lines. - VBP: u10, - padding: u22, + }; + }; + + pub const dbgmcu_l4 = struct { + /// MCU debug component + pub const DBGMCU = extern struct { + /// DBGMCU_IDCODE + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device identifier + DEV_ID: u16, + /// Revision identifie + REV_ID: u16, }), - /// DSI Host video VFP configuration register. - VVFPCR: mmio.Mmio(packed struct(u32) { - /// Vertical front-porch duration This fields configures the vertical front-porch period measured in number of horizontal lines. - VFP: u10, - padding: u22, + /// Debug MCU configuration register + CR: mmio.Mmio(packed struct(u32) { + /// Debug Sleep mode + DBG_SLEEP: u1, + /// Debug Stop mode + DBG_STOP: u1, + /// Debug Standby mode + DBG_STANDBY: u1, + reserved5: u2, + /// Trace pin assignment control + TRACE_IOEN: u1, + /// Trace pin assignment control + TRACE_MODE: u2, + padding: u24, }), - /// DSI Host video VA configuration register. - VVACR: mmio.Mmio(packed struct(u32) { - /// Vertical active duration This fields configures the vertical active period measured in number of horizontal lines. - VA: u14, - padding: u18, + /// Debug MCU APB1 freeze register1 + APB1FZR1: mmio.Mmio(packed struct(u32) { + /// TIM2 counter stopped when core is halted + TIM2: u1, + /// TIM3 counter stopped when core is halted + TIM3: u1, + /// TIM4 counter stopped when core is halted + TIM4: u1, + /// TIM5 counter stopped when core is halted + TIM5: u1, + /// TIM6 counter stopped when core is halted + TIM6: u1, + /// TIM7 counter stopped when core is halted + TIM7: u1, + reserved10: u4, + /// RTC counter stopped when core is halted + RTC: u1, + /// Window watchdog counter stopped when core is halted + WWDG: u1, + /// Independent watchdog counter stopped when core is halted + IWDG: u1, + reserved21: u8, + /// I2C1 SMBUS timeout counter stopped when core is halted + I2C1: u1, + /// I2C2 SMBUS timeout counter stopped when core is halted + I2C2: u1, + /// I2C3 SMBUS timeout counter stopped when core is halted + I2C3: u1, + reserved25: u1, + /// bxCAN stopped when core is halted + CAN: u1, + reserved31: u5, + /// LPTIM1 counter stopped when core is halted + LPTIM1: u1, }), - /// DSI Host LTDC command configuration register. - LCCR: mmio.Mmio(packed struct(u32) { - /// Command size This field configures the maximum allowed size for an LTDC write memory command, measured in pixels. Automatic partitioning of data obtained from LTDC is permanently enabled. - CMDSIZE: u16, - padding: u16, + /// Debug MCU APB1 freeze register 2 + APB1FZR2: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// LPTIM2 counter stopped when core is halted + LPTIM2: u1, + padding: u26, }), - /// DSI Host command mode configuration register. - CMCR: mmio.Mmio(packed struct(u32) { - /// Tearing effect acknowledge request enable This bit enables the tearing effect acknowledge request:. - TEARE: u1, - /// Acknowledge request enable This bit enables the acknowledge request after each packet transmission:. - ARE: u1, - reserved8: u6, - /// Generic short write zero parameters transmission This bit configures the generic short write packet with zero parameters command transmission type:. - GSW0TX: u1, - /// Generic short write one parameters transmission This bit configures the generic short write packet with one parameters command transmission type:. - GSW1TX: u1, - /// Generic short write two parameters transmission This bit configures the generic short write packet with two parameters command transmission type:. - GSW2TX: u1, - /// Generic short read zero parameters transmission This bit configures the generic short read packet with zero parameters command transmission type:. - GSR0TX: u1, - /// Generic short read one parameters transmission This bit configures the generic short read packet with one parameters command transmission type:. - GSR1TX: u1, - /// Generic short read two parameters transmission This bit configures the generic short read packet with two parameters command transmission type:. - GSR2TX: u1, - /// Generic long write transmission This bit configures the generic long write packet command transmission type :. - GLWTX: u1, - reserved16: u1, - /// DCS short write zero parameter transmission This bit configures the DCS short write packet with zero parameter command transmission type:. - DSW0TX: u1, - /// DCS short read one parameter transmission This bit configures the DCS short read packet with one parameter command transmission type:. - DSW1TX: u1, - /// DCS short read zero parameter transmission This bit configures the DCS short read packet with zero parameter command transmission type:. - DSR0TX: u1, - /// DCS long write transmission This bit configures the DCS long write packet command transmission type:. - DLWTX: u1, - reserved24: u4, - /// Maximum read packet size This bit configures the maximum read packet size command transmission type:. - MRDPS: u1, - padding: u7, + /// Debug MCU APB2 freeze register + APB2FZR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 counter stopped when core is halted + TIM1: u1, + reserved13: u1, + /// TIM8 counter stopped when core is halted + TIM8: u1, + reserved16: u2, + /// TIM15 counter stopped when core is halted + TIM15: u1, + /// TIM16 counter stopped when core is halted + TIM16: u1, + /// TIM17 counter stopped when core is halted + TIM17: u1, + padding: u13, }), - /// DSI Host generic header configuration register. - GHCR: mmio.Mmio(packed struct(u32) { - /// Type This field configures the packet data type of the header packet. - DT: u6, - /// Channel This field configures the virtual channel ID of the header packet. - VCID: u2, - /// WordCount LSB This field configures the less significant byte of the header packet word count for long packets, or data 0 for short packets. - WCLSB: u8, - /// WordCount MSB This field configures the most significant byte of the header packet's word count for long packets, or data 1 for short packets. - WCMSB: u8, - padding: u8, + }; + }; + + pub const dbgmcu_l5 = struct { + /// MCU debug component + pub const DBGMCU = extern struct { + /// DBGMCU_IDCODE + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device identifier + DEV_ID: u12, + reserved16: u4, + /// Revision identifie + REV_ID: u16, }), - /// DSI Host generic payload data register. - GPDR: mmio.Mmio(packed struct(u32) { - /// Payload byte 1 This field indicates the byte 1 of the packet payload. - DATA1: u8, - /// Payload byte 2 This field indicates the byte 2 of the packet payload. - DATA2: u8, - /// Payload byte 3 This field indicates the byte 3 of the packet payload. - DATA3: u8, - /// Payload byte 4 This field indicates the byte 4 of the packet payload. - DATA4: u8, + /// Debug MCU configuration register + CR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Debug Stop mode + DBG_STOP: u1, + /// Debug Standby mode + DBG_STANDBY: u1, + reserved4: u1, + /// Trace pin assignment control + TRACE_IOEN: u1, + /// Trace port and clock enable + TRACE_EN: u1, + /// Trace pin assignment control + TRACE_MODE: u2, + padding: u24, }), - /// DSI Host generic packet status register. - GPSR: mmio.Mmio(packed struct(u32) { - /// Command FIFO empty This bit indicates the empty status of the generic command FIFO:. - CMDFE: u1, - /// Command FIFO full This bit indicates the full status of the generic command FIFO:. - CMDFF: u1, - /// Payload write FIFO empty This bit indicates the empty status of the generic write payload FIFO:. - PWRFE: u1, - /// Payload write FIFO full This bit indicates the full status of the generic write payload FIFO:. - PWRFF: u1, - /// Payload read FIFO empty This bit indicates the empty status of the generic read payload FIFO:. - PRDFE: u1, - /// Payload read FIFO full This bit indicates the full status of the generic read payload FIFO:. - PRDFF: u1, - /// Read command busy This bit is set when a read command is issued and cleared when the entire response is stored in the FIFO:. - RCB: u1, - reserved16: u9, - /// Command buffer empty This bit indicates the empty status of the generic payload internal buffer:. - CMDBE: u1, - /// Command buffer full This bit indicates the full status of the generic command internal buffer:. - CMDBF: u1, - /// Payload buffer empty This bit indicates the empty status of the generic payload internal buffer:. - PBE: u1, - /// Payload buffer full This bit indicates the full status of the generic payload internal buffer:. - PBF: u1, - padding: u12, + /// Debug MCU APB1 freeze register1 + APB1FZR1: mmio.Mmio(packed struct(u32) { + /// TIM2 counter stopped when core is halted + TIM2: u1, + /// TIM3 counter stopped when core is halted + TIM3: u1, + /// TIM4 counter stopped when core is halted + TIM4: u1, + /// TIM5 counter stopped when core is halted + TIM5: u1, + /// TIM6 counter stopped when core is halted + TIM6: u1, + /// TIM7 counter stopped when core is halted + TIM7: u1, + reserved10: u4, + /// RTC counter stopped when core is halted + RTC: u1, + /// Window watchdog counter stopped when core is halted + WWDG: u1, + /// Independent watchdog counter stopped when core is halted + IWDG: u1, + reserved21: u8, + /// I2C1 SMBUS timeout counter stopped when core is halted + I2C1: u1, + /// I2C2 SMBUS timeout counter stopped when core is halted + I2C2: u1, + /// I2C3 SMBUS timeout counter stopped when core is halted + I2C3: u1, + reserved31: u7, + /// LPTIM1 counter stopped when core is halted + LPTIM1: u1, }), - /// DSI Host timeout counter configuration register 0. - TCCR0: mmio.Mmio(packed struct(u32) { - /// Low-power reception timeout counter This field configures the timeout counter that triggers a low-power reception timeout contention detection (measured in TOCKDIV cycles). - LPRX_TOCNT: u16, - /// High-speed transmission timeout counter This field configures the timeout counter that triggers a high-speed transmission timeout contention detection (measured in TOCKDIV cycles). If using the non-burst mode and there is no enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link returns the low-power state once per frame, then configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV ≥ the time of one FRAME data transmission * (1 + 10%) In burst mode, RGB pixel packets are time-compressed, leaving more time during a scan line. Therefore, if in burst mode and there is enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link can return low-power mode and back in this time interval to save power. For this, configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV ≥ the time of one LINE data transmission * (1 + 10%). - HSTX_TOCNT: u16, + /// Debug MCU APB1 freeze register 2 + APB1FZR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// I2C4 counter stopped when core is halted + I2C4: u1, + reserved5: u3, + /// LPTIM2 counter stopped when core is halted + LPTIM2: u1, + /// LPTIM3 counter stopped when core is halted + LPTIM3: u1, + padding: u25, }), - /// DSI Host timeout counter configuration register 1. - TCCR1: mmio.Mmio(packed struct(u32) { - /// High-speed read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a high-speed read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. - HSRD_TOCNT: u16, - padding: u16, + /// Debug MCU APB2 freeze register + APB2FZR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 counter stopped when core is halted + TIM1: u1, + reserved13: u1, + /// TIM8 counter stopped when core is halted + TIM8: u1, + reserved16: u2, + /// TIM15 counter stopped when core is halted + TIM15: u1, + /// TIM16 counter stopped when core is halted + TIM16: u1, + /// TIM17 counter stopped when core is halted + TIM17: u1, + padding: u13, }), - /// DSI Host timeout counter configuration register 2. - TCCR2: mmio.Mmio(packed struct(u32) { - /// Low-power read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. - LPRD_TOCNT: u16, - padding: u16, + }; + }; + + pub const dbgmcu_u5 = struct { + /// MCU debug component + pub const DBGMCU = extern struct { + /// DBGMCU_IDCODE + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device dentification + DEV_ID: u12, + reserved16: u4, + /// Revision + REV_ID: u16, }), - /// DSI Host timeout counter configuration register 3. - TCCR3: mmio.Mmio(packed struct(u32) { - /// High-speed write timeout counter This field sets a period for which the DSI Host keeps the link inactive after sending a high-speed write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. - HSWR_TOCNT: u16, - reserved24: u8, - /// Presp mode When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met: dpivsync_edpiwms has risen and fallen. Packets originated from LTDC in command mode have been transmitted and its FIFO is empty again. In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready. - PM: u1, - padding: u7, + /// Debug MCU configuration register + CR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Debug Stop mode + DBG_STOP: u1, + /// Debug Standby mode + DBG_STANDBY: u1, + reserved4: u1, + /// Trace pin assignment control + TRACE_IOEN: u1, + /// trace port and clock enable + TRACE_EN: u1, + /// Trace pin assignment control + TRACE_MODE: u2, + padding: u24, }), - /// DSI Host timeout counter configuration register 4. - TCCR4: mmio.Mmio(packed struct(u32) { - /// Low-power write timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. - LPWR_TOCNT: u16, + /// Debug MCU APB1L peripheral freeze register + APB1LFZR: mmio.Mmio(packed struct(u32) { + /// TIM2 stop in debug + DBG_TIM2_STOP: u1, + /// TIM3 stop in debug + DBG_TIM3_STOP: u1, + /// TIM4 stop in debug + DBG_TIM4_STOP: u1, + /// TIM5 stop in debug + DBG_TIM5_STOP: u1, + /// TIM6 stop in debug + DBG_TIM6_STOP: u1, + /// TIM7 stop in debug + DBG_TIM7_STOP: u1, + reserved11: u5, + /// Window watchdog counter stop in debug + DBG_WWDG_STOP: u1, + /// Independent watchdog counter stop in debug + DBG_IWDG_STOP: u1, + reserved21: u8, + /// I2C1 SMBUS timeout stop in debug + DBG_I2C1_STOP: u1, + /// I2C2 SMBUS timeout stop in debug + DBG_I2C2_STOP: u1, + padding: u9, + }), + /// Debug MCU APB1H peripheral freeze register + APB1HFZR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// I2C4 stop in debug + DBG_I2C4_STOP: u1, + reserved5: u3, + /// LPTIM2 stop in debug + DBG_LPTIM2_STOP: u1, + padding: u26, + }), + /// Debug MCU APB2 peripheral freeze register + APB2FZR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 counter stopped when core is halted + DBG_TIM1_STOP: u1, + reserved13: u1, + /// TIM8 stop in debug + DBG_TIM8_STOP: u1, + reserved16: u2, + /// TIM15 counter stopped when core is halted + DBG_TIM15_STOP: u1, + /// TIM16 counter stopped when core is halted + DBG_TIM16_STOP: u1, + /// DBG_TIM17_STOP + DBG_TIM17_STOP: u1, + padding: u13, + }), + /// Debug MCU APB3 peripheral freeze register + APB3FZR: mmio.Mmio(packed struct(u32) { + reserved10: u10, + /// I2C3 stop in debug + DBG_I2C3_STOP: u1, + reserved17: u6, + /// LPTIM1 stop in debug + DBG_LPTIM1_STOP: u1, + /// LPTIM3 stop in debug + DBG_LPTIM3_STOP: u1, + /// LPTIM4 stop in debug + DBG_LPTIM4_STOP: u1, + reserved30: u10, + /// RTC stop in debug + DBG_RTC_STOP: u1, + padding: u1, + }), + reserved32: [8]u8, + /// Debug MCU AHB1 peripheral freeze register + AHB1FZR: mmio.Mmio(packed struct(u32) { + /// GPDMA channel 0 stop in debug + DBG_GPDMA0_STOP: u1, + /// GPDMA channel 1 stop in debug + DBG_GPDMA1_STOP: u1, + /// GPDMA channel 2 stop in debug + DBG_GPDMA2_STOP: u1, + /// GPDMA channel 3 stop in debug + DBG_GPDMA3_STOP: u1, + /// GPDMA channel 4 stop in debug + DBG_GPDMA4_STOP: u1, + /// GPDMA channel 5 stop in debug + DBG_GPDMA5_STOP: u1, + /// GPDMA channel 6 stop in debug + DBG_GPDMA6_STOP: u1, + /// GPDMA channel 7 stop in debug + DBG_GPDMA7_STOP: u1, + /// GPDMA channel 8 stop in debug + DBG_GPDMA8_STOP: u1, + /// GPDMA channel 9 stop in debug + DBG_GPDMA9_STOP: u1, + /// GPDMA channel 10 stop in debug + DBG_GPDMA10_STOP: u1, + /// GPDMA channel 11 stop in debug + DBG_GPDMA11_STOP: u1, + /// GPDMA channel 12 stop in debug + DBG_GPDMA12_STOP: u1, + /// GPDMA channel 13 stop in debug + DBG_GPDMA13_STOP: u1, + /// GPDMA channel 14 stop in debug + DBG_GPDMA14_STOP: u1, + /// GPDMA channel 15 stop in debug + DBG_GPDMA15_STOP: u1, padding: u16, }), - /// DSI Host timeout counter configuration register 5. - TCCR5: mmio.Mmio(packed struct(u32) { - /// Bus-turn-around timeout counter This field sets a period for which the DSI Host keeps the link still, after completing a bus-turn-around. This period is measured in cycles of lanebyteclk. The counting starts when the D‑PHY enters the Stop state and causes no interrupts. - BTA_TOCNT: u16, + reserved40: [4]u8, + /// Debug MCU AHB3 peripheral freeze register + AHB3FZR: mmio.Mmio(packed struct(u32) { + /// LPDMA channel 0 stop in debug + DBG_LPDMA0_STOP: u1, + /// LPDMA channel 1 stop in debug + DBG_LPDMA1_STOP: u1, + /// LPDMA channel 2 stop in debug + DBG_LPDMA2_STOP: u1, + /// LPDMA channel 3 stop in debug + DBG_LPDMA3_STOP: u1, + padding: u28, + }), + reserved252: [208]u8, + /// DBGMCU status register + DBGMCU_SR: mmio.Mmio(packed struct(u32) { + /// Bit n identifies whether access port AP n is present in device Bit n = 0: APn absent Bit n = 1: APn present + AP_PRESENT: u8, + /// DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) Bit n = 0: APn locked Bit n = 1: APn enabled + AP_LOCKED: u8, padding: u16, }), - reserved148: [4]u8, - /// DSI Host clock lane configuration register. - CLCR: mmio.Mmio(packed struct(u32) { - /// D-PHY clock control This bit controls the D-PHY clock state:. - DPCC: u1, - /// Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows. - ACR: u1, - padding: u30, + /// DBGMCU debug host authentication register + DBGMCU_DBG_AUTH_HOST: mmio.Mmio(packed struct(u32) { + /// Device authentication key The device specific 64-bit authentication key (OEM key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory. + AUTH_KEY: u32, }), - /// DSI Host clock lane timer configuration register. - CLTCR: mmio.Mmio(packed struct(u32) { - /// Low-power to high-speed time This field configures the maximum time that the D-PHY clock lane takes to go from low‑power to high-speed transmission measured in lane byte clock cycles. - LP2HS_TIME: u10, - reserved16: u6, - /// High-speed to low-power time This field configures the maximum time that the D-PHY clock lane takes to go from high‑speed to low-power transmission measured in lane byte clock cycles. - HS2LP_TIME: u10, - padding: u6, + /// DBGMCU debug device authentication register + DBGMCU_DBG_AUTH_DEVICE: mmio.Mmio(packed struct(u32) { + /// Device specific ID Device specific ID used for RDP regression. + AUTH_ID: u32, }), - /// DSI Host data lane timer configuration register. - DLTCR: mmio.Mmio(packed struct(u32) { - /// Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles. - LP2HS_TIME: u10, - reserved16: u6, - /// High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles. - HS2LP_TIME: u10, - padding: u6, + reserved4048: [3784]u8, + /// Debug MCU CoreSight peripheral identity register 4 + PIDR4: mmio.Mmio(packed struct(u32) { + /// JEP106 continuation code + JEP106CON: u4, + /// register file size + KCOUNT_4: u4, + padding: u24, }), - /// DSI Host PHY control register. - PCTLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Digital enable When set to 0, this bit places the digital section of the D-PHY in the reset state. - DEN: u1, - /// Clock enable This bit enables the D-PHY clock lane module:. - CKE: u1, - padding: u29, + reserved4064: [12]u8, + /// Debug MCU CoreSight peripheral identity register 0 + PIDR0: mmio.Mmio(packed struct(u32) { + /// part number bits [7:0] + PARTNUM: u8, + padding: u24, }), - /// DSI Host PHY configuration register. - PCONFR: mmio.Mmio(packed struct(u32) { - /// Number of lanes This field configures the number of active data lanes: Others: Reserved. - NL: u2, - reserved8: u6, - /// Stop wait time This field configures the minimum wait period to request a high-speed transmission after the Stop state. - SW_TIME: u8, - padding: u16, + /// Debug MCU CoreSight peripheral identity register 1 + PIDR1: mmio.Mmio(packed struct(u32) { + /// part number bits [11:8] + PARTNUM: u4, + /// JEP106 identity code bits [3:0] + JEP106ID: u4, + padding: u24, }), - /// DSI Host PHY ULPS control register. - PUCR: mmio.Mmio(packed struct(u32) { - /// ULPS request on clock lane ULPS mode request on clock lane. - URCL: u1, - /// ULPS exit on clock lane ULPS mode exit on clock lane. - UECL: u1, - /// ULPS request on data lane ULPS mode request on all active data lanes. - URDL: u1, - /// ULPS exit on data lane ULPS mode exit on all active data lanes. - UEDL: u1, - padding: u28, + /// Debug MCU CoreSight peripheral identity register 2 + PIDR2: mmio.Mmio(packed struct(u32) { + /// JEP106 identity code bits [6:4] + JEP106ID: u3, + /// JEDEC assigned value + JEDEC: u1, + /// component revision number + REVISION: u4, + padding: u24, }), - /// DSI Host PHY TX triggers configuration register. - PTTCR: mmio.Mmio(packed struct(u32) { - /// Transmission trigger Escape mode transmit trigger 0-3. Only one bit of TX_TRIG is asserted at any given time. - TX_TRIG: u4, - padding: u28, + /// Debug MCU CoreSight peripheral identity register 3 + PIDR3: mmio.Mmio(packed struct(u32) { + /// customer modified + CMOD: u4, + /// metal fix version + REVAND: u4, + padding: u24, }), - /// DSI Host PHY status register. - PSR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// PHY direction This bit indicates the status of phydirection D-PHY signal. - PD: u1, - /// PHY stop state clock lane This bit indicates the status of phystopstateclklane D-PHY signal. - PSSC: u1, - /// ULPS active not clock lane This bit indicates the status of ulpsactivenotclklane D-PHY signal. - UANC: u1, - /// PHY stop state lane 0 This bit indicates the status of phystopstate0lane D-PHY signal. - PSS0: u1, - /// ULPS active not lane 1 This bit indicates the status of ulpsactivenot0lane D-PHY signal. - UAN0: u1, - /// RX ULPS escape lane 0 This bit indicates the status of rxulpsesc0lane D-PHY signal. - RUE0: u1, - /// PHY stop state lane 1 This bit indicates the status of phystopstate1lane D-PHY signal. - PSS1: u1, - /// ULPS active not lane 1 This bit indicates the status of ulpsactivenot1lane D-PHY signal. - UAN1: u1, - padding: u23, + /// Debug MCU CoreSight component identity register 0 + CIDR0: mmio.Mmio(packed struct(u32) { + /// component identification bits [7:0] + PREAMBLE: u8, + padding: u24, }), - reserved188: [8]u8, - /// DSI Host interrupt and status register 0. - ISR0: mmio.Mmio(packed struct(u32) { - /// Acknowledge error 0 This bit retrieves the SoT error from the acknowledge error report. - AE0: u1, - /// Acknowledge error 1 This bit retrieves the SoT sync error from the acknowledge error report. - AE1: u1, - /// Acknowledge error 2 This bit retrieves the EoT sync error from the acknowledge error report. - AE2: u1, - /// Acknowledge error 3 This bit retrieves the escape mode entry command error from the acknowledge error report. - AE3: u1, - /// Acknowledge error 4 This bit retrieves the LP transmit sync error from the acknowledge error report. - AE4: u1, - /// Acknowledge error 5 This bit retrieves the peripheral timeout error from the acknowledge error report. - AE5: u1, - /// Acknowledge error 6 This bit retrieves the false control error from the acknowledge error report. - AE6: u1, - /// Acknowledge error 7 This bit retrieves the reserved (specific to the device) from the acknowledge error report. - AE7: u1, - /// Acknowledge error 8 This bit retrieves the ECC error, single-bit (detected and corrected) from the acknowledge error report. - AE8: u1, - /// Acknowledge error 9 This bit retrieves the ECC error, multi-bit (detected, not corrected) from the acknowledge error report. - AE9: u1, - /// Acknowledge error 10 This bit retrieves the checksum error (long packet only) from the acknowledge error report. - AE10: u1, - /// Acknowledge error 11 This bit retrieves the not recognized DSI data type from the acknowledge error report. - AE11: u1, - /// Acknowledge error 12 This bit retrieves the DSI VC ID Invalid from the acknowledge error report. - AE12: u1, - /// Acknowledge error 13 This bit retrieves the invalid transmission length from the acknowledge error report. - AE13: u1, - /// Acknowledge error 14 This bit retrieves the reserved (specific to the device) from the acknowledge error report. - AE14: u1, - /// Acknowledge error 15 This bit retrieves the DSI protocol violation from the acknowledge error report. - AE15: u1, - /// PHY error 0 This bit indicates the ErrEsc escape entry error from lane 0. - PE0: u1, - /// PHY error 1 This bit indicates the ErrSyncEsc low-power transmission synchronization error from lane 0. - PE1: u1, - /// PHY error 2 This bit indicates the ErrControl error from lane 0. - PE2: u1, - /// PHY error 3 This bit indicates the LP0 contention error ErrContentionLP0 from lane 0. - PE3: u1, - /// PHY error 4 This bit indicates the LP1 contention error ErrContentionLP1 from lane 0. - PE4: u1, - padding: u11, + /// Debug MCU CoreSight component identity register 1 + CIDR1: mmio.Mmio(packed struct(u32) { + /// component identification bits [11:8] + PREAMBLE: u4, + /// component identification bits [15:12] - component class + CLASS: u4, + padding: u24, }), - /// DSI Host interrupt and status register 1. - ISR1: mmio.Mmio(packed struct(u32) { - /// Timeout high-speed transmission This bit indicates that the high-speed transmission timeout counter reached the end and contention is detected. - TOHSTX: u1, - /// Timeout low-power reception This bit indicates that the low-power reception timeout counter reached the end and contention is detected. - TOLPRX: u1, - /// ECC single-bit error This bit indicates that the ECC single error is detected and corrected in a received packet. - ECCSE: u1, - /// ECC multi-bit error This bit indicates that the ECC multiple error is detected in a received packet. - ECCME: u1, - /// CRC error This bit indicates that the CRC error is detected in the received packet payload. - CRCE: u1, - /// Packet size error This bit indicates that the packet size error is detected during the packet reception. - PSE: u1, - /// EoTp error This bit indicates that the EoTp packet is not received at the end of the incoming peripheral transmission. - EOTPE: u1, - /// LTDC payload write error This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted. - LPWRE: u1, - /// Generic command write error This bit indicates that the system tried to write a command through the generic interface and the FIFO is full. Therefore, the command is not written. - GCWRE: u1, - /// Generic payload write error This bit indicates that the system tried to write a payload data through the generic interface and the FIFO is full. Therefore, the payload is not written. - GPWRE: u1, - /// Generic payload transmit error This bit indicates that during a generic interface packet build, the payload FIFO becomes empty and corrupt data is sent. - GPTXE: u1, - /// Generic payload read error This bit indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted. - GPRDE: u1, - /// Generic payload receive error This bit indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted. - GPRXE: u1, - reserved19: u6, - /// Payload buffer underflow error This bit indicates that underflow has occurred when reading payload to build DSI packet for video mode. - PBUE: u1, - padding: u12, + /// Debug MCU CoreSight component identity register 2 + CIDR2: mmio.Mmio(packed struct(u32) { + /// component identification bits [23:16] + PREAMBLE: u8, + padding: u24, }), - /// DSI Host interrupt enable register 0. - IER0: mmio.Mmio(packed struct(u32) { - /// Acknowledge error 0 interrupt enable This bit enables the interrupt generation on acknowledge error 0. - AE0IE: u1, - /// Acknowledge error 1 interrupt enable This bit enables the interrupt generation on acknowledge error 1. - AE1IE: u1, - /// Acknowledge error 2 interrupt enable This bit enables the interrupt generation on acknowledge error 2. - AE2IE: u1, - /// Acknowledge error 3 interrupt enable This bit enables the interrupt generation on acknowledge error 3. - AE3IE: u1, - /// Acknowledge error 4 interrupt enable This bit enables the interrupt generation on acknowledge error 4. - AE4IE: u1, - /// Acknowledge error 5 interrupt enable This bit enables the interrupt generation on acknowledge error 5. - AE5IE: u1, - /// Acknowledge error 6 interrupt enable This bit enables the interrupt generation on acknowledge error 6. - AE6IE: u1, - /// Acknowledge error 7 interrupt enable This bit enables the interrupt generation on acknowledge error 7. - AE7IE: u1, - /// Acknowledge error 8 interrupt enable This bit enables the interrupt generation on acknowledge error 8. - AE8IE: u1, - /// Acknowledge error 9 interrupt enable This bit enables the interrupt generation on acknowledge error 9. - AE9IE: u1, - /// Acknowledge error 10 interrupt enable This bit enables the interrupt generation on acknowledge error 10. - AE10IE: u1, - /// Acknowledge error 11 interrupt enable This bit enables the interrupt generation on acknowledge error 11. - AE11IE: u1, - /// Acknowledge error 12 interrupt enable This bit enables the interrupt generation on acknowledge error 12. - AE12IE: u1, - /// Acknowledge error 13 interrupt enable This bit enables the interrupt generation on acknowledge error 13. - AE13IE: u1, - /// Acknowledge error 14 interrupt enable This bit enables the interrupt generation on acknowledge error 14. - AE14IE: u1, - /// Acknowledge error 15 interrupt enable This bit enables the interrupt generation on acknowledge error 15. - AE15IE: u1, - /// PHY error 0 interrupt enable This bit enables the interrupt generation on PHY error 0. - PE0IE: u1, - /// PHY error 1 interrupt enable This bit enables the interrupt generation on PHY error 1. - PE1IE: u1, - /// PHY error 2 interrupt enable This bit enables the interrupt generation on PHY error 2. - PE2IE: u1, - /// PHY error 3 interrupt enable This bit enables the interrupt generation on PHY error 4. - PE3IE: u1, - /// PHY error 4 interrupt enable This bit enables the interrupt generation on PHY error 4. - PE4IE: u1, - padding: u11, + /// Debug MCU CoreSight component identity register 3 + CIDR3: mmio.Mmio(packed struct(u32) { + /// component identification bits [31:24] + PREAMBLE: u8, + padding: u24, }), - /// DSI Host interrupt enable register 1. - IER1: mmio.Mmio(packed struct(u32) { - /// Timeout high-speed transmission interrupt enable This bit enables the interrupt generation on timeout high-speed transmission. - TOHSTXIE: u1, - /// Timeout low-power reception interrupt enable This bit enables the interrupt generation on timeout low-power reception. - TOLPRXIE: u1, - /// ECC single-bit error interrupt enable This bit enables the interrupt generation on ECC single-bit error. - ECCSEIE: u1, - /// ECC multi-bit error interrupt enable This bit enables the interrupt generation on ECC multi-bit error. - ECCMEIE: u1, - /// CRC error interrupt enable This bit enables the interrupt generation on CRC error. - CRCEIE: u1, - /// Packet size error interrupt enable This bit enables the interrupt generation on packet size error. - PSEIE: u1, - /// EoTp error interrupt enable This bit enables the interrupt generation on EoTp error. - EOTPEIE: u1, - /// LTDC payload write error interrupt enable This bit enables the interrupt generation on LTDC payload write error. - LPWREIE: u1, - /// Generic command write error interrupt enable This bit enables the interrupt generation on generic command write error. - GCWREIE: u1, - /// Generic payload write error interrupt enable This bit enables the interrupt generation on generic payload write error. - GPWREIE: u1, - /// Generic payload transmit error interrupt enable This bit enables the interrupt generation on generic payload transmit error. - GPTXEIE: u1, - /// Generic payload read error interrupt enable This bit enables the interrupt generation on generic payload read error. - GPRDEIE: u1, - /// Generic payload receive error interrupt enable This bit enables the interrupt generation on generic payload receive error. - GPRXEIE: u1, - reserved19: u6, - /// Payload buffer underflow error interrupt enable This bit enables the interrupt generation on payload buffer underflow error. - PBUEIE: u1, - padding: u12, + }; + }; + + pub const dbgmcu_wb = struct { + /// Debug support + pub const DBGMCU = extern struct { + /// MCU Device ID Code Register + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device Identifier + DEV_ID: u12, + reserved16: u4, + /// Revision Identifier + REV_ID: u16, }), - reserved216: [12]u8, - /// DSI Host force interrupt register 0. - FIR0: mmio.Mmio(packed struct(u32) { - /// Force acknowledge error 0 Writing one to this bit forces an acknowledge error 0. - FAE0: u1, - /// Force acknowledge error 1 Writing one to this bit forces an acknowledge error 1. - FAE1: u1, - /// Force acknowledge error 2 Writing one to this bit forces an acknowledge error 2. - FAE2: u1, - /// Force acknowledge error 3 Writing one to this bit forces an acknowledge error 3. - FAE3: u1, - /// Force acknowledge error 4 Writing one to this bit forces an acknowledge error 4. - FAE4: u1, - /// Force acknowledge error 5 Writing one to this bit forces an acknowledge error 5. - FAE5: u1, - /// Force acknowledge error 6 Writing one to this bit forces an acknowledge error 6. - FAE6: u1, - /// Force acknowledge error 7 Writing one to this bit forces an acknowledge error 7. - FAE7: u1, - /// Force acknowledge error 8 Writing one to this bit forces an acknowledge error 8. - FAE8: u1, - /// Force acknowledge error 9 Writing one to this bit forces an acknowledge error 9. - FAE9: u1, - /// Force acknowledge error 10 Writing one to this bit forces an acknowledge error 10. - FAE10: u1, - /// Force acknowledge error 11 Writing one to this bit forces an acknowledge error 11. - FAE11: u1, - /// Force acknowledge error 12 Writing one to this bit forces an acknowledge error 12. - FAE12: u1, - /// Force acknowledge error 13 Writing one to this bit forces an acknowledge error 13. - FAE13: u1, - /// Force acknowledge error 14 Writing one to this bit forces an acknowledge error 14. - FAE14: u1, - /// Force acknowledge error 15 Writing one to this bit forces an acknowledge error 15. - FAE15: u1, - /// Force PHY error 0 Writing one to this bit forces a PHY error 0. - FPE0: u1, - /// Force PHY error 1 Writing one to this bit forces a PHY error 1. - FPE1: u1, - /// Force PHY error 2 Writing one to this bit forces a PHY error 2. - FPE2: u1, - /// Force PHY error 3 Writing one to this bit forces a PHY error 3. - FPE3: u1, - /// Force PHY error 4 Writing one to this bit forces a PHY error 4. - FPE4: u1, - padding: u11, - }), - /// DSI Host force interrupt register 1. - FIR1: mmio.Mmio(packed struct(u32) { - /// Force timeout high-speed transmission Writing one to this bit forces a timeout high-speed transmission. - FTOHSTX: u1, - /// Force timeout low-power reception Writing one to this bit forces a timeout low-power reception. - FTOLPRX: u1, - /// Force ECC single-bit error Writing one to this bit forces a ECC single-bit error. - FECCSE: u1, - /// Force ECC multi-bit error Writing one to this bit forces a ECC multi-bit error. - FECCME: u1, - /// Force CRC error Writing one to this bit forces a CRC error. - FCRCE: u1, - /// Force packet size error Writing one to this bit forces a packet size error. - FPSE: u1, - /// Force EoTp error Writing one to this bit forces a EoTp error. - FEOTPE: u1, - /// Force LTDC payload write error Writing one to this bit forces a LTDC payload write error. - FLPWRE: u1, - /// Force generic command write error Writing one to this bit forces a generic command write error. - FGCWRE: u1, - /// Force generic payload write error Writing one to this bit forces a generic payload write error. - FGPWRE: u1, - /// Force generic payload transmit error Writing one to this bit forces a generic payload transmit error. - FGPTXE: u1, - /// Force generic payload read error Writing one to this bit forces a generic payload read error. - FGPRDE: u1, - /// Force generic payload receive error Writing one to this bit forces a generic payload receive error. - FGPRXE: u1, - reserved19: u6, - /// Force payload buffer underflow error Writing one to this bit forces a payload undrflow error. - FPBUE: u1, - padding: u12, - }), - reserved244: [20]u8, - /// DSI Host data lane timer read configuration register. - DLTRCR: mmio.Mmio(packed struct(u32) { - /// Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress. - MRD_TIME: u15, - padding: u17, - }), - reserved256: [8]u8, - /// DSI Host video shadow control register. - VSCR: mmio.Mmio(packed struct(u32) { - /// Enable When set to 1, DSI Host LTDC interface receives the active configuration from the auxiliary registers. When this bit is set along with the UR bit, the auxiliary registers are automatically updated. - EN: u1, - reserved8: u7, - /// Update register When set to 1, the LTDC registers are copied to the auxiliary registers. After copying, this bit is auto cleared. - UR: u1, - padding: u23, - }), - reserved268: [8]u8, - /// DSI Host LTDC current VCID register. - LCVCIDR: mmio.Mmio(packed struct(u32) { - /// Virtual channel ID This field returns the virtual channel ID for the LTDC interface. - VCID: u2, - padding: u30, - }), - /// DSI Host LTDC current color coding register. - LCCCR: mmio.Mmio(packed struct(u32) { - /// Color coding This field returns the current LTDC interface color coding. 0110-1111: reserved If LTDC interface in command mode is chosen and currently works in the command mode (CMDM=1), then 0110-1111: 24-bit. - COLC: u4, - reserved8: u4, - /// Loosely packed enable This bit returns the current state of the loosely packed variant to 18-bit configurations. - LPE: u1, - padding: u23, - }), - reserved280: [4]u8, - /// DSI Host low-power mode current configuration register. - LPMCCR: mmio.Mmio(packed struct(u32) { - /// VACT largest packet size This field returns the current size, in bytes, of the largest packet that can fit in a line during VACT regions, for the transmission of commands in low-power mode. - VLPSIZE: u8, - reserved16: u8, - /// Largest packet size This field is returns the current size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions, for the transmission of commands in low-power mode. - LPSIZE: u8, - padding: u8, - }), - reserved312: [28]u8, - /// DSI Host video mode current configuration register. - VMCCR: mmio.Mmio(packed struct(u32) { - /// Video mode type This field returns the current video mode transmission type: 1x: Burst mode. - VMT: u2, - /// Low-power vertical sync time enable This bit returns the current state of return to low-power inside the vertical sync time (VSA) period when timing allows. - LPVSAE: u1, - /// Low-power vertical back-porch enable This bit returns the current state of return to low-power inside the vertical back-porch (VBP) period when timing allows. - LPVBPE: u1, - /// Low-power vertical front-porch enable This bit returns the current state of return to low-power inside the vertical front-porch (VFP) period when timing allows. - LPVFPE: u1, - /// Low-power vertical active enable This bit returns the current state of return to low-power inside the vertical active (VACT) period when timing allows. - LPVAE: u1, - /// Low-power horizontal back-porch enable This bit returns the current state of return to low-power inside the horizontal back-porch (HBP) period when timing allows. - LPHBPE: u1, - /// Low-power horizontal front-porch enable This bit returns the current state of return to low-power inside the horizontal front-porch (HFP) period when timing allows. - LPHFE: u1, - /// Frame BTA acknowledge enable This bit returns the current state of request for an acknowledge response at the end of a frame. - FBTAAE: u1, - /// Low-power command enable This bit returns the current command transmission state in low-power mode. - LPCE: u1, - padding: u22, + /// Debug MCU Configuration Register + CR: mmio.Mmio(packed struct(u32) { + /// Debug Sleep Mode + DBG_SLEEP: u1, + /// Debug Stop Mode + DBG_STOP: u1, + /// Debug Standby Mode + DBG_STANDBY: u1, + reserved5: u2, + /// Trace port and clock enable + TRACE_IOEN: u1, + reserved28: u22, + /// External trigger output enable + TRGOEN: u1, + padding: u3, }), - /// DSI Host video packet current configuration register. - VPCCR: mmio.Mmio(packed struct(u32) { - /// Video packet size This field returns the number of pixels in a single video packet. - VPSIZE: u14, - padding: u18, + reserved60: [52]u8, + /// APB1 Low Freeze Register CPU1 + APB1FZR1: mmio.Mmio(packed struct(u32) { + /// Debug Timer 2 stopped when Core is halted + TIM2: u1, + reserved10: u9, + /// RTC counter stopped when core is halted + RTC: u1, + /// WWDG counter stopped when core is halted + WWDG: u1, + /// IWDG counter stopped when core is halted + IWDG: u1, + reserved21: u8, + /// Debug I2C1 SMBUS timeout stopped when Core is halted + I2C1: u1, + reserved23: u1, + /// Debug I2C3 SMBUS timeout stopped when core is halted + I2C3: u1, + reserved31: u7, + /// Debug LPTIM1 stopped when Core is halted + LPTIM1: u1, }), - /// DSI Host video chunks current configuration register. - VCCCR: mmio.Mmio(packed struct(u32) { - /// Number of chunks This field returns the number of chunks being transmitted during a line period. - NUMC: u13, - padding: u19, + /// APB1 Low Freeze Register CPU2 + C2AP_B1FZR1: mmio.Mmio(packed struct(u32) { + /// LPTIM2 counter stopped when core is halted + LPTIM2: u1, + reserved10: u9, + /// RTC counter stopped when core is halted + RTC: u1, + reserved12: u1, + /// IWDG stopped when core is halted + IWDG: u1, + reserved21: u8, + /// I2C1 SMBUS timeout stopped when core is halted + I2C1: u1, + reserved23: u1, + /// I2C3 SMBUS timeout stopped when core is halted + I2C3: u1, + reserved31: u7, + /// LPTIM1 counter stopped when core is halted + LPTIM1: u1, }), - /// DSI Host video null packet current configuration register. - VNPCCR: mmio.Mmio(packed struct(u32) { - /// Null packet size This field returns the number of bytes inside a null packet. - NPSIZE: u13, - padding: u19, + /// APB1 High Freeze Register CPU1 + APB1FZR2: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// LPTIM2 counter stopped when core is halted + LPTIM2: u1, + padding: u26, }), - /// DSI Host video HSA current configuration register. - VHSACCR: mmio.Mmio(packed struct(u32) { - /// Horizontal synchronism active duration This fields returns the horizontal synchronism active period in lane byte clock cycles. - HSA: u12, - padding: u20, + /// APB1 High Freeze Register CPU2 + C2APB1FZR2: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// LPTIM2 counter stopped when core is halted + LPTIM2: u1, + padding: u26, }), - /// DSI Host video HBP current configuration register. - VHBPCCR: mmio.Mmio(packed struct(u32) { - /// Horizontal back-porch duration This field returns the horizontal back-porch period in lane byte clock cycles. - HBP: u12, - padding: u20, + /// APB2 Freeze Register CPU1 + APB2FZR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 counter stopped when core is halted + TIM1: u1, + reserved17: u5, + /// TIM16 counter stopped when core is halted + TIM16: u1, + /// TIM17 counter stopped when core is halted + TIM17: u1, + padding: u13, }), - /// DSI Host video line current configuration register. - VLCCR: mmio.Mmio(packed struct(u32) { - /// Horizontal line duration This field returns the current total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles. - HLINE: u15, - padding: u17, + }; + }; + + pub const dbgmcu_wba = struct { + /// Microcontroller debug unit + pub const DBGMCU = extern struct { + /// identity code register + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device ID + DEV_ID: u12, + reserved16: u4, + /// Revision ID + REV_ID: u16, }), - /// DSI Host video VSA current configuration register. - VVSACCR: mmio.Mmio(packed struct(u32) { - /// Vertical synchronism active duration This field returns the current vertical synchronism active period measured in number of horizontal lines. - VSA: u10, - padding: u22, + /// status and configuration register + CR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Allows debug in Stop mode Write access can be protected by PWR_SECCFGR.LPMSEC. The CPU debug and clocks remain active and the HSI oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state. + DBG_STOP: u1, + /// Allows debug in Standby mode Write access can be protected by PWR_SECCFGR.LPMSEC. The CPU debug and clocks remain active and the HSI oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed. + DBG_STANDBY: u1, + reserved16: u13, + /// Device low power mode selected 10x: Standby mode others reserved + LPMS: u3, + /// Device Stop flag + STOPF: u1, + /// Device Standby flag + SBF: u1, + reserved24: u3, + /// CPU Sleep + CS: u1, + /// CPU DeepSleep + CDS: u1, + padding: u6, }), - /// DSI Host video VBP current configuration register. - VVBPCCR: mmio.Mmio(packed struct(u32) { - /// Vertical back-porch duration This field returns the current vertical back-porch period measured in number of horizontal lines. - VBP: u10, - padding: u22, + /// APB1L peripheral freeze register + APB1LFZR: mmio.Mmio(packed struct(u32) { + /// TIM2 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM2SEC. + DBG_TIM2_STOP: u1, + /// TIM3 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM3SEC. + DBG_TIM3_STOP: u1, + reserved11: u9, + /// WWDG stop in CPU debug Write access can be protected by GTZC_TZSC.WWDGSEC + DBG_WWDG_STOP: u1, + /// IWDG stop in CPU debug Write access can be protected by GTZC_TZSC.IWDGSEC. + DBG_IWDG_STOP: u1, + reserved21: u8, + /// I2C1 SMBUS timeout stop in CPU debug Write access can be protected by GTZC_TZSC.I2C1SEC. + DBG_I2C1_STOP: u1, + padding: u10, }), - /// DSI Host video VFP current configuration register. - VVFPCCR: mmio.Mmio(packed struct(u32) { - /// Vertical front-porch duration This field returns the current vertical front-porch period measured in number of horizontal lines. - VFP: u10, - padding: u22, + /// APB1H peripheral freeze register + APB1HFZR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// LPTIM2 stop in CPU debug Write access can be protected by GTZC_TZSC.LPTIM2SEC. + DBG_LPTIM2_STOP: u1, + padding: u26, }), - /// DSI Host video VA current configuration register. - VVACCR: mmio.Mmio(packed struct(u32) { - /// Vertical active duration This field returns the current vertical active period measured in number of horizontal lines. - VA: u14, - padding: u18, + /// APB2 peripheral freeze register + APB2FZR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM1SEC. + DBG_TIM1_STOP: u1, + reserved17: u5, + /// TIM16 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM16SEC. + DBG_TIM16_STOP: u1, + /// TIM17 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM17SEC. + DBG_TIM17_STOP: u1, + padding: u13, }), - reserved360: [4]u8, - /// DSI Host FIFO and buffer status register. - FBSR: mmio.Mmio(packed struct(u32) { - /// Video mode command write FIFO empty This bit indicates the empty status of the video mode write command FIFO:. - VCWFE: u1, - /// Video mode command write FIFO full This bit indicates the full status of the video mode write command FIFO:. - VCWFF: u1, - /// Video mode payload write FIFO empty This bit indicates the empty status of the video mode write payload FIFO:. - VPWFE: u1, - /// Video mode payload write FIFO full This bit indicates the full status of the video mode write payload FIFO:. - VPWFF: u1, - /// Adapted command mode command write FIFO empty This bit indicates the empty status of the adapted command mode write command FIFO:. - ACWFE: u1, - /// Adapted command mode command write FIFO full This bit indicates the full status of the adapted command mode write command FIFO:. - ACWFF: u1, - /// Adapted command mode payload write FIFO empty This bit indicates the empty status of the adapted command mode write payload FIFO:. - APWFE: u1, - /// Adapted command mode payload write FIFO full This bit indicates the full status of the adapted command mode write payload FIFO:. - APWFF: u1, - reserved16: u8, - /// Video mode payload buffer empty This bit indicates the empty status of the video mode payload internal buffer:. - VPBE: u1, - /// Video mode payload buffer full This bit indicates the full status of the video mode payload internal buffer:. - VPBF: u1, - reserved20: u2, - /// Adapted command mode command buffer empty This bit indicates the empty status of the adapted command mode command internal buffer:. - ACBE: u1, - /// Adapted command mode command buffer full This bit indicates the full status of the adapted command mode command internal buffer:. - ACBF: u1, - /// Adapted command mode payload buffer empty This bit indicates the empty status of the adapted command mode payload internal buffer:. - APBE: u1, - /// Adapted command mode payload buffer full This bit indicates the full status of the adapted command mode payload internal buffer:. - APBF: u1, - padding: u8, + reserved36: [16]u8, + /// APB7 peripheral freeze register + APB7FZR: mmio.Mmio(packed struct(u32) { + reserved10: u10, + /// I2C3 stop in CPU debug Access can be protected by GTZC_TZSC.I2C3SEC. + DBG_I2C3_STOP: u1, + reserved17: u6, + /// LPTIM1 stop in CPU debug Access can be protected by GTZC_TZSC.LPTIM1SEC. + DBG_LPTIM1_STOP: u1, + reserved30: u12, + /// RTC stop in CPU debug Access can be protected by GTZC_TZSC.TIM17SEC. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. + DBG_RTC_STOP: u1, + padding: u1, }), - reserved1024: [660]u8, - /// DSI Wrapper configuration register. - WCFGR: mmio.Mmio(packed struct(u32) { - /// DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (CR.EN = 0). - DSIM: u1, - /// Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.EN = 0). - COLMUX: u3, - /// TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0). - TESRC: u1, - /// TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0). - TEPOL: u1, - /// Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (CR.EN = 0). - AR: u1, - /// VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.EN = 0). - VSPOL: u1, + /// AHB1 peripheral freeze register + AHB1FZR: mmio.Mmio(packed struct(u32) { + /// GPDMA 1 channel 0 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC0. + DBG_GPDMA1_CH0_STOP: u1, + /// GPDMA 1 channel 1 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC1. + DBG_GPDMA1_CH1_STOP: u1, + /// GPDMA 1 channel 2 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC2. + DBG_GPDMA1_CH2_STOP: u1, + /// GPDMA 1 channel 3 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC3. + DBG_GPDMA1_CH3_STOP: u1, + /// GPDMA 1 channel 4 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC4. + DBG_GPDMA1_CH4_STOP: u1, + /// GPDMA 1 channel 5 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC5. + DBG_GPDMA1_CH5_STOP: u1, + /// GPDMA 1 channel 6 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC6. + DBG_GPDMA1_CH6_STOP: u1, + /// GPDMA 1 channel 7 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC7. + DBG_GPDMA1_CH7_STOP: u1, padding: u24, }), - /// DSI Wrapper control register. - WCR: mmio.Mmio(packed struct(u32) { - /// Color mode This bit controls the display color mode in video mode. - COLM: u1, - /// Shutdown This bit controls the display shutdown in video mode. - SHTDN: u1, - /// LTDC enable This bit enables the LTDC for a frame transfer in adapted command mode. - LTDCEN: u1, - /// DSI enable This bit enables the DSI Wrapper. - DSIEN: u1, - padding: u28, + reserved252: [208]u8, + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Bit n identifies whether access port APn is present in device Bit n�=�0: APn absent Bit n�=�1: APn present + AP_PRESENT: u16, + /// Bit n identifies whether access port APn is open (can be accessed via the debug port) or locked (debug access to the APn is blocked, except for access) Bit n�=�0: APn locked (except for access to DBGMCU) Bit n�=�1: APn enabled + AP_ENABLED: u16, }), - /// DSI Wrapper interrupt enable register. - WIER: mmio.Mmio(packed struct(u32) { - /// Tearing effect interrupt enable This bit enables the tearing effect interrupt. - TEIE: u1, - /// End of refresh interrupt enable This bit enables the end of refresh interrupt. - ERIE: u1, - reserved9: u7, - /// PLL lock interrupt enable This bit enables the PLL lock interrupt. - PLLLIE: u1, - /// PLL unlock interrupt enable This bit enables the PLL unlock interrupt. - PLLUIE: u1, - padding: u21, + /// debug host authentication register + DBG_AUTH_HOST: mmio.Mmio(packed struct(u32) { + /// Device authentication key The device specific 64-bit authentication key (OEMn key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory. + AUTH_KEY: u32, }), - /// DSI Wrapper interrupt and status register. - WISR: mmio.Mmio(packed struct(u32) { - /// Tearing effect interrupt flag This bit is set when a tearing effect event occurs. - TEIF: u1, - /// End of refresh interrupt flag This bit is set when the transfer of a frame in adapted command mode is finished. - ERIF: u1, - /// Busy flag This bit is set when the transfer of a frame in adapted command mode is ongoing. - BUSY: u1, - reserved8: u5, - /// PLL lock status This bit is set when the PLL is locked and cleared when it is unlocked. - PLLLS: u1, - /// PLL lock interrupt flag This bit is set when the PLL becomes locked. - PLLLIF: u1, - /// PLL unlock interrupt flag This bit is set when the PLL becomes unlocked. - PLLUIF: u1, - padding: u21, + /// debug device authentication register + DBG_AUTH_DEVICE: mmio.Mmio(packed struct(u32) { + /// Device specific ID Device specific ID used for RDP regression. + AUTH_ID: u32, }), - /// DSI Wrapper interrupt flag clear register. - WIFCR: mmio.Mmio(packed struct(u32) { - /// Clear tearing effect interrupt flag Write 1 clears the TEIF flag in the WSR register. - CTEIF: u1, - /// Clear end of refresh interrupt flag Write 1 clears the ERIF flag in the WSR register. - CERIF: u1, - reserved9: u7, - /// Clear PLL lock interrupt flag Write 1 clears the PLLLIF flag in the WSR register. - CPLLLIF: u1, - /// Clear PLL unlock interrupt flag Write 1 clears the PLLUIF flag in the WSR register. - CPLLUIF: u1, - padding: u21, + reserved2012: [1748]u8, + /// part number codification register + PNCR: mmio.Mmio(packed struct(u32) { + /// Part number codification + CODIFICATION: u32, }), - reserved1048: [4]u8, - /// DSI Wrapper PHY configuration register 0. - WPCR0: mmio.Mmio(packed struct(u32) { - reserved6: u6, - /// Swap clock lane pins This bit swaps the pins on clock lane. - SWCL: u1, - /// Swap data lane 0 pins This bit swaps the pins on data lane 0. - SWDL0: u1, - /// Swap data lane 1 pins This bit swaps the pins on clock lane. - SWDL1: u1, - reserved12: u3, - /// Force in TX Stop mode the clock lane This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. - FTXSMCL: u1, - /// Force in TX Stop mode the data lanes This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. - FTXSMDL: u1, - padding: u18, + reserved4048: [2032]u8, + /// CoreSight peripheral identity register 4 + PIDR4: mmio.Mmio(packed struct(u32) { + /// JEP106 continuation code + JEP106CON: u4, + /// Register file size + F4KCOUNT: u4, + padding: u24, }), - reserved1072: [20]u8, - /// DSI Wrapper regulator and PLL control register. - WRPCR: mmio.Mmio(packed struct(u32) { - /// PLL enable This bit enables the D-PHY PLL. - PLLEN: u1, - reserved2: u1, - /// PLL loop division factor This field configures the PLL loop division factor. 2: PLL loop divided by 2x2 ... 511: PLL loop divided by 511x2. - NDIV: u9, - /// PLL input division factor This field configures the PLL input division factor. 2: PLL input divided by 2 ... 511: PLL input divided by 511. - IDF: u9, - /// PLL output division factor This field configures the PLL output division factor. 2: PLL output divided by 2 ... 511: PLL output divided by 511. - ODF: u9, - padding: u3, + reserved4064: [12]u8, + /// CoreSight peripheral identity register 0 + PIDR0: mmio.Mmio(packed struct(u32) { + /// Part number bits [7:0] + PARTNUM: u8, + padding: u24, }), - reserved2056: [980]u8, - /// DSI bias configuration register. - BCFGR: mmio.Mmio(packed struct(u32) { - reserved6: u6, - /// Power-up This bit powers-up the reference bias for the MIPI D-PHY. - PWRUP: u1, - padding: u25, + /// CoreSight peripheral identity register 1 + PIDR1: mmio.Mmio(packed struct(u32) { + /// Part number bits [11:8] + PARTNUM: u4, + /// JEP106 identity code bits [3:0] + JEP106ID: u4, + padding: u24, }), - reserved3076: [1016]u8, - /// DSI D-PHY clock band control register. - DPCBCR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Band control This field selects the frequency band used by the D-PHY. Others: Reserved. - BC: u5, + /// CoreSight peripheral identity register 2 + PIDR2: mmio.Mmio(packed struct(u32) { + /// JEP106 identity code bits [6:4] + JEP106ID: u3, + /// JEDEC assigned value + JEDEC: u1, + /// Component revision number + REVISION: u4, padding: u24, }), - reserved3124: [44]u8, - /// DSI D-PHY clock skew rate control register. - DPCSRCR: mmio.Mmio(packed struct(u32) { - /// Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved. - SRC: u8, + /// CoreSight peripheral identity register 3 + PIDR3: mmio.Mmio(packed struct(u32) { + /// Customer modified + CMOD: u4, + /// Metal fix version + REVAND: u4, padding: u24, }), - reserved3184: [56]u8, - /// DSI D-PHY data lane 0 band control register. - DPDL0BCR: mmio.Mmio(packed struct(u32) { - /// Band control This field selects the frequency band used by the D-PHY. Others: Reserved. - BC: u5, - padding: u27, + /// CoreSight component identity register 0 + CIDR0: mmio.Mmio(packed struct(u32) { + /// Component ID bits [7:0] + PREAMBLE: u8, + padding: u24, }), - reserved3232: [44]u8, - /// DSI D-PHY data lane 0 skew rate control register. - DPDL0SRCR: mmio.Mmio(packed struct(u32) { - /// Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved. - SRC: u8, + /// CoreSight peripheral identity register 1 + CIDR1: mmio.Mmio(packed struct(u32) { + /// Component ID bits [11:8] + PREAMBLE: u4, + /// Component ID bits [15:12] - component class + CLASS: u4, padding: u24, }), - reserved3336: [100]u8, - /// DSI D-PHY data lane 1 band control register. - DPDL1BCR: mmio.Mmio(packed struct(u32) { - /// Band control This field selects the frequency band used by the D-PHY. Others: Reserved. - BC: u5, - padding: u27, + /// CoreSight component identity register 2 + CIDR2: mmio.Mmio(packed struct(u32) { + /// Component ID bits [23:16] + PREAMBLE: u8, + padding: u24, }), - reserved3384: [44]u8, - /// DSI D-PHY data lane 1 skew rate control register. - DPDL1SRCR: mmio.Mmio(packed struct(u32) { - /// Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved. - SRC: u8, + /// CoreSight component identity register 3 + CIDR3: mmio.Mmio(packed struct(u32) { + /// Component ID bits [31:24] + PREAMBLE: u8, padding: u24, }), }; }; - pub const syscfg_h7od = struct { - pub const ETH_SEL_PHY = enum(u3) { - /// GMII or MII - MII_GMII = 0x0, - /// RMII - RMII = 0x4, - _, - }; - - /// System configuration controller - pub const SYSCFG = extern struct { - reserved4: [4]u8, - /// peripheral mode configuration register - PMCR: mmio.Mmio(packed struct(u32) { - /// I2C1 Fm+ - I2C1FMP: u1, - /// I2C2 Fm+ - I2C2FMP: u1, - /// I2C3 Fm+ - I2C3FMP: u1, - /// I2C4 Fm+ - I2C4FMP: u1, - /// PB(6) Fm+ - PB6FMP: u1, - /// PB(7) Fast Mode Plus - PB7FMP: u1, - /// PB(8) Fast Mode Plus - PB8FMP: u1, - /// PB(9) Fm+ - PB9FMP: u1, - /// Booster Enable - BOOSTE: u1, - /// Analog switch supply voltage selection - BOOSTVDDSEL: u1, - reserved21: u11, - /// Ethernet PHY interface selection. - ETH_SEL_PHY: packed union { - raw: u3, - value: ETH_SEL_PHY, - }, - /// PA0 Switch Open - PA0SO: u1, - /// PA1 Switch Open - PA1SO: u1, - /// PC2 Switch Open - PC2SO: u1, - /// PC3 Switch Open - PC3SO: u1, - padding: u4, - }), - /// external interrupt configuration register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration (x = 4 to 7) - EXTI: u4, - padding: u28, - }), - reserved32: [8]u8, - /// compensation cell control/status register - CCCSR: mmio.Mmio(packed struct(u32) { - /// enable - EN: u1, - /// Code selection - CS: u1, - reserved8: u6, - /// Compensation cell ready flag - RDY: u1, - reserved16: u7, - /// High-speed at low-voltage - HSLV: u1, - padding: u15, - }), - /// SYSCFG compensation cell value register - CCVR: mmio.Mmio(packed struct(u32) { - /// NMOS compensation value - NCV: u4, - /// PMOS compensation value - PCV: u4, - padding: u24, - }), - /// SYSCFG compensation cell code register - CCCR: mmio.Mmio(packed struct(u32) { - /// NMOS compensation code - NCC: u4, - /// PMOS compensation code - PCC: u4, - padding: u24, - }), - /// SYSCFG power control register - PWRCR: mmio.Mmio(packed struct(u32) { - /// Overdrive enable - ODEN: u4, - padding: u28, - }), - reserved292: [244]u8, - /// SYSCFG package register - PKGR: mmio.Mmio(packed struct(u32) { - /// Package - PKG: u4, - padding: u28, - }), - reserved768: [472]u8, - /// SYSCFG user register 0 - UR0: mmio.Mmio(packed struct(u32) { - /// Bank Swap - BKS: u1, - reserved16: u15, - /// Readout protection - RDP: u8, - padding: u8, - }), - reserved776: [4]u8, - /// SYSCFG user register 2 - UR2: mmio.Mmio(packed struct(u32) { - /// BOR_LVL Brownout Reset Threshold Level - BORH: u2, - reserved16: u14, - /// Boot Address 0 - BOOT_ADD0: u16, + pub const dbgmcu_wl = struct { + /// Microcontroller Debug Unit + pub const DBGMCU = extern struct { + /// Identity Code Register + IDCODER: mmio.Mmio(packed struct(u32) { + /// Device ID + DEV_ID: u12, + reserved16: u4, + /// Revision + REV_ID: u16, }), - /// SYSCFG user register 3 - UR3: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Boot Address 1 - BOOT_ADD1: u16, + /// Configuration Register + CR: mmio.Mmio(packed struct(u32) { + /// Allow debug in SLEEP mode + DBG_SLEEP: u1, + /// Allow debug in STOP mode + DBG_STOP: u1, + /// Allow debug in STANDBY mode + DBG_STANDBY: u1, + padding: u29, }), - /// SYSCFG user register 4 - UR4: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Mass Erase Protected Area Disabled for bank 1 - MEPAD_1: u1, - padding: u15, + reserved60: [52]u8, + /// CPU1 APB1 Peripheral Freeze Register 1 + APB1FZR1: mmio.Mmio(packed struct(u32) { + /// TIM2 stop in CPU1 debug + TIM2: u1, + reserved10: u9, + /// RTC stop in CPU1 debug + RTC: u1, + /// WWDG stop in CPU1 debug + WWDG: u1, + /// IWDG stop in CPU1 debug + IWDG: u1, + reserved21: u8, + /// I2C1 SMBUS timeout stop in CPU1 debug + I2C1: u1, + /// I2C2 SMBUS timeout stop in CPU1 debug + I2C2: u1, + /// I2C3 SMBUS timeout stop in CPU1 debug + I2C3: u1, + reserved31: u7, + /// LPTIM1 stop in CPU1 debug + LPTIM1: u1, }), - /// SYSCFG user register 5 - UR5: mmio.Mmio(packed struct(u32) { - /// Mass erase secured area disabled for bank 1 - MESAD_1: u1, - reserved16: u15, - /// Write protection for flash bank 1 - WRPN_1: u8, - padding: u8, + /// CPU2 APB1 Peripheral Freeze Register 1 [dual core device + C2APB1FZR1: mmio.Mmio(packed struct(u32) { + /// TIM2 + TIM2: u1, + reserved10: u9, + /// RTC + RTC: u1, + reserved12: u1, + /// IWDG + IWDG: u1, + reserved21: u8, + /// I2C1 + I2C1: u1, + /// I2C2 + I2C2: u1, + /// I2C3 + I2C3: u1, + reserved31: u7, + /// LPTIM1 + LPTIM1: u1, }), - /// SYSCFG user register 6 - UR6: mmio.Mmio(packed struct(u32) { - /// Protected area start address for bank 1 - PA_BEG_1: u12, - reserved16: u4, - /// Protected area end address for bank 1 - PA_END_1: u12, - padding: u4, + /// CPU1 APB1 Peripheral Freeze Register 2 + APB1FZR2: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// LPTIM2 + LPTIM2: u1, + /// LPTIM3 + LPTIM3: u1, + padding: u25, }), - /// SYSCFG user register 7 - UR7: mmio.Mmio(packed struct(u32) { - /// Secured area start address for bank 1 - SA_BEG_1: u12, - reserved16: u4, - /// Secured area end address for bank 1 - SA_END_1: u12, - padding: u4, + /// CPU2 APB1 Peripheral Freeze Register 2 [dual core device + C2APB1FZR2: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// LPTIM2 + LPTIM2: u1, + /// LPTIM3 + LPTIM3: u1, + padding: u25, }), - /// SYSCFG user register 8 - UR8: mmio.Mmio(packed struct(u32) { - /// Mass erase protected area disabled for bank 2 - MEPAD_2: u1, - reserved16: u15, - /// Mass erase secured area disabled for bank 2 - MESAD_2: u1, - padding: u15, + /// CPU1 APB2 Peripheral Freeze Register + APB2FZR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 + TIM1: u1, + reserved17: u5, + /// TIM16 + TIM16: u1, + /// TIM17 + TIM17: u1, + padding: u13, }), - /// SYSCFG user register 9 - UR9: mmio.Mmio(packed struct(u32) { - /// Write protection for flash bank 2 - WRPN_2: u8, - reserved16: u8, - /// Protected area start address for bank 2 - PA_BEG_2: u12, - padding: u4, + /// CPU2 APB2 Peripheral Freeze Register [dual core device + C2APB2FZR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 + TIM1: u1, + reserved17: u5, + /// TIM16 + TIM16: u1, + /// TIM17 + TIM17: u1, + padding: u13, }), - /// SYSCFG user register 10 - UR10: mmio.Mmio(packed struct(u32) { - /// Protected area end address for bank 2 - PA_END_2: u12, + }; + }; + + pub const dcache_v1 = struct { + /// Data cache. + pub const DCACHE = extern struct { + /// DCACHE control register. + CR: mmio.Mmio(packed struct(u32) { + /// enable. + EN: u1, + /// full cache invalidation Can be set by software, only when EN = 1. Cleared by hardware when the BUSYF flag is set (during full cache invalidation operation). Writing 0 has no effect. + CACHEINV: u1, + reserved8: u6, + /// cache command maintenance operation (cleans and/or invalidates an address range) Can be set and cleared by software, only when no maintenance command is ongoing (BUSYCMDF = 0). others: reserved. + CACHECMD: u3, + /// starts maintenance command (maintenance operation defined in CACHECMD). Can be set by software, only when EN = 1, BUSYCMDF = 0, BUSYF = 0 and CACHECMD = 0b001, 0b010 or 0b011. Cleared by hardware when the BUSYCMDF flag is set (during cache maintenance operation). Writing 0 has no effect. + STARTCMD: u1, reserved16: u4, - /// Secured area start address for bank 2 - SA_BEG_2: u12, - padding: u4, + /// read-hit monitor enable. + RHITMEN: u1, + /// read-miss monitor enable. + RMISSMEN: u1, + /// read-hit monitor reset. + RHITMRST: u1, + /// read-miss monitor reset. + RMISSMRST: u1, + /// write-hit monitor enable. + WHITMEN: u1, + /// write-miss monitor enable. + WMISSMEN: u1, + /// write-hit monitor reset. + WHITMRST: u1, + /// write-miss monitor reset. + WMISSMRST: u1, + reserved31: u7, + /// output burst type for cache master port read accesses Write access is always done in INCR burst type. + HBURST: u1, }), - /// SYSCFG user register 11 - UR11: mmio.Mmio(packed struct(u32) { - /// Secured area end address for bank 2 - SA_END_2: u12, - reserved16: u4, - /// Independent Watchdog 1 mode - IWDG1M: u1, - padding: u15, + /// DCACHE status register. + SR: mmio.Mmio(packed struct(u32) { + /// full invalidate busy flag. + BUSYF: u1, + /// full invalidate busy end flag Cleared by writing DCACHE_FCR.CBSYENDF = 1. + BSYENDF: u1, + /// cache error flag Cleared by writing DCACHE_FCR.CERRF = 1. + ERRF: u1, + /// command busy flag. + BUSYCMDF: u1, + /// command end flag Cleared by writing DCACHE_FCR.CCMDENDF = 1. + CMDENDF: u1, + padding: u27, }), - /// SYSCFG user register 12 - UR12: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Secure mode - SECURE: u1, - padding: u15, + /// DCACHE interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// interrupt enable on busy end Set by SW to enable an interrupt generation at the end of a cache full invalidate operation. + BSYENDIE: u1, + /// interrupt enable on cache error Set by software to enable an interrupt generation in case of cache functional error (eviction or clean operation write-back error). + ERRIE: u1, + reserved4: u1, + /// interrupt enable on command end Set by software to enable an interrupt generation at the end of a cache command (clean and/or invalidate an address range). + CMDENDIE: u1, + padding: u27, }), - /// SYSCFG user register 13 - UR13: mmio.Mmio(packed struct(u32) { - /// Secured DTCM RAM Size - SDRS: u2, - reserved16: u14, - /// D1 Standby reset - D1SBRST: u1, - padding: u15, + /// DCACHE flag clear register. + FCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// clear full invalidate busy end flag Set by software. + CBSYENDF: u1, + /// clear cache error flag Set by software. + CERRF: u1, + reserved4: u1, + /// clear command end flag Set by software. + CCMDENDF: u1, + padding: u27, }), - /// SYSCFG user register 14 - UR14: mmio.Mmio(packed struct(u32) { - /// D1 Stop Reset - D1STPRST: u1, - padding: u31, + /// DCACHE read-hit monitor register. + RHMONR: u32, + /// DCACHE read-miss monitor register. + RMMONR: mmio.Mmio(packed struct(u32) { + /// cache read-miss monitor counter. + RMISSMON: u16, + padding: u16, }), - /// SYSCFG user register 15 - UR15: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Freeze independent watchdog in Standby mode - FZIWDGSTB: u1, - padding: u15, + reserved32: [8]u8, + /// DCACHE write-hit monitor register. + WHMONR: u32, + /// DCACHE write-miss monitor register. + WMMONR: mmio.Mmio(packed struct(u32) { + /// cache write-miss monitor counter. + WMISSMON: u16, + padding: u16, }), - /// SYSCFG user register 16 - UR16: mmio.Mmio(packed struct(u32) { - /// Freeze independent watchdog in Stop mode - FZIWDGSTP: u1, - reserved16: u15, - /// Private key programmed - PKP: u1, - padding: u15, + /// DCACHE command range start address register. + CMDRSADDRR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// start address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written.. + CMDSTARTADDR: u28, }), - /// SYSCFG user register 17 - UR17: mmio.Mmio(packed struct(u32) { - /// I/O high speed / low voltage - IO_HSLV: u1, - padding: u31, + /// DCACHE command range end address register. + CMDREADDRR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// end address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written. + CMDENDADDR: u28, }), }; }; - pub const pwr_l5 = struct { - pub const LPMS = enum(u3) { - /// Stop 0 mode - Stop0 = 0x0, - /// Stop 1 mode - Stop1 = 0x1, - /// Stop 2 mode - Stop2 = 0x2, - /// Standby mode - Standby = 0x3, - /// Shutdown mode - Shutdown = 0x4, + pub const dcmi_v1 = struct { + /// Digital camera interface + pub const DCMI = extern struct { + /// control register 1 + CR: mmio.Mmio(packed struct(u32) { + /// Capture enable + CAPTURE: u1, + /// Capture mode + CM: u1, + /// Crop feature + CROP: u1, + /// JPEG format + JPEG: u1, + /// Embedded synchronization select + ESS: u1, + /// Pixel clock polarity + PCKPOL: u1, + /// Horizontal synchronization polarity + HSPOL: u1, + /// Vertical synchronization polarity + VSPOL: u1, + /// Frame capture rate control + FCRC: u2, + /// Extended data mode + EDM: u2, + reserved14: u2, + /// DCMI enable + ENABLE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// HSYNC + HSYNC: u1, + /// VSYNC + VSYNC: u1, + /// FIFO not empty + FNE: u1, + padding: u29, + }), + /// raw interrupt status register + RIS: mmio.Mmio(packed struct(u32) { + /// Capture complete raw interrupt status + FRAME_RIS: u1, + /// Overrun raw interrupt status + OVR_RIS: u1, + /// Synchronization error raw interrupt status + ERR_RIS: u1, + /// VSYNC raw interrupt status + VSYNC_RIS: u1, + /// Line raw interrupt status + LINE_RIS: u1, + padding: u27, + }), + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// Capture complete interrupt enable + FRAME_IE: u1, + /// Overrun interrupt enable + OVR_IE: u1, + /// Synchronization error interrupt enable + ERR_IE: u1, + /// VSYNC interrupt enable + VSYNC_IE: u1, + /// Line interrupt enable + LINE_IE: u1, + padding: u27, + }), + /// masked interrupt status register + MIS: mmio.Mmio(packed struct(u32) { + /// Capture complete masked interrupt status + FRAME_MIS: u1, + /// Overrun masked interrupt status + OVR_MIS: u1, + /// Synchronization error masked interrupt status + ERR_MIS: u1, + /// VSYNC masked interrupt status + VSYNC_MIS: u1, + /// Line masked interrupt status + LINE_MIS: u1, + padding: u27, + }), + /// interrupt clear register + ICR: mmio.Mmio(packed struct(u32) { + /// Capture complete interrupt status clear + FRAME_ISC: u1, + /// Overrun interrupt status clear + OVR_ISC: u1, + /// Synchronization error interrupt status clear + ERR_ISC: u1, + /// Vertical synch interrupt status clear + VSYNC_ISC: u1, + /// line interrupt status clear + LINE_ISC: u1, + padding: u27, + }), + /// embedded synchronization code register + ESCR: mmio.Mmio(packed struct(u32) { + /// Frame start delimiter code + FSC: u8, + /// Line start delimiter code + LSC: u8, + /// Line end delimiter code + LEC: u8, + /// Frame end delimiter code + FEC: u8, + }), + /// embedded synchronization unmask register + ESUR: mmio.Mmio(packed struct(u32) { + /// Frame start delimiter unmask + FSU: u8, + /// Line start delimiter unmask + LSU: u8, + /// Line end delimiter unmask + LEU: u8, + /// Frame end delimiter unmask + FEU: u8, + }), + /// crop window start + CWSTRT: mmio.Mmio(packed struct(u32) { + /// Horizontal offset count + HOFFCNT: u14, + reserved16: u2, + /// Vertical start line count + VST: u13, + padding: u3, + }), + /// crop window size + CWSIZE: mmio.Mmio(packed struct(u32) { + /// Capture count + CAPCNT: u14, + reserved16: u2, + /// Vertical line count + VLINE: u14, + padding: u2, + }), + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Data byte 0 + Byte0: u8, + /// Data byte 1 + Byte1: u8, + /// Data byte 2 + Byte2: u8, + /// Data byte 3 + Byte3: u8, + }), + }; + }; + + pub const dma2d_v1 = struct { + pub const ABORT = enum(u1) { + /// Transfer abort requested + AbortRequest = 0x1, _, }; - pub const LPR = enum(u1) { - /// Voltage regulator in Main mode - MainMode = 0x0, - /// Voltage regulator in low-power mode - LowPowerMode = 0x1, + pub const BGPFCCR_AM = enum(u2) { + /// No modification of alpha channel + NoModify = 0x0, + /// Replace with value in ALPHA[7:0] + Replace = 0x1, + /// Multiply with value in ALPHA[7:0] + Multiply = 0x2, + _, }; - pub const PLS = enum(u3) { - /// 2.0V - V2_0 = 0x0, - /// 2.2V - V2_2 = 0x1, - /// 2.4V - V2_4 = 0x2, - /// 2.5V - V2_5 = 0x3, - /// 2.6V - V2_6 = 0x4, - /// 2.8V - V2_8 = 0x5, - /// 2.9V - V2_9 = 0x6, - /// External input analog voltage PVD_IN (compared internally to VREFINT) - External = 0x7, + pub const BGPFCCR_CCM = enum(u1) { + /// CLUT color format ARGB8888 + ARGB8888 = 0x0, + /// CLUT color format RGB888 + RGB888 = 0x1, }; - pub const RRS = enum(u2) { - /// SRAM2 powered off in Standby mode (SRAM2 content lost) - PowerOff = 0x0, - /// SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) - OnLPR = 0x1, - /// Only the upper 4 Kbytes of SRAM2 are powered by the low-power regulator in Standby mode (upper 4 Kbytes of SRAM2 content 0x2003 F000 - 0x2003 FFFF is kept). - OnLPRTop4kb = 0x2, + pub const BGPFCCR_CM = enum(u4) { + /// Color mode ARGB8888 + ARGB8888 = 0x0, + /// Color mode RGB888 + RGB888 = 0x1, + /// Color mode RGB565 + RGB565 = 0x2, + /// Color mode ARGB1555 + ARGB1555 = 0x3, + /// Color mode ARGB4444 + ARGB4444 = 0x4, + /// Color mode L8 + L8 = 0x5, + /// Color mode AL44 + AL44 = 0x6, + /// Color mode AL88 + AL88 = 0x7, + /// Color mode L4 + L4 = 0x8, + /// Color mode A8 + A8 = 0x9, + /// Color mode A4 + A4 = 0xa, _, }; - pub const VOS = enum(u2) { - /// Range 0 - Range0 = 0x0, - /// Range 1 - Range1 = 0x1, - /// Range 2 - Range2 = 0x2, + pub const BGPFCCR_START = enum(u1) { + /// Start the automatic loading of the CLUT + Start = 0x1, _, }; - /// Power control - pub const PWR = extern struct { - /// Power control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection - LPMS: packed union { - raw: u3, - value: LPMS, + pub const CAECIF = enum(u1) { + /// Clear the CAEIF flag in the ISR register + Clear = 0x1, + _, + }; + + pub const CCEIF = enum(u1) { + /// Clear the CEIF flag in the ISR register + Clear = 0x1, + _, + }; + + pub const CCTCIF = enum(u1) { + /// Clear the CTCIF flag in the ISR register + Clear = 0x1, + _, + }; + + pub const CR_START = enum(u1) { + /// Launch the DMA2D + Start = 0x1, + _, + }; + + pub const CTCIF = enum(u1) { + /// Clear the TCIF flag in the ISR register + Clear = 0x1, + _, + }; + + pub const CTEIF = enum(u1) { + /// Clear the TEIF flag in the ISR register + Clear = 0x1, + _, + }; + + pub const CTWIF = enum(u1) { + /// Clear the TWIF flag in the ISR register + Clear = 0x1, + _, + }; + + pub const FGPFCCR_AM = enum(u2) { + /// No modification of alpha channel + NoModify = 0x0, + /// Replace with value in ALPHA[7:0] + Replace = 0x1, + /// Multiply with value in ALPHA[7:0] + Multiply = 0x2, + _, + }; + + pub const FGPFCCR_CCM = enum(u1) { + /// CLUT color format ARGB8888 + ARGB8888 = 0x0, + /// CLUT color format RGB888 + RGB888 = 0x1, + }; + + pub const FGPFCCR_CM = enum(u4) { + /// Color mode ARGB8888 + ARGB8888 = 0x0, + /// Color mode RGB888 + RGB888 = 0x1, + /// Color mode RGB565 + RGB565 = 0x2, + /// Color mode ARGB1555 + ARGB1555 = 0x3, + /// Color mode ARGB4444 + ARGB4444 = 0x4, + /// Color mode L8 + L8 = 0x5, + /// Color mode AL44 + AL44 = 0x6, + /// Color mode AL88 + AL88 = 0x7, + /// Color mode L4 + L4 = 0x8, + /// Color mode A8 + A8 = 0x9, + /// Color mode A4 + A4 = 0xa, + _, + }; + + pub const FGPFCCR_START = enum(u1) { + /// Start the automatic loading of the CLUT + Start = 0x1, + _, + }; + + pub const MODE = enum(u2) { + /// Memory-to-memory (FG fetch only) + MemoryToMemory = 0x0, + /// Memory-to-memory with PFC (FG fetch only with FG PFC active) + MemoryToMemoryPFC = 0x1, + /// Memory-to-memory with blending (FG and BG fetch with PFC and blending) + MemoryToMemoryPFCBlending = 0x2, + /// Register-to-memory + RegisterToMemory = 0x3, + }; + + pub const OPFCCR_CM = enum(u3) { + /// ARGB8888 + ARGB8888 = 0x0, + /// RGB888 + RGB888 = 0x1, + /// RGB565 + RGB565 = 0x2, + /// ARGB1555 + ARGB1555 = 0x3, + /// ARGB4444 + ARGB4444 = 0x4, + _, + }; + + /// DMA2D controller + pub const DMA2D = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// Start + START: packed union { + raw: u1, + value: CR_START, + }, + /// Suspend + SUSP: u1, + /// Abort + ABORT: packed union { + raw: u1, + value: ABORT, }, reserved8: u5, - /// Disable backup domain write protection - DBP: u1, - /// Voltage scaling range selection - VOS: packed union { + /// Transfer error interrupt enable + TEIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Transfer watermark interrupt enable + TWIE: u1, + /// CLUT access error interrupt enable + CAEIE: u1, + /// CLUT transfer complete interrupt enable + CTCIE: u1, + /// Configuration Error Interrupt Enable + CEIE: u1, + reserved16: u2, + /// DMA2D mode + MODE: packed union { raw: u2, - value: VOS, + value: MODE, }, - reserved14: u3, - /// Low-power run - LPR: packed union { + padding: u14, + }), + /// Interrupt Status Register + ISR: mmio.Mmio(packed struct(u32) { + /// Transfer error interrupt flag + TEIF: u1, + /// Transfer complete interrupt flag + TCIF: u1, + /// Transfer watermark interrupt flag + TWIF: u1, + /// CLUT access error interrupt flag + CAEIF: u1, + /// CLUT transfer complete interrupt flag + CTCIF: u1, + /// Configuration error interrupt flag + CEIF: u1, + padding: u26, + }), + /// interrupt flag clear register + IFCR: mmio.Mmio(packed struct(u32) { + /// Clear Transfer error interrupt flag + CTEIF: packed union { raw: u1, - value: LPR, + value: CTEIF, }, - padding: u17, - }), - /// Power control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Power voltage detector enable - PVDE: u1, - /// Power voltage detector level selection - PLS: packed union { - raw: u3, - value: PLS, + /// Clear transfer complete interrupt flag + CTCIF: packed union { + raw: u1, + value: CTCIF, }, - /// Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V - PVME1: u1, - /// Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V - PVME2: u1, - /// Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V - PVME3: u1, - /// Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V - PVME4: u1, - reserved9: u1, - /// VDDIO2 Independent I/Os supply valid - IOSV: u1, - /// VDDUSB USB supply valid - USV: u1, - padding: u21, - }), - /// Power control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin WKUP - EWUP: u1, - reserved8: u7, - /// SRAM2 retention in Standby mode - RRS: packed union { - raw: u2, - value: RRS, + /// Clear transfer watermark interrupt flag + CTWIF: packed union { + raw: u1, + value: CTWIF, }, - /// Apply pull-up and pull-down configuration - APC: u1, - /// ULPMEN - ULPMEN: u1, - reserved13: u1, - /// UCPD_STDBY - UCPD_STDBY: u1, - /// UCPD_DBDIS - UCPD_DBDIS: u1, - padding: u17, - }), - /// Power control register 4 - CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity - WP1: u1, - /// Wakeup pin WKUP2 polarity - WP2: u1, - /// Wakeup pin WKUP3 polarity - WP3: u1, - /// Wakeup pin WKUP4 polarity - WP4: u1, - /// Wakeup pin WKUP5 polarity - WP5: u1, - reserved8: u3, - /// VBAT battery charging enable - VBE: u1, - /// VBAT battery charging resistor selection - VBRS: u1, - reserved12: u2, - /// SMPSBYP - SMPSBYP: u1, - /// EXTSMPSEN - EXTSMPSEN: u1, - /// SMPSFSTEN - SMPSFSTEN: u1, - /// SMPSLPEN - SMPSLPEN: u1, - padding: u16, - }), - /// Power status register 1 - SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag 1 - CWUF1: u1, - /// Wakeup flag 2 - CWUF2: u1, - /// Wakeup flag 3 - CWUF3: u1, - /// Wakeup flag 4 - CWUF4: u1, - /// Wakeup flag 5 - CWUF5: u1, - reserved8: u3, - /// Standby flag - CSBF: u1, - reserved15: u6, - /// Wakeup flag internal - WUFI: u1, - padding: u16, - }), - /// Power status register 2 - SR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Low-power regulator started - REGLPS: u1, - /// Low-power regulator flag - REGLPF: u1, - /// Voltage scaling flag - VOSF: u1, - /// Power voltage detector output - PVDO: u1, - /// Peripheral voltage monitoring output: VDDUSB vs. 1.2 V - PVMO1: u1, - /// Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V - PVMO2: u1, - /// Peripheral voltage monitoring output: VDDA vs. 1.62 V - PVMO3: u1, - /// Peripheral voltage monitoring output: VDDA vs. 2.2 V - PVMO4: u1, - padding: u16, - }), - /// Power status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag - CWUF: u1, - reserved8: u7, - /// Clear standby flag - SBF: u1, - padding: u23, + /// Clear CLUT access error interrupt flag + CAECIF: packed union { + raw: u1, + value: CAECIF, + }, + /// Clear CLUT transfer complete interrupt flag + CCTCIF: packed union { + raw: u1, + value: CCTCIF, + }, + /// Clear configuration error interrupt flag + CCEIF: packed union { + raw: u1, + value: CCEIF, + }, + padding: u26, }), - reserved32: [4]u8, - /// Power Port A pull-up control register - PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// foreground memory address register + FGMAR: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, }), - /// Power Port A pull-down control register - PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// foreground offset register + FGOR: mmio.Mmio(packed struct(u32) { + /// Line offset + LO: u14, + padding: u18, }), - reserved120: [80]u8, - /// Power secure configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// WKUP1 pin security - WUP1SEC: u1, - /// WKUP2 pin security - WUP2SEC: u1, - /// WKUP3 pin security - WUP3SEC: u1, - /// WKUP4 pin security - WUP4SEC: u1, - /// WKUP5 pin security - WUP5SEC: u1, - reserved8: u3, - /// LPMSEC - LPMSEC: u1, - /// VDMSEC - VDMSEC: u1, - /// VBSEC - VBSEC: u1, - /// APCSEC - APCSEC: u1, - padding: u20, + /// background memory address register + BGMAR: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, }), - reserved128: [4]u8, - /// Power privilege configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// PRIV - PRIV: u1, - padding: u31, + /// background offset register + BGOR: mmio.Mmio(packed struct(u32) { + /// Line offset + LO: u14, + padding: u18, }), - }; - }; - - pub const fdcanram_v1 = struct { - /// FDCAN Message RAM - pub const FDCANRAM = extern struct { - /// 11-bit filter - FLSSA: [28]u32, - /// 29-bit filter - FLESA: [16]u32, - /// Rx FIFO 0 - RXFIFO0: [54]u32, - /// Rx FIFO 1 - RXFIFO1: [54]u32, - /// Tx event FIFO - TXEFIFO: [6]u32, - /// Tx buffer - TXBUF: [54]u32, - }; - }; - - pub const usb_v1 = struct { - pub const DIR = enum(u1) { - /// data transmitted by the USB peripheral to the host PC - To = 0x0, - /// data received by the USB peripheral from the host PC - From = 0x1, - }; - - pub const EP_TYPE = enum(u2) { - /// Bulk endpoint - Bulk = 0x0, - /// Control endpoint - Control = 0x1, - /// Iso endpoint - Iso = 0x2, - /// Interrupt endpoint - Interrupt = 0x3, - }; - - pub const STAT = enum(u2) { - /// all requests addressed to this endpoint are ignored - Disabled = 0x0, - /// the endpoint is stalled and all requests result in a STALL handshake - Stall = 0x1, - /// the endpoint is naked and all requests result in a NAK handshake - Nak = 0x2, - /// this endpoint is enabled, requests are ACKed - Valid = 0x3, - }; - - /// Universal serial bus full-speed device interface - pub const USB = extern struct { - /// endpoint register - EPR: [8]mmio.Mmio(packed struct(u32) { - /// EA - EA: u4, - /// STAT_TX - STAT_TX: packed union { - raw: u2, - value: STAT, + /// foreground PFC control register + FGPFCCR: mmio.Mmio(packed struct(u32) { + /// Color mode + CM: packed union { + raw: u4, + value: FGPFCCR_CM, }, - /// DTOG_TX - DTOG_TX: u1, - /// CTR_TX - CTR_TX: u1, - /// EP_KIND - EP_KIND: u1, - /// EPTYPE - EP_TYPE: packed union { - raw: u2, - value: EP_TYPE, + /// CLUT color mode + CCM: packed union { + raw: u1, + value: FGPFCCR_CCM, }, - /// SETUP - SETUP: u1, - /// STAT_RX - STAT_RX: packed union { + /// Start + START: packed union { + raw: u1, + value: FGPFCCR_START, + }, + reserved8: u2, + /// CLUT size + CS: u8, + /// Alpha mode + AM: packed union { raw: u2, - value: STAT, + value: FGPFCCR_AM, }, - /// DTOG_RX - DTOG_RX: u1, - /// CTR_RX - CTR_RX: u1, - padding: u16, + reserved24: u6, + /// Alpha value + ALPHA: u8, }), - reserved64: [32]u8, - /// control register - CNTR: mmio.Mmio(packed struct(u32) { - /// Force a reset of the USB peripheral, exactly like a RESET signaling on the USB - FRES: u1, - /// Enter power down mode - PDWN: u1, - /// Enter low-power mode - LPMODE: u1, - /// Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected - FSUSP: u1, - /// Resume request - RESUME: u1, - reserved8: u3, - /// ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - ESOFM: u1, - /// SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - SOFM: u1, - /// RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - RESETM: u1, - /// SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - SUSPM: u1, - /// WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - WKUPM: u1, - /// ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - ERRM: u1, - /// PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - PMAOVRM: u1, - /// CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - CTRM: u1, - padding: u16, + /// foreground color register + FGCOLR: mmio.Mmio(packed struct(u32) { + /// Blue Value + BLUE: u8, + /// Green Value + GREEN: u8, + /// Red Value + RED: u8, + padding: u8, }), - /// interrupt status register - ISTR: mmio.Mmio(packed struct(u32) { - /// EP_ID - EP_ID: u4, - /// DIR - DIR: packed union { + /// background PFC control register + BGPFCCR: mmio.Mmio(packed struct(u32) { + /// Color mode + CM: packed union { + raw: u4, + value: BGPFCCR_CM, + }, + /// CLUT Color mode + CCM: packed union { raw: u1, - value: DIR, + value: BGPFCCR_CCM, }, - reserved8: u3, - /// an SOF packet is expected but not received - ESOF: u1, - /// beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus - SOF: u1, - /// peripheral detects an active USB RESET signal at its inputs - RESET: u1, - /// no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus - SUSP: u1, - /// activity is detected that wakes up the USB peripheral - WKUP: u1, - /// One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred - ERR: u1, - /// microcontroller has not been able to respond in time to an USB memory request - PMAOVR: u1, - /// endpoint has successfully completed a transaction - CTR: u1, - padding: u16, - }), - /// frame number register - FNR: mmio.Mmio(packed struct(u32) { - /// FN - FN: u11, - /// LSOF - LSOF: u2, - /// the frame timer remains in this state until an USB reset or USB suspend event occurs - LCK: u1, - /// received data minus upstream port data line - RXDM: u1, - /// received data plus upstream port data line - RXDP: u1, - padding: u16, - }), - /// device address - DADDR: mmio.Mmio(packed struct(u32) { - /// device address - ADD: u7, - /// USB device enabled - EF: u1, - padding: u24, + /// Start + START: packed union { + raw: u1, + value: BGPFCCR_START, + }, + reserved8: u2, + /// CLUT size + CS: u8, + /// Alpha mode + AM: packed union { + raw: u2, + value: BGPFCCR_AM, + }, + reserved24: u6, + /// Alpha value + ALPHA: u8, }), - /// Buffer table address - BTABLE: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// BTABLE - BTABLE: u13, - padding: u16, + /// background color register + BGCOLR: mmio.Mmio(packed struct(u32) { + /// Blue Value + BLUE: u8, + /// Green Value + GREEN: u8, + /// Red Value + RED: u8, + padding: u8, }), - }; - }; - - pub const exti_h5 = struct { - /// Extended interrupt and event controller - pub const EXTI = extern struct { - /// rising trigger selection register - RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// foreground CLUT memory address register + FGCMAR: mmio.Mmio(packed struct(u32) { + /// Memory Address + MA: u32, }), - /// falling trigger selection register - FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// background CLUT memory address register + BGCMAR: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, }), - /// software interrupt event register - SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// output PFC control register + OPFCCR: mmio.Mmio(packed struct(u32) { + /// Color mode + CM: packed union { + raw: u3, + value: OPFCCR_CM, + }, + padding: u29, }), - /// rising edge pending register - RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// output color register + OCOLR: mmio.Mmio(packed struct(u32) { + /// Blue Value + BLUE: u8, + /// Green Value + GREEN: u8, + /// Red Value + RED: u8, + /// Alpha Channel Value + APLHA: u8, }), - /// falling edge pending register - FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// output memory address register + OMAR: mmio.Mmio(packed struct(u32) { + /// Memory Address + MA: u32, }), - /// security configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. - SEC: u1, - padding: u31, + /// output offset register + OOR: mmio.Mmio(packed struct(u32) { + /// Line Offset + LO: u14, + padding: u18, }), - /// privilege configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. - PRIV: u1, - padding: u31, + /// number of line register + NLR: mmio.Mmio(packed struct(u32) { + /// Number of lines + NL: u16, + /// Pixel per lines + PL: u14, + padding: u2, }), - reserved96: [68]u8, - /// external interrupt selection register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved - EXTI: u8, - padding: u24, + /// line watermark register + LWR: mmio.Mmio(packed struct(u32) { + /// Line watermark + LW: u16, + padding: u16, }), - /// lock register - LOCKR: mmio.Mmio(packed struct(u32) { - /// Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock This bit is written once after reset. - LOCK: u1, - padding: u31, + /// AHB master timer configuration register + AMTCR: mmio.Mmio(packed struct(u32) { + /// Enable + EN: u1, + reserved8: u7, + /// Dead Time + DT: u8, + padding: u16, }), - reserved128: [12]u8, - /// CPU wakeup with interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + reserved1024: [944]u8, + /// FGCLUT + FGCLUT: mmio.Mmio(packed struct(u32) { + /// BLUE + BLUE: u8, + /// GREEN + GREEN: u8, + /// RED + RED: u8, + /// APLHA + APLHA: u8, }), - /// CPU wakeup with event mask register - EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + reserved2048: [1020]u8, + /// BGCLUT + BGCLUT: mmio.Mmio(packed struct(u32) { + /// BLUE + BLUE: u8, + /// GREEN + GREEN: u8, + /// RED + RED: u8, + /// APLHA + APLHA: u8, }), }; }; - pub const syscfg_g0 = struct { - pub const MEM_MODE = enum(u2) { - /// Main Flash memory mapped at address 0 - MAIN_FLASH = 0x0, - /// System Flash memory mapped at address 0 - SYSTEM_FLASH = 0x1, - /// Main Flash memory mapped at address 0 (alternate encoding) - MAIN_FLASH_ALT = 0x2, - /// Embedded SRAM mapped at address 0 - SRAM = 0x3, + pub const dma2d_v2 = struct { + pub const ABORT = enum(u1) { + /// Transfer abort requested + AbortRequest = 0x1, + _, }; - /// System configuration controller - pub const SYSCFG = extern struct { - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details. - MEM_MODE: packed union { - raw: u2, - value: MEM_MODE, + pub const BGPFCCR_AI = enum(u1) { + /// Regular alpha + RegularAlpha = 0x0, + /// Inverted alpha + InvertedAlpha = 0x1, + }; + + pub const BGPFCCR_AM = enum(u2) { + /// No modification of alpha channel + NoModify = 0x0, + /// Replace with value in ALPHA[7:0] + Replace = 0x1, + /// Multiply with value in ALPHA[7:0] + Multiply = 0x2, + _, + }; + + pub const BGPFCCR_CCM = enum(u1) { + /// CLUT color format ARGB8888 + ARGB8888 = 0x0, + /// CLUT color format RGB888 + RGB888 = 0x1, + }; + + pub const BGPFCCR_CM = enum(u4) { + /// Color mode ARGB8888 + ARGB8888 = 0x0, + /// Color mode RGB888 + RGB888 = 0x1, + /// Color mode RGB565 + RGB565 = 0x2, + /// Color mode ARGB1555 + ARGB1555 = 0x3, + /// Color mode ARGB4444 + ARGB4444 = 0x4, + /// Color mode L8 + L8 = 0x5, + /// Color mode AL44 + AL44 = 0x6, + /// Color mode AL88 + AL88 = 0x7, + /// Color mode L4 + L4 = 0x8, + /// Color mode A8 + A8 = 0x9, + /// Color mode A4 + A4 = 0xa, + _, + }; + + pub const BGPFCCR_RBS = enum(u1) { + /// No Red Blue Swap (RGB or ARGB) + Regular = 0x0, + /// Red Blue Swap (BGR or ABGR) + Swap = 0x1, + }; + + pub const BGPFCCR_START = enum(u1) { + /// Start the automatic loading of the CLUT + Start = 0x1, + _, + }; + + pub const CAECIF = enum(u1) { + /// Clear the CAEIF flag in the ISR register + Clear = 0x1, + _, + }; + + pub const CCEIF = enum(u1) { + /// Clear the CEIF flag in the ISR register + Clear = 0x1, + _, + }; + + pub const CCTCIF = enum(u1) { + /// Clear the CTCIF flag in the ISR register + Clear = 0x1, + _, + }; + + pub const CR_START = enum(u1) { + /// Launch the DMA2D + Start = 0x1, + _, + }; + + pub const CTCIF = enum(u1) { + /// Clear the TCIF flag in the ISR register + Clear = 0x1, + _, + }; + + pub const CTEIF = enum(u1) { + /// Clear the TEIF flag in the ISR register + Clear = 0x1, + _, + }; + + pub const CTWIF = enum(u1) { + /// Clear the TWIF flag in the ISR register + Clear = 0x1, + _, + }; + + pub const FGPFCCR_AI = enum(u1) { + /// Regular alpha + RegularAlpha = 0x0, + /// Inverted alpha + InvertedAlpha = 0x1, + }; + + pub const FGPFCCR_AM = enum(u2) { + /// No modification of alpha channel + NoModify = 0x0, + /// Replace with value in ALPHA[7:0] + Replace = 0x1, + /// Multiply with value in ALPHA[7:0] + Multiply = 0x2, + _, + }; + + pub const FGPFCCR_CCM = enum(u1) { + /// CLUT color format ARGB8888 + ARGB8888 = 0x0, + /// CLUT color format RGB888 + RGB888 = 0x1, + }; + + pub const FGPFCCR_CM = enum(u4) { + /// Color mode ARGB8888 + ARGB8888 = 0x0, + /// Color mode RGB888 + RGB888 = 0x1, + /// Color mode RGB565 + RGB565 = 0x2, + /// Color mode ARGB1555 + ARGB1555 = 0x3, + /// Color mode ARGB4444 + ARGB4444 = 0x4, + /// Color mode L8 + L8 = 0x5, + /// Color mode AL44 + AL44 = 0x6, + /// Color mode AL88 + AL88 = 0x7, + /// Color mode L4 + L4 = 0x8, + /// Color mode A8 + A8 = 0x9, + /// Color mode A4 + A4 = 0xa, + /// Color mode YCbCr + YCbCr = 0xb, + _, + }; + + pub const FGPFCCR_RBS = enum(u1) { + /// No Red Blue Swap (RGB or ARGB) + Regular = 0x0, + /// Red Blue Swap (BGR or ABGR) + Swap = 0x1, + }; + + pub const FGPFCCR_START = enum(u1) { + /// Start the automatic loading of the CLUT + Start = 0x1, + _, + }; + + pub const MODE = enum(u2) { + /// Memory-to-memory (FG fetch only) + MemoryToMemory = 0x0, + /// Memory-to-memory with PFC (FG fetch only with FG PFC active) + MemoryToMemoryPFC = 0x1, + /// Memory-to-memory with blending (FG and BG fetch with PFC and blending) + MemoryToMemoryPFCBlending = 0x2, + /// Register-to-memory + RegisterToMemory = 0x3, + }; + + pub const OPFCCR_AI = enum(u1) { + /// Regular alpha + RegularAlpha = 0x0, + /// Inverted alpha + InvertedAlpha = 0x1, + }; + + pub const OPFCCR_CM = enum(u3) { + /// ARGB8888 + ARGB8888 = 0x0, + /// RGB888 + RGB888 = 0x1, + /// RGB565 + RGB565 = 0x2, + /// ARGB1555 + ARGB1555 = 0x3, + /// ARGB4444 + ARGB4444 = 0x4, + _, + }; + + pub const OPFCCR_RBS = enum(u1) { + /// No Red Blue Swap (RGB or ARGB) + Regular = 0x0, + /// Red Blue Swap (BGR or ABGR) + Swap = 0x1, + }; + + pub const SB = enum(u1) { + /// Regular byte order + Regular = 0x0, + /// Bytes are swapped two by two + SwapBytes = 0x1, + }; + + /// DMA2D + pub const DMA2D = extern struct { + /// DMA2D control register + CR: mmio.Mmio(packed struct(u32) { + /// Start This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers + START: packed union { + raw: u1, + value: CR_START, }, - reserved3: u1, - /// PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. - PA11_RMP: u1, - /// PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. - PA12_RMP: u1, - /// IR output polarity selection - IR_POL: u1, - /// IR Modulation Envelope signal selection. - IR_MOD: u2, - /// I/O analog switch voltage booster enable - BOOSTEN: u1, - /// Strobe signal bit for UCPD1 - UCPD1_STROBE: u1, - /// Strobe signal bit for UCPD2 - UCPD2_STROBE: u1, - reserved16: u5, - /// Fast Mode Plus (FM+) driving capability activation bits - I2C_PBx_FMP: u4, - /// FM+ driving capability activation for I2C1 - I2C1_FMP: u1, - /// FM+ driving capability activation for I2C2 - I2C2_FMP: u1, - /// Fast Mode Plus (FM+) driving capability activation bits - I2C_PAx_FMP: u2, - padding: u8, - }), - reserved24: [20]u8, - /// configuration register 1 - CFGR2: mmio.Mmio(packed struct(u32) { - /// Cortex-M0+ LOCKUP bit enable bit - LOCKUP_LOCK: u1, - /// SRAM parity lock bit - SRAM_PARITY_LOCK: u1, - /// PVD lock enable bit - PVD_LOCK: u1, - /// ECC error lock bit - ECC_LOCK: u1, - reserved8: u4, - /// SRAM parity error flag - SRAM_PEF: u1, - reserved16: u7, - /// PA1_CDEN - PA1_CDEN: u1, - /// PA3_CDEN - PA3_CDEN: u1, - /// PA5_CDEN - PA5_CDEN: u1, - /// PA6_CDEN - PA6_CDEN: u1, - /// PA13_CDEN - PA13_CDEN: u1, - /// PB0_CDEN - PB0_CDEN: u1, - /// PB1_CDEN - PB1_CDEN: u1, - /// PB2_CDEN - PB2_CDEN: u1, - padding: u8, - }), - reserved48: [20]u8, - /// VREFBUF control and status register - VREFBUF_CSR: mmio.Mmio(packed struct(u32) { - /// Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. - ENVR: u1, - /// High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration. - HIZ: u1, - reserved3: u1, - /// Voltage reference buffer ready - VRR: u1, - /// Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved - VRS: u3, - padding: u25, + /// Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset. + SUSP: u1, + /// Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset. + ABORT: packed union { + raw: u1, + value: ABORT, + }, + reserved8: u5, + /// Transfer error interrupt enable This bit is set and cleared by software. + TEIE: u1, + /// Transfer complete interrupt enable This bit is set and cleared by software. + TCIE: u1, + /// Transfer watermark interrupt enable This bit is set and cleared by software. + TWIE: u1, + /// CLUT access error interrupt enable This bit is set and cleared by software. + CAEIE: u1, + /// CLUT transfer complete interrupt enable This bit is set and cleared by software. + CTCIE: u1, + /// Configuration Error Interrupt Enable This bit is set and cleared by software. + CEIE: u1, + reserved16: u2, + /// DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing. + MODE: packed union { + raw: u2, + value: MODE, + }, + padding: u14, }), - /// VREFBUF calibration control register - VREFBUF_CCR: mmio.Mmio(packed struct(u32) { - /// Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage. - TRIM: u6, + /// DMA2D Interrupt Status Register + ISR: mmio.Mmio(packed struct(u32) { + /// Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading). + TEIF: u1, + /// Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only). + TCIF: u1, + /// Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred. + TWIF: u1, + /// CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D. + CAEIF: u1, + /// CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete. + CTCIF: u1, + /// Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed. + CEIF: u1, padding: u26, }), - reserved128: [72]u8, - /// interrupt line 0 status register - ITLINE0: mmio.Mmio(packed struct(u32) { - /// Window watchdog interrupt pending flag - WWDG: u1, - padding: u31, - }), - /// interrupt line 1 status register - ITLINE1: mmio.Mmio(packed struct(u32) { - /// PVD supply monitoring interrupt request pending (EXTI line 16). - PVDOUT: u1, - padding: u31, - }), - /// interrupt line 2 status register - ITLINE2: mmio.Mmio(packed struct(u32) { - /// TAMP - TAMP: u1, - /// RTC - RTC: u1, - padding: u30, - }), - /// interrupt line 3 status register - ITLINE3: mmio.Mmio(packed struct(u32) { - /// FLASH_ITF - FLASH_ITF: u1, - /// FLASH_ECC - FLASH_ECC: u1, - padding: u30, - }), - /// interrupt line 4 status register - ITLINE4: mmio.Mmio(packed struct(u32) { - /// RCC - RCC: u1, - padding: u31, - }), - /// interrupt line 5 status register - ITLINE5: mmio.Mmio(packed struct(u32) { - /// EXTI0 - EXTI0: u1, - /// EXTI1 - EXTI1: u1, - padding: u30, - }), - /// interrupt line 6 status register - ITLINE6: mmio.Mmio(packed struct(u32) { - /// EXTI2 - EXTI2: u1, - /// EXTI3 - EXTI3: u1, - padding: u30, - }), - /// interrupt line 7 status register - ITLINE7: mmio.Mmio(packed struct(u32) { - /// EXTI4 - EXTI4: u1, - /// EXTI5 - EXTI5: u1, - /// EXTI6 - EXTI6: u1, - /// EXTI7 - EXTI7: u1, - /// EXTI8 - EXTI8: u1, - /// EXTI9 - EXTI9: u1, - /// EXTI10 - EXTI10: u1, - /// EXTI11 - EXTI11: u1, - /// EXTI12 - EXTI12: u1, - /// EXTI13 - EXTI13: u1, - /// EXTI14 - EXTI14: u1, - /// EXTI15 - EXTI15: u1, - padding: u20, - }), - /// interrupt line 8 status register - ITLINE8: mmio.Mmio(packed struct(u32) { - /// UCPD1 - UCPD1: u1, - /// UCPD2 - UCPD2: u1, - /// USB - USB: u1, - padding: u29, - }), - /// interrupt line 9 status register - ITLINE9: mmio.Mmio(packed struct(u32) { - /// DMA1_CH1 - DMA1_CH1: u1, - padding: u31, - }), - /// interrupt line 10 status register - ITLINE10: mmio.Mmio(packed struct(u32) { - /// DMA1_CH1 - DMA1_CH2: u1, - /// DMA1_CH3 - DMA1_CH3: u1, - padding: u30, - }), - /// interrupt line 11 status register - ITLINE11: mmio.Mmio(packed struct(u32) { - /// DMAMUX - DMAMUX: u1, - /// DMA1_CH4 - DMA1_CH4: u1, - /// DMA1_CH5 - DMA1_CH5: u1, - /// DMA1_CH6 - DMA1_CH6: u1, - /// DMA1_CH7 - DMA1_CH7: u1, - padding: u27, - }), - /// interrupt line 12 status register - ITLINE12: mmio.Mmio(packed struct(u32) { - /// ADC - ADC: u1, - /// COMP1 - COMP1: u1, - /// COMP2 - COMP2: u1, - padding: u29, + /// DMA2D interrupt flag clear register + IFCR: mmio.Mmio(packed struct(u32) { + /// Clear Transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register + CTEIF: packed union { + raw: u1, + value: CTEIF, + }, + /// Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register + CTCIF: packed union { + raw: u1, + value: CTCIF, + }, + /// Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register + CTWIF: packed union { + raw: u1, + value: CTWIF, + }, + /// Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register + CAECIF: packed union { + raw: u1, + value: CAECIF, + }, + /// Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register + CCTCIF: packed union { + raw: u1, + value: CCTCIF, + }, + /// Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register + CCEIF: packed union { + raw: u1, + value: CCEIF, + }, + padding: u26, }), - /// interrupt line 13 status register - ITLINE13: mmio.Mmio(packed struct(u32) { - /// TIM1_CCU - TIM1_CCU: u1, - /// TIM1_TRG - TIM1_TRG: u1, - /// TIM1_UPD - TIM1_UPD: u1, - /// TIM1_BRK - TIM1_BRK: u1, - padding: u28, + /// DMA2D foreground memory address register + FGMAR: mmio.Mmio(packed struct(u32) { + /// Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned. + MA: u32, }), - /// interrupt line 14 status register - ITLINE14: mmio.Mmio(packed struct(u32) { - /// TIM1_CC - TIM1_CC: u1, - padding: u31, + /// DMA2D foreground offset register + FGOR: mmio.Mmio(packed struct(u32) { + /// Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even. + LO: u16, + padding: u16, }), - /// interrupt line 15 status register - ITLINE15: mmio.Mmio(packed struct(u32) { - /// TIM2 - TIM2: u1, - padding: u31, + /// DMA2D background memory address register + BGMAR: mmio.Mmio(packed struct(u32) { + /// Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned. + MA: u32, }), - /// interrupt line 16 status register - ITLINE16: mmio.Mmio(packed struct(u32) { - /// TIM3 - TIM3: u1, - padding: u31, + /// DMA2D background offset register + BGOR: mmio.Mmio(packed struct(u32) { + /// Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even. + LO: u16, + padding: u16, }), - /// interrupt line 17 status register - ITLINE17: mmio.Mmio(packed struct(u32) { - /// TIM6 - TIM6: u1, - /// DAC - DAC: u1, - /// LPTIM1 - LPTIM1: u1, - padding: u29, + /// DMA2D foreground PFC control register + FGPFCCR: mmio.Mmio(packed struct(u32) { + /// Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless + CM: packed union { + raw: u4, + value: FGPFCCR_CM, + }, + /// CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only. + CCM: packed union { + raw: u1, + value: FGPFCCR_CCM, + }, + /// Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer). + START: packed union { + raw: u1, + value: FGPFCCR_START, + }, + reserved8: u2, + /// CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1. + CS: u8, + /// Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless + AM: packed union { + raw: u2, + value: FGPFCCR_AM, + }, + /// Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless + CSS: u2, + /// Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. + AI: packed union { + raw: u1, + value: FGPFCCR_AI, + }, + /// Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. + RBS: packed union { + raw: u1, + value: FGPFCCR_RBS, + }, + reserved24: u2, + /// Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only. + ALPHA: u8, }), - /// interrupt line 18 status register - ITLINE18: mmio.Mmio(packed struct(u32) { - /// TIM7 - TIM7: u1, - /// LPTIM2 - LPTIM2: u1, - padding: u30, + /// DMA2D foreground color register + FGCOLR: mmio.Mmio(packed struct(u32) { + /// Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only. + BLUE: u8, + /// Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only. + GREEN: u8, + /// Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. + RED: u8, + padding: u8, }), - /// interrupt line 19 status register - ITLINE19: mmio.Mmio(packed struct(u32) { - /// TIM14 - TIM14: u1, - padding: u31, + /// DMA2D background PFC control register + BGPFCCR: mmio.Mmio(packed struct(u32) { + /// Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless + CM: packed union { + raw: u4, + value: BGPFCCR_CM, + }, + /// CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only. + CCM: packed union { + raw: u1, + value: BGPFCCR_CCM, + }, + /// Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer). + START: packed union { + raw: u1, + value: BGPFCCR_START, + }, + reserved8: u2, + /// CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1. + CS: u8, + /// Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless + AM: packed union { + raw: u2, + value: BGPFCCR_AM, + }, + reserved20: u2, + /// Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. + AI: packed union { + raw: u1, + value: BGPFCCR_AI, + }, + /// Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. + RBS: packed union { + raw: u1, + value: BGPFCCR_RBS, + }, + reserved24: u2, + /// Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. + ALPHA: u8, }), - /// interrupt line 20 status register - ITLINE20: mmio.Mmio(packed struct(u32) { - /// TIM15 - TIM15: u1, - padding: u31, + /// DMA2D background color register + BGCOLR: mmio.Mmio(packed struct(u32) { + /// Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. + BLUE: u8, + /// Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. + GREEN: u8, + /// Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. + RED: u8, + padding: u8, }), - /// interrupt line 21 status register - ITLINE21: mmio.Mmio(packed struct(u32) { - /// TIM16 - TIM16: u1, - padding: u31, + /// DMA2D foreground CLUT memory address register + FGCMAR: mmio.Mmio(packed struct(u32) { + /// Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned. + MA: u32, }), - /// interrupt line 22 status register - ITLINE22: mmio.Mmio(packed struct(u32) { - /// TIM17 - TIM17: u1, - padding: u31, + /// DMA2D background CLUT memory address register + BGCMAR: mmio.Mmio(packed struct(u32) { + /// Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned. + MA: u32, }), - /// interrupt line 23 status register - ITLINE23: mmio.Mmio(packed struct(u32) { - /// I2C1 - I2C1: u1, - padding: u31, + /// DMA2D output PFC control register + OPFCCR: mmio.Mmio(packed struct(u32) { + /// Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless + CM: packed union { + raw: u3, + value: OPFCCR_CM, + }, + reserved8: u5, + /// Swap Bytes + SB: packed union { + raw: u1, + value: SB, + }, + reserved20: u11, + /// Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. + AI: packed union { + raw: u1, + value: OPFCCR_AI, + }, + /// Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. + RBS: packed union { + raw: u1, + value: OPFCCR_RBS, + }, + padding: u10, }), - /// interrupt line 24 status register - ITLINE24: mmio.Mmio(packed struct(u32) { - /// I2C2 - I2C2: u1, - padding: u31, + /// DMA2D output color register + OCOLR: mmio.Mmio(packed struct(u32) { + /// Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. + BLUE: u8, + /// Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. + GREEN: u8, + /// Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. + RED: u8, + /// Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. + ALPHA: u8, }), - /// interrupt line 25 status register - ITLINE25: mmio.Mmio(packed struct(u32) { - /// SPI1 - SPI1: u1, - padding: u31, + /// DMA2D output memory address register + OMAR: mmio.Mmio(packed struct(u32) { + /// Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned. + MA: u32, }), - /// interrupt line 26 status register - ITLINE26: mmio.Mmio(packed struct(u32) { - /// SPI2 - SPI2: u1, - padding: u31, + /// DMA2D output offset register + OOR: mmio.Mmio(packed struct(u32) { + /// Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. + LO: u16, + padding: u16, }), - /// interrupt line 27 status register - ITLINE27: mmio.Mmio(packed struct(u32) { - /// USART1 - USART1: u1, - padding: u31, + /// DMA2D number of line register + NLR: mmio.Mmio(packed struct(u32) { + /// Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. + NL: u16, + /// Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even. + PL: u14, + padding: u2, }), - /// interrupt line 28 status register - ITLINE28: mmio.Mmio(packed struct(u32) { - /// USART2 - USART2: u1, - padding: u31, + /// DMA2D line watermark register + LWR: mmio.Mmio(packed struct(u32) { + /// Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. + LW: u16, + padding: u16, }), - /// interrupt line 29 status register - ITLINE29: mmio.Mmio(packed struct(u32) { - USART3: u1, - USART4: u1, - reserved3: u1, - USART5: u1, - USART6: u1, - padding: u27, + /// DMA2D AXI master timer configuration register + AMTCR: mmio.Mmio(packed struct(u32) { + /// Enable Enables the dead time functionality. + EN: u1, + reserved8: u7, + /// Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses. + DT: u8, + padding: u16, }), - /// interrupt line 30 status register - ITLINE30: mmio.Mmio(packed struct(u32) { - /// CEC - CEC: u1, - padding: u31, + }; + }; + + pub const dma_v1 = struct { + pub const BURST = enum(u2) { + /// Single transfer + Single = 0x0, + /// Incremental burst of 4 beats + INCR4 = 0x1, + /// Incremental burst of 8 beats + INCR8 = 0x2, + /// Incremental burst of 16 beats + INCR16 = 0x3, + }; + + pub const CT = enum(u1) { + /// The current target memory is Memory 0 + Memory0 = 0x0, + /// The current target memory is Memory 1 + Memory1 = 0x1, + }; + + pub const DIR = enum(u2) { + /// Peripheral-to-memory + PeripheralToMemory = 0x0, + /// Memory-to-peripheral + MemoryToPeripheral = 0x1, + /// Memory-to-memory + MemoryToMemory = 0x2, + _, + }; + + pub const DMDIS = enum(u1) { + /// Direct mode is enabled + Enabled = 0x0, + /// Direct mode is disabled + Disabled = 0x1, + }; + + pub const FS = enum(u3) { + /// 0 < fifo_level < 1/4 + Quarter1 = 0x0, + /// 1/4 <= fifo_level < 1/2 + Quarter2 = 0x1, + /// 1/2 <= fifo_level < 3/4 + Quarter3 = 0x2, + /// 3/4 <= fifo_level < full + Quarter4 = 0x3, + /// FIFO is empty + Empty = 0x4, + /// FIFO is full + Full = 0x5, + _, + }; + + pub const FTH = enum(u2) { + /// 1/4 full FIFO + Quarter = 0x0, + /// 1/2 full FIFO + Half = 0x1, + /// 3/4 full FIFO + ThreeQuarters = 0x2, + /// Full FIFO + Full = 0x3, + }; + + pub const PFCTRL = enum(u1) { + /// The DMA is the flow controller + DMA = 0x0, + /// The peripheral is the flow controller + Peripheral = 0x1, + }; + + pub const PINCOS = enum(u1) { + /// The offset size for the peripheral address calculation is linked to the PSIZE + PSIZE = 0x0, + /// The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) + Fixed4 = 0x1, + }; + + pub const PL = enum(u2) { + /// Low + Low = 0x0, + /// Medium + Medium = 0x1, + /// High + High = 0x2, + /// Very high + VeryHigh = 0x3, + }; + + pub const SIZE = enum(u2) { + /// Byte (8-bit) + Bits8 = 0x0, + /// Half-word (16-bit) + Bits16 = 0x1, + /// Word (32-bit) + Bits32 = 0x2, + _, + }; + + /// DMA controller + pub const DMA = extern struct { + /// low interrupt status register + ISR: [2]mmio.Mmio(packed struct(u32) { + /// Stream x FIFO error interrupt flag (x=3..0) + FEIF: u1, + reserved2: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + DMEIF: u1, + /// Stream x transfer error interrupt flag (x=3..0) + TEIF: u1, + /// Stream x half transfer interrupt flag (x=3..0) + HTIF: u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + TCIF: u1, + padding: u26, }), - /// interrupt line 31 status register - ITLINE31: mmio.Mmio(packed struct(u32) { - /// RNG - RNG: u1, - /// AES - AES: u1, - padding: u30, + /// low interrupt flag clear register + IFCR: [2]mmio.Mmio(packed struct(u32) { + /// Stream x FIFO error interrupt flag (x=3..0) + FEIF: u1, + reserved2: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + DMEIF: u1, + /// Stream x transfer error interrupt flag (x=3..0) + TEIF: u1, + /// Stream x half transfer interrupt flag (x=3..0) + HTIF: u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + TCIF: u1, + padding: u26, }), + /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers + ST: u32, }; - }; - pub const flash_l5 = struct { - /// Flash - pub const FLASH = extern struct { - /// Access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: u4, - reserved13: u9, - /// Flash Power-down mode during Low-power run mode - RUN_PD: u1, - /// Flash Power-down mode during Low-power sleep mode - SLEEP_PD: u1, - /// LVEN - LVEN: u1, + /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers + pub const ST = extern struct { + /// stream x configuration register + CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: packed union { + raw: u1, + value: PFCTRL, + }, + /// Data transfer direction + DIR: packed union { + raw: u2, + value: DIR, + }, + /// Circular mode enabled + CIRC: u1, + /// Peripheral increment mode enabled + PINC: u1, + /// Memory increment mode enabled + MINC: u1, + /// Peripheral data size + PSIZE: packed union { + raw: u2, + value: SIZE, + }, + /// Memory data size + MSIZE: packed union { + raw: u2, + value: SIZE, + }, + /// Peripheral increment offset size + PINCOS: packed union { + raw: u1, + value: PINCOS, + }, + /// Priority level + PL: packed union { + raw: u2, + value: PL, + }, + /// Double buffer mode enabled + DBM: u1, + /// Current target (only in double buffer mode) + CT: packed union { + raw: u1, + value: CT, + }, + /// Enable bufferable transfers + TRBUFF: u1, + /// Peripheral burst transfer configuration + PBURST: packed union { + raw: u2, + value: BURST, + }, + /// Memory burst transfer configuration + MBURST: packed union { + raw: u2, + value: BURST, + }, + padding: u7, + }), + /// stream x number of data register + NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, padding: u16, }), - /// Power down key register - PDKEYR: u32, - /// Flash non-secure key register - NSKEYR: u32, - /// Flash secure key register - SECKEYR: u32, - /// Flash option key register - OPTKEYR: u32, - /// Flash low voltage key register - LVEKEYR: u32, - reserved32: [8]u8, - /// Flash status register - NSSR: mmio.Mmio(packed struct(u32) { - /// NSEOP - NSEOP: u1, - /// NSOPERR - NSOPERR: u1, - reserved3: u1, - /// NSPROGERR - NSPROGERR: u1, - /// NSWRPERR - NSWRPERR: u1, - /// NSPGAERR - NSPGAERR: u1, - /// NSSIZERR - NSSIZERR: u1, - /// NSPGSERR - NSPGSERR: u1, - reserved13: u5, - /// OPTWERR - OPTWERR: u1, - reserved15: u1, - /// OPTVERR - OPTVERR: u1, - /// NSBusy - NSBSY: u1, - padding: u15, - }), - /// Flash status register - SECSR: mmio.Mmio(packed struct(u32) { - /// SECEOP - SECEOP: u1, - /// SECOPERR - SECOPERR: u1, - reserved3: u1, - /// SECPROGERR - SECPROGERR: u1, - /// SECWRPERR - SECWRPERR: u1, - /// SECPGAERR - SECPGAERR: u1, - /// SECSIZERR - SECSIZERR: u1, - /// SECPGSERR - SECPGSERR: u1, - reserved14: u6, - /// Secure read protection error - SECRDERR: u1, - reserved16: u1, - /// SECBusy - SECBSY: u1, - padding: u15, - }), - /// Flash non-secure control register - NSCR: mmio.Mmio(packed struct(u32) { - /// NSPG - NSPG: u1, - /// NSPER - NSPER: u1, - /// NSMER1 - NSMER1: u1, - /// NSPNB - NSPNB: u7, - reserved11: u1, - /// NSBKER - NSBKER: u1, - reserved15: u3, - /// NSMER2 - NSMER2: u1, - /// Options modification start - NSSTRT: u1, - /// Options modification start - OPTSTRT: u1, - reserved24: u6, - /// NSEOPIE - NSEOPIE: u1, - /// NSERRIE - NSERRIE: u1, - reserved27: u1, - /// Force the option byte loading - OBL_LAUNCH: u1, - reserved30: u2, - /// Options Lock - OPTLOCK: u1, - /// NSLOCK - NSLOCK: u1, - }), - /// Flash secure control register - SECCR: mmio.Mmio(packed struct(u32) { - /// SECPG - SECPG: u1, - /// SECPER - SECPER: u1, - /// SECMER1 - SECMER1: u1, - /// SECPNB - SECPNB: u7, - reserved11: u1, - /// SECBKER - SECBKER: u1, - reserved15: u3, - /// SECMER2 - SECMER2: u1, - /// SECSTRT - SECSTRT: u1, - reserved24: u7, - /// SECEOPIE - SECEOPIE: u1, - /// SECERRIE - SECERRIE: u1, - /// SECRDERRIE - SECRDERRIE: u1, - reserved29: u2, - /// SECINV - SECINV: u1, - reserved31: u1, - /// SECLOCK - SECLOCK: u1, - }), - /// Flash ECC register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC fail address - ADDR_ECC: u19, - reserved21: u2, - /// BK_ECC - BK_ECC: u1, - /// SYSF_ECC - SYSF_ECC: u1, - reserved24: u1, - /// ECC correction interrupt enable - ECCIE: u1, - reserved28: u3, - /// ECCC2 - ECCC2: u1, - /// ECCD2 - ECCD2: u1, - /// ECC correction - ECCC: u1, - /// ECC detection - ECCD: u1, - }), - reserved64: [12]u8, - /// Flash option register - OPTR: mmio.Mmio(packed struct(u32) { - /// Read protection level - RDP: u8, - /// BOR reset Level - BOR_LEV: u3, - reserved12: u1, - /// nRST_STOP - nRST_STOP: u1, - /// nRST_STDBY - nRST_STDBY: u1, - /// nRST_SHDW - nRST_SHDW: u1, - reserved16: u1, - /// Independent watchdog selection - IWDG_SW: u1, - /// Independent watchdog counter freeze in Stop mode - IWDG_STOP: u1, - /// Independent watchdog counter freeze in Standby mode - IWDG_STDBY: u1, - /// Window watchdog selection - WWDG_SW: u1, - /// SWAP_BANK - SWAP_BANK: u1, - /// DB256K - DB256K: u1, - /// DBANK - DBANK: u1, - reserved24: u1, - /// SRAM2 parity check enable - SRAM2_PE: u1, - /// SRAM2 Erase when system reset - SRAM2_RST: u1, - /// nSWBOOT0 - nSWBOOT0: u1, - /// nBOOT0 - nBOOT0: u1, - /// PA15_PUPEN - PA15_PUPEN: u1, - reserved31: u2, - /// TZEN - TZEN: u1, - }), - /// Flash non-secure boot address 0 register - NSBOOTADD0R: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// NSBOOTADD0 - NSBOOTADD0: u25, - }), - /// Flash non-secure boot address 1 register - NSBOOTADD1R: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// NSBOOTADD1 - NSBOOTADD1: u25, - }), - /// FFlash secure boot address 0 register - SECBOOTADD0R: mmio.Mmio(packed struct(u32) { - /// BOOT_LOCK - BOOT_LOCK: u1, - reserved7: u6, - /// SECBOOTADD0 - SECBOOTADD0: u25, - }), - /// Flash bank 1 secure watermak1 register - SECWM1R1: mmio.Mmio(packed struct(u32) { - /// SECWM1_PSTRT - SECWM1_PSTRT: u7, - reserved16: u9, - /// SECWM1_PEND - SECWM1_PEND: u7, - padding: u9, - }), - /// Flash secure watermak1 register 2 - SECWM1R2: mmio.Mmio(packed struct(u32) { - /// PCROP1_PSTRT - PCROP1_PSTRT: u7, - reserved15: u8, - /// PCROP1EN - PCROP1EN: u1, - /// HDP1_PEND - HDP1_PEND: u7, - reserved31: u8, - /// HDP1EN - HDP1EN: u1, - }), - /// Flash Bank 1 WRP area A address register - WRP1AR: mmio.Mmio(packed struct(u32) { - /// WRP1A_PSTRT - WRP1A_PSTRT: u7, - reserved16: u9, - /// WRP1A_PEND - WRP1A_PEND: u7, - padding: u9, - }), - /// Flash Bank 1 WRP area B address register - WRP1BR: mmio.Mmio(packed struct(u32) { - /// WRP1B_PSTRT - WRP1B_PSTRT: u7, - reserved16: u9, - /// WRP1B_PEND - WRP1B_PEND: u7, - padding: u9, - }), - /// Flash secure watermak2 register - SECWM2R1: mmio.Mmio(packed struct(u32) { - /// SECWM2_PSTRT - SECWM2_PSTRT: u7, - reserved16: u9, - /// SECWM2_PEND - SECWM2_PEND: u7, - padding: u9, - }), - /// Flash secure watermak2 register2 - SECWM2R2: mmio.Mmio(packed struct(u32) { - /// PCROP2_PSTRT - PCROP2_PSTRT: u7, - reserved15: u8, - /// PCROP2EN - PCROP2EN: u1, - /// HDP2_PEND - HDP2_PEND: u7, - reserved31: u8, - /// HDP2EN - HDP2EN: u1, - }), - /// Flash WPR2 area A address register - WRP2AR: mmio.Mmio(packed struct(u32) { - /// WRP2A_PSTRT - WRP2A_PSTRT: u7, - reserved16: u9, - /// WRP2A_PEND - WRP2A_PEND: u7, - padding: u9, - }), - /// Flash WPR2 area B address register - WRP2BR: mmio.Mmio(packed struct(u32) { - /// WRP2B_PSTRT - WRP2B_PSTRT: u7, - reserved16: u9, - /// WRP2B_PEND - WRP2B_PEND: u7, - padding: u9, - }), - reserved128: [16]u8, - /// FLASH secure block based bank 1 register - SECBB1R1: mmio.Mmio(packed struct(u32) { - /// SECBB1 - SECBB1: u32, - }), - /// FLASH secure block based bank 1 register - SECBB1R2: mmio.Mmio(packed struct(u32) { - /// SECBB1 - SECBB1: u32, - }), - /// FLASH secure block based bank 1 register - SECBB1R3: mmio.Mmio(packed struct(u32) { - /// SECBB1 - SECBB1: u32, - }), - /// FLASH secure block based bank 1 register - SECBB1R4: mmio.Mmio(packed struct(u32) { - /// SECBB1 - SECBB1: u32, - }), - reserved160: [16]u8, - /// FLASH secure block based bank 2 register - SECBB2R1: mmio.Mmio(packed struct(u32) { - /// SECBB2 - SECBB2: u32, - }), - /// FLASH secure block based bank 2 register - SECBB2R2: mmio.Mmio(packed struct(u32) { - /// SECBB2 - SECBB2: u32, - }), - /// FLASH secure block based bank 2 register - SECBB2R3: mmio.Mmio(packed struct(u32) { - /// SECBB2 - SECBB2: u32, - }), - /// FLASH secure block based bank 2 register - SECBB2R4: mmio.Mmio(packed struct(u32) { - /// SECBB2 - SECBB2: u32, - }), - reserved192: [16]u8, - /// FLASH secure HDP control register - SECHDPCR: mmio.Mmio(packed struct(u32) { - /// HDP1_ACCDIS - HDP1_ACCDIS: u1, - /// HDP2_ACCDIS - HDP2_ACCDIS: u1, - padding: u30, - }), - /// Power privilege configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// PRIV - PRIV: u1, - padding: u31, - }), - }; - }; - - pub const lcd_v1 = struct { - /// Liquid crystal display controller - pub const LCD = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// LCD controller enable - LCDEN: u1, - /// Voltage source selection - VSEL: u1, - /// Duty selection - DUTY: u3, - /// Bias selector - BIAS: u2, - /// Mux segment enable - MUX_SEG: u1, - padding: u24, - }), - /// frame control register + /// stream x peripheral address register + PAR: u32, + /// stream x memory 0 address register + M0AR: u32, + /// stream x memory 1 address register + M1AR: u32, + /// stream x FIFO control register FCR: mmio.Mmio(packed struct(u32) { - /// High drive enable - HD: u1, - /// Start of frame interrupt enable - SOFIE: u1, - reserved3: u1, - /// Update display done interrupt enable - UDDIE: u1, - /// Pulse ON duration - PON: u3, - /// Dead time duration - DEAD: u3, - /// Contrast control - CC: u3, - /// Blink frequency selection - BLINKF: u3, - /// Blink mode selection - BLINK: u2, - /// DIV clock divider - DIV: u4, - /// PS 16-bit prescaler - PS: u4, - padding: u6, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// LCD enabled status - ENS: u1, - /// Start of frame flag - SOF: u1, - /// Update display request - UDR: u1, - /// Update Display Done - UDD: u1, - /// Ready flag - RDY: u1, - /// LCD Frame Control Register Synchronization flag - FCRSF: u1, - padding: u26, - }), - /// clear register - CLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Start of frame flag clear - SOFC: u1, - reserved3: u1, - /// Update display done clear - UDDC: u1, - padding: u28, + /// FIFO threshold selection + FTH: packed union { + raw: u2, + value: FTH, + }, + /// Direct mode disable + DMDIS: packed union { + raw: u1, + value: DMDIS, + }, + /// FIFO status + FS: packed union { + raw: u3, + value: FS, + }, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, }), - reserved20: [4]u8, - /// display memory - RAM_COM: u32, - }; - - /// display memory - pub const RAM_COM = extern struct { - /// display memory low word - LOW: u32, - /// display memory high word - HIGH: u32, }; }; - pub const cryp_v3 = struct { - /// Cryptographic processor. - pub const CRYP = extern struct { - /// control register. - CR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Algorithm direction. - ALGODIR: u1, - /// Algorithm mode. - ALGOMODE0: u3, - /// Data type selection. - DATATYPE: u2, - /// Key size selection (AES mode only). - KEYSIZE: u2, - reserved14: u4, - /// FIFO flush. - FFLUSH: u1, - /// Cryptographic processor enable. - CRYPEN: u1, - /// GCM_CCMPH. - GCM_CCMPH: u2, - reserved19: u1, - /// ALGOMODE. - ALGOMODE3: u1, - /// Number of Padding Bytes in Last Block of payload. - NPBLB: u4, - padding: u8, - }), - /// status register. - SR: mmio.Mmio(packed struct(u32) { - /// Input FIFO empty. - IFEM: u1, - /// Input FIFO not full. - IFNF: u1, - /// Output FIFO not empty. - OFNE: u1, - /// Output FIFO full. - OFFU: u1, - /// Busy bit. - BUSY: u1, - padding: u27, - }), - /// data input register. - DIN: u32, - /// data output register. - DOUT: u32, - /// DMA control register. - DMACR: mmio.Mmio(packed struct(u32) { - /// DMA input enable. - DIEN: u1, - /// DMA output enable. - DOEN: u1, - padding: u30, - }), - /// interrupt mask set/clear register. - IMSCR: mmio.Mmio(packed struct(u32) { - /// Input FIFO service interrupt mask. - INIM: u1, - /// Output FIFO service interrupt mask. - OUTIM: u1, - padding: u30, - }), - /// raw interrupt status register. - RISR: mmio.Mmio(packed struct(u32) { - /// Input FIFO service raw interrupt status. - INRIS: u1, - /// Output FIFO service raw interrupt status. - OUTRIS: u1, - padding: u30, - }), - /// masked interrupt status register. - MISR: mmio.Mmio(packed struct(u32) { - /// Input FIFO service masked interrupt status. - INMIS: u1, - /// Output FIFO service masked interrupt status. - OUTMIS: u1, - padding: u30, - }), - /// Cluster KEY%s, containing K?LR, K?RR. - KEY: u32, - reserved64: [28]u8, - /// Cluster INIT%s, containing IV?LR, IV?RR. - INIT: u32, - reserved80: [12]u8, - /// context swap register. - CSGCMCCMR: [8]u32, - /// context swap register. - CSGCMR: [8]u32, - }; - - /// Cluster INIT%s, containing IV?LR, IV?RR. - pub const INIT = extern struct { - /// initialization vector registers. - IVLR: u32, - /// initialization vector registers. - IVRR: u32, + pub const dma_v2 = struct { + pub const BURST = enum(u2) { + /// Single transfer + Single = 0x0, + /// Incremental burst of 4 beats + INCR4 = 0x1, + /// Incremental burst of 8 beats + INCR8 = 0x2, + /// Incremental burst of 16 beats + INCR16 = 0x3, }; - /// Cluster KEY%s, containing K?LR, K?RR. - pub const KEY = extern struct { - /// key registers. - KLR: u32, - /// key registers. - KRR: u32, + pub const CT = enum(u1) { + /// The current target memory is Memory 0 + Memory0 = 0x0, + /// The current target memory is Memory 1 + Memory1 = 0x1, }; - }; - pub const aes_v3b = struct { - pub const CHMOD = enum(u3) { - /// Electronic codebook - ECB = 0x0, - /// Cipher-block chaining - CBC = 0x1, - /// Counter mode - CTR = 0x2, - /// Galois counter mode and Galois message authentication code - GCM_GMAC = 0x3, - /// Counter with CBC-MAC - CCM = 0x4, + pub const DIR = enum(u2) { + /// Peripheral-to-memory + PeripheralToMemory = 0x0, + /// Memory-to-peripheral + MemoryToPeripheral = 0x1, + /// Memory-to-memory + MemoryToMemory = 0x2, _, }; - pub const DATATYPE = enum(u2) { - /// Word - None = 0x0, - /// Half-word (16-bit) - HalfWord = 0x1, - /// Byte (8-bit) - Byte = 0x2, - /// Bit - Bit = 0x3, - }; - - pub const GCMPH = enum(u2) { - /// Init phase - @"Init phase" = 0x0, - /// Header phase - @"Header phase" = 0x1, - /// Payload phase - @"Payload phase" = 0x2, - /// Final phase - @"Final phase" = 0x3, + pub const DMDIS = enum(u1) { + /// Direct mode is enabled + Enabled = 0x0, + /// Direct mode is disabled + Disabled = 0x1, }; - pub const MODE = enum(u2) { - /// Encryption - Mode1 = 0x0, - /// Key derivation (or key preparation for ECB/CBC decryption) - Mode2 = 0x1, - /// Decryption - Mode3 = 0x2, + pub const FS = enum(u3) { + /// 0 < fifo_level < 1/4 + Quarter1 = 0x0, + /// 1/4 <= fifo_level < 1/2 + Quarter2 = 0x1, + /// 1/2 <= fifo_level < 3/4 + Quarter3 = 0x2, + /// 3/4 <= fifo_level < full + Quarter4 = 0x3, + /// FIFO is empty + Empty = 0x4, + /// FIFO is full + Full = 0x5, _, }; - /// Advanced encryption standard hardware accelerator - pub const AES = extern struct { - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// AES enable - EN: u1, - /// Data type selection - DATATYPE: packed union { - raw: u2, - value: DATATYPE, - }, - /// Operating mode - MODE: packed union { - raw: u2, - value: MODE, - }, - padding: u27, - }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Computation complete flag - CCF: u1, - /// Read error flag - RDERR: u1, - /// Write error flag - WRERR: u1, - /// Busy flag - BUSY: u1, - reserved7: u3, - /// Key valid flag - KEYVALID: u1, - padding: u24, - }), - /// Data input register - DINR: u32, - /// Data output register - DOUTR: u32, - /// Key register - KEYR: u32, - reserved32: [12]u8, - /// Initialization vector register - IVR: [4]u32, - reserved64: [16]u8, - /// Suspend register - SUSPR: [8]u32, - reserved768: [672]u8, - /// interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// Computation complete flag interrupt enable - CCFIE: u1, - /// Read or write error interrupt enable - RWEIE: u1, - /// Key error interrupt enable - KEIE: u1, - padding: u29, - }), - /// interrupt status register - ISR: mmio.Mmio(packed struct(u32) { - /// Computation complete flag - CCF: u1, - /// Read or write error interrupt flag - RWEIF: u1, - /// Key error interrupt flag - KEIF: u1, - padding: u29, - }), - /// interrupt clear register - ICR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Read or write error interrupt flag clear - RWEIF: u1, - /// Key error interrupt flag clear - KEIF: u1, - padding: u29, - }), - }; - }; - - pub const opamp_g4 = struct { - pub const CALSEL = enum(u2) { - /// VREFOPAMP=3.3% VDDA - Percent3_3 = 0x0, - /// VREFOPAMP=10% VDDA - Percent10 = 0x1, - /// VREFOPAMP=50% VDDA - Percent50 = 0x2, - /// VREFOPAMP=90% VDDA - Percent90 = 0x3, - }; - - pub const FORCE_VP = enum(u1) { - /// Normal operating mode - Normal = 0x0, - /// Calibration mode. Non-inverting input connected to calibration reference - Calibration = 0x1, + pub const FTH = enum(u2) { + /// 1/4 full FIFO + Quarter = 0x0, + /// 1/2 full FIFO + Half = 0x1, + /// 3/4 full FIFO + ThreeQuarters = 0x2, + /// Full FIFO + Full = 0x3, }; - pub const OPAHSM = enum(u1) { - /// OpAmp in normal mode - Normal = 0x0, - /// OpAmp in high speed mode - HighSpeed = 0x1, + pub const PFCTRL = enum(u1) { + /// The DMA is the flow controller + DMA = 0x0, + /// The peripheral is the flow controller + Peripheral = 0x1, }; - pub const OPAINTOEN = enum(u1) { - /// Output is connected to the output Pin - OutputPin = 0x0, - /// Output is connected internally to ADC channel - ADCChannel = 0x1, + pub const PINCOS = enum(u1) { + /// The offset size for the peripheral address calculation is linked to the PSIZE + PSIZE = 0x0, + /// The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) + Fixed4 = 0x1, }; - pub const OUTCAL = enum(u1) { - /// Non-inverting < inverting + pub const PL = enum(u2) { + /// Low Low = 0x0, - /// Non-inverting > inverting - High = 0x1, + /// Medium + Medium = 0x1, + /// High + High = 0x2, + /// Very high + VeryHigh = 0x3, }; - pub const PGA_GAIN = enum(u5) { - /// Gain 2 - Gain2 = 0x0, - /// Gain 4 - Gain4 = 0x1, - /// Gain 8 - Gain8 = 0x2, - /// Gain 16 - Gain16 = 0x3, - /// Gain 32 - Gain32 = 0x4, - /// Gain 64 - Gain64 = 0x5, - /// Gain 2, input/bias connected to VINM0 or inverting gain - Gain2_InputVINM0 = 0x8, - /// Gain 4, input/bias connected to VINM0 or inverting gain - Gain4_InputVINM0 = 0x9, - /// Gain 8, input/bias connected to VINM0 or inverting gain - Gain8_InputVINM0 = 0xa, - /// Gain 16, input/bias connected to VINM0 or inverting gain - Gain16_InputVINM0 = 0xb, - /// Gain 32, input/bias connected to VINM0 or inverting gain - Gain32_InputVINM0 = 0xc, - /// Gain 64, input/bias connected to VINM0 or inverting gain - Gain64_InputVINM0 = 0xd, - /// Gain 2, with filtering on VINM0 - Gain2_FilteringVINM0 = 0x10, - /// Gain 4, with filtering on VINM0 - Gain4_FilteringVINM0 = 0x11, - /// Gain 8, with filtering on VINM0 - Gain8_FilteringVINM0 = 0x12, - /// Gain 16, with filtering on VINM0 - Gain16_FilteringVINM0 = 0x13, - /// Gain 32, with filtering on VINM0 - Gain32_FilteringVINM0 = 0x14, - /// Gain 64, with filtering on VINM0 - Gain64_FilteringVINM0 = 0x15, - /// Gain 2, input/bias connected to VINM0 with filtering on VINM1 or inverting gain - Gain2_InputVINM0FilteringVINM1 = 0x18, - /// Gain 4, input/bias connected to VINM0 with filtering on VINM1 or inverting gain - Gain4_InputVINM0FilteringVINM1 = 0x19, - /// Gain 8, input/bias connected to VINM0 with filtering on VINM1 or inverting gain - Gain8_InputVINM0FilteringVINM1 = 0x1a, - /// Gain 16, input/bias connected to VINM0 with filtering on VINM1 or inverting gain - Gain16_InputVINM0FilteringVINM1 = 0x1b, - /// Gain 32, input/bias connected to VINM0 with filtering on VINM1 or inverting gain - Gain32_InputVINM0FilteringVINM1 = 0x1c, - /// Gain 64, input/bias connected to VINM0 with filtering on VINM1 or inverting gain - Gain64_InputVINM0FilteringVINM1 = 0x1d, + pub const SIZE = enum(u2) { + /// Byte (8-bit) + Bits8 = 0x0, + /// Half-word (16-bit) + Bits16 = 0x1, + /// Word (32-bit) + Bits32 = 0x2, _, }; - pub const USERTRIM = enum(u1) { - /// Factory trim used - Factory = 0x0, - /// User trim used - User = 0x1, - }; - - pub const VM_SEL = enum(u2) { - /// VINM0 connected to VINM input - VINM0 = 0x0, - /// VINM1 connected to VINM input - VINM1 = 0x1, - /// Feedback resistor connected to VINM (PGA mode) - PGA = 0x2, - /// OpAmp output connected to VINM (Follower mode) - Output = 0x3, - }; - - pub const VPS_SEL = enum(u2) { - /// VINP0 connected to VINP input - VINP0 = 0x0, - /// VINP1 connected to VINP input - VINP1 = 0x1, - /// VINP2 connected to VINP input - VINP2 = 0x2, - /// DAC3_CH1 connected to VINP input - DAC3_CH1 = 0x3, - }; - - pub const VP_SEL = enum(u2) { - /// VINP0 connected to VINP input - VINP0 = 0x0, - /// VINP1 connected to VINP input - VINP1 = 0x1, - /// VINP2 connected to VINP input - VINP2 = 0x2, - /// DAC3_CH1 connected to VINP input - DAC3_CH1 = 0x3, + /// DMA controller + pub const DMA = extern struct { + /// low interrupt status register + ISR: [2]mmio.Mmio(packed struct(u32) { + /// Stream x FIFO error interrupt flag (x=3..0) + FEIF: u1, + reserved2: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + DMEIF: u1, + /// Stream x transfer error interrupt flag (x=3..0) + TEIF: u1, + /// Stream x half transfer interrupt flag (x=3..0) + HTIF: u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + TCIF: u1, + padding: u26, + }), + /// low interrupt flag clear register + IFCR: [2]mmio.Mmio(packed struct(u32) { + /// Stream x FIFO error interrupt flag (x=3..0) + FEIF: u1, + reserved2: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + DMEIF: u1, + /// Stream x transfer error interrupt flag (x=3..0) + TEIF: u1, + /// Stream x half transfer interrupt flag (x=3..0) + HTIF: u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + TCIF: u1, + padding: u26, + }), + /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers + ST: u32, }; - /// Operational Amplifier - pub const OPAMP = extern struct { - /// OPAMP control/status register - CSR: mmio.Mmio(packed struct(u32) { - /// OPAMP enable - OPAMPEN: u1, - /// Forces a calibration reference voltage on non-inverting input and disables external connections. - FORCE_VP: packed union { + /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers + pub const ST = extern struct { + /// stream x configuration register + CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: packed union { raw: u1, - value: FORCE_VP, + value: PFCTRL, }, - /// VP_SEL - VP_SEL: packed union { + /// Data transfer direction + DIR: packed union { raw: u2, - value: VP_SEL, - }, - /// USERTRIM - USERTRIM: packed union { - raw: u1, - value: USERTRIM, + value: DIR, }, - /// OPAMP inverting input selection - VM_SEL: packed union { + /// Circular mode enabled + CIRC: u1, + /// Peripheral increment mode enabled + PINC: u1, + /// Memory increment mode enabled + MINC: u1, + /// Peripheral data size + PSIZE: packed union { raw: u2, - value: VM_SEL, + value: SIZE, }, - /// OPAHSM - OPAHSM: packed union { - raw: u1, - value: OPAHSM, + /// Memory data size + MSIZE: packed union { + raw: u2, + value: SIZE, }, - /// OPAINTOEN - OPAINTOEN: packed union { + /// Peripheral increment offset size + PINCOS: packed union { raw: u1, - value: OPAINTOEN, + value: PINCOS, }, - reserved11: u2, - /// Calibration mode enable - CALON: u1, - /// Calibration selection - CALSEL: packed union { + /// Priority level + PL: packed union { raw: u2, - value: CALSEL, - }, - /// Gain in PGA mode - PGA_GAIN: packed union { - raw: u5, - value: PGA_GAIN, + value: PL, }, - /// Offset trimming value (PMOS) - TRIMOFFSETP: u5, - /// Offset trimming value (NMOS) - TRIMOFFSETN: u5, - reserved30: u1, - /// OPAMP ouput status flag - OUTCAL: packed union { + /// Double buffer mode enabled + DBM: u1, + /// Current target (only in double buffer mode) + CT: packed union { raw: u1, - value: OUTCAL, + value: CT, }, - /// LOCK - LOCK: u1, - }), - reserved24: [20]u8, - /// OPAMP control/status register - TCMR: mmio.Mmio(packed struct(u32) { - /// VMS_SEL - VMS_SEL: u1, - /// VPS_SEL - VPS_SEL: packed union { + reserved21: u1, + /// Peripheral burst transfer configuration + PBURST: packed union { raw: u2, - value: VPS_SEL, + value: BURST, }, - /// T1CM_EN - T1CM_EN: u1, - /// T8CM_EN - T8CM_EN: u1, - /// T20CM_EN - T20CM_EN: u1, - reserved31: u25, - /// TCMR LOCK - LOCK: u1, - }), - }; - }; - - pub const crs_v1 = struct { - pub const SYNCSRC = enum(u2) { - /// GPIO selected as SYNC signal source - GPIO = 0x0, - /// LSE selected as SYNC signal source - LSE = 0x1, - /// USB SOF selected as SYNC signal source - USB = 0x2, - _, - }; - - /// Clock recovery system - pub const CRS = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// SYNC event OK interrupt enable - SYNCOKIE: u1, - /// SYNC warning interrupt enable - SYNCWARNIE: u1, - /// Synchronization or trimming error interrupt enable - ERRIE: u1, - /// Expected SYNC interrupt enable - ESYNCIE: u1, - reserved5: u1, - /// Frequency error counter enable - CEN: u1, - /// Automatic trimming enable - AUTOTRIMEN: u1, - /// Generate software SYNC event - SWSYNC: u1, - /// HSI48 oscillator smooth trimming - TRIM: u6, - padding: u18, - }), - /// configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// Counter reload value - RELOAD: u16, - /// Frequency error limit - FELIM: u8, - /// SYNC divider - SYNCDIV: u3, - reserved28: u1, - /// SYNC signal source selection - SYNCSRC: packed union { + /// Memory burst transfer configuration + MBURST: packed union { raw: u2, - value: SYNCSRC, + value: BURST, }, - reserved31: u1, - /// SYNC polarity selection - SYNCPOL: u1, + /// Channel selection + CHSEL: u4, + padding: u3, }), - /// interrupt and status register - ISR: mmio.Mmio(packed struct(u32) { - /// SYNC event OK flag - SYNCOKF: u1, - /// SYNC warning flag - SYNCWARNF: u1, - /// Error flag - ERRF: u1, - /// Expected SYNC flag - ESYNCF: u1, - reserved8: u4, - /// SYNC error - SYNCERR: u1, - /// SYNC missed - SYNCMISS: u1, - /// Trimming overflow or underflow - TRIMOVF: u1, - reserved15: u4, - /// Frequency error direction - FEDIR: u1, - /// Frequency error capture - FECAP: u16, + /// stream x number of data register + NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, }), - /// interrupt flag clear register - ICR: mmio.Mmio(packed struct(u32) { - /// SYNC event OK clear flag - SYNCOKC: u1, - /// SYNC warning clear flag - SYNCWARNC: u1, - /// Error clear flag - ERRC: u1, - /// Expected SYNC clear flag - ESYNCC: u1, - padding: u28, + /// stream x peripheral address register + PAR: u32, + /// stream x memory 0 address register + M0AR: u32, + /// stream x memory 1 address register + M1AR: u32, + /// stream x FIFO control register + FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: packed union { + raw: u2, + value: FTH, + }, + /// Direct mode disable + DMDIS: packed union { + raw: u1, + value: DMDIS, + }, + /// FIFO status + FS: packed union { + raw: u3, + value: FS, + }, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, }), }; }; - pub const otg_v1 = struct { - pub const DPID = enum(u2) { - DATA0 = 0x0, - DATA2 = 0x1, - DATA1 = 0x2, - MDATA = 0x3, - }; - - pub const DSPD = enum(u2) { - /// High speed - HIGH_SPEED = 0x0, - /// Full speed using external ULPI PHY - FULL_SPEED_EXTERNAL = 0x1, - /// Full speed using internal embedded PHY - FULL_SPEED_INTERNAL = 0x3, - _, - }; - - pub const EPTYP = enum(u2) { - CONTROL = 0x0, - ISOCHRONOUS = 0x1, - BULK = 0x2, - INTERRUPT = 0x3, - }; - - pub const PFIVL = enum(u2) { - /// 80% of the frame interval - FRAME_INTERVAL_80 = 0x0, - /// 85% of the frame interval - FRAME_INTERVAL_85 = 0x1, - /// 90% of the frame interval - FRAME_INTERVAL_90 = 0x2, - /// 95% of the frame interval - FRAME_INTERVAL_95 = 0x3, - }; - - pub const PKTSTSD = enum(u4) { - /// Global OUT NAK (triggers an interrupt) - OUT_NAK = 0x1, - /// OUT data packet received - OUT_DATA_RX = 0x2, - /// OUT transfer completed (triggers an interrupt) - OUT_DATA_DONE = 0x3, - /// SETUP transaction completed (triggers an interrupt) - SETUP_DATA_DONE = 0x4, - /// SETUP data packet received - SETUP_DATA_RX = 0x6, - _, + pub const dmamux_v1 = struct { + pub const POL = enum(u2) { + /// No event, i.e. no synchronization nor detection + NoEdge = 0x0, + /// Rising edge + RisingEdge = 0x1, + /// Falling edge + FallingEdge = 0x2, + /// Rising and falling edges + BothEdges = 0x3, }; - pub const PKTSTSH = enum(u4) { - /// IN data packet received - IN_DATA_RX = 0x2, - /// IN transfer completed (triggers an interrupt) - IN_DATA_DONE = 0x3, - /// Data toggle error (triggers an interrupt) - DATA_TOGGLE_ERR = 0x5, - /// Channel halted (triggers an interrupt) - CHANNEL_HALTED = 0x7, - _, + /// DMAMUX + pub const DMAMUX = extern struct { + /// DMAMux - DMA request line multiplexer channel x control register + CCR: [16]mmio.Mmio(packed struct(u32) { + /// Input DMA request line selected + DMAREQ_ID: u8, + /// Interrupt enable at synchronization event overrun + SOIE: u1, + /// Event generation enable/disable + EGE: u1, + reserved16: u6, + /// Synchronous operating mode enable/disable + SE: u1, + /// Synchronization event type selector Defines the synchronization event on the selected synchronization input: + SPOL: packed union { + raw: u2, + value: POL, + }, + /// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + NBREQ: u5, + /// Synchronization input selected + SYNC_ID: u5, + padding: u3, + }), + reserved128: [64]u8, + /// DMAMUX request line multiplexer interrupt channel status register + CSR: mmio.Mmio(packed struct(u32) { + /// Synchronization overrun event flag + SOF: u1, + padding: u31, + }), + /// DMAMUX request line multiplexer interrupt clear flag register + CFR: mmio.Mmio(packed struct(u32) { + /// Synchronization overrun event flag + SOF: u1, + padding: u31, + }), + reserved256: [120]u8, + /// DMAMux - DMA request generator channel x control register + RGCR: [8]mmio.Mmio(packed struct(u32) { + /// DMA request trigger input selected + SIG_ID: u5, + reserved8: u3, + /// Interrupt enable at trigger event overrun + OIE: u1, + reserved16: u7, + /// DMA request generator channel enable/disable + GE: u1, + /// DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + GPOL: packed union { + raw: u2, + value: POL, + }, + /// Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + GNBREQ: u5, + padding: u8, + }), + reserved320: [32]u8, + /// DMAMux - DMA request generator status register + RGSR: mmio.Mmio(packed struct(u32) { + /// Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + OF: u1, + padding: u31, + }), + /// DMAMux - DMA request generator clear flag register + RGCFR: mmio.Mmio(packed struct(u32) { + /// Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + OF: u1, + padding: u31, + }), }; + }; - /// USB on the go - pub const OTG = extern struct { - /// Control and status register - GOTGCTL: mmio.Mmio(packed struct(u32) { - /// Session request success - SRQSCS: u1, - /// Session request - SRQ: u1, - /// VBUS valid override enable - VBVALOEN: u1, - /// VBUS valid override value - VBVALOVAL: u1, - /// A-peripheral session valid override enable - AVALOEN: u1, - /// A-peripheral session valid override value - AVALOVAL: u1, - /// B-peripheral session valid override enable - BVALOEN: u1, - /// B-peripheral session valid override value - BVALOVAL: u1, - /// Host negotiation success - HNGSCS: u1, - /// HNP request - HNPRQ: u1, - /// Host set HNP enable - HSHNPEN: u1, - /// Device HNP enabled - DHNPEN: u1, - /// Embedded host enable - EHEN: u1, - reserved16: u3, - /// Connector ID status - CIDSTS: u1, - /// Long/short debounce time - DBCT: u1, - /// A-session valid - ASVLD: u1, - /// B-session valid - BSVLD: u1, - padding: u12, + pub const dsihost_u5 = struct { + /// DSI Host. + pub const DSIHOST = extern struct { + /// DSI Host version register. + VR: mmio.Mmio(packed struct(u32) { + /// Version of the DSI Host This read-only register contains the version of the DSI Host. + VERSION: u32, }), - /// Interrupt register - GOTGINT: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Session end detected - SEDET: u1, - reserved8: u5, - /// Session request success status change - SRSSCHG: u1, - /// Host negotiation success status change - HNSSCHG: u1, - reserved17: u7, - /// Host negotiation detected - HNGDET: u1, - /// A-device timeout change - ADTOCHG: u1, - /// Debounce done - DBCDNE: u1, - /// ID input pin changed - IDCHNG: u1, - padding: u11, + /// DSI Host control register. + CR: mmio.Mmio(packed struct(u32) { + /// Enable This bit configures the DSI Host in either power-up mode or to reset. + EN: u1, + padding: u31, }), - /// AHB configuration register - GAHBCFG: mmio.Mmio(packed struct(u32) { - /// Global interrupt mask - GINT: u1, - /// Burst length/type - HBSTLEN: u4, - /// DMA enable - DMAEN: u1, - reserved7: u1, - /// TxFIFO empty level - TXFELVL: u1, - /// Periodic TxFIFO empty level - PTXFELVL: u1, + /// DSI Host clock control register. + CCR: mmio.Mmio(packed struct(u32) { + /// TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation. + TXECKDIV: u8, + /// Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error. + TOCKDIV: u8, + padding: u16, + }), + /// DSI Host LTDC VCID register. + LVCIDR: mmio.Mmio(packed struct(u32) { + /// Virtual channel ID These bits configure the virtual channel ID for the LTDC interface traffic. + VCID: u2, + padding: u30, + }), + /// DSI Host LTDC color coding register. + LCOLCR: mmio.Mmio(packed struct(u32) { + /// Color coding This field configures the DPI color coding. Others: Reserved. + COLC: u4, + reserved8: u4, + /// Loosely packet enable This bit enables the loosely packed variant to 18-bit configuration. + LPE: u1, padding: u23, }), - /// USB configuration register - GUSBCFG: mmio.Mmio(packed struct(u32) { - /// FS timeout calibration - TOCAL: u3, - reserved6: u3, - /// Full-speed internal serial transceiver enable - PHYSEL: u1, - reserved8: u1, - /// SRP-capable - SRPCAP: u1, - /// HNP-capable - HNPCAP: u1, - /// USB turnaround time - TRDT: u4, - reserved15: u1, - /// PHY Low-power clock select - PHYLPCS: u1, - reserved17: u1, - /// ULPI FS/LS select - ULPIFSLS: u1, - /// ULPI Auto-resume - ULPIAR: u1, - /// ULPI Clock SuspendM - ULPICSM: u1, - /// ULPI External VBUS Drive - ULPIEVBUSD: u1, - /// ULPI external VBUS indicator - ULPIEVBUSI: u1, - /// TermSel DLine pulsing selection - TSDPS: u1, - /// Indicator complement - PCCI: u1, - /// Indicator pass through - PTCI: u1, - /// ULPI interface protect disable - ULPIIPD: u1, - reserved29: u3, - /// Force host mode - FHMOD: u1, - /// Force device mode - FDMOD: u1, - /// Corrupt Tx packet - CTXPKT: u1, + /// DSI Host LTDC polarity configuration register. + LPCR: mmio.Mmio(packed struct(u32) { + /// Data enable polarity This bit configures the polarity of data enable pin. + DEP: u1, + /// VSYNC polarity This bit configures the polarity of VSYNC pin. + VSP: u1, + /// HSYNC polarity This bit configures the polarity of HSYNC pin. + HSP: u1, + padding: u29, }), - /// Reset register - GRSTCTL: mmio.Mmio(packed struct(u32) { - /// Core soft reset - CSRST: u1, - /// HCLK soft reset - HSRST: u1, - /// Host frame counter reset - FCRST: u1, - reserved4: u1, - /// RxFIFO flush - RXFFLSH: u1, - /// TxFIFO flush - TXFFLSH: u1, - /// TxFIFO number - TXFNUM: u5, - reserved30: u19, - /// DMA request signal enabled for USB OTG HS - DMAREQ: u1, - /// AHB master idle - AHBIDL: u1, + /// DSI Host low-power mode configuration register. + LPMCR: mmio.Mmio(packed struct(u32) { + /// VACT largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VACT regions. + VLPSIZE: u8, + reserved16: u8, + /// Largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions. + LPSIZE: u8, + padding: u8, }), - /// Core interrupt register - GINTSTS: mmio.Mmio(packed struct(u32) { - /// Current mode of operation - CMOD: u1, - /// Mode mismatch interrupt - MMIS: u1, - /// OTG interrupt - OTGINT: u1, - /// Start of frame - SOF: u1, - /// RxFIFO non-empty - RXFLVL: u1, - /// Non-periodic TxFIFO empty - NPTXFE: u1, - /// Global IN non-periodic NAK effective - GINAKEFF: u1, - /// Global OUT NAK effective - GOUTNAKEFF: u1, - reserved10: u2, - /// Early suspend - ESUSP: u1, - /// USB suspend - USBSUSP: u1, - /// USB reset - USBRST: u1, - /// Enumeration done - ENUMDNE: u1, - /// Isochronous OUT packet dropped interrupt - ISOODRP: u1, - /// End of periodic frame interrupt - EOPF: u1, - reserved18: u2, - /// IN endpoint interrupt - IEPINT: u1, - /// OUT endpoint interrupt - OEPINT: u1, - /// Incomplete isochronous IN transfer - IISOIXFR: u1, - /// Incomplete periodic transfer (host mode) / Incomplete isochronous OUT transfer (device mode) - IPXFR_INCOMPISOOUT: u1, - /// Data fetch suspended - DATAFSUSP: u1, - reserved24: u1, - /// Host port interrupt - HPRTINT: u1, - /// Host channels interrupt - HCINT: u1, - /// Periodic TxFIFO empty - PTXFE: u1, - reserved28: u1, - /// Connector ID status change - CIDSCHG: u1, - /// Disconnect detected interrupt - DISCINT: u1, - /// Session request/new session detected interrupt - SRQINT: u1, - /// Resume/remote wakeup detected interrupt - WKUPINT: u1, + reserved44: [16]u8, + /// DSI Host protocol configuration register. + PCR: mmio.Mmio(packed struct(u32) { + /// EoTp transmission enable This bit enables the EoTP transmission. + ETTXE: u1, + /// EoTp reception enable This bit enables the EoTp reception. + ETRXE: u1, + /// Bus-turn-around enable This bit enables the bus-turn-around (BTA) request. + BTAE: u1, + /// ECC reception enable This bit enables the ECC reception, error correction and reporting. + ECCRXE: u1, + /// CRC reception enable This bit enables the CRC reception and error reporting. + CRCRXE: u1, + /// EoTp transmission in low-power enable This bit enables the EoTP transmission in low-power. + ETTXLPE: u1, + padding: u26, }), - /// Interrupt mask register - GINTMSK: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Mode mismatch interrupt mask - MMISM: u1, - /// OTG interrupt mask - OTGINT: u1, - /// Start of frame mask - SOFM: u1, - /// Receive FIFO non-empty mask - RXFLVLM: u1, - /// Non-periodic TxFIFO empty mask - NPTXFEM: u1, - /// Global non-periodic IN NAK effective mask - GINAKEFFM: u1, - /// Global OUT NAK effective mask - GONAKEFFM: u1, - reserved10: u2, - /// Early suspend mask - ESUSPM: u1, - /// USB suspend mask - USBSUSPM: u1, - /// USB reset mask - USBRST: u1, - /// Enumeration done mask - ENUMDNEM: u1, - /// Isochronous OUT packet dropped interrupt mask - ISOODRPM: u1, - /// End of periodic frame interrupt mask - EOPFM: u1, - reserved17: u1, - /// Endpoint mismatch interrupt mask - EPMISM: u1, - /// IN endpoints interrupt mask - IEPINT: u1, - /// OUT endpoints interrupt mask - OEPINT: u1, - /// Incomplete isochronous IN transfer mask - IISOIXFRM: u1, - /// Incomplete periodic transfer mask (host mode) / Incomplete isochronous OUT transfer mask (device mode) - IPXFRM_IISOOXFRM: u1, - /// Data fetch suspended mask - FSUSPM: u1, - /// Reset detected interrupt mask - RSTDE: u1, - /// Host port interrupt mask - PRTIM: u1, - /// Host channels interrupt mask - HCIM: u1, - /// Periodic TxFIFO empty mask - PTXFEM: u1, - /// LPM interrupt mask - LPMINTM: u1, - /// Connector ID status change mask - CIDSCHGM: u1, - /// Disconnect detected interrupt mask - DISCINT: u1, - /// Session request/new session detected interrupt mask - SRQIM: u1, - /// Resume/remote wakeup detected interrupt mask - WUIM: u1, + /// DSI Host generic VCID register. + GVCIDR: mmio.Mmio(packed struct(u32) { + /// Virtual channel ID for reception This field indicates the generic interface read-back virtual channel identification. + VCIDRX: u2, + reserved16: u14, + /// Virtual channel ID for transmission This field indicates the generic interface virtual channel identification where the generic packet is automatically generated and transmitted. + VCIDTX: u2, + padding: u14, }), - /// Receive status debug read register - GRXSTSR: mmio.Mmio(packed struct(u32) { - /// Endpoint number (device mode) / Channel number (host mode) - EPNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: packed union { - raw: u2, - value: DPID, - }, - /// Packet status (device mode) - PKTSTSD: packed union { - raw: u4, - value: PKTSTSD, - }, - /// Frame number (device mode) - FRMNUM: u4, - padding: u7, + /// DSI Host mode configuration register. + MCR: mmio.Mmio(packed struct(u32) { + /// Command mode This bit configures the DSI Host in either video or command mode. + CMDM: u1, + padding: u31, }), - /// Status read and pop register - GRXSTSP: mmio.Mmio(packed struct(u32) { - /// Endpoint number (device mode) / Channel number (host mode) - EPNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: packed union { - raw: u2, - value: DPID, - }, - /// Packet status (device mode) - PKTSTSD: packed union { - raw: u4, - value: PKTSTSD, - }, - /// Frame number (device mode) - FRMNUM: u4, + /// DSI Host video mode configuration register. + VMCR: mmio.Mmio(packed struct(u32) { + /// Video mode type This field configures the video mode transmission type : 1x: Burst mode. + VMT: u2, + reserved8: u6, + /// Low-power vertical sync active enable This bit enables to return to low-power inside the vertical sync time (VSA) period when timing allows. + LPVSAE: u1, + /// Low-power vertical back-porch enable This bit enables to return to low-power inside the vertical back-porch (VBP) period when timing allows. + LPVBPE: u1, + /// Low-power vertical front-porch enable This bit enables to return to low-power inside the vertical front-porch (VFP) period when timing allows. + LPVFPE: u1, + /// Low-power vertical active enable This bit enables to return to low-power inside the vertical active (VACT) period when timing allows. + LPVAE: u1, + /// Low-power horizontal back-porch enable This bit enables the return to low-power inside the horizontal back-porch (HBP) period when timing allows. + LPHBPE: u1, + /// Low-power horizontal front-porch enable This bit enables the return to low-power inside the horizontal front-porch (HFP) period when timing allows. + LPHFPE: u1, + /// Frame bus-turn-around acknowledge enable This bit enables the request for an acknowledge response at the end of a frame. + FBTAAE: u1, + /// Low-power command enable This bit enables the command transmission only in low-power mode. + LPCE: u1, + /// Pattern generator enable This bit enables the video mode pattern generator. + PGE: u1, + reserved20: u3, + /// Pattern generator mode This bit configures the pattern generator mode. + PGM: u1, + reserved24: u3, + /// Pattern generator orientation This bit configures the color bar orientation. + PGO: u1, padding: u7, }), - /// Receive FIFO size register - GRXFSIZ: mmio.Mmio(packed struct(u32) { - /// RxFIFO depth - RXFD: u16, - padding: u16, + /// DSI Host video packet configuration register. + VPCR: mmio.Mmio(packed struct(u32) { + /// Video packet size This field configures the number of pixels in a single video packet. For 18-bit not loosely packed data types, this number must be a multiple of 4. For YCbCr data types, it must be a multiple of 2 as described in the DSI specification. + VPSIZE: u14, + padding: u18, }), - /// Endpoint 0 transmit FIFO size register (device mode) - DIEPTXF0: mmio.Mmio(packed struct(u32) { - /// RAM start address - SA: u16, - /// FIFO depth - FD: u16, + /// DSI Host video chunks configuration register. + VCCR: mmio.Mmio(packed struct(u32) { + /// Number of chunks This register configures the number of chunks to be transmitted during a line period (a chunk consists of a video packet and a null packet). If set to 0 or 1, the video line is transmitted in a single packet. If set to 1, the packet is part of a chunk, so a null packet follows it if NPSIZE > 0. Otherwise, multiple chunks are used to transmit each video line. + NUMC: u13, + padding: u19, }), - /// Non-periodic transmit FIFO/queue status register (host mode) - HNPTXSTS: mmio.Mmio(packed struct(u32) { - /// Non-periodic TxFIFO space available - NPTXFSAV: u16, - /// Non-periodic transmit request queue space available - NPTQXSAV: u8, - /// Top of the non-periodic transmit request queue - NPTXQTOP: u7, - padding: u1, + /// DSI Host video null packet configuration register. + VNPCR: mmio.Mmio(packed struct(u32) { + /// Null packet size This field configures the number of bytes inside a null packet. Setting to 0 disables the null packets. + NPSIZE: u13, + padding: u19, }), - /// OTG I2C access register - GI2CCTL: mmio.Mmio(packed struct(u32) { - /// I2C Read/Write Data - RWDATA: u8, - /// I2C Register Address - REGADDR: u8, - /// I2C Address - ADDR: u7, - /// I2C Enable - I2CEN: u1, - /// I2C ACK - ACK: u1, - reserved26: u1, - /// I2C Device Address - I2CDEVADR: u2, - /// I2C DatSe0 USB mode - I2CDATSE0: u1, - reserved30: u1, - /// Read/Write Indicator - RW: u1, - /// I2C Busy/Done - BSYDNE: u1, + /// DSI Host video HSA configuration register. + VHSACR: mmio.Mmio(packed struct(u32) { + /// Horizontal synchronism active duration This fields configures the horizontal synchronism active period in lane byte clock cycles. + HSA: u12, + padding: u20, }), - reserved56: [4]u8, - /// General core configuration register, for core_id 0x0000_1xxx - GCCFG_V1: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Power down - PWRDWN: u1, - reserved18: u1, - /// Enable the VBUS "A" sensing device - VBUSASEN: u1, - /// Enable the VBUS "B" sensing device - VBUSBSEN: u1, - /// SOF output enable - SOFOUTEN: u1, - /// VBUS sensing disable - NOVBUSSENS: u1, - padding: u10, + /// DSI Host video HBP configuration register. + VHBPCR: mmio.Mmio(packed struct(u32) { + /// Horizontal back-porch duration This fields configures the horizontal back-porch period in lane byte clock cycles. + HBP: u12, + padding: u20, }), - /// Core ID register - CID: mmio.Mmio(packed struct(u32) { - /// Product ID field - PRODUCT_ID: u32, + /// DSI Host video line configuration register. + VLCR: mmio.Mmio(packed struct(u32) { + /// Horizontal line duration This fields configures the total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles. + HLINE: u15, + padding: u17, }), - reserved84: [20]u8, - /// OTG core LPM configuration register - GLPMCFG: mmio.Mmio(packed struct(u32) { - /// LPM support enable - LPMEN: u1, - /// LPM token acknowledge enable - LPMACK: u1, - /// Best effort service latency - BESL: u4, - /// bRemoteWake value - REMWAKE: u1, - /// L1 Shallow Sleep enable - L1SSEN: u1, - /// BESL threshold - BESLTHRS: u4, - /// L1 deep sleep enable - L1DSEN: u1, - /// LPM response - LPMRST: u2, - /// Port sleep status - SLPSTS: u1, - /// Sleep State Resume OK - L1RSMOK: u1, - /// LPM Channel Index - LPMCHIDX: u4, - /// LPM retry count - LPMRCNT: u3, - /// Send LPM transaction - SNDLPM: u1, - /// LPM retry count status - LPMRCNTSTS: u3, - /// Enable best effort service latency - ENBESL: u1, - padding: u3, + /// DSI Host video VSA configuration register. + VVSACR: mmio.Mmio(packed struct(u32) { + /// Vertical synchronism active duration This fields configures the vertical synchronism active period measured in number of horizontal lines. + VSA: u10, + padding: u22, }), - reserved256: [168]u8, - /// Host periodic transmit FIFO size register - HPTXFSIZ: mmio.Mmio(packed struct(u32) { - /// RAM start address - SA: u16, - /// FIFO depth - FD: u16, + /// DSI Host video VBP configuration register. + VVBPCR: mmio.Mmio(packed struct(u32) { + /// Vertical back-porch duration This fields configures the vertical back-porch period measured in number of horizontal lines. + VBP: u10, + padding: u22, }), - /// Device IN endpoint transmit FIFO size register - DIEPTXF: [7]mmio.Mmio(packed struct(u32) { - /// RAM start address - SA: u16, - /// FIFO depth - FD: u16, + /// DSI Host video VFP configuration register. + VVFPCR: mmio.Mmio(packed struct(u32) { + /// Vertical front-porch duration This fields configures the vertical front-porch period measured in number of horizontal lines. + VFP: u10, + padding: u22, }), - reserved1024: [736]u8, - /// Host configuration register - HCFG: mmio.Mmio(packed struct(u32) { - /// FS/LS PHY clock select - FSLSPCS: u2, - /// FS- and LS-only support - FSLSS: u1, - padding: u29, + /// DSI Host video VA configuration register. + VVACR: mmio.Mmio(packed struct(u32) { + /// Vertical active duration This fields configures the vertical active period measured in number of horizontal lines. + VA: u14, + padding: u18, }), - /// Host frame interval register - HFIR: mmio.Mmio(packed struct(u32) { - /// Frame interval - FRIVL: u16, + /// DSI Host LTDC command configuration register. + LCCR: mmio.Mmio(packed struct(u32) { + /// Command size This field configures the maximum allowed size for an LTDC write memory command, measured in pixels. Automatic partitioning of data obtained from LTDC is permanently enabled. + CMDSIZE: u16, padding: u16, }), - /// Host frame number/frame time remaining register - HFNUM: mmio.Mmio(packed struct(u32) { - /// Frame number - FRNUM: u16, - /// Frame time remaining - FTREM: u16, + /// DSI Host command mode configuration register. + CMCR: mmio.Mmio(packed struct(u32) { + /// Tearing effect acknowledge request enable This bit enables the tearing effect acknowledge request:. + TEARE: u1, + /// Acknowledge request enable This bit enables the acknowledge request after each packet transmission:. + ARE: u1, + reserved8: u6, + /// Generic short write zero parameters transmission This bit configures the generic short write packet with zero parameters command transmission type:. + GSW0TX: u1, + /// Generic short write one parameters transmission This bit configures the generic short write packet with one parameters command transmission type:. + GSW1TX: u1, + /// Generic short write two parameters transmission This bit configures the generic short write packet with two parameters command transmission type:. + GSW2TX: u1, + /// Generic short read zero parameters transmission This bit configures the generic short read packet with zero parameters command transmission type:. + GSR0TX: u1, + /// Generic short read one parameters transmission This bit configures the generic short read packet with one parameters command transmission type:. + GSR1TX: u1, + /// Generic short read two parameters transmission This bit configures the generic short read packet with two parameters command transmission type:. + GSR2TX: u1, + /// Generic long write transmission This bit configures the generic long write packet command transmission type :. + GLWTX: u1, + reserved16: u1, + /// DCS short write zero parameter transmission This bit configures the DCS short write packet with zero parameter command transmission type:. + DSW0TX: u1, + /// DCS short read one parameter transmission This bit configures the DCS short read packet with one parameter command transmission type:. + DSW1TX: u1, + /// DCS short read zero parameter transmission This bit configures the DCS short read packet with zero parameter command transmission type:. + DSR0TX: u1, + /// DCS long write transmission This bit configures the DCS long write packet command transmission type:. + DLWTX: u1, + reserved24: u4, + /// Maximum read packet size This bit configures the maximum read packet size command transmission type:. + MRDPS: u1, + padding: u7, }), - reserved1040: [4]u8, - /// Periodic transmit FIFO/queue status register - HPTXSTS: mmio.Mmio(packed struct(u32) { - /// Periodic transmit data FIFO space available - PTXFSAVL: u16, - /// Periodic transmit request queue space available - PTXQSAV: u8, - /// Top of the periodic transmit request queue - PTXQTOP: u8, + /// DSI Host generic header configuration register. + GHCR: mmio.Mmio(packed struct(u32) { + /// Type This field configures the packet data type of the header packet. + DT: u6, + /// Channel This field configures the virtual channel ID of the header packet. + VCID: u2, + /// WordCount LSB This field configures the less significant byte of the header packet word count for long packets, or data 0 for short packets. + WCLSB: u8, + /// WordCount MSB This field configures the most significant byte of the header packet's word count for long packets, or data 1 for short packets. + WCMSB: u8, + padding: u8, }), - /// Host all channels interrupt register - HAINT: mmio.Mmio(packed struct(u32) { - /// Channel interrupts - HAINT: u16, + /// DSI Host generic payload data register. + GPDR: mmio.Mmio(packed struct(u32) { + /// Payload byte 1 This field indicates the byte 1 of the packet payload. + DATA1: u8, + /// Payload byte 2 This field indicates the byte 2 of the packet payload. + DATA2: u8, + /// Payload byte 3 This field indicates the byte 3 of the packet payload. + DATA3: u8, + /// Payload byte 4 This field indicates the byte 4 of the packet payload. + DATA4: u8, + }), + /// DSI Host generic packet status register. + GPSR: mmio.Mmio(packed struct(u32) { + /// Command FIFO empty This bit indicates the empty status of the generic command FIFO:. + CMDFE: u1, + /// Command FIFO full This bit indicates the full status of the generic command FIFO:. + CMDFF: u1, + /// Payload write FIFO empty This bit indicates the empty status of the generic write payload FIFO:. + PWRFE: u1, + /// Payload write FIFO full This bit indicates the full status of the generic write payload FIFO:. + PWRFF: u1, + /// Payload read FIFO empty This bit indicates the empty status of the generic read payload FIFO:. + PRDFE: u1, + /// Payload read FIFO full This bit indicates the full status of the generic read payload FIFO:. + PRDFF: u1, + /// Read command busy This bit is set when a read command is issued and cleared when the entire response is stored in the FIFO:. + RCB: u1, + reserved16: u9, + /// Command buffer empty This bit indicates the empty status of the generic payload internal buffer:. + CMDBE: u1, + /// Command buffer full This bit indicates the full status of the generic command internal buffer:. + CMDBF: u1, + /// Payload buffer empty This bit indicates the empty status of the generic payload internal buffer:. + PBE: u1, + /// Payload buffer full This bit indicates the full status of the generic payload internal buffer:. + PBF: u1, + padding: u12, + }), + /// DSI Host timeout counter configuration register 0. + TCCR0: mmio.Mmio(packed struct(u32) { + /// Low-power reception timeout counter This field configures the timeout counter that triggers a low-power reception timeout contention detection (measured in TOCKDIV cycles). + LPRX_TOCNT: u16, + /// High-speed transmission timeout counter This field configures the timeout counter that triggers a high-speed transmission timeout contention detection (measured in TOCKDIV cycles). If using the non-burst mode and there is no enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link returns the low-power state once per frame, then configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV ≥ the time of one FRAME data transmission * (1 + 10%) In burst mode, RGB pixel packets are time-compressed, leaving more time during a scan line. Therefore, if in burst mode and there is enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link can return low-power mode and back in this time interval to save power. For this, configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV ≥ the time of one LINE data transmission * (1 + 10%). + HSTX_TOCNT: u16, + }), + /// DSI Host timeout counter configuration register 1. + TCCR1: mmio.Mmio(packed struct(u32) { + /// High-speed read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a high-speed read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + HSRD_TOCNT: u16, padding: u16, }), - /// Host all channels interrupt mask register - HAINTMSK: mmio.Mmio(packed struct(u32) { - /// Channel interrupt mask - HAINTM: u16, + /// DSI Host timeout counter configuration register 2. + TCCR2: mmio.Mmio(packed struct(u32) { + /// Low-power read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + LPRD_TOCNT: u16, padding: u16, }), - reserved1088: [36]u8, - /// Host port control and status register - HPRT: mmio.Mmio(packed struct(u32) { - /// Port connect status - PCSTS: u1, - /// Port connect detected - PCDET: u1, - /// Port enable - PENA: u1, - /// Port enable/disable change - PENCHNG: u1, - /// Port overcurrent active - POCA: u1, - /// Port overcurrent change - POCCHNG: u1, - /// Port resume - PRES: u1, - /// Port suspend - PSUSP: u1, - /// Port reset - PRST: u1, - reserved10: u1, - /// Port line status - PLSTS: u2, - /// Port power - PPWR: u1, - /// Port test control - PTCTL: u4, - /// Port speed - PSPD: u2, - padding: u13, + /// DSI Host timeout counter configuration register 3. + TCCR3: mmio.Mmio(packed struct(u32) { + /// High-speed write timeout counter This field sets a period for which the DSI Host keeps the link inactive after sending a high-speed write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + HSWR_TOCNT: u16, + reserved24: u8, + /// Presp mode When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met: dpivsync_edpiwms has risen and fallen. Packets originated from LTDC in command mode have been transmitted and its FIFO is empty again. In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready. + PM: u1, + padding: u7, }), - reserved1280: [188]u8, - /// Host channel characteristics register - HCCHAR: mmio.Mmio(packed struct(u32) { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved17: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: packed union { - raw: u2, - value: EPTYP, - }, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, + /// DSI Host timeout counter configuration register 4. + TCCR4: mmio.Mmio(packed struct(u32) { + /// Low-power write timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + LPWR_TOCNT: u16, + padding: u16, }), - /// Host channel split control register - HCSPLT: u32, - /// Host channel interrupt register - HCINT: mmio.Mmio(packed struct(u32) { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved3: u1, - /// STALL response received interrupt - STALL: u1, - /// NAK response received interrupt - NAK: u1, - /// ACK response received/transmitted interrupt - ACK: u1, - reserved7: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding: u21, + /// DSI Host timeout counter configuration register 5. + TCCR5: mmio.Mmio(packed struct(u32) { + /// Bus-turn-around timeout counter This field sets a period for which the DSI Host keeps the link still, after completing a bus-turn-around. This period is measured in cycles of lanebyteclk. The counting starts when the D‑PHY enters the Stop state and causes no interrupts. + BTA_TOCNT: u16, + padding: u16, }), - /// Host channel mask register - HCINTMSK: mmio.Mmio(packed struct(u32) { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved3: u1, - /// STALL response received interrupt mask - STALLM: u1, - /// NAK response received interrupt mask - NAKM: u1, - /// ACK response received/transmitted interrupt mask - ACKM: u1, - /// Response received interrupt mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding: u21, + reserved148: [4]u8, + /// DSI Host clock lane configuration register. + CLCR: mmio.Mmio(packed struct(u32) { + /// D-PHY clock control This bit controls the D-PHY clock state:. + DPCC: u1, + /// Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows. + ACR: u1, + padding: u30, }), - /// Host channel transfer size register - HCTSIZ: mmio.Mmio(packed struct(u32) { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding: u1, + /// DSI Host clock lane timer configuration register. + CLTCR: mmio.Mmio(packed struct(u32) { + /// Low-power to high-speed time This field configures the maximum time that the D-PHY clock lane takes to go from low‑power to high-speed transmission measured in lane byte clock cycles. + LP2HS_TIME: u10, + reserved16: u6, + /// High-speed to low-power time This field configures the maximum time that the D-PHY clock lane takes to go from high‑speed to low-power transmission measured in lane byte clock cycles. + HS2LP_TIME: u10, + padding: u6, }), - reserved2048: [748]u8, - /// Device configuration register - DCFG: mmio.Mmio(packed struct(u32) { - /// Device speed - DSPD: packed union { - raw: u2, - value: DSPD, - }, - /// Non-zero-length status OUT handshake - NZLSOHSK: u1, - reserved4: u1, - /// Device address - DAD: u7, - /// Periodic frame interval - PFIVL: packed union { - raw: u2, - value: PFIVL, - }, - reserved14: u1, - /// Transceiver delay - XCVRDLY: u1, + /// DSI Host data lane timer configuration register. + DLTCR: mmio.Mmio(packed struct(u32) { + /// Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles. + LP2HS_TIME: u10, + reserved16: u6, + /// High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles. + HS2LP_TIME: u10, + padding: u6, + }), + /// DSI Host PHY control register. + PCTLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Digital enable When set to 0, this bit places the digital section of the D-PHY in the reset state. + DEN: u1, + /// Clock enable This bit enables the D-PHY clock lane module:. + CKE: u1, + padding: u29, + }), + /// DSI Host PHY configuration register. + PCONFR: mmio.Mmio(packed struct(u32) { + /// Number of lanes This field configures the number of active data lanes: Others: Reserved. + NL: u2, + reserved8: u6, + /// Stop wait time This field configures the minimum wait period to request a high-speed transmission after the Stop state. + SW_TIME: u8, + padding: u16, + }), + /// DSI Host PHY ULPS control register. + PUCR: mmio.Mmio(packed struct(u32) { + /// ULPS request on clock lane ULPS mode request on clock lane. + URCL: u1, + /// ULPS exit on clock lane ULPS mode exit on clock lane. + UECL: u1, + /// ULPS request on data lane ULPS mode request on all active data lanes. + URDL: u1, + /// ULPS exit on data lane ULPS mode exit on all active data lanes. + UEDL: u1, + padding: u28, + }), + /// DSI Host PHY TX triggers configuration register. + PTTCR: mmio.Mmio(packed struct(u32) { + /// Transmission trigger Escape mode transmit trigger 0-3. Only one bit of TX_TRIG is asserted at any given time. + TX_TRIG: u4, + padding: u28, + }), + /// DSI Host PHY status register. + PSR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PHY direction This bit indicates the status of phydirection D-PHY signal. + PD: u1, + /// PHY stop state clock lane This bit indicates the status of phystopstateclklane D-PHY signal. + PSSC: u1, + /// ULPS active not clock lane This bit indicates the status of ulpsactivenotclklane D-PHY signal. + UANC: u1, + /// PHY stop state lane 0 This bit indicates the status of phystopstate0lane D-PHY signal. + PSS0: u1, + /// ULPS active not lane 1 This bit indicates the status of ulpsactivenot0lane D-PHY signal. + UAN0: u1, + /// RX ULPS escape lane 0 This bit indicates the status of rxulpsesc0lane D-PHY signal. + RUE0: u1, + /// PHY stop state lane 1 This bit indicates the status of phystopstate1lane D-PHY signal. + PSS1: u1, + /// ULPS active not lane 1 This bit indicates the status of ulpsactivenot1lane D-PHY signal. + UAN1: u1, + padding: u23, + }), + reserved188: [8]u8, + /// DSI Host interrupt and status register 0. + ISR0: mmio.Mmio(packed struct(u32) { + /// Acknowledge error 0 This bit retrieves the SoT error from the acknowledge error report. + AE0: u1, + /// Acknowledge error 1 This bit retrieves the SoT sync error from the acknowledge error report. + AE1: u1, + /// Acknowledge error 2 This bit retrieves the EoT sync error from the acknowledge error report. + AE2: u1, + /// Acknowledge error 3 This bit retrieves the escape mode entry command error from the acknowledge error report. + AE3: u1, + /// Acknowledge error 4 This bit retrieves the LP transmit sync error from the acknowledge error report. + AE4: u1, + /// Acknowledge error 5 This bit retrieves the peripheral timeout error from the acknowledge error report. + AE5: u1, + /// Acknowledge error 6 This bit retrieves the false control error from the acknowledge error report. + AE6: u1, + /// Acknowledge error 7 This bit retrieves the reserved (specific to the device) from the acknowledge error report. + AE7: u1, + /// Acknowledge error 8 This bit retrieves the ECC error, single-bit (detected and corrected) from the acknowledge error report. + AE8: u1, + /// Acknowledge error 9 This bit retrieves the ECC error, multi-bit (detected, not corrected) from the acknowledge error report. + AE9: u1, + /// Acknowledge error 10 This bit retrieves the checksum error (long packet only) from the acknowledge error report. + AE10: u1, + /// Acknowledge error 11 This bit retrieves the not recognized DSI data type from the acknowledge error report. + AE11: u1, + /// Acknowledge error 12 This bit retrieves the DSI VC ID Invalid from the acknowledge error report. + AE12: u1, + /// Acknowledge error 13 This bit retrieves the invalid transmission length from the acknowledge error report. + AE13: u1, + /// Acknowledge error 14 This bit retrieves the reserved (specific to the device) from the acknowledge error report. + AE14: u1, + /// Acknowledge error 15 This bit retrieves the DSI protocol violation from the acknowledge error report. + AE15: u1, + /// PHY error 0 This bit indicates the ErrEsc escape entry error from lane 0. + PE0: u1, + /// PHY error 1 This bit indicates the ErrSyncEsc low-power transmission synchronization error from lane 0. + PE1: u1, + /// PHY error 2 This bit indicates the ErrControl error from lane 0. + PE2: u1, + /// PHY error 3 This bit indicates the LP0 contention error ErrContentionLP0 from lane 0. + PE3: u1, + /// PHY error 4 This bit indicates the LP1 contention error ErrContentionLP1 from lane 0. + PE4: u1, + padding: u11, + }), + /// DSI Host interrupt and status register 1. + ISR1: mmio.Mmio(packed struct(u32) { + /// Timeout high-speed transmission This bit indicates that the high-speed transmission timeout counter reached the end and contention is detected. + TOHSTX: u1, + /// Timeout low-power reception This bit indicates that the low-power reception timeout counter reached the end and contention is detected. + TOLPRX: u1, + /// ECC single-bit error This bit indicates that the ECC single error is detected and corrected in a received packet. + ECCSE: u1, + /// ECC multi-bit error This bit indicates that the ECC multiple error is detected in a received packet. + ECCME: u1, + /// CRC error This bit indicates that the CRC error is detected in the received packet payload. + CRCE: u1, + /// Packet size error This bit indicates that the packet size error is detected during the packet reception. + PSE: u1, + /// EoTp error This bit indicates that the EoTp packet is not received at the end of the incoming peripheral transmission. + EOTPE: u1, + /// LTDC payload write error This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted. + LPWRE: u1, + /// Generic command write error This bit indicates that the system tried to write a command through the generic interface and the FIFO is full. Therefore, the command is not written. + GCWRE: u1, + /// Generic payload write error This bit indicates that the system tried to write a payload data through the generic interface and the FIFO is full. Therefore, the payload is not written. + GPWRE: u1, + /// Generic payload transmit error This bit indicates that during a generic interface packet build, the payload FIFO becomes empty and corrupt data is sent. + GPTXE: u1, + /// Generic payload read error This bit indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted. + GPRDE: u1, + /// Generic payload receive error This bit indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted. + GPRXE: u1, + reserved19: u6, + /// Payload buffer underflow error This bit indicates that underflow has occurred when reading payload to build DSI packet for video mode. + PBUE: u1, + padding: u12, + }), + /// DSI Host interrupt enable register 0. + IER0: mmio.Mmio(packed struct(u32) { + /// Acknowledge error 0 interrupt enable This bit enables the interrupt generation on acknowledge error 0. + AE0IE: u1, + /// Acknowledge error 1 interrupt enable This bit enables the interrupt generation on acknowledge error 1. + AE1IE: u1, + /// Acknowledge error 2 interrupt enable This bit enables the interrupt generation on acknowledge error 2. + AE2IE: u1, + /// Acknowledge error 3 interrupt enable This bit enables the interrupt generation on acknowledge error 3. + AE3IE: u1, + /// Acknowledge error 4 interrupt enable This bit enables the interrupt generation on acknowledge error 4. + AE4IE: u1, + /// Acknowledge error 5 interrupt enable This bit enables the interrupt generation on acknowledge error 5. + AE5IE: u1, + /// Acknowledge error 6 interrupt enable This bit enables the interrupt generation on acknowledge error 6. + AE6IE: u1, + /// Acknowledge error 7 interrupt enable This bit enables the interrupt generation on acknowledge error 7. + AE7IE: u1, + /// Acknowledge error 8 interrupt enable This bit enables the interrupt generation on acknowledge error 8. + AE8IE: u1, + /// Acknowledge error 9 interrupt enable This bit enables the interrupt generation on acknowledge error 9. + AE9IE: u1, + /// Acknowledge error 10 interrupt enable This bit enables the interrupt generation on acknowledge error 10. + AE10IE: u1, + /// Acknowledge error 11 interrupt enable This bit enables the interrupt generation on acknowledge error 11. + AE11IE: u1, + /// Acknowledge error 12 interrupt enable This bit enables the interrupt generation on acknowledge error 12. + AE12IE: u1, + /// Acknowledge error 13 interrupt enable This bit enables the interrupt generation on acknowledge error 13. + AE13IE: u1, + /// Acknowledge error 14 interrupt enable This bit enables the interrupt generation on acknowledge error 14. + AE14IE: u1, + /// Acknowledge error 15 interrupt enable This bit enables the interrupt generation on acknowledge error 15. + AE15IE: u1, + /// PHY error 0 interrupt enable This bit enables the interrupt generation on PHY error 0. + PE0IE: u1, + /// PHY error 1 interrupt enable This bit enables the interrupt generation on PHY error 1. + PE1IE: u1, + /// PHY error 2 interrupt enable This bit enables the interrupt generation on PHY error 2. + PE2IE: u1, + /// PHY error 3 interrupt enable This bit enables the interrupt generation on PHY error 4. + PE3IE: u1, + /// PHY error 4 interrupt enable This bit enables the interrupt generation on PHY error 4. + PE4IE: u1, + padding: u11, + }), + /// DSI Host interrupt enable register 1. + IER1: mmio.Mmio(packed struct(u32) { + /// Timeout high-speed transmission interrupt enable This bit enables the interrupt generation on timeout high-speed transmission. + TOHSTXIE: u1, + /// Timeout low-power reception interrupt enable This bit enables the interrupt generation on timeout low-power reception. + TOLPRXIE: u1, + /// ECC single-bit error interrupt enable This bit enables the interrupt generation on ECC single-bit error. + ECCSEIE: u1, + /// ECC multi-bit error interrupt enable This bit enables the interrupt generation on ECC multi-bit error. + ECCMEIE: u1, + /// CRC error interrupt enable This bit enables the interrupt generation on CRC error. + CRCEIE: u1, + /// Packet size error interrupt enable This bit enables the interrupt generation on packet size error. + PSEIE: u1, + /// EoTp error interrupt enable This bit enables the interrupt generation on EoTp error. + EOTPEIE: u1, + /// LTDC payload write error interrupt enable This bit enables the interrupt generation on LTDC payload write error. + LPWREIE: u1, + /// Generic command write error interrupt enable This bit enables the interrupt generation on generic command write error. + GCWREIE: u1, + /// Generic payload write error interrupt enable This bit enables the interrupt generation on generic payload write error. + GPWREIE: u1, + /// Generic payload transmit error interrupt enable This bit enables the interrupt generation on generic payload transmit error. + GPTXEIE: u1, + /// Generic payload read error interrupt enable This bit enables the interrupt generation on generic payload read error. + GPRDEIE: u1, + /// Generic payload receive error interrupt enable This bit enables the interrupt generation on generic payload receive error. + GPRXEIE: u1, + reserved19: u6, + /// Payload buffer underflow error interrupt enable This bit enables the interrupt generation on payload buffer underflow error. + PBUEIE: u1, + padding: u12, + }), + reserved216: [12]u8, + /// DSI Host force interrupt register 0. + FIR0: mmio.Mmio(packed struct(u32) { + /// Force acknowledge error 0 Writing one to this bit forces an acknowledge error 0. + FAE0: u1, + /// Force acknowledge error 1 Writing one to this bit forces an acknowledge error 1. + FAE1: u1, + /// Force acknowledge error 2 Writing one to this bit forces an acknowledge error 2. + FAE2: u1, + /// Force acknowledge error 3 Writing one to this bit forces an acknowledge error 3. + FAE3: u1, + /// Force acknowledge error 4 Writing one to this bit forces an acknowledge error 4. + FAE4: u1, + /// Force acknowledge error 5 Writing one to this bit forces an acknowledge error 5. + FAE5: u1, + /// Force acknowledge error 6 Writing one to this bit forces an acknowledge error 6. + FAE6: u1, + /// Force acknowledge error 7 Writing one to this bit forces an acknowledge error 7. + FAE7: u1, + /// Force acknowledge error 8 Writing one to this bit forces an acknowledge error 8. + FAE8: u1, + /// Force acknowledge error 9 Writing one to this bit forces an acknowledge error 9. + FAE9: u1, + /// Force acknowledge error 10 Writing one to this bit forces an acknowledge error 10. + FAE10: u1, + /// Force acknowledge error 11 Writing one to this bit forces an acknowledge error 11. + FAE11: u1, + /// Force acknowledge error 12 Writing one to this bit forces an acknowledge error 12. + FAE12: u1, + /// Force acknowledge error 13 Writing one to this bit forces an acknowledge error 13. + FAE13: u1, + /// Force acknowledge error 14 Writing one to this bit forces an acknowledge error 14. + FAE14: u1, + /// Force acknowledge error 15 Writing one to this bit forces an acknowledge error 15. + FAE15: u1, + /// Force PHY error 0 Writing one to this bit forces a PHY error 0. + FPE0: u1, + /// Force PHY error 1 Writing one to this bit forces a PHY error 1. + FPE1: u1, + /// Force PHY error 2 Writing one to this bit forces a PHY error 2. + FPE2: u1, + /// Force PHY error 3 Writing one to this bit forces a PHY error 3. + FPE3: u1, + /// Force PHY error 4 Writing one to this bit forces a PHY error 4. + FPE4: u1, + padding: u11, + }), + /// DSI Host force interrupt register 1. + FIR1: mmio.Mmio(packed struct(u32) { + /// Force timeout high-speed transmission Writing one to this bit forces a timeout high-speed transmission. + FTOHSTX: u1, + /// Force timeout low-power reception Writing one to this bit forces a timeout low-power reception. + FTOLPRX: u1, + /// Force ECC single-bit error Writing one to this bit forces a ECC single-bit error. + FECCSE: u1, + /// Force ECC multi-bit error Writing one to this bit forces a ECC multi-bit error. + FECCME: u1, + /// Force CRC error Writing one to this bit forces a CRC error. + FCRCE: u1, + /// Force packet size error Writing one to this bit forces a packet size error. + FPSE: u1, + /// Force EoTp error Writing one to this bit forces a EoTp error. + FEOTPE: u1, + /// Force LTDC payload write error Writing one to this bit forces a LTDC payload write error. + FLPWRE: u1, + /// Force generic command write error Writing one to this bit forces a generic command write error. + FGCWRE: u1, + /// Force generic payload write error Writing one to this bit forces a generic payload write error. + FGPWRE: u1, + /// Force generic payload transmit error Writing one to this bit forces a generic payload transmit error. + FGPTXE: u1, + /// Force generic payload read error Writing one to this bit forces a generic payload read error. + FGPRDE: u1, + /// Force generic payload receive error Writing one to this bit forces a generic payload receive error. + FGPRXE: u1, + reserved19: u6, + /// Force payload buffer underflow error Writing one to this bit forces a payload undrflow error. + FPBUE: u1, + padding: u12, + }), + reserved244: [20]u8, + /// DSI Host data lane timer read configuration register. + DLTRCR: mmio.Mmio(packed struct(u32) { + /// Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress. + MRD_TIME: u15, padding: u17, }), - /// Device control register - DCTL: mmio.Mmio(packed struct(u32) { - /// Remote wakeup signaling - RWUSIG: u1, - /// Soft disconnect - SDIS: u1, - /// Global IN NAK status - GINSTS: u1, - /// Global OUT NAK status - GONSTS: u1, - /// Test control - TCTL: u3, - /// Set global IN NAK - SGINAK: u1, - /// Clear global IN NAK - CGINAK: u1, - /// Set global OUT NAK - SGONAK: u1, - /// Clear global OUT NAK - CGONAK: u1, - /// Power-on programming done - POPRGDNE: u1, - padding: u20, + reserved256: [8]u8, + /// DSI Host video shadow control register. + VSCR: mmio.Mmio(packed struct(u32) { + /// Enable When set to 1, DSI Host LTDC interface receives the active configuration from the auxiliary registers. When this bit is set along with the UR bit, the auxiliary registers are automatically updated. + EN: u1, + reserved8: u7, + /// Update register When set to 1, the LTDC registers are copied to the auxiliary registers. After copying, this bit is auto cleared. + UR: u1, + padding: u23, }), - /// Device status register - DSTS: mmio.Mmio(packed struct(u32) { - /// Suspend status - SUSPSTS: u1, - /// Enumerated speed - ENUMSPD: packed union { - raw: u2, - value: DSPD, - }, - /// Erratic error - EERR: u1, + reserved268: [8]u8, + /// DSI Host LTDC current VCID register. + LCVCIDR: mmio.Mmio(packed struct(u32) { + /// Virtual channel ID This field returns the virtual channel ID for the LTDC interface. + VCID: u2, + padding: u30, + }), + /// DSI Host LTDC current color coding register. + LCCCR: mmio.Mmio(packed struct(u32) { + /// Color coding This field returns the current LTDC interface color coding. 0110-1111: reserved If LTDC interface in command mode is chosen and currently works in the command mode (CMDM=1), then 0110-1111: 24-bit. + COLC: u4, reserved8: u4, - /// Frame number of the received SOF - FNSOF: u14, - padding: u10, + /// Loosely packed enable This bit returns the current state of the loosely packed variant to 18-bit configurations. + LPE: u1, + padding: u23, }), - reserved2064: [4]u8, - /// Device IN endpoint common interrupt mask register - DIEPMSK: mmio.Mmio(packed struct(u32) { - /// Transfer completed interrupt mask - XFRCM: u1, - /// Endpoint disabled interrupt mask - EPDM: u1, - reserved3: u1, - /// Timeout condition mask (Non-isochronous endpoints) - TOM: u1, - /// IN token received when TxFIFO empty mask - ITTXFEMSK: u1, - /// IN token received with EP mismatch mask - INEPNMM: u1, - /// IN endpoint NAK effective mask - INEPNEM: u1, - padding: u25, + reserved280: [4]u8, + /// DSI Host low-power mode current configuration register. + LPMCCR: mmio.Mmio(packed struct(u32) { + /// VACT largest packet size This field returns the current size, in bytes, of the largest packet that can fit in a line during VACT regions, for the transmission of commands in low-power mode. + VLPSIZE: u8, + reserved16: u8, + /// Largest packet size This field is returns the current size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions, for the transmission of commands in low-power mode. + LPSIZE: u8, + padding: u8, }), - /// Device OUT endpoint common interrupt mask register - DOEPMSK: mmio.Mmio(packed struct(u32) { - /// Transfer completed interrupt mask - XFRCM: u1, - /// Endpoint disabled interrupt mask - EPDM: u1, - reserved3: u1, - /// SETUP phase done mask - STUPM: u1, - /// OUT token received when endpoint disabled mask - OTEPDM: u1, - padding: u27, + reserved312: [28]u8, + /// DSI Host video mode current configuration register. + VMCCR: mmio.Mmio(packed struct(u32) { + /// Video mode type This field returns the current video mode transmission type: 1x: Burst mode. + VMT: u2, + /// Low-power vertical sync time enable This bit returns the current state of return to low-power inside the vertical sync time (VSA) period when timing allows. + LPVSAE: u1, + /// Low-power vertical back-porch enable This bit returns the current state of return to low-power inside the vertical back-porch (VBP) period when timing allows. + LPVBPE: u1, + /// Low-power vertical front-porch enable This bit returns the current state of return to low-power inside the vertical front-porch (VFP) period when timing allows. + LPVFPE: u1, + /// Low-power vertical active enable This bit returns the current state of return to low-power inside the vertical active (VACT) period when timing allows. + LPVAE: u1, + /// Low-power horizontal back-porch enable This bit returns the current state of return to low-power inside the horizontal back-porch (HBP) period when timing allows. + LPHBPE: u1, + /// Low-power horizontal front-porch enable This bit returns the current state of return to low-power inside the horizontal front-porch (HFP) period when timing allows. + LPHFE: u1, + /// Frame BTA acknowledge enable This bit returns the current state of request for an acknowledge response at the end of a frame. + FBTAAE: u1, + /// Low-power command enable This bit returns the current command transmission state in low-power mode. + LPCE: u1, + padding: u22, }), - /// Device all endpoints interrupt register - DAINT: mmio.Mmio(packed struct(u32) { - /// IN endpoint interrupt bits - IEPINT: u16, - /// OUT endpoint interrupt bits - OEPINT: u16, + /// DSI Host video packet current configuration register. + VPCCR: mmio.Mmio(packed struct(u32) { + /// Video packet size This field returns the number of pixels in a single video packet. + VPSIZE: u14, + padding: u18, }), - /// All endpoints interrupt mask register - DAINTMSK: mmio.Mmio(packed struct(u32) { - /// IN EP interrupt mask bits - IEPM: u16, - /// OUT EP interrupt mask bits - OEPM: u16, + /// DSI Host video chunks current configuration register. + VCCCR: mmio.Mmio(packed struct(u32) { + /// Number of chunks This field returns the number of chunks being transmitted during a line period. + NUMC: u13, + padding: u19, }), - reserved2088: [8]u8, - /// Device VBUS discharge time register - DVBUSDIS: mmio.Mmio(packed struct(u32) { - /// Device VBUS discharge time - VBUSDT: u16, - padding: u16, + /// DSI Host video null packet current configuration register. + VNPCCR: mmio.Mmio(packed struct(u32) { + /// Null packet size This field returns the number of bytes inside a null packet. + NPSIZE: u13, + padding: u19, }), - /// Device VBUS pulsing time register - DVBUSPULSE: mmio.Mmio(packed struct(u32) { - /// Device VBUS pulsing time - DVBUSP: u12, + /// DSI Host video HSA current configuration register. + VHSACCR: mmio.Mmio(packed struct(u32) { + /// Horizontal synchronism active duration This fields returns the horizontal synchronism active period in lane byte clock cycles. + HSA: u12, padding: u20, }), - reserved2100: [4]u8, - /// Device IN endpoint FIFO empty interrupt mask register - DIEPEMPMSK: mmio.Mmio(packed struct(u32) { - /// IN EP Tx FIFO empty interrupt mask bits - INEPTXFEM: u16, - padding: u16, + /// DSI Host video HBP current configuration register. + VHBPCCR: mmio.Mmio(packed struct(u32) { + /// Horizontal back-porch duration This field returns the horizontal back-porch period in lane byte clock cycles. + HBP: u12, + padding: u20, }), - reserved2304: [200]u8, - /// Device IN endpoint control register - DIEPCTL: mmio.Mmio(packed struct(u32) { - /// MPSIZ - MPSIZ: u11, - reserved15: u4, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: packed union { - raw: u2, - value: EPTYP, - }, - /// SNPM - SNPM: u1, - /// STALL - STALL: u1, - /// TXFNUM - TXFNUM: u4, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM/SD1PID - SODDFRM_SD1PID: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, + /// DSI Host video line current configuration register. + VLCCR: mmio.Mmio(packed struct(u32) { + /// Horizontal line duration This field returns the current total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles. + HLINE: u15, + padding: u17, }), - reserved2312: [4]u8, - /// Device IN endpoint interrupt register - DIEPINT: mmio.Mmio(packed struct(u32) { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved3: u1, - /// TOC - TOC: u1, - /// ITTXFE - ITTXFE: u1, - reserved6: u1, - /// INEPNE - INEPNE: u1, - /// TXFE - TXFE: u1, + /// DSI Host video VSA current configuration register. + VVSACCR: mmio.Mmio(packed struct(u32) { + /// Vertical synchronism active duration This field returns the current vertical synchronism active period measured in number of horizontal lines. + VSA: u10, + padding: u22, + }), + /// DSI Host video VBP current configuration register. + VVBPCCR: mmio.Mmio(packed struct(u32) { + /// Vertical back-porch duration This field returns the current vertical back-porch period measured in number of horizontal lines. + VBP: u10, + padding: u22, + }), + /// DSI Host video VFP current configuration register. + VVFPCCR: mmio.Mmio(packed struct(u32) { + /// Vertical front-porch duration This field returns the current vertical front-porch period measured in number of horizontal lines. + VFP: u10, + padding: u22, + }), + /// DSI Host video VA current configuration register. + VVACCR: mmio.Mmio(packed struct(u32) { + /// Vertical active duration This field returns the current vertical active period measured in number of horizontal lines. + VA: u14, + padding: u18, + }), + reserved360: [4]u8, + /// DSI Host FIFO and buffer status register. + FBSR: mmio.Mmio(packed struct(u32) { + /// Video mode command write FIFO empty This bit indicates the empty status of the video mode write command FIFO:. + VCWFE: u1, + /// Video mode command write FIFO full This bit indicates the full status of the video mode write command FIFO:. + VCWFF: u1, + /// Video mode payload write FIFO empty This bit indicates the empty status of the video mode write payload FIFO:. + VPWFE: u1, + /// Video mode payload write FIFO full This bit indicates the full status of the video mode write payload FIFO:. + VPWFF: u1, + /// Adapted command mode command write FIFO empty This bit indicates the empty status of the adapted command mode write command FIFO:. + ACWFE: u1, + /// Adapted command mode command write FIFO full This bit indicates the full status of the adapted command mode write command FIFO:. + ACWFF: u1, + /// Adapted command mode payload write FIFO empty This bit indicates the empty status of the adapted command mode write payload FIFO:. + APWFE: u1, + /// Adapted command mode payload write FIFO full This bit indicates the full status of the adapted command mode write payload FIFO:. + APWFF: u1, + reserved16: u8, + /// Video mode payload buffer empty This bit indicates the empty status of the video mode payload internal buffer:. + VPBE: u1, + /// Video mode payload buffer full This bit indicates the full status of the video mode payload internal buffer:. + VPBF: u1, + reserved20: u2, + /// Adapted command mode command buffer empty This bit indicates the empty status of the adapted command mode command internal buffer:. + ACBE: u1, + /// Adapted command mode command buffer full This bit indicates the full status of the adapted command mode command internal buffer:. + ACBF: u1, + /// Adapted command mode payload buffer empty This bit indicates the empty status of the adapted command mode payload internal buffer:. + APBE: u1, + /// Adapted command mode payload buffer full This bit indicates the full status of the adapted command mode payload internal buffer:. + APBF: u1, + padding: u8, + }), + reserved1024: [660]u8, + /// DSI Wrapper configuration register. + WCFGR: mmio.Mmio(packed struct(u32) { + /// DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (CR.EN = 0). + DSIM: u1, + /// Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.EN = 0). + COLMUX: u3, + /// TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0). + TESRC: u1, + /// TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0). + TEPOL: u1, + /// Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (CR.EN = 0). + AR: u1, + /// VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.EN = 0). + VSPOL: u1, padding: u24, }), - reserved2320: [4]u8, - /// Device IN endpoint transfer size register - DIEPTSIZ: mmio.Mmio(packed struct(u32) { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding: u1, + /// DSI Wrapper control register. + WCR: mmio.Mmio(packed struct(u32) { + /// Color mode This bit controls the display color mode in video mode. + COLM: u1, + /// Shutdown This bit controls the display shutdown in video mode. + SHTDN: u1, + /// LTDC enable This bit enables the LTDC for a frame transfer in adapted command mode. + LTDCEN: u1, + /// DSI enable This bit enables the DSI Wrapper. + DSIEN: u1, + padding: u28, }), - reserved2328: [4]u8, - /// Device IN endpoint transmit FIFO status register - DTXFSTS: mmio.Mmio(packed struct(u32) { - /// IN endpoint TxFIFO space available - INEPTFSAV: u16, - padding: u16, + /// DSI Wrapper interrupt enable register. + WIER: mmio.Mmio(packed struct(u32) { + /// Tearing effect interrupt enable This bit enables the tearing effect interrupt. + TEIE: u1, + /// End of refresh interrupt enable This bit enables the end of refresh interrupt. + ERIE: u1, + reserved9: u7, + /// PLL lock interrupt enable This bit enables the PLL lock interrupt. + PLLLIE: u1, + /// PLL unlock interrupt enable This bit enables the PLL unlock interrupt. + PLLUIE: u1, + padding: u21, }), - reserved2816: [484]u8, - /// Device OUT endpoint control register - DOEPCTL: mmio.Mmio(packed struct(u32) { - /// MPSIZ - MPSIZ: u11, - reserved15: u4, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: packed union { - raw: u2, - value: EPTYP, - }, - /// SNPM - SNPM: u1, - /// STALL - STALL: u1, - reserved26: u4, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM - SODDFRM: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, + /// DSI Wrapper interrupt and status register. + WISR: mmio.Mmio(packed struct(u32) { + /// Tearing effect interrupt flag This bit is set when a tearing effect event occurs. + TEIF: u1, + /// End of refresh interrupt flag This bit is set when the transfer of a frame in adapted command mode is finished. + ERIF: u1, + /// Busy flag This bit is set when the transfer of a frame in adapted command mode is ongoing. + BUSY: u1, + reserved8: u5, + /// PLL lock status This bit is set when the PLL is locked and cleared when it is unlocked. + PLLLS: u1, + /// PLL lock interrupt flag This bit is set when the PLL becomes locked. + PLLLIF: u1, + /// PLL unlock interrupt flag This bit is set when the PLL becomes unlocked. + PLLUIF: u1, + padding: u21, }), - reserved2824: [4]u8, - /// Device OUT endpoint interrupt register - DOEPINT: mmio.Mmio(packed struct(u32) { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved3: u1, - /// STUP - STUP: u1, - /// OTEPDIS - OTEPDIS: u1, - reserved6: u1, - /// B2BSTUP - B2BSTUP: u1, + /// DSI Wrapper interrupt flag clear register. + WIFCR: mmio.Mmio(packed struct(u32) { + /// Clear tearing effect interrupt flag Write 1 clears the TEIF flag in the WSR register. + CTEIF: u1, + /// Clear end of refresh interrupt flag Write 1 clears the ERIF flag in the WSR register. + CERIF: u1, + reserved9: u7, + /// Clear PLL lock interrupt flag Write 1 clears the PLLLIF flag in the WSR register. + CPLLLIF: u1, + /// Clear PLL unlock interrupt flag Write 1 clears the PLLUIF flag in the WSR register. + CPLLUIF: u1, + padding: u21, + }), + reserved1048: [4]u8, + /// DSI Wrapper PHY configuration register 0. + WPCR0: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// Swap clock lane pins This bit swaps the pins on clock lane. + SWCL: u1, + /// Swap data lane 0 pins This bit swaps the pins on data lane 0. + SWDL0: u1, + /// Swap data lane 1 pins This bit swaps the pins on clock lane. + SWDL1: u1, + reserved12: u3, + /// Force in TX Stop mode the clock lane This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. + FTXSMCL: u1, + /// Force in TX Stop mode the data lanes This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. + FTXSMDL: u1, + padding: u18, + }), + reserved1072: [20]u8, + /// DSI Wrapper regulator and PLL control register. + WRPCR: mmio.Mmio(packed struct(u32) { + /// PLL enable This bit enables the D-PHY PLL. + PLLEN: u1, + reserved2: u1, + /// PLL loop division factor This field configures the PLL loop division factor. 2: PLL loop divided by 2x2 ... 511: PLL loop divided by 511x2. + NDIV: u9, + /// PLL input division factor This field configures the PLL input division factor. 2: PLL input divided by 2 ... 511: PLL input divided by 511. + IDF: u9, + /// PLL output division factor This field configures the PLL output division factor. 2: PLL output divided by 2 ... 511: PLL output divided by 511. + ODF: u9, + padding: u3, + }), + reserved2056: [980]u8, + /// DSI bias configuration register. + BCFGR: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// Power-up This bit powers-up the reference bias for the MIPI D-PHY. + PWRUP: u1, padding: u25, }), - reserved2832: [4]u8, - /// Device OUT endpoint transfer size register - DOEPTSIZ: mmio.Mmio(packed struct(u32) { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet count - RXDPID_STUPCNT: u2, - padding: u1, + reserved3076: [1016]u8, + /// DSI D-PHY clock band control register. + DPCBCR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Band control This field selects the frequency band used by the D-PHY. Others: Reserved. + BC: u5, + padding: u24, }), - reserved3584: [748]u8, - /// Power and clock gating control register - PCGCCTL: mmio.Mmio(packed struct(u32) { - /// Stop PHY clock - STPPCLK: u1, - /// Gate HCLK - GATEHCLK: u1, - reserved4: u2, - /// PHY Suspended - PHYSUSP: u1, + reserved3124: [44]u8, + /// DSI D-PHY clock skew rate control register. + DPCSRCR: mmio.Mmio(packed struct(u32) { + /// Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved. + SRC: u8, + padding: u24, + }), + reserved3184: [56]u8, + /// DSI D-PHY data lane 0 band control register. + DPDL0BCR: mmio.Mmio(packed struct(u32) { + /// Band control This field selects the frequency band used by the D-PHY. Others: Reserved. + BC: u5, padding: u27, }), - reserved4096: [508]u8, - /// Device endpoint / host channel FIFO register - FIFO: mmio.Mmio(packed struct(u32) { - /// Data - DATA: u32, + reserved3232: [44]u8, + /// DSI D-PHY data lane 0 skew rate control register. + DPDL0SRCR: mmio.Mmio(packed struct(u32) { + /// Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved. + SRC: u8, + padding: u24, + }), + reserved3336: [100]u8, + /// DSI D-PHY data lane 1 band control register. + DPDL1BCR: mmio.Mmio(packed struct(u32) { + /// Band control This field selects the frequency band used by the D-PHY. Others: Reserved. + BC: u5, + padding: u27, + }), + reserved3384: [44]u8, + /// DSI D-PHY data lane 1 skew rate control register. + DPDL1SRCR: mmio.Mmio(packed struct(u32) { + /// Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved. + SRC: u8, + padding: u24, }), }; }; - pub const icache_v1_4crr = struct { - pub const HBURST = enum(u1) { - Wrap = 0x0, - Increment = 0x1, - }; - - pub const MSTSEL = enum(u1) { - Master1Selected = 0x0, - Master2Selected = 0x1, - }; - - pub const RSIZE = enum(u3) { - MegaBytes2 = 0x1, - MegaBytes4 = 0x2, - MegaBytes8 = 0x3, - MegaBytes16 = 0x4, - MegaBytes32 = 0x5, - MegaBytes64 = 0x6, - MegaBytes128 = 0x7, - _, - }; - - pub const WAYSEL = enum(u1) { - /// direct mapped cache (1-way cache) - DirectMapped = 0x0, - /// n-way set associative cache (reset value) - NWaySetAssociative = 0x1, - }; - - /// Instruction Cache Control Registers. - pub const ICACHE = extern struct { - /// ICACHE control register. + pub const dsihost_v1 = struct { + /// DSI Host. + pub const DSIHOST = extern struct { + /// DSI Host Version Register. + VR: mmio.Mmio(packed struct(u32) { + /// Version of the DSI Host. + VERSION: u32, + }), + /// DSI Host Control Register. CR: mmio.Mmio(packed struct(u32) { - /// EN. + /// Enable. EN: u1, - /// Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. - CACHEINV: u1, - /// This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). - WAYSEL: packed union { - raw: u1, - value: WAYSEL, - }, - reserved16: u13, - /// Hit monitor enable. - HITMEN: u1, - /// Miss monitor enable. - MISSMEN: u1, - /// Hit monitor reset. - HITMRST: u1, - /// Miss monitor reset. - MISSMRST: u1, - padding: u12, + padding: u31, }), - /// ICACHE status register. - SR: mmio.Mmio(packed struct(u32) { - /// cache busy executing a full invalidate CACHEINV operation. - BUSYF: u1, - /// full invalidate CACHEINV operation finished. - BSYENDF: u1, - /// an error occurred during the operation. - ERRF: u1, - padding: u29, + /// DSI HOST Clock Control Register. + CCR: mmio.Mmio(packed struct(u32) { + /// TX Escape Clock Division. + TXECKDIV: u8, + /// Timeout Clock Division. + TOCKDIV: u8, + padding: u16, }), - /// ICACHE interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Interrupt enable on busy end. - BSYENDIE: u1, - /// Error interrupt on cache error. - ERRIE: u1, - padding: u29, + /// DSI Host LTDC VCID Register. + LVCIDR: mmio.Mmio(packed struct(u32) { + /// Virtual Channel ID. + VCID: u2, + padding: u30, }), - /// ICACHE flag clear register. - FCR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clear busy end flag. - CBSYENDF: u1, - /// Clear ERRF flag in SR. - CERRF: u1, - padding: u29, - }), - /// ICACHE hit monitor register. - HMONR: u32, - /// ICACHE miss monitor register. - MMONR: mmio.Mmio(packed struct(u32) { - /// Miss monitor register. - MISSMON: u16, - padding: u16, - }), - reserved32: [8]u8, - /// Cluster CRR%s, container region configuration registers. - CRR: [4]mmio.Mmio(packed struct(u32) { - /// base address for region. - BASEADDR: u8, - reserved9: u1, - /// size for region. - RSIZE: packed union { - raw: u3, - value: RSIZE, - }, - reserved15: u3, - /// enable for region. - REN: u1, - /// remapped address for region. - REMAPADDR: u11, - reserved28: u1, - /// AHB cache master selection for region. - MSTSEL: packed union { - raw: u1, - value: MSTSEL, - }, - reserved31: u2, - /// output burst type for region. - HBURST: packed union { - raw: u1, - value: HBURST, - }, + /// DSI Host LTDC Color Coding Register. + LCOLCR: mmio.Mmio(packed struct(u32) { + /// Color Coding. + COLC: u4, + reserved8: u4, + /// Loosely Packet Enable. + LPE: u1, + padding: u23, }), - }; - }; - - pub const syscfg_f7 = struct { - /// System configuration controller - pub const SYSCFG = extern struct { - /// memory remap register - MEMRMP: mmio.Mmio(packed struct(u32) { - /// Memory boot mapping - MEM_BOOT: u1, - reserved8: u7, - /// Flash bank mode selection - FB_MODE: u1, - reserved10: u1, - /// FMC memory mapping swap - SWP_FMC: u2, - padding: u20, + /// DSI Host LTDC Polarity Configuration Register. + LPCR: mmio.Mmio(packed struct(u32) { + /// Data Enable Polarity. + DEP: u1, + /// VSYNC Polarity. + VSP: u1, + /// HSYNC Polarity. + HSP: u1, + padding: u29, }), - /// peripheral mode configuration register - PMC: mmio.Mmio(packed struct(u32) { - /// I2C1_FMP I2C1 Fast Mode + Enable - I2C1_FMP: u1, - /// I2C2_FMP I2C2 Fast Mode + Enable - I2C2_FMP: u1, - /// I2C3_FMP I2C3 Fast Mode + Enable - I2C3_FMP: u1, - /// I2C4 Fast Mode + Enable - I2C4_FMP: u1, - /// PB6_FMP Fast Mode - PB6_FMP: u1, - /// PB7_FMP Fast Mode + Enable - PB7_FMP: u1, - /// PB8_FMP Fast Mode + Enable - PB8_FMP: u1, - /// Fast Mode + Enable - PB9_FMP: u1, + /// DSI Host Low-Power mode Configuration Register. + LPMCR: mmio.Mmio(packed struct(u32) { + /// VACT Largest Packet Size. + VLPSIZE: u8, reserved16: u8, - /// ADC3DC2 - ADC1DC2: u1, - /// ADC2DC2 - ADC2DC2: u1, - /// ADC3DC2 - ADC3DC2: u1, - reserved23: u4, - /// Ethernet PHY interface selection - MII_RMII_SEL: u1, + /// Largest Packet Size. + LPSIZE: u8, padding: u8, }), - /// external interrupt configuration register 1 - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration (x = 0 to 3) - EXTI: u4, - padding: u28, - }), - reserved32: [8]u8, - /// Compensation cell control register - CMPCR: mmio.Mmio(packed struct(u32) { - /// Compensation cell power-down - CMP_PD: u1, - reserved8: u7, - /// READY - READY: u1, - padding: u23, - }), - }; - }; - - pub const dma_v2 = struct { - pub const BURST = enum(u2) { - /// Single transfer - Single = 0x0, - /// Incremental burst of 4 beats - INCR4 = 0x1, - /// Incremental burst of 8 beats - INCR8 = 0x2, - /// Incremental burst of 16 beats - INCR16 = 0x3, - }; - - pub const CT = enum(u1) { - /// The current target memory is Memory 0 - Memory0 = 0x0, - /// The current target memory is Memory 1 - Memory1 = 0x1, - }; - - pub const DIR = enum(u2) { - /// Peripheral-to-memory - PeripheralToMemory = 0x0, - /// Memory-to-peripheral - MemoryToPeripheral = 0x1, - /// Memory-to-memory - MemoryToMemory = 0x2, - _, - }; - - pub const DMDIS = enum(u1) { - /// Direct mode is enabled - Enabled = 0x0, - /// Direct mode is disabled - Disabled = 0x1, - }; - - pub const FS = enum(u3) { - /// 0 < fifo_level < 1/4 - Quarter1 = 0x0, - /// 1/4 <= fifo_level < 1/2 - Quarter2 = 0x1, - /// 1/2 <= fifo_level < 3/4 - Quarter3 = 0x2, - /// 3/4 <= fifo_level < full - Quarter4 = 0x3, - /// FIFO is empty - Empty = 0x4, - /// FIFO is full - Full = 0x5, - _, - }; - - pub const FTH = enum(u2) { - /// 1/4 full FIFO - Quarter = 0x0, - /// 1/2 full FIFO - Half = 0x1, - /// 3/4 full FIFO - ThreeQuarters = 0x2, - /// Full FIFO - Full = 0x3, - }; - - pub const PFCTRL = enum(u1) { - /// The DMA is the flow controller - DMA = 0x0, - /// The peripheral is the flow controller - Peripheral = 0x1, - }; - - pub const PINCOS = enum(u1) { - /// The offset size for the peripheral address calculation is linked to the PSIZE - PSIZE = 0x0, - /// The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) - Fixed4 = 0x1, - }; - - pub const PL = enum(u2) { - /// Low - Low = 0x0, - /// Medium - Medium = 0x1, - /// High - High = 0x2, - /// Very high - VeryHigh = 0x3, - }; - - pub const SIZE = enum(u2) { - /// Byte (8-bit) - Bits8 = 0x0, - /// Half-word (16-bit) - Bits16 = 0x1, - /// Word (32-bit) - Bits32 = 0x2, - _, - }; - - /// DMA controller - pub const DMA = extern struct { - /// low interrupt status register - ISR: [2]mmio.Mmio(packed struct(u32) { - /// Stream x FIFO error interrupt flag (x=3..0) - FEIF: u1, - reserved2: u1, - /// Stream x direct mode error interrupt flag (x=3..0) - DMEIF: u1, - /// Stream x transfer error interrupt flag (x=3..0) - TEIF: u1, - /// Stream x half transfer interrupt flag (x=3..0) - HTIF: u1, - /// Stream x transfer complete interrupt flag (x = 3..0) - TCIF: u1, - padding: u26, + reserved44: [16]u8, + /// DSI Host Protocol Configuration Register. + PCR: mmio.Mmio(packed struct(u32) { + /// EoTp Transmission Enable. + ETTXE: u1, + /// EoTp Reception Enable. + ETRXE: u1, + /// Bus Turn Around Enable. + BTAE: u1, + /// ECC Reception Enable. + ECCRXE: u1, + /// CRC Reception Enable. + CRCRXE: u1, + padding: u27, }), - /// low interrupt flag clear register - IFCR: [2]mmio.Mmio(packed struct(u32) { - /// Stream x FIFO error interrupt flag (x=3..0) - FEIF: u1, - reserved2: u1, - /// Stream x direct mode error interrupt flag (x=3..0) - DMEIF: u1, - /// Stream x transfer error interrupt flag (x=3..0) - TEIF: u1, - /// Stream x half transfer interrupt flag (x=3..0) - HTIF: u1, - /// Stream x transfer complete interrupt flag (x = 3..0) - TCIF: u1, - padding: u26, + /// DSI Host Generic VCID Register. + GVCIDR: mmio.Mmio(packed struct(u32) { + /// Virtual Channel ID. + VCID: u2, + padding: u30, }), - /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers - ST: u32, - }; - - /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers - pub const ST = extern struct { - /// stream x configuration register - CR: mmio.Mmio(packed struct(u32) { - /// Stream enable / flag stream ready when read low - EN: u1, - /// Direct mode error interrupt enable - DMEIE: u1, - /// Transfer error interrupt enable - TEIE: u1, - /// Half transfer interrupt enable - HTIE: u1, - /// Transfer complete interrupt enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: packed union { - raw: u1, - value: PFCTRL, - }, - /// Data transfer direction - DIR: packed union { - raw: u2, - value: DIR, - }, - /// Circular mode enabled - CIRC: u1, - /// Peripheral increment mode enabled - PINC: u1, - /// Memory increment mode enabled - MINC: u1, - /// Peripheral data size - PSIZE: packed union { - raw: u2, - value: SIZE, - }, - /// Memory data size - MSIZE: packed union { - raw: u2, - value: SIZE, - }, - /// Peripheral increment offset size - PINCOS: packed union { - raw: u1, - value: PINCOS, - }, - /// Priority level - PL: packed union { - raw: u2, - value: PL, - }, - /// Double buffer mode enabled - DBM: u1, - /// Current target (only in double buffer mode) - CT: packed union { - raw: u1, - value: CT, - }, - reserved21: u1, - /// Peripheral burst transfer configuration - PBURST: packed union { - raw: u2, - value: BURST, - }, - /// Memory burst transfer configuration - MBURST: packed union { - raw: u2, - value: BURST, - }, - /// Channel selection - CHSEL: u4, - padding: u3, + /// DSI Host mode Configuration Register. + MCR: mmio.Mmio(packed struct(u32) { + /// Command mode. + CMDM: u1, + padding: u31, }), - /// stream x number of data register - NDTR: mmio.Mmio(packed struct(u32) { - /// Number of data items to transfer - NDT: u16, - padding: u16, + /// DSI Host Video mode Configuration Register. + VMCR: mmio.Mmio(packed struct(u32) { + /// Video mode Type. + VMT: u2, + reserved8: u6, + /// Low-Power Vertical Sync Active Enable. + LPVSAE: u1, + /// Low-power Vertical Back-Porch Enable. + LPVBPE: u1, + /// Low-power Vertical Front-porch Enable. + LPVFPE: u1, + /// Low-Power Vertical Active Enable. + LPVAE: u1, + /// Low-Power Horizontal Back-Porch Enable. + LPHBPE: u1, + /// Low-Power Horizontal Front-Porch Enable. + LPHFPE: u1, + /// Frame Bus-Turn-Around Acknowledge Enable. + FBTAAE: u1, + /// Low-Power Command Enable. + LPCE: u1, + /// Pattern Generator Enable. + PGE: u1, + reserved20: u3, + /// Pattern Generator mode. + PGM: u1, + reserved24: u3, + /// Pattern Generator Orientation. + PGO: u1, + padding: u7, }), - /// stream x peripheral address register - PAR: u32, - /// stream x memory 0 address register - M0AR: u32, - /// stream x memory 1 address register - M1AR: u32, - /// stream x FIFO control register - FCR: mmio.Mmio(packed struct(u32) { - /// FIFO threshold selection - FTH: packed union { - raw: u2, - value: FTH, - }, - /// Direct mode disable - DMDIS: packed union { - raw: u1, - value: DMDIS, - }, - /// FIFO status - FS: packed union { - raw: u3, - value: FS, - }, - reserved7: u1, - /// FIFO error interrupt enable - FEIE: u1, - padding: u24, + /// DSI Host Video Packet Configuration Register. + VPCR: mmio.Mmio(packed struct(u32) { + /// Video Packet Size. + VPSIZE: u14, + padding: u18, }), - }; - }; - - pub const adc_u5 = struct { - /// ADC. - pub const ADC = extern struct { - /// ADC interrupt and status register. - ISR: mmio.Mmio(packed struct(u32) { - /// ADRDY. - ADRDY: u1, - /// EOSMP. - EOSMP: u1, - /// EOC. - EOC: u1, - /// EOS. - EOS: u1, - /// OVR. - OVR: u1, - reserved7: u2, - /// AWD1. - AWD1: u1, - /// AWD2. - AWD2: u1, - /// AWD3. - AWD3: u1, - reserved11: u1, - /// EOCAL. - EOCAL: u1, - /// LDORDY. - LDORDY: u1, + /// DSI Host Video Chunks Configuration Register. + VCCR: mmio.Mmio(packed struct(u32) { + /// Number of Chunks. + NUMC: u13, padding: u19, }), - /// ADC interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// ADRDYIE. - ADRDYIE: u1, - /// EOSMPIE. - EOSMPIE: u1, - /// EOCIE. - EOCIE: u1, - /// EOSIE. - EOSIE: u1, - /// OVRIE. - OVRIE: u1, - reserved7: u2, - /// AWD1IE. - AWD1IE: u1, - /// AWD2IE. - AWD2IE: u1, - /// AWD3IE. - AWD3IE: u1, - reserved11: u1, - /// EOCALIE. - EOCALIE: u1, - /// LDORDYIE. - LDORDYIE: u1, + /// DSI Host Video Null Packet Configuration Register. + VNPCR: mmio.Mmio(packed struct(u32) { + /// Null Packet Size. + NPSIZE: u13, padding: u19, }), - /// ADC control register. - CR: mmio.Mmio(packed struct(u32) { - /// ADEN. - ADEN: u1, - /// ADDIS. - ADDIS: u1, - /// ADSTART. - ADSTART: u1, - reserved4: u1, - /// ADSTP. - ADSTP: u1, - reserved28: u23, - /// ADVREGEN. - ADVREGEN: u1, - reserved31: u2, - /// ADCAL. - ADCAL: u1, - }), - /// ADC configuration register. - CFGR1: mmio.Mmio(packed struct(u32) { - /// DMAEN. - DMAEN: u1, - /// DMACFG. - DMACFG: u1, - /// RES. - RES: u2, - /// SCANDIR. - SCANDIR: u1, - /// ALIGN. - ALIGN: u1, - /// EXTSEL. - EXTSEL: u3, - reserved10: u1, - /// EXTEN. - EXTEN: u2, - /// OVRMOD. - OVRMOD: u1, - /// CONT. - CONT: u1, - /// WAIT. - WAIT: u1, - reserved16: u1, - /// DISCEN. - DISCEN: u1, - reserved21: u4, - /// CHSELRMOD. - CHSELRMOD: u1, - /// AWD1SGL. - AWD1SGL: u1, - /// AWD1EN. - AWD1EN: u1, - reserved26: u2, - /// AWD1CH. - AWD1CH: u5, - padding: u1, + /// DSI Host Video HSA Configuration Register. + VHSACR: mmio.Mmio(packed struct(u32) { + /// Horizontal Synchronism Active duration. + HSA: u12, + padding: u20, }), - /// ADC configuration register 2. - CFGR2: mmio.Mmio(packed struct(u32) { - /// OVSE. - OVSE: u1, - reserved2: u1, - /// OVSR. - OVSR: u3, - /// OVSS. - OVSS: u4, - /// TOVS. - TOVS: u1, - reserved29: u19, - /// LFTRIG. - LFTRIG: u1, - padding: u2, + /// DSI Host Video HBP Configuration Register. + VHBPCR: mmio.Mmio(packed struct(u32) { + /// Horizontal Back-Porch duration. + HBP: u12, + padding: u20, }), - /// ADC sample time register. - SMPR: mmio.Mmio(packed struct(u32) { - /// SMP1. - SMP1: u3, - reserved4: u1, - /// SMP2. - SMP2: u3, - reserved8: u1, - /// SMPSEL0. - SMPSEL0: u1, - /// SMPSEL1. - SMPSEL1: u1, - /// SMPSEL2. - SMPSEL2: u1, - /// SMPSEL3. - SMPSEL3: u1, - /// SMPSEL4. - SMPSEL4: u1, - /// SMPSEL5. - SMPSEL5: u1, - /// SMPSEL6. - SMPSEL6: u1, - /// SMPSEL7. - SMPSEL7: u1, - /// SMPSEL8. - SMPSEL8: u1, - /// SMPSEL9. - SMPSEL9: u1, - /// SMPSEL10. - SMPSEL10: u1, - /// SMPSEL11. - SMPSEL11: u1, - /// SMPSEL12. - SMPSEL12: u1, - /// SMPSEL13. - SMPSEL13: u1, - /// SMPSEL14. - SMPSEL14: u1, - /// SMPSEL15. - SMPSEL15: u1, - /// SMPSEL16. - SMPSEL16: u1, - /// SMPSEL17. - SMPSEL17: u1, - /// SMPSEL18. - SMPSEL18: u1, - /// SMPSEL19. - SMPSEL19: u1, - /// SMPSEL20. - SMPSEL20: u1, - /// SMPSEL21. - SMPSEL21: u1, - /// SMPSEL22. - SMPSEL22: u1, - /// SMPSEL23. - SMPSEL23: u1, + /// DSI Host Video Line Configuration Register. + VLCR: mmio.Mmio(packed struct(u32) { + /// Horizontal Line duration. + HLINE: u15, + padding: u17, }), - reserved32: [8]u8, - /// ADC watchdog threshold register. - AWD1TR: mmio.Mmio(packed struct(u32) { - /// LT1. - LT1: u12, - reserved16: u4, - /// HT1. - HT1: u12, - padding: u4, + /// DSI Host Video VSA Configuration Register. + VVSACR: mmio.Mmio(packed struct(u32) { + /// Vertical Synchronism Active duration. + VSA: u10, + padding: u22, }), - /// ADC watchdog threshold register. - AWD2TR: mmio.Mmio(packed struct(u32) { - /// LT2. - LT2: u12, - reserved16: u4, - /// HT2. - HT2: u12, - padding: u4, + /// DSI Host Video VBP Configuration Register. + VVBPCR: mmio.Mmio(packed struct(u32) { + /// Vertical Back-Porch duration. + VBP: u10, + padding: u22, }), - /// ADC channel selection register [alternate]. - CHSELRMOD0: mmio.Mmio(packed struct(u32) { - /// CHSEL. - CHSEL: u24, - padding: u8, + /// DSI Host Video VFP Configuration Register. + VVFPCR: mmio.Mmio(packed struct(u32) { + /// Vertical Front-Porch duration. + VFP: u10, + padding: u22, }), - /// ADC watchdog threshold register. - AWD3TR: mmio.Mmio(packed struct(u32) { - /// LT3. - LT3: u12, - reserved16: u4, - /// HT3. - HT3: u12, - padding: u4, + /// DSI Host Video VA Configuration Register. + VVACR: mmio.Mmio(packed struct(u32) { + /// Vertical Active duration. + VA: u14, + padding: u18, }), - reserved64: [16]u8, - /// ADC data register. - DR: mmio.Mmio(packed struct(u32) { - /// DATA. - DATA: u16, + /// DSI Host LTDC Command Configuration Register. + LCCR: mmio.Mmio(packed struct(u32) { + /// Command Size. + CMDSIZE: u16, padding: u16, }), - /// ADC data register. - PWRR: mmio.Mmio(packed struct(u32) { - /// AUTOFF. - AUTOFF: u1, - /// DPD. - DPD: u1, - /// VREFPROT. - VREFPROT: u1, - /// VREFSECSMP. - VREFSECSMP: u1, - padding: u28, + /// DSI Host Command mode Configuration Register. + CMCR: mmio.Mmio(packed struct(u32) { + /// Tearing Effect Acknowledge Request Enable. + TEARE: u1, + /// Acknowledge Request Enable. + ARE: u1, + reserved8: u6, + /// Generic Short Write Zero parameters Transmission. + GSW0TX: u1, + /// Generic Short Write One parameters Transmission. + GSW1TX: u1, + /// Generic Short Write Two parameters Transmission. + GSW2TX: u1, + /// Generic Short Read Zero parameters Transmission. + GSR0TX: u1, + /// Generic Short Read One parameters Transmission. + GSR1TX: u1, + /// Generic Short Read Two parameters Transmission. + GSR2TX: u1, + /// Generic Long Write Transmission. + GLWTX: u1, + reserved16: u1, + /// DCS Short Write Zero parameter Transmission. + DSW0TX: u1, + /// DCS Short Read One parameter Transmission. + DSW1TX: u1, + /// DCS Short Read Zero parameter Transmission. + DSR0TX: u1, + /// DCS Long Write Transmission. + DLWTX: u1, + reserved24: u4, + /// Maximum Read Packet Size. + MRDPS: u1, + padding: u7, }), - reserved160: [88]u8, - /// ADC Analog Watchdog 2 Configuration register. - AWD2CR: mmio.Mmio(packed struct(u32) { - /// AWD2CH0. - AWD2CH0: u1, - /// AWD2CH1. - AWD2CH1: u1, - /// AWD2CH2. - AWD2CH2: u1, - /// AWD2CH3. - AWD2CH3: u1, - /// AWD2CH4. - AWD2CH4: u1, - /// AWD2CH5. - AWD2CH5: u1, - /// AWD2CH6. - AWD2CH6: u1, - /// AWD2CH7. - AWD2CH7: u1, - /// AWD2CH8. - AWD2CH8: u1, - /// AWD2CH9. - AWD2CH9: u1, - /// AWD2CH10. - AWD2CH10: u1, - /// AWD2CH11. - AWD2CH11: u1, - /// AWD2CH12. - AWD2CH12: u1, - /// AWD2CH13. - AWD2CH13: u1, - /// AWD2CH14. - AWD2CH14: u1, - /// AWD2CH15. - AWD2CH15: u1, - /// AWD2CH16. - AWD2CH16: u1, - /// AWD2CH17. - AWD2CH17: u1, - /// AWD2CH18. - AWD2CH18: u1, - /// AWD2CH19. - AWD2CH19: u1, - /// AWD2CH20. - AWD2CH20: u1, - /// AWD2CH21. - AWD2CH21: u1, - /// AWD2CH22. - AWD2CH22: u1, - /// AWD2CH23. - AWD2CH23: u1, + /// DSI Host Generic Header Configuration Register. + GHCR: mmio.Mmio(packed struct(u32) { + /// Type. + DT: u6, + /// Channel. + VCID: u2, + /// WordCount LSB. + WCLSB: u8, + /// WordCount MSB. + WCMSB: u8, padding: u8, }), - /// ADC Analog Watchdog 3 Configuration register. - AWD3CR: mmio.Mmio(packed struct(u32) { - /// AWD3CH0. - AWD3CH0: u1, - /// AWD3CH1. - AWD3CH1: u1, - /// AWD3CH2. - AWD3CH2: u1, - /// AWD3CH3. - AWD3CH3: u1, - /// AWD3CH4. - AWD3CH4: u1, - /// AWD3CH5. - AWD3CH5: u1, - /// AWD3CH6. - AWD3CH6: u1, - /// AWD3CH7. - AWD3CH7: u1, - /// AWD3CH8. - AWD3CH8: u1, - /// AWD3CH9. - AWD3CH9: u1, - /// AWD3CH10. - AWD3CH10: u1, - /// AWD3CH11. - AWD3CH11: u1, - /// AWD3CH12. - AWD3CH12: u1, - /// AWD3CH13. - AWD3CH13: u1, - /// AWD3CH14. - AWD3CH14: u1, - /// AWD3CH15. - AWD3CH15: u1, - /// AWD3CH16. - AWD3CH16: u1, - /// AWD3CH17. - AWD3CH17: u1, - /// AWD3CH18. - AWD3CH18: u1, - /// AWD3CH19. - AWD3CH19: u1, - /// AWD3CH20. - AWD3CH20: u1, - /// AWD3CH21. - AWD3CH21: u1, - /// AWD3CH22. - AWD3CH22: u1, - /// AWD3CH23. - AWD3CH23: u1, - padding: u8, + /// DSI Host Generic Payload Data Register. + GPDR: mmio.Mmio(packed struct(u32) { + /// Payload Byte 1. + DATA1: u8, + /// Payload Byte 2. + DATA2: u8, + /// Payload Byte 3. + DATA3: u8, + /// Payload Byte 4. + DATA4: u8, }), - reserved196: [28]u8, - /// ADC Calibration factor. - CALFACT: mmio.Mmio(packed struct(u32) { - /// CALFACT. - CALFACT: u7, + /// DSI Host Generic Packet Status Register. + GPSR: mmio.Mmio(packed struct(u32) { + /// Command FIFO Empty. + CMDFE: u1, + /// Command FIFO Full. + CMDFF: u1, + /// Payload Write FIFO Empty. + PWRFE: u1, + /// Payload Write FIFO Full. + PWRFF: u1, + /// Payload Read FIFO Empty. + PRDFE: u1, + /// Payload Read FIFO Full. + PRDFF: u1, + /// Read Command Busy. + RCB: u1, padding: u25, }), - reserved208: [8]u8, - /// ADC option register. - OR: mmio.Mmio(packed struct(u32) { - /// CHN21SEL. - CHN21SEL: u1, - padding: u31, + /// DSI Host Timeout Counter Configuration Register 0. + TCCR0: mmio.Mmio(packed struct(u32) { + /// Low-power Reception Timeout Counter. + LPRX_TOCNT: u16, + /// High-Speed Transmission Timeout Counter. + HSTX_TOCNT: u16, }), - reserved776: [564]u8, - /// ADC common configuration register. - CCR: mmio.Mmio(packed struct(u32) { - reserved18: u18, - /// PRESC. - PRESC: u4, - /// VREFEN. - VREFEN: u1, - /// VSENSESEL. - VSENSESEL: u1, - /// VBATEN. - VBATEN: u1, + /// DSI Host Timeout Counter Configuration Register 1. + TCCR1: mmio.Mmio(packed struct(u32) { + /// High-Speed Read Timeout Counter. + HSRD_TOCNT: u16, + padding: u16, + }), + /// DSI Host Timeout Counter Configuration Register 2. + TCCR2: mmio.Mmio(packed struct(u32) { + /// Low-Power Read Timeout Counter. + LPRD_TOCNT: u16, + padding: u16, + }), + /// DSI Host Timeout Counter Configuration Register 3. + TCCR3: mmio.Mmio(packed struct(u32) { + /// High-Speed Write Timeout Counter. + HSWR_TOCNT: u16, + reserved24: u8, + /// Presp mode. + PM: u1, padding: u7, }), - }; - }; - - pub const flash_h5 = struct { - pub const BOOTR_SECBOOT_LOCK = enum(u8) { - /// The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). - B_0xB4 = 0xb4, - /// The BOOT_UBE, SWAP_ BANK and SECBOOTADD can still be modified following their individual rules. - B_0xC3 = 0xc3, - _, - }; - - pub const CODE_OP = enum(u3) { - /// No flash operation on going during previous reset - B_0x0 = 0x0, - /// Single write operation interrupted - B_0x1 = 0x1, - /// OBK alternate sector erase - B_0x2 = 0x2, - /// Sector erase operation interrupted - B_0x3 = 0x3, - /// Bank erase operation interrupted - B_0x4 = 0x4, - /// Mass erase operation interrupted - B_0x5 = 0x5, - /// Option change operation interrupted - B_0x6 = 0x6, - /// OBK swap sector request - B_0x7 = 0x7, - }; - - pub const NSBOOTR_NSBOOT_LOCK = enum(u8) { - /// The NSBOOTADD is frozen. SWAP_ BANK can only be modified with TZEN set to 0xB4 (enabled). - B_0xB4 = 0xb4, - /// The SWAP_ BANK and NSBOOTADD can still be modified following their individual rules. - B_0xC3 = 0xc3, - _, - }; - - pub const NSCR_BKSEL = enum(u1) { - /// Bank1 is selected for Bank erase / sector erase / interrupt enable - B_0x0 = 0x0, - /// Bank2 is selected for BER / SER - B_0x1 = 0x1, - }; - - pub const NSPRIV = enum(u1) { - /// access to non secure registers is always granted - B_0x0 = 0x0, - /// access to non secure registers is denied in case of unprivileged access. - B_0x1 = 0x1, - }; - - pub const OPTCR_SWAP_BANK = enum(u1) { - /// Bank1 and Bank2 not swapped - B_0x0 = 0x0, - /// Bank1 and Bank2 swapped - B_0x1 = 0x1, - }; - - pub const OPTSR_BKPRAM_ECC = enum(u1) { - /// BKPRAM ECC check enabled - B_0x0 = 0x0, - /// BKPRAM ECC check disabled - B_0x1 = 0x1, - }; - - pub const OPTSR_BOOT_UBE = enum(u8) { - /// OEM-iRoT (user flash) selected. In Open PRODUCT_STATE this value selects bootloader. Defaut value. - B_0xB4 = 0xb4, - /// ST-iRoT (system flash) selected - B_0xC3 = 0xc3, - _, - }; - - pub const OPTSR_BOR_LEV = enum(u2) { - /// BOR Level 2, the threshold level is medium (around 2.4 V) - B_0x1 = 0x1, - /// BOR Level 3, the threshold level is high (around 2.7 V) - B_0x2 = 0x2, - _, - }; - - pub const OPTSR_IO_VDDIO_HSLV = enum(u1) { - /// High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7�V) - B_0x0 = 0x0, - /// High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7�V) - B_0x1 = 0x1, - }; - - pub const OPTSR_IO_VDD_HSLV = enum(u1) { - /// High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7�V) - B_0x0 = 0x0, - /// High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7�V) - B_0x1 = 0x1, - }; - - pub const OPTSR_IWDG_STDBY = enum(u1) { - /// Independent watchdog frozen in Standby mode - B_0x0 = 0x0, - /// Independent watchdog keep running in Standby mode. - B_0x1 = 0x1, - }; - - pub const OPTSR_IWDG_STOP = enum(u1) { - /// Independent watchdog frozen in system Stop mode - B_0x0 = 0x0, - /// Independent watchdog keep running in system Stop mode. - B_0x1 = 0x1, - }; - - pub const OPTSR_IWDG_SW = enum(u1) { - /// IWDG watchdog is controlled by hardware - B_0x0 = 0x0, - /// IWDG watchdog is controlled by software - B_0x1 = 0x1, - }; - - pub const OPTSR_NRST_STDBY = enum(u1) { - /// a reset is generated when entering Standby mode on core domain - B_0x0 = 0x0, - /// no reset generated when entering Standby mode on core domain. - B_0x1 = 0x1, - }; - - pub const OPTSR_NRST_STOP = enum(u1) { - /// a reset is generated when entering Stop mode on core domain - B_0x0 = 0x0, - /// no reset generated when entering Stop mode on core domain. - B_0x1 = 0x1, - }; - - pub const OPTSR_SRAM_ECC = enum(u1) { - /// SRAM2 ECC check enabled - B_0x0 = 0x0, - /// SRAM2 ECC check disabled - B_0x1 = 0x1, - }; - - pub const OPTSR_SWAP_BANK = enum(u1) { - /// Bank1 and Bank2 not swapped - B_0x0 = 0x0, - /// Bank1 and Bank2 swapped - B_0x1 = 0x1, - }; - - pub const OPTSR_TZEN = enum(u8) { - /// TrustZone enabled. - B_0xB4 = 0xb4, - /// TrustZone disabled - B_0xC3 = 0xc3, - _, - }; - - pub const OPTSR_WWDG_SW = enum(u1) { - /// WWDG watchdog is controlled by hardware - B_0x0 = 0x0, - /// WWDG watchdog is controlled by software - B_0x1 = 0x1, - }; - - pub const PRIVBBR_PRIVBB = enum(u32) { - /// sectors (32 * (x-1) + y) in bank 2 is unprivileged - B_0x0 = 0x0, - /// sector (32 * (x-1) + y) in bank 2 is privileged - B_0x1 = 0x1, - _, - }; - - pub const SECBBR_SECBB = enum(u32) { - /// sectors (32 * (x-1) + y) in bank 2 is non secure - B_0x0 = 0x0, - /// sector (32 * (x-1) + y) in bank 2 is secure - B_0x1 = 0x1, - _, - }; - - pub const SECBOOTR_SECBOOT_LOCK = enum(u8) { - /// The BOOT_UBE and SECBOOTADD are frozen. SWAP_ BANK can only be modified with TZEN set to 0xC3 (disabled). - B_0xB4 = 0xb4, - /// The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. - B_0xC3 = 0xc3, - _, - }; - - pub const SECCR_BKSEL = enum(u1) { - /// Bank1 is selected for Bank erase / sector erase / interrupt enable - B_0x0 = 0x0, - /// Bank2 is selected for BER / SER - B_0x1 = 0x1, - }; - - pub const SPRIV = enum(u1) { - /// access to secure registers is always granted - B_0x0 = 0x0, - /// access to secure registers is denied in case of unprivileged access. - B_0x1 = 0x1, - }; - - /// FLASH address block description - pub const FLASH = extern struct { - /// FLASH access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Read latency These bits are used to control the number of wait states used during read operations on both nonvolatile memory banks. The application software has to program them to the correct value depending on the embedded flash memory interface frequency and voltage conditions. ... Note: No check is performed by hardware to verify that the configuration is correct. - LATENCY: u4, - /// Flash signal delay These bits are used to control the delay between nonvolatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded flash memory interface frequency. Please refer to Table�44 for details. Note: No check is performed to verify that the configuration is correct. Note: Two WRHIGHFREQ values can be selected for some frequencies. - WRHIGHFREQ: u2, - reserved8: u2, - /// Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account. Bits used to control the prefetch. - PRFTEN: u1, - padding: u23, + /// DSI Host Timeout Counter Configuration Register 4. + TCCR4: mmio.Mmio(packed struct(u32) { + /// Low-Power Write Timeout Counter. + LSWR_TOCNT: u16, + padding: u16, }), - /// FLASH non-secure key register - NSKEYR: u32, - /// FLASH secure key register - SECKEYR: u32, - /// FLASH option key register - OPTKEYR: u32, - /// FLASH non-secure OBK key register - NSOBKKEYR: u32, - /// FLASH secure OBK key register - SECOBKKEYR: u32, - /// FLASH operation status register - OPSR: mmio.Mmio(packed struct(u32) { - /// Interrupted operation address - ADDR_OP: u20, - reserved21: u1, - /// Flash high-cycle data area operation interrupted It indicates if flash high-cycle data area is concerned by operation. - DATA_OP: u1, - /// Interrupted operation bank It indicates which bank was concerned by operation. - BK_OP: u1, - /// Operation in system flash memory interrupted Indicates that reset interrupted an ongoing operation in system flash. - SYSF_OP: u1, - /// OTP operation interrupted Indicates that reset interrupted an ongoing operation in OTP area (or OBKeys area). - OTP_OP: u1, - reserved29: u4, - /// Flash memory operation code - CODE_OP: packed union { - raw: u3, - value: CODE_OP, - }, + /// DSI Host Timeout Counter Configuration Register 5. + TCCR5: mmio.Mmio(packed struct(u32) { + /// Bus-Turn-Around Timeout Counter. + BTA_TOCNT: u16, + padding: u16, }), - /// FLASH option control register - OPTCR: mmio.Mmio(packed struct(u32) { - /// FLASH_OPTCR lock option configuration bit The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset. It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change. - OPTLOCK: u1, - /// Option byte start change option configuration bit OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It is set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It is reseted at the same time as BSY bit. The user application cannot modify any FLASH_XXX_PRG flash interface register until the option change operation has been completed. Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in nonvolatile memory. - OPTSTRT: u1, - reserved31: u29, - /// Bank swapping option configuration bit SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR. - SWAP_BANK: packed union { - raw: u1, - value: OPTCR_SWAP_BANK, - }, + reserved148: [4]u8, + /// DSI Host Clock Lane Configuration Register. + CLCR: mmio.Mmio(packed struct(u32) { + /// D-PHY Clock Control. + DPCC: u1, + /// Automatic Clock lane Control. + ACR: u1, + padding: u30, }), - /// FLASH non-secure status register - NSSR: mmio.Mmio(packed struct(u32) { - /// busy flag BSY flag indicates that a flash memory is busy by an operation (write, erase, option byte change, OBK operation). It is set at the beginning of a flash memory operation and cleared when the operation finishes, or an error occurs. - BSY: u1, - /// write buffer not empty flag WBNE flag is set when the flash interface is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_NSCR the embedded flash memory detects an error that involves data loss This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. - WBNE: u1, - reserved3: u1, - /// data buffer not empty flag DBNE flag is set when the flash interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free. - DBNE: u1, - reserved16: u12, - /// end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register. - EOP: u1, - /// write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR. - WRPERR: u1, - /// programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR. - PGSERR: u1, - /// strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR. - STRBERR: u1, - /// inconsistency error flag NSINCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears NSINCERR. - INCERR: u1, - /// OBK general error flag OBKERR flag is raised when the OBK-HDPL signal from the SBS does not match the HDPL value associated with the key slot during access to the key location. Alternatively also when the ALT_SECT is unexpectedly changed while the write buffer is being filled. - OBKERR: u1, - /// OBK write error flag OBKWERR flag is raised when the address is not virgin on a write access to the OBK storage. Alternatively also when the OBK selector in the alternate sector is not virgin during a swap operation. - OBKWERR: u1, - /// Option byte change error flag OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1. Writing 1 to CLR_OPTCHANGEERR of register FLASH_NSCCR clears OPTCHANGEERR. Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set. - OPTCHANGEERR: u1, - padding: u8, + /// DSI Host Clock Lane Timer Configuration Register. + CLTCR: mmio.Mmio(packed struct(u32) { + /// Low-Power to High-Speed Time. + LP2HS_TIME: u10, + reserved16: u6, + /// High-Speed to Low-Power Time. + HS2LP_TIME: u10, + padding: u6, }), - /// FLASH secure status register - SECSR: mmio.Mmio(packed struct(u32) { - /// busy flag BSY flag indicates that a FLASH memory is busy (write, erase, option byte change, OBK operations). It is set at the beginning of a flash memory operation and cleared when the operation finishes or an error occurs. - BSY: u1, - /// write buffer not empty flag WBNE flag is set when the flash interface is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_SECCR the flash interface detects an error that involves data loss This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. - WBNE: u1, - reserved3: u1, - /// data buffer not empty flag DBNE flag is set when the embedded flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free. - DBNE: u1, - reserved16: u12, - /// end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register. - EOP: u1, - /// write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR. - WRPERR: u1, - /// programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR. - PGSERR: u1, - /// strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR. - STRBERR: u1, - /// inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR. - INCERR: u1, - /// OBK general error flag OBKERR flag is raised when the OBK-HDPL signal from the SBS does not match the HDPL value associated with the key slot during access to the key location. Alternatively also when the ALT_SECT is unexpectedly changed while the write buffer is being filled. - OBKERR: u1, - /// OBK write error flag OBKWERR flag is raised when the address is not virgin on a write access to the OBK storage. Alternatively also when the OBK selector in the alternate sector is not virgin during a swap operation. - OBKWERR: u1, - padding: u9, + /// DSI Host Data Lane Timer Configuration Register. + DLTCR: mmio.Mmio(packed struct(u32) { + /// Maximum Read Time. + MRD_TIME: u15, + reserved16: u1, + /// Low-Power To High-Speed Time. + LP2HS_TIME: u8, + /// High-Speed To Low-Power Time. + HS2LP_TIME: u8, }), - /// FLASH non-secure control register - NSCR: mmio.Mmio(packed struct(u32) { - /// configuration lock bit This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change. - LOCK: u1, - /// programming control bit PG can be programmed only when LOCK is cleared to 0. PG allows programming in Bank1 and Bank2. - PG: u1, - /// sector erase request Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. - SER: u1, - /// erase request Setting BER bit to 1 requests a bank erase operation (user flash memory only). BER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. Note: Write protection error is triggered when a bank erase is required and some sectors are protected. - BER: u1, - /// write forcing control bit FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. The embedded flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error. Write forcing is effective only if the write buffer is not empty and was filled by non-secure access (in particular, FW does not start several write operations when the force-write operations are performed consecutively). Since there is just one write buffer, FW can force a write in bank1 or bank2. - FW: u1, - /// erase start control bit STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software. - STRT: u1, - /// sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0. .. - SNB: u7, - reserved15: u2, - /// Mass erase request Setting MER bit to 1 requests a mass erase operation (user flash memory only). MER can be programmed only when LOCK is cleared to 0. If BER or SER are both set, a PGSERR is raised. Error is triggered when a mass erase is required and some sectors are protected. - MER: u1, - /// end of operation interrupt control bit Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0. - EOPIE: u1, - /// write protection error interrupt enable bit When this bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0. - WRPERRIE: u1, - /// programming sequence error interrupt enable bit When this bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0. - PGSERRIE: u1, - /// strobe error interrupt enable bit When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0. - STRBERRIE: u1, - /// inconsistency error interrupt enable bit When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0. - INCERRIE: u1, - /// OBK general error interrupt enable bit OBKERRIE enables generating an interrupt in case of OBK specific access error. This bit can be programmed only when LOCK bit is cleared to 0. - OBKERRIE: u1, - /// OBK write error interrupt enable bit OBKWERRIE enables generation of interrupt in case of OBK specific write error. This bit can be programmed only when LOCK bit is cleared to 0. - OBKWERRIE: u1, - /// Option byte change error interrupt enable bit This bit controls if an interrupt must be generated when an error occurs during an option byte change. It can be programmed only when LOCK bit is cleared to 0. - OPTCHANGEERRIE: u1, - reserved31: u7, - /// Bank selector bit BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored. - BKSEL: packed union { - raw: u1, - value: NSCR_BKSEL, - }, + /// DSI Host PHY Control Register. + PCTLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Digital Enable. + DEN: u1, + /// Clock Enable. + CKE: u1, + padding: u29, }), - /// FLASH secure control register - SECCR: mmio.Mmio(packed struct(u32) { - /// configuration lock bit This bit locks the FLASH_SECCR register. The correct write sequence to FLASH_SECKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_SECCR register do not change. - LOCK: u1, - /// programming control bit PG can be programmed only when LOCK is cleared to 0. PG allows programming in Bank1 and Bank2. - PG: u1, - /// sector erase request Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. If BER and MER are also set, a PGSERR is raised. - SER: u1, - /// erase request Setting BER bit to 1 requests a bank erase operation (user flash memory only). BER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. Note: Write protection error is triggered when a bank erase is required and some sectors are protected. - BER: u1, - /// write forcing control bit FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. The embedded flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error. Write forcing is effective only if the write buffer is not empty and was filled by secure access (in particular, FW does not start several write operations when the force-write operations are performed consecutively). Since there is just one write buffer, FW can force a write in bank1 or bank2. - FW: u1, - /// erase start control bit STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. STRT is reseted at the end of the operation or when an error occurs. It cannot be reset by software. - STRT: u1, - /// sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0. .. - SNB: u7, - reserved15: u2, - /// mass erase request Setting MER bit to 1 requests a mass erase operation (user flash memory only). MER can be programmed only when LOCK is cleared to 0. If BER or SER are also set, a PGSERR is raised. Error is triggered when a mass erase is required and some sectors are protected. - MER: u1, - /// end of operation interrupt control bit Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program/erase operation. EOPIE can be programmed only when LOCK is cleared to 0. - EOPIE: u1, - /// write protection error interrupt enable bit When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0. - WRPERRIE: u1, - /// programming sequence error interrupt enable bit When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0. - PGSERRIE: u1, - /// strobe error interrupt enable bit When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0. - STRBERRIE: u1, - /// inconsistency error interrupt enable bit When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0. - INCERRIE: u1, - /// OBK general error interrupt enable bit OBKERRIE enables generating an interrupt in case of OBK specific access error. OBKERRIE can be programmed only when LOCK is cleared to 0. - OBKERRIE: u1, - /// OBK write error interrupt enable bit OBKWERRIE enables generation of interrupt in case of OBK specific write error. OBKWERRIE can be programmed only when LOCK is cleared to 0. - OBKWERRIE: u1, - reserved29: u6, - /// Flash memory security state invert. This bit inverts the flash memory security state. - INV: u1, - reserved31: u1, - /// bank selector bit BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored. - BKSEL: packed union { - raw: u1, - value: SECCR_BKSEL, - }, + /// DSI Host PHY Configuration Register. + PCONFR: mmio.Mmio(packed struct(u32) { + /// Number of Lanes. + NL: u2, + reserved8: u6, + /// Stop Wait Time. + SW_TIME: u8, + padding: u16, }), - /// FLASH non-secure clear control register - NSCCR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// EOP flag clear bit Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register. - CLR_EOP: u1, - /// WRPERR flag clear bit Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register. - CLR_WRPERR: u1, - /// PGSERR flag clear bit Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register. - CLR_PGSERR: u1, - /// STRBERR flag clear bit Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register. - CLR_STRBERR: u1, - /// INCERR flag clear bit Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register. - CLR_INCERR: u1, - /// OBKERR flag clear bit. Setting this bit to 1 resets to 0 OBKERR flag in FLASH_NSSR register. - CLR_OBKERR: u1, - /// OBKWERR flag clear bit. Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_NSSR register. - CLR_OBKWERR: u1, - /// Clear the flag corresponding flag in FLASH_NSSR by writing this bit. - CLR_OPTCHANGEERR: u1, - padding: u8, + /// DSI Host PHY ULPS Control Register. + PUCR: mmio.Mmio(packed struct(u32) { + /// ULPS Request on Clock Lane. + URCL: u1, + /// ULPS Exit on Clock Lane. + UECL: u1, + /// ULPS Request on Data Lane. + URDL: u1, + /// ULPS Exit on Data Lane. + UEDL: u1, + padding: u28, }), - /// FLASH secure clear control register - SECCCR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// EOP flag clear bit Setting this bit to 1 resets to 0 EOP flag in FLASH_SECSR register. - CLR_EOP: u1, - /// WRPERR flag clear bit Setting this bit to 1 resets to 0 WRPERR flag in FLASH_SECSR register. - CLR_WRPERR: u1, - /// PGSERR flag clear bit Setting this bit to 1 resets to 0 PGSERR flag in FLASH_SECSR register. - CLR_PGSERR: u1, - /// STRBERR flag clear bit Setting this bit to 1 resets to 0 STRBERR flag in FLASH_SECSR register. - CLR_STRBERR: u1, - /// INCERR flag clear bit Setting this bit to 1 resets to 0 INCERR flag in FLASH_SECSR register. - CLR_INCERR: u1, - /// OBKWERR flag clear bit Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_SECSR register. - CLR_OBKERR: u1, - /// OBKWERR flag clear bit Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_SECSR register. - CLR_OBKWERR: u1, - padding: u9, + /// DSI Host PHY TX Triggers Configuration Register. + PTTCR: mmio.Mmio(packed struct(u32) { + /// Transmission Trigger. + TX_TRIG: u4, + padding: u28, }), - reserved60: [4]u8, - /// FLASH privilege configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// privilege attribute for secure registers - SPRIV: packed union { - raw: u1, - value: SPRIV, - }, - /// privilege attribute for non secure registers - NSPRIV: packed union { - raw: u1, - value: NSPRIV, - }, - padding: u30, + /// DSI Host PHY Status Register. + PSR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PHY Direction. + PD: u1, + /// PHY Stop State Clock lane. + PSSC: u1, + /// ULPS Active Not Clock lane. + UANC: u1, + /// PHY Stop State lane 0. + PSS0: u1, + /// ULPS Active Not lane 1. + UAN0: u1, + /// RX ULPS Escape lane 0. + RUE0: u1, + /// PHY Stop State lane 1. + PSS1: u1, + /// ULPS Active Not lane 1. + UAN1: u1, + padding: u23, }), - /// FLASH non-secure OBK configuration register - NSOBKCFGR: mmio.Mmio(packed struct(u32) { - /// OBKCFGR lock option configuration bit This bit locks the FLASH_NSOBKCFGR register. The correct write sequence to FLASH_NSOBKKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSOBKKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change. - LOCK: u1, - /// OBK swap sector request bit When set, all the OBKs which have not been updated in the alternate sector is copied from current sector to alternate one. The SWAP_OFFSET value must be a certain minimum value in order for the swap to be launched in OBK-HDPL ≠ 0. Minimum value is 16 for OBK-HDPL = 1, 144 for OBK-HDPL = 2 and 192 for OBK-HDPL = 3. - SWAP_SECT_REQ: u1, - /// alternate sector bit This bit must not change while filling the write buffer, otherwise an error (OBKERR) is generated - ALT_SECT: u1, - /// alternate sector erase bit When ALT_SECT bit is set, use this bit to generate an erase command for the OBK alternate sector. It is set only by Software and cleared when the OBK swap operation is completed or an error occurs (PGSERR). It is reseted at the same time as BUSY bit. - ALT_SECT_ERASE: u1, - reserved16: u12, - /// Key index (offset /16 bits) pointing for next swap. 0x01 means that only the first OBK data (128 bits) is copied from current to alternate OBK sector 0x02 means that the two first OBK data is copied … … - SWAP_OFFSET: u9, - padding: u7, + reserved188: [8]u8, + /// DSI Host Interrupt & Status Register 0. + ISR0: mmio.Mmio(packed struct(u32) { + /// Acknowledge Error 0. + AE0: u1, + /// Acknowledge Error 1. + AE1: u1, + /// Acknowledge Error 2. + AE2: u1, + /// Acknowledge Error 3. + AE3: u1, + /// Acknowledge Error 4. + AE4: u1, + /// Acknowledge Error 5. + AE5: u1, + /// Acknowledge Error 6. + AE6: u1, + /// Acknowledge Error 7. + AE7: u1, + /// Acknowledge Error 8. + AE8: u1, + /// Acknowledge Error 9. + AE9: u1, + /// Acknowledge Error 10. + AE10: u1, + /// Acknowledge Error 11. + AE11: u1, + /// Acknowledge Error 12. + AE12: u1, + /// Acknowledge Error 13. + AE13: u1, + /// Acknowledge Error 14. + AE14: u1, + /// Acknowledge Error 15. + AE15: u1, + /// PHY Error 0. + PE0: u1, + /// PHY Error 1. + PE1: u1, + /// PHY Error 2. + PE2: u1, + /// PHY Error 3. + PE3: u1, + /// PHY Error 4. + PE4: u1, + padding: u11, }), - /// FLASH secure OBK configuration register - SECOBKCFGR: mmio.Mmio(packed struct(u32) { - /// OBKCFGR lock option configuration bit This bit locks the FLASH_OBKCFGR register. The correct write sequence to FLASH_SECOBKKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_SECOBKKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change. - LOCK: u1, - /// OBK swap sector request bit When set, all the OBKs which have not been updated in the alternate sector is copied from current sector to alternate one. The SWAP_OFFSET value must be a certain minimum value in order for the swap to be launched in OBK-HDPL ≠ 0. Minimum value is 16 for OBK-HDPL = 1, 144 for OBK-HDPL = 2 and 192 for OBK-HDPL = 3. - SWAP_SECT_REQ: u1, - /// alternate sector bit This bit must not change while filling the write buffer, otherwise an error is generated - ALT_SECT: u1, - /// alternate sector erase bit When ALT_SECT bit is set, use this bit to generate an erase command for the OBK alternate sector. It is set only by Software and cleared when the OBK swap operation is completed or an error occurs (PGSERR). It is reseted at the same time as the BUSY bit. - ALT_SECT_ERASE: u1, - reserved16: u12, - /// key index (offset /16 bits) pointing for next swap. … - SWAP_OFFSET: u9, - padding: u7, + /// DSI Host Interrupt & Status Register 1. + ISR1: mmio.Mmio(packed struct(u32) { + /// Timeout High-Speed Transmission. + TOHSTX: u1, + /// Timeout Low-Power Reception. + TOLPRX: u1, + /// ECC Single-bit Error. + ECCSE: u1, + /// ECC Multi-bit Error. + ECCME: u1, + /// CRC Error. + CRCE: u1, + /// Packet Size Error. + PSE: u1, + /// EoTp Error. + EOTPE: u1, + /// LTDC Payload Write Error. + LPWRE: u1, + /// Generic Command Write Error. + GCWRE: u1, + /// Generic Payload Write Error. + GPWRE: u1, + /// Generic Payload Transmit Error. + GPTXE: u1, + /// Generic Payload Read Error. + GPRDE: u1, + /// Generic Payload Receive Error. + GPRXE: u1, + padding: u19, }), - /// FLASH HDP extension register - HDPEXTR: mmio.Mmio(packed struct(u32) { - /// HDP area extension in 8�Kbytes sectors in Bank1. Extension is added after the HDP1_END sector (included). - HDP1_EXT: u7, - reserved16: u9, - /// HDP area extension in 8�Kbytes sectors in bank 2. Extension is added after the HDP2_END sector (included). - HDP2_EXT: u7, - padding: u9, + /// DSI Host Interrupt Enable Register 0. + IER0: mmio.Mmio(packed struct(u32) { + /// Acknowledge Error 0 Interrupt Enable. + AE0IE: u1, + /// Acknowledge Error 1 Interrupt Enable. + AE1IE: u1, + /// Acknowledge Error 2 Interrupt Enable. + AE2IE: u1, + /// Acknowledge Error 3 Interrupt Enable. + AE3IE: u1, + /// Acknowledge Error 4 Interrupt Enable. + AE4IE: u1, + /// Acknowledge Error 5 Interrupt Enable. + AE5IE: u1, + /// Acknowledge Error 6 Interrupt Enable. + AE6IE: u1, + /// Acknowledge Error 7 Interrupt Enable. + AE7IE: u1, + /// Acknowledge Error 8 Interrupt Enable. + AE8IE: u1, + /// Acknowledge Error 9 Interrupt Enable. + AE9IE: u1, + /// Acknowledge Error 10 Interrupt Enable. + AE10IE: u1, + /// Acknowledge Error 11 Interrupt Enable. + AE11IE: u1, + /// Acknowledge Error 12 Interrupt Enable. + AE12IE: u1, + /// Acknowledge Error 13 Interrupt Enable. + AE13IE: u1, + /// Acknowledge Error 14 Interrupt Enable. + AE14IE: u1, + /// Acknowledge Error 15 Interrupt Enable. + AE15IE: u1, + /// PHY Error 0 Interrupt Enable. + PE0IE: u1, + /// PHY Error 1 Interrupt Enable. + PE1IE: u1, + /// PHY Error 2 Interrupt Enable. + PE2IE: u1, + /// PHY Error 3 Interrupt Enable. + PE3IE: u1, + /// PHY Error 4 Interrupt Enable. + PE4IE: u1, + padding: u11, }), - reserved80: [4]u8, - /// FLASH option status register - OPTSR_CUR: mmio.Mmio(packed struct(u32) { - /// Brownout level option status bit These bits reflects the power level that generates a system reset. 00 or 11: BOR Level 1, the threshold level is low (around 2.1�V) - BOR_LEV: packed union { - raw: u2, - value: OPTSR_BOR_LEV, - }, - /// Brownout high enable - BORH_EN: u1, - /// IWDG control mode option status bit - IWDG_SW: packed union { - raw: u1, - value: OPTSR_IWDG_SW, - }, - /// WWDG control mode option status bit - WWDG_SW: packed union { - raw: u1, - value: OPTSR_WWDG_SW, - }, - reserved6: u1, - /// Core domain Stop entry reset option status bit - NRST_STOP: packed union { - raw: u1, - value: OPTSR_NRST_STOP, - }, - /// Core domain Standby entry reset option status bit - NRST_STDBY: packed union { - raw: u1, - value: OPTSR_NRST_STDBY, - }, - /// Life state code (based on Hamming 8,4). More information in Section�7.6.11: Product state transitions. - PRODUCT_STATE: u8, - /// High-speed IO at low VDD voltage configuration bit. This bit can be set only with VDD below 2.7�V. - IO_VDD_HSLV: packed union { - raw: u1, - value: OPTSR_IO_VDD_HSLV, - }, - /// High-speed IO at low VDDIO2 voltage configuration bit. This bit can be set only with VDDIO2 below 2.7�V. - IO_VDDIO2_HSLV: packed union { - raw: u1, - value: OPTSR_IO_VDDIO_HSLV, - }, - reserved20: u2, - /// IWDG Stop mode freeze option status bit When set the independent watchdog IWDG is in system Stop mode. - IWDG_STOP: packed union { - raw: u1, - value: OPTSR_IWDG_STOP, - }, - /// IWDG Standby mode freeze option status bit When set the independent watchdog IWDG is frozen in system Standby mode. - IWDG_STDBY: packed union { - raw: u1, - value: OPTSR_IWDG_STDBY, - }, - /// Available only on cryptography enabled devices. Unique boot entry control, selects either ST or OEM iRoT for secure boot. - BOOT_UBE: packed union { - raw: u8, - value: OPTSR_BOOT_UBE, - }, - reserved31: u1, - /// Bank swapping option status bit SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset. - SWAP_BANK: packed union { - raw: u1, - value: OPTSR_SWAP_BANK, - }, + /// DSI Host Interrupt Enable Register 1. + IER1: mmio.Mmio(packed struct(u32) { + /// Timeout High-Speed Transmission Interrupt Enable. + TOHSTXIE: u1, + /// Timeout Low-Power Reception Interrupt Enable. + TOLPRXIE: u1, + /// ECC Single-bit Error Interrupt Enable. + ECCSEIE: u1, + /// ECC Multi-bit Error Interrupt Enable. + ECCMEIE: u1, + /// CRC Error Interrupt Enable. + CRCEIE: u1, + /// Packet Size Error Interrupt Enable. + PSEIE: u1, + /// EoTp Error Interrupt Enable. + EOTPEIE: u1, + /// LTDC Payload Write Error Interrupt Enable. + LPWREIE: u1, + /// Generic Command Write Error Interrupt Enable. + GCWREIE: u1, + /// Generic Payload Write Error Interrupt Enable. + GPWREIE: u1, + /// Generic Payload Transmit Error Interrupt Enable. + GPTXEIE: u1, + /// Generic Payload Read Error Interrupt Enable. + GPRDEIE: u1, + /// Generic Payload Receive Error Interrupt Enable. + GPRXEIE: u1, + padding: u19, }), - /// FLASH option status register - OPTSR_PRG: mmio.Mmio(packed struct(u32) { - /// Brownout level option status bit These bits reflects the power level that generates a system reset. 00 or 11: BOR Level 1, the threshold level is low (around 2.1�V) - BOR_LEV: packed union { - raw: u2, - value: OPTSR_BOR_LEV, - }, - /// Brownout high enable - BORH_EN: u1, - /// IWDG control mode option status bit - IWDG_SW: packed union { - raw: u1, - value: OPTSR_IWDG_SW, - }, - /// WWDG control mode option status bit - WWDG_SW: packed union { - raw: u1, - value: OPTSR_WWDG_SW, - }, - reserved6: u1, - /// Core domain Stop entry reset option status bit - NRST_STOP: packed union { - raw: u1, - value: OPTSR_NRST_STOP, - }, - /// Core domain Standby entry reset option status bit - NRST_STDBY: packed union { - raw: u1, - value: OPTSR_NRST_STDBY, - }, - /// Life state code (based on Hamming 8,4). More information in Section�7.6.11: Product state transitions. - PRODUCT_STATE: u8, - /// High-speed IO at low VDD voltage configuration bit. This bit can be set only with VDD below 2.7�V. - IO_VDD_HSLV: packed union { - raw: u1, - value: OPTSR_IO_VDD_HSLV, - }, - /// High-speed IO at low VDDIO2 voltage configuration bit. This bit can be set only with VDDIO2 below 2.7�V. - IO_VDDIO2_HSLV: packed union { - raw: u1, - value: OPTSR_IO_VDDIO_HSLV, - }, - reserved20: u2, - /// IWDG Stop mode freeze option status bit When set the independent watchdog IWDG is in system Stop mode. - IWDG_STOP: packed union { - raw: u1, - value: OPTSR_IWDG_STOP, - }, - /// IWDG Standby mode freeze option status bit When set the independent watchdog IWDG is frozen in system Standby mode. - IWDG_STDBY: packed union { - raw: u1, - value: OPTSR_IWDG_STDBY, - }, - /// Available only on cryptography enabled devices. Unique boot entry control, selects either ST or OEM iRoT for secure boot. - BOOT_UBE: packed union { - raw: u8, - value: OPTSR_BOOT_UBE, - }, - reserved31: u1, - /// Bank swapping option status bit SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset. - SWAP_BANK: packed union { - raw: u1, - value: OPTSR_SWAP_BANK, - }, + reserved216: [12]u8, + /// DSI Host Force Interrupt Register 0. + FIR0: mmio.Mmio(packed struct(u32) { + /// Force Acknowledge Error 0. + FAE0: u1, + /// Force Acknowledge Error 1. + FAE1: u1, + /// Force Acknowledge Error 2. + FAE2: u1, + /// Force Acknowledge Error 3. + FAE3: u1, + /// Force Acknowledge Error 4. + FAE4: u1, + /// Force Acknowledge Error 5. + FAE5: u1, + /// Force Acknowledge Error 6. + FAE6: u1, + /// Force Acknowledge Error 7. + FAE7: u1, + /// Force Acknowledge Error 8. + FAE8: u1, + /// Force Acknowledge Error 9. + FAE9: u1, + /// Force Acknowledge Error 10. + FAE10: u1, + /// Force Acknowledge Error 11. + FAE11: u1, + /// Force Acknowledge Error 12. + FAE12: u1, + /// Force Acknowledge Error 13. + FAE13: u1, + /// Force Acknowledge Error 14. + FAE14: u1, + /// Force Acknowledge Error 15. + FAE15: u1, + /// Force PHY Error 0. + FPE0: u1, + /// Force PHY Error 1. + FPE1: u1, + /// Force PHY Error 2. + FPE2: u1, + /// Force PHY Error 3. + FPE3: u1, + /// Force PHY Error 4. + FPE4: u1, + padding: u11, }), - reserved96: [8]u8, - /// FLASH non-secure EPOCH register - NSEPOCHR_CUR: mmio.Mmio(packed struct(u32) { - /// Non-volatile non-secure EPOCH counter - NS_EPOCH: u24, - padding: u8, + /// DSI Host Force Interrupt Register 1. + FIR1: mmio.Mmio(packed struct(u32) { + /// Force Timeout High-Speed Transmission. + FTOHSTX: u1, + /// Force Timeout Low-Power Reception. + FTOLPRX: u1, + /// Force ECC Single-bit Error. + FECCSE: u1, + /// Force ECC Multi-bit Error. + FECCME: u1, + /// Force CRC Error. + FCRCE: u1, + /// Force Packet Size Error. + FPSE: u1, + /// Force EoTp Error. + FEOTPE: u1, + /// Force LTDC Payload Write Error. + FLPWRE: u1, + /// Force Generic Command Write Error. + FGCWRE: u1, + /// Force Generic Payload Write Error. + FGPWRE: u1, + /// Force Generic Payload Transmit Error. + FGPTXE: u1, + /// Force Generic Payload Read Error. + FGPRDE: u1, + /// Force Generic Payload Receive Error. + FGPRXE: u1, + padding: u19, }), - reserved104: [4]u8, - /// FLASH secure EPOCH register - SECEPOCHR_CUR: mmio.Mmio(packed struct(u32) { - /// Non-volatile secure EPOCH counter - SEC_EPOCH: u24, - padding: u8, + reserved256: [32]u8, + /// DSI Host Video Shadow Control Register. + VSCR: mmio.Mmio(packed struct(u32) { + /// Enable. + EN: u1, + reserved8: u7, + /// Update Register. + UR: u1, + padding: u23, }), - reserved112: [4]u8, - /// FLASH option status register 2 - OPTSR2_CUR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// SRAM1 and SRAM3 erase upon system reset - SRAM13_RST: u1, - /// SRAM2 erase when system reset - SRAM2_RST: u1, - /// Backup RAM ECC detection and correction disable - BKPRAM_ECC: packed union { - raw: u1, - value: OPTSR_BKPRAM_ECC, - }, - /// SRAM3 ECC detection and correction disable - SRAM3_ECC: packed union { - raw: u1, - value: OPTSR_SRAM_ECC, - }, - /// SRAM2 ECC detection and correction disable - SRAM2_ECC: packed union { - raw: u1, - value: OPTSR_SRAM_ECC, - }, - reserved8: u1, - /// USB power delivery configuration option bit - USBPD_DIS: u1, - reserved24: u15, - /// TrustZone enable configuration bits This bit enables the device is in TrustZone mode during an option byte change. - TZEN: packed union { - raw: u8, - value: OPTSR_TZEN, - }, + reserved268: [8]u8, + /// DSI Host LTDC Current VCID Register. + LCVCIDR: mmio.Mmio(packed struct(u32) { + /// Virtual Channel ID. + VCID: u2, + padding: u30, }), - /// FLASH option status register 2 - OPTSR2_PRG: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// SRAM1 and SRAM3 erase upon system reset - SRAM13_RST: u1, - /// SRAM2 erase when system reset - SRAM2_RST: u1, - /// Backup RAM ECC detection and correction disable - BKPRAM_ECC: packed union { - raw: u1, - value: OPTSR_BKPRAM_ECC, - }, - /// SRAM3 ECC detection and correction disable - SRAM3_ECC: packed union { - raw: u1, - value: OPTSR_SRAM_ECC, - }, - /// SRAM2 ECC detection and correction disable - SRAM2_ECC: packed union { - raw: u1, - value: OPTSR_SRAM_ECC, - }, - reserved8: u1, - /// USB power delivery configuration option bit - USBPD_DIS: u1, - reserved24: u15, - /// TrustZone enable configuration bits This bit enables the device is in TrustZone mode during an option byte change. - TZEN: packed union { - raw: u8, - value: OPTSR_TZEN, - }, + /// DSI Host LTDC Current Color Coding Register. + LCCCR: mmio.Mmio(packed struct(u32) { + /// Color Coding. + COLC: u4, + reserved8: u4, + /// Loosely Packed Enable. + LPE: u1, + padding: u23, }), - reserved128: [8]u8, - /// FLASH non-secure boot register - NSBOOTR_CUR: mmio.Mmio(packed struct(u32) { - /// A field locking the values of SWAP_ BANK, and NSBOOTADD settings. - NSBOOT_LOCK: packed union { - raw: u8, - value: NSBOOTR_NSBOOT_LOCK, - }, - /// Non secure unique boot entry address These bits allow configuring the Non secure BOOT address - NSBOOTADD: u24, + reserved280: [4]u8, + /// DSI Host Low-Power mode Current Configuration Register. + LPMCCR: mmio.Mmio(packed struct(u32) { + /// VACT Largest Packet Size. + VLPSIZE: u8, + reserved16: u8, + /// Largest Packet Size. + LPSIZE: u8, + padding: u8, }), - /// FLASH non-secure boot register - NSBOOTR_PRG: mmio.Mmio(packed struct(u32) { - /// A field locking the values of SWAP_ BANK, and NSBOOTADD settings. - NSBOOT_LOCK: packed union { - raw: u8, - value: NSBOOTR_NSBOOT_LOCK, - }, - /// Non secure unique boot entry address These bits allow configuring the Non secure BOOT address - NSBOOTADD: u24, + reserved312: [28]u8, + /// DSI Host Video mode Current Configuration Register. + VMCCR: mmio.Mmio(packed struct(u32) { + /// Video mode Type. + VMT: u2, + /// Low-Power Vertical Sync time Enable. + LPVSAE: u1, + /// Low-power Vertical Back-Porch Enable. + LPVBPE: u1, + /// Low-power Vertical Front-Porch Enable. + LPVFPE: u1, + /// Low-Power Vertical Active Enable. + LPVAE: u1, + /// Low-power Horizontal Back-Porch Enable. + LPHBPE: u1, + /// Low-Power Horizontal Front-Porch Enable. + LPHFE: u1, + /// Frame BTA Acknowledge Enable. + FBTAAE: u1, + /// Low-Power Command Enable. + LPCE: u1, + padding: u22, }), - /// FLASH secure boot register - SECBOOTR_CUR: mmio.Mmio(packed struct(u32) { - /// A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. - SECBOOT_LOCK: packed union { - raw: u8, - value: SECBOOTR_SECBOOT_LOCK, - }, - /// Unique boot entry secure address These bits reflect the Secure UBE address - SECBOOTADD: u24, + /// DSI Host Video Packet Current Configuration Register. + VPCCR: mmio.Mmio(packed struct(u32) { + /// Video Packet Size. + VPSIZE: u14, + padding: u18, }), - /// FLASH secure boot register - BOOTR_PRG: mmio.Mmio(packed struct(u32) { - /// A field locking the values of UBE, SWAP_ BANK, and SECBOOTADD setting. - SECBOOT_LOCK: packed union { - raw: u8, - value: BOOTR_SECBOOT_LOCK, - }, - /// Secure unique boot entry address. These bits allow configuring the secure UBE address. - SECBOOTADD: u24, + /// DSI Host Video Chunks Current Configuration Register. + VCCCR: mmio.Mmio(packed struct(u32) { + /// Number of Chunks. + NUMC: u13, + padding: u19, }), - /// FLASH non-secure OTP block lock - OTPBLR_CUR: mmio.Mmio(packed struct(u32) { - /// OTP block lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR. LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked. When one block is locked, it’s not possible to remove the write protection. Also if not locked, it is not possible to erase OTP words. - LOCKBL: u32, + /// DSI Host Video Null Packet Current Configuration Register. + VNPCCR: mmio.Mmio(packed struct(u32) { + /// Null Packet Size. + NPSIZE: u13, + padding: u19, }), - /// FLASH non-secure OTP block lock - OTPBLR_PRG: mmio.Mmio(packed struct(u32) { - /// OTP block lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR. LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked. When one block is locked, it’s not possible to remove the write protection. Also if not locked, it is not possible to erase OTP words. - LOCKBL: u32, + /// DSI Host Video HSA Current Configuration Register. + VHSACCR: mmio.Mmio(packed struct(u32) { + /// Horizontal Synchronism Active duration. + HSA: u12, + padding: u20, }), - reserved160: [8]u8, - /// FLASH secure block based register for Bank 1 - SECBB1R1: mmio.Mmio(packed struct(u32) { - /// Secure/non-secure flash Bank 2 sector attribute - SECBB: packed union { - raw: u32, - value: SECBBR_SECBB, - }, + /// DSI Host Video HBP Current Configuration Register. + VHBPCCR: mmio.Mmio(packed struct(u32) { + /// Horizontal Back-Porch duration. + HBP: u12, + padding: u20, }), - /// FLASH secure block based register for Bank 1 - SECBB1R2: mmio.Mmio(packed struct(u32) { - /// Secure/non-secure flash Bank 2 sector attribute - SECBB: packed union { - raw: u32, - value: SECBBR_SECBB, - }, + /// DSI Host Video Line Current Configuration Register. + VLCCR: mmio.Mmio(packed struct(u32) { + /// Horizontal Line duration. + HLINE: u15, + padding: u17, }), - /// FLASH secure block based register for Bank 1 - SECBB1R3: mmio.Mmio(packed struct(u32) { - /// Secure/non-secure flash Bank 2 sector attribute - SECBB: packed union { - raw: u32, - value: SECBBR_SECBB, - }, + /// DSI Host Video VSA Current Configuration Register. + VVSACCR: mmio.Mmio(packed struct(u32) { + /// Vertical Synchronism Active duration. + VSA: u10, + padding: u22, }), - /// FLASH secure block based register for Bank 1 - SECBB1R4: mmio.Mmio(packed struct(u32) { - /// Secure/non-secure flash Bank 2 sector attribute - SECBB: packed union { - raw: u32, - value: SECBBR_SECBB, - }, + /// DSI Host Video VBP Current Configuration Register. + VVBPCCR: mmio.Mmio(packed struct(u32) { + /// Vertical Back-Porch duration. + VBP: u10, + padding: u22, }), - reserved192: [16]u8, - /// FLASH privilege block based register for Bank 1 - PRIVBB1R1: mmio.Mmio(packed struct(u32) { - /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute - PRIVBB: packed union { - raw: u32, - value: PRIVBBR_PRIVBB, - }, + /// DSI Host Video VFP Current Configuration Register. + VVFPCCR: mmio.Mmio(packed struct(u32) { + /// Vertical Front-Porch duration. + VFP: u10, + padding: u22, }), - /// FLASH privilege block based register for Bank 1 - PRIVBB1R2: mmio.Mmio(packed struct(u32) { - /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute - PRIVBB: packed union { - raw: u32, - value: PRIVBBR_PRIVBB, - }, + /// DSI Host Video VA Current Configuration Register. + VVACCR: mmio.Mmio(packed struct(u32) { + /// Vertical Active duration. + VA: u14, + padding: u18, }), - /// FLASH privilege block based register for Bank 1 - PRIVBB1R3: mmio.Mmio(packed struct(u32) { - /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute - PRIVBB: packed union { - raw: u32, - value: PRIVBBR_PRIVBB, - }, + reserved1024: [668]u8, + /// DSI Wrapper Configuration Register. + WCFGR: mmio.Mmio(packed struct(u32) { + /// DSI Mode. + DSIM: u1, + /// Color Multiplexing. + COLMUX: u3, + /// TE Source. + TESRC: u1, + /// TE Polarity. + TEPOL: u1, + /// Automatic Refresh. + AR: u1, + /// VSync Polarity. + VSPOL: u1, + padding: u24, }), - /// FLASH privilege block based register for Bank 1 - PRIVBB1R4: mmio.Mmio(packed struct(u32) { - /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute - PRIVBB: packed union { - raw: u32, - value: PRIVBBR_PRIVBB, - }, + /// DSI Wrapper Control Register. + WCR: mmio.Mmio(packed struct(u32) { + /// Color Mode. + COLM: u1, + /// Shutdown. + SHTDN: u1, + /// LTDC Enable. + LTDCEN: u1, + /// DSI Enable. + DSIEN: u1, + padding: u28, }), - reserved224: [16]u8, - /// FLASH security watermark for Bank 1 - SECWM1R_CUR: mmio.Mmio(packed struct(u32) { - /// Bank2 security WM area start sector - SECWMSTRT: u7, - reserved16: u9, - /// Bank2 security WM end sector - SECWMEND: u7, - padding: u9, + /// DSI Wrapper Interrupt Enable Register. + WIER: mmio.Mmio(packed struct(u32) { + /// Tearing Effect Interrupt Enable. + TEIE: u1, + /// End of Refresh Interrupt Enable. + ERIE: u1, + reserved9: u7, + /// PLL Lock Interrupt Enable. + PLLLIE: u1, + /// PLL Unlock Interrupt Enable. + PLLUIE: u1, + reserved13: u2, + /// Regulator Ready Interrupt Enable. + RRIE: u1, + padding: u18, }), - /// FLASH security watermark for Bank 1 - SECWM1R_PRG: mmio.Mmio(packed struct(u32) { - /// Bank2 security WM area start sector - SECWMSTRT: u7, - reserved16: u9, - /// Bank2 security WM end sector - SECWMEND: u7, - padding: u9, + /// DSI Wrapper Interrupt & Status Register. + WISR: mmio.Mmio(packed struct(u32) { + /// Tearing Effect Interrupt Flag. + TEIF: u1, + /// End of Refresh Interrupt Flag. + ERIF: u1, + /// Busy Flag. + BUSY: u1, + reserved8: u5, + /// PLL Lock Status. + PLLLS: u1, + /// PLL Lock Interrupt Flag. + PLLLIF: u1, + /// PLL Unlock Interrupt Flag. + PLLUIF: u1, + reserved12: u1, + /// Regulator Ready Status. + RRS: u1, + /// Regulator Ready Interrupt Flag. + RRIF: u1, + padding: u18, }), - /// FLASH write sector group protection for Bank 1 - WRP1R_CUR: mmio.Mmio(packed struct(u32) { - /// Bank1 sector group protection option status byte Setting WRPSG1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected) Bit 0: Group embedding sectors 0 to 3 Bit 1: Group embedding sectors 4 to 7 Bit N: Group embedding sectors 4 x N to 4 x N + 3 Bit 31: Group embedding sectors 124 to 127 - WRPSG: u32, + /// DSI Wrapper Interrupt Flag Clear Register. + WIFCR: mmio.Mmio(packed struct(u32) { + /// Clear Tearing Effect Interrupt Flag. + CTEIF: u1, + /// Clear End of Refresh Interrupt Flag. + CERIF: u1, + reserved9: u7, + /// Clear PLL Lock Interrupt Flag. + CPLLLIF: u1, + /// Clear PLL Unlock Interrupt Flag. + CPLLUIF: u1, + reserved13: u2, + /// Clear Regulator Ready Interrupt Flag. + CRRIF: u1, + padding: u18, }), - /// FLASH write sector group protection for Bank 1 - WRP1R_PRG: mmio.Mmio(packed struct(u32) { - /// Bank1 sector group protection option status byte Setting WRPSG1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected) Bit 0: Group embedding sectors 0 to 3 Bit 1: Group embedding sectors 4 to 7 Bit N: Group embedding sectors 4 x N to 4 x N + 3 Bit 31: Group embedding sectors 124 to 127 - WRPSG: u32, + reserved1048: [4]u8, + /// DSI Wrapper PHY Configuration Register 0. + WPCR0: mmio.Mmio(packed struct(u32) { + /// Unit Interval multiplied by 4. + UIX4: u6, + /// Swap Clock Lane pins. + SWCL: u1, + /// Swap Data Lane 0 pins. + SWDL0: u1, + /// Swap Data Lane 1 pins. + SWDL1: u1, + /// Invert Hight-Speed data signal on Clock Lane. + HSICL: u1, + /// Invert the Hight-Speed data signal on Data Lane 0. + HSIDL0: u1, + /// Invert the High-Speed data signal on Data Lane 1. + HSIDL1: u1, + /// Force in TX Stop Mode the Clock Lane. + FTXSMCL: u1, + /// Force in TX Stop Mode the Data Lanes. + FTXSMDL: u1, + /// Contention Detection OFF on Data Lanes. + CDOFFDL: u1, + reserved16: u1, + /// Turn Disable Data Lanes. + TDDL: u1, + reserved18: u1, + /// Pull-Down Enable. + PDEN: u1, + /// custom time for tCLK-PREPARE Enable. + TCLKPREPEN: u1, + /// custom time for tCLK-ZERO Enable. + TCLKZEROEN: u1, + /// custom time for tHS-PREPARE Enable. + THSPREPEN: u1, + /// custom time for tHS-TRAIL Enable. + THSTRAILEN: u1, + /// custom time for tHS-ZERO Enable. + THSZEROEN: u1, + /// custom time for tLPX for Data lanes Enable. + TLPXDEN: u1, + /// custom time for tHS-EXIT Enable. + THSEXITEN: u1, + /// custom time for tLPX for Clock lane Enable. + TLPXCEN: u1, + /// custom time for tCLK-POST Enable. + TCLKPOSTEN: u1, + padding: u4, }), - /// FLASH data sector configuration Bank 1 - EDATA1R_CUR: mmio.Mmio(packed struct(u32) { - /// EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank 1 There is no hardware effect to those bits. They shall be managed by ST tools in Flasher. ... Note: 111: The eight last sectors of the Bank 1 are reserved for flash high-cycle data - EDATA1_STRT: u3, - reserved15: u12, - /// Bank 1 flash high-cycle data enable - EDATA1_EN: u1, - padding: u16, + /// DSI Wrapper PHY Configuration Register 1. + WPCR1: mmio.Mmio(packed struct(u32) { + /// High-Speed Transmission Delay on Clock Lane. + HSTXDCL: u2, + /// High-Speed Transmission Delay on Data Lanes. + HSTXDLL: u2, + reserved6: u2, + /// Low-Power transmission Slew Rate Compensation on Clock Lane. + LPSRCL: u2, + /// Low-Power transmission Slew Rate Compensation on Data Lanes. + LPSRDL: u2, + reserved12: u2, + /// SDD Control. + SDCC: u1, + reserved16: u3, + /// High-Speed Transmission Slew Rate Control on Clock Lane. + HSTXSRCCL: u2, + /// High-Speed Transmission Slew Rate Control on Data Lanes. + HSTXSRCDL: u2, + reserved22: u2, + /// Forces LP Receiver in Low-Power Mode. + FLPRXLPM: u1, + reserved25: u2, + /// Low-Power RX low-pass Filtering Tuning. + LPRXFT: u2, + padding: u5, }), - /// FLASH data sector configuration Bank 1 - EDATA1R_PRG: mmio.Mmio(packed struct(u32) { - /// EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank 1 There is no hardware effect to those bits. They shall be managed by ST tools in Flasher. ... Note: 111: The eight last sectors of the Bank 1 are reserved for flash high-cycle data - EDATA1_STRT: u3, - reserved15: u12, - /// Bank 1 flash high-cycle data enable - EDATA1_EN: u1, - padding: u16, + /// DSI Wrapper PHY Configuration Register 2. + WPCR2: mmio.Mmio(packed struct(u32) { + /// tCLK-PREPARE. + TCLKPREP: u8, + /// tCLK-ZERO. + TCLKZEO: u8, + /// tHS-PREPARE. + THSPREP: u8, + /// tHSTRAIL. + THSTRAIL: u8, }), - /// FLASH HDP Bank 1 configuration - HDP1R_CUR: mmio.Mmio(packed struct(u32) { - /// HDPL barrier start set in number of 8-Kbyte sectors - HDP1_STRT: u7, - reserved16: u9, - /// HDPL barrier end set in number of 8-Kbyte sectors - HDP1_END: u7, - padding: u9, + /// DSI Wrapper PHY Configuration Register 3. + WPCR3: mmio.Mmio(packed struct(u32) { + /// tHS-ZERO. + THSZERO: u8, + /// tLPX for Data lanes. + TLPXD: u8, + /// tHSEXIT. + THSEXIT: u8, + /// tLPXC for Clock lane. + TLPXC: u8, }), - /// FLASH HDP Bank 1 configuration - HDP1R_PRG: mmio.Mmio(packed struct(u32) { - /// HDPL barrier start set in number of 8-Kbyte sectors - HDP1_STRT: u7, - reserved16: u9, - /// HDPL barrier end set in number of 8-Kbyte sectors - HDP1_END: u7, - padding: u9, + /// DSI Wrapper PHY Configuration Register 4. + WPCR4: mmio.Mmio(packed struct(u32) { + /// tCLK-POST. + TCLKPOST: u8, + padding: u24, }), - /// FLASH ECC correction register - ECCCORR: mmio.Mmio(packed struct(u32) { - /// ECC error address When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The flash interface programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved. The address in ADDR_ECC is relative to the flash memory area where the error occurred (user flash memory, system flash memory, data area, read-only/OTP area). - ADDR_ECC: u16, - reserved20: u4, - /// Single ECC error corrected in flash OB Keys storage area. It indicates the OBK storage concerned by ECC error. - OBK_ECC: u1, - /// ECC fail for corrected ECC error in flash high-cycle data area It indicates if flash high-cycle data area is concerned by ECC error. - EDATA_ECC: u1, - /// ECC fail bank for corrected ECC error It indicates which bank is concerned by ECC error - BK_ECC: u1, - /// ECC fail for corrected ECC error in system flash memory It indicates if system flash memory is concerned by ECC error. - SYSF_ECC: u1, - /// OTP ECC error bit This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield. - OTP_ECC: u1, - /// ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation. - ECCCIE: u1, - reserved30: u4, - /// ECC correction set by hardware when single ECC error has been detected and corrected. Cleared by writing 1. - ECCC: u1, - padding: u1, + reserved1072: [4]u8, + /// DSI Wrapper Regulator and PLL Control Register. + WRPCR: mmio.Mmio(packed struct(u32) { + /// PLL Enable. + PLLEN: u1, + reserved2: u1, + /// PLL Loop Division Factor. + NDIV: u7, + reserved11: u2, + /// PLL Input Division Factor. + IDF: u4, + reserved16: u1, + /// PLL Output Division Factor. + ODF: u2, + reserved24: u6, + /// Regulator Enable. + REGEN: u1, + padding: u7, }), - /// FLASH ECC detection register - ECCDETR: mmio.Mmio(packed struct(u32) { - /// ECC error address When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The flash interface programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved. The address in ADDR_ECC is relative to the flash memory area where the error occurred (user flash memory, system flash memory, data area, read-only/OTP area). - ADDR_ECC: u16, - reserved20: u4, - /// ECC fail double ECC error in flash OB Keys storage area. It indicates the OBK storage concerned by ECC error. - OBK_ECC: u1, - /// ECC fail double ECC error in flash high-cycle data area It indicates if flash high-cycle data area is concerned by ECC error. - EDATA_ECC: u1, - /// ECC fail bank for double ECC error It indicates which bank is concerned by ECC error - BK_ECC: u1, - /// ECC fail for double ECC error in system flash memory It indicates if system flash memory is concerned by ECC error. - SYSF_ECC: u1, - /// OTP ECC error bit This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield. - OTP_ECC: u1, - reserved31: u6, - /// ECC detection Set by hardware when two ECC error has been detected. When this bit is set, a NMI is generated. Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors. - ECCD: u1, + }; + }; + + pub const dsihost_v2 = struct { + /// DSIHOST1. + pub const DSIHOST = extern struct { + /// DSI Host version register. + VR: mmio.Mmio(packed struct(u32) { + /// VERSION. + VERSION: u32, }), - /// FLASH ECC data - ECCDR: mmio.Mmio(packed struct(u32) { - /// ECC error data When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit data (data area, read-only/OTP area), the failing data is read to this register. By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory. - DATA_ECC: u16, + /// DSI Host control register. + CR: mmio.Mmio(packed struct(u32) { + /// EN. + EN: u1, + padding: u31, + }), + /// DSI Host clock control register. + CCR: mmio.Mmio(packed struct(u32) { + /// TXECKDIV. + TXECKDIV: u8, + /// TOCKDIV. + TOCKDIV: u8, padding: u16, }), - reserved416: [148]u8, - /// FLASH secure block-based register for Bank 2 - SECBB2R1: mmio.Mmio(packed struct(u32) { - /// Secure/non-secure flash Bank 2 sector attribute - SECBB: packed union { - raw: u32, - value: SECBBR_SECBB, - }, + /// DSI Host LTDC VCID register. + LVCIDR: mmio.Mmio(packed struct(u32) { + /// VCID. + VCID: u2, + padding: u30, }), - /// FLASH secure block-based register for Bank 2 - SECBB2R2: mmio.Mmio(packed struct(u32) { - /// Secure/non-secure flash Bank 2 sector attribute - SECBB: packed union { - raw: u32, - value: SECBBR_SECBB, - }, + /// DSI Host LTDC color coding register. + LCOLCR: mmio.Mmio(packed struct(u32) { + /// COLC. + COLC: u4, + reserved8: u4, + /// LPE. + LPE: u1, + padding: u23, }), - /// FLASH secure block-based register for Bank 2 - SECBB2R3: mmio.Mmio(packed struct(u32) { - /// Secure/non-secure flash Bank 2 sector attribute - SECBB: packed union { - raw: u32, - value: SECBBR_SECBB, - }, + /// DSI Host LTDC polarity configuration register. + LPCR: mmio.Mmio(packed struct(u32) { + /// DEP. + DEP: u1, + /// VSP. + VSP: u1, + /// HSP. + HSP: u1, + padding: u29, }), - /// FLASH secure block-based register for Bank 2 - SECBB2R4: mmio.Mmio(packed struct(u32) { - /// Secure/non-secure flash Bank 2 sector attribute - SECBB: packed union { - raw: u32, - value: SECBBR_SECBB, - }, + /// DSI Host low-power mode configuration register. + LPMCR: mmio.Mmio(packed struct(u32) { + /// VLPSIZE. + VLPSIZE: u8, + reserved16: u8, + /// LPSIZE. + LPSIZE: u8, + padding: u8, }), - reserved448: [16]u8, - /// FLASH privilege block-based register for Bank 2 - PRIVBB2R1: mmio.Mmio(packed struct(u32) { - /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute - PRIVBB: packed union { - raw: u32, - value: PRIVBBR_PRIVBB, - }, + reserved44: [16]u8, + /// DSI Host protocol configuration register. + PCR: mmio.Mmio(packed struct(u32) { + /// ETTXE. + ETTXE: u1, + /// ETRXE. + ETRXE: u1, + /// BTAE. + BTAE: u1, + /// ECCRXE. + ECCRXE: u1, + /// CRCRXE. + CRCRXE: u1, + padding: u27, }), - /// FLASH privilege block-based register for Bank 2 - PRIVBB2R2: mmio.Mmio(packed struct(u32) { - /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute - PRIVBB: packed union { - raw: u32, - value: PRIVBBR_PRIVBB, - }, + /// DSI Host generic VCID register. + GVCIDR: mmio.Mmio(packed struct(u32) { + /// VCID. + VCID: u2, + padding: u30, }), - /// FLASH privilege block-based register for Bank 2 - PRIVBB2R3: mmio.Mmio(packed struct(u32) { - /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute - PRIVBB: packed union { - raw: u32, - value: PRIVBBR_PRIVBB, - }, + /// DSI Host mode configuration register. + MCR: mmio.Mmio(packed struct(u32) { + /// CMDM. + CMDM: u1, + padding: u31, }), - /// FLASH privilege block-based register for Bank 2 - PRIVBB2R4: mmio.Mmio(packed struct(u32) { - /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute - PRIVBB: packed union { - raw: u32, - value: PRIVBBR_PRIVBB, - }, + /// DSI Host video mode configuration register. + VMCR: mmio.Mmio(packed struct(u32) { + /// VMT. + VMT: u2, + reserved8: u6, + /// LPVSAE. + LPVSAE: u1, + /// LPVBPE. + LPVBPE: u1, + /// LPVFPE. + LPVFPE: u1, + /// LPVAE. + LPVAE: u1, + /// LPHBPE. + LPHBPE: u1, + /// LPHFPE. + LPHFPE: u1, + /// FBTAAE. + FBTAAE: u1, + /// LPCE. + LPCE: u1, + /// PGE. + PGE: u1, + reserved20: u3, + /// PGM. + PGM: u1, + reserved24: u3, + /// PGO. + PGO: u1, + padding: u7, }), - reserved480: [16]u8, - /// FLASH security watermark for Bank 2 - SECWM2R_CUR: mmio.Mmio(packed struct(u32) { - /// Bank2 security WM area start sector - SECWMSTRT: u7, - reserved16: u9, - /// Bank2 security WM end sector - SECWMEND: u7, - padding: u9, + /// DSI Host video packet configuration register. + VPCR: mmio.Mmio(packed struct(u32) { + /// VPSIZE. + VPSIZE: u14, + padding: u18, }), - /// FLASH security watermark for Bank 2 - SECWM2R_PRG: mmio.Mmio(packed struct(u32) { - /// Bank2 security WM area start sector - SECWMSTRT: u7, - reserved16: u9, - /// Bank2 security WM end sector - SECWMEND: u7, - padding: u9, + /// DSI Host video chunks configuration register. + VCCR: mmio.Mmio(packed struct(u32) { + /// NUMC. + NUMC: u13, + padding: u19, }), - /// FLASH write sector group protection for Bank 2 - WRP2R_CUR: mmio.Mmio(packed struct(u32) { - /// Bank1 sector group protection option status byte Setting WRPSG1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected) Bit 0: Group embedding sectors 0 to 3 Bit 1: Group embedding sectors 4 to 7 Bit N: Group embedding sectors 4 x N to 4 x N + 3 Bit 31: Group embedding sectors 124 to 127 - WRPSG: u32, + /// DSI Host video null packet configuration register. + VNPCR: mmio.Mmio(packed struct(u32) { + /// NPSIZE. + NPSIZE: u13, + padding: u19, }), - /// FLASH write sector group protection for Bank 2 - WRP2R_PRG: mmio.Mmio(packed struct(u32) { - /// Bank1 sector group protection option status byte Setting WRPSG1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected) Bit 0: Group embedding sectors 0 to 3 Bit 1: Group embedding sectors 4 to 7 Bit N: Group embedding sectors 4 x N to 4 x N + 3 Bit 31: Group embedding sectors 124 to 127 - WRPSG: u32, + /// DSI Host video HSA configuration register. + VHSACR: mmio.Mmio(packed struct(u32) { + /// HSA. + HSA: u12, + padding: u20, }), - /// FLASH data sectors configuration Bank 2 - EDATA2R_CUR: mmio.Mmio(packed struct(u32) { - /// EDATA2_STRT contains the start sectors of the flash high-cycle data area in Bank 2 There is no hardware effect to those bits. They shall be managed by ST tools in Flasher. ... Note: 111: The eight last sectors of the Bank 2 are reserved for flash high-cycle data. - EDATA2_STRT: u3, - reserved15: u12, - /// Bank 2 flash high-cycle data enable - EDATA2_EN: u1, - padding: u16, + /// DSI Host video HBP configuration register. + VHBPCR: mmio.Mmio(packed struct(u32) { + /// HBP. + HBP: u12, + padding: u20, }), - /// FLASH data sector configuration Bank 2 - EDATA2R_PRG: mmio.Mmio(packed struct(u32) { - /// EDATA2_STRT contains the start sectors of the flash high-cycle data area in Bank 2 There is no hardware effect to those bits. They shall be managed by ST tools in Flasher. ... Note: 111: The eight last sectors of the Bank 2 are reserved for flash high-cycle data. - EDATA2_STRT: u3, - reserved15: u12, - /// Bank 2 flash high-cycle data enable - EDATA2_EN: u1, - padding: u16, + /// DSI Host video line configuration register. + VLCR: mmio.Mmio(packed struct(u32) { + /// HLINE. + HLINE: u15, + padding: u17, }), - /// FLASH HDP Bank 2 configuration - HDP2R_CUR: mmio.Mmio(packed struct(u32) { - /// HDPL barrier start set in number of 8-Kbyte sectors - HDP2_STRT: u7, - reserved16: u9, - /// HDPL barrier end set in number of 8-Kbyte sectors - HDP2_END: u7, - padding: u9, + /// DSI Host video VSA configuration register. + VVSACR: mmio.Mmio(packed struct(u32) { + /// VSA. + VSA: u10, + padding: u22, }), - /// FLASH HDP Bank 2 configuration - HDP2R_PRG: mmio.Mmio(packed struct(u32) { - /// HDPL barrier start set in number of 8-Kbyte sectors - HDP2_STRT: u7, - reserved16: u9, - /// HDPL barrier end set in number of 8-Kbyte sectors - HDP2_END: u7, - padding: u9, + /// DSI Host video VBP configuration register. + VVBPCR: mmio.Mmio(packed struct(u32) { + /// VBP. + VBP: u10, + padding: u22, }), - }; - }; - - pub const exti_h50 = struct { - /// Extended interrupt and event controller - pub const EXTI = extern struct { - /// rising trigger selection register - RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host video VFP configuration register. + VVFPCR: mmio.Mmio(packed struct(u32) { + /// VFP. + VFP: u10, + padding: u22, }), - /// falling trigger selection register - FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host video VA configuration register. + VVACR: mmio.Mmio(packed struct(u32) { + /// VA. + VA: u14, + padding: u18, }), - /// software interrupt event register - SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host LTDC command configuration register. + LCCR: mmio.Mmio(packed struct(u32) { + /// CMDSIZE. + CMDSIZE: u16, + padding: u16, }), - /// rising edge pending register - RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host command mode configuration register. + CMCR: mmio.Mmio(packed struct(u32) { + /// TEARE. + TEARE: u1, + /// ARE. + ARE: u1, + reserved8: u6, + /// GSW0TX. + GSW0TX: u1, + /// GSW1TX. + GSW1TX: u1, + /// GSW2TX. + GSW2TX: u1, + /// GSR0TX. + GSR0TX: u1, + /// GSR1TX. + GSR1TX: u1, + /// GSR2TX. + GSR2TX: u1, + /// GLWTX. + GLWTX: u1, + reserved16: u1, + /// DSW0TX. + DSW0TX: u1, + /// DSW1TX. + DSW1TX: u1, + /// DSR0TX. + DSR0TX: u1, + /// DLWTX. + DLWTX: u1, + reserved24: u4, + /// MRDPS. + MRDPS: u1, + padding: u7, }), - /// falling edge pending register - FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host generic header configuration register. + GHCR: mmio.Mmio(packed struct(u32) { + /// DT. + DT: u6, + /// VCID. + VCID: u2, + /// WCLSB. + WCLSB: u8, + /// WCMSB. + WCMSB: u8, + padding: u8, }), - reserved24: [4]u8, - /// privilege configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. - PRIV: u1, - padding: u31, + /// DSI Host generic payload data register. + GPDR: mmio.Mmio(packed struct(u32) { + /// DATA1. + DATA1: u8, + /// DATA2. + DATA2: u8, + /// DATA3. + DATA3: u8, + /// DATA4. + DATA4: u8, }), - reserved96: [68]u8, - /// external interrupt selection register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved - EXTI: u8, - padding: u24, + /// DSI Host generic packet status register. + GPSR: mmio.Mmio(packed struct(u32) { + /// CMDFE. + CMDFE: u1, + /// CMDFF. + CMDFF: u1, + /// PWRFE. + PWRFE: u1, + /// PWRFF. + PWRFF: u1, + /// PRDFE. + PRDFE: u1, + /// PRDFF. + PRDFF: u1, + /// RCB. + RCB: u1, + padding: u25, }), - reserved128: [16]u8, - /// CPU wakeup with interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host timeout counter configuration register 0. + TCCR0: mmio.Mmio(packed struct(u32) { + /// LPRX_TOCNT. + LPRX_TOCNT: u16, + /// HSTX_TOCNT. + HSTX_TOCNT: u16, }), - /// CPU wakeup with event mask register - EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host timeout counter configuration register 1. + TCCR1: mmio.Mmio(packed struct(u32) { + /// HSRD_TOCNT. + HSRD_TOCNT: u16, + padding: u16, }), - }; - }; - - pub const exti_l5 = struct { - /// External interrupt/event controller - pub const EXTI = extern struct { - /// Rising Trigger selection register - RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host timeout counter configuration register 2. + TCCR2: mmio.Mmio(packed struct(u32) { + /// LPRD_TOCNT. + LPRD_TOCNT: u16, + padding: u16, }), - /// Falling Trigger selection register - FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host timeout counter configuration register 3. + TCCR3: mmio.Mmio(packed struct(u32) { + /// HSWR_TOCNT. + HSWR_TOCNT: u16, + reserved24: u8, + /// PM. + PM: u1, + padding: u7, }), - /// Software interrupt event register - SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host timeout counter configuration register 4. + TCCR4: mmio.Mmio(packed struct(u32) { + /// LPWR_TOCNT. + LPWR_TOCNT: u16, + padding: u16, }), - /// Rising pending register - RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host timeout counter configuration register 5. + TCCR5: mmio.Mmio(packed struct(u32) { + /// BTA_TOCNT. + BTA_TOCNT: u16, + padding: u16, }), - /// Falling pending register - FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + reserved148: [4]u8, + /// DSI Host clock lane configuration register. + CLCR: mmio.Mmio(packed struct(u32) { + /// DPCC. + DPCC: u1, + /// ACR. + ACR: u1, + padding: u30, }), - /// Security configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x - SEC: u1, - padding: u31, + /// DSI Host clock lane timer configuration register. + CLTCR: mmio.Mmio(packed struct(u32) { + /// LP2HS_TIME. + LP2HS_TIME: u10, + reserved16: u6, + /// HS2LP_TIME. + HS2LP_TIME: u10, + padding: u6, }), - /// Privilege configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x - PRIV: u1, - padding: u31, + /// DSI Host data lane timer configuration register. + DLTCR: mmio.Mmio(packed struct(u32) { + /// LP2HS_TIME. + LP2HS_TIME: u10, + reserved16: u6, + /// HS2LP_TIME. + HS2LP_TIME: u10, + padding: u6, }), - reserved96: [68]u8, - /// Configuration register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u8, - padding: u24, + /// DSI Host PHY control register. + PCTLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// DEN. + DEN: u1, + /// CKE. + CKE: u1, + padding: u29, }), - /// EXTI lock register - LOCKRG: mmio.Mmio(packed struct(u32) { - /// LOCK - LOCK: u1, - padding: u31, + /// DSI Host PHY configuration register. + PCONFR: mmio.Mmio(packed struct(u32) { + /// NL. + NL: u2, + reserved8: u6, + /// SW_TIME. + SW_TIME: u8, + padding: u16, }), - reserved128: [12]u8, - /// Interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host PHY ULPS control register. + PUCR: mmio.Mmio(packed struct(u32) { + /// URCL. + URCL: u1, + /// UECL. + UECL: u1, + /// URDL. + URDL: u1, + /// UEDL. + UEDL: u1, + padding: u28, }), - /// Event mask register - EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// DSI Host PHY TX triggers configuration register. + PTTCR: mmio.Mmio(packed struct(u32) { + /// TX_TRIG. + TX_TRIG: u4, + padding: u28, }), - }; - }; - - pub const eth_v1a = struct { - pub const APCS = enum(u1) { - /// MAC passes all incoming frames unmodified - Disabled = 0x0, - /// MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes - Strip = 0x1, - }; - - pub const BFD = enum(u1) { - /// Address filters pass all received broadcast frames - Enabled = 0x0, - /// Address filters filter all incoming broadcast frames - Disabled = 0x1, - }; - - pub const BL = enum(u2) { - /// For retransmission n, wait up to 2^min(n, 10) time slots - BL10 = 0x0, - /// For retransmission n, wait up to 2^min(n, 8) time slots - BL8 = 0x1, - /// For retransmission n, wait up to 2^min(n, 4) time slots - BL4 = 0x2, - /// For retransmission n, wait up to 2^min(n, 1) time slots - BL1 = 0x3, - }; - - pub const CR = enum(u3) { - /// 60-100MHz HCLK/42 - CR_60_100 = 0x0, - /// 100-150 MHz HCLK/62 - CR_100_150 = 0x1, - /// 20-35MHz HCLK/16 - CR_20_35 = 0x2, - /// 35-60MHz HCLK/16 - CR_35_60 = 0x3, - /// 150-168MHz HCLK/102 - CR_150_168 = 0x4, - _, - }; - - pub const CSD = enum(u1) { - /// Errors generated due to loss of carrier - Enabled = 0x0, - /// No error generated due to loss of carrier - Disabled = 0x1, - }; - - pub const CSR = enum(u1) { - /// Counters roll over to zero after reaching the maximum value - Rollover = 0x0, - /// Counters do not roll over to zero after reaching the maximum value - NotRollover = 0x1, - }; - - pub const CounterReset = enum(u1) { - /// Reset all counters. Cleared automatically - Reset = 0x1, - _, - }; - - pub const DA = enum(u1) { - /// Round-robin with Rx:Tx priority given by PM - RoundRobin = 0x0, - /// Rx has priority over Tx - RxPriority = 0x1, - }; - - pub const DAIF = enum(u1) { - /// Normal filtering of frames - Normal = 0x0, - /// Address check block operates in inverse filtering mode for the DA address comparison - Invert = 0x1, - }; - - pub const DM = enum(u1) { - /// MAC operates in half-duplex mode - HalfDuplex = 0x0, - /// MAC operates in full-duplex mode - FullDuplex = 0x1, - }; - - pub const DMAOMR_SR = enum(u1) { - /// Reception is stopped after transfer of the current frame - Stopped = 0x0, - /// Reception is placed in the Running state - Started = 0x1, - }; - - pub const DTCEFD = enum(u1) { - /// Drop frames with errors only in the receive checksum offload engine - Enabled = 0x0, - /// Do not drop frames that only have errors in the receive checksum offload engine - Disabled = 0x1, - }; - - pub const FB = enum(u1) { - /// AHB uses SINGLE and INCR burst transfers - Variable = 0x0, - /// AHB uses only fixed burst transfers - Fixed = 0x1, - }; - - pub const FCB = enum(u1) { - /// In half duplex only, deasserts back pressure - DisableBackPressure = 0x0, - /// In full duplex, initiate a Pause control frame. In half duplex, assert back pressure - PauseOrBackPressure = 0x1, - }; + /// DSI Host PHY status register. + PSR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PD. + PD: u1, + /// PSSC. + PSSC: u1, + /// UANC. + UANC: u1, + /// PSS0. + PSS0: u1, + /// UAN0. + UAN0: u1, + /// RUE0. + RUE0: u1, + /// PSS1. + PSS1: u1, + /// UAN1. + UAN1: u1, + padding: u23, + }), + reserved188: [8]u8, + /// DSI Host interrupt and status register 0. + ISR0: mmio.Mmio(packed struct(u32) { + /// AE0. + AE0: u1, + /// AE1. + AE1: u1, + /// AE2. + AE2: u1, + /// AE3. + AE3: u1, + /// AE4. + AE4: u1, + /// AE5. + AE5: u1, + /// AE6. + AE6: u1, + /// AE7. + AE7: u1, + /// AE8. + AE8: u1, + /// AE9. + AE9: u1, + /// AE10. + AE10: u1, + /// AE11. + AE11: u1, + /// AE12. + AE12: u1, + /// AE13. + AE13: u1, + /// AE14. + AE14: u1, + /// AE15. + AE15: u1, + /// PE0. + PE0: u1, + /// PE1. + PE1: u1, + /// PE2. + PE2: u1, + /// PE3. + PE3: u1, + /// PE4. + PE4: u1, + padding: u11, + }), + /// DSI Host interrupt and status register 1. + ISR1: mmio.Mmio(packed struct(u32) { + /// TOHSTX. + TOHSTX: u1, + /// TOLPRX. + TOLPRX: u1, + /// ECCSE. + ECCSE: u1, + /// ECCME. + ECCME: u1, + /// CRCE. + CRCE: u1, + /// PSE. + PSE: u1, + /// EOTPE. + EOTPE: u1, + /// LPWRE. + LPWRE: u1, + /// GCWRE. + GCWRE: u1, + /// GPWRE. + GPWRE: u1, + /// GPTXE. + GPTXE: u1, + /// GPRDE. + GPRDE: u1, + /// GPRXE. + GPRXE: u1, + padding: u19, + }), + /// DSI Host interrupt enable register 0. + IER0: mmio.Mmio(packed struct(u32) { + /// AE0IE. + AE0IE: u1, + /// AE1IE. + AE1IE: u1, + /// AE2IE. + AE2IE: u1, + /// AE3IE. + AE3IE: u1, + /// AE4IE. + AE4IE: u1, + /// AE5IE. + AE5IE: u1, + /// AE6IE. + AE6IE: u1, + /// AE7IE. + AE7IE: u1, + /// AE8IE. + AE8IE: u1, + /// AE9IE. + AE9IE: u1, + /// AE10IE. + AE10IE: u1, + /// AE11IE. + AE11IE: u1, + /// AE12IE. + AE12IE: u1, + /// AE13IE. + AE13IE: u1, + /// AE14IE. + AE14IE: u1, + /// AE15IE. + AE15IE: u1, + /// PE0IE. + PE0IE: u1, + /// PE1IE. + PE1IE: u1, + /// PE2IE. + PE2IE: u1, + /// PE3IE. + PE3IE: u1, + /// PE4IE. + PE4IE: u1, + padding: u11, + }), + /// DSI Host interrupt enable register 1. + IER1: mmio.Mmio(packed struct(u32) { + /// TOHSTXIE. + TOHSTXIE: u1, + /// TOLPRXIE. + TOLPRXIE: u1, + /// ECCSEIE. + ECCSEIE: u1, + /// ECCMEIE. + ECCMEIE: u1, + /// CRCEIE. + CRCEIE: u1, + /// PSEIE. + PSEIE: u1, + /// EOTPEIE. + EOTPEIE: u1, + /// LPWREIE. + LPWREIE: u1, + /// GCWREIE. + GCWREIE: u1, + /// GPWREIE. + GPWREIE: u1, + /// GPTXEIE. + GPTXEIE: u1, + /// GPRDEIE. + GPRDEIE: u1, + /// GPRXEIE. + GPRXEIE: u1, + padding: u19, + }), + reserved216: [12]u8, + /// DSI Host force interrupt register 0. + FIR0: mmio.Mmio(packed struct(u32) { + /// FAE0. + FAE0: u1, + /// FAE1. + FAE1: u1, + /// FAE2. + FAE2: u1, + /// FAE3. + FAE3: u1, + /// FAE4. + FAE4: u1, + /// FAE5. + FAE5: u1, + /// FAE6. + FAE6: u1, + /// FAE7. + FAE7: u1, + /// FAE8. + FAE8: u1, + /// FAE9. + FAE9: u1, + /// FAE10. + FAE10: u1, + /// FAE11. + FAE11: u1, + /// FAE12. + FAE12: u1, + /// FAE13. + FAE13: u1, + /// FAE14. + FAE14: u1, + /// FAE15. + FAE15: u1, + /// FPE0. + FPE0: u1, + /// FPE1. + FPE1: u1, + /// FPE2. + FPE2: u1, + /// FPE3. + FPE3: u1, + /// FPE4. + FPE4: u1, + padding: u11, + }), + /// DSI Host force interrupt register 1. + FIR1: mmio.Mmio(packed struct(u32) { + /// FTOHSTX. + FTOHSTX: u1, + /// FTOLPRX. + FTOLPRX: u1, + /// FECCSE. + FECCSE: u1, + /// FECCME. + FECCME: u1, + /// FCRCE. + FCRCE: u1, + /// FPSE. + FPSE: u1, + /// FEOTPE. + FEOTPE: u1, + /// FLPWRE. + FLPWRE: u1, + /// FGCWRE. + FGCWRE: u1, + /// FGPWRE. + FGPWRE: u1, + /// FGPTXE. + FGPTXE: u1, + /// FGPRDE. + FGPRDE: u1, + /// FGPRXE. + FGPRXE: u1, + padding: u19, + }), + reserved244: [20]u8, + /// DSI Host data lane timer read configuration register. + DLTRCR: mmio.Mmio(packed struct(u32) { + /// MRD_TIME. + MRD_TIME: u15, + padding: u17, + }), + reserved256: [8]u8, + /// DSI Host video shadow control register. + VSCR: mmio.Mmio(packed struct(u32) { + /// EN. + EN: u1, + reserved8: u7, + /// UR. + UR: u1, + padding: u23, + }), + reserved268: [8]u8, + /// DSI Host LTDC current VCID register. + LCVCIDR: mmio.Mmio(packed struct(u32) { + /// VCID. + VCID: u2, + padding: u30, + }), + /// DSI Host LTDC current color coding register. + LCCCR: mmio.Mmio(packed struct(u32) { + /// COLC. + COLC: u4, + reserved8: u4, + /// LPE. + LPE: u1, + padding: u23, + }), + reserved280: [4]u8, + /// DSI Host low-power mode current configuration register. + LPMCCR: mmio.Mmio(packed struct(u32) { + /// VLPSIZE. + VLPSIZE: u8, + reserved16: u8, + /// LPSIZE. + LPSIZE: u8, + padding: u8, + }), + reserved312: [28]u8, + /// DSI Host video mode current configuration register. + VMCCR: mmio.Mmio(packed struct(u32) { + /// VMT. + VMT: u2, + /// LPVSAE. + LPVSAE: u1, + /// LPVBPE. + LPVBPE: u1, + /// LPVFPE. + LPVFPE: u1, + /// LPVAE. + LPVAE: u1, + /// LPHBPE. + LPHBPE: u1, + /// LPHFE. + LPHFE: u1, + /// FBTAAE. + FBTAAE: u1, + /// LPCE. + LPCE: u1, + padding: u22, + }), + /// DSI Host video packet current configuration register. + VPCCR: mmio.Mmio(packed struct(u32) { + /// VPSIZE. + VPSIZE: u14, + padding: u18, + }), + /// DSI Host video chunks current configuration register. + VCCCR: mmio.Mmio(packed struct(u32) { + /// NUMC. + NUMC: u13, + padding: u19, + }), + /// DSI Host video null packet current configuration register. + VNPCCR: mmio.Mmio(packed struct(u32) { + /// NPSIZE. + NPSIZE: u13, + padding: u19, + }), + /// DSI Host video HSA current configuration register. + VHSACCR: mmio.Mmio(packed struct(u32) { + /// HSA. + HSA: u12, + padding: u20, + }), + /// DSI Host video HBP current configuration register. + VHBPCCR: mmio.Mmio(packed struct(u32) { + /// HBP. + HBP: u12, + padding: u20, + }), + /// DSI Host video line current configuration register. + VLCCR: mmio.Mmio(packed struct(u32) { + /// HLINE. + HLINE: u15, + padding: u17, + }), + /// DSI Host video VSA current configuration register. + VVSACCR: mmio.Mmio(packed struct(u32) { + /// VSA. + VSA: u10, + padding: u22, + }), + /// DSI Host video VBP current configuration register. + VVBPCCR: mmio.Mmio(packed struct(u32) { + /// VBP. + VBP: u10, + padding: u22, + }), + /// DSI Host video VFP current configuration register. + VVFPCCR: mmio.Mmio(packed struct(u32) { + /// VFP. + VFP: u10, + padding: u22, + }), + /// DSI Host video VA current configuration register. + VVACCR: mmio.Mmio(packed struct(u32) { + /// VA. + VA: u14, + padding: u18, + }), + reserved1024: [668]u8, + /// DSI wrapper configuration register. + WCFGR: mmio.Mmio(packed struct(u32) { + /// DSIM. + DSIM: u1, + /// COLMUX. + COLMUX: u3, + /// TESRC. + TESRC: u1, + /// TEPOL. + TEPOL: u1, + /// AR. + AR: u1, + /// VSPOL. + VSPOL: u1, + padding: u24, + }), + /// DSI wrapper control register. + WCR: mmio.Mmio(packed struct(u32) { + /// COLM. + COLM: u1, + /// SHTDN. + SHTDN: u1, + /// LTDCEN. + LTDCEN: u1, + /// DSIEN. + DSIEN: u1, + padding: u28, + }), + /// DSI wrapper interrupt enable register. + WIER: mmio.Mmio(packed struct(u32) { + /// TEIE. + TEIE: u1, + /// ERIE. + ERIE: u1, + reserved9: u7, + /// PLLLIE. + PLLLIE: u1, + /// PLLUIE. + PLLUIE: u1, + reserved13: u2, + /// RRIE. + RRIE: u1, + padding: u18, + }), + /// DSI wrapper interrupt and status register. + WISR: mmio.Mmio(packed struct(u32) { + /// TEIF. + TEIF: u1, + /// ERIF. + ERIF: u1, + /// BUSY. + BUSY: u1, + reserved8: u5, + /// PLLLS. + PLLLS: u1, + /// PLLLIF. + PLLLIF: u1, + /// PLLUIF. + PLLUIF: u1, + reserved12: u1, + /// RRS. + RRS: u1, + /// RRIF. + RRIF: u1, + padding: u18, + }), + /// DSI wrapper interrupt flag clear register. + WIFCR: mmio.Mmio(packed struct(u32) { + /// CTEIF. + CTEIF: u1, + /// CERIF. + CERIF: u1, + reserved9: u7, + /// CPLLLIF. + CPLLLIF: u1, + /// CPLLUIF. + CPLLUIF: u1, + reserved13: u2, + /// CRRIF. + CRRIF: u1, + padding: u18, + }), + reserved1048: [4]u8, + /// DSI wrapper PHY configuration register 0. + WPCR0: mmio.Mmio(packed struct(u32) { + /// UIX4. + UIX4: u6, + /// SWCL. + SWCL: u1, + /// SWDL0. + SWDL0: u1, + /// SWDL1. + SWDL1: u1, + /// HSICL. + HSICL: u1, + /// HSIDL0. + HSIDL0: u1, + /// HSIDL1. + HSIDL1: u1, + /// FTXSMCL. + FTXSMCL: u1, + /// FTXSMDL. + FTXSMDL: u1, + /// CDOFFDL. + CDOFFDL: u1, + reserved16: u1, + /// TDDL. + TDDL: u1, + padding: u15, + }), + /// This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0). + WPCR1: mmio.Mmio(packed struct(u32) { + /// SKEWCL. + SKEWCL: u2, + /// SKEWDL. + SKEWDL: u2, + reserved6: u2, + /// LPTXSRCL. + LPTXSRCL: u2, + /// LPTXSRDL. + LPTXSRDL: u2, + reserved12: u2, + /// SDDCCL. + SDDCCL: u1, + /// SDDCDL. + SDDCDL: u1, + reserved16: u2, + /// HSTXSRUCL. + HSTXSRUCL: u1, + /// HSTXSRDCL. + HSTXSRDCL: u1, + /// HSTXSRUDL. + HSTXSRUDL: u1, + /// HSTXSRDDL. + HSTXSRDDL: u1, + padding: u12, + }), + reserved1072: [16]u8, + /// DSI wrapper regulator and PLL control register. + WRPCR: mmio.Mmio(packed struct(u32) { + /// PLLEN. + PLLEN: u1, + reserved2: u1, + /// NDIV. + NDIV: u7, + reserved11: u2, + /// IDF. + IDF: u4, + reserved16: u1, + /// ODF. + ODF: u2, + reserved24: u6, + /// REGEN. + REGEN: u1, + reserved28: u3, + /// BGREN. + BGREN: u1, + padding: u3, + }), + reserved2032: [956]u8, + /// DSI Host hardware configuration register. + HWCFGR: mmio.Mmio(packed struct(u32) { + /// TECHNO. + TECHNO: u4, + /// FIFOSIZE. + FIFOSIZE: u12, + padding: u16, + }), + /// DSI Host version register. + VERR: mmio.Mmio(packed struct(u32) { + /// MINREV. + MINREV: u4, + /// MAJREV. + MAJREV: u4, + padding: u24, + }), + /// DSI Host identification register. + IPIDR: mmio.Mmio(packed struct(u32) { + /// ID. + ID: u32, + }), + /// DSI Host size identification register. + SIDR: mmio.Mmio(packed struct(u32) { + /// SID. + SID: u32, + }), + }; + }; + + pub const dts_v1 = struct { + /// Digital temperature sensor. + pub const DTS = extern struct { + /// Temperature sensor configuration register 1. + CFGR1: mmio.Mmio(packed struct(u32) { + /// Temperature sensor 1 enable bit This bit is set and cleared by software. Note: Once enabled, the temperature sensor is active after a specific delay time. The TS1_RDY flag will be set when the sensor is ready. + EN: u1, + reserved4: u3, + /// Start frequency measurement on temperature sensor 1 This bit is set and cleared by software. + START: u1, + reserved8: u3, + /// Input trigger selection bit for temperature sensor 1 These bits are set and cleared by software. They select which input triggers a temperature measurement. Refer to Section 19.3.10: Trigger input. + INTRIG_SEL: u4, + reserved16: u4, + /// Sampling time for temperature sensor 1 These bits allow increasing the sampling time to improve measurement precision. When the PCLK clock is selected as reference clock (REFCLK_SEL = 0), the measurement will be performed at TS1_SMP_TIME period of CLK_PTAT. When the LSE is selected as reference clock (REFCLK_SEL =1), the measurement will be performed at TS1_SMP_TIME period of LSE. + SMP_TIME: u4, + /// Reference clock selection bit This bit is set and cleared by software. It indicates whether the reference clock is the high speed clock (PCLK) or the low speed clock (LSE). + REFCLK_SEL: u1, + /// Quick measurement option bit This bit is set and cleared by software. It is used to increase the measurement speed by suppressing the calibration step. It is effective only when the LSE clock is used as reference clock (REFCLK_SEL=1). + Q_MEAS_OPT: u1, + reserved24: u2, + /// High speed clock division ratio These bits are set and cleared by software. They can be used to define the division ratio for the main clock in order to obtain the internal frequency lower than 1 MHz required for the calibration. They are applicable only for calibration when PCLK is selected as reference clock (REFCLK_SEL=0). ... + HSREF_CLK_DIV: u7, + padding: u1, + }), + reserved8: [4]u8, + /// Temperature sensor T0 value register 1. + T0VALR1: mmio.Mmio(packed struct(u32) { + /// Engineering value of the frequency measured at T0 for. temperature sensor 1 This value is expressed in 0.1 kHz. + FMT0: u16, + /// Engineering value of the T0 temperature for temperature sensor 1. Others: Reserved, must not be used. + T0: u2, + padding: u14, + }), + reserved16: [4]u8, + /// Temperature sensor ramp value register. + RAMPVALR: mmio.Mmio(packed struct(u32) { + /// Engineering value of the ramp coefficient for the temperature sensor 1. This value is expressed in Hz/�C. + RAMP_COEFF: u16, + padding: u16, + }), + /// Temperature sensor interrupt threshold register 1. + ITR1: mmio.Mmio(packed struct(u32) { + /// Low interrupt threshold for temperature sensor 1 These bits are set and cleared by software. They indicate the lowest value than can be reached before raising an interrupt signal. + LITTHD: u16, + /// High interrupt threshold for temperature sensor 1 These bits are set and cleared by software. They indicate the highest value than can be reached before raising an interrupt signal. + HITTHD: u16, + }), + reserved28: [4]u8, + /// Temperature sensor data register. + DR: mmio.Mmio(packed struct(u32) { + /// Value of the counter output value for temperature sensor 1. + MFREQ: u16, + padding: u16, + }), + /// Temperature sensor status register. + SR: mmio.Mmio(packed struct(u32) { + /// Interrupt flag for end of measurement on temperature sensor 1, synchronized on PCLK. This bit is set by hardware when a temperature measure is done. It is cleared by software by writing 1 to the TS2_CITEF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITEFEN bit is set. + ITEF: u1, + /// Interrupt flag for low threshold on temperature sensor 1, synchronized on PCLK. This bit is set by hardware when the low threshold is set and reached. It is cleared by software by writing 1 to the TS1_CITLF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITLFEN bit is set. + ITLF: u1, + /// Interrupt flag for high threshold on temperature sensor 1, synchronized on PCLK This bit is set by hardware when the high threshold is set and reached. It is cleared by software by writing 1 to the TS1_CITHF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITHFEN bit is set. + ITHF: u1, + reserved4: u1, + /// Asynchronous interrupt flag for end of measure on temperature sensor 1 This bit is set by hardware when a temperature measure is done. It is cleared by software by writing 1 to the TS1_CAITEF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITEFEN bit is set. + AITEF: u1, + /// Asynchronous interrupt flag for low threshold on temperature sensor 1 This bit is set by hardware when the low threshold is reached. It is cleared by software by writing 1 to the TS1_CAITLF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITLFEN bit is set. + AITLF: u1, + /// Asynchronous interrupt flag for high threshold on temperature sensor 1 This bit is set by hardware when the high threshold is reached. It is cleared by software by writing 1 to the TS1_CAITHF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITHFEN bit is set. + AITHF: u1, + reserved15: u8, + /// Temperature sensor 1 ready flag This bit is set and reset by hardware. It indicates that a measurement is ongoing. + RDY: u1, + padding: u16, + }), + /// Temperature sensor interrupt enable register. + ITENR: mmio.Mmio(packed struct(u32) { + /// Interrupt enable flag for end of measurement on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the synchronous interrupt for end of measurement. + ITEEN: u1, + /// Interrupt enable flag for low threshold on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the synchronous interrupt when the measure reaches or is below the low threshold. + ITLEN: u1, + /// Interrupt enable flag for high threshold on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the interrupt when the measure reaches or is above the high threshold. + ITHEN: u1, + reserved4: u1, + /// Asynchronous interrupt enable flag for end of measurement on temperature sensor 1 This bit are set and cleared by software. It enables the asynchronous interrupt for end of measurement (only when REFCLK_SEL = 1). + AITEEN: u1, + /// Asynchronous interrupt enable flag for low threshold on temperature sensor 1. This bit are set and cleared by software. It enables the asynchronous interrupt when the temperature is below the low threshold (only when REFCLK_SEL= 1). + AITLEN: u1, + /// Asynchronous interrupt enable flag on high threshold for temperature sensor 1. This bit are set and cleared by software. It enables the asynchronous interrupt when the temperature is above the high threshold (only when REFCLK_SEL= 1’’). + AITHEN: u1, + padding: u25, + }), + /// Temperature sensor clear interrupt flag register. + ICIFR: mmio.Mmio(packed struct(u32) { + /// Interrupt clear flag for end of measurement on temperature sensor 1 Writing 1 to this bit clears the TS1_ITEF flag in the DTS_SR register. + CITEF: u1, + /// Interrupt clear flag for low threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_ITLF flag in the DTS_SR register. + CITLF: u1, + /// Interrupt clear flag for high threshold on temperature sensor 1 Writing this bit to 1 clears the TS1_ITHF flag in the DTS_SR register. + CITHF: u1, + reserved4: u1, + /// Write once bit. Clear the asynchronous IT flag for End Of Measure for thermal sensor 1. Writing 1 clears the TS1_AITEF flag of the DTS_SR register. + CAITEF: u1, + /// Asynchronous interrupt clear flag for low threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_AITLF flag in the DTS_SR register. + CAITLF: u1, + /// Asynchronous interrupt clear flag for high threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_AITHF flag in the DTS_SR register. + CAITHF: u1, + padding: u25, + }), + /// Temperature sensor option register. + OR: mmio.Mmio(packed struct(u32) { + /// general purpose option bits. + OP: u1, + padding: u31, + }), + }; + }; + + pub const eth_v1a = struct { + pub const APCS = enum(u1) { + /// MAC passes all incoming frames unmodified + Disabled = 0x0, + /// MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes + Strip = 0x1, + }; + + pub const BFD = enum(u1) { + /// Address filters pass all received broadcast frames + Enabled = 0x0, + /// Address filters filter all incoming broadcast frames + Disabled = 0x1, + }; + + pub const BL = enum(u2) { + /// For retransmission n, wait up to 2^min(n, 10) time slots + BL10 = 0x0, + /// For retransmission n, wait up to 2^min(n, 8) time slots + BL8 = 0x1, + /// For retransmission n, wait up to 2^min(n, 4) time slots + BL4 = 0x2, + /// For retransmission n, wait up to 2^min(n, 1) time slots + BL1 = 0x3, + }; + + pub const CR = enum(u3) { + /// 60-100MHz HCLK/42 + CR_60_100 = 0x0, + /// 100-150 MHz HCLK/62 + CR_100_150 = 0x1, + /// 20-35MHz HCLK/16 + CR_20_35 = 0x2, + /// 35-60MHz HCLK/16 + CR_35_60 = 0x3, + /// 150-168MHz HCLK/102 + CR_150_168 = 0x4, + _, + }; + + pub const CSD = enum(u1) { + /// Errors generated due to loss of carrier + Enabled = 0x0, + /// No error generated due to loss of carrier + Disabled = 0x1, + }; + + pub const CSR = enum(u1) { + /// Counters roll over to zero after reaching the maximum value + Rollover = 0x0, + /// Counters do not roll over to zero after reaching the maximum value + NotRollover = 0x1, + }; + + pub const CounterReset = enum(u1) { + /// Reset all counters. Cleared automatically + Reset = 0x1, + _, + }; + + pub const DA = enum(u1) { + /// Round-robin with Rx:Tx priority given by PM + RoundRobin = 0x0, + /// Rx has priority over Tx + RxPriority = 0x1, + }; + + pub const DAIF = enum(u1) { + /// Normal filtering of frames + Normal = 0x0, + /// Address check block operates in inverse filtering mode for the DA address comparison + Invert = 0x1, + }; + + pub const DM = enum(u1) { + /// MAC operates in half-duplex mode + HalfDuplex = 0x0, + /// MAC operates in full-duplex mode + FullDuplex = 0x1, + }; + + pub const DMAOMR_SR = enum(u1) { + /// Reception is stopped after transfer of the current frame + Stopped = 0x0, + /// Reception is placed in the Running state + Started = 0x1, + }; + + pub const DTCEFD = enum(u1) { + /// Drop frames with errors only in the receive checksum offload engine + Enabled = 0x0, + /// Do not drop frames that only have errors in the receive checksum offload engine + Disabled = 0x1, + }; + + pub const FB = enum(u1) { + /// AHB uses SINGLE and INCR burst transfers + Variable = 0x0, + /// AHB uses only fixed burst transfers + Fixed = 0x1, + }; + + pub const FCB = enum(u1) { + /// In half duplex only, deasserts back pressure + DisableBackPressure = 0x0, + /// In full duplex, initiate a Pause control frame. In half duplex, assert back pressure + PauseOrBackPressure = 0x1, + }; pub const FEF = enum(u1) { /// Rx FIFO drops frames with error status @@ -326547,3792 +325614,2733 @@ pub const types = struct { }; }; - pub const syscfg_c0 = struct { - pub const IR_MOD = enum(u2) { - /// TIM16 - TIM16 = 0x0, - /// USART1 - USART1 = 0x1, - /// USART2 - USART2 = 0x2, - _, + pub const eth_v1b = struct { + pub const APCS = enum(u1) { + /// MAC passes all incoming frames unmodified + Disabled = 0x0, + /// MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes + Strip = 0x1, }; - pub const MEM_MODE = enum(u2) { - /// Main Flash memory mapped at address 0 - MAIN_FLASH = 0x0, - /// System Flash memory mapped at address 0 - SYSTEM_FLASH = 0x1, - /// Main Flash memory mapped at address 0 (alternate encoding) - MAIN_FLASH_ALT = 0x2, - /// Embedded SRAM mapped at address 0 - SRAM = 0x3, + pub const BFD = enum(u1) { + /// Address filters pass all received broadcast frames + Enabled = 0x0, + /// Address filters filter all incoming broadcast frames + Disabled = 0x1, }; - pub const PINMUX0 = enum(u2) { - /// PB7 - PB7 = 0x0, - /// PC14 - PC14 = 0x1, + pub const BL = enum(u2) { + /// For retransmission n, wait up to 2^min(n, 10) time slots + BL10 = 0x0, + /// For retransmission n, wait up to 2^min(n, 8) time slots + BL8 = 0x1, + /// For retransmission n, wait up to 2^min(n, 4) time slots + BL4 = 0x2, + /// For retransmission n, wait up to 2^min(n, 1) time slots + BL1 = 0x3, + }; + + pub const CR = enum(u3) { + /// 60-100MHz HCLK/42 + CR_60_100 = 0x0, + /// 100-150 MHz HCLK/62 + CR_100_150 = 0x1, + /// 20-35MHz HCLK/16 + CR_20_35 = 0x2, + /// 35-60MHz HCLK/16 + CR_35_60 = 0x3, + /// 150-168MHz HCLK/102 + CR_150_168 = 0x4, _, }; - pub const PINMUX1 = enum(u2) { - /// PF2 - PF2 = 0x0, - /// PA0 - PA0 = 0x1, - /// PA1 - PA1 = 0x2, - /// PA2 - PA2 = 0x3, + pub const CSD = enum(u1) { + /// Errors generated due to loss of carrier + Enabled = 0x0, + /// No error generated due to loss of carrier + Disabled = 0x1, }; - pub const PINMUX2 = enum(u2) { - /// PA8 - PA8 = 0x0, - /// PA11 - PA11 = 0x1, - _, + pub const CSR = enum(u1) { + /// Counters roll over to zero after reaching the maximum value + Rollover = 0x0, + /// Counters do not roll over to zero after reaching the maximum value + NotRollover = 0x1, }; - pub const PINMUX3 = enum(u2) { - /// PA14 - PA14 = 0x0, - /// PB6 - PB6 = 0x1, - /// PC15 - PC15 = 0x2, + pub const CounterReset = enum(u1) { + /// Reset all counters. Cleared automatically + Reset = 0x1, _, }; - pub const PINMUX4 = enum(u2) { - /// PA7 - PA7 = 0x0, - /// PA12 - PA12 = 0x1, + pub const DA = enum(u1) { + /// Round-robin with Rx:Tx priority given by PM + RoundRobin = 0x0, + /// Rx has priority over Tx + RxPriority = 0x1, + }; + + pub const DAIF = enum(u1) { + /// Normal filtering of frames + Normal = 0x0, + /// Address check block operates in inverse filtering mode for the DA address comparison + Invert = 0x1, + }; + + pub const DM = enum(u1) { + /// MAC operates in half-duplex mode + HalfDuplex = 0x0, + /// MAC operates in full-duplex mode + FullDuplex = 0x1, + }; + + pub const DMAOMR_SR = enum(u1) { + /// Reception is stopped after transfer of the current frame + Stopped = 0x0, + /// Reception is placed in the Running state + Started = 0x1, + }; + + pub const DTCEFD = enum(u1) { + /// Drop frames with errors only in the receive checksum offload engine + Enabled = 0x0, + /// Do not drop frames that only have errors in the receive checksum offload engine + Disabled = 0x1, + }; + + pub const FB = enum(u1) { + /// AHB uses SINGLE and INCR burst transfers + Variable = 0x0, + /// AHB uses only fixed burst transfers + Fixed = 0x1, + }; + + pub const FCB = enum(u1) { + /// In half duplex only, deasserts back pressure + DisableBackPressure = 0x0, + /// In full duplex, initiate a Pause control frame. In half duplex, assert back pressure + PauseOrBackPressure = 0x1, + }; + + pub const FEF = enum(u1) { + /// Rx FIFO drops frames with error status + Drop = 0x0, + /// All frames except runt error frames are forwarded to the DMA + Forward = 0x1, + }; + + pub const FES = enum(u1) { + /// 10 Mbit/s + FES10 = 0x0, + /// 100 Mbit/s + FES100 = 0x1, + }; + + pub const FPM = enum(u1) { + /// PBL values used as-is + x1 = 0x0, + /// PBL values multiplied by 4 + x4 = 0x1, + }; + + pub const FTF = enum(u1) { + /// Transmit FIFO controller logic is reset to its default values. Cleared automatically + Flush = 0x1, _, }; - pub const PINMUX5 = enum(u2) { - /// PA3 - PA3 = 0x0, - /// PA4 - PA4 = 0x1, - /// PA5 - PA5 = 0x2, - /// PA6 - PA6 = 0x3, + pub const FUGF = enum(u1) { + /// Rx FIFO drops all frames of less than 64 bytes + Drop = 0x0, + /// Rx FIFO forwards undersized frames + Forward = 0x1, }; - /// register block - pub const SYSCFG = extern struct { - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details. - MEM_MODE: packed union { - raw: u2, - value: MEM_MODE, - }, - reserved3: u1, - /// PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. - PA11_RMP: u1, - /// PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. - PA12_RMP: u1, - /// IR output polarity selection - IR_POL: u1, - /// IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope: - IR_MOD: packed union { - raw: u2, - value: IR_MOD, - }, - reserved16: u8, - /// Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. - I2C_PB6_FMP: u1, - /// Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. - I2C_PB7_FMP: u1, - /// Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. - I2C_PB8_FMP: u1, - /// Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. - I2C_PB9_FMP: u1, - /// Fast Mode Plus (FM+) enable for I2C1 This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers. With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C1 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored. - I2C1_FMP: u1, - reserved22: u1, - /// Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. - I2C_PA9_FMP: u1, - /// Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. - I2C_PA10_FMP: u1, - /// Fast Mode Plus (FM+) enable for PC14 This bit is set and cleared by software. It enables I2C FM+ driving capability on PC14 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. - I2C_PC14_FMP: u1, - padding: u7, - }), - reserved24: [20]u8, - /// configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// Cortex�-M0+ LOCKUP enable This bit is set by software and cleared by system reset. When set, it enables the connection of Cortex�-M0+ LOCKUP (HardFault) output to the TIM1/16/17 Break input. - LOCKUP_LOCK: u1, - padding: u31, - }), - reserved60: [32]u8, - /// configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - /// Pin GPIO multiplexer 0 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved Pin F2 of WLCSP14 package GPIO assignment 1x: Reserved - PINMUX0: packed union { - raw: u2, - value: PINMUX0, - }, - /// Pin GPIO multiplexer 1 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved - PINMUX1: packed union { - raw: u2, - value: PINMUX1, - }, - /// Pin GPIO multiplexer 2 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 1x: Reserved - PINMUX2: packed union { - raw: u2, - value: PINMUX2, - }, - /// Pin GPIO multiplexer 3 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved - PINMUX3: packed union { - raw: u2, - value: PINMUX3, - }, - /// Pin GPIO multiplexer 4 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 1x: Reserved - PINMUX4: packed union { - raw: u2, - value: PINMUX4, - }, - /// Pin GPIO multiplexer 5 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved - PINMUX5: packed union { - raw: u2, - value: PINMUX5, - }, - padding: u20, - }), - reserved128: [64]u8, - /// interrupt line 0 status register - ITLINE0: mmio.Mmio(packed struct(u32) { - /// Window watchdog interrupt pending flag - WWDG: u1, - padding: u31, - }), - reserved136: [4]u8, - /// interrupt line 2 status register - ITLINE2: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// RTC interrupt request pending (EXTI line 19) - RTC: u1, - padding: u30, - }), - /// interrupt line 3 status register - ITLINE3: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Flash interface interrupt request pending - FLASH_ITF: u1, - padding: u30, - }), - /// interrupt line 4 status register - ITLINE4: mmio.Mmio(packed struct(u32) { - /// Reset and clock control interrupt request pending - RCC: u1, - padding: u31, - }), - /// interrupt line 5 status register - ITLINE5: mmio.Mmio(packed struct(u32) { - /// EXTI - EXTI: u1, - padding: u31, - }), - /// interrupt line 6 status register - ITLINE6: mmio.Mmio(packed struct(u32) { - /// EXTI - EXTI: u1, - padding: u31, - }), - /// interrupt line 7 status register - ITLINE7: mmio.Mmio(packed struct(u32) { - /// EXTI - EXTI: u1, - padding: u31, - }), - reserved164: [4]u8, - /// interrupt line 9 status register - ITLINE9: mmio.Mmio(packed struct(u32) { - /// DMA1 channel 1interrupt request pending - DMA1_CH1: u1, - padding: u31, - }), - /// interrupt line 10 status register - ITLINE10: mmio.Mmio(packed struct(u32) { - /// DMA1 channel 2 interrupt request pending - DMA1_CH2: u1, - /// DMA1 channel 3 interrupt request pending - DMA1_CH3: u1, - padding: u30, - }), - /// interrupt line 11 status register - ITLINE11: mmio.Mmio(packed struct(u32) { - /// DMAMUX interrupt request pending - DMAMUX: u1, - padding: u31, - }), - /// interrupt line 12 status register - ITLINE12: mmio.Mmio(packed struct(u32) { - /// ADC interrupt request pending - ADC: u1, - padding: u31, - }), - /// interrupt line 13 status register - ITLINE13: mmio.Mmio(packed struct(u32) { - /// Timer 1 commutation interrupt request pending - TIM1_CCU: u1, - /// Timer 1 trigger interrupt request pending - TIM1_TRG: u1, - /// Timer 1 update interrupt request pending - TIM1_UPD: u1, - /// Timer 1 break interrupt request pending - TIM1_BRK: u1, - padding: u28, - }), - /// interrupt line 14 status register - ITLINE14: mmio.Mmio(packed struct(u32) { - /// Timer 1 capture compare interrupt request pending - TIM1_CC: u1, - padding: u31, - }), - reserved192: [4]u8, - /// interrupt line 16 status register - ITLINE16: mmio.Mmio(packed struct(u32) { - /// Timer 3 interrupt request pending - TIM3: u1, - padding: u31, - }), - reserved204: [8]u8, - /// interrupt line 19 status register - ITLINE19: mmio.Mmio(packed struct(u32) { - /// Timer 14 interrupt request pending - TIM14: u1, - padding: u31, - }), - reserved212: [4]u8, - /// interrupt line 21 status register - ITLINE21: mmio.Mmio(packed struct(u32) { - /// Timer 16 interrupt request pending - TIM16: u1, - padding: u31, - }), - /// interrupt line 22 status register - ITLINE22: mmio.Mmio(packed struct(u32) { - /// Timer 17 interrupt request pending - TIM17: u1, - padding: u31, - }), - /// interrupt line 23 status register - ITLINE23: mmio.Mmio(packed struct(u32) { - /// I2C1 interrupt request pending, combined with EXTI line 23 - I2C1: u1, - padding: u31, - }), - reserved228: [4]u8, - /// interrupt line 25 status register - ITLINE25: mmio.Mmio(packed struct(u32) { - /// SPI1 interrupt request pending - SPI1: u1, - padding: u31, - }), - reserved236: [4]u8, - /// interrupt line 27 status register - ITLINE27: mmio.Mmio(packed struct(u32) { - /// USART1 interrupt request pending, combined with EXTI line 25 - USART1: u1, - padding: u31, - }), - /// interrupt line 28 status register - ITLINE28: mmio.Mmio(packed struct(u32) { - /// USART2 interrupt request pending (EXTI line 26) - USART2: u1, - padding: u31, - }), + pub const HM = enum(u1) { + /// MAC performs a perfect destination address filtering for multicast frames + Perfect = 0x0, + /// MAC performs destination address filtering of received multicast frames according to the hash table + Hash = 0x1, }; - }; - pub const rcc_wle = struct { - pub const ADCSEL = enum(u2) { - /// HSI used as ADC clock source - HSI = 0x1, - /// PLLPCLK used as ADC clock source - PLL1_P = 0x2, - /// SYSCLK used as ADC clock source - SYS = 0x3, - _, + pub const HPF = enum(u1) { + /// If HM or HU is set, only frames that match the Hash filter are passed + HashOnly = 0x0, + /// If HM or HU is set, frames that match either the perfect filter or the hash filter are passed + HashOrPerfect = 0x1, }; - pub const HPRE = enum(u4) { - /// DCLK not divided - Div1 = 0x0, - /// hclk = SYSCLK divided by 3 - Div3 = 0x1, - /// hclk = SYSCLK divided by 5 - Div5 = 0x2, - /// hclk = SYSCLK divided by 6 - Div6 = 0x5, - /// hclk = SYSCLK divided by 8 - Div10 = 0x6, - /// hclk = SYSCLK divided by 32 - Div32 = 0x7, - /// hclk = SYSCLK divided by 2 - Div2 = 0x8, - /// hclk = SYSCLK divided by 4 - Div4 = 0x9, - /// hclk = SYSCLK divided by 8 - Div8 = 0xa, - /// hclk = SYSCLK divided by 16 - Div16 = 0xb, - /// hclk = SYSCLK divided by 64 - Div64 = 0xc, - /// hclk = SYSCLK divided by 128 - Div128 = 0xd, - /// hclk = SYSCLK divided by 256 - Div256 = 0xe, - /// hclk = SYSCLK divided by 256 - Div512 = 0xf, + pub const HU = enum(u1) { + /// MAC performs a perfect destination address filtering for unicast frames + Perfect = 0x0, + /// MAC performs destination address filtering of received unicast frames according to the hash table + Hash = 0x1, + }; + + pub const IFG = enum(u3) { + /// 96 bit times + IFG96 = 0x0, + /// 88 bit times + IFG88 = 0x1, + /// 80 bit times + IFG80 = 0x2, + /// 72 bit times + IFG72 = 0x3, + /// 64 bit times + IFG64 = 0x4, + /// 56 bit times + IFG56 = 0x5, + /// 48 bit times + IFG48 = 0x6, + /// 40 bit times + IFG40 = 0x7, + }; + + pub const IPCO = enum(u1) { + /// IPv4 checksum offload disabled + Disabled = 0x0, + /// IPv4 checksums are checked in received frames + Offload = 0x1, + }; + + pub const JD = enum(u1) { + /// Jabber enabled, transmit frames up to 2048 bytes + Enabled = 0x0, + /// Jabber disabled, transmit frames up to 16384 bytes + Disabled = 0x1, + }; + + pub const LM = enum(u1) { + /// Normal mode + Normal = 0x0, + /// MAC operates in loopback mode at the MII + Loopback = 0x1, + }; + + pub const MACAHR_SA = enum(u1) { + /// This address is used for comparison with DA fields of the received frame + Destination = 0x0, + /// This address is used for comparison with SA fields of received frames + Source = 0x1, + }; + + pub const MB = enum(u1) { + /// Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below + Normal = 0x0, + /// If FB is low, start all bursts greater than 16 with INCR (undefined burst) + Mixed = 0x1, + }; + + pub const MB_progress = enum(u1) { + /// This bit is set to 1 by the application to indicate that a read or write access is in progress + Busy = 0x1, _, }; - pub const HSEPRE = enum(u1) { - Div1 = 0x0, - Div2 = 0x1, + pub const MCFHP = enum(u1) { + /// When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0 + AlmostHalf = 0x0, + /// When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0 + AlmostFull = 0x1, }; - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, + pub const MCP = enum(u1) { + /// MMC counters will be preset to almost full or almost half. Cleared automatically + Preset = 0x1, + _, }; - pub const MCOPRE = enum(u3) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x1, - /// Division by 4 - Div4 = 0x2, - /// Division by 8 - Div8 = 0x3, - /// Division by 16 - Div16 = 0x4, + pub const MW = enum(u1) { + /// Read operation + Read = 0x0, + /// Write operation + Write = 0x1, + }; + + pub const PBL = enum(u6) { + /// Maximum of 1 beat per DMA transaction + PBL1 = 0x1, + /// Maximum of 2 beats per DMA transaction + PBL2 = 0x2, + /// Maximum of 4 beats per DMA transaction + PBL4 = 0x4, + /// Maximum of 8 beats per DMA transaction + PBL8 = 0x8, + /// Maximum of 16 beats per DMA transaction + PBL16 = 0x10, + /// Maximum of 32 beats per DMA transaction + PBL32 = 0x20, _, }; - pub const MCOSEL = enum(u4) { - /// No clock - DISABLE = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// MSI oscillator clock selected - MSI = 0x2, - /// HSI oscillator clock selected - HSI = 0x3, - /// HSE oscillator clock selected - HSE = 0x4, - /// Main PLLRCLK clock selected - PLL1_R = 0x5, - /// LSI oscillator clock selected - LSI = 0x6, - /// LSE oscillator clock selected - LSE = 0x8, - /// Main PLLCLK oscillator clock selected - PLL1_P = 0xd, - /// Main PLLQCLK oscillator clock selected - PLL1_Q = 0xe, + pub const PCF = enum(u2) { + /// MAC prevents all control frames from reaching the application + PreventAll = 0x0, + /// MAC forwards all control frames to application except Pause + ForwardAllExceptPause = 0x1, + /// MAC forwards all control frames to application even if they fail the address filter + ForwardAll = 0x2, + /// MAC forwards control frames that pass the address filter + ForwardAllFiltered = 0x3, + }; + + pub const PD = enum(u1) { + /// All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received + Enabled = 0x1, _, }; - pub const MSIRANGE = enum(u4) { - /// range 0 around 100 kHz - Range100K = 0x0, - /// range 1 around 200 kHz - Range200K = 0x1, - /// range 2 around 400 kHz - Range400K = 0x2, - /// range 3 around 800 kHz - Range800K = 0x3, - /// range 4 around 1 MHz - Range1M = 0x4, - /// range 5 around 2 MHz - Range2M = 0x5, - /// range 6 around 4 MHz - Range4M = 0x6, - /// range 7 around 8 MHz - Range8M = 0x7, - /// range 8 around 16 MHz - Range16M = 0x8, - /// range 9 around 24 MHz - Range24M = 0x9, - /// range 10 around 32 MHz - Range32M = 0xa, - /// range 11 around 48 MHz - Range48M = 0xb, + pub const PLT = enum(u2) { + /// Pause time minus 4 slot times + PLT4 = 0x0, + /// Pause time minus 28 slot times + PLT28 = 0x1, + /// Pause time minus 144 slot times + PLT144 = 0x2, + /// Pause time minus 256 slot times + PLT256 = 0x3, + }; + + pub const PMTIM = enum(u1) { + /// PMT Status interrupt generation enabled + Unmasked = 0x0, + /// PMT Status interrupt generation disabled + Masked = 0x1, + }; + + pub const PriorityRxOverTx = enum(u2) { + /// RxDMA priority over TxDMA is 1:1 + OneToOne = 0x0, + /// RxDMA priority over TxDMA is 2:1 + TwoToOne = 0x1, + /// RxDMA priority over TxDMA is 3:1 + ThreeToOne = 0x2, + /// RxDMA priority over TxDMA is 4:1 + FourToOne = 0x3, + }; + + pub const RD = enum(u1) { + /// MAC attempts retries based on the settings of BL + Enabled = 0x0, + /// MAC attempts only 1 transmission + Disabled = 0x1, + }; + + pub const RDP = enum(u6) { + /// 1 beat per RxDMA transaction + RDP1 = 0x1, + /// 2 beats per RxDMA transaction + RDP2 = 0x2, + /// 4 beats per RxDMA transaction + RDP4 = 0x4, + /// 8 beats per RxDMA transaction + RDP8 = 0x8, + /// 16 beats per RxDMA transaction + RDP16 = 0x10, + /// 32 beats per RxDMA transaction + RDP32 = 0x20, _, }; - pub const MSIRGSEL = enum(u1) { - /// MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register - CSR = 0x0, - /// MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register - CR = 0x1, + pub const RFAEM = enum(u1) { + /// Received-alignment-error counter half-full interrupt enabled + Unmasked = 0x0, + /// Received-alignment-error counter half-full interrupt disabled + Masked = 0x1, }; - pub const PLLM = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, + pub const RFCEM = enum(u1) { + /// Received-crc-error counter half-full interrupt enabled + Unmasked = 0x0, + /// Received-crc-error counter half-full interrupt disabled + Masked = 0x1, }; - pub const PLLN = enum(u7) { - Mul6 = 0x6, - Mul7 = 0x7, - Mul8 = 0x8, - Mul9 = 0x9, - Mul10 = 0xa, - Mul11 = 0xb, - Mul12 = 0xc, - Mul13 = 0xd, - Mul14 = 0xe, - Mul15 = 0xf, - Mul16 = 0x10, - Mul17 = 0x11, - Mul18 = 0x12, - Mul19 = 0x13, - Mul20 = 0x14, - Mul21 = 0x15, - Mul22 = 0x16, - Mul23 = 0x17, - Mul24 = 0x18, - Mul25 = 0x19, - Mul26 = 0x1a, - Mul27 = 0x1b, - Mul28 = 0x1c, - Mul29 = 0x1d, - Mul30 = 0x1e, - Mul31 = 0x1f, - Mul32 = 0x20, - Mul33 = 0x21, - Mul34 = 0x22, - Mul35 = 0x23, - Mul36 = 0x24, - Mul37 = 0x25, - Mul38 = 0x26, - Mul39 = 0x27, - Mul40 = 0x28, - Mul41 = 0x29, - Mul42 = 0x2a, - Mul43 = 0x2b, - Mul44 = 0x2c, - Mul45 = 0x2d, - Mul46 = 0x2e, - Mul47 = 0x2f, - Mul48 = 0x30, - Mul49 = 0x31, - Mul50 = 0x32, - Mul51 = 0x33, - Mul52 = 0x34, - Mul53 = 0x35, - Mul54 = 0x36, - Mul55 = 0x37, - Mul56 = 0x38, - Mul57 = 0x39, - Mul58 = 0x3a, - Mul59 = 0x3b, - Mul60 = 0x3c, - Mul61 = 0x3d, - Mul62 = 0x3e, - Mul63 = 0x3f, - Mul64 = 0x40, - Mul65 = 0x41, - Mul66 = 0x42, - Mul67 = 0x43, - Mul68 = 0x44, - Mul69 = 0x45, - Mul70 = 0x46, - Mul71 = 0x47, - Mul72 = 0x48, - Mul73 = 0x49, - Mul74 = 0x4a, - Mul75 = 0x4b, - Mul76 = 0x4c, - Mul77 = 0x4d, - Mul78 = 0x4e, - Mul79 = 0x4f, - Mul80 = 0x50, - Mul81 = 0x51, - Mul82 = 0x52, - Mul83 = 0x53, - Mul84 = 0x54, - Mul85 = 0x55, - Mul86 = 0x56, - Mul87 = 0x57, - Mul88 = 0x58, - Mul89 = 0x59, - Mul90 = 0x5a, - Mul91 = 0x5b, - Mul92 = 0x5c, - Mul93 = 0x5d, - Mul94 = 0x5e, - Mul95 = 0x5f, - Mul96 = 0x60, - Mul97 = 0x61, - Mul98 = 0x62, - Mul99 = 0x63, - Mul100 = 0x64, - Mul101 = 0x65, - Mul102 = 0x66, - Mul103 = 0x67, - Mul104 = 0x68, - Mul105 = 0x69, - Mul106 = 0x6a, - Mul107 = 0x6b, - Mul108 = 0x6c, - Mul109 = 0x6d, - Mul110 = 0x6e, - Mul111 = 0x6f, - Mul112 = 0x70, - Mul113 = 0x71, - Mul114 = 0x72, - Mul115 = 0x73, - Mul116 = 0x74, - Mul117 = 0x75, - Mul118 = 0x76, - Mul119 = 0x77, - Mul120 = 0x78, - Mul121 = 0x79, - Mul122 = 0x7a, - Mul123 = 0x7b, - Mul124 = 0x7c, - Mul125 = 0x7d, - Mul126 = 0x7e, - Mul127 = 0x7f, + pub const RGUFM = enum(u1) { + /// Received-good-unicast counter half-full interrupt enabled + Unmasked = 0x0, + /// Received-good-unicast counter half-full interrupt disabled + Masked = 0x1, + }; + + pub const ROD = enum(u1) { + /// MAC receives all packets from PHY while transmitting + Enabled = 0x0, + /// MAC disables reception of frames in half-duplex mode + Disabled = 0x1, + }; + + pub const RPD = enum(u32) { + /// Poll the receive descriptor list + Poll = 0x0, _, }; - pub const PLLP = enum(u5) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, - Div17 = 0x10, - Div18 = 0x11, - Div19 = 0x12, - Div20 = 0x13, - Div21 = 0x14, - Div22 = 0x15, - Div23 = 0x16, - Div24 = 0x17, - Div25 = 0x18, - Div26 = 0x19, - Div27 = 0x1a, - Div28 = 0x1b, - Div29 = 0x1c, - Div30 = 0x1d, - Div31 = 0x1e, + pub const RPS = enum(u3) { + /// Stopped, reset or Stop Receive command issued + Stopped = 0x0, + /// Running, fetching receive transfer descriptor + RunningFetching = 0x1, + /// Running, waiting for receive packet + RunningWaiting = 0x3, + /// Suspended, receive descriptor unavailable + Suspended = 0x4, + /// Running, writing data to host memory buffer + RunningWriting = 0x7, _, }; - pub const PLLQ = enum(u3) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, + pub const RSF = enum(u1) { + /// Rx FIFO operates in cut-through mode, subject to RTC bits + CutThrough = 0x0, + /// Frames are read from Rx FIFO after complete frame has been written + StoreForward = 0x1, + }; + + pub const RTC = enum(u2) { + /// 64 bytes + RTC64 = 0x0, + /// 32 bytes + RTC32 = 0x1, + /// 96 bytes + RTC96 = 0x2, + /// 128 bytes + RTC128 = 0x3, + }; + + pub const SAIF = enum(u1) { + /// Source address filter operates normally + Normal = 0x0, + /// Source address filter operation inverted + Invert = 0x1, + }; + + pub const ST = enum(u1) { + /// Transmission is placed in the Stopped state + Stopped = 0x0, + /// Transmission is placed in Running state + Started = 0x1, + }; + + pub const TGFM = enum(u1) { + /// Transmitted-good counter half-full interrupt enabled + Unmasked = 0x0, + /// Transmitted-good counter half-full interrupt disabled + Masked = 0x1, + }; + + pub const TGFMSCM = enum(u1) { + /// Transmitted-good-multiple-collision half-full interrupt enabled + Unmasked = 0x0, + /// Transmitted-good-multiple-collision half-full interrupt disabled + Masked = 0x1, + }; + + pub const TGFSCM = enum(u1) { + /// Transmitted-good-single-collision half-full interrupt enabled + Unmasked = 0x0, + /// Transmitted-good-single-collision half-full interrupt disabled + Masked = 0x1, + }; + + pub const TPD = enum(u32) { + /// Poll the transmit descriptor list + Poll = 0x0, _, }; - pub const PLLR = enum(u3) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, + pub const TPS = enum(u3) { + /// Stopped, Reset or Stop Transmit command issued + Stopped = 0x0, + /// Running, fetching transmit transfer descriptor + RunningFetching = 0x1, + /// Running, waiting for status + RunningWaiting = 0x2, + /// Running, reading data from host memory buffer + RunningReading = 0x3, + /// Suspended, transmit descriptor unavailable or transmit buffer underflow + Suspended = 0x6, + /// Running, closing transmit descriptor + Running = 0x7, _, }; - pub const PLLSRC = enum(u2) { - /// No clock selected as PLL entry clock source - DISABLE = 0x0, - /// MSI selected as PLL entry clock source - MSI = 0x1, - /// HSI selected as PLL entry clock source - HSI = 0x2, - /// HSE selected as PLL entry clock source - HSE = 0x3, + pub const TSF = enum(u1) { + /// Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold + CutThrough = 0x0, + /// Transmission starts when a full frame is in the Tx FIFO + StoreForward = 0x1, }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, + pub const TSTIM = enum(u1) { + /// Time stamp interrupt generation enabled + Unmasked = 0x0, + /// Time stamp interrupt generation disabled + Masked = 0x1, }; - pub const RNGSEL = enum(u2) { - PLL1_Q = 0x0, - LSI = 0x1, - LSE = 0x2, - MSI = 0x3, + pub const TTC = enum(u3) { + /// 64 bytes + TTC64 = 0x0, + /// 128 bytes + TTC128 = 0x1, + /// 192 bytes + TTC192 = 0x2, + /// 256 bytes + TTC256 = 0x3, + /// 40 bytes + TTC40 = 0x4, + /// 32 bytes + TTC32 = 0x5, + /// 24 bytes + TTC24 = 0x6, + /// 16 bytes + TTC16 = 0x7, }; - pub const RTCSEL = enum(u2) { - /// No clock selected - DISABLE = 0x0, - /// LSE oscillator clock selected - LSE = 0x1, - /// LSI oscillator clock selected - LSI = 0x2, - /// HSE oscillator clock divided by 32 selected - HSE = 0x3, + pub const USP = enum(u1) { + /// PBL value used for both Rx and Tx DMA + Combined = 0x0, + /// RxDMA uses RDP value, TxDMA uses PBL value + Separate = 0x1, }; - pub const SW = enum(u2) { - MSI = 0x0, - HSI = 0x1, - HSE = 0x2, - PLL1_R = 0x3, + pub const VLANTC = enum(u1) { + /// Full 16 bit VLAN identifiers are used for comparison and filtering + VLANTC16 = 0x0, + /// 12 bit VLAN identifies are used for comparison and filtering + VLANTC12 = 0x1, }; - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// MSI clock enable - MSION: u1, - /// MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) - MSIRDY: u1, - /// MSI clock PLL enable - MSIPLLEN: u1, - /// MSI range control selection - MSIRGSEL: packed union { - raw: u1, - value: MSIRGSEL, - }, - /// MSI clock ranges - MSIRANGE: packed union { - raw: u4, - value: MSIRANGE, - }, - /// HSI clock enable - HSION: u1, - /// HSI always enable for peripheral kernel clocks. - HSIKERON: u1, - /// HSI clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI is ready) - HSIRDY: u1, - /// HSI automatic start from Stop - HSIASFS: u1, - /// HSI kernel clock ready flag for peripherals requests. - HSIKERDY: u1, - reserved16: u3, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - reserved19: u1, - /// HSE Clock security system enable - CSSON: u1, - /// HSE sysclk prescaler - HSEPRE: packed union { + pub const WD = enum(u1) { + /// Watchdog enabled, receive frames limited to 2048 bytes + Enabled = 0x0, + /// Watchdog disabled, receive frames may be up to to 16384 bytes + Disabled = 0x1, + }; + + pub const WFFRPR = enum(u1) { + /// Reset wakeup frame filter register point to 0b000. Automatically cleared + Reset = 0x1, + _, + }; + + pub const ZQPD = enum(u1) { + /// Normal operation with automatic zero-quanta pause control frame generation + Enabled = 0x0, + /// Automatic generation of zero-quanta pause control frames is disabled + Disabled = 0x1, + }; + + /// Ethernet Peripheral + pub const ETH = extern struct { + /// Ethernet: media access control (MAC) + ETHERNET_MAC: u32, + reserved1792: [1788]u8, + /// Ethernet: Precision Time Protocol (PTP) + ETHERNET_PTP: u32, + reserved4096: [2300]u8, + /// Ethernet: DMA mode register (DMA) + ETHERNET_DMA: u32, + }; + + /// Ethernet: DMA controller operation + pub const ETHERNET_DMA = extern struct { + /// Ethernet DMA bus mode register + DMABMR: mmio.Mmio(packed struct(u32) { + /// Software reset + SR: u1, + /// DMA arbitration + DA: packed union { raw: u1, - value: HSEPRE, + value: DA, }, - /// Enable HSE VDDTCXO output on package pin PB0-VDDTCXO. - HSEBYPPWR: u1, - reserved24: u2, - /// Main PLL enable - PLLON: u1, - /// Main PLL clock ready flag - PLLRDY: u1, - padding: u6, - }), - /// Internal clock sources calibration register - ICSCR: mmio.Mmio(packed struct(u32) { - /// MSI clock calibration - MSICAL: u8, - /// MSI clock trimming - MSITRIM: u8, - /// HSI clock calibration - HSICAL: u8, - /// HSI clock trimming - HSITRIM: u7, - padding: u1, - }), - /// Clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u2, - value: SW, + /// Descriptor skip length + DSL: u5, + /// Enhanced descriptor format enable + EDFE: u1, + /// Programmable burst length + PBL: packed union { + raw: u6, + value: PBL, }, - /// System clock switch status - SWS: packed union { + /// Rx-Tx priority ratio + PM: packed union { raw: u2, - value: SW, + value: PriorityRxOverTx, }, - /// HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.) - HPRE: packed union { - raw: u4, - value: HPRE, + /// Fixed burst + FB: packed union { + raw: u1, + value: FB, }, - /// PCLK1 low-speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, + /// Rx DMA PBL + RDP: packed union { + raw: u6, + value: RDP, }, - /// PCLK2 high-speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, + /// Use separate PBL + USP: packed union { + raw: u1, + value: USP, }, - reserved15: u1, - /// Wakeup from Stop and CSS backup clock selection - STOPWUCK: u1, - /// HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1) - HPREF: u1, - /// PCLK1 prescaler flag (APB1) - PPRE1F: u1, - /// PCLK2 prescaler flag (APB2) - PPRE2F: u1, - reserved24: u5, - /// Microcontroller clock output - MCOSEL: packed union { - raw: u4, - value: MCOSEL, + /// 4xPBL mode + FPM: packed union { + raw: u1, + value: FPM, }, - /// Microcontroller clock output prescaler - MCOPRE: packed union { - raw: u3, - value: MCOPRE, + /// Address-aligned beats + AAB: u1, + /// Mixed burst + MB: packed union { + raw: u1, + value: MB, }, - padding: u1, + padding: u5, }), - /// PLL configuration register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// Main PLL entry clock source - PLLSRC: packed union { - raw: u2, - value: PLLSRC, + /// Ethernet DMA transmit poll demand register + DMATPDR: mmio.Mmio(packed struct(u32) { + /// Transmit poll demand + TPD: packed union { + raw: u32, + value: TPD, }, - reserved4: u2, - /// Division factor for the main PLL input clock - PLLM: packed union { - raw: u3, - value: PLLM, + }), + /// EHERNET DMA receive poll demand register + DMARPDR: mmio.Mmio(packed struct(u32) { + /// Receive poll demand + RPD: packed union { + raw: u32, + value: RPD, }, - reserved8: u1, - /// Main PLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, - }, - reserved16: u1, - /// Main PLL PLLPCLK output enable - PLLPEN: u1, - /// Main PLL division factor for PLLPCLK. - PLLP: packed union { - raw: u5, - value: PLLP, + }), + /// Ethernet DMA receive descriptor list address register + DMARDLAR: mmio.Mmio(packed struct(u32) { + /// Start of receive list + SRL: u32, + }), + /// Ethernet DMA transmit descriptor list address register + DMATDLAR: mmio.Mmio(packed struct(u32) { + /// Start of transmit list + STL: u32, + }), + /// Ethernet DMA status register + DMASR: mmio.Mmio(packed struct(u32) { + /// Transmit status + TS: u1, + /// Transmit process stopped status + TPSS: u1, + /// Transmit buffer unavailable status + TBUS: u1, + /// Transmit jabber timeout status + TJTS: u1, + /// Receive overflow status + ROS: u1, + /// Transmit underflow status + TUS: u1, + /// Receive status + RS: u1, + /// Receive buffer unavailable status + RBUS: u1, + /// Receive process stopped status + RPSS: u1, + /// PWTS + PWTS: u1, + /// Early transmit status + ETS: u1, + reserved13: u2, + /// Fatal bus error status + FBES: u1, + /// Early receive status + ERS: u1, + /// Abnormal interrupt summary + AIS: u1, + /// Normal interrupt summary + NIS: u1, + /// Receive process state + RPS: packed union { + raw: u3, + value: RPS, }, - reserved24: u2, - /// Main PLL PLLQCLK output enable - PLLQEN: u1, - /// Main PLL division factor for PLLQCLK - PLLQ: packed union { + /// Transmit process state + TPS: packed union { raw: u3, - value: PLLQ, + value: TPS, }, - /// Main PLL PLLRCLK output enable - PLLREN: u1, - /// Main PLL division factor for PLLRCLK - PLLR: packed union { + /// Error bits status + EBS: u3, + reserved27: u1, + /// MMC status + MMCS: u1, + /// PMT status + PMTS: u1, + /// Time stamp trigger status + TSTS: u1, + padding: u2, + }), + /// Ethernet DMA operation mode register + DMAOMR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Start/stop receive + SR: packed union { + raw: u1, + value: DMAOMR_SR, + }, + /// Operate on second frame + OSF: u1, + /// Receive threshold control + RTC: packed union { + raw: u2, + value: RTC, + }, + reserved6: u1, + /// Forward undersized good frames + FUGF: packed union { + raw: u1, + value: FUGF, + }, + /// Forward error frames + FEF: packed union { + raw: u1, + value: FEF, + }, + reserved13: u5, + /// Start/stop transmission + ST: packed union { + raw: u1, + value: ST, + }, + /// Transmit threshold control + TTC: packed union { raw: u3, - value: PLLR, + value: TTC, + }, + reserved20: u3, + /// Flush transmit FIFO + FTF: packed union { + raw: u1, + value: FTF, + }, + /// Transmit store and forward + TSF: packed union { + raw: u1, + value: TSF, }, + reserved24: u2, + /// Disable flushing of received frames + DFRF: u1, + /// Receive store and forward + RSF: packed union { + raw: u1, + value: RSF, + }, + /// Dropping of TCP/IP checksum error frames disable + DTCEFD: packed union { + raw: u1, + value: DTCEFD, + }, + padding: u5, }), - reserved24: [8]u8, - /// Clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - /// MSI ready interrupt enable - MSIRDYIE: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// PLL ready interrupt enable - PLLRDYIE: u1, - reserved9: u3, - /// LSE clock security system interrupt enable - LSECSSIE: u1, - padding: u22, + /// Ethernet DMA interrupt enable register + DMAIER: mmio.Mmio(packed struct(u32) { + /// Transmit interrupt enable + TIE: u1, + /// Transmit process stopped interrupt enable + TPSIE: u1, + /// Transmit buffer unavailable interrupt enable + TBUIE: u1, + /// Transmit jabber timeout interrupt enable + TJTIE: u1, + /// Receive overflow interrupt enable + ROIE: u1, + /// Transmit underflow interrupt enable + TUIE: u1, + /// Receive interrupt enable + RIE: u1, + /// Receive buffer unavailable interrupt enable + RBUIE: u1, + /// Receive process stopped interrupt enable + RPSIE: u1, + /// Receive watchdog timeout interrupt enable + RWTIE: u1, + /// Early transmit interrupt enable + ETIE: u1, + reserved13: u2, + /// Fatal bus error interrupt enable + FBEIE: u1, + /// Early receive interrupt enable + ERIE: u1, + /// Abnormal interrupt summary enable + AISE: u1, + /// Normal interrupt summary enable + NISE: u1, + padding: u15, }), - /// Clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// MSI ready interrupt flag - MSIRDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// PLL ready interrupt flag - PLLRDYF: u1, - reserved8: u2, - /// HSE Clock security system interrupt flag - CSSF: u1, - /// LSE Clock security system interrupt flag - LSECSSF: u1, - padding: u22, + /// Ethernet DMA missed frame and buffer overflow counter register + DMAMFBOCR: mmio.Mmio(packed struct(u32) { + /// Missed frames by the controller + MFC: u16, + /// Overflow bit for missed frame counter + OMFC: u1, + /// Missed frames by the application + MFA: u11, + /// Overflow bit for FIFO overflow counter + OFOC: u1, + padding: u3, }), - /// Clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// MSI ready interrupt clear - MSIRDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// PLL ready interrupt clear - PLLRDYC: u1, - reserved8: u2, - /// HSE Clock security system interrupt clear - CSSC: u1, - /// LSE Clock security system interrupt clear - LSECSSC: u1, - padding: u22, + /// Ethernet DMA receive status watchdog timer register + DMARSWTR: mmio.Mmio(packed struct(u32) { + /// Receive status watchdog timer count + RSWTC: u8, + padding: u24, }), - reserved40: [4]u8, - /// AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - /// DMAMUX1 reset - DMAMUX1RST: u1, - reserved12: u9, - /// CRC reset - CRCRST: u1, - padding: u19, + reserved72: [32]u8, + /// Ethernet DMA current host transmit descriptor register + DMACHTDR: mmio.Mmio(packed struct(u32) { + /// Host transmit descriptor address pointer + HTDAP: u32, }), - /// AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - reserved7: u4, - /// IO port H reset - GPIOHRST: u1, - padding: u24, + /// Ethernet DMA current host receive descriptor register + DMACHRDR: mmio.Mmio(packed struct(u32) { + /// Host receive descriptor address pointer + HRDAP: u32, }), - /// AHB3 peripheral reset register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// PKARST - PKARST: u1, - /// AESRST - AESRST: u1, - /// RNGRST - RNGRST: u1, - /// HSEMRST - HSEMRST: u1, - reserved25: u5, - /// Flash interface reset - FLASHRST: u1, + /// Ethernet DMA current host transmit buffer address register + DMACHTBAR: mmio.Mmio(packed struct(u32) { + /// Host transmit buffer address pointer + HTBAP: u32, + }), + /// Ethernet DMA current host receive buffer address register + DMACHRBAR: mmio.Mmio(packed struct(u32) { + /// Host receive buffer address pointer + HRBAP: u32, + }), + }; + + /// Ethernet: media access control (MAC) + pub const ETHERNET_MAC = extern struct { + /// Ethernet MAC configuration register + MACCR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// Deferral check + DC: u1, + /// Back-off limit + BL: packed union { + raw: u2, + value: BL, + }, + /// Automatic pad/CRC stripping + APCS: packed union { + raw: u1, + value: APCS, + }, + reserved9: u1, + /// Retry disable + RD: packed union { + raw: u1, + value: RD, + }, + /// IPv4 checksum offload + IPCO: packed union { + raw: u1, + value: IPCO, + }, + /// Duplex mode + DM: packed union { + raw: u1, + value: DM, + }, + /// Loopback mode + LM: packed union { + raw: u1, + value: LM, + }, + /// Receive own disable + ROD: packed union { + raw: u1, + value: ROD, + }, + /// Fast Ethernet speed + FES: packed union { + raw: u1, + value: FES, + }, + reserved16: u1, + /// Carrier sense disable + CSD: packed union { + raw: u1, + value: CSD, + }, + /// Interframe gap + IFG: packed union { + raw: u3, + value: IFG, + }, + reserved22: u2, + /// Jabber disable + JD: packed union { + raw: u1, + value: JD, + }, + /// Watchdog disable + WD: packed union { + raw: u1, + value: WD, + }, + reserved25: u1, + /// CRC stripping for type frames + CSTF: u1, padding: u6, }), - reserved56: [4]u8, - /// APB1 peripheral reset register 1 - APB1RSTR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer reset - TIM2RST: u1, - reserved14: u13, - /// SPI2 reset - SPI2RST: u1, - reserved17: u2, - /// USART2 reset - USART2RST: u1, - reserved21: u3, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// I2C3 reset - I2C3RST: u1, - reserved29: u5, - /// DAC reset - DACRST: u1, - reserved31: u1, - /// Low Power Timer 1 reset - LPTIM1RST: u1, + /// Ethernet MAC frame filter register + MACFFR: mmio.Mmio(packed struct(u32) { + /// Promiscuous mode + PM: u1, + /// Hash unicast + HU: packed union { + raw: u1, + value: HU, + }, + /// Hash multicast + HM: packed union { + raw: u1, + value: HM, + }, + /// Destination address unique filtering + DAIF: packed union { + raw: u1, + value: DAIF, + }, + /// Pass all multicast + PAM: u1, + /// Broadcast frames disable + BFD: packed union { + raw: u1, + value: BFD, + }, + /// Pass control frames + PCF: packed union { + raw: u2, + value: PCF, + }, + /// Source address filter + SAF: u1, + /// Hash or perfect filter + HPF: packed union { + raw: u1, + value: HPF, + }, + reserved31: u21, + /// Receive all + RA: u1, }), - /// APB1 peripheral reset register 2 - APB1RSTR2: mmio.Mmio(packed struct(u32) { - /// Low-power UART 1 reset - LPUART1RST: u1, - reserved5: u4, - /// Low-power timer 2 reset - LPTIM2RST: u1, - /// Low-power timer 3 reset - LPTIM3RST: u1, - padding: u25, + /// Ethernet MAC hash table high register + MACHTHR: mmio.Mmio(packed struct(u32) { + /// Upper 32 bits of hash table + HTH: u32, }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - reserved9: u9, - /// ADC reset - ADCRST: u1, - reserved11: u1, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI1 reset - SPI1RST: u1, - reserved14: u1, - /// USART1 reset - USART1RST: u1, - reserved17: u2, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - padding: u13, + /// Ethernet MAC hash table low register + MACHTLR: mmio.Mmio(packed struct(u32) { + /// Lower 32 bits of hash table + HTL: u32, }), - /// APB3 peripheral reset register - APB3RSTR: mmio.Mmio(packed struct(u32) { - /// Sub-GHz radio SPI reset - SUBGHZSPIRST: u1, - padding: u31, + /// Ethernet MAC MII address register + MACMIIAR: mmio.Mmio(packed struct(u32) { + /// MII busy + MB: packed union { + raw: u1, + value: MB_progress, + }, + /// MII write + MW: packed union { + raw: u1, + value: MW, + }, + /// Clock range + CR: packed union { + raw: u3, + value: CR, + }, + reserved6: u1, + /// MII register - select the desired MII register in the PHY device + MR: u5, + /// PHY address - select which of possible 32 PHYs is being accessed + PA: u5, + padding: u16, }), - /// AHB1 peripheral clock enable register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// CPU1 DMA1 clock enable - DMA1EN: u1, - /// CPU1 DMA2 clock enable - DMA2EN: u1, - /// CPU1 DMAMUX1 clock enable - DMAMUX1EN: u1, - reserved12: u9, - /// CPU1 CRC clock enable - CRCEN: u1, - padding: u19, + /// Ethernet MAC MII data register + MACMIIDR: mmio.Mmio(packed struct(u32) { + /// MII data read from/written to the PHY + MD: u16, + padding: u16, }), - /// AHB2 peripheral clock enable register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// CPU1 IO port A clock enable - GPIOAEN: u1, - /// CPU1 IO port B clock enable - GPIOBEN: u1, - /// CPU1 IO port C clock enable - GPIOCEN: u1, - reserved7: u4, - /// CPU1 IO port H clock enable - GPIOHEN: u1, - padding: u24, + /// Ethernet MAC flow control register + MACFCR: mmio.Mmio(packed struct(u32) { + /// Flow control busy/back pressure activate + FCB: packed union { + raw: u1, + value: FCB, + }, + /// Transmit flow control enable + TFCE: u1, + /// Receive flow control enable + RFCE: u1, + /// Unicast pause frame detect + UPFD: u1, + /// Pause low threshold + PLT: packed union { + raw: u2, + value: PLT, + }, + reserved7: u1, + /// Zero-quanta pause disable + ZQPD: packed union { + raw: u1, + value: ZQPD, + }, + reserved16: u8, + /// Pause time + PT: u16, }), - /// AHB3 peripheral clock enable register - AHB3ENR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// PKAEN - PKAEN: u1, - /// AESEN - AESEN: u1, - /// RNGEN - RNGEN: u1, - /// HSEMEN - HSEMEN: u1, - reserved25: u5, - /// CPU1 Flash interface clock enable - FLASHEN: u1, - padding: u6, + /// Ethernet MAC VLAN tag register + MACVLANTR: mmio.Mmio(packed struct(u32) { + /// VLAN tag identifier (for receive frames) + VLANTI: u16, + /// 12-bit VLAN tag comparison + VLANTC: packed union { + raw: u1, + value: VLANTC, + }, + padding: u15, }), - reserved88: [4]u8, - /// APB1 peripheral clock enable register 1 - APB1ENR1: mmio.Mmio(packed struct(u32) { - /// CPU1 TIM2 timer clock enable - TIM2EN: u1, - reserved10: u9, - /// CPU1 RTC APB clock enable - RTCAPBEN: u1, - /// CPU1 Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// CPU1 SPI2 clock enable - SPI2EN: u1, - reserved17: u2, - /// CPU1 USART2 clock enable - USART2EN: u1, - reserved21: u3, - /// CPU1 I2C1 clocks enable - I2C1EN: u1, - /// CPU1 I2C2 clocks enable - I2C2EN: u1, - /// CPU1 I2C3 clocks enable - I2C3EN: u1, - reserved29: u5, - /// CPU1 DAC clock enable - DACEN: u1, - reserved31: u1, - /// CPU1 Low power timer 1 clocks enable - LPTIM1EN: u1, + reserved40: [8]u8, + /// Ethernet MAC remote wakeup frame filter register + MACRWUFFR: u32, + /// Ethernet MAC PMT control and status register + MACPMTCSR: mmio.Mmio(packed struct(u32) { + /// Power down + PD: packed union { + raw: u1, + value: PD, + }, + /// Magic packet enable + MPE: u1, + /// Wakeup frame enable + WFE: u1, + reserved5: u2, + /// Magic packet received + MPR: u1, + /// Wakeup frame received + WFR: u1, + reserved9: u2, + /// Global unicast + GU: u1, + reserved31: u21, + /// Wakeup frame filter register pointer reset + WFFRPR: packed union { + raw: u1, + value: WFFRPR, + }, }), - /// APB1 peripheral clock enable register 2 - APB1ENR2: mmio.Mmio(packed struct(u32) { - /// CPU1 Low power UART 1 clocks enable - LPUART1EN: u1, - reserved5: u4, - /// CPU1 Low power timer 2 clocks enable - LPTIM2EN: u1, - /// CPU1 Low power timer 3 clocks enable - LPTIM3EN: u1, - padding: u25, + reserved52: [4]u8, + /// Ethernet MAC debug register + MACDBGR: mmio.Mmio(packed struct(u32) { + /// MAC MII receive protocol engine active + MMRPEA: u1, + /// MAC small FIFO read/write controllers status + MSFRWCS: u2, + reserved4: u1, + /// Rx FIFO write controller active + RFWRA: u1, + /// Rx FIFO read controller status + RFRCS: u2, + reserved8: u1, + /// Rx FIFO fill level + RFFL: u2, + reserved16: u6, + /// MAC MII transmit engine active + MMTEA: u1, + /// MAC transmit frame controller status + MTFCS: u2, + /// MAC transmitter in pause + MTP: u1, + /// Tx FIFO read status + TFRS: u2, + /// Tx FIFO write active + TFWA: u1, + reserved24: u1, + /// Tx FIFO not empty + TFNE: u1, + /// Tx FIFO full + TFF: u1, + padding: u6, }), - /// APB2 peripheral clock enable register - APB2ENR: mmio.Mmio(packed struct(u32) { - reserved9: u9, - /// CPU1 ADC clocks enable - ADCEN: u1, - reserved11: u1, - /// CPU1 TIM1 timer clock enable - TIM1EN: u1, - /// CPU1 SPI1 clock enable - SPI1EN: u1, - reserved14: u1, - /// CPU1 USART1clocks enable - USART1EN: u1, - reserved17: u2, - /// CPU1 TIM16 timer clock enable - TIM16EN: u1, - /// CPU1 TIM17 timer clock enable - TIM17EN: u1, - padding: u13, + /// Ethernet MAC interrupt status register + MACSR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// PMT status + PMTS: u1, + /// MMC status + MMCS: u1, + /// MMC receive status + MMCRS: u1, + /// MMC transmit status + MMCTS: u1, + reserved9: u2, + /// Time stamp trigger status + TSTS: u1, + padding: u22, }), - /// APB3 peripheral clock enable register - APB3ENR: mmio.Mmio(packed struct(u32) { - /// sub-GHz radio SPI clock enable - SUBGHZSPIEN: u1, - padding: u31, + /// Ethernet MAC interrupt mask register + MACIMR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// PMT interrupt mask + PMTIM: packed union { + raw: u1, + value: PMTIM, + }, + reserved9: u5, + /// Time stamp trigger interrupt mask + TSTIM: packed union { + raw: u1, + value: TSTIM, + }, + padding: u22, }), - /// AHB1 peripheral clocks enable in Sleep modes register - AHB1SMENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable during CPU1 CSleep mode. - DMA1SMEN: u1, - /// DMA2 clock enable during CPU1 CSleep mode - DMA2SMEN: u1, - /// DMAMUX1 clock enable during CPU1 CSleep mode. - DMAMUX1SMEN: u1, - reserved12: u9, - /// CRC clock enable during CPU1 CSleep mode. - CRCSMEN: u1, - padding: u19, + /// Ethernet MAC address 0 high register + MACA0HR: mmio.Mmio(packed struct(u32) { + /// Ethernet MAC address 0 high + MACA0H: u16, + reserved31: u15, + /// Always 1 + MO: u1, }), - /// AHB2 peripheral clocks enable in Sleep modes register - AHB2SMENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable during CPU1 CSleep mode. - GPIOASMEN: u1, - /// IO port B clock enable during CPU1 CSleep mode. - GPIOBSMEN: u1, - /// IO port C clock enable during CPU1 CSleep mode. - GPIOCSMEN: u1, - reserved7: u4, - /// IO port H clock enable during CPU1 CSleep mode. - GPIOHSMEN: u1, - padding: u24, + /// Ethernet MAC address 0 low register + MACA0LR: mmio.Mmio(packed struct(u32) { + /// Ethernet MAC address 0 low + MACA0L: u32, }), - /// AHB3 peripheral clocks enable in Sleep and Stop modes register - AHB3SMENR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// PKA accelerator clock enable during CPU1 CSleep mode. - PKASMEN: u1, - /// AES accelerator clock enable during CPU1 CSleep mode. - AESSMEN: u1, - /// True RNG clocks enable during CPU1 Csleep and CStop modes - RNGSMEN: u1, - reserved23: u4, - /// SRAM1 interface clock enable during CPU1 CSleep mode. - SRAM1SMEN: u1, - /// SRAM2 memory interface clock enable during CPU1 CSleep mode - SRAM2SMEN: u1, - /// Flash interface clock enable during CPU1 CSleep mode. - FLASHSMEN: u1, - padding: u6, + /// Ethernet MAC address 1/2/3 high register + MACAHR: mmio.Mmio(packed struct(u32) { + /// Ethernet MAC address 1/2/3 high + MACAH: u16, + reserved24: u8, + /// MBC + MBC: u6, + /// SA + SA: packed union { + raw: u1, + value: MACAHR_SA, + }, + /// AE + AE: u1, }), - reserved120: [4]u8, - /// APB1 peripheral clocks enable in Sleep mode register 1 - APB1SMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clock enable during CPU1 CSleep mode. - TIM2SMEN: u1, - reserved10: u9, - /// RTC bus clock enable during CPU1 CSleep mode. - RTCAPBSMEN: u1, - /// Window watchdog clocks enable during CPU1 CSleep mode. - WWDGSMEN: u1, - reserved14: u2, - /// SPI2 clock enable during CPU1 CSleep mode. - SPI2SMEN: u1, - reserved17: u2, - /// USART2 clock enable during CPU1 CSleep mode. - USART2SMEN: u1, - reserved21: u3, - /// I2C1 clock enable during CPU1 Csleep and CStop modes - I2C1SMEN: u1, - /// I2C2 clock enable during CPU1 Csleep and CStop modes - I2C2SMEN: u1, - /// I2C3 clock enable during CPU1 Csleep and CStop modes - I2C3SMEN: u1, - reserved29: u5, - /// DAC clock enable during CPU1 CSleep mode. - DACSMEN: u1, - reserved31: u1, - /// Low power timer 1 clock enable during CPU1 Csleep and CStop mode - LPTIM1SMEN: u1, + /// Ethernet MAC address 1/2/3 low register + MACALR: mmio.Mmio(packed struct(u32) { + /// Ethernet MAC address 1/2/3 low + MACAL: u32, }), - /// APB1 peripheral clocks enable in Sleep mode register 2 - APB1SMENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clock enable during CPU1 Csleep and CStop modes. - LPUART1SMEN: u1, - reserved5: u4, - /// Low power timer 2 clock enable during CPU1 Csleep and CStop modes - LPTIM2SMEN: u1, - /// Low power timer 3 clock enable during CPU1 Csleep and CStop modes - LPTIM3SMEN: u1, - padding: u25, + reserved256: [176]u8, + /// Ethernet MMC control register + MMCCR: mmio.Mmio(packed struct(u32) { + /// Counter reset + CR: packed union { + raw: u1, + value: CounterReset, + }, + /// Counter stop rollover + CSR: packed union { + raw: u1, + value: CSR, + }, + /// Reset on read + ROR: u1, + /// MMC counter freeze + MCF: u1, + /// MMC counter preset + MCP: packed union { + raw: u1, + value: MCP, + }, + /// MMC counter Full-Half preset + MCFHP: packed union { + raw: u1, + value: MCFHP, + }, + padding: u26, }), - /// APB2 peripheral clocks enable in Sleep mode register - APB2SMENR: mmio.Mmio(packed struct(u32) { - reserved9: u9, - /// ADC clocks enable during CPU1 Csleep and CStop modes - ADCSMEN: u1, - reserved11: u1, - /// TIM1 timer clock enable during CPU1 CSleep mode. - TIM1SMEN: u1, - /// SPI1 clock enable during CPU1 CSleep mode. - SPI1SMEN: u1, - reserved14: u1, - /// USART1 clock enable during CPU1 Csleep and CStop modes. - USART1SMEN: u1, - reserved17: u2, - /// TIM16 timer clock enable during CPU1 CSleep mode. - TIM16SMEN: u1, - /// TIM17 timer clock enable during CPU1 CSleep mode. - TIM17SMEN: u1, - padding: u13, + /// Ethernet MMC receive interrupt register + MMCRIR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Received frames CRC error status + RFCES: u1, + /// Received frames alignment error status + RFAES: u1, + reserved17: u10, + /// Received good Unicast frames status + RGUFS: u1, + padding: u14, }), - /// APB3 peripheral clock enable in Sleep mode register - APB3SMENR: mmio.Mmio(packed struct(u32) { - /// Sub-GHz radio SPI clock enable during Sleep and Stop modes - SUBGHZSPISMEN: u1, - padding: u31, + /// Ethernet MMC transmit interrupt register + MMCTIR: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// Transmitted good frames single collision status + TGFSCS: u1, + /// Transmitted good frames more than single collision status + TGFMSCS: u1, + reserved21: u5, + /// Transmitted good frames status + TGFS: u1, + padding: u10, }), - /// Peripherals independent clock configuration register - CCIPR: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SEL: u2, - /// USART2 clock source selection - USART2SEL: u2, - reserved8: u4, - /// SPI2 I2S clock source selection - SPI2SEL: u2, - /// LPUART1 clock source selection - LPUART1SEL: u2, - /// I2C1 clock source selection - I2C1SEL: u2, - /// I2C2 clock source selection - I2C2SEL: u2, - /// I2C3 clock source selection - I2C3SEL: u2, - /// Low power timer 1 clock source selection - LPTIM1SEL: u2, - /// Low power timer 2 clock source selection - LPTIM2SEL: u2, - /// Low power timer 3 clock source selection - LPTIM3SEL: u2, - reserved28: u4, - /// ADC clock source selection - ADCSEL: packed union { - raw: u2, - value: ADCSEL, + /// Ethernet MMC receive interrupt mask register + MMCRIMR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Received frame CRC error mask + RFCEM: packed union { + raw: u1, + value: RFCEM, }, - /// RNG clock source selection - RNGSEL: packed union { - raw: u2, - value: RNGSEL, + /// Received frames alignment error mask + RFAEM: packed union { + raw: u1, + value: RFAEM, + }, + reserved17: u10, + /// Received good Unicast frames mask + RGUFM: packed union { + raw: u1, + value: RGUFM, }, + padding: u14, }), - reserved144: [4]u8, - /// Backup domain control register - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enable - LSEON: u1, - /// LSE oscillator ready - LSERDY: u1, - /// LSE oscillator bypass - LSEBYP: u1, - /// LSE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, + /// Ethernet MMC transmit interrupt mask register + MMCTIMR: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// Transmitted good frames single collision mask + TGFSCM: packed union { + raw: u1, + value: TGFSCM, }, - /// CSS on LSE enable - LSECSSON: u1, - /// CSS on LSE failure Detection - LSECSSD: u1, - /// LSE system clock enable - LSESYSEN: u1, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, + /// Transmitted good frames more than single collision mask + TGFMSCM: packed union { + raw: u1, + value: TGFMSCM, }, - reserved11: u1, - /// LSE system clock ready - LSESYSRDY: u1, - reserved15: u3, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - reserved24: u7, - /// Low speed clock output enable - LSCOEN: u1, - /// Low speed clock output selection - LSCOSEL: u1, - padding: u6, - }), - /// Control/status register - CSR: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable - LSION: u1, - /// LSI oscillator ready - LSIRDY: u1, - reserved4: u2, - /// LSI frequency prescaler - LSIPRE: u1, - reserved8: u3, - /// MSI clock ranges - MSISRANGE: u4, - reserved14: u2, - /// Radio in reset status flag - RFRSTF: u1, - /// Radio reset - RFRST: u1, - reserved23: u7, - /// Remove reset flag - RMVF: u1, - /// Radio illegal access flag - RFILARSTF: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// Pin reset flag - PINRSTF: u1, - /// BOR flag - BORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent window watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, - }), - reserved264: [112]u8, - /// Extended clock recovery register - EXTCFGR: mmio.Mmio(packed struct(u32) { - /// HCLK3 shared prescaler (AHB3, Flash, and SRAM2) - SHDHPRE: packed union { - raw: u4, - value: HPRE, + /// Transmitted good frames mask + TGFM: packed union { + raw: u1, + value: TGFM, }, - reserved16: u12, - /// HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2) - SHDHPREF: u1, padding: u15, }), + reserved332: [56]u8, + /// Ethernet MMC transmitted good frames after a single collision counter + MMCTGFSCCR: mmio.Mmio(packed struct(u32) { + /// Transmitted good frames single collision counter + TGFSCC: u32, + }), + /// Ethernet MMC transmitted good frames after more than a single collision + MMCTGFMSCCR: mmio.Mmio(packed struct(u32) { + /// TGFMSCC + TGFMSCC: u32, + }), + reserved360: [20]u8, + /// Ethernet MMC transmitted good frames counter register + MMCTGFCR: mmio.Mmio(packed struct(u32) { + /// HTL + TGFC: u32, + }), + reserved404: [40]u8, + /// Ethernet MMC received frames with CRC error counter register + MMCRFCECR: mmio.Mmio(packed struct(u32) { + /// RFCFC + RFCFC: u32, + }), + /// Ethernet MMC received frames with alignment error counter register + MMCRFAECR: mmio.Mmio(packed struct(u32) { + /// RFAEC + RFAEC: u32, + }), + reserved452: [40]u8, + /// MMC received good unicast frames counter register + MMCRGUFCR: mmio.Mmio(packed struct(u32) { + /// RGUFC + RGUFC: u32, + }), }; - }; - pub const cryp_v2 = struct { - /// Cryptographic processor. - pub const CRYP = extern struct { - /// control register. - CR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Algorithm direction. - ALGODIR: u1, - /// Algorithm mode. - ALGOMODE0: u3, - /// Data type selection. - DATATYPE: u2, - /// Key size selection (AES mode only). - KEYSIZE: u2, - reserved14: u4, - /// FIFO flush. - FFLUSH: u1, - /// Cryptographic processor enable. - CRYPEN: u1, - /// GCM_CCMPH. - GCM_CCMPH: u2, - reserved19: u1, - /// ALGOMODE. - ALGOMODE3: u1, - padding: u12, + /// Ethernet: Precision time protocol + pub const ETHERNET_PTP = extern struct { + /// Ethernet PTP time stamp control register + PTPTSCR: mmio.Mmio(packed struct(u32) { + /// TSE + TSE: u1, + /// TSFCU + TSFCU: u1, + /// TSSTI + TSSTI: u1, + /// TSSTU + TSSTU: u1, + /// TSITE + TSITE: u1, + /// TTSARU + TTSARU: u1, + reserved8: u2, + /// TSSARFE + TSSARFE: u1, + /// TSSSR + TSSSR: u1, + /// TSPTPPSV2E + TSPTPPSV2E: u1, + /// TSSPTPOEFE + TSSPTPOEFE: u1, + /// TSSIPV6FE + TSSIPV6FE: u1, + /// TSSIPV4FE + TSSIPV4FE: u1, + /// TSSEME + TSSEME: u1, + /// TSSMRME + TSSMRME: u1, + /// TSCNT + TSCNT: u2, + /// TSPFFMAE + TSPFFMAE: u1, + padding: u13, }), - /// status register. - SR: mmio.Mmio(packed struct(u32) { - /// Input FIFO empty. - IFEM: u1, - /// Input FIFO not full. - IFNF: u1, - /// Output FIFO not empty. - OFNE: u1, - /// Output FIFO full. - OFFU: u1, - /// Busy bit. - BUSY: u1, - padding: u27, + /// Ethernet PTP subsecond increment register + PTPSSIR: mmio.Mmio(packed struct(u32) { + /// STSSI + STSSI: u8, + padding: u24, }), - /// data input register. - DIN: u32, - /// data output register. - DOUT: u32, - /// DMA control register. - DMACR: mmio.Mmio(packed struct(u32) { - /// DMA input enable. - DIEN: u1, - /// DMA output enable. - DOEN: u1, - padding: u30, + /// Ethernet PTP time stamp high register + PTPTSHR: mmio.Mmio(packed struct(u32) { + /// STS + STS: u32, }), - /// interrupt mask set/clear register. - IMSCR: mmio.Mmio(packed struct(u32) { - /// Input FIFO service interrupt mask. - INIM: u1, - /// Output FIFO service interrupt mask. - OUTIM: u1, - padding: u30, + /// Ethernet PTP time stamp low register + PTPTSLR: mmio.Mmio(packed struct(u32) { + /// STSS + STSS: u31, + /// STPNS + STPNS: u1, }), - /// raw interrupt status register. - RISR: mmio.Mmio(packed struct(u32) { - /// Input FIFO service raw interrupt status. - INRIS: u1, - /// Output FIFO service raw interrupt status. - OUTRIS: u1, + /// Ethernet PTP time stamp high update register + PTPTSHUR: mmio.Mmio(packed struct(u32) { + /// TSUS + TSUS: u32, + }), + /// Ethernet PTP time stamp low update register + PTPTSLUR: mmio.Mmio(packed struct(u32) { + /// TSUSS + TSUSS: u31, + /// TSUPNS + TSUPNS: u1, + }), + /// Ethernet PTP time stamp addend register + PTPTSAR: mmio.Mmio(packed struct(u32) { + /// TSA + TSA: u32, + }), + /// Ethernet PTP target time high register + PTPTTHR: mmio.Mmio(packed struct(u32) { + /// 0 + TTSH: u32, + }), + /// Ethernet PTP target time low register + PTPTTLR: mmio.Mmio(packed struct(u32) { + /// TTSL + TTSL: u32, + }), + reserved40: [4]u8, + /// Ethernet PTP time stamp status register + PTPTSSR: mmio.Mmio(packed struct(u32) { + /// TSSO + TSSO: u1, + /// TSSO + TSTTR: u1, padding: u30, }), - /// masked interrupt status register. - MISR: mmio.Mmio(packed struct(u32) { - /// Input FIFO service masked interrupt status. - INMIS: u1, - /// Output FIFO service masked interrupt status. - OUTMIS: u1, + /// Ethernet PTP PPS control register + PTPPPSCR: mmio.Mmio(packed struct(u32) { + /// TSSO + TSSO: u1, + /// TSTTR + TSTTR: u1, padding: u30, }), - /// Cluster KEY%s, containing K?LR, K?RR. - KEY: u32, - reserved64: [28]u8, - /// Cluster INIT%s, containing IV?LR, IV?RR. - INIT: u32, - reserved80: [12]u8, - /// context swap register. - CSGCMCCMR: [8]u32, - /// context swap register. - CSGCMR: [8]u32, - }; - - /// Cluster INIT%s, containing IV?LR, IV?RR. - pub const INIT = extern struct { - /// initialization vector registers. - IVLR: u32, - /// initialization vector registers. - IVRR: u32, - }; - - /// Cluster KEY%s, containing K?LR, K?RR. - pub const KEY = extern struct { - /// key registers. - KLR: u32, - /// key registers. - KRR: u32, }; }; - pub const opamp_f3 = struct { - pub const CALSEL = enum(u2) { - /// VREFOPAMP=3.3% VDDA - Percent3_3 = 0x0, - /// VREFOPAMP=10% VDDA - Percent10 = 0x1, - /// VREFOPAMP=50% VDDA - Percent50 = 0x2, - /// VREFOPAMP=90% VDDA - Percent90 = 0x3, + pub const eth_v1c = struct { + pub const APCS = enum(u1) { + /// MAC passes all incoming frames unmodified + Disabled = 0x0, + /// MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes + Strip = 0x1, }; - pub const FORCE_VP = enum(u1) { - /// Normal operating mode - Normal = 0x0, - /// Calibration mode. Non-inverting input connected to calibration reference - Calibration = 0x1, + pub const BFD = enum(u1) { + /// Address filters pass all received broadcast frames + Enabled = 0x0, + /// Address filters filter all incoming broadcast frames + Disabled = 0x1, }; - pub const OUTCAL = enum(u1) { - /// Non-inverting < inverting - Low = 0x0, - /// Non-inverting > inverting - High = 0x1, + pub const BL = enum(u2) { + /// For retransmission n, wait up to 2^min(n, 10) time slots + BL10 = 0x0, + /// For retransmission n, wait up to 2^min(n, 8) time slots + BL8 = 0x1, + /// For retransmission n, wait up to 2^min(n, 4) time slots + BL4 = 0x2, + /// For retransmission n, wait up to 2^min(n, 1) time slots + BL1 = 0x3, }; - pub const PGA_GAIN = enum(u4) { - /// Gain 2 - Gain2 = 0x0, - /// Gain 4 - Gain4 = 0x1, - /// Gain 8 - Gain8 = 0x2, - /// Gain 16 - Gain16 = 0x4, - /// Gain 2, feedback connected to VM0 - Gain2_VM0 = 0x8, - /// Gain 4, feedback connected to VM0 - Gain4_VM0 = 0x9, - /// Gain 8, feedback connected to VM0 - Gain8_VM0 = 0xa, - /// Gain 16, feedback connected to VM0 - Gain16_VM0 = 0xb, - /// Gain 2, feedback connected to VM1 - Gain2_VM1 = 0xc, - /// Gain 4, feedback connected to VM1 - Gain4_VM1 = 0xd, - /// Gain 8, feedback connected to VM1 - Gain8_VM1 = 0xe, - /// Gain 16, feedback connected to VM1 - Gain16_VM1 = 0xf, + pub const CR = enum(u3) { + /// 60-100MHz HCLK/42 + CR_60_100 = 0x0, + /// 100-150 MHz HCLK/62 + CR_100_150 = 0x1, + /// 20-35MHz HCLK/16 + CR_20_35 = 0x2, + /// 35-60MHz HCLK/16 + CR_35_60 = 0x3, + /// 150-168MHz HCLK/102 + CR_150_168 = 0x4, _, }; - pub const VMS_SEL = enum(u1) { - /// PC5 (VM0) used as OPAMP2 inverting input when TCM_EN=1 - PC5 = 0x0, - /// PA5 (VM1) used as OPAMP2 inverting input when TCM_EN=1 - PA5 = 0x1, + pub const CSD = enum(u1) { + /// Errors generated due to loss of carrier + Enabled = 0x0, + /// No error generated due to loss of carrier + Disabled = 0x1, }; - pub const VM_SEL = enum(u2) { - /// PC5 (VM0) used as OPAMP2 inverting input - PC5 = 0x0, - /// PA5 (VM1) used as OPAMP2 inverting input - PA5 = 0x1, - /// Resistor feedback output (PGA mode) - PGA = 0x2, - /// Follower mode - Follower = 0x3, + pub const CSR = enum(u1) { + /// Counters roll over to zero after reaching the maximum value + Rollover = 0x0, + /// Counters do not roll over to zero after reaching the maximum value + NotRollover = 0x1, }; - pub const VPS_SEL = enum(u2) { - /// PB14 used as OPAMP2 non-inverting input when TCM_EN=1 - PB14 = 0x1, - /// PB0 used as OPAMP2 non-inverting input when TCM_EN=1 - PB0 = 0x2, - /// PA7 used as OPAMP2 non-inverting input when TCM_EN=1 - PA7 = 0x3, + pub const CounterReset = enum(u1) { + /// Reset all counters. Cleared automatically + Reset = 0x1, _, }; - pub const VP_SEL = enum(u2) { - /// PB14 used as OPAMP2 non-inverting input - PB14 = 0x1, - /// PB0 used as OPAMP2 non-inverting input - PB0 = 0x2, - /// PA7 used as OPAMP2 non-inverting input - PA7 = 0x3, - _, + pub const DA = enum(u1) { + /// Round-robin with Rx:Tx priority given by PM + RoundRobin = 0x0, + /// Rx has priority over Tx + RxPriority = 0x1, }; - /// Operational Amplifier - pub const OPAMP = extern struct { - /// OPAMP control/status register - CSR: mmio.Mmio(packed struct(u32) { - /// OPAMP enable - OPAMPEN: u1, - /// Forces a calibration reference voltage on non-inverting input and disables external connections. - FORCE_VP: packed union { - raw: u1, - value: FORCE_VP, - }, - /// OPAMP Non inverting input selection - VP_SEL: packed union { - raw: u2, - value: VP_SEL, - }, - reserved5: u1, - /// OPAMP inverting input selection - VM_SEL: packed union { - raw: u2, - value: VM_SEL, - }, - /// Timer controlled Mux mode enable - TCM_EN: u1, - /// OPAMP inverting input secondary selection - VMS_SEL: packed union { - raw: u1, - value: VMS_SEL, - }, - /// OPAMP Non inverting input secondary selection - VPS_SEL: packed union { - raw: u2, - value: VPS_SEL, - }, - /// Calibration mode enable - CALON: u1, - /// Calibration selection - CALSEL: packed union { - raw: u2, - value: CALSEL, - }, - /// Gain in PGA mode - PGA_GAIN: packed union { - raw: u4, - value: PGA_GAIN, - }, - /// User trimming enable - USER_TRIM: u1, - /// Offset trimming value (PMOS) - TRIMOFFSETP: u5, - /// Offset trimming value (NMOS) - TRIMOFFSETN: u5, - /// Output the internal reference voltage - TSTREF: u1, - /// OPAMP ouput status flag - OUTCAL: packed union { - raw: u1, - value: OUTCAL, - }, - /// OPAMP lock - LOCK: u1, - }), + pub const DAIF = enum(u1) { + /// Normal filtering of frames + Normal = 0x0, + /// Address check block operates in inverse filtering mode for the DA address comparison + Invert = 0x1, }; - }; - pub const flash_l4 = struct { - /// Flash - pub const FLASH = extern struct { - /// Access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: u3, - reserved8: u5, - /// Prefetch enable - PRFTEN: u1, - /// Instruction cache enable - ICEN: u1, - /// Data cache enable - DCEN: u1, - /// Instruction cache reset - ICRST: u1, - /// Data cache reset - DCRST: u1, - /// Flash Power-down mode during Low-power run mode - RUN_PD: u1, - /// Flash Power-down mode during Low-power sleep mode - SLEEP_PD: u1, - padding: u17, - }), - /// Power down key register - PDKEYR: u32, - /// Flash key register - KEYR: u32, - /// Option byte key register - OPTKEYR: u32, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved3: u1, - /// Programming error - PROGERR: u1, - /// Write protected error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Size error - SIZERR: u1, - /// Programming sequence error - PGSERR: u1, - /// Fast programming data miss error - MISERR: u1, - /// Fast programming error - FASTERR: u1, - reserved14: u4, - /// PCROP read error - RDERR: u1, - /// Option validity error - OPTVERR: u1, - /// Busy - BSY: u1, - padding: u15, - }), - /// Flash control register - CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Page erase - PER: u1, - /// Bank 1 Mass erase - MER: u1, - /// Page number - PNB: u8, - /// Bank erase - BKER: u1, - reserved16: u4, - /// Start - START: u1, - /// Options modification start - OPTSTRT: u1, - /// Fast programming - FSTPG: u1, - reserved24: u5, - /// End of operation interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// PCROP read error interrupt enable - RDERRIE: u1, - /// Force the option byte loading - OBL_LAUNCH: u1, - reserved30: u2, - /// Options Lock - OPTLOCK: u1, - /// FLASH_CR Lock - LOCK: u1, - }), - /// Flash ECC register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC fail address - ADDR_ECC: u19, - /// ECC fail bank - BK_ECC: u1, - /// System Flash ECC fail - SYSF_ECC: u1, - reserved24: u3, - /// ECC correction interrupt enable - ECCIE: u1, - reserved30: u5, - /// ECC correction - ECCC: u1, - /// ECC detection - ECCD: u1, - }), - reserved32: [4]u8, - /// Flash option register - OPTR: mmio.Mmio(packed struct(u32) { - /// Read protection level - RDP: u8, - /// BOR reset Level - BOR_LEV: u3, - reserved12: u1, - /// nRST_STOP - nRST_STOP: u1, - /// nRST_STDBY - nRST_STDBY: u1, - reserved16: u2, - /// Independent watchdog selection - IDWG_SW: u1, - /// Independent watchdog counter freeze in Stop mode - IWDG_STOP: u1, - /// Independent watchdog counter freeze in Standby mode - IWDG_STDBY: u1, - /// Window watchdog selection - WWDG_SW: u1, - /// Dual-bank boot - BFB: u1, - /// Dual-Bank on 512 KB or 256 KB Flash memory devices - DUALBANK: u1, - reserved23: u1, - /// Boot configuration - nBOOT1: u1, - /// SRAM2 parity check enable - SRAM2_PE: u1, - /// SRAM2 Erase when system reset - SRAM2_RST: u1, - /// Software BOOT0 - nSWBOOT0: u1, - /// nBOOT0 option bit - nBOOT0: u1, - padding: u4, - }), - /// Flash Bank 1 PCROP Start address register - PCROP1SR: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area start offset - PCROP1_STRT: u16, - padding: u16, - }), - /// Flash Bank 1 PCROP End address register - PCROP1ER: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area end offset - PCROP1_END: u16, - reserved31: u15, - /// PCROP area preserved when RDP level decreased - PCROP_RDP: u1, - }), - /// Flash Bank 1 WRP area A address register - WRP1AR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP first area tart offset - WRP1A_STRT: u8, - reserved16: u8, - /// Bank 1 WRP first area A end offset - WRP1A_END: u8, - padding: u8, - }), - /// Flash Bank 1 WRP area B address register - WRP1BR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP second area B start offset - WRP1B_STRT: u8, - reserved16: u8, - /// Bank 1 WRP second area B end offset - WRP1B_END: u8, - padding: u8, - }), - reserved68: [16]u8, - /// Flash Bank 2 PCROP Start address register - PCROP2SR: mmio.Mmio(packed struct(u32) { - /// Bank 2 PCROP area start offset - PCROP2_STRT: u16, - padding: u16, - }), - /// Flash Bank 2 PCROP End address register - PCROP2ER: mmio.Mmio(packed struct(u32) { - /// Bank 2 PCROP area end offset - PCROP2_END: u16, - padding: u16, - }), - /// Flash Bank 2 WRP area A address register - WRP2AR: mmio.Mmio(packed struct(u32) { - /// Bank 2 WRP first area A start offset - WRP2A_STRT: u8, - reserved16: u8, - /// Bank 2 WRP first area A end offset - WRP2A_END: u8, - padding: u8, - }), - /// Flash Bank 2 WRP area B address register - WRP2BR: mmio.Mmio(packed struct(u32) { - /// Bank 2 WRP second area B start offset - WRP2B_STRT: u8, - reserved16: u8, - /// Bank 2 WRP second area B end offset - WRP2B_END: u8, - padding: u8, - }), + pub const DM = enum(u1) { + /// MAC operates in half-duplex mode + HalfDuplex = 0x0, + /// MAC operates in full-duplex mode + FullDuplex = 0x1, }; - }; - pub const syscfg_wb = struct { - /// System configuration controller - pub const SYSCFG = extern struct { - /// memory remap register - MEMRMP: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection - MEM_MODE: u3, - padding: u29, - }), - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// I/O analog switch voltage booster enable - BOOSTEN: u1, - reserved16: u7, - /// Fast-mode Plus (Fm+) driving capability activation on PB6 - I2C_PB6_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB7 - I2C_PB7_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB8 - I2C_PB8_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB9 - I2C_PB9_FMP: u1, - /// I2C1 Fast-mode Plus driving capability activation - I2C1_FMP: u1, - reserved22: u1, - /// I2C3 Fast-mode Plus driving capability activation - I2C3_FMP: u1, - reserved26: u3, - /// Floating Point Unit interrupts enable bits - FPU_IE: u6, - }), - /// external interrupt configuration register 1 - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI 0 configuration bits - EXTI: u3, - padding: u29, - }), - /// SCSR - SCSR: mmio.Mmio(packed struct(u32) { - /// SRAM2 Erase - SRAM2ER: u1, - /// SRAM2 busy by erase operation - SRAM2BSY: u1, - reserved31: u29, - /// CPU2 SRAM fetch (execution) disable. - C2RFD: u1, - }), - /// CFGR2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// Cortex-M4 LOCKUP (Hardfault) output enable bit - CLL: u1, - /// SRAM2 parity lock bit - SPL: u1, - /// PVD lock enable bit - PVDL: u1, - /// ECC Lock - ECCL: u1, - reserved8: u4, - /// SRAM2 parity error flag - SPF: u1, - padding: u23, - }), - /// SRAM2 write protection register - SWPR: mmio.Mmio(packed struct(u32) { - /// P0WP - PWP: u1, - padding: u31, - }), - /// SKR - SKR: mmio.Mmio(packed struct(u32) { - /// SRAM2 write protection key for software erase - KEY: u8, - padding: u24, - }), - /// SRAM2 write protection register 2 - SWPR2: mmio.Mmio(packed struct(u32) { - /// P32WP - PWP: u1, - padding: u31, - }), - reserved256: [212]u8, - /// CPU1 interrupt mask register 1 - IMR1: mmio.Mmio(packed struct(u32) { - reserved13: u13, - /// Peripheral TIM1 interrupt mask to CPU1 - TIM1IM: u1, - /// Peripheral TIM16 interrupt mask to CPU1 - TIM16IM: u1, - /// Peripheral TIM17 interrupt mask to CPU1 - TIM17IM: u1, - reserved21: u5, - /// Peripheral EXIT5 interrupt mask to CPU1 - EXIT5IM: u1, - /// Peripheral EXIT6 interrupt mask to CPU1 - EXIT6IM: u1, - /// Peripheral EXIT7 interrupt mask to CPU1 - EXIT7IM: u1, - /// Peripheral EXIT8 interrupt mask to CPU1 - EXIT8IM: u1, - /// Peripheral EXIT9 interrupt mask to CPU1 - EXIT9IM: u1, - /// Peripheral EXIT10 interrupt mask to CPU1 - EXIT10IM: u1, - /// Peripheral EXIT11 interrupt mask to CPU1 - EXIT11IM: u1, - /// Peripheral EXIT12 interrupt mask to CPU1 - EXIT12IM: u1, - /// Peripheral EXIT13 interrupt mask to CPU1 - EXIT13IM: u1, - /// Peripheral EXIT14 interrupt mask to CPU1 - EXIT14IM: u1, - /// Peripheral EXIT15 interrupt mask to CPU1 - EXIT15IM: u1, - }), - /// CPU1 interrupt mask register 2 - IMR2: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Peripheral PVM1 interrupt mask to CPU1 - PVM1IM: u1, - reserved18: u1, - /// Peripheral PVM3 interrupt mask to CPU1 - PVM3IM: u1, - reserved20: u1, - /// Peripheral PVD interrupt mask to CPU1 - PVDIM: u1, - padding: u11, - }), - /// CPU2 interrupt mask register 1 - C2IMR1: mmio.Mmio(packed struct(u32) { - /// Peripheral RTCSTAMP interrupt mask to CPU2 - RTCSTAMP: u1, - reserved3: u2, - /// Peripheral RTCWKUP interrupt mask to CPU2 - RTCWKUP: u1, - /// Peripheral RTCALARM interrupt mask to CPU2 - RTCALARM: u1, - /// Peripheral RCC interrupt mask to CPU2 - RCC: u1, - /// Peripheral FLASH interrupt mask to CPU2 - FLASH: u1, - reserved8: u1, - /// Peripheral PKA interrupt mask to CPU2 - PKA: u1, - /// Peripheral RNG interrupt mask to CPU2 - RNG: u1, - /// Peripheral AES1 interrupt mask to CPU2 - AES1: u1, - /// Peripheral COMP interrupt mask to CPU2 - COMP: u1, - /// Peripheral ADC interrupt mask to CPU2 - ADC: u1, - padding: u19, - }), - /// CPU2 interrupt mask register 1 - C2IMR2: mmio.Mmio(packed struct(u32) { - /// Peripheral DMA1 CH1 interrupt mask to CPU2 - DMA1_CH1_IM: u1, - /// Peripheral DMA1 CH2 interrupt mask to CPU2 - DMA1_CH2_IM: u1, - /// Peripheral DMA1 CH3 interrupt mask to CPU2 - DMA1_CH3_IM: u1, - /// Peripheral DMA1 CH4 interrupt mask to CPU2 - DMA1_CH4_IM: u1, - /// Peripheral DMA1 CH5 interrupt mask to CPU2 - DMA1_CH5_IM: u1, - /// Peripheral DMA1 CH6 interrupt mask to CPU2 - DMA1_CH6_IM: u1, - /// Peripheral DMA1 CH7 interrupt mask to CPU2 - DMA1_CH7_IM: u1, - reserved8: u1, - /// Peripheral DMA2 CH1 interrupt mask to CPU1 - DMA2_CH1_IM: u1, - /// Peripheral DMA2 CH2 interrupt mask to CPU1 - DMA2_CH2_IM: u1, - /// Peripheral DMA2 CH3 interrupt mask to CPU1 - DMA2_CH3_IM: u1, - /// Peripheral DMA2 CH4 interrupt mask to CPU1 - DMA2_CH4_IM: u1, - /// Peripheral DMA2 CH5 interrupt mask to CPU1 - DMA2_CH5_IM: u1, - /// Peripheral DMA2 CH6 interrupt mask to CPU1 - DMA2_CH6_IM: u1, - /// Peripheral DMA2 CH7 interrupt mask to CPU1 - DMA2_CH7_IM: u1, - /// Peripheral DMAM UX1 interrupt mask to CPU1 - DMAM_UX1_IM: u1, - /// Peripheral PVM1IM interrupt mask to CPU1 - PVM1IM: u1, - reserved18: u1, - /// Peripheral PVM3IM interrupt mask to CPU1 - PVM3IM: u1, - reserved20: u1, - /// Peripheral PVDIM interrupt mask to CPU1 - PVDIM: u1, - /// Peripheral TSCIM interrupt mask to CPU1 - TSCIM: u1, - /// Peripheral LCDIM interrupt mask to CPU1 - LCDIM: u1, - padding: u9, - }), - /// secure IP control register - SIPCR: mmio.Mmio(packed struct(u32) { - /// Enable AES1 KEY[7:0] security. - SAES: u1, - reserved2: u1, - /// Enable PKA security - SPKA: u1, - /// Enable True RNG security - SRNG: u1, - padding: u28, - }), + pub const DMAOMR_SR = enum(u1) { + /// Reception is stopped after transfer of the current frame + Stopped = 0x0, + /// Reception is placed in the Running state + Started = 0x1, }; - }; - pub const pwr_f0x0 = struct { - pub const PDDS = enum(u1) { - /// Enter Stop mode when the CPU enters deepsleep - STOP_MODE = 0x0, - /// Enter Standby mode when the CPU enters deepsleep - STANDBY_MODE = 0x1, + pub const DTCEFD = enum(u1) { + /// Drop frames with errors only in the receive checksum offload engine + Enabled = 0x0, + /// Do not drop frames that only have errors in the receive checksum offload engine + Disabled = 0x1, }; - /// Power control - pub const PWR = extern struct { - /// power control register - CR: mmio.Mmio(packed struct(u32) { - /// Low-power deep sleep - LPDS: u1, - /// Power down deepsleep - PDDS: packed union { - raw: u1, - value: PDDS, - }, - /// Clear wakeup flag - CWUF: u1, - /// Clear standby flag - CSBF: u1, - reserved8: u4, - /// Disable backup domain write protection - DBP: u1, - padding: u23, - }), - /// power control/status register - CSR: mmio.Mmio(packed struct(u32) { - /// Wakeup flag - WUF: u1, - /// Standby flag - SBF: u1, - reserved8: u6, - /// Enable WKUP pin 1 - EWUP: u1, - padding: u23, - }), + pub const FB = enum(u1) { + /// AHB uses SINGLE and INCR burst transfers + Variable = 0x0, + /// AHB uses only fixed burst transfers + Fixed = 0x1, }; - }; - pub const saes_v1a = struct { - pub const CHMOD = enum(u3) { - /// Electronic codebook - ECB = 0x0, - /// Cipher-block chaining - CBC = 0x1, - /// Counter mode - CTR = 0x2, - /// Galois counter mode and Galois message authentication code - GCM_GMAC = 0x3, - /// Counter with CBC-MAC - CCM = 0x4, - _, + pub const FCB = enum(u1) { + /// In half duplex only, deasserts back pressure + DisableBackPressure = 0x0, + /// In full duplex, initiate a Pause control frame. In half duplex, assert back pressure + PauseOrBackPressure = 0x1, }; - pub const DATATYPE = enum(u2) { - /// No swapping (32-bit data). - None = 0x0, - /// Half-word swapping (16-bit data) - HalfWord = 0x1, - /// Byte swapping (8-bit data) - Byte = 0x2, - /// Bit-level swapping - Bit = 0x3, + pub const FEF = enum(u1) { + /// Rx FIFO drops frames with error status + Drop = 0x0, + /// All frames except runt error frames are forwarded to the DMA + Forward = 0x1, }; - pub const GCMPH = enum(u2) { - /// Initialization phase - InitPhase = 0x0, - /// Header phase - HeaderPhase = 0x1, - /// Payload phase - PayloadPhase = 0x2, - /// Final phase - FinalPhase = 0x3, + pub const FES = enum(u1) { + /// 10 Mbit/s + FES10 = 0x0, + /// 100 Mbit/s + FES100 = 0x1, }; - pub const KEYSEL = enum(u3) { - /// Software key, loaded in key registers SAES_KEYx - SoftwareKey = 0x0, - /// Derived hardware unique key - DHUK = 0x1, - /// Boot hardware key - BHK = 0x2, - /// XOR of DHUK and BHK - XOR_DHUK_BHK = 0x4, + pub const FPM = enum(u1) { + /// PBL values used as-is + x1 = 0x0, + /// PBL values multiplied by 4 + x4 = 0x1, + }; + + pub const FTF = enum(u1) { + /// Transmit FIFO controller logic is reset to its default values. Cleared automatically + Flush = 0x1, _, }; - pub const KEYSIZE = enum(u1) { - /// 128-bit - Bits128 = 0x0, - /// 256-bit - Bits256 = 0x1, + pub const FUGF = enum(u1) { + /// Rx FIFO drops all frames of less than 64 bytes + Drop = 0x0, + /// Rx FIFO forwards undersized frames + Forward = 0x1, }; - pub const KMOD = enum(u2) { - /// AES peripheral + pub const HM = enum(u1) { + /// MAC performs a perfect destination address filtering for multicast frames + Perfect = 0x0, + /// MAC performs destination address filtering of received multicast frames according to the hash table + Hash = 0x1, + }; + + pub const HPF = enum(u1) { + /// If HM or HU is set, only frames that match the Hash filter are passed + HashOnly = 0x0, + /// If HM or HU is set, frames that match either the perfect filter or the hash filter are passed + HashOrPerfect = 0x1, + }; + + pub const HU = enum(u1) { + /// MAC performs a perfect destination address filtering for unicast frames + Perfect = 0x0, + /// MAC performs destination address filtering of received unicast frames according to the hash table + Hash = 0x1, + }; + + pub const IFG = enum(u3) { + /// 96 bit times + IFG96 = 0x0, + /// 88 bit times + IFG88 = 0x1, + /// 80 bit times + IFG80 = 0x2, + /// 72 bit times + IFG72 = 0x3, + /// 64 bit times + IFG64 = 0x4, + /// 56 bit times + IFG56 = 0x5, + /// 48 bit times + IFG48 = 0x6, + /// 40 bit times + IFG40 = 0x7, + }; + + pub const IPCO = enum(u1) { + /// IPv4 checksum offload disabled + Disabled = 0x0, + /// IPv4 checksums are checked in received frames + Offload = 0x1, + }; + + pub const JD = enum(u1) { + /// Jabber enabled, transmit frames up to 2048 bytes + Enabled = 0x0, + /// Jabber disabled, transmit frames up to 16384 bytes + Disabled = 0x1, + }; + + pub const LM = enum(u1) { + /// Normal mode Normal = 0x0, - /// Wrapped key for SAES mode. Key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process. - WrappedKey = 0x1, - /// Shared key mode. After a successful decryption process (unwrapping), SAES key registers are shared with the peripheral described in KSHAREID[1:0] bitfield. This sharing is valid only while KMOD[1:0] at 0x2 and KEYVALID=1. When a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process. - SharedKey = 0x2, - _, + /// MAC operates in loopback mode at the MII + Loopback = 0x1, }; - pub const KSHAREID = enum(u2) { - /// AES peripheral - AES = 0x0, + pub const MACAHR_SA = enum(u1) { + /// This address is used for comparison with DA fields of the received frame + Destination = 0x0, + /// This address is used for comparison with SA fields of received frames + Source = 0x1, + }; + + pub const MB = enum(u1) { + /// Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below + Normal = 0x0, + /// If FB is low, start all bursts greater than 16 with INCR (undefined burst) + Mixed = 0x1, + }; + + pub const MB_progress = enum(u1) { + /// This bit is set to 1 by the application to indicate that a read or write access is in progress + Busy = 0x1, _, }; - pub const MODE = enum(u2) { - Encryption = 0x0, - /// Key derivation (or key preparation), for ECB/CBC decryption only - KeyDerivation = 0x1, - Decryption = 0x2, + pub const MCFHP = enum(u1) { + /// When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0 + AlmostHalf = 0x0, + /// When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0 + AlmostFull = 0x1, + }; + + pub const MCP = enum(u1) { + /// MMC counters will be preset to almost full or almost half. Cleared automatically + Preset = 0x1, _, }; - /// Secure advanced encryption standard hardware accelerator. - pub const SAES = extern struct { - /// SAES control register. - CR: mmio.Mmio(packed struct(u32) { - /// SAES enable This bit enables/disables the SAES peripheral: At any moment, clearing then setting the bit re-initializes the SAES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD = 01 + CHMOD = 011 and KMOD = 01 + CHMOD = 010 + MODE = 00. Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN. - EN: u1, - /// Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. - DATATYPE: packed union { - raw: u2, - value: DATATYPE, - }, - /// SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. - MODE: packed union { - raw: u2, - value: MODE, - }, - padding: u27, - }), - /// SAES status register. - SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero. - RDERR: u1, - /// Write error This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected write is ignored. - WRERR: u1, - /// Busy This flag indicates whether SAES is idle or busy during GCM payload encryption phase: The flag is set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase. - BUSY: u1, - reserved7: u3, - /// Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to. - KEYVALID: u1, - padding: u24, - }), - /// SAES data input register. - DINR: u32, - /// SAES data output register. - DOUTR: u32, - /// SAES key register 0. - KEYR: u32, - reserved32: [12]u8, - /// SAES initialization vector register 0. - IVR: [4]u32, - reserved64: [16]u8, - /// SAES suspend registers. - SUSPR: [8]u32, - reserved768: [672]u8, - /// SAES interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set. - CCFIE: u1, - /// Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set. - RWEIE: u1, - /// Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set. - KEIE: u1, - /// RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set. - RNGEIE: u1, - padding: u28, - }), - /// SAES interrupt status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1. - CCF: u1, - /// Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected. - RWEIF: u1, - /// Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. AES fails to load the key shared by SAES peripheral (KMOD=10). When KEYVALID = 1 and (KEYPROT = 1 or KEYSEL is not 0x0), the security context of the application that loads the key (secure or non-secure) does not match the security attribute of the access to SAES_CR or SAES_DOUT. In this case, KEYVALID and EN bits are cleared. SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set. - KEIF: u1, - /// RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral. - RNGEIF: u1, - padding: u28, - }), - /// SAES interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_SR and SAES_ISR registers. - CCF: u1, - /// Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and both RDERR and WRERR flags in the SAES_SR register. - RWEIF: u1, - /// Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register. - KEIF: u1, - /// RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register. - RNGEIF: u1, - padding: u28, - }), + pub const MW = enum(u1) { + /// Read operation + Read = 0x0, + /// Write operation + Write = 0x1, }; - }; - pub const hrtim_v1 = struct { - pub const ACTIVEEFFECT = enum(u1) { - /// Timer event has no effect - NoEffect = 0x0, - /// Timer event forces the output to its active state - SetActive = 0x1, + pub const PBL = enum(u6) { + /// Maximum of 1 beat per DMA transaction + PBL1 = 0x1, + /// Maximum of 2 beats per DMA transaction + PBL2 = 0x2, + /// Maximum of 4 beats per DMA transaction + PBL4 = 0x4, + /// Maximum of 8 beats per DMA transaction + PBL8 = 0x8, + /// Maximum of 16 beats per DMA transaction + PBL16 = 0x10, + /// Maximum of 32 beats per DMA transaction + PBL32 = 0x20, + _, }; - pub const BRSTDMA = enum(u2) { - /// Update done independently from the DMA burst transfer completion - Independent = 0x0, - /// Update done when the DMA burst transfer is completed - Completion = 0x1, - /// Update done on master timer roll-over following a DMA burst transfer completion - Rollover = 0x2, + pub const PCF = enum(u2) { + /// MAC prevents all control frames from reaching the application + PreventAll = 0x0, + /// MAC forwards all control frames to application except Pause + ForwardAllExceptPause = 0x1, + /// MAC forwards all control frames to application even if they fail the address filter + ForwardAll = 0x2, + /// MAC forwards control frames that pass the address filter + ForwardAllFiltered = 0x3, + }; + + pub const PD = enum(u1) { + /// All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received + Enabled = 0x1, _, }; - pub const CAPTUREEFFECT = enum(u1) { - /// Timer event has no effect - NoEffect = 0x0, - /// Timer event triggers capture - TriggerCapture = 0x1, + pub const PLT = enum(u2) { + /// Pause time minus 4 slot times + PLT4 = 0x0, + /// Pause time minus 28 slot times + PLT28 = 0x1, + /// Pause time minus 144 slot times + PLT144 = 0x2, + /// Pause time minus 256 slot times + PLT256 = 0x3, }; - pub const CPPSTAT = enum(u1) { - /// Signal applied on output 1 and output 2 forced inactive - Output1Active = 0x0, - /// Signal applied on output 2 and output 1 forced inactive - Output2Active = 0x1, + pub const PMTIM = enum(u1) { + /// PMT Status interrupt generation enabled + Unmasked = 0x0, + /// PMT Status interrupt generation disabled + Masked = 0x1, }; - pub const DACSYNC = enum(u2) { - /// No DAC trigger generated - Disabled = 0x0, - /// Trigger generated on DACSync1 - DACSync1 = 0x1, - /// Trigger generated on DACSync2 - DACSync2 = 0x2, - /// Trigger generated on DACSync3 - DACSync3 = 0x3, + pub const PriorityRxOverTx = enum(u2) { + /// RxDMA priority over TxDMA is 1:1 + OneToOne = 0x0, + /// RxDMA priority over TxDMA is 2:1 + TwoToOne = 0x1, + /// RxDMA priority over TxDMA is 3:1 + ThreeToOne = 0x2, + /// RxDMA priority over TxDMA is 4:1 + FourToOne = 0x3, }; - pub const DELCMP = enum(u2) { - /// CMP register is always active (standard compare mode) - Standard = 0x0, - /// CMP is recomputed and is active following a capture 1 event - Capture1 = 0x1, - /// CMP is recomputed and is active following a capture 1 event or a Compare 1 match - CaptureX_Compare1 = 0x2, - /// CMP is recomputed and is active following a capture 1 event or a Compare 3 match - CaptureX_Compare3 = 0x3, + pub const RD = enum(u1) { + /// MAC attempts retries based on the settings of BL + Enabled = 0x0, + /// MAC attempts only 1 transmission + Disabled = 0x1, }; - pub const DLYPRT = enum(u3) { - /// Output 1 delayed idle on external event 6 - Output1_EE6 = 0x0, - /// Output 2 delayed idle on external event 6 - Output2_EE6 = 0x1, - /// Output 1 and 2 delayed idle on external event 6 - Output1_2_EE6 = 0x2, - /// Balanced idle on external event 6 - Balanced_EE6 = 0x3, - /// Output 1 delayed idle on external event 7 - Output1_EE7 = 0x4, - /// Output 2 delayed idle on external event 7 - Output2_EE7 = 0x5, - /// Output 1 and 2 delayed idle on external event 7 - Output1_2_EE7 = 0x6, - /// Balanced idle on external event 7 - Balanced_EE7 = 0x7, + pub const RDP = enum(u6) { + /// 1 beat per RxDMA transaction + RDP1 = 0x1, + /// 2 beats per RxDMA transaction + RDP2 = 0x2, + /// 4 beats per RxDMA transaction + RDP4 = 0x4, + /// 8 beats per RxDMA transaction + RDP8 = 0x8, + /// 16 beats per RxDMA transaction + RDP16 = 0x10, + /// 32 beats per RxDMA transaction + RDP32 = 0x20, + _, }; - pub const EEFLTR = enum(u4) { - /// No filtering - Disabled = 0x0, - /// Blanking from counter reset/roll-over to Compare 1 - BlankResetToCompare1 = 0x1, - /// Blanking from counter reset/roll-over to Compare 2 - BlankResetToCompare2 = 0x2, - /// Blanking from counter reset/roll-over to Compare 3 - BlankResetToCompare3 = 0x3, - /// Blanking from counter reset/roll-over to Compare 4 - BlankResetToCompare4 = 0x4, - /// Blanking from another timing unit: TIMFLTR1 source - BlankTIMFLTR1 = 0x5, - /// Blanking from another timing unit: TIMFLTR2 source - BlankTIMFLTR2 = 0x6, - /// Blanking from another timing unit: TIMFLTR3 source - BlankTIMFLTR3 = 0x7, - /// Blanking from another timing unit: TIMFLTR4 source - BlankTIMFLTR4 = 0x8, - /// Blanking from another timing unit: TIMFLTR5 source - BlankTIMFLTR5 = 0x9, - /// Blanking from another timing unit: TIMFLTR6 source - BlankTIMFLTR6 = 0xa, - /// Blanking from another timing unit: TIMFLTR7 source - BlankTIMFLTR7 = 0xb, - /// Blanking from another timing unit: TIMFLTR8 source - BlankTIMFLTR8 = 0xc, - /// Windowing from counter reset/roll-over to compare 2 - WindowResetToCompare2 = 0xd, - /// Windowing from counter reset/roll-over to compare 3 - WindowResetToCompare3 = 0xe, - /// Windowing from another timing unit: TIMWIN source - WindowTIMWIN = 0xf, + pub const RFAEM = enum(u1) { + /// Received-alignment-error counter half-full interrupt enabled + Unmasked = 0x0, + /// Received-alignment-error counter half-full interrupt disabled + Masked = 0x1, }; - pub const FAULT = enum(u2) { - /// No action: the output is not affected by the fault input and stays in run mode - Disabled = 0x0, - /// Output goes to active state after a fault event - SetActive = 0x1, - /// Output goes to inactive state after a fault event - SetInactive = 0x2, - /// Output goes to high-z state after a fault event - SetHighZ = 0x3, + pub const RFCEM = enum(u1) { + /// Received-crc-error counter half-full interrupt enabled + Unmasked = 0x0, + /// Received-crc-error counter half-full interrupt disabled + Masked = 0x1, }; - pub const FLTEN = enum(u1) { - /// Fault input ignored - Ignored = 0x0, - /// Fault input is active and can disable HRTIM outputs - Active = 0x1, + pub const RGUFM = enum(u1) { + /// Received-good-unicast counter half-full interrupt enabled + Unmasked = 0x0, + /// Received-good-unicast counter half-full interrupt disabled + Masked = 0x1, }; - pub const INACTIVEEFFECT = enum(u1) { - /// Timer event has no effect - NoEffect = 0x0, - /// Timer event forces the output to its inactive state - SetInactive = 0x1, + pub const ROD = enum(u1) { + /// MAC receives all packets from PHY while transmitting + Enabled = 0x0, + /// MAC disables reception of frames in half-duplex mode + Disabled = 0x1, }; - pub const IPPSTAT = enum(u1) { - /// Protection occurred when the output 1 was active and output 2 forced inactive - Output1Active = 0x0, - /// Protection occurred when the output 2 was active and output 1 forced inactive - Output2Active = 0x1, + pub const RPD = enum(u32) { + /// Poll the receive descriptor list + Poll = 0x0, + _, }; - pub const OUTPUTSTATE = enum(u1) { - /// Output is or was inactive - Inactive = 0x0, - /// Output is or was active - Active = 0x1, + pub const RPS = enum(u3) { + /// Stopped, reset or Stop Receive command issued + Stopped = 0x0, + /// Running, fetching receive transfer descriptor + RunningFetching = 0x1, + /// Running, waiting for receive packet + RunningWaiting = 0x3, + /// Suspended, receive descriptor unavailable + Suspended = 0x4, + /// Running, writing data to host memory buffer + RunningWriting = 0x7, + _, }; - pub const POL = enum(u1) { - /// Positive polarity (output active high) - ActiveHigh = 0x0, - /// Negative polarity (output active low) - ActiveLow = 0x1, + pub const RSF = enum(u1) { + /// Rx FIFO operates in cut-through mode, subject to RTC bits + CutThrough = 0x0, + /// Frames are read from Rx FIFO after complete frame has been written + StoreForward = 0x1, }; - pub const RESETEFFECT = enum(u1) { - /// Timer Y compare Z event has no effect - NoEffect = 0x0, - /// Timer X counter is reset upon timer Y compare Z event - ResetCounter = 0x1, + pub const RTC = enum(u2) { + /// 64 bytes + RTC64 = 0x0, + /// 32 bytes + RTC32 = 0x1, + /// 96 bytes + RTC96 = 0x2, + /// 128 bytes + RTC128 = 0x3, }; - pub const SDTF = enum(u1) { - /// Positive deadtime on falling edge - Positive = 0x0, - /// Negative deadtime on falling edge - Negative = 0x1, + pub const SAIF = enum(u1) { + /// Source address filter operates normally + Normal = 0x0, + /// Source address filter operation inverted + Invert = 0x1, }; - pub const SDTR = enum(u1) { - /// Positive deadtime on rising edge - Positive = 0x0, - /// Negative deadtime on rising edge - Negative = 0x1, + pub const ST = enum(u1) { + /// Transmission is placed in the Stopped state + Stopped = 0x0, + /// Transmission is placed in Running state + Started = 0x1, }; - pub const SYNCIN = enum(u2) { - /// Disabled. HRTIM is not synchronized and runs in standalone mode - Disabled = 0x0, - /// Internal event: the HRTIM is synchronized with the on-chip timer - Internal = 0x2, - /// External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM - External = 0x3, + pub const TGFM = enum(u1) { + /// Transmitted-good counter half-full interrupt enabled + Unmasked = 0x0, + /// Transmitted-good counter half-full interrupt disabled + Masked = 0x1, + }; + + pub const TGFMSCM = enum(u1) { + /// Transmitted-good-multiple-collision half-full interrupt enabled + Unmasked = 0x0, + /// Transmitted-good-multiple-collision half-full interrupt disabled + Masked = 0x1, + }; + + pub const TGFSCM = enum(u1) { + /// Transmitted-good-single-collision half-full interrupt enabled + Unmasked = 0x0, + /// Transmitted-good-single-collision half-full interrupt disabled + Masked = 0x1, + }; + + pub const TPD = enum(u32) { + /// Poll the transmit descriptor list + Poll = 0x0, _, }; - pub const SYNCOUT = enum(u2) { - /// Disabled - Disabled = 0x0, - /// Positive pulse on SCOUT output (16x f_HRTIM clock cycles) - PositivePulse = 0x2, - /// Negative pulse on SCOUT output (16x f_HRTIM clock cycles) - NegativePulse = 0x3, + pub const TPS = enum(u3) { + /// Stopped, Reset or Stop Transmit command issued + Stopped = 0x0, + /// Running, fetching transmit transfer descriptor + RunningFetching = 0x1, + /// Running, waiting for status + RunningWaiting = 0x2, + /// Running, reading data from host memory buffer + RunningReading = 0x3, + /// Suspended, transmit descriptor unavailable or transmit buffer underflow + Suspended = 0x6, + /// Running, closing transmit descriptor + Running = 0x7, _, }; - pub const SYNCRST = enum(u1) { - /// Synchronization event has no effect on Timer x - Disabled = 0x0, - /// Synchronization event resets Timer x - Reset = 0x1, + pub const TSF = enum(u1) { + /// Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold + CutThrough = 0x0, + /// Transmission starts when a full frame is in the Tx FIFO + StoreForward = 0x1, }; - pub const SYNCSRC = enum(u2) { - /// Master timer Start - MasterStart = 0x0, - /// Master timer Compare 1 event - MasterCompare1 = 0x1, - /// Timer A start/reset - TimerAStart = 0x2, - /// Timer A Compare 1 event - TimerACompare1 = 0x3, + pub const TSTIM = enum(u1) { + /// Time stamp interrupt generation enabled + Unmasked = 0x0, + /// Time stamp interrupt generation disabled + Masked = 0x1, }; - pub const SYNCSTRT = enum(u1) { - /// Synchronization event has no effect on Timer x - Disabled = 0x0, - /// Synchronization event starts Timer x - Start = 0x1, + pub const TTC = enum(u3) { + /// 64 bytes + TTC64 = 0x0, + /// 128 bytes + TTC128 = 0x1, + /// 192 bytes + TTC192 = 0x2, + /// 256 bytes + TTC256 = 0x3, + /// 40 bytes + TTC40 = 0x4, + /// 32 bytes + TTC32 = 0x5, + /// 24 bytes + TTC24 = 0x6, + /// 16 bytes + TTC16 = 0x7, }; - pub const TIMAISR_DLYPRT = enum(u1) { - /// Not in delayed idle or balanced idle mode - Inactive = 0x0, - /// Delayed idle or balanced idle mode entry - Active = 0x1, + pub const USP = enum(u1) { + /// PBL value used for both Rx and Tx DMA + Combined = 0x0, + /// RxDMA uses RDP value, TxDMA uses PBL value + Separate = 0x1, }; - pub const UPDGAT = enum(u4) { - /// Update occurs independently from the DMA burst transfer - Independent = 0x0, - /// Update occurs when the DMA burst transfer is completed - DMABurst = 0x1, - /// Update occurs on the update event following DMA burst transfer completion - DMABurst_Update = 0x2, - /// Update occurs on a rising edge of HRTIM update enable input 1 - Input1 = 0x3, - /// Update occurs on a rising edge of HRTIM update enable input 2 - Input2 = 0x4, - /// Update occurs on a rising edge of HRTIM update enable input 3 - Input3 = 0x5, - /// Update occurs on the update event following a rising edge of HRTIM update enable input 1 - Input1_Update = 0x6, - /// Update occurs on the update event following a rising edge of HRTIM update enable input 2 - Input2_Update = 0x7, - /// Update occurs on the update event following a rising edge of HRTIM update enable input 3 - Input3_Update = 0x8, + pub const VLANTC = enum(u1) { + /// Full 16 bit VLAN identifiers are used for comparison and filtering + VLANTC16 = 0x0, + /// 12 bit VLAN identifies are used for comparison and filtering + VLANTC12 = 0x1, + }; + + pub const WD = enum(u1) { + /// Watchdog enabled, receive frames limited to 2048 bytes + Enabled = 0x0, + /// Watchdog disabled, receive frames may be up to to 16384 bytes + Disabled = 0x1, + }; + + pub const WFFRPR = enum(u1) { + /// Reset wakeup frame filter register point to 0b000. Automatically cleared + Reset = 0x1, _, }; - /// High Resolution Timer - pub const HRTIM = extern struct { - /// Master Timer Control Register - MCR: mmio.Mmio(packed struct(u32) { - /// HRTIM Master Clock prescaler - CKPSC: u3, - /// Master Continuous mode - CONT: u1, - /// Master Re-triggerable mode - RETRIG: u1, - /// Half mode enable - HALF: u1, - reserved8: u2, - /// Synchronization input - SYNCIN: packed union { - raw: u2, - value: SYNCIN, + pub const ZQPD = enum(u1) { + /// Normal operation with automatic zero-quanta pause control frame generation + Enabled = 0x0, + /// Automatic generation of zero-quanta pause control frames is disabled + Disabled = 0x1, + }; + + /// Ethernet Peripheral + pub const ETH = extern struct { + /// Ethernet: media access control (MAC) + ETHERNET_MAC: u32, + reserved1792: [1788]u8, + /// Ethernet: Precision Time Protocol (PTP) + ETHERNET_PTP: u32, + reserved4096: [2300]u8, + /// Ethernet: DMA mode register (DMA) + ETHERNET_DMA: u32, + }; + + /// Ethernet: DMA controller operation + pub const ETHERNET_DMA = extern struct { + /// Ethernet DMA bus mode register + DMABMR: mmio.Mmio(packed struct(u32) { + /// Software reset + SR: u1, + /// DMA arbitration + DA: packed union { + raw: u1, + value: DA, }, - /// Synchronization Resets Master - SYNCRSTM: u1, - /// Synchronization Starts Master - SYNCSTRTM: u1, - /// Synchronization output - SYNCOUT: packed union { - raw: u2, - value: SYNCOUT, + /// Descriptor skip length + DSL: u5, + /// Enhanced descriptor format enable + EDFE: u1, + /// Programmable burst length + PBL: packed union { + raw: u6, + value: PBL, }, - /// Synchronization source - SYNCSRC: packed union { + /// Rx-Tx priority ratio + PM: packed union { raw: u2, - value: SYNCSRC, + value: PriorityRxOverTx, }, - /// Master Counter enable - MCEN: u1, - /// Timer X counter enable - TCEN: u1, - reserved25: u7, - /// AC Synchronization - DACSYNC: packed union { - raw: u2, - value: DACSYNC, + /// Fixed burst + FB: packed union { + raw: u1, + value: FB, }, - /// Preload enable - PREEN: u1, - reserved29: u1, - /// Master Timer Repetition update - MREPU: u1, - /// Burst DMA Update - BRSTDMA: packed union { - raw: u2, - value: BRSTDMA, + /// Rx DMA PBL + RDP: packed union { + raw: u6, + value: RDP, + }, + /// Use separate PBL + USP: packed union { + raw: u1, + value: USP, + }, + /// 4xPBL mode + FPM: packed union { + raw: u1, + value: FPM, + }, + /// Address-aligned beats + AAB: u1, + /// Mixed burst + MB: packed union { + raw: u1, + value: MB, }, + padding: u5, }), - /// Master Timer Interrupt Status Register - MISR: mmio.Mmio(packed struct(u32) { - /// Master Compare X Interrupt Flag - MCMP: u1, - reserved4: u3, - /// Master Repetition Interrupt Flag - MREP: u1, - /// Sync Input Interrupt Flag - SYNC: u1, - /// Master Update Interrupt Flag - MUPD: u1, - padding: u25, + /// Ethernet DMA transmit poll demand register + DMATPDR: mmio.Mmio(packed struct(u32) { + /// Transmit poll demand + TPD: packed union { + raw: u32, + value: TPD, + }, }), - /// Master Timer Interrupt Clear Register - MICR: mmio.Mmio(packed struct(u32) { - /// Master Compare X Interrupt flag clear - MCMPC: u1, - reserved4: u3, - /// Repetition Interrupt flag clear - MREPC: u1, - /// Sync Input Interrupt flag clear - SYNCC: u1, - /// Master update Interrupt flag clear - MUPDC: u1, - padding: u25, + /// EHERNET DMA receive poll demand register + DMARPDR: mmio.Mmio(packed struct(u32) { + /// Receive poll demand + RPD: packed union { + raw: u32, + value: RPD, + }, }), - /// Master Timer DMA / Interrupt Enable Register - MDIER: mmio.Mmio(packed struct(u32) { - /// Master Compare X Interrupt Enable - MCMPIE: u1, - reserved4: u3, - /// Master Repetition Interrupt Enable - MREPIE: u1, - /// Sync Input Interrupt Enable - SYNCIE: u1, - /// Master Update Interrupt Enable - MUPDIE: u1, - reserved16: u9, - /// Master Compare X DMA request Enable - MCMPDE: u1, + /// Ethernet DMA receive descriptor list address register + DMARDLAR: mmio.Mmio(packed struct(u32) { + /// Start of receive list + SRL: u32, + }), + /// Ethernet DMA transmit descriptor list address register + DMATDLAR: mmio.Mmio(packed struct(u32) { + /// Start of transmit list + STL: u32, + }), + /// Ethernet DMA status register + DMASR: mmio.Mmio(packed struct(u32) { + /// Transmit status + TS: u1, + /// Transmit process stopped status + TPSS: u1, + /// Transmit buffer unavailable status + TBUS: u1, + /// Transmit jabber timeout status + TJTS: u1, + /// Receive overflow status + ROS: u1, + /// Transmit underflow status + TUS: u1, + /// Receive status + RS: u1, + /// Receive buffer unavailable status + RBUS: u1, + /// Receive process stopped status + RPSS: u1, + /// PWTS + PWTS: u1, + /// Early transmit status + ETS: u1, + reserved13: u2, + /// Fatal bus error status + FBES: u1, + /// Early receive status + ERS: u1, + /// Abnormal interrupt summary + AIS: u1, + /// Normal interrupt summary + NIS: u1, + /// Receive process state + RPS: packed union { + raw: u3, + value: RPS, + }, + /// Transmit process state + TPS: packed union { + raw: u3, + value: TPS, + }, + /// Error bits status + EBS: u3, + reserved27: u1, + /// MMC status + MMCS: u1, + /// PMT status + PMTS: u1, + /// Time stamp trigger status + TSTS: u1, + padding: u2, + }), + /// Ethernet DMA operation mode register + DMAOMR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Start/stop receive + SR: packed union { + raw: u1, + value: DMAOMR_SR, + }, + /// Operate on second frame + OSF: u1, + /// Receive threshold control + RTC: packed union { + raw: u2, + value: RTC, + }, + reserved6: u1, + /// Forward undersized good frames + FUGF: packed union { + raw: u1, + value: FUGF, + }, + /// Forward error frames + FEF: packed union { + raw: u1, + value: FEF, + }, + reserved13: u5, + /// Start/stop transmission + ST: packed union { + raw: u1, + value: ST, + }, + /// Transmit threshold control + TTC: packed union { + raw: u3, + value: TTC, + }, reserved20: u3, - /// Master Repetition DMA request Enable - MREPDE: u1, - /// Sync Input DMA request Enable - SYNCDE: u1, - /// Master Update DMA request Enable - MUPDDE: u1, - padding: u9, + /// Flush transmit FIFO + FTF: packed union { + raw: u1, + value: FTF, + }, + /// Transmit store and forward + TSF: packed union { + raw: u1, + value: TSF, + }, + reserved24: u2, + /// Disable flushing of received frames + DFRF: u1, + /// Receive store and forward + RSF: packed union { + raw: u1, + value: RSF, + }, + /// Dropping of TCP/IP checksum error frames disable + DTCEFD: packed union { + raw: u1, + value: DTCEFD, + }, + padding: u5, }), - /// Master Timer Counter Register - MCNTR: mmio.Mmio(packed struct(u32) { - /// Counter value - MCNT: u16, - padding: u16, + /// Ethernet DMA interrupt enable register + DMAIER: mmio.Mmio(packed struct(u32) { + /// Transmit interrupt enable + TIE: u1, + /// Transmit process stopped interrupt enable + TPSIE: u1, + /// Transmit buffer unavailable interrupt enable + TBUIE: u1, + /// Transmit jabber timeout interrupt enable + TJTIE: u1, + /// Receive overflow interrupt enable + ROIE: u1, + /// Transmit underflow interrupt enable + TUIE: u1, + /// Receive interrupt enable + RIE: u1, + /// Receive buffer unavailable interrupt enable + RBUIE: u1, + /// Receive process stopped interrupt enable + RPSIE: u1, + /// Receive watchdog timeout interrupt enable + RWTIE: u1, + /// Early transmit interrupt enable + ETIE: u1, + reserved13: u2, + /// Fatal bus error interrupt enable + FBEIE: u1, + /// Early receive interrupt enable + ERIE: u1, + /// Abnormal interrupt summary enable + AISE: u1, + /// Normal interrupt summary enable + NISE: u1, + padding: u15, }), - /// Master Timer Period Register - MPER: mmio.Mmio(packed struct(u32) { - /// Master Timer Period value - MPER: u16, - padding: u16, + /// Ethernet DMA missed frame and buffer overflow counter register + DMAMFBOCR: mmio.Mmio(packed struct(u32) { + /// Missed frames by the controller + MFC: u16, + /// Overflow bit for missed frame counter + OMFC: u1, + /// Missed frames by the application + MFA: u11, + /// Overflow bit for FIFO overflow counter + OFOC: u1, + padding: u3, }), - /// Master Timer Repetition Register - MREP: mmio.Mmio(packed struct(u32) { - /// Master Timer Repetition counter value - MREP: u8, + /// Ethernet DMA receive status watchdog timer register + DMARSWTR: mmio.Mmio(packed struct(u32) { + /// Receive status watchdog timer count + RSWTC: u8, padding: u24, }), - /// Master Timer Compare X Register - MCMP: mmio.Mmio(packed struct(u32) { - /// Master Timer Compare X value - MCMP: u16, - padding: u16, + reserved72: [32]u8, + /// Ethernet DMA current host transmit descriptor register + DMACHTDR: mmio.Mmio(packed struct(u32) { + /// Host transmit descriptor address pointer + HTDAP: u32, }), - reserved128: [96]u8, - /// High Resolution Timer: Timing Unit - TIM: u32, - reserved896: [764]u8, - /// High Resolution Timer: Control Register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Master Update Disable - MUDIS: u1, - /// Timer X Update Disable - TUDIS: u1, - reserved16: u14, - /// ADC Trigger X Update Source - ADUSRC: u3, - padding: u13, + /// Ethernet DMA current host receive descriptor register + DMACHRDR: mmio.Mmio(packed struct(u32) { + /// Host receive descriptor address pointer + HRDAP: u32, }), - /// High Resolution Timer: Control Register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Master Timer Software Update - MSWU: u1, - /// Timer X Software Update - TSWU: u1, - reserved8: u6, - /// Master Counter Software Reset - MRST: u1, - /// Timer X Counter Software Reset - TRST: u1, - padding: u22, + /// Ethernet DMA current host transmit buffer address register + DMACHTBAR: mmio.Mmio(packed struct(u32) { + /// Host transmit buffer address pointer + HTBAP: u32, }), - /// High Resolution Timer: Interrupt Status Register - ISR: mmio.Mmio(packed struct(u32) { - /// Fault X Interrupt Flag - FLT: u1, - reserved5: u4, - /// System Fault Interrupt Flag - SYSFLT: u1, - reserved16: u10, - /// DLL Ready Interrupt Flag - DLLRDY: u1, - /// Burst Mode Period Interrupt Flag - BMPER: u1, - padding: u14, - }), - /// High Resolution Timer: Interrupt Clear Register - ICR: mmio.Mmio(packed struct(u32) { - /// Fault X Interrupt Flag Clear - FLT: u1, - reserved5: u4, - /// System Fault Interrupt Flag Clear - SYSFLT: u1, - reserved16: u10, - /// DLL Ready Interrupt Flag Clear - DLLRDY: u1, - /// Burst Mode Period Interrupt Flag Clear - BMPER: u1, - padding: u14, - }), - /// High Resolution Timer: Interrupt Enable Register - IER: mmio.Mmio(packed struct(u32) { - /// Fault X Interrupt Flag Enable - FLT: u1, - reserved5: u4, - /// System Fault Interrupt Flag Enable - SYSFLT: u1, - reserved16: u10, - /// DLL Ready Interrupt Flag Enable - DLLRDY: u1, - /// Burst Mode Period Interrupt Flag Enable - BMPER: u1, - padding: u14, - }), - /// High Resolution Timer: Output Enable Register - OENR: mmio.Mmio(packed struct(u32) { - /// Timer X Output Enable - T1OEN: u1, - /// Timer X Complementary Output Enable - T2OEN: u1, - padding: u30, - }), - /// High Resolution Timer: Output Disable Register - ODISR: mmio.Mmio(packed struct(u32) { - /// Timer X Output Disable - T1ODIS: u1, - /// Timer X Complementary Output Disable - T2ODIS: u1, - padding: u30, - }), - /// High Resolution Timer: Output Disable Status Register - ODSR: mmio.Mmio(packed struct(u32) { - /// Timer X Output Disable Status - T1ODIS: u1, - /// Timer X Complementary Output Disable Status - T2ODIS: u1, - padding: u30, - }), - /// High Resolution Timer: Burst Mode Control Register - BMCR: mmio.Mmio(packed struct(u32) { - /// Burst Mode Enable - BME: u1, - /// Burst Mode Operating Mode - BMOM: u1, - /// Burst Mode Clock source - BMCLK: u3, - reserved6: u1, - /// Burst Mode Prescaler - BMPRSC: u3, - reserved10: u1, - /// Burst Mode Preload Enable - BMPREN: u1, - reserved16: u5, - /// Master Timer Burst Mode - MTBM: u1, - /// Timer X Burst Mode - TBM: u1, - reserved31: u13, - BMSTAT: u1, - }), - /// High Resolution Timer: Burst Mode Trigger Register - BMTRGR: mmio.Mmio(packed struct(u32) { - /// Software start - SW: u1, - /// Master reset or roll-over - MSTRST: u1, - /// Master repetition - MSTREP: u1, - /// Master Compare X - MSTCMP: u1, - reserved7: u3, - /// Timer X reset or roll-over - TRST: u1, - /// Timer X repetition - TREP: u1, - /// Timer X compare 1 event - TCMP1: u1, - /// Timer X compare 2 event - TCMP2: u1, - padding: u21, - }), - /// High Resolution Timer: Burst Mode Compare Register - BMCMPR: mmio.Mmio(packed struct(u32) { - /// Burst mode compare value - BMCMP: u16, - padding: u16, - }), - /// High Resolution Timer: Burst Mode Period Register - BMPER: mmio.Mmio(packed struct(u32) { - /// Burst mode period value - BMPER: u16, - padding: u16, - }), - /// High Resolution Timer: External Event Control Register 1 - EECR1: mmio.Mmio(packed struct(u32) { - /// External Event X Source - EESRC: u2, - /// External Event X Polarity - EEPOL: u1, - /// External Event X Sensitivity - EESNS: u2, - /// External Event X Fast Mode - EEFAST: u2, - padding: u25, - }), - /// High Resolution Timer: External Event Control Register 2 - EECR2: mmio.Mmio(packed struct(u32) { - /// External Event X Source - EESRC: u2, - /// External Event X Polarity - EEPOL: u1, - /// External Event X Sensitivity - EESNS: u2, - padding: u27, - }), - /// High Resolution Timer: External Event Control Register 3 - EECR3: mmio.Mmio(packed struct(u32) { - /// External Event X filter - EEF: u3, - reserved30: u27, - /// External Event Sampling Clock Division - EEVSD: u2, - }), - /// High Resolution Timer: ADC Trigger [1, 3] Register - ADC1R: mmio.Mmio(packed struct(u32) { - /// ADC trigger X on Master Compare Y - ADCMC: u1, - reserved4: u3, - /// ADC trigger X on Master Period - ADCMPER: u1, - /// ADC trigger X on External Event Y - ADCEEV: u1, - reserved10: u4, - /// ADC trigger X on Timer Y Compare 2 - ADCTC2: u1, - /// ADC trigger X on Timer Y Compare 3 - ADCTC3: u1, - /// ADC trigger X on Timer Y Compare 3 - ADCTC4: u1, - /// ADC trigger X on Timer Y Period - ADCTPER: u1, - /// ADC trigger X on Timer Y Reset - ADCTRST: u1, - padding: u17, - }), - /// High Resolution Timer: ADC Trigger [2, 4] Register - ADC2R: mmio.Mmio(packed struct(u32) { - /// ADC trigger X on Master Compare Y - ADCMC: u1, - reserved4: u3, - /// ADC trigger X on Master Period - ADCMPER: u1, - /// ADC trigger X on External Event Y - ADCEEV: u1, - reserved10: u4, - /// ADC trigger X on Timer Y Compare 2 - ADCTC2: u1, - /// ADC trigger X on Timer Y Compare 3 - ADCTC3: u1, - /// ADC trigger X on Timer Y Compare 3 - ADCTC4: u1, - /// ADC trigger X on Timer Y Period - ADCTPER: u1, - reserved22: u8, - /// ADC trigger X on Timer Y Reset - ADCTRST: u1, - padding: u9, - }), - reserved972: [8]u8, - /// High Resolution Timer: DLL Control Register - DLLCR: mmio.Mmio(packed struct(u32) { - /// DLL Calibration Start - CAL: u1, - /// DLL Calibration Enable - CALEN: u1, - /// DLL Calibration Rate - CALRTE: u2, - padding: u28, - }), - /// High Resolution Timer: Fault Input Register 1 - FLTINR1: mmio.Mmio(packed struct(u32) { - /// Fault X enable - FLTE: u1, - /// Fault X polarity - FLTP: u1, - /// Fault X source - FLTSRC: u1, - /// Fault X filter - FLTF: u4, - /// Fault X Lock - FLTLCK: u1, - padding: u24, - }), - reserved984: [4]u8, - /// High Resolution Timer: Burst DMA Master timer update Register - BDMUPR: mmio.Mmio(packed struct(u32) { - /// MCR register update enable - MCR: u1, - /// MICR register update enable - MICR: u1, - /// MDIER register update enable - MDIER: u1, - /// MCNT register update enable - MCNT: u1, - /// MPER register update enable - MPER: u1, - /// MREP register update enable - MREP: u1, - /// MCMP register X update enable - MCMP: u1, - padding: u25, - }), - /// High Resolution Timer: Burst DMA Timer X update Register - BDTUPR: [5]mmio.Mmio(packed struct(u32) { - /// CR register update enable - CR: u1, - /// ICR register update enable - ICR: u1, - /// DIER register update enable - DIER: u1, - /// CNT register update enable - CNT: u1, - /// PER register update enable - PER: u1, - /// REP register update enable - REP: u1, - /// CMP register X update enable - CMP: u1, - padding: u25, - }), - /// High Resolution Timer: Burst DMA Data Register - BDMADR: mmio.Mmio(packed struct(u32) { - /// Burst DMA Data register - BDMADR: u31, - padding: u1, + /// Ethernet DMA current host receive buffer address register + DMACHRBAR: mmio.Mmio(packed struct(u32) { + /// Host receive buffer address pointer + HRBAP: u32, }), }; - /// High Resolution Timer: Timing Unit - pub const HRTIM_TIMX = extern struct { - /// Timer X Control Register - CR: mmio.Mmio(packed struct(u32) { - /// HRTIM Timer x Clock prescaler - CKPSC: u3, - /// Continuous mode - CONT: u1, - /// Re-triggerable mode - RETRIG: u1, - /// Half mode enable - HALF: u1, - /// Push-Pull mode enable - PSHPLL: u1, - reserved10: u3, - /// Synchronization Resets Timer X - SYNCRST: packed union { - raw: u1, - value: SYNCRST, - }, - /// Synchronization Starts Timer X - SYNCSTRT: packed union { - raw: u1, - value: SYNCSTRT, - }, - /// Delayed CMP2 mode - DELCMP2: packed union { - raw: u2, - value: DELCMP, - }, - /// Delayed CMP4 mode - DELCMP4: packed union { - raw: u2, - value: DELCMP, - }, - reserved17: u1, - /// Timer X Repetition update - REPU: u1, - /// Timer X reset update - RSTU: u1, - /// Timer A update - TAU: u1, - /// Timer B update - TBU: u1, - /// Timer C update - TCU: u1, - /// Timer D update - TDU: u1, - /// Timer E update - TEU: u1, - /// Master Timer update - MSTU: u1, - /// AC Synchronization - DACSYNC: packed union { + /// Ethernet: media access control (MAC) + pub const ETHERNET_MAC = extern struct { + /// Ethernet MAC configuration register + MACCR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// Deferral check + DC: u1, + /// Back-off limit + BL: packed union { raw: u2, - value: DACSYNC, - }, - /// Preload enable - PREEN: u1, - /// Update Gating - UPDGAT: packed union { - raw: u4, - value: UPDGAT, - }, - }), - /// Timer X Interrupt Status Register - ISR: mmio.Mmio(packed struct(u32) { - /// Compare X Interrupt Flag - CMP: u1, - reserved4: u3, - /// Repetition Interrupt Flag - REP: u1, - reserved6: u1, - /// Update Interrupt Flag - UPD: u1, - /// Capture X Interrupt Flag - CPT: u1, - reserved9: u1, - /// Output X Set Interrupt Flag - SETR: u1, - /// Output X Reset Interrupt Flag - RSTR: u1, - reserved13: u2, - /// Reset Interrupt Flag - RST: u1, - /// Delayed Protection Flag - DLYPRT: packed union { - raw: u1, - value: TIMAISR_DLYPRT, - }, - reserved16: u1, - /// Current Push Pull Status - CPPSTAT: packed union { - raw: u1, - value: CPPSTAT, - }, - /// Idle Push Pull Status - IPPSTAT: packed union { - raw: u1, - value: IPPSTAT, - }, - /// Output X State - OSTAT: packed union { - raw: u1, - value: OUTPUTSTATE, + value: BL, }, - reserved20: u1, - /// Output X Copy - OCPY: packed union { + /// Automatic pad/CRC stripping + APCS: packed union { raw: u1, - value: OUTPUTSTATE, + value: APCS, }, - padding: u11, - }), - /// Timer X Interrupt Clear Register - ICR: mmio.Mmio(packed struct(u32) { - /// Compare X Interrupt flag Clear - CMPC: u1, - reserved4: u3, - /// Repetition Interrupt flag Clear - REPC: u1, - reserved6: u1, - /// Update Interrupt flag Clear - UPDC: u1, - /// Capture X Interrupt flag Clear - CPTC: u1, - reserved9: u1, - /// Output X Set flag Clear - SETRC: u1, - /// Output X Reset flag Clear - RSTRC: u1, - reserved13: u2, - /// Reset Interrupt flag Clear - RSTC: u1, - /// Delayed Protection Flag Clear - DLYPRTC: u1, - padding: u17, - }), - /// Timer X DMA / Interrupt Enable Register - DIER: mmio.Mmio(packed struct(u32) { - /// Compare X Interrupt Enable - CMPIE: u1, - reserved4: u3, - /// Repetition Interrupt Enable - REPIE: u1, - reserved6: u1, - /// Update Interrupt Enable - UPDIE: u1, - /// Capture Interrupt Enable - CPTIE: u1, reserved9: u1, - /// Output X Set Interrupt Enable - SETRIE: u1, - /// Output X Reset Interrupt Enable - RSTRIE: u1, - reserved13: u2, - /// Reset/roll-over Interrupt Enable - RSTIE: u1, - /// Delayed Protection Interrupt Enable - DLYPRTIE: u1, - reserved16: u1, - /// Compare X DMA request Enable - CMPDE: u1, - reserved20: u3, - /// Repetition DMA request Enable - REPDE: u1, - reserved22: u1, - /// Update DMA request Enable - UPDDE: u1, - /// Capture X DMA request Enable - CPTDE: u1, - reserved25: u1, - /// Output X Set DMA request Enable - SETRDE: u1, - /// Output X Reset DMA request Enable - RSTRDE: u1, - reserved29: u2, - /// Reset/roll-over DMA request Enable - RSTDE: u1, - /// Delayed Protection DMA request Enable - DLYPRTDE: u1, - padding: u1, - }), - /// Timer X Counter Register - CNT: mmio.Mmio(packed struct(u32) { - /// Timerx Counter value - CNT: u16, - padding: u16, - }), - /// Timer X Period Register - PER: mmio.Mmio(packed struct(u32) { - /// Timerx Period value - PER: u16, - padding: u16, - }), - /// Timer X Repetition Register - REP: mmio.Mmio(packed struct(u32) { - /// Timerx Repetition counter value - REP: u8, - padding: u24, - }), - /// Timer X Compare X Register - CMP: mmio.Mmio(packed struct(u32) { - /// Timerx Compare X value - CMP: u16, - padding: u16, - }), - /// Timer X Compare X Compound Register - CMPC: mmio.Mmio(packed struct(u32) { - /// Timerx Compare X value - CMP: u16, - /// Timerx Repetition value (aliased from HRTIM_REPx register) - REP: u8, - padding: u8, - }), - reserved48: [12]u8, - /// Timer X Capture X Register - CPT: [2]mmio.Mmio(packed struct(u32) { - /// Timerx Capture X value - CPT: u16, - padding: u16, - }), - /// Timer X Deadtime Register - DT: mmio.Mmio(packed struct(u32) { - /// Deadtime Rising value - DTR: u9, - /// Sign Deadtime Rising value - SDTR: packed union { - raw: u1, - value: SDTR, - }, - /// Deadtime Prescaler - DTPRSC: u3, - reserved14: u1, - /// Deadtime Rising Sign Lock - DTRSLK: u1, - /// Deadtime Rising Lock - DTRLK: u1, - /// Deadtime Falling value - DTF: u9, - /// Sign Deadtime Falling value - SDTF: packed union { + /// Retry disable + RD: packed union { raw: u1, - value: SDTF, + value: RD, }, - reserved30: u4, - /// Deadtime Falling Sign Lock - DTFSLK: u1, - /// Deadtime Falling Lock - DTFLK: u1, - }), - /// Timer X Output X Set Register - SETR: mmio.Mmio(packed struct(u32) { - /// Software Set trigger - SST: packed union { + /// IPv4 checksum offload + IPCO: packed union { raw: u1, - value: ACTIVEEFFECT, + value: IPCO, }, - /// Timer X resynchronizaton - RESYNC: packed union { + /// Duplex mode + DM: packed union { raw: u1, - value: ACTIVEEFFECT, + value: DM, }, - /// Timer X Period - PER: packed union { + /// Loopback mode + LM: packed union { raw: u1, - value: ACTIVEEFFECT, + value: LM, }, - /// Timer X compare X - CMP: packed union { + /// Receive own disable + ROD: packed union { raw: u1, - value: ACTIVEEFFECT, + value: ROD, }, - reserved7: u3, - /// Master Period - MSTPER: packed union { + /// Fast Ethernet speed + FES: packed union { raw: u1, - value: ACTIVEEFFECT, + value: FES, }, - /// Master Compare X - MSTCMPX: packed union { + reserved16: u1, + /// Carrier sense disable + CSD: packed union { raw: u1, - value: ACTIVEEFFECT, + value: CSD, }, - reserved12: u3, - /// Timer Event X - TIMEVNT: packed union { - raw: u1, - value: ACTIVEEFFECT, + /// Interframe gap + IFG: packed union { + raw: u3, + value: IFG, }, - reserved21: u8, - /// External Event X - EXTEVNT: packed union { + reserved22: u2, + /// Jabber disable + JD: packed union { raw: u1, - value: ACTIVEEFFECT, + value: JD, }, - reserved31: u9, - /// Registers update (transfer preload to active) - UPDATE: packed union { + /// Watchdog disable + WD: packed union { raw: u1, - value: ACTIVEEFFECT, + value: WD, }, + reserved25: u1, + /// CRC stripping for type frames + CSTF: u1, + padding: u6, }), - /// Timer X Output X Reset Register - RSTR: mmio.Mmio(packed struct(u32) { - /// Software Reset trigger - SRT: packed union { + /// Ethernet MAC frame filter register + MACFFR: mmio.Mmio(packed struct(u32) { + /// Promiscuous mode + PM: u1, + /// Hash unicast + HU: packed union { raw: u1, - value: INACTIVEEFFECT, + value: HU, }, - /// Timer X resynchronizaton - RESYNC: packed union { + /// Hash multicast + HM: packed union { raw: u1, - value: INACTIVEEFFECT, + value: HM, }, - /// Timer X Period - PER: packed union { + /// Destination address unique filtering + DAIF: packed union { raw: u1, - value: INACTIVEEFFECT, + value: DAIF, }, - /// Timer X compare X - CMP: packed union { + /// Pass all multicast + PAM: u1, + /// Broadcast frames disable + BFD: packed union { raw: u1, - value: INACTIVEEFFECT, + value: BFD, }, - reserved7: u3, - /// Master Period - MSTPER: packed union { - raw: u1, - value: INACTIVEEFFECT, + /// Pass control frames + PCF: packed union { + raw: u2, + value: PCF, }, - /// Master Compare X - MSTCMP: packed union { + /// Source address filter + SAF: u1, + /// Hash or perfect filter + HPF: packed union { raw: u1, - value: INACTIVEEFFECT, + value: HPF, }, - reserved12: u3, - /// Timer Event X - TIMEVNT: packed union { + reserved31: u21, + /// Receive all + RA: u1, + }), + /// Ethernet MAC hash table high register + MACHTHR: mmio.Mmio(packed struct(u32) { + /// Upper 32 bits of hash table + HTH: u32, + }), + /// Ethernet MAC hash table low register + MACHTLR: mmio.Mmio(packed struct(u32) { + /// Lower 32 bits of hash table + HTL: u32, + }), + /// Ethernet MAC MII address register + MACMIIAR: mmio.Mmio(packed struct(u32) { + /// MII busy + MB: packed union { raw: u1, - value: INACTIVEEFFECT, + value: MB_progress, }, - reserved21: u8, - /// External Event X - EXTEVNT: packed union { + /// MII write + MW: packed union { raw: u1, - value: INACTIVEEFFECT, + value: MW, }, - reserved31: u9, - /// Registers update (transfer preload to active) - UPDATE: packed union { - raw: u1, - value: INACTIVEEFFECT, + /// Clock range + CR: packed union { + raw: u3, + value: CR, }, + reserved6: u1, + /// MII register - select the desired MII register in the PHY device + MR: u5, + /// PHY address - select which of possible 32 PHYs is being accessed + PA: u5, + padding: u16, }), - reserved76: [8]u8, - /// Timer X External Event Filtering Register 1 - EEF: mmio.Mmio(packed struct(u32) { - /// External Event X latch - LTCH: u1, - /// External Event X filter - FLTR: packed union { - raw: u4, - value: EEFLTR, - }, - padding: u27, + /// Ethernet MAC MII data register + MACMIIDR: mmio.Mmio(packed struct(u32) { + /// MII data read from/written to the PHY + MD: u16, + padding: u16, }), - reserved84: [4]u8, - /// Timer X Reset Register - RST: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Timer X Update reset - UPDT: packed union { - raw: u1, - value: RESETEFFECT, - }, - /// Timer X compare X reset - CMP: packed union { - raw: u1, - value: RESETEFFECT, - }, - reserved4: u1, - /// Master timer Period - MSTPER: packed union { + /// Ethernet MAC flow control register + MACFCR: mmio.Mmio(packed struct(u32) { + /// Flow control busy/back pressure activate + FCB: packed union { raw: u1, - value: RESETEFFECT, + value: FCB, }, - /// Master compare X - MSTCMP: packed union { - raw: u1, - value: RESETEFFECT, + /// Transmit flow control enable + TFCE: u1, + /// Receive flow control enable + RFCE: u1, + /// Unicast pause frame detect + UPFD: u1, + /// Pause low threshold + PLT: packed union { + raw: u2, + value: PLT, }, - reserved9: u3, - /// External Event X - EXTEVNT: packed union { + reserved7: u1, + /// Zero-quanta pause disable + ZQPD: packed union { raw: u1, - value: RESETEFFECT, + value: ZQPD, }, - reserved19: u9, - /// Timer X compare 1 event - TCMP1: packed union { + reserved16: u8, + /// Pause time + PT: u16, + }), + /// Ethernet MAC VLAN tag register + MACVLANTR: mmio.Mmio(packed struct(u32) { + /// VLAN tag identifier (for receive frames) + VLANTI: u16, + /// 12-bit VLAN tag comparison + VLANTC: packed union { raw: u1, - value: RESETEFFECT, + value: VLANTC, }, - /// Timer X compare 2 event - TCMP2: packed union { + padding: u15, + }), + reserved40: [8]u8, + /// Ethernet MAC remote wakeup frame filter register + MACRWUFFR: u32, + /// Ethernet MAC PMT control and status register + MACPMTCSR: mmio.Mmio(packed struct(u32) { + /// Power down + PD: packed union { raw: u1, - value: RESETEFFECT, + value: PD, }, - /// Timer X compare 4 event - TCMP4: packed union { + /// Magic packet enable + MPE: u1, + /// Wakeup frame enable + WFE: u1, + reserved5: u2, + /// Magic packet received + MPR: u1, + /// Wakeup frame received + WFR: u1, + reserved9: u2, + /// Global unicast + GU: u1, + reserved31: u21, + /// Wakeup frame filter register pointer reset + WFFRPR: packed union { raw: u1, - value: RESETEFFECT, + value: WFFRPR, }, - padding: u10, }), - /// Timer X Chopper Register - CHP: mmio.Mmio(packed struct(u32) { - /// Timerx carrier frequency value - CARFRQ: u4, - /// Timerx chopper duty cycle value - CARDTY: u3, - /// Timerx start pulsewidth - STRTPW: u4, - padding: u21, + reserved52: [4]u8, + /// Ethernet MAC debug register + MACDBGR: mmio.Mmio(packed struct(u32) { + /// MAC MII receive protocol engine active + MMRPEA: u1, + /// MAC small FIFO read/write controllers status + MSFRWCS: u2, + reserved4: u1, + /// Rx FIFO write controller active + RFWRA: u1, + /// Rx FIFO read controller status + RFRCS: u2, + reserved8: u1, + /// Rx FIFO fill level + RFFL: u2, + reserved16: u6, + /// MAC MII transmit engine active + MMTEA: u1, + /// MAC transmit frame controller status + MTFCS: u2, + /// MAC transmitter in pause + MTP: u1, + /// Tx FIFO read status + TFRS: u2, + /// Tx FIFO write active + TFWA: u1, + reserved24: u1, + /// Tx FIFO not empty + TFNE: u1, + /// Tx FIFO full + TFF: u1, + padding: u6, }), - /// Timer X Capture X Control Register - CCR: mmio.Mmio(packed struct(u32) { - /// Software Capture - SWCPT: packed union { - raw: u1, - value: CAPTUREEFFECT, - }, - /// Update Capture - UPDCPT: packed union { - raw: u1, - value: CAPTUREEFFECT, - }, - /// External Event X Capture - EXEVCPT: packed union { + /// Ethernet MAC interrupt status register + MACSR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// PMT status + PMTS: u1, + /// MMC status + MMCS: u1, + /// MMC receive status + MMCRS: u1, + /// MMC transmit status + MMCTS: u1, + reserved9: u2, + /// Time stamp trigger status + TSTS: u1, + padding: u22, + }), + /// Ethernet MAC interrupt mask register + MACIMR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// PMT interrupt mask + PMTIM: packed union { raw: u1, - value: CAPTUREEFFECT, + value: PMTIM, }, - reserved16: u13, - /// Timer X output Set - TXSET: packed union { + reserved9: u5, + /// Time stamp trigger interrupt mask + TSTIM: packed union { raw: u1, - value: CAPTUREEFFECT, + value: TSTIM, }, - /// Timer X output Reset - TXRST: packed union { + padding: u22, + }), + /// Ethernet MAC address 0 high register + MACA0HR: mmio.Mmio(packed struct(u32) { + /// Ethernet MAC address 0 high + MACA0H: u16, + reserved31: u15, + /// Always 1 + MO: u1, + }), + /// Ethernet MAC address 0 low register + MACA0LR: mmio.Mmio(packed struct(u32) { + /// Ethernet MAC address 0 low + MACA0L: u32, + }), + /// Ethernet MAC address 1/2/3 high register + MACAHR: mmio.Mmio(packed struct(u32) { + /// Ethernet MAC address 1/2/3 high + MACAH: u16, + reserved24: u8, + /// MBC + MBC: u6, + /// SA + SA: packed union { raw: u1, - value: CAPTUREEFFECT, + value: MACAHR_SA, }, - /// Timer X Compare X - TXCMP: packed union { + /// AE + AE: u1, + }), + /// Ethernet MAC address 1/2/3 low register + MACALR: mmio.Mmio(packed struct(u32) { + /// thernet MAC address 1/2/3 low + MACAL: u32, + }), + reserved256: [176]u8, + /// Ethernet MMC control register + MMCCR: mmio.Mmio(packed struct(u32) { + /// Counter reset + CR: packed union { raw: u1, - value: CAPTUREEFFECT, + value: CounterReset, }, - reserved20: u1, - /// Timer Y output Set - TYSET: packed union { + /// Counter stop rollover + CSR: packed union { raw: u1, - value: CAPTUREEFFECT, + value: CSR, }, - /// Timer Y output Reset - TYRST: packed union { + /// Reset on read + ROR: u1, + /// MMC counter freeze + MCF: u1, + /// MMC counter preset + MCP: packed union { raw: u1, - value: CAPTUREEFFECT, + value: MCP, }, - /// Timer Y Compare X - TYCMP: packed union { + /// MMC counter Full-Half preset + MCFHP: packed union { raw: u1, - value: CAPTUREEFFECT, + value: MCFHP, }, - reserved24: u1, - /// Timer Z output Set - TZSET: packed union { + padding: u26, + }), + /// Ethernet MMC receive interrupt register + MMCRIR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Received frames CRC error status + RFCES: u1, + /// Received frames alignment error status + RFAES: u1, + reserved17: u10, + /// Received good Unicast frames status + RGUFS: u1, + padding: u14, + }), + /// Ethernet MMC transmit interrupt register + MMCTIR: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// Transmitted good frames single collision status + TGFSCS: u1, + /// Transmitted good frames more than single collision status + TGFMSCS: u1, + reserved21: u5, + /// Transmitted good frames status + TGFS: u1, + padding: u10, + }), + /// Ethernet MMC receive interrupt mask register + MMCRIMR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Received frame CRC error mask + RFCEM: packed union { raw: u1, - value: CAPTUREEFFECT, + value: RFCEM, }, - /// Timer Z output Reset - TZRST: packed union { + /// Received frames alignment error mask + RFAEM: packed union { raw: u1, - value: CAPTUREEFFECT, + value: RFAEM, }, - /// Timer Z Compare X - TZCMP: packed union { + reserved17: u10, + /// Received good Unicast frames mask + RGUFM: packed union { raw: u1, - value: CAPTUREEFFECT, + value: RGUFM, }, - reserved28: u1, - /// Timer T output Set - TTSET: packed union { + padding: u14, + }), + /// Ethernet MMC transmit interrupt mask register + MMCTIMR: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// Transmitted good frames single collision mask + TGFSCM: packed union { raw: u1, - value: CAPTUREEFFECT, + value: TGFSCM, }, - /// Timer T output Reset - TTRST: packed union { + /// Transmitted good frames more than single collision mask + TGFMSCM: packed union { raw: u1, - value: CAPTUREEFFECT, + value: TGFMSCM, }, - /// Timer T Compare X - TTCMP: packed union { + /// Transmitted good frames mask + TGFM: packed union { raw: u1, - value: CAPTUREEFFECT, + value: TGFM, }, - padding: u1, + padding: u15, }), - reserved100: [4]u8, - /// Timer X Output Register - OUTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Output 1 polarity - POL: packed union { - raw: u1, - value: POL, - }, - /// Output X Idle mode - IDLEM: u1, - /// Output X Idle State - IDLES: u1, - /// Output X Fault state - FAULTX: packed union { - raw: u2, - value: FAULT, - }, - /// Output X Chopper enable - CHP: u1, - /// Output X Deadtime upon burst mode Idle entry - DIDL: u1, - /// Deadtime enable - DTEN: u1, - /// Delayed Protection Enable - DLYPRTEN: u1, - /// Delayed Protection - DLYPRT: packed union { - raw: u3, - value: DLYPRT, - }, - padding: u19, - }), - /// Timer X Fault Register - FLT: mmio.Mmio(packed struct(u32) { - /// Fault X enable - FLTEN: packed union { - raw: u1, - value: FLTEN, - }, - reserved31: u30, - /// Fault sources Lock - FLTLCK: u1, - }), - }; - }; - - pub const fdcanram_h7 = struct { - /// FDCAN Message RAM - pub const FDCANRAM = extern struct { - /// FDCAN Message RAM - RAM: [2560]u32, - }; - }; - - pub const rtc_v1 = struct { - pub const RTOFF = enum(u1) { - /// Last write operation on RTC registers is still ongoing - Ongoing = 0x0, - /// Last write operation on RTC registers terminated - Terminated = 0x1, - }; - - /// Real-time clock - pub const RTC = extern struct { - /// Control Register High - CRH: mmio.Mmio(packed struct(u32) { - /// Second interrupt enable - SECIE: u1, - /// Alarm interrupt enable - ALRIE: u1, - /// Overflow interrupt enable - OWIE: u1, - padding: u29, - }), - /// Control Register Low - CRL: mmio.Mmio(packed struct(u32) { - /// Second flag - SECF: u1, - /// Alarm flag - ALRF: u1, - /// Overflow flag - OWF: u1, - /// Registers synchronized flag - RSF: u1, - /// Enter configuration mode - CNF: u1, - /// RTC operation OFF - RTOFF: packed union { - raw: u1, - value: RTOFF, - }, - padding: u26, - }), - /// Prescaler Load Register High - PRLH: mmio.Mmio(packed struct(u32) { - /// Prescaler load register high - PRLH: u4, - padding: u28, - }), - /// Prescaler Load Register Low - PRLL: mmio.Mmio(packed struct(u32) { - /// Prescaler divider register low - PRLL: u16, - padding: u16, - }), - /// Prescaler Divider Register High - DIVH: mmio.Mmio(packed struct(u32) { - /// Prescaler divider register high - DIVH: u4, - padding: u28, + reserved332: [56]u8, + /// Ethernet MMC transmitted good frames after a single collision counter + MMCTGFSCCR: mmio.Mmio(packed struct(u32) { + /// Transmitted good frames single collision counter + TGFSCC: u32, }), - /// Prescaler Divider Register Low - DIVL: mmio.Mmio(packed struct(u32) { - /// Prescaler divider register low - DIVL: u16, - padding: u16, + /// Ethernet MMC transmitted good frames after more than a single collision + MMCTGFMSCCR: mmio.Mmio(packed struct(u32) { + /// TGFMSCC + TGFMSCC: u32, }), - /// Counter Register High - CNTH: mmio.Mmio(packed struct(u32) { - /// Counter register high - CNTH: u16, - padding: u16, + reserved360: [20]u8, + /// Ethernet MMC transmitted good frames counter register + MMCTGFCR: mmio.Mmio(packed struct(u32) { + /// HTL + TGFC: u32, }), - /// Counter Register Low - CNTL: mmio.Mmio(packed struct(u32) { - /// Counter register low - CNTL: u16, - padding: u16, + reserved404: [40]u8, + /// Ethernet MMC received frames with CRC error counter register + MMCRFCECR: mmio.Mmio(packed struct(u32) { + /// RFCFC + RFCFC: u32, }), - /// Alarm Register High - ALRH: mmio.Mmio(packed struct(u32) { - /// Alarm register high - ALRH: u16, - padding: u16, + /// Ethernet MMC received frames with alignment error counter register + MMCRFAECR: mmio.Mmio(packed struct(u32) { + /// RFAEC + RFAEC: u32, }), - /// Alarm Register Low - ALRL: mmio.Mmio(packed struct(u32) { - /// Alarm register low - ALRL: u16, - padding: u16, + reserved452: [40]u8, + /// MMC received good unicast frames counter register + MMCRGUFCR: mmio.Mmio(packed struct(u32) { + /// RGUFC + RGUFC: u32, }), }; - }; - - pub const pwr_l4 = struct { - pub const LPMS = enum(u3) { - /// Stop 0 mode - Stop0 = 0x0, - /// Stop 1 mode - Stop1 = 0x1, - /// Stop 2 mode - Stop2 = 0x2, - /// Standby mode - Standby = 0x3, - /// Shutdown mode - Shutdown = 0x4, - _, - }; - pub const LPR = enum(u1) { - /// Voltage regulator in Main mode - MainMode = 0x0, - /// Voltage regulator in low-power mode - LowPowerMode = 0x1, - }; - - pub const PLS = enum(u3) { - /// 2.0V - V2_0 = 0x0, - /// 2.2V - V2_2 = 0x1, - /// 2.4V - V2_4 = 0x2, - /// 2.5V - V2_5 = 0x3, - /// 2.6V - V2_6 = 0x4, - /// 2.8V - V2_8 = 0x5, - /// 2.9V - V2_9 = 0x6, - /// External input analog voltage PVD_IN (compared internally to VREFINT) - External = 0x7, - }; - - pub const RRS = enum(u1) { - /// SRAM2 powered off in Standby mode (SRAM2 content lost) - PowerOff = 0x0, - /// SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) - OnLPR = 0x1, - }; - - pub const VOS = enum(u2) { - /// Range 1 - Range1 = 0x1, - /// Range 2 - Range2 = 0x2, - _, - }; - - /// Power control - pub const PWR = extern struct { - /// Power control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection - LPMS: packed union { - raw: u3, - value: LPMS, - }, - reserved8: u5, - /// Disable backup domain write protection - DBP: u1, - /// Voltage scaling range selection - VOS: packed union { - raw: u2, - value: VOS, - }, - reserved14: u3, - /// Low-power run - LPR: packed union { - raw: u1, - value: LPR, - }, - padding: u17, + /// Ethernet: Precision time protocol + pub const ETHERNET_PTP = extern struct { + /// Ethernet PTP time stamp control register + PTPTSCR: mmio.Mmio(packed struct(u32) { + /// TSE + TSE: u1, + /// TSFCU + TSFCU: u1, + /// TSSTI + TSSTI: u1, + /// TSSTU + TSSTU: u1, + /// TSITE + TSITE: u1, + /// TTSARU + TTSARU: u1, + reserved8: u2, + /// TSSARFE + TSSARFE: u1, + /// TSSSR + TSSSR: u1, + /// TSPTPPSV2E + TSPTPPSV2E: u1, + /// TSSPTPOEFE + TSSPTPOEFE: u1, + /// TSSIPV6FE + TSSIPV6FE: u1, + /// TSSIPV4FE + TSSIPV4FE: u1, + /// TSSEME + TSSEME: u1, + /// TSSMRME + TSSMRME: u1, + /// TSCNT + TSCNT: u2, + /// TSPFFMAE + TSPFFMAE: u1, + padding: u13, }), - /// Power control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Power voltage detector enable - PVDE: u1, - /// Power voltage detector level selection - PLS: packed union { - raw: u3, - value: PLS, - }, - /// Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V - PVME1: u1, - /// Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V - PVME2: u1, - /// Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V - PVME3: u1, - /// Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V - PVME4: u1, - reserved9: u1, - /// VDDIO2 Independent I/Os supply valid - IOSV: u1, - /// VDDUSB USB supply valid - USV: u1, - padding: u21, + /// Ethernet PTP subsecond increment register + PTPSSIR: mmio.Mmio(packed struct(u32) { + /// STSSI + STSSI: u8, + padding: u24, }), - /// Power control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin WKUP - EWUP: u1, - reserved8: u7, - /// SRAM2 retention in Standby mode - RRS: packed union { - raw: u1, - value: RRS, - }, - reserved10: u1, - /// Apply pull-up and pull-down configuration - APC: u1, - reserved15: u4, - /// Enable internal wakeup line - EWF: u1, - padding: u16, + /// Ethernet PTP time stamp high register + PTPTSHR: mmio.Mmio(packed struct(u32) { + /// STS + STS: u32, }), - /// Power control register 4 - CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity - WP1: u1, - /// Wakeup pin WKUP2 polarity - WP2: u1, - /// Wakeup pin WKUP3 polarity - WP3: u1, - /// Wakeup pin WKUP4 polarity - WP4: u1, - /// Wakeup pin WKUP5 polarity - WP5: u1, - reserved8: u3, - /// VBAT battery charging enable - VBE: u1, - /// VBAT battery charging resistor selection - VBRS: u1, - padding: u22, + /// Ethernet PTP time stamp low register + PTPTSLR: mmio.Mmio(packed struct(u32) { + /// STSS + STSS: u31, + /// STPNS + STPNS: u1, }), - /// Power status register 1 - SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag 1 - CWUF1: u1, - /// Wakeup flag 2 - CWUF2: u1, - /// Wakeup flag 3 - CWUF3: u1, - /// Wakeup flag 4 - CWUF4: u1, - /// Wakeup flag 5 - CWUF5: u1, - reserved8: u3, - /// Standby flag - CSBF: u1, - reserved15: u6, - /// Wakeup flag internal - WUFI: u1, - padding: u16, + /// Ethernet PTP time stamp high update register + PTPTSHUR: mmio.Mmio(packed struct(u32) { + /// TSUS + TSUS: u32, }), - /// Power status register 2 - SR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Low-power regulator started - REGLPS: u1, - /// Low-power regulator flag - REGLPF: u1, - /// Voltage scaling flag - VOSF: u1, - /// Power voltage detector output - PVDO: u1, - /// Peripheral voltage monitoring output: VDDUSB vs. 1.2 V - PVMO1: u1, - /// Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V - PVMO2: u1, - /// Peripheral voltage monitoring output: VDDA vs. 1.62 V - PVMO3: u1, - /// Peripheral voltage monitoring output: VDDA vs. 2.2 V - PVMO4: u1, - padding: u16, + /// Ethernet PTP time stamp low update register + PTPTSLUR: mmio.Mmio(packed struct(u32) { + /// TSUSS + TSUSS: u31, + /// TSUPNS + TSUPNS: u1, }), - /// Power status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag - CWUF: u1, - reserved8: u7, - /// Clear standby flag - SBF: u1, - padding: u23, + /// Ethernet PTP time stamp addend register + PTPTSAR: mmio.Mmio(packed struct(u32) { + /// TSA + TSA: u32, }), - reserved32: [4]u8, - /// Power Port A pull-up control register - PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// Ethernet PTP target time high register + PTPTTHR: mmio.Mmio(packed struct(u32) { + /// 0 + TTSH: u32, }), - /// Power Port A pull-down control register - PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// Ethernet PTP target time low register + PTPTTLR: mmio.Mmio(packed struct(u32) { + /// TTSL + TTSL: u32, + }), + reserved40: [4]u8, + /// Ethernet PTP time stamp status register + PTPTSSR: mmio.Mmio(packed struct(u32) { + /// TSSO + TSSO: u1, + /// TSSO + TSTTR: u1, + padding: u30, + }), + /// Ethernet PTP PPS control register + PTPPPSCR: mmio.Mmio(packed struct(u32) { + /// TSSO + TSSO: u1, + /// TSTTR + TSTTR: u1, + padding: u30, }), - }; - }; - - pub const usbram_16x1_512 = struct { - /// USB Endpoint memory - pub const USBRAM = extern struct { - /// USB Endpoint memory - MEM: [256]u32, }; }; @@ -331730,5488 +329738,8788 @@ pub const types = struct { }; }; - pub const syscfg_u5 = struct { - /// System configuration controller - pub const SYSCFG = extern struct { - /// SYSCFG secure configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock control security - SYSCFGSEC: u1, - /// CLASSBSEC - CLASSBSEC: u1, - reserved3: u1, - /// FPUSEC - FPUSEC: u1, - padding: u28, + pub const exti_c0 = struct { + /// External interrupt/event controller + pub const EXTI = extern struct { + /// Rising Trigger selection register + RTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// I/O analog switch voltage booster enable - BOOSTEN: u1, - /// GPIO analog switch control voltage selection - ANASWVDD: u1, - reserved16: u6, - /// PB6_FMP - PB6_FMP: u1, - /// PB7_FMP - PB7_FMP: u1, - /// PB8_FMP - PB8_FMP: u1, - /// PB9_FMP - PB9_FMP: u1, - padding: u12, + /// Falling Trigger selection register + FTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - /// FPU interrupt mask register - FPUIMR: mmio.Mmio(packed struct(u32) { - /// Floating point unit interrupts enable bits - FPU_IE: u6, - padding: u26, + /// Software interrupt event register + SWIER: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - /// SYSCFG CPU non-secure lock register - CNSLCKR: mmio.Mmio(packed struct(u32) { - /// VTOR_NS register lock - LOCKNSVTOR: u1, - /// Non-secure MPU registers lock - LOCKNSMPU: u1, - padding: u30, + /// Rising pending register + RPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - /// SYSCFG CPU secure lock register - CSLOCKR: mmio.Mmio(packed struct(u32) { - /// LOCKSVTAIRCR - LOCKSVTAIRCR: u1, - /// LOCKSMPU - LOCKSMPU: u1, - /// LOCKSAU - LOCKSAU: u1, - padding: u29, + /// Falling pending register + FPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - /// configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// LOCKUP (hardfault) output enable bit - CLL: u1, - /// SRAM ECC lock bit - SPL: u1, - /// PVD lock enable bit - PVDL: u1, - /// ECC Lock - ECCL: u1, - padding: u28, + reserved96: [76]u8, + /// Configuration register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI configuration bits + EXTI: u8, + padding: u24, }), - /// memory erase status register - MESR: mmio.Mmio(packed struct(u32) { - /// MCLR - MCLR: u1, - reserved16: u15, - /// IPMEE - IPMEE: u1, - padding: u15, + reserved128: [16]u8, + /// Interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - /// compensation cell control/status register - CCCSR: mmio.Mmio(packed struct(u32) { - /// EN1 - EN1: u1, - /// CS1 - CS1: u1, - /// EN2 - EN2: u1, - /// CS2 - CS2: u1, - reserved8: u4, - /// RDY1 - RDY1: u1, - /// RDY2 - RDY2: u1, - padding: u22, + /// Event mask register + EMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - /// compensation cell value register - CCVR: mmio.Mmio(packed struct(u32) { - /// NCV1 - NCV1: u4, - /// PCV1 - PCV1: u4, - /// NCV2 - NCV2: u4, - /// PCV2 - PCV2: u4, - padding: u16, + }; + }; + + pub const exti_g0 = struct { + /// External interrupt/event controller + pub const EXTI = extern struct { + /// Rising Trigger selection register + RTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - /// compensation cell code register - CCCR: mmio.Mmio(packed struct(u32) { - /// NCC1 - NCC1: u4, - /// PCC1 - PCC1: u4, - /// NCC2 - NCC2: u4, - /// PCC2 - PCC2: u4, - padding: u16, + /// Falling Trigger selection register + FTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - reserved44: [4]u8, - /// RSS command register - RSSCMDR: mmio.Mmio(packed struct(u32) { - /// RSS commands - RSSCMD: u16, - padding: u16, + /// Software interrupt event register + SWIER: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - reserved112: [64]u8, - /// USB Type C and Power Delivery register - UCPDR: mmio.Mmio(packed struct(u32) { - /// CC1ENRXFILTER - CC1ENRXFILTER: u1, - /// CC2ENRXFILTER - CC2ENRXFILTER: u1, - padding: u30, + /// Rising pending register + RPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Falling pending register + FPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + reserved96: [76]u8, + /// Configuration register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI configuration bits + EXTI: u8, + padding: u24, + }), + reserved128: [16]u8, + /// Interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Event mask register + EMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), }; }; - pub const gfxmmu_v1 = struct { - pub const BM192 = enum(u1) { - /// 256 blocks per line. - @"256BlocksPerLine" = 0x0, - /// 192 blocks per line. - @"192BlocksPerLine" = 0x1, + pub const exti_h5 = struct { + /// Extended interrupt and event controller + pub const EXTI = extern struct { + /// rising trigger selection register + RTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// falling trigger selection register + FTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// software interrupt event register + SWIER: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// rising edge pending register + RPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// falling edge pending register + FPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// security configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + SEC: u1, + padding: u31, + }), + /// privilege configuration register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + PRIV: u1, + padding: u31, + }), + reserved96: [68]u8, + /// external interrupt selection register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved + EXTI: u8, + padding: u24, + }), + /// lock register + LOCKR: mmio.Mmio(packed struct(u32) { + /// Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock This bit is written once after reset. + LOCK: u1, + padding: u31, + }), + reserved128: [12]u8, + /// CPU wakeup with interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// CPU wakeup with event mask register + EMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), }; + }; - /// GFXMMU. - pub const GFXMMU = extern struct { - /// GFXMMU configuration register. - CR: mmio.Mmio(packed struct(u32) { - /// Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. - BOIE: u1, - reserved4: u3, - /// AHB master error interrupt enable. This bit enables the AHB master error interrupt. - AMEIE: u1, - reserved6: u1, - /// 192 Block mode. This bit defines the number of blocks per line. - BM: packed union { - raw: u1, - value: BM192, - }, - padding: u25, + pub const exti_h50 = struct { + /// Extended interrupt and event controller + pub const EXTI = extern struct { + /// rising trigger selection register + RTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - /// GFXMMU status register. - SR: mmio.Mmio(packed struct(u32) { - /// Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. - BOF: u1, - reserved4: u3, - /// AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF. - AMEF: u1, - padding: u27, + /// falling trigger selection register + FTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - /// GFXMMU flag clear register. - FCR: mmio.Mmio(packed struct(u32) { - /// Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. - CBOF: u1, - reserved4: u3, - /// Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register. - CAMEF: u1, - padding: u27, + /// software interrupt event register + SWIER: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - reserved16: [4]u8, - /// GFXMMU default value register. - DVR: mmio.Mmio(packed struct(u32) { - /// Default value. This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped. - DV: u32, + /// rising edge pending register + RPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - reserved32: [12]u8, - /// GFXMMU buffer 0 configuration register. - BCR: [4]mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Physical buffer offset. Offset of the physical buffer. - PBO: u19, - /// Physical buffer base address. Base address MSB of the physical buffer. - PBBA: u9, + /// falling edge pending register + FPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), - reserved4096: [4048]u8, - /// GFXMMU LUT entry 0 low. - LUTL: mmio.Mmio(packed struct(u32) { - /// Line enable. - EN: u1, - reserved8: u7, - /// First Valid Block. Number of the first valid block of line number x. - FVB: u8, - /// Last Valid Block. Number of the last valid block of line number X. - LVB: u8, - padding: u8, + reserved24: [4]u8, + /// privilege configuration register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + PRIV: u1, + padding: u31, }), - /// GFXMMU LUT entry 0 high. - LUTH: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Line offset. Line offset of line number x (i.e. offset of block 0 of line x). - LO: u18, - padding: u10, + reserved96: [68]u8, + /// external interrupt selection register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved + EXTI: u8, + padding: u24, + }), + reserved128: [16]u8, + /// CPU wakeup with interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// CPU wakeup with event mask register + EMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, }), }; }; - pub const crc_v3 = struct { - pub const POLYSIZE = enum(u2) { - /// 32-bit polynomial - Polysize32 = 0x0, - /// 16-bit polynomial - Polysize16 = 0x1, - /// 8-bit polynomial - Polysize8 = 0x2, - /// 7-bit polynomial - Polysize7 = 0x3, + pub const exti_h7 = struct { + /// External interrupt/event controller + pub const EXTI = extern struct { + /// Rising Trigger selection register + RTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Falling Trigger selection register + FTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Software interrupt event register + SWIER: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + reserved128: [116]u8, + /// Interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Event mask register + EMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Pending register + PR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), }; + }; - pub const REV_IN = enum(u2) { - /// Bit order not affected - Normal = 0x0, - /// Bit reversal done by byte - Byte = 0x1, - /// Bit reversal done by half-word - HalfWord = 0x2, - /// Bit reversal done by word - Word = 0x3, + pub const exti_l5 = struct { + /// External interrupt/event controller + pub const EXTI = extern struct { + /// Rising Trigger selection register + RTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Falling Trigger selection register + FTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Software interrupt event register + SWIER: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Rising pending register + RPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Falling pending register + FPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Security configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// Security enable on event input x + SEC: u1, + padding: u31, + }), + /// Privilege configuration register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// Security enable on event input x + PRIV: u1, + padding: u31, + }), + reserved96: [68]u8, + /// Configuration register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI configuration bits + EXTI: u8, + padding: u24, + }), + /// EXTI lock register + LOCKRG: mmio.Mmio(packed struct(u32) { + /// LOCK + LOCK: u1, + padding: u31, + }), + reserved128: [12]u8, + /// Interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Event mask register + EMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), }; + }; - pub const REV_OUT = enum(u1) { - /// Bit order not affected - Normal = 0x0, - /// Bit reversed output - Reversed = 0x1, + pub const exti_u0 = struct { + /// External interrupt/event controller + pub const EXTI = extern struct { + /// Rising Trigger selection register + RTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Falling Trigger selection register + FTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Software interrupt event register + SWIER: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Rising pending register + RPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Falling pending register + FPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + reserved96: [76]u8, + /// Configuration register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI configuration bits + EXTI: u8, + padding: u24, + }), + reserved128: [16]u8, + /// Interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Event mask register + EMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), }; + }; - /// Cyclic Redundancy Check calculation unit - pub const CRC = extern struct { - /// Data register - half-word sized - DR16: u32, - /// Independent Data register - IDR: u32, - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// RESET bit - RESET: u1, - reserved3: u2, - /// Polynomial size - POLYSIZE: packed union { - raw: u2, - value: POLYSIZE, - }, - /// Reverse input data - REV_IN: packed union { - raw: u2, - value: REV_IN, - }, - /// Reverse output data - REV_OUT: packed union { - raw: u1, - value: REV_OUT, - }, + pub const exti_u5 = struct { + /// External interrupt/event controller + pub const EXTI = extern struct { + /// Rising Trigger selection register + RTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Falling Trigger selection register + FTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Software interrupt event register + SWIER: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Rising pending register + RPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Falling pending register + FPR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Security configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// Security enable on event input x + SEC: u1, + padding: u31, + }), + /// Privilege configuration register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// Security enable on event input x + PRIV: u1, + padding: u31, + }), + reserved96: [68]u8, + /// Configuration register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI configuration bits + EXTI: u8, padding: u24, }), - reserved16: [4]u8, - /// Initial CRC value - INIT: u32, - /// CRC polynomial - POL: u32, + /// EXTI lock register + LOCKRG: mmio.Mmio(packed struct(u32) { + /// LOCK + LOCK: u1, + padding: u31, + }), + reserved128: [12]u8, + /// Interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Event mask register + EMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), }; }; - pub const pwr_h5 = struct { - pub const ALS = enum(u2) { - /// AVD level0 (VAVD0 ~ 1.7 V) - Level0 = 0x0, - /// AVD level1 (VAVD1 ~ 2.1 V) - Level1 = 0x1, - /// AVD level2 (VAVD2 ~ 2.5 V) - Level2 = 0x2, - /// AVD level3 (VAVD3 ~ 2.8 V) - Level3 = 0x3, + pub const exti_v1 = struct { + /// External interrupt/event controller + pub const EXTI = extern struct { + /// Interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Interrupt mask register + EMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Rising Trigger selection register + RTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Falling Trigger selection register + FTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Software interrupt event register + SWIER: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Pending register + PR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), }; + }; - pub const LPMS = enum(u1) { - /// Keeps Stop mode when entering DeepSleep. - Stop = 0x0, - /// Allows Standby mode when entering DeepSleep. - Standby = 0x1, + pub const exti_w = struct { + /// CPU-specific registers + pub const CPU = extern struct { + /// CPU x interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// CPU x event mask register + EMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), }; - pub const PLS = enum(u3) { - /// PVD level0 (VPVD0 ~ 1.95 V) - Level0 = 0x0, - /// PVD level1 (VPVD1 ~ 2.10 V) - Level1 = 0x1, - /// PVD level2 (VPVD2 ~ 2.25 V) - Level2 = 0x2, - /// PVD level3 (VPVD3 ~ 2.40 V) - Level3 = 0x3, - /// PVD level4 (VPVD4 ~ 2.55 V) - Level4 = 0x4, - /// PVD level5 (VPVD5 ~ 2.70 V) - Level5 = 0x5, - /// PVD level6 (VPVD6 ~ 2.85 V) - Level6 = 0x6, - /// PVD_IN pin - PVDInPin = 0x7, + /// External interrupt/event controller + pub const EXTI = extern struct { + /// rising trigger selection register + RTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// falling trigger selection register + FTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// software interrupt event register + SWIER: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// EXTI pending register + PR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + reserved128: [112]u8, + /// CPU specific registers + CPU: u32, }; + }; - pub const PowerModeInStopMode = enum(u1) { - /// Remains in normal mode when the system enters Stop mode (quick restart time). - Normal = 0x0, - /// Enters low-power mode when the system enters Stop mode (low-power consumption). - LowPower = 0x1, + pub const exti_wle = struct { + /// External interrupt/event controller + pub const EXTI = extern struct { + /// Rising Trigger selection register + RTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Falling Trigger selection register + FTSR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Software interrupt event register + SWIER: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Pending register + PR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + reserved128: [112]u8, + /// Interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), + /// Event mask register + EMR: mmio.Mmio(packed struct(u32) { + /// EXTI line + LINE: u1, + padding: u31, + }), }; + }; - pub const Retention = enum(u1) { - /// Content is lost. - Lost = 0x0, - /// Content is preserved. - Preserved = 0x1, + pub const fdcanram_h7 = struct { + /// FDCAN Message RAM + pub const FDCANRAM = extern struct { + /// FDCAN Message RAM + RAM: [2560]u32, }; + }; - pub const SVOS = enum(u2) { - /// SVOS5 scale 5 - Scale5 = 0x1, - /// SVOS4 scale 4 - Scale4 = 0x2, - /// SVOS3 scale 3 (default) - Scale3 = 0x3, - _, + pub const fdcanram_v1 = struct { + /// FDCAN Message RAM + pub const FDCANRAM = extern struct { + /// 11-bit filter + FLSSA: [28]u32, + /// 29-bit filter + FLESA: [16]u32, + /// Rx FIFO 0 + RXFIFO0: [54]u32, + /// Rx FIFO 1 + RXFIFO1: [54]u32, + /// Tx event FIFO + TXEFIFO: [6]u32, + /// Tx buffer + TXBUF: [54]u32, }; + }; - pub const ShutOff = enum(u1) { - /// Content is kept. - Kept = 0x0, - /// Content is lost. - Lost = 0x1, + pub const flash_c0 = struct { + pub const BORF_LEV = enum(u2) { + /// BOR falling level 1 with threshold around 2.0V + FALLING_0 = 0x0, + /// BOR falling level 2 with threshold around 2.2V + FALLING_1 = 0x1, + /// BOR falling level 3 with threshold around 2.5V + FALLING_2 = 0x2, + /// BOR falling level 4 with threshold around 2.8V + FALLING_3 = 0x3, }; - pub const VBRS = enum(u1) { - /// Charge VBAT through a 5 kΩ resistor. - R5kOhm = 0x0, - /// Charge VBAT through a 1.5 kΩ resistor. - R1_5kOhm = 0x1, + pub const BORR_LEV = enum(u2) { + /// BOR rising level 1 with threshold around 2.1V + RISING_0 = 0x0, + /// BOR rising level 2 with threshold around 2.3V + RISING_1 = 0x1, + /// BOR rising level 3 with threshold around 2.6V + RISING_2 = 0x2, + /// BOR rising level 4 with threshold around 2.9V + RISING_3 = 0x3, }; - pub const VOS = enum(u2) { - Scale3 = 0x0, - Scale2 = 0x1, - Scale1 = 0x2, - Scale0 = 0x3, + pub const LATENCY = enum(u3) { + /// Zero wait states + WS0 = 0x0, + /// One wait state + WS1 = 0x1, + _, }; - pub const WUPP = enum(u1) { - /// detection on high level (rising edge) - High = 0x0, - /// detection on low level (falling edge) - Low = 0x1, + pub const NRST_MODE = enum(u2) { + /// Reset pin is in reset input mode only + INPUT_ONLY = 0x1, + /// Reset pin is in GPIO mode only + GPIO = 0x2, + /// Reset pin is in resety input and output mode + INPUT_OUTPUT = 0x3, + _, }; - pub const WUPPUPD = enum(u2) { - NoPullUp = 0x0, - PullUp = 0x1, - PullDown = 0x2, + pub const RDP = enum(u8) { + /// Read protection not active + LEVEL_0 = 0xaa, + /// Memories read protection active + LEVEL_1 = 0xbb, + /// Chip read protection active + LEVEL_2 = 0xcc, _, }; - /// Power control. - pub const PWR = extern struct { - /// PWR power mode control register. - PMCR: mmio.Mmio(packed struct(u32) { - /// low-power mode selection This bit defines the Deepsleep mode. - LPMS: packed union { - raw: u1, - value: LPMS, - }, - reserved2: u1, - /// system Stop mode voltage scaling selection These bits control the V_CORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. - SVOS: packed union { - raw: u2, - value: SVOS, - }, - reserved7: u3, - /// clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware. - CSSF: u1, - reserved9: u1, - /// Flash memory low-power mode in Stop mode This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode. Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode. - FLPS: packed union { - raw: u1, - value: PowerModeInStopMode, - }, - reserved12: u2, - /// analog switch V_BOOST control This bit enables the booster to guarantee the analog switch AC performance when the V_DD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V_DD supply voltage can be monitored through the PVD and the PLS bits. - BOOSTE: u1, - /// analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected V_DDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored. (ALS bits). - AVD_READY: u1, - reserved16: u2, - /// ETHERNET RAM shut-off in Stop mode. - ETHERNETSO: packed union { - raw: u1, - value: ShutOff, - }, - reserved23: u6, - /// AHB SRAM3 shut-off in Stop mode. - SRAM3SO: packed union { - raw: u1, - value: ShutOff, - }, - /// AHB SRAM2 16-Kbyte shut-off in Stop mode. - SRAM2_16SO: packed union { - raw: u1, - value: ShutOff, - }, - /// AHB SRAM2 48-Kbyte shut-off in Stop mode. - SRAM2_48SO: packed union { - raw: u1, - value: ShutOff, + /// Flash + pub const FLASH = extern struct { + /// Access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: packed union { + raw: u3, + value: LATENCY, }, - /// AHB SRAM1 shut-off in Stop mode. - SRAM1SO: packed union { - raw: u1, - value: ShutOff, - }, - padding: u5, - }), - /// PWR status register. - PMSR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// Stop flag This bit is set by hardware and cleared only by any reset or by setting the CSSF bit. - STOPF: u1, - /// System standby flag This bit is set by hardware and cleared only by a POR or by setting the CSSF bit. - SBF: u1, - padding: u25, + reserved8: u5, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + reserved11: u1, + /// Instruction cache reset + ICRST: u1, + reserved16: u4, + /// Flash User area empty + EMPTY: u1, + reserved18: u1, + /// Debug access software enable + DBG_SWEN: u1, + padding: u13, }), - reserved16: [8]u8, - /// PWR voltage scaling control register. - VOSCR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// voltage scaling selection according to performance These bits control the V_CORE voltage level and allow to obtain the best trade-off between power consumption and performance: - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance. - When increasing the performance, the voltage scaling must be changed before increasing the system frequency. - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling. - VOS: packed union { - raw: u2, - value: VOS, - }, - padding: u26, + reserved8: [4]u8, + /// Flash key register + KEYR: u32, + /// Option byte key register + OPTKEYR: u32, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved3: u1, + /// Programming error + PROGERR: u1, + /// Write protected error + WRPERR: u1, + /// Programming alignment error + PGAERR: u1, + /// Size error + SIZERR: u1, + /// Programming sequence error + PGSERR: u1, + /// Fast programming data miss error + MISERR: u1, + /// Fast programming error + FASTERR: u1, + reserved14: u4, + /// PCROP read error + RDERR: u1, + /// Option and Engineering bits loading validity error + OPTVERR: u1, + /// Busy + BSY: u1, + reserved18: u1, + /// Programming or erase configuration busy. + CFGBSY: u1, + padding: u13, }), - /// PWR voltage scaling status register. - VOSSR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Ready bit for V_CORE voltage scaling output selection. - VOSRDY: u1, - reserved13: u9, - /// Voltage level ready for currently used VOS. - ACTVOSRDY: u1, - /// voltage output scaling currently applied to V_CORE This field provides the last VOS value. - ACTVOS: packed union { - raw: u2, - value: VOS, - }, - padding: u16, + /// Flash control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Page erase + PER: u1, + /// Mass erase + MER: u1, + /// Page number + PNB: u4, + reserved16: u9, + /// Start + STRT: u1, + /// Options modification start + OPTSTRT: u1, + /// Fast programming + FSTPG: u1, + reserved24: u5, + /// End of operation interrupt enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + /// PCROP read error interrupt enable + RDERRIE: u1, + /// Force the option byte loading + OBL_LAUNCH: u1, + /// Securable memory area protection enable + SEC_PROT: u1, + reserved30: u1, + /// Options Lock + OPTLOCK: u1, + /// FLASH_CR Lock + LOCK: u1, }), reserved32: [8]u8, - /// PWR Backup domain control register. - BDCR: mmio.Mmio(packed struct(u32) { - /// Backup RAM retention in Standby and V_BAT modes When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and V_BAT modes) is enabled. If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in. Run and Stop modes. However its content is lost in Standby and V_BAT modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and V_BAT modes. - BREN: packed union { - raw: u1, - value: Retention, - }, - /// Backup domain voltage and temperature monitoring enable. - MONEN: u1, - reserved8: u6, - /// V_BAT charging enable Note: Reset only by POR,. - VBE: u1, - /// V_BAT charging resistor selection. - VBRS: packed union { - raw: u1, - value: VBRS, + /// Flash option register + OPTR: mmio.Mmio(packed struct(u32) { + /// Read protection level + RDP: packed union { + raw: u8, + value: RDP, }, - padding: u22, - }), - /// PWR Backup domain control register. - DBPCR: mmio.Mmio(packed struct(u32) { - /// Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write. access. This bit must be set to enable write access to these registers. - DBP: u1, - padding: u31, - }), - /// PWR Backup domain status register. - BDSR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready. - BRRDY: u1, - reserved20: u3, - /// V_BAT level monitoring versus low threshold. - VBATL: u1, - /// V_BAT level monitoring versus high threshold. - VBATH: u1, - /// temperature level monitoring versus low threshold. - TEMPL: u1, - /// temperature level monitoring versus high threshold. - TEMPH: u1, - padding: u8, - }), - /// PWR USB Type-C power delivery register. - UCPDR: mmio.Mmio(packed struct(u32) { - /// USB Type-C and power delivery dead battery disable After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all case, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable). - UCPD_DBDIS: u1, - /// USB Type-c and Power delivery Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD, and it must be written to 0 after exiting the standby mode and before writing any UCPD register. - UCPD_STBY: u1, - padding: u30, - }), - /// PWR supply configuration control register. - SCCR: mmio.Mmio(packed struct(u32) { - /// power management unit bypass. - BYPASS: u1, - reserved8: u7, - /// LDO enable The value is set by hardware when the package uses the LDO regulator. - LDOEN: u1, - /// SMPS enable The value is set by hardware when the package uses the SMPS regulator. - SMPSEN: u1, - padding: u22, - }), - /// PWR voltage monitor control register. - VMCR: mmio.Mmio(packed struct(u32) { - /// PVD enable. - PVDE: u1, - /// programmable voltage detector (PVD) level selection These bits select the voltage threshold detected by the PVD. - PLS: packed union { - raw: u3, - value: PLS, + /// BOR reset Level + BOREN: u1, + /// These bits contain the VDD supply level threshold that activates the reset + BORF_LEV: packed union { + raw: u2, + value: BORF_LEV, }, - reserved8: u4, - /// peripheral voltage monitor on V_DDA enable. - AVDEN: u1, - /// analog voltage detector (AVD) level selection These bits select the voltage threshold detected by the AVD. - ALS: packed union { + /// These bits contain the VDD supply level threshold that releases the reset. + BORR_LEV: packed union { raw: u2, - value: ALS, + value: BORR_LEV, }, - padding: u21, - }), - /// PWR USB supply control register. - USBSCR: mmio.Mmio(packed struct(u32) { - reserved24: u24, - /// V_DDUSB voltage level detector enable. - USB33DEN: u1, - /// independent USB supply valid This bit is used to validate the V_DDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USBFS peripheral. If V_DDUSB is not always present in the application, the V_DDUSB voltage monitor can be used to determine whether this supply is ready or not. - USB33SV: u1, - padding: u6, - }), - /// PWR voltage monitor status register. - VMSR: mmio.Mmio(packed struct(u32) { - reserved19: u19, - /// analog voltage detector output on V_DDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set. - AVDO: u1, - /// voltage detector output on V_DDIO2 This bit is set and cleared by hardware. - VDDIO2RDY: u1, - reserved22: u1, - /// programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. - PVDO: u1, + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + /// nRSTS_HDW + nRSTS_HDW: u1, + /// Independent watchdog selection + IDWG_SW: u1, + /// Independent watchdog counter freeze in Stop mode + IWDG_STOP: u1, + /// Independent watchdog counter freeze in Standby mode + IWDG_STDBY: u1, + /// Window watchdog selection + WWDG_SW: u1, + reserved22: u2, + /// SRAM parity check control + RAM_PARITY_CHECK: u1, reserved24: u1, - /// V_DDUSB ready. - USB33RDY: u1, - padding: u7, - }), - /// PWR wakeup status clear register. - WUSCR: mmio.Mmio(packed struct(u32) { - /// clear wakeup pin flag for WUFx These bits are always read as 0. - CWUF: u1, - padding: u31, - }), - /// PWR wakeup status register. - WUSR: mmio.Mmio(packed struct(u32) { - /// wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. - WUF: u1, - padding: u31, - }), - /// PWR wakeup configuration register. - WUCR: mmio.Mmio(packed struct(u32) { - /// enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. - WUPEN: u1, - reserved8: u7, - /// wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. - WUPP: packed union { - raw: u1, - value: WUPP, - }, - reserved16: u7, - /// wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. - WUPPUPD: packed union { + /// nBOOT_SEL + nBOOT_SEL: u1, + /// Boot configuration + nBOOT1: u1, + /// nBOOT0 option bit + nBOOT0: u1, + /// NRST_MODE + NRST_MODE: packed union { raw: u2, - value: WUPPUPD, + value: NRST_MODE, }, - padding: u14, - }), - reserved80: [4]u8, - /// PWR I/O retention register. - IORETR: mmio.Mmio(packed struct(u32) { - /// IO retention enable: When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register. - IORETEN: u1, - reserved16: u15, - /// IO retention enable for JTAG IOs when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. - JTAGIORETEN: u1, - padding: u15, - }), - reserved256: [172]u8, - /// PWR security configuration register. - SECCFGR: mmio.Mmio(packed struct(u32) { - /// WUPx secure protection. - WUPSEC: u1, - reserved11: u10, - /// retention secure protection. - RETSEC: u1, - /// low-power modes secure protection. - LPMSEC: u1, - /// supply configuration and monitoring secure protection. - SCMSEC: u1, - /// backup domain secure protection. - VBSEC: u1, - /// voltage USB secure protection. - VUSBSEC: u1, - padding: u16, - }), - /// PWR privilege configuration register. - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// PWR secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access. - SPRIV: u1, - /// PWR non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure. - NSPRIV: u1, - padding: u30, - }), - }; - }; - - pub const dbgmcu_f4 = struct { - /// Debug support - pub const DBGMCU = extern struct { - /// IDCODE - IDCODE: mmio.Mmio(packed struct(u32) { - /// DEV_ID - DEV_ID: u12, - reserved16: u4, - /// REV_ID - REV_ID: u16, - }), - /// Control Register - CR: mmio.Mmio(packed struct(u32) { - /// DBG_SLEEP - DBG_SLEEP: u1, - /// DBG_STOP - DBG_STOP: u1, - /// DBG_STANDBY - DBG_STANDBY: u1, - reserved5: u2, - /// TRACE_IOEN - TRACE_IOEN: u1, - /// TRACE_MODE - TRACE_MODE: u2, - padding: u24, - }), - /// Debug MCU APB1 Freeze registe - APB1FZR: mmio.Mmio(packed struct(u32) { - /// TIM2 - TIM2: u1, - /// TIM3 - TIM3: u1, - /// TIM4 - TIM4: u1, - /// TIM5 - TIM5: u1, - /// TIM6 - TIM6: u1, - /// TIM7 - TIM7: u1, - /// TIM12 - TIM12: u1, - /// TIM13 - TIM13: u1, - /// TIM14 - TIM14: u1, - reserved10: u1, - /// RTC stopped when Core is halted - RTC: u1, - /// WWDG - WWDG: u1, - /// IWDEG - IWDG: u1, - reserved21: u8, - /// I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT: u1, - /// I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT: u1, - /// I2C3SMBUS_TIMEOUT - I2C3_SMBUS_TIMEOUT: u1, - /// SMBUS timeout mode stopped when Core is halted - I2CFMP_SMBUS_TIMEOUT: u1, - /// CAN1 - CAN1: u1, - /// CAN2 - CAN2: u1, - padding: u5, - }), - /// Debug MCU APB2 Freeze registe - APB2FZR: mmio.Mmio(packed struct(u32) { - /// TIM1 counter stopped when core is halted - TIM1: u1, - /// TIM8 counter stopped when core is halted - TIM8: u1, - reserved16: u14, - /// TIM9 counter stopped when core is halted - TIM9: u1, - /// TIM10 counter stopped when core is halted - TIM10: u1, - /// TIM11 counter stopped when core is halted - TIM11: u1, - padding: u13, + /// Internal reset holder enable bit + IRHEN: u1, + padding: u2, }), - }; - }; - - pub const tamp_g4 = struct { - /// Tamper and backup registers - pub const TAMP = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Tamper detection on IN X enable - TAMPE: u1, - reserved16: u15, - /// Internal tamper X enable - ITAMPE: u1, - padding: u15, + /// Flash PCROP zone A Start address register + PCROP1ASR: mmio.Mmio(packed struct(u32) { + /// PCROP1A area start offset + PCROP1A_STRT: u6, + padding: u26, }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Tamper X no erase - TAMPNOER: u1, - reserved16: u15, - /// Tamper X mask. - TAMPMSK: u1, - reserved24: u7, - /// Active level for tamper X input. - TAMPTRG: u1, - padding: u7, + /// Flash PCROP zone A End address register + PCROP1AER: mmio.Mmio(packed struct(u32) { + /// PCROP1A area end offset + PCROP1A_END: u6, + reserved31: u25, + /// PCROP area preserved when RDP level decreased + PCROP_RDP: u1, }), - reserved12: [4]u8, - /// TAMP filter control register - FLTCR: mmio.Mmio(packed struct(u32) { - /// Tamper sampling frequency. Determines the frequency at which each of the INx inputs are sampled. - TAMPFREQ: u3, - /// INx filter count. These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the INx inputs. - TAMPFLT: u2, - /// INx precharge duration. These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the INx inputs. - TAMPPRCH: u2, - /// INx pull-up disable. This bit determines if each of the TAMPx pins are precharged before each sample. - TAMPPUDIS: u1, - padding: u24, + /// Flash WRP area A address register + WRP1AR: mmio.Mmio(packed struct(u32) { + /// WRP area A start offset + WRP1A_STRT: u6, + reserved16: u10, + /// WRP area A end offset + WRP1A_END: u6, + padding: u10, }), - reserved44: [28]u8, - /// TAMP interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt enable - TAMPIE: u1, - reserved16: u15, - /// Internal tamper X interrupt enable - ITAMPIE: u1, - padding: u15, + /// Flash WRP area B address register + WRP1BR: mmio.Mmio(packed struct(u32) { + /// WRP area B start offset + WRP1B_STRT: u6, + reserved16: u10, + /// WRP area B end offset + WRP1B_END: u6, + padding: u10, }), - /// TAMP status register - SR: mmio.Mmio(packed struct(u32) { - /// Tamper X detection flag - TAMPF: u1, - reserved16: u15, - /// Internal tamper X detection flag - ITAMPF: u1, - padding: u15, + /// Flash PCROP zone B Start address register + PCROP1BSR: mmio.Mmio(packed struct(u32) { + /// PCROP1B area start offset + PCROP1B_STRT: u6, + padding: u26, }), - /// TAMP masked interrupt status register - MISR: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt masked flag - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X interrupt masked flag - ITAMPMF: u1, - padding: u15, + /// Flash PCROP zone B End address register + PCROP1BER: mmio.Mmio(packed struct(u32) { + /// PCROP1B area end offset + PCROP1B_END: u6, + padding: u26, }), - reserved60: [4]u8, - /// TAMP status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear tamper X detection flag - CTAMPF: u1, - reserved16: u15, - /// Clear internal tamper X detection flag - CITAMPF: u1, + reserved128: [68]u8, + /// Flash Security register + SECR: mmio.Mmio(packed struct(u32) { + /// Securable memory area size + SEC_SIZE: u5, + reserved16: u11, + /// used to force boot from user area + BOOT_LOCK: u1, padding: u15, }), - reserved256: [192]u8, - /// TAMP backup register - BKPR: [32]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, - }), }; }; - pub const lpdma_v1 = struct { - pub const BREQ = enum(u1) { - /// the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. - Burst = 0x0, - /// the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ). - Block = 0x1, - }; - - pub const DEC = enum(u1) { - /// The address is incremented by the programmed offset. - Add = 0x0, - /// The address is decremented by the programmed offset. - Subtract = 0x1, - }; - - pub const DREQ = enum(u1) { - /// selected hardware request driven by a source peripheral (request signal taken into account by the LPDMA transfer scheduler over the source/read port) - SourcePeripheral = 0x0, - /// selected hardware request driven by a destination peripheral (request signal taken into account by the LPDMA transfer scheduler over the destination/write port) - DestinationPeripheral = 0x1, + pub const flash_f0 = struct { + pub const BOOT_SEL = enum(u1) { + /// BOOT0 signal is defined by nBOOT0 option bit + nBOOT0 = 0x0, + /// BOOT0 signal is defined by BOOT0 pin value (legacy mode) + BOOT0 = 0x1, }; - pub const DW = enum(u2) { - /// byte - Byte = 0x0, - /// half-word (2 bytes) - HalfWord = 0x1, - /// word (4 bytes) - Word = 0x2, + pub const LATENCY = enum(u3) { + /// 0 wait states + WS0 = 0x0, + /// 1 wait state + WS1 = 0x1, _, }; - pub const LSM = enum(u1) { - /// channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. - RunToCompletion = 0x0, - /// channel executed once for the current LLI - LinkStep = 0x1, + pub const RAM_PARITY_CHECK = enum(u1) { + /// RAM parity check enabled + Enabled = 0x0, + /// RAM parity check disabled + Disabled = 0x1, }; - pub const PAM = enum(u2) { - /// If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width If source is wider: source data is transferred as right aligned, left-truncated down to the destination data width - ZeroExtendOrLeftTruncate = 0x0, - /// If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width If source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width - SignExtendOrRightTruncate = 0x1, - /// source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination - Pack = 0x2, + pub const RDPRT = enum(u2) { + /// Level 0 + Level0 = 0x0, + /// Level 1 + Level1 = 0x1, + /// Level 2 + Level2 = 0x3, _, }; - pub const PRIO = enum(u2) { - /// low priority, low weight - LowWithLowhWeight = 0x0, - /// low priority, mid weight - LowWithMidWeight = 0x1, - /// low priority, high weight - LowWithHighWeight = 0x2, - /// high priority - High = 0x3, - }; - - pub const SWREQ = enum(u1) { - /// no software request. The selected hardware request REQSEL[6:0] is taken into account. + pub const WDG_SW = enum(u1) { + /// Hardware watchdog Hardware = 0x0, - /// software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored. + /// Software watchdog Software = 0x1, }; - pub const TCEM = enum(u2) { - /// at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. - EachBlock = 0x0, - /// channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block. - Each2DBlock = 0x1, - /// at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer. - EachLinkedListItem = 0x2, - /// at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated. - LastLinkedListItem = 0x3, - }; - - pub const TRIGM = enum(u2) { - /// at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0). - Block = 0x0, - /// channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the - @"2DBlock" = 0x1, - /// at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned. - LinkedListItem = 0x2, - /// at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger. - Burst = 0x3, + pub const nRST_STDBY = enum(u1) { + /// Reset generated when entering Standby mode + Reset = 0x0, + /// No reset generated + NoReset = 0x1, }; - pub const TRIGPOL = enum(u2) { - /// no trigger (masked trigger event) - None = 0x0, - /// trigger on the rising edge - RisingEdge = 0x1, - /// trigger on the falling edge - FallingEdge = 0x2, - /// same as 00 - NoneAlt = 0x3, + pub const nRST_STOP = enum(u1) { + /// Reset generated when entering Stop mode + Reset = 0x0, + /// No reset generated + NoReset = 0x1, }; - pub const Channel = extern struct { - /// LPDMA channel 15 linked-list base address register - LBAR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// linked-list base address of LPDMA channel x - LBA: u16, - }), - reserved12: [8]u8, - /// LPDMA channel 15 flag clear register - FCR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// transfer complete flag clear - TCF: u1, - /// half transfer flag clear - HTF: u1, - /// data transfer error flag clear - DTEF: u1, - /// update link transfer error flag clear - ULEF: u1, - /// user setting error flag clear - USEF: u1, - /// completed suspension flag clear - SUSPF: u1, - /// trigger overrun flag clear - TOF: u1, - padding: u17, + /// Flash + pub const FLASH = extern struct { + /// Flash access control register + ACR: mmio.Mmio(packed struct(u32) { + /// LATENCY + LATENCY: packed union { + raw: u3, + value: LATENCY, + }, + reserved4: u1, + /// Prefetch buffer enable + PRFTBE: u1, + /// Prefetch buffer status + PRFTBS: u1, + padding: u26, }), - /// LPDMA channel 15 status register + /// Flash key register + KEYR: u32, + /// Flash option key register + OPTKEYR: u32, + /// Flash status register SR: mmio.Mmio(packed struct(u32) { - /// idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state). - IDLEF: u1, - reserved8: u7, - /// transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). - TCF: u1, - /// half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination. - HTF: u1, - /// data transfer error flag - DTEF: u1, - /// update link transfer error flag - ULEF: u1, - /// user setting error flag - USEF: u1, - /// completed suspension flag - SUSPF: u1, - /// trigger overrun flag - TOF: u1, - padding: u17, + /// Busy + BSY: u1, + reserved2: u1, + /// Programming error + PGERR: u1, + reserved4: u1, + /// Write protection error + WRPRT: u1, + /// End of operation + EOP: u1, + padding: u26, }), - /// LPDMA channel 15 control register + /// Flash control register CR: mmio.Mmio(packed struct(u32) { - /// enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. - EN: u1, - /// reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in ). - RESET: u1, - /// suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going LPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in . - SUSP: u1, - reserved8: u5, - /// transfer complete interrupt enable - TCIE: u1, - /// half transfer complete interrupt enable - HTIE: u1, - /// data transfer error interrupt enable - DTEIE: u1, - /// update link transfer error interrupt enable - ULEIE: u1, - /// user setting error interrupt enable - USEIE: u1, - /// completed suspension interrupt enable - SUSPIE: u1, - /// trigger overrun interrupt enable - TOIE: u1, - reserved16: u1, - /// Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1. - LSM: packed union { - raw: u1, - value: LSM, - }, - reserved22: u5, - /// priority level of the channel x LPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. - PRIO: packed union { - raw: u2, - value: PRIO, - }, - padding: u8, + /// Programming + PG: u1, + /// Page erase + PER: u1, + /// Mass erase + MER: u1, + reserved4: u1, + /// Option byte programming + OPTPG: u1, + /// Option byte erase + OPTER: u1, + /// Start + STRT: u1, + /// Lock + LOCK: u1, + reserved9: u1, + /// Option bytes write enable + OPTWRE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved12: u1, + /// End of operation interrupt enable + EOPIE: u1, + /// Force option byte loading + FORCE_OPTLOAD: u1, + padding: u18, }), - reserved64: [40]u8, - /// LPDMA channel 15 transfer register 1 - TR1: mmio.Mmio(packed struct(u32) { - /// binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued. - SDW: packed union { - raw: u2, - value: DW, - }, - reserved3: u1, - /// source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. - SINC: u1, - reserved11: u7, - /// padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note: - PAM: packed union { - raw: u2, - value: PAM, - }, - reserved15: u2, - /// security attribute of the LPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure. - SSEC: u1, - /// binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued. - DDW: packed union { - raw: u2, - value: DW, - }, - reserved19: u1, - /// destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. - DINC: u1, - reserved31: u11, - /// security attribute of the LPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure. - DSEC: u1, + /// Flash address register + AR: mmio.Mmio(packed struct(u32) { + /// Flash address + FAR: u32, }), - /// LPDMA channel 15 transfer register 2 - TR2: mmio.Mmio(packed struct(u32) { - /// LPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active LPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). LPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. - REQSEL: u7, - reserved9: u2, - /// software request. This bit is internally taken into account when CH[x].CR.EN is asserted. - SWREQ: packed union { - raw: u1, - value: SWREQ, - }, - /// destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note: - DREQ: packed union { - raw: u1, - value: DREQ, - }, - /// Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: - BREQ: packed union { - raw: u1, - value: BREQ, - }, - reserved14: u2, - /// trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a LPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger. - TRIGM: packed union { - raw: u2, - value: TRIGM, - }, - /// trigger event input selection. These bits select the trigger event input of the LPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00. - TRIGSEL: u6, - reserved24: u2, - /// trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - TRIGPOL: packed union { + reserved28: [4]u8, + /// Option byte register + OBR: mmio.Mmio(packed struct(u32) { + /// Option byte error + OPTERR: u1, + /// Read protection level status + RDPRT: packed union { raw: u2, - value: TRIGPOL, + value: RDPRT, }, - reserved30: u4, - /// transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - TCEM: packed union { - raw: u2, - value: TCEM, + reserved8: u5, + /// WDG_SW + WDG_SW: packed union { + raw: u1, + value: WDG_SW, }, - }), - /// LPDMA channel 15 alternate block register 1 - BR1: mmio.Mmio(packed struct(u32) { - /// block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued. - BNDT: u16, - /// Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer. - BRC: u11, - reserved28: u1, - /// source address decrement - SDEC: packed union { + /// nRST_STOP + nRST_STOP: packed union { raw: u1, - value: DEC, + value: nRST_STOP, }, - /// destination address decrement - DDEC: packed union { + /// nRST_STDBY + nRST_STDBY: packed union { raw: u1, - value: DEC, + value: nRST_STDBY, }, - /// Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer. - BRSDEC: packed union { + /// nBOOT0 + nBOOT0: u1, + /// BOOT1 + nBOOT1: u1, + /// VDDA power supply supervisor enabled + VDDA_MONITOR: u1, + /// RAM_PARITY_CHECK + RAM_PARITY_CHECK: packed union { raw: u1, - value: DEC, + value: RAM_PARITY_CHECK, }, - /// Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer. - BRDDEC: packed union { + /// BOOT_SEL + BOOT_SEL: packed union { raw: u1, - value: DEC, + value: BOOT_SEL, }, + /// Data0 + Data0: u8, + /// Data1 + Data1: u8, }), - /// LPDMA channel 15 source address register - SAR: u32, - /// LPDMA channel 15 destination address register - DAR: u32, - /// LPDMA channel 15 transfer register 3 - TR3: mmio.Mmio(packed struct(u32) { - /// source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied. - SAO: u13, - reserved16: u3, - /// destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued. - DAO: u13, - padding: u3, - }), - /// LPDMA channel 15 block register 2 - BR2: mmio.Mmio(packed struct(u32) { - /// Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. - BRSAO: u16, - /// Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued. - BRDAO: u16, - }), - reserved124: [32]u8, - /// LPDMA channel 15 alternate linked-list address register - LLR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list LPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list LPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. - LA: u14, - /// Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer. - ULL: u1, - reserved25: u8, - /// Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer. - UB2: u1, - /// Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer. - UT3: u1, - /// Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer. - UDA: u1, - /// update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer. - USA: u1, - /// Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. - UB1: u1, - /// Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer. - UT2: u1, - /// Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer. - UT1: u1, - }), - }; - - /// LPDMA - pub const LPDMA = extern struct { - /// LPDMA secure configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// SEC0 - SEC: u1, - padding: u31, - }), - /// LPDMA privileged configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// PRIV0 - PRIV: u1, - padding: u31, - }), - /// LPDMA configuration lock register - RCFGLOCKR: mmio.Mmio(packed struct(u32) { - /// LOCK0 - LOCK: u1, - padding: u31, - }), - /// LPDMA non-secure masked interrupt status register - MISR: mmio.Mmio(packed struct(u32) { - /// MIS0 - MIS: u1, - padding: u31, - }), - /// LPDMA secure masked interrupt status register - SMISR: mmio.Mmio(packed struct(u32) { - /// MIS0 - MIS: u1, - padding: u31, + /// Write protection register + WRPR: mmio.Mmio(packed struct(u32) { + /// Write protect + WRP: u32, }), - reserved80: [60]u8, - CH: u32, }; }; - pub const dac_v2 = struct { - pub const WAVE = enum(u2) { - /// Wave generation disabled - Disabled = 0x0, - /// Noise wave generation enabled - Noise = 0x1, - /// Triangle wave generation enabled - Triangle = 0x2, + pub const flash_f1 = struct { + pub const LATENCY = enum(u3) { + /// Zero wait state, if 0 < SYSCLK≤ 24 MHz + WS0 = 0x0, + /// One wait state, if 24 MHz < SYSCLK ≤ 48 MHz + WS1 = 0x1, + /// Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz + WS2 = 0x2, _, }; - /// Digital-to-analog converter - pub const DAC = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, - /// channel output buffer disable - BOFF: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u3, - /// channel noise/triangle wave generation enable - WAVE: packed union { - raw: u2, - value: WAVE, + /// FLASH + pub const FLASH = extern struct { + /// Flash access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: packed union { + raw: u3, + value: LATENCY, }, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - /// channel DMA Underrun Interrupt enable - DMAUDRIE: u1, - padding: u18, - }), - /// software trigger register - SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - padding: u31, - }), - /// channel 12-bit right-aligned data holding register - DHR12R: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, - }), - /// channel 12-bit left-aligned data holding register - DHR12L: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, - }), - /// channel 8-bit right-aligned data holding register - DHR8R: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// Flash half cycle access enable + HLFCYA: u1, + /// Prefetch buffer enable + PRFTBE: u1, + /// Prefetch buffer status + PRFTBS: u1, + padding: u26, }), - reserved32: [12]u8, - /// dual 12-bit right-aligned data holding register - DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// Flash key register + KEYR: u32, + /// Flash option key register + OPTKEYR: u32, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Busy + BSY: u1, + reserved2: u1, + /// Programming error + PGERR: u1, + reserved4: u1, + /// Write protection error + WRPRTERR: u1, + /// End of operation + EOP: u1, + padding: u26, }), - /// dual 12-bit left aligned data holding register - DHR12LD: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Page Erase + PER: u1, + /// Mass Erase + MER: u1, + reserved4: u1, + /// Option byte programming + OPTPG: u1, + /// Option byte erase + OPTER: u1, + /// Start + STRT: u1, + /// Lock + LOCK: u1, + reserved9: u1, + /// Option bytes write enable + OPTWRE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved12: u1, + /// End of operation interrupt enable + EOPIE: u1, + padding: u19, }), - /// dual 8-bit right aligned data holding register - DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// Flash address register + AR: mmio.Mmio(packed struct(u32) { + /// Flash Address + FAR: u32, }), - /// channel data output register - DOR: [2]mmio.Mmio(packed struct(u32) { - /// channel data output - DOR: u12, - padding: u20, + reserved28: [4]u8, + /// Option byte register + OBR: mmio.Mmio(packed struct(u32) { + /// Option byte error + OPTERR: u1, + /// Read protection + RDPRT: u1, + /// WDG_SW + WDG_SW: u1, + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + reserved10: u5, + /// Data0 + Data0: u8, + /// Data1 + Data1: u8, + padding: u6, }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved13: u13, - /// channel DMA underrun flag - DMAUDR: u1, - padding: u18, + /// Write protection register + WRPR: mmio.Mmio(packed struct(u32) { + /// Write protect + WRP: u32, }), }; }; - pub const pka_v1a = struct { - pub const LMF = enum(u1) { - /// All values documented in MODE bitfield can be used. - All = 0x0, - /// Only ECDSA verification (MODE = 0x26) is supported by the PKA. - Limited = 0x1, + pub const flash_f2 = struct { + pub const LATENCY = enum(u3) { + /// 0 wait states + WS0 = 0x0, + /// 1 wait states + WS1 = 0x1, + /// 2 wait states + WS2 = 0x2, + /// 3 wait states + WS3 = 0x3, + /// 4 wait states + WS4 = 0x4, + /// 5 wait states + WS5 = 0x5, + /// 6 wait states + WS6 = 0x6, + /// 7 wait states + WS7 = 0x7, }; - /// Public key accelerator. - pub const PKA = extern struct { - /// PKA control register. - CR: mmio.Mmio(packed struct(u32) { - /// PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application. - EN: u1, - /// start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy. - START: u1, - reserved8: u6, - /// PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. - MODE: u6, - reserved17: u3, - /// End of operation interrupt enable. - PROCENDIE: u1, - reserved19: u1, - /// RAM error interrupt enable. - RAMERRIE: u1, - /// Address error interrupt enable. - ADDRERRIE: u1, - /// Operation error interrupt enable. - OPERRIE: u1, - padding: u10, + pub const PSIZE = enum(u2) { + /// Program x8 + PSIZE8 = 0x0, + /// Program x16 + PSIZE16 = 0x1, + /// Program x32 + PSIZE32 = 0x2, + /// Program x64 + PSIZE64 = 0x3, + }; + + /// FLASH + pub const FLASH = extern struct { + /// Flash access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: packed union { + raw: u3, + value: LATENCY, + }, + reserved8: u5, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + /// Data cache enable + DCEN: u1, + /// Instruction cache reset + ICRST: u1, + /// Data cache reset + DCRST: u1, + padding: u19, }), - /// PKA status register. + /// Flash key register + KEYR: u32, + /// Flash option key register + OPTKEYR: u32, + /// Status register SR: mmio.Mmio(packed struct(u32) { - /// PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. - INITOK: u1, - /// Limited mode flag This bit is updated when EN bit in PKA_CR is set. - LMF: packed union { - raw: u1, - value: LMF, + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved4: u2, + /// Write protection error + WRPERR: u1, + /// Programming alignment error + PGAERR: u1, + /// Programming parallelism error + PGPERR: u1, + /// Programming sequence error + PGSERR: u1, + reserved16: u8, + /// Busy + BSY: u1, + padding: u15, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Sector Erase + SER: u1, + /// Mass Erase + MER: u1, + /// Sector number + SNB: u4, + reserved8: u1, + /// Program size + PSIZE: packed union { + raw: u2, + value: PSIZE, }, - reserved16: u14, - /// PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). - BUSY: u1, - /// PKA End of Operation flag. - PROCENDF: u1, - reserved19: u1, - /// PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. - RAMERRF: u1, - /// Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. - ADDRERRF: u1, - /// Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. - OPERRF: u1, - padding: u10, + reserved16: u6, + /// Start + STRT: u1, + reserved24: u7, + /// End of operation interrupt enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved31: u5, + /// Lock + LOCK: u1, }), - /// PKA clear flag register. - CLRFR: mmio.Mmio(packed struct(u32) { - reserved17: u17, - /// Clear PKA End of Operation flag. - PROCENDFC: u1, - reserved19: u1, - /// Clear PKA RAM error flag. - RAMERRFC: u1, - /// Clear address error flag. - ADDRERRFC: u1, - /// Clear operation error flag. - OPERRFC: u1, - padding: u10, + /// Flash option control register + OPTCR: mmio.Mmio(packed struct(u32) { + /// Option lock + OPTLOCK: u1, + /// Option start + OPTSTRT: u1, + /// BOR reset Level + BOR_LEV: u2, + reserved5: u1, + /// WDG_SW User option bytes + WDG_SW: u1, + /// nRST_STOP User option bytes + nRST_STOP: u1, + /// nRST_STDBY User option bytes + nRST_STDBY: u1, + /// Read protect + RDP: u8, + /// Not write protect + nWRP: u12, + padding: u4, }), - reserved1024: [1012]u8, - /// PKA internal memeory. - RAM: [1334]u32, }; }; - pub const spi_v3 = struct { - pub const CHLEN = enum(u1) { - /// 16 bits per channel - Bits16 = 0x0, - /// 32 bits per channel - Bits32 = 0x1, - }; - - pub const CKPOL = enum(u1) { - /// CK idle Level is Low. Signals are sampled on rising and changed on falling clock edges - IdleLow = 0x0, - /// CK idle level is High. Signals are sampled on falling and changed on rising clock edges - IdleHigh = 0x1, - }; - - pub const COMM = enum(u2) { - /// Full duplex - FullDuplex = 0x0, - /// Simplex transmitter only - Transmitter = 0x1, - /// Simplex receiver only - Receiver = 0x2, - /// Half duplex - HalfDuplex = 0x3, - }; - - pub const CPHA = enum(u1) { - /// The first clock transition is the first data capture edge - FirstEdge = 0x0, - /// The second clock transition is the first data capture edge - SecondEdge = 0x1, - }; - - pub const CPOL = enum(u1) { - /// SCK to 0 when idle - IdleLow = 0x0, - /// SCK to 1 when idle - IdleHigh = 0x1, - }; - - pub const DATFMT = enum(u1) { - /// The data inside RXDR and TXDR are right aligned - RightAligned = 0x0, - /// The data inside RXDR and TXDR are left aligned - LeftAligned = 0x1, - }; - - pub const DATLEN = enum(u2) { - /// 16-bit data length - Bits16 = 0x0, - /// 24-bit data length - Bits24 = 0x1, - /// 32-bit data length - Bits32 = 0x2, + pub const flash_f3 = struct { + pub const LATENCY = enum(u3) { + /// 0 wait states, if 0 < HCLK <= 24 MHz + WS0 = 0x0, + /// 1 wait state, if 24 < HCLK <= 48 MHz + WS1 = 0x1, + /// 2 wait states, if 48 < HCLK <= 72 MHz + WS2 = 0x2, _, }; - pub const FIXCH = enum(u1) { - /// The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account) - NotFixed = 0x0, - /// The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN) - Fixed = 0x1, + pub const RDPRT = enum(u2) { + /// Level 0 + Level0 = 0x0, + /// Level 1 + Level1 = 0x1, + /// Level 2 + Level2 = 0x3, + _, }; - pub const FTHLV = enum(u4) { - /// 1 frame - OneFrame = 0x0, - /// 2 frames - TwoFrames = 0x1, - /// 3 frames - ThreeFrames = 0x2, - /// 4 frames - FourFrames = 0x3, - /// 5 frames - FiveFrames = 0x4, - /// 6 frames - SixFrames = 0x5, - /// 7 frames - SevenFrames = 0x6, - /// 8 frames - EightFrames = 0x7, - /// 9 frames - NineFrames = 0x8, - /// 10 frames - TenFrames = 0x9, - /// 11 frames - ElevenFrames = 0xa, - /// 12 frames - TwelveFrames = 0xb, - /// 13 frames - ThirteenFrames = 0xc, - /// 14 frames - FourteenFrames = 0xd, - /// 15 frames - FifteenFrames = 0xe, - /// 16 frames - SixteenFrames = 0xf, + pub const WDG_SW = enum(u1) { + /// Hardware watchdog + Hardware = 0x0, + /// Software watchdog + Software = 0x1, }; - pub const HDDIR = enum(u1) { - /// Receiver in half duplex mode - Receiver = 0x0, - /// Transmitter in half duplex mode - Transmitter = 0x1, + pub const nRST_STDBY = enum(u1) { + /// Reset generated when entering Standby mode + Reset = 0x0, + /// No reset generated + NoReset = 0x1, }; - pub const I2SCFG = enum(u3) { - /// Slave, transmit - SlaveTx = 0x0, - /// Slave, receive - SlaveRx = 0x1, - /// Master, transmit - MasterTx = 0x2, - /// Master, receive - MasterRx = 0x3, - /// Slave, full duplex - SlaveFullDuplex = 0x4, - /// Master, full duplex - MasterFullDuplex = 0x5, - _, + pub const nRST_STOP = enum(u1) { + /// Reset generated when entering Stop mode + Reset = 0x0, + /// No reset generated + NoReset = 0x1, }; - pub const I2SSTD = enum(u2) { - /// I2S Philips standard - Philips = 0x0, - /// MSB/left justified standard - MSB = 0x1, - /// LSB/right justified standard - LSB = 0x2, - /// PCM standard - PCM = 0x3, + /// Flash + pub const FLASH = extern struct { + /// Flash access control register + ACR: mmio.Mmio(packed struct(u32) { + /// LATENCY + LATENCY: packed union { + raw: u3, + value: LATENCY, + }, + /// Flash half cycle access enable + HLFCYA: u1, + /// PRFTBE + PRFTBE: u1, + /// PRFTBS + PRFTBS: u1, + padding: u26, + }), + /// Flash key register + KEYR: u32, + /// Flash option key register + OPTKEYR: u32, + /// Flash status register + SR: mmio.Mmio(packed struct(u32) { + /// Busy + BSY: u1, + reserved2: u1, + /// Programming error + PGERR: u1, + reserved4: u1, + /// Write protection error + WRPRTERR: u1, + /// End of operation + EOP: u1, + padding: u26, + }), + /// Flash control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Page erase + PER: u1, + /// Mass erase + MER: u1, + reserved4: u1, + /// Option byte programming + OPTPG: u1, + /// Option byte erase + OPTER: u1, + /// Start + STRT: u1, + /// Lock + LOCK: u1, + reserved9: u1, + /// Option bytes write enable + OPTWRE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved12: u1, + /// End of operation interrupt enable + EOPIE: u1, + /// Force option byte loading + OBL_LAUNCH: u1, + padding: u18, + }), + /// Flash address register + AR: mmio.Mmio(packed struct(u32) { + /// Flash address + FAR: u32, + }), + reserved28: [4]u8, + /// Option byte register + OBR: mmio.Mmio(packed struct(u32) { + /// Option byte error + OPTERR: u1, + /// Read protection Level status + RDPRT: packed union { + raw: u2, + value: RDPRT, + }, + reserved8: u5, + /// WDG_SW + WDG_SW: packed union { + raw: u1, + value: WDG_SW, + }, + /// nRST_STOP + nRST_STOP: packed union { + raw: u1, + value: nRST_STOP, + }, + /// nRST_STDBY + nRST_STDBY: packed union { + raw: u1, + value: nRST_STDBY, + }, + reserved12: u1, + /// BOOT1 + nBOOT1: u1, + /// VDDA_MONITOR + VDDA_MONITOR: u1, + /// SRAM_PARITY_CHECK + SRAM_PARITY_CHECK: u1, + /// SDADC12_VDD_MONITOR + SDADC12_VDD_MONITOR: u1, + /// Data0 + Data0: u8, + /// Data1 + Data1: u8, + }), + /// Write protection register + WRPR: mmio.Mmio(packed struct(u32) { + /// Write protect + WRP: u32, + }), }; + }; - pub const LSBFIRST = enum(u1) { - /// Data is transmitted/received with the MSB first - MSBFirst = 0x0, - /// Data is transmitted/received with the LSB first - LSBFirst = 0x1, + pub const flash_f4 = struct { + pub const LATENCY = enum(u4) { + /// 0 wait states + WS0 = 0x0, + /// 1 wait states + WS1 = 0x1, + /// 2 wait states + WS2 = 0x2, + /// 3 wait states + WS3 = 0x3, + /// 4 wait states + WS4 = 0x4, + /// 5 wait states + WS5 = 0x5, + /// 6 wait states + WS6 = 0x6, + /// 7 wait states + WS7 = 0x7, + /// 8 wait states + WS8 = 0x8, + /// 9 wait states + WS9 = 0x9, + /// 10 wait states + WS10 = 0xa, + /// 11 wait states + WS11 = 0xb, + /// 12 wait states + WS12 = 0xc, + /// 13 wait states + WS13 = 0xd, + /// 14 wait states + WS14 = 0xe, + /// 15 wait states + WS15 = 0xf, }; - pub const MASTER = enum(u1) { - /// Slave configuration - Slave = 0x0, - /// Master configuration - Master = 0x1, + pub const PSIZE = enum(u2) { + /// Program x8 + PSIZE8 = 0x0, + /// Program x16 + PSIZE16 = 0x1, + /// Program x32 + PSIZE32 = 0x2, + /// Program x64 + PSIZE64 = 0x3, }; - pub const MBR = enum(u3) { - /// f_spi_ker_ck / 2 - Div2 = 0x0, - /// f_spi_ker_ck / 4 - Div4 = 0x1, - /// f_spi_ker_ck / 8 - Div8 = 0x2, - /// f_spi_ker_ck / 16 - Div16 = 0x3, - /// f_spi_ker_ck / 32 - Div32 = 0x4, - /// f_spi_ker_ck / 64 - Div64 = 0x5, - /// f_spi_ker_ck / 128 - Div128 = 0x6, - /// f_spi_ker_ck / 256 - Div256 = 0x7, + /// FLASH + pub const FLASH = extern struct { + /// Flash access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: packed union { + raw: u4, + value: LATENCY, + }, + reserved8: u4, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + /// Data cache enable + DCEN: u1, + /// Instruction cache reset + ICRST: u1, + /// Data cache reset + DCRST: u1, + padding: u19, + }), + /// Flash key register + KEYR: u32, + /// Flash option key register + OPTKEYR: u32, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved4: u2, + /// Write protection error + WRPERR: u1, + /// Programming alignment error + PGAERR: u1, + /// Programming parallelism error + PGPERR: u1, + /// Programming sequence error + PGSERR: u1, + reserved16: u8, + /// Busy + BSY: u1, + padding: u15, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Sector Erase + SER: u1, + /// Mass Erase + MER: u1, + /// Sector number + SNB: u5, + /// Program size + PSIZE: packed union { + raw: u2, + value: PSIZE, + }, + reserved16: u6, + /// Start + STRT: u1, + reserved24: u7, + /// End of operation interrupt enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved31: u5, + /// Lock + LOCK: u1, + }), + /// Flash option control register + OPTCR: mmio.Mmio(packed struct(u32) { + /// Option lock + OPTLOCK: u1, + /// Option start + OPTSTRT: u1, + /// BOR reset Level + BOR_LEV: u2, + reserved5: u1, + /// WDG_SW User option bytes + WDG_SW: u1, + /// nRST_STOP User option bytes + nRST_STOP: u1, + /// nRST_STDBY User option bytes + nRST_STDBY: u1, + /// Read protect + RDP: u8, + /// Not write protect + nWRP: u12, + reserved30: u2, + /// Dual-bank enable on 1 Mbyte Flash memory devices + DB1M: u1, + /// Selection of protection mode for nWPRi bits + SPRMOD: u1, + }), }; + }; - pub const ODD = enum(u1) { - /// Real divider value is I2SDIV*2 - Even = 0x0, - /// Real divider value is I2SDIV*2 + 1 - Odd = 0x1, + pub const flash_f7 = struct { + pub const LATENCY = enum(u4) { + /// 0 wait states + WS0 = 0x0, + /// 1 wait states + WS1 = 0x1, + /// 2 wait states + WS2 = 0x2, + /// 3 wait states + WS3 = 0x3, + /// 4 wait states + WS4 = 0x4, + /// 5 wait states + WS5 = 0x5, + /// 6 wait states + WS6 = 0x6, + /// 7 wait states + WS7 = 0x7, + /// 8 wait states + WS8 = 0x8, + /// 9 wait states + WS9 = 0x9, + /// 10 wait states + WS10 = 0xa, + /// 11 wait states + WS11 = 0xb, + /// 12 wait states + WS12 = 0xc, + /// 13 wait states + WS13 = 0xd, + /// 14 wait states + WS14 = 0xe, + /// 15 wait states + WS15 = 0xf, }; - pub const PCMSYNC = enum(u1) { - /// Short PCM frame synchronization - Short = 0x0, - /// Long PCM frame synchronization - Long = 0x1, + pub const PSIZE = enum(u2) { + /// Program x8 + PSIZE8 = 0x0, + /// Program x16 + PSIZE16 = 0x1, + /// Program x32 + PSIZE32 = 0x2, + /// Program x64 + PSIZE64 = 0x3, }; - pub const RCRCINI = enum(u1) { - /// All zeros RX CRC initialization pattern - AllZeros = 0x0, - /// All ones RX CRC initialization pattern - AllOnes = 0x1, + /// FLASH + pub const FLASH = extern struct { + /// Flash access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: packed union { + raw: u4, + value: LATENCY, + }, + reserved8: u4, + /// Prefetch enable + PRFTEN: u1, + /// ART Accelerator Enable + ARTEN: u1, + reserved11: u1, + /// ART Accelerator reset + ARTRST: u1, + padding: u20, + }), + /// Flash key register + KEYR: u32, + /// Flash option key register + OPTKEYR: u32, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved4: u2, + /// Write protection error + WRPERR: u1, + /// Programming alignment error + PGAERR: u1, + /// Programming parallelism error + PGPERR: u1, + /// Erase Sequence Error + ERSERR: u1, + /// RDERR + RDERR: u1, + reserved16: u7, + /// Busy + BSY: u1, + padding: u15, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Sector Erase + SER: u1, + /// Mass Erase of sectors 0 to 11 + MER: u1, + /// Sector number + SNB: u4, + reserved8: u1, + /// Program size + PSIZE: packed union { + raw: u2, + value: PSIZE, + }, + reserved16: u6, + /// Start + STRT: u1, + reserved24: u7, + /// End of operation interrupt enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + /// PCROP error interrupt enable + RDERRIE: u1, + reserved31: u4, + /// Lock + LOCK: u1, + }), + /// Flash option control register + OPTCR: mmio.Mmio(packed struct(u32) { + /// Option lock + OPTLOCK: u1, + /// Option start + OPTSTRT: u1, + /// BOR reset Level + BOR_LEV: u2, + /// User option bytes + WWDG_SW: u1, + /// WDG_SW User option bytes + IWDG_SW: u1, + /// nRST_STOP User option bytes + nRST_STOP: u1, + /// nRST_STDBY User option bytes + nRST_STDBY: u1, + /// Read protect + RDP: u8, + /// Not write protect + nWRP: u8, + reserved28: u4, + /// Dual Boot mode (valid only when nDBANK=0) + nDBOOT: u1, + /// Not dual bank mode + nDBANK: u1, + /// Independent watchdog counter freeze in standby mode + IWDG_STDBY: u1, + /// Independent watchdog counter freeze in Stop mode + IWDG_STOP: u1, + }), + /// Flash option control register 1 + OPTCR1: mmio.Mmio(packed struct(u32) { + /// Boot base address when Boot pin =0 + BOOT_ADD0: u16, + /// Boot base address when Boot pin =1 + BOOT_ADD1: u16, + }), + /// Flash option control register + OPTCR2: mmio.Mmio(packed struct(u32) { + /// PCROP option byte + PCROPi: u8, + reserved31: u23, + /// PCROP zone preserved when RDP level decreased + PCROP_RDP: u1, + }), }; + }; - pub const RXPLVL = enum(u2) { - /// Zero frames beyond packing ratio available - ZeroFrames = 0x0, - /// One frame beyond packing ratio available - OneFrame = 0x1, - /// Two frame beyond packing ratio available - TwoFrames = 0x2, - /// Three frame beyond packing ratio available - ThreeFrames = 0x3, + pub const flash_g0 = struct { + pub const BORF_LEV = enum(u2) { + /// BOR falling level 1 with threshold around 2.0V + FALLING_0 = 0x0, + /// BOR falling level 2 with threshold around 2.2V + FALLING_1 = 0x1, + /// BOR falling level 3 with threshold around 2.5V + FALLING_2 = 0x2, + /// BOR falling level 4 with threshold around 2.8V + FALLING_3 = 0x3, }; - pub const RXWNE = enum(u1) { - /// Less than 32-bit data frame received - LessThan32 = 0x0, - /// At least 32-bit data frame received - AtLeast32 = 0x1, + pub const BORR_LEV = enum(u2) { + /// BOR rising level 1 with threshold around 2.1V + RISING_0 = 0x0, + /// BOR rising level 2 with threshold around 2.3V + RISING_1 = 0x1, + /// BOR rising level 3 with threshold around 2.6V + RISING_2 = 0x2, + /// BOR rising level 4 with threshold around 2.9V + RISING_3 = 0x3, }; - pub const SP = enum(u3) { - /// Motorola SPI protocol - Motorola = 0x0, - /// TI SPI protocol - TI = 0x1, + pub const LATENCY = enum(u3) { + /// Zero wait states + WS0 = 0x0, + /// One wait state + WS1 = 0x1, + /// Two wait states + WS2 = 0x2, _, }; - pub const SSIOP = enum(u1) { - /// Low level is active for SS signal - ActiveLow = 0x0, - /// High level is active for SS signal - ActiveHigh = 0x1, + pub const NRST_MODE = enum(u2) { + /// Reset pin is in reset input mode only + INPUT_ONLY = 0x1, + /// Reset pin is in GPIO mode only + GPIO = 0x2, + /// Reset pin is in resety input and output mode + INPUT_OUTPUT = 0x3, + _, }; - pub const SSOM = enum(u1) { - /// SS is asserted until data transfer complete - Asserted = 0x0, - /// Data frames interleaved with SS not asserted during MIDI - NotAsserted = 0x1, + pub const RDP = enum(u8) { + /// Read protection not active + LEVEL_0 = 0xaa, + /// Memories read protection active + LEVEL_1 = 0xbb, + /// Chip read protection active + LEVEL_2 = 0xcc, + _, }; - pub const TCRCINI = enum(u1) { - /// All zeros TX CRC initialization pattern - AllZeros = 0x0, - /// All ones TX CRC initialization pattern - AllOnes = 0x1, - }; - - pub const UDRCFG = enum(u2) { - /// Slave sends a constant underrun pattern - Constant = 0x0, - /// Slave repeats last received data frame from master - RepeatReceived = 0x1, - /// Slave repeats last transmitted data frame - RepeatTransmitted = 0x2, - _, - }; - - pub const UDRDET = enum(u2) { - /// Underrun is detected at begin of data frame - StartOfFrame = 0x0, - /// Underrun is detected at end of last data frame - EndOfFrame = 0x1, - /// Underrun is detected at begin of active SS signal - StartOfSlaveSelect = 0x2, - _, - }; - - /// Serial peripheral interface - pub const SPI = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Serial Peripheral Enable - SPE: u1, - reserved8: u7, - /// Master automatic SUSP in Receive mode - MASRX: u1, - /// Master transfer start - CSTART: u1, - /// Master SUSPend request - CSUSP: u1, - /// Rx/Tx direction at Half-duplex mode - HDDIR: packed union { - raw: u1, - value: HDDIR, - }, - /// Internal SS signal input level - SSI: u1, - /// Full size (33-bit or 17-bit) CRC polynomial is used - CRC33_17: u1, - /// CRC calculation initialization pattern control for receiver - RCRCINI: packed union { - raw: u1, - value: RCRCINI, - }, - /// CRC calculation initialization pattern control for transmitter - TCRCINI: packed union { - raw: u1, - value: TCRCINI, + /// Flash + pub const FLASH = extern struct { + /// Access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: packed union { + raw: u3, + value: LATENCY, }, - /// Locking the AF configuration of associated IOs - IOLOCK: u1, - padding: u15, + reserved8: u5, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + reserved11: u1, + /// Instruction cache reset + ICRST: u1, + reserved16: u4, + /// Flash User area empty + EMPTY: u1, + reserved18: u1, + /// Debug access software enable + DBG_SWEN: u1, + padding: u13, }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Number of data at current transfer - TSIZE: u16, - /// Number of data transfer extension to be reload into TSIZE just when a previous - TSER: u16, + reserved8: [4]u8, + /// Flash key register + KEYR: u32, + /// Option byte key register + OPTKEYR: u32, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved3: u1, + /// Programming error + PROGERR: u1, + /// Write protected error + WRPERR: u1, + /// Programming alignment error + PGAERR: u1, + /// Size error + SIZERR: u1, + /// Programming sequence error + PGSERR: u1, + /// Fast programming data miss error + MISERR: u1, + /// Fast programming error + FASTERR: u1, + reserved14: u4, + /// PCROP read error + RDERR: u1, + /// Option and Engineering bits loading validity error + OPTVERR: u1, + /// Busy + BSY: u1, + reserved18: u1, + /// Programming or erase configuration busy. + CFGBSY: u1, + padding: u13, }), - /// configuration register 1 - CFG1: mmio.Mmio(packed struct(u32) { - /// Number of bits in at single SPI data frame - DSIZE: u5, - /// threshold level - FTHLV: packed union { - raw: u4, - value: FTHLV, + /// Flash control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Page erase + PER: u1, + /// Mass erase + MER: u1, + /// Page number + PNB: u6, + reserved16: u7, + /// Start + STRT: u1, + /// Options modification start + OPTSTRT: u1, + /// Fast programming + FSTPG: u1, + reserved24: u5, + /// End of operation interrupt enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + /// PCROP read error interrupt enable + RDERRIE: u1, + /// Force the option byte loading + OBL_LAUNCH: u1, + /// Securable memory area protection enable + SEC_PROT: u1, + reserved30: u1, + /// Options Lock + OPTLOCK: u1, + /// FLASH_CR Lock + LOCK: u1, + }), + /// Flash ECC register + ECCR: mmio.Mmio(packed struct(u32) { + /// ECC fail address + ADDR_ECC: u14, + reserved20: u6, + /// ECC fail for Corrected ECC Error or Double ECC Error in info block + SYSF_ECC: u1, + reserved24: u3, + /// ECC correction interrupt enable + ECCIE: u1, + reserved30: u5, + /// ECC correction + ECCC: u1, + /// ECC detection + ECCD: u1, + }), + reserved32: [4]u8, + /// Flash option register + OPTR: mmio.Mmio(packed struct(u32) { + /// Read protection level + RDP: packed union { + raw: u8, + value: RDP, }, - /// Behavior of slave transmitter at underrun condition - UDRCFG: packed union { + /// BOR reset Level + BOREN: u1, + /// These bits contain the VDD supply level threshold that activates the reset + BORF_LEV: packed union { raw: u2, - value: UDRCFG, + value: BORF_LEV, }, - /// Detection of underrun condition at slave transmitter - UDRDET: packed union { + /// These bits contain the VDD supply level threshold that releases the reset. + BORR_LEV: packed union { raw: u2, - value: UDRDET, - }, - reserved14: u1, - /// Rx DMA stream enable - RXDMAEN: u1, - /// Tx DMA stream enable - TXDMAEN: u1, - /// Length of CRC frame to be transacted and compared - CRCSIZE: u5, - reserved22: u1, - /// Hardware CRC computation enable - CRCEN: u1, - reserved28: u5, - /// Master baud rate - MBR: packed union { - raw: u3, - value: MBR, + value: BORR_LEV, }, - padding: u1, - }), - /// configuration register 2 - CFG2: mmio.Mmio(packed struct(u32) { - /// Master SS Idleness - MSSI: u4, - /// Master Inter-Data Idleness - MIDI: u4, - reserved15: u7, - /// Swap functionality of MISO and MOSI pins - IOSWP: u1, - reserved17: u1, - /// SPI Communication Mode - COMM: packed union { + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + /// nRSTS_HDW + nRSTS_HDW: u1, + /// Independent watchdog selection + IDWG_SW: u1, + /// Independent watchdog counter freeze in Stop mode + IWDG_STOP: u1, + /// Independent watchdog counter freeze in Standby mode + IWDG_STDBY: u1, + /// Window watchdog selection + WWDG_SW: u1, + reserved22: u2, + /// SRAM parity check control + RAM_PARITY_CHECK: u1, + reserved24: u1, + /// nBOOT_SEL + nBOOT_SEL: u1, + /// Boot configuration + nBOOT1: u1, + /// nBOOT0 option bit + nBOOT0: u1, + /// NRST_MODE + NRST_MODE: packed union { raw: u2, - value: COMM, - }, - /// Serial Protocol - SP: packed union { - raw: u3, - value: SP, - }, - /// SPI Master - MASTER: packed union { - raw: u1, - value: MASTER, - }, - /// Data frame format - LSBFIRST: packed union { - raw: u1, - value: LSBFIRST, - }, - /// Clock phase - CPHA: packed union { - raw: u1, - value: CPHA, - }, - /// Clock polarity - CPOL: packed union { - raw: u1, - value: CPOL, - }, - /// Software management of SS signal input - SSM: u1, - reserved28: u1, - /// SS input/output polarity - SSIOP: packed union { - raw: u1, - value: SSIOP, - }, - /// SS output enable - SSOE: u1, - /// SS output management in master mode - SSOM: packed union { - raw: u1, - value: SSOM, + value: NRST_MODE, }, - /// Alternate function always control GPIOs - AFCNTR: u1, - }), - /// Interrupt Enable Register - IER: mmio.Mmio(packed struct(u32) { - /// RXP Interrupt Enable - RXPIE: u1, - /// TXP interrupt enable - TXPIE: u1, - /// DXP interrupt enabled - DXPIE: u1, - /// EOT, SUSP and TXC interrupt enable - EOTIE: u1, - /// TXTFIE interrupt enable - TXTFIE: u1, - /// UDR interrupt enable - UDRIE: u1, - /// OVR interrupt enable - OVRIE: u1, - /// CRC Interrupt enable - CRCEIE: u1, - /// TIFRE interrupt enable - TIFREIE: u1, - /// Mode Fault interrupt enable - MODFIE: u1, - /// Additional number of transactions reload interrupt enable - TSERFIE: u1, - padding: u21, + /// Internal reset holder enable bit + IRHEN: u1, + padding: u2, }), - /// Status Register - SR: mmio.Mmio(packed struct(u32) { - /// Rx-Packet available - RXP: u1, - /// Tx-Packet space available - TXP: u1, - /// Duplex Packet - DXP: u1, - /// End Of Transfer - EOT: u1, - /// Transmission Transfer Filled - TXTF: u1, - /// Underrun at slave transmission mode - UDR: u1, - /// Overrun - OVR: u1, - /// CRC Error - CRCE: u1, - /// TI frame format error - TIFRE: u1, - /// Mode Fault - MODF: u1, - /// Additional number of SPI data to be transacted was reload - TSERF: u1, - /// SUSPend - SUSP: u1, - /// TxFIFO transmission complete - TXC: u1, - /// RxFIFO Packing LeVeL - RXPLVL: packed union { - raw: u2, - value: RXPLVL, - }, - /// RxFIFO Word Not Empty - RXWNE: packed union { - raw: u1, - value: RXWNE, - }, - /// Number of data frames remaining in current TSIZE session - CTSIZE: u16, + /// Flash PCROP zone A Start address register + PCROP1ASR: mmio.Mmio(packed struct(u32) { + /// PCROP1A area start offset + PCROP1A_STRT: u8, + padding: u24, }), - /// Interrupt/Status Flags Clear Register - IFCR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// End Of Transfer flag clear - EOTC: u1, - /// Transmission Transfer Filled flag clear - TXTFC: u1, - /// Underrun flag clear - UDRC: u1, - /// Overrun flag clear - OVRC: u1, - /// CRC Error flag clear - CRCEC: u1, - /// TI frame format error flag clear - TIFREC: u1, - /// Mode Fault flag clear - MODFC: u1, - /// TSERFC flag clear - TSERFC: u1, - /// SUSPend flag clear - SUSPC: u1, - padding: u20, + /// Flash PCROP zone A End address register + PCROP1AER: mmio.Mmio(packed struct(u32) { + /// PCROP1A area end offset + PCROP1A_END: u8, + reserved31: u23, + /// PCROP area preserved when RDP level decreased + PCROP_RDP: u1, }), - reserved32: [4]u8, - /// Transmit Data Register - half-word sized - TXDR16: u32, - reserved48: [12]u8, - /// Receive Data Register - half-word sized - RXDR16: u32, - reserved64: [12]u8, - /// Polynomial Register - CRCPOLY: mmio.Mmio(packed struct(u32) { - /// CRC polynomial register - CRCPOLY: u32, + /// Flash WRP area A address register + WRP1AR: mmio.Mmio(packed struct(u32) { + /// WRP area A start offset + WRP1A_STRT: u6, + reserved16: u10, + /// WRP area A end offset + WRP1A_END: u6, + padding: u10, }), - /// Transmitter CRC Register - TXCRC: mmio.Mmio(packed struct(u32) { - /// CRC register for transmitter - TXCRC: u32, + /// Flash WRP area B address register + WRP1BR: mmio.Mmio(packed struct(u32) { + /// WRP area B start offset + WRP1B_STRT: u6, + reserved16: u10, + /// WRP area B end offset + WRP1B_END: u6, + padding: u10, }), - /// Receiver CRC Register - RXCRC: mmio.Mmio(packed struct(u32) { - /// CRC register for receiver - RXCRC: u32, + /// Flash PCROP zone B Start address register + PCROP1BSR: mmio.Mmio(packed struct(u32) { + /// PCROP1B area start offset + PCROP1B_STRT: u8, + padding: u24, }), - /// Underrun Data Register - UDRDR: mmio.Mmio(packed struct(u32) { - /// Data at slave underrun condition - UDRDR: u32, + /// Flash PCROP zone B End address register + PCROP1BER: mmio.Mmio(packed struct(u32) { + /// PCROP1B area end offset + PCROP1B_END: u8, + padding: u24, }), - /// I2S Configuration Register - I2SCFGR: mmio.Mmio(packed struct(u32) { - /// I2S mode selection - I2SMOD: u1, - /// I2S configuration mode - I2SCFG: packed union { - raw: u3, - value: I2SCFG, - }, - /// I2S standard selection - I2SSTD: packed union { - raw: u2, - value: I2SSTD, - }, - reserved7: u1, - /// PCM frame synchronization - PCMSYNC: packed union { - raw: u1, - value: PCMSYNC, - }, - /// Data length to be transferred - DATLEN: packed union { - raw: u2, - value: DATLEN, - }, - /// Channel length (number of bits per audio channel) - CHLEN: packed union { - raw: u1, - value: CHLEN, - }, - /// Serial audio clock polarity - CKPOL: packed union { - raw: u1, - value: CKPOL, - }, - /// Fixed channel length in slave - FIXCH: packed union { - raw: u1, - value: FIXCH, - }, - /// Word select inversion - WSINV: u1, - /// Data format - DATFMT: packed union { - raw: u1, - value: DATFMT, - }, - reserved16: u1, - /// I2S linear prescaler - I2SDIV: u8, - /// Odd factor for the prescaler - ODD: packed union { - raw: u1, - value: ODD, - }, - /// Master clock output enable - MCKOE: u1, - padding: u6, + reserved128: [68]u8, + /// Flash Security register + SECR: mmio.Mmio(packed struct(u32) { + /// Securable memory area size + SEC_SIZE: u7, + reserved16: u9, + /// used to force boot from user area + BOOT_LOCK: u1, + padding: u15, }), }; }; - pub const sai_v3_4pdm = struct { - pub const CKSTR = enum(u1) { - /// Data strobing edge is falling edge of SCK - FallingEdge = 0x0, - /// Data strobing edge is rising edge of SCK - RisingEdge = 0x1, - }; - - pub const CNRDY = enum(u1) { - /// External AC’97 Codec is ready - Ready = 0x0, - /// External AC’97 Codec is not ready - NotReady = 0x1, - }; - - pub const COMP = enum(u2) { - /// No companding algorithm - NoCompanding = 0x0, - /// μ-Law algorithm - MuLaw = 0x2, - /// A-Law algorithm - ALaw = 0x3, - _, - }; - - pub const CPL = enum(u1) { - /// 1’s complement representation - OnesComplement = 0x0, - /// 2’s complement representation - TwosComplement = 0x1, - }; - - pub const DS = enum(u3) { - /// 8 bits - Bit8 = 0x2, - /// 10 bits - Bit10 = 0x3, - /// 16 bits - Bit16 = 0x4, - /// 20 bits - Bit20 = 0x5, - /// 24 bits - Bit24 = 0x6, - /// 32 bits - Bit32 = 0x7, + pub const flash_g4c2 = struct { + pub const LATENCY = enum(u4) { + /// Zero wait states + WS0 = 0x0, + /// One wait state + WS1 = 0x1, + /// Two wait states + WS2 = 0x2, + /// Three wait states + WS3 = 0x3, + /// Four wait states + WS4 = 0x4, _, }; - pub const FLVL = enum(u3) { - /// FIFO empty - Empty = 0x0, - /// FIFO <= 1⁄4 but not empty - Quarter1 = 0x1, - /// 1⁄4 < FIFO <= 1⁄2 - Quarter2 = 0x2, - /// 1⁄2 < FIFO <= 3⁄4 - Quarter3 = 0x3, - /// 3⁄4 < FIFO but not full - Quarter4 = 0x4, - /// FIFO full - Full = 0x5, + pub const NRST_MODE = enum(u2) { + /// Reset pin is in reset input mode only + INPUT_ONLY = 0x1, + /// Reset pin is in GPIO mode only + GPIO = 0x2, + /// Reset pin is in reset input and output mode + INPUT_OUTPUT = 0x3, _, }; - pub const FSOFF = enum(u1) { - /// FS is asserted on the first bit of the slot 0 - OnFirst = 0x0, - /// FS is asserted one bit before the first bit of the slot 0 - BeforeFirst = 0x1, - }; - - pub const FSPOL = enum(u1) { - /// FS is active low (falling edge) - FallingEdge = 0x0, - /// FS is active high (rising edge) - RisingEdge = 0x1, - }; - - pub const FTH = enum(u3) { - /// FIFO empty - Empty = 0x0, - /// 1⁄4 FIFO - Quarter1 = 0x1, - /// 1⁄2 FIFO - Quarter2 = 0x2, - /// 3⁄4 FIFO - Quarter3 = 0x3, - /// FIFO full - Full = 0x4, + pub const RDP = enum(u8) { + /// Read protection not active + LEVEL_0 = 0xaa, + /// Memories read protection active + LEVEL_1 = 0xbb, + /// Chip read protection active + LEVEL_2 = 0xcc, _, }; - pub const LSBFIRST = enum(u1) { - /// Data are transferred with MSB first - MsbFirst = 0x0, - /// Data are transferred with LSB first - LsbFirst = 0x1, - }; - - pub const MODE = enum(u2) { - /// Master transmitter - MasterTx = 0x0, - /// Master receiver - MasterRx = 0x1, - /// Slave transmitter - SlaveTx = 0x2, - /// Slave receiver - SlaveRx = 0x3, - }; - - pub const MONO = enum(u1) { - /// Stereo mode - Stereo = 0x0, - /// Mono mode - Mono = 0x1, - }; - - pub const MUTEVAL = enum(u1) { - /// Bit value 0 is sent during the mute mode - SendZero = 0x0, - /// Last values are sent during the mute mode - SendLast = 0x1, - }; - - pub const NODIV = enum(u1) { - /// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value - MasterClock = 0x0, - /// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. - NoDiv = 0x1, - }; - - pub const OUTDRIV = enum(u1) { - /// Audio block output driven when SAIEN is set - OnStart = 0x0, - /// Audio block output driven immediately after the setting of this bit - Immediately = 0x1, - }; - - pub const PRTCFG = enum(u2) { - /// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol - Free = 0x0, - /// SPDIF protocol - Spdif = 0x1, - /// AC’97 protocol - Ac97 = 0x2, - _, + /// Flash + pub const FLASH = extern struct { + /// Access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: packed union { + raw: u4, + value: LATENCY, + }, + reserved8: u4, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + /// Data cache enable + DCEN: u1, + /// Instruction cache reset + ICRST: u1, + /// Data cache reset + DCRST: u1, + /// Flash Power-down mode during Low-power run mode + RUN_PD: u1, + /// Flash Power-down mode during Low-power sleep mode + SLEEP_PD: u1, + reserved18: u3, + /// Debug software enable + DBG_SWEN: u1, + padding: u13, + }), + /// Power down key register + PDKEYR: u32, + /// Flash key register + KEYR: u32, + /// Option byte key register + OPTKEYR: u32, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved3: u1, + /// Programming error + PROGERR: u1, + /// Write protected error + WRPERR: u1, + /// Programming alignment error + PGAERR: u1, + /// Size error + SIZERR: u1, + /// Programming sequence error + PGSERR: u1, + /// Fast programming data miss error + MISERR: u1, + /// Fast programming error + FASTERR: u1, + reserved14: u4, + /// PCROP read error + RDERR: u1, + /// Option validity error + OPTVERR: u1, + /// Busy + BSY: u1, + padding: u15, + }), + /// Flash control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Page erase + PER: u1, + /// Bank 1 Mass erase + MER1: u1, + /// Page number + PNB: u7, + reserved16: u6, + /// Start + STRT: u1, + /// Options modification start + OPTSTRT: u1, + /// Fast programming + FSTPG: u1, + reserved24: u5, + /// End of operation interrupt enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + /// PCROP read error interrupt enable + RDERRIE: u1, + /// Force the option byte loading + OBL_LAUNCH: u1, + /// Securable memory area protection enable + SEC_PROT1: u1, + reserved30: u1, + /// Options Lock + OPTLOCK: u1, + /// FLASH_CR Lock + LOCK: u1, + }), + /// Flash ECC register + ECCR: mmio.Mmio(packed struct(u32) { + /// ECC fail address + ADDR_ECC: u19, + reserved21: u2, + /// ECC fail for Corrected ECC Error or Double ECC Error in info block + BK_ECC: u1, + /// ECC fail for Corrected ECC Error or Double ECC Error in info block + SYSF_ECC: u1, + reserved24: u1, + /// ECC correction interrupt enable + ECCIE: u1, + reserved28: u3, + /// ECC correction + ECCC2: u1, + /// ECC2 detection + ECCD2: u1, + /// ECC correction + ECCC: u1, + /// ECC detection + ECCD: u1, + }), + reserved32: [4]u8, + /// Flash option register + OPTR: mmio.Mmio(packed struct(u32) { + /// Read protection level + RDP: packed union { + raw: u8, + value: RDP, + }, + /// BOR reset Level + BOR_LEV: u3, + reserved12: u1, + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + /// nRST_SHDW + nRST_SHDW: u1, + reserved16: u1, + /// Independent watchdog selection + IDWG_SW: u1, + /// Independent watchdog counter freeze in Stop mode + IWDG_STOP: u1, + /// Independent watchdog counter freeze in Standby mode + IWDG_STDBY: u1, + /// Window watchdog selection + WWDG_SW: u1, + reserved23: u3, + /// Boot configuration + nBOOT1: u1, + /// SRAM2 parity check enable + SRAM2_PE: u1, + /// SRAM2 Erase when system reset + SRAM2_RST: u1, + /// nSWBOOT0 + nSWBOOT0: u1, + /// nBOOT0 option bit + nBOOT0: u1, + /// NRST_MODE + NRST_MODE: packed union { + raw: u2, + value: NRST_MODE, + }, + /// Internal reset holder enable bit + IRHEN: u1, + padding: u1, + }), + /// Flash Bank 1 PCROP Start address register + PCROP1SR: mmio.Mmio(packed struct(u32) { + /// Bank 1 PCROP area start offset + PCROP1_STRT: u15, + padding: u17, + }), + /// Flash Bank 1 PCROP End address register + PCROP1ER: mmio.Mmio(packed struct(u32) { + /// Bank 1 PCROP area end offset + PCROP1_END: u15, + reserved31: u16, + /// PCROP area preserved when RDP level decreased + PCROP_RDP: u1, + }), + /// Flash Bank 1 WRP area A address register + WRP1AR: mmio.Mmio(packed struct(u32) { + /// Bank 1 WRP first area start offset + WRP1A_STRT: u7, + reserved16: u9, + /// Bank 1 WRP first area A end offset + WRP1A_END: u7, + padding: u9, + }), + /// Flash Bank 1 WRP area B address register + WRP1BR: mmio.Mmio(packed struct(u32) { + /// Bank 1 WRP second area B end offset + WRP1B_STRT: u7, + reserved16: u9, + /// Bank 1 WRP second area B start offset + WRP1B_END: u7, + padding: u9, + }), + reserved112: [60]u8, + /// securable area bank1 register + SEC1R: mmio.Mmio(packed struct(u32) { + /// SEC_SIZE1 + SEC_SIZE1: u8, + reserved16: u8, + /// used to force boot from user area + BOOT_LOCK: u1, + padding: u15, + }), }; + }; - pub const SLOTEN = enum(u16) { - /// Inactive slot - Inactive = 0x0, - /// Active slot - Active = 0x1, + pub const flash_g4c3 = struct { + pub const LATENCY = enum(u4) { + /// Zero wait states + WS0 = 0x0, + /// One wait state + WS1 = 0x1, + /// Two wait states + WS2 = 0x2, + /// Three wait states + WS3 = 0x3, + /// Four wait states + WS4 = 0x4, _, }; - pub const SLOTSZ = enum(u2) { - /// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) - DataSize = 0x0, - /// 16-bit - Bit16 = 0x1, - /// 32-bit - Bit32 = 0x2, + pub const NRST_MODE = enum(u2) { + /// Reset pin is in reset input mode only + INPUT_ONLY = 0x1, + /// Reset pin is in GPIO mode only + GPIO = 0x2, + /// Reset pin is in reset input and output mode + INPUT_OUTPUT = 0x3, _, }; - pub const SYNCEN = enum(u2) { - /// audio sub-block in asynchronous mode - Asynchronous = 0x0, - /// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode - Internal = 0x1, - /// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode - External = 0x2, + pub const RDP = enum(u8) { + /// Read protection not active + LEVEL_0 = 0xaa, + /// Memories read protection active + LEVEL_1 = 0xbb, + /// Chip read protection active + LEVEL_2 = 0xcc, _, }; - pub const WCKCFG = enum(u1) { - /// Clock configuration is correct - Correct = 0x0, - /// Clock configuration does not respect the rule concerning the frame length specification - Wrong = 0x1, - }; - - /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - pub const CH = extern struct { - /// Configuration register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// SAIx audio block mode immediately - MODE: packed union { - raw: u2, - value: MODE, - }, - /// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. - PRTCFG: packed union { - raw: u2, - value: PRTCFG, - }, - reserved5: u1, - /// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. - DS: packed union { - raw: u3, - value: DS, - }, - /// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. - LSBFIRST: packed union { - raw: u1, - value: LSBFIRST, - }, - /// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. - CKSTR: packed union { - raw: u1, - value: CKSTR, - }, - /// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. - SYNCEN: packed union { - raw: u2, - value: SYNCEN, - }, - /// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. - MONO: packed union { - raw: u1, - value: MONO, - }, - /// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. - OUTDRIV: packed union { - raw: u1, - value: OUTDRIV, - }, - reserved16: u2, - /// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. - SAIEN: u1, - /// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. - DMAEN: u1, - reserved19: u1, - /// No fixed divider between MCLK and FS - NODIV: packed union { - raw: u1, - value: NODIV, - }, - /// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: - MCKDIV: u6, - /// Oversampling ratio for master clock - OSR: u1, - padding: u5, - }), - /// Configuration register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// FIFO threshold. This bit is set and cleared by software. - FTH: packed union { - raw: u3, - value: FTH, - }, - /// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. - FFLUSH: u1, - /// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. - TRIS: u1, - /// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. - MUTE: u1, - /// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. - MUTEVAL: packed union { - raw: u1, - value: MUTEVAL, - }, - /// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. - MUTECNT: u6, - /// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. - CPL: packed union { - raw: u1, - value: CPL, - }, - /// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. - COMP: packed union { - raw: u2, - value: COMP, - }, - padding: u16, - }), - /// This register has no meaning in AC97 and SPDIF audio protocol - FRCR: mmio.Mmio(packed struct(u32) { - /// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. - FRL: u8, - /// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. - FSALL: u7, - reserved16: u1, - /// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. - FSDEF: u1, - /// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - FSPOL: packed union { - raw: u1, - value: FSPOL, - }, - /// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - FSOFF: packed union { - raw: u1, - value: FSOFF, + /// Flash + pub const FLASH = extern struct { + /// Access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: packed union { + raw: u4, + value: LATENCY, }, + reserved8: u4, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + /// Data cache enable + DCEN: u1, + /// Instruction cache reset + ICRST: u1, + /// Data cache reset + DCRST: u1, + /// Flash Power-down mode during Low-power run mode + RUN_PD: u1, + /// Flash Power-down mode during Low-power sleep mode + SLEEP_PD: u1, + reserved18: u3, + /// Debug software enable + DBG_SWEN: u1, padding: u13, }), - /// This register has no meaning in AC97 and SPDIF audio protocol - SLOTR: mmio.Mmio(packed struct(u32) { - /// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - FBOFF: u5, - reserved6: u1, - /// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - SLOTSZ: packed union { - raw: u2, - value: SLOTSZ, - }, - /// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - NBSLOT: u4, - reserved16: u4, - /// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - SLOTEN: packed union { - raw: u16, - value: SLOTEN, - }, - }), - /// Interrupt mask register 2 - IM: mmio.Mmio(packed struct(u32) { - /// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. - OVRUDRIE: u1, - /// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. - MUTEDETIE: u1, - /// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. - WCKCFGIE: u1, - /// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, - FREQIE: u1, - /// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. - CNRDYIE: u1, - /// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. - AFSDETIE: u1, - /// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. - LFSDETIE: u1, - padding: u25, - }), + /// Power down key register + PDKEYR: u32, + /// Flash key register + KEYR: u32, + /// Option byte key register + OPTKEYR: u32, /// Status register SR: mmio.Mmio(packed struct(u32) { - /// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. - OVRUDR: u1, - /// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. - MUTEDET: u1, - /// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. - WCKCFG: packed union { - raw: u1, - value: WCKCFG, - }, - /// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. - FREQ: u1, - /// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. - CNRDY: packed union { - raw: u1, - value: CNRDY, + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved3: u1, + /// Programming error + PROGERR: u1, + /// Write protected error + WRPERR: u1, + /// Programming alignment error + PGAERR: u1, + /// Size error + SIZERR: u1, + /// Programming sequence error + PGSERR: u1, + /// Fast programming data miss error + MISERR: u1, + /// Fast programming error + FASTERR: u1, + reserved14: u4, + /// PCROP read error + RDERR: u1, + /// Option validity error + OPTVERR: u1, + /// Busy + BSY: u1, + padding: u15, + }), + /// Flash control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Page erase + PER: u1, + /// Bank 1 Mass erase + MER1: u1, + /// Page number + PNB: u7, + reserved15: u5, + /// Bank 2 Mass erase + MER2: u1, + /// Start + STRT: u1, + /// Options modification start + OPTSTRT: u1, + /// Fast programming + FSTPG: u1, + reserved24: u5, + /// End of operation interrupt enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + /// PCROP read error interrupt enable + RDERRIE: u1, + /// Force the option byte loading + OBL_LAUNCH: u1, + /// Securable memory area protection enable + SEC_PROT1: u1, + reserved30: u1, + /// Options Lock + OPTLOCK: u1, + /// FLASH_CR Lock + LOCK: u1, + }), + /// Flash ECC register + ECCR: mmio.Mmio(packed struct(u32) { + /// ECC fail address + ADDR_ECC: u19, + reserved21: u2, + /// ECC fail for Corrected ECC Error or Double ECC Error in info block + BK_ECC: u1, + /// ECC fail for Corrected ECC Error or Double ECC Error in info block + SYSF_ECC: u1, + reserved24: u1, + /// ECC correction interrupt enable + ECCIE: u1, + reserved28: u3, + /// ECC correction + ECCC2: u1, + /// ECC2 detection + ECCD2: u1, + /// ECC correction + ECCC: u1, + /// ECC detection + ECCD: u1, + }), + reserved32: [4]u8, + /// Flash option register + OPTR: mmio.Mmio(packed struct(u32) { + /// Read protection level + RDP: packed union { + raw: u8, + value: RDP, }, - /// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. - AFSDET: u1, - /// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register - LFSDET: u1, - reserved16: u9, - /// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: - FLVL: packed union { - raw: u3, - value: FLVL, + /// BOR reset Level + BOR_LEV: u3, + reserved12: u1, + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + /// nRST_SHDW + nRST_SHDW: u1, + reserved16: u1, + /// Independent watchdog selection + IDWG_SW: u1, + /// Independent watchdog counter freeze in Stop mode + IWDG_STOP: u1, + /// Independent watchdog counter freeze in Standby mode + IWDG_STDBY: u1, + /// Window watchdog selection + WWDG_SW: u1, + /// Dual bank boot + BFB2: u1, + reserved22: u1, + /// Dual bank memory mode + DBANK: u1, + /// Boot configuration + nBOOT1: u1, + /// SRAM2 parity check enable + SRAM2_PE: u1, + /// SRAM2 Erase when system reset + SRAM2_RST: u1, + /// nSWBOOT0 + nSWBOOT0: u1, + /// nBOOT0 option bit + nBOOT0: u1, + /// NRST_MODE + NRST_MODE: packed union { + raw: u2, + value: NRST_MODE, }, - padding: u13, + /// Internal reset holder enable bit + IRHEN: u1, + padding: u1, }), - /// Clear flag register - CLRFR: mmio.Mmio(packed struct(u32) { - /// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. - COVRUDR: u1, - /// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. - CMUTEDET: u1, - /// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. - CWCKCFG: u1, - reserved4: u1, - /// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. - CCNRDY: u1, - /// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. - CAFSDET: u1, - /// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. - CLFSDET: u1, - padding: u25, + /// Flash Bank 1 PCROP Start address register + PCROP1SR: mmio.Mmio(packed struct(u32) { + /// Bank 1 PCROP area start offset + PCROP1_STRT: u15, + padding: u17, }), - /// Data register - DR: mmio.Mmio(packed struct(u32) { - /// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. - DATA: u32, + /// Flash Bank 1 PCROP End address register + PCROP1ER: mmio.Mmio(packed struct(u32) { + /// Bank 1 PCROP area end offset + PCROP1_END: u15, + reserved31: u16, + /// PCROP area preserved when RDP level decreased + PCROP_RDP: u1, }), - }; - - /// Serial audio interface - pub const SAI = extern struct { - /// Global configuration register - GCR: mmio.Mmio(packed struct(u32) { - /// Synchronization inputs - SYNCIN: u2, - reserved4: u2, - /// Synchronization outputs These bits are set and cleared by software. - SYNCOUT: u2, - padding: u26, + /// Flash Bank 1 WRP area A address register + WRP1AR: mmio.Mmio(packed struct(u32) { + /// Bank 1 WRP first area start offset + WRP1A_STRT: u7, + reserved16: u9, + /// Bank 1 WRP first area A end offset + WRP1A_END: u7, + padding: u9, }), - /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - CH: u32, - reserved68: [60]u8, - /// PDM control register - PDMCR: mmio.Mmio(packed struct(u32) { - /// PDM enable - PDMEN: u1, - reserved4: u3, - /// Number of microphones - MICNBR: u2, - reserved8: u2, - /// Clock enable of bitstream clock number 1 - CKEN: u1, - padding: u23, + /// Flash Bank 1 WRP area B address register + WRP1BR: mmio.Mmio(packed struct(u32) { + /// Bank 1 WRP second area B end offset + WRP1B_STRT: u7, + reserved16: u9, + /// Bank 1 WRP second area B start offset + WRP1B_END: u7, + padding: u9, }), - /// PDM delay register - PDMDLY: mmio.Mmio(packed struct(u32) { - /// Delay line adjust for first microphone of pair 1 - DLYML: u3, - reserved4: u1, - /// Delay line adjust for second microphone of pair 1 - DLYMR: u3, - padding: u25, + reserved112: [60]u8, + /// securable area bank1 register + SEC1R: mmio.Mmio(packed struct(u32) { + /// SEC_SIZE1 + SEC_SIZE1: u8, + reserved16: u8, + /// used to force boot from user area + BOOT_LOCK: u1, + padding: u15, }), }; }; - pub const syscfg_l5 = struct { - /// System configuration controller - pub const SYSCFG = extern struct { - /// SYSCFG secure configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock control security - SYSCFGSEC: u1, - /// ClassB security - CLASSBSEC: u1, - /// SRAM2 security - SRAM2SEC: u1, - /// FPUSEC - FPUSEC: u1, - padding: u28, - }), - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// I/O analog switch voltage booster enable - BOOSTEN: u1, - /// GPIO analog switch control voltage selection - ANASWVDD: u1, - reserved16: u6, - /// Fast-mode Plus (Fm+) driving capability activation on PB6 - I2C_PB6_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB7 - I2C_PB7_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB8 - I2C_PB8_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB9 - I2C_PB9_FMP: u1, - /// I2C1 Fast-mode Plus driving capability activation - I2C1_FMP: u1, - /// I2C2 Fast-mode Plus driving capability activation - I2C2_FMP: u1, - /// I2C3 Fast-mode Plus driving capability activation - I2C3_FMP: u1, - /// I2C4_FMP - I2C4_FMP: u1, - padding: u8, - }), - /// FPU interrupt mask register - FPUIMR: mmio.Mmio(packed struct(u32) { - /// Floating point unit interrupts enable bits - FPU_IE: u6, - padding: u26, - }), - /// SYSCFG CPU non-secure lock register - CNSLCKR: mmio.Mmio(packed struct(u32) { - /// VTOR_NS register lock - LOCKNSVTOR: u1, - /// Non-secure MPU registers lock - LOCKNSMPU: u1, - padding: u30, - }), - /// SYSCFG CPU secure lock register - CSLOCKR: mmio.Mmio(packed struct(u32) { - /// LOCKSVTAIRCR - LOCKSVTAIRCR: u1, - /// LOCKSMPU - LOCKSMPU: u1, - /// LOCKSAU - LOCKSAU: u1, - padding: u29, - }), - /// CFGR2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// LOCKUP (hardfault) output enable bit - CLL: u1, - /// SRAM2 parity lock bit - SPL: u1, - /// PVD lock enable bit - PVDL: u1, - /// ECC Lock - ECCL: u1, - reserved8: u4, - /// SRAM2 parity error flag - SPF: u1, - padding: u23, - }), - /// SCSR - SCSR: mmio.Mmio(packed struct(u32) { - /// SRAM2 Erase - SRAM2ER: u1, - /// SRAM2 busy by erase operation - SRAM2BSY: u1, - padding: u30, - }), - /// SKR - SKR: mmio.Mmio(packed struct(u32) { - /// SRAM2 write protection key for software erase - KEY: u8, - padding: u24, - }), - /// SWPR - SWPR: mmio.Mmio(packed struct(u32) { - /// P0WP - P0WP: u1, - /// P1WP - P1WP: u1, - /// P2WP - P2WP: u1, - /// P3WP - P3WP: u1, - /// P4WP - P4WP: u1, - /// P5WP - P5WP: u1, - /// P6WP - P6WP: u1, - /// P7WP - P7WP: u1, - /// P8WP - P8WP: u1, - /// P9WP - P9WP: u1, - /// P10WP - P10WP: u1, - /// P11WP - P11WP: u1, - /// P12WP - P12WP: u1, - /// P13WP - P13WP: u1, - /// P14WP - P14WP: u1, - /// P15WP - P15WP: u1, - /// P16WP - P16WP: u1, - /// P17WP - P17WP: u1, - /// P18WP - P18WP: u1, - /// P19WP - P19WP: u1, - /// P20WP - P20WP: u1, - /// P21WP - P21WP: u1, - /// P22WP - P22WP: u1, - /// P23WP - P23WP: u1, - /// P24WP - P24WP: u1, - /// P25WP - P25WP: u1, - /// P26WP - P26WP: u1, - /// P27WP - P27WP: u1, - /// P28WP - P28WP: u1, - /// P29WP - P29WP: u1, - /// P30WP - P30WP: u1, - /// SRAM2 page 31 write protection - P31WP: u1, - }), - /// SWPR2 - SWPR2: mmio.Mmio(packed struct(u32) { - /// P32WP - P32WP: u1, - /// P33WP - P33WP: u1, - /// P34WP - P34WP: u1, - /// P35WP - P35WP: u1, - /// P36WP - P36WP: u1, - /// P37WP - P37WP: u1, - /// P38WP - P38WP: u1, - /// P39WP - P39WP: u1, - /// P40WP - P40WP: u1, - /// P41WP - P41WP: u1, - /// P42WP - P42WP: u1, - /// P43WP - P43WP: u1, - /// P44WP - P44WP: u1, - /// P45WP - P45WP: u1, - /// P46WP - P46WP: u1, - /// P47WP - P47WP: u1, - /// P48WP - P48WP: u1, - /// P49WP - P49WP: u1, - /// P50WP - P50WP: u1, - /// P51WP - P51WP: u1, - /// P52WP - P52WP: u1, - /// P53WP - P53WP: u1, - /// P54WP - P54WP: u1, - /// P55WP - P55WP: u1, - /// P56WP - P56WP: u1, - /// P57WP - P57WP: u1, - /// P58WP - P58WP: u1, - /// P59WP - P59WP: u1, - /// P60WP - P60WP: u1, - /// P61WP - P61WP: u1, - /// P62WP - P62WP: u1, - /// P63WP - P63WP: u1, - }), - reserved44: [4]u8, - /// RSSCMDR - RSSCMDR: mmio.Mmio(packed struct(u32) { - /// RSS commands - RSSCMD: u8, - padding: u24, - }), + pub const flash_g4c4 = struct { + pub const LATENCY = enum(u4) { + /// Zero wait states + WS0 = 0x0, + /// One wait state + WS1 = 0x1, + /// Two wait states + WS2 = 0x2, + /// Three wait states + WS3 = 0x3, + /// Four wait states + WS4 = 0x4, + _, }; - }; - pub const exti_c0 = struct { - /// External interrupt/event controller - pub const EXTI = extern struct { - /// Rising Trigger selection register - RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Falling Trigger selection register - FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Software interrupt event register - SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Rising pending register - RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Falling pending register - FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - reserved96: [76]u8, - /// Configuration register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u8, - padding: u24, - }), - reserved128: [16]u8, - /// Interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Event mask register - EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), + pub const NRST_MODE = enum(u2) { + /// Reset pin is in reset input mode only + INPUT_ONLY = 0x1, + /// Reset pin is in GPIO mode only + GPIO = 0x2, + /// Reset pin is in reset input and output mode + INPUT_OUTPUT = 0x3, + _, }; - }; - pub const jpeg_v1 = struct { - /// JPEG codec - pub const JPEG = extern struct { - /// JPEG codec configuration register 0 - JPEG_CONFR0: mmio.Mmio(packed struct(u32) { - /// Start - START: u1, - padding: u31, + pub const RDP = enum(u8) { + /// Read protection not active + LEVEL_0 = 0xaa, + /// Memories read protection active + LEVEL_1 = 0xbb, + /// Chip read protection active + LEVEL_2 = 0xcc, + _, + }; + + /// Flash + pub const FLASH = extern struct { + /// Access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: packed union { + raw: u4, + value: LATENCY, + }, + reserved8: u4, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + /// Data cache enable + DCEN: u1, + /// Instruction cache reset + ICRST: u1, + /// Data cache reset + DCRST: u1, + /// Flash Power-down mode during Low-power run mode + RUN_PD: u1, + /// Flash Power-down mode during Low-power sleep mode + SLEEP_PD: u1, + reserved18: u3, + /// Debug software enable + DBG_SWEN: u1, + padding: u13, }), - /// JPEG codec configuration register 1 - JPEG_CONFR1: mmio.Mmio(packed struct(u32) { - /// Number of color components - NF: u2, + /// Power down key register + PDKEYR: u32, + /// Flash key register + KEYR: u32, + /// Option byte key register + OPTKEYR: u32, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, reserved3: u1, - /// Decoding Enable - DE: u1, - /// Color Space - COLORSPACE: u2, - /// Number of components for Scan - NS: u2, - /// Header Processing - HDR: u1, - reserved16: u7, - /// Y Size - YSIZE: u16, - }), - /// JPEG codec configuration register 2 - JPEG_CONFR2: mmio.Mmio(packed struct(u32) { - /// Number of MCU - NMCU: u26, - padding: u6, - }), - /// JPEG codec configuration register 3 - JPEG_CONFR3: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// X size - XSIZE: u16, - }), - /// JPEG codec configuration register 4 - JPEG_CONFR4: mmio.Mmio(packed struct(u32) { - /// Huffman DC - HD: u1, - /// Huffman AC - HA: u1, - /// Quantization Table - QT: u2, - /// Number of Block - NB: u4, - /// Vertical Sampling Factor - VSF: u4, - /// Horizontal Sampling Factor - HSF: u4, - padding: u16, + /// Programming error + PROGERR: u1, + /// Write protected error + WRPERR: u1, + /// Programming alignment error + PGAERR: u1, + /// Size error + SIZERR: u1, + /// Programming sequence error + PGSERR: u1, + /// Fast programming data miss error + MISERR: u1, + /// Fast programming error + FASTERR: u1, + reserved14: u4, + /// PCROP read error + RDERR: u1, + /// Option validity error + OPTVERR: u1, + /// Busy + BSY: u1, + padding: u15, }), - /// JPEG codec configuration register 5 - JPEG_CONFR5: mmio.Mmio(packed struct(u32) { - /// Huffman DC - HD: u1, - /// Huffman AC - HA: u1, - /// Quantization Table - QT: u2, - /// Number of Block - NB: u4, - /// Vertical Sampling Factor - VSF: u4, - /// Horizontal Sampling Factor - HSF: u4, - padding: u16, + /// Flash control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Page erase + PER: u1, + /// Bank 1 Mass erase + MER1: u1, + /// Page number + PNB: u7, + reserved16: u6, + /// Start + STRT: u1, + /// Options modification start + OPTSTRT: u1, + /// Fast programming + FSTPG: u1, + reserved24: u5, + /// End of operation interrupt enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + /// PCROP read error interrupt enable + RDERRIE: u1, + /// Force the option byte loading + OBL_LAUNCH: u1, + /// Securable memory area protection enable + SEC_PROT1: u1, + reserved30: u1, + /// Options Lock + OPTLOCK: u1, + /// FLASH_CR Lock + LOCK: u1, }), - /// JPEG codec configuration register 6 - JPEG_CONFR6: mmio.Mmio(packed struct(u32) { - /// Huffman DC - HD: u1, - /// Huffman AC - HA: u1, - /// Quantization Table - QT: u2, - /// Number of Block - NB: u4, - /// Vertical Sampling Factor - VSF: u4, - /// Horizontal Sampling Factor - HSF: u4, - padding: u16, + /// Flash ECC register + ECCR: mmio.Mmio(packed struct(u32) { + /// ECC fail address + ADDR_ECC: u19, + reserved21: u2, + /// ECC fail for Corrected ECC Error or Double ECC Error in info block + BK_ECC: u1, + /// ECC fail for Corrected ECC Error or Double ECC Error in info block + SYSF_ECC: u1, + reserved24: u1, + /// ECC correction interrupt enable + ECCIE: u1, + reserved28: u3, + /// ECC correction + ECCC2: u1, + /// ECC2 detection + ECCD2: u1, + /// ECC correction + ECCC: u1, + /// ECC detection + ECCD: u1, }), - /// JPEG codec configuration register 7 - JPEG_CONFR7: mmio.Mmio(packed struct(u32) { - /// Huffman DC - HD: u1, - /// Huffman AC - HA: u1, - /// Quantization Table - QT: u2, - /// Number of Block - NB: u4, - /// Vertical Sampling Factor - VSF: u4, - /// Horizontal Sampling Factor - HSF: u4, - padding: u16, + reserved32: [4]u8, + /// Flash option register + OPTR: mmio.Mmio(packed struct(u32) { + /// Read protection level + RDP: packed union { + raw: u8, + value: RDP, + }, + /// BOR reset Level + BOR_LEV: u3, + reserved12: u1, + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + /// nRST_SHDW + nRST_SHDW: u1, + reserved16: u1, + /// Independent watchdog selection + IDWG_SW: u1, + /// Independent watchdog counter freeze in Stop mode + IWDG_STOP: u1, + /// Independent watchdog counter freeze in Standby mode + IWDG_STDBY: u1, + /// Window watchdog selection + WWDG_SW: u1, + reserved22: u2, + /// PB4 pull-up enable + PB4_PUPEN: u1, + /// Boot configuration + nBOOT1: u1, + /// SRAM2 parity check enable + SRAM2_PE: u1, + /// SRAM2 Erase when system reset + SRAM2_RST: u1, + /// nSWBOOT0 + nSWBOOT0: u1, + /// nBOOT0 option bit + nBOOT0: u1, + /// NRST_MODE + NRST_MODE: packed union { + raw: u2, + value: NRST_MODE, + }, + /// Internal reset holder enable bit + IRHEN: u1, + padding: u1, }), - reserved48: [16]u8, - /// JPEG control register - JPEG_CR: mmio.Mmio(packed struct(u32) { - /// JPEG Core Enable - JCEN: u1, - /// Input FIFO Threshold Interrupt Enable - IFTIE: u1, - /// Input FIFO Not Full Interrupt Enable - IFNFIE: u1, - /// Output FIFO Threshold Interrupt Enable - OFTIE: u1, - /// Output FIFO Not Empty Interrupt Enable - OFNEIE: u1, - /// End of Conversion Interrupt Enable - EOCIE: u1, - /// Header Parsing Done Interrupt Enable - HPDIE: u1, - reserved11: u4, - /// Input DMA Enable - IDMAEN: u1, - /// Output DMA Enable - ODMAEN: u1, - /// Input FIFO Flush - IFF: u1, - /// Output FIFO Flush - OFF: u1, + /// Flash Bank 1 PCROP Start address register + PCROP1SR: mmio.Mmio(packed struct(u32) { + /// Bank 1 PCROP area start offset + PCROP1_STRT: u15, padding: u17, }), - /// JPEG status register - JPEG_SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Input FIFO Threshold Flag - IFTF: u1, - /// Input FIFO Not Full Flag - IFNFF: u1, - /// Output FIFO Threshold Flag - OFTF: u1, - /// Output FIFO Not Empty Flag - OFNEF: u1, - /// End of Conversion Flag - EOCF: u1, - /// Header Parsing Done Flag - HPDF: u1, - /// Codec Operation Flag - COF: u1, - padding: u24, - }), - /// JPEG clear flag register - JPEG_CFR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// Clear End of Conversion Flag - CEOCF: u1, - /// Clear Header Parsing Done Flag - CHPDF: u1, - padding: u25, + /// Flash Bank 1 PCROP End address register + PCROP1ER: mmio.Mmio(packed struct(u32) { + /// Bank 1 PCROP area end offset + PCROP1_END: u15, + reserved31: u16, + /// PCROP area preserved when RDP level decreased + PCROP_RDP: u1, }), - reserved64: [4]u8, - /// JPEG data input register - JPEG_DIR: mmio.Mmio(packed struct(u32) { - /// Data Input FIFO - DATAIN: u32, + /// Flash Bank 1 WRP area A address register + WRP1AR: mmio.Mmio(packed struct(u32) { + /// Bank 1 WRP first area start offset + WRP1A_STRT: u7, + reserved16: u9, + /// Bank 1 WRP first area A end offset + WRP1A_END: u7, + padding: u9, }), - /// JPEG data output register - JPEG_DOR: mmio.Mmio(packed struct(u32) { - /// Data Output FIFO - DATAOUT: u32, + /// Flash Bank 1 WRP area B address register + WRP1BR: mmio.Mmio(packed struct(u32) { + /// Bank 1 WRP second area B end offset + WRP1B_STRT: u7, + reserved16: u9, + /// Bank 1 WRP second area B start offset + WRP1B_END: u7, + padding: u9, }), - reserved80: [8]u8, - /// JPEG quantization tables - QMEM0_0: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, - }), - /// JPEG quantization tables - QMEM0_1: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved112: [60]u8, + /// securable area bank1 register + SEC1R: mmio.Mmio(packed struct(u32) { + /// SEC_SIZE1 + SEC_SIZE1: u8, + reserved16: u8, + /// used to force boot from user area + BOOT_LOCK: u1, + padding: u15, }), - /// JPEG quantization tables - QMEM0_2: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + }; + }; + + pub const flash_h5 = struct { + pub const BOOTR_SECBOOT_LOCK = enum(u8) { + /// The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + B_0xB4 = 0xb4, + /// The BOOT_UBE, SWAP_ BANK and SECBOOTADD can still be modified following their individual rules. + B_0xC3 = 0xc3, + _, + }; + + pub const CODE_OP = enum(u3) { + /// No flash operation on going during previous reset + B_0x0 = 0x0, + /// Single write operation interrupted + B_0x1 = 0x1, + /// OBK alternate sector erase + B_0x2 = 0x2, + /// Sector erase operation interrupted + B_0x3 = 0x3, + /// Bank erase operation interrupted + B_0x4 = 0x4, + /// Mass erase operation interrupted + B_0x5 = 0x5, + /// Option change operation interrupted + B_0x6 = 0x6, + /// OBK swap sector request + B_0x7 = 0x7, + }; + + pub const NSBOOTR_NSBOOT_LOCK = enum(u8) { + /// The NSBOOTADD is frozen. SWAP_ BANK can only be modified with TZEN set to 0xB4 (enabled). + B_0xB4 = 0xb4, + /// The SWAP_ BANK and NSBOOTADD can still be modified following their individual rules. + B_0xC3 = 0xc3, + _, + }; + + pub const NSCR_BKSEL = enum(u1) { + /// Bank1 is selected for Bank erase / sector erase / interrupt enable + B_0x0 = 0x0, + /// Bank2 is selected for BER / SER + B_0x1 = 0x1, + }; + + pub const NSPRIV = enum(u1) { + /// access to non secure registers is always granted + B_0x0 = 0x0, + /// access to non secure registers is denied in case of unprivileged access. + B_0x1 = 0x1, + }; + + pub const OPTCR_SWAP_BANK = enum(u1) { + /// Bank1 and Bank2 not swapped + B_0x0 = 0x0, + /// Bank1 and Bank2 swapped + B_0x1 = 0x1, + }; + + pub const OPTSR_BKPRAM_ECC = enum(u1) { + /// BKPRAM ECC check enabled + B_0x0 = 0x0, + /// BKPRAM ECC check disabled + B_0x1 = 0x1, + }; + + pub const OPTSR_BOOT_UBE = enum(u8) { + /// OEM-iRoT (user flash) selected. In Open PRODUCT_STATE this value selects bootloader. Defaut value. + B_0xB4 = 0xb4, + /// ST-iRoT (system flash) selected + B_0xC3 = 0xc3, + _, + }; + + pub const OPTSR_BOR_LEV = enum(u2) { + /// BOR Level 2, the threshold level is medium (around 2.4 V) + B_0x1 = 0x1, + /// BOR Level 3, the threshold level is high (around 2.7 V) + B_0x2 = 0x2, + _, + }; + + pub const OPTSR_IO_VDDIO_HSLV = enum(u1) { + /// High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7�V) + B_0x0 = 0x0, + /// High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7�V) + B_0x1 = 0x1, + }; + + pub const OPTSR_IO_VDD_HSLV = enum(u1) { + /// High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7�V) + B_0x0 = 0x0, + /// High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7�V) + B_0x1 = 0x1, + }; + + pub const OPTSR_IWDG_STDBY = enum(u1) { + /// Independent watchdog frozen in Standby mode + B_0x0 = 0x0, + /// Independent watchdog keep running in Standby mode. + B_0x1 = 0x1, + }; + + pub const OPTSR_IWDG_STOP = enum(u1) { + /// Independent watchdog frozen in system Stop mode + B_0x0 = 0x0, + /// Independent watchdog keep running in system Stop mode. + B_0x1 = 0x1, + }; + + pub const OPTSR_IWDG_SW = enum(u1) { + /// IWDG watchdog is controlled by hardware + B_0x0 = 0x0, + /// IWDG watchdog is controlled by software + B_0x1 = 0x1, + }; + + pub const OPTSR_NRST_STDBY = enum(u1) { + /// a reset is generated when entering Standby mode on core domain + B_0x0 = 0x0, + /// no reset generated when entering Standby mode on core domain. + B_0x1 = 0x1, + }; + + pub const OPTSR_NRST_STOP = enum(u1) { + /// a reset is generated when entering Stop mode on core domain + B_0x0 = 0x0, + /// no reset generated when entering Stop mode on core domain. + B_0x1 = 0x1, + }; + + pub const OPTSR_SRAM_ECC = enum(u1) { + /// SRAM2 ECC check enabled + B_0x0 = 0x0, + /// SRAM2 ECC check disabled + B_0x1 = 0x1, + }; + + pub const OPTSR_SWAP_BANK = enum(u1) { + /// Bank1 and Bank2 not swapped + B_0x0 = 0x0, + /// Bank1 and Bank2 swapped + B_0x1 = 0x1, + }; + + pub const OPTSR_TZEN = enum(u8) { + /// TrustZone enabled. + B_0xB4 = 0xb4, + /// TrustZone disabled + B_0xC3 = 0xc3, + _, + }; + + pub const OPTSR_WWDG_SW = enum(u1) { + /// WWDG watchdog is controlled by hardware + B_0x0 = 0x0, + /// WWDG watchdog is controlled by software + B_0x1 = 0x1, + }; + + pub const PRIVBBR_PRIVBB = enum(u32) { + /// sectors (32 * (x-1) + y) in bank 2 is unprivileged + B_0x0 = 0x0, + /// sector (32 * (x-1) + y) in bank 2 is privileged + B_0x1 = 0x1, + _, + }; + + pub const SECBBR_SECBB = enum(u32) { + /// sectors (32 * (x-1) + y) in bank 2 is non secure + B_0x0 = 0x0, + /// sector (32 * (x-1) + y) in bank 2 is secure + B_0x1 = 0x1, + _, + }; + + pub const SECBOOTR_SECBOOT_LOCK = enum(u8) { + /// The BOOT_UBE and SECBOOTADD are frozen. SWAP_ BANK can only be modified with TZEN set to 0xC3 (disabled). + B_0xB4 = 0xb4, + /// The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. + B_0xC3 = 0xc3, + _, + }; + + pub const SECCR_BKSEL = enum(u1) { + /// Bank1 is selected for Bank erase / sector erase / interrupt enable + B_0x0 = 0x0, + /// Bank2 is selected for BER / SER + B_0x1 = 0x1, + }; + + pub const SPRIV = enum(u1) { + /// access to secure registers is always granted + B_0x0 = 0x0, + /// access to secure registers is denied in case of unprivileged access. + B_0x1 = 0x1, + }; + + /// FLASH address block description + pub const FLASH = extern struct { + /// FLASH access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Read latency These bits are used to control the number of wait states used during read operations on both nonvolatile memory banks. The application software has to program them to the correct value depending on the embedded flash memory interface frequency and voltage conditions. ... Note: No check is performed by hardware to verify that the configuration is correct. + LATENCY: u4, + /// Flash signal delay These bits are used to control the delay between nonvolatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded flash memory interface frequency. Please refer to Table�44 for details. Note: No check is performed to verify that the configuration is correct. Note: Two WRHIGHFREQ values can be selected for some frequencies. + WRHIGHFREQ: u2, + reserved8: u2, + /// Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account. Bits used to control the prefetch. + PRFTEN: u1, + padding: u23, }), - /// JPEG quantization tables - QMEM0_3: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH non-secure key register + NSKEYR: u32, + /// FLASH secure key register + SECKEYR: u32, + /// FLASH option key register + OPTKEYR: u32, + /// FLASH non-secure OBK key register + NSOBKKEYR: u32, + /// FLASH secure OBK key register + SECOBKKEYR: u32, + /// FLASH operation status register + OPSR: mmio.Mmio(packed struct(u32) { + /// Interrupted operation address + ADDR_OP: u20, + reserved21: u1, + /// Flash high-cycle data area operation interrupted It indicates if flash high-cycle data area is concerned by operation. + DATA_OP: u1, + /// Interrupted operation bank It indicates which bank was concerned by operation. + BK_OP: u1, + /// Operation in system flash memory interrupted Indicates that reset interrupted an ongoing operation in system flash. + SYSF_OP: u1, + /// OTP operation interrupted Indicates that reset interrupted an ongoing operation in OTP area (or OBKeys area). + OTP_OP: u1, + reserved29: u4, + /// Flash memory operation code + CODE_OP: packed union { + raw: u3, + value: CODE_OP, + }, }), - /// JPEG quantization tables - QMEM0_4: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH option control register + OPTCR: mmio.Mmio(packed struct(u32) { + /// FLASH_OPTCR lock option configuration bit The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset. It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change. + OPTLOCK: u1, + /// Option byte start change option configuration bit OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It is set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It is reseted at the same time as BSY bit. The user application cannot modify any FLASH_XXX_PRG flash interface register until the option change operation has been completed. Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in nonvolatile memory. + OPTSTRT: u1, + reserved31: u29, + /// Bank swapping option configuration bit SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR. + SWAP_BANK: packed union { + raw: u1, + value: OPTCR_SWAP_BANK, + }, }), - /// JPEG quantization tables - QMEM0_5: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH non-secure status register + NSSR: mmio.Mmio(packed struct(u32) { + /// busy flag BSY flag indicates that a flash memory is busy by an operation (write, erase, option byte change, OBK operation). It is set at the beginning of a flash memory operation and cleared when the operation finishes, or an error occurs. + BSY: u1, + /// write buffer not empty flag WBNE flag is set when the flash interface is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_NSCR the embedded flash memory detects an error that involves data loss This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. + WBNE: u1, + reserved3: u1, + /// data buffer not empty flag DBNE flag is set when the flash interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free. + DBNE: u1, + reserved16: u12, + /// end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register. + EOP: u1, + /// write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR. + WRPERR: u1, + /// programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR. + PGSERR: u1, + /// strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR. + STRBERR: u1, + /// inconsistency error flag NSINCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears NSINCERR. + INCERR: u1, + /// OBK general error flag OBKERR flag is raised when the OBK-HDPL signal from the SBS does not match the HDPL value associated with the key slot during access to the key location. Alternatively also when the ALT_SECT is unexpectedly changed while the write buffer is being filled. + OBKERR: u1, + /// OBK write error flag OBKWERR flag is raised when the address is not virgin on a write access to the OBK storage. Alternatively also when the OBK selector in the alternate sector is not virgin during a swap operation. + OBKWERR: u1, + /// Option byte change error flag OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1. Writing 1 to CLR_OPTCHANGEERR of register FLASH_NSCCR clears OPTCHANGEERR. Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set. + OPTCHANGEERR: u1, + padding: u8, }), - /// JPEG quantization tables - QMEM0_6: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH secure status register + SECSR: mmio.Mmio(packed struct(u32) { + /// busy flag BSY flag indicates that a FLASH memory is busy (write, erase, option byte change, OBK operations). It is set at the beginning of a flash memory operation and cleared when the operation finishes or an error occurs. + BSY: u1, + /// write buffer not empty flag WBNE flag is set when the flash interface is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_SECCR the flash interface detects an error that involves data loss This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. + WBNE: u1, + reserved3: u1, + /// data buffer not empty flag DBNE flag is set when the embedded flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free. + DBNE: u1, + reserved16: u12, + /// end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register. + EOP: u1, + /// write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR. + WRPERR: u1, + /// programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR. + PGSERR: u1, + /// strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR. + STRBERR: u1, + /// inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR. + INCERR: u1, + /// OBK general error flag OBKERR flag is raised when the OBK-HDPL signal from the SBS does not match the HDPL value associated with the key slot during access to the key location. Alternatively also when the ALT_SECT is unexpectedly changed while the write buffer is being filled. + OBKERR: u1, + /// OBK write error flag OBKWERR flag is raised when the address is not virgin on a write access to the OBK storage. Alternatively also when the OBK selector in the alternate sector is not virgin during a swap operation. + OBKWERR: u1, + padding: u9, }), - /// JPEG quantization tables - QMEM0_7: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH non-secure control register + NSCR: mmio.Mmio(packed struct(u32) { + /// configuration lock bit This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change. + LOCK: u1, + /// programming control bit PG can be programmed only when LOCK is cleared to 0. PG allows programming in Bank1 and Bank2. + PG: u1, + /// sector erase request Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. + SER: u1, + /// erase request Setting BER bit to 1 requests a bank erase operation (user flash memory only). BER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. Note: Write protection error is triggered when a bank erase is required and some sectors are protected. + BER: u1, + /// write forcing control bit FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. The embedded flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error. Write forcing is effective only if the write buffer is not empty and was filled by non-secure access (in particular, FW does not start several write operations when the force-write operations are performed consecutively). Since there is just one write buffer, FW can force a write in bank1 or bank2. + FW: u1, + /// erase start control bit STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software. + STRT: u1, + /// sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0. .. + SNB: u7, + reserved15: u2, + /// Mass erase request Setting MER bit to 1 requests a mass erase operation (user flash memory only). MER can be programmed only when LOCK is cleared to 0. If BER or SER are both set, a PGSERR is raised. Error is triggered when a mass erase is required and some sectors are protected. + MER: u1, + /// end of operation interrupt control bit Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0. + EOPIE: u1, + /// write protection error interrupt enable bit When this bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0. + WRPERRIE: u1, + /// programming sequence error interrupt enable bit When this bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0. + PGSERRIE: u1, + /// strobe error interrupt enable bit When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0. + STRBERRIE: u1, + /// inconsistency error interrupt enable bit When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0. + INCERRIE: u1, + /// OBK general error interrupt enable bit OBKERRIE enables generating an interrupt in case of OBK specific access error. This bit can be programmed only when LOCK bit is cleared to 0. + OBKERRIE: u1, + /// OBK write error interrupt enable bit OBKWERRIE enables generation of interrupt in case of OBK specific write error. This bit can be programmed only when LOCK bit is cleared to 0. + OBKWERRIE: u1, + /// Option byte change error interrupt enable bit This bit controls if an interrupt must be generated when an error occurs during an option byte change. It can be programmed only when LOCK bit is cleared to 0. + OPTCHANGEERRIE: u1, + reserved31: u7, + /// Bank selector bit BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored. + BKSEL: packed union { + raw: u1, + value: NSCR_BKSEL, + }, }), - /// JPEG quantization tables - QMEM0_8: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH secure control register + SECCR: mmio.Mmio(packed struct(u32) { + /// configuration lock bit This bit locks the FLASH_SECCR register. The correct write sequence to FLASH_SECKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_SECCR register do not change. + LOCK: u1, + /// programming control bit PG can be programmed only when LOCK is cleared to 0. PG allows programming in Bank1 and Bank2. + PG: u1, + /// sector erase request Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. If BER and MER are also set, a PGSERR is raised. + SER: u1, + /// erase request Setting BER bit to 1 requests a bank erase operation (user flash memory only). BER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. Note: Write protection error is triggered when a bank erase is required and some sectors are protected. + BER: u1, + /// write forcing control bit FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. The embedded flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error. Write forcing is effective only if the write buffer is not empty and was filled by secure access (in particular, FW does not start several write operations when the force-write operations are performed consecutively). Since there is just one write buffer, FW can force a write in bank1 or bank2. + FW: u1, + /// erase start control bit STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. STRT is reseted at the end of the operation or when an error occurs. It cannot be reset by software. + STRT: u1, + /// sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0. .. + SNB: u7, + reserved15: u2, + /// mass erase request Setting MER bit to 1 requests a mass erase operation (user flash memory only). MER can be programmed only when LOCK is cleared to 0. If BER or SER are also set, a PGSERR is raised. Error is triggered when a mass erase is required and some sectors are protected. + MER: u1, + /// end of operation interrupt control bit Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program/erase operation. EOPIE can be programmed only when LOCK is cleared to 0. + EOPIE: u1, + /// write protection error interrupt enable bit When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0. + WRPERRIE: u1, + /// programming sequence error interrupt enable bit When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0. + PGSERRIE: u1, + /// strobe error interrupt enable bit When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0. + STRBERRIE: u1, + /// inconsistency error interrupt enable bit When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0. + INCERRIE: u1, + /// OBK general error interrupt enable bit OBKERRIE enables generating an interrupt in case of OBK specific access error. OBKERRIE can be programmed only when LOCK is cleared to 0. + OBKERRIE: u1, + /// OBK write error interrupt enable bit OBKWERRIE enables generation of interrupt in case of OBK specific write error. OBKWERRIE can be programmed only when LOCK is cleared to 0. + OBKWERRIE: u1, + reserved29: u6, + /// Flash memory security state invert. This bit inverts the flash memory security state. + INV: u1, + reserved31: u1, + /// bank selector bit BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored. + BKSEL: packed union { + raw: u1, + value: SECCR_BKSEL, + }, }), - /// JPEG quantization tables - QMEM0_9: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH non-secure clear control register + NSCCR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// EOP flag clear bit Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register. + CLR_EOP: u1, + /// WRPERR flag clear bit Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register. + CLR_WRPERR: u1, + /// PGSERR flag clear bit Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register. + CLR_PGSERR: u1, + /// STRBERR flag clear bit Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register. + CLR_STRBERR: u1, + /// INCERR flag clear bit Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register. + CLR_INCERR: u1, + /// OBKERR flag clear bit. Setting this bit to 1 resets to 0 OBKERR flag in FLASH_NSSR register. + CLR_OBKERR: u1, + /// OBKWERR flag clear bit. Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_NSSR register. + CLR_OBKWERR: u1, + /// Clear the flag corresponding flag in FLASH_NSSR by writing this bit. + CLR_OPTCHANGEERR: u1, + padding: u8, }), - /// JPEG quantization tables - QMEM0_10: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH secure clear control register + SECCCR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// EOP flag clear bit Setting this bit to 1 resets to 0 EOP flag in FLASH_SECSR register. + CLR_EOP: u1, + /// WRPERR flag clear bit Setting this bit to 1 resets to 0 WRPERR flag in FLASH_SECSR register. + CLR_WRPERR: u1, + /// PGSERR flag clear bit Setting this bit to 1 resets to 0 PGSERR flag in FLASH_SECSR register. + CLR_PGSERR: u1, + /// STRBERR flag clear bit Setting this bit to 1 resets to 0 STRBERR flag in FLASH_SECSR register. + CLR_STRBERR: u1, + /// INCERR flag clear bit Setting this bit to 1 resets to 0 INCERR flag in FLASH_SECSR register. + CLR_INCERR: u1, + /// OBKWERR flag clear bit Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_SECSR register. + CLR_OBKERR: u1, + /// OBKWERR flag clear bit Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_SECSR register. + CLR_OBKWERR: u1, + padding: u9, }), - /// JPEG quantization tables - QMEM0_11: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved60: [4]u8, + /// FLASH privilege configuration register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// privilege attribute for secure registers + SPRIV: packed union { + raw: u1, + value: SPRIV, + }, + /// privilege attribute for non secure registers + NSPRIV: packed union { + raw: u1, + value: NSPRIV, + }, + padding: u30, }), - /// JPEG quantization tables - QMEM0_12: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH non-secure OBK configuration register + NSOBKCFGR: mmio.Mmio(packed struct(u32) { + /// OBKCFGR lock option configuration bit This bit locks the FLASH_NSOBKCFGR register. The correct write sequence to FLASH_NSOBKKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSOBKKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change. + LOCK: u1, + /// OBK swap sector request bit When set, all the OBKs which have not been updated in the alternate sector is copied from current sector to alternate one. The SWAP_OFFSET value must be a certain minimum value in order for the swap to be launched in OBK-HDPL ≠ 0. Minimum value is 16 for OBK-HDPL = 1, 144 for OBK-HDPL = 2 and 192 for OBK-HDPL = 3. + SWAP_SECT_REQ: u1, + /// alternate sector bit This bit must not change while filling the write buffer, otherwise an error (OBKERR) is generated + ALT_SECT: u1, + /// alternate sector erase bit When ALT_SECT bit is set, use this bit to generate an erase command for the OBK alternate sector. It is set only by Software and cleared when the OBK swap operation is completed or an error occurs (PGSERR). It is reseted at the same time as BUSY bit. + ALT_SECT_ERASE: u1, + reserved16: u12, + /// Key index (offset /16 bits) pointing for next swap. 0x01 means that only the first OBK data (128 bits) is copied from current to alternate OBK sector 0x02 means that the two first OBK data is copied … … + SWAP_OFFSET: u9, + padding: u7, }), - /// JPEG quantization tables - QMEM0_13: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH secure OBK configuration register + SECOBKCFGR: mmio.Mmio(packed struct(u32) { + /// OBKCFGR lock option configuration bit This bit locks the FLASH_OBKCFGR register. The correct write sequence to FLASH_SECOBKKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_SECOBKKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change. + LOCK: u1, + /// OBK swap sector request bit When set, all the OBKs which have not been updated in the alternate sector is copied from current sector to alternate one. The SWAP_OFFSET value must be a certain minimum value in order for the swap to be launched in OBK-HDPL ≠ 0. Minimum value is 16 for OBK-HDPL = 1, 144 for OBK-HDPL = 2 and 192 for OBK-HDPL = 3. + SWAP_SECT_REQ: u1, + /// alternate sector bit This bit must not change while filling the write buffer, otherwise an error is generated + ALT_SECT: u1, + /// alternate sector erase bit When ALT_SECT bit is set, use this bit to generate an erase command for the OBK alternate sector. It is set only by Software and cleared when the OBK swap operation is completed or an error occurs (PGSERR). It is reseted at the same time as the BUSY bit. + ALT_SECT_ERASE: u1, + reserved16: u12, + /// key index (offset /16 bits) pointing for next swap. … + SWAP_OFFSET: u9, + padding: u7, }), - /// JPEG quantization tables - QMEM0_14: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH HDP extension register + HDPEXTR: mmio.Mmio(packed struct(u32) { + /// HDP area extension in 8�Kbytes sectors in Bank1. Extension is added after the HDP1_END sector (included). + HDP1_EXT: u7, + reserved16: u9, + /// HDP area extension in 8�Kbytes sectors in bank 2. Extension is added after the HDP2_END sector (included). + HDP2_EXT: u7, + padding: u9, }), - /// JPEG quantization tables - QMEM0_15: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved80: [4]u8, + /// FLASH option status register + OPTSR_CUR: mmio.Mmio(packed struct(u32) { + /// Brownout level option status bit These bits reflects the power level that generates a system reset. 00 or 11: BOR Level 1, the threshold level is low (around 2.1�V) + BOR_LEV: packed union { + raw: u2, + value: OPTSR_BOR_LEV, + }, + /// Brownout high enable + BORH_EN: u1, + /// IWDG control mode option status bit + IWDG_SW: packed union { + raw: u1, + value: OPTSR_IWDG_SW, + }, + /// WWDG control mode option status bit + WWDG_SW: packed union { + raw: u1, + value: OPTSR_WWDG_SW, + }, + reserved6: u1, + /// Core domain Stop entry reset option status bit + NRST_STOP: packed union { + raw: u1, + value: OPTSR_NRST_STOP, + }, + /// Core domain Standby entry reset option status bit + NRST_STDBY: packed union { + raw: u1, + value: OPTSR_NRST_STDBY, + }, + /// Life state code (based on Hamming 8,4). More information in Section�7.6.11: Product state transitions. + PRODUCT_STATE: u8, + /// High-speed IO at low VDD voltage configuration bit. This bit can be set only with VDD below 2.7�V. + IO_VDD_HSLV: packed union { + raw: u1, + value: OPTSR_IO_VDD_HSLV, + }, + /// High-speed IO at low VDDIO2 voltage configuration bit. This bit can be set only with VDDIO2 below 2.7�V. + IO_VDDIO2_HSLV: packed union { + raw: u1, + value: OPTSR_IO_VDDIO_HSLV, + }, + reserved20: u2, + /// IWDG Stop mode freeze option status bit When set the independent watchdog IWDG is in system Stop mode. + IWDG_STOP: packed union { + raw: u1, + value: OPTSR_IWDG_STOP, + }, + /// IWDG Standby mode freeze option status bit When set the independent watchdog IWDG is frozen in system Standby mode. + IWDG_STDBY: packed union { + raw: u1, + value: OPTSR_IWDG_STDBY, + }, + /// Available only on cryptography enabled devices. Unique boot entry control, selects either ST or OEM iRoT for secure boot. + BOOT_UBE: packed union { + raw: u8, + value: OPTSR_BOOT_UBE, + }, + reserved31: u1, + /// Bank swapping option status bit SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset. + SWAP_BANK: packed union { + raw: u1, + value: OPTSR_SWAP_BANK, + }, }), - /// JPEG quantization tables - QMEM1_0: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH option status register + OPTSR_PRG: mmio.Mmio(packed struct(u32) { + /// Brownout level option status bit These bits reflects the power level that generates a system reset. 00 or 11: BOR Level 1, the threshold level is low (around 2.1�V) + BOR_LEV: packed union { + raw: u2, + value: OPTSR_BOR_LEV, + }, + /// Brownout high enable + BORH_EN: u1, + /// IWDG control mode option status bit + IWDG_SW: packed union { + raw: u1, + value: OPTSR_IWDG_SW, + }, + /// WWDG control mode option status bit + WWDG_SW: packed union { + raw: u1, + value: OPTSR_WWDG_SW, + }, + reserved6: u1, + /// Core domain Stop entry reset option status bit + NRST_STOP: packed union { + raw: u1, + value: OPTSR_NRST_STOP, + }, + /// Core domain Standby entry reset option status bit + NRST_STDBY: packed union { + raw: u1, + value: OPTSR_NRST_STDBY, + }, + /// Life state code (based on Hamming 8,4). More information in Section�7.6.11: Product state transitions. + PRODUCT_STATE: u8, + /// High-speed IO at low VDD voltage configuration bit. This bit can be set only with VDD below 2.7�V. + IO_VDD_HSLV: packed union { + raw: u1, + value: OPTSR_IO_VDD_HSLV, + }, + /// High-speed IO at low VDDIO2 voltage configuration bit. This bit can be set only with VDDIO2 below 2.7�V. + IO_VDDIO2_HSLV: packed union { + raw: u1, + value: OPTSR_IO_VDDIO_HSLV, + }, + reserved20: u2, + /// IWDG Stop mode freeze option status bit When set the independent watchdog IWDG is in system Stop mode. + IWDG_STOP: packed union { + raw: u1, + value: OPTSR_IWDG_STOP, + }, + /// IWDG Standby mode freeze option status bit When set the independent watchdog IWDG is frozen in system Standby mode. + IWDG_STDBY: packed union { + raw: u1, + value: OPTSR_IWDG_STDBY, + }, + /// Available only on cryptography enabled devices. Unique boot entry control, selects either ST or OEM iRoT for secure boot. + BOOT_UBE: packed union { + raw: u8, + value: OPTSR_BOOT_UBE, + }, + reserved31: u1, + /// Bank swapping option status bit SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset. + SWAP_BANK: packed union { + raw: u1, + value: OPTSR_SWAP_BANK, + }, }), - /// JPEG quantization tables - QMEM1_1: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved96: [8]u8, + /// FLASH non-secure EPOCH register + NSEPOCHR_CUR: mmio.Mmio(packed struct(u32) { + /// Non-volatile non-secure EPOCH counter + NS_EPOCH: u24, + padding: u8, }), - /// JPEG quantization tables - QMEM1_2: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved104: [4]u8, + /// FLASH secure EPOCH register + SECEPOCHR_CUR: mmio.Mmio(packed struct(u32) { + /// Non-volatile secure EPOCH counter + SEC_EPOCH: u24, + padding: u8, }), - /// JPEG quantization tables - QMEM1_3: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved112: [4]u8, + /// FLASH option status register 2 + OPTSR2_CUR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// SRAM1 and SRAM3 erase upon system reset + SRAM13_RST: u1, + /// SRAM2 erase when system reset + SRAM2_RST: u1, + /// Backup RAM ECC detection and correction disable + BKPRAM_ECC: packed union { + raw: u1, + value: OPTSR_BKPRAM_ECC, + }, + /// SRAM3 ECC detection and correction disable + SRAM3_ECC: packed union { + raw: u1, + value: OPTSR_SRAM_ECC, + }, + /// SRAM2 ECC detection and correction disable + SRAM2_ECC: packed union { + raw: u1, + value: OPTSR_SRAM_ECC, + }, + reserved8: u1, + /// USB power delivery configuration option bit + USBPD_DIS: u1, + reserved24: u15, + /// TrustZone enable configuration bits This bit enables the device is in TrustZone mode during an option byte change. + TZEN: packed union { + raw: u8, + value: OPTSR_TZEN, + }, }), - /// JPEG quantization tables - QMEM1_4: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH option status register 2 + OPTSR2_PRG: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// SRAM1 and SRAM3 erase upon system reset + SRAM13_RST: u1, + /// SRAM2 erase when system reset + SRAM2_RST: u1, + /// Backup RAM ECC detection and correction disable + BKPRAM_ECC: packed union { + raw: u1, + value: OPTSR_BKPRAM_ECC, + }, + /// SRAM3 ECC detection and correction disable + SRAM3_ECC: packed union { + raw: u1, + value: OPTSR_SRAM_ECC, + }, + /// SRAM2 ECC detection and correction disable + SRAM2_ECC: packed union { + raw: u1, + value: OPTSR_SRAM_ECC, + }, + reserved8: u1, + /// USB power delivery configuration option bit + USBPD_DIS: u1, + reserved24: u15, + /// TrustZone enable configuration bits This bit enables the device is in TrustZone mode during an option byte change. + TZEN: packed union { + raw: u8, + value: OPTSR_TZEN, + }, }), - /// JPEG quantization tables - QMEM1_5: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved128: [8]u8, + /// FLASH non-secure boot register + NSBOOTR_CUR: mmio.Mmio(packed struct(u32) { + /// A field locking the values of SWAP_ BANK, and NSBOOTADD settings. + NSBOOT_LOCK: packed union { + raw: u8, + value: NSBOOTR_NSBOOT_LOCK, + }, + /// Non secure unique boot entry address These bits allow configuring the Non secure BOOT address + NSBOOTADD: u24, }), - /// JPEG quantization tables - QMEM1_6: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH non-secure boot register + NSBOOTR_PRG: mmio.Mmio(packed struct(u32) { + /// A field locking the values of SWAP_ BANK, and NSBOOTADD settings. + NSBOOT_LOCK: packed union { + raw: u8, + value: NSBOOTR_NSBOOT_LOCK, + }, + /// Non secure unique boot entry address These bits allow configuring the Non secure BOOT address + NSBOOTADD: u24, }), - /// JPEG quantization tables - QMEM1_7: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH secure boot register + SECBOOTR_CUR: mmio.Mmio(packed struct(u32) { + /// A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. + SECBOOT_LOCK: packed union { + raw: u8, + value: SECBOOTR_SECBOOT_LOCK, + }, + /// Unique boot entry secure address These bits reflect the Secure UBE address + SECBOOTADD: u24, }), - /// JPEG quantization tables - QMEM1_8: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH secure boot register + BOOTR_PRG: mmio.Mmio(packed struct(u32) { + /// A field locking the values of UBE, SWAP_ BANK, and SECBOOTADD setting. + SECBOOT_LOCK: packed union { + raw: u8, + value: BOOTR_SECBOOT_LOCK, + }, + /// Secure unique boot entry address. These bits allow configuring the secure UBE address. + SECBOOTADD: u24, }), - /// JPEG quantization tables - QMEM1_9: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH non-secure OTP block lock + OTPBLR_CUR: mmio.Mmio(packed struct(u32) { + /// OTP block lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR. LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked. When one block is locked, it’s not possible to remove the write protection. Also if not locked, it is not possible to erase OTP words. + LOCKBL: u32, }), - /// JPEG quantization tables - QMEM1_10: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH non-secure OTP block lock + OTPBLR_PRG: mmio.Mmio(packed struct(u32) { + /// OTP block lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR. LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked. When one block is locked, it’s not possible to remove the write protection. Also if not locked, it is not possible to erase OTP words. + LOCKBL: u32, }), - /// JPEG quantization tables - QMEM1_11: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved160: [8]u8, + /// FLASH secure block based register for Bank 1 + SECBB1R1: mmio.Mmio(packed struct(u32) { + /// Secure/non-secure flash Bank 2 sector attribute + SECBB: packed union { + raw: u32, + value: SECBBR_SECBB, + }, }), - /// JPEG quantization tables - QMEM1_12: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH secure block based register for Bank 1 + SECBB1R2: mmio.Mmio(packed struct(u32) { + /// Secure/non-secure flash Bank 2 sector attribute + SECBB: packed union { + raw: u32, + value: SECBBR_SECBB, + }, }), - /// JPEG quantization tables - QMEM1_13: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH secure block based register for Bank 1 + SECBB1R3: mmio.Mmio(packed struct(u32) { + /// Secure/non-secure flash Bank 2 sector attribute + SECBB: packed union { + raw: u32, + value: SECBBR_SECBB, + }, }), - /// JPEG quantization tables - QMEM1_14: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH secure block based register for Bank 1 + SECBB1R4: mmio.Mmio(packed struct(u32) { + /// Secure/non-secure flash Bank 2 sector attribute + SECBB: packed union { + raw: u32, + value: SECBBR_SECBB, + }, }), - /// JPEG quantization tables - QMEM1_15: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved192: [16]u8, + /// FLASH privilege block based register for Bank 1 + PRIVBB1R1: mmio.Mmio(packed struct(u32) { + /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute + PRIVBB: packed union { + raw: u32, + value: PRIVBBR_PRIVBB, + }, }), - /// JPEG quantization tables - QMEM2_0: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH privilege block based register for Bank 1 + PRIVBB1R2: mmio.Mmio(packed struct(u32) { + /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute + PRIVBB: packed union { + raw: u32, + value: PRIVBBR_PRIVBB, + }, }), - /// JPEG quantization tables - QMEM2_1: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH privilege block based register for Bank 1 + PRIVBB1R3: mmio.Mmio(packed struct(u32) { + /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute + PRIVBB: packed union { + raw: u32, + value: PRIVBBR_PRIVBB, + }, }), - /// JPEG quantization tables - QMEM2_2: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH privilege block based register for Bank 1 + PRIVBB1R4: mmio.Mmio(packed struct(u32) { + /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute + PRIVBB: packed union { + raw: u32, + value: PRIVBBR_PRIVBB, + }, }), - /// JPEG quantization tables - QMEM2_3: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved224: [16]u8, + /// FLASH security watermark for Bank 1 + SECWM1R_CUR: mmio.Mmio(packed struct(u32) { + /// Bank2 security WM area start sector + SECWMSTRT: u7, + reserved16: u9, + /// Bank2 security WM end sector + SECWMEND: u7, + padding: u9, }), - /// JPEG quantization tables - QMEM2_4: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH security watermark for Bank 1 + SECWM1R_PRG: mmio.Mmio(packed struct(u32) { + /// Bank2 security WM area start sector + SECWMSTRT: u7, + reserved16: u9, + /// Bank2 security WM end sector + SECWMEND: u7, + padding: u9, }), - /// JPEG quantization tables - QMEM2_5: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH write sector group protection for Bank 1 + WRP1R_CUR: mmio.Mmio(packed struct(u32) { + /// Bank1 sector group protection option status byte Setting WRPSG1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected) Bit 0: Group embedding sectors 0 to 3 Bit 1: Group embedding sectors 4 to 7 Bit N: Group embedding sectors 4 x N to 4 x N + 3 Bit 31: Group embedding sectors 124 to 127 + WRPSG: u32, }), - /// JPEG quantization tables - QMEM2_6: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH write sector group protection for Bank 1 + WRP1R_PRG: mmio.Mmio(packed struct(u32) { + /// Bank1 sector group protection option status byte Setting WRPSG1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected) Bit 0: Group embedding sectors 0 to 3 Bit 1: Group embedding sectors 4 to 7 Bit N: Group embedding sectors 4 x N to 4 x N + 3 Bit 31: Group embedding sectors 124 to 127 + WRPSG: u32, }), - /// JPEG quantization tables - QMEM2_7: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH data sector configuration Bank 1 + EDATA1R_CUR: mmio.Mmio(packed struct(u32) { + /// EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank 1 There is no hardware effect to those bits. They shall be managed by ST tools in Flasher. ... Note: 111: The eight last sectors of the Bank 1 are reserved for flash high-cycle data + EDATA1_STRT: u3, + reserved15: u12, + /// Bank 1 flash high-cycle data enable + EDATA1_EN: u1, + padding: u16, }), - /// JPEG quantization tables - QMEM2_8: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH data sector configuration Bank 1 + EDATA1R_PRG: mmio.Mmio(packed struct(u32) { + /// EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank 1 There is no hardware effect to those bits. They shall be managed by ST tools in Flasher. ... Note: 111: The eight last sectors of the Bank 1 are reserved for flash high-cycle data + EDATA1_STRT: u3, + reserved15: u12, + /// Bank 1 flash high-cycle data enable + EDATA1_EN: u1, + padding: u16, }), - /// JPEG quantization tables - QMEM2_9: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH HDP Bank 1 configuration + HDP1R_CUR: mmio.Mmio(packed struct(u32) { + /// HDPL barrier start set in number of 8-Kbyte sectors + HDP1_STRT: u7, + reserved16: u9, + /// HDPL barrier end set in number of 8-Kbyte sectors + HDP1_END: u7, + padding: u9, }), - /// JPEG quantization tables - QMEM2_10: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH HDP Bank 1 configuration + HDP1R_PRG: mmio.Mmio(packed struct(u32) { + /// HDPL barrier start set in number of 8-Kbyte sectors + HDP1_STRT: u7, + reserved16: u9, + /// HDPL barrier end set in number of 8-Kbyte sectors + HDP1_END: u7, + padding: u9, }), - /// JPEG quantization tables - QMEM2_11: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH ECC correction register + ECCCORR: mmio.Mmio(packed struct(u32) { + /// ECC error address When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The flash interface programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved. The address in ADDR_ECC is relative to the flash memory area where the error occurred (user flash memory, system flash memory, data area, read-only/OTP area). + ADDR_ECC: u16, + reserved20: u4, + /// Single ECC error corrected in flash OB Keys storage area. It indicates the OBK storage concerned by ECC error. + OBK_ECC: u1, + /// ECC fail for corrected ECC error in flash high-cycle data area It indicates if flash high-cycle data area is concerned by ECC error. + EDATA_ECC: u1, + /// ECC fail bank for corrected ECC error It indicates which bank is concerned by ECC error + BK_ECC: u1, + /// ECC fail for corrected ECC error in system flash memory It indicates if system flash memory is concerned by ECC error. + SYSF_ECC: u1, + /// OTP ECC error bit This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield. + OTP_ECC: u1, + /// ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation. + ECCCIE: u1, + reserved30: u4, + /// ECC correction set by hardware when single ECC error has been detected and corrected. Cleared by writing 1. + ECCC: u1, + padding: u1, }), - /// JPEG quantization tables - QMEM2_12: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH ECC detection register + ECCDETR: mmio.Mmio(packed struct(u32) { + /// ECC error address When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The flash interface programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved. The address in ADDR_ECC is relative to the flash memory area where the error occurred (user flash memory, system flash memory, data area, read-only/OTP area). + ADDR_ECC: u16, + reserved20: u4, + /// ECC fail double ECC error in flash OB Keys storage area. It indicates the OBK storage concerned by ECC error. + OBK_ECC: u1, + /// ECC fail double ECC error in flash high-cycle data area It indicates if flash high-cycle data area is concerned by ECC error. + EDATA_ECC: u1, + /// ECC fail bank for double ECC error It indicates which bank is concerned by ECC error + BK_ECC: u1, + /// ECC fail for double ECC error in system flash memory It indicates if system flash memory is concerned by ECC error. + SYSF_ECC: u1, + /// OTP ECC error bit This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield. + OTP_ECC: u1, + reserved31: u6, + /// ECC detection Set by hardware when two ECC error has been detected. When this bit is set, a NMI is generated. Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors. + ECCD: u1, }), - /// JPEG quantization tables - QMEM2_13: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH ECC data + ECCDR: mmio.Mmio(packed struct(u32) { + /// ECC error data When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit data (data area, read-only/OTP area), the failing data is read to this register. By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory. + DATA_ECC: u16, + padding: u16, }), - /// JPEG quantization tables - QMEM2_14: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved416: [148]u8, + /// FLASH secure block-based register for Bank 2 + SECBB2R1: mmio.Mmio(packed struct(u32) { + /// Secure/non-secure flash Bank 2 sector attribute + SECBB: packed union { + raw: u32, + value: SECBBR_SECBB, + }, }), - /// JPEG quantization tables - QMEM2_15: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH secure block-based register for Bank 2 + SECBB2R2: mmio.Mmio(packed struct(u32) { + /// Secure/non-secure flash Bank 2 sector attribute + SECBB: packed union { + raw: u32, + value: SECBBR_SECBB, + }, }), - /// JPEG quantization tables - QMEM3_0: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH secure block-based register for Bank 2 + SECBB2R3: mmio.Mmio(packed struct(u32) { + /// Secure/non-secure flash Bank 2 sector attribute + SECBB: packed union { + raw: u32, + value: SECBBR_SECBB, + }, }), - /// JPEG quantization tables - QMEM3_1: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH secure block-based register for Bank 2 + SECBB2R4: mmio.Mmio(packed struct(u32) { + /// Secure/non-secure flash Bank 2 sector attribute + SECBB: packed union { + raw: u32, + value: SECBBR_SECBB, + }, }), - /// JPEG quantization tables - QMEM3_2: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved448: [16]u8, + /// FLASH privilege block-based register for Bank 2 + PRIVBB2R1: mmio.Mmio(packed struct(u32) { + /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute + PRIVBB: packed union { + raw: u32, + value: PRIVBBR_PRIVBB, + }, }), - /// JPEG quantization tables - QMEM3_3: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH privilege block-based register for Bank 2 + PRIVBB2R2: mmio.Mmio(packed struct(u32) { + /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute + PRIVBB: packed union { + raw: u32, + value: PRIVBBR_PRIVBB, + }, }), - /// JPEG quantization tables - QMEM3_4: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH privilege block-based register for Bank 2 + PRIVBB2R3: mmio.Mmio(packed struct(u32) { + /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute + PRIVBB: packed union { + raw: u32, + value: PRIVBBR_PRIVBB, + }, }), - /// JPEG quantization tables - QMEM3_5: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH privilege block-based register for Bank 2 + PRIVBB2R4: mmio.Mmio(packed struct(u32) { + /// Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute + PRIVBB: packed union { + raw: u32, + value: PRIVBBR_PRIVBB, + }, }), - /// JPEG quantization tables - QMEM3_6: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + reserved480: [16]u8, + /// FLASH security watermark for Bank 2 + SECWM2R_CUR: mmio.Mmio(packed struct(u32) { + /// Bank2 security WM area start sector + SECWMSTRT: u7, + reserved16: u9, + /// Bank2 security WM end sector + SECWMEND: u7, + padding: u9, }), - /// JPEG quantization tables - QMEM3_7: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH security watermark for Bank 2 + SECWM2R_PRG: mmio.Mmio(packed struct(u32) { + /// Bank2 security WM area start sector + SECWMSTRT: u7, + reserved16: u9, + /// Bank2 security WM end sector + SECWMEND: u7, + padding: u9, }), - /// JPEG quantization tables - QMEM3_8: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH write sector group protection for Bank 2 + WRP2R_CUR: mmio.Mmio(packed struct(u32) { + /// Bank1 sector group protection option status byte Setting WRPSG1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected) Bit 0: Group embedding sectors 0 to 3 Bit 1: Group embedding sectors 4 to 7 Bit N: Group embedding sectors 4 x N to 4 x N + 3 Bit 31: Group embedding sectors 124 to 127 + WRPSG: u32, }), - /// JPEG quantization tables - QMEM3_9: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH write sector group protection for Bank 2 + WRP2R_PRG: mmio.Mmio(packed struct(u32) { + /// Bank1 sector group protection option status byte Setting WRPSG1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected) Bit 0: Group embedding sectors 0 to 3 Bit 1: Group embedding sectors 4 to 7 Bit N: Group embedding sectors 4 x N to 4 x N + 3 Bit 31: Group embedding sectors 124 to 127 + WRPSG: u32, }), - /// JPEG quantization tables - QMEM3_10: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH data sectors configuration Bank 2 + EDATA2R_CUR: mmio.Mmio(packed struct(u32) { + /// EDATA2_STRT contains the start sectors of the flash high-cycle data area in Bank 2 There is no hardware effect to those bits. They shall be managed by ST tools in Flasher. ... Note: 111: The eight last sectors of the Bank 2 are reserved for flash high-cycle data. + EDATA2_STRT: u3, + reserved15: u12, + /// Bank 2 flash high-cycle data enable + EDATA2_EN: u1, + padding: u16, }), - /// JPEG quantization tables - QMEM3_11: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH data sector configuration Bank 2 + EDATA2R_PRG: mmio.Mmio(packed struct(u32) { + /// EDATA2_STRT contains the start sectors of the flash high-cycle data area in Bank 2 There is no hardware effect to those bits. They shall be managed by ST tools in Flasher. ... Note: 111: The eight last sectors of the Bank 2 are reserved for flash high-cycle data. + EDATA2_STRT: u3, + reserved15: u12, + /// Bank 2 flash high-cycle data enable + EDATA2_EN: u1, + padding: u16, }), - /// JPEG quantization tables - QMEM3_12: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH HDP Bank 2 configuration + HDP2R_CUR: mmio.Mmio(packed struct(u32) { + /// HDPL barrier start set in number of 8-Kbyte sectors + HDP2_STRT: u7, + reserved16: u9, + /// HDPL barrier end set in number of 8-Kbyte sectors + HDP2_END: u7, + padding: u9, }), - /// JPEG quantization tables - QMEM3_13: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH HDP Bank 2 configuration + HDP2R_PRG: mmio.Mmio(packed struct(u32) { + /// HDPL barrier start set in number of 8-Kbyte sectors + HDP2_STRT: u7, + reserved16: u9, + /// HDPL barrier end set in number of 8-Kbyte sectors + HDP2_END: u7, + padding: u9, }), - /// JPEG quantization tables - QMEM3_14: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + }; + }; + + pub const flash_h50 = struct { + pub const BKSEL = enum(u1) { + /// Bank1 is selected for Bank erase / sector erase / interrupt enable + BANK1 = 0x0, + /// Bank1 is selected for Bank erase / sector erase / interrupt enable + BANK2 = 0x1, + }; + + pub const CODE_OP = enum(u3) { + /// No Flash operation on going during previous reset + B_0x0 = 0x0, + /// Single write operation interrupted + B_0x1 = 0x1, + /// Sector erase operation interrupted + B_0x3 = 0x3, + /// Bank erase operation interrupted + B_0x4 = 0x4, + /// Mass erase operation interrupted + B_0x5 = 0x5, + /// Option change operation interrupted + B_0x6 = 0x6, + _, + }; + + pub const NSBOOTR_NSBOOT_LOCK = enum(u8) { + /// The NSBOOTADD and SWAP_BANK are frozen. + B_0xB4 = 0xb4, + /// The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. + B_0xC3 = 0xc3, + _, + }; + + pub const NSPRIV = enum(u1) { + /// access to non secure registers is always granted + B_0x0 = 0x0, + /// access to non secure registers is denied in case of non privileged access. + B_0x1 = 0x1, + }; + + pub const OPTSR_BKPRAM_ECC = enum(u1) { + /// BKPRAM ECC check enabled + B_0x0 = 0x0, + /// BKPRAM ECC check disabled + B_0x1 = 0x1, + }; + + pub const OPTSR_BOR_LEV = enum(u2) { + /// BOR OFF, POR/PDR reset threshold level is applied + B_0x0 = 0x0, + /// BOR Level 1, the threshold level is low (around 2.1 V) + B_0x1 = 0x1, + /// BOR Level 2, the threshold level is medium (around 2.4 V) + B_0x2 = 0x2, + /// BOR Level 3, the threshold level is high (around 2.7 V) + B_0x3 = 0x3, + }; + + pub const OPTSR_IO_VDDIO_HSLV = enum(u1) { + /// High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) + B_0x0 = 0x0, + /// High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) + B_0x1 = 0x1, + }; + + pub const OPTSR_IO_VDD_HSLV = enum(u1) { + /// High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) + B_0x0 = 0x0, + /// High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) + B_0x1 = 0x1, + }; + + pub const OPTSR_IWDG_STDBY = enum(u1) { + /// Independent watchdog frozen in Standby mode + B_0x0 = 0x0, + /// Independent watchdog keep running in Standby mode. + B_0x1 = 0x1, + }; + + pub const OPTSR_IWDG_STOP = enum(u1) { + /// Independent watchdog frozen in system Stop mode + B_0x0 = 0x0, + /// Independent watchdog keep running in system Stop mode. + B_0x1 = 0x1, + }; + + pub const OPTSR_IWDG_SW = enum(u1) { + /// IWDG watchdog is controlled by hardware + B_0x0 = 0x0, + /// IWDG watchdog is controlled by software + B_0x1 = 0x1, + }; + + pub const OPTSR_NRST_SHDW = enum(u1) { + /// a reset is generated when entering Shutdown mode on core domain + B_0x0 = 0x0, + /// no reset generated when entering Shutdown mode on core domain. + B_0x1 = 0x1, + }; + + pub const OPTSR_NRST_STDBY = enum(u1) { + /// a reset is generated when entering Standby mode on core domain + B_0x0 = 0x0, + /// no reset generated when entering Standby mode on core domain. + B_0x1 = 0x1, + }; + + pub const OPTSR_NRST_STOP = enum(u1) { + /// a reset is generated when entering Stop mode on core domain + B_0x0 = 0x0, + /// no reset generated when entering Stop mode on core domain. + B_0x1 = 0x1, + }; + + pub const OPTSR_SRAM_ECC = enum(u1) { + /// SRAM2 ECC check enabled + B_0x0 = 0x0, + /// SRAM2 ECC check disabled + B_0x1 = 0x1, + }; + + pub const OPTSR_WWDG_SW = enum(u1) { + /// WWDG watchdog is controlled by hardware + B_0x0 = 0x0, + /// WWDG watchdog is controlled by software + B_0x1 = 0x1, + }; + + pub const PRIVBB = enum(u8) { + /// sectors y in bank 1 is non privileged + B_0x0 = 0x0, + /// sector y in bank 1 is privileged + B_0x1 = 0x1, + _, + }; + + pub const PRODUCT_STATE = enum(u8) { + /// Provisioning + PROVISIONING = 0x17, + /// iROT-Provisioned + IROT_PROVISIONED = 0x2e, + /// Locked + LOCKED = 0x5c, + /// Closed + CLOSED = 0x72, + /// Regression + REGRESSION = 0x9a, + /// Open + OPEN = 0xed, + _, + }; + + /// FLASH address block description + pub const FLASH = extern struct { + /// FLASH access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. ... Note: No check is performed by hardware to verify that the configuration is correct. + LATENCY: u4, + /// Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to for details. Note: No check is performed to verify that the configuration is correct. Two WRHIGHFREQ values can be selected for some frequencies. + WRHIGHFREQ: u2, + reserved8: u2, + /// Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account. Bits used to control the prefetch. + PRFTEN: u1, + /// Smart prefetch enable. When bit value is modified, user must read back ACR register to be sure S_PRFTEN has been taken into account. Bits used to control the prefetch functionality. + S_PRFTEN: u1, + padding: u22, }), - /// JPEG quantization tables - QMEM3_15: mmio.Mmio(packed struct(u32) { - /// QMem RAM - QMem_RAM: u32, + /// FLASH key register + NSKEYR: u32, + reserved12: [4]u8, + /// FLASH option key register + OPTKEYR: u32, + reserved24: [8]u8, + /// FLASH operation status register + OPSR: mmio.Mmio(packed struct(u32) { + /// Interrupted operation address. + ADDR_OP: u20, + reserved22: u2, + /// Interrupted operation bank It indicates which bank was concerned by operation. + BK_OP: u1, + /// Operation in system Flash memory interrupted Indicates that reset interrupted an ongoing operation in System Flash. + SYSF_OP: u1, + /// OTP operation interrupted Indicates that reset interrupted an ongoing operation in OTP area. + OTP_OP: u1, + reserved29: u4, + /// Flash memory operation code + CODE_OP: packed union { + raw: u3, + value: CODE_OP, + }, }), - /// JPEG HuffMin tables - HUFFMIN_0: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + /// FLASH option control register + OPTCR: mmio.Mmio(packed struct(u32) { + /// FLASH_OPTCR lock option configuration bit The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset. It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change. + OPTLOCK: u1, + /// Option byte start change option configuration bit OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It’s set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It’s reseted at the same time as BSY bit. The user application cannot modify any FLASH_XXX_PRG embedded Flash memory register until the option change operation has been completed. Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in non-volatile memory. + OPTSTRT: u1, + reserved31: u29, + /// Bank swapping option configuration bit SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR. + SWAP_BANK: u1, }), - /// JPEG HuffMin tables - HUFFMIN_1: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + /// FLASH non-secure status register + NSSR: mmio.Mmio(packed struct(u32) { + /// busy flag BSY flag indicates that a Flash memory is busy by an operation (write, erase, option byte change). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs. + BSY: u1, + /// write buffer not empty flag WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_NSCR the embedded Flash memory detects an error that involves data loss This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. + WBNE: u1, + reserved3: u1, + /// data buffer not empty flag DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free. + DBNE: u1, + reserved16: u12, + /// end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register. + EOP: u1, + /// write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR. + WRPERR: u1, + /// programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR. + PGSERR: u1, + /// strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR. + STRBERR: u1, + /// inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears INCERR. + INCERR: u1, + reserved23: u2, + /// Option byte change error flag OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1. Writing 1 to CLR_OPTCHANGEERR of register FLASH_CCR clears OPTCHANGEERR. Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set. + OPTCHANGEERR: u1, + padding: u8, }), - /// JPEG HuffMin tables - HUFFMIN_2: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + /// FLASH secure status register + SECSR: mmio.Mmio(packed struct(u32) { + /// busy flag BSY flag indicates that a FLASH memory is busy by an operation (write, erase, option byte change, OBK operations, PUF operation). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs. + SECBSY: u1, + /// write buffer not empty flag WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_SECCR the embedded Flash memory detects an error that involves data loss This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. + SECWBNE: u1, + reserved3: u1, + /// data buffer not empty flag DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free. + SECDBNE: u1, + reserved16: u12, + /// end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register. + SECEOP: u1, + /// write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR. + SECWRPERR: u1, + /// programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR. + SECPGSERR: u1, + /// strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR. + SECSTRBERR: u1, + /// inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR. + SECINCERR: u1, + padding: u11, }), - /// JPEG HuffMin tables - HUFFMIN_3: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + /// FLASH Non Secure control register + NSCR: mmio.Mmio(packed struct(u32) { + /// configuration lock bit This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change. + LOCK: u1, + /// programming control bit PG can be programmed only when LOCK is cleared to 0. PG allows programming in Bank1 and Bank2. + PG: u1, + /// sector erase request Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. + SER: u1, + /// erase request Setting BER bit to 1 requests a bank erase operation (user Flash memory only). BER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. Note: Write protection error is triggered when a bank erase is required and some sectors are protected. + BER: u1, + /// write forcing control bit FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. The embedded Flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively). Since there is just one write buffer, FW can force a write in bank1 or bank2. + FW: u1, + /// erase start control bit STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software. + STRT: u1, + /// sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0. ... + SNB: u3, + reserved15: u6, + /// Mass erase request Setting MER bit to 1 requests a mass erase operation (user Flash memory only). MER can be programmed only when LOCK is cleared to 0. If BER or SER are both set, a PGSERR is raised. Error is triggered when a mass erase is required and some sectors are protected. + MER: u1, + /// end of operation interrupt control bit Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0. + EOPIE: u1, + /// write protection error interrupt enable bit When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0. + WRPERRIE: u1, + /// programming sequence error interrupt enable bit When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0. + PGSERRIE: u1, + /// strobe error interrupt enable bit When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0. + STRBERRIE: u1, + /// inconsistency error interrupt enable bit When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0. + INCERRIE: u1, + reserved23: u2, + /// Option byte change error interrupt enable bit OPTCHANGEERRIE bit controls if an interrupt has to be generated when an error occurs during an option byte change. This bit can be programmed only when LOCK bit is cleared to 0. + OPTCHANGEERRIE: u1, + reserved31: u7, + /// Bank selector bit BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored. + BKSEL: packed union { + raw: u1, + value: BKSEL, + }, }), - /// JPEG HuffMin tables - HUFFMIN_4: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + reserved48: [4]u8, + /// FLASH non-secure clear control register + NSCCR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// EOP flag clear bit Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register. + CLR_EOP: u1, + /// WRPERR flag clear bit Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register. + CLR_WRPERR: u1, + /// PGSERR flag clear bit Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register. + CLR_PGSERR: u1, + /// STRBERR flag clear bit Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register. + CLR_STRBERR: u1, + /// INCERR flag clear bit Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register. + CLR_INCERR: u1, + reserved23: u2, + /// Clear the flag corresponding flag in FLASH_NSSR by writing this bit. + CLR_OPTCHANGEERR: u1, + padding: u8, }), - /// JPEG HuffMin tables - HUFFMIN_5: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + reserved60: [8]u8, + /// FLASH privilege configuration register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// privilege attribute for non secure registers + NSPRIV: packed union { + raw: u1, + value: NSPRIV, + }, + padding: u30, }), - /// JPEG HuffMin tables - HUFFMIN_6: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + reserved72: [8]u8, + /// FLASH HDP extension register + HDPEXTR: mmio.Mmio(packed struct(u32) { + /// HDP area extension in 8 Kbytes sectors in Bank1. Extension is added after the HDP1_END sector. + HDP1_EXT: u3, + reserved16: u13, + /// HDP area extension in 8 Kbytes sectors in Bank2. Extension is added after the HDP2_END sector. + HDP2_EXT: u3, + padding: u13, }), - /// JPEG HuffMin tables - HUFFMIN_7: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + reserved80: [4]u8, + /// FLASH option status register + OPTSR_CUR: mmio.Mmio(packed struct(u32) { + /// Brownout level option status bit These bits reflects the power level that generates a system reset. + BOR_LEV: packed union { + raw: u2, + value: OPTSR_BOR_LEV, + }, + /// Brownout high enable status bit + BORH_EN: u1, + /// IWDG control mode option status bit + IWDG_SW: packed union { + raw: u1, + value: OPTSR_IWDG_SW, + }, + /// WWDG control mode option status bit + WWDG_SW: packed union { + raw: u1, + value: OPTSR_WWDG_SW, + }, + /// Core domain Shutdown entry reset option status bit + NRST_SHDW: packed union { + raw: u1, + value: OPTSR_NRST_SHDW, + }, + /// Core domain Stop entry reset option status bit + NRST_STOP: packed union { + raw: u1, + value: OPTSR_NRST_STOP, + }, + /// Core domain Standby entry reset option status bit + NRST_STDBY: packed union { + raw: u1, + value: OPTSR_NRST_STDBY, + }, + /// Life state code (based on Hamming 8,4). + PRODUCT_STATE: packed union { + raw: u8, + value: PRODUCT_STATE, + }, + /// High-speed IO at low VDD voltage status bit. This bit can be set only with VDD below 2.5 V. + IO_VDD_HSLV: packed union { + raw: u1, + value: OPTSR_IO_VDD_HSLV, + }, + /// High-speed IO at low VDDIO2 voltage status bit. This bit can be set only with VDDIO2 below 2.5 V. + IO_VDDIO2_HSLV: packed union { + raw: u1, + value: OPTSR_IO_VDDIO_HSLV, + }, + reserved20: u2, + /// IWDG Stop mode freeze option status bit When set the independent watchdog IWDG is in system Stop mode. + IWDG_STOP: packed union { + raw: u1, + value: OPTSR_IWDG_STOP, + }, + /// IWDG Standby mode freeze option status bit When set the independent watchdog IWDG is frozen in system Standby mode. + IWDG_STDBY: packed union { + raw: u1, + value: OPTSR_IWDG_STDBY, + }, + reserved31: u9, + /// Bank swapping option status bit SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset. + SWAP_BANK: u1, }), - /// JPEG HuffMin tables - HUFFMIN_8: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + /// FLASH option status register + OPTSR_PRG: mmio.Mmio(packed struct(u32) { + /// Brownout level option status bit These bits reflects the power level that generates a system reset. + BOR_LEV: packed union { + raw: u2, + value: OPTSR_BOR_LEV, + }, + /// Brownout high enable status bit + BORH_EN: u1, + /// IWDG control mode option status bit + IWDG_SW: packed union { + raw: u1, + value: OPTSR_IWDG_SW, + }, + /// WWDG control mode option status bit + WWDG_SW: packed union { + raw: u1, + value: OPTSR_WWDG_SW, + }, + /// Core domain Shutdown entry reset option status bit + NRST_SHDW: packed union { + raw: u1, + value: OPTSR_NRST_SHDW, + }, + /// Core domain Stop entry reset option status bit + NRST_STOP: packed union { + raw: u1, + value: OPTSR_NRST_STOP, + }, + /// Core domain Standby entry reset option status bit + NRST_STDBY: packed union { + raw: u1, + value: OPTSR_NRST_STDBY, + }, + /// Life state code (based on Hamming 8,4). + PRODUCT_STATE: packed union { + raw: u8, + value: PRODUCT_STATE, + }, + /// High-speed IO at low VDD voltage status bit. This bit can be set only with VDD below 2.5 V. + IO_VDD_HSLV: packed union { + raw: u1, + value: OPTSR_IO_VDD_HSLV, + }, + /// High-speed IO at low VDDIO2 voltage status bit. This bit can be set only with VDDIO2 below 2.5 V. + IO_VDDIO2_HSLV: packed union { + raw: u1, + value: OPTSR_IO_VDDIO_HSLV, + }, + reserved20: u2, + /// IWDG Stop mode freeze option status bit When set the independent watchdog IWDG is in system Stop mode. + IWDG_STOP: packed union { + raw: u1, + value: OPTSR_IWDG_STOP, + }, + /// IWDG Standby mode freeze option status bit When set the independent watchdog IWDG is frozen in system Standby mode. + IWDG_STDBY: packed union { + raw: u1, + value: OPTSR_IWDG_STDBY, + }, + reserved31: u9, + /// Bank swapping option status bit SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset. + SWAP_BANK: u1, }), - /// JPEG HuffMin tables - HUFFMIN_9: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + reserved112: [24]u8, + /// FLASH option status register 2 + OPTSR2_CUR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// SRAM2 erase when system reset + SRAM2_RST: u1, + /// Backup RAM ECC detection and correction disable + BKPRAM_ECC: packed union { + raw: u1, + value: OPTSR_BKPRAM_ECC, + }, + reserved6: u1, + /// SRAM2 ECC detection and correction disable + SRAM2_ECC: packed union { + raw: u1, + value: OPTSR_SRAM_ECC, + }, + reserved9: u2, + /// SRAM1 erase upon system reset + SRAM1_RST: u1, + /// SRAM1 ECC detection and correction disable + SRAM1_ECC: packed union { + raw: u1, + value: OPTSR_SRAM_ECC, + }, + padding: u21, }), - /// JPEG HuffMin tables - HUFFMIN_10: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + /// FLASH option status register 2 + OPTSR2_PRG: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// SRAM2 erase when system reset + SRAM2_RST: u1, + /// Backup RAM ECC detection and correction disable + BKPRAM_ECC: packed union { + raw: u1, + value: OPTSR_BKPRAM_ECC, + }, + reserved6: u1, + /// SRAM2 ECC detection and correction disable + SRAM2_ECC: packed union { + raw: u1, + value: OPTSR_SRAM_ECC, + }, + reserved9: u2, + /// SRAM1 erase upon system reset + SRAM1_RST: u1, + /// SRAM1 ECC detection and correction disable + SRAM1_ECC: packed union { + raw: u1, + value: OPTSR_SRAM_ECC, + }, + padding: u21, }), - /// JPEG HuffMin tables - HUFFMIN_11: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + reserved128: [8]u8, + /// FLASH non-secure unique boot entry register + NSBOOTR_CUR: mmio.Mmio(packed struct(u32) { + /// A field locking the values of SWAP_BANK, and NSBOOTADD settings. + NSBOOT_LOCK: packed union { + raw: u8, + value: NSBOOTR_NSBOOT_LOCK, + }, + /// unique boot entry address These bits reflect the UBE address + NSBOOTADD: u24, }), - /// JPEG HuffMin tables - HUFFMIN_12: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + /// FLASH non-secure unique boot entry address + NSBOOTR_PRG: mmio.Mmio(packed struct(u32) { + /// A field locking the values of SWAP_BANK, and NSBOOTADD settings. + NSBOOT_LOCK: packed union { + raw: u8, + value: NSBOOTR_NSBOOT_LOCK, + }, + /// unique boot entry address These bits reflect the UBE address + NSBOOTADD: u24, }), - /// JPEG HuffMin tables - HUFFMIN_13: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + reserved144: [8]u8, + /// FLASH non-secure OTP block lock + OTPBLR_CUR: mmio.Mmio(packed struct(u32) { + /// OTP block lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR. LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked. When one block is locked, it is not possible to remove the write protection. LOCKBL bits can be set if the corresponding bit in FLASH_OTPBLR_CUR is cleared. + LOCKBL: u32, }), - /// JPEG HuffMin tables - HUFFMIN_14: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + /// FLASH non-secure OTP block lock + OTPBLR_PRG: mmio.Mmio(packed struct(u32) { + /// OTP block lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR. LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked. When one block is locked, it is not possible to remove the write protection. LOCKBL bits can be set if the corresponding bit in FLASH_OTPBLR_CUR is cleared. + LOCKBL: u32, }), - /// JPEG HuffMin tables - HUFFMIN_15: mmio.Mmio(packed struct(u32) { - /// HuffMin RAM - HuffMin_RAM: u32, + reserved192: [40]u8, + /// FLASH privilege register for bank 1 + PRIVBB1R: mmio.Mmio(packed struct(u32) { + /// Privileged / unprivileged 8 Kbytes Flash Bank1 sector attribute (y = 0 to 7) + PRIVBB: packed union { + raw: u8, + value: PRIVBB, + }, + padding: u24, }), - /// JPEG HuffSymb tables - HUFFBASE0: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + reserved232: [36]u8, + /// FLASH write sector protection for Bank1 + WRPSGN1R_CUR: mmio.Mmio(packed struct(u32) { + /// Bank2 sector protection option status byte Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected) + WRPSG: u8, + padding: u24, }), - /// JPEG HuffSymb tables - HUFFBASE1: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH write sector protection for Bank1 + WRPSGN1R_PRG: mmio.Mmio(packed struct(u32) { + /// Bank2 sector protection option status byte Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected) + WRPSG: u8, + padding: u24, }), - /// JPEG HuffSymb tables - HUFFBASE2: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + reserved248: [8]u8, + /// FLASH HDP Bank1 register + HDP1R_CUR: mmio.Mmio(packed struct(u32) { + /// HDPL barrier start set in number of 8 Kbytes sectors + HDP1_STRT: u3, + reserved16: u13, + /// HDPL barrier end set in number of 8 Kbytes sectors + HDP1_END: u3, + padding: u13, }), - /// JPEG HuffSymb tables - HUFFBASE3: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH HDP Bank1 register + HDP1R_PRG: mmio.Mmio(packed struct(u32) { + /// HDPL barrier start set in number of 8 Kbytes sectors + HDP1_STRT: u3, + reserved16: u13, + /// HDPL barrier end set in number of 8 Kbytes sectors + HDP1_END: u3, + padding: u13, }), - /// JPEG HuffSymb tables - HUFFBASE4: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH Flash ECC correction register + ECCCORR: mmio.Mmio(packed struct(u32) { + /// ECC error address When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved. The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area). + ADDR_ECC: u16, + reserved22: u6, + /// ECC bank flag for corrected ECC error It indicates which bank is concerned by ECC error + BK_ECC: u1, + /// ECC flag for corrected ECC error in system FLASH It indicates if system Flash memory is concerned by ECC error. + SYSF_ECC: u1, + /// OTP ECC error bit This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield. + OTP_ECC: u1, + /// ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation. + ECCCIE: u1, + reserved30: u4, + /// ECC correction set by hardware when single ECC error has been detected and corrected. Cleared by writing 1. + ECCC: u1, + padding: u1, }), - /// JPEG HuffSymb tables - HUFFBASE5: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH ECC detection register + ECCDETR: mmio.Mmio(packed struct(u32) { + /// ECC error address When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved. The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area). + ADDR_ECC: u16, + reserved22: u6, + /// ECC fail bank for double ECC Error It indicates which bank is concerned by ECC error + BK_ECC: u1, + /// ECC fail for double ECC error in system Flash memory It indicates if system Flash memory is concerned by ECC error. + SYSF_ECC: u1, + /// OTP ECC error bit This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bit field. + OTP_ECC: u1, + reserved31: u6, + /// ECC detection set by hardware when two ECC error has been detected. When this bit is set, a NMI is generated. Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors. + ECCD: u1, }), - /// JPEG HuffSymb tables - HUFFBASE6: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH ECC data + ECCDR: mmio.Mmio(packed struct(u32) { + /// ECC error data When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit of data (data area, read-only/OTP area), the failing data is read to this register. By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory. + DATA_ECC: u16, + padding: u16, }), - /// JPEG HuffSymb tables - HUFFBASE7: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + reserved488: [220]u8, + /// FLASH write sector protection for Bank2 + WRPSGN2R_CUR: mmio.Mmio(packed struct(u32) { + /// Bank2 sector protection option status byte Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected) + WRPSG: u8, + padding: u24, }), - /// JPEG HuffSymb tables - HUFFBASE8: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH write sector protection for Bank2 + WRPSGN2R_PRG: mmio.Mmio(packed struct(u32) { + /// Bank2 sector protection option status byte Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected) + WRPSG: u8, + padding: u24, }), - /// JPEG HuffSymb tables - HUFFBASE9: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + reserved504: [8]u8, + /// FLASH HDP Bank2 register + HDP2R_CUR: mmio.Mmio(packed struct(u32) { + /// Bank 2 HDPL barrier start set in number of 8 Kbytes sectors + HDP2_STRT: u3, + reserved16: u13, + /// Bank 2 HDPL barrier end set in number of 8 Kbytes sectors + HDP2_END: u3, + padding: u13, }), - /// JPEG HuffSymb tables - HUFFBASE10: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH HDP Bank2 register + HDP2R_PRG: mmio.Mmio(packed struct(u32) { + /// Bank 2 HDPL barrier start set in number of 8 Kbytes sectors + HDP2_STRT: u3, + reserved16: u13, + /// Bank 2 HDPL barrier end set in number of 8 Kbytes sectors + HDP2_END: u3, + padding: u13, }), - /// JPEG HuffSymb tables - HUFFBASE11: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, - }), - /// JPEG HuffSymb tables - HUFFBASE12: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + }; + }; + + pub const flash_h7 = struct { + /// Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R + pub const BANK = extern struct { + /// FLASH key register for bank 1 + KEYR: u32, + reserved8: [4]u8, + /// FLASH control register for bank 1 + CR: mmio.Mmio(packed struct(u32) { + /// Bank 1 configuration lock bit + LOCK: u1, + /// Bank 1 program enable bit + PG: u1, + /// Bank 1 sector erase request + SER: u1, + /// Bank 1 erase request + BER: u1, + /// Bank 1 program size + PSIZE: u2, + /// Bank 1 write forcing control bit + FW: u1, + /// Bank 1 bank or sector erase start control bit + START: u1, + /// Bank 1 sector erase selection number + SNB: u3, + reserved15: u4, + /// Bank 1 CRC control bit + CRC_EN: u1, + /// Bank 1 end-of-program interrupt control bit + EOPIE: u1, + /// Bank 1 write protection error interrupt enable bit + WRPERRIE: u1, + /// Bank 1 programming sequence error interrupt enable bit + PGSERRIE: u1, + /// Bank 1 strobe error interrupt enable bit + STRBERRIE: u1, + reserved21: u1, + /// Bank 1 inconsistency error interrupt enable bit + INCERRIE: u1, + /// Bank 1 write/erase error interrupt enable bit + OPERRIE: u1, + /// Bank 1 read protection error interrupt enable bit + RDPERRIE: u1, + /// Bank 1 secure error interrupt enable bit + RDSERRIE: u1, + /// Bank 1 ECC single correction error interrupt enable bit + SNECCERRIE: u1, + /// Bank 1 ECC double detection error interrupt enable bit + DBECCERRIE: u1, + /// Bank 1 end of CRC calculation interrupt enable bit + CRCENDIE: u1, + /// Bank 1 CRC read error interrupt enable bit + CRCRDERRIE: u1, + padding: u3, }), - /// JPEG HuffSymb tables - HUFFBASE13: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH status register for bank 1 + SR: mmio.Mmio(packed struct(u32) { + /// Bank 1 ongoing program flag + BSY: u1, + /// Bank 1 write buffer not empty flag + WBNE: u1, + /// Bank 1 wait queue flag + QW: u1, + /// Bank 1 CRC busy flag + CRC_BUSY: u1, + reserved16: u12, + /// Bank 1 end-of-program flag + EOP: u1, + /// Bank 1 write protection error flag + WRPERR: u1, + /// Bank 1 programming sequence error flag + PGSERR: u1, + /// Bank 1 strobe error flag + STRBERR: u1, + reserved21: u1, + /// Bank 1 inconsistency error flag + INCERR: u1, + /// Bank 1 write/erase error flag + OPERR: u1, + /// Bank 1 read protection error flag + RDPERR: u1, + /// Bank 1 secure error flag + RDSERR: u1, + /// Bank 1 single correction error flag + SNECCERR1: u1, + /// Bank 1 ECC double detection error flag + DBECCERR: u1, + /// Bank 1 CRC-complete flag + CRCEND: u1, + /// Bank 1 CRC read error flag + CRCRDERR: u1, + padding: u3, }), - /// JPEG HuffSymb tables - HUFFBASE14: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH clear control register for bank 1 + CCR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Bank 1 EOP1 flag clear bit + CLR_EOP: u1, + /// Bank 1 WRPERR1 flag clear bit + CLR_WRPERR: u1, + /// Bank 1 PGSERR1 flag clear bi + CLR_PGSERR: u1, + /// Bank 1 STRBERR1 flag clear bit + CLR_STRBERR: u1, + reserved21: u1, + /// Bank 1 INCERR1 flag clear bit + CLR_INCERR: u1, + /// Bank 1 OPERR1 flag clear bit + CLR_OPERR: u1, + /// Bank 1 RDPERR1 flag clear bit + CLR_RDPERR: u1, + /// Bank 1 RDSERR1 flag clear bit + CLR_RDSERR: u1, + /// Bank 1 SNECCERR1 flag clear bit + CLR_SNECCERR: u1, + /// Bank 1 DBECCERR1 flag clear bit + CLR_DBECCERR: u1, + /// Bank 1 CRCEND1 flag clear bit + CLR_CRCEND: u1, + /// Bank 1 CRC read error clear bit + CLR_CRCRDERR: u1, + padding: u3, }), - /// JPEG HuffSymb tables - HUFFBASE15: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + reserved36: [16]u8, + /// FLASH protection address for bank 1 + PRAR_CUR: mmio.Mmio(packed struct(u32) { + /// Bank 1 lowest PCROP protected address + PROT_AREA_START: u12, + reserved16: u4, + /// Bank 1 highest PCROP protected address + PROT_AREA_END: u12, + reserved31: u3, + /// Bank 1 PCROP protected erase enable option status bit + DMEP: u1, }), - /// JPEG HuffSymb tables - HUFFBASE16: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH protection address for bank 1 + PRAR_PRG: mmio.Mmio(packed struct(u32) { + /// Bank 1 lowest PCROP protected address configuration + PROT_AREA_START: u12, + reserved16: u4, + /// Bank 1 highest PCROP protected address configuration + PROT_AREA_END: u12, + reserved31: u3, + /// Bank 1 PCROP protected erase enable option configuration bit + DMEP: u1, }), - /// JPEG HuffSymb tables - HUFFBASE17: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH secure address for bank 1 + SCAR_CUR: mmio.Mmio(packed struct(u32) { + /// Bank 1 lowest secure protected address + SEC_AREA_START: u12, + reserved16: u4, + /// Bank 1 highest secure protected address + SEC_AREA_END: u12, + reserved31: u3, + /// Bank 1 secure protected erase enable option status bit + DMES: u1, }), - /// JPEG HuffSymb tables - HUFFBASE18: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH secure address for bank 1 + SCAR_PRG: mmio.Mmio(packed struct(u32) { + /// Bank 1 lowest secure protected address configuration + SEC_AREA_START: u12, + reserved16: u4, + /// Bank 1 highest secure protected address configuration + SEC_AREA_END: u12, + reserved31: u3, + /// Bank 1 secure protected erase enable option configuration bit + DMES: u1, }), - /// JPEG HuffSymb tables - HUFFBASE19: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH write sector protection for bank 1 + WPSN_CURR: mmio.Mmio(packed struct(u32) { + /// Bank 1 sector write protection option status byte + WRPSn: u8, + padding: u24, }), - /// JPEG HuffSymb tables - HUFFBASE20: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH write sector protection for bank 1 + WPSN_PRGR: mmio.Mmio(packed struct(u32) { + /// Bank 1 sector write protection configuration byte + WRPSn: u8, + padding: u24, }), - /// JPEG HuffSymb tables - HUFFBASE21: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + reserved76: [16]u8, + /// FLASH CRC control register for bank 1 + CRCCR: mmio.Mmio(packed struct(u32) { + /// Bank 1 CRC sector number + CRC_SECT: u3, + reserved7: u4, + /// Bank 1 CRC select bit + ALL_BANK: u1, + /// Bank 1 CRC sector mode select bit + CRC_BY_SECT: u1, + /// Bank 1 CRC sector select bit + ADD_SECT: u1, + /// Bank 1 CRC sector list clear bit + CLEAN_SECT: u1, + reserved16: u5, + /// Bank 1 CRC start bit + START_CRC: u1, + /// Bank 1 CRC clear bit + CLEAN_CRC: u1, + reserved20: u2, + /// Bank 1 CRC burst size + CRC_BURST: u2, + padding: u10, }), - /// JPEG HuffSymb tables - HUFFBASE22: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH CRC start address register for bank 1 + CRCSADDR: mmio.Mmio(packed struct(u32) { + /// CRC start address on bank 1 + CRC_START_ADDR: u32, }), - /// JPEG HuffSymb tables - HUFFBASE23: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH CRC end address register for bank 1 + CRCEADDR: mmio.Mmio(packed struct(u32) { + /// CRC end address on bank 1 + CRC_END_ADDR: u32, }), - /// JPEG HuffSymb tables - HUFFBASE24: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + reserved92: [4]u8, + /// FLASH ECC fail address for bank 1 + FAR: mmio.Mmio(packed struct(u32) { + /// Bank 1 ECC error address + FAIL_ECC_ADDR: u15, + padding: u17, }), - /// JPEG HuffSymb tables - HUFFBASE25: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + }; + + /// Flash + pub const FLASH = extern struct { + /// Access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Read latency + LATENCY: u3, + reserved4: u1, + /// Flash signal delay + WRHIGHFREQ: u2, + padding: u26, }), - /// JPEG HuffSymb tables - HUFFBASE26: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R + BANK: u32, + /// FLASH option key register + OPTKEYR: u32, + reserved24: [12]u8, + /// FLASH option control register + OPTCR: mmio.Mmio(packed struct(u32) { + /// FLASH_OPTCR lock option configuration bit + OPTLOCK: u1, + /// Option byte start change option configuration bit + OPTSTART: u1, + reserved4: u2, + /// Flash mass erase enable bit + MER: u1, + reserved30: u25, + /// Option byte change error interrupt enable bit + OPTCHANGEERRIE: u1, + /// Bank swapping configuration bit + SWAP_BANK: u1, }), - /// JPEG HuffSymb tables - HUFFBASE27: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH option status register + OPTSR_CUR: mmio.Mmio(packed struct(u32) { + /// Option byte change ongoing flag + OPT_BUSY: u1, + reserved2: u1, + /// Brownout level option status bit + BOR_LEV: u2, + /// IWDG1 control option status bit + IWDG1_HW: u1, + reserved6: u1, + /// D1 DStop entry reset option status bit + nRST_STOP_D1: u1, + /// D1 DStandby entry reset option status bit + nRST_STBY_D1: u1, + /// Readout protection level option status byte + RDP: u8, + reserved17: u1, + /// IWDG Stop mode freeze option status bit + FZ_IWDG_STOP: u1, + /// IWDG Standby mode freeze option status bit + FZ_IWDG_SDBY: u1, + /// DTCM RAM size option status + ST_RAM_SIZE: u2, + /// Security enable option status bit + SECURITY: u1, + reserved26: u4, + /// User option bit 1 + RSS1: u1, + reserved28: u1, + /// Device personalization status bit + PERSO_OK: u1, + /// I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V) + IO_HSLV: u1, + /// Option byte change error flag + OPTCHANGEERR: u1, + /// Bank swapping option status bit + SWAP_BANK_OPT: u1, }), - /// JPEG HuffSymb tables - HUFFBASE28: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH option status register + OPTSR_PRG: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// BOR reset level option configuration bits + BOR_LEV: u2, + /// IWDG1 option configuration bit + IWDG1_HW: u1, + reserved6: u1, + /// Option byte erase after D1 DStop option configuration bit + nRST_STOP_D1: u1, + /// Option byte erase after D1 DStandby option configuration bit + nRST_STBY_D1: u1, + /// Readout protection level option configuration byte + RDP: u8, + reserved17: u1, + /// IWDG Stop mode freeze option configuration bit + FZ_IWDG_STOP: u1, + /// IWDG Standby mode freeze option configuration bit + FZ_IWDG_SDBY: u1, + /// DTCM size select option configuration bits + ST_RAM_SIZE: u2, + /// Security option configuration bit + SECURITY: u1, + reserved26: u4, + /// User option configuration bit 1 + RSS1: u1, + /// User option configuration bit 2 + RSS2: u1, + reserved29: u1, + /// I/O high-speed at low-voltage (PRODUCT_BELOW_25V) + IO_HSLV: u1, + reserved31: u1, + /// Bank swapping option configuration bit + SWAP_BANK_OPT: u1, }), - /// JPEG HuffSymb tables - HUFFBASE29: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH option clear control register + OPTCCR: mmio.Mmio(packed struct(u32) { + reserved30: u30, + /// OPTCHANGEERR reset bit + CLR_OPTCHANGEERR: u1, + padding: u1, }), - /// JPEG HuffSymb tables - HUFFBASE30: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + reserved64: [24]u8, + /// FLASH register with boot address + BOOT_CURR: mmio.Mmio(packed struct(u32) { + /// Boot address 0 + BOOT_ADD0: u16, + /// Boot address 1 + BOOT_ADD1: u16, }), - /// JPEG HuffSymb tables - HUFFBASE31: mmio.Mmio(packed struct(u32) { - /// HuffBase RAM - HuffBase_RAM_0: u9, - reserved16: u7, - /// HuffBase RAM - HuffBase_RAM_1: u9, - padding: u7, + /// FLASH register with boot address + BOOT_PRGR: mmio.Mmio(packed struct(u32) { + /// Boot address 0 + BOOT_ADD0: u16, + /// Boot address 1 + BOOT_ADD1: u16, }), - /// JPEG HUFFSYMB tables - HUFFSYMB0: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + reserved92: [20]u8, + /// FLASH CRC data register + CRCDATAR: mmio.Mmio(packed struct(u32) { + /// CRC result + CRC_DATA: u32, }), - /// JPEG HUFFSYMB tables - HUFFSYMB1: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + }; + }; + + pub const flash_h7ab = struct { + /// Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R + pub const BANK = extern struct { + /// FLASH key register for bank 1 + KEYR: u32, + reserved8: [4]u8, + /// FLASH control register for bank 1 + CR: mmio.Mmio(packed struct(u32) { + /// Bank 1 configuration lock bit + LOCK: u1, + /// Bank 1 program enable bit + PG: u1, + /// Bank 1 sector erase request + SER: u1, + /// Bank 1 erase request + BER: u1, + /// Bank 1 write forcing control bit + FW: u1, + /// Bank 1 bank or sector erase start control bit + START: u1, + /// Bank 1 sector erase selection number + SSN: u7, + reserved15: u2, + /// Bank 1 CRC control bit + CRC_EN: u1, + /// Bank 1 end-of-program interrupt control bit + EOPIE: u1, + /// Bank 1 write protection error interrupt enable bit + WRPERRIE: u1, + /// Bank 1 programming sequence error interrupt enable bit + PGSERRIE: u1, + /// Bank 1 strobe error interrupt enable bit + STRBERRIE: u1, + reserved21: u1, + /// Bank 1 inconsistency error interrupt enable bit + INCERRIE: u1, + /// Bank 1 write/erase error interrupt enable bit + OPERRIE: u1, + /// Bank 1 read protection error interrupt enable bit + RDPERRIE: u1, + /// Bank 1 secure error interrupt enable bit + RDSERRIE: u1, + /// Bank 1 ECC single correction error interrupt enable bit + SNECCERRIE: u1, + /// Bank 1 ECC double detection error interrupt enable bit + DBECCERRIE: u1, + /// Bank 1 end of CRC calculation interrupt enable bit + CRCENDIE: u1, + /// Bank 1 CRC read error interrupt enable bit + CRCRDERRIE: u1, + padding: u3, }), - /// JPEG HUFFSYMB tables - HUFFSYMB2: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH status register for bank 1 + SR: mmio.Mmio(packed struct(u32) { + /// Bank 1 ongoing program flag + BSY: u1, + /// Bank 1 write buffer not empty flag + WBNE: u1, + /// Bank 1 wait queue flag + QW: u1, + /// Bank 1 CRC busy flag + CRC_BUSY: u1, + reserved16: u12, + /// Bank 1 end-of-program flag + EOP: u1, + /// Bank 1 write protection error flag + WRPERR: u1, + /// Bank 1 programming sequence error flag + PGSERR: u1, + /// Bank 1 strobe error flag + STRBERR: u1, + reserved21: u1, + /// Bank 1 inconsistency error flag + INCERR: u1, + /// Bank 1 write/erase error flag + OPERR: u1, + /// Bank 1 read protection error flag + RDPERR: u1, + /// Bank 1 secure error flag + RDSERR: u1, + /// Bank 1 single correction error flag + SNECCERR1: u1, + /// Bank 1 ECC double detection error flag + DBECCERR: u1, + /// Bank 1 CRC-complete flag + CRCEND: u1, + /// Bank 1 CRC read error flag + CRCRDERR: u1, + padding: u3, }), - /// JPEG HUFFSYMB tables - HUFFSYMB3: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH clear control register for bank 1 + CCR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Bank 1 EOP1 flag clear bit + CLR_EOP: u1, + /// Bank 1 WRPERR1 flag clear bit + CLR_WRPERR: u1, + /// Bank 1 PGSERR1 flag clear bi + CLR_PGSERR: u1, + /// Bank 1 STRBERR1 flag clear bit + CLR_STRBERR: u1, + reserved21: u1, + /// Bank 1 INCERR1 flag clear bit + CLR_INCERR: u1, + /// Bank 1 OPERR1 flag clear bit + CLR_OPERR: u1, + /// Bank 1 RDPERR1 flag clear bit + CLR_RDPERR: u1, + /// Bank 1 RDSERR1 flag clear bit + CLR_RDSERR: u1, + /// Bank 1 SNECCERR1 flag clear bit + CLR_SNECCERR: u1, + /// Bank 1 DBECCERR1 flag clear bit + CLR_DBECCERR: u1, + /// Bank 1 CRCEND1 flag clear bit + CLR_CRCEND: u1, + /// Bank 1 CRC read error clear bit + CLR_CRCRDERR: u1, + padding: u3, }), - /// JPEG HUFFSYMB tables - HUFFSYMB4: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + reserved36: [16]u8, + /// FLASH protection address for bank 1 + PRAR_CUR: mmio.Mmio(packed struct(u32) { + /// Bank 1 lowest PCROP protected address + PROT_AREA_START: u12, + reserved16: u4, + /// Bank 1 highest PCROP protected address + PROT_AREA_END: u12, + reserved31: u3, + /// Bank 1 PCROP protected erase enable option status bit + DMEP: u1, }), - /// JPEG HUFFSYMB tables - HUFFSYMB5: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH protection address for bank 1 + PRAR_PRG: mmio.Mmio(packed struct(u32) { + /// Bank 1 lowest PCROP protected address configuration + PROT_AREA_START: u12, + reserved16: u4, + /// Bank 1 highest PCROP protected address configuration + PROT_AREA_END: u12, + reserved31: u3, + /// Bank 1 PCROP protected erase enable option configuration bit + DMEP: u1, }), - /// JPEG HUFFSYMB tables - HUFFSYMB6: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH secure address for bank 1 + SCAR_CUR: mmio.Mmio(packed struct(u32) { + /// Bank 1 lowest secure protected address + SEC_AREA_START: u12, + reserved16: u4, + /// Bank 1 highest secure protected address + SEC_AREA_END: u12, + reserved31: u3, + /// Bank 1 secure protected erase enable option status bit + DMES: u1, }), - /// JPEG HUFFSYMB tables - HUFFSYMB7: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH secure address for bank 1 + SCAR_PRG: mmio.Mmio(packed struct(u32) { + /// Bank 1 lowest secure protected address configuration + SEC_AREA_START: u12, + reserved16: u4, + /// Bank 1 highest secure protected address configuration + SEC_AREA_END: u12, + reserved31: u3, + /// Bank 1 secure protected erase enable option configuration bit + DMES: u1, }), - /// JPEG HUFFSYMB tables - HUFFSYMB8: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH write sector protection for bank 1 + WPSN_CURR: mmio.Mmio(packed struct(u32) { + /// Bank 1 sector write protection option status byte + WRPSn: u8, + padding: u24, }), - /// JPEG HUFFSYMB tables - HUFFSYMB9: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH write sector protection for bank 1 + WPSN_PRGR: mmio.Mmio(packed struct(u32) { + /// Bank 1 sector write protection configuration byte + WRPSn: u8, + padding: u24, }), - /// JPEG HUFFSYMB tables - HUFFSYMB10: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + reserved76: [16]u8, + /// FLASH CRC control register for bank 1 + CRCCR: mmio.Mmio(packed struct(u32) { + /// Bank 1 CRC sector number + CRC_SECT: u3, + reserved7: u4, + /// Bank 1 CRC select bit + ALL_BANK: u1, + /// Bank 1 CRC sector mode select bit + CRC_BY_SECT: u1, + /// Bank 1 CRC sector select bit + ADD_SECT: u1, + /// Bank 1 CRC sector list clear bit + CLEAN_SECT: u1, + reserved16: u5, + /// Bank 1 CRC start bit + START_CRC: u1, + /// Bank 1 CRC clear bit + CLEAN_CRC: u1, + reserved20: u2, + /// Bank 1 CRC burst size + CRC_BURST: u2, + padding: u10, }), - /// JPEG HUFFSYMB tables - HUFFSYMB11: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH CRC start address register for bank 1 + CRCSADDR: mmio.Mmio(packed struct(u32) { + /// CRC start address on bank 1 + CRC_START_ADDR: u32, }), - /// JPEG HUFFSYMB tables - HUFFSYMB12: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH CRC end address register for bank 1 + CRCEADDR: mmio.Mmio(packed struct(u32) { + /// CRC end address on bank 1 + CRC_END_ADDR: u32, }), - /// JPEG HUFFSYMB tables - HUFFSYMB13: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + reserved92: [4]u8, + /// FLASH ECC fail address for bank 1 + FAR: mmio.Mmio(packed struct(u32) { + /// Bank 1 ECC error address + FAIL_ECC_ADDR: u15, + padding: u17, }), - /// JPEG HUFFSYMB tables - HUFFSYMB14: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + }; + + /// Flash + pub const FLASH = extern struct { + /// Access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Read latency + LATENCY: u3, + reserved4: u1, + /// Flash signal delay + WRHIGHFREQ: u2, + padding: u26, }), - /// JPEG HUFFSYMB tables - HUFFSYMB15: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R + BANK: u32, + /// FLASH option key register + OPTKEYR: u32, + reserved24: [12]u8, + /// FLASH option control register + OPTCR: mmio.Mmio(packed struct(u32) { + /// FLASH_OPTCR lock option configuration bit + OPTLOCK: u1, + /// Option byte start change option configuration bit + OPTSTART: u1, + reserved4: u2, + /// Flash mass erase enable bit + MER: u1, + /// OTP program control bit + PG_OTP: u1, + reserved30: u24, + /// Option byte change error interrupt enable bit + OPTCHANGEERRIE: u1, + /// Bank swapping configuration bit + SWAP_BANK: u1, }), - /// JPEG HUFFSYMB tables - HUFFSYMB16: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH option status register + OPTSR_CUR: mmio.Mmio(packed struct(u32) { + /// Option byte change ongoing flag + OPT_BUSY: u1, + reserved2: u1, + /// Brownout level option status bit + BOR_LEV: u2, + /// IWDG1 control option status bit + IWDG1_HW: u1, + reserved6: u1, + /// D1 DStop entry reset option status bit + nRST_STOP_D1: u1, + /// D1 DStandby entry reset option status bit + nRST_STBY_D1: u1, + /// Readout protection level option status byte + RDP: u8, + reserved17: u1, + /// IWDG Stop mode freeze option status bit + FZ_IWDG_STOP: u1, + /// IWDG Standby mode freeze option status bit + FZ_IWDG_SDBY: u1, + /// DTCM RAM size option status + ST_RAM_SIZE: u2, + /// Security enable option status bit + SECURITY: u1, + reserved26: u4, + /// User option bit 1 + RSS1: u1, + reserved28: u1, + /// Device personalization status bit + PERSO_OK: u1, + /// I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V) + IO_HSLV: u1, + /// Option byte change error flag + OPTCHANGEERR: u1, + /// Bank swapping option status bit + SWAP_BANK_OPT: u1, }), - /// JPEG HUFFSYMB tables - HUFFSYMB17: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH option status register + OPTSR_PRG: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// BOR reset level option configuration bits + BOR_LEV: u2, + /// IWDG1 option configuration bit + IWDG1_HW: u1, + reserved6: u1, + /// Option byte erase after D1 DStop option configuration bit + nRST_STOP_D1: u1, + /// Option byte erase after D1 DStandby option configuration bit + nRST_STBY_D1: u1, + /// Readout protection level option configuration byte + RDP: u8, + reserved17: u1, + /// IWDG Stop mode freeze option configuration bit + FZ_IWDG_STOP: u1, + /// IWDG Standby mode freeze option configuration bit + FZ_IWDG_SDBY: u1, + /// DTCM size select option configuration bits + ST_RAM_SIZE: u2, + /// Security option configuration bit + SECURITY: u1, + reserved26: u4, + /// User option configuration bit 1 + RSS1: u1, + /// User option configuration bit 2 + RSS2: u1, + reserved29: u1, + /// I/O high-speed at low-voltage (PRODUCT_BELOW_25V) + IO_HSLV: u1, + reserved31: u1, + /// Bank swapping option configuration bit + SWAP_BANK_OPT: u1, }), - /// JPEG HUFFSYMB tables - HUFFSYMB18: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH option clear control register + OPTCCR: mmio.Mmio(packed struct(u32) { + reserved30: u30, + /// OPTCHANGEERR reset bit + CLR_OPTCHANGEERR: u1, + padding: u1, }), - /// JPEG HUFFSYMB tables - HUFFSYMB19: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + reserved64: [24]u8, + /// FLASH register with boot address + BOOT_CURR: mmio.Mmio(packed struct(u32) { + /// Boot address 0 + BOOT_ADD0: u16, + /// Boot address 1 + BOOT_ADD1: u16, }), - /// JPEG HUFFSYMB tables - HUFFSYMB20: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH register with boot address + BOOT_PRGR: mmio.Mmio(packed struct(u32) { + /// Boot address 0 + BOOT_ADD0: u16, + /// Boot address 1 + BOOT_ADD1: u16, }), - /// JPEG HUFFSYMB tables - HUFFSYMB21: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + reserved92: [20]u8, + /// FLASH CRC data register + CRCDATAR: mmio.Mmio(packed struct(u32) { + /// CRC result + CRC_DATA: u32, }), - /// JPEG HUFFSYMB tables - HUFFSYMB22: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + }; + }; + + pub const flash_h7rs = struct { + pub const BOR_LEV = enum(u2) { + /// BOR OFF, POR/PDR reset threshold level is applied. + Disabled = 0x0, + /// BOR Level 1, the threshold level is low (around 2.1 V). + Level1 = 0x1, + /// BOR Level 2, the threshold level is medium (around 2.4 V). + Level2 = 0x2, + /// BOR Level 3, the threshold level is high (around 2.7 V). + Level3 = 0x3, + }; + + pub const CRC_BURST = enum(u2) { + /// every burst has a size of 4 Flash words (64 Bytes). + Word4 = 0x0, + /// every burst has a size of 16 Flash words (256 Bytes). + Word16 = 0x1, + /// every burst has a size of 64 Flash words (1 Kbytes). + Word64 = 0x2, + /// every burst has a size of 256 Flash words (4 Kbytes). + Word256 = 0x3, + }; + + pub const DBG_AUTH = enum(u8) { + /// Authentication method using ECDSA signature (NIST P256). + ECDSA = 0x51, + /// Delegated debug (to OEM iRoT code in user Flash). + Delegated = 0x6f, + /// Authentication method using password. + Password = 0x8a, + /// Locked device (no debug allowed). + Locked = 0xb4, + _, + }; + + pub const IROT_SELECT = enum(u8) { + /// ST iRoT is selected at boot. + Selected = 0xb4, + _, + }; + + pub const NEXTKL = enum(u2) { + /// OBKINDEX represents the index of the option byte key stored for the hide protection level indicated in SBS_HDPLSR. + Plus0 = 0x0, + /// OBKINDEX represents the index of the option byte key stored for the hide protection level indicated in SBS_HDPLSR plus one (e.g. if HDPL=1 in SBS_HDPLR the key of level 2 is selected). + Plus1 = 0x1, + _, + }; + + pub const NVSRP_NVSTATE = enum(u8) { + /// CLOSE. + Close = 0x51, + /// OPEN. + Open = 0xb4, + _, + }; + + pub const NVSR_NVSTATE = enum(u8) { + /// CLOSED device. + Closed = 0x51, + /// OPEN device. + Open = 0xb4, + _, + }; + + pub const OBKSIZE = enum(u2) { + /// Key size is 32 bits. + Bits32 = 0x0, + /// Key size is 64 bits. + Bits64 = 0x1, + /// Key size is 128 bits. + Bits128 = 0x2, + /// Key size is 256 bits. + Bits256 = 0x3, + }; + + pub const OEM_PROVD = enum(u8) { + /// Device has been provisioned by the OEM. + Provisioned = 0xb4, + _, + }; + + /// Embedded Flash memory. + pub const FLASH = extern struct { + /// Access control register. + ACR: mmio.Mmio(packed struct(u32) { + /// Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. Please refer to Table 27 for details. ... Note: Embedded Flash does not verify that the configuration is correct. + LATENCY: u4, + /// Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to Table 27 for details. Note: Embedded Flash does not verify that the configuration is correct. + WRHIGHFREQ: u2, + padding: u26, }), - /// JPEG HUFFSYMB tables - HUFFSYMB23: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, - }), - /// JPEG HUFFSYMB tables - HUFFSYMB24: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH control key register. + KEYR: mmio.Mmio(packed struct(u32) { + /// Control unlock key Following values must be written to FLASH_KEYR consecutively to unlock FLASH_CR register: 1st key = 0x4567 0123 2nd key = 0xCDEF 89AB Reads to this register returns zero. If above sequence is wrong or performed twice, the FLASH_CR register is locked until the next system reset, and access to it generates a bus error. + CUKEY: u32, }), - /// JPEG HUFFSYMB tables - HUFFSYMB25: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + reserved16: [8]u8, + /// FLASH control register. + CR: mmio.Mmio(packed struct(u32) { + /// Configuration lock bit When this bit is set write to all other bits in this register, and to FLASH_IER register, are ignored. Clearing this bit requires the correct write sequence to FLASH_KEYR register (see this register for details). If a wrong sequence is executed, or if the unlock sequence is performed twice, this bit remains locked until the next system reset. During the write access to set LOCK bit from 0 to 1, it is possible to change the other bits of this register. + LOCK: u1, + /// Internal buffer control bit Setting this bit enables internal buffer for write operations. This allows preparing program operations even if a sector or bank erase is ongoing. When PG is cleared, the internal buffer is disabled for write operations, and all the data stored in the buffer but not sent to the operation queue are lost. + PG: u1, + /// Sector erase request Setting this bit requests a sector erase. Write protection error is triggered when a sector erase is required on at least one protected sector. BER has a higher priority than SER: if both bits are set, the embedded Flash memory executes a bank erase. + SER: u1, + /// Bank erase request Setting this bit requests a bank erase operation (user Flash memory only). Write protection error is triggered when a bank erase is required and some sectors are protected. BER has a higher priority than SER: if both are set, the embedded Flash memory executes a bank erase. + BER: u1, + /// Force write This bit forces a write operation even if the write buffer is not full. In this case all bits not written are set by hardware. The embedded Flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it will lead to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively). + FW: u1, + /// Erase start control bit This bit is used to start a sector erase or a bank erase operation. The embedded Flash memory resets START when the corresponding operation has been acknowledged. The user application cannot access any embedded Flash memory register until the operation is acknowledged. + START: u1, + /// Sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). ... + SSN: u2, + reserved16: u8, + /// Program Enable for OTP Area Set this bit to enable write operations to OTP area. + PG_OTP: u1, + /// CRC enable Setting this bit enables the CRC calculation. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR register. When CRC calculation is performed it can be disabled by clearing CRC_EN bit. Doing so sets CRCDATA to 0x0, clears CRC configuration and resets the content of FLASH_CRCDATAR register. + CRC_EN: u1, + reserved24: u6, + /// All banks select bit When this bit is set the erase is done on all Flash Memory sectors. ALL_BANKS is used only if a bank erase is required (BER=1). In all others operations, this control bit is ignored. + ALL_BANKS: u1, + padding: u7, }), - /// JPEG HUFFSYMB tables - HUFFSYMB26: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH status register. + SR: mmio.Mmio(packed struct(u32) { + /// Busy flag This bit is set when an effective write, erase or option byte change operation is ongoing. It is possible to know what type of operation is being executed reading the flags IS_PROGRAM, IS_ERASE and IS_OPTCHANGE. BUSY cannot be cleared by application. It is automatically reset by hardware every time a step in a write, erase or option byte change operation completes. It is not recommended to do software polling on BUSY to know when one operation completed because, depending of operation, more pulses are possible for one only operation. For software polling it is therefore better to use QW flag or to check the EOPF flag. + BUSY: u1, + /// Write buffer not empty flag This bit is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_CR the embedded Flash memory detects an error that involves data loss the application software has disabled write operations This bit cannot be forced to 0. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. + WBNE: u1, + /// Wait queue flag This bit is set when a write, erase or option byte change operation is pending in the command queue buffer. It is not possible to know what type of programming operation is present in the queue. This flag is reset by hardware when all write, erase or option byte change operations have been executed and thus removed from the waiting queue(s). This bit cannot be forced to 0. It is reset after a deterministic time if no other operations are requested. + QW: u1, + /// CRC busy flag This bit is set when a CRC calculation is ongoing. This bit cannot be forced to 0. The user must wait until the CRC calculation has completed or disable CRC computation using CRC_EN bit in FLASH_CR register. + CRC_BUSY: u1, + /// Is a program This bit is set together with BUSY when a program operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_OPTCHANGE, because an program operation can happen during an option change. + IS_PROGRAM: u1, + /// Is an erase This bit is set together with BUSY when an erase operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_OPTCHANGE, because an erase operation can happen during an option change. + IS_ERASE: u1, + /// Is an option change This bit is set together with BUSY when an option change operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_PROGRAM or IS_ERASE, because a program or erase step is ongoing during option change. + IS_OPTCHANGE: u1, + reserved25: u18, + /// Root code check flag This bit returns the status of the root code check performed following the first access to the Flash. This bit is cleared with RCHECKF bit in FLASH_FCR (optional). + RCHECKF: u1, + padding: u6, }), - /// JPEG HUFFSYMB tables - HUFFSYMB27: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH status register. + FCR: mmio.Mmio(packed struct(u32) { + reserved25: u25, + /// Root code check flag clear Set this bit to clear RCHECKF bit in FLASH_SR. + RCHECKF: u1, + padding: u6, }), - /// JPEG HUFFSYMB tables - HUFFSYMB28: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + reserved32: [4]u8, + /// FLASH interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// End-of-program interrupt control bit. + EOPIE: u1, + /// Write protection error interrupt enable bit. + WRPERRIE: u1, + /// Programming sequence error interrupt enable bit. + PGSERRIE: u1, + /// Strobe error interrupt enable bit. + STRBERRIE: u1, + /// Option byte loading error interrupt enable bit. + OBLERRIE: u1, + /// Inconsistency error interrupt enable bit. + INCERRIE: u1, + reserved24: u2, + /// Read security error interrupt enable bit. + RDSERRIE: u1, + /// ECC single correction error interrupt enable bit. + SNECCERRIE: u1, + /// ECC double detection error interrupt enable bit. + DBECCERRIE: u1, + /// CRC end of calculation interrupt enable bit. + CRCENDIE: u1, + /// CRC read error interrupt enable bit. + CRCRDERRIE: u1, + padding: u3, }), - /// JPEG HUFFSYMB tables - HUFFSYMB29: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH interrupt status register. + ISR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// End-of-program flag This bit is set when a programming operation completes. An interrupt is generated if the EOPIE is set. It is not necessary to reset EOPF before starting a new operation. Setting EOPF bit in FLASH_ICR register clears this bit. + EOPF: u1, + /// Write protection error flag This bit is set when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set. Setting WRPERRF bit in FLASH_ICR register clears this bit. + WRPERRF: u1, + /// Programming sequence error flag This bit is set when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set. Setting PGSERRF bit in FLASH_ICR register clears this bit. + PGSERRF: u1, + /// Strobe error flag This bit is set when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set. Setting STRBERRF bit in FLASH_ICR register clears this bit. + STRBERRF: u1, + /// Option byte loading error flag This bit is set when an error is found during the option byte loading sequence. An interrupt is generated if OBLERRIE is set. Setting OBLERRF bit in the FLASH_ICR register clears this bit. + OBLERRF: u1, + /// Inconsistency error flag This bit is set when a inconsistency error occurs. An interrupt is generated if INCERRIE is set. Setting INCERRF bit in the FLASH_ICR register clears this bit. + INCERRF: u1, + reserved24: u2, + /// Read security error flag This bit is set when a read security error occurs (read access to hide protected area with incorrect hide protection level). An interrupt is generated if RDSERRIE is set. Setting RDSERRF bit in FLASH_ICR register clears this bit. + RDSERRF: u1, + /// ECC single error flag This bit is set when an ECC single correction error occurs during a read operation. An interrupt is generated if SNECCERRIE is set. Setting SNECCERRF bit in FLASH_ICR register clears this bit. + SNECCERRF: u1, + /// ECC double error flag This bit is set when an ECC double detection error occurs during a read operation. An interrupt is generated if DBECCERRIE is set. Setting DBECCERRF bit in FLASH_ICR register clears this bit. + DBECCERRF: u1, + /// CRC end flag This bit is set when the CRC computation has completed. An interrupt is generated if CRCENDIE is set. It is not necessary to reset CRCEND before restarting CRC computation. Setting CRCENDF bit in FLASH_ICR register clears this bit. + CRCENDF: u1, + /// CRC read error flag This bit is set when a word is found read protected during a CRC operation. An interrupt is generated if CRCRDIE is set. Setting CRCRDERRF bit in FLASH_ICR register clears this bit. This flag is valid only when CRCEND bit is set. + CRCRDERRF: u1, + padding: u3, }), - /// JPEG HUFFSYMB tables - HUFFSYMB30: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// End-of-program flag clear Setting this bit clears EOPF flag in FLASH_ISR register. + EOPF: u1, + /// Write protection error flag clear Setting this bit clears WRPERRF flag in FLASH_ISR register. + WRPERRF: u1, + /// Programming sequence error flag clear Setting this bit clears PGSERRF flag in FLASH_ISR register. + PGSERRF: u1, + /// Strobe error flag clear Setting this bit clears STRBERRF flag in FLASH_ISR register. + STRBERRF: u1, + /// Option byte loading error flag clear Setting this bit clears OBLERRF flag in FLASH_ISR register. + OBLERRF: u1, + /// Inconsistency error flag clear Setting this bit clears INCERRF flag in FLASH_ISR register. + INCERRF: u1, + reserved24: u2, + /// Read security error flag clear Setting this bit clears RDSERRF flag in FLASH_ISR register. + RDSERRF: u1, + /// ECC single error flag clear Setting this bit clears SNECCERRF flag in FLASH_ISR register. If the DBECCERRF flag of FLASH_ISR register is also cleared, FLASH_ECCFAR register is reset to zero as well. + SNECCERRF: u1, + /// ECC double error flag clear Setting this bit clears DBECCERRF flag in FLASH_ISR register. If the SNECCERRF flag of FLASH_ISR register is also cleared, FLASH_ECCFAR register is reset to zero as well. + DBECCERRF: u1, + /// CRC end flag clear Setting this bit clears CRCENDF flag in FLASH_ISR register. + CRCENDF: u1, + /// CRC error flag clear Setting this bit clears CRCRDERRF flag in FLASH_ISR register. + CRCRDERRF: u1, + padding: u3, }), - /// JPEG HUFFSYMB tables - HUFFSYMB31: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + reserved48: [4]u8, + /// FLASH CRC control register. + CRCCR: mmio.Mmio(packed struct(u32) { + /// CRC sector number CRC_SECT is used to select one user Flash sectors to be added to the list of sectors on which the CRC is calculated. The CRC can be computed either between two addresses (using registers FLASH_CRCSADDR and FLASH_CRCEADDR) or on a list of sectors using this register. If this latter option is selected, it is possible to add a sector to the list of sectors by programming the sector number in CRC_SECT and then setting ADD_SECT bit. The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC computation. ... + CRC_SECT: u2, + reserved9: u7, + /// CRC sector mode select bit When this bit is set the CRC calculation is performed at sector level, on the sectors present in the list of sectors. To add a sector to this list, use ADD_SECT and CRC_SECT bits. To clean the list, use CLEAN_SECT bit. When CRC_BY_SECT is cleared the CRC calculation is performed on all addresses defined between start and end addresses defined in FLASH_CRCSADDR and FLASH_CRCEADDR registers. + CRC_BY_SECT: u1, + /// CRC sector select bit When this bit is set the sector whose number is written in CRC_SECT is added to the list of sectors on which the CRC is calculated. + ADD_SECT: u1, + /// CRC sector list clear bit When this bit is set the list of sectors on which the CRC is calculated is cleared. + CLEAN_SECT: u1, + reserved16: u4, + /// CRC start bit START_CRC bit triggers a CRC calculation using the current configuration. No CRC calculation can launched when an option byte change operation is ongoing because all read accesses to embedded Flash memory registers are put on hold until the option byte change operation has completed. This bit is cleared when CRC computation starts. + START_CRC: u1, + /// CRC clear bit Setting CLEAN_CRC to 1 clears the current CRC result stored in the FLASH_CRCDATAR register. + CLEAN_CRC: u1, + reserved20: u2, + /// CRC burst size CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit. A Flash word is 128-bit. + CRC_BURST: packed union { + raw: u2, + value: CRC_BURST, + }, + reserved24: u2, + /// All sectors selection When this bit is set all the sectors in user Flash are added to list of sectors on which the CRC shall be calculated. This bit is cleared when CRC computation starts. + ALL_SECT: u1, + padding: u7, }), - /// JPEG HUFFSYMB tables - HUFFSYMB32: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH CRC start address register. + CRCSADDR: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// CRC start address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the first Flash word to use for the CRC calculation, done burst by burst. CRC computation starts at an address aligned to the burst size defined in CRC_BURST of FLASH_CRCCR register. Hence least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank. + CRC_START_ADDR: u11, + padding: u15, }), - /// JPEG HUFFSYMB tables - HUFFSYMB33: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH CRC end address register. + CRCEADDR: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// CRC end address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the Flash word starting the last burst of the CRC calculation. The burst size is defined in CRC_BURST of FLASH_CRCCR register. The least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank. + CRC_END_ADDR: u11, + padding: u15, }), - /// JPEG HUFFSYMB tables - HUFFSYMB34: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH CRC data register. + CRCDATAR: mmio.Mmio(packed struct(u32) { + /// CRC result This bitfield contains the result of the last CRC calculation. The value is valid only when CRC calculation completed (CRCENDF is set in FLASH_ISR register). CRC_DATA is cleared when CRC_EN is cleared in FLASH_CR register (CRC disabled), or when CLEAN_CRC bit is set in FLASH_CRCCR register. + CRC_DATA: u32, }), - /// JPEG HUFFSYMB tables - HUFFSYMB35: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH ECC single error fail address. + ECCSFADDR: mmio.Mmio(packed struct(u32) { + /// ECC single error correction fail address When a single ECC error correction occurs during a read operation, the SEC_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when SNECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC single error correction error is saved in this register. + SEC_FADD: u32, }), - /// JPEG HUFFSYMB tables - HUFFSYMB36: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH ECC double error fail address. + ECCDFADDR: mmio.Mmio(packed struct(u32) { + /// ECC double error detection fail address When a double ECC detection occurs during a read operation, the DED_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when the DBECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC double error detection error is saved in this register. + DED_FADD: u32, }), - /// JPEG HUFFSYMB tables - HUFFSYMB37: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + reserved256: [184]u8, + /// FLASH options key register. + OPTKEYR: mmio.Mmio(packed struct(u32) { + /// Options configuration unlock key Following values must be written to FLASH_OPTKEYR consecutively to unlock FLASH_OPTCR register: 1st key = 0x0819 2A3B 2nd key = 0x4C5D 6E7F Reads to this register returns zero. If above sequence is performed twice locks up the corresponding register/bit until the next system reset, and generates a bus error. + OCUKEY: u32, }), - /// JPEG HUFFSYMB tables - HUFFSYMB38: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH options control register. + OPTCR: mmio.Mmio(packed struct(u32) { + /// Options lock When this bit is set write to all other bits in this register, and write to OTP words, option bytes and option bytes keys control registers, are ignored. Clearing this bit requires the correct write sequence to FLASH_OPTKEYR register (see this register for details). If a wrong sequence is executed, or the unlock sequence is performed twice, this bit remains locked until next system reset. During the write access to set LOCK bit from 0 to 1, it is possible to change the other bits of this register. + OPTLOCK: u1, + /// Program options. + PG_OPT: u1, + reserved27: u25, + /// Key valid error interrupt enable bit This bit controls if an interrupt has to be generated when KVEF is set in FLASH_OPTISR. + KVEIE: u1, + /// Key transfer error interrupt enable bit This bit controls if an interrupt has to be generated when KTEF is set in FLASH_OPTISR. + KTEIE: u1, + reserved30: u1, + /// Option byte change error interrupt enable bit This bit controls if an interrupt has to be generated when an error occurs during an option byte change. + OPTERRIE: u1, + padding: u1, }), - /// JPEG HUFFSYMB tables - HUFFSYMB39: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH options interrupt status register. + OPTISR: mmio.Mmio(packed struct(u32) { + reserved27: u27, + /// Key valid error flag This bit is set when loading an unknown or corrupted option byte key. More specifically: Embedded Flash did not find an option byte key that corresponds to the given OBKINDEX[4:0] and the requested HDPL (optionally modified by NEXTKL[1:0]). It can happen for example when requested key has not being provisioned. A double error detection was found when loading the requested option byte key. In this case, if this key is provisioned again the error should disappear. When KVEF is set write to START bit in FLASH_OBKCR is ignored. An interrupt is generated when this flag is raised if the KVEIE bit of FLASH_OPTCR register is set. Setting KVEF bit of register FLASH_OPTICR clears this bit. + KVEF: u1, + /// Key transfer error flag This bit is set when embedded Flash signals an error to the SAES peripheral. It happens when the key size (128-bit or 256-bit) is not matching between embedded Flash OBKSIZE[1:0] and KEYSIZE bit in SAES_CR register. It also happen when an ECC dual error detection occurred while embedded Flash loaded an option byte key for the SAES peripheral. When KTEF is set write to START bit in FLASH_OBKCR is ignored. An interrupt is generated when this flag is raised if the KTEIE bit of FLASH_OPTCR register is set. Setting KTEF bit of register FLASH_OPTICR clears this bit. + KTEF: u1, + reserved30: u1, + /// Option byte change error flag When OPTERRF is set, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTERRIE bit of FLASH_OPTCR register is set. Setting OPTERRF of register FLASH_OPTICR clears this bit. + OPTERRF: u1, + padding: u1, }), - /// JPEG HUFFSYMB tables - HUFFSYMB40: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH options interrupt clear register. + OPTICR: mmio.Mmio(packed struct(u32) { + reserved27: u27, + /// key valid error flag Set this bit to clear KVEF flag in FLASH_OPTISR register. + KVEF: u1, + /// key transfer error flag Set this bit to clear KTEF flag in FLASH_OPTISR register. + KTEF: u1, + reserved30: u1, + /// Option byte change error flag Set this bit to clear OPTERRF flag in FLASH_OPTISR register. + OPTERRF: u1, + padding: u1, }), - /// JPEG HUFFSYMB tables - HUFFSYMB41: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH option byte key control register. + OBKCR: mmio.Mmio(packed struct(u32) { + /// Option byte key index This bitfield represents the index of the option byte key in a given hide protection level. Reading keys with index lower that 8, the value is not be available in OBKDRx registers. It is instead sent directly to SAES peripheral. All others keys can be read using OBKDRx registers. Up to 32 keys can be provisioned per hide protection level (0, 1 or 2), provided there is enough space left in the Flash to store them. + OBKINDEX: u5, + reserved8: u3, + /// Next key level 10 or 11: reserved. + NEXTKL: packed union { + raw: u2, + value: NEXTKL, + }, + /// Option byte key size Application must use this bitfield to specify how many bits must be used for the new key. Embedded Flash ignores OBKSIZE during read of option keys because size is stored with the key. + OBKSIZE: packed union { + raw: u2, + value: OBKSIZE, + }, + reserved14: u2, + /// Key program This bit must be set to write option byte keys (keys are read otherwise). + KEYPROG: u1, + /// Key option start This bit is used to start the option byte key operation defined by the PROG bit. The embedded Flash memory resets START when the corresponding operation has been acknowledged. + KEYSTART: u1, + padding: u16, }), - /// JPEG HUFFSYMB tables - HUFFSYMB42: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + reserved280: [4]u8, + /// FLASH option bytes key data register 0. + OBKDR: [8]u32, + reserved512: [200]u8, + /// FLASH non-volatile status register. + NVSR: mmio.Mmio(packed struct(u32) { + /// Non-volatile state others: invalid configuration. + NVSTATE: packed union { + raw: u8, + value: NVSR_NVSTATE, + }, + padding: u24, }), - /// JPEG HUFFSYMB tables - HUFFSYMB43: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH security status register programming. + NVSRP: mmio.Mmio(packed struct(u32) { + /// Non-volatile state programming Write to change corresponding bits in FLASH_NVSR register: Actual option byte change from close to open is triggered only after memory clear hardware process is confirmed. When NVSTATE=0xB4 (resp. 0x51) writing any other value than 0x51 (resp. 0xB4) triggers an option byte change error (OPTERRF). + NVSTATE: packed union { + raw: u8, + value: NVSRP_NVSTATE, + }, + padding: u24, }), - /// JPEG HUFFSYMB tables - HUFFSYMB44: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH RoT status register. + ROTSR: mmio.Mmio(packed struct(u32) { + /// OEM provisioned device Any other value: device is not provisioned by the OEM. + OEM_PROVD: packed union { + raw: u8, + value: OEM_PROVD, + }, + /// Debug authentication method Any other value: no authentication method selected (NotSet). + DBG_AUTH: packed union { + raw: u8, + value: DBG_AUTH, + }, + reserved24: u8, + /// iRoT selection This option is ignored for STM32H7R devices (OEM iRoT is always selected). Any other value: OEM iRoT is selected at boot. + IROT_SELECT: packed union { + raw: u8, + value: IROT_SELECT, + }, }), - /// JPEG HUFFSYMB tables - HUFFSYMB45: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH RoT status register programming. + ROTSRP: mmio.Mmio(packed struct(u32) { + /// OEM provisioned device Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 1. + OEM_PROVD: u8, + /// Debug authentication method programming Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 0. + DBG_AUTH: u8, + reserved24: u8, + /// iRoT selection This option is ignored for STM32H7R devices. Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 1 and if NVSTATE is not 0xB4 (OPEN). + IROT_SELECT: u8, }), - /// JPEG HUFFSYMB tables - HUFFSYMB46: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH OTP lock status register. + OTPLSR: mmio.Mmio(packed struct(u32) { + /// OTP lock n Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. OTPL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and can no longer be programmed. OTPL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked and can still be modified. + OTPL: u16, + padding: u16, }), - /// JPEG HUFFSYMB tables - HUFFSYMB47: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH OTP lock status register programming. + OTPLSRP: mmio.Mmio(packed struct(u32) { + /// OTP lock n programming Write to change corresponding option byte bit in FLASH_OTPLSR. OTPL bits can be only be set, not cleared. + OTPL: u16, + padding: u16, }), - /// JPEG HUFFSYMB tables - HUFFSYMB48: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH write protection status register. + WRPSR: mmio.Mmio(packed struct(u32) { + /// Write protection for sector n This bit reflects the write protection status of user Flash sector n. + WRPS: u8, + padding: u24, }), - /// JPEG HUFFSYMB tables - HUFFSYMB49: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + /// FLASH write protection status register programming. + WRPSRP: mmio.Mmio(packed struct(u32) { + /// Write protection for sector n programming Write to change corresponding bit in FLASH_WRPSR. + WRPS: u8, + padding: u24, }), - /// JPEG HUFFSYMB tables - HUFFSYMB50: mmio.Mmio(packed struct(u32) { - /// DHTSymb RAM - HuffSymb_RAM: u32, + reserved560: [16]u8, + /// FLASH hide protection status register. + HDPSR: mmio.Mmio(packed struct(u32) { + /// Hide protection user Flash area start This option sets the start address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_ENDDD supply level threshold that activates/releases the reset. + BOR_LEV: packed union { + raw: u3, + value: BOR_LEV, + }, + reserved12: u1, + /// Reset generation in Stop mode + NRST_STOP: u1, + /// Reset generation in Standby mode + NRST_STDBY: u1, + reserved15: u1, + /// SRAM1 erase upon system reset + SRAM1_RST: u1, + /// Independent watchdog enable selection + IWDG_SW: u1, + /// Independent watchdog counter freeze in Stop mode + IWDG_STOP: u1, + /// Independent watchdog counter freeze in Standby mode + IWDG_STDBY: u1, + /// Window watchdog selection + WWDG_SW: u1, + reserved24: u4, + /// SRAM2 parity check enable + SRAM2_PE: u1, + /// SRAM2 erase when system reset + SRAM2_RST: u1, + /// Software BOOT0 + NSWBOOT0: u1, + /// NBOOT0 option bit + NBOOT0: u1, + reserved31: u3, + /// Global TrustZone security enable + TZEN: u1, }), - /// DSI Host video HBP configuration register. - VHBPCR: mmio.Mmio(packed struct(u32) { - /// HBP. - HBP: u12, - padding: u20, + /// boot address 0 register + NSBOOTADD0R: mmio.Mmio(packed struct(u32) { + reserved7: u7, + /// Non-secure boot base address 0 This address is only used when TZEN = 0. The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: NSBOOTADD0[24:0] = 0x0100000: Boot from memory (0x0800 0000) NSBOOTADD0[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000) NSBOOTADD0[24:0] = 0x0400200: Boot from SRAM2 on S-Bus (0x2001 0000) + NSBOOTADD0: u25, }), - /// DSI Host video line configuration register. - VLCR: mmio.Mmio(packed struct(u32) { - /// HLINE. - HLINE: u15, - padding: u17, + /// boot address 1 register + NSBOOTADD1R: mmio.Mmio(packed struct(u32) { + reserved7: u7, + /// Non-secure boot address 1 This address is only used when TZEN = 0. The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: NSBOOTADD1[24:0] = 0x0100000: Boot from memory (0x0800 0000) NSBOOTADD1[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000) NSBOOTADD1[24:0] = 0x0400200: Boot from SRAM2 (0x2001 0000) + NSBOOTADD1: u25, }), - /// DSI Host video VSA configuration register. - VVSACR: mmio.Mmio(packed struct(u32) { - /// VSA. - VSA: u10, - padding: u22, + /// secure boot address 0 register + SECBOOTADD0R: mmio.Mmio(packed struct(u32) { + /// Boot lock This lock is only used when TZEN = 0. When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP regression level 1 to level 0. + BOOT_LOCK: u1, + reserved7: u6, + /// Secure boot base address 0 This address is only used when TZEN = 1. The secure boot memory address can be programmed to any address in the valid address range (see Table�28: Boot space versus RDP protection) with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: SECBOOTADD0[24:0] = 0x018 0000: Boot from secure user memory (0x0C00 0000) SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS system memory (0x0FF8 0000) SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000) + SECBOOTADD0: u25, }), - /// DSI Host video VBP configuration register. - VVBPCR: mmio.Mmio(packed struct(u32) { - /// VBP. - VBP: u10, - padding: u22, + /// secure watermark register 1 + SECWMR1: mmio.Mmio(packed struct(u32) { + /// Start page of secure area This field contains the first page of the secure area. + SECWM_PSTRT: u7, + reserved16: u9, + /// End page of secure area This field contains the last page of the secure area. + SECWM_PEND: u7, + padding: u9, }), - /// DSI Host video VFP configuration register. - VVFPCR: mmio.Mmio(packed struct(u32) { - /// VFP. - VFP: u10, - padding: u22, + /// secure watermark register 2 + SECWMR2: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// End page of secure hide protection area This field contains the last page of the secure HDP area. + HDP_PEND: u7, + reserved31: u8, + /// Secure Hide protection area enable + HDPEN: u1, }), - /// DSI Host video VA configuration register. - VVACR: mmio.Mmio(packed struct(u32) { - /// VA. - VA: u14, - padding: u18, + /// WRP area A address register + WRPAR: mmio.Mmio(packed struct(u32) { + /// WPR area A start page This field contains the first page of the WPR area A. Note that bit 6 is reserved on STM32WBAxEx devices. + WRPA_PSTRT: u7, + reserved16: u9, + /// WPR area A end page This field contains the last page of the WPR area A. Note that bit 22 is reserved on STM32WBAxEx devices. + WRPA_PEND: u7, + reserved31: u8, + /// WPR area A unlock + UNLOCK: u1, }), - /// DSI Host LTDC command configuration register. - LCCR: mmio.Mmio(packed struct(u32) { - /// CMDSIZE. - CMDSIZE: u16, - padding: u16, + /// WRP area B address register + WRPBR: mmio.Mmio(packed struct(u32) { + /// WRP area B start page This field contains the first page of the WRP area B. Note that bit 6 is reserved on STM32WBAxEx devices. + WRPB_PSTRT: u7, + reserved16: u9, + /// WRP area B end page This field contains the last page of the WRP area B. Note that bit 22 is reserved on STM32WBAxEx devices. + WRPB_PEND: u7, + reserved31: u8, + /// WPR area B unlock + UNLOCK: u1, }), - /// DSI Host command mode configuration register. - CMCR: mmio.Mmio(packed struct(u32) { - /// TEARE. - TEARE: u1, - /// ARE. - ARE: u1, - reserved8: u6, - /// GSW0TX. - GSW0TX: u1, - /// GSW1TX. - GSW1TX: u1, - /// GSW2TX. - GSW2TX: u1, - /// GSR0TX. - GSR0TX: u1, - /// GSR1TX. - GSR1TX: u1, - /// GSR2TX. - GSR2TX: u1, - /// GLWTX. - GLWTX: u1, - reserved16: u1, - /// DSW0TX. - DSW0TX: u1, - /// DSW1TX. - DSW1TX: u1, - /// DSR0TX. - DSR0TX: u1, - /// DLWTX. - DLWTX: u1, - reserved24: u4, - /// MRDPS. - MRDPS: u1, - padding: u7, + reserved112: [16]u8, + /// OEM1 key register 1 + OEM1KEYR1: u32, + /// OEM1 key register 2 + OEM1KEYR2: u32, + /// OEM2 key register 1 + OEM2KEYR1: u32, + /// OEM2 key register 2 + OEM2KEYR2: u32, + /// secure block based register 1 + SECBBR: [4]mmio.Mmio(packed struct(u32) { + BLOCK: u1, + padding: u31, }), - /// DSI Host generic header configuration register. - GHCR: mmio.Mmio(packed struct(u32) { - /// DT. - DT: u6, - /// VCID. - VCID: u2, - /// WCLSB. - WCLSB: u8, - /// WCMSB. - WCMSB: u8, - padding: u8, + reserved192: [48]u8, + /// secure HDP control register + SECHDPCR: mmio.Mmio(packed struct(u32) { + /// Secure HDP area access disable When set, this bit is only cleared by a system reset. + HDP_ACCDIS: u1, + padding: u31, }), - /// DSI Host generic payload data register. - GPDR: mmio.Mmio(packed struct(u32) { - /// DATA1. - DATA1: u8, - /// DATA2. - DATA2: u8, - /// DATA3. - DATA3: u8, - /// DATA4. - DATA4: u8, + /// privilege configuration register + PRIFCFGR: mmio.Mmio(packed struct(u32) { + /// Privileged protection for secure registers This bit is secure write protected. It can only be written by a secure privileged access when TrustZone is enabled (TZEN�=�1). + SPRIV: u1, + /// Privileged protection for non-secure registers + NSPRIV: u1, + padding: u30, }), - /// DSI Host generic packet status register. - GPSR: mmio.Mmio(packed struct(u32) { - /// CMDFE. - CMDFE: u1, - /// CMDFF. - CMDFF: u1, - /// PWRFE. - PWRFE: u1, - /// PWRFF. - PWRFF: u1, - /// PRDFE. - PRDFE: u1, - /// PRDFF. - PRDFF: u1, - /// RCB. - RCB: u1, - padding: u25, + reserved208: [8]u8, + /// privilege block based register 1 + PRIVBBR: [4]mmio.Mmio(packed struct(u32) { + BLOCK: u1, + padding: u31, }), - /// DSI Host timeout counter configuration register 0. - TCCR0: mmio.Mmio(packed struct(u32) { - /// LPRX_TOCNT. - LPRX_TOCNT: u16, - /// HSTX_TOCNT. - HSTX_TOCNT: u16, + }; + }; + + pub const flash_wl = struct { + /// Flash + pub const FLASH = extern struct { + /// Access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: u3, + reserved8: u5, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + /// Data cache enable + DCEN: u1, + /// Instruction cache reset + ICRST: u1, + /// Data cache reset + DCRST: u1, + reserved15: u2, + /// CPU1 CortexM4 program erase suspend request + PES: u1, + /// Flash User area empty + EMPTY: u1, + padding: u15, }), - /// DSI Host timeout counter configuration register 1. - TCCR1: mmio.Mmio(packed struct(u32) { - /// HSRD_TOCNT. - HSRD_TOCNT: u16, - padding: u16, + reserved8: [4]u8, + /// Flash key register + KEYR: u32, + /// Option byte key register + OPTKEYR: u32, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved3: u1, + /// Programming error + PROGERR: u1, + /// Write protected error + WRPERR: u1, + /// Programming alignment error + PGAERR: u1, + /// Size error + SIZERR: u1, + /// Programming sequence error + PGSERR: u1, + /// Fast programming data miss error + MISERR: u1, + /// Fast programming error + FASTERR: u1, + reserved13: u3, + /// User Option OPTVAL indication + OPTNV: u1, + /// PCROP read error + RDERR: u1, + /// Option validity error + OPTVERR: u1, + /// Busy + BSY: u1, + reserved18: u1, + /// Programming or erase configuration busy + CFGBSY: u1, + /// Programming or erase operation suspended + PESD: u1, + padding: u12, }), - /// DSI Host timeout counter configuration register 2. - TCCR2: mmio.Mmio(packed struct(u32) { - /// LPRD_TOCNT. - LPRD_TOCNT: u16, - padding: u16, + /// Flash control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Page erase + PER: u1, + /// This bit triggers the mass erase (all user pages) when set + MER: u1, + /// Page number selection + PNB: u8, + reserved16: u5, + /// Start + STRT: u1, + /// Options modification start + OPTSTRT: u1, + /// Fast programming + FSTPG: u1, + reserved24: u5, + /// End of operation interrupt enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + /// PCROP read error interrupt enable + RDERRIE: u1, + /// Force the option byte loading + OBL_LAUNCH: u1, + reserved30: u2, + /// Options Lock + OPTLOCK: u1, + /// FLASH_CR Lock + LOCK: u1, }), - /// DSI Host timeout counter configuration register 3. - TCCR3: mmio.Mmio(packed struct(u32) { - /// HSWR_TOCNT. - HSWR_TOCNT: u16, - reserved24: u8, - /// PM. - PM: u1, - padding: u7, + /// Flash ECC register + ECCR: mmio.Mmio(packed struct(u32) { + /// ECC fail address + ADDR_ECC: u17, + reserved20: u3, + /// System Flash ECC fail + SYSF_ECC: u1, + reserved24: u3, + /// ECC correction interrupt enable + ECCCIE: u1, + reserved26: u1, + /// CPU identification + CPUID: u3, + reserved30: u1, + /// ECC correction + ECCC: u1, + /// ECC detection + ECCD: u1, }), - /// DSI Host timeout counter configuration register 4. - TCCR4: mmio.Mmio(packed struct(u32) { - /// LPWR_TOCNT. - LPWR_TOCNT: u16, - padding: u16, + reserved32: [4]u8, + /// Flash option register + OPTR: mmio.Mmio(packed struct(u32) { + /// Read protection level + RDP: u8, + /// Security enabled + ESE: u1, + /// BOR reset Level + BOR_LEV: u3, + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + /// nRST_SHDW + nRST_SHDW: u1, + reserved16: u1, + /// Independent watchdog selection + IDWG_SW: u1, + /// Independent watchdog counter freeze in Stop mode + IWDG_STOP: u1, + /// Independent watchdog counter freeze in Standby mode + IWDG_STDBY: u1, + /// Window watchdog selection + WWDG_SW: u1, + reserved23: u3, + /// Boot configuration + nBOOT1: u1, + /// SRAM2 parity check enable + SRAM2_PE: u1, + /// SRAM2 Erase when system reset + SRAM2_RST: u1, + /// Software Boot0 + nSWBOOT0: u1, + /// nBoot0 option bit + nBOOT0: u1, + reserved29: u1, + /// Radio Automatic Gain Control Trimming + AGC_TRIM: u3, }), - /// DSI Host timeout counter configuration register 5. - TCCR5: mmio.Mmio(packed struct(u32) { - /// BTA_TOCNT. - BTA_TOCNT: u16, - padding: u16, + /// Flash Bank 1 PCROP Start address zone A register + PCROP1ASR: mmio.Mmio(packed struct(u32) { + /// Bank 1 PCROPQ area start offset + PCROP1A_STRT: u9, + padding: u23, }), - reserved148: [4]u8, - /// DSI Host clock lane configuration register. - CLCR: mmio.Mmio(packed struct(u32) { - /// DPCC. - DPCC: u1, - /// ACR. - ACR: u1, - padding: u30, + /// Flash Bank 1 PCROP End address zone A register + PCROP1AER: mmio.Mmio(packed struct(u32) { + /// Bank 1 PCROP area end offset + PCROP1A_END: u9, + reserved31: u22, + /// PCROP area preserved when RDP level decreased + PCROP_RDP: u1, }), - /// DSI Host clock lane timer configuration register. - CLTCR: mmio.Mmio(packed struct(u32) { - /// LP2HS_TIME. - LP2HS_TIME: u10, - reserved16: u6, - /// HS2LP_TIME. - HS2LP_TIME: u10, - padding: u6, + /// Flash Bank 1 WRP area A address register + WRP1AR: mmio.Mmio(packed struct(u32) { + /// Bank 1 WRP first area A start offset + WRP1A_STRT: u8, + reserved16: u8, + /// Bank 1 WRP first area A end offset + WRP1A_END: u8, + padding: u8, }), - /// DSI Host data lane timer configuration register. - DLTCR: mmio.Mmio(packed struct(u32) { - /// LP2HS_TIME. - LP2HS_TIME: u10, - reserved16: u6, - /// HS2LP_TIME. - HS2LP_TIME: u10, - padding: u6, + /// Flash Bank 1 WRP area B address register + WRP1BR: mmio.Mmio(packed struct(u32) { + /// Bank 1 WRP second area B start offset + WRP1B_END: u8, + reserved16: u8, + /// Bank 1 WRP second area B end offset + WRP1B_STRT: u8, + padding: u8, }), - /// DSI Host PHY control register. - PCTLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// DEN. - DEN: u1, - /// CKE. - CKE: u1, - padding: u29, + /// Flash Bank 1 PCROP Start address area B register + PCROP1BSR: mmio.Mmio(packed struct(u32) { + /// Bank 1 PCROP area B start offset + PCROP1B_STRT: u9, + padding: u23, }), - /// DSI Host PHY configuration register. - PCONFR: mmio.Mmio(packed struct(u32) { - /// NL. - NL: u2, - reserved8: u6, - /// SW_TIME. - SW_TIME: u8, - padding: u16, + /// Flash Bank 1 PCROP End address area B register + PCROP1BER: mmio.Mmio(packed struct(u32) { + /// Bank 1 PCROP area end area B offset + PCROP1B_END: u9, + padding: u23, }), - /// DSI Host PHY ULPS control register. - PUCR: mmio.Mmio(packed struct(u32) { - /// URCL. - URCL: u1, - /// UECL. - UECL: u1, - /// URDL. - URDL: u1, - /// UEDL. - UEDL: u1, - padding: u28, + /// IPCC mailbox data buffer address register + IPCCBR: mmio.Mmio(packed struct(u32) { + /// PCC mailbox data buffer base address + IPCCDBA: u14, + padding: u18, }), - /// DSI Host PHY TX triggers configuration register. - PTTCR: mmio.Mmio(packed struct(u32) { - /// TX_TRIG. - TX_TRIG: u4, - padding: u28, + reserved92: [28]u8, + /// CPU2 cortex M0 access control register + C2ACR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// CPU2 cortex M0 prefetch enable + PRFTEN: u1, + /// CPU2 cortex M0 instruction cache enable + ICEN: u1, + reserved11: u1, + /// CPU2 cortex M0 instruction cache reset + ICRST: u1, + reserved15: u3, + /// CPU2 cortex M0 program erase suspend request + PES: u1, + padding: u16, }), - /// DSI Host PHY status register. - PSR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// PD. - PD: u1, - /// PSSC. - PSSC: u1, - /// UANC. - UANC: u1, - /// PSS0. - PSS0: u1, - /// UAN0. - UAN0: u1, - /// RUE0. - RUE0: u1, - /// PSS1. - PSS1: u1, - /// UAN1. - UAN1: u1, - padding: u23, - }), - reserved188: [8]u8, - /// DSI Host interrupt and status register 0. - ISR0: mmio.Mmio(packed struct(u32) { - /// AE0. - AE0: u1, - /// AE1. - AE1: u1, - /// AE2. - AE2: u1, - /// AE3. - AE3: u1, - /// AE4. - AE4: u1, - /// AE5. - AE5: u1, - /// AE6. - AE6: u1, - /// AE7. - AE7: u1, - /// AE8. - AE8: u1, - /// AE9. - AE9: u1, - /// AE10. - AE10: u1, - /// AE11. - AE11: u1, - /// AE12. - AE12: u1, - /// AE13. - AE13: u1, - /// AE14. - AE14: u1, - /// AE15. - AE15: u1, - /// PE0. - PE0: u1, - /// PE1. - PE1: u1, - /// PE2. - PE2: u1, - /// PE3. - PE3: u1, - /// PE4. - PE4: u1, - padding: u11, - }), - /// DSI Host interrupt and status register 1. - ISR1: mmio.Mmio(packed struct(u32) { - /// TOHSTX. - TOHSTX: u1, - /// TOLPRX. - TOLPRX: u1, - /// ECCSE. - ECCSE: u1, - /// ECCME. - ECCME: u1, - /// CRCE. - CRCE: u1, - /// PSE. - PSE: u1, - /// EOTPE. - EOTPE: u1, - /// LPWRE. - LPWRE: u1, - /// GCWRE. - GCWRE: u1, - /// GPWRE. - GPWRE: u1, - /// GPTXE. - GPTXE: u1, - /// GPRDE. - GPRDE: u1, - /// GPRXE. - GPRXE: u1, - padding: u19, - }), - /// DSI Host interrupt enable register 0. - IER0: mmio.Mmio(packed struct(u32) { - /// AE0IE. - AE0IE: u1, - /// AE1IE. - AE1IE: u1, - /// AE2IE. - AE2IE: u1, - /// AE3IE. - AE3IE: u1, - /// AE4IE. - AE4IE: u1, - /// AE5IE. - AE5IE: u1, - /// AE6IE. - AE6IE: u1, - /// AE7IE. - AE7IE: u1, - /// AE8IE. - AE8IE: u1, - /// AE9IE. - AE9IE: u1, - /// AE10IE. - AE10IE: u1, - /// AE11IE. - AE11IE: u1, - /// AE12IE. - AE12IE: u1, - /// AE13IE. - AE13IE: u1, - /// AE14IE. - AE14IE: u1, - /// AE15IE. - AE15IE: u1, - /// PE0IE. - PE0IE: u1, - /// PE1IE. - PE1IE: u1, - /// PE2IE. - PE2IE: u1, - /// PE3IE. - PE3IE: u1, - /// PE4IE. - PE4IE: u1, - padding: u11, - }), - /// DSI Host interrupt enable register 1. - IER1: mmio.Mmio(packed struct(u32) { - /// TOHSTXIE. - TOHSTXIE: u1, - /// TOLPRXIE. - TOLPRXIE: u1, - /// ECCSEIE. - ECCSEIE: u1, - /// ECCMEIE. - ECCMEIE: u1, - /// CRCEIE. - CRCEIE: u1, - /// PSEIE. - PSEIE: u1, - /// EOTPEIE. - EOTPEIE: u1, - /// LPWREIE. - LPWREIE: u1, - /// GCWREIE. - GCWREIE: u1, - /// GPWREIE. - GPWREIE: u1, - /// GPTXEIE. - GPTXEIE: u1, - /// GPRDEIE. - GPRDEIE: u1, - /// GPRXEIE. - GPRXEIE: u1, - padding: u19, - }), - reserved216: [12]u8, - /// DSI Host force interrupt register 0. - FIR0: mmio.Mmio(packed struct(u32) { - /// FAE0. - FAE0: u1, - /// FAE1. - FAE1: u1, - /// FAE2. - FAE2: u1, - /// FAE3. - FAE3: u1, - /// FAE4. - FAE4: u1, - /// FAE5. - FAE5: u1, - /// FAE6. - FAE6: u1, - /// FAE7. - FAE7: u1, - /// FAE8. - FAE8: u1, - /// FAE9. - FAE9: u1, - /// FAE10. - FAE10: u1, - /// FAE11. - FAE11: u1, - /// FAE12. - FAE12: u1, - /// FAE13. - FAE13: u1, - /// FAE14. - FAE14: u1, - /// FAE15. - FAE15: u1, - /// FPE0. - FPE0: u1, - /// FPE1. - FPE1: u1, - /// FPE2. - FPE2: u1, - /// FPE3. - FPE3: u1, - /// FPE4. - FPE4: u1, - padding: u11, - }), - /// DSI Host force interrupt register 1. - FIR1: mmio.Mmio(packed struct(u32) { - /// FTOHSTX. - FTOHSTX: u1, - /// FTOLPRX. - FTOLPRX: u1, - /// FECCSE. - FECCSE: u1, - /// FECCME. - FECCME: u1, - /// FCRCE. - FCRCE: u1, - /// FPSE. - FPSE: u1, - /// FEOTPE. - FEOTPE: u1, - /// FLPWRE. - FLPWRE: u1, - /// FGCWRE. - FGCWRE: u1, - /// FGPWRE. - FGPWRE: u1, - /// FGPTXE. - FGPTXE: u1, - /// FGPRDE. - FGPRDE: u1, - /// FGPRXE. - FGPRXE: u1, - padding: u19, - }), - reserved244: [20]u8, - /// DSI Host data lane timer read configuration register. - DLTRCR: mmio.Mmio(packed struct(u32) { - /// MRD_TIME. - MRD_TIME: u15, - padding: u17, - }), - reserved256: [8]u8, - /// DSI Host video shadow control register. - VSCR: mmio.Mmio(packed struct(u32) { - /// EN. - EN: u1, - reserved8: u7, - /// UR. - UR: u1, - padding: u23, - }), - reserved268: [8]u8, - /// DSI Host LTDC current VCID register. - LCVCIDR: mmio.Mmio(packed struct(u32) { - /// VCID. - VCID: u2, - padding: u30, - }), - /// DSI Host LTDC current color coding register. - LCCCR: mmio.Mmio(packed struct(u32) { - /// COLC. - COLC: u4, - reserved8: u4, - /// LPE. - LPE: u1, - padding: u23, - }), - reserved280: [4]u8, - /// DSI Host low-power mode current configuration register. - LPMCCR: mmio.Mmio(packed struct(u32) { - /// VLPSIZE. - VLPSIZE: u8, - reserved16: u8, - /// LPSIZE. - LPSIZE: u8, - padding: u8, - }), - reserved312: [28]u8, - /// DSI Host video mode current configuration register. - VMCCR: mmio.Mmio(packed struct(u32) { - /// VMT. - VMT: u2, - /// LPVSAE. - LPVSAE: u1, - /// LPVBPE. - LPVBPE: u1, - /// LPVFPE. - LPVFPE: u1, - /// LPVAE. - LPVAE: u1, - /// LPHBPE. - LPHBPE: u1, - /// LPHFE. - LPHFE: u1, - /// FBTAAE. - FBTAAE: u1, - /// LPCE. - LPCE: u1, - padding: u22, - }), - /// DSI Host video packet current configuration register. - VPCCR: mmio.Mmio(packed struct(u32) { - /// VPSIZE. - VPSIZE: u14, - padding: u18, + /// CPU2 cortex M0 status register + C2SR: mmio.Mmio(packed struct(u32) { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved3: u1, + /// Programming error + PROGERR: u1, + /// write protection error + WRPERR: u1, + /// Programming alignment error + PGAERR: u1, + /// Size error + SIZERR: u1, + /// Programming sequence error + PGSERR: u1, + /// Fast programming data miss error + MISSERR: u1, + /// Fast programming error + FASTERR: u1, + reserved14: u4, + /// PCROP read error + RDERR: u1, + reserved16: u1, + /// Busy + BSY: u1, + reserved18: u1, + /// Programming or erase configuration busy + CFGBSY: u1, + /// Programming or erase operation suspended + PESD: u1, + padding: u12, }), - /// DSI Host video chunks current configuration register. - VCCCR: mmio.Mmio(packed struct(u32) { - /// NUMC. - NUMC: u13, - padding: u19, + /// CPU2 cortex M0 control register + C2CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Page erase + PER: u1, + /// Masse erase + MER: u1, + /// Page Number selection + PNB: u8, + reserved16: u5, + /// Start + STRT: u1, + reserved18: u1, + /// Fast programming + FSTPG: u1, + reserved24: u5, + /// End of operation interrupt enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + /// PCROP read error interrupt enable + RDERRIE: u1, + padding: u5, }), - /// DSI Host video null packet current configuration register. - VNPCCR: mmio.Mmio(packed struct(u32) { - /// NPSIZE. - NPSIZE: u13, + reserved128: [24]u8, + /// Secure flash start address register + SFR: mmio.Mmio(packed struct(u32) { + /// Secure flash start address + SFSA: u8, + /// Flash security disable + FSD: u1, + reserved12: u3, + /// Disable Cortex M0 debug access + DDS: u1, padding: u19, }), - /// DSI Host video HSA current configuration register. - VHSACCR: mmio.Mmio(packed struct(u32) { - /// HSA. - HSA: u12, - padding: u20, - }), - /// DSI Host video HBP current configuration register. - VHBPCCR: mmio.Mmio(packed struct(u32) { - /// HBP. - HBP: u12, - padding: u20, - }), - /// DSI Host video line current configuration register. - VLCCR: mmio.Mmio(packed struct(u32) { - /// HLINE. - HLINE: u15, - padding: u17, - }), - /// DSI Host video VSA current configuration register. - VVSACCR: mmio.Mmio(packed struct(u32) { - /// VSA. - VSA: u10, - padding: u22, - }), - /// DSI Host video VBP current configuration register. - VVBPCCR: mmio.Mmio(packed struct(u32) { - /// VBP. - VBP: u10, - padding: u22, - }), - /// DSI Host video VFP current configuration register. - VVFPCCR: mmio.Mmio(packed struct(u32) { - /// VFP. - VFP: u10, - padding: u22, - }), - /// DSI Host video VA current configuration register. - VVACCR: mmio.Mmio(packed struct(u32) { - /// VA. - VA: u14, - padding: u18, - }), - reserved1024: [668]u8, - /// DSI wrapper configuration register. - WCFGR: mmio.Mmio(packed struct(u32) { - /// DSIM. - DSIM: u1, - /// COLMUX. - COLMUX: u3, - /// TESRC. - TESRC: u1, - /// TEPOL. - TEPOL: u1, - /// AR. - AR: u1, - /// VSPOL. - VSPOL: u1, - padding: u24, + /// Secure SRAM2 start address and cortex M0 reset vector register + SRRVR: mmio.Mmio(packed struct(u32) { + /// cortex M0 access control register + SBRV: u18, + /// Secure backup SRAM2a start address + SBRSA: u5, + /// backup SRAM2a security disable + BRSD: u1, + reserved25: u1, + /// Secure non backup SRAM2a start address + SNBRSA: u5, + /// non-backup SRAM2b security disable + NBRSD: u1, + /// CPU2 cortex M0 boot reset vector memory selection + C2OPT: u1, }), - /// DSI wrapper control register. - WCR: mmio.Mmio(packed struct(u32) { - /// COLM. - COLM: u1, - /// SHTDN. - SHTDN: u1, - /// LTDCEN. - LTDCEN: u1, - /// DSIEN. - DSIEN: u1, - padding: u28, + }; + }; + + pub const fmac_v1 = struct { + /// Filter math accelerator + pub const FMAC = extern struct { + /// X1 buffer configuration register + X1BUFCFG: mmio.Mmio(packed struct(u32) { + /// Base address of X1 buffer + X1_BASE: u8, + /// Allocated size of X1 buffer in 16-bit words + X1_BUF_SIZE: u8, + reserved24: u8, + /// Watermark for buffer full flag + FULL_WM: u2, + padding: u6, }), - /// DSI wrapper interrupt enable register. - WIER: mmio.Mmio(packed struct(u32) { - /// TEIE. - TEIE: u1, - /// ERIE. - ERIE: u1, - reserved9: u7, - /// PLLLIE. - PLLLIE: u1, - /// PLLUIE. - PLLUIE: u1, - reserved13: u2, - /// RRIE. - RRIE: u1, - padding: u18, + /// X2 buffer configuration register + X2BUFCFG: mmio.Mmio(packed struct(u32) { + /// Base address of X2 buffer + X2_BASE: u8, + /// Size of X2 buffer in 16-bit words + X2_BUF_SIZE: u8, + padding: u16, }), - /// DSI wrapper interrupt and status register. - WISR: mmio.Mmio(packed struct(u32) { - /// TEIF. - TEIF: u1, - /// ERIF. - ERIF: u1, - /// BUSY. - BUSY: u1, - reserved8: u5, - /// PLLLS. - PLLLS: u1, - /// PLLLIF. - PLLLIF: u1, - /// PLLUIF. - PLLUIF: u1, - reserved12: u1, - /// RRS. - RRS: u1, - /// RRIF. - RRIF: u1, - padding: u18, + /// Y buffer configuration register + YBUFCFG: mmio.Mmio(packed struct(u32) { + /// Base address of Y buffer + Y_BASE: u8, + /// Size of Y buffer in 16-bit words + Y_BUF_SIZE: u8, + reserved24: u8, + /// Watermark for buffer empty flag + EMPTY_WM: u2, + padding: u6, }), - /// DSI wrapper interrupt flag clear register. - WIFCR: mmio.Mmio(packed struct(u32) { - /// CTEIF. - CTEIF: u1, - /// CERIF. - CERIF: u1, - reserved9: u7, - /// CPLLLIF. - CPLLLIF: u1, - /// CPLLUIF. - CPLLUIF: u1, - reserved13: u2, - /// CRRIF. - CRRIF: u1, - padding: u18, + /// Parameter register + PARAM: mmio.Mmio(packed struct(u32) { + /// Input parameter P + P: u8, + /// Input parameter Q + Q: u8, + /// Input parameter R + R: u8, + /// Function + FUNC: u7, + /// Enable execution + START: u1, }), - reserved1048: [4]u8, - /// DSI wrapper PHY configuration register 0. - WPCR0: mmio.Mmio(packed struct(u32) { - /// UIX4. - UIX4: u6, - /// SWCL. - SWCL: u1, - /// SWDL0. - SWDL0: u1, - /// SWDL1. - SWDL1: u1, - /// HSICL. - HSICL: u1, - /// HSIDL0. - HSIDL0: u1, - /// HSIDL1. - HSIDL1: u1, - /// FTXSMCL. - FTXSMCL: u1, - /// FTXSMDL. - FTXSMDL: u1, - /// CDOFFDL. - CDOFFDL: u1, - reserved16: u1, - /// TDDL. - TDDL: u1, + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Enable read interrupt + RIEN: u1, + /// Enable write interrupt + WIEN: u1, + /// Enable overflow error interrupts + OVFLIEN: u1, + /// Enable underflow error interrupts + UNFLIEN: u1, + /// Enable saturation error interrupts + SATIEN: u1, + reserved8: u3, + /// Enable DMA read channel requests + DMAREN: u1, + /// Enable DMA write channel requests + DMAWEN: u1, + reserved15: u5, + /// Enable clipping + CLIPEN: u1, + /// Reset FMAC unit + RESET: u1, padding: u15, }), - /// This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0). - WPCR1: mmio.Mmio(packed struct(u32) { - /// SKEWCL. - SKEWCL: u2, - /// SKEWDL. - SKEWDL: u2, - reserved6: u2, - /// LPTXSRCL. - LPTXSRCL: u2, - /// LPTXSRDL. - LPTXSRDL: u2, - reserved12: u2, - /// SDDCCL. - SDDCCL: u1, - /// SDDCDL. - SDDCDL: u1, - reserved16: u2, - /// HSTXSRUCL. - HSTXSRUCL: u1, - /// HSTXSRDCL. - HSTXSRDCL: u1, - /// HSTXSRUDL. - HSTXSRUDL: u1, - /// HSTXSRDDL. - HSTXSRDDL: u1, - padding: u12, - }), - reserved1072: [16]u8, - /// DSI wrapper regulator and PLL control register. - WRPCR: mmio.Mmio(packed struct(u32) { - /// PLLEN. - PLLEN: u1, - reserved2: u1, - /// NDIV. - NDIV: u7, - reserved11: u2, - /// IDF. - IDF: u4, - reserved16: u1, - /// ODF. - ODF: u2, - reserved24: u6, - /// REGEN. - REGEN: u1, - reserved28: u3, - /// BGREN. - BGREN: u1, - padding: u3, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Y buffer empty flag + YEMPTY: u1, + /// X1 buffer full flag + X1FULL: u1, + reserved8: u6, + /// Overflow error flag + OVFL: u1, + /// Underflow error flag + UNFL: u1, + /// Saturation error flag + SAT: u1, + padding: u21, }), - reserved2032: [956]u8, - /// DSI Host hardware configuration register. - HWCFGR: mmio.Mmio(packed struct(u32) { - /// TECHNO. - TECHNO: u4, - /// FIFOSIZE. - FIFOSIZE: u12, + /// Write data register + WDATA: mmio.Mmio(packed struct(u32) { + /// Write data (write data are transferred to the address indicated by the write pointer) + WDATA: u16, padding: u16, }), - /// DSI Host version register. - VERR: mmio.Mmio(packed struct(u32) { - /// MINREV. - MINREV: u4, - /// MAJREV. - MAJREV: u4, - padding: u24, - }), - /// DSI Host identification register. - IPIDR: mmio.Mmio(packed struct(u32) { - /// ID. - ID: u32, - }), - /// DSI Host size identification register. - SIDR: mmio.Mmio(packed struct(u32) { - /// SID. - SID: u32, + /// Read data register + RDATA: mmio.Mmio(packed struct(u32) { + /// Read data (contents of the Y output buffer at the address indicated by the READ pointer) + RES: u16, + padding: u16, }), }; }; - pub const rcc_f1 = struct { - pub const ADCPRE = enum(u2) { - /// PCLK2 divided by 2 - Div2 = 0x0, - /// PCLK2 divided by 4 - Div4 = 0x1, - /// PCLK2 divided by 6 - Div6 = 0x2, - /// PCLK2 divided by 8 - Div8 = 0x3, + pub const fmc_v1x3 = struct { + pub const ACCMOD = enum(u2) { + /// Access mode A + A = 0x0, + /// Access mode B + B = 0x1, + /// Access mode C + C = 0x2, + /// Access mode D + D = 0x3, }; - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, + pub const CAS = enum(u2) { + /// 1 cycle + Clocks1 = 0x1, + /// 2 cycles + Clocks2 = 0x2, + /// 3 cycles + Clocks3 = 0x3, _, }; - pub const MCOSEL = enum(u3) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// System clock selected - SYS = 0x4, - /// HSI oscillator clock selected - HSI = 0x5, - /// HSE oscillator clock selected - HSE = 0x6, - /// PLL clock divided by 2 selected - PLL = 0x7, + pub const CPSIZE = enum(u3) { + /// No burst split when crossing page boundary + NoBurstSplit = 0x0, + /// 128 bytes CRAM page size + Bytes128 = 0x1, + /// 256 bytes CRAM page size + Bytes256 = 0x2, + /// 512 bytes CRAM page size + Bytes512 = 0x3, + /// 1024 bytes CRAM page size + Bytes1024 = 0x4, _, }; - pub const PLLMUL = enum(u4) { - /// PLL input clock x2 - Mul2 = 0x0, - /// PLL input clock x3 - Mul3 = 0x1, - /// PLL input clock x4 - Mul4 = 0x2, - /// PLL input clock x5 - Mul5 = 0x3, - /// PLL input clock x6 - Mul6 = 0x4, - /// PLL input clock x7 - Mul7 = 0x5, - /// PLL input clock x8 - Mul8 = 0x6, - /// PLL input clock x9 - Mul9 = 0x7, - /// PLL input clock x10 - Mul10 = 0x8, - /// PLL input clock x11 - Mul11 = 0x9, - /// PLL input clock x12 - Mul12 = 0xa, - /// PLL input clock x13 - Mul13 = 0xb, - /// PLL input clock x14 - Mul14 = 0xc, - /// PLL input clock x15 - Mul15 = 0xd, - /// PLL input clock x16 - Mul16 = 0xe, + pub const ECCPS = enum(u3) { + /// ECC page size 256 bytes + Bytes256 = 0x0, + /// ECC page size 512 bytes + Bytes512 = 0x1, + /// ECC page size 1024 bytes + Bytes1024 = 0x2, + /// ECC page size 2048 bytes + Bytes2048 = 0x3, + /// ECC page size 4096 bytes + Bytes4096 = 0x4, + /// ECC page size 8192 bytes + Bytes8192 = 0x5, _, }; - pub const PLLSRC = enum(u1) { - /// HSI divided by 2 selected as PLL input clock - HSI_Div2 = 0x0, - /// HSE divided by PREDIV selected as PLL input clock - HSE_Div_PREDIV = 0x1, + pub const MODE = enum(u3) { + /// Normal Mode + Normal = 0x0, + /// Clock Configuration Enable + ClockConfigurationEnable = 0x1, + /// PALL (All Bank Precharge) command + PALL = 0x2, + /// Auto-refresh command + AutoRefreshCommand = 0x3, + /// Load Mode Resgier + LoadModeRegister = 0x4, + /// Self-refresh command + SelfRefreshCommand = 0x5, + /// Power-down command + PowerDownCommand = 0x6, + _, }; - pub const PLLXTPRE = enum(u1) { - /// HSE clock not divided - Div1 = 0x0, - /// HSE clock divided by 2 - Div2 = 0x1, + pub const MODES = enum(u2) { + /// Normal Mode + Normal = 0x0, + /// Self-refresh mode + SelfRefresh = 0x1, + /// Power-down mode + PowerDown = 0x2, + _, }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, + pub const MTYP = enum(u2) { + /// SRAM memory type + SRAM = 0x0, + /// PSRAM (CRAM) memory type + PSRAM = 0x1, + /// NOR Flash/OneNAND Flash + Flash = 0x2, _, }; - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, + pub const MWID = enum(u2) { + /// Memory data bus width 8 bits + Bits8 = 0x0, + /// Memory data bus width 16 bits + Bits16 = 0x1, + /// Memory data bus width 32 bits + Bits32 = 0x2, + _, }; - pub const SW = enum(u2) { - /// HSI selected as system clock - HSI = 0x0, - /// HSE selected as system clock - HSE = 0x1, - /// PLL selected as system clock - PLL1_P = 0x2, + pub const NB = enum(u1) { + /// Two internal Banks + NB2 = 0x0, + /// Four internal Banks + NB4 = 0x1, + }; + + pub const NC = enum(u2) { + /// 8 bits + Bits8 = 0x0, + /// 9 bits + Bits9 = 0x1, + /// 10 bits + Bits10 = 0x2, + /// 11 bits + Bits11 = 0x3, + }; + + pub const NR = enum(u2) { + /// 11 bits + Bits11 = 0x0, + /// 12 bits + Bits12 = 0x1, + /// 13 bits + Bits13 = 0x2, _, }; - pub const USBPRE = enum(u1) { - /// PLL clock is divided by 1.5 - Div1_5 = 0x0, - /// PLL clock is not divided - Div1 = 0x1, + pub const PTYP = enum(u1) { + /// NAND Flash + NANDFlash = 0x1, + _, }; - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal High Speed clock enable - HSION: u1, - /// Internal High Speed clock ready flag - HSIRDY: u1, - reserved3: u1, - /// Internal High Speed clock trimming - HSITRIM: u5, - /// Internal High Speed clock Calibration - HSICAL: u8, - /// External High Speed clock enable - HSEON: u1, - /// External High Speed clock ready flag - HSERDY: u1, - /// External High Speed clock Bypass - HSEBYP: u1, - /// Clock Security System enable - CSSON: u1, - reserved24: u4, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding: u6, - }), - /// Clock configuration register (RCC_CFGR) - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock Switch - SW: packed union { + pub const PWID = enum(u2) { + /// External memory device width 8 bits + Bits8 = 0x0, + /// External memory device width 16 bits + Bits16 = 0x1, + _, + }; + + pub const RPIPE = enum(u2) { + /// No clock cycle delay + NoDelay = 0x0, + /// One clock cycle delay + Clocks1 = 0x1, + /// Two clock cycles delay + Clocks2 = 0x2, + _, + }; + + pub const SDCLK = enum(u2) { + /// SDCLK clock disabled + Disabled = 0x0, + /// SDCLK period = 2 x HCLK period + Div2 = 0x2, + /// SDCLK period = 3 x HCLK period + Div3 = 0x3, + _, + }; + + pub const WAITCFG = enum(u1) { + /// NWAIT signal is active one data cycle before wait state + BeforeWaitState = 0x0, + /// NWAIT signal is active during wait state + DuringWaitState = 0x1, + }; + + pub const WAITPOL = enum(u1) { + /// NWAIT active low + ActiveLow = 0x0, + /// NWAIT active high + ActiveHigh = 0x1, + }; + + /// Flexible memory controller + pub const FMC = extern struct { + /// SRAM/NOR-Flash chip-select control register 1 + BCR1: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { raw: u2, - value: SW, + value: MTYP, }, - /// System Clock Switch Status - SWS: packed union { + /// Memory data bus width + MWID: packed union { raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, + value: MWID, }, - /// APB Low speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { + raw: u1, + value: WAITPOL, }, - /// APB High speed prescaler (APB2) - PPRE2: packed union { + /// WRAPMOD + WRAPMOD: u1, + /// Wait timing configuration + WAITCFG: packed union { + raw: u1, + value: WAITCFG, + }, + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + /// CRAM page size + CPSIZE: packed union { raw: u3, - value: PPRE, + value: CPSIZE, }, - /// ADC prescaler - ADCPRE: packed union { + /// Write burst enable + CBURSTRW: u1, + /// Continuous clock enable + CCLKEN: u1, + padding: u11, + }), + /// SRAM/NOR-Flash chip-select timing register 1-4 + BTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + /// Clock divide ratio (for FMC_CLK signal) + CLKDIV: u4, + /// Data latency for synchronous memory + DATLAT: u4, + /// Access mode + ACCMOD: packed union { raw: u2, - value: ADCPRE, + value: ACCMOD, }, - /// PLL entry clock source - PLLSRC: packed union { + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 2-4 + BCR: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { + raw: u2, + value: MTYP, + }, + /// Memory data bus width + MWID: packed union { + raw: u2, + value: MWID, + }, + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { raw: u1, - value: PLLSRC, + value: WAITPOL, }, - /// HSE divider for PLL entry - PLLXTPRE: packed union { + /// WRAPMOD + WRAPMOD: u1, + /// Wait timing configuration + WAITCFG: packed union { raw: u1, - value: PLLXTPRE, + value: WAITCFG, }, - /// PLL Multiplication Factor - PLLMUL: packed union { - raw: u4, - value: PLLMUL, + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + /// CRAM page size + CPSIZE: packed union { + raw: u3, + value: CPSIZE, }, - /// USB prescaler - USBPRE: packed union { + /// Write burst enable + CBURSTRW: u1, + padding: u12, + }), + reserved96: [84]u8, + /// PC Card/NAND Flash control register 2-4 + PCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Wait feature enable bit + PWAITEN: u1, + /// NAND Flash memory bank enable bit + PBKEN: u1, + /// Memory type + PTYP: packed union { raw: u1, - value: USBPRE, + value: PTYP, }, - reserved24: u1, - /// Microcontroller clock output - MCOSEL: packed union { + /// Data bus width + PWID: packed union { + raw: u2, + value: PWID, + }, + /// ECC computation logic enable bit + ECCEN: u1, + reserved9: u2, + /// CLE to RE delay + TCLR: u4, + /// ALE to RE delay + TAR: u4, + /// ECC page size + ECCPS: packed union { raw: u3, - value: MCOSEL, + value: ECCPS, }, - padding: u5, + padding: u12, }), - /// Clock interrupt register (RCC_CIR) - CIR: mmio.Mmio(packed struct(u32) { - /// LSI Ready Interrupt flag - LSIRDYF: u1, - /// LSE Ready Interrupt flag - LSERDYF: u1, - /// HSI Ready Interrupt flag - HSIRDYF: u1, - /// HSE Ready Interrupt flag - HSERDYF: u1, - /// PLL Ready Interrupt flag - PLLRDYF: u1, - reserved7: u2, - /// Clock Security System Interrupt flag - CSSF: u1, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1, - /// LSE Ready Interrupt Enable - LSERDYIE: u1, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1, - /// HSE Ready Interrupt Enable - HSERDYIE: u1, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1, - reserved16: u3, - /// LSI Ready Interrupt Clear - LSIRDYC: u1, - /// LSE Ready Interrupt Clear - LSERDYC: u1, - /// HSI Ready Interrupt Clear - HSIRDYC: u1, - /// HSE Ready Interrupt Clear - HSERDYC: u1, - /// PLL Ready Interrupt Clear - PLLRDYC: u1, - reserved23: u2, - /// Clock security system interrupt clear - CSSC: u1, - padding: u8, + /// FIFO status and interrupt register 2-4 + SR: mmio.Mmio(packed struct(u32) { + /// Interrupt rising edge status + IRS: u1, + /// Interrupt high-level status + ILS: u1, + /// Interrupt falling edge status + IFS: u1, + /// Interrupt rising edge detection enable bit + IREN: u1, + /// Interrupt high-level detection enable bit + ILEN: u1, + /// Interrupt falling edge detection enable bit + IFEN: u1, + /// FIFO empty status + FEMPT: u1, + padding: u25, }), - /// APB2 peripheral reset register (RCC_APB2RSTR) - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// Alternate function I/O reset - AFIORST: u1, - reserved2: u1, - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - /// IO port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// ADC 1 interface reset - ADC1RST: u1, - /// ADC 2 interface reset - ADC2RST: u1, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI 1 reset - SPI1RST: u1, - /// TIM8 timer reset - TIM8RST: u1, - /// USART1 reset - USART1RST: u1, - /// ADC 3 interface reset - ADC3RST: u1, - reserved19: u3, - /// TIM9 timer reset - TIM9RST: u1, - /// TIM10 timer reset - TIM10RST: u1, - /// TIM11 timer reset - TIM11RST: u1, - padding: u10, + /// Common memory space timing register 2-4 + PMEM: mmio.Mmio(packed struct(u32) { + /// Common memory x setup time + MEMSET: u8, + /// Common memory wait time + MEMWAIT: u8, + /// Common memory hold time + MEMHOLD: u8, + /// Common memory x data bus Hi-Z time + MEMHIZ: u8, }), - /// APB1 peripheral reset register (RCC_APB1RSTR) - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - /// Timer 4 reset - TIM4RST: u1, - /// Timer 5 reset - TIM5RST: u1, - /// Timer 6 reset - TIM6RST: u1, - /// Timer 7 reset - TIM7RST: u1, - /// Timer 12 reset - TIM12RST: u1, - /// Timer 13 reset - TIM13RST: u1, - /// Timer 14 reset - TIM14RST: u1, - reserved11: u2, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI2 reset - SPI2RST: u1, - /// SPI3 reset - SPI3RST: u1, - reserved17: u1, - /// USART 2 reset - USART2RST: u1, - /// USART 3 reset - USART3RST: u1, - /// USART 4 reset - UART4RST: u1, - /// USART 5 reset - UART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// USB reset - USBRST: u1, - reserved25: u1, - /// CAN reset - CANRST: u1, - reserved27: u1, - /// Backup interface reset - BKPRST: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - padding: u2, + /// Attribute memory space timing register 2-4 + PATT: mmio.Mmio(packed struct(u32) { + /// Attribute memory setup time + ATTSET: u8, + /// Attribute memory wait time + ATTWAIT: u8, + /// Attribute memory hold time + ATTHOLD: u8, + /// Attribute memory data bus Hi-Z time + ATTHIZ: u8, }), - /// AHB Peripheral Clock enable register (RCC_AHBENR) - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// SRAM interface clock enable - SRAMEN: u1, - reserved4: u1, - /// FLASH clock enable - FLASHEN: u1, - reserved6: u1, - /// CRC clock enable - CRCEN: u1, - reserved8: u1, - /// FSMC clock enable - FSMCEN: u1, - reserved10: u1, - /// SDIO clock enable - SDIOEN: u1, - padding: u21, + reserved116: [4]u8, + /// ECC result register 2-3 + ECCR: mmio.Mmio(packed struct(u32) { + /// ECC computation result value + ECC: u32, }), - /// APB2 peripheral clock enable register (RCC_APB2ENR) - APB2ENR: mmio.Mmio(packed struct(u32) { - /// Alternate function I/O clock enable - AFIOEN: u1, - reserved2: u1, - /// I/O port A clock enable - GPIOAEN: u1, - /// I/O port B clock enable - GPIOBEN: u1, - /// I/O port C clock enable - GPIOCEN: u1, - /// I/O port D clock enable - GPIODEN: u1, - /// I/O port E clock enable - GPIOEEN: u1, - /// I/O port F clock enable - GPIOFEN: u1, - /// I/O port G clock enable - GPIOGEN: u1, - /// ADC 1 interface clock enable - ADC1EN: u1, - /// ADC 2 interface clock enable - ADC2EN: u1, - /// TIM1 Timer clock enable - TIM1EN: u1, - /// SPI 1 clock enable - SPI1EN: u1, - /// TIM8 Timer clock enable - TIM8EN: u1, - /// USART1 clock enable - USART1EN: u1, - /// ADC3 interface clock enable - ADC3EN: u1, - reserved19: u3, - /// TIM9 Timer clock enable - TIM9EN: u1, - /// TIM10 Timer clock enable - TIM10EN: u1, - /// TIM11 Timer clock enable - TIM11EN: u1, - padding: u10, + reserved176: [56]u8, + /// I/O space timing register 4 + PIO4: mmio.Mmio(packed struct(u32) { + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, }), - /// APB1 peripheral clock enable register (RCC_APB1ENR) - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer 2 clock enable - TIM2EN: u1, - /// Timer 3 clock enable - TIM3EN: u1, - /// Timer 4 clock enable - TIM4EN: u1, - /// Timer 5 clock enable - TIM5EN: u1, - /// Timer 6 clock enable - TIM6EN: u1, - /// Timer 7 clock enable - TIM7EN: u1, - /// Timer 12 clock enable - TIM12EN: u1, - /// Timer 13 clock enable - TIM13EN: u1, - /// Timer 14 clock enable - TIM14EN: u1, - reserved11: u2, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI 2 clock enable - SPI2EN: u1, - /// SPI 3 clock enable - SPI3EN: u1, - reserved17: u1, - /// USART 2 clock enable - USART2EN: u1, - /// USART 3 clock enable - USART3EN: u1, - /// UART 4 clock enable - UART4EN: u1, - /// UART 5 clock enable - UART5EN: u1, - /// I2C 1 clock enable - I2C1EN: u1, - /// I2C 2 clock enable - I2C2EN: u1, - /// USB clock enable - USBEN: u1, - reserved25: u1, - /// CAN clock enable - CANEN: u1, - reserved27: u1, - /// Backup interface clock enable - BKPEN: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, + reserved260: [80]u8, + /// SRAM/NOR-Flash write timing registers 1-4 + BWTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + reserved28: u8, + /// Access mode + ACCMOD: packed union { + raw: u2, + value: ACCMOD, + }, padding: u2, }), - /// Backup domain control register (RCC_BDCR) - BDCR: mmio.Mmio(packed struct(u32) { - /// External Low Speed oscillator enable - LSEON: u1, - /// External Low Speed oscillator ready - LSERDY: u1, - /// External Low Speed oscillator bypass - LSEBYP: u1, - reserved8: u5, - /// RTC clock source selection - RTCSEL: packed union { + reserved320: [56]u8, + /// SDRAM Control Register 1-2 + SDCR: [2]mmio.Mmio(packed struct(u32) { + /// Number of column address bits + NC: packed union { raw: u2, - value: RTCSEL, + value: NC, }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - padding: u15, - }), - /// Control/status register (RCC_CSR) - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low speed oscillator enable - LSION: u1, - /// Internal low speed oscillator ready - LSIRDY: u1, - reserved24: u22, - /// Remove reset flag - RMVF: u1, - reserved26: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, - }), - }; - }; - - pub const pwr_g0 = struct { - pub const VOS = enum(u2) { - Range1 = 0x1, - Range2 = 0x2, - _, - }; - - /// Power control - pub const PWR = extern struct { - /// Power control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection - LPMS: u3, - /// Flash memory powered down during Stop mode - FPD_STOP: u1, - /// Flash memory powered down during Low-power run mode - FPD_LPRUN: u1, - /// Flash memory powered down during Low-power sleep mode - FPD_LPSLP: u1, - reserved8: u2, - /// Disable backup domain write protection - DBP: u1, - /// Voltage scaling range selection - VOS: packed union { + /// Number of row address bits + NR: packed union { raw: u2, - value: VOS, + value: NR, }, - reserved14: u3, - /// Low-power run - LPR: u1, - padding: u17, - }), - /// Power control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Power voltage detector enable - PVDE: u1, - /// Power voltage detector falling threshold selection - PVDFT: u3, - /// Power voltage detector rising threshold selection - PVDRT: u3, - padding: u25, - }), - /// Power control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin - EWUP: u1, - reserved8: u7, - /// SRAM retention in Standby mode - RRS: u1, - /// Enable the periodical sampling mode for PDR detection - ULPEN: u1, - /// Apply pull-up and pull-down configuration - APC: u1, - reserved15: u4, - /// Enable internal wakeup line - EIWUL: u1, - padding: u16, - }), - /// Power control register 4 - CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity + /// Memory data bus width + MWID: packed union { + raw: u2, + value: MWID, + }, + /// Number of internal banks + NB: packed union { + raw: u1, + value: NB, + }, + /// CAS latency + CAS: packed union { + raw: u2, + value: CAS, + }, + /// Write protection WP: u1, - reserved8: u7, - /// VBAT battery charging enable - VBE: u1, - /// VBAT battery charging resistor selection - VBRS: u1, - padding: u22, - }), - /// Power status register 1 - SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag - WUF: u1, - reserved8: u7, - /// Standby flag - SBF: u1, - reserved15: u6, - /// Wakeup flag internal - WUFI: u1, - padding: u16, + /// SDRAM clock configuration + SDCLK: packed union { + raw: u2, + value: SDCLK, + }, + /// Burst read + RBURST: u1, + /// Read pipe + RPIPE: packed union { + raw: u2, + value: RPIPE, + }, + padding: u17, }), - /// Power status register 2 - SR2: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// Flash ready flag - FLASH_RDY: u1, - /// Low-power regulator started - REGLPS: u1, - /// Low-power regulator flag - REGLPF: u1, - /// Voltage scaling flag - VOSF: u1, - /// Power voltage detector output - PVDO: u1, - padding: u20, + /// SDRAM Timing register 1-2 + SDTR: [2]mmio.Mmio(packed struct(u32) { + /// Load Mode Register to Active + TMRD: u4, + /// Exit self-refresh delay + TXSR: u4, + /// Self refresh time + TRAS: u4, + /// Row cycle delay + TRC: u4, + /// Recovery delay + TWR: u4, + /// Row precharge delay + TRP: u4, + /// Row to column delay + TRCD: u4, + padding: u4, }), - /// Power status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear Wakeup flag - CWUF: u1, - reserved8: u7, - /// Clear standby flag - CSBF: u1, - padding: u23, + /// SDRAM Command Mode register + SDCMR: mmio.Mmio(packed struct(u32) { + /// Command mode + MODE: packed union { + raw: u3, + value: MODE, + }, + /// Command target bank 2 + CTB2: u1, + /// Command target bank 1 + CTB1: u1, + /// Number of Auto-refresh + NRFS: u4, + /// Mode Register definition + MRD: u13, + padding: u10, }), - reserved32: [4]u8, - /// Power Port pull-up control register - PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// SDRAM Refresh Timer register + SDRTR: mmio.Mmio(packed struct(u32) { + /// Clear Refresh error flag + CRE: u1, + /// Refresh Timer Count + COUNT: u13, + /// RES Interrupt Enable + REIE: u1, + padding: u17, }), - /// Power Port pull-down control register - PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// SDRAM Status register + SDSR: mmio.Mmio(packed struct(u32) { + /// Refresh error flag + RE: u1, + /// Status Mode for Bank 1 + MODES1: packed union { + raw: u2, + value: MODES, + }, + /// Status Mode for Bank 2 + MODES2: packed union { + raw: u2, + value: MODES, + }, + /// Busy status + BUSY: u1, + padding: u26, }), }; }; - pub const adc_v3 = struct { - pub const DMACFG = enum(u1) { - /// DMA One Shot mode selected - OneShot = 0x0, - /// DMA Circular mode selected - Circular = 0x1, + pub const fmc_v2x1 = struct { + pub const ACCMOD = enum(u2) { + /// Access mode A + A = 0x0, + /// Access mode B + B = 0x1, + /// Access mode C + C = 0x2, + /// Access mode D + D = 0x3, }; - pub const RES = enum(u2) { - /// 12-bit resolution - Bits12 = 0x0, - /// 10-bit resolution - Bits10 = 0x1, - /// 8-bit resolution - Bits8 = 0x2, - /// 6-bit resolution - Bits6 = 0x3, + pub const CAS = enum(u2) { + /// 1 cycle + Clocks1 = 0x1, + /// 2 cycles + Clocks2 = 0x2, + /// 3 cycles + Clocks3 = 0x3, + _, }; - pub const SAMPLE_TIME = enum(u3) { - /// 2.5 ADC cycles - Cycles2_5 = 0x0, - /// 6.5 ADC cycles - Cycles6_5 = 0x1, - /// 12.5 ADC cycles - Cycles12_5 = 0x2, - /// 24.5 ADC cycles - Cycles24_5 = 0x3, - /// 47.5 ADC cycles - Cycles47_5 = 0x4, - /// 92.5 ADC cycles - Cycles92_5 = 0x5, - /// 247.5 ADC cycles - Cycles247_5 = 0x6, - /// 640.5 ADC cycles - Cycles640_5 = 0x7, + pub const CPSIZE = enum(u3) { + /// No burst split when crossing page boundary + NoBurstSplit = 0x0, + /// 128 bytes CRAM page size + Bytes128 = 0x1, + /// 256 bytes CRAM page size + Bytes256 = 0x2, + /// 512 bytes CRAM page size + Bytes512 = 0x3, + /// 1024 bytes CRAM page size + Bytes1024 = 0x4, + _, }; - /// Analog-to-Digital Converter - pub const ADC = extern struct { - /// interrupt and status register - ISR: mmio.Mmio(packed struct(u32) { - /// ADRDY - ADRDY: u1, - /// EOSMP - EOSMP: u1, - /// EOC - EOC: u1, - /// EOS - EOS: u1, - /// OVR - OVR: u1, - /// JEOC - JEOC: u1, - /// JEOS - JEOS: u1, - /// AWD1 - AWD: u1, - reserved10: u2, - /// JQOVF - JQOVF: u1, - padding: u21, - }), - /// interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// ADRDYIE - ADRDYIE: u1, - /// EOSMPIE - EOSMPIE: u1, - /// EOCIE - EOCIE: u1, - /// EOSIE - EOSIE: u1, - /// OVRIE - OVRIE: u1, - /// JEOCIE - JEOCIE: u1, - /// JEOSIE - JEOSIE: u1, - /// AWD1IE - AWD1IE: u1, - /// AWD2IE - AWD2IE: u1, - /// AWD3IE - AWD3IE: u1, - /// JQOVFIE - JQOVFIE: u1, - padding: u21, - }), - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// ADEN - ADEN: u1, - /// ADDIS - ADDIS: u1, - /// ADSTART - ADSTART: u1, - /// JADSTART - JADSTART: u1, - /// ADSTP - ADSTP: u1, - /// JADSTP - JADSTP: u1, - reserved28: u22, - /// ADVREGEN - ADVREGEN: u1, - /// DEEPPWD - DEEPPWD: u1, - /// ADCALDIF - ADCALDIF: u1, - /// ADCAL - ADCAL: u1, - }), - /// configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// DMAEN - DMAEN: u1, - /// Direct memory access configuration - DMACFG: packed union { - raw: u1, - value: DMACFG, - }, - reserved3: u1, - /// RES - RES: packed union { + pub const ECCPS = enum(u3) { + /// ECC page size 256 bytes + Bytes256 = 0x0, + /// ECC page size 512 bytes + Bytes512 = 0x1, + /// ECC page size 1024 bytes + Bytes1024 = 0x2, + /// ECC page size 2048 bytes + Bytes2048 = 0x3, + /// ECC page size 4096 bytes + Bytes4096 = 0x4, + /// ECC page size 8192 bytes + Bytes8192 = 0x5, + _, + }; + + pub const MODE = enum(u3) { + /// Normal Mode + Normal = 0x0, + /// Clock Configuration Enable + ClockConfigurationEnable = 0x1, + /// PALL (All Bank Precharge) command + PALL = 0x2, + /// Auto-refresh command + AutoRefreshCommand = 0x3, + /// Load Mode Resgier + LoadModeRegister = 0x4, + /// Self-refresh command + SelfRefreshCommand = 0x5, + /// Power-down command + PowerDownCommand = 0x6, + _, + }; + + pub const MODES = enum(u2) { + /// Normal Mode + Normal = 0x0, + /// Self-refresh mode + SelfRefresh = 0x1, + /// Power-down mode + PowerDown = 0x2, + _, + }; + + pub const MTYP = enum(u2) { + /// SRAM memory type + SRAM = 0x0, + /// PSRAM (CRAM) memory type + PSRAM = 0x1, + /// NOR Flash/OneNAND Flash + Flash = 0x2, + _, + }; + + pub const MWID = enum(u2) { + /// Memory data bus width 8 bits + Bits8 = 0x0, + /// Memory data bus width 16 bits + Bits16 = 0x1, + /// Memory data bus width 32 bits + Bits32 = 0x2, + _, + }; + + pub const NB = enum(u1) { + /// Two internal Banks + NB2 = 0x0, + /// Four internal Banks + NB4 = 0x1, + }; + + pub const NC = enum(u2) { + /// 8 bits + Bits8 = 0x0, + /// 9 bits + Bits9 = 0x1, + /// 10 bits + Bits10 = 0x2, + /// 11 bits + Bits11 = 0x3, + }; + + pub const NR = enum(u2) { + /// 11 bits + Bits11 = 0x0, + /// 12 bits + Bits12 = 0x1, + /// 13 bits + Bits13 = 0x2, + _, + }; + + pub const PTYP = enum(u1) { + /// NAND Flash + NANDFlash = 0x1, + _, + }; + + pub const PWID = enum(u2) { + /// External memory device width 8 bits + Bits8 = 0x0, + /// External memory device width 16 bits + Bits16 = 0x1, + _, + }; + + pub const RPIPE = enum(u2) { + /// No clock cycle delay + NoDelay = 0x0, + /// One clock cycle delay + Clocks1 = 0x1, + /// Two clock cycles delay + Clocks2 = 0x2, + _, + }; + + pub const SDCLK = enum(u2) { + /// SDCLK clock disabled + Disabled = 0x0, + /// SDCLK period = 2 x HCLK period + Div2 = 0x2, + /// SDCLK period = 3 x HCLK period + Div3 = 0x3, + _, + }; + + pub const WAITCFG = enum(u1) { + /// NWAIT signal is active one data cycle before wait state + BeforeWaitState = 0x0, + /// NWAIT signal is active during wait state + DuringWaitState = 0x1, + }; + + pub const WAITPOL = enum(u1) { + /// NWAIT active low + ActiveLow = 0x0, + /// NWAIT active high + ActiveHigh = 0x1, + }; + + /// Flexible memory controller + pub const FMC = extern struct { + /// SRAM/NOR-Flash chip-select control register 1 + BCR1: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { raw: u2, - value: RES, + value: MTYP, }, - /// ALIGN - ALIGN: u1, - /// EXTSEL - EXTSEL: u4, - /// EXTEN - EXTEN: u2, - /// OVRMOD - OVRMOD: u1, - /// CONT - CONT: u1, - /// AUTDLY - AUTDLY: u1, - /// AUTOFF - AUTOFF: u1, - /// DISCEN - DISCEN: u1, - /// DISCNUM - DISCNUM: u3, - /// JDISCEN - JDISCEN: u1, - /// JQM - JQM: u1, - /// AWD1SGL - AWD1SGL: u1, - /// AWD1EN - AWD1EN: u1, - /// JAWD1EN - JAWD1EN: u1, - /// JAUTO - JAUTO: u1, - /// AWDCH1CH - AWDCH1CH: u5, - padding: u1, - }), - /// configuration register - CFGR2: mmio.Mmio(packed struct(u32) { - /// DMAEN - ROVSE: u1, - /// DMACFG - JOVSE: u1, - /// RES - OVSR: u3, - /// ALIGN - OVSS: u4, - /// EXTSEL - TOVS: u1, - /// EXTEN - ROVSM: u1, - padding: u21, - }), - /// sample time register 1 - SMPR: [2]mmio.Mmio(packed struct(u32) { - /// Channel 0 sampling time selection - SMP: packed union { + /// Memory data bus width + MWID: packed union { + raw: u2, + value: MWID, + }, + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { + raw: u1, + value: WAITPOL, + }, + reserved11: u1, + /// Wait timing configuration + WAITCFG: packed union { + raw: u1, + value: WAITCFG, + }, + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + /// CRAM page size + CPSIZE: packed union { raw: u3, - value: SAMPLE_TIME, + value: CPSIZE, }, - padding: u29, + /// Write burst enable + CBURSTRW: u1, + /// Continuous clock enable + CCLKEN: u1, + /// Write FIFO disable + WFDIS: u1, + padding: u10, }), - reserved32: [4]u8, - /// watchdog threshold register 1 - TR: [3]mmio.Mmio(packed struct(u32) { - /// LT1 - LT: u12, - reserved16: u4, - /// HT1 - HT: u12, - padding: u4, + /// SRAM/NOR-Flash chip-select timing register 1-4 + BTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + /// Clock divide ratio (for FMC_CLK signal) + CLKDIV: u4, + /// Data latency for synchronous memory + DATLAT: u4, + /// Access mode + ACCMOD: packed union { + raw: u2, + value: ACCMOD, + }, + padding: u2, }), - reserved48: [4]u8, - /// regular sequence register 1 - SQR1: mmio.Mmio(packed struct(u32) { - /// Regular channel sequence length - L: u4, - reserved6: u2, - /// SQ1 - SQ: u5, - padding: u21, + /// SRAM/NOR-Flash chip-select control register 2-4 + BCR: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { + raw: u2, + value: MTYP, + }, + /// Memory data bus width + MWID: packed union { + raw: u2, + value: MWID, + }, + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { + raw: u1, + value: WAITPOL, + }, + reserved11: u1, + /// Wait timing configuration + WAITCFG: packed union { + raw: u1, + value: WAITCFG, + }, + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + /// CRAM page size + CPSIZE: packed union { + raw: u3, + value: CPSIZE, + }, + /// Write burst enable + CBURSTRW: u1, + padding: u12, }), - /// regular sequence register 2 - SQR2: mmio.Mmio(packed struct(u32) { - /// SQ5 - SQ: u5, - padding: u27, + reserved128: [116]u8, + /// PC Card/NAND Flash control register + PCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Wait feature enable bit + PWAITEN: u1, + /// NAND Flash memory bank enable bit + PBKEN: u1, + /// Memory type + PTYP: packed union { + raw: u1, + value: PTYP, + }, + /// Data bus width + PWID: packed union { + raw: u2, + value: PWID, + }, + /// ECC computation logic enable bit + ECCEN: u1, + reserved9: u2, + /// CLE to RE delay + TCLR: u4, + /// ALE to RE delay + TAR: u4, + /// ECC page size + ECCPS: packed union { + raw: u3, + value: ECCPS, + }, + padding: u12, }), - /// regular sequence register 3 - SQR3: mmio.Mmio(packed struct(u32) { - /// SQ10 - SQ: u5, - padding: u27, + /// FIFO status and interrupt register + SR: mmio.Mmio(packed struct(u32) { + /// Interrupt rising edge status + IRS: u1, + /// Interrupt high-level status + ILS: u1, + /// Interrupt falling edge status + IFS: u1, + /// Interrupt rising edge detection enable bit + IREN: u1, + /// Interrupt high-level detection enable bit + ILEN: u1, + /// Interrupt falling edge detection enable bit + IFEN: u1, + /// FIFO empty status + FEMPT: u1, + padding: u25, }), - /// regular sequence register 4 - SQR4: mmio.Mmio(packed struct(u32) { - /// SQ15 - SQ: u5, - padding: u27, + /// Common memory space timing register + PMEM: mmio.Mmio(packed struct(u32) { + /// Common memory x setup time + MEMSET: u8, + /// Common memory wait time + MEMWAIT: u8, + /// Common memory hold time + MEMHOLD: u8, + /// Common memory x data bus Hi-Z time + MEMHIZ: u8, }), - /// regular Data Register - DR: mmio.Mmio(packed struct(u32) { - /// regularDATA - regularDATA: u16, - padding: u16, + /// Attribute memory space timing register + PATT: mmio.Mmio(packed struct(u32) { + /// Attribute memory setup time + ATTSET: u8, + /// Attribute memory wait time + ATTWAIT: u8, + /// Attribute memory hold time + ATTHOLD: u8, + /// Attribute memory data bus Hi-Z time + ATTHIZ: u8, }), - reserved76: [8]u8, - /// injected sequence register - JSQR: mmio.Mmio(packed struct(u32) { - /// JL - JL: u2, - /// JEXTSEL - JEXTSEL: u4, - /// JEXTEN - JEXTEN: u2, - /// JSQ1 - JSQ: u5, - padding: u19, + reserved148: [4]u8, + /// ECC result register + ECCR: mmio.Mmio(packed struct(u32) { + /// ECC computation result value + ECC: u32, }), - reserved96: [16]u8, - /// offset register 1 - OFR: [4]mmio.Mmio(packed struct(u32) { - OFFSET: u12, - reserved26: u14, - OFFSET_CH: u5, - OFFSET_EN: u1, + reserved260: [108]u8, + /// SRAM/NOR-Flash write timing registers 1-4 + BWTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + reserved28: u8, + /// Access mode + ACCMOD: packed union { + raw: u2, + value: ACCMOD, + }, + padding: u2, }), - reserved128: [16]u8, - /// injected data registers - JDR: [4]mmio.Mmio(packed struct(u32) { - /// JDATA1 - JDATA: u16, - padding: u16, + reserved320: [56]u8, + /// SDRAM Control Register 1-2 + SDCR: [2]mmio.Mmio(packed struct(u32) { + /// Number of column address bits + NC: packed union { + raw: u2, + value: NC, + }, + /// Number of row address bits + NR: packed union { + raw: u2, + value: NR, + }, + /// Memory data bus width + MWID: packed union { + raw: u2, + value: MWID, + }, + /// Number of internal banks + NB: packed union { + raw: u1, + value: NB, + }, + /// CAS latency + CAS: packed union { + raw: u2, + value: CAS, + }, + /// Write protection + WP: u1, + /// SDRAM clock configuration + SDCLK: packed union { + raw: u2, + value: SDCLK, + }, + /// Burst read + RBURST: u1, + /// Read pipe + RPIPE: packed union { + raw: u2, + value: RPIPE, + }, + padding: u17, }), - reserved160: [16]u8, - /// Analog Watchdog 2 Configuration Register - AWD2CR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// AWD2CH - AWD2CH: u18, - padding: u13, + /// SDRAM Timing register 1-2 + SDTR: [2]mmio.Mmio(packed struct(u32) { + /// Load Mode Register to Active + TMRD: u4, + /// Exit self-refresh delay + TXSR: u4, + /// Self refresh time + TRAS: u4, + /// Row cycle delay + TRC: u4, + /// Recovery delay + TWR: u4, + /// Row precharge delay + TRP: u4, + /// Row to column delay + TRCD: u4, + padding: u4, }), - /// Analog Watchdog 3 Configuration Register - AWD3CR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// AWD3CH - AWD3CH: u18, - padding: u13, + /// SDRAM Command Mode register + SDCMR: mmio.Mmio(packed struct(u32) { + /// Command mode + MODE: packed union { + raw: u3, + value: MODE, + }, + /// Command target bank 2 + CTB2: u1, + /// Command target bank 1 + CTB1: u1, + /// Number of Auto-refresh + NRFS: u4, + /// Mode Register definition + MRD: u13, + padding: u10, }), - reserved176: [8]u8, - /// Differential Mode Selection Register 2 - DIFSEL: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Differential mode for channels 15 to 1 - DIFSEL_1_15: u15, - /// Differential mode for channels 18 to 16 - DIFSEL_16_18: u3, - padding: u13, + /// SDRAM Refresh Timer register + SDRTR: mmio.Mmio(packed struct(u32) { + /// Clear Refresh error flag + CRE: u1, + /// Refresh Timer Count + COUNT: u13, + /// RES Interrupt Enable + REIE: u1, + padding: u17, }), - /// Calibration Factors - CALFACT: mmio.Mmio(packed struct(u32) { - /// CALFACT_S - CALFACT_S: u7, - reserved16: u9, - /// CALFACT_D - CALFACT_D: u7, - padding: u9, + /// SDRAM Status register + SDSR: mmio.Mmio(packed struct(u32) { + /// Refresh error flag + RE: u1, + /// Status Mode for Bank 1 + MODES1: packed union { + raw: u2, + value: MODES, + }, + /// Status Mode for Bank 2 + MODES2: packed union { + raw: u2, + value: MODES, + }, + /// Busy status + BUSY: u1, + padding: u26, }), }; }; - pub const lptim_v2a = struct { - pub const CCP_Input = enum(u2) { - Rising = 0x0, - Falling = 0x1, - Both = 0x3, + pub const fmc_v3x1 = struct { + pub const ACCMOD = enum(u2) { + /// Access mode A + A = 0x0, + /// Access mode B + B = 0x1, + /// Access mode C + C = 0x2, + /// Access mode D + D = 0x3, + }; + + pub const CAS = enum(u2) { + /// 1 cycle + Clocks1 = 0x1, + /// 2 cycles + Clocks2 = 0x2, + /// 3 cycles + Clocks3 = 0x3, _, }; - pub const CCP_Output = enum(u2) { - ActiveHigh = 0x0, - ActiveLow = 0x1, + pub const CPSIZE = enum(u3) { + /// No burst split when crossing page boundary + NoBurstSplit = 0x0, + /// 128 bytes CRAM page size + Bytes128 = 0x1, + /// 256 bytes CRAM page size + Bytes256 = 0x2, + /// 512 bytes CRAM page size + Bytes512 = 0x3, + /// 1024 bytes CRAM page size + Bytes1024 = 0x4, _, }; - pub const CCSEL = enum(u1) { - /// channel is configured in output PWM mode - OutputCompare = 0x0, - /// channel is configured in input capture mode - InputCapture = 0x1, + pub const ECCPS = enum(u3) { + /// ECC page size 256 bytes + Bytes256 = 0x0, + /// ECC page size 512 bytes + Bytes512 = 0x1, + /// ECC page size 1024 bytes + Bytes1024 = 0x2, + /// ECC page size 2048 bytes + Bytes2048 = 0x3, + /// ECC page size 4096 bytes + Bytes4096 = 0x4, + /// ECC page size 8192 bytes + Bytes8192 = 0x5, + _, }; - pub const CKPOL = enum(u2) { - /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. - Rising = 0x0, - /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. - Falling = 0x1, - /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. - Both = 0x2, + pub const MODE = enum(u3) { + /// Normal Mode + Normal = 0x0, + /// Clock Configuration Enable + ClockConfigurationEnable = 0x1, + /// PALL (All Bank Precharge) command + PALL = 0x2, + /// Auto-refresh command + AutoRefreshCommand = 0x3, + /// Load Mode Resgier + LoadModeRegister = 0x4, + /// Self-refresh command + SelfRefreshCommand = 0x5, + /// Power-down command + PowerDownCommand = 0x6, _, }; - pub const ClockSource = enum(u1) { - /// clocked by internal clock source (APB clock or any of the embedded oscillators) - Internal = 0x0, - /// clocked by an external clock source through the LPTIM external Input1 - External = 0x1, + pub const MODES = enum(u2) { + /// Normal Mode + Normal = 0x0, + /// Self-refresh mode + SelfRefresh = 0x1, + /// Power-down mode + PowerDown = 0x2, + _, }; - pub const Filter = enum(u2) { - Count1 = 0x0, - Count2 = 0x1, - Count4 = 0x2, - Count8 = 0x3, + pub const MTYP = enum(u2) { + /// SRAM memory type + SRAM = 0x0, + /// PSRAM (CRAM) memory type + PSRAM = 0x1, + /// NOR Flash/OneNAND Flash + Flash = 0x2, + _, }; - pub const PRESC = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div4 = 0x2, - Div8 = 0x3, - Div16 = 0x4, - Div32 = 0x5, - Div64 = 0x6, - Div128 = 0x7, + pub const MWID = enum(u2) { + /// Memory data bus width 8 bits + Bits8 = 0x0, + /// Memory data bus width 16 bits + Bits16 = 0x1, + /// Memory data bus width 32 bits + Bits32 = 0x2, + _, }; - pub const TRIGEN = enum(u2) { - /// software trigger (counting start is initiated by software) - Software = 0x0, - /// rising edge is the active edge - RisingEdge = 0x1, - /// falling edge is the active edge - FallingEdge = 0x2, - /// both edges are active edges - BothEdge = 0x3, + pub const NB = enum(u1) { + /// Two internal Banks + NB2 = 0x0, + /// Four internal Banks + NB4 = 0x1, }; - pub const WAVPOL = enum(u1) { - /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. - Positive = 0x0, - /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. - Negative = 0x1, + pub const NC = enum(u2) { + /// 8 bits + Bits8 = 0x0, + /// 9 bits + Bits9 = 0x1, + /// 10 bits + Bits10 = 0x2, + /// 11 bits + Bits11 = 0x3, }; - /// Low power timer with Output Compare - pub const LPTIM = extern struct { - /// LPTIM interrupt and status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, - reserved3: u2, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, - reserved12: u8, - /// Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCOF: u1, - padding: u19, - }), - /// LPTIM interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, - reserved3: u2, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, - reserved12: u8, - /// Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCOCF: u1, - padding: u19, - }), - /// LPTIM interrupt enable register. - DIER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, - reserved3: u2, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, - reserved12: u8, - /// Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCOIE: u1, - reserved16: u3, - /// Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCDE: u1, - padding: u15, - }), - reserved20: [8]u8, - /// LPTIM compare register 1. - CCR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. - CCR: u16, - padding: u16, - }), - reserved44: [20]u8, - /// LPTIM capture/compare mode register 1. - CCMR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. - CCSEL: packed union { - raw: u1, - value: CCSEL, - }, - /// Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. - CCE: u1, - /// Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. - CCP_Input: packed union { + pub const NR = enum(u2) { + /// 11 bits + Bits11 = 0x0, + /// 12 bits + Bits12 = 0x1, + /// 13 bits + Bits13 = 0x2, + _, + }; + + pub const PWID = enum(u2) { + /// External memory device width 8 bits + Bits8 = 0x0, + /// External memory device width 16 bits + Bits16 = 0x1, + _, + }; + + pub const RPIPE = enum(u2) { + /// No clock cycle delay + NoDelay = 0x0, + /// One clock cycle delay + Clocks1 = 0x1, + /// Two clock cycles delay + Clocks2 = 0x2, + _, + }; + + pub const SDCLK = enum(u2) { + /// SDCLK clock disabled + Disabled = 0x0, + /// SDCLK period = 2 x HCLK period + Div2 = 0x2, + /// SDCLK period = 3 x HCLK period + Div3 = 0x3, + _, + }; + + pub const WAITCFG = enum(u1) { + /// NWAIT signal is active one data cycle before wait state + BeforeWaitState = 0x0, + /// NWAIT signal is active during wait state + DuringWaitState = 0x1, + }; + + pub const WAITPOL = enum(u1) { + /// NWAIT active low + ActiveLow = 0x0, + /// NWAIT active high + ActiveHigh = 0x1, + }; + + /// Flexible memory controller + pub const FMC = extern struct { + /// SRAM/NOR-Flash chip-select control register 1 + BCR1: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { raw: u2, - value: CCP_Input, + value: MTYP, }, - reserved8: u4, - /// Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). - ICPSC: packed union { + /// Memory data bus width + MWID: packed union { raw: u2, - value: Filter, + value: MWID, }, - reserved12: u2, - /// Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - ICF: packed union { - raw: u2, - value: Filter, + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { + raw: u1, + value: WAITPOL, }, - padding: u18, - }), - }; - - /// Low power timer with Output Compare - pub const LPTIM_BASIC = extern struct { - /// LPTIM interrupt and status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, - /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. - ARRM: u1, - /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. - EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, - /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. - ARROK: u1, - /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UP: u1, - /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWN: u1, - /// LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. - UE: u1, - /// Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. - REPOK: u1, - reserved24: u15, - /// Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. - DIEROK: u1, - padding: u7, - }), - /// LPTIM interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, - /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. - ARRMCF: u1, - /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. - EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, - /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. - ARROKCF: u1, - /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPCF: u1, - /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNCF: u1, - /// Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. - UECF: u1, - /// Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. - REPOKCF: u1, - reserved24: u15, - /// Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. - DIEROKCF: u1, - padding: u7, - }), - /// LPTIM interrupt enable register. - DIER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, - /// Autoreload match Interrupt Enable. - ARRMIE: u1, - /// External trigger valid edge Interrupt Enable. - EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, - /// Autoreload register update OK Interrupt Enable. - ARROKIE: u1, - /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPIE: u1, - /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNIE: u1, - /// Update event interrupt enable. - UEIE: u1, - /// Repetition register update OK interrupt Enable. - REPOKIE: u1, - padding: u23, - }), - /// LPTIM configuration register. - CFGR: mmio.Mmio(packed struct(u32) { - /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. - CKSEL: packed union { + reserved11: u1, + /// Wait timing configuration + WAITCFG: packed union { raw: u1, - value: ClockSource, + value: WAITCFG, }, - /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. - CKPOL: packed union { - raw: u2, - value: CKPOL, + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + /// CRAM page size + CPSIZE: packed union { + raw: u3, + value: CPSIZE, }, - /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - CKFLT: packed union { + /// Write burst enable + CBURSTRW: u1, + /// Continuous clock enable + CCLKEN: u1, + /// Write FIFO disable + WFDIS: u1, + reserved24: u2, + /// FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register. + BMAP: u2, + reserved31: u5, + /// FMC controller enable + FMCEN: u1, + }), + /// SRAM/NOR-Flash chip-select timing register 1-4 + BTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + /// Clock divide ratio (for FMC_CLK signal) + CLKDIV: u4, + /// Data latency for synchronous memory + DATLAT: u4, + /// Access mode + ACCMOD: packed union { raw: u2, - value: Filter, + value: ACCMOD, }, - reserved6: u1, - /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. - TRGFLT: packed union { + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 2-4 + BCR: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { raw: u2, - value: Filter, - }, - reserved9: u1, - /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. - PRESC: packed union { - raw: u3, - value: PRESC, + value: MTYP, }, - reserved13: u1, - /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. - TRIGSEL: u3, - reserved17: u1, - /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. - TRIGEN: packed union { + /// Memory data bus width + MWID: packed union { raw: u2, - value: TRIGEN, + value: MWID, }, - /// Timeout enable The TIMOUT bit controls the Timeout feature. - TIMOUT: u1, - /// Waveform shape The WAVE bit controls the output shape. - WAVE: u1, - /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. - WAVPOL: packed union { + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { raw: u1, - value: WAVPOL, + value: WAITPOL, }, - /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. - PRELOAD: u1, - /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. - COUNTMODE: packed union { + reserved11: u1, + /// Wait timing configuration + WAITCFG: packed union { raw: u1, - value: ClockSource, + value: WAITCFG, }, - /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - ENC: u1, - padding: u7, - }), - /// LPTIM control register. - CR: mmio.Mmio(packed struct(u32) { - /// LPTIM enable The ENABLE bit is set and cleared by software. - ENABLE: u1, - /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. - SNGSTRT: u1, - /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. - CNTSTRT: u1, - /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. - COUNTRST: u1, - /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. - RSTARE: u1, - padding: u27, + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + /// CRAM page size + CPSIZE: packed union { + raw: u3, + value: CPSIZE, + }, + /// Write burst enable + CBURSTRW: u1, + padding: u12, }), - /// LPTIM compare register 1. - CCR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. - CCR: u16, - padding: u16, + reserved128: [116]u8, + /// PC Card/NAND Flash control register + PCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Wait feature enable bit + PWAITEN: u1, + /// NAND Flash memory bank enable bit + PBKEN: u1, + reserved4: u1, + /// Data bus width + PWID: packed union { + raw: u2, + value: PWID, + }, + /// ECC computation logic enable bit + ECCEN: u1, + reserved9: u2, + /// CLE to RE delay + TCLR: u4, + /// ALE to RE delay + TAR: u4, + /// ECC page size + ECCPS: packed union { + raw: u3, + value: ECCPS, + }, + padding: u12, }), - /// LPTIM autoreload register. - ARR: mmio.Mmio(packed struct(u32) { - /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. - ARR: u16, - padding: u16, + /// FIFO status and interrupt register + SR: mmio.Mmio(packed struct(u32) { + /// Interrupt rising edge status + IRS: u1, + /// Interrupt high-level status + ILS: u1, + /// Interrupt falling edge status + IFS: u1, + /// Interrupt rising edge detection enable bit + IREN: u1, + /// Interrupt high-level detection enable bit + ILEN: u1, + /// Interrupt falling edge detection enable bit + IFEN: u1, + /// FIFO empty status + FEMPT: u1, + padding: u25, }), - /// LPTIM counter register. - CNT: mmio.Mmio(packed struct(u32) { - /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. - CNT: u16, - padding: u16, - }), - reserved36: [4]u8, - /// LPTIM configuration register 2. - CFGR2: mmio.Mmio(packed struct(u32) { - /// LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. - INSEL: u2, - reserved16: u14, - /// LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. - ICSEL: u2, - padding: u14, - }), - /// LPTIM repetition register. - RCR: mmio.Mmio(packed struct(u32) { - /// Repetition register value REP is the repetition value for the LPTIM. - REP: u8, - padding: u24, + /// Common memory space timing register + PMEM: mmio.Mmio(packed struct(u32) { + /// Common memory x setup time + MEMSET: u8, + /// Common memory wait time + MEMWAIT: u8, + /// Common memory hold time + MEMHOLD: u8, + /// Common memory x data bus Hi-Z time + MEMHIZ: u8, }), - }; - }; - - pub const hsem_v3 = struct { - /// Hardware semaphore. - pub const HSEM = extern struct { - /// HSEM register HSEM_R%s HSEM_R31. - R: [16]mmio.Mmio(packed struct(u32) { - /// Semaphore ProcessID. - PROCID: u8, - /// COREID. - COREID: u4, - reserved31: u19, - /// Lock indication. - LOCK: u1, + /// Attribute memory space timing register + PATT: mmio.Mmio(packed struct(u32) { + /// Attribute memory setup time + ATTSET: u8, + /// Attribute memory wait time + ATTWAIT: u8, + /// Attribute memory hold time + ATTHOLD: u8, + /// Attribute memory data bus Hi-Z time + ATTHIZ: u8, }), - reserved128: [64]u8, - /// HSEM Read lock register. - RLR: [16]mmio.Mmio(packed struct(u32) { - /// Semaphore ProcessID. - PROCID: u8, - /// COREID. - COREID: u4, - reserved31: u19, - /// Lock indication. - LOCK: u1, + reserved148: [4]u8, + /// ECC result register + ECCR: mmio.Mmio(packed struct(u32) { + /// ECC computation result value + ECC: u32, }), - reserved256: [64]u8, - /// HSEM Interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x enable bit. - ISE: u1, - padding: u31, + reserved260: [108]u8, + /// SRAM/NOR-Flash write timing registers 1-4 + BWTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + reserved28: u8, + /// Access mode + ACCMOD: packed union { + raw: u2, + value: ACCMOD, + }, + padding: u2, }), - /// HSEM Interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x clear bit. - ISC: u1, - padding: u31, + reserved320: [56]u8, + /// SDRAM Control Register 1-2 + SDCR: [2]mmio.Mmio(packed struct(u32) { + /// Number of column address bits + NC: packed union { + raw: u2, + value: NC, + }, + /// Number of row address bits + NR: packed union { + raw: u2, + value: NR, + }, + /// Memory data bus width + MWID: packed union { + raw: u2, + value: MWID, + }, + /// Number of internal banks + NB: packed union { + raw: u1, + value: NB, + }, + /// CAS latency + CAS: packed union { + raw: u2, + value: CAS, + }, + /// Write protection + WP: u1, + /// SDRAM clock configuration + SDCLK: packed union { + raw: u2, + value: SDCLK, + }, + /// Burst read + RBURST: u1, + /// Read pipe + RPIPE: packed union { + raw: u2, + value: RPIPE, + }, + padding: u17, }), - /// HSEM Interrupt status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x status bit before enable (mask). - ISF: u1, - padding: u31, + /// SDRAM Timing register 1-2 + SDTR: [2]mmio.Mmio(packed struct(u32) { + /// Load Mode Register to Active + TMRD: u4, + /// Exit self-refresh delay + TXSR: u4, + /// Self refresh time + TRAS: u4, + /// Row cycle delay + TRC: u4, + /// Recovery delay + TWR: u4, + /// Row precharge delay + TRP: u4, + /// Row to column delay + TRCD: u4, + padding: u4, }), - /// HSEM Masked interrupt status register. - MISR: mmio.Mmio(packed struct(u32) { - /// masked interrupt semaphore x status bit after enable (mask). - MISF: u1, - padding: u31, + /// SDRAM Command Mode register + SDCMR: mmio.Mmio(packed struct(u32) { + /// Command mode + MODE: packed union { + raw: u3, + value: MODE, + }, + /// Command target bank 2 + CTB2: u1, + /// Command target bank 1 + CTB1: u1, + /// Number of Auto-refresh + NRFS: u4, + /// Mode Register definition + MRD: u13, + padding: u10, }), - reserved320: [48]u8, - /// HSEM Clear register. - CR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// COREID. - COREID: u4, - reserved16: u4, - /// Semaphore clear Key. - KEY: u16, + /// SDRAM Refresh Timer register + SDRTR: mmio.Mmio(packed struct(u32) { + /// Clear Refresh error flag + CRE: u1, + /// Refresh Timer Count + COUNT: u13, + /// RES Interrupt Enable + REIE: u1, + padding: u17, }), - /// HSEM Interrupt clear register. - KEYR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Semaphore Clear Key. - KEY: u16, + /// SDRAM Status register + SDSR: mmio.Mmio(packed struct(u32) { + /// Refresh error flag + RE: u1, + /// Status Mode for Bank 1 + MODES1: packed union { + raw: u2, + value: MODES, + }, + /// Status Mode for Bank 2 + MODES2: packed union { + raw: u2, + value: MODES, + }, + padding: u27, }), }; }; - pub const exti_u5 = struct { - /// External interrupt/event controller - pub const EXTI = extern struct { - /// Rising Trigger selection register - RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Falling Trigger selection register - FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Software interrupt event register - SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Rising pending register - RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Falling pending register - FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Security configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x - SEC: u1, - padding: u31, - }), - /// Privilege configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x - PRIV: u1, - padding: u31, - }), - reserved96: [68]u8, - /// Configuration register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u8, - padding: u24, - }), - /// EXTI lock register - LOCKRG: mmio.Mmio(packed struct(u32) { - /// LOCK - LOCK: u1, - padding: u31, - }), - reserved128: [12]u8, - /// Interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Event mask register - EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), + pub const fmc_v4 = struct { + pub const ACCMOD = enum(u2) { + /// Access mode A + A = 0x0, + /// Access mode B + B = 0x1, + /// Access mode C + C = 0x2, + /// Access mode D + D = 0x3, }; - }; - pub const syscfg_wle = struct { - /// System configuration controller - pub const SYSCFG = extern struct { - /// memory remap register - MEMRMP: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection - MEM_MODE: u3, - padding: u29, - }), - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// I/O analog switch voltage booster enable - BOOSTEN: u1, - reserved16: u7, - /// Fast-mode Plus (Fm+) driving capability activation on PB6 - I2C_PB6_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB7 - I2C_PB7_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB8 - I2C_PB8_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB9 - I2C_PB9_FMP: u1, - /// I2C1 Fast-mode Plus driving capability activation - I2C1_FMP: u1, - /// I2C2 Fast-mode Plus driving capability activation - I2C2_FMP: u1, - /// I2C3 Fast-mode Plus driving capability activation - I2C3_FMP: u1, - padding: u9, - }), - /// external interrupt configuration register 1 - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI12 configuration bits - EXTI: u3, - padding: u29, - }), - /// SCSR - SCSR: mmio.Mmio(packed struct(u32) { - /// SRAM2 erase - SRAM2ER: u1, - /// SRAM1, SRAM2 and PKA SRAM busy by erase operation - SRAMBSY: u1, - reserved8: u6, - /// PKA SRAM busy by erase operation - PKASRAMBSY: u1, - padding: u23, - }), - /// CFGR2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// CPU1 LOCKUP (Hardfault) output enable bit - CLL: u1, - /// SRAM2 parity lock bit - SPL: u1, - /// PVD lock enable bit - PVDL: u1, - /// ECC Lock - ECCL: u1, - reserved8: u4, - /// SRAM2 parity error flag - SPF: u1, - padding: u23, - }), - /// SWPR - SWPR: mmio.Mmio(packed struct(u32) { - /// SRAM2 1Kbyte page 0 write protection - PWP: u1, - padding: u31, - }), - /// SKR - SKR: mmio.Mmio(packed struct(u32) { - /// SRAM2 write protection key for software erase - KEY: u8, - padding: u24, - }), - reserved520: [480]u8, - /// radio debug control register - RFDCR: mmio.Mmio(packed struct(u32) { - /// radio debug test bus selection - RFTBSEL: u1, - padding: u31, - }), + pub const CAS = enum(u2) { + /// 1 cycle + Clocks1 = 0x1, + /// 2 cycles + Clocks2 = 0x2, + /// 3 cycles + Clocks3 = 0x3, + _, }; - }; - pub const hash_v3 = struct { - /// Hash processor. - pub const HASH = extern struct { - /// control register. - CR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Initialize message digest calculation. - INIT: u1, - /// DMA enable. - DMAE: u1, - /// Data type selection. - DATATYPE: u2, - /// Mode selection. - MODE: u1, - reserved8: u1, - /// Number of words already pushed. - NBW: u4, - /// DIN not empty. - DINNE: u1, - /// Multiple DMA Transfers. - MDMAT: u1, - reserved16: u2, - /// Long key selection. - LKEY: u1, - /// Algorithm selection. - ALGO: u2, - padding: u13, - }), - /// data input register. - DIN: u32, - /// start register. - STR: mmio.Mmio(packed struct(u32) { - /// Number of valid bits in the last word of the message. - NBLW: u5, - reserved8: u3, - /// Digest calculation. - DCAL: u1, - padding: u23, - }), - /// digest registers. - HRA: [5]u32, - /// interrupt enable register. - IMR: mmio.Mmio(packed struct(u32) { - /// Data input interrupt enable. - DINIE: u1, - /// Digest calculation completion interrupt enable. - DCIE: u1, - padding: u30, - }), - /// status register. - SR: mmio.Mmio(packed struct(u32) { - /// Data input interrupt status. - DINIS: u1, - /// Digest calculation completion interrupt status. - DCIS: u1, - /// DMA Status. - DMAS: u1, - /// Busy bit. - BUSY: u1, - reserved9: u5, - /// Number of words already pushed. - NBWP: u5, - reserved15: u1, - /// DIN not empty. - DINNE: u1, - /// Number of words expected. - NBWE: u5, - padding: u11, - }), - reserved248: [208]u8, - /// context swap registers. - CSR: [103]u32, - reserved784: [124]u8, - /// HASH digest register. - HR: [16]u32, + pub const CBURSTRW = enum(u1) { + /// Write operations are always performed in Asynchronous mode. + Asynchronous = 0x0, + /// Write operations are performed in Synchronous mode. + Synchronous = 0x1, }; - }; - pub const rcc_f0v3 = struct { - pub const CECSW = enum(u1) { - /// HSI clock divided by 244 selected as CEC clock source - HSI_DIV_244 = 0x0, - /// LSE clock selected as CEC clock source - LSE = 0x1, + pub const CPSIZE = enum(u3) { + /// No burst split when crossing page boundary + NoBurstSplit = 0x0, + /// 128 bytes CRAM page size + Bytes128 = 0x1, + /// 256 bytes CRAM page size + Bytes256 = 0x2, + /// 512 bytes CRAM page size + Bytes512 = 0x3, + /// 1024 bytes CRAM page size + Bytes1024 = 0x4, + _, }; - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, + pub const ECCPS = enum(u3) { + /// ECC page size 256 bytes + Bytes256 = 0x0, + /// ECC page size 512 bytes + Bytes512 = 0x1, + /// ECC page size 1024 bytes + Bytes1024 = 0x2, + /// ECC page size 2048 bytes + Bytes2048 = 0x3, + /// ECC page size 4096 bytes + Bytes4096 = 0x4, + /// ECC page size 8192 bytes + Bytes8192 = 0x5, _, }; - pub const ICSW = enum(u1) { - /// HSI clock selected as I2C clock source - HSI = 0x0, - /// SYSCLK clock selected as I2C clock source - SYS = 0x1, + pub const MODE = enum(u3) { + /// Normal Mode + Normal = 0x0, + /// Clock Configuration Enable + ClockConfigurationEnable = 0x1, + /// PALL (All Bank Precharge) command + PALL = 0x2, + /// Auto-refresh command + AutoRefreshCommand = 0x3, + /// Load Mode Resgier + LoadModeRegister = 0x4, + /// Self-refresh command + SelfRefreshCommand = 0x5, + /// Power-down command + PowerDownCommand = 0x6, + _, }; - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium high driving capability - MediumHigh = 0x1, - /// Medium low driving capability - MediumLow = 0x2, - /// High driving capability - High = 0x3, + pub const MODES = enum(u2) { + /// Normal Mode + Normal = 0x0, + /// Self-refresh mode + SelfRefresh = 0x1, + /// Power-down mode + PowerDown = 0x2, + _, }; - pub const MCOPRE = enum(u3) { - /// MCO is divided by 1 - Div1 = 0x0, - /// MCO is divided by 2 - Div2 = 0x1, - /// MCO is divided by 4 - Div4 = 0x2, - /// MCO is divided by 8 - Div8 = 0x3, - /// MCO is divided by 16 - Div16 = 0x4, - /// MCO is divided by 32 - Div32 = 0x5, - /// MCO is divided by 64 - Div64 = 0x6, - /// MCO is divided by 128 - Div128 = 0x7, + pub const MTYP = enum(u2) { + /// SRAM memory type + SRAM = 0x0, + /// PSRAM (CRAM) memory type + PSRAM = 0x1, + /// NOR Flash/OneNAND Flash + Flash = 0x2, + _, }; - pub const MCOSEL = enum(u4) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// Internal RC 14 MHz (HSI14) oscillator clock selected - HSI14 = 0x1, - /// Internal low speed (LSI) oscillator clock selected - LSI = 0x2, - /// External low speed (LSE) oscillator clock selected - LSE = 0x3, - /// System clock selected - SYS = 0x4, - /// Internal RC 8 MHz (HSI) oscillator clock selected - HSI = 0x5, - /// External 4-32 MHz (HSE) oscillator clock selected - HSE = 0x6, - /// PLL clock selected (divided by 1 or 2, depending en PLLMCODIV) - PLL = 0x7, + pub const MWID = enum(u2) { + /// Memory data bus width 8 bits + Bits8 = 0x0, + /// Memory data bus width 16 bits + Bits16 = 0x1, + /// Memory data bus width 32 bits + Bits32 = 0x2, _, }; - pub const PLLMCODIV = enum(u1) { - /// PLL is divided by 2 for MCO - Div2 = 0x0, - /// PLL is not divided for MCO - Div1 = 0x1, + pub const NB = enum(u1) { + /// Two internal Banks + NB2 = 0x0, + /// Four internal Banks + NB4 = 0x1, }; - pub const PLLMUL = enum(u4) { - /// PLL input clock x2 - Mul2 = 0x0, - /// PLL input clock x3 - Mul3 = 0x1, - /// PLL input clock x4 - Mul4 = 0x2, - /// PLL input clock x5 - Mul5 = 0x3, - /// PLL input clock x6 - Mul6 = 0x4, - /// PLL input clock x7 - Mul7 = 0x5, - /// PLL input clock x8 - Mul8 = 0x6, - /// PLL input clock x9 - Mul9 = 0x7, - /// PLL input clock x10 - Mul10 = 0x8, - /// PLL input clock x11 - Mul11 = 0x9, - /// PLL input clock x12 - Mul12 = 0xa, - /// PLL input clock x13 - Mul13 = 0xb, - /// PLL input clock x14 - Mul14 = 0xc, - /// PLL input clock x15 - Mul15 = 0xd, - /// PLL input clock x16 - Mul16 = 0xe, - _, + pub const NC = enum(u2) { + /// 8 bits + Bits8 = 0x0, + /// 9 bits + Bits9 = 0x1, + /// 10 bits + Bits10 = 0x2, + /// 11 bits + Bits11 = 0x3, }; - pub const PLLSRC = enum(u2) { - /// HSI divided by 2 selected as PLL input clock - HSI_Div2 = 0x0, - /// HSI divided by PREDIV selected as PLL input clock - HSI_Div_PREDIV = 0x1, - /// HSE divided by PREDIV selected as PLL input clock - HSE_Div_PREDIV = 0x2, + pub const NR = enum(u2) { + /// 11 bits + Bits11 = 0x0, + /// 12 bits + Bits12 = 0x1, + /// 13 bits + Bits13 = 0x2, _, }; - pub const PLLXTPRE = enum(u1) { - /// HSE clock not divided - Div1 = 0x0, - /// HSE clock divided by 2 - Div2 = 0x1, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, + pub const PTYP = enum(u1) { + /// NAND flash + NAND = 0x1, _, }; - pub const PREDIV = enum(u4) { - /// PREDIV input clock not divided - Div1 = 0x0, - /// PREDIV input clock divided by 2 - Div2 = 0x1, - /// PREDIV input clock divided by 3 - Div3 = 0x2, - /// PREDIV input clock divided by 4 - Div4 = 0x3, - /// PREDIV input clock divided by 5 - Div5 = 0x4, - /// PREDIV input clock divided by 6 - Div6 = 0x5, - /// PREDIV input clock divided by 7 - Div7 = 0x6, - /// PREDIV input clock divided by 8 - Div8 = 0x7, - /// PREDIV input clock divided by 9 - Div9 = 0x8, - /// PREDIV input clock divided by 10 - Div10 = 0x9, - /// PREDIV input clock divided by 11 - Div11 = 0xa, - /// PREDIV input clock divided by 12 - Div12 = 0xb, - /// PREDIV input clock divided by 13 - Div13 = 0xc, - /// PREDIV input clock divided by 14 - Div14 = 0xd, - /// PREDIV input clock divided by 15 - Div15 = 0xe, - /// PREDIV input clock divided by 16 - Div16 = 0xf, + pub const PWID = enum(u2) { + /// External memory device width 8 bits + Bits8 = 0x0, + /// External memory device width 16 bits + Bits16 = 0x1, + _, }; - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, + pub const RPIPE = enum(u2) { + /// No clock cycle delay + NoDelay = 0x0, + /// One clock cycle delay + Clocks1 = 0x1, + /// Two clock cycles delay + Clocks2 = 0x2, + _, }; - pub const SW = enum(u2) { - /// HSI oscillator used as system clock - HSI = 0x0, - /// HSE oscillator used as system clock - HSE = 0x1, - /// PLL used as system clock - PLL1_P = 0x2, + pub const SDCLK = enum(u2) { + /// SDCLK clock disabled + Disabled = 0x0, + /// SDCLK period = 2 x HCLK period + Div2 = 0x2, + /// SDCLK period = 3 x HCLK period + Div3 = 0x3, _, }; - pub const USART1SW = enum(u2) { - /// PCLK selected as USART clock source - PCLK2 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, + pub const WAITCFG = enum(u1) { + /// NWAIT signal is active one data cycle before wait state + BeforeWaitState = 0x0, + /// NWAIT signal is active during wait state + DuringWaitState = 0x1, }; - pub const USARTSW = enum(u2) { - /// PCLK selected as USART clock source - PCLK1 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, + pub const WAITPOL = enum(u1) { + /// NWAIT active low + ActiveLow = 0x0, + /// NWAIT active high + ActiveHigh = 0x1, }; - pub const USBSW = enum(u1) { - /// PLL clock selected as USB clock source - PLL1_P = 0x1, - _, + /// Flexible memory controller. + pub const FMC = extern struct { + NOR_PSRAM: u32, + reserved128: [124]u8, + NAND: u32, + reserved320: [188]u8, + SDRAM: u32, }; - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal High Speed clock enable - HSION: u1, - /// Internal High Speed clock ready flag - HSIRDY: u1, - reserved3: u1, - /// Internal High Speed clock trimming - HSITRIM: u5, - /// Internal High Speed clock Calibration - HSICAL: u8, - /// External High Speed clock enable - HSEON: u1, - /// External High Speed clock ready flag - HSERDY: u1, - /// External High Speed clock Bypass - HSEBYP: u1, - /// Clock Security System enable - CSSON: u1, - reserved24: u4, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding: u6, - }), - /// Clock configuration register (RCC_CFGR) - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock Switch - SW: packed union { - raw: u2, - value: SW, + pub const NAND = extern struct { + /// NAND Flash control registers. + PCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Wait feature enable bit Enables the Wait feature for the NAND Flash memory bank:. + PWAITEN: u1, + /// NAND Flash memory bank enable bit Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. + PBKEN: u1, + /// Memory type Defines the type of device attached to the corresponding memory bank:. + PTYP: packed union { + raw: u1, + value: PTYP, }, - /// System Clock Switch Status - SWS: packed union { + /// Data bus width Defines the external memory device width. + PWID: packed union { raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, + value: PWID, }, - /// APB Low speed prescaler (APB1) - PPRE: packed union { + /// ECC computation logic enable bit. + ECCEN: u1, + reserved9: u2, + /// CLE to RE delay Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). Time is t_clr = (TCLR + SET + 2) � THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space. + TCLR: u4, + /// ALE to RE delay Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). Time is: t_ar = (TAR + SET + 2) � THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space. + TAR: u4, + /// ECC page size Defines the page size for the extended ECC:. + ECCPS: packed union { raw: u3, - value: PPRE, + value: ECCPS, }, - reserved14: u3, - /// APCPRE is deprecated. See ADC field in CFGR2 register. - ADCPRE: u1, - /// PLL input clock source - PLLSRC: packed union { + padding: u12, + }), + /// FIFO status and interrupt register. + SR: mmio.Mmio(packed struct(u32) { + /// Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it is set. + IRS: u1, + /// Interrupt high-level status The flag is set by hardware and reset by software. + ILS: u1, + /// Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it is set. + IFS: u1, + /// Interrupt rising edge detection enable bit. + IREN: u1, + /// Interrupt high-level detection enable bit. + ILEN: u1, + /// Interrupt falling edge detection enable bit. + IFEN: u1, + /// FIFO empty Read-only bit that provides the status of the FIFO. + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register. + PMEM: mmio.Mmio(packed struct(u32) { + /// Common memory x setup time Defines the number of HCLK (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space on socket x:. + MEMSET: u8, + /// Common memory wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space on socket. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:. + MEMWAIT: u8, + /// Common memory hold time Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write accesses) after the command is deasserted (NWE, NOE), for NAND Flash read or write access to common memory space on socket x:. + MEMHOLD: u8, + /// Common memory x data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space on socket. This is only valid for write transactions:. + MEMHIZ: u8, + }), + /// Attribute memory space timing register. + PATT: mmio.Mmio(packed struct(u32) { + /// Attribute memory setup time Defines the number of HCLK (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket:. + ATTSET: u8, + /// Attribute memory wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:. + ATTWAIT: u8, + /// Attribute memory hold time Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write access) after the command deassertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket:. + ATTHOLD: u8, + /// Attribute memory data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:. + ATTHIZ: u8, + }), + reserved20: [4]u8, + /// ECC result registers. + ECCR: u32, + }; + + pub const NOR_PSRAM = extern struct { + /// SRAM/NOR-Flash chip-select control register for bank 1. + BCR1: mmio.Mmio(packed struct(u32) { + reserved20: u20, + /// Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.). + CCLKEN: u1, + /// Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. + WFDIS: u1, + padding: u10, + }), + /// SRAM/NOR-Flash chip-select timing register for bank 1. + BTR: mmio.Mmio(packed struct(u32) { + reserved20: u20, + /// Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula). + CLKDIV: u4, + /// (see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don't care. + DATLAT: u4, + padding: u4, + }), + /// SRAM/NOR-Flash chip-select control register for bank 2. + BCR: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. + MBKEN: u1, + /// Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:. + MUXEN: u1, + /// Memory type Defines the type of external memory attached to the corresponding memory bank. + MTYP: packed union { raw: u2, - value: PLLSRC, + value: MTYP, }, - /// HSE divider for PLL entry. Same bit as PREDIV[0] from CFGR2 register. Refer to it for its meaning - PLLXTPRE: packed union { - raw: u1, - value: PLLXTPRE, + /// Memory data bus width Defines the external memory device width, valid for all type of memories. + MWID: packed union { + raw: u2, + value: MWID, }, - /// PLL Multiplication Factor - PLLMUL: packed union { - raw: u4, - value: PLLMUL, + /// Flash access enable Enables NOR Flash memory access operations. + FACCEN: u1, + reserved8: u1, + /// Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode. + BURSTEN: u1, + /// Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. + WAITPOL: packed union { + raw: u1, + value: WAITPOL, }, - reserved24: u2, - /// Microcontroller clock output - MCOSEL: packed union { - raw: u4, - value: MCOSEL, + reserved11: u1, + /// Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. + WAITCFG: packed union { + raw: u1, + value: WAITCFG, }, - /// Microcontroller Clock Output Prescaler - MCOPRE: packed union { + /// Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. + WREN: u1, + /// Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. + WAITEN: u1, + /// Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). + EXTMOD: u1, + /// Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. + ASYNCWAIT: u1, + /// CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved. + CPSIZE: packed union { raw: u3, - value: MCOPRE, + value: CPSIZE, }, - /// PLL clock not divided for MCO - PLLMCODIV: packed union { + /// Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. + CBURSTRW: packed union { raw: u1, - value: PLLMCODIV, + value: CBURSTRW, }, + /// Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.). + CCLKEN: u1, + /// Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. + WFDIS: u1, + /// Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low. + NBLSET: u2, + reserved31: u7, + /// FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. + FMCEN: u1, }), - /// Clock interrupt register (RCC_CIR) - CIR: mmio.Mmio(packed struct(u32) { - /// LSI Ready Interrupt flag - LSIRDYF: u1, - /// LSE Ready Interrupt flag - LSERDYF: u1, - /// HSI Ready Interrupt flag - HSIRDYF: u1, - /// HSE Ready Interrupt flag - HSERDYF: u1, - /// PLL Ready Interrupt flag - PLLRDYF: u1, - /// HSI14 ready interrupt flag - HSI14RDYF: u1, - reserved7: u1, - /// Clock Security System Interrupt flag - CSSF: u1, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1, - /// LSE Ready Interrupt Enable - LSERDYIE: u1, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1, - /// HSE Ready Interrupt Enable - HSERDYIE: u1, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1, - /// HSI14 ready interrupt enable - HSI14RDYIE: u1, - reserved16: u2, - /// LSI Ready Interrupt Clear - LSIRDYC: u1, - /// LSE Ready Interrupt Clear - LSERDYC: u1, - /// HSI Ready Interrupt Clear - HSIRDYC: u1, - /// HSE Ready Interrupt Clear - HSERDYC: u1, - /// PLL Ready Interrupt Clear - PLLRDYC: u1, - /// HSI 14 MHz Ready Interrupt Clear - HSI14RDYC: u1, - reserved23: u1, - /// Clock security system interrupt clear - CSSC: u1, - padding: u8, - }), - /// APB2 peripheral reset register (RCC_APB2RSTR) - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// SYSCFG and COMP reset - SYSCFGRST: u1, - reserved5: u4, - /// USART6 reset - USART6RST: u1, - /// USART7 reset - USART7RST: u1, - /// USART8 reset - USART8RST: u1, - reserved9: u1, - /// ADC interface reset - ADCRST: u1, - reserved11: u1, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI 1 reset - SPI1RST: u1, - reserved14: u1, - /// USART1 reset - USART1RST: u1, - reserved16: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - reserved22: u3, - /// Debug MCU reset - DBGMCURST: u1, - padding: u9, - }), - /// APB1 peripheral reset register (RCC_APB1RSTR) - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - reserved4: u2, - /// Timer 6 reset - TIM6RST: u1, - /// TIM7 timer reset - TIM7RST: u1, - reserved8: u2, - /// Timer 14 reset - TIM14RST: u1, - reserved11: u2, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI2 reset - SPI2RST: u1, - reserved17: u2, - /// USART 2 reset - USART2RST: u1, - /// USART3 reset - USART3RST: u1, - /// USART4 reset - USART4RST: u1, - /// USART5 reset - USART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// USB interface reset - USBRST: u1, - reserved25: u1, - /// CAN interface reset - CANRST: u1, - reserved27: u1, - /// Clock Recovery System interface reset - CRSRST: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - /// HDMI CEC reset - CECRST: u1, - padding: u1, - }), - /// AHB Peripheral Clock enable register (RCC_AHBENR) - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA clock enable - DMAEN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// SRAM interface clock enable - SRAMEN: u1, - reserved4: u1, - /// FLASH clock enable - FLASHEN: u1, - reserved6: u1, - /// CRC clock enable - CRCEN: u1, - reserved17: u10, - /// I/O port A clock enable - GPIOAEN: u1, - /// I/O port B clock enable - GPIOBEN: u1, - /// I/O port C clock enable - GPIOCEN: u1, - /// I/O port D clock enable - GPIODEN: u1, - /// I/O port E clock enable - GPIOEEN: u1, - /// I/O port F clock enable - GPIOFEN: u1, - reserved24: u1, - /// Touch sensing controller clock enable - TSCEN: u1, - padding: u7, - }), - /// APB2 peripheral clock enable register (RCC_APB2ENR) - APB2ENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved5: u4, - /// USART6 clock enable - USART6EN: u1, - /// USART7 clock enable - USART7EN: u1, - /// USART8 clock enable - USART8EN: u1, - reserved9: u1, - /// ADC 1 interface clock enable - ADCEN: u1, - reserved11: u1, - /// TIM1 Timer clock enable - TIM1EN: u1, - /// SPI 1 clock enable - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable - USART1EN: u1, - reserved16: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - reserved22: u3, - /// MCU debug module clock enable - DBGMCUEN: u1, - padding: u9, - }), - /// APB1 peripheral clock enable register (RCC_APB1ENR) - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer 2 clock enable - TIM2EN: u1, - /// Timer 3 clock enable - TIM3EN: u1, - reserved4: u2, - /// Timer 6 clock enable - TIM6EN: u1, - /// TIM7 timer clock enable - TIM7EN: u1, - reserved8: u2, - /// Timer 14 clock enable - TIM14EN: u1, - reserved11: u2, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI 2 clock enable - SPI2EN: u1, - reserved17: u2, - /// USART 2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// USART4 clock enable - USART4EN: u1, - /// USART5 clock enable - USART5EN: u1, - /// I2C 1 clock enable - I2C1EN: u1, - /// I2C 2 clock enable - I2C2EN: u1, - /// USB interface clock enable - USBEN: u1, - reserved25: u1, - /// CAN interface clock enable - CANEN: u1, - reserved27: u1, - /// Clock Recovery System interface clock enable - CRSEN: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - /// HDMI CEC interface clock enable - CECEN: u1, - padding: u1, + reserved32: [20]u8, + /// PSRAM chip select counter register. + PCSCNTR: mmio.Mmio(packed struct(u32) { + /// Chip select counter. These bits are written by software to define the maximum chip select low pulse duration. It is expressed in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous accesses. The counter is disabled if the programmed value is 0. + CSCOUNT: u16, + /// Counter Bank 1 enable This bit enables the chip select counter for PSRAM/NOR Bank 1. + CNTBEN: u1, + padding: u15, }), - /// Backup domain control register (RCC_BDCR) - BDCR: mmio.Mmio(packed struct(u32) { - /// External Low Speed oscillator enable - LSEON: u1, - /// External Low Speed oscillator ready - LSERDY: u1, - /// External Low Speed oscillator bypass - LSEBYP: u1, - /// LSE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - reserved8: u3, - /// RTC clock source selection - RTCSEL: packed union { + reserved260: [224]u8, + /// SRAM/NOR-Flash write timing registers 1. + BWTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. + ADDSET: u4, + /// Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. + ADDHLD: u4, + /// Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ... + DATAST: u8, + /// Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... + BUSTURN: u4, + reserved28: u8, + /// Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + ACCMOD: packed union { raw: u2, - value: RTCSEL, + value: ACCMOD, }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - padding: u15, - }), - /// Control/status register (RCC_CSR) - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low speed oscillator enable - LSION: u1, - /// Internal low speed oscillator ready - LSIRDY: u1, - reserved23: u21, - /// 1.8 V domain reset flag - V18PWRRSTF: u1, - /// Remove reset flag - RMVF: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, - }), - /// AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - reserved17: u17, - /// I/O port A reset - GPIOARST: u1, - /// I/O port B reset - GPIOBRST: u1, - /// I/O port C reset - GPIOCRST: u1, - /// I/O port D reset - GPIODRST: u1, - /// I/O port E reset - GPIOERST: u1, - /// I/O port F reset - GPIOFRST: u1, - reserved24: u1, - /// Touch sensing controller reset - TSCRST: u1, - padding: u7, + /// Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:. + DATAHLD: u2, }), - /// Clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// PREDIV division factor - PREDIV: packed union { - raw: u4, - value: PREDIV, + }; + + pub const SDRAM = extern struct { + /// SDRAM control registers 1. + SDCR: [2]mmio.Mmio(packed struct(u32) { + /// Number of column address bits These bits define the number of bits of a column address. + NC: packed union { + raw: u2, + value: NC, }, - padding: u28, - }), - /// Clock configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SW: packed union { + /// Number of row address bits These bits define the number of bits of a row address. + NR: packed union { raw: u2, - value: USART1SW, + value: NR, }, - reserved4: u2, - /// I2C1 clock source selection - I2C1SW: packed union { - raw: u1, - value: ICSW, + /// Memory data bus width. These bits define the memory device width. + MWID: packed union { + raw: u2, + value: MWID, }, - reserved6: u1, - /// HDMI CEC clock source selection - CECSW: packed union { + /// Number of internal banks This bit sets the number of internal banks. + NB: packed union { raw: u1, - value: CECSW, + value: NB, }, - /// USB clock source selection - USBSW: packed union { - raw: u1, - value: USBSW, + /// CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles. + CAS: packed union { + raw: u2, + value: CAS, }, - /// ADCSW is deprecated. See ADC field in CFGR2 register. - ADCSW: u1, - reserved16: u7, - /// USART2 clock source selection - USART2SW: packed union { + /// Write protection This bit enables write mode access to the SDRAM bank. + WP: u1, + /// SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register are don’t care. + SDCLK: packed union { raw: u2, - value: USARTSW, + value: SDCLK, }, - /// USART3 clock source - USART3SW: packed union { + /// Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is don’t care. + RBURST: u1, + /// Read pipe These bits define the delay, in clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only. + RPIPE: packed union { raw: u2, - value: USARTSW, + value: RPIPE, }, - padding: u12, - }), - /// Clock control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// HSI14 clock enable - HSI14ON: u1, - /// HR14 clock ready flag - HSI14RDY: u1, - /// HSI14 clock request from ADC disable - HSI14DIS: u1, - /// HSI14 clock trimming - HSI14TRIM: u5, - /// HSI14 clock calibration - HSI14CAL: u8, - padding: u16, - }), - }; - }; - - pub const dbgmcu_h7 = struct { - /// Debug support - pub const DBGMCU = extern struct { - /// Identity code - IDC: mmio.Mmio(packed struct(u32) { - /// Device ID - DEV_ID: u12, - reserved16: u4, - /// Revision ID - REV_ID: u16, - }), - /// Configuration register - CR: mmio.Mmio(packed struct(u32) { - /// Allow debug in D1 Sleep mode - DBGSLEEP_D1: u1, - /// Allow debug in D1 Stop mode - DBGSTOP_D1: u1, - /// Allow debug in D1 Standby mode - DBGSTBY_D1: u1, - reserved20: u17, - /// Trace clock enable enable - TRACECLKEN: u1, - /// D1 debug clock enable enable - D1DBGCKEN: u1, - /// D3 debug clock enable enable - D3DBGCKEN: u1, - reserved28: u5, - /// External trigger output enable - TRGOEN: u1, - padding: u3, + padding: u17, }), - reserved52: [44]u8, - /// APB3 peripheral freeze register - APB3FZR1: mmio.Mmio(packed struct(u32) { - reserved6: u6, - /// WWDG1 stop in debug mode - WWDG1: u1, - padding: u25, + /// SDRAM timing registers 1. + SDTR: [2]mmio.Mmio(packed struct(u32) { + /// Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. .... + TMRD: u4, + /// Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device. + TXSR: u4, + /// Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. .... + TRAS: u4, + /// Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are don’t care. + TRC: u4, + /// Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: Note: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Note: Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device. Note: If only one SDRAM device is used, the TWR timing must be kept at reset value (0xF) for the not used bank. + TWR: u4, + /// Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are don’t care. + TRP: u4, + /// Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. .... + TRCD: u4, + padding: u4, }), - reserved60: [4]u8, - /// APB1L peripheral freeze register - APB1LFZR1: mmio.Mmio(packed struct(u32) { - /// TIM2 stop in debug mode - TIM2: u1, - /// TIM3 stop in debug mode - TIM3: u1, - /// TIM4 stop in debug mode - TIM4: u1, - /// TIM5 stop in debug mode - TIM5: u1, - /// TIM6 stop in debug mode - TIM6: u1, - /// TIM7 stop in debug mode - TIM7: u1, - /// TIM12 stop in debug mode - TIM12: u1, - /// TIM13 stop in debug mode - TIM13: u1, - /// TIM14 stop in debug mode - TIM14: u1, - /// LPTIM1 stop in debug mode - LPTIM1: u1, - reserved21: u11, - /// I2C1 SMBUS timeout stop in debug mode - I2C1: u1, - /// I2C2 SMBUS timeout stop in debug mode - I2C2: u1, - /// I2C3 SMBUS timeout stop in debug mode - I2C3: u1, - padding: u8, + /// SDRAM Command Mode register. + SDCMR: mmio.Mmio(packed struct(u32) { + /// Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with it’s associated CTB bit set, the other CTB bit of the the unused bank must be kept to 0. + MODE: packed union { + raw: u3, + value: MODE, + }, + /// Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. + CTB: u1, + reserved5: u1, + /// Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = ‘011’. .... + NRFS: u4, + /// Mode Register definition This 13-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. + MRD: u13, + padding: u10, }), - reserved76: [12]u8, - /// APB2 peripheral freeze register - APB2FZR1: mmio.Mmio(packed struct(u32) { - /// TIM1 stop in debug mode - TIM1: u1, - /// TIM8 stop in debug mode - TIM8: u1, - reserved16: u14, - /// TIM15 stop in debug mode - TIM15: u1, - /// TIM16 stop in debug mode - TIM16: u1, - /// TIM17 stop in debug mode - TIM17: u1, - reserved29: u10, - /// HRTIM stop in debug mode - HRTIM: u1, - padding: u2, + /// SDRAM refresh timer register. + SDRTR: mmio.Mmio(packed struct(u32) { + /// Clear Refresh error flag This bit is used to clear the Refresh Error Flag (RE) in the Status Register. + CRE: u1, + /// Refresh Timer Count This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29). Refresh rate = (COUNT + 1) x SDRAM frequency clock COUNT = (SDRAM refresh period / Number of rows) - 20. + COUNT: u13, + /// RES Interrupt Enable. + REIE: u1, + padding: u17, }), - reserved84: [4]u8, - /// APB4 peripheral freeze register - APB4FZR1: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// I2C4 SMBUS timeout stop in debug mode - I2C4: u1, - reserved9: u1, - /// LPTIM2 stop in debug mode - LPTIM2: u1, - /// LPTIM3 stop in debug mode - LPTIM3: u1, - /// LPTIM4 stop in debug mode - LPTIM4: u1, - /// LPTIM5 stop in debug mode - LPTIM5: u1, - reserved16: u3, - /// RTC stop in debug mode - RTC: u1, - reserved18: u1, - /// Independent watchdog for D1 stop in debug mode - IWDG1: u1, - padding: u13, + /// SDRAM status register. + SDSR: mmio.Mmio(packed struct(u32) { + /// Refresh error flag An interrupt is generated if REIE = 1 and RE = 1. + RE: u1, + /// Status Mode for Bank 1 This bit defines the Status Mode of SDRAM Bank 1. + MODES: packed union { + raw: u2, + value: MODES, + }, + reserved5: u2, + /// Busy status This bit defines the status of the SDRAM controller after a Command Mode request 1; SDRAM Controller is not ready to accept a new request. + BUSY: u1, + padding: u26, }), }; }; - pub const fsmc_v4x1 = struct { + pub const fsmc_v1x0 = struct { pub const ACCMOD = enum(u2) { /// Access mode A A = 0x0, @@ -340777,22 +341637,6 @@ pub const types = struct { _, }; - pub const ECCPS = enum(u3) { - /// ECC page size 256 bytes - Bytes256 = 0x0, - /// ECC page size 512 bytes - Bytes512 = 0x1, - /// ECC page size 1024 bytes - Bytes1024 = 0x2, - /// ECC page size 2048 bytes - Bytes2048 = 0x3, - /// ECC page size 4096 bytes - Bytes4096 = 0x4, - /// ECC page size 8192 bytes - Bytes8192 = 0x5, - _, - }; - pub const MTYP = enum(u2) { /// SRAM memory type SRAM = 0x0, @@ -340813,20 +341657,6 @@ pub const types = struct { _, }; - pub const PTYP = enum(u1) { - /// NAND Flash - NANDFlash = 0x1, - _, - }; - - pub const PWID = enum(u2) { - /// External memory device width 8 bits - Bits8 = 0x0, - /// External memory device width 16 bits - Bits16 = 0x1, - _, - }; - pub const WAITCFG = enum(u1) { /// NWAIT signal is active one data cycle before wait state BeforeWaitState = 0x0, @@ -340843,8 +341673,8 @@ pub const types = struct { /// Flexible static memory controller pub const FSMC = extern struct { - /// SRAM/NOR-Flash chip-select control register 1 - BCR1: mmio.Mmio(packed struct(u32) { + /// SRAM/NOR-Flash chip-select control register 1-4 + BCR: mmio.Mmio(packed struct(u32) { /// Memory bank enable bit MBKEN: u1, /// Address/data multiplexing enable bit @@ -340869,7 +341699,8 @@ pub const types = struct { raw: u1, value: WAITPOL, }, - reserved11: u1, + /// WRAPMOD + WRAPMOD: u1, /// Wait timing configuration WAITCFG: packed union { raw: u1, @@ -340890,15 +341721,7 @@ pub const types = struct { }, /// Write burst enable CBURSTRW: u1, - /// Continuous clock enable - CCLKEN: u1, - /// Write FIFO disable - WFDIS: u1, - /// Byte lane (NBL) setup - NBLSET: u2, - reserved31: u7, - /// FMC controller enable - FMCEN: u1, + padding: u12, }), /// SRAM/NOR-Flash chip-select timing register 1-4 BTR: mmio.Mmio(packed struct(u32) { @@ -340919,10 +341742,123 @@ pub const types = struct { raw: u2, value: ACCMOD, }, - /// Data hold phase duration - DATAHLD: u2, + padding: u2, }), - /// SRAM/NOR-Flash chip-select control register 2-4 + reserved260: [252]u8, + /// SRAM/NOR-Flash write timing registers 1-4 + BWTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + reserved28: u8, + /// Access mode + ACCMOD: packed union { + raw: u2, + value: ACCMOD, + }, + padding: u2, + }), + }; + }; + + pub const fsmc_v1x3 = struct { + pub const ACCMOD = enum(u2) { + /// Access mode A + A = 0x0, + /// Access mode B + B = 0x1, + /// Access mode C + C = 0x2, + /// Access mode D + D = 0x3, + }; + + pub const CPSIZE = enum(u3) { + /// No burst split when crossing page boundary + NoBurstSplit = 0x0, + /// 128 bytes CRAM page size + Bytes128 = 0x1, + /// 256 bytes CRAM page size + Bytes256 = 0x2, + /// 512 bytes CRAM page size + Bytes512 = 0x3, + /// 1024 bytes CRAM page size + Bytes1024 = 0x4, + _, + }; + + pub const ECCPS = enum(u3) { + /// ECC page size 256 bytes + Bytes256 = 0x0, + /// ECC page size 512 bytes + Bytes512 = 0x1, + /// ECC page size 1024 bytes + Bytes1024 = 0x2, + /// ECC page size 2048 bytes + Bytes2048 = 0x3, + /// ECC page size 4096 bytes + Bytes4096 = 0x4, + /// ECC page size 8192 bytes + Bytes8192 = 0x5, + _, + }; + + pub const MTYP = enum(u2) { + /// SRAM memory type + SRAM = 0x0, + /// PSRAM (CRAM) memory type + PSRAM = 0x1, + /// NOR Flash/OneNAND Flash + Flash = 0x2, + _, + }; + + pub const MWID = enum(u2) { + /// Memory data bus width 8 bits + Bits8 = 0x0, + /// Memory data bus width 16 bits + Bits16 = 0x1, + /// Memory data bus width 32 bits + Bits32 = 0x2, + _, + }; + + pub const PTYP = enum(u1) { + /// NAND Flash + NANDFlash = 0x1, + _, + }; + + pub const PWID = enum(u2) { + /// External memory device width 8 bits + Bits8 = 0x0, + /// External memory device width 16 bits + Bits16 = 0x1, + _, + }; + + pub const WAITCFG = enum(u1) { + /// NWAIT signal is active one data cycle before wait state + BeforeWaitState = 0x0, + /// NWAIT signal is active during wait state + DuringWaitState = 0x1, + }; + + pub const WAITPOL = enum(u1) { + /// NWAIT active low + ActiveLow = 0x0, + /// NWAIT active high + ActiveHigh = 0x1, + }; + + /// Flexible static memory controller + pub const FSMC = extern struct { + /// SRAM/NOR-Flash chip-select control register 1-4 BCR: mmio.Mmio(packed struct(u32) { /// Memory bank enable bit MBKEN: u1, @@ -340948,7 +341884,8 @@ pub const types = struct { raw: u1, value: WAITPOL, }, - reserved11: u1, + /// WRAPMOD + WRAPMOD: u1, /// Wait timing configuration WAITCFG: packed union { raw: u1, @@ -340969,28 +341906,31 @@ pub const types = struct { }, /// Write burst enable CBURSTRW: u1, - reserved22: u2, - /// Byte lane (NBL) setup - NBLSET: u2, - padding: u8, - }), - reserved32: [20]u8, - /// PSRAM chip select counter register - PCSCNTR: mmio.Mmio(packed struct(u32) { - /// Chip select counter - CSCOUNT: u16, - /// Counter Bank 1 enable - CNTB1EN: u1, - /// Counter Bank 2 enable - CNTB2EN: u1, - /// Counter Bank 3 enable - CNTB3EN: u1, - /// Counter Bank 4 enable - CNTB4EN: u1, padding: u12, }), - reserved128: [92]u8, - /// PC Card/NAND Flash control register + /// SRAM/NOR-Flash chip-select timing register 1-4 + BTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + /// Clock divide ratio (for FMC_CLK signal) + CLKDIV: u4, + /// Data latency for synchronous memory + DATLAT: u4, + /// Access mode + ACCMOD: packed union { + raw: u2, + value: ACCMOD, + }, + padding: u2, + }), + reserved96: [88]u8, + /// PC Card/NAND Flash control register 2-4 PCR: mmio.Mmio(packed struct(u32) { reserved1: u1, /// Wait feature enable bit @@ -341021,7 +341961,7 @@ pub const types = struct { }, padding: u12, }), - /// FIFO status and interrupt register + /// FIFO status and interrupt register 2-4 SR: mmio.Mmio(packed struct(u32) { /// Interrupt rising edge status IRS: u1, @@ -341039,7 +341979,7 @@ pub const types = struct { FEMPT: u1, padding: u25, }), - /// Common memory space timing register + /// Common memory space timing register 2-4 PMEM: mmio.Mmio(packed struct(u32) { /// Common memory x setup time MEMSET: u8, @@ -341050,7 +341990,7 @@ pub const types = struct { /// Common memory x data bus Hi-Z time MEMHIZ: u8, }), - /// Attribute memory space timing register + /// Attribute memory space timing register 2-4 PATT: mmio.Mmio(packed struct(u32) { /// Attribute memory setup time ATTSET: u8, @@ -341061,13 +342001,25 @@ pub const types = struct { /// Attribute memory data bus Hi-Z time ATTHIZ: u8, }), - reserved148: [4]u8, - /// ECC result register + reserved116: [4]u8, + /// ECC result register 2-3 ECCR: mmio.Mmio(packed struct(u32) { /// ECC computation result value ECC: u32, }), - reserved260: [108]u8, + reserved176: [56]u8, + /// I/O space timing register 4 + PIO4: mmio.Mmio(packed struct(u32) { + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), + reserved260: [80]u8, /// SRAM/NOR-Flash write timing registers 1-4 BWTR: mmio.Mmio(packed struct(u32) { /// Address setup phase duration @@ -341084,6658 +342036,5613 @@ pub const types = struct { raw: u2, value: ACCMOD, }, - /// Data hold phase duration - DATAHLD: u2, + padding: u2, }), }; }; - pub const syscfg_wba = struct { - /// System configuration controller - pub const SYSCFG = extern struct { - /// secure configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// clock control, memory erase status and compensation cell registers security - SYSCFGSEC: u1, - /// Class B security - CLASSBSEC: u1, - reserved3: u1, - /// FPU security - FPUSEC: u1, - padding: u28, - }), - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// I/O analog switch voltage booster enable Access can be protected by GTZC_TZSC ADC4SEC. Note: Refer to Table�121 for setting. - BOOSTEN: u1, - /// GPIO analog switch control voltage selection Access can be protected by GTZC_TZSC ADC4SEC. Note: Refer to Table�121 for setting. - ANASWVDD: u1, - reserved16: u6, - /// Fast-mode Plus drive capability activation on PA6 This bit can be read and written only with secure access if PA6 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA6 when PA6 is not used by I2C peripheral. This can be used to dive a LED for instance. Access can be protected by GPIOA SEC6. - PA6_FMP: u1, - /// Fast-mode Plus drive capability activation on PA7 This bit can be read and written only with secure access if PA7 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA7 when PA7 is not used by I2C peripheral. This can be used to dive a LED for instance. Access can be protected by GPIOA SEC7. - PA7_FMP: u1, - /// Fast-mode Plus drive capability activation on PA15 This bit can be read and written only with secure access if PA15 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA15 when PA15 is not used by I2C peripheral. This can be used to dive a LED for instance. Access can be protected by GPIOA SEC15. - PA15_FMP: u1, - /// Fast-mode Plus drive capability activation on PB3 This bit can be read and written only with secure access if PB3 is secure in GPIOB. This bit enables the Fast-mode Plus drive mode for PB3 when PB3 is not used by I2C peripheral. This can be used to dive a LED for instance. Access can be protected by GPIOB SEC3. - PB3_FMP: u1, - padding: u12, - }), - /// FPU interrupt mask register - FPUIMR: mmio.Mmio(packed struct(u32) { - /// Floating point unit interrupts enable bits FPU_IE[5]: Inexact interrupt enable (interrupt disable at reset) FPU_IE[4]: Input abnormal interrupt enable FPU_IE[3]: Overflow interrupt enable FPU_IE[2]: Underflow interrupt enable FPU_IE[1]: Divide-by-zero interrupt enable FPU_IE[0]: Invalid operation Interrupt enable - FPU_IE: u6, - padding: u26, - }), - /// CPU non-secure lock register - CNSLCKR: mmio.Mmio(packed struct(u32) { - /// VTOR_NS register lock This bit is set by software and cleared only by a system reset. - LOCKNSVTOR: u1, - /// Non-secure MPU registers lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers. - LOCKNSMPU: u1, - padding: u30, - }), - /// CPU secure lock register - CSLOCKR: mmio.Mmio(packed struct(u32) { - /// VTOR_S register and AIRCR register bits lock This bit is set by software and cleared only by a system reset. When set, it disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register. - LOCKSVTAIRCR: u1, - /// Secure MPU registers lock This bit is set by software and cleared only by a system reset. When set, it disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers. - LOCKSMPU: u1, - /// SAU registers lock This bit is set by software and cleared only by a system reset. When set, it disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers. - LOCKSAU: u1, - padding: u29, - }), - /// configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// Cortex-M33 LOCKUP (hardfault) output enable This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex-M33 LOCKUP (hardfault) output to TIM1/16/17 break input. - CLL: u1, - /// SRAM2 parity lock bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs. - SPL: u1, - /// PVD lock enable bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PVDLS[2:0] in the PWR register. - PVDL: u1, - /// ECC lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC double error signal connection to TIM1/16/17 break input. - ECCL: u1, - padding: u28, - }), - /// memory erase status register - MESR: mmio.Mmio(packed struct(u32) { - /// Device memories erase status This bit is set by hardware when SRAM2, ICACHE, PKA SRAM erase is completed after power-on reset or tamper detection (refer to Section�75: Tamper and backup registers (TAMP) for more details). This bit is not reset by system reset and is cleared by software by writing 1 to it. - MCLR: u1, - reserved16: u15, - /// ICACHE and PKA SRAM erase status This bit is set by hardware when ICACHE and PKA SRAM erase is completed after potential tamper detection (refer to Section�75: Tamper and backup registers (TAMP) for more details). This bit is cleared by software by writing 1 to it. - IPMEE: u1, - padding: u15, - }), - /// compensation cell control/status register - CCCSR: mmio.Mmio(packed struct(u32) { - /// VDD I/Os compensation cell enable This bit enables the compensation cell of the I/Os supplied by VDD. - EN1: u1, - /// VDD I/Os code selection This bit selects the code to be applied for the compensation cell of the I/Os supplied by VDD. - CS1: u1, - reserved8: u6, - /// VDD I/Os compensation cell ready flag This bit provides the compensation cell status of the I/Os supplied by VDD. Note: The HSI clock is required for the compensation cell to work properly. The compensation cell ready bit (RDY1) is not set if the HSI clock is not enabled (HSION). - RDY1: u1, - padding: u23, - }), - /// compensation cell value register - CCVR: mmio.Mmio(packed struct(u32) { - /// NMOS compensation value of the I/Os supplied by VDD This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is reset. - NCV1: u4, - /// PMOS compensation value of the I/Os supplied by VDD This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is reset. - PCV1: u4, - padding: u24, - }), - /// compensation cell code register - CCCR: mmio.Mmio(packed struct(u32) { - /// NMOS compensation code of the I/Os supplied by VDD These bits are written by software to define an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is set. - NCC1: u4, - /// PMOS compensation code of the I/Os supplied by VDD These bits are written by software to define an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is set. - PCC1: u4, - padding: u24, - }), - reserved44: [4]u8, - /// RSS command register - RSSCMDR: mmio.Mmio(packed struct(u32) { - /// RSS commands This field defines a command to be executed by the RSS. - RSSCMD: u16, - padding: u16, - }), + pub const fsmc_v2x3 = struct { + pub const ACCMOD = enum(u2) { + /// Access mode A + A = 0x0, + /// Access mode B + B = 0x1, + /// Access mode C + C = 0x2, + /// Access mode D + D = 0x3, }; - }; - pub const dbgmcu_f3 = struct { - /// Debug support - pub const DBGMCU = extern struct { - /// MCU Device ID Code Register - IDCODE: mmio.Mmio(packed struct(u32) { - /// Device Identifier - DEV_ID: u12, - reserved16: u4, - /// Revision Identifier - REV_ID: u16, - }), - /// Debug MCU Configuration Register - CR: mmio.Mmio(packed struct(u32) { - /// Debug Sleep mode - DBG_SLEEP: u1, - /// Debug Stop Mode - DBG_STOP: u1, - /// Debug Standby Mode - DBG_STANDBY: u1, - reserved5: u2, - /// Trace pin assignment control - TRACE_IOEN: u1, - /// Trace pin assignment control - TRACE_MODE: u2, - padding: u24, - }), - /// APB Low Freeze Register - APB1FZR: mmio.Mmio(packed struct(u32) { - /// Debug Timer 2 stopped when Core is halted - TIM2: u1, - /// Debug Timer 3 stopped when Core is halted - TIM3: u1, - /// Debug Timer 4 stopped when Core is halted - TIM4: u1, - /// Debug Timer 5 stopped when Core is halted - TIM5: u1, - /// Debug Timer 6 stopped when Core is halted - TIM6: u1, - /// Debug Timer 7 stopped when Core is halted - TIM7: u1, - /// Debug Timer 12 stopped when Core is halted - TIM12: u1, - /// Debug Timer 13 stopped when Core is halted - TIM13: u1, - /// Debug Timer 14 stopped when Core is halted - TIM14: u1, - /// Debug Timer 18 stopped when Core is halted - TIM18: u1, - /// Debug RTC stopped when Core is halted - RTC: u1, - /// Debug Window Wachdog stopped when Core is halted - WWDG: u1, - /// Debug Independent Wachdog stopped when Core is halted - IWDG: u1, - reserved21: u8, - /// SMBUS timeout mode stopped when Core is halted - I2C1_SMBUS_TIMEOUT: u1, - /// SMBUS timeout mode stopped when Core is halted - I2C2_SMBUS_TIMEOUT: u1, - reserved25: u2, - /// Debug CAN stopped when core is halted - CAN: u1, - padding: u6, - }), - /// APB High Freeze Register - APB2FZR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Debug Timer 15 stopped when Core is halted - TIM15: u1, - /// Debug Timer 16 stopped when Core is halted - TIM16: u1, - /// Debug Timer 17 stopped when Core is halted - TIM17: u1, - /// Debug Timer 19 stopped when Core is halted - TIM19: u1, - padding: u26, - }), - }; - }; - - pub const syscfg_wl5 = struct { - /// System configuration controller - pub const SYSCFG = extern struct { - /// memory remap register - MEMRMP: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection - MEM_MODE: u3, - padding: u29, - }), - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// I/O analog switch voltage booster enable - BOOSTEN: u1, - reserved16: u7, - /// Fast-mode Plus (Fm+) driving capability activation on PB6 - I2C_PB6_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB7 - I2C_PB7_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB8 - I2C_PB8_FMP: u1, - /// Fast-mode Plus (Fm+) driving capability activation on PB9 - I2C_PB9_FMP: u1, - /// I2C1 Fast-mode Plus driving capability activation - I2C1_FMP: u1, - /// I2C2 Fast-mode Plus driving capability activation - I2C2_FMP: u1, - /// I2C3 Fast-mode Plus driving capability activation - I2C3_FMP: u1, - padding: u9, - }), - /// external interrupt configuration register 1 - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI12 configuration bits - EXTI: u3, - padding: u29, - }), - /// SCSR - SCSR: mmio.Mmio(packed struct(u32) { - /// SRAM2 erase - SRAM2ER: u1, - /// SRAM1, SRAM2 and PKA SRAM busy by erase operation - SRAMBSY: u1, - reserved8: u6, - /// PKA SRAM busy by erase operation - PKASRAMBSY: u1, - padding: u23, - }), - /// CFGR2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// CPU1 LOCKUP (Hardfault) output enable bit - CLL: u1, - /// SRAM2 parity lock bit - SPL: u1, - /// PVD lock enable bit - PVDL: u1, - /// ECC Lock - ECCL: u1, - reserved8: u4, - /// SRAM2 parity error flag - SPF: u1, - padding: u23, - }), - /// SWPR - SWPR: mmio.Mmio(packed struct(u32) { - /// SRAM2 1Kbyte page 0 write protection - PWP: u1, - padding: u31, - }), - /// SKR - SKR: mmio.Mmio(packed struct(u32) { - /// SRAM2 write protection key for software erase - KEY: u8, - padding: u24, - }), - reserved256: [216]u8, - /// SYSCFG CPU1 interrupt mask register 1 - IMR1: mmio.Mmio(packed struct(u32) { - /// RTCSTAMPTAMPLSECSSIM - RTCSTAMPTAMPLSECSSIM: u1, - reserved2: u1, - /// RTCSSRUIM - RTCSSRUIM: u1, - reserved21: u18, - /// EXTI5IM - EXTI5IM: u1, - /// EXTI6IM - EXTI6IM: u1, - /// EXTI7IM - EXTI7IM: u1, - /// EXTI8IM - EXTI8IM: u1, - /// EXTI9IM - EXTI9IM: u1, - /// EXTI10IM - EXTI10IM: u1, - /// EXTI11IM - EXTI11IM: u1, - /// EXTI12IM - EXTI12IM: u1, - /// EXTI13IM - EXTI13IM: u1, - /// EXTI14IM - EXTI14IM: u1, - /// EXTI15IM - EXTI15IM: u1, - }), - /// SYSCFG CPU1 interrupt mask register 2 - IMR2: mmio.Mmio(packed struct(u32) { - reserved18: u18, - /// PVM3IM - PVM3IM: u1, - reserved20: u1, - /// PVDIM - PVDIM: u1, - padding: u11, - }), - /// SYSCFG CPU2 interrupt mask register 1 - C2IMR1: mmio.Mmio(packed struct(u32) { - /// RTCSTAMPTAMPLSECSSIM - RTCSTAMPTAMPLSECSSIM: u1, - /// RTCALARMIM - RTCALARMIM: u1, - /// RTCSSRUIM - RTCSSRUIM: u1, - /// RTCWKUPIM - RTCWKUPIM: u1, - reserved5: u1, - /// RCCIM - RCCIM: u1, - /// FLASHIM - FLASHIM: u1, - reserved8: u1, - /// PKAIM - PKAIM: u1, - reserved10: u1, - /// AESIM - AESIM: u1, - /// COMPIM - COMPIM: u1, - /// ADCIM - ADCIM: u1, - /// DACIM - DACIM: u1, - reserved16: u2, - /// EXTI0IM - EXTI0IM: u1, - /// EXTI1IM - EXTI1IM: u1, - /// EXTI2IM - EXTI2IM: u1, - /// EXTI3IM - EXTI3IM: u1, - /// EXTI4IM - EXTI4IM: u1, - /// EXTI5IM - EXTI5IM: u1, - /// EXTI6IM - EXTI6IM: u1, - /// EXTI7IM - EXTI7IM: u1, - /// EXTI8IM - EXTI8IM: u1, - /// EXTI9IM - EXTI9IM: u1, - /// EXTI10IM - EXTI10IM: u1, - /// EXTI11IM - EXTI11IM: u1, - /// EXTI12IM - EXTI12IM: u1, - /// EXTI13IM - EXTI13IM: u1, - /// EXTI14IM - EXTI14IM: u1, - /// EXTI15IM - EXTI15IM: u1, - }), - /// SYSCFG CPU2 interrupt mask register 2 - C2IMR2: mmio.Mmio(packed struct(u32) { - /// DMA1CH1IM - DMA1CH1IM: u1, - /// DMA1CH2IM - DMA1CH2IM: u1, - /// DMA1CH3IM - DMA1CH3IM: u1, - /// DMA1CH4IM - DMA1CH4IM: u1, - /// DMA1CH5IM - DMA1CH5IM: u1, - /// DMA1CH6IM - DMA1CH6IM: u1, - /// DMA1CH7IM - DMA1CH7IM: u1, - reserved8: u1, - /// DMA2CH1IM - DMA2CH1IM: u1, - /// DMA2CH2IM - DMA2CH2IM: u1, - /// DMA2CH3IM - DMA2CH3IM: u1, - /// DMA2CH4IM - DMA2CH4IM: u1, - /// DMA2CH5IM - DMA2CH5IM: u1, - /// DMA2CH6IM - DMA2CH6IM: u1, - /// DMA2CH7IM - DMA2CH7IM: u1, - /// DMAMUX1IM - DMAMUX1IM: u1, - reserved18: u2, - /// PVM3IM - PVM3IM: u1, - reserved20: u1, - /// PVDIM - PVDIM: u1, - padding: u11, - }), - reserved520: [248]u8, - /// radio debug control register - RFDCR: mmio.Mmio(packed struct(u32) { - /// radio debug test bus selection - RFTBSEL: u1, - padding: u31, - }), + pub const ECCPS = enum(u3) { + /// ECC page size 256 bytes + Bytes256 = 0x0, + /// ECC page size 512 bytes + Bytes512 = 0x1, + /// ECC page size 1024 bytes + Bytes1024 = 0x2, + /// ECC page size 2048 bytes + Bytes2048 = 0x3, + /// ECC page size 4096 bytes + Bytes4096 = 0x4, + /// ECC page size 8192 bytes + Bytes8192 = 0x5, + _, }; - }; - pub const adccommon_v2 = struct { - pub const ADCPRE = enum(u2) { - /// PCLK2 divided by 2 - Div2 = 0x0, - /// PCLK2 divided by 4 - Div4 = 0x1, - /// PCLK2 divided by 6 - Div6 = 0x2, - /// PCLK2 divided by 8 - Div8 = 0x3, + pub const MTYP = enum(u2) { + /// SRAM memory type + SRAM = 0x0, + /// PSRAM (CRAM) memory type + PSRAM = 0x1, + /// NOR Flash/OneNAND Flash + Flash = 0x2, + _, }; - pub const DDS = enum(u1) { - /// No new DMA request is issued after the last transfer - Single = 0x0, - /// DMA requests are issued as long as data are converted and DMA=01, 10 or 11 - Continuous = 0x1, + pub const MWID = enum(u2) { + /// Memory data bus width 8 bits + Bits8 = 0x0, + /// Memory data bus width 16 bits + Bits16 = 0x1, + /// Memory data bus width 32 bits + Bits32 = 0x2, + _, }; - pub const DMA = enum(u2) { - /// DMA mode disabled - Disabled = 0x0, - /// DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3) - Mode1 = 0x1, - /// DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) - Mode2 = 0x2, - /// DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) - Mode3 = 0x3, + pub const PTYP = enum(u1) { + /// NAND Flash + NANDFlash = 0x1, + _, }; - pub const MULTI = enum(u5) { - /// All the ADCs independent: independent mode - Independent = 0x0, - /// Dual ADC1 and ADC2, combined regular and injected simultaneous mode - DualRJ = 0x1, - /// Dual ADC1 and ADC2, combined regular and alternate trigger mode - DualRA = 0x2, - /// Dual ADC1 and ADC2, injected simultaneous mode only - DualJ = 0x5, - /// Dual ADC1 and ADC2, regular simultaneous mode only - DualR = 0x6, - /// Dual ADC1 and ADC2, interleaved mode only - DualI = 0x7, - /// Dual ADC1 and ADC2, alternate trigger mode only - DualA = 0x9, - /// Triple ADC, regular and injected simultaneous mode - TripleRJ = 0x11, - /// Triple ADC, regular and alternate trigger mode - TripleRA = 0x12, - /// Triple ADC, injected simultaneous mode only - TripleJ = 0x15, - /// Triple ADC, regular simultaneous mode only - TripleR = 0x16, - /// Triple ADC, interleaved mode only - TripleI = 0x17, - /// Triple ADC, alternate trigger mode only - TripleA = 0x18, + pub const PWID = enum(u2) { + /// External memory device width 8 bits + Bits8 = 0x0, + /// External memory device width 16 bits + Bits16 = 0x1, _, }; - /// ADC common registers - pub const ADC_COMMON = extern struct { - /// ADC Common status register - CSR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog event occurred - AWD: u1, - /// End of conversion of ADC - EOC: u1, - /// Injected channel end of conversion of ADC - JEOC: u1, - /// Injected channel conversion started - JSTRT: u1, - /// regular channel conversion started - STRT: u1, - /// Overrun occurred - OVR: u1, - padding: u26, - }), - /// ADC common control register - CCR: mmio.Mmio(packed struct(u32) { - /// Multi ADC mode selection - MULTI: packed union { - raw: u5, - value: MULTI, + pub const WAITCFG = enum(u1) { + /// NWAIT signal is active one data cycle before wait state + BeforeWaitState = 0x0, + /// NWAIT signal is active during wait state + DuringWaitState = 0x1, + }; + + pub const WAITPOL = enum(u1) { + /// NWAIT active low + ActiveLow = 0x0, + /// NWAIT active high + ActiveHigh = 0x1, + }; + + /// Flexible static memory controller + pub const FSMC = extern struct { + /// SRAM/NOR-Flash chip-select control register 1 + BCR1: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { + raw: u2, + value: MTYP, }, - reserved8: u3, - /// Delay between 2 sampling phases - DELAY: u4, - reserved13: u1, - /// DMA disable selection for multi-ADC mode - DDS: packed union { + /// Memory data bus width + MWID: packed union { + raw: u2, + value: MWID, + }, + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { raw: u1, - value: DDS, + value: WAITPOL, }, - /// Direct memory access mode for multi ADC mode - DMA: packed union { + /// WRAPMOD + WRAPMOD: u1, + /// Wait timing configuration + WAITCFG: packed union { + raw: u1, + value: WAITCFG, + }, + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + reserved19: u3, + /// Write burst enable + CBURSTRW: u1, + /// Continuous clock enable + CCLKEN: u1, + padding: u11, + }), + /// SRAM/NOR-Flash chip-select timing register 1-4 + BTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + /// Clock divide ratio (for FMC_CLK signal) + CLKDIV: u4, + /// Data latency for synchronous memory + DATLAT: u4, + /// Access mode + ACCMOD: packed union { raw: u2, - value: DMA, + value: ACCMOD, }, - /// ADC prescaler - ADCPRE: packed union { + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 2-4 + BCR: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { raw: u2, - value: ADCPRE, + value: MTYP, }, - reserved22: u4, - /// VBAT enable - VBATE: u1, - /// Temperature sensor and VREFINT enable - TSVREFE: u1, - padding: u8, + /// Memory data bus width + MWID: packed union { + raw: u2, + value: MWID, + }, + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { + raw: u1, + value: WAITPOL, + }, + /// WRAPMOD + WRAPMOD: u1, + /// Wait timing configuration + WAITCFG: packed union { + raw: u1, + value: WAITCFG, + }, + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + reserved19: u3, + /// Write burst enable + CBURSTRW: u1, + padding: u12, }), - /// ADC common regular data register for dual and triple modes - CDR: mmio.Mmio(packed struct(u32) { - /// 1st data item of a pair of regular conversions - DATA: u16, - padding: u16, + reserved96: [84]u8, + /// PC Card/NAND Flash control register 2-4 + PCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Wait feature enable bit + PWAITEN: u1, + /// NAND Flash memory bank enable bit + PBKEN: u1, + /// Memory type + PTYP: packed union { + raw: u1, + value: PTYP, + }, + /// Data bus width + PWID: packed union { + raw: u2, + value: PWID, + }, + /// ECC computation logic enable bit + ECCEN: u1, + reserved9: u2, + /// CLE to RE delay + TCLR: u4, + /// ALE to RE delay + TAR: u4, + /// ECC page size + ECCPS: packed union { + raw: u3, + value: ECCPS, + }, + padding: u12, + }), + /// FIFO status and interrupt register 2-4 + SR: mmio.Mmio(packed struct(u32) { + /// Interrupt rising edge status + IRS: u1, + /// Interrupt high-level status + ILS: u1, + /// Interrupt falling edge status + IFS: u1, + /// Interrupt rising edge detection enable bit + IREN: u1, + /// Interrupt high-level detection enable bit + ILEN: u1, + /// Interrupt falling edge detection enable bit + IFEN: u1, + /// FIFO empty status + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 2-4 + PMEM: mmio.Mmio(packed struct(u32) { + /// Common memory x setup time + MEMSET: u8, + /// Common memory wait time + MEMWAIT: u8, + /// Common memory hold time + MEMHOLD: u8, + /// Common memory x data bus Hi-Z time + MEMHIZ: u8, + }), + /// Attribute memory space timing register 2-4 + PATT: mmio.Mmio(packed struct(u32) { + /// Attribute memory setup time + ATTSET: u8, + /// Attribute memory wait time + ATTWAIT: u8, + /// Attribute memory hold time + ATTHOLD: u8, + /// Attribute memory data bus Hi-Z time + ATTHIZ: u8, + }), + reserved116: [4]u8, + /// ECC result register 2-3 + ECCR: mmio.Mmio(packed struct(u32) { + /// ECC computation result value + ECC: u32, + }), + reserved176: [56]u8, + /// I/O space timing register 4 + PIO4: mmio.Mmio(packed struct(u32) { + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), + reserved260: [80]u8, + /// SRAM/NOR-Flash write timing registers 1-4 + BWTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + reserved28: u12, + /// Access mode + ACCMOD: packed union { + raw: u2, + value: ACCMOD, + }, + padding: u2, }), }; }; - pub const octospi_v1 = struct { - pub const FlashSelect = enum(u1) { - /// FLASH 1 selected (data exchanged over IO[3:0]) - FlashOne = 0x0, - /// FLASH 2 selected (data exchanged over IO[7:4]) - FlashTwo = 0x1, + pub const fsmc_v3x1 = struct { + pub const ACCMOD = enum(u2) { + /// Access mode A + A = 0x0, + /// Access mode B + B = 0x1, + /// Access mode C + C = 0x2, + /// Access mode D + D = 0x3, }; - pub const FunctionalMode = enum(u2) { - /// Indirect-write mode - IndirectWrite = 0x0, - /// Indirect-read mode - IndirectRead = 0x1, - /// Automatic status-polling mode - AutoStatusPolling = 0x2, - /// Memory-mapped mode - MemoryMapped = 0x3, + pub const CPSIZE = enum(u3) { + /// No burst split when crossing page boundary + NoBurstSplit = 0x0, + /// 128 bytes CRAM page size + Bytes128 = 0x1, + /// 256 bytes CRAM page size + Bytes256 = 0x2, + /// 512 bytes CRAM page size + Bytes512 = 0x3, + /// 1024 bytes CRAM page size + Bytes1024 = 0x4, + _, }; - pub const LatencyMode = enum(u1) { - /// Variable initial latency - Variable = 0x0, - /// Fixed latency - Fixed = 0x1, + pub const ECCPS = enum(u3) { + /// ECC page size 256 bytes + Bytes256 = 0x0, + /// ECC page size 512 bytes + Bytes512 = 0x1, + /// ECC page size 1024 bytes + Bytes1024 = 0x2, + /// ECC page size 2048 bytes + Bytes2048 = 0x3, + /// ECC page size 4096 bytes + Bytes4096 = 0x4, + /// ECC page size 8192 bytes + Bytes8192 = 0x5, + _, }; - pub const MatchMode = enum(u1) { - /// AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register. - MatchAnd = 0x0, - /// OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register. - MatchOr = 0x1, + pub const MTYP = enum(u2) { + /// SRAM memory type + SRAM = 0x0, + /// PSRAM (CRAM) memory type + PSRAM = 0x1, + /// NOR Flash/OneNAND Flash + Flash = 0x2, + _, }; - pub const MemType = enum(u3) { - /// Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes. - Micron = 0x0, - /// Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes. - Macronix = 0x1, - /// Standard mode - B_Standard = 0x2, - /// Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping. - MacronixRam = 0x3, - /// HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected. - HyperBusMemory = 0x4, - /// HyperBus register mode, addressing register space. The memory-mapped accesses in. this mode must be non-cacheable, or Indirect read/write modes must be used. - HyperBusRegister = 0x5, + pub const MWID = enum(u2) { + /// Memory data bus width 8 bits + Bits8 = 0x0, + /// Memory data bus width 16 bits + Bits16 = 0x1, + /// Memory data bus width 32 bits + Bits32 = 0x2, _, }; - pub const PhaseMode = enum(u3) { - /// No alternate bytes - None = 0x0, - /// Alternate bytes on a single line - OneLine = 0x1, - /// Alternate bytes on two lines - TwoLines = 0x2, - /// Alternate bytes on four lines - FourLines = 0x3, - /// Alternate bytes on eight lines - EightLines = 0x4, + pub const PTYP = enum(u1) { + /// NAND Flash + NANDFlash = 0x1, _, }; - pub const SampleShift = enum(u1) { - /// No shift - None = 0x0, - /// 1/2 cycle shift - HalfCycle = 0x1, + pub const PWID = enum(u2) { + /// External memory device width 8 bits + Bits8 = 0x0, + /// External memory device width 16 bits + Bits16 = 0x1, + _, }; - pub const SizeInBits = enum(u2) { - /// 8-bit alternate bytes - @"8Bit" = 0x0, - /// 16-bit alternate bytes - @"16Bit" = 0x1, - /// 24-bit alternate bytes - @"24Bit" = 0x2, - /// 32-bit alternate bytes - @"32Bit" = 0x3, + pub const WAITCFG = enum(u1) { + /// NWAIT signal is active one data cycle before wait state + BeforeWaitState = 0x0, + /// NWAIT signal is active during wait state + DuringWaitState = 0x1, }; - pub const Threshold = enum(u5) { - /// FTF is set if there are one or more free bytes available to be written to in the FIFO in Indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in Indirect-read mode. - NeedOneByte = 0x0, - /// FTF is set if there are two or more free bytes available to be written to in the FIFO in Indirect‑write mode, or if there are two or more valid bytes can be read from the FIFO in Indirect-read mode. - NeedTwoBytes = 0x1, - /// FTF is set if there are 32 free bytes available to be written to in the FIFO in Indirect-write mode, or if there are 32 valid bytes can be read from the FIFO in Indirect-read mode. - NeedThirtyTwoBytes = 0x1f, - _, + pub const WAITPOL = enum(u1) { + /// NWAIT active low + ActiveLow = 0x0, + /// NWAIT active high + ActiveHigh = 0x1, }; - /// OctoSPI - pub const OCTOSPI = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// Enable This bit enables the OCTOSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case. this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active. - EN: u1, - /// Abort request. This bit aborts the ongoing command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0. - ABORT: u1, - /// DMA enable In Indirect mode, the DMA can be used to input or output data via DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write. this bit during DMA operation. - DMAEN: u1, - /// Timeout counter enable. This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter. - TCEN: u1, - reserved6: u2, - /// Dual-memory configuration. This bit activates the dual-memory configuration, where two external devices are used simultaneously to double the throughput and the capacity - DMM: u1, - /// Flash select. This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in single-memory configuration (when DMM = 0). This bit is ignored when DMM = 1 or when Octal-SPI mode is selected. - FSEL: packed union { - raw: u1, - value: FlashSelect, + /// Flexible static memory controller + pub const FSMC = extern struct { + /// SRAM/NOR-Flash chip-select control register 1 + BCR1: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { + raw: u2, + value: MTYP, }, - /// FIFO threshold level. This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[4:0] value. - FTHRES: packed union { - raw: u5, - value: Threshold, + /// Memory data bus width + MWID: packed union { + raw: u2, + value: MWID, }, - reserved16: u3, - /// Transfer error interrupt enable. This bit enables the transfer error interrupt. - TEIE: u1, - /// Transfer complete interrupt enable. This bit enables the transfer complete interrupt. - TCIE: u1, - /// FIFO threshold interrupt enable. This bit enables the FIFO threshold interrupt. - FTIE: u1, - /// Status match interrupt enable. This bit enables the status match interrupt. - SMIE: u1, - /// Timeout interrupt enable. This bit enables the timeout interrupt. - TOIE: u1, - reserved22: u1, - /// Automatic status-polling mode stop. This bit determines if the Automatic status-polling mode is stopped after a match. - APMS: u1, - /// Polling match mode. This bit indicates which method must be used to determine a match during the Automatic status-polling mode. - PMM: packed union { + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { raw: u1, - value: MatchMode, + value: WAITPOL, }, - reserved28: u4, - /// Functional mode. This field defines the OCTOSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state. - FMODE: packed union { + reserved11: u1, + /// Wait timing configuration + WAITCFG: packed union { + raw: u1, + value: WAITCFG, + }, + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + /// CRAM page size + CPSIZE: packed union { + raw: u3, + value: CPSIZE, + }, + /// Write burst enable + CBURSTRW: u1, + /// Continuous clock enable + CCLKEN: u1, + /// Write FIFO disable + WFDIS: u1, + padding: u10, + }), + /// SRAM/NOR-Flash chip-select timing register 1-4 + BTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + /// Clock divide ratio (for FMC_CLK signal) + CLKDIV: u4, + /// Data latency for synchronous memory + DATLAT: u4, + /// Access mode + ACCMOD: packed union { raw: u2, - value: FunctionalMode, + value: ACCMOD, }, padding: u2, }), - reserved8: [4]u8, - /// device configuration register 1 - DCR1: mmio.Mmio(packed struct(u32) { - /// Mode 0/Mode 3 This bit indicates the level taken by the CLK between commands (when NCS = 1). - CKMODE: u1, - /// Free running clock. This bit configures the free running clock. - FRCK: u1, - reserved3: u1, - /// Delay block bypass - DLYBYP: u1, - reserved8: u4, - /// Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (NCS) must remain high between commands issued to the external device. ... - CSHT: u6, - reserved16: u2, - /// Device size. This field defines the size of the external device using the following formula: Number of bytes in device = 2[DEVSIZE+1]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes. In Regular-command protocol, if DMM = 1, DEVSIZE[4:0] indicates the total capacity of the two devices together. - DEVSIZE: u5, - reserved24: u3, - /// Memory type. This bit indicates the type of memory to be supported. Note: In. this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP[2:0] for memories different from Micron. Others: Reserved + /// SRAM/NOR-Flash chip-select control register 2-4 + BCR: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type MTYP: packed union { + raw: u2, + value: MTYP, + }, + /// Memory data bus width + MWID: packed union { + raw: u2, + value: MWID, + }, + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { + raw: u1, + value: WAITPOL, + }, + reserved11: u1, + /// Wait timing configuration + WAITCFG: packed union { + raw: u1, + value: WAITCFG, + }, + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + /// CRAM page size + CPSIZE: packed union { raw: u3, - value: MemType, + value: CPSIZE, }, - padding: u5, - }), - /// device configuration register 2 - DCR2: mmio.Mmio(packed struct(u32) { - /// Clock prescaler. This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). 2: FCLK = FKERNEL/3 ... 255: FCLK = FKERNEL/256 For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low one cycle longer than it stays high. - PRESCALER: u8, - reserved16: u8, - /// Wrap size. This field indicates the wrap size to which the memory is configured. For memories which have a separate command for wrapped instructions, this field indicates the wrap-size associated with the command held in the OCTOSPI1_WPIR register. 110-111: Reserved - WRAPSIZE: u3, - padding: u13, - }), - /// device configuration register 3 - DCR3: mmio.Mmio(packed struct(u32) { - /// Maximum transfer - MAXTRAN: u8, - reserved16: u8, - /// NCS boundary. This field enables the transaction boundary feature. When active, a minimum value of 3 is recommended. The NCS is released on each boundary of 2CSBOUND bytes. others: NCS boundary set to 2CSBOUND bytes - CSBOUND: u5, - padding: u11, + /// Write burst enable + CBURSTRW: u1, + padding: u12, }), - /// device configuration register 4 - DCR4: mmio.Mmio(packed struct(u32) { - /// Refresh rate. This field enables the refresh rate feature. The NCS is released every REFRESH + 1 clock cycles for writes, and REFRESH + 4 clock cycles for reads. Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in Single-, Dual- or Quad-SPI mode, because the byte transmission must be completed. others: Maximum communication length is set to REFRESH + 1 clock cycles. - REFRESH: u32, + reserved128: [116]u8, + /// PC Card/NAND Flash control register + PCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Wait feature enable bit + PWAITEN: u1, + /// NAND Flash memory bank enable bit + PBKEN: u1, + /// Memory type + PTYP: packed union { + raw: u1, + value: PTYP, + }, + /// Data bus width + PWID: packed union { + raw: u2, + value: PWID, + }, + /// ECC computation logic enable bit + ECCEN: u1, + reserved9: u2, + /// CLE to RE delay + TCLR: u4, + /// ALE to RE delay + TAR: u4, + /// ECC page size + ECCPS: packed union { + raw: u3, + value: ECCPS, + }, + padding: u12, }), - reserved32: [8]u8, - /// status register + /// FIFO status and interrupt register SR: mmio.Mmio(packed struct(u32) { - /// Transfer error flag. This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode. It is cleared by writing 1 to CTEF. - TEF: u1, - /// Transfer complete flag. This bit is set in Indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF. - TCF: u1, - /// FIFO threshold flag In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete. It is cleared automatically as soon as the threshold condition is no longer true. In Automatic status-polling mode, this bit is set every time the status register is read, and the bit is cleared when the data register is read. - FTF: u1, - /// Status match flag. This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (PSMAR). It is cleared by writing 1 to CSMF. - SMF: u1, - /// Timeout flag. This bit is set when timeout occurs. It is cleared by writing 1 to CTOF. - TOF: u1, - /// Busy. This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty. - BUSY: u1, - reserved8: u2, - /// FIFO level. This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 32 when it is full. In Automatic status-polling mode, FLEVEL is zero. - FLEVEL: u6, - padding: u18, + /// Interrupt rising edge status + IRS: u1, + /// Interrupt high-level status + ILS: u1, + /// Interrupt falling edge status + IFS: u1, + /// Interrupt rising edge detection enable bit + IREN: u1, + /// Interrupt high-level detection enable bit + ILEN: u1, + /// Interrupt falling edge detection enable bit + IFEN: u1, + /// FIFO empty status + FEMPT: u1, + padding: u25, }), - /// flag clear register - FCR: mmio.Mmio(packed struct(u32) { - /// Clear transfer error flag Writing 1 clears the TEF flag in the SR register. - CTEF: u1, - /// Clear transfer complete flag Writing 1 clears the TCF flag in the SR register. - CTCF: u1, - reserved3: u1, - /// Clear status match flag Writing 1 clears the SMF flag in the SR register. - CSMF: u1, - /// Clear timeout flag Writing 1 clears the TOF flag in the SR register. - CTOF: u1, - padding: u27, + /// Common memory space timing register + PMEM: mmio.Mmio(packed struct(u32) { + /// Common memory x setup time + MEMSET: u8, + /// Common memory wait time + MEMWAIT: u8, + /// Common memory hold time + MEMHOLD: u8, + /// Common memory x data bus Hi-Z time + MEMHIZ: u8, }), - reserved64: [24]u8, - /// data length register - DLR: mmio.Mmio(packed struct(u32) { - /// [31: 0]: Data length Number of data to be retrieved (value+1) in Indirect and Automatic status-polling modes. A value not greater than three (indicating 4 bytes) must be used for Automatic status-polling mode. All 1’s in Indirect mode means undefined length, where OCTOSPI continues until the end of the memory, as defined by DEVSIZE. 0x0000_0000: 1 byte is to be transferred. 0x0000_0001: 2 bytes are to be transferred. 0x0000_0002: 3 bytes are to be transferred. 0x0000_0003: 4 bytes are to be transferred. ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred. 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred. 0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F. DL[0] is stuck at 1 in dual-memory configuration (DMM = 1) even when 0 is written to. this bit, thus assuring that each access transfers an even number of bytes. This field has no effect in Memory-mapped mode. - DL: u32, - }), - reserved72: [4]u8, - /// address register - AR: mmio.Mmio(packed struct(u32) { - /// Address to be sent to the external device. In HyperBus protocol, this field must be even as this protocol is 16-bit word oriented. In dual-memory configuration, AR[0] is forced to 1. Writes to. this field are ignored when BUSY = 1 or when FMODE = 11 (Memory-mapped mode). - ADDRESS: u32, - }), - reserved80: [4]u8, - /// data register - DR: mmio.Mmio(packed struct(u32) { - /// [31: 0]: Data Data to be sent/received to/from the external SPI device In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In Indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In Automatic status-polling mode, this register contains the last data read from the external device (without masking). Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes. Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read 2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom of. this register: A byte read must read DATA[7:0] and a half-word read must read DATA[15:0]. - DATA: u32, - }), - reserved128: [44]u8, - /// polling status mask register - PSMKR: mmio.Mmio(packed struct(u32) { - /// Status mask Mask to be applied to the status bytes received in Automatic status-polling mode For bit n: - MASK: u32, - }), - reserved136: [4]u8, - /// polling status match register - PSMAR: mmio.Mmio(packed struct(u32) { - /// [31: 0]: Status match Value to be compared with the masked status register to get a match - MATCH: u32, + /// Attribute memory space timing register + PATT: mmio.Mmio(packed struct(u32) { + /// Attribute memory setup time + ATTSET: u8, + /// Attribute memory wait time + ATTWAIT: u8, + /// Attribute memory hold time + ATTHOLD: u8, + /// Attribute memory data bus Hi-Z time + ATTHIZ: u8, }), - reserved144: [4]u8, - /// polling interval register - PIR: mmio.Mmio(packed struct(u32) { - /// [15: 0]: Polling interval Number of CLK cycle between a read during the Automatic status-polling phases - INTERVAL: u16, - padding: u16, + reserved148: [4]u8, + /// ECC result register + ECCR: mmio.Mmio(packed struct(u32) { + /// ECC computation result value + ECC: u32, }), - reserved256: [108]u8, - /// communication configuration register - CCR: mmio.Mmio(packed struct(u32) { - /// Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved - IMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// Instruction double transfer rate. This bit sets the DTR mode for the instruction phase. - IDTR: u1, - /// Instruction size. This bit defines instruction size. - ISIZE: packed union { + reserved260: [108]u8, + /// SRAM/NOR-Flash write timing registers 1-4 + BWTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + reserved28: u8, + /// Access mode + ACCMOD: packed union { raw: u2, - value: SizeInBits, - }, - reserved8: u2, - /// Address mode. This field defines the address phase mode of operation. 101-111: Reserved - ADMODE: packed union { - raw: u3, - value: PhaseMode, + value: ACCMOD, }, - /// Address double transfer rate. This bit sets the DTR mode for the address phase. - ADDTR: u1, - /// Address size. This field defines address size. - ADSIZE: packed union { + padding: u2, + }), + }; + }; + + pub const fsmc_v4x1 = struct { + pub const ACCMOD = enum(u2) { + /// Access mode A + A = 0x0, + /// Access mode B + B = 0x1, + /// Access mode C + C = 0x2, + /// Access mode D + D = 0x3, + }; + + pub const CPSIZE = enum(u3) { + /// No burst split when crossing page boundary + NoBurstSplit = 0x0, + /// 128 bytes CRAM page size + Bytes128 = 0x1, + /// 256 bytes CRAM page size + Bytes256 = 0x2, + /// 512 bytes CRAM page size + Bytes512 = 0x3, + /// 1024 bytes CRAM page size + Bytes1024 = 0x4, + _, + }; + + pub const ECCPS = enum(u3) { + /// ECC page size 256 bytes + Bytes256 = 0x0, + /// ECC page size 512 bytes + Bytes512 = 0x1, + /// ECC page size 1024 bytes + Bytes1024 = 0x2, + /// ECC page size 2048 bytes + Bytes2048 = 0x3, + /// ECC page size 4096 bytes + Bytes4096 = 0x4, + /// ECC page size 8192 bytes + Bytes8192 = 0x5, + _, + }; + + pub const MTYP = enum(u2) { + /// SRAM memory type + SRAM = 0x0, + /// PSRAM (CRAM) memory type + PSRAM = 0x1, + /// NOR Flash/OneNAND Flash + Flash = 0x2, + _, + }; + + pub const MWID = enum(u2) { + /// Memory data bus width 8 bits + Bits8 = 0x0, + /// Memory data bus width 16 bits + Bits16 = 0x1, + /// Memory data bus width 32 bits + Bits32 = 0x2, + _, + }; + + pub const PTYP = enum(u1) { + /// NAND Flash + NANDFlash = 0x1, + _, + }; + + pub const PWID = enum(u2) { + /// External memory device width 8 bits + Bits8 = 0x0, + /// External memory device width 16 bits + Bits16 = 0x1, + _, + }; + + pub const WAITCFG = enum(u1) { + /// NWAIT signal is active one data cycle before wait state + BeforeWaitState = 0x0, + /// NWAIT signal is active during wait state + DuringWaitState = 0x1, + }; + + pub const WAITPOL = enum(u1) { + /// NWAIT active low + ActiveLow = 0x0, + /// NWAIT active high + ActiveHigh = 0x1, + }; + + /// Flexible static memory controller + pub const FSMC = extern struct { + /// SRAM/NOR-Flash chip-select control register 1 + BCR1: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { raw: u2, - value: SizeInBits, - }, - reserved16: u2, - /// Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved - ABMODE: packed union { - raw: u3, - value: PhaseMode, + value: MTYP, }, - /// Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase. This field can be written only when BUSY = 0. - ABDTR: u1, - /// Alternate bytes size. This bit defines alternate bytes size. - ABSIZE: packed union { + /// Memory data bus width + MWID: packed union { raw: u2, - value: SizeInBits, + value: MWID, }, - reserved24: u2, - /// Data mode. This field defines the data phase mode of operation. 101-111: Reserved - DMODE: packed union { - raw: u3, - value: PhaseMode, + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { + raw: u1, + value: WAITPOL, }, - /// Data double transfer rate. This bit sets the DTR mode for the data phase. - DDTR: u1, - reserved29: u1, - /// DQS enable. This bit enables the data strobe management. - DQSE: u1, - reserved31: u1, - /// Send instruction only once mode. This bit has no effect when IMODE = 00 (see ). - SIOO: u1, - }), - reserved264: [4]u8, - /// timing configuration register - TCR: mmio.Mmio(packed struct(u32) { - /// Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least six dummy cycles when using memories with DQS activated. - DCYC: u5, - reserved28: u23, - /// Delay hold quarter cycle - DHQC: u1, - reserved30: u1, - /// Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.) - SSHIFT: packed union { + reserved11: u1, + /// Wait timing configuration + WAITCFG: packed union { raw: u1, - value: SampleShift, + value: WAITCFG, }, - padding: u1, - }), - reserved272: [4]u8, - /// instruction register - IR: mmio.Mmio(packed struct(u32) { - /// Instruction to be sent to the external SPI device - INSTRUCTION: u32, - }), - reserved288: [12]u8, - /// alternate bytes register - ABR: mmio.Mmio(packed struct(u32) { - /// Alternate bytes - ALTERNATE: u32, - }), - reserved304: [12]u8, - /// low-power timeout register - LPTR: mmio.Mmio(packed struct(u32) { - /// [15: 0]: Timeout period After each access in Memory-mapped mode, the OCTOSPI prefetches the subsequent bytes and hold them in the FIFO. This field indicates how many CLK cycles the OCTOSPI waits after the clock becomes inactive and until it raises the NCS, putting the external device in a lower-consumption state. - TIMEOUT: u16, - padding: u16, - }), - reserved320: [12]u8, - /// wrap communication configuration register - WPCCR: mmio.Mmio(packed struct(u32) { - /// Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved - IMODE: packed union { + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + /// CRAM page size + CPSIZE: packed union { raw: u3, - value: PhaseMode, + value: CPSIZE, }, - /// Instruction double transfer rate. This bit sets the DTR mode for the instruction phase. - IDTR: u1, - /// Instruction size. This field defines instruction size. - ISIZE: packed union { + /// Write burst enable + CBURSTRW: u1, + /// Continuous clock enable + CCLKEN: u1, + /// Write FIFO disable + WFDIS: u1, + /// Byte lane (NBL) setup + NBLSET: u2, + reserved31: u7, + /// FMC controller enable + FMCEN: u1, + }), + /// SRAM/NOR-Flash chip-select timing register 1-4 + BTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + /// Clock divide ratio (for FMC_CLK signal) + CLKDIV: u4, + /// Data latency for synchronous memory + DATLAT: u4, + /// Access mode + ACCMOD: packed union { raw: u2, - value: SizeInBits, - }, - reserved8: u2, - /// Address mode. This field defines the address phase mode of operation. 101-111: Reserved - ADMODE: packed union { - raw: u3, - value: PhaseMode, + value: ACCMOD, }, - /// Address double transfer rate. This bit sets the DTR mode for the address phase. - ADDTR: u1, - /// Address size. This field defines address size. - ADSIZE: packed union { + /// Data hold phase duration + DATAHLD: u2, + }), + /// SRAM/NOR-Flash chip-select control register 2-4 + BCR: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { raw: u2, - value: SizeInBits, - }, - reserved16: u2, - /// Alternate-byte mode. This field defines the alternate byte phase mode of operation. 101-111: Reserved - ABMODE: packed union { - raw: u3, - value: PhaseMode, + value: MTYP, }, - /// Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase. - ABDTR: u1, - /// Alternate bytes size. This bit defines alternate bytes size. - ABSIZE: packed union { + /// Memory data bus width + MWID: packed union { raw: u2, - value: SizeInBits, - }, - reserved24: u2, - /// Data mode. This field defines the data phase mode of operation. 101-111: Reserved - DMODE: packed union { - raw: u3, - value: PhaseMode, + value: MWID, }, - /// Data double transfer rate. This bit sets the DTR mode for the data phase. - DDTR: u1, - reserved29: u1, - /// DQS enable. This bit enables the data strobe management. - DQSE: u1, - padding: u2, - }), - reserved328: [4]u8, - /// wrap timing configuration register - WPTCR: mmio.Mmio(packed struct(u32) { - /// Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. - DCYC: u5, - reserved28: u23, - /// Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement. - DHQC: u1, - reserved30: u1, - /// Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1). - SSHIFT: packed union { + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { raw: u1, - value: SampleShift, - }, - padding: u1, - }), - reserved336: [4]u8, - /// wrap instruction register - WPIR: mmio.Mmio(packed struct(u32) { - /// [31: 0]: Instruction Instruction to be sent to the external SPI device - INSTRUCTION: u32, - }), - reserved352: [12]u8, - /// wrap alternate bytes register - WPABR: mmio.Mmio(packed struct(u32) { - /// [31: 0]: Alternate bytes Optional data to be sent to the external SPI device right after the address - ALTERNATE: u32, - }), - reserved384: [28]u8, - /// write communication configuration register - WCCR: mmio.Mmio(packed struct(u32) { - /// Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved - IMODE: packed union { - raw: u3, - value: PhaseMode, + value: WAITPOL, }, - /// Instruction double transfer rate. This bit sets the DTR mode for the instruction phase. - IDTR: u1, - /// Instruction size. This bit defines instruction size: - ISIZE: packed union { - raw: u2, - value: SizeInBits, + reserved11: u1, + /// Wait timing configuration + WAITCFG: packed union { + raw: u1, + value: WAITCFG, }, - reserved8: u2, - /// Address mode. This field defines the address phase mode of operation. 101-111: Reserved - ADMODE: packed union { + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + /// CRAM page size + CPSIZE: packed union { raw: u3, - value: PhaseMode, - }, - /// Address double transfer rate. This bit sets the DTR mode for the address phase. - ADDTR: u1, - /// Address size. This field defines address size. - ADSIZE: packed union { - raw: u2, - value: SizeInBits, + value: CPSIZE, }, - reserved16: u2, - /// Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved - ABMODE: packed union { - raw: u3, - value: PhaseMode, + /// Write burst enable + CBURSTRW: u1, + reserved22: u2, + /// Byte lane (NBL) setup + NBLSET: u2, + padding: u8, + }), + reserved32: [20]u8, + /// PSRAM chip select counter register + PCSCNTR: mmio.Mmio(packed struct(u32) { + /// Chip select counter + CSCOUNT: u16, + /// Counter Bank 1 enable + CNTB1EN: u1, + /// Counter Bank 2 enable + CNTB2EN: u1, + /// Counter Bank 3 enable + CNTB3EN: u1, + /// Counter Bank 4 enable + CNTB4EN: u1, + padding: u12, + }), + reserved128: [92]u8, + /// PC Card/NAND Flash control register + PCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Wait feature enable bit + PWAITEN: u1, + /// NAND Flash memory bank enable bit + PBKEN: u1, + /// Memory type + PTYP: packed union { + raw: u1, + value: PTYP, }, - /// Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate-bytes phase. - ABDTR: u1, - /// Alternate bytes size. This field defines alternate bytes size: - ABSIZE: packed union { + /// Data bus width + PWID: packed union { raw: u2, - value: SizeInBits, + value: PWID, }, - reserved24: u2, - /// Data mode. This field defines the data phase mode of operation. 101-111: Reserved - DMODE: packed union { + /// ECC computation logic enable bit + ECCEN: u1, + reserved9: u2, + /// CLE to RE delay + TCLR: u4, + /// ALE to RE delay + TAR: u4, + /// ECC page size + ECCPS: packed union { raw: u3, - value: PhaseMode, + value: ECCPS, }, - /// data double transfer rate. This bit sets the DTR mode for the data phase. - DDTR: u1, - reserved29: u1, - /// DQS enable. This bit enables the data strobe management. - DQSE: u1, - padding: u2, + padding: u12, }), - reserved392: [4]u8, - /// write timing configuration register - WTCR: mmio.Mmio(packed struct(u32) { - /// Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. - DCYC: u5, - padding: u27, + /// FIFO status and interrupt register + SR: mmio.Mmio(packed struct(u32) { + /// Interrupt rising edge status + IRS: u1, + /// Interrupt high-level status + ILS: u1, + /// Interrupt falling edge status + IFS: u1, + /// Interrupt rising edge detection enable bit + IREN: u1, + /// Interrupt high-level detection enable bit + ILEN: u1, + /// Interrupt falling edge detection enable bit + IFEN: u1, + /// FIFO empty status + FEMPT: u1, + padding: u25, }), - reserved400: [4]u8, - /// write instruction register - WIR: mmio.Mmio(packed struct(u32) { - /// Instruction Instruction to be sent to the external SPI device - INSTRUCTION: u32, + /// Common memory space timing register + PMEM: mmio.Mmio(packed struct(u32) { + /// Common memory x setup time + MEMSET: u8, + /// Common memory wait time + MEMWAIT: u8, + /// Common memory hold time + MEMHOLD: u8, + /// Common memory x data bus Hi-Z time + MEMHIZ: u8, }), - reserved416: [12]u8, - /// write alternate bytes register - WABR: mmio.Mmio(packed struct(u32) { - /// [31: 0]: Alternate bytes. Optional data to be sent to the external SPI device right after the address - ALTERNATE: u32, + /// Attribute memory space timing register + PATT: mmio.Mmio(packed struct(u32) { + /// Attribute memory setup time + ATTSET: u8, + /// Attribute memory wait time + ATTWAIT: u8, + /// Attribute memory hold time + ATTHOLD: u8, + /// Attribute memory data bus Hi-Z time + ATTHIZ: u8, }), - reserved512: [92]u8, - /// OCTOSPI HyperBus latency configuration register - HLCR: mmio.Mmio(packed struct(u32) { - /// Latency mode. This bit selects the Latency mode. - LM: packed union { - raw: u1, - value: LatencyMode, + reserved148: [4]u8, + /// ECC result register + ECCR: mmio.Mmio(packed struct(u32) { + /// ECC computation result value + ECC: u32, + }), + reserved260: [108]u8, + /// SRAM/NOR-Flash write timing registers 1-4 + BWTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + reserved28: u8, + /// Access mode + ACCMOD: packed union { + raw: u2, + value: ACCMOD, }, - /// Write zero latency. This bit enables zero latency on write operations. - WZL: u1, - reserved8: u6, - /// [7: 0]: Access time. Device access time expressed in number of communication clock cycles - TACC: u8, - /// Read write recovery time Device read write recovery time expressed in number of communication clock cycles - TRWR: u8, - padding: u8, + /// Data hold phase duration + DATAHLD: u2, }), }; }; - pub const adccommon_h5 = struct { - pub const CKMODE = enum(u2) { - /// Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock - Asynchronous = 0x0, - /// Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck - SyncDiv1 = 0x1, - /// Use AHB clock rcc_hclk3 divided by 2 - SyncDiv2 = 0x2, - /// Use AHB clock rcc_hclk3 divided by 4 - SyncDiv4 = 0x3, + pub const fsmc_v5x1 = struct { + pub const ACCMOD = enum(u2) { + /// Access mode A + A = 0x0, + /// Access mode B + B = 0x1, + /// Access mode C + C = 0x2, + /// Access mode D + D = 0x3, }; - pub const DMACFG = enum(u1) { - /// DMA One Shot mode selected - OneShot = 0x0, - /// DMA Circular mode selected - Circular = 0x1, + pub const CPSIZE = enum(u3) { + /// No burst split when crossing page boundary + NoBurstSplit = 0x0, + /// 128 bytes CRAM page size + Bytes128 = 0x1, + /// 256 bytes CRAM page size + Bytes256 = 0x2, + /// 512 bytes CRAM page size + Bytes512 = 0x3, + /// 1024 bytes CRAM page size + Bytes1024 = 0x4, + _, }; - pub const DUAL = enum(u5) { - /// Independent mode - Independent = 0x0, - /// Dual, combined regular simultaneous + injected simultaneous mode - DualRJ = 0x1, - /// Dual, combined regular simultaneous + alternate trigger mode - DualRA = 0x2, - /// Dual, combined interleaved mode + injected simultaneous mode - DualIJ = 0x3, - /// Dual, injected simultaneous mode only - DualJ = 0x5, - /// Dual, regular simultaneous mode only - DualR = 0x6, - /// Dual, interleaved mode only - DualI = 0x7, - /// Dual, alternate trigger mode only - DualA = 0x9, + pub const ECCPS = enum(u3) { + /// ECC page size 256 bytes + Bytes256 = 0x0, + /// ECC page size 512 bytes + Bytes512 = 0x1, + /// ECC page size 1024 bytes + Bytes1024 = 0x2, + /// ECC page size 2048 bytes + Bytes2048 = 0x3, + /// ECC page size 4096 bytes + Bytes4096 = 0x4, + /// ECC page size 8192 bytes + Bytes8192 = 0x5, _, }; - pub const IDLEVALUE = enum(u4) { - /// Dummy channel selection is 0x13 - H13 = 0x0, - /// Dummy channel selection is 0x1F - H1F = 0x1, + pub const MTYP = enum(u2) { + /// SRAM memory type + SRAM = 0x0, + /// PSRAM (CRAM) memory type + PSRAM = 0x1, + /// NOR Flash/OneNAND Flash + Flash = 0x2, _, }; - pub const MDMA = enum(u2) { - /// Without data packing, CDR/CDR2 not used - NoPack = 0x0, - /// CDR formatted for 32-bit down to 10-bit resolution - Format32to10 = 0x2, - /// CDR formatted for 8-bit resolution - Format8 = 0x3, + pub const MWID = enum(u2) { + /// Memory data bus width 8 bits + Bits8 = 0x0, + /// Memory data bus width 16 bits + Bits16 = 0x1, + /// Memory data bus width 32 bits + Bits32 = 0x2, _, }; - pub const PRESC = enum(u4) { - /// adc_ker_ck_input not divided - Div1 = 0x0, - /// adc_ker_ck_input divided by 2 - Div2 = 0x1, - /// adc_ker_ck_input divided by 4 - Div4 = 0x2, - /// adc_ker_ck_input divided by 6 - Div6 = 0x3, - /// adc_ker_ck_input divided by 8 - Div8 = 0x4, - /// adc_ker_ck_input divided by 10 - Div10 = 0x5, - /// adc_ker_ck_input divided by 12 - Div12 = 0x6, - /// adc_ker_ck_input divided by 16 - Div16 = 0x7, - /// adc_ker_ck_input divided by 32 - Div32 = 0x8, - /// adc_ker_ck_input divided by 64 - Div64 = 0x9, - /// adc_ker_ck_input divided by 128 - Div128 = 0xa, - /// adc_ker_ck_input divided by 256 - Div256 = 0xb, + pub const PTYP = enum(u1) { + /// NAND Flash + NANDFlash = 0x1, _, }; - /// ADC common registers - pub const ADC_COMMON = extern struct { - /// common status register - CSR: mmio.Mmio(packed struct(u32) { - /// Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register. - ADRDY_MST: u1, - /// End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register. - EOSMP_MST: u1, - /// End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register. - EOC_MST: u1, - /// End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register. - EOS_MST: u1, - /// Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register. - OVR_MST: u1, - /// End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register. - JEOC_MST: u1, - /// End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. - JEOS_MST: u1, - /// Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. - AWD_MST: u1, - reserved10: u2, - /// Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register. - JQOVF_MST: u1, - reserved16: u5, - /// Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register. - ADRDY_SLV: u1, - /// End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADC_ISR register. - EOSMP_SLV: u1, - /// End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register. - EOC_SLV: u1, - /// End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register. - EOS_SLV: u1, - /// Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register. - OVR_SLV: u1, - /// End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register. - JEOC_SLV: u1, - /// End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. - JEOS_SLV: u1, - /// Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. - AWD_SLV: u1, - reserved26: u2, - /// Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register. - JQOVF_SLV: u1, - padding: u5, - }), - reserved8: [4]u8, - /// common control register - CCR: mmio.Mmio(packed struct(u32) { - /// Dual ADC mode selection These bits are written by software to select the operating mode. 0 value means Independent Mode. Values 00001 to 01001 means Dual mode, master and slave ADCs are working together. All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). - DUAL: packed union { - raw: u5, - value: DUAL, + pub const PWID = enum(u2) { + /// External memory device width 8 bits + Bits8 = 0x0, + /// External memory device width 16 bits + Bits16 = 0x1, + _, + }; + + pub const WAITCFG = enum(u1) { + /// NWAIT signal is active one data cycle before wait state + BeforeWaitState = 0x0, + /// NWAIT signal is active during wait state + DuringWaitState = 0x1, + }; + + pub const WAITPOL = enum(u1) { + /// NWAIT active low + ActiveLow = 0x0, + /// NWAIT active high + ActiveHigh = 0x1, + }; + + /// Flexible static memory controller + pub const FSMC = extern struct { + /// SRAM/NOR-Flash chip-select control register 1 + BCR1: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { + raw: u2, + value: MTYP, }, - reserved8: u3, - /// Delay between 2 sampling phases These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). - DELAY: u4, - reserved13: u1, - /// DMA configuration (for dual ADC mode) This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - DMACFG: packed union { + /// Memory data bus width + MWID: packed union { + raw: u2, + value: MWID, + }, + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { raw: u1, - value: DMACFG, + value: WAITPOL, }, - /// Direct memory access mode for dual ADC mode This bitfield is set and cleared by software. Refer to the DMA controller section for more details. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - MDMA: packed union { + reserved11: u1, + /// Wait timing configuration + WAITCFG: packed union { + raw: u1, + value: WAITCFG, + }, + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + /// CRAM page size + CPSIZE: packed union { + raw: u3, + value: CPSIZE, + }, + /// Write burst enable + CBURSTRW: u1, + /// Continuous clock enable + CCLKEN: u1, + /// Write FIFO disable + WFDIS: u1, + /// Byte lane (NBL) setup + NBLSET: u2, + reserved31: u7, + /// FMC controller enable + FMCEN: u1, + }), + /// SRAM/NOR-Flash chip-select timing register 1-4 + BTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + /// Clock divide ratio (for FMC_CLK signal) + CLKDIV: u4, + /// Data latency for synchronous memory + DATLAT: u4, + /// Access mode + ACCMOD: packed union { raw: u2, - value: MDMA, + value: ACCMOD, }, - /// ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). - CKMODE: packed union { + /// Data hold phase duration + DATAHLD: u2, + }), + /// SRAM/NOR-Flash chip-select control register 2-4 + BCR: mmio.Mmio(packed struct(u32) { + /// Memory bank enable bit + MBKEN: u1, + /// Address/data multiplexing enable bit + MUXEN: u1, + /// Memory type + MTYP: packed union { raw: u2, - value: CKMODE, + value: MTYP, }, - /// ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00. - PRESC: packed union { - raw: u4, - value: PRESC, + /// Memory data bus width + MWID: packed union { + raw: u2, + value: MWID, }, - /// VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel - VREFEN: u1, - /// VSENSE enable This bit is set and cleared by software to control VSENSE - TSEN: u1, - /// VBAT enable This bit is set and cleared by software to control - VBATEN: u1, - padding: u7, + /// Flash access enable + FACCEN: u1, + reserved8: u1, + /// Burst enable bit + BURSTEN: u1, + /// Wait signal polarity bit + WAITPOL: packed union { + raw: u1, + value: WAITPOL, + }, + reserved11: u1, + /// Wait timing configuration + WAITCFG: packed union { + raw: u1, + value: WAITCFG, + }, + /// Write enable bit + WREN: u1, + /// Wait enable bit + WAITEN: u1, + /// Extended mode enable + EXTMOD: u1, + /// Wait signal during asynchronous transfers + ASYNCWAIT: u1, + /// CRAM page size + CPSIZE: packed union { + raw: u3, + value: CPSIZE, + }, + /// Write burst enable + CBURSTRW: u1, + reserved22: u2, + /// Byte lane (NBL) setup + NBLSET: u2, + padding: u8, }), - /// common regular data register for dual mode - CDR: mmio.Mmio(packed struct(u32) { - /// Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)) In MDMA = 0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0]. - RDATA_MST: u16, - /// Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)). - RDATA_SLV: u16, + reserved32: [20]u8, + /// PSRAM chip select counter register + PCSCNTR: mmio.Mmio(packed struct(u32) { + /// Chip select counter + CSCOUNT: u16, + /// Counter Bank 1 enable + CNTB1EN: u1, + /// Counter Bank 2 enable + CNTB2EN: u1, + /// Counter Bank 3 enable + CNTB3EN: u1, + /// Counter Bank 4 enable + CNTB4EN: u1, + padding: u12, }), - reserved240: [224]u8, - /// hardware configuration register - HWCFGR0: mmio.Mmio(packed struct(u32) { - /// Number of ADCs implemented - ADCNUM: u4, - /// Number of pipeline stages - MULPIPE: u4, - /// Number of option bits 0002: 2 option bits implemented in the ADC option register (ADC_OR) at address offset 0xC8. - OPBITS: u4, - /// Idle value for non-selected channels - IDLEVALUE: packed union { - raw: u4, - value: IDLEVALUE, + reserved128: [92]u8, + /// PC Card/NAND Flash control register + PCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Wait feature enable bit + PWAITEN: u1, + /// NAND Flash memory bank enable bit + PBKEN: u1, + /// Memory type + PTYP: packed union { + raw: u1, + value: PTYP, }, - padding: u16, - }), - /// version register - VERR: mmio.Mmio(packed struct(u32) { - /// Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2. - MINREV: u4, - /// Major revision These bits returns the ADC IP major revision - MAJREV: u4, - padding: u24, + /// Data bus width + PWID: packed union { + raw: u2, + value: PWID, + }, + /// ECC computation logic enable bit + ECCEN: u1, + reserved9: u2, + /// CLE to RE delay + TCLR: u4, + /// ALE to RE delay + TAR: u4, + /// ECC page size + ECCPS: packed union { + raw: u3, + value: ECCPS, + }, + padding: u12, + }), + /// FIFO status and interrupt register + SR: mmio.Mmio(packed struct(u32) { + /// Interrupt rising edge status + IRS: u1, + /// Interrupt high-level status + ILS: u1, + /// Interrupt falling edge status + IFS: u1, + /// Interrupt rising edge detection enable bit + IREN: u1, + /// Interrupt high-level detection enable bit + ILEN: u1, + /// Interrupt falling edge detection enable bit + IFEN: u1, + /// FIFO empty status + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register + PMEM: mmio.Mmio(packed struct(u32) { + /// Common memory x setup time + MEMSET: u8, + /// Common memory wait time + MEMWAIT: u8, + /// Common memory hold time + MEMHOLD: u8, + /// Common memory x data bus Hi-Z time + MEMHIZ: u8, + }), + /// Attribute memory space timing register + PATT: mmio.Mmio(packed struct(u32) { + /// Attribute memory setup time + ATTSET: u8, + /// Attribute memory wait time + ATTWAIT: u8, + /// Attribute memory hold time + ATTHOLD: u8, + /// Attribute memory data bus Hi-Z time + ATTHIZ: u8, + }), + reserved148: [4]u8, + /// ECC result register + ECCR: mmio.Mmio(packed struct(u32) { + /// ECC computation result value + ECC: u32, + }), + reserved260: [108]u8, + /// SRAM/NOR-Flash write timing registers 1-4 + BWTR: mmio.Mmio(packed struct(u32) { + /// Address setup phase duration + ADDSET: u4, + /// Address-hold phase duration + ADDHLD: u4, + /// Data-phase duration + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + reserved28: u8, + /// Access mode + ACCMOD: packed union { + raw: u2, + value: ACCMOD, + }, + /// Data hold phase duration + DATAHLD: u2, }), - /// identification register - IPDR: u32, - /// size identification register - SIDR: u32, - }; - }; - - pub const rcc_l4 = struct { - pub const ADCSEL = enum(u2) { - /// No clock selected - DISABLE = 0x0, - /// PLLADC1CLK clock selected - PLL1_Q = 0x1, - /// SYSCLK clock selected - SYS = 0x3, - _, - }; - - pub const CLK48SEL = enum(u2) { - /// HSI48 clock selected (only for STM32L41x/L42x/L43x/L44x/L45x/L46x/L49x/L4Ax devices, otherwise no clock selected) - HSI48 = 0x0, - /// PLLSAI1_Q aka PLL48M1CLK clock selected - PLLSAI1_Q = 0x1, - /// PLL_Q aka PLL48M2CLK clock selected - PLL1_Q = 0x2, - /// MSI clock selected - MSI = 0x3, - }; - - pub const DFSDMSEL = enum(u1) { - /// APB2 clock (PCLK2) selected as DFSDM kernel clock - PCLK2 = 0x0, - /// System clock selected as DFSDM kernel clock - SYS = 0x1, - }; - - pub const HPRE = enum(u4) { - /// system clock not divided - Div1 = 0x0, - /// system clock divided by 2 - Div2 = 0x8, - /// system clock divided by 4 - Div4 = 0x9, - /// system clock divided by 8 - Div8 = 0xa, - /// system clock divided by 16 - Div16 = 0xb, - /// system clock divided by 64 - Div64 = 0xc, - /// system clock divided by 128 - Div128 = 0xd, - /// system clock divided by 256 - Div256 = 0xe, - /// system clock divided by 512 - Div512 = 0xf, - _, - }; - - pub const I2C1SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - _, - }; - - pub const I2C2SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - _, - }; - - pub const I2C3SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - _, - }; - - pub const LPTIM1SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// LSI clock selected - LSI = 0x1, - /// HSI clock selected - HSI = 0x2, - /// LSE clock selected - LSE = 0x3, - }; - - pub const LPTIM2SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// LSI clock selected - LSI = 0x1, - /// HSI clock selected - HSI = 0x2, - /// LSE clock selected - LSE = 0x3, }; + }; - pub const LPUART1SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - /// LSE clock selected - LSE = 0x3, + pub const gfxmmu_v1 = struct { + pub const BM192 = enum(u1) { + /// 256 blocks per line. + @"256BlocksPerLine" = 0x0, + /// 192 blocks per line. + @"192BlocksPerLine" = 0x1, }; - pub const LSCOSEL = enum(u1) { - /// LSI clock selected - LSI = 0x0, - /// LSE clock selected - LSE = 0x1, + /// GFXMMU. + pub const GFXMMU = extern struct { + /// GFXMMU configuration register. + CR: mmio.Mmio(packed struct(u32) { + /// Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. + BOIE: u1, + reserved4: u3, + /// AHB master error interrupt enable. This bit enables the AHB master error interrupt. + AMEIE: u1, + reserved6: u1, + /// 192 Block mode. This bit defines the number of blocks per line. + BM: packed union { + raw: u1, + value: BM192, + }, + padding: u25, + }), + /// GFXMMU status register. + SR: mmio.Mmio(packed struct(u32) { + /// Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + BOF: u1, + reserved4: u3, + /// AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF. + AMEF: u1, + padding: u27, + }), + /// GFXMMU flag clear register. + FCR: mmio.Mmio(packed struct(u32) { + /// Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + CBOF: u1, + reserved4: u3, + /// Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register. + CAMEF: u1, + padding: u27, + }), + reserved16: [4]u8, + /// GFXMMU default value register. + DVR: mmio.Mmio(packed struct(u32) { + /// Default value. This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped. + DV: u32, + }), + reserved32: [12]u8, + /// GFXMMU buffer 0 configuration register. + BCR: [4]mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Physical buffer offset. Offset of the physical buffer. + PBO: u19, + /// Physical buffer base address. Base address MSB of the physical buffer. + PBBA: u9, + }), + reserved4096: [4048]u8, + /// GFXMMU LUT entry 0 low. + LUTL: mmio.Mmio(packed struct(u32) { + /// Line enable. + EN: u1, + reserved8: u7, + /// First Valid Block. Number of the first valid block of line number x. + FVB: u8, + /// Last Valid Block. Number of the last valid block of line number X. + LVB: u8, + padding: u8, + }), + /// GFXMMU LUT entry 0 high. + LUTH: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Line offset. Line offset of line number x (i.e. offset of block 0 of line x). + LO: u18, + padding: u10, + }), }; + }; - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, + pub const gfxmmu_v2 = struct { + pub const BM192 = enum(u1) { + /// 256 blocks per line. + @"256BlocksPerLine" = 0x0, + /// 192 blocks per line. + @"192BlocksPerLine" = 0x1, }; - pub const MCOPRE = enum(u3) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x1, - /// Division by 4 - Div4 = 0x2, - /// Division by 8 - Div8 = 0x3, - /// Division by 16 - Div16 = 0x4, - _, + pub const CLB = enum(u2) { + /// Cache locked on buffer 0. + LockedOnBuffer0 = 0x0, + /// Cache locked on buffer 1. + LockedOnBuffer1 = 0x1, + /// Cache locked on buffer 2. + LockedOnBuffer2 = 0x2, + /// Cache locked on buffer 3. + LockedOnBuffer3 = 0x3, }; - pub const MCOSEL = enum(u4) { - /// No clock - DISABLE = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// MSI oscillator clock selected - MSI = 0x2, - /// HSI oscillator clock selected - HSI = 0x3, - /// HSE oscillator clock selected - HSE = 0x4, - /// PLL clock selected - PLL = 0x5, - /// LSI oscillator clock selected - LSI = 0x6, - /// LSE oscillator clock selected - LSE = 0x7, - /// HSI48 oscillator clock selected - HSI48 = 0x8, - _, + /// GFXMMU. + pub const GFXMMU = extern struct { + /// GFXMMU configuration register. + CR: mmio.Mmio(packed struct(u32) { + /// Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. + BOIE: u1, + reserved4: u3, + /// AHB master error interrupt enable. This bit enables the AHB master error interrupt. + AMEIE: u1, + reserved6: u1, + /// 192 Block mode. This bit defines the number of blocks per line. + BM: packed union { + raw: u1, + value: BM192, + }, + /// Cache enable. This bit enables the cache unit. + CE: u1, + /// Cache lock. This bit lock the cache onto the buffer defined in the CLB field. + CL: u1, + /// Cache lock buffer. This field select the buffer on which the cache is locked. + CLB: packed union { + raw: u2, + value: CLB, + }, + /// Force caching. This bit force the caching into the cache regardless of the MPU attributes. The cache must be enable (CE bit set). + FC: u1, + /// Prefetch disable. This bit disables the prefetch of the cache. + PD: u1, + reserved16: u3, + /// Outter cachability. This bit configure the cachability of an access generated by the GFXMMU cache. + OC: u1, + /// Outter bufferability. This bit configure the bufferability of an access generated by the GFXMMU cache. + OB: u1, + padding: u14, + }), + /// GFXMMU status register. + SR: mmio.Mmio(packed struct(u32) { + /// Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + BOF: u1, + reserved4: u3, + /// AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF. + AMEF: u1, + padding: u27, + }), + /// GFXMMU flag clear register. + FCR: mmio.Mmio(packed struct(u32) { + /// Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + CBOF: u1, + reserved4: u3, + /// Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register. + CAMEF: u1, + padding: u27, + }), + /// GFXMMU cache control register. + CCR: mmio.Mmio(packed struct(u32) { + /// Force flush. When set, the cache entries are flushed. This bit is reset by hardware when the flushing is complete. Write 0 has no effect. + FF: u1, + /// Force invalidate. When set, the cache entries are invalidated. This bit is reset by hardware when the invalidation is complete. Write 0 has no effect. + FI: u1, + padding: u30, + }), + /// GFXMMU default value register. + DVR: mmio.Mmio(packed struct(u32) { + /// Default value. This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped. + DV: u32, + }), + reserved32: [12]u8, + /// GFXMMU buffer 0 configuration register. + BCR: [4]mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Physical buffer offset. Offset of the physical buffer. + PBO: u19, + /// Physical buffer base address. Base address MSB of the physical buffer. + PBBA: u9, + }), + reserved4096: [4048]u8, + /// GFXMMU LUT entry 0 low. + LUTL: mmio.Mmio(packed struct(u32) { + /// Line enable. + EN: u1, + reserved8: u7, + /// First Valid Block. Number of the first valid block of line number x. + FVB: u8, + /// Last Valid Block. Number of the last valid block of line number X. + LVB: u8, + padding: u8, + }), + /// GFXMMU LUT entry 0 high. + LUTH: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Line offset. Line offset of line number x (i.e. offset of block 0 of line x). + LO: u18, + padding: u10, + }), }; + }; - pub const MSIRANGE = enum(u4) { - /// range 0 around 100 kHz - Range100K = 0x0, - /// range 1 around 200 kHz - Range200K = 0x1, - /// range 2 around 400 kHz - Range400K = 0x2, - /// range 3 around 800 kHz - Range800K = 0x3, - /// range 4 around 1 MHz - Range1M = 0x4, - /// range 5 around 2 MHz - Range2M = 0x5, - /// range 6 around 4 MHz - Range4M = 0x6, - /// range 7 around 8 MHz - Range8M = 0x7, - /// range 8 around 16 MHz - Range16M = 0x8, - /// range 9 around 24 MHz - Range24M = 0x9, - /// range 10 around 32 MHz - Range32M = 0xa, - /// range 11 around 48 MHz - Range48M = 0xb, - _, + pub const gpdma_v1 = struct { + pub const AP = enum(u1) { + /// port 0 (AHB) allocated + Port0 = 0x0, + /// port 1 (AHB) allocated + Port1 = 0x1, }; - pub const MSIRGSEL = enum(u1) { - /// MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register - CSR = 0x0, - /// MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register - CR = 0x1, + pub const BREQ = enum(u1) { + /// the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + Burst = 0x0, + /// the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ). + Block = 0x1, }; - pub const PLLM = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, + pub const DEC = enum(u1) { + /// The address is incremented by the programmed offset. + Add = 0x0, + /// The address is decremented by the programmed offset. + Subtract = 0x1, }; - pub const PLLN = enum(u7) { - Mul8 = 0x8, - Mul9 = 0x9, - Mul10 = 0xa, - Mul11 = 0xb, - Mul12 = 0xc, - Mul13 = 0xd, - Mul14 = 0xe, - Mul15 = 0xf, - Mul16 = 0x10, - Mul17 = 0x11, - Mul18 = 0x12, - Mul19 = 0x13, - Mul20 = 0x14, - Mul21 = 0x15, - Mul22 = 0x16, - Mul23 = 0x17, - Mul24 = 0x18, - Mul25 = 0x19, - Mul26 = 0x1a, - Mul27 = 0x1b, - Mul28 = 0x1c, - Mul29 = 0x1d, - Mul30 = 0x1e, - Mul31 = 0x1f, - Mul32 = 0x20, - Mul33 = 0x21, - Mul34 = 0x22, - Mul35 = 0x23, - Mul36 = 0x24, - Mul37 = 0x25, - Mul38 = 0x26, - Mul39 = 0x27, - Mul40 = 0x28, - Mul41 = 0x29, - Mul42 = 0x2a, - Mul43 = 0x2b, - Mul44 = 0x2c, - Mul45 = 0x2d, - Mul46 = 0x2e, - Mul47 = 0x2f, - Mul48 = 0x30, - Mul49 = 0x31, - Mul50 = 0x32, - Mul51 = 0x33, - Mul52 = 0x34, - Mul53 = 0x35, - Mul54 = 0x36, - Mul55 = 0x37, - Mul56 = 0x38, - Mul57 = 0x39, - Mul58 = 0x3a, - Mul59 = 0x3b, - Mul60 = 0x3c, - Mul61 = 0x3d, - Mul62 = 0x3e, - Mul63 = 0x3f, - Mul64 = 0x40, - Mul65 = 0x41, - Mul66 = 0x42, - Mul67 = 0x43, - Mul68 = 0x44, - Mul69 = 0x45, - Mul70 = 0x46, - Mul71 = 0x47, - Mul72 = 0x48, - Mul73 = 0x49, - Mul74 = 0x4a, - Mul75 = 0x4b, - Mul76 = 0x4c, - Mul77 = 0x4d, - Mul78 = 0x4e, - Mul79 = 0x4f, - Mul80 = 0x50, - Mul81 = 0x51, - Mul82 = 0x52, - Mul83 = 0x53, - Mul84 = 0x54, - Mul85 = 0x55, - Mul86 = 0x56, - Mul87 = 0x57, - Mul88 = 0x58, - Mul89 = 0x59, - Mul90 = 0x5a, - Mul91 = 0x5b, - Mul92 = 0x5c, - Mul93 = 0x5d, - Mul94 = 0x5e, - Mul95 = 0x5f, - Mul96 = 0x60, - Mul97 = 0x61, - Mul98 = 0x62, - Mul99 = 0x63, - Mul100 = 0x64, - Mul101 = 0x65, - Mul102 = 0x66, - Mul103 = 0x67, - Mul104 = 0x68, - Mul105 = 0x69, - Mul106 = 0x6a, - Mul107 = 0x6b, - Mul108 = 0x6c, - Mul109 = 0x6d, - Mul110 = 0x6e, - Mul111 = 0x6f, - Mul112 = 0x70, - Mul113 = 0x71, - Mul114 = 0x72, - Mul115 = 0x73, - Mul116 = 0x74, - Mul117 = 0x75, - Mul118 = 0x76, - Mul119 = 0x77, - Mul120 = 0x78, - Mul121 = 0x79, - Mul122 = 0x7a, - Mul123 = 0x7b, - Mul124 = 0x7c, - Mul125 = 0x7d, - Mul126 = 0x7e, - Mul127 = 0x7f, - _, + pub const DREQ = enum(u1) { + /// selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + SourcePeripheral = 0x0, + /// selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + DestinationPeripheral = 0x1, }; - pub const PLLP = enum(u5) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - Div16 = 0x10, - Div17 = 0x11, - Div18 = 0x12, - Div19 = 0x13, - Div20 = 0x14, - Div21 = 0x15, - Div22 = 0x16, - Div23 = 0x17, - Div24 = 0x18, - Div25 = 0x19, - Div26 = 0x1a, - Div27 = 0x1b, - Div28 = 0x1c, - Div29 = 0x1d, - Div30 = 0x1e, - Div31 = 0x1f, + pub const DW = enum(u2) { + /// byte + Byte = 0x0, + /// half-word (2 bytes) + HalfWord = 0x1, + /// word (4 bytes) + Word = 0x2, _, }; - pub const PLLPBIT = enum(u1) { - Div7 = 0x0, - Div17 = 0x1, - }; - - pub const PLLQ = enum(u2) { - Div2 = 0x0, - Div4 = 0x1, - Div6 = 0x2, - Div8 = 0x3, - }; - - pub const PLLR = enum(u2) { - Div2 = 0x0, - Div4 = 0x1, - Div6 = 0x2, - Div8 = 0x3, - }; - - pub const PLLSRC = enum(u2) { - /// No clock sent to PLL - DISABLE = 0x0, - /// MSI selected as PLL input clock - MSI = 0x1, - /// HSI selected as PLL input clock - HSI = 0x2, - /// HSE selected as PLL input clock - HSE = 0x3, + pub const LSM = enum(u1) { + /// channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. + RunToCompletion = 0x0, + /// channel executed once for the current LLI + LinkStep = 0x1, }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, + pub const PAM = enum(u2) { + /// If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width If source is wider: source data is transferred as right aligned, left-truncated down to the destination data width + ZeroExtendOrLeftTruncate = 0x0, + /// If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width If source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width + SignExtendOrRightTruncate = 0x1, + /// source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination + Pack = 0x2, _, }; - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by 32 used as the RTC clock - HSE = 0x3, - }; - - pub const SAI1SEL = enum(u2) { - /// PLLSAI1CLK clock is selected as SAIx clock - PLLSAI1_P = 0x0, - /// PLLSAI2CLK clock is selected as SAIx clock - PLLSAI2_P = 0x1, - /// PLLSAI3CLK clock is selected as SAIx clock - PLL1_P = 0x2, - /// External clock SAIx_EXTCLK clock selected as SAIx clock - SAI1_EXTCLK = 0x3, - }; - - pub const SAI2SEL = enum(u2) { - /// PLLSAI1CLK clock is selected as SAIx clock - PLLSAI1_P = 0x0, - /// PLLSAI2CLK clock is selected as SAIx clock - PLLSAI2_P = 0x1, - /// PLLSAI3CLK clock is selected as SAIx clock - PLL1_P = 0x2, - /// External clock SAIx_EXTCLK clock selected as SAIx clock - SAI2_EXTCLK = 0x3, - }; - - pub const STOPWUCK = enum(u1) { - /// MSI oscillator selected as wake-up from Stop clock - MSI = 0x0, - /// HSI oscillator selected as wake-up from Stop clock - HSI = 0x1, + pub const PRIO = enum(u2) { + /// low priority, low weight + LowWithLowhWeight = 0x0, + /// low priority, mid weight + LowWithMidWeight = 0x1, + /// low priority, high weight + LowWithHighWeight = 0x2, + /// high priority + High = 0x3, }; - pub const SW = enum(u2) { - /// MSI selected as system clock - MSI = 0x0, - /// HSI selected as system clock - HSI = 0x1, - /// HSE selected as system clock - HSE = 0x2, - /// PLL selected as system clock - PLL1_R = 0x3, + pub const SWREQ = enum(u1) { + /// no software request. The selected hardware request REQSEL[6:0] is taken into account. + Hardware = 0x0, + /// software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored. + Software = 0x1, }; - pub const SWPMI1SEL = enum(u1) { - PCLK1 = 0x0, - HSI = 0x1, + pub const TCEM = enum(u2) { + /// at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. + EachBlock = 0x0, + /// channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block. + Each2DBlock = 0x1, + /// at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer. + EachLinkedListItem = 0x2, + /// at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated. + LastLinkedListItem = 0x3, }; - pub const USART1SEL = enum(u2) { - /// PCLK clock selected - PCLK2 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - /// LSE clock selected - LSE = 0x3, + pub const TRIGM = enum(u2) { + /// at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0). + Block = 0x0, + /// channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the + @"2DBlock" = 0x1, + /// at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned. + LinkedListItem = 0x2, + /// at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger. + Burst = 0x3, }; - pub const USARTSEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - /// LSE clock selected - LSE = 0x3, + pub const TRIGPOL = enum(u2) { + /// no trigger (masked trigger event) + None = 0x0, + /// trigger on the rising edge + RisingEdge = 0x1, + /// trigger on the falling edge + FallingEdge = 0x2, + /// same as 00 + NoneAlt = 0x3, }; - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register + pub const Channel = extern struct { + /// GPDMA channel 15 linked-list base address register + LBAR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// linked-list base address of GPDMA channel x + LBA: u16, + }), + reserved12: [8]u8, + /// GPDMA channel 15 flag clear register + FCR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// transfer complete flag clear + TCF: u1, + /// half transfer flag clear + HTF: u1, + /// data transfer error flag clear + DTEF: u1, + /// update link transfer error flag clear + ULEF: u1, + /// user setting error flag clear + USEF: u1, + /// completed suspension flag clear + SUSPF: u1, + /// trigger overrun flag clear + TOF: u1, + padding: u17, + }), + /// GPDMA channel 15 status register + SR: mmio.Mmio(packed struct(u32) { + /// idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state). + IDLEF: u1, + reserved8: u7, + /// transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). + TCF: u1, + /// half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination. + HTF: u1, + /// data transfer error flag + DTEF: u1, + /// update link transfer error flag + ULEF: u1, + /// user setting error flag + USEF: u1, + /// completed suspension flag + SUSPF: u1, + /// trigger overrun flag + TOF: u1, + reserved16: u1, + /// monitored FIFO level. Number of available write beats in the FIFO, in units of the programmed destination data width (see CH[x].TR1.DDW[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to CH[x].BR1.BDNT[15:0] and CH[x].BR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (CH[x].SR.SUSPF = 1). + FIFOL: u8, + padding: u8, + }), + /// GPDMA channel 15 control register CR: mmio.Mmio(packed struct(u32) { - /// MSI clock enable - MSION: u1, - /// MSI clock ready flag - MSIRDY: u1, - /// MSI clock PLL enable - MSIPLLEN: u1, - /// MSI clock range selection - MSIRGSEL: packed union { + /// enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + EN: u1, + /// reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in ). + RESET: u1, + /// suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in . + SUSP: u1, + reserved8: u5, + /// transfer complete interrupt enable + TCIE: u1, + /// half transfer complete interrupt enable + HTIE: u1, + /// data transfer error interrupt enable + DTEIE: u1, + /// update link transfer error interrupt enable + ULEIE: u1, + /// user setting error interrupt enable + USEIE: u1, + /// completed suspension interrupt enable + SUSPIE: u1, + /// trigger overrun interrupt enable + TOIE: u1, + reserved16: u1, + /// Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1. + LSM: packed union { raw: u1, - value: MSIRGSEL, + value: LSM, }, - /// MSI clock ranges - MSIRANGE: packed union { - raw: u4, - value: MSIRANGE, + /// linked-list allocated port. This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1. + LAP: packed union { + raw: u1, + value: AP, }, - /// HSI clock enable - HSION: u1, - /// HSI always enable for peripheral kernels - HSIKERON: u1, - /// HSI clock ready flag - HSIRDY: u1, - /// HSI automatic start from Stop - HSIASFS: u1, - reserved16: u4, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE crystal oscillator bypass - HSEBYP: u1, - /// Clock security system enable - CSSON: u1, - reserved24: u4, - /// Main PLL enable - PLLON: u1, - /// Main PLL clock ready flag - PLLRDY: u1, - /// SAI1 PLL enable - PLLSAI1ON: u1, - /// SAI1 PLL clock ready flag - PLLSAI1RDY: u1, - /// SAI2 PLL enable - PLLSAI2ON: u1, - /// SAI2 PLL clock ready flag - PLLSAI2RDY: u1, - padding: u2, - }), - /// Internal clock sources calibration register - ICSCR: mmio.Mmio(packed struct(u32) { - /// MSI clock calibration - MSICAL: u8, - /// MSI clock trimming - MSITRIM: u8, - /// HSI clock calibration - HSICAL: u8, - /// HSI clock trimming - HSITRIM: u7, - padding: u1, + reserved22: u4, + /// priority level of the channel x GPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. + PRIO: packed union { + raw: u2, + value: PRIO, + }, + padding: u8, }), - /// Clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { + reserved64: [40]u8, + /// GPDMA channel 15 transfer register 1 + TR1: mmio.Mmio(packed struct(u32) { + /// binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued. + SDW: packed union { raw: u2, - value: SW, + value: DW, }, - /// System clock switch status - SWS: packed union { + reserved3: u1, + /// source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + SINC: u1, + /// source burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed. + SBL_1: u6, + reserved11: u1, + /// padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note: + PAM: packed union { raw: u2, - value: SW, + value: PAM, }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, + /// source byte exchange within the unaligned half-word of each source word. If set, the two consecutive bytes within the unaligned half-word of each source word are exchanged. If the source data width is shorter than a word, this bit is ignored. + SBX: u1, + /// source allocated port. This bit is used to allocate the master port for the source transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. + SAP: packed union { + raw: u1, + value: AP, }, - /// APB low-speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, + /// security attribute of the GPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure. + SSEC: u1, + /// binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued. + DDW: packed union { + raw: u2, + value: DW, }, - /// APB high-speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, + reserved19: u1, + /// destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + DINC: u1, + /// destination burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed. + DBL_1: u6, + /// destination byte exchange. IF set, the two consecutive (post PAM) bytes are exchanged in each destination half-word. If the destination data size is a byte, this bit is ignored. + DBX: u1, + /// destination half-word exchange. If set, e two consecutive (post PAM) half-words are exchanged in each destination word. If the destination data size is shorter than a word, this bit is ignored. + DHX: u1, + reserved30: u2, + /// destination allocated port. This bit is used to allocate the master port for the destination transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. + DAP: packed union { + raw: u1, + value: AP, }, - reserved15: u1, - /// Wakeup from Stop and CSS backup clock selection - STOPWUCK: packed union { + /// security attribute of the GPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure. + DSEC: u1, + }), + /// GPDMA channel 15 transfer register 2 + TR2: mmio.Mmio(packed struct(u32) { + /// GPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. + REQSEL: u7, + reserved9: u2, + /// software request. This bit is internally taken into account when CH[x].CR.EN is asserted. + SWREQ: packed union { raw: u1, - value: STOPWUCK, + value: SWREQ, }, - reserved24: u8, - /// Microcontroller clock output selection - MCOSEL: packed union { - raw: u4, - value: MCOSEL, + /// destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note: + DREQ: packed union { + raw: u1, + value: DREQ, }, - /// Microcontroller clock output prescaler - MCOPRE: packed union { - raw: u3, - value: MCOPRE, - }, - padding: u1, - }), - /// PLL configuration register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// Main PLL, PLLSAI1 and PLLSAI2 entry clock source - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - reserved4: u2, - /// Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock - PLLM: packed union { - raw: u3, - value: PLLM, - }, - reserved8: u1, - /// Main PLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, - }, - reserved16: u1, - /// Main PLL PLLSAI3CLK output enable - PLLPEN: u1, - /// Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) - PLLPBIT: packed union { + /// Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: + BREQ: packed union { raw: u1, - value: PLLPBIT, + value: BREQ, }, - reserved20: u2, - /// Main PLL PLLUSB1CLK output enable - PLLQEN: u1, - /// Main PLL division factor for PLLUSB1CLK(48 MHz clock) - PLLQ: packed union { + reserved14: u2, + /// trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger. + TRIGM: packed union { raw: u2, - value: PLLQ, + value: TRIGM, }, - reserved24: u1, - /// Main PLL PLLCLK output enable - PLLREN: u1, - /// Main PLL division factor for PLLCLK (system clock) - PLLR: packed union { + /// trigger event input selection. These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00. + TRIGSEL: u6, + reserved24: u2, + /// trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]. + TRIGPOL: packed union { raw: u2, - value: PLLR, + value: TRIGPOL, }, - /// Main PLL division factor for PLLSAI2CLK - PLLP: packed union { - raw: u5, - value: PLLP, + reserved30: u4, + /// transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. + TCEM: packed union { + raw: u2, + value: TCEM, }, }), - /// PLLSAI1 configuration register - PLLSAI1CFGR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// SAI1PLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, + /// GPDMA channel 15 alternate block register 1 + BR1: mmio.Mmio(packed struct(u32) { + /// block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued. + BNDT: u16, + /// Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer. + BRC: u11, + reserved28: u1, + /// source address decrement + SDEC: packed union { + raw: u1, + value: DEC, }, - reserved16: u1, - /// SAI1PLL PLLSAICLK output enable - PLLPEN: u1, - /// SAI1PLL division factor for PLLSAICLK - PLLPBIT: packed union { + /// destination address decrement + DDEC: packed union { raw: u1, - value: PLLPBIT, + value: DEC, }, - reserved20: u2, - /// SAI1PLL PLLUSB2CLK output enable - PLLQEN: u1, - /// SAI1PLL division factor for PLLUSB2CLK - PLLQ: packed union { + /// Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer. + BRSDEC: packed union { + raw: u1, + value: DEC, + }, + /// Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer. + BRDDEC: packed union { + raw: u1, + value: DEC, + }, + }), + /// GPDMA channel 15 source address register + SAR: u32, + /// GPDMA channel 15 destination address register + DAR: u32, + /// GPDMA channel 15 transfer register 3 + TR3: mmio.Mmio(packed struct(u32) { + /// source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied. + SAO: u13, + reserved16: u3, + /// destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued. + DAO: u13, + padding: u3, + }), + /// GPDMA channel 15 block register 2 + BR2: mmio.Mmio(packed struct(u32) { + /// Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. + BRSAO: u16, + /// Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued. + BRDAO: u16, + }), + reserved124: [32]u8, + /// GPDMA channel 15 alternate linked-list address register + LLR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. + LA: u14, + /// Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer. + ULL: u1, + reserved25: u8, + /// Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer. + UB2: u1, + /// Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer. + UT3: u1, + /// Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer. + UDA: u1, + /// update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer. + USA: u1, + /// Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. + UB1: u1, + /// Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer. + UT2: u1, + /// Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer. + UT1: u1, + }), + }; + + /// GPDMA + pub const GPDMA = extern struct { + /// GPDMA secure configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// SEC0 + SEC: u1, + padding: u31, + }), + /// GPDMA privileged configuration register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// PRIV0 + PRIV: u1, + padding: u31, + }), + /// GPDMA configuration lock register + RCFGLOCKR: mmio.Mmio(packed struct(u32) { + /// LOCK0 + LOCK: u1, + padding: u31, + }), + /// GPDMA non-secure masked interrupt status register + MISR: mmio.Mmio(packed struct(u32) { + /// MIS0 + MIS: u1, + padding: u31, + }), + /// GPDMA secure masked interrupt status register + SMISR: mmio.Mmio(packed struct(u32) { + /// MIS0 + MIS: u1, + padding: u31, + }), + reserved80: [60]u8, + CH: u32, + }; + }; + + pub const gpio_v1 = struct { + pub const CNF_IN = enum(u2) { + /// Analog mode + Analog = 0x0, + /// Floating input (reset state) + Floating = 0x1, + /// Input with pull-up/pull-down + Pull = 0x2, + _, + }; + + pub const CNF_OUT = enum(u2) { + /// Push-Pull mode + PushPull = 0x0, + /// Open Drain-Mode + OpenDrain = 0x1, + /// Alternate Function Push-Pull Mode + AltPushPull = 0x2, + /// Alternate Function Open-Drain Mode + AltOpenDrain = 0x3, + }; + + pub const IDR = enum(u1) { + /// Input is logic low + Low = 0x0, + /// Input is logic high + High = 0x1, + }; + + pub const MODE = enum(u2) { + /// Input mode (reset state) + Input = 0x0, + /// Output mode 10 MHz + Output10Mhz = 0x1, + /// Output mode 2 MHz + Output2Mhz = 0x2, + /// Output mode 50 MHz + Output50Mhz = 0x3, + }; + + pub const ODR = enum(u1) { + /// Set output to logic low + Low = 0x0, + /// Set output to logic high + High = 0x1, + }; + + /// General purpose I/O + pub const GPIO = extern struct { + /// Port configuration register low (GPIOn_CRL) + CR: [2]mmio.Mmio(packed struct(u32) { + /// Port n mode bits + MODE: packed union { raw: u2, - value: PLLQ, + value: MODE, }, - reserved24: u1, - /// PLLSAI PLLADC1CLK output enable - PLLREN: u1, - /// PLLSAI division factor for PLLADC1CLK - PLLR: packed union { + /// Port n configuration bits, for input mode + CNF_IN: packed union { raw: u2, - value: PLLR, + value: CNF_IN, }, - /// PLLSAI division factor for PLLSAICLK - PLLP: packed union { - raw: u5, - value: PLLP, + padding: u28, + }), + /// Port input data register (GPIOn_IDR) + IDR: mmio.Mmio(packed struct(u32) { + /// Port input data + IDR: packed union { + raw: u1, + value: IDR, }, + padding: u31, }), - /// PLLSAI2 configuration register - PLLSAI2CFGR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// SAI1PLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, + /// Port output data register (GPIOn_ODR) + ODR: mmio.Mmio(packed struct(u32) { + /// Port output data + ODR: packed union { + raw: u1, + value: ODR, }, - reserved16: u1, - /// SAI1PLL PLLSAICLK output enable - PLLPEN: u1, - /// SAI1PLL division factor for PLLSAICLK - PLLPBIT: packed union { + padding: u31, + }), + /// Port bit set/reset register (GPIOn_BSRR) + BSRR: mmio.Mmio(packed struct(u32) { + /// Set bit + BS: u1, + reserved16: u15, + /// Reset bit + BR: u1, + padding: u15, + }), + /// Port bit reset register (GPIOn_BRR) + BRR: mmio.Mmio(packed struct(u32) { + /// Reset bit + BR: u1, + padding: u31, + }), + /// Port configuration lock register + LCKR: mmio.Mmio(packed struct(u32) { + /// Port configuration locked + LCK: u1, + reserved16: u15, + /// Port configuration lock key active + LCKK: u1, + padding: u15, + }), + }; + }; + + pub const gpio_v2 = struct { + pub const IDR = enum(u1) { + /// Input is logic low + Low = 0x0, + /// Input is logic high + High = 0x1, + }; + + pub const MODER = enum(u2) { + /// Input mode (reset state) + Input = 0x0, + /// General purpose output mode + Output = 0x1, + /// Alternate function mode + Alternate = 0x2, + /// Analog mode + Analog = 0x3, + }; + + pub const ODR = enum(u1) { + /// Set output to logic low + Low = 0x0, + /// Set output to logic high + High = 0x1, + }; + + pub const OSPEEDR = enum(u2) { + /// Low speed + LowSpeed = 0x0, + /// Medium speed + MediumSpeed = 0x1, + /// High speed + HighSpeed = 0x2, + /// Very high speed + VeryHighSpeed = 0x3, + }; + + pub const OT = enum(u1) { + /// Output push-pull (reset state) + PushPull = 0x0, + /// Output open-drain + OpenDrain = 0x1, + }; + + pub const PUPDR = enum(u2) { + /// No pull-up, pull-down + Floating = 0x0, + /// Pull-up + PullUp = 0x1, + /// Pull-down + PullDown = 0x2, + _, + }; + + /// General-purpose I/Os + pub const GPIO = extern struct { + /// GPIO port mode register + MODER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + MODER: packed union { + raw: u2, + value: MODER, + }, + padding: u30, + }), + /// GPIO port output type register + OTYPER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OT: packed union { raw: u1, - value: PLLPBIT, + value: OT, }, - reserved20: u2, - /// SAI1PLL PLLUSB2CLK output enable - PLLQEN: u1, - /// SAI1PLL division factor for PLLUSB2CLK - PLLQ: packed union { + padding: u31, + }), + /// GPIO port output speed register + OSPEEDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OSPEEDR: packed union { raw: u2, - value: PLLQ, + value: OSPEEDR, }, - reserved24: u1, - /// PLLSAI PLLADC1CLK output enable - PLLREN: u1, - /// PLLSAI division factor for PLLADC1CLK - PLLR: packed union { + padding: u30, + }), + /// GPIO port pull-up/pull-down register + PUPDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + PUPDR: packed union { raw: u2, - value: PLLR, + value: PUPDR, }, - /// PLLSAI division factor for PLLSAICLK - PLLP: packed union { - raw: u5, - value: PLLP, + padding: u30, + }), + /// GPIO port input data register + IDR: mmio.Mmio(packed struct(u32) { + /// Port input data (y = 0..15) + IDR: packed union { + raw: u1, + value: IDR, }, + padding: u31, }), - /// Clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - /// MSI ready interrupt enable - MSIRDYIE: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// PLL ready interrupt enable - PLLRDYIE: u1, - /// PLLSAI1 ready interrupt enable - PLLSAI1RDYIE: u1, - /// PLLSAI2 ready interrupt enable - PLLSAI2RDYIE: u1, - reserved9: u1, - /// LSE clock security system interrupt enable - LSECSSIE: u1, - /// HSI48 ready interrupt enable - HSI48RDYIE: u1, - padding: u21, + /// GPIO port output data register + ODR: mmio.Mmio(packed struct(u32) { + /// Port output data (y = 0..15) + ODR: packed union { + raw: u1, + value: ODR, + }, + padding: u31, }), - /// Clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// MSI ready interrupt flag - MSIRDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// PLL ready interrupt flag - PLLRDYF: u1, - /// PLLSAI1 ready interrupt flag - PLLSAI1RDYF: u1, - /// PLLSAI2 ready interrupt flag - PLLSAI2RDYF: u1, - /// Clock security system interrupt flag - CSSF: u1, - /// LSE Clock security system interrupt flag - LSECSSF: u1, - /// HSI48 ready interrupt flag - HSI48RDYF: u1, - padding: u21, + /// GPIO port bit set/reset register + BSRR: mmio.Mmio(packed struct(u32) { + /// Port x set bit y (y= 0..15) + BS: u1, + reserved16: u15, + /// Port x set bit y (y= 0..15) + BR: u1, + padding: u15, }), - /// Clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// MSI ready interrupt clear - MSIRDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// PLL ready interrupt clear - PLLRDYC: u1, - /// PLLSAI1 ready interrupt clear - PLLSAI1RDYC: u1, - /// PLLSAI2 ready interrupt clear - PLLSAI2RDYC: u1, - /// Clock security system interrupt clear - CSSC: u1, - /// LSE Clock security system interrupt clear - LSECSSC: u1, - /// HSI48 oscillator ready interrupt clear - HSI48RDYC: u1, - padding: u21, + /// GPIO port configuration lock register + LCKR: mmio.Mmio(packed struct(u32) { + /// Port configuration locked + LCK: u1, + reserved16: u15, + /// Port configuration lock key active + LCKK: u1, + padding: u15, }), - reserved40: [4]u8, - /// AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - reserved8: u6, - /// Flash memory interface reset - FLASHRST: u1, - reserved12: u3, - /// CRC reset - CRCRST: u1, - reserved16: u3, - /// Touch Sensing Controller reset - TSCRST: u1, - /// DMA2D reset - DMA2DRST: u1, - padding: u14, + /// GPIO alternate function registers. The register described in the datasheet as AFRL is index 0 in this array, and AFRH is index 1. Note that when operating on AFRH, you need to subtract 8 from any operations on the field array it contains -- the alternate function for pin 9 is at index 1, for instance. + AFR: [2]mmio.Mmio(packed struct(u32) { + /// Alternate function selection for one of the pins controlled by this register (0-7). + AFR: u4, + padding: u28, }), - /// AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - /// IO port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// IO port H reset - GPIOHRST: u1, - /// IO port I reset - GPIOIRST: u1, - reserved12: u3, - /// USB OTG FS reset - USB_OTG_FSRST: u1, - /// ADC reset - ADCRST: u1, - /// Digital Camera Interface reset - DCMIRST: u1, - reserved16: u1, - /// AES hardware accelerator reset - AESRST: u1, - /// Hash reset - HASHRST: u1, - /// Random number generator reset - RNGRST: u1, - padding: u13, + }; + }; + + pub const hash_v1 = struct { + /// Hash processor. + pub const HASH = extern struct { + /// control register. + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Initialize message digest calculation. + INIT: u1, + /// DMA enable. + DMAE: u1, + /// Data type selection. + DATATYPE: u2, + /// Mode selection. + MODE: u1, + /// Algorithm selection. + ALGO: u1, + /// Number of words already pushed. + NBW: u4, + /// DIN not empty. + DINNE: u1, + reserved16: u3, + /// Long key selection. + LKEY: u1, + padding: u15, }), - /// AHB3 peripheral reset register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller reset - FMCRST: u1, - reserved8: u7, - /// Quad SPI memory interface reset - QUADSPIRST: u1, + /// data input register. + DIN: u32, + /// start register. + STR: mmio.Mmio(packed struct(u32) { + /// Number of valid bits in the last word of the message. + NBLW: u5, + reserved8: u3, + /// Digest calculation. + DCAL: u1, padding: u23, }), - reserved56: [4]u8, - /// APB1 peripheral reset register 1 - APB1RSTR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer reset - TIM2RST: u1, - /// TIM3 timer reset - TIM3RST: u1, - /// TIM3 timer reset - TIM4RST: u1, - /// TIM5 timer reset - TIM5RST: u1, - /// TIM6 timer reset - TIM6RST: u1, - /// TIM7 timer reset - TIM7RST: u1, - reserved9: u3, - /// LCD interface reset - LCDRST: u1, - reserved14: u4, - /// SPI2 reset - SPI2RST: u1, - /// SPI3 reset - SPI3RST: u1, - reserved17: u1, - /// USART2 reset - USART2RST: u1, - /// USART3 reset - USART3RST: u1, - /// UART4 reset - UART4RST: u1, - /// UART5 reset - UART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// I2C3 reset - I2C3RST: u1, - /// CRS reset - CRSRST: u1, - /// CAN1 reset - CAN1RST: u1, - /// CAN2 reset - CAN2RST: u1, - reserved28: u1, - /// Power interface reset - PWRRST: u1, - /// DAC1 interface reset - DAC1RST: u1, - /// OPAMP interface reset - OPAMPRST: u1, - /// Low Power Timer 1 reset - LPTIM1RST: u1, + /// digest registers. + HR: [5]u32, + /// interrupt enable register. + IMR: mmio.Mmio(packed struct(u32) { + /// Data input interrupt enable. + DINIE: u1, + /// Digest calculation completion interrupt enable. + DCIE: u1, + padding: u30, }), - /// APB1 peripheral reset register 2 - APB1RSTR2: mmio.Mmio(packed struct(u32) { - /// Low-power UART 1 reset - LPUART1RST: u1, - /// I2C4 reset - I2C4RST: u1, - /// Single wire protocol reset - SWPMI1RST: u1, - reserved5: u2, - /// Low-power timer 2 reset - LPTIM2RST: u1, - padding: u26, + /// status register. + SR: mmio.Mmio(packed struct(u32) { + /// Data input interrupt status. + DINIS: u1, + /// Digest calculation completion interrupt status. + DCIS: u1, + /// DMA Status. + DMAS: u1, + /// Busy bit. + BUSY: u1, + padding: u28, }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// System configuration (SYSCFG) reset - SYSCFGRST: u1, - reserved10: u9, - /// SDMMC reset - SDMMCRST: u1, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI1 reset - SPI1RST: u1, - /// TIM8 timer reset - TIM8RST: u1, - /// USART1 reset - USART1RST: u1, - reserved16: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - reserved21: u2, - /// Serial audio interface 1 (SAI1) reset - SAI1RST: u1, - /// Serial audio interface 2 (SAI2) reset - SAI2RST: u1, - reserved24: u1, - /// DFSDM filter reset - DFSDMRST: u1, - padding: u7, + reserved248: [208]u8, + /// context swap registers. + CSR: [51]u32, + }; + }; + + pub const hash_v2 = struct { + /// Hash processor. + pub const HASH = extern struct { + /// control register. + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Initialize message digest calculation. + INIT: u1, + /// DMA enable. + DMAE: u1, + /// Data type selection. + DATATYPE: u2, + /// Mode selection. + MODE: u1, + /// Algorithm selection. + ALGO0: u1, + /// Number of words already pushed. + NBW: u4, + /// DIN not empty. + DINNE: u1, + /// Multiple DMA Transfers. + MDMAT: u1, + reserved16: u2, + /// Long key selection. + LKEY: u1, + reserved18: u1, + /// ALGO. + ALGO1: u1, + padding: u13, }), - reserved72: [4]u8, - /// AHB1 peripheral clock enable register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - reserved8: u6, - /// Flash memory interface clock enable - FLASHEN: u1, - reserved12: u3, - /// CRC clock enable - CRCEN: u1, - reserved16: u3, - /// Touch Sensing Controller clock enable - TSCEN: u1, - /// DMA2D clock enable - DMA2DEN: u1, - padding: u14, + /// data input register. + DIN: u32, + /// start register. + STR: mmio.Mmio(packed struct(u32) { + /// Number of valid bits in the last word of the message. + NBLW: u5, + reserved8: u3, + /// Digest calculation. + DCAL: u1, + padding: u23, }), - /// AHB2 peripheral clock enable register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port C clock enable - GPIOCEN: u1, - /// IO port D clock enable - GPIODEN: u1, - /// IO port E clock enable - GPIOEEN: u1, - /// IO port F clock enable - GPIOFEN: u1, - /// IO port G clock enable - GPIOGEN: u1, - /// IO port H clock enable - GPIOHEN: u1, - /// IO port I clock enable - GPIOIEN: u1, - reserved12: u3, - /// OTG full speed clock enable - USB_OTG_FSEN: u1, - /// ADC clock enable - ADCEN: u1, - /// DCMI clock enable - DCMIEN: u1, - reserved16: u1, - /// AES accelerator clock enable - AESEN: u1, - /// HASH clock enable - HASHEN: u1, - /// Random Number Generator clock enable - RNGEN: u1, + /// digest registers. + HRA: [5]u32, + /// interrupt enable register. + IMR: mmio.Mmio(packed struct(u32) { + /// Data input interrupt enable. + DINIE: u1, + /// Digest calculation completion interrupt enable. + DCIE: u1, + padding: u30, + }), + /// status register. + SR: mmio.Mmio(packed struct(u32) { + /// Data input interrupt status. + DINIS: u1, + /// Digest calculation completion interrupt status. + DCIS: u1, + /// DMA Status. + DMAS: u1, + /// Busy bit. + BUSY: u1, + padding: u28, + }), + reserved248: [208]u8, + /// context swap registers. + CSR: [54]u32, + reserved784: [320]u8, + /// HASH digest register. + HR: [8]u32, + }; + }; + + pub const hash_v3 = struct { + /// Hash processor. + pub const HASH = extern struct { + /// control register. + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Initialize message digest calculation. + INIT: u1, + /// DMA enable. + DMAE: u1, + /// Data type selection. + DATATYPE: u2, + /// Mode selection. + MODE: u1, + reserved8: u1, + /// Number of words already pushed. + NBW: u4, + /// DIN not empty. + DINNE: u1, + /// Multiple DMA Transfers. + MDMAT: u1, + reserved16: u2, + /// Long key selection. + LKEY: u1, + /// Algorithm selection. + ALGO: u2, padding: u13, }), - /// AHB3 peripheral clock enable register - AHB3ENR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller clock enable - FMCEN: u1, - reserved8: u7, - /// QUADSPIEN - QUADSPIEN: u1, + /// data input register. + DIN: u32, + /// start register. + STR: mmio.Mmio(packed struct(u32) { + /// Number of valid bits in the last word of the message. + NBLW: u5, + reserved8: u3, + /// Digest calculation. + DCAL: u1, padding: u23, }), - reserved88: [4]u8, - /// APB1ENR1 - APB1ENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clock enable - TIM2EN: u1, - /// TIM3 timer clock enable - TIM3EN: u1, - /// TIM4 timer clock enable - TIM4EN: u1, - /// TIM5 timer clock enable - TIM5EN: u1, - /// TIM6 timer clock enable - TIM6EN: u1, - /// TIM7 timer clock enable - TIM7EN: u1, - reserved9: u3, - /// LCD clock enable - LCDEN: u1, - /// RTC APB clock enable - RTCAPBEN: u1, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI2 clock enable - SPI2EN: u1, - /// SPI3 clock enable - SPI3EN: u1, - reserved17: u1, - /// USART2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// UART5 clock enable - UART5EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - /// I2C2 clock enable - I2C2EN: u1, - /// I2C3 clock enable - I2C3EN: u1, - /// Clock Recovery System clock enable - CRSEN: u1, - /// CAN1 clock enable - CAN1EN: u1, - /// CAN2 clock enable - CAN2EN: u1, - reserved28: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC1 interface clock enable - DAC1EN: u1, - /// OPAMP interface clock enable - OPAMPEN: u1, - /// Low power timer 1 clock enable - LPTIM1EN: u1, + /// digest registers. + HRA: [5]u32, + /// interrupt enable register. + IMR: mmio.Mmio(packed struct(u32) { + /// Data input interrupt enable. + DINIE: u1, + /// Digest calculation completion interrupt enable. + DCIE: u1, + padding: u30, }), - /// APB1 peripheral clock enable register 2 - APB1ENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clock enable - LPUART1EN: u1, - /// I2C4 clock enable - I2C4EN: u1, - /// Single wire protocol clock enable - SWPMI1EN: u1, - reserved5: u2, - /// LPTIM2EN - LPTIM2EN: u1, - padding: u26, + /// status register. + SR: mmio.Mmio(packed struct(u32) { + /// Data input interrupt status. + DINIS: u1, + /// Digest calculation completion interrupt status. + DCIS: u1, + /// DMA Status. + DMAS: u1, + /// Busy bit. + BUSY: u1, + reserved9: u5, + /// Number of words already pushed. + NBWP: u5, + reserved15: u1, + /// DIN not empty. + DINNE: u1, + /// Number of words expected. + NBWE: u5, + padding: u11, }), - /// APB2ENR - APB2ENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved7: u6, - /// Firewall clock enable - FWEN: u1, - reserved10: u2, - /// SDMMC clock enable - SDMMCEN: u1, - /// TIM1 timer clock enable - TIM1EN: u1, - /// SPI1 clock enable - SPI1EN: u1, - /// TIM8 timer clock enable - TIM8EN: u1, - /// USART1clock enable - USART1EN: u1, - reserved16: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - reserved21: u2, - /// SAI1 clock enable - SAI1EN: u1, - /// SAI2 clock enable - SAI2EN: u1, - reserved24: u1, - /// DFSDMEN enable - DFSDMEN: u1, - padding: u7, - }), - reserved104: [4]u8, - /// AHB1 peripheral clocks enable in Sleep and Stop modes register - AHB1SMENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clocks enable during Sleep and Stop modes - DMA1SMEN: u1, - /// DMA2 clocks enable during Sleep and Stop modes - DMA2SMEN: u1, - reserved8: u6, - /// Flash memory interface clocks enable during Sleep and Stop modes - FLASHSMEN: u1, - /// SRAM1 interface clocks enable during Sleep and Stop modes - SRAM1SMEN: u1, - reserved12: u2, - /// CRCSMEN - CRCSMEN: u1, - reserved16: u3, - /// Touch Sensing Controller clocks enable during Sleep and Stop modes - TSCSMEN: u1, - /// DMA2D clock enable during Sleep and Stop modes - DMA2DSMEN: u1, - padding: u14, - }), - /// AHB2 peripheral clocks enable in Sleep and Stop modes register - AHB2SMENR: mmio.Mmio(packed struct(u32) { - /// IO port A clocks enable during Sleep and Stop modes - GPIOASMEN: u1, - /// IO port B clocks enable during Sleep and Stop modes - GPIOBSMEN: u1, - /// IO port C clocks enable during Sleep and Stop modes - GPIOCSMEN: u1, - /// IO port D clocks enable during Sleep and Stop modes - GPIODSMEN: u1, - /// IO port E clocks enable during Sleep and Stop modes - GPIOESMEN: u1, - /// IO port F clocks enable during Sleep and Stop modes - GPIOFSMEN: u1, - /// IO port G clocks enable during Sleep and Stop modes - GPIOGSMEN: u1, - /// IO port H clocks enable during Sleep and Stop modes - GPIOHSMEN: u1, - /// IO port I clocks enable during Sleep and Stop modes - GPIOISMEN: u1, - /// SRAM2 interface clocks enable during Sleep and Stop modes - SRAM2SMEN: u1, - reserved12: u2, - /// OTG full speed clocks enable during Sleep and Stop modes - USB_OTG_FSSMEN: u1, - /// ADC clocks enable during Sleep and Stop modes - ADCFSSMEN: u1, - /// DCMI clock enable during Sleep and Stop modes - DCMISMEN: u1, - reserved16: u1, - /// AES accelerator clocks enable during Sleep and Stop modes - AESSMEN: u1, - /// HASH clock enable during Sleep and Stop modes - HASHSMEN: u1, - /// Random Number Generator clocks enable during Sleep and Stop modes - RNGSMEN: u1, + reserved248: [208]u8, + /// context swap registers. + CSR: [103]u32, + reserved784: [124]u8, + /// HASH digest register. + HR: [16]u32, + }; + }; + + pub const hash_v4 = struct { + /// Hash processor. + pub const HASH = extern struct { + /// control register. + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Initialize message digest calculation. + INIT: u1, + /// DMA enable. + DMAE: u1, + /// Data type selection. + DATATYPE: u2, + /// Mode selection. + MODE: u1, + reserved8: u1, + /// Number of words already pushed. + NBW: u4, + /// DIN not empty. + DINNE: u1, + /// Multiple DMA Transfers. + MDMAT: u1, + reserved16: u2, + /// Long key selection. + LKEY: u1, + /// Algorithm selection. + ALGO: u2, padding: u13, }), - /// AHB3 peripheral clocks enable in Sleep and Stop modes register - AHB3SMENR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller clocks enable during Sleep and Stop modes - FMCSMEN: u1, - reserved8: u7, - /// QUADSPISMEN - QUADSPISMEN: u1, + /// data input register. + DIN: u32, + /// start register. + STR: mmio.Mmio(packed struct(u32) { + /// Number of valid bits in the last word of the message. + NBLW: u5, + reserved8: u3, + /// Digest calculation. + DCAL: u1, padding: u23, }), - reserved120: [4]u8, - /// APB1SMENR1 - APB1SMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clocks enable during Sleep and Stop modes - TIM2SMEN: u1, - /// TIM3 timer clocks enable during Sleep and Stop modes - TIM3SMEN: u1, - /// TIM4 timer clocks enable during Sleep and Stop modes - TIM4SMEN: u1, - /// TIM5 timer clocks enable during Sleep and Stop modes - TIM5SMEN: u1, - /// TIM6 timer clocks enable during Sleep and Stop modes - TIM6SMEN: u1, - /// TIM7 timer clocks enable during Sleep and Stop modes - TIM7SMEN: u1, - reserved9: u3, - /// LCD clocks enable during Sleep and Stop modes - LCDSMEN: u1, - /// RTC APB clock enable during Sleep and Stop modes - RTCAPBSMEN: u1, - /// Window watchdog clocks enable during Sleep and Stop modes - WWDGSMEN: u1, - reserved14: u2, - /// SPI2 clocks enable during Sleep and Stop modes - SPI2SMEN: u1, - /// SPI3 clocks enable during Sleep and Stop modes - SP3SMEN: u1, - reserved17: u1, - /// USART2 clocks enable during Sleep and Stop modes - USART2SMEN: u1, - /// USART3 clocks enable during Sleep and Stop modes - USART3SMEN: u1, - /// UART4 clocks enable during Sleep and Stop modes - UART4SMEN: u1, - /// UART5 clocks enable during Sleep and Stop modes - UART5SMEN: u1, - /// I2C1 clocks enable during Sleep and Stop modes - I2C1SMEN: u1, - /// I2C2 clocks enable during Sleep and Stop modes - I2C2SMEN: u1, - /// I2C3 clocks enable during Sleep and Stop modes - I2C3SMEN: u1, - /// CRS clock enable during Sleep and Stop modes - CRSSMEN: u1, - /// CAN1 clocks enable during Sleep and Stop modes - CAN1SMEN: u1, - /// CAN2 clocks enable during Sleep and Stop modes - CAN2SMEN: u1, - reserved28: u1, - /// Power interface clocks enable during Sleep and Stop modes - PWRSMEN: u1, - /// DAC1 interface clocks enable during Sleep and Stop modes - DAC1SMEN: u1, - /// OPAMP interface clocks enable during Sleep and Stop modes - OPAMPSMEN: u1, - /// Low power timer 1 clocks enable during Sleep and Stop modes - LPTIM1SMEN: u1, - }), - /// APB1 peripheral clocks enable in Sleep and Stop modes register 2 - APB1SMENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clocks enable during Sleep and Stop modes - LPUART1SMEN: u1, - /// I2C4 clocks enable during Sleep and Stop modes - I2C4SMEN: u1, - /// Single wire protocol clocks enable during Sleep and Stop modes - SWPMI1SMEN: u1, - reserved5: u2, - /// LPTIM2SMEN - LPTIM2SMEN: u1, - padding: u26, - }), - /// APB2SMENR - APB2SMENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clocks enable during Sleep and Stop modes - SYSCFGSMEN: u1, - reserved10: u9, - /// SDMMC clocks enable during Sleep and Stop modes - SDMMCSMEN: u1, - /// TIM1 timer clocks enable during Sleep and Stop modes - TIM1SMEN: u1, - /// SPI1 clocks enable during Sleep and Stop modes - SPI1SMEN: u1, - /// TIM8 timer clocks enable during Sleep and Stop modes - TIM8SMEN: u1, - /// USART1clocks enable during Sleep and Stop modes - USART1SMEN: u1, - reserved16: u1, - /// TIM15 timer clocks enable during Sleep and Stop modes - TIM15SMEN: u1, - /// TIM16 timer clocks enable during Sleep and Stop modes - TIM16SMEN: u1, - /// TIM17 timer clocks enable during Sleep and Stop modes - TIM17SMEN: u1, - reserved21: u2, - /// SAI1 clocks enable during Sleep and Stop modes - SAI1SMEN: u1, - /// SAI2 clocks enable during Sleep and Stop modes - SAI2SMEN: u1, - reserved24: u1, - /// DFSDM timer clocks enable during Sleep and Stop modes - DFSDMSMEN: u1, - padding: u7, - }), - reserved136: [4]u8, - /// CCIPR - CCIPR: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SEL: packed union { - raw: u2, - value: USART1SEL, - }, - /// USART2 clock source selection - USART2SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// USART3 clock source selection - USART3SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// UART4 clock source selection - UART4SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// UART5 clock source selection - UART5SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// LPUART1 clock source selection - LPUART1SEL: packed union { - raw: u2, - value: LPUART1SEL, - }, - /// I2C1 clock source selection - I2C1SEL: packed union { - raw: u2, - value: I2C1SEL, - }, - /// I2C2 clock source selection - I2C2SEL: packed union { - raw: u2, - value: I2C2SEL, - }, - /// I2C3 clock source selection - I2C3SEL: packed union { - raw: u2, - value: I2C3SEL, - }, - /// Low power timer 1 clock source selection - LPTIM1SEL: packed union { - raw: u2, - value: LPTIM1SEL, - }, - /// Low power timer 2 clock source selection - LPTIM2SEL: packed union { - raw: u2, - value: LPTIM2SEL, - }, - /// SAI1 clock source selection - SAI1SEL: packed union { - raw: u2, - value: SAI1SEL, - }, - /// SAI2 clock source selection - SAI2SEL: packed union { - raw: u2, - value: SAI2SEL, - }, - /// 48 MHz clock source selection - CLK48SEL: packed union { - raw: u2, - value: CLK48SEL, - }, - /// ADCs clock source selection - ADCSEL: packed union { - raw: u2, - value: ADCSEL, - }, - /// SWPMI1 clock source selection - SWPMI1SEL: packed union { - raw: u1, - value: SWPMI1SEL, - }, - /// DFSDM clock source selection - DFSDMSEL: packed union { - raw: u1, - value: DFSDMSEL, - }, - }), - reserved144: [4]u8, - /// BDCR - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enable - LSEON: u1, - /// LSE oscillator ready - LSERDY: u1, - /// LSE oscillator bypass - LSEBYP: u1, - /// SE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// LSECSSON - LSECSSON: u1, - /// LSECSSD - LSECSSD: u1, - reserved8: u1, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - reserved24: u7, - /// Low speed clock output enable - LSCOEN: u1, - /// Low speed clock output selection - LSCOSEL: packed union { - raw: u1, - value: LSCOSEL, - }, - padding: u6, - }), - /// CSR - CSR: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable - LSION: u1, - /// LSI oscillator ready - LSIRDY: u1, - reserved8: u6, - /// SI range after Standby mode - MSISRANGE: u4, - reserved23: u11, - /// Remove reset flag - RMVF: u1, - /// Firewall reset flag - FWRSTF: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// Pin reset flag - PINRSTF: u1, - /// BOR flag - BORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent window watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// digest registers. + HRA: [5]u32, + /// interrupt enable register. + IMR: mmio.Mmio(packed struct(u32) { + /// Data input interrupt enable. + DINIE: u1, + /// Digest calculation completion interrupt enable. + DCIE: u1, + padding: u30, }), - /// Clock recovery RC register - CRRCR: mmio.Mmio(packed struct(u32) { - /// HSI48 clock enable - HSI48ON: u1, - /// HSI48 clock ready flag - HSI48RDY: u1, - reserved7: u5, - /// HSI48 clock calibration - HSI48CAL: u9, - padding: u16, + /// status register. + SR: mmio.Mmio(packed struct(u32) { + /// Data input interrupt status. + DINIS: u1, + /// Digest calculation completion interrupt status. + DCIS: u1, + /// DMA Status. + DMAS: u1, + /// Busy bit. + BUSY: u1, + reserved9: u5, + /// Number of words already pushed. + NBWP: u5, + reserved15: u1, + /// DIN not empty. + DINNE: u1, + /// Number of words expected. + NBWE: u5, + padding: u11, }), + reserved248: [208]u8, + /// context swap registers. + CSR: [54]u32, + reserved784: [320]u8, + /// HASH digest register. + HR: [8]u32, }; }; - pub const rtc_v2l4 = struct { - pub const ALRMR_MSK = enum(u1) { - /// Alarm set if the date/day match - ToMatch = 0x0, - /// Date/day don’t care in Alarm comparison - NotMatch = 0x1, + pub const hrtim_v1 = struct { + pub const ACTIVEEFFECT = enum(u1) { + /// Timer event has no effect + NoEffect = 0x0, + /// Timer event forces the output to its active state + SetActive = 0x1, }; - pub const ALRMR_PM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const BRSTDMA = enum(u2) { + /// Update done independently from the DMA burst transfer completion + Independent = 0x0, + /// Update done when the DMA burst transfer is completed + Completion = 0x1, + /// Update done on master timer roll-over following a DMA burst transfer completion + Rollover = 0x2, + _, }; - pub const ALRMR_WDSEL = enum(u1) { - /// DU[3:0] represents the date units - DateUnits = 0x0, - /// DU[3:0] represents the week day. DT[1:0] is don’t care - WeekDay = 0x1, + pub const CAPTUREEFFECT = enum(u1) { + /// Timer event has no effect + NoEffect = 0x0, + /// Timer event triggers capture + TriggerCapture = 0x1, }; - pub const AMPM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const CPPSTAT = enum(u1) { + /// Signal applied on output 1 and output 2 forced inactive + Output1Active = 0x0, + /// Signal applied on output 2 and output 1 forced inactive + Output2Active = 0x1, }; - pub const CALP = enum(u1) { - /// No RTCCLK pulses are added - NoChange = 0x0, - /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - IncreaseFreq = 0x1, + pub const DACSYNC = enum(u2) { + /// No DAC trigger generated + Disabled = 0x0, + /// Trigger generated on DACSync1 + DACSync1 = 0x1, + /// Trigger generated on DACSync2 + DACSync2 = 0x2, + /// Trigger generated on DACSync3 + DACSync3 = 0x3, }; - pub const CALW16 = enum(u1) { - /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 - Sixteen_Second = 0x1, - _, + pub const DELCMP = enum(u2) { + /// CMP register is always active (standard compare mode) + Standard = 0x0, + /// CMP is recomputed and is active following a capture 1 event + Capture1 = 0x1, + /// CMP is recomputed and is active following a capture 1 event or a Compare 1 match + CaptureX_Compare1 = 0x2, + /// CMP is recomputed and is active following a capture 1 event or a Compare 3 match + CaptureX_Compare3 = 0x3, }; - pub const CALW8 = enum(u1) { - /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected - Eight_Second = 0x1, - _, + pub const DLYPRT = enum(u3) { + /// Output 1 delayed idle on external event 6 + Output1_EE6 = 0x0, + /// Output 2 delayed idle on external event 6 + Output2_EE6 = 0x1, + /// Output 1 and 2 delayed idle on external event 6 + Output1_2_EE6 = 0x2, + /// Balanced idle on external event 6 + Balanced_EE6 = 0x3, + /// Output 1 delayed idle on external event 7 + Output1_EE7 = 0x4, + /// Output 2 delayed idle on external event 7 + Output2_EE7 = 0x5, + /// Output 1 and 2 delayed idle on external event 7 + Output1_2_EE7 = 0x6, + /// Balanced idle on external event 7 + Balanced_EE7 = 0x7, }; - pub const COSEL = enum(u1) { - /// Calibration output is 512 Hz (with default prescaler setting) - CalFreq_512Hz = 0x0, - /// Calibration output is 1 Hz (with default prescaler setting) - CalFreq_1Hz = 0x1, + pub const EEFLTR = enum(u4) { + /// No filtering + Disabled = 0x0, + /// Blanking from counter reset/roll-over to Compare 1 + BlankResetToCompare1 = 0x1, + /// Blanking from counter reset/roll-over to Compare 2 + BlankResetToCompare2 = 0x2, + /// Blanking from counter reset/roll-over to Compare 3 + BlankResetToCompare3 = 0x3, + /// Blanking from counter reset/roll-over to Compare 4 + BlankResetToCompare4 = 0x4, + /// Blanking from another timing unit: TIMFLTR1 source + BlankTIMFLTR1 = 0x5, + /// Blanking from another timing unit: TIMFLTR2 source + BlankTIMFLTR2 = 0x6, + /// Blanking from another timing unit: TIMFLTR3 source + BlankTIMFLTR3 = 0x7, + /// Blanking from another timing unit: TIMFLTR4 source + BlankTIMFLTR4 = 0x8, + /// Blanking from another timing unit: TIMFLTR5 source + BlankTIMFLTR5 = 0x9, + /// Blanking from another timing unit: TIMFLTR6 source + BlankTIMFLTR6 = 0xa, + /// Blanking from another timing unit: TIMFLTR7 source + BlankTIMFLTR7 = 0xb, + /// Blanking from another timing unit: TIMFLTR8 source + BlankTIMFLTR8 = 0xc, + /// Windowing from counter reset/roll-over to compare 2 + WindowResetToCompare2 = 0xd, + /// Windowing from counter reset/roll-over to compare 3 + WindowResetToCompare3 = 0xe, + /// Windowing from another timing unit: TIMWIN source + WindowTIMWIN = 0xf, }; - pub const FMT = enum(u1) { - /// 24 hour/day format - Twenty_Four_Hour = 0x0, - /// AM/PM hour format - AM_PM = 0x1, + pub const FAULT = enum(u2) { + /// No action: the output is not affected by the fault input and stays in run mode + Disabled = 0x0, + /// Output goes to active state after a fault event + SetActive = 0x1, + /// Output goes to inactive state after a fault event + SetInactive = 0x2, + /// Output goes to high-z state after a fault event + SetHighZ = 0x3, }; - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Alarm B output enabled - AlarmB = 0x2, - /// Wakeup output enabled - Wakeup = 0x3, + pub const FLTEN = enum(u1) { + /// Fault input ignored + Ignored = 0x0, + /// Fault input is active and can disable HRTIM outputs + Active = 0x1, + }; + + pub const INACTIVEEFFECT = enum(u1) { + /// Timer event has no effect + NoEffect = 0x0, + /// Timer event forces the output to its inactive state + SetInactive = 0x1, + }; + + pub const IPPSTAT = enum(u1) { + /// Protection occurred when the output 1 was active and output 2 forced inactive + Output1Active = 0x0, + /// Protection occurred when the output 2 was active and output 1 forced inactive + Output2Active = 0x1, + }; + + pub const OUTPUTSTATE = enum(u1) { + /// Output is or was inactive + Inactive = 0x0, + /// Output is or was active + Active = 0x1, }; pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - Low = 0x1, + /// Positive polarity (output active high) + ActiveHigh = 0x0, + /// Negative polarity (output active low) + ActiveLow = 0x1, }; - pub const RECALPF = enum(u1) { - /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 - Pending = 0x1, - _, + pub const RESETEFFECT = enum(u1) { + /// Timer Y compare Z event has no effect + NoEffect = 0x0, + /// Timer X counter is reset upon timer Y compare Z event + ResetCounter = 0x1, }; - pub const TAMPFLT = enum(u2) { - /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - Immediate = 0x0, - /// Tamper event is activated after 2 consecutive samples at the active level - Samples2 = 0x1, - /// Tamper event is activated after 4 consecutive samples at the active level - Samples4 = 0x2, - /// Tamper event is activated after 8 consecutive samples at the active level - Samples8 = 0x3, + pub const SDTF = enum(u1) { + /// Positive deadtime on falling edge + Positive = 0x0, + /// Negative deadtime on falling edge + Negative = 0x1, }; - pub const TAMPFREQ = enum(u3) { - /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - Div32768 = 0x0, - /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - Div16384 = 0x1, - /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - Div8192 = 0x2, - /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - Div4096 = 0x3, - /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - Div2048 = 0x4, - /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - Div1024 = 0x5, - /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - Div512 = 0x6, - /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - Div256 = 0x7, + pub const SDTR = enum(u1) { + /// Positive deadtime on rising edge + Positive = 0x0, + /// Negative deadtime on rising edge + Negative = 0x1, }; - pub const TAMPPRCH = enum(u2) { - /// 1 RTCCLK cycle - Cycles1 = 0x0, - /// 2 RTCCLK cycles - Cycles2 = 0x1, - /// 4 RTCCLK cycles - Cycles4 = 0x2, - /// 8 RTCCLK cycles - Cycles8 = 0x3, + pub const SYNCIN = enum(u2) { + /// Disabled. HRTIM is not synchronized and runs in standalone mode + Disabled = 0x0, + /// Internal event: the HRTIM is synchronized with the on-chip timer + Internal = 0x2, + /// External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM + External = 0x3, + _, }; - pub const TAMPPUDIS = enum(u1) { - /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - Enabled = 0x0, - /// Disable precharge of RTC_TAMPx pins - Disabled = 0x1, + pub const SYNCOUT = enum(u2) { + /// Disabled + Disabled = 0x0, + /// Positive pulse on SCOUT output (16x f_HRTIM clock cycles) + PositivePulse = 0x2, + /// Negative pulse on SCOUT output (16x f_HRTIM clock cycles) + NegativePulse = 0x3, + _, }; - pub const TAMPTRG = enum(u1) { - /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. - RisingEdge = 0x0, - /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event - FallingEdge = 0x1, + pub const SYNCRST = enum(u1) { + /// Synchronization event has no effect on Timer x + Disabled = 0x0, + /// Synchronization event resets Timer x + Reset = 0x1, }; - pub const TSEDGE = enum(u1) { - /// RTC_TS input rising edge generates a time-stamp event - RisingEdge = 0x0, - /// RTC_TS input falling edge generates a time-stamp event - FallingEdge = 0x1, + pub const SYNCSRC = enum(u2) { + /// Master timer Start + MasterStart = 0x0, + /// Master timer Compare 1 event + MasterCompare1 = 0x1, + /// Timer A start/reset + TimerAStart = 0x2, + /// Timer A Compare 1 event + TimerACompare1 = 0x3, }; - pub const WUCKSEL = enum(u3) { - /// RTC/16 clock is selected - Div16 = 0x0, - /// RTC/8 clock is selected - Div8 = 0x1, - /// RTC/4 clock is selected - Div4 = 0x2, - /// RTC/2 clock is selected - Div2 = 0x3, - /// ck_spre (usually 1 Hz) clock is selected - ClockSpare = 0x4, - /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - ClockSpareWithOffset = 0x6, + pub const SYNCSTRT = enum(u1) { + /// Synchronization event has no effect on Timer x + Disabled = 0x0, + /// Synchronization event starts Timer x + Start = 0x1, + }; + + pub const TIMAISR_DLYPRT = enum(u1) { + /// Not in delayed idle or balanced idle mode + Inactive = 0x0, + /// Delayed idle or balanced idle mode entry + Active = 0x1, + }; + + pub const UPDGAT = enum(u4) { + /// Update occurs independently from the DMA burst transfer + Independent = 0x0, + /// Update occurs when the DMA burst transfer is completed + DMABurst = 0x1, + /// Update occurs on the update event following DMA burst transfer completion + DMABurst_Update = 0x2, + /// Update occurs on a rising edge of HRTIM update enable input 1 + Input1 = 0x3, + /// Update occurs on a rising edge of HRTIM update enable input 2 + Input2 = 0x4, + /// Update occurs on a rising edge of HRTIM update enable input 3 + Input3 = 0x5, + /// Update occurs on the update event following a rising edge of HRTIM update enable input 1 + Input1_Update = 0x6, + /// Update occurs on the update event following a rising edge of HRTIM update enable input 2 + Input2_Update = 0x7, + /// Update occurs on the update event following a rising edge of HRTIM update enable input 3 + Input3_Update = 0x8, _, }; - /// Real-time clock - pub const RTC = extern struct { - /// Time register - TR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, - }), - /// Date register - DR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, + /// High Resolution Timer + pub const HRTIM = extern struct { + /// Master Timer Control Register + MCR: mmio.Mmio(packed struct(u32) { + /// HRTIM Master Clock prescaler + CKPSC: u3, + /// Master Continuous mode + CONT: u1, + /// Master Re-triggerable mode + RETRIG: u1, + /// Half mode enable + HALF: u1, reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding: u8, - }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Wakeup clock selection - WUCKSEL: packed union { - raw: u3, - value: WUCKSEL, - }, - /// Timestamp event active edge - TSEDGE: packed union { - raw: u1, - value: TSEDGE, + /// Synchronization input + SYNCIN: packed union { + raw: u2, + value: SYNCIN, }, - /// Reference clock detection enable (50 or 60 Hz) - REFCKON: u1, - /// Bypass the shadow registers - BYPSHAD: u1, - /// Hour format - FMT: packed union { - raw: u1, - value: FMT, + /// Synchronization Resets Master + SYNCRSTM: u1, + /// Synchronization Starts Master + SYNCSTRTM: u1, + /// Synchronization output + SYNCOUT: packed union { + raw: u2, + value: SYNCOUT, }, - reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, - /// Wakeup timer enable - WUTE: u1, - /// Timestamp enable - TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, - /// Wakeup timer interrupt enable - WUTIE: u1, - /// Timestamp interrupt enable - TSIE: u1, - /// Add 1 hour (summer time change) - ADD1H: u1, - /// Subtract 1 hour (winter time change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output selection - COSEL: packed union { - raw: u1, - value: COSEL, + /// Synchronization source + SYNCSRC: packed union { + raw: u2, + value: SYNCSRC, }, - /// Output polarity - POL: packed union { - raw: u1, - value: POL, + /// Master Counter enable + MCEN: u1, + /// Timer X counter enable + TCEN: u1, + reserved25: u7, + /// AC Synchronization + DACSYNC: packed union { + raw: u2, + value: DACSYNC, }, - /// Output selection - OSEL: packed union { + /// Preload enable + PREEN: u1, + reserved29: u1, + /// Master Timer Repetition update + MREPU: u1, + /// Burst DMA Update + BRSTDMA: packed union { raw: u2, - value: OSEL, + value: BRSTDMA, }, - /// Calibration output enable - COE: u1, - /// Timestamp on internal event enable - ITSE: u1, - padding: u7, }), - /// Initialization and status register - ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, - /// Wakeup timer write enabled - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Enter Initialization mode - INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, - /// Wakeup timer flag - WUTF: u1, - /// Timestamp flag - TSF: u1, - /// Timestamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, - /// Recalibration pending flag - RECALPF: packed union { - raw: u1, - value: RECALPF, - }, - padding: u15, + /// Master Timer Interrupt Status Register + MISR: mmio.Mmio(packed struct(u32) { + /// Master Compare X Interrupt Flag + MCMP: u1, + reserved4: u3, + /// Master Repetition Interrupt Flag + MREP: u1, + /// Sync Input Interrupt Flag + SYNC: u1, + /// Master Update Interrupt Flag + MUPD: u1, + padding: u25, }), - /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, + /// Master Timer Interrupt Clear Register + MICR: mmio.Mmio(packed struct(u32) { + /// Master Compare X Interrupt flag clear + MCMPC: u1, + reserved4: u3, + /// Repetition Interrupt flag clear + MREPC: u1, + /// Sync Input Interrupt flag clear + SYNCC: u1, + /// Master update Interrupt flag clear + MUPDC: u1, + padding: u25, + }), + /// Master Timer DMA / Interrupt Enable Register + MDIER: mmio.Mmio(packed struct(u32) { + /// Master Compare X Interrupt Enable + MCMPIE: u1, + reserved4: u3, + /// Master Repetition Interrupt Enable + MREPIE: u1, + /// Sync Input Interrupt Enable + SYNCIE: u1, + /// Master Update Interrupt Enable + MUPDIE: u1, + reserved16: u9, + /// Master Compare X DMA request Enable + MCMPDE: u1, + reserved20: u3, + /// Master Repetition DMA request Enable + MREPDE: u1, + /// Sync Input DMA request Enable + SYNCDE: u1, + /// Master Update DMA request Enable + MUPDDE: u1, padding: u9, }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, + /// Master Timer Counter Register + MCNTR: mmio.Mmio(packed struct(u32) { + /// Counter value + MCNT: u16, padding: u16, }), - reserved28: [4]u8, - /// Alarm register - ALRMR: [2]mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm seconds mask - MSK1: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm minutes mask - MSK2: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: ALRMR_PM, - }, - /// Alarm hours mask - MSK3: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { - raw: u1, - value: ALRMR_WDSEL, - }, - /// Alarm date mask - MSK4: packed union { - raw: u1, - value: ALRMR_MSK, - }, + /// Master Timer Period Register + MPER: mmio.Mmio(packed struct(u32) { + /// Master Timer Period value + MPER: u16, + padding: u16, }), - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: u8, + /// Master Timer Repetition Register + MREP: mmio.Mmio(packed struct(u32) { + /// Master Timer Repetition counter value + MREP: u8, padding: u24, }), - /// Sub second register - SSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, + /// Master Timer Compare X Register + MCMP: mmio.Mmio(packed struct(u32) { + /// Master Timer Compare X value + MCMP: u16, padding: u16, }), - /// Shift control register - SHIFTR: mmio.Mmio(packed struct(u32) { - /// Subtract a fraction of a second - SUBFS: u15, - reserved31: u16, - /// Add one second - ADD1S: u1, + reserved128: [96]u8, + /// High Resolution Timer: Timing Unit + TIM: u32, + reserved896: [764]u8, + /// High Resolution Timer: Control Register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Master Update Disable + MUDIS: u1, + /// Timer X Update Disable + TUDIS: u1, + reserved16: u14, + /// ADC Trigger X Update Source + ADUSRC: u3, + padding: u13, }), - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, + /// High Resolution Timer: Control Register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Master Timer Software Update + MSWU: u1, + /// Timer X Software Update + TSWU: u1, + reserved8: u6, + /// Master Counter Software Reset + MRST: u1, + /// Timer X Counter Software Reset + TRST: u1, + padding: u22, }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, + /// High Resolution Timer: Interrupt Status Register + ISR: mmio.Mmio(packed struct(u32) { + /// Fault X Interrupt Flag + FLT: u1, + reserved5: u4, + /// System Fault Interrupt Flag + SYSFLT: u1, + reserved16: u10, + /// DLL Ready Interrupt Flag + DLLRDY: u1, + /// Burst Mode Period Interrupt Flag + BMPER: u1, + padding: u14, + }), + /// High Resolution Timer: Interrupt Clear Register + ICR: mmio.Mmio(packed struct(u32) { + /// Fault X Interrupt Flag Clear + FLT: u1, + reserved5: u4, + /// System Fault Interrupt Flag Clear + SYSFLT: u1, + reserved16: u10, + /// DLL Ready Interrupt Flag Clear + DLLRDY: u1, + /// Burst Mode Period Interrupt Flag Clear + BMPER: u1, + padding: u14, + }), + /// High Resolution Timer: Interrupt Enable Register + IER: mmio.Mmio(packed struct(u32) { + /// Fault X Interrupt Flag Enable + FLT: u1, + reserved5: u4, + /// System Fault Interrupt Flag Enable + SYSFLT: u1, + reserved16: u10, + /// DLL Ready Interrupt Flag Enable + DLLRDY: u1, + /// Burst Mode Period Interrupt Flag Enable + BMPER: u1, + padding: u14, + }), + /// High Resolution Timer: Output Enable Register + OENR: mmio.Mmio(packed struct(u32) { + /// Timer X Output Enable + T1OEN: u1, + /// Timer X Complementary Output Enable + T2OEN: u1, + padding: u30, + }), + /// High Resolution Timer: Output Disable Register + ODISR: mmio.Mmio(packed struct(u32) { + /// Timer X Output Disable + T1ODIS: u1, + /// Timer X Complementary Output Disable + T2ODIS: u1, + padding: u30, + }), + /// High Resolution Timer: Output Disable Status Register + ODSR: mmio.Mmio(packed struct(u32) { + /// Timer X Output Disable Status + T1ODIS: u1, + /// Timer X Complementary Output Disable Status + T2ODIS: u1, + padding: u30, + }), + /// High Resolution Timer: Burst Mode Control Register + BMCR: mmio.Mmio(packed struct(u32) { + /// Burst Mode Enable + BME: u1, + /// Burst Mode Operating Mode + BMOM: u1, + /// Burst Mode Clock source + BMCLK: u3, + reserved6: u1, + /// Burst Mode Prescaler + BMPRSC: u3, + reserved10: u1, + /// Burst Mode Preload Enable + BMPREN: u1, + reserved16: u5, + /// Master Timer Burst Mode + MTBM: u1, + /// Timer X Burst Mode + TBM: u1, + reserved31: u13, + BMSTAT: u1, + }), + /// High Resolution Timer: Burst Mode Trigger Register + BMTRGR: mmio.Mmio(packed struct(u32) { + /// Software start + SW: u1, + /// Master reset or roll-over + MSTRST: u1, + /// Master repetition + MSTREP: u1, + /// Master Compare X + MSTCMP: u1, + reserved7: u3, + /// Timer X reset or roll-over + TRST: u1, + /// Timer X repetition + TREP: u1, + /// Timer X compare 1 event + TCMP1: u1, + /// Timer X compare 2 event + TCMP2: u1, + padding: u21, + }), + /// High Resolution Timer: Burst Mode Compare Register + BMCMPR: mmio.Mmio(packed struct(u32) { + /// Burst mode compare value + BMCMP: u16, padding: u16, }), - /// Timestamp sub second register - TSSSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, + /// High Resolution Timer: Burst Mode Period Register + BMPER: mmio.Mmio(packed struct(u32) { + /// Burst mode period value + BMPER: u16, padding: u16, }), - /// Calibration register - CALR: mmio.Mmio(packed struct(u32) { - /// Calibration minus - CALM: u9, - reserved13: u4, - /// Use a 16-second calibration cycle period - CALW16: packed union { + /// High Resolution Timer: External Event Control Register 1 + EECR1: mmio.Mmio(packed struct(u32) { + /// External Event X Source + EESRC: u2, + /// External Event X Polarity + EEPOL: u1, + /// External Event X Sensitivity + EESNS: u2, + /// External Event X Fast Mode + EEFAST: u2, + padding: u25, + }), + /// High Resolution Timer: External Event Control Register 2 + EECR2: mmio.Mmio(packed struct(u32) { + /// External Event X Source + EESRC: u2, + /// External Event X Polarity + EEPOL: u1, + /// External Event X Sensitivity + EESNS: u2, + padding: u27, + }), + /// High Resolution Timer: External Event Control Register 3 + EECR3: mmio.Mmio(packed struct(u32) { + /// External Event X filter + EEF: u3, + reserved30: u27, + /// External Event Sampling Clock Division + EEVSD: u2, + }), + /// High Resolution Timer: ADC Trigger [1, 3] Register + ADC1R: mmio.Mmio(packed struct(u32) { + /// ADC trigger X on Master Compare Y + ADCMC: u1, + reserved4: u3, + /// ADC trigger X on Master Period + ADCMPER: u1, + /// ADC trigger X on External Event Y + ADCEEV: u1, + reserved10: u4, + /// ADC trigger X on Timer Y Compare 2 + ADCTC2: u1, + /// ADC trigger X on Timer Y Compare 3 + ADCTC3: u1, + /// ADC trigger X on Timer Y Compare 3 + ADCTC4: u1, + /// ADC trigger X on Timer Y Period + ADCTPER: u1, + /// ADC trigger X on Timer Y Reset + ADCTRST: u1, + padding: u17, + }), + /// High Resolution Timer: ADC Trigger [2, 4] Register + ADC2R: mmio.Mmio(packed struct(u32) { + /// ADC trigger X on Master Compare Y + ADCMC: u1, + reserved4: u3, + /// ADC trigger X on Master Period + ADCMPER: u1, + /// ADC trigger X on External Event Y + ADCEEV: u1, + reserved10: u4, + /// ADC trigger X on Timer Y Compare 2 + ADCTC2: u1, + /// ADC trigger X on Timer Y Compare 3 + ADCTC3: u1, + /// ADC trigger X on Timer Y Compare 3 + ADCTC4: u1, + /// ADC trigger X on Timer Y Period + ADCTPER: u1, + reserved22: u8, + /// ADC trigger X on Timer Y Reset + ADCTRST: u1, + padding: u9, + }), + reserved972: [8]u8, + /// High Resolution Timer: DLL Control Register + DLLCR: mmio.Mmio(packed struct(u32) { + /// DLL Calibration Start + CAL: u1, + /// DLL Calibration Enable + CALEN: u1, + /// DLL Calibration Rate + CALRTE: u2, + padding: u28, + }), + /// High Resolution Timer: Fault Input Register 1 + FLTINR1: mmio.Mmio(packed struct(u32) { + /// Fault X enable + FLTE: u1, + /// Fault X polarity + FLTP: u1, + /// Fault X source + FLTSRC: u1, + /// Fault X filter + FLTF: u4, + /// Fault X Lock + FLTLCK: u1, + padding: u24, + }), + reserved984: [4]u8, + /// High Resolution Timer: Burst DMA Master timer update Register + BDMUPR: mmio.Mmio(packed struct(u32) { + /// MCR register update enable + MCR: u1, + /// MICR register update enable + MICR: u1, + /// MDIER register update enable + MDIER: u1, + /// MCNT register update enable + MCNT: u1, + /// MPER register update enable + MPER: u1, + /// MREP register update enable + MREP: u1, + /// MCMP register X update enable + MCMP: u1, + padding: u25, + }), + /// High Resolution Timer: Burst DMA Timer X update Register + BDTUPR: [5]mmio.Mmio(packed struct(u32) { + /// CR register update enable + CR: u1, + /// ICR register update enable + ICR: u1, + /// DIER register update enable + DIER: u1, + /// CNT register update enable + CNT: u1, + /// PER register update enable + PER: u1, + /// REP register update enable + REP: u1, + /// CMP register X update enable + CMP: u1, + padding: u25, + }), + /// High Resolution Timer: Burst DMA Data Register + BDMADR: mmio.Mmio(packed struct(u32) { + /// Burst DMA Data register + BDMADR: u31, + padding: u1, + }), + }; + + /// High Resolution Timer: Timing Unit + pub const HRTIM_TIMX = extern struct { + /// Timer X Control Register + CR: mmio.Mmio(packed struct(u32) { + /// HRTIM Timer x Clock prescaler + CKPSC: u3, + /// Continuous mode + CONT: u1, + /// Re-triggerable mode + RETRIG: u1, + /// Half mode enable + HALF: u1, + /// Push-Pull mode enable + PSHPLL: u1, + reserved10: u3, + /// Synchronization Resets Timer X + SYNCRST: packed union { raw: u1, - value: CALW16, + value: SYNCRST, }, - /// Use an 8-second calibration cycle period - CALW8: packed union { + /// Synchronization Starts Timer X + SYNCSTRT: packed union { raw: u1, - value: CALW8, + value: SYNCSTRT, }, - /// Increase frequency of RTC by 488.5 ppm - CALP: packed union { - raw: u1, - value: CALP, + /// Delayed CMP2 mode + DELCMP2: packed union { + raw: u2, + value: DELCMP, + }, + /// Delayed CMP4 mode + DELCMP4: packed union { + raw: u2, + value: DELCMP, + }, + reserved17: u1, + /// Timer X Repetition update + REPU: u1, + /// Timer X reset update + RSTU: u1, + /// Timer A update + TAU: u1, + /// Timer B update + TBU: u1, + /// Timer C update + TCU: u1, + /// Timer D update + TDU: u1, + /// Timer E update + TEU: u1, + /// Master Timer update + MSTU: u1, + /// AC Synchronization + DACSYNC: packed union { + raw: u2, + value: DACSYNC, + }, + /// Preload enable + PREEN: u1, + /// Update Gating + UPDGAT: packed union { + raw: u4, + value: UPDGAT, }, - padding: u16, }), - /// Tamper configuration register - TAMPCR: mmio.Mmio(packed struct(u32) { - /// Tamper detection enable - TAMPE: u1, - /// Active level for tamper - TAMPTRG: packed union { + /// Timer X Interrupt Status Register + ISR: mmio.Mmio(packed struct(u32) { + /// Compare X Interrupt Flag + CMP: u1, + reserved4: u3, + /// Repetition Interrupt Flag + REP: u1, + reserved6: u1, + /// Update Interrupt Flag + UPD: u1, + /// Capture X Interrupt Flag + CPT: u1, + reserved9: u1, + /// Output X Set Interrupt Flag + SETR: u1, + /// Output X Reset Interrupt Flag + RSTR: u1, + reserved13: u2, + /// Reset Interrupt Flag + RST: u1, + /// Delayed Protection Flag + DLYPRT: packed union { raw: u1, - value: TAMPTRG, + value: TIMAISR_DLYPRT, }, - /// Tamper interrupt enable - TAMPIE: u1, - reserved7: u4, - /// Activate timestamp on tamper detection event - TAMPTS: u1, - /// Tamper sampling frequency - TAMPFREQ: packed union { - raw: u3, - value: TAMPFREQ, + reserved16: u1, + /// Current Push Pull Status + CPPSTAT: packed union { + raw: u1, + value: CPPSTAT, }, - /// Tamper filter count - TAMPFLT: packed union { - raw: u2, - value: TAMPFLT, + /// Idle Push Pull Status + IPPSTAT: packed union { + raw: u1, + value: IPPSTAT, }, - /// Tamper precharge duration - TAMPPRCH: packed union { - raw: u2, - value: TAMPPRCH, + /// Output X State + OSTAT: packed union { + raw: u1, + value: OUTPUTSTATE, }, - /// Tamper pull-up disable - TAMPPUDIS: packed union { + reserved20: u1, + /// Output X Copy + OCPY: packed union { raw: u1, - value: TAMPPUDIS, + value: OUTPUTSTATE, }, - /// Tamper interrupt enable - TAMPXIE: u1, - /// Tamper no erase - TAMPXNOERASE: u1, - /// Tamper mask flag - TAMPXMF: u1, - padding: u13, + padding: u11, }), - /// Alarm sub second register - ALRMSSR: [2]mmio.Mmio(packed struct(u32) { - /// Sub seconds value - SS: u15, - reserved24: u9, - /// Mask the most-significant bits starting at this bit - MASKSS: u4, - padding: u4, + /// Timer X Interrupt Clear Register + ICR: mmio.Mmio(packed struct(u32) { + /// Compare X Interrupt flag Clear + CMPC: u1, + reserved4: u3, + /// Repetition Interrupt flag Clear + REPC: u1, + reserved6: u1, + /// Update Interrupt flag Clear + UPDC: u1, + /// Capture X Interrupt flag Clear + CPTC: u1, + reserved9: u1, + /// Output X Set flag Clear + SETRC: u1, + /// Output X Reset flag Clear + RSTRC: u1, + reserved13: u2, + /// Reset Interrupt flag Clear + RSTC: u1, + /// Delayed Protection Flag Clear + DLYPRTC: u1, + padding: u17, }), - /// Option register - OR: mmio.Mmio(packed struct(u32) { - /// RTC_ALARM on PC13 output type - RTC_ALARM_TYPE: u1, - /// RTC_OUT remap - RTC_OUT_RMP: u1, - padding: u30, + /// Timer X DMA / Interrupt Enable Register + DIER: mmio.Mmio(packed struct(u32) { + /// Compare X Interrupt Enable + CMPIE: u1, + reserved4: u3, + /// Repetition Interrupt Enable + REPIE: u1, + reserved6: u1, + /// Update Interrupt Enable + UPDIE: u1, + /// Capture Interrupt Enable + CPTIE: u1, + reserved9: u1, + /// Output X Set Interrupt Enable + SETRIE: u1, + /// Output X Reset Interrupt Enable + RSTRIE: u1, + reserved13: u2, + /// Reset/roll-over Interrupt Enable + RSTIE: u1, + /// Delayed Protection Interrupt Enable + DLYPRTIE: u1, + reserved16: u1, + /// Compare X DMA request Enable + CMPDE: u1, + reserved20: u3, + /// Repetition DMA request Enable + REPDE: u1, + reserved22: u1, + /// Update DMA request Enable + UPDDE: u1, + /// Capture X DMA request Enable + CPTDE: u1, + reserved25: u1, + /// Output X Set DMA request Enable + SETRDE: u1, + /// Output X Reset DMA request Enable + RSTRDE: u1, + reserved29: u2, + /// Reset/roll-over DMA request Enable + RSTDE: u1, + /// Delayed Protection DMA request Enable + DLYPRTDE: u1, + padding: u1, }), - /// Backup register - BKPR: [32]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, + /// Timer X Counter Register + CNT: mmio.Mmio(packed struct(u32) { + /// Timerx Counter value + CNT: u16, + padding: u16, }), - }; - }; - - pub const usart_v1 = struct { - pub const CPHA = enum(u1) { - /// The first clock transition is the first data capture edge - First = 0x0, - /// The second clock transition is the first data capture edge - Second = 0x1, - }; - - pub const CPOL = enum(u1) { - /// Steady low value on CK pin outside transmission window - Low = 0x0, - /// Steady high value on CK pin outside transmission window - High = 0x1, - }; - - pub const IRLP = enum(u1) { - /// Normal mode - Normal = 0x0, - /// Low-power mode - LowPower = 0x1, - }; - - pub const LBDL = enum(u1) { - /// 10-bit break detection - Bit10 = 0x0, - /// 11-bit break detection - Bit11 = 0x1, - }; - - pub const M0 = enum(u1) { - /// 1 start bit, 8 data bits, n stop bits - Bit8 = 0x0, - /// 1 start bit, 9 data bits, n stop bits - Bit9 = 0x1, - }; - - pub const PS = enum(u1) { - /// Even parity - Even = 0x0, - /// Odd parity - Odd = 0x1, - }; - - pub const RWU = enum(u1) { - /// Receiver in active mode - Active = 0x0, - /// Receiver in mute mode - Mute = 0x1, - }; - - pub const STOP = enum(u2) { - /// 1 stop bit - Stop1 = 0x0, - /// 0.5 stop bits - Stop0p5 = 0x1, - /// 2 stop bits - Stop2 = 0x2, - /// 1.5 stop bits - Stop1p5 = 0x3, - }; - - pub const WAKE = enum(u1) { - /// USART wakeup on idle line - IdleLine = 0x0, - /// USART wakeup on address mark - AddressMark = 0x1, - }; - - /// Universal asynchronous receiver transmitter - pub const UART = extern struct { - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise error flag - NE: u1, - /// Overrun error - ORE: u1, - /// Idle line detected - IDLE: u1, - /// Read data register not empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding: u22, + /// Timer X Period Register + PER: mmio.Mmio(packed struct(u32) { + /// Timerx Period value + PER: u16, + padding: u16, }), - /// Data register - DR: mmio.Mmio(packed struct(u32) { - /// Data value - DR: u9, - padding: u23, + /// Timer X Repetition Register + REP: mmio.Mmio(packed struct(u32) { + /// Timerx Repetition counter value + REP: u8, + padding: u24, }), - /// Baud rate register - BRR: mmio.Mmio(packed struct(u32) { - /// USARTDIV - BRR: u16, + /// Timer X Compare X Register + CMP: mmio.Mmio(packed struct(u32) { + /// Timerx Compare X value + CMP: u16, padding: u16, }), - /// Control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: packed union { + /// Timer X Compare X Compound Register + CMPC: mmio.Mmio(packed struct(u32) { + /// Timerx Compare X value + CMP: u16, + /// Timerx Repetition value (aliased from HRTIM_REPx register) + REP: u8, + padding: u8, + }), + reserved48: [12]u8, + /// Timer X Capture X Register + CPT: [2]mmio.Mmio(packed struct(u32) { + /// Timerx Capture X value + CPT: u16, + padding: u16, + }), + /// Timer X Deadtime Register + DT: mmio.Mmio(packed struct(u32) { + /// Deadtime Rising value + DTR: u9, + /// Sign Deadtime Rising value + SDTR: packed union { raw: u1, - value: RWU, + value: SDTR, }, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: packed union { + /// Deadtime Prescaler + DTPRSC: u3, + reserved14: u1, + /// Deadtime Rising Sign Lock + DTRSLK: u1, + /// Deadtime Rising Lock + DTRLK: u1, + /// Deadtime Falling value + DTF: u9, + /// Sign Deadtime Falling value + SDTF: packed union { raw: u1, - value: PS, + value: SDTF, }, - /// Parity control enable - PCE: u1, - /// Receiver wakeup method - WAKE: packed union { + reserved30: u4, + /// Deadtime Falling Sign Lock + DTFSLK: u1, + /// Deadtime Falling Lock + DTFLK: u1, + }), + /// Timer X Output X Set Register + SETR: mmio.Mmio(packed struct(u32) { + /// Software Set trigger + SST: packed union { raw: u1, - value: WAKE, + value: ACTIVEEFFECT, }, - /// Word length - M0: packed union { + /// Timer X resynchronizaton + RESYNC: packed union { raw: u1, - value: M0, + value: ACTIVEEFFECT, }, - /// USART enable - UE: u1, - padding: u18, - }), - /// Control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Address of the USART node - ADD: u4, - reserved5: u1, - /// Line break detection length - LBDL: packed union { + /// Timer X Period + PER: packed union { raw: u1, - value: LBDL, + value: ACTIVEEFFECT, }, - /// LIN break detection interrupt enable - LBDIE: u1, - reserved12: u5, - /// STOP bits - STOP: packed union { - raw: u2, - value: STOP, + /// Timer X compare X + CMP: packed union { + raw: u1, + value: ACTIVEEFFECT, }, - /// LIN mode enable - LINEN: u1, - padding: u17, - }), - /// Control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: packed union { + reserved7: u3, + /// Master Period + MSTPER: packed union { raw: u1, - value: IRLP, + value: ACTIVEEFFECT, }, - /// Half-duplex selection - HDSEL: u1, - reserved6: u2, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - padding: u24, - }), - }; - - /// Universal synchronous asynchronous receiver transmitter - pub const USART = extern struct { - reserved16: [16]u8, - /// Control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: packed union { + /// Master Compare X + MSTCMPX: packed union { raw: u1, - value: CPHA, + value: ACTIVEEFFECT, }, - /// Clock polarity - CPOL: packed union { + reserved12: u3, + /// Timer Event X + TIMEVNT: packed union { raw: u1, - value: CPOL, + value: ACTIVEEFFECT, + }, + reserved21: u8, + /// External Event X + EXTEVNT: packed union { + raw: u1, + value: ACTIVEEFFECT, + }, + reserved31: u9, + /// Registers update (transfer preload to active) + UPDATE: packed union { + raw: u1, + value: ACTIVEEFFECT, }, - /// Clock enable - CLKEN: u1, - padding: u20, }), - /// Control register 3 - CR3: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - reserved8: u2, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - padding: u21, + /// Timer X Output X Reset Register + RSTR: mmio.Mmio(packed struct(u32) { + /// Software Reset trigger + SRT: packed union { + raw: u1, + value: INACTIVEEFFECT, + }, + /// Timer X resynchronizaton + RESYNC: packed union { + raw: u1, + value: INACTIVEEFFECT, + }, + /// Timer X Period + PER: packed union { + raw: u1, + value: INACTIVEEFFECT, + }, + /// Timer X compare X + CMP: packed union { + raw: u1, + value: INACTIVEEFFECT, + }, + reserved7: u3, + /// Master Period + MSTPER: packed union { + raw: u1, + value: INACTIVEEFFECT, + }, + /// Master Compare X + MSTCMP: packed union { + raw: u1, + value: INACTIVEEFFECT, + }, + reserved12: u3, + /// Timer Event X + TIMEVNT: packed union { + raw: u1, + value: INACTIVEEFFECT, + }, + reserved21: u8, + /// External Event X + EXTEVNT: packed union { + raw: u1, + value: INACTIVEEFFECT, + }, + reserved31: u9, + /// Registers update (transfer preload to active) + UPDATE: packed union { + raw: u1, + value: INACTIVEEFFECT, + }, }), - /// Guard time and prescaler register - GTPR: mmio.Mmio(packed struct(u32) { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding: u16, + reserved76: [8]u8, + /// Timer X External Event Filtering Register 1 + EEF: mmio.Mmio(packed struct(u32) { + /// External Event X latch + LTCH: u1, + /// External Event X filter + FLTR: packed union { + raw: u4, + value: EEFLTR, + }, + padding: u27, }), - }; - }; - - pub const comp_h7_a = struct { - pub const BLANKING = enum(u4) { - NoBlanking = 0x0, - Tim1Oc5 = 0x1, - Tim2Oc3 = 0x2, - Tim3Oc3 = 0x3, - Tim3Oc4 = 0x4, - Tim8Oc5 = 0x5, - Tim15Oc1 = 0x6, - _, - }; - - pub const HYST = enum(u2) { - None = 0x0, - Low = 0x1, - Medium = 0x2, - High = 0x3, - }; - - pub const INMSEL = enum(u4) { - VRef_1over4 = 0x0, - VRef_1over2 = 0x1, - VRef_3over4 = 0x2, - VRef = 0x3, - Inm4 = 0x4, - Inm5 = 0x5, - Inm6 = 0x6, - Inm7 = 0x7, - Inm8 = 0x8, - Inm9 = 0x9, - _, - }; - - pub const INPSEL = enum(u1) { - INP1 = 0x0, - INP2 = 0x1, - }; - - pub const PWRMODE = enum(u2) { - /// High speed / full power - High = 0x0, - /// Medium speed / medium power - Medium = 0x1, - /// Medium speed / medium power - MediumEither = 0x2, - /// Ultra low power / ultra-low-power - Low = 0x3, - }; - - /// COMP1. - pub const COMP = extern struct { - /// Comparator status register. - SR: mmio.Mmio(packed struct(u32) { - /// COMP channel 1 output status bit. - CVAL: u1, - reserved16: u15, - /// COMP channel 1 Interrupt Flag. - CIF: u1, - padding: u15, - }), - /// Comparator interrupt clear flag register. - ICFR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Clear COMP channel 1 Interrupt Flag. - CCIF: u1, - padding: u15, + reserved84: [4]u8, + /// Timer X Reset Register + RST: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Timer X Update reset + UPDT: packed union { + raw: u1, + value: RESETEFFECT, + }, + /// Timer X compare X reset + CMP: packed union { + raw: u1, + value: RESETEFFECT, + }, + reserved4: u1, + /// Master timer Period + MSTPER: packed union { + raw: u1, + value: RESETEFFECT, + }, + /// Master compare X + MSTCMP: packed union { + raw: u1, + value: RESETEFFECT, + }, + reserved9: u3, + /// External Event X + EXTEVNT: packed union { + raw: u1, + value: RESETEFFECT, + }, + reserved19: u9, + /// Timer X compare 1 event + TCMP1: packed union { + raw: u1, + value: RESETEFFECT, + }, + /// Timer X compare 2 event + TCMP2: packed union { + raw: u1, + value: RESETEFFECT, + }, + /// Timer X compare 4 event + TCMP4: packed union { + raw: u1, + value: RESETEFFECT, + }, + padding: u10, }), - /// Comparator option register. - OR: mmio.Mmio(packed struct(u32) { - /// Selection of source for alternate function of output ports. - AFOP: u11, + /// Timer X Chopper Register + CHP: mmio.Mmio(packed struct(u32) { + /// Timerx carrier frequency value + CARFRQ: u4, + /// Timerx chopper duty cycle value + CARDTY: u3, + /// Timerx start pulsewidth + STRTPW: u4, padding: u21, }), - /// Comparator configuration register 1. - CFGR1: mmio.Mmio(packed struct(u32) { - /// COMP channel 1 enable bit. - EN: u1, - /// Scaler bridge enable. - BRGEN: u1, - /// Voltage scaler enable bit. - SCALEN: u1, - /// COMP channel 1 polarity selection bit. - POLARITY: u1, - reserved6: u2, - /// COMP channel 1 interrupt enable. - ITEN: u1, - reserved8: u1, - /// COMP channel 1 hysteresis selection bits. - HYST: packed union { - raw: u2, - value: HYST, + /// Timer X Capture X Control Register + CCR: mmio.Mmio(packed struct(u32) { + /// Software Capture + SWCPT: packed union { + raw: u1, + value: CAPTUREEFFECT, }, - reserved12: u2, - /// Power Mode of the COMP channel 1. - PWRMODE: packed union { - raw: u2, - value: PWRMODE, + /// Update Capture + UPDCPT: packed union { + raw: u1, + value: CAPTUREEFFECT, }, - reserved16: u2, - /// COMP channel 1 inverting input selection field. - INMSEL: packed union { - raw: u4, - value: INMSEL, + /// External Event X Capture + EXEVCPT: packed union { + raw: u1, + value: CAPTUREEFFECT, }, - /// COMP channel 1 non-inverting input selection bit. - INPSEL: packed union { + reserved16: u13, + /// Timer X output Set + TXSET: packed union { raw: u1, - value: INPSEL, + value: CAPTUREEFFECT, }, - reserved24: u3, - /// COMP channel 1 blanking source selection bits. - BLANKING: packed union { - raw: u4, - value: BLANKING, + /// Timer X output Reset + TXRST: packed union { + raw: u1, + value: CAPTUREEFFECT, }, - reserved31: u3, - /// Lock bit. - LOCK: u1, - }), - /// Comparator configuration register 2. - CFGR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Window comparator mode selection bit. - WINMODE: u1, - padding: u27, - }), - }; - }; - - pub const iwdg_v2 = struct { - pub const KEY = enum(u16) { - /// Enable access to PR, RLR and WINR registers (0x5555) - Enable = 0x5555, - /// Reset the watchdog value (0xAAAA) - Reset = 0xaaaa, - /// Start the watchdog (0xCCCC) - Start = 0xcccc, - _, - }; - - pub const PR = enum(u3) { - /// Divider /4 - DivideBy4 = 0x0, - /// Divider /8 - DivideBy8 = 0x1, - /// Divider /16 - DivideBy16 = 0x2, - /// Divider /32 - DivideBy32 = 0x3, - /// Divider /64 - DivideBy64 = 0x4, - /// Divider /128 - DivideBy128 = 0x5, - /// Divider /256 - DivideBy256 = 0x6, - /// Divider /256 - DivideBy256bis = 0x7, - }; - - /// Independent watchdog - pub const IWDG = extern struct { - /// Key register - KR: mmio.Mmio(packed struct(u32) { - /// Key value (write only, read 0000h) - KEY: packed union { - raw: u16, - value: KEY, + /// Timer X Compare X + TXCMP: packed union { + raw: u1, + value: CAPTUREEFFECT, }, - padding: u16, + reserved20: u1, + /// Timer Y output Set + TYSET: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + /// Timer Y output Reset + TYRST: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + /// Timer Y Compare X + TYCMP: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + reserved24: u1, + /// Timer Z output Set + TZSET: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + /// Timer Z output Reset + TZRST: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + /// Timer Z Compare X + TZCMP: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + reserved28: u1, + /// Timer T output Set + TTSET: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + /// Timer T output Reset + TTRST: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + /// Timer T Compare X + TTCMP: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + padding: u1, }), - /// Prescaler register - PR: mmio.Mmio(packed struct(u32) { - /// Prescaler divider - PR: packed union { + reserved100: [4]u8, + /// Timer X Output Register + OUTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Output 1 polarity + POL: packed union { + raw: u1, + value: POL, + }, + /// Output X Idle mode + IDLEM: u1, + /// Output X Idle State + IDLES: u1, + /// Output X Fault state + FAULTX: packed union { + raw: u2, + value: FAULT, + }, + /// Output X Chopper enable + CHP: u1, + /// Output X Deadtime upon burst mode Idle entry + DIDL: u1, + /// Deadtime enable + DTEN: u1, + /// Delayed Protection Enable + DLYPRTEN: u1, + /// Delayed Protection + DLYPRT: packed union { raw: u3, - value: PR, + value: DLYPRT, }, - padding: u29, - }), - /// Reload register - RLR: mmio.Mmio(packed struct(u32) { - /// Watchdog counter reload value - RL: u12, - padding: u20, - }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Watchdog prescaler value update - PVU: u1, - /// Watchdog counter reload value update - RVU: u1, - /// Watchdog counter window value update - WVU: u1, - padding: u29, + padding: u19, }), - /// Window register - WINR: mmio.Mmio(packed struct(u32) { - /// Watchdog counter window value - WIN: u12, - padding: u20, + /// Timer X Fault Register + FLT: mmio.Mmio(packed struct(u32) { + /// Fault X enable + FLTEN: packed union { + raw: u1, + value: FLTEN, + }, + reserved31: u30, + /// Fault sources Lock + FLTLCK: u1, }), }; }; - pub const rcc_h5 = struct { - pub const ADCDACSEL = enum(u3) { - /// rcc_hclk selected as kernel clock (default after reset) - HCLK2 = 0x0, - /// sys_ck selected as kernel clock - SYS = 0x1, - /// pll2_r_ck selected as kernel clock - PLL2_R = 0x2, - /// hse_ck selected as kernel clock - HSE = 0x3, - /// hsi_ker_ck selected as kernel clock - HSI = 0x4, - /// csi_ker_ck selected as kernel clock - CSI = 0x5, - _, + pub const hrtim_v2 = struct { + pub const ACTIVEEFFECT = enum(u1) { + /// Timer event has no effect + NoEffect = 0x0, + /// Timer event forces the output to its active state + SetActive = 0x1, }; - pub const CECSEL = enum(u2) { - /// lse_ck selected as kernel clock (default after reset) - LSE = 0x0, - /// lsi_ker_ck selected as kernel clock - LSI = 0x1, - /// csi_ker_ck/122 selected as kernel clock - CSI_DIV_122 = 0x2, + pub const BRSTDMA = enum(u2) { + /// Update done independently from the DMA burst transfer completion + Independent = 0x0, + /// Update done when the DMA burst transfer is completed + Completion = 0x1, + /// Update done on master timer roll-over following a DMA burst transfer completion + Rollover = 0x2, _, }; - pub const DACHOLDSEL = enum(u1) { - /// dac_hold_ck selected as kernel clock (default after reset) - DAC_HOLD = 0x0, - /// dac_hold_ck selected as kernel clock - DAC_HOLD_2 = 0x1, + pub const CAPTUREEFFECT = enum(u1) { + /// Timer event has no effect + NoEffect = 0x0, + /// Timer event triggers capture + TriggerCapture = 0x1, }; - pub const FDCANSEL = enum(u2) { - /// hse_ck selected as kernel clock (default after reset) - HSE = 0x0, - /// pll1_q_ck selected as kernel clock - PLL1_Q = 0x1, - /// pll2_q_ck selected as kernel clock - PLL2_Q = 0x2, - _, + pub const CPPSTAT = enum(u1) { + /// Signal applied on output 1 and output 2 forced inactive + Output1Active = 0x0, + /// Signal applied on output 2 and output 1 forced inactive + Output2Active = 0x1, }; - pub const HPRE = enum(u4) { - /// sys_ck not divided - Div1 = 0x0, - /// sys_ck divided by 2 - Div2 = 0x8, - /// sys_ck divided by 4 - Div4 = 0x9, - /// sys_ck divided by 8 - Div8 = 0xa, - /// sys_ck divided by 16 - Div16 = 0xb, - /// sys_ck divided by 64 - Div64 = 0xc, - /// sys_ck divided by 128 - Div128 = 0xd, - /// sys_ck divided by 256 - Div256 = 0xe, - /// sys_ck divided by 512 - Div512 = 0xf, - _, + pub const DACSYNC = enum(u2) { + /// No DAC trigger generated + Disabled = 0x0, + /// Trigger generated on DACSync1 + DACSync1 = 0x1, + /// Trigger generated on DACSync2 + DACSync2 = 0x2, + /// Trigger generated on DACSync3 + DACSync3 = 0x3, }; - pub const HSEEXT = enum(u1) { - /// HSE in analog mode (default after reset) - Analog = 0x0, - /// HSE in digital mode - Digital = 0x1, + pub const DELCMP = enum(u2) { + /// CMP register is always active (standard compare mode) + Standard = 0x0, + /// CMP is recomputed and is active following a capture 1 event + Capture1 = 0x1, + /// CMP is recomputed and is active following a capture 1 event or a Compare 1 match + CaptureX_Compare1 = 0x2, + /// CMP is recomputed and is active following a capture 1 event or a Compare 3 match + CaptureX_Compare3 = 0x3, }; - pub const HSIDIV = enum(u2) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x1, - /// Division by 4 - Div4 = 0x2, - /// Division by 8 - Div8 = 0x3, + pub const DLYPRT = enum(u3) { + /// Output 1 delayed idle on external event 6 + Output1_EE6 = 0x0, + /// Output 2 delayed idle on external event 6 + Output2_EE6 = 0x1, + /// Output 1 and 2 delayed idle on external event 6 + Output1_2_EE6 = 0x2, + /// Balanced idle on external event 6 + Balanced_EE6 = 0x3, + /// Output 1 delayed idle on external event 7 + Output1_EE7 = 0x4, + /// Output 2 delayed idle on external event 7 + Output2_EE7 = 0x5, + /// Output 1 and 2 delayed idle on external event 7 + Output1_2_EE7 = 0x6, + /// Balanced idle on external event 7 + Balanced_EE7 = 0x7, }; - pub const I2C34SEL = enum(u2) { - /// rcc_pclk3 selected as peripheral clock - PCLK3 = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// hsi_ker selected as peripheral clock - HSI = 0x2, - /// csi_ker selected as peripheral clock - CSI = 0x3, + pub const EEFLTR = enum(u4) { + /// No filtering + Disabled = 0x0, + /// Blanking from counter reset/roll-over to Compare 1 + BlankResetToCompare1 = 0x1, + /// Blanking from counter reset/roll-over to Compare 2 + BlankResetToCompare2 = 0x2, + /// Blanking from counter reset/roll-over to Compare 3 + BlankResetToCompare3 = 0x3, + /// Blanking from counter reset/roll-over to Compare 4 + BlankResetToCompare4 = 0x4, + /// Blanking from another timing unit: TIMFLTR1 source + BlankTIMFLTR1 = 0x5, + /// Blanking from another timing unit: TIMFLTR2 source + BlankTIMFLTR2 = 0x6, + /// Blanking from another timing unit: TIMFLTR3 source + BlankTIMFLTR3 = 0x7, + /// Blanking from another timing unit: TIMFLTR4 source + BlankTIMFLTR4 = 0x8, + /// Blanking from another timing unit: TIMFLTR5 source + BlankTIMFLTR5 = 0x9, + /// Blanking from another timing unit: TIMFLTR6 source + BlankTIMFLTR6 = 0xa, + /// Blanking from another timing unit: TIMFLTR7 source + BlankTIMFLTR7 = 0xb, + /// Blanking from another timing unit: TIMFLTR8 source + BlankTIMFLTR8 = 0xc, + /// Windowing from counter reset/roll-over to compare 2 + WindowResetToCompare2 = 0xd, + /// Windowing from counter reset/roll-over to compare 3 + WindowResetToCompare3 = 0xe, + /// Windowing from another timing unit: TIMWIN source + WindowTIMWIN = 0xf, }; - pub const I2CSEL = enum(u2) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// hsi_ker selected as peripheral clock - HSI = 0x2, - /// csi_ker selected as peripheral clock - CSI = 0x3, + pub const FAULT = enum(u2) { + /// No action: the output is not affected by the fault input and stays in run mode + Disabled = 0x0, + /// Output goes to active state after a fault event + SetActive = 0x1, + /// Output goes to inactive state after a fault event + SetInactive = 0x2, + /// Output goes to high-z state after a fault event + SetHighZ = 0x3, }; - pub const LPTIM2SEL = enum(u3) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// LSE selected as peripheral clock - LSE = 0x3, - /// LSI selected as peripheral clock - LSI = 0x4, - /// PER selected as peripheral clock - PER = 0x5, - _, + pub const FLTEN = enum(u1) { + /// Fault input ignored + Ignored = 0x0, + /// Fault input is active and can disable HRTIM outputs + Active = 0x1, }; - pub const LPTIMSEL = enum(u3) { - /// rcc_pclk3 selected as peripheral clock - PCLK3 = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_r selected as peripheral clock - PLL3_R = 0x2, - /// LSE selected as peripheral clock - LSE = 0x3, - /// LSI selected as peripheral clock - LSI = 0x4, - /// PER selected as peripheral clock - PER = 0x5, - _, + pub const INACTIVEEFFECT = enum(u1) { + /// Timer event has no effect + NoEffect = 0x0, + /// Timer event forces the output to its inactive state + SetInactive = 0x1, }; - pub const LPUSARTSEL = enum(u3) { - /// rcc_pclk3 selected as kernel clock (default after reset) - PCLK3 = 0x0, - /// pll2_q_ck selected as kernel clock - PLL2_Q = 0x1, - /// pll3_q_ck selected as kernel clock - PLL3_Q = 0x2, - /// hsi_ker_ck selected as kernel clock - HSI = 0x3, - /// csi_ker_ck selected as kernel clock - CSI = 0x4, - /// lse_ck selected as kernel clock - LSE = 0x5, - _, + pub const IPPSTAT = enum(u1) { + /// Protection occurred when the output 1 was active and output 2 forced inactive + Output1Active = 0x0, + /// Protection occurred when the output 2 was active and output 1 forced inactive + Output2Active = 0x1, }; - pub const LSCOSEL = enum(u1) { - /// LSI clock selected - LSI = 0x0, - /// LSE clock selected - LSE = 0x1, + pub const OUTPUTSTATE = enum(u1) { + /// Output is or was inactive + Inactive = 0x0, + /// Output is or was active + Active = 0x1, }; - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, + pub const POL = enum(u1) { + /// Positive polarity (output active high) + ActiveHigh = 0x0, + /// Negative polarity (output active low) + ActiveLow = 0x1, }; - pub const LSEEXT = enum(u1) { - /// LSE in analog mode (default after Backup domain reset) - Analog = 0x0, - /// LSE in digital mode (do not use if RTC is active). - Digital = 0x1, + pub const RESETEFFECT = enum(u1) { + /// Timer Y compare Z event has no effect + NoEffect = 0x0, + /// Timer X counter is reset upon timer Y compare Z event + ResetCounter = 0x1, }; - pub const MCO1SEL = enum(u3) { - /// HSI selected for micro-controller clock output - HSI = 0x0, - /// LSE selected for micro-controller clock output - LSE = 0x1, - /// HSE selected for micro-controller clock output - HSE = 0x2, - /// pll1_q selected for micro-controller clock output - PLL1_Q = 0x3, - /// HSI48 selected for micro-controller clock output - HSI48 = 0x4, - _, + pub const SDTF = enum(u1) { + /// Positive deadtime on falling edge + Positive = 0x0, + /// Negative deadtime on falling edge + Negative = 0x1, }; - pub const MCO2SEL = enum(u3) { - /// System clock selected for micro-controller clock output - SYS = 0x0, - /// pll2_p selected for micro-controller clock output - PLL2_P = 0x1, - /// HSE selected for micro-controller clock output - HSE = 0x2, - /// pll1_p selected for micro-controller clock output - PLL1_P = 0x3, - /// CSI selected for micro-controller clock output - CSI = 0x4, - /// LSI selected for micro-controller clock output - LSI = 0x5, + pub const SDTR = enum(u1) { + /// Positive deadtime on rising edge + Positive = 0x0, + /// Negative deadtime on rising edge + Negative = 0x1, + }; + + pub const SYNCIN = enum(u2) { + /// Disabled. HRTIM is not synchronized and runs in standalone mode + Disabled = 0x0, + /// Internal event: the HRTIM is synchronized with the on-chip timer + Internal = 0x2, + /// External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM + External = 0x3, _, }; - pub const MCOPRE = enum(u4) { - /// Divide by 1 - Div1 = 0x1, - /// Divide by 2 - Div2 = 0x2, - /// Divide by 3 - Div3 = 0x3, - /// Divide by 4 - Div4 = 0x4, - /// Divide by 5 - Div5 = 0x5, - /// Divide by 6 - Div6 = 0x6, - /// Divide by 7 - Div7 = 0x7, - /// Divide by 8 - Div8 = 0x8, - /// Divide by 9 - Div9 = 0x9, - /// Divide by 10 - Div10 = 0xa, - /// Divide by 11 - Div11 = 0xb, - /// Divide by 12 - Div12 = 0xc, - /// Divide by 13 - Div13 = 0xd, - /// Divide by 14 - Div14 = 0xe, - /// Divide by 15 - Div15 = 0xf, + pub const SYNCOUT = enum(u2) { + /// Disabled + Disabled = 0x0, + /// Positive pulse on SCOUT output (16x f_HRTIM clock cycles) + PositivePulse = 0x2, + /// Negative pulse on SCOUT output (16x f_HRTIM clock cycles) + NegativePulse = 0x3, _, }; - pub const NSPRIV = enum(u1) { - /// Read and write to RCC non-secure functions can be done by privileged or unprivileged access. - B_0x0 = 0x0, - /// Read and write to RCC non-secure functions can be done by privileged access only - B_0x1 = 0x1, + pub const SYNCRST = enum(u1) { + /// Synchronization event has no effect on Timer x + Disabled = 0x0, + /// Synchronization event resets Timer x + Reset = 0x1, }; - pub const OCTOSPISEL = enum(u2) { - /// rcc_hclk selected as kernel clock (default after reset) - HCLK4 = 0x0, - /// pll1_q_ck selected as kernel clock - PLL1_Q = 0x1, - /// pll2_r_ck selected as kernel clock - PLL2_R = 0x2, - /// per_ck selected as kernel clock - PER = 0x3, + pub const SYNCSRC = enum(u2) { + /// Master timer Start + MasterStart = 0x0, + /// Master timer Compare 1 event + MasterCompare1 = 0x1, + /// Timer A start/reset + TimerAStart = 0x2, + /// Timer A Compare 1 event + TimerACompare1 = 0x3, }; - pub const PERSEL = enum(u2) { - /// hsi_ker_ck selected as kernel clock (default after reset) - HSI = 0x0, - /// csi_ker_ck selected as kernel clock - CSI = 0x1, - /// hse_ck selected as kernel clock - HSE = 0x2, - _, + pub const SYNCSTRT = enum(u1) { + /// Synchronization event has no effect on Timer x + Disabled = 0x0, + /// Synchronization event starts Timer x + Start = 0x1, }; - pub const PLLDIV = enum(u7) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, - Div17 = 0x10, - Div18 = 0x11, - Div19 = 0x12, - Div20 = 0x13, - Div21 = 0x14, - Div22 = 0x15, - Div23 = 0x16, - Div24 = 0x17, - Div25 = 0x18, - Div26 = 0x19, - Div27 = 0x1a, - Div28 = 0x1b, - Div29 = 0x1c, - Div30 = 0x1d, - Div31 = 0x1e, - Div32 = 0x1f, - Div33 = 0x20, - Div34 = 0x21, - Div35 = 0x22, - Div36 = 0x23, - Div37 = 0x24, - Div38 = 0x25, - Div39 = 0x26, - Div40 = 0x27, - Div41 = 0x28, - Div42 = 0x29, - Div43 = 0x2a, - Div44 = 0x2b, - Div45 = 0x2c, - Div46 = 0x2d, - Div47 = 0x2e, - Div48 = 0x2f, - Div49 = 0x30, - Div50 = 0x31, - Div51 = 0x32, - Div52 = 0x33, - Div53 = 0x34, - Div54 = 0x35, - Div55 = 0x36, - Div56 = 0x37, - Div57 = 0x38, - Div58 = 0x39, - Div59 = 0x3a, - Div60 = 0x3b, - Div61 = 0x3c, - Div62 = 0x3d, - Div63 = 0x3e, - Div64 = 0x3f, - Div65 = 0x40, - Div66 = 0x41, - Div67 = 0x42, - Div68 = 0x43, - Div69 = 0x44, - Div70 = 0x45, - Div71 = 0x46, - Div72 = 0x47, - Div73 = 0x48, - Div74 = 0x49, - Div75 = 0x4a, - Div76 = 0x4b, - Div77 = 0x4c, - Div78 = 0x4d, - Div79 = 0x4e, - Div80 = 0x4f, - Div81 = 0x50, - Div82 = 0x51, - Div83 = 0x52, - Div84 = 0x53, - Div85 = 0x54, - Div86 = 0x55, - Div87 = 0x56, - Div88 = 0x57, - Div89 = 0x58, - Div90 = 0x59, - Div91 = 0x5a, - Div92 = 0x5b, - Div93 = 0x5c, - Div94 = 0x5d, - Div95 = 0x5e, - Div96 = 0x5f, - Div97 = 0x60, - Div98 = 0x61, - Div99 = 0x62, - Div100 = 0x63, - Div101 = 0x64, - Div102 = 0x65, - Div103 = 0x66, - Div104 = 0x67, - Div105 = 0x68, - Div106 = 0x69, - Div107 = 0x6a, - Div108 = 0x6b, - Div109 = 0x6c, - Div110 = 0x6d, - Div111 = 0x6e, - Div112 = 0x6f, - Div113 = 0x70, - Div114 = 0x71, - Div115 = 0x72, - Div116 = 0x73, - Div117 = 0x74, - Div118 = 0x75, - Div119 = 0x76, - Div120 = 0x77, - Div121 = 0x78, - Div122 = 0x79, - Div123 = 0x7a, - Div124 = 0x7b, - Div125 = 0x7c, - Div126 = 0x7d, - Div127 = 0x7e, - Div128 = 0x7f, + pub const TIMAISR_DLYPRT = enum(u1) { + /// Not in delayed idle or balanced idle mode + Inactive = 0x0, + /// Delayed idle or balanced idle mode entry + Active = 0x1, }; - pub const PLLM = enum(u6) { - Div1 = 0x1, - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - Div16 = 0x10, - Div17 = 0x11, - Div18 = 0x12, - Div19 = 0x13, - Div20 = 0x14, - Div21 = 0x15, - Div22 = 0x16, - Div23 = 0x17, - Div24 = 0x18, - Div25 = 0x19, - Div26 = 0x1a, - Div27 = 0x1b, - Div28 = 0x1c, - Div29 = 0x1d, - Div30 = 0x1e, - Div31 = 0x1f, - Div32 = 0x20, - Div33 = 0x21, - Div34 = 0x22, - Div35 = 0x23, - Div36 = 0x24, - Div37 = 0x25, - Div38 = 0x26, - Div39 = 0x27, - Div40 = 0x28, - Div41 = 0x29, - Div42 = 0x2a, - Div43 = 0x2b, - Div44 = 0x2c, - Div45 = 0x2d, - Div46 = 0x2e, - Div47 = 0x2f, - Div48 = 0x30, - Div49 = 0x31, - Div50 = 0x32, - Div51 = 0x33, - Div52 = 0x34, - Div53 = 0x35, - Div54 = 0x36, - Div55 = 0x37, - Div56 = 0x38, - Div57 = 0x39, - Div58 = 0x3a, - Div59 = 0x3b, - Div60 = 0x3c, - Div61 = 0x3d, - Div62 = 0x3e, + pub const UPDGAT = enum(u4) { + /// Update occurs independently from the DMA burst transfer + Independent = 0x0, + /// Update occurs when the DMA burst transfer is completed + DMABurst = 0x1, + /// Update occurs on the update event following DMA burst transfer completion + DMABurst_Update = 0x2, + /// Update occurs on a rising edge of HRTIM update enable input 1 + Input1 = 0x3, + /// Update occurs on a rising edge of HRTIM update enable input 2 + Input2 = 0x4, + /// Update occurs on a rising edge of HRTIM update enable input 3 + Input3 = 0x5, + /// Update occurs on the update event following a rising edge of HRTIM update enable input 1 + Input1_Update = 0x6, + /// Update occurs on the update event following a rising edge of HRTIM update enable input 2 + Input2_Update = 0x7, + /// Update occurs on the update event following a rising edge of HRTIM update enable input 3 + Input3_Update = 0x8, _, }; - pub const PLLN = enum(u9) { - Mul4 = 0x3, - Mul5 = 0x4, - Mul6 = 0x5, - Mul7 = 0x6, - Mul8 = 0x7, - Mul9 = 0x8, - Mul10 = 0x9, - Mul11 = 0xa, - Mul12 = 0xb, - Mul13 = 0xc, - Mul14 = 0xd, - Mul15 = 0xe, - Mul16 = 0xf, - Mul17 = 0x10, - Mul18 = 0x11, - Mul19 = 0x12, - Mul20 = 0x13, - Mul21 = 0x14, - Mul22 = 0x15, - Mul23 = 0x16, - Mul24 = 0x17, - Mul25 = 0x18, - Mul26 = 0x19, - Mul27 = 0x1a, - Mul28 = 0x1b, - Mul29 = 0x1c, - Mul30 = 0x1d, - Mul31 = 0x1e, - Mul32 = 0x1f, - Mul33 = 0x20, - Mul34 = 0x21, - Mul35 = 0x22, - Mul36 = 0x23, - Mul37 = 0x24, - Mul38 = 0x25, - Mul39 = 0x26, - Mul40 = 0x27, - Mul41 = 0x28, - Mul42 = 0x29, - Mul43 = 0x2a, - Mul44 = 0x2b, - Mul45 = 0x2c, - Mul46 = 0x2d, - Mul47 = 0x2e, - Mul48 = 0x2f, - Mul49 = 0x30, - Mul50 = 0x31, - Mul51 = 0x32, - Mul52 = 0x33, - Mul53 = 0x34, - Mul54 = 0x35, - Mul55 = 0x36, - Mul56 = 0x37, - Mul57 = 0x38, - Mul58 = 0x39, - Mul59 = 0x3a, - Mul60 = 0x3b, - Mul61 = 0x3c, - Mul62 = 0x3d, - Mul63 = 0x3e, - Mul64 = 0x3f, - Mul65 = 0x40, - Mul66 = 0x41, - Mul67 = 0x42, - Mul68 = 0x43, - Mul69 = 0x44, - Mul70 = 0x45, - Mul71 = 0x46, - Mul72 = 0x47, - Mul73 = 0x48, - Mul74 = 0x49, - Mul75 = 0x4a, - Mul76 = 0x4b, - Mul77 = 0x4c, - Mul78 = 0x4d, - Mul79 = 0x4e, - Mul80 = 0x4f, - Mul81 = 0x50, - Mul82 = 0x51, - Mul83 = 0x52, - Mul84 = 0x53, - Mul85 = 0x54, - Mul86 = 0x55, - Mul87 = 0x56, - Mul88 = 0x57, - Mul89 = 0x58, - Mul90 = 0x59, - Mul91 = 0x5a, - Mul92 = 0x5b, - Mul93 = 0x5c, - Mul94 = 0x5d, - Mul95 = 0x5e, - Mul96 = 0x5f, - Mul97 = 0x60, - Mul98 = 0x61, - Mul99 = 0x62, - Mul100 = 0x63, - Mul101 = 0x64, - Mul102 = 0x65, - Mul103 = 0x66, - Mul104 = 0x67, - Mul105 = 0x68, - Mul106 = 0x69, - Mul107 = 0x6a, - Mul108 = 0x6b, - Mul109 = 0x6c, - Mul110 = 0x6d, - Mul111 = 0x6e, - Mul112 = 0x6f, - Mul113 = 0x70, - Mul114 = 0x71, - Mul115 = 0x72, - Mul116 = 0x73, - Mul117 = 0x74, - Mul118 = 0x75, - Mul119 = 0x76, - Mul120 = 0x77, - Mul121 = 0x78, - Mul122 = 0x79, - Mul123 = 0x7a, - Mul124 = 0x7b, - Mul125 = 0x7c, - Mul126 = 0x7d, - Mul127 = 0x7e, - Mul128 = 0x7f, - Mul129 = 0x80, - Mul130 = 0x81, - Mul131 = 0x82, - Mul132 = 0x83, - Mul133 = 0x84, - Mul134 = 0x85, - Mul135 = 0x86, - Mul136 = 0x87, - Mul137 = 0x88, - Mul138 = 0x89, - Mul139 = 0x8a, - Mul140 = 0x8b, - Mul141 = 0x8c, - Mul142 = 0x8d, - Mul143 = 0x8e, - Mul144 = 0x8f, - Mul145 = 0x90, - Mul146 = 0x91, - Mul147 = 0x92, - Mul148 = 0x93, - Mul149 = 0x94, - Mul150 = 0x95, - Mul151 = 0x96, - Mul152 = 0x97, - Mul153 = 0x98, - Mul154 = 0x99, - Mul155 = 0x9a, - Mul156 = 0x9b, - Mul157 = 0x9c, - Mul158 = 0x9d, - Mul159 = 0x9e, - Mul160 = 0x9f, - Mul161 = 0xa0, - Mul162 = 0xa1, - Mul163 = 0xa2, - Mul164 = 0xa3, - Mul165 = 0xa4, - Mul166 = 0xa5, - Mul167 = 0xa6, - Mul168 = 0xa7, - Mul169 = 0xa8, - Mul170 = 0xa9, - Mul171 = 0xaa, - Mul172 = 0xab, - Mul173 = 0xac, - Mul174 = 0xad, - Mul175 = 0xae, - Mul176 = 0xaf, - Mul177 = 0xb0, - Mul178 = 0xb1, - Mul179 = 0xb2, - Mul180 = 0xb3, - Mul181 = 0xb4, - Mul182 = 0xb5, - Mul183 = 0xb6, - Mul184 = 0xb7, - Mul185 = 0xb8, - Mul186 = 0xb9, - Mul187 = 0xba, - Mul188 = 0xbb, - Mul189 = 0xbc, - Mul190 = 0xbd, - Mul191 = 0xbe, - Mul192 = 0xbf, - Mul193 = 0xc0, - Mul194 = 0xc1, - Mul195 = 0xc2, - Mul196 = 0xc3, - Mul197 = 0xc4, - Mul198 = 0xc5, - Mul199 = 0xc6, - Mul200 = 0xc7, - Mul201 = 0xc8, - Mul202 = 0xc9, - Mul203 = 0xca, - Mul204 = 0xcb, - Mul205 = 0xcc, - Mul206 = 0xcd, - Mul207 = 0xce, - Mul208 = 0xcf, - Mul209 = 0xd0, - Mul210 = 0xd1, - Mul211 = 0xd2, - Mul212 = 0xd3, - Mul213 = 0xd4, - Mul214 = 0xd5, - Mul215 = 0xd6, - Mul216 = 0xd7, - Mul217 = 0xd8, - Mul218 = 0xd9, - Mul219 = 0xda, - Mul220 = 0xdb, - Mul221 = 0xdc, - Mul222 = 0xdd, - Mul223 = 0xde, - Mul224 = 0xdf, - Mul225 = 0xe0, - Mul226 = 0xe1, - Mul227 = 0xe2, - Mul228 = 0xe3, - Mul229 = 0xe4, - Mul230 = 0xe5, - Mul231 = 0xe6, - Mul232 = 0xe7, - Mul233 = 0xe8, - Mul234 = 0xe9, - Mul235 = 0xea, - Mul236 = 0xeb, - Mul237 = 0xec, - Mul238 = 0xed, - Mul239 = 0xee, - Mul240 = 0xef, - Mul241 = 0xf0, - Mul242 = 0xf1, - Mul243 = 0xf2, - Mul244 = 0xf3, - Mul245 = 0xf4, - Mul246 = 0xf5, - Mul247 = 0xf6, - Mul248 = 0xf7, - Mul249 = 0xf8, - Mul250 = 0xf9, - Mul251 = 0xfa, - Mul252 = 0xfb, - Mul253 = 0xfc, - Mul254 = 0xfd, - Mul255 = 0xfe, - Mul256 = 0xff, - Mul257 = 0x100, - Mul258 = 0x101, - Mul259 = 0x102, - Mul260 = 0x103, - Mul261 = 0x104, - Mul262 = 0x105, - Mul263 = 0x106, - Mul264 = 0x107, - Mul265 = 0x108, - Mul266 = 0x109, - Mul267 = 0x10a, - Mul268 = 0x10b, - Mul269 = 0x10c, - Mul270 = 0x10d, - Mul271 = 0x10e, - Mul272 = 0x10f, - Mul273 = 0x110, - Mul274 = 0x111, - Mul275 = 0x112, - Mul276 = 0x113, - Mul277 = 0x114, - Mul278 = 0x115, - Mul279 = 0x116, - Mul280 = 0x117, - Mul281 = 0x118, - Mul282 = 0x119, - Mul283 = 0x11a, - Mul284 = 0x11b, - Mul285 = 0x11c, - Mul286 = 0x11d, - Mul287 = 0x11e, - Mul288 = 0x11f, - Mul289 = 0x120, - Mul290 = 0x121, - Mul291 = 0x122, - Mul292 = 0x123, - Mul293 = 0x124, - Mul294 = 0x125, - Mul295 = 0x126, - Mul296 = 0x127, - Mul297 = 0x128, - Mul298 = 0x129, - Mul299 = 0x12a, - Mul300 = 0x12b, - Mul301 = 0x12c, - Mul302 = 0x12d, - Mul303 = 0x12e, - Mul304 = 0x12f, - Mul305 = 0x130, - Mul306 = 0x131, - Mul307 = 0x132, - Mul308 = 0x133, - Mul309 = 0x134, - Mul310 = 0x135, - Mul311 = 0x136, - Mul312 = 0x137, - Mul313 = 0x138, - Mul314 = 0x139, - Mul315 = 0x13a, - Mul316 = 0x13b, - Mul317 = 0x13c, - Mul318 = 0x13d, - Mul319 = 0x13e, - Mul320 = 0x13f, - Mul321 = 0x140, - Mul322 = 0x141, - Mul323 = 0x142, - Mul324 = 0x143, - Mul325 = 0x144, - Mul326 = 0x145, - Mul327 = 0x146, - Mul328 = 0x147, - Mul329 = 0x148, - Mul330 = 0x149, - Mul331 = 0x14a, - Mul332 = 0x14b, - Mul333 = 0x14c, - Mul334 = 0x14d, - Mul335 = 0x14e, - Mul336 = 0x14f, - Mul337 = 0x150, - Mul338 = 0x151, - Mul339 = 0x152, - Mul340 = 0x153, - Mul341 = 0x154, - Mul342 = 0x155, - Mul343 = 0x156, - Mul344 = 0x157, - Mul345 = 0x158, - Mul346 = 0x159, - Mul347 = 0x15a, - Mul348 = 0x15b, - Mul349 = 0x15c, - Mul350 = 0x15d, - Mul351 = 0x15e, - Mul352 = 0x15f, - Mul353 = 0x160, - Mul354 = 0x161, - Mul355 = 0x162, - Mul356 = 0x163, - Mul357 = 0x164, - Mul358 = 0x165, - Mul359 = 0x166, - Mul360 = 0x167, - Mul361 = 0x168, - Mul362 = 0x169, - Mul363 = 0x16a, - Mul364 = 0x16b, - Mul365 = 0x16c, - Mul366 = 0x16d, - Mul367 = 0x16e, - Mul368 = 0x16f, - Mul369 = 0x170, - Mul370 = 0x171, - Mul371 = 0x172, - Mul372 = 0x173, - Mul373 = 0x174, - Mul374 = 0x175, - Mul375 = 0x176, - Mul376 = 0x177, - Mul377 = 0x178, - Mul378 = 0x179, - Mul379 = 0x17a, - Mul380 = 0x17b, - Mul381 = 0x17c, - Mul382 = 0x17d, - Mul383 = 0x17e, - Mul384 = 0x17f, - Mul385 = 0x180, - Mul386 = 0x181, - Mul387 = 0x182, - Mul388 = 0x183, - Mul389 = 0x184, - Mul390 = 0x185, - Mul391 = 0x186, - Mul392 = 0x187, - Mul393 = 0x188, - Mul394 = 0x189, - Mul395 = 0x18a, - Mul396 = 0x18b, - Mul397 = 0x18c, - Mul398 = 0x18d, - Mul399 = 0x18e, - Mul400 = 0x18f, - Mul401 = 0x190, - Mul402 = 0x191, - Mul403 = 0x192, - Mul404 = 0x193, - Mul405 = 0x194, - Mul406 = 0x195, - Mul407 = 0x196, - Mul408 = 0x197, - Mul409 = 0x198, - Mul410 = 0x199, - Mul411 = 0x19a, - Mul412 = 0x19b, - Mul413 = 0x19c, - Mul414 = 0x19d, - Mul415 = 0x19e, - Mul416 = 0x19f, - Mul417 = 0x1a0, - Mul418 = 0x1a1, - Mul419 = 0x1a2, - Mul420 = 0x1a3, - Mul421 = 0x1a4, - Mul422 = 0x1a5, - Mul423 = 0x1a6, - Mul424 = 0x1a7, - Mul425 = 0x1a8, - Mul426 = 0x1a9, - Mul427 = 0x1aa, - Mul428 = 0x1ab, - Mul429 = 0x1ac, - Mul430 = 0x1ad, - Mul431 = 0x1ae, - Mul432 = 0x1af, - Mul433 = 0x1b0, - Mul434 = 0x1b1, - Mul435 = 0x1b2, - Mul436 = 0x1b3, - Mul437 = 0x1b4, - Mul438 = 0x1b5, - Mul439 = 0x1b6, - Mul440 = 0x1b7, - Mul441 = 0x1b8, - Mul442 = 0x1b9, - Mul443 = 0x1ba, - Mul444 = 0x1bb, - Mul445 = 0x1bc, - Mul446 = 0x1bd, - Mul447 = 0x1be, - Mul448 = 0x1bf, - Mul449 = 0x1c0, - Mul450 = 0x1c1, - Mul451 = 0x1c2, - Mul452 = 0x1c3, - Mul453 = 0x1c4, - Mul454 = 0x1c5, - Mul455 = 0x1c6, - Mul456 = 0x1c7, - Mul457 = 0x1c8, - Mul458 = 0x1c9, - Mul459 = 0x1ca, - Mul460 = 0x1cb, - Mul461 = 0x1cc, - Mul462 = 0x1cd, - Mul463 = 0x1ce, - Mul464 = 0x1cf, - Mul465 = 0x1d0, - Mul466 = 0x1d1, - Mul467 = 0x1d2, - Mul468 = 0x1d3, - Mul469 = 0x1d4, - Mul470 = 0x1d5, - Mul471 = 0x1d6, - Mul472 = 0x1d7, - Mul473 = 0x1d8, - Mul474 = 0x1d9, - Mul475 = 0x1da, - Mul476 = 0x1db, - Mul477 = 0x1dc, - Mul478 = 0x1dd, - Mul479 = 0x1de, - Mul480 = 0x1df, - Mul481 = 0x1e0, - Mul482 = 0x1e1, - Mul483 = 0x1e2, - Mul484 = 0x1e3, - Mul485 = 0x1e4, - Mul486 = 0x1e5, - Mul487 = 0x1e6, - Mul488 = 0x1e7, - Mul489 = 0x1e8, - Mul490 = 0x1e9, - Mul491 = 0x1ea, - Mul492 = 0x1eb, - Mul493 = 0x1ec, - Mul494 = 0x1ed, - Mul495 = 0x1ee, - Mul496 = 0x1ef, - Mul497 = 0x1f0, - Mul498 = 0x1f1, - Mul499 = 0x1f2, - Mul500 = 0x1f3, - Mul501 = 0x1f4, - Mul502 = 0x1f5, - Mul503 = 0x1f6, - Mul504 = 0x1f7, - Mul505 = 0x1f8, - Mul506 = 0x1f9, - Mul507 = 0x1fa, - Mul508 = 0x1fb, - Mul509 = 0x1fc, - Mul510 = 0x1fd, - Mul511 = 0x1fe, - Mul512 = 0x1ff, - _, - }; - - pub const PLLRGE = enum(u2) { - /// Frequency is between 1 and 2 MHz - Range1 = 0x0, - /// Frequency is between 2 and 4 MHz - Range2 = 0x1, - /// Frequency is between 4 and 8 MHz - Range4 = 0x2, - /// Frequency is between 8 and 16 MHz - Range8 = 0x3, - }; - - pub const PLLSRC = enum(u2) { - /// no clock send to DIVMx divider and PLLs (default after reset) - DISABLE = 0x0, - /// HSI selected as PLL clock (hsi_ck) - HSI = 0x1, - /// CSI selected as PLL clock (csi_ck) - CSI = 0x2, - /// HSE selected as PLL clock (hse_ck) - HSE = 0x3, - }; - - pub const PLLVCOSEL = enum(u1) { - /// VCO frequency range 192 to 836 MHz - WideVCO = 0x0, - /// VCO frequency range 150 to 420 MHz - MediumVCO = 0x1, - }; - - pub const PPRE = enum(u3) { - /// rcc_pclk3 = rcc_hclk1 / 1 - Div1 = 0x0, - /// rcc_pclk3 = rcc_hclk1 / 2 - Div2 = 0x4, - /// rcc_pclk3 = rcc_hclk1 / 4 - Div4 = 0x5, - /// rcc_pclk3 = rcc_hclk1 / 8 - Div8 = 0x6, - /// rcc_pclk3 = rcc_hclk1 / 16 - Div16 = 0x7, - _, - }; - - pub const RNGSEL = enum(u2) { - /// hsi48_ker_ck selected as kernel clock (default after reset) - HSI48 = 0x0, - /// pll1_q_ck selected as kernel clock - PLL1_Q = 0x1, - /// lse_ck selected as kernel clock - LSE = 0x2, - /// lsi_ker_ck selected as kernel clock - LSI = 0x3, - }; - - pub const RTCSEL = enum(u2) { - /// no clock (default after Backup domain reset) - DISABLE = 0x0, - /// LSE selected as RTC clock - LSE = 0x1, - /// LSI selected as RTC clock - LSI = 0x2, - /// HSE divided by RTCPRE value selected as RTC clock - HSE_DIV_RTCPRE = 0x3, - }; - - pub const SAISEL = enum(u3) { - /// pll1_q_ck selected as kernel clock (default after reset) - PLL1_Q = 0x0, - /// pll2_p_ck selected as kernel clock - PLL2_P = 0x1, - /// pll3_p_ck selected as kernel clock - PLL3_P = 0x2, - /// AUDIOCLK selected as kernel clock - AUDIOCLK = 0x3, - /// per_ck selected as kernel clock - PER = 0x4, - _, - }; - - pub const SDMMCSEL = enum(u1) { - /// pll1_q_ck selected as kernel clock (default after reset) - PLL1_Q = 0x0, - /// pll2_r_ck selected as kernel clock - PLL2_R = 0x1, - }; - - pub const SPI1SEL = enum(u3) { - /// pll1_q_ck selected as kernel clock (default after reset) - PLL1_Q = 0x0, - /// pll2_p_ck selected as kernel clock - PLL2_P = 0x1, - /// pll3_p_ck selected as kernel clock - PLL3_P = 0x2, - /// AUDIOCLK selected as kernel clock - AUDIOCLK = 0x3, - /// per_ck selected as kernel clock - PER = 0x4, - _, - }; - - pub const SPI2SEL = enum(u3) { - /// pll1_q_ck selected as kernel clock (default after reset) - PLL1_Q = 0x0, - /// pll2_p_ck selected as kernel clock - PLL2_P = 0x1, - /// pll3_p_ck selected as kernel clock - PLL3_P = 0x2, - /// AUDIOCLK selected as kernel clock - AUDIOCLK = 0x3, - /// per_ck selected as kernel clock - PER = 0x4, - _, - }; - - pub const SPI3SEL = enum(u3) { - /// pll1_q_ck selected as kernel clock (default after reset) - PLL1_Q = 0x0, - /// pll2_p_ck selected as kernel clock - PLL2_P = 0x1, - /// pll3_p_ck selected as kernel clock - PLL3_P = 0x2, - /// AUDIOCLK selected as kernel clock - AUDIOCLK = 0x3, - /// per_ck selected as kernel clock - PER = 0x4, - _, - }; - - pub const SPI4SEL = enum(u3) { - /// rcc_pclk2 selected as kernel clock (default after reset) - PCLK2 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// HSE selected as peripheral clock - HSE = 0x5, - _, - }; - - pub const SPI5SEL = enum(u3) { - /// rcc_pclk3 selected as kernel clock (default after reset) - PCLK3 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// HSE selected as peripheral clock - HSE = 0x5, - _, - }; - - pub const SPI6SEL = enum(u3) { - /// rcc_pclk2 selected as peripheral clock - PCLK2 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// HSE selected as peripheral clock - HSE = 0x5, - _, - }; - - pub const SPRIV = enum(u1) { - /// Read and write to RCC secure functions can be done by privileged or unprivileged access. - Any = 0x0, - /// Read and write to RCC secure functions can be done by privileged access only - Privileged = 0x1, - }; - - pub const STOPKERWUCK = enum(u1) { - /// HSI selected as wakeup clock from system Stop (default after reset) - HSI = 0x0, - /// CSI selected as wakeup clock from system Stop - CSI = 0x1, - }; - - pub const STOPWUCK = enum(u1) { - /// CSI selected as wakeup clock from system Stop - CSI = 0x1, - _, - }; - - pub const SW = enum(u3) { - /// HSI selected as system clock - HSI = 0x0, - /// CSI selected as system clock - CSI = 0x1, - /// HSE selected as system clock - HSE = 0x2, - /// PLL1 selected as system clock - PLL1_P = 0x3, - _, - }; - - pub const SYSTICKSEL = enum(u2) { - /// rcc_hclk/8 selected as clock source (default after reset) - HCLK1_DIV_8 = 0x0, - /// lsi_ker_ck[1] selected as clock source - LSI = 0x1, - /// lse_ck[1] selected as clock source - LSE = 0x2, - _, - }; - - pub const TIMICSEL = enum(u1) { - /// No internal clock available for timers input capture (default after reset) - B_0x0 = 0x0, - /// hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture - B_0x1 = 0x1, - }; - - pub const TIMPRE = enum(u1) { - /// The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset) - DefaultX2 = 0x0, - /// The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2 - DefaultX4 = 0x1, - }; - - pub const USART1SEL = enum(u3) { - /// rcc_pclk2 selected as peripheral clock - PCLK2 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, - _, - }; - - pub const USARTSEL = enum(u3) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, - _, - }; - - pub const USBSEL = enum(u2) { - /// Disable the kernel clock - DISABLE = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// HSI48 selected as peripheral clock - HSI48 = 0x3, - }; - - /// Reset and clock controller - pub const RCC = extern struct { - /// RCC clock control register - CR: mmio.Mmio(packed struct(u32) { - /// HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). - HSION: u1, - /// HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable. - HSIRDY: u1, - /// HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION. - HSIKERON: u1, - /// HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored. - HSIDIV: packed union { - raw: u2, - value: HSIDIV, - }, - /// HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. - HSIDIVF: u1, + /// High Resolution Timer + pub const HRTIM = extern struct { + /// Master Timer Control Register + MCR: mmio.Mmio(packed struct(u32) { + /// HRTIM Master Clock prescaler + CKPSC: u3, + /// Master Continuous mode + CONT: u1, + /// Master Re-triggerable mode + RETRIG: u1, + /// Half mode enable + HALF: u1, reserved8: u2, - /// CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). - CSION: u1, - /// CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request). - CSIRDY: u1, - /// CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION. - CSIKERON: u1, - reserved12: u1, - /// HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode. - HSI48ON: u1, - /// HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable. - HSI48RDY: u1, - reserved16: u2, - /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). - HSEON: u1, - /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. - HSERDY: u1, - /// HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. - HSEBYP: u1, - /// HSE clock security system enable Set by software to enable clock security system on HSE. This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected. - HSECSSON: u1, - /// external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled. - HSEEXT: packed union { - raw: u1, - value: HSEEXT, - }, - reserved24: u3, - /// PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock. - PLLON: u1, - /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. - PLLRDY: u1, - padding: u6, - }), - reserved16: [12]u8, - /// RCC HSI calibration register - HSICFGR: mmio.Mmio(packed struct(u32) { - /// HSI clock calibration Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value. - HSICAL: u12, - reserved16: u4, - /// HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_OPT. After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated Note: The reset value of the field is 0x40. - HSITRIM: u7, - padding: u9, - }), - /// RCC clock recovery RC register - CRRCR: mmio.Mmio(packed struct(u32) { - /// Internal RC 48 MHz clock calibration Set by hardware by option-byte loading during system reset NRESET. Read-only. - HSI48CAL: u10, - padding: u22, - }), - /// RCC CSI calibration register - CSICFGR: mmio.Mmio(packed struct(u32) { - /// CSI clock calibration Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value. - CSICAL: u8, - reserved16: u8, - /// CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_OPT. Note: The reset value of the field is 0x20. - CSITRIM: u6, - padding: u10, - }), - /// RCC clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// system clock and trace clock switch Set and reset by software to select system clock and trace clock sources (sys_ck). Set by hardware in order to: - force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode - force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock others: reserved - SW: packed union { - raw: u3, - value: SW, - }, - /// system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset). others: reserved - SWS: packed union { - raw: u3, - value: SW, - }, - /// system clock selection after a wakeup from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset) STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10). - STOPWUCK: packed union { - raw: u1, - value: STOPWUCK, - }, - /// kernel clock selection after a wakeup from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. - STOPKERWUCK: packed union { - raw: u1, - value: STOPKERWUCK, - }, - /// HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ... - RTCPRE: u6, - reserved15: u1, - /// timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. - TIMPRE: packed union { - raw: u1, - value: TIMPRE, - }, - reserved18: u2, - /// MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... - MCO1PRE: packed union { - raw: u4, - value: MCOPRE, - }, - /// Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved - MCO1SEL: packed union { - raw: u3, - value: MCO1SEL, - }, - /// MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... - MCO2PRE: packed union { - raw: u4, - value: MCOPRE, - }, - /// microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved - MCO2SEL: packed union { - raw: u3, - value: MCO2SEL, - }, - }), - /// RCC CPU domain clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// AHB prescaler Set and reset by software to control the division factor of rcc_hclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks 0xxx: rcc_hclk = sys_ck (default after reset) - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// APB low-speed prescaler (APB1) Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write. 0xx: rcc_pclk1 = rcc_hclk1 (default after reset) - PPRE1: packed union { - raw: u3, - value: PPRE, - }, - reserved8: u1, - /// APB high-speed prescaler (APB2) Set and reset by software to control APB high-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write. 0xx: rcc_pclk2 = rcc_hclk1 - PPRE2: packed union { - raw: u3, - value: PPRE, - }, - reserved12: u1, - /// APB low-speed prescaler (APB3) Set and reset by software to control APB low-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write. 0xx: rcc_pclk3 = rcc_hclk1 - PPRE3: packed union { - raw: u3, - value: PPRE, - }, - reserved16: u1, - /// AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals from RCC_AHB1ENR are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from RCC_AHB1ENR are off. enable control bits - AHB1DIS: u1, - /// AHB2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR are used and when their clocks are disabled in RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR are off. enable control bits - AHB2DIS: u1, - reserved19: u1, - /// AHB4 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB4 peripherals from RCC_AHB4ENR are used and when their clocks are disabled in RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from RCC_AHB4ENR are off. enable control bits - AHB4DIS: u1, - /// APB1 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. control bits - APB1DIS: u1, - /// APB2 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off. control bits - APB2DIS: u1, - /// APB3 clock disable value.Set and cleared by software This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. control bits - APB3DIS: u1, - padding: u9, - }), - reserved40: [4]u8, - /// RCC PLL clock source selection register - PLLCFGR: [3]mmio.Mmio(packed struct(u32) { - /// DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset). - PLLSRC: packed union { + /// Synchronization input + SYNCIN: packed union { raw: u2, - value: PLLSRC, + value: SYNCIN, }, - /// PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. - PLLRGE: packed union { + /// Synchronization Resets Master + SYNCRSTM: u1, + /// Synchronization Starts Master + SYNCSTRTM: u1, + /// Synchronization output + SYNCOUT: packed union { raw: u2, - value: PLLRGE, - }, - /// PLL1 fractional latch enable Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator. In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator. - PLLFRACEN: u1, - /// PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. - PLLVCOSEL: packed union { - raw: u1, - value: PLLVCOSEL, - }, - reserved8: u2, - /// prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... - DIVM: packed union { - raw: u6, - value: PLLM, - }, - reserved16: u2, - /// PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. - PLLPEN: u1, - /// PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). - PLLQEN: u1, - /// PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). - PLLREN: u1, - padding: u13, - }), - /// RCC PLL1 dividers register - PLLDIVR: mmio.Mmio(packed struct(u32) { - /// Multiplication factor for PLL1VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved - PLLN: packed union { - raw: u9, - value: PLLN, + value: SYNCOUT, }, - /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... - PLLP: packed union { - raw: u7, - value: PLLDIV, + /// Synchronization source + SYNCSRC: packed union { + raw: u2, + value: SYNCSRC, }, - /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLQ: packed union { - raw: u7, - value: PLLDIV, + /// Master Counter enable + MCEN: u1, + /// Timer X counter enable + TCEN: u1, + reserved25: u7, + /// AC Synchronization + DACSYNC: packed union { + raw: u2, + value: DACSYNC, }, - reserved24: u1, - /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLR: packed union { - raw: u7, - value: PLLDIV, + /// Preload enable + PREEN: u1, + reserved29: u1, + /// Master Timer Repetition update + MREPU: u1, + /// Burst DMA Update + BRSTDMA: packed union { + raw: u2, + value: BRSTDMA, }, - padding: u1, }), - /// RCC PLL1 fractional divider register - PLLFRACR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: * 128 to 560 MHz if PLL1VCOSEL = 0 * 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with * PLL1N between 8 and 420 * PLL1FRACN can be between 0 and 213- 1 * The input frequency Fref1_ck must be between 1 and 16 MHz. To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: * Set the bit PLL1FRACEN to 0 * Write the new fractional value into PLL1FRACN * Set the bit PLL1FRACEN to 1 - PLLFRACN: u13, - padding: u16, + /// Master Timer Interrupt Status Register + MISR: mmio.Mmio(packed struct(u32) { + /// Master Compare X Interrupt Flag + MCMP: u1, + reserved4: u3, + /// Master Repetition Interrupt Flag + MREP: u1, + /// Sync Input Interrupt Flag + SYNC: u1, + /// Master Update Interrupt Flag + MUPD: u1, + padding: u25, }), - reserved80: [20]u8, - /// RCC clock source interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization. - LSIRDYIE: u1, - /// LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization. - LSERDYIE: u1, - /// CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization. - CSIRDYIE: u1, - /// HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization. - HSIRDYIE: u1, - /// HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization. - HSERDYIE: u1, - /// HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. - HSI48RDYIE: u1, - /// PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. - PLLRDYIE: u1, + /// Master Timer Interrupt Clear Register + MICR: mmio.Mmio(packed struct(u32) { + /// Master Compare X Interrupt flag clear + MCMPC: u1, + reserved4: u3, + /// Repetition Interrupt flag clear + MREPC: u1, + /// Sync Input Interrupt flag clear + SYNCC: u1, + /// Master update Interrupt flag clear + MUPDC: u1, padding: u25, }), - /// RCC clock source interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. - LSIRDYF: u1, - /// LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set. - LSERDYF: u1, - /// CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set. - CSIRDYF: u1, - /// HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set. - HSIRDYF: u1, - /// HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. - HSERDYF: u1, - /// HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. - HSI48RDYF: u1, - /// PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. - PLLRDYF: u1, - reserved10: u3, - /// HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. - HSECSSF: u1, - padding: u21, + /// Master Timer DMA / Interrupt Enable Register + MDIER: mmio.Mmio(packed struct(u32) { + /// Master Compare X Interrupt Enable + MCMPIE: u1, + reserved4: u3, + /// Master Repetition Interrupt Enable + MREPIE: u1, + /// Sync Input Interrupt Enable + SYNCIE: u1, + /// Master Update Interrupt Enable + MUPDIE: u1, + reserved16: u9, + /// Master Compare X DMA request Enable + MCMPDE: u1, + reserved20: u3, + /// Master Repetition DMA request Enable + MREPDE: u1, + /// Sync Input DMA request Enable + SYNCDE: u1, + /// Master Update DMA request Enable + MUPDDE: u1, + padding: u9, }), - /// RCC clock source interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done. - LSIRDYC: u1, - /// LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done. - LSERDYC: u1, - /// HSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done. - CSIRDYC: u1, - /// HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done. - HSIRDYC: u1, - /// HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done. - HSERDYC: u1, - /// HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. - HSI48RDYC: u1, - /// PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. - PLLRDYC: u1, - reserved10: u3, - /// HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done. - HSECSSC: u1, - padding: u21, + /// Master Timer Counter Register + MCNTR: mmio.Mmio(packed struct(u32) { + /// Counter value + MCNT: u16, + padding: u16, }), - reserved96: [4]u8, - /// RCC AHB1 reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 block reset Set and reset by software. - GPDMA1RST: u1, - /// GPDMA2 block reset Set and reset by software. - GPDMA2RST: u1, - reserved12: u10, - /// CRC block reset Set and reset by software. - CRCRST: u1, - reserved14: u1, - /// CORDIC block reset Set and reset by software. - CORDICRST: u1, - /// FMAC block reset Set and reset by software. - FMACRST: u1, - reserved17: u1, - /// RAMCFG block reset Set and reset by software. - RAMCFGRST: u1, - reserved19: u1, - /// ETH1 block reset Set and reset by software - ETHRST: u1, - reserved24: u4, - /// TZSC1 reset Set and reset by software - TZSC1RST: u1, - padding: u7, + /// Master Timer Period Register + MPER: mmio.Mmio(packed struct(u32) { + /// Master Timer Period value + MPER: u16, + padding: u16, }), - /// RCC AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// GPIOA block reset Set and reset by software. - GPIOARST: u1, - /// GPIOB block reset Set and reset by software. - GPIOBRST: u1, - /// GPIOC block reset Set and reset by software. - GPIOCRST: u1, - /// GPIOD block reset Set and reset by software. - GPIODRST: u1, - /// GPIOE block reset Set and reset by software. - GPIOERST: u1, - /// GPIOF block reset Set and reset by software. - GPIOFRST: u1, - /// GPIOG block reset Set and reset by software. - GPIOGRST: u1, - /// GPIOH block reset Set and reset by software. - GPIOHRST: u1, - /// GPIOI block reset Set and reset by software. - GPIOIRST: u1, - reserved10: u1, - /// ADC1 and 2 blocks reset Set and reset by software. - ADC12RST: u1, - /// DAC block reset Set and reset by software. - DAC1RST: u1, - /// digital camera interface block reset (DCMI or PSSI depending which interface is active) Set and reset by software. - DCMI_PSSIRST: u1, - reserved16: u3, - /// AES block reset Set and reset by software. - AESRST: u1, - /// HASH block reset Set and reset by software. - HASHRST: u1, - /// RNG block reset Set and reset by software. - RNGRST: u1, - /// PKA block reset Set and reset by software. - PKARST: u1, - /// SAES block reset Set and reset by software. - SAESRST: u1, - padding: u11, + /// Master Timer Repetition Register + MREP: mmio.Mmio(packed struct(u32) { + /// Master Timer Repetition counter value + MREP: u8, + padding: u24, }), - reserved108: [4]u8, - /// RCC AHB4 peripheral reset register - AHB4RSTR: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// OTFDEC1 block reset Set and reset by software. - OTFDEC1RST: u1, - reserved11: u3, - /// SDMMC1 and SDMMC1 delay blocks reset Set and reset by software. - SDMMC1RST: u1, - /// SDMMC2 and SDMMC2 delay blocks reset Set and reset by software. - SDMMC2RST: u1, - reserved16: u3, - /// FMC block reset Set and reset by software. - FMCRST: u1, - reserved20: u3, - /// OCTOSPI1 block reset Set and reset by software. - OCTOSPI1RST: u1, - padding: u11, + /// Master Timer Compare X Register + MCMP: mmio.Mmio(packed struct(u32) { + /// Master Timer Compare X value + MCMP: u16, + padding: u16, }), - reserved116: [4]u8, - /// RCC APB1 peripheral low reset register - APB1LRSTR: mmio.Mmio(packed struct(u32) { - /// TIM2 block reset Set and reset by software. - TIM2RST: u1, - /// TIM3 block reset Set and reset by software. - TIM3RST: u1, - /// TIM4 block reset Set and reset by software. - TIM4RST: u1, - /// TIM5 block reset Set and reset by software. - TIM5RST: u1, - /// TIM6 block reset Set and reset by software. - TIM6RST: u1, - /// TIM7 block reset Set and reset by software. - TIM7RST: u1, - /// TIM12 block reset Set and reset by software. - TIM12RST: u1, - /// TIM13 block reset t Set and reset by software. - TIM13RST: u1, - /// TIM14 block reset Set and reset by software. - TIM14RST: u1, - reserved14: u5, - /// SPI2 block reset Set and reset by software. - SPI2RST: u1, - /// SPI3 block reset Set and reset by software. - SPI3RST: u1, - reserved17: u1, - /// USART2 block reset Set and reset by software. - USART2RST: u1, - /// USART3 block reset Set and reset by software. - USART3RST: u1, - /// UART4 block reset Set and reset by software. - UART4RST: u1, - /// UART5 block reset Set and reset by software. - UART5RST: u1, - /// I2C1 block reset Set and reset by software. - I2C1RST: u1, - /// I2C2 block reset Set and reset by software. - I2C2RST: u1, - /// I3C1 block reset Set and reset by software. - I3C1RST: u1, - /// CRS block reset Set and reset by software. - CRSRST: u1, - /// USART6 block reset Set and reset by software. - USART6RST: u1, - /// USART10 block reset Set and reset by software. - USART10RST: u1, - /// USART11 block reset Set and reset by software. - USART11RST: u1, - /// HDMI-CEC block reset Set and reset by software. - CECRST: u1, - reserved30: u1, - /// UART7 block reset Set and reset by software. - UART7RST: u1, - /// UART8 block reset Set and reset by software. - UART8RST: u1, + reserved128: [96]u8, + /// High Resolution Timer: Timing Unit + TIM: u32, + reserved896: [764]u8, + /// High Resolution Timer: Control Register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Master Update Disable + MUDIS: u1, + /// Timer X Update Disable + TUDIS: u1, + reserved16: u14, + /// ADC Trigger X Update Source + ADUSRC: u3, + padding: u13, }), - /// RCC APB1 peripheral high reset register - APB1HRSTR: mmio.Mmio(packed struct(u32) { - /// UART9 block reset Set and reset by software. - UART9RST: u1, - /// UART12 block reset Set and reset by software. - UART12RST: u1, - reserved3: u1, - /// DTS block reset Set and reset by software. - DTSRST: u1, - reserved5: u1, - /// LPTIM2 block reset Set and reset by software. - LPTIM2RST: u1, - reserved9: u3, - /// FDCAN1 and FDCAN2 blocks reset Set and reset by software. - FDCAN12RST: u1, - reserved23: u13, - /// UCPD block reset Set and reset by software. - UCPDRST: u1, - padding: u8, + /// High Resolution Timer: Control Register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Master Timer Software Update + MSWU: u1, + /// Timer X Software Update + TSWU: u1, + reserved8: u6, + /// Master Counter Software Reset + MRST: u1, + /// Timer X Counter Software Reset + TRST: u1, + padding: u22, }), - /// RCC APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 block reset Set and reset by software. - TIM1RST: u1, - /// SPI1 block reset Set and reset by software. - SPI1RST: u1, - /// TIM8 block reset Set and reset by software. - TIM8RST: u1, - /// USART1 block reset Set and reset by software. - USART1RST: u1, - reserved16: u1, - /// TIM15 block reset Set and reset by software. - TIM15RST: u1, - /// TIM16 block reset Set and reset by software. - TIM16RST: u1, - /// TIM17 block reset Set and reset by software. - TIM17RST: u1, - /// SPI4 block reset Set and reset by software. - SPI4RST: u1, - /// SPI6 block reset Set and reset by software. - SPI6RST: u1, - /// SAI1 block reset Set and reset by software. - SAI1RST: u1, - /// SAI2 block reset Set and reset by software. - SAI2RST: u1, - reserved24: u1, - /// USB block reset Set and reset by software. - USBRST: u1, - padding: u7, + /// High Resolution Timer: Interrupt Status Register + ISR: mmio.Mmio(packed struct(u32) { + /// Fault X Interrupt Flag + FLT: u1, + reserved5: u4, + /// System Fault Interrupt Flag + SYSFLT: u1, + reserved16: u10, + /// DLL Ready Interrupt Flag + DLLRDY: u1, + /// Burst Mode Period Interrupt Flag + BMPER: u1, + padding: u14, }), - /// RCC APB3 peripheral reset register - APB3RSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SBS block reset Set and reset by software. - SYSCFGRST: u1, - reserved5: u3, - /// SPI5 block reset Set and reset by software. - SPI5RST: u1, - /// LPUART1 block reset Set and reset by software. - LPUART1RST: u1, - /// I2C3 block reset Set and reset by software. - I2C3RST: u1, - /// I2C4 block reset Set and reset by software. - I2C4RST: u1, - reserved11: u2, - /// LPTIM1 block reset Set and reset by software. - LPTIM1RST: u1, - /// LPTIM3 block reset Set and reset by software. - LPTIM3RST: u1, - /// LPTIM4 block reset Set and reset by software. - LPTIM4RST: u1, - /// LPTIM5 block reset Set and reset by software. - LPTIM5RST: u1, - /// LPTIM6 block reset Set and reset by software. - LPTIM6RST: u1, - reserved20: u4, - /// VREF block reset Set and reset by software. - VREFRST: u1, - padding: u11, + /// High Resolution Timer: Interrupt Clear Register + ICR: mmio.Mmio(packed struct(u32) { + /// Fault X Interrupt Flag Clear + FLT: u1, + reserved5: u4, + /// System Fault Interrupt Flag Clear + SYSFLT: u1, + reserved16: u10, + /// DLL Ready Interrupt Flag Clear + DLLRDY: u1, + /// Burst Mode Period Interrupt Flag Clear + BMPER: u1, + padding: u14, }), - reserved136: [4]u8, - /// RCC AHB1 peripherals clock register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 clock enable Set and reset by software. - GPDMA1EN: u1, - /// GPDMA2 clock enable Set and reset by software. - GPDMA2EN: u1, - reserved8: u6, - /// Flash interface clock enable Set and reset by software. - FLITFEN: u1, - reserved12: u3, - /// CRC clock enable Set and reset by software. - CRCEN: u1, - reserved14: u1, - /// CORDIC clock enable Set and reset by software. - CORDICEN: u1, - /// FMAC clock enable Set and reset by software. - FMACEN: u1, - reserved17: u1, - /// RAMCFG clock enable Set and reset by software. - RAMCFGEN: u1, - reserved19: u1, - /// ETH clock enable Set and reset by software - ETHEN: u1, - /// ETHTX clock enable Set and reset by software - ETHTXEN: u1, - /// ETHRX clock enable Set and reset by software - ETHRXEN: u1, - reserved24: u2, - /// TZSC1 clock enable Set and reset by software - TZSC1EN: u1, - reserved28: u3, - /// BKPRAM clock enable Set and reset by software - BKPRAMEN: u1, - reserved30: u1, - /// DCACHE clock enable Set and reset by software - DCACHEEN: u1, - /// SRAM1 clock enable Set and reset by software. - SRAM1EN: u1, + /// High Resolution Timer: Interrupt Enable Register + IER: mmio.Mmio(packed struct(u32) { + /// Fault X Interrupt Flag Enable + FLT: u1, + reserved5: u4, + /// System Fault Interrupt Flag Enable + SYSFLT: u1, + reserved16: u10, + /// DLL Ready Interrupt Flag Enable + DLLRDY: u1, + /// Burst Mode Period Interrupt Flag Enable + BMPER: u1, + padding: u14, }), - /// RCC AHB2 peripheral clock register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// GPIOA clock enable Set and reset by software. - GPIOAEN: u1, - /// GPIOB clock enable Set and reset by software. - GPIOBEN: u1, - /// GPIOC clock enable Set and reset by software. - GPIOCEN: u1, - /// GPIOD clock enable Set and reset by software. - GPIODEN: u1, - /// GPIOE clock enable Set and reset by software. - GPIOEEN: u1, - /// GPIOF clock enable Set and reset by software. - GPIOFEN: u1, - /// GPIOG clock enable Set and reset by software. - GPIOGEN: u1, - /// GPIOH clock enable Set and reset by software. - GPIOHEN: u1, - /// GPIOI clock enable Set and reset by software. - GPIOIEN: u1, - reserved10: u1, - /// ADC1 and 2 peripherals clock enabled Set and reset by software. - ADC12EN: u1, - /// DAC clock enable Set and reset by software. - DAC1EN: u1, - /// digital camera interface clock enable (DCMI or PSSI depending which interface is active) Set and reset by software. - DCMI_PSSIEN: u1, - reserved16: u3, - /// AES clock enable Set and reset by software. - AESEN: u1, - /// HASH clock enable Set and reset by software. - HASHEN: u1, - /// RNG clock enable Set and reset by software. - RNGEN: u1, - /// PKA clock enable Set and reset by software. - PKAEN: u1, - /// SAES clock enable Set and reset by software. - SAESEN: u1, - reserved30: u9, - /// SRAM3 clock enable Set and reset by software. - SRAM3EN: u1, - /// SRAM2 clock enable Set and reset by software. - SRAM2EN: u1, + /// High Resolution Timer: Output Enable Register + OENR: mmio.Mmio(packed struct(u32) { + /// Timer X Output Enable + T1OEN: u1, + /// Timer X Complementary Output Enable + T2OEN: u1, + padding: u30, }), - reserved148: [4]u8, - /// RCC AHB4 peripheral clock register - AHB4ENR: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// OTFDEC1 clock enable Set and reset by software. - OTFDEC1EN: u1, - reserved11: u3, - /// SDMMC1 and SDMMC1 delay peripheral clock enable reset - SDMMC1EN: u1, - /// SDMMC2 and SDMMC2 delay peripheral clock enabled Set and reset by software. - SDMMC2EN: u1, - reserved16: u3, - /// FMC clock enable Set and reset by software. - FMCEN: u1, - reserved20: u3, - /// OCTOSPI1 clock enable Set and reset by software. - OCTOSPI1EN: u1, - padding: u11, + /// High Resolution Timer: Output Disable Register + ODISR: mmio.Mmio(packed struct(u32) { + /// Timer X Output Disable + T1ODIS: u1, + /// Timer X Complementary Output Disable + T2ODIS: u1, + padding: u30, }), - reserved156: [4]u8, - /// RCC APB1 peripheral clock register - APB1LENR: mmio.Mmio(packed struct(u32) { - /// TIM2 clock enable Set and reset by software. - TIM2EN: u1, - /// TIM3 clock enable Set and reset by software. - TIM3EN: u1, - /// TIM4 clock enable Set and reset by software. - TIM4EN: u1, - /// TIM5 clock enable Set and reset by software. - TIM5EN: u1, - /// TIM6 clock enable Set and reset by software. - TIM6EN: u1, - /// TIM7 clock enable Set and reset by software. - TIM7EN: u1, - /// TIM12 clock enable Set and reset by software. - TIM12EN: u1, - /// TIM13 clock enable Set and reset by software. - TIM13EN: u1, - /// TIM14 clock enable Set and reset by software. - TIM14EN: u1, - reserved11: u2, - /// WWDG clock enable Set and reset by software. - WWDGEN: u1, - reserved14: u2, - /// SPI2 clock enable Set and reset by software. - SPI2EN: u1, - /// SPI3 clock enable Set and reset by software. - SPI3EN: u1, - reserved17: u1, - /// USART2 clock enable Set and reset by software. - USART2EN: u1, - /// USART3 clock enable Set and reset by software. - USART3EN: u1, - /// UART4 clock enable Set and reset by software. - UART4EN: u1, - /// UART5 clock enable Set and reset by software. - UART5EN: u1, - /// I2C1 clock enable Set and reset by software. - I2C1EN: u1, - /// I2C2 clock enable Set and reset by software. - I2C2EN: u1, - /// I3C1 clock enable Set and reset by software. - I3C1EN: u1, - /// CRS clock enable Set and reset by software. - CRSEN: u1, - /// USART6 clock enable Set and reset by software. - USART6EN: u1, - /// USART10 clock enable Set and reset by software. - USART10EN: u1, - /// USART11 clock enable - USART11EN: u1, - /// HDMI-CEC clock enable Set and reset by software. - CECEN: u1, - reserved30: u1, - /// UART7 clock enable Set and reset by software. - UART7EN: u1, - /// UART8 clock enable Set and reset by software. - UART8EN: u1, + /// High Resolution Timer: Output Disable Status Register + ODSR: mmio.Mmio(packed struct(u32) { + /// Timer X Output Disable Status + T1ODIS: u1, + /// Timer X Complementary Output Disable Status + T2ODIS: u1, + padding: u30, }), - /// RCC APB1 peripheral clock register - APB1HENR: mmio.Mmio(packed struct(u32) { - /// UART9 clock enable Set and reset by software. - UART9EN: u1, - /// UART12 clock enable Set and reset by software. - UART12EN: u1, - reserved3: u1, - /// DTS clock enable Set and reset by software. - DTSEN: u1, - reserved5: u1, - /// LPTIM2 clock enable Set and reset by software. - LPTIM2EN: u1, - reserved9: u3, - /// FDCAN1 and FDCAN2 peripheral clock enable Set and reset by software. - FDCAN12EN: u1, - reserved23: u13, - /// UCPD clock enable Set and reset by software. - UCPDEN: u1, - padding: u8, + /// High Resolution Timer: Burst Mode Control Register + BMCR: mmio.Mmio(packed struct(u32) { + /// Burst Mode Enable + BME: u1, + /// Burst Mode Operating Mode + BMOM: u1, + /// Burst Mode Clock source + BMCLK: u3, + reserved6: u1, + /// Burst Mode Prescaler + BMPRSC: u3, + reserved10: u1, + /// Burst Mode Preload Enable + BMPREN: u1, + reserved16: u5, + /// Master Timer Burst Mode + MTBM: u1, + /// Timer X Burst Mode + TBM: u1, + reserved31: u13, + BMSTAT: u1, }), - /// RCC APB2 peripheral clock register - APB2ENR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 clock enable Set and reset by software. - TIM1EN: u1, - /// SPI1 clock enable Set and reset by software. - SPI1EN: u1, - /// TIM8 clock enable Set and reset by software. - TIM8EN: u1, - /// USART1 clock enable Set and reset by software. - USART1EN: u1, - reserved16: u1, - /// TIM15 clock enable Set and reset by software. - TIM15EN: u1, - /// TIM16 clock enable Set and reset by software. - TIM16EN: u1, - /// TIM17 clock enable Set and reset by software. - TIM17EN: u1, - /// SPI4 clock enable Set and reset by software. - SPI4EN: u1, - /// SPI6 clock enable Set and reset by software. - SPI6EN: u1, - /// SAI1 clock enable Set and reset by software. - SAI1EN: u1, - /// SAI2 clock enable Set and cleared by software. - SAI2EN: u1, - reserved24: u1, - /// USB clock enable Set and reset by software. - USBEN: u1, - padding: u7, + /// High Resolution Timer: Burst Mode Trigger Register + BMTRGR: mmio.Mmio(packed struct(u32) { + /// Software start + SW: u1, + /// Master reset or roll-over + MSTRST: u1, + /// Master repetition + MSTREP: u1, + /// Master Compare X + MSTCMP: u1, + reserved7: u3, + /// Timer X reset or roll-over + TRST: u1, + /// Timer X repetition + TREP: u1, + /// Timer X compare 1 event + TCMP1: u1, + /// Timer X compare 2 event + TCMP2: u1, + padding: u21, }), - /// RCC APB3 peripheral clock register - APB3ENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SBS clock enable Set and reset by software. - SYSCFGEN: u1, - reserved5: u3, - /// SPI5 clock enable Set and reset by software. - SPI5EN: u1, - /// LPUART1 clock enable Set and reset by software. - LPUART1EN: u1, - /// I2C3 clock enable Set and reset by software. - I2C3EN: u1, - /// I2C4 clock enable Set and reset by software. - I2C4EN: u1, - reserved11: u2, - /// LPTIM1 clock enable Set and reset by software. - LPTIM1EN: u1, - /// LPTIM3 clock enable Set and reset by software. - LPTIM3EN: u1, - /// LPTIM4 clock enable Set and reset by software. - LPTIM4EN: u1, - /// LPTIM5 clock enable Set and reset by software. - LPTIM5EN: u1, - /// LPTIM6 clock enable Set and reset by software. - LPTIM6EN: u1, - reserved20: u4, - /// VREF clock enable Set and reset by software. - VREFEN: u1, - /// RTC APB interface clock enable Set and reset by software. - RTCAPBEN: u1, - padding: u10, + /// High Resolution Timer: Burst Mode Compare Register + BMCMPR: mmio.Mmio(packed struct(u32) { + /// Burst mode compare value + BMCMP: u16, + padding: u16, }), - reserved176: [4]u8, - /// RCC AHB1 sleep clock register - AHB1LPENR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 clock enable during sleep mode Set and reset by software. - GPDMA1LPEN: u1, - /// GPDMA2 clock enable during sleep mode Set and reset by software. - GPDMA2LPEN: u1, - reserved8: u6, - /// Flash interface (FLITF) clock enable during sleep mode Set and reset by software. - FLITFLPEN: u1, - reserved12: u3, - /// CRC clock enable during sleep mode Set and reset by software. - CRCLPEN: u1, - reserved14: u1, - /// CORDIC clock enable during sleep mode Set and reset by software. - CORDICLPEN: u1, - /// FMAC clock enable during sleep mode Set and reset by software. - FMACLPEN: u1, - reserved17: u1, - /// RAMCFG clock enable during sleep mode Set and reset by software. - RAMCFGLPEN: u1, - reserved19: u1, - /// ETH clock enable during Sleep mode Set and reset by software - ETHLPEN: u1, - /// ETHTX clock enable during sleep mode Set and reset by software - ETHTXLPEN: u1, - /// ETHRX clock enable during sleep mode Set and reset by software - ETHRXLPEN: u1, - reserved24: u2, - /// TZSC1 clock enable during sleep mode Set and reset by software - TZSC1LPEN: u1, - reserved28: u3, - /// BKPRAM clock enable during sleep mode Set and reset by software - BKPRAMLPEN: u1, - /// ICACHE clock enable during sleep mode Set and reset by software - ICACHELPEN: u1, - /// DCACHE clock enable during sleep mode Set and reset by software - DCACHELPEN: u1, - /// SRAM1 clock enable during sleep mode Set and reset by software - SRAM1LPEN: u1, + /// High Resolution Timer: Burst Mode Period Register + BMPER: mmio.Mmio(packed struct(u32) { + /// Burst mode period value + BMPER: u16, + padding: u16, }), - /// RCC AHB2 sleep clock register - AHB2LPENR: mmio.Mmio(packed struct(u32) { - /// GPIOA clock enable during sleep mode Set and reset by software. - GPIOALPEN: u1, - /// GPIOB clock enable during sleep mode Set and reset by software. - GPIOBLPEN: u1, - /// GPIOC clock enable during sleep mode Set and reset by software. - GPIOCLPEN: u1, - /// GPIOD clock enable during sleep mode Set and reset by software. - GPIODLPEN: u1, - /// GPIOE clock enable during sleep mode Set and reset by software. - GPIOELPEN: u1, - /// GPIOF clock enable during sleep mode Set and reset by software. - GPIOFLPEN: u1, - /// GPIOG clock enable during sleep mode Set and reset by software. - GPIOGLPEN: u1, - /// GPIOH clock enable during sleep mode Set and reset by software. - GPIOHLPEN: u1, - /// GPIOI clock enable during sleep mode Set and reset by software. - GPIOILPEN: u1, - reserved10: u1, - /// ADC1 and 2 peripherals clock enable during sleep mode Set and reset by software. - ADC12LPEN: u1, - /// DAC clock enable during sleep mode Set and reset by software. - DAC1LPEN: u1, - /// digital camera interface clock enable during sleep mode (DCMI or PSSI depending which interface is active) Set and reset by software. - DCMI_PSSILPEN: u1, - reserved16: u3, - /// AES clock enable during sleep mode Set and reset by software. - AESLPEN: u1, - /// HASH clock enable during sleep mode Set and reset by software. - HASHLPEN: u1, - /// RNG clock enable during sleep mode Set and reset by software. - RNGLPEN: u1, - /// PKA clock enable during sleep mode Set and reset by software. - PKALPEN: u1, - /// SAES clock enable during sleep mode Set and reset by software. - SAESLPEN: u1, - reserved30: u9, - /// SRAM2 clock enable during sleep mode Set and reset by software. - SRAM2LPEN: u1, - /// SRAM3 clock enable during sleep mode Set and reset by software. - SRAM3LPEN: u1, + /// High Resolution Timer: External Event Control Register 1 + EECR1: mmio.Mmio(packed struct(u32) { + /// External Event X Source + EESRC: u2, + /// External Event X Polarity + EEPOL: u1, + /// External Event X Sensitivity + EESNS: u2, + /// External Event X Fast Mode + EEFAST: u2, + padding: u25, }), - reserved188: [4]u8, - /// RCC AHB4 sleep clock register - AHB4LPENR: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// OTFDEC1 clock enable during sleep mode Set and reset by software. - OTFDEC1LPEN: u1, - reserved11: u3, - /// SDMMC1 and SDMMC1 delay peripheral clock enable during sleep mode Set and reset by software - SDMMC1LPEN: u1, - /// SDMMC2 and SDMMC2 delay peripheral clock enable during sleep mode Set and reset by software. - SDMMC2LPEN: u1, - reserved16: u3, - /// FMC clock enable during sleep mode Set and reset by software. - FMCLPEN: u1, - reserved20: u3, - /// OCTOSPI1 clock enable during sleep mode Set and reset by software. - OCTOSPI1LPEN: u1, - padding: u11, + /// High Resolution Timer: External Event Control Register 2 + EECR2: mmio.Mmio(packed struct(u32) { + /// External Event X Source + EESRC: u2, + /// External Event X Polarity + EEPOL: u1, + /// External Event X Sensitivity + EESNS: u2, + padding: u27, }), - reserved196: [4]u8, - /// RCC APB1 sleep clock register - APB1LLPENR: mmio.Mmio(packed struct(u32) { - /// TIM2 clock enable during sleep mode Set and reset by software. - TIM2LPEN: u1, - /// TIM3 clock enable during sleep mode Set and reset by software. - TIM3LPEN: u1, - /// TIM4 clock enable during sleep mode Set and reset by software. - TIM4LPEN: u1, - /// TIM5 clock enable during sleep mode Set and reset by software. - TIM5LPEN: u1, - /// TIM6 clock enable during sleep mode Set and reset by software. - TIM6LPEN: u1, - /// TIM7 clock enable during sleep mode Set and reset by software. - TIM7LPEN: u1, - /// TIM12 clock enable during sleep mode Set and reset by software. - TIM12LPEN: u1, - /// TIM13 clock enable during sleep mode Set and reset by software. - TIM13LPEN: u1, - /// TIM14 clock enable during sleep mode Set and reset by software. - TIM14LPEN: u1, - reserved11: u2, - /// WWDG clock enable during sleep mode Set and reset by software. - WWDGLPEN: u1, - reserved14: u2, - /// SPI2 clock enable during sleep mode Set and reset by software. - SPI2LPEN: u1, - /// SPI3 clock enable during sleep mode Set and reset by software. - SPI3LPEN: u1, - reserved17: u1, - /// USART2 clock enable during sleep mode Set and reset by software. - USART2LPEN: u1, - /// USART3 clock enable during sleep mode Set and reset by software. - USART3LPEN: u1, - /// UART4 clock enable during sleep mode Set and reset by software. - UART4LPEN: u1, - /// UART5 clock enable during sleep mode Set and reset by software. - UART5LPEN: u1, - /// I2C1 clock enable during sleep mode Set and reset by software. - I2C1LPEN: u1, - /// I2C2 clock enable during sleep mode Set and reset by software. - I2C2LPEN: u1, - /// I3C1 clock enable during sleep mode Set and reset by software. - I3C1LPEN: u1, - /// CRS clock enable during sleep mode Set and reset by software. - CRSLPEN: u1, - /// USART6 clock enable during sleep mode Set and reset by software. - USART6LPEN: u1, - /// USART10 clock enable during sleep mode Set and reset by software. - USART10LPEN: u1, - /// USART11 clock enable during sleep mode Set and reset by software. - USART11LPEN: u1, - /// HDMI-CEC clock enable during sleep mode Set and reset by software. - CECLPEN: u1, - reserved30: u1, - /// UART7 clock enable during sleep mode Set and reset by software. - UART7LPEN: u1, - /// UART8 clock enable during sleep mode Set and reset by software. - UART8LPEN: u1, + /// High Resolution Timer: External Event Control Register 3 + EECR3: mmio.Mmio(packed struct(u32) { + /// External Event X filter + EEF: u3, + reserved30: u27, + /// External Event Sampling Clock Division + EEVSD: u2, }), - /// RCC APB1 sleep clock register - APB1HLPENR: mmio.Mmio(packed struct(u32) { - /// UART9 clock enable during sleep mode Set and reset by software. - UART9LPEN: u1, - /// UART12 clock enable during sleep mode Set and reset by software. - UART12LPEN: u1, - reserved3: u1, - /// DTS clock enable during sleep mode Set and reset by software. - DTSLPEN: u1, - reserved5: u1, - /// LPTIM2 clock enable during sleep mode Set and reset by software. - LPTIM2LPEN: u1, - reserved9: u3, - /// FDCAN1 and FDCAN2 peripheral clock enable during sleep mode Set and reset by software. - FDCAN12LPEN: u1, - reserved23: u13, - /// UCPD clock enable during sleep mode Set and reset by software. - UCPDLPEN: u1, - padding: u8, + /// High Resolution Timer: ADC Trigger [1, 3] Register + ADC1R: mmio.Mmio(packed struct(u32) { + /// ADC trigger X on Master Compare Y + ADCMC: u1, + reserved4: u3, + /// ADC trigger X on Master Period + ADCMPER: u1, + /// ADC trigger X on External Event Y + ADCEEV: u1, + reserved10: u4, + /// ADC trigger X on Timer Y Compare 2 + ADCTC2: u1, + /// ADC trigger X on Timer Y Compare 3 + ADCTC3: u1, + /// ADC trigger X on Timer Y Compare 3 + ADCTC4: u1, + /// ADC trigger X on Timer Y Period + ADCTPER: u1, + /// ADC trigger X on Timer Y Reset + ADCTRST: u1, + padding: u17, }), - /// RCC APB2 sleep clock register - APB2LPENR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 clock enable during sleep mode Set and reset by software. - TIM1LPEN: u1, - /// SPI1 clock enable during sleep mode Set and reset by software. - SPI1LPEN: u1, - /// TIM8 clock enable during sleep mode Set and reset by software. - TIM8LPEN: u1, - /// USART1 clock enable during sleep mode Set and reset by software. - USART1LPEN: u1, - reserved16: u1, - /// TIM15 clock enable during sleep mode Set and reset by software. - TIM15LPEN: u1, - /// TIM16 clock enable during sleep mode Set and reset by software. - TIM16LPEN: u1, - /// TIM17 clock enable during sleep mode Set and reset by software. - TIM17LPEN: u1, - /// SPI4 clock enable during sleep mode Set and reset by software. - SPI4LPEN: u1, - /// SPI6 clock enable during sleep mode Set and reset by software. - SPI6LPEN: u1, - /// SAI1 clock enable during sleep mode Set and reset by software. - SAI1LPEN: u1, - /// SAI2 clock enable during sleep mode Set and reset by software. - SAI2LPEN: u1, - reserved24: u1, - /// USB clock enable during sleep mode Set and reset by software. - USBLPEN: u1, - padding: u7, + /// High Resolution Timer: ADC Trigger [2, 4] Register + ADC2R: mmio.Mmio(packed struct(u32) { + /// ADC trigger X on Master Compare Y + ADCMC: u1, + reserved4: u3, + /// ADC trigger X on Master Period + ADCMPER: u1, + /// ADC trigger X on External Event Y + ADCEEV: u1, + reserved10: u4, + /// ADC trigger X on Timer Y Compare 2 + ADCTC2: u1, + reserved12: u1, + /// ADC trigger X on Timer Y Compare 3 + ADCTC4: u1, + /// ADC trigger X on Timer Y Period + ADCTPER: u1, + reserved15: u1, + /// ADC trigger X on Timer Y Compare 3 + ADCTC3: u1, + reserved22: u6, + /// ADC trigger X on Timer Y Reset + ADCTRST: u1, + padding: u9, }), - /// RCC APB3 sleep clock register - APB3LPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SBS clock enable during sleep mode Set and reset by software. - SYSCFGLPEN: u1, - reserved5: u3, - /// SPI5 clock enable during Slsleepeep mode Set and reset by software. - SPI5LPEN: u1, - /// LPUART1 clock enable during sleep mode Set and reset by software. - LPUART1LPEN: u1, - /// I2C3 clock enable during sleep mode Set and reset by software. - I2C3LPEN: u1, - /// I2C4 clock enable during sleep mode Set and reset by software. - I2C4LPEN: u1, - reserved11: u2, - /// LPTIM1 clock enable during sleep mode Set and reset by software. - LPTIM1LPEN: u1, - /// LPTIM3 clock enable during sleep mode Set and reset by software. - LPTIM3LPEN: u1, - /// LPTIM4 clock enable during sleep mode Set and reset by software. - LPTIM4LPEN: u1, - /// LPTIM5 clock enable during sleep mode Set and reset by software. - LPTIM5LPEN: u1, - /// LPTIM6 clock enable during sleep mode Set and reset by software. - LPTIM6LPEN: u1, - reserved20: u4, - /// VREF clock enable during sleep mode Set and reset by software. - VREFLPEN: u1, - /// RTC APB interface clock enable during sleep mode Set and reset by software. - RTCAPBLPEN: u1, - padding: u10, + reserved972: [8]u8, + /// High Resolution Timer: DLL Control Register + DLLCR: mmio.Mmio(packed struct(u32) { + /// DLL Calibration Start + CAL: u1, + /// DLL Calibration Enable + CALEN: u1, + /// DLL Calibration Rate + CALRTE: u2, + padding: u28, }), - reserved216: [4]u8, - /// RCC kernel clock configuration register - CCIPR1: mmio.Mmio(packed struct(u32) { - /// USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - USART1SEL: packed union { - raw: u3, - value: USART1SEL, - }, - /// USART2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - USART2SEL: packed union { - raw: u3, - value: USARTSEL, - }, - /// USART3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - USART3SEL: packed union { - raw: u3, - value: USARTSEL, - }, - /// UART4 kernel clock source selection others: reserved, the kernel clock is disabled - UART4SEL: packed union { - raw: u3, - value: USARTSEL, - }, - /// UART5 kernel clock source selection others: reserved, the kernel clock is disabled - UART5SEL: packed union { - raw: u3, - value: USARTSEL, - }, - /// USART6 kernel clock source selection others: reserved, the kernel clock is disabled - USART6SEL: packed union { - raw: u3, - value: USARTSEL, + /// High Resolution Timer: Fault Input Register 1 + FLTINR1: mmio.Mmio(packed struct(u32) { + /// Fault X enable + FLTE: u1, + /// Fault X polarity + FLTP: u1, + /// Fault X source + FLTSRC: u1, + /// Fault X filter + FLTF: u4, + /// Fault X Lock + FLTLCK: u1, + padding: u24, + }), + reserved984: [4]u8, + /// High Resolution Timer: Burst DMA Master timer update Register + BDMUPR: mmio.Mmio(packed struct(u32) { + /// MCR register update enable + MCR: u1, + /// MICR register update enable + MICR: u1, + /// MDIER register update enable + MDIER: u1, + /// MCNT register update enable + MCNT: u1, + /// MPER register update enable + MPER: u1, + /// MREP register update enable + MREP: u1, + /// MCMP register X update enable + MCMP: u1, + padding: u25, + }), + /// High Resolution Timer: Burst DMA Timer X update Register + BDTUPR: [5]mmio.Mmio(packed struct(u32) { + /// CR register update enable + CR: u1, + /// ICR register update enable + ICR: u1, + /// DIER register update enable + DIER: u1, + /// CNT register update enable + CNT: u1, + /// PER register update enable + PER: u1, + /// REP register update enable + REP: u1, + /// CMP register X update enable + CMP: u1, + padding: u25, + }), + /// High Resolution Timer: Burst DMA Data Register + BDMADR: mmio.Mmio(packed struct(u32) { + /// Burst DMA Data register + BDMADR: u31, + padding: u1, + }), + }; + + /// High Resolution Timer: Timing Unit + pub const HRTIM_TIMX = extern struct { + /// Timer X Control Register + CR: mmio.Mmio(packed struct(u32) { + /// HRTIM Timer x Clock prescaler + CKPSC: u3, + /// Continuous mode + CONT: u1, + /// Re-triggerable mode + RETRIG: u1, + /// Half mode enable + HALF: u1, + /// Push-Pull mode enable + PSHPLL: u1, + reserved10: u3, + /// Synchronization Resets Timer X + SYNCRST: packed union { + raw: u1, + value: SYNCRST, }, - /// UART7 kernel clock source selection others: reserved, the kernel clock is disabled - UART7SEL: packed union { - raw: u3, - value: USARTSEL, + /// Synchronization Starts Timer X + SYNCSTRT: packed union { + raw: u1, + value: SYNCSTRT, }, - /// UART8 kernel clock source selection others: reserved, the kernel clock is disabled - UART8SEL: packed union { - raw: u3, - value: USARTSEL, + /// Delayed CMP2 mode + DELCMP2: packed union { + raw: u2, + value: DELCMP, }, - /// UART9 kernel clock source selection others: reserved, the kernel clock is disabled - UART9SEL: packed union { - raw: u3, - value: USARTSEL, + /// Delayed CMP4 mode + DELCMP4: packed union { + raw: u2, + value: DELCMP, }, - /// USART10 kernel clock source selection others: reserved, the kernel clock is disabled - USART10SEL: packed union { - raw: u3, - value: USARTSEL, + reserved17: u1, + /// Timer X Repetition update + REPU: u1, + /// Timer X reset update + RSTU: u1, + /// Timer A update + TAU: u1, + /// Timer B update + TBU: u1, + /// Timer C update + TCU: u1, + /// Timer D update + TDU: u1, + /// Timer E update + TEU: u1, + /// Master Timer update + MSTU: u1, + /// AC Synchronization + DACSYNC: packed union { + raw: u2, + value: DACSYNC, }, - reserved31: u1, - /// TIM12, TIM15 and LPTIM2 input capture source selection Set and reset by software. - TIMICSEL: packed union { - raw: u1, - value: TIMICSEL, + /// Preload enable + PREEN: u1, + /// Update Gating + UPDGAT: packed union { + raw: u4, + value: UPDGAT, }, }), - /// RCC kernel clock configuration register - CCIPR2: mmio.Mmio(packed struct(u32) { - /// USART11 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - USART11SEL: packed union { - raw: u3, - value: USARTSEL, - }, - reserved4: u1, - /// USART12 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - USART12SEL: packed union { - raw: u3, - value: USARTSEL, - }, - reserved8: u1, - /// LPTIM1 kernel clock source selection others: reserved, the kernel clock is disabled - LPTIM1SEL: packed union { - raw: u3, - value: LPTIMSEL, - }, - reserved12: u1, - /// LPTIM2 kernel clock source selection others: reserved, the kernel clock is disabled - LPTIM2SEL: packed union { - raw: u3, - value: LPTIM2SEL, + /// Timer X Interrupt Status Register + ISR: mmio.Mmio(packed struct(u32) { + /// Compare X Interrupt Flag + CMP: u1, + reserved4: u3, + /// Repetition Interrupt Flag + REP: u1, + reserved6: u1, + /// Update Interrupt Flag + UPD: u1, + /// Capture X Interrupt Flag + CPT: u1, + reserved9: u1, + /// Output X Set Interrupt Flag + SETR: u1, + /// Output X Reset Interrupt Flag + RSTR: u1, + reserved13: u2, + /// Reset Interrupt Flag + RST: u1, + /// Delayed Protection Flag + DLYPRT: packed union { + raw: u1, + value: TIMAISR_DLYPRT, }, reserved16: u1, - /// LPTIM3 kernel clock source selection others: reserved, the kernel clock is disabled - LPTIM3SEL: packed union { - raw: u3, - value: LPTIMSEL, + /// Current Push Pull Status + CPPSTAT: packed union { + raw: u1, + value: CPPSTAT, }, - reserved20: u1, - /// LPTIM4 kernel clock source selection others: reserved, the kernel clock is disabled - LPTIM4SEL: packed union { - raw: u3, - value: LPTIMSEL, + /// Idle Push Pull Status + IPPSTAT: packed union { + raw: u1, + value: IPPSTAT, }, - reserved24: u1, - /// LPTIM5 kernel clock source selection others: reserved, the kernel clock is disabled - LPTIM5SEL: packed union { - raw: u3, - value: LPTIMSEL, + /// Output X State + OSTAT: packed union { + raw: u1, + value: OUTPUTSTATE, }, - reserved28: u1, - /// LPTIM6 kernel clock source selection others: reserved, the kernel clock is disabled - LPTIM6SEL: packed union { - raw: u3, - value: LPTIMSEL, + reserved20: u1, + /// Output X Copy + OCPY: packed union { + raw: u1, + value: OUTPUTSTATE, }, + padding: u11, + }), + /// Timer X Interrupt Clear Register + ICR: mmio.Mmio(packed struct(u32) { + /// Compare X Interrupt flag Clear + CMPC: u1, + reserved4: u3, + /// Repetition Interrupt flag Clear + REPC: u1, + reserved6: u1, + /// Update Interrupt flag Clear + UPDC: u1, + /// Capture X Interrupt flag Clear + CPTC: u1, + reserved9: u1, + /// Output X Set flag Clear + SETRC: u1, + /// Output X Reset flag Clear + RSTRC: u1, + reserved13: u2, + /// Reset Interrupt flag Clear + RSTC: u1, + /// Delayed Protection Flag Clear + DLYPRTC: u1, + padding: u17, + }), + /// Timer X DMA / Interrupt Enable Register + DIER: mmio.Mmio(packed struct(u32) { + /// Compare X Interrupt Enable + CMPIE: u1, + reserved4: u3, + /// Repetition Interrupt Enable + REPIE: u1, + reserved6: u1, + /// Update Interrupt Enable + UPDIE: u1, + /// Capture Interrupt Enable + CPTIE: u1, + reserved9: u1, + /// Output X Set Interrupt Enable + SETRIE: u1, + /// Output X Reset Interrupt Enable + RSTRIE: u1, + reserved13: u2, + /// Reset/roll-over Interrupt Enable + RSTIE: u1, + /// Delayed Protection Interrupt Enable + DLYPRTIE: u1, + reserved16: u1, + /// Compare X DMA request Enable + CMPDE: u1, + reserved20: u3, + /// Repetition DMA request Enable + REPDE: u1, + reserved22: u1, + /// Update DMA request Enable + UPDDE: u1, + /// Capture X DMA request Enable + CPTDE: u1, + reserved25: u1, + /// Output X Set DMA request Enable + SETRDE: u1, + /// Output X Reset DMA request Enable + RSTRDE: u1, + reserved29: u2, + /// Reset/roll-over DMA request Enable + RSTDE: u1, + /// Delayed Protection DMA request Enable + DLYPRTDE: u1, padding: u1, }), - /// RCC kernel clock configuration register - CCIPR3: mmio.Mmio(packed struct(u32) { - /// SPI1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - SPI1SEL: packed union { - raw: u3, - value: SPI1SEL, + /// Timer X Counter Register + CNT: mmio.Mmio(packed struct(u32) { + /// Timerx Counter value + CNT: u16, + padding: u16, + }), + /// Timer X Period Register + PER: mmio.Mmio(packed struct(u32) { + /// Timerx Period value + PER: u16, + padding: u16, + }), + /// Timer X Repetition Register + REP: mmio.Mmio(packed struct(u32) { + /// Timerx Repetition counter value + REP: u8, + padding: u24, + }), + /// Timer X Compare X Register + CMP: mmio.Mmio(packed struct(u32) { + /// Timerx Compare X value + CMP: u16, + padding: u16, + }), + /// Timer X Compare X Compound Register + CMPC: mmio.Mmio(packed struct(u32) { + /// Timerx Compare X value + CMP: u16, + /// Timerx Repetition value (aliased from HRTIM_REPx register) + REP: u8, + padding: u8, + }), + reserved48: [12]u8, + /// Timer X Capture X Register + CPT: [2]mmio.Mmio(packed struct(u32) { + /// Timerx Capture X value + CPT: u16, + padding: u16, + }), + /// Timer X Deadtime Register + DT: mmio.Mmio(packed struct(u32) { + /// Deadtime Rising value + DTR: u9, + /// Sign Deadtime Rising value + SDTR: packed union { + raw: u1, + value: SDTR, }, - /// SPI2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - SPI2SEL: packed union { - raw: u3, - value: SPI2SEL, + /// Deadtime Prescaler + DTPRSC: u3, + reserved14: u1, + /// Deadtime Rising Sign Lock + DTRSLK: u1, + /// Deadtime Rising Lock + DTRLK: u1, + /// Deadtime Falling value + DTF: u9, + /// Sign Deadtime Falling value + SDTF: packed union { + raw: u1, + value: SDTF, }, - /// SPI3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled - SPI3SEL: packed union { - raw: u3, - value: SPI3SEL, + reserved30: u4, + /// Deadtime Falling Sign Lock + DTFSLK: u1, + /// Deadtime Falling Lock + DTFLK: u1, + }), + /// Timer X Output X Set Register + SETR: mmio.Mmio(packed struct(u32) { + /// Software Set trigger + SST: packed union { + raw: u1, + value: ACTIVEEFFECT, }, - /// SPI4 kernel clock source selection others: reserved, the kernel clock is disabled - SPI4SEL: packed union { - raw: u3, - value: SPI4SEL, + /// Timer X resynchronizaton + RESYNC: packed union { + raw: u1, + value: ACTIVEEFFECT, }, - /// SPI5 kernel clock source selection others: reserved, the kernel clock is disabled - SPI5SEL: packed union { - raw: u3, - value: SPI5SEL, + /// Timer X Period + PER: packed union { + raw: u1, + value: ACTIVEEFFECT, }, - /// SPI6 kernel clock source selection others: reserved, the kernel clock is disabled - SPI6SEL: packed union { - raw: u3, - value: SPI6SEL, + /// Timer X compare X + CMP: packed union { + raw: u1, + value: ACTIVEEFFECT, }, - reserved24: u6, - /// LPUART1 kernel clock source selection others: reserved, the kernel clock is disabled - LPUART1SEL: packed union { - raw: u3, - value: LPUSARTSEL, + reserved7: u3, + /// Master Period + MSTPER: packed union { + raw: u1, + value: ACTIVEEFFECT, }, - padding: u5, - }), - /// RCC kernel clock configuration register - CCIPR4: mmio.Mmio(packed struct(u32) { - /// OCTOSPI1 kernel clock source selection Set and reset by software. - OCTOSPI1SEL: packed union { - raw: u2, - value: OCTOSPISEL, + /// Master Compare X + MSTCMPX: packed union { + raw: u1, + value: ACTIVEEFFECT, }, - /// SYSTICK clock source selection Note: rcc_hclk frequency must be four times higher than lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK). - SYSTICKSEL: packed union { - raw: u2, - value: SYSTICKSEL, + reserved12: u3, + /// Timer Event X + TIMEVNT: packed union { + raw: u1, + value: ACTIVEEFFECT, }, - /// USB kernel clock source selection - USBSEL: packed union { - raw: u2, - value: USBSEL, + reserved21: u8, + /// External Event X + EXTEVNT: packed union { + raw: u1, + value: ACTIVEEFFECT, }, - /// SDMMC1 kernel clock source selection - SDMMC1SEL: packed union { + reserved31: u9, + /// Registers update (transfer preload to active) + UPDATE: packed union { raw: u1, - value: SDMMCSEL, + value: ACTIVEEFFECT, }, - /// SDMMC2 kernel clock source selection - SDMMC2SEL: packed union { + }), + /// Timer X Output X Reset Register + RSTR: mmio.Mmio(packed struct(u32) { + /// Software Reset trigger + SRT: packed union { raw: u1, - value: SDMMCSEL, + value: INACTIVEEFFECT, }, - reserved16: u8, - /// I2C1 kernel clock source selection - I2C1SEL: packed union { - raw: u2, - value: I2CSEL, + /// Timer X resynchronizaton + RESYNC: packed union { + raw: u1, + value: INACTIVEEFFECT, }, - /// I2C2 kernel clock source selection - I2C2SEL: packed union { - raw: u2, - value: I2CSEL, + /// Timer X Period + PER: packed union { + raw: u1, + value: INACTIVEEFFECT, }, - /// I2C3 kernel clock source selection - I2C3SEL: packed union { - raw: u2, - value: I2C34SEL, + /// Timer X compare X + CMP: packed union { + raw: u1, + value: INACTIVEEFFECT, }, - /// I2C4 kernel clock source selection - I2C4SEL: packed union { - raw: u2, - value: I2C34SEL, + reserved7: u3, + /// Master Period + MSTPER: packed union { + raw: u1, + value: INACTIVEEFFECT, }, - /// I3C1 kernel clock source selection - I3C1SEL: packed union { - raw: u2, - value: I2CSEL, + /// Master Compare X + MSTCMP: packed union { + raw: u1, + value: INACTIVEEFFECT, }, - padding: u6, - }), - /// RCC kernel clock configuration register - CCIPR5: mmio.Mmio(packed struct(u32) { - /// ADC and DAC kernel clock source selection others: reserved, the kernel clock is disabled - ADCDACSEL: packed union { - raw: u3, - value: ADCDACSEL, + reserved12: u3, + /// Timer Event X + TIMEVNT: packed union { + raw: u1, + value: INACTIVEEFFECT, }, - /// DAC hold clock - DACHOLDSEL: packed union { + reserved21: u8, + /// External Event X + EXTEVNT: packed union { raw: u1, - value: DACHOLDSEL, + value: INACTIVEEFFECT, }, - /// RNG kernel clock source selection - RNGSEL: packed union { - raw: u2, - value: RNGSEL, + reserved31: u9, + /// Registers update (transfer preload to active) + UPDATE: packed union { + raw: u1, + value: INACTIVEEFFECT, }, - /// HSMI-CEC kernel clock source selection - CECSEL: packed union { - raw: u2, - value: CECSEL, + }), + reserved76: [8]u8, + /// Timer X External Event Filtering Register 1 + EEF: mmio.Mmio(packed struct(u32) { + /// External Event X latch + LTCH: u1, + /// External Event X filter + FLTR: packed union { + raw: u4, + value: EEFLTR, }, - /// FDCAN1 and FDCAN2 kernel clock source selection - FDCAN12SEL: packed union { - raw: u2, - value: FDCANSEL, + padding: u27, + }), + reserved84: [4]u8, + /// Timer X Reset Register + RST: mmio.Mmio(packed struct(u32) { + /// Timer X compare 1 event + TCMP1: packed union { + raw: u1, + value: RESETEFFECT, }, - reserved16: u6, - /// SAI1 kernel clock source selection others: reserved, the kernel clock is disabled - SAI1SEL: packed union { - raw: u3, - value: SAISEL, + /// Timer X Update reset + UPDT: packed union { + raw: u1, + value: RESETEFFECT, }, - /// SAI2 kernel clock source selection others: reserved, the kernel clock is disabled - SAI2SEL: packed union { - raw: u3, - value: SAISEL, + /// Timer X compare X reset + CMP: packed union { + raw: u1, + value: RESETEFFECT, }, - reserved30: u8, - /// per_ck clock source selection - PERSEL: packed union { - raw: u2, - value: PERSEL, + reserved4: u1, + /// Master timer Period + MSTPER: packed union { + raw: u1, + value: RESETEFFECT, }, - }), - reserved240: [4]u8, - /// RCC Backup domain control register - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enabled Set and reset by software. - LSEON: u1, - /// LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0. - LSERDY: u1, - /// LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1) - LSEBYP: u1, - /// LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0). - LSEDRV: packed union { - raw: u2, - value: LSEDRV, + /// Master compare X + MSTCMP: packed union { + raw: u1, + value: RESETEFFECT, }, - /// LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON. - LSECSSON: u1, - /// LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator. - LSECSSD: u1, - /// low-speed external clock type in bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled. - LSEEXT: packed union { + reserved9: u3, + /// External Event X + EXTEVNT: packed union { raw: u1, - value: LSEEXT, + value: RESETEFFECT, }, - /// RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST). - RTCSEL: packed union { - raw: u2, - value: RTCSEL, + reserved20: u10, + /// Timer X compare 2 event + TCMP2: packed union { + raw: u1, + value: RESETEFFECT, }, - reserved15: u5, - /// RTC clock enable Set and reset by software. - RTCEN: u1, - /// VSwitch domain software reset Set and reset by software. - VSWRST: u1, - reserved24: u7, - /// Low-speed clock output (LSCO) enable Set and cleared by software. - LSCOEN: u1, - /// Low-speed clock output selection Set and cleared by software. - LSCOSEL: packed union { + /// Timer X compare 4 event + TCMP4: packed union { raw: u1, - value: LSCOSEL, + value: RESETEFFECT, }, - /// LSI oscillator enable Set and cleared by software. - LSION: u1, - /// LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0. - LSIRDY: u1, - padding: u4, - }), - /// RCC reset status register - RSR: mmio.Mmio(packed struct(u32) { - reserved23: u23, - /// remove reset flag Set and reset by software to reset the value of the reset flags. - RMVF: u1, - reserved26: u2, - /// pin reset flag (NRST) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. - PINRSTF: u1, - /// BOR reset flag Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). - BORRSTF: u1, - /// system reset from CPU reset flag Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33. - SFTRSTF: u1, - /// independent watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. - IWDGRSTF: u1, - /// window watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. - WWDGRSTF: u1, - /// Low-power reset flag Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared. Cleared by writing to the RMVF bit. - LPWRRSTF: u1, + padding: u10, }), - reserved272: [24]u8, - /// RCC secure configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// HSI clock configuration and status bits security Set and reset by software. - HSISEC: u1, - /// HSE clock configuration bits, status bits and HSE_CSS security Set and reset by software. - HSESEC: u1, - /// CSI clock configuration and status bits security Set and reset by software. - CSISEC: u1, - /// LSI clock configuration and status bits security Set and reset by software. - LSISEC: u1, - /// LSE clock configuration and status bits security Set and reset by software. - LSESEC: u1, - /// SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security Set and reset by software. - SYSCLKSEC: u1, - /// AHBx/APBx prescaler configuration bits security Set and reset by software. - PRESCSEC: u1, - /// PLL1 clock configuration and status bits security Set and reset by software. - PLLSEC: u1, - reserved11: u3, - /// HSI48 clock configuration and status bits security Set and reset by software. - HSI48SEC: u1, - /// Remove reset flag security Set and reset by software. - RMVFSEC: u1, - /// per_ck selection security Set and reset by software. - PERSELSEC: u1, - padding: u18, + /// Timer X Chopper Register + CHP: mmio.Mmio(packed struct(u32) { + /// Timerx carrier frequency value + CARFRQ: u4, + /// Timerx chopper duty cycle value + CARDTY: u3, + /// Timerx start pulsewidth + STRTPW: u4, + padding: u21, }), - /// RCC privilege configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access. - SPRIV: packed union { + /// Timer X Capture X Control Register + CCR: mmio.Mmio(packed struct(u32) { + /// Software Capture + SWCPT: packed union { raw: u1, - value: SPRIV, + value: CAPTUREEFFECT, }, - /// RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure. - NSPRIV: packed union { + /// Update Capture + UPDCPT: packed union { raw: u1, - value: NSPRIV, + value: CAPTUREEFFECT, }, - padding: u30, - }), - }; - }; - - pub const adccommon_h50 = struct { - pub const CKMODE = enum(u2) { - /// Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock - Asynchronous = 0x0, - /// Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck - SyncDiv1 = 0x1, - /// Use AHB clock rcc_hclk3 divided by 2 - SyncDiv2 = 0x2, - /// Use AHB clock rcc_hclk3 divided by 4 - SyncDiv4 = 0x3, - }; - - pub const IDLEVALUE = enum(u4) { - /// Dummy channel selection is 0x13 - H13 = 0x0, - /// Dummy channel selection is 0x1F - H1F = 0x1, - _, - }; - - pub const PRESC = enum(u4) { - /// adc_ker_ck_input not divided - Div1 = 0x0, - /// adc_ker_ck_input divided by 2 - Div2 = 0x1, - /// adc_ker_ck_input divided by 4 - Div4 = 0x2, - /// adc_ker_ck_input divided by 6 - Div6 = 0x3, - /// adc_ker_ck_input divided by 8 - Div8 = 0x4, - /// adc_ker_ck_input divided by 10 - Div10 = 0x5, - /// adc_ker_ck_input divided by 12 - Div12 = 0x6, - /// adc_ker_ck_input divided by 16 - Div16 = 0x7, - /// adc_ker_ck_input divided by 32 - Div32 = 0x8, - /// adc_ker_ck_input divided by 64 - Div64 = 0x9, - /// adc_ker_ck_input divided by 128 - Div128 = 0xa, - /// adc_ker_ck_input divided by 256 - Div256 = 0xb, - _, - }; - - /// ADC common registers - pub const ADC_COMMON = extern struct { - reserved8: [8]u8, - /// common control register - CCR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). - CKMODE: packed union { - raw: u2, - value: CKMODE, + /// External Event X Capture + EXEVCPT: packed union { + raw: u1, + value: CAPTUREEFFECT, }, - /// ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00. - PRESC: packed union { - raw: u4, - value: PRESC, + reserved16: u13, + /// Timer X output Set + TXSET: packed union { + raw: u1, + value: CAPTUREEFFECT, }, - /// VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel - VREFEN: u1, - /// VSENSE enable This bit is set and cleared by software to control VSENSE - TSEN: u1, - /// VBAT enable This bit is set and cleared by software to control - VBATEN: u1, - padding: u7, - }), - reserved240: [228]u8, - /// hardware configuration register - HWCFGR0: mmio.Mmio(packed struct(u32) { - /// Number of ADCs implemented - ADCNUM: u4, - /// Number of pipeline stages - MULPIPE: u4, - /// Number of option bits 0002: 2 option bits implemented in the ADC option register (ADC_OR) at address offset 0xC8. - OPBITS: u4, - /// Idle value for non-selected channels - IDLEVALUE: packed union { - raw: u4, - value: IDLEVALUE, + /// Timer X output Reset + TXRST: packed union { + raw: u1, + value: CAPTUREEFFECT, }, - padding: u16, - }), - /// version register - VERR: mmio.Mmio(packed struct(u32) { - /// Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2. - MINREV: u4, - /// Major revision These bits returns the ADC IP major revision - MAJREV: u4, - padding: u24, - }), - /// identification register - IPDR: u32, - /// size identification register - SIDR: u32, - }; - }; - - pub const i2c_v2 = struct { - pub const ADDMODE = enum(u1) { - /// 7-bit addressing mode - Bit7 = 0x0, - /// 10-bit addressing mode - Bit10 = 0x1, - }; - - pub const AUTOEND = enum(u1) { - /// Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low - Software = 0x0, - /// Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred - Automatic = 0x1, - }; - - pub const DIR = enum(u1) { - /// Write transfer, slave enters receiver mode - Write = 0x0, - /// Read transfer, slave enters transmitter mode - Read = 0x1, - }; - - pub const DNF = enum(u4) { - /// Digital filter disabled - NoFilter = 0x0, - /// Digital filter enabled and filtering capability up to 1 tI2CCLK - Filter1 = 0x1, - /// Digital filter enabled and filtering capability up to 2 tI2CCLK - Filter2 = 0x2, - /// Digital filter enabled and filtering capability up to 3 tI2CCLK - Filter3 = 0x3, - /// Digital filter enabled and filtering capability up to 4 tI2CCLK - Filter4 = 0x4, - /// Digital filter enabled and filtering capability up to 5 tI2CCLK - Filter5 = 0x5, - /// Digital filter enabled and filtering capability up to 6 tI2CCLK - Filter6 = 0x6, - /// Digital filter enabled and filtering capability up to 7 tI2CCLK - Filter7 = 0x7, - /// Digital filter enabled and filtering capability up to 8 tI2CCLK - Filter8 = 0x8, - /// Digital filter enabled and filtering capability up to 9 tI2CCLK - Filter9 = 0x9, - /// Digital filter enabled and filtering capability up to 10 tI2CCLK - Filter10 = 0xa, - /// Digital filter enabled and filtering capability up to 11 tI2CCLK - Filter11 = 0xb, - /// Digital filter enabled and filtering capability up to 12 tI2CCLK - Filter12 = 0xc, - /// Digital filter enabled and filtering capability up to 13 tI2CCLK - Filter13 = 0xd, - /// Digital filter enabled and filtering capability up to 14 tI2CCLK - Filter14 = 0xe, - /// Digital filter enabled and filtering capability up to 15 tI2CCLK - Filter15 = 0xf, - }; - - pub const HEADR = enum(u1) { - /// The master sends the complete 10 bit slave address read sequence - Complete = 0x0, - /// The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction - Partial = 0x1, - }; - - pub const OAMSK = enum(u3) { - /// No mask - NoMask = 0x0, - /// OA2[1] is masked and don’t care. Only OA2[7:2] are compared - Mask1 = 0x1, - /// OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared - Mask2 = 0x2, - /// OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared - Mask3 = 0x3, - /// OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared - Mask4 = 0x4, - /// OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared - Mask5 = 0x5, - /// OA2[6:1] are masked and don’t care. Only OA2[7] is compared. - Mask6 = 0x6, - /// OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged - Mask7 = 0x7, - }; - - pub const RELOAD = enum(u1) { - /// The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) - Completed = 0x0, - /// The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) - NotCompleted = 0x1, - }; - - /// Inter-integrated circuit - pub const I2C = extern struct { - /// Control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Peripheral enable - PE: u1, - /// TX Interrupt enable - TXIE: u1, - /// RX Interrupt enable - RXIE: u1, - /// Address match interrupt enable (slave only) - ADDRIE: u1, - /// Not acknowledge received interrupt enable - NACKIE: u1, - /// STOP detection Interrupt enable - STOPIE: u1, - /// Transfer Complete interrupt enable - TCIE: u1, - /// Error interrupts enable - ERRIE: u1, - /// Digital noise filter - DNF: packed union { - raw: u4, - value: DNF, + /// Timer X Compare X + TXCMP: packed union { + raw: u1, + value: CAPTUREEFFECT, }, - /// Analog noise filter OFF - ANFOFF: u1, - reserved14: u1, - /// DMA transmission requests enable - TXDMAEN: u1, - /// DMA reception requests enable - RXDMAEN: u1, - /// Slave byte control - SBC: u1, - /// Clock stretching disable - NOSTRETCH: u1, - reserved19: u1, - /// General call enable - GCEN: u1, - /// SMBus Host address enable - SMBHEN: u1, - /// SMBus Device Default address enable - SMBDEN: u1, - /// SMBUS alert enable - ALERTEN: u1, - /// PEC enable - PECEN: u1, - padding: u8, - }), - /// Control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Slave address bit (master mode) - SADD: u10, - /// Transfer direction (master mode) - DIR: packed union { + reserved20: u1, + /// Timer Y output Set + TYSET: packed union { raw: u1, - value: DIR, + value: CAPTUREEFFECT, }, - /// 10-bit addressing mode (master mode) - ADD10: packed union { + /// Timer Y output Reset + TYRST: packed union { raw: u1, - value: ADDMODE, + value: CAPTUREEFFECT, }, - /// 10-bit address header only read direction (master receiver mode) - HEAD10R: packed union { + /// Timer Y Compare X + TYCMP: packed union { raw: u1, - value: HEADR, + value: CAPTUREEFFECT, }, - /// Start generation - START: u1, - /// Stop generation (master mode) - STOP: u1, - /// NACK generation (slave mode) - NACK: u1, - /// Number of bytes - NBYTES: u8, - /// NBYTES reload mode - RELOAD: packed union { + reserved24: u1, + /// Timer Z output Set + TZSET: packed union { raw: u1, - value: RELOAD, + value: CAPTUREEFFECT, }, - /// Automatic end mode (master mode) - AUTOEND: packed union { + /// Timer Z output Reset + TZRST: packed union { raw: u1, - value: AUTOEND, + value: CAPTUREEFFECT, }, - /// Packet error checking byte - PECBYTE: u1, - padding: u5, - }), - /// Own address register 1 - OAR1: mmio.Mmio(packed struct(u32) { - /// Interface address + /// Timer Z Compare X + TZCMP: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + reserved28: u1, + /// Timer T output Set + TTSET: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + /// Timer T output Reset + TTRST: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + /// Timer T Compare X + TTCMP: packed union { + raw: u1, + value: CAPTUREEFFECT, + }, + padding: u1, + }), + reserved100: [4]u8, + /// Timer X Output Register + OUTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Output 1 polarity + POL: packed union { + raw: u1, + value: POL, + }, + /// Output X Idle mode + IDLEM: u1, + /// Output X Idle State + IDLES: u1, + /// Output X Fault state + FAULTX: packed union { + raw: u2, + value: FAULT, + }, + /// Output X Chopper enable + CHP: u1, + /// Output X Deadtime upon burst mode Idle entry + DIDL: u1, + /// Deadtime enable + DTEN: u1, + /// Delayed Protection Enable + DLYPRTEN: u1, + /// Delayed Protection + DLYPRT: packed union { + raw: u3, + value: DLYPRT, + }, + padding: u19, + }), + /// Timer X Fault Register + FLT: mmio.Mmio(packed struct(u32) { + /// Fault X enable + FLTEN: packed union { + raw: u1, + value: FLTEN, + }, + reserved31: u30, + /// Fault sources Lock + FLTLCK: u1, + }), + }; + }; + + pub const hsem_v1 = struct { + /// Hardware semaphore (HSEM). + pub const HSEM = extern struct { + /// HSEM register HSEM_R%s HSEM_R31. + R: [32]mmio.Mmio(packed struct(u32) { + /// Semaphore ProcessID. + PROCID: u8, + /// Semaphore COREID. + COREID: u4, + reserved31: u19, + /// Lock indication. + LOCK: u1, + }), + /// HSEM Read lock register. + RLR: [32]mmio.Mmio(packed struct(u32) { + /// Semaphore ProcessID. + PROCID: u8, + /// Semaphore COREID. + COREID: u4, + reserved31: u19, + /// Lock indication. + LOCK: u1, + }), + /// HSEM Interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Interrupt semaphore x enable bit. + ISE: u1, + padding: u31, + }), + /// HSEM Interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Interrupt semaphore x clear bit. + ISC: u1, + padding: u31, + }), + /// HSEM Interrupt status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Interrupt semaphore x status bit before enable (mask). + ISF: u1, + padding: u31, + }), + /// HSEM Masked interrupt status register. + MISR: mmio.Mmio(packed struct(u32) { + /// masked interrupt semaphore x status bit after enable (mask). + MISF: u1, + padding: u31, + }), + reserved320: [48]u8, + /// HSEM Clear register. + CR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// COREID of semaphores to be cleared. + COREID: u4, + reserved16: u4, + /// Semaphore clear Key. + KEY: u16, + }), + /// HSEM Interrupt clear register. + KEYR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Semaphore Clear Key. + KEY: u16, + }), + }; + }; + + pub const hsem_v2 = struct { + /// HSEM. + pub const HSEM = extern struct { + /// HSEM register HSEM_R%s HSEM_R31. + R: [32]mmio.Mmio(packed struct(u32) { + /// Semaphore ProcessID. + PROCID: u8, + /// Semaphore COREID. + COREID: u4, + reserved31: u19, + /// Lock indication. + LOCK: u1, + }), + /// HSEM Read lock register. + RLR: [32]mmio.Mmio(packed struct(u32) { + /// Semaphore ProcessID. + PROCID: u8, + /// Semaphore COREID. + COREID: u4, + reserved31: u19, + /// Lock indication. + LOCK: u1, + }), + /// HSEM Interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Interrupt semaphore x enable bit. + ISE: u1, + padding: u31, + }), + /// HSEM Interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Interrupt semaphore x clear bit. + ISC: u1, + padding: u31, + }), + /// HSEM Interrupt status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Interrupt semaphore x status bit before enable (mask). + ISF: u1, + padding: u31, + }), + /// HSEM Masked interrupt status register. + MISR: mmio.Mmio(packed struct(u32) { + /// masked interrupt semaphore x status bit after enable (mask). + MISF: u1, + padding: u31, + }), + reserved320: [48]u8, + /// HSEM Clear register. + CR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// COREID of semaphores to be cleared. + COREID: u4, + reserved16: u4, + /// Semaphore clear Key. + KEY: u16, + }), + /// HSEM Interrupt clear register. + KEYR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Semaphore Clear Key. + KEY: u16, + }), + }; + }; + + pub const hsem_v3 = struct { + /// Hardware semaphore. + pub const HSEM = extern struct { + /// HSEM register HSEM_R%s HSEM_R31. + R: [16]mmio.Mmio(packed struct(u32) { + /// Semaphore ProcessID. + PROCID: u8, + /// COREID. + COREID: u4, + reserved31: u19, + /// Lock indication. + LOCK: u1, + }), + reserved128: [64]u8, + /// HSEM Read lock register. + RLR: [16]mmio.Mmio(packed struct(u32) { + /// Semaphore ProcessID. + PROCID: u8, + /// COREID. + COREID: u4, + reserved31: u19, + /// Lock indication. + LOCK: u1, + }), + reserved256: [64]u8, + /// HSEM Interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Interrupt semaphore x enable bit. + ISE: u1, + padding: u31, + }), + /// HSEM Interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Interrupt semaphore x clear bit. + ISC: u1, + padding: u31, + }), + /// HSEM Interrupt status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Interrupt semaphore x status bit before enable (mask). + ISF: u1, + padding: u31, + }), + /// HSEM Masked interrupt status register. + MISR: mmio.Mmio(packed struct(u32) { + /// masked interrupt semaphore x status bit after enable (mask). + MISF: u1, + padding: u31, + }), + reserved320: [48]u8, + /// HSEM Clear register. + CR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// COREID. + COREID: u4, + reserved16: u4, + /// Semaphore clear Key. + KEY: u16, + }), + /// HSEM Interrupt clear register. + KEYR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Semaphore Clear Key. + KEY: u16, + }), + }; + }; + + pub const hsem_v4 = struct { + /// Hardware semaphore. + pub const HSEM = extern struct { + /// HSEM register HSEM_R%s HSEM_R31. + R: [16]mmio.Mmio(packed struct(u32) { + /// Semaphore ProcessID. + PROCID: u8, + /// Semaphore COREID. + COREID: u4, + reserved31: u19, + /// Lock indication. + LOCK: u1, + }), + reserved128: [64]u8, + /// HSEM Read lock register. + RLR: [16]mmio.Mmio(packed struct(u32) { + /// Semaphore ProcessID. + PROCID: u8, + /// Semaphore COREID. + COREID: u4, + reserved31: u19, + /// Lock indication. + LOCK: u1, + }), + reserved256: [64]u8, + /// HSEM Interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Interrupt semaphore n enable bit. + ISE: u1, + padding: u31, + }), + /// HSEM Interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Interrupt(N) semaphore n clear bit. + ISC: u1, + padding: u31, + }), + /// HSEM Interrupt status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Interrupt(N) semaphore n status bit before enable (mask). + ISF: u1, + padding: u31, + }), + /// HSEM Masked interrupt status register. + MISR: mmio.Mmio(packed struct(u32) { + /// masked interrupt(N) semaphore n status bit after enable (mask). + MISF: u1, + padding: u31, + }), + reserved320: [48]u8, + /// HSEM Clear register. + CR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// COREID. + COREID: u4, + reserved16: u4, + /// Semaphore clear Key. + KEY: u16, + }), + /// HSEM Interrupt clear register. + KEYR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Semaphore Clear Key. + KEY: u16, + }), + }; + }; + + pub const i2c_v1 = struct { + pub const ADDMODE = enum(u1) { + /// 7-bit addressing mode + Bit7 = 0x0, + /// 10-bit addressing mode + Bit10 = 0x1, + }; + + pub const DNF = enum(u4) { + /// Digital filter disabled + NoFilter = 0x0, + /// Digital filter enabled and filtering capability up to 1 tI2CCLK + Filter1 = 0x1, + /// Digital filter enabled and filtering capability up to 2 tI2CCLK + Filter2 = 0x2, + /// Digital filter enabled and filtering capability up to 3 tI2CCLK + Filter3 = 0x3, + /// Digital filter enabled and filtering capability up to 4 tI2CCLK + Filter4 = 0x4, + /// Digital filter enabled and filtering capability up to 5 tI2CCLK + Filter5 = 0x5, + /// Digital filter enabled and filtering capability up to 6 tI2CCLK + Filter6 = 0x6, + /// Digital filter enabled and filtering capability up to 7 tI2CCLK + Filter7 = 0x7, + /// Digital filter enabled and filtering capability up to 8 tI2CCLK + Filter8 = 0x8, + /// Digital filter enabled and filtering capability up to 9 tI2CCLK + Filter9 = 0x9, + /// Digital filter enabled and filtering capability up to 10 tI2CCLK + Filter10 = 0xa, + /// Digital filter enabled and filtering capability up to 11 tI2CCLK + Filter11 = 0xb, + /// Digital filter enabled and filtering capability up to 12 tI2CCLK + Filter12 = 0xc, + /// Digital filter enabled and filtering capability up to 13 tI2CCLK + Filter13 = 0xd, + /// Digital filter enabled and filtering capability up to 14 tI2CCLK + Filter14 = 0xe, + /// Digital filter enabled and filtering capability up to 15 tI2CCLK + Filter15 = 0xf, + }; + + pub const DUTY = enum(u1) { + /// Duty cycle t_low/t_high = 2/1 + Duty2_1 = 0x0, + /// Duty cycle t_low/t_high = 16/9 + Duty16_9 = 0x1, + }; + + pub const ENDUAL = enum(u1) { + /// Single addressing mode + Single = 0x0, + /// Dual addressing mode + Dual = 0x1, + }; + + pub const F_S = enum(u1) { + /// Standard mode I2C + Standard = 0x0, + /// Fast mode I2C + Fast = 0x1, + }; + + pub const POS = enum(u1) { + /// ACK bit controls the (N)ACK of the current byte being received + Current = 0x0, + /// ACK bit controls the (N)ACK of the next byte to be received + Next = 0x1, + }; + + pub const SMBTYPE = enum(u1) { + /// SMBus Device + Device = 0x0, + /// SMBus Host + Host = 0x1, + }; + + pub const SMBUS = enum(u1) { + /// I2C Mode + I2C = 0x0, + /// SMBus + SMBus = 0x1, + }; + + /// Inter-integrated circuit + pub const I2C = extern struct { + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: packed union { + raw: u1, + value: SMBUS, + }, + reserved3: u1, + /// SMBus type + SMBTYPE: packed union { + raw: u1, + value: SMBTYPE, + }, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data reception) + POS: packed union { + raw: u1, + value: POS, + }, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved15: u1, + /// Software reset + SWRST: u1, + padding: u16, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Peripheral clock frequency + FREQ: u6, + reserved8: u2, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding: u19, + }), + /// Own address register 1 + OAR1: mmio.Mmio(packed struct(u32) { + /// Interface address + ADD: u10, + reserved15: u5, + /// Addressing mode (slave mode) + ADDMODE: packed union { + raw: u1, + value: ADDMODE, + }, + padding: u16, + }), + /// Own address register 2 + OAR2: mmio.Mmio(packed struct(u32) { + /// Dual addressing mode enable + ENDUAL: packed union { + raw: u1, + value: ENDUAL, + }, + /// Interface address + ADD2: u7, + padding: u24, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// 8-bit data register + DR: u8, + padding: u24, + }), + /// Status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Start bit (Master mode) + START: u1, + /// Address sent (master mode)/matched (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master mode) + ADD10: u1, + /// Stop detection (slave mode) + STOPF: u1, + reserved6: u1, + /// Data register not empty (receivers) + RXNE: u1, + /// Data register empty (transmitters) + TXE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved14: u1, + /// Timeout or t_low detection flag + TIMEOUT: u1, + /// SMBus alert + ALERT: u1, + padding: u16, + }), + /// Status register 2 + SR2: mmio.Mmio(packed struct(u32) { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved4: u1, + /// General call address (Slave mode) + GENCALL: u1, + /// SMBus device default address (Slave mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// Packet error checking register + PEC: u8, + padding: u16, + }), + /// Clock control register + CCR: mmio.Mmio(packed struct(u32) { + /// Clock control register in Fast/Standard mode (Master mode) + CCR: u12, + reserved14: u2, + /// Fast mode duty cycle + DUTY: packed union { + raw: u1, + value: DUTY, + }, + /// I2C master mode selection + F_S: packed union { + raw: u1, + value: F_S, + }, + padding: u16, + }), + /// TRISE register + TRISE: mmio.Mmio(packed struct(u32) { + /// Maximum rise time in Fast/Standard mode (Master mode) + TRISE: u6, + padding: u26, + }), + /// FLTR register + FLTR: mmio.Mmio(packed struct(u32) { + /// Digital noise filter + DNF: packed union { + raw: u4, + value: DNF, + }, + /// Analog noise filter + ANOFF: u1, + padding: u27, + }), + }; + }; + + pub const i2c_v2 = struct { + pub const ADDMODE = enum(u1) { + /// 7-bit addressing mode + Bit7 = 0x0, + /// 10-bit addressing mode + Bit10 = 0x1, + }; + + pub const AUTOEND = enum(u1) { + /// Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low + Software = 0x0, + /// Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred + Automatic = 0x1, + }; + + pub const DIR = enum(u1) { + /// Write transfer, slave enters receiver mode + Write = 0x0, + /// Read transfer, slave enters transmitter mode + Read = 0x1, + }; + + pub const DNF = enum(u4) { + /// Digital filter disabled + NoFilter = 0x0, + /// Digital filter enabled and filtering capability up to 1 tI2CCLK + Filter1 = 0x1, + /// Digital filter enabled and filtering capability up to 2 tI2CCLK + Filter2 = 0x2, + /// Digital filter enabled and filtering capability up to 3 tI2CCLK + Filter3 = 0x3, + /// Digital filter enabled and filtering capability up to 4 tI2CCLK + Filter4 = 0x4, + /// Digital filter enabled and filtering capability up to 5 tI2CCLK + Filter5 = 0x5, + /// Digital filter enabled and filtering capability up to 6 tI2CCLK + Filter6 = 0x6, + /// Digital filter enabled and filtering capability up to 7 tI2CCLK + Filter7 = 0x7, + /// Digital filter enabled and filtering capability up to 8 tI2CCLK + Filter8 = 0x8, + /// Digital filter enabled and filtering capability up to 9 tI2CCLK + Filter9 = 0x9, + /// Digital filter enabled and filtering capability up to 10 tI2CCLK + Filter10 = 0xa, + /// Digital filter enabled and filtering capability up to 11 tI2CCLK + Filter11 = 0xb, + /// Digital filter enabled and filtering capability up to 12 tI2CCLK + Filter12 = 0xc, + /// Digital filter enabled and filtering capability up to 13 tI2CCLK + Filter13 = 0xd, + /// Digital filter enabled and filtering capability up to 14 tI2CCLK + Filter14 = 0xe, + /// Digital filter enabled and filtering capability up to 15 tI2CCLK + Filter15 = 0xf, + }; + + pub const HEADR = enum(u1) { + /// The master sends the complete 10 bit slave address read sequence + Complete = 0x0, + /// The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction + Partial = 0x1, + }; + + pub const OAMSK = enum(u3) { + /// No mask + NoMask = 0x0, + /// OA2[1] is masked and don’t care. Only OA2[7:2] are compared + Mask1 = 0x1, + /// OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared + Mask2 = 0x2, + /// OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared + Mask3 = 0x3, + /// OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared + Mask4 = 0x4, + /// OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared + Mask5 = 0x5, + /// OA2[6:1] are masked and don’t care. Only OA2[7] is compared. + Mask6 = 0x6, + /// OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged + Mask7 = 0x7, + }; + + pub const RELOAD = enum(u1) { + /// The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) + Completed = 0x0, + /// The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) + NotCompleted = 0x1, + }; + + /// Inter-integrated circuit + pub const I2C = extern struct { + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Peripheral enable + PE: u1, + /// TX Interrupt enable + TXIE: u1, + /// RX Interrupt enable + RXIE: u1, + /// Address match interrupt enable (slave only) + ADDRIE: u1, + /// Not acknowledge received interrupt enable + NACKIE: u1, + /// STOP detection Interrupt enable + STOPIE: u1, + /// Transfer Complete interrupt enable + TCIE: u1, + /// Error interrupts enable + ERRIE: u1, + /// Digital noise filter + DNF: packed union { + raw: u4, + value: DNF, + }, + /// Analog noise filter OFF + ANFOFF: u1, + reserved14: u1, + /// DMA transmission requests enable + TXDMAEN: u1, + /// DMA reception requests enable + RXDMAEN: u1, + /// Slave byte control + SBC: u1, + /// Clock stretching disable + NOSTRETCH: u1, + reserved19: u1, + /// General call enable + GCEN: u1, + /// SMBus Host address enable + SMBHEN: u1, + /// SMBus Device Default address enable + SMBDEN: u1, + /// SMBUS alert enable + ALERTEN: u1, + /// PEC enable + PECEN: u1, + padding: u8, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Slave address bit (master mode) + SADD: u10, + /// Transfer direction (master mode) + DIR: packed union { + raw: u1, + value: DIR, + }, + /// 10-bit addressing mode (master mode) + ADD10: packed union { + raw: u1, + value: ADDMODE, + }, + /// 10-bit address header only read direction (master receiver mode) + HEAD10R: packed union { + raw: u1, + value: HEADR, + }, + /// Start generation + START: u1, + /// Stop generation (master mode) + STOP: u1, + /// NACK generation (slave mode) + NACK: u1, + /// Number of bytes + NBYTES: u8, + /// NBYTES reload mode + RELOAD: packed union { + raw: u1, + value: RELOAD, + }, + /// Automatic end mode (master mode) + AUTOEND: packed union { + raw: u1, + value: AUTOEND, + }, + /// Packet error checking byte + PECBYTE: u1, + padding: u5, + }), + /// Own address register 1 + OAR1: mmio.Mmio(packed struct(u32) { + /// Interface address OA1: u10, /// Own Address 1 10-bit mode OA1MODE: packed union { @@ -347878,35537 +347785,19920 @@ pub const types = struct { }; }; - pub const wwdg_v2 = struct { - pub const WDGTB = enum(u3) { - /// Counter clock (PCLK1 div 4096) div 1 - Div1 = 0x0, - /// Counter clock (PCLK1 div 4096) div 2 - Div2 = 0x1, - /// Counter clock (PCLK1 div 4096) div 4 - Div4 = 0x2, - /// Counter clock (PCLK1 div 4096) div 8 - Div8 = 0x3, - /// Counter clock (PCLK1 div 4096) div 16 - Div16 = 0x4, - /// Counter clock (PCLK1 div 4096) div 32 - Div32 = 0x5, - /// Counter clock (PCLK1 div 4096) div 64 - Div64 = 0x6, - /// Counter clock (PCLK1 div 4096) div 128 - Div128 = 0x7, - }; - - /// Window watchdog - pub const WWDG = extern struct { - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// 7-bit counter (MSB to LSB) - T: u7, - /// Activation bit (true is enabled, false is disabled) - WDGA: u1, - padding: u24, - }), - /// Configuration register - CFR: mmio.Mmio(packed struct(u32) { - /// 7-bit window value - W: u7, - reserved9: u2, - /// Early wakeup interrupt - EWI: u1, - reserved11: u1, - /// Timer base - WDGTB: packed union { - raw: u3, - value: WDGTB, - }, - padding: u18, - }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Early wakeup interrupt flag - EWIF: u1, - padding: u31, - }), - }; - }; - - pub const rcc_f100 = struct { - pub const ADCPRE = enum(u2) { - /// PCLK2 divided by 2 - Div2 = 0x0, - /// PCLK2 divided by 4 - Div4 = 0x1, - /// PCLK2 divided by 6 - Div6 = 0x2, - /// PCLK2 divided by 8 - Div8 = 0x3, + pub const i2c_v3 = struct { + pub const ADDMODE = enum(u1) { + /// 7-bit addressing mode + Bit7 = 0x0, + /// 10-bit addressing mode + Bit10 = 0x1, }; - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, - _, + pub const AUTOEND = enum(u1) { + /// Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low + Software = 0x0, + /// Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred + Automatic = 0x1, }; - pub const MCOSEL = enum(u3) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// System clock selected - SYS = 0x4, - /// HSI oscillator clock selected - HSI = 0x5, - /// HSE oscillator clock selected - HSE = 0x6, - /// PLL clock divided by 2 selected - PLL = 0x7, - _, + pub const DIR = enum(u1) { + /// Write transfer, slave enters receiver mode + Write = 0x0, + /// Read transfer, slave enters transmitter mode + Read = 0x1, }; - pub const PLLMUL = enum(u4) { - /// PLL input clock x2 - Mul2 = 0x0, - /// PLL input clock x3 - Mul3 = 0x1, - /// PLL input clock x4 - Mul4 = 0x2, - /// PLL input clock x5 - Mul5 = 0x3, - /// PLL input clock x6 - Mul6 = 0x4, - /// PLL input clock x7 - Mul7 = 0x5, - /// PLL input clock x8 - Mul8 = 0x6, - /// PLL input clock x9 - Mul9 = 0x7, - /// PLL input clock x10 - Mul10 = 0x8, - /// PLL input clock x11 - Mul11 = 0x9, - /// PLL input clock x12 - Mul12 = 0xa, - /// PLL input clock x13 - Mul13 = 0xb, - /// PLL input clock x14 - Mul14 = 0xc, - /// PLL input clock x15 - Mul15 = 0xd, - /// PLL input clock x16 - Mul16 = 0xe, - _, + pub const DNF = enum(u4) { + /// Digital filter disabled + NoFilter = 0x0, + /// Digital filter enabled and filtering capability up to 1 tI2CCLK + Filter1 = 0x1, + /// Digital filter enabled and filtering capability up to 2 tI2CCLK + Filter2 = 0x2, + /// Digital filter enabled and filtering capability up to 3 tI2CCLK + Filter3 = 0x3, + /// Digital filter enabled and filtering capability up to 4 tI2CCLK + Filter4 = 0x4, + /// Digital filter enabled and filtering capability up to 5 tI2CCLK + Filter5 = 0x5, + /// Digital filter enabled and filtering capability up to 6 tI2CCLK + Filter6 = 0x6, + /// Digital filter enabled and filtering capability up to 7 tI2CCLK + Filter7 = 0x7, + /// Digital filter enabled and filtering capability up to 8 tI2CCLK + Filter8 = 0x8, + /// Digital filter enabled and filtering capability up to 9 tI2CCLK + Filter9 = 0x9, + /// Digital filter enabled and filtering capability up to 10 tI2CCLK + Filter10 = 0xa, + /// Digital filter enabled and filtering capability up to 11 tI2CCLK + Filter11 = 0xb, + /// Digital filter enabled and filtering capability up to 12 tI2CCLK + Filter12 = 0xc, + /// Digital filter enabled and filtering capability up to 13 tI2CCLK + Filter13 = 0xd, + /// Digital filter enabled and filtering capability up to 14 tI2CCLK + Filter14 = 0xe, + /// Digital filter enabled and filtering capability up to 15 tI2CCLK + Filter15 = 0xf, }; - pub const PLLSRC = enum(u1) { - /// HSI divided by 2 selected as PLL input clock - HSI_Div2 = 0x0, - /// HSE divided by PREDIV selected as PLL input clock - HSE_Div_PREDIV = 0x1, + pub const HEADR = enum(u1) { + /// The master sends the complete 10 bit slave address read sequence + Complete = 0x0, + /// The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction + Partial = 0x1, }; - pub const PLLXTPRE = enum(u1) { - /// HSE clock not divided - Div1 = 0x0, - /// HSE clock divided by 2 - Div2 = 0x1, + pub const OAMSK = enum(u3) { + /// No mask + NoMask = 0x0, + /// OA2[1] is masked and don’t care. Only OA2[7:2] are compared + Mask1 = 0x1, + /// OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared + Mask2 = 0x2, + /// OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared + Mask3 = 0x3, + /// OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared + Mask4 = 0x4, + /// OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared + Mask5 = 0x5, + /// OA2[6:1] are masked and don’t care. Only OA2[7] is compared. + Mask6 = 0x6, + /// OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged + Mask7 = 0x7, }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, + pub const RELOAD = enum(u1) { + /// The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) + Completed = 0x0, + /// The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) + NotCompleted = 0x1, }; - pub const PREDIV1 = enum(u4) { - /// PREDIV input clock not divided - Div1 = 0x0, - /// PREDIV input clock divided by 2 - Div2 = 0x1, - /// PREDIV input clock divided by 3 - Div3 = 0x2, - /// PREDIV input clock divided by 4 - Div4 = 0x3, - /// PREDIV input clock divided by 5 - Div5 = 0x4, - /// PREDIV input clock divided by 6 - Div6 = 0x5, - /// PREDIV input clock divided by 7 - Div7 = 0x6, - /// PREDIV input clock divided by 8 - Div8 = 0x7, - /// PREDIV input clock divided by 9 - Div9 = 0x8, - /// PREDIV input clock divided by 10 - Div10 = 0x9, - /// PREDIV input clock divided by 11 - Div11 = 0xa, - /// PREDIV input clock divided by 12 - Div12 = 0xb, - /// PREDIV input clock divided by 13 - Div13 = 0xc, - /// PREDIV input clock divided by 14 - Div14 = 0xd, - /// PREDIV input clock divided by 15 - Div15 = 0xe, - /// PREDIV input clock divided by 16 - Div16 = 0xf, - }; - - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, - }; - - pub const SW = enum(u2) { - /// HSI selected as system clock - HSI = 0x0, - /// HSE selected as system clock - HSE = 0x1, - /// PLL selected as system clock - PLL1_P = 0x2, - _, - }; - - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal High Speed clock enable - HSION: u1, - /// Internal High Speed clock ready flag - HSIRDY: u1, - reserved3: u1, - /// Internal High Speed clock trimming - HSITRIM: u5, - /// Internal High Speed clock Calibration - HSICAL: u8, - /// External High Speed clock enable - HSEON: u1, - /// External High Speed clock ready flag - HSERDY: u1, - /// External High Speed clock Bypass - HSEBYP: u1, - /// Clock Security System enable - CSSON: u1, - reserved24: u4, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding: u6, - }), - /// Clock configuration register (RCC_CFGR) - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock Switch - SW: packed union { - raw: u2, - value: SW, - }, - /// System Clock Switch Status - SWS: packed union { - raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { + /// Inter-integrated circuit + pub const I2C = extern struct { + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Peripheral enable + PE: u1, + /// TX Interrupt enable + TXIE: u1, + /// RX Interrupt enable + RXIE: u1, + /// Address match interrupt enable (slave only) + ADDRIE: u1, + /// Not acknowledge received interrupt enable + NACKIE: u1, + /// STOP detection Interrupt enable + STOPIE: u1, + /// Transfer Complete interrupt enable + TCIE: u1, + /// Error interrupts enable + ERRIE: u1, + /// Digital noise filter + DNF: packed union { raw: u4, - value: HPRE, - }, - /// APB Low speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, - }, - /// APB High speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, + value: DNF, }, - /// ADC prescaler - ADCPRE: packed union { - raw: u2, - value: ADCPRE, + /// Analog noise filter OFF + ANFOFF: u1, + reserved14: u1, + /// DMA transmission requests enable + TXDMAEN: u1, + /// DMA reception requests enable + RXDMAEN: u1, + /// Slave byte control + SBC: u1, + /// Clock stretching disable + NOSTRETCH: u1, + reserved19: u1, + /// General call enable + GCEN: u1, + /// SMBus Host address enable + SMBHEN: u1, + /// SMBus Device Default address enable + SMBDEN: u1, + /// SMBUS alert enable + ALERTEN: u1, + /// PEC enable + PECEN: u1, + /// Fast-mode Plus 20 mA drive enable. + FMP: u1, + reserved30: u5, + /// Address match flag (ADDR) automatic clear. + ADDRACLR: u1, + /// STOP detection flag (STOPF) automatic clear. + STOPFACLR: u1, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Slave address bit (master mode) + SADD: u10, + /// Transfer direction (master mode) + DIR: packed union { + raw: u1, + value: DIR, }, - /// PLL entry clock source - PLLSRC: packed union { + /// 10-bit addressing mode (master mode) + ADD10: packed union { raw: u1, - value: PLLSRC, + value: ADDMODE, }, - /// HSE divider for PLL entry - PLLXTPRE: packed union { + /// 10-bit address header only read direction (master receiver mode) + HEAD10R: packed union { raw: u1, - value: PLLXTPRE, + value: HEADR, }, - /// PLL Multiplication Factor - PLLMUL: packed union { - raw: u4, - value: PLLMUL, + /// Start generation + START: u1, + /// Stop generation (master mode) + STOP: u1, + /// NACK generation (slave mode) + NACK: u1, + /// Number of bytes + NBYTES: u8, + /// NBYTES reload mode + RELOAD: packed union { + raw: u1, + value: RELOAD, }, - reserved24: u2, - /// Microcontroller clock output - MCOSEL: packed union { - raw: u3, - value: MCOSEL, + /// Automatic end mode (master mode) + AUTOEND: packed union { + raw: u1, + value: AUTOEND, }, + /// Packet error checking byte + PECBYTE: u1, padding: u5, }), - /// Clock interrupt register (RCC_CIR) - CIR: mmio.Mmio(packed struct(u32) { - /// LSI Ready Interrupt flag - LSIRDYF: u1, - /// LSE Ready Interrupt flag - LSERDYF: u1, - /// HSI Ready Interrupt flag - HSIRDYF: u1, - /// HSE Ready Interrupt flag - HSERDYF: u1, - /// PLL Ready Interrupt flag - PLLRDYF: u1, - reserved7: u2, - /// Clock Security System Interrupt flag - CSSF: u1, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1, - /// LSE Ready Interrupt Enable - LSERDYIE: u1, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1, - /// HSE Ready Interrupt Enable - HSERDYIE: u1, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1, - reserved16: u3, - /// LSI Ready Interrupt Clear - LSIRDYC: u1, - /// LSE Ready Interrupt Clear - LSERDYC: u1, - /// HSI Ready Interrupt Clear - HSIRDYC: u1, - /// HSE Ready Interrupt Clear - HSERDYC: u1, - /// PLL Ready Interrupt Clear - PLLRDYC: u1, - reserved23: u2, - /// Clock security system interrupt clear - CSSC: u1, - padding: u8, + /// Own address register 1 + OAR1: mmio.Mmio(packed struct(u32) { + /// Interface address + OA1: u10, + /// Own Address 1 10-bit mode + OA1MODE: packed union { + raw: u1, + value: ADDMODE, + }, + reserved15: u4, + /// Own Address 1 enable + OA1EN: u1, + padding: u16, }), - /// APB2 peripheral reset register (RCC_APB2RSTR) - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// Alternate function I/O reset - AFIORST: u1, - reserved2: u1, - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - /// IO port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// ADC 1 interface reset - ADC1RST: u1, - reserved11: u1, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI 1 reset - SPI1RST: u1, - reserved14: u1, - /// USART1 reset - USART1RST: u1, - reserved16: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - padding: u13, + /// Own address register 2 + OAR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Interface address + OA2: u7, + /// Own Address 2 masks + OA2MSK: packed union { + raw: u3, + value: OAMSK, + }, + reserved15: u4, + /// Own Address 2 enable + OA2EN: u1, + padding: u16, }), - /// APB1 peripheral reset register (RCC_APB1RSTR) - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - /// Timer 4 reset - TIM4RST: u1, - /// Timer 5 reset - TIM5RST: u1, - /// Timer 6 reset - TIM6RST: u1, - /// Timer 7 reset - TIM7RST: u1, - /// Timer 12 reset - TIM12RST: u1, - /// Timer 13 reset - TIM13RST: u1, - /// Timer 14 reset - TIM14RST: u1, - reserved11: u2, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI2 reset - SPI2RST: u1, - /// SPI3 reset - SPI3RST: u1, - reserved17: u1, - /// USART 2 reset - USART2RST: u1, - /// USART 3 reset - USART3RST: u1, - /// USART 4 reset - UART4RST: u1, - /// USART 5 reset - UART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - reserved27: u4, - /// Backup interface reset - BKPRST: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - /// CEC reset - CECRST: u1, - padding: u1, + /// Timing register + TIMINGR: mmio.Mmio(packed struct(u32) { + /// SCL low period (master mode) + SCLL: u8, + /// SCL high period (master mode) + SCLH: u8, + /// Data hold time + SDADEL: u4, + /// Data setup time + SCLDEL: u4, + reserved28: u4, + /// Timing prescaler + PRESC: u4, }), - /// AHB Peripheral Clock enable register (RCC_AHBENR) - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// SRAM interface clock enable - SRAMEN: u1, - reserved4: u1, - /// FLASH clock enable - FLASHEN: u1, - reserved6: u1, - /// CRC clock enable - CRCEN: u1, - reserved8: u1, - /// FSMC clock enable - FSMCEN: u1, - padding: u23, + /// Timeout register + TIMEOUTR: mmio.Mmio(packed struct(u32) { + /// Bus timeout A + TIMEOUTA: u12, + /// Idle clock timeout detection + TIDLE: u1, + reserved15: u2, + /// Clock timeout enable + TIMOUTEN: u1, + /// Bus timeout B + TIMEOUTB: u12, + reserved31: u3, + /// Extended clock timeout enable + TEXTEN: u1, }), - /// APB2 peripheral clock enable register (RCC_APB2ENR) - APB2ENR: mmio.Mmio(packed struct(u32) { - /// Alternate function I/O clock enable - AFIOEN: u1, - reserved2: u1, - /// I/O port A clock enable - GPIOAEN: u1, - /// I/O port B clock enable - GPIOBEN: u1, - /// I/O port C clock enable - GPIOCEN: u1, - /// I/O port D clock enable - GPIODEN: u1, - /// I/O port E clock enable - GPIOEEN: u1, - /// I/O port F clock enable - GPIOFEN: u1, - /// I/O port G clock enable - GPIOGEN: u1, - /// ADC 1 interface clock enable - ADC1EN: u1, - reserved11: u1, - /// TIM1 Timer clock enable - TIM1EN: u1, - /// SPI 1 clock enable - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable - USART1EN: u1, - reserved16: u1, - /// TIM15 Timer clock enable - TIM15EN: u1, - /// TIM16 Timer clock enable - TIM16EN: u1, - /// TIM17 Timer clock enable - TIM17EN: u1, - padding: u13, + /// Interrupt and Status register + ISR: mmio.Mmio(packed struct(u32) { + /// Transmit data register empty (transmitters) + TXE: u1, + /// Transmit interrupt status (transmitters) + TXIS: u1, + /// Receive data register not empty (receivers) + RXNE: u1, + /// Address matched (slave mode) + ADDR: u1, + /// Not acknowledge received flag + NACKF: u1, + /// Stop detection flag + STOPF: u1, + /// Transfer Complete (master mode) + TC: u1, + /// Transfer Complete Reload + TCR: u1, + /// Bus error + BERR: u1, + /// Arbitration lost + ARLO: u1, + /// Overrun/Underrun (slave mode) + OVR: u1, + /// PEC Error in reception + PECERR: u1, + /// Timeout or t_low detection flag + TIMEOUT: u1, + /// SMBus alert + ALERT: u1, + reserved15: u1, + /// Bus busy + BUSY: u1, + /// Transfer direction (Slave mode) + DIR: packed union { + raw: u1, + value: DIR, + }, + /// Address match code (Slave mode) + ADDCODE: u7, + padding: u8, }), - /// APB1 peripheral clock enable register (RCC_APB1ENR) - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer 2 clock enable - TIM2EN: u1, - /// Timer 3 clock enable - TIM3EN: u1, - /// Timer 4 clock enable - TIM4EN: u1, - /// Timer 5 clock enable - TIM5EN: u1, - /// Timer 6 clock enable - TIM6EN: u1, - /// Timer 7 clock enable - TIM7EN: u1, - /// Timer 12 clock enable - TIM12EN: u1, - /// Timer 13 clock enable - TIM13EN: u1, - /// Timer 14 clock enable - TIM14EN: u1, - reserved11: u2, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI 2 clock enable - SPI2EN: u1, - /// SPI 3 clock enable - SPI3EN: u1, - reserved17: u1, - /// USART 2 clock enable - USART2EN: u1, - /// USART 3 clock enable - USART3EN: u1, - /// UART 4 clock enable - UART4EN: u1, - /// UART 5 clock enable - UART5EN: u1, - /// I2C 1 clock enable - I2C1EN: u1, - /// I2C 2 clock enable - I2C2EN: u1, - reserved27: u4, - /// Backup interface clock enable - BKPEN: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - /// CEC clock enable - CECEN: u1, - padding: u1, + /// Interrupt clear register + ICR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Address Matched flag clear + ADDRCF: u1, + /// Not Acknowledge flag clear + NACKCF: u1, + /// Stop detection flag clear + STOPCF: u1, + reserved8: u2, + /// Bus error flag clear + BERRCF: u1, + /// Arbitration lost flag clear + ARLOCF: u1, + /// Overrun/Underrun flag clear + OVRCF: u1, + /// PEC Error flag clear + PECCF: u1, + /// Timeout detection flag clear + TIMOUTCF: u1, + /// Alert flag clear + ALERTCF: u1, + padding: u18, }), - /// Backup domain control register (RCC_BDCR) - BDCR: mmio.Mmio(packed struct(u32) { - /// External Low Speed oscillator enable - LSEON: u1, - /// External Low Speed oscillator ready - LSERDY: u1, - /// External Low Speed oscillator bypass - LSEBYP: u1, - reserved8: u5, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - padding: u15, + /// PEC register + PECR: mmio.Mmio(packed struct(u32) { + /// Packet error checking register + PEC: u8, + padding: u24, }), - /// Control/status register (RCC_CSR) - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low speed oscillator enable - LSION: u1, - /// Internal low speed oscillator ready - LSIRDY: u1, - reserved24: u22, - /// Remove reset flag - RMVF: u1, - reserved26: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// Receive data register + RXDR: mmio.Mmio(packed struct(u32) { + /// 8-bit receive data + RXDATA: u8, + padding: u24, }), - reserved44: [4]u8, - /// Clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// PREDIV1 division factor - PREDIV1: packed union { - raw: u4, - value: PREDIV1, - }, - padding: u28, + /// Transmit data register + TXDR: mmio.Mmio(packed struct(u32) { + /// 8-bit transmit data + TXDATA: u8, + padding: u24, }), }; }; - pub const syscfg_f0 = struct { - pub const FMP = enum(u1) { - /// Standard - Standard = 0x0, - /// FM+ - FMP = 0x1, + pub const i3c_v1 = struct { + pub const ACK = enum(u1) { + Must_NACKed = 0x0, + Must_ACKed = 0x1, }; - pub const IR_MOD = enum(u2) { - /// TIM16 selected - TIM16 = 0x0, - /// USART1 selected - USART1 = 0x1, - /// USART4 selected - USART4 = 0x2, + pub const CODERR = enum(u4) { + /// Transaction after sending CCC. Controller detected an illegally formatted CCC + CE0 = 0x0, + /// Monitoring error. Controller detected that transmitted data on the bus is different from expected + CE1 = 0x1, + /// No response to broadcast address. Controller detected a not acknowledged broadcast address (0b111_1110) + CE2 = 0x2, + /// Failed controller-role hand-off. Controller detected the new controller did not drive bus after controller-role hand-off + CE3 = 0x3, + /// Invalid broadcast address 0b111_1110 + W. Target detected an invalid broadcast address 0b111_1110 + W + TE0 = 0x8, + /// CCC code. Target detected a parity error on a CCC code via a parity check (vs. T bit) + TE1 = 0x9, + /// Write data. Target detected a parity error on a write data via a parity check (vs. T bit) + TE2 = 0xa, + /// Assigned address during dynamic address arbitration. Target detected a parity error on the assigned address during dynamic address arbitration via a parity check (vs. PAR bit) + TE3 = 0xb, + /// 0b111_1110 + R missing after Sr during dynamic address arbitration. Target detected a 0b111_1110 + R missing after Sr during dynamic address arbitration + TE4 = 0xc, + /// Transaction after detecting CCC. Target detected an illegally formatted CCC + TE5 = 0xd, + /// Monitoring error. Target detected that transmitted data on the bus is different from expected + TE6 = 0xe, _, }; - pub const MEM_MODE = enum(u2) { - /// Main Flash memory mapped at 0x0000_0000 - MainFlash = 0x0, - /// System Flash memory mapped at 0x0000_0000 - SystemFlash = 0x1, - /// Main Flash memory mapped at 0x0000_0000 - MainFlash2 = 0x2, - /// Embedded SRAM mapped at 0x0000_0000 - SRAM = 0x3, + pub const CRINIT = enum(u1) { + /// Once enabled by setting EN = 1, the peripheral initially acts as a target. I3C does not drive SCL line and does not enable SDA pull-up, until it eventually acquires the controller role. + Target = 0x0, + /// Once enabled by setting EN = 1, the peripheral initially acts as a controller. It has the I3C controller role, so drives SCL line and enables SDA pull-up, until it eventually offers the controller role to an I3C secondary controller. + Controller = 0x1, }; - /// System configuration controller - pub const SYSCFG = extern struct { - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection bits - MEM_MODE: packed union { - raw: u2, - value: MEM_MODE, - }, - reserved4: u2, - /// PA11 and PA12 remapping bit for small packages (28 and 20 pins) 0: Pin pair PA9/PA10 mapped on the pins 1: Pin pair PA11/PA12 mapped instead of PA9/PA10 - PA11_PA12_RMP: u1, - reserved6: u1, - /// IR Modulation Envelope signal selection - IR_MOD: packed union { - raw: u2, - value: IR_MOD, - }, - /// ADC DMA remapping bit 0: ADC DMA request mapped on DMA channel 1 1: ADC DMA request mapped on DMA channel 2 - ADC_DMA_RMP: u1, - /// USART1_TX DMA remapping bit 0: USART1_TX DMA request mapped on DMA channel 2 1: USART1_TX DMA request mapped on DMA channel 4 - USART1_TX_DMA_RMP: u1, - /// USART1_RX DMA request remapping bit 0: USART1_RX DMA request mapped on DMA channel 3 1: USART1_RX DMA request mapped on DMA channel 5 - USART1_RX_DMA_RMP: u1, - /// TIM16 DMA request remapping bit 0: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3 1: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4 - TIM16_DMA_RMP: u1, - /// TIM17 DMA request remapping bit 0: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1 1: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2 - TIM17_DMA_RMP: u1, - /// TIM16 alternate DMA request remapping bit 0: TIM16 DMA request mapped according to TIM16_DMA_RMP bit 1: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6 - TIM16_DMA_RMP2: u1, - /// TIM17 alternate DMA request remapping bit 0: TIM17 DMA request mapped according to TIM16_DMA_RMP bit 1: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7 - TIM17_DMA_RMP2: u1, - reserved16: u1, - /// Fast Mode Plus (FM plus) driving capability activation bits. 0: PB6 pin operate in standard mode 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed - I2C_PB6_FMP: packed union { - raw: u1, - value: FMP, - }, - /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB7 pin operate in standard mode 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed - I2C_PB7_FMP: packed union { - raw: u1, - value: FMP, - }, - /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB8 pin operate in standard mode 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed - I2C_PB8_FMP: packed union { - raw: u1, - value: FMP, - }, - /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB9 pin operate in standard mode 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed - I2C_PB9_FMP: packed union { + pub const DIR = enum(u1) { + Write = 0x0, + Read = 0x1, + }; + + pub const DIS = enum(u1) { + /// write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed + Allowed = 0x0, + /// write to DA[7:0] and to IBIDEN is disabled/locked + Locked = 0x1, + }; + + pub const MEND = enum(u1) { + /// this message from controller is followed by a repeated start (Sr), before another message must be emitted + RepeatedStart = 0x0, + /// this message from controller ends with a stop (P), being the last message of a frame + Stop = 0x1, + }; + + pub const RNW = enum(u1) { + /// write message + Write = 0x0, + /// read message + Read = 0x1, + }; + + pub const RSTACT = enum(u2) { + NoReset = 0x0, + /// first level of reset: the application software must either: a) partially reset the peripheral, by a write and clear of the enable bit of the I3C configuration register (write EN = 0). This resets the I3C bus interface and the I3C kernel sub-parts, without modifying the content of the I3C APB registers (except the EN bit). b) fully reset the peripheral, including all its registers, via a write and set of the I3C reset control bit of the RCC (reset and clock controller) register. + FirstLevel = 0x1, + /// second level of reset: the application software must issue a warm reset, also known as a system reset. This (see Section 11: Reset and clock control (RCC)) has the same impact as a pin reset (NRST = 0): – the software writes and sets the SYSRESETREQ control bit of the AITR register, when the device is controlled by a Cortex®-M. – the software writes and sets SYSRST = 1 in the RCC_GRSTCSETR register, when the device is controlled by a Cortex®-A. + SecondLevel = 0x2, + NoResetEither = 0x3, + }; + + pub const THRES = enum(u1) { + /// TXFNFF is set when 1 byte must be written in TX-FIFO (in I3C_TDR). + Byte = 0x0, + /// TXFNFF is set when 1 word / 4 bytes must be written in TX-FIFO (in the I3C_TDWR register). If the a number of the last transmitted data is not a multiple of 4 bytes (XDCNT[1:0] = 00 in the I3C_SR register), only the relevant 1, 2, or 3 valid LSB bytes of the last word are taken into account by the hardware, and sent on the I3C bus. + Word = 0x1, + }; + + pub const DataRegs = extern struct { + /// I3C receive data byte register. + DR: mmio.Mmio(packed struct(u32) { + /// 8-bit received data on I3C bus. + DB: u8, + padding: u24, + }), + /// I3C receive data word register. + DWR: mmio.Mmio(packed struct(u32) { + /// 8-bit received data (earliest byte on I3C bus). + DB: u8, + padding: u24, + }), + }; + + /// Improved inter-integrated circuit. + pub const I3C = extern struct { + /// I3C message control register. + CR: mmio.Mmio(packed struct(u32) { + /// count of data to transfer during a read or write message, in bytes (whatever I3C is acting as controller/target) Linear encoding up to 64 Kbytes -1 ... + DCNT: u16, + /// read / non-write message (when I3C is acting as controller) When I3C is acting as controller, this field is used if MTYPE[3:0]=0010 (private message) or MTYPE[3:0]=0011 (direct message) or MTYPE[3:0]=0100 (legacy I2C message), in order to emit the RnW bit on the I3C bus. + RNW: packed union { raw: u1, - value: FMP, + value: RNW, }, - /// FM+ driving capability activation for I2C1 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers - I2C1_FMP: packed union { + /// 7-bit I3C dynamic / I2C static target address (when I3C is acting as controller) When I3C is acting as controller, this field is used if MTYPE[3:0]=0010 (private message) or MTYPE[3:0]=0011 (direct message) or MTYPE[3:0]=0100 (legacy I2C message). + ADD: u7, + reserved27: u3, + /// message type (whatever I3C is acting as controller/target) Bits[26:0] are ignored. After M2 error detection on an I3C SDR message, this is needed for SCL “stuck at” recovery. Bits[26:0] are ignored. If I3C_CFGR.EXITPTRN=1, an HDR exit pattern is emitted on the bus to generate an escalation fault. Bits[23:17] (ADD[6:0]) is the emitted 7-bit dynamic address. Bit[16] (RNW) is the emitted RnW bit. The transferred private message is: {S / S+7’h7E+RnW=0+Sr / Sr+*} + 7-bit DynAddr + RnW + (8-bit Data + T)* + Sr/P. After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7’h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7’h7E+RnW=0) if needed, i.e. if it follows an I3C direct message without ending by a P (Stop). Bits[23:17] (ADD[6:0]) is the emitted 7-bit dynamic address. Bit[16] (RNW) is the emitted RnW bit. The transferred direct message is: Sr + 7-bit DynAddr + RnW + (8-bit Data + T)* + Sr/P Bits[23:17] (ADD[6:0]) is the emitted 7-bit static address. Bit[16] (RNW) is the emitted RnW bit. The transferred legacy I2C message is: {S / S+ 7’h7E+RnW=0 + Sr / Sr+*} + 7-bit StaAddr + RnW + (8-bit Data + T)* + Sr/P. After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7’h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7’h7E+RnW=0) if needed, i.e. if it follows an I3C direct message without ending by a P (Stop). 1xxx: reserved (when I3C is acting as I3C controller, used when target) 0xxx: reserved {S +} 7’h02 addr + RnW=0 {S +} 7-bit I3C_DEVR0.DA[6:0] + RnW=0 after a bus available condition (the target first emits a START request), or once the controller drives a START. {S +} 7-bit I3C_DEVR0.DA[6:0] + RnW=1 (+Ack/Nack from controller) When acknowledged from controller, the next (optional, depending on I3C_BCR.BCR2) transmitted IBI payload data is defined by I3C_CR.DCNT[15:0] and must be consistently programmed vs the maximum IBI payload data size which is defined by I3C_IBIDR.IBIP[2:0]. Others: reserved. + MTYPE: u4, + /// message end type (when the I3C is acting as controller). + MEND: packed union { raw: u1, - value: FMP, + value: MEND, }, - /// FM+ driving capability activation for I2C2 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers - I2C2_FMP: packed union { + }), + /// I3C configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// I3C enable (whatever I3C is acting as controller/target) - Except registers, the peripheral is under reset (a.k.a. partial reset). - Before clearing EN, when I3C is acting as a controller, all the possible target requests must be disabled using DISEC CCC. - When I3C is acting as a target, software should not disable the I3C, unless a partial reset is needed. In this state, some register fields can not be modified (like CRINIT, HKSDAEN for the I3C_CFGR). + EN: u1, + /// initial controller/target role This bit can be modified only when I3C_CFGR.EN = 0. Once enabled by setting I3C_CFGR.EN = 1, I3C peripheral initially acts as an I3C target. I3C does not drive SCL line and does not enable SDA pull-up, until it eventually acquires the controller role. Once enabled by setting I3C_CFGR.EN = 1, I3C peripheral initially acts as a controller. It has the I3C controller role, so drives SCL line and enables SDA pull-up, until it eventually offers the controller role to an I3C secondary controller. + CRINIT: packed union { raw: u1, - value: FMP, + value: CRINIT, }, - /// Fast Mode Plus (FM+) driving capability activation bits 0: PA9 pin operate in standard mode 1: I2C FM+ mode enabled on PA9 and the Speed control is bypassed - I2C_PA9_FMP: packed union { + /// no arbitrable header after a START (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame. - The target address is emitted directly after a START in case of a legacy I2C message or an I3C SDR private read/write message. - This is a more performing option (when is useless the emission of the 0x7E arbitrable header), but this is to be used only when the controller is sure that the addressed target device can not emit concurrently an IBI or a controller-role request (to insure no misinterpretation and no potential conflict between the address emitted by the controller in open-drain mode and the same address a target device can emit after a START, for IBI or MR). + NOARBH: u1, + /// HDR reset pattern enable (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame. + RSTPTRN: u1, + /// HDR Exit Pattern enable (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame. This is used to send only the header to test ownership of the bus when there is a suspicion of problem after controller-role hand-off (new controller didn’t assert its controller-role by accessing the previous one in less than Activity State time). The HDR Exit Pattern is sent even if the message header {S/Sr + 0x7E addr + W } is ACKed. + EXITPTRN: u1, + /// High-keeper enable on SDA line (when I3C is acting as a controller) This bit can be modified only when I3C_CFGR.EN=0. + HKSDAEN: u1, + reserved7: u1, + /// Hot Join request acknowledge (when I3C is acting as a controller) After the NACK, the message continues as initially programmed (the hot-joining target is aware of the NACK and surely emits another hot-join request later on). After the ACK, the message continues as initially programmed. The software is aware by the HJ interrupt (flag I3C_EVR.HJF is set) and initiates the ENTDAA sequence later on, potentially preventing others Hot Join requests with a Disable target events command (DISEC, with DISHJ=1). Independently of the HJACK configuration, further Hot Join request(s) are NACKed until the Hot Join flag, HJF, is cleared. However, a NACKed target can be assigned a dynamic address by the ENTDAA sequence initiated later on by the first HJ request, preventing this target to emit an HJ request again. + HJACK: u1, + /// RX-FIFO DMA request enable (whatever I3C is acting as controller/target) - Software reads and pops a data byte/word from RX-FIFO i.e. reads I3C_RDR or I3C_RDWR register. - A next data byte/word is to be read by the software either via polling on the flag I3C_EVR.RXFNEF=1 or via interrupt notification (enabled by I3C_IER.RXFNEIE=1). - DMA reads and pops data byte(s)/word(s) from RX-FIFO i.e. reads I3C_RDR or I3C_RDWR register. - A next data byte/word is automatically read by the programmed hardware (i.e. via the asserted RX-FIFO DMA request from the I3C and the programmed DMA channel). + RXDMAEN: u1, + /// RX-FIFO flush (whatever I3C is acting as controller/target) This bit can only be written. + RXFLUSH: u1, + /// RX-FIFO threshold (whatever I3C is acting as controller/target) This threshold defines, compared to the RX-FIFO level, when the I3C_EVR.RXFNEF flag is set (and consequently if RXDMAEN=1 when is asserted a DMA RX request). RXFNEF is set when 1 byte is to be read in RX-FIFO (i.e. in I3C_RDR). RXFNEF is set when 4 bytes are to be read in RX-FIFO (i.e. in I3C_RDWR). + RXTHRES: packed union { raw: u1, - value: FMP, + value: THRES, }, - /// Fast Mode Plus (FM+) driving capability activation bits 0: PA10 pin operate in standard mode 1: I2C FM+ mode enabled on PA10 and the Speed control is bypassed - I2C_PA10_FMP: packed union { + reserved12: u1, + /// TX-FIFO DMA request enable (whatever I3C is acting as controller/target) - Software writes and pushes a data byte/word into TX-FIFO i.e. writes I3C_TDR or I3C_TDWR register, to be transmitted over the I3C bus. - A next data byte/word is to be written by the software either via polling on the flag I3C_EVR.TXFNFF=1 or via interrupt notification (enabled by I3C_IER.TXFNFIE=1). - DMA writes and pushes data byte(s)/word(s) into TX-FIFO i.e. writes I3C_TDR or I3C_TDWR register. - A next data byte/word transfer is automatically pushed by the programmed hardware (i.e. via the asserted TX-FIFO DMA request from the I3C and the programmed DMA channel). + TXDMAEN: u1, + /// TX-FIFO flush (whatever I3C is acting as controller/target) This bit can only be written. When the I3C is acting as target, this bit can be used to flush the TX-FIFO on a private read if the controller has early ended the read data (i.e. driven low the T bit) and there is/are remaining data in the TX-FIFO (i.e. I3C_SR.ABT=1 and I3C_SR.XDCNT[15:0] < I3C_TGTTDR.TGTTDCNT[15:0]). + TXFLUSH: u1, + /// TX-FIFO threshold (whatever I3C is acting as controller/target) This threshold defines, compared to the TX-FIFO level, when the I3C_EVR.TXFNFF flag is set (and consequently if TXDMAEN=1 when is asserted a DMA TX request). TXFNFF is set when 1 byte is to be written in TX-FIFO (i.e. in I3C_TDR). TXFNFF is set when 4 bytes are to be written in TX-FIFO (i.e. in I3C_TDWR). + TXTHRES: packed union { raw: u1, - value: FMP, + value: THRES, }, - /// SPI2 DMA request remapping bit 0: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively 1: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively - SPI2_DMA_RMP: u1, - /// USART2 DMA request remapping bit 0: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively 1: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively - USART2_DMA_RMP: u1, - /// USART3 DMA request remapping bit 0: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0) 1: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively - USART3_DMA_RMP: u1, - /// I2C1 DMA request remapping bit 0: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively 1: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively - I2C1_DMA_RMP: u1, - /// TIM1 DMA request remapping bit 0: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively 1: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 - TIM1_DMA_RMP: u1, - /// TIM2 DMA request remapping bit 0: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively 1: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 - TIM2_DMA_RMP: u1, - /// TIM3 DMA request remapping bit 0: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 1: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 - TIM3_DMA_RMP: u1, + reserved16: u1, + /// S-FIFO DMA request enable (when I3C is acting as controller) Condition: When RMODE=1 (FIFO is enabled for the status): - Software reads and pops a status word from S-FIFO i.e. reads I3C_SR register after a completed frame (I3C_EVR.FCF=1) or an error (I3C_EVR.ERRF=1). - A status word can be read by the software either via polling on these register flags or via interrupt notification (enabled by I3C_IER.FCIE=1 and I3C_IER.ERRIE=1). - DMA reads and pops status word(s) from S-FIFO i.e. reads I3C_SR register. - Status word(s) are automatically read by the programmed hardware (i.e. via the asserted S-FIFO DMA request from the I3C and the programmed DMA channel). + SDMAEN: u1, + /// S-FIFO flush (when I3C is acting as controller) When I3C is acting as I3C controller, this bit can only be written (and is only used when I3C is acting as controller). + SFLUSH: u1, + /// S-FIFO enable / status receive mode (when I3C is acting as controller) When I3C is acting as I3C controller, this bit is used for the enabling the FIFO for the status (S-FIFO) vs the received status from the target on the I3C bus. When I3C is acting as target, this bit must be cleared. - Status register (i.e. I3C_SR) is used without FIFO mechanism. - There is no SCL stretch if a new status register content is not read. - Status register must be read before being lost/overwritten. All message status must be read. There is SCL stretch when there is no more space in the S-FIFO. + RMODE: u1, + /// transmit mode (when I3C is acting as controller) When I3C is acting as I3C controller, this bit is used for the C-FIFO and TX-FIFO management vs the emitted frame on the I3C bus. A frame transfer starts as soon as first control word is present in C-FIFO. + TMODE: u1, + /// C-FIFO DMA request enable (when I3C is acting as controller) When I3C is acting as controller: - Software writes and pushes control word(s) into C-FIFO i.e. writes I3C_CR register, as needed for a given frame. - A next control word transfer can be written by software either via polling on the flag I3C_EVR.CFNFF=1 or via interrupt notification (enabled by I3C_IER.CFNFIE=1). - DMA writes and pushes control word(s) into C-FIFO i.e. writes I3C_CR register, as needed for a given frame. - A next control word transfer is automatically written by the programmed hardware (i.e. via the asserted C-FIFO DMA request from the I3C and the programmed DMA channel). + CDMAEN: u1, + /// C-FIFO flush (when I3C is acting as controller) This bit can only be written. + CFLUSH: u1, + reserved30: u8, + /// frame transfer set (a.k.a. software trigger) (when I3C is acting as controller) This bit can only be written. When I3C is acting as I3C controller: Note: If this bit is not set, the other alternative for the software to initiate a frame transfer is to directly write the first control word register (i.e. I3C_CR) while C-FIFO is empty (i.e. I3C_EVR.CFEF=1). Then, if the first written control word is not tagged as a message end (i.e I3C_CR.MEND=0), it causes the hardware to assert the flag I3C_EVR.CFNFF (C-FIFO not full and a next control word is needed). + TSFSET: u1, padding: u1, }), - reserved8: [4]u8, - /// external interrupt configuration register 1 - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u4, - padding: u28, + reserved16: [8]u8, + RxDataRegs: u32, + reserved24: [4]u8, + TxDataRegs: u32, + reserved32: [4]u8, + /// I3C IBI payload data register. + IBIDR: mmio.Mmio(packed struct(u32) { + /// 8-bit IBI payload data (earliest byte on I3C bus, i.e. MDB[7:0] mandatory data byte). + IBIDB: u8, + padding: u24, }), - /// configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// Cortex-M0 LOCKUP bit enable bit - LOCKUP_LOCK: u1, - /// SRAM parity lock bit - SRAM_PARITY_LOCK: u1, - /// PVD lock enable bit - PVD_LOCK: u1, - reserved8: u5, - /// SRAM parity flag - SRAM_PEF: u1, - padding: u23, + /// I3C target transmit configuration register. + TGTTDR: mmio.Mmio(packed struct(u32) { + /// transmit data counter, in bytes (when I3C is configured as target) This field must be written by software in the same access when is asserted PRELOAD, in order to define the number of bytes to preload and to transmit. This field is updated by hardware and reports, when read, the remaining number of bytes to be loaded into the TX-FIFO. + TGTTDCNT: u16, + /// preload of the TX-FIFO (when I3C is configured as target) This bit must be written and asserted by software in the same access when is written and defined the number of bytes to preload into the TX-FIFO and to transmit. This bit is cleared by hardware when all the data bytes to transmit are loaded into the TX-FIFO. + PRELOAD: u1, + padding: u15, }), - }; - }; - - pub const bdma_v1 = struct { - pub const DIR = enum(u1) { - /// Read from peripheral - FromPeripheral = 0x0, - /// Read from memory - FromMemory = 0x1, - }; - - pub const PL = enum(u2) { - /// Low priority - Low = 0x0, - /// Medium priority - Medium = 0x1, - /// High priority - High = 0x2, - /// Very high priority - VeryHigh = 0x3, - }; - - pub const SIZE = enum(u2) { - /// 8-bit size - Bits8 = 0x0, - /// 16-bit size - Bits16 = 0x1, - /// 32-bit size - Bits32 = 0x2, - _, - }; - - /// Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers - pub const CH = extern struct { - /// DMA channel configuration register (DMA_CCR) - CR: mmio.Mmio(packed struct(u32) { - /// Channel enable - EN: u1, - /// Transfer complete interrupt enable - TCIE: u1, - /// Half Transfer interrupt enable - HTIE: u1, - /// Transfer error interrupt enable - TEIE: u1, - /// Data transfer direction + reserved48: [8]u8, + /// I3C status register. + SR: mmio.Mmio(packed struct(u32) { + /// data counter - When the I3C is acting as controller: number of targets detected on the bus - When the I3C is acting as target: number of transmitted bytes - Whatever the I3C is acting as controller or target: number of data bytes read from or transmitted on the I3C bus during the MID[7:0] message. + XDCNT: u16, + reserved17: u1, + /// a private read message is completed/aborted prematurely by the target (when the I3C is acting as controller) When the I3C is acting as controller, this bit indicates if the private read data which is transmitted by the target early terminates (i.e. the target drives T bit low earlier vs what does expect the controller in terms of programmed number of read data bytes i.e. I3C_CR.DCNT[15:0]). + ABT: u1, + /// message direction Whatever the I3C is acting as controller or target, this bit indicates the direction of the related message on the I3C bus Note: ENTDAA CCC is considered as a write command. DIR: packed union { raw: u1, value: DIR, }, - /// Circular mode enabled - CIRC: u1, - /// Peripheral increment mode enabled - PINC: u1, - /// Memory increment mode enabled - MINC: u1, - /// Peripheral size - PSIZE: packed union { - raw: u2, - value: SIZE, - }, - /// Memory size - MSIZE: packed union { - raw: u2, - value: SIZE, - }, - /// Channel Priority level - PL: packed union { - raw: u2, - value: PL, - }, - /// Memory to memory mode enabled - MEM2MEM: u1, - padding: u17, + reserved24: u5, + /// message identifier/counter of a given frame (when the I3C is acting as controller) When the I3C is acting as controller, this field identifies the control word message (i.e. I3C_CR) to which the I3C_SR status register refers. First message of a frame is identified with MID[7:0]=0. This field is incremented (by hardware) on the completion of a new message control word (i.e. I3C_CR) over I3C bus. This field is reset for every new frame start. + MID: u8, }), - /// DMA channel 1 number of data register - NDTR: mmio.Mmio(packed struct(u32) { - /// Number of data to transfer - NDT: u16, - padding: u16, + /// I3C status error register. + SER: mmio.Mmio(packed struct(u32) { + /// protocol error code/type controller detected an illegally formatted CCC controller detected that transmitted data on the bus is different from expected controller detected a not acknowledged broadcast address (7’hE) controller detected the new controller did not drive bus after controller-role hand-off target detected an invalid broadcast address 7’hE+W target detected a parity error on a CCC code via a parity check (vs T bit) target detected a parity error on a write data via a parity check (vs T bit) target detected a parity error on the assigned address during dynamic address arbitration via a parity check (vs PAR bit) target detected a 7’hE+R missing after Sr during dynamic address arbitration target detected an illegally formatted CCC target detected that transmitted data on the bus is different from expected others: reserved. + CODERR: packed union { + raw: u4, + value: CODERR, + }, + /// protocol error. + PERR: u1, + /// SCL stall error (when the I3C is acting as target). + STALL: u1, + /// RX-FIFO overrun or TX-FIFO underrun i) a TX-FIFO underrun: TX-FIFO is empty and a write data byte has to be transmitted ii) a RX-FIFO overrun: RX-FIFO is full and a new data byte is received. + DOVR: u1, + /// C-FIFO underrun or S-FIFO overrun (when the I3C is acting as controller) i) a C-FIFO underrun: control FIFO is empty and a restart has to be emitted ii) a S-FIFO overrun: S-FIFO is full and a new message ends. + COVR: u1, + /// address not acknowledged (when the I3C is configured as controller) i) a legacy I2C read/write transfer ii) a direct CCC write transfer iii) the second trial of a direct CCC read transfer iv) a private read/write transfer. + ANACK: u1, + /// data not acknowledged (when the I3C is acting as controller) i) a legacy I2C write transfer ii) the second trial when sending dynamic address during ENTDAA procedure. + DNACK: u1, + /// data error (when the I3C is acting as controller). + DERR: u1, + padding: u21, + }), + reserved64: [8]u8, + /// I3C received message register. + RMR: mmio.Mmio(packed struct(u32) { + /// IBI received payload data count (when the I3C is configured as controller) When the I3C is configured as controller, this field logs the number of data bytes effectively received in the I3C_IBIDR register. + IBIRDCNT: u3, + reserved8: u5, + /// received CCC code (when the I3C is configured as target) When the I3C is configured as target, this field logs the received CCC code. + RCODE: u8, + reserved17: u1, + /// received target address (when the I3C is configured as controller) When the I3C is configured as controller, this field logs the received dynamic address from the target during acknowledged IBI or controller-role request. + RADD: u7, + padding: u8, + }), + reserved80: [12]u8, + /// I3C event register. + EVR: mmio.Mmio(packed struct(u32) { + /// C-FIFO empty flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the C-FIFO is empty when controller, and that the I3C_CR register contains no control word (i.e. none IBI/CR/HJ request) when target. This flag is de-asserted by hardware to indicate that the C-FIFO is not empty when controller, and that the I3C_CR register contains one control word (i.e. a pending IBI/CR/HJ request) when target. Note: When the I3C is acting as controller, if the C-FIFO and TX-FIFO preload is configured (i.e. I3C_CFGR.TMODE=1), the software must wait for TXFEF=1 and CFEF=1 before starting a new frame transfer. + CFEF: u1, + /// TX-FIFO empty flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the TX-FIFO is empty. This flag is de-asserted by hardware to indicate that the TX-FIFO is not empty. Note: When the I3C is acting as controller, if the C-FIFO and TX-FIFO preload is configured (i.e. I3C_CFGR.TMODE=1), the software must wait for TXFEF=1 and CFEF=1 before starting a new frame transfer. + TXFEF: u1, + /// C-FIFO not full flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that a control word is to be written to the C-FIFO. This flag is de-asserted by hardware to indicate that a control word is not to be written to the C-FIFO. Note: The software must wait for CFNFF=1 (by polling or via the enabled interrupt) before writing to C-FIFO (i.e. writing to I3C_CR). + CFNFF: u1, + /// S-FIFO not empty flag (when the I3C is acting as controller) When the I3C is acting as controller, if the S-FIFO is enabled (i.e. I3C_CFGR.RMODE=1), this flag is asserted by hardware to indicate that a status word is to be read from the S-FIFO. This flag is de-asserted by hardware to indicate that a status word is not to be read from the S-FIFO. + SFNEF: u1, + /// TX-FIFO not full flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that a data byte/word is to be written to the TX-FIFO. This flag is de-asserted by hardware to indicate that a data byte/word is not to be written to the TX-FIFO. Note: The software must wait for TXFNFF=1 (by polling or via the enabled interrupt) before writing to TX-FIFO (i.e. writing to I3C_TDR or I3C_TDWR depending on I3C_CFGR.TXTHRES). Note: When the I3C is acting as target, if the software intends to use the TXFNFF flag for writing into I3C_TDR/I3C_TDWR, it must have configured and set the TX-FIFO preload (i.e. write I3C_TGTTDR.PRELOAD). + TXFNFF: u1, + /// RX-FIFO not empty flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that a data byte is to be read from the RX-FIFO. This flag is de-asserted by hardware to indicate that a data byte is not to be read from the RX-FIFO. Note: The software must wait for RXFNEF=1 (by polling or via the enabled interrupt) before reading from RX-FIFO (i.e. writing to I3C_RDR or I3C_RDWR depending on I3C_CFGR.RXTHRES). + RXFNEF: u1, + /// last written data byte/word flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the last data byte/word (depending on I3C_CFGR.TXTHRES) of a message is to be written to the TX-FIFO. This flag is de-asserted by hardware when the last data byte/word of a message is written. + TXLASTF: u1, + /// last read data byte/word flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the last data byte/word (depending on I3C_CFGR.RXTHRES) of a message is to be read from the RX-FIFO. This flag is de-asserted by hardware when the last data byte/word of a message is read. + RXLASTF: u1, + reserved9: u1, + /// frame complete flag (whatever the I3C is acting as controller/target) When the I3C is acting as controller, this flag is asserted by hardware to indicate that a frame has been (normally) completed on the I3C bus, i.e when a stop is issued. When the I3C is acting as target, this flag is asserted by hardware to indicate that a message addressed to/by this target has been (normally) completed on the I3C bus, i.e when a next stop or repeated start is then issued by the controller. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CFCF bit. + FCF: u1, + /// target-initiated read end flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that the target has prematurely ended a read transfer. Then, software should read I3C_SR to get more information on the prematurely read transfer. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CRXTGTENDF bit. + RXTGTENDF: u1, + /// flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that an error occurred.Then, software should read I3C_SER to get the error type. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CERRF bit. + ERRF: u1, + reserved15: u3, + /// IBI flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that an IBI request has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CIBIF bit. + IBIF: u1, + /// IBI end flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a IBI transfer has been received and completed (IBI acknowledged and IBI data bytes read by controller if any). This flag is cleared when software writes 1 into corresponding I3C_CEVR.CIBIENDF bit. + IBIENDF: u1, + /// controller-role request flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that a controller-role request has been acknowledged and completed (by hardware). The software should then issue a GETACCCR CCC (get accept controller role) for the controller-role hand-off procedure. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CCRF bit. + CRF: u1, + /// controller-role update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that it has now gained the controller role after the completed controller-role hand-off procedure. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CCRUPDF bit. + CRUPDF: u1, + /// hot-join flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that an hot join request has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CHJF bit. + HJF: u1, + reserved21: u1, + /// wakeup/missed start flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a start has been detected (i.e. a SDA falling edge followed by a SCL falling edge) but on the next SCL falling edge, the I3C kernel clock is (still) gated. Thus an I3C bus transaction may have been lost by the target. The corresponding interrupt may be used to wakeup the device from a low power mode (Sleep or Stop mode). This flag is cleared when software writes 1 into corresponding I3C_CEVR.CWKPF bit. + WKPF: u1, + /// get flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that any direct CCC of get type (GET*** CCC) has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CGETF bit. + GETF: u1, + /// get status flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a direct GETSTATUS CCC (get status) has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CSTAF bit. + STAF: u1, + /// dynamic address update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a dynamic address update has been received via any of the broadcast ENTDAA, RSTDAA and direct SETNEWDA CCC. Then, software should read I3C_DEVR0.DA[6:0] to get the maximum write length value. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CDAUPDF bit. + DAUPDF: u1, + /// maximum write length update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a direct SETMWL CCC (set max write length) has been received. Then, software should read I3C_MAXWLR.MWL[15:0] to get the maximum write length value. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CMWLUPDF bit. + MWLUPDF: u1, + /// maximum read length update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a direct SETMRL CCC (set max read length) has been received. Then, software should read I3C_MAXRLR.MRL[15:0] to get the maximum read length value. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CMRLUPDF bit. + MRLUPDF: u1, + /// reset pattern flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a reset pattern has been detected (i.e. 14 SDA transitions while SCL is low, followed by repeated start, then stop). Then, software should read I3C_DEVR0.RSTACT[1:0] and I3C_DEVR0.RSTVAL, to know what reset level is required. If RSTVAL=1: when the RSTF is asserted (and/or the corresponding interrupt if enabled), I3C_DEVR0.RSTACT[1:0] dictates the reset action to be performed by the software if any. If RSTVAL=0: when the RSTF is asserted (and/or the corresponding interrupt if enabled), the software should issue an I3C reset after a first detected reset pattern, and a system reset on the second one. The corresponding interrupt may be used to wakeup the device from a low power mode (Sleep or Stop mode). This flag is cleared when software writes 1 into corresponding I3C_CEVR.CRSTF bit. + RSTF: u1, + /// activity state update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that the direct or broadcast ENTASx CCC (with x=0...3) has been received. Then, software should read I3C_DEVR0.AS[1:0]. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CASUPDF bit. + ASUPDF: u1, + /// interrupt/controller-role/hot-join update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that the direct or broadcast ENEC/DISEC CCC (enable/disable target events) has been received, where a target event is either an interrupt/IBI request, a controller-role request, or an hot-join request. Then, software should read respectively I3C_DEVR0.IBIEN, I3C_DEVR0.CREN or I3C_DEVR0.HJEN. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CINTUPDF bit. + INTUPDF: u1, + /// DEFTGTS flag (when the I3C is acting as target) When the I3C is acting as target (and is typically controller capable), this flag is asserted by hardware to indicate that the broadcast DEFTGTS CCC (define list of targets) has been received. Then, software may store the received data for when getting the controller role. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CDEFF bit. + DEFF: u1, + /// group addressing flag (when the I3C is acting as target) When the I3C is acting as target (and is typically controller capable), this flag is asserted by hardware to indicate that the broadcast DEFGRPA CCC (define list of group addresses) has been received. Then, software may store the received data for when getting the controller role. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CGRPF bit. + GRPF: u1, + }), + /// I3C interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// C-FIFO not full interrupt enable (whatever the I3C is acting as controller/target). + CFNFIE: u1, + /// S-FIFO not empty interrupt enable (whatever the I3C is acting as controller/target). + SFNEIE: u1, + /// TX-FIFO not full interrupt enable (whatever the I3C is acting as controller/target). + TXFNFIE: u1, + /// RX-FIFO not empty interrupt enable (whatever the I3C is acting as controller/target). + RXFNEIE: u1, + reserved9: u3, + /// frame complete interrupt enable (whatever the I3C is acting as controller/target). + FCIE: u1, + /// target-initiated read end interrupt enable (when the I3C is acting as controller). + RXTGTENDIE: u1, + /// error interrupt enable (whatever the I3C is acting as controller/target). + ERRIE: u1, + reserved15: u3, + /// IBI request interrupt enable (when the I3C is acting as controller). + IBIIE: u1, + /// IBI end interrupt enable (when the I3C is acting as target). + IBIENDIE: u1, + /// controller-role request interrupt enable (when the I3C is acting as controller). + CRIE: u1, + /// controller-role update interrupt enable (when the I3C is acting as target). + CRUPDIE: u1, + /// hot-join interrupt enable (when the I3C is acting as controller). + HJIE: u1, + reserved21: u1, + /// wakeup interrupt enable (when the I3C is acting as target). + WKPIE: u1, + /// GETxxx CCC interrupt enable (when the I3C is acting as target). + GETIE: u1, + /// GETSTATUS CCC interrupt enable (when the I3C is acting as target). + STAIE: u1, + /// ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C is acting as target). + DAUPDIE: u1, + /// SETMWL CCC interrupt enable (when the I3C is acting as target). + MWLUPDIE: u1, + /// SETMRL CCC interrupt enable (when the I3C is acting as target). + MRLUPDIE: u1, + /// reset pattern interrupt enable (when the I3C is acting as target). + RSTIE: u1, + /// ENTASx CCC interrupt enable (when the I3C is acting as target). + ASUPDIE: u1, + /// ENEC/DISEC CCC interrupt enable (when the I3C is acting as target). + INTUPDIE: u1, + /// DEFTGTS CCC interrupt enable (when the I3C is acting as target). + DEFIE: u1, + /// DEFGRPA CCC interrupt enable (when the I3C is acting as target). + GRPIE: u1, + }), + /// I3C clear event register. + CEVR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// clear frame complete flag (whatever the I3C is acting as controller/target). + CFCF: u1, + /// clear target-initiated read end flag (when the I3C is acting as controller). + CRXTGTENDF: u1, + /// clear error flag (whatever the I3C is acting as controller/target). + CERRF: u1, + reserved15: u3, + /// clear IBI request flag (when the I3C is acting as controller). + CIBIF: u1, + /// clear IBI end flag (when the I3C is acting as target). + CIBIENDF: u1, + /// clear controller-role request flag (when the I3C is acting as controller). + CCRF: u1, + /// clear controller-role update flag (when the I3C is acting as target). + CCRUPDF: u1, + /// clear hot-join flag (when the I3C is acting as controller). + CHJF: u1, + reserved21: u1, + /// clear wakeup flag (when the I3C is acting as target). + CWKPF: u1, + /// clear GETxxx CCC flag (when the I3C is acting as target). + CGETF: u1, + /// clear GETSTATUS CCC flag (when the I3C is acting as target). + CSTAF: u1, + /// clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C is acting as target). + CDAUPDF: u1, + /// clear SETMWL CCC flag (when the I3C is acting as target). + CMWLUPDF: u1, + /// clear SETMRL CCC flag (when the I3C is acting as target). + CMRLUPDF: u1, + /// clear reset pattern flag (when the I3C is acting as target). + CRSTF: u1, + /// clear ENTASx CCC flag (when the I3C is acting as target). + CASUPDF: u1, + /// clear ENEC/DISEC CCC flag (when the I3C is acting as target). + CINTUPDF: u1, + /// clear DEFTGTS CCC flag (when the I3C is acting as target). + CDEFF: u1, + /// clear DEFGRPA CCC flag (when the I3C is acting as target). + CGRPF: u1, + }), + reserved96: [4]u8, + /// I3C own device characteristics register. + DEVR0: mmio.Mmio(packed struct(u32) { + /// dynamic address is valid (when the I3C is acting as target) When the I3C is acting as controller, this field can be written by software, for validating its own dynamic address, for example before a controller-role hand-off. When the I3C is acting as target, this field is asserted by hardware on the acknowledge of the broadcast ENTDAA CCC or the direct SETNEWDA CCC, and this field is cleared by hardware on the acknowledge of the broadcast RSTDAA CCC. + DAVAL: u1, + /// 7-bit dynamic address When the I3C is acting as controller, this field can be written by software, for defining its own dynamic address. When the I3C is acting as target, this field is updated by hardware on the reception of either the broadcast ENTDAA CCC or the direct SETNEWDA CCC. + DA: u7, + reserved16: u8, + /// IBI request enable (when the I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0, and is updated by hardware on the reception of DISEC CCC with DISINT=1 (i.e. cleared) and the reception of ENEC CCC with ENINT=1 (i.e. set). + IBIEN: u1, + /// controller-role request enable (when the I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0, and is updated by hardware on the reception of DISEC CCC with DISCR=1 (i.e. cleared) and the reception of ENEC CCC with ENCR=1 (i.e. set). + CREN: u1, + reserved19: u1, + /// hot-join request enable (when the I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0, and is updated by hardware on the reception of DISEC CCC with DISHJ=1 (i.e. cleared) and the reception of ENEC CCC with ENHJ=1 (i.e. set). + HJEN: u1, + /// activity state (when the I3C is acting as target) This read field is updated by hardware on the reception of a ENTASx CCC (enter activity state, with x=0-3):. + AS: u2, + /// reset action/level on received reset pattern (when the I3C is acting as target) This read field is used by hardware on the reception of a direct read RSTACT CCC in order to return the corresponding data byte on the I3C bus. This read field is updated by hardware on the reception of a broadcast or direct write RSTACT CCC (target reset action). Only the defining bytes 0x00, 0x01 and 0x02 are mapped, and RSTACT[1:0] = Defining Byte[1:0]. a) partially reset the I3C peripheral, by a write and clear of the enable bit of the i3C configuration register (i.e. write I3C_CFGR.EN=0). This reset the I3C bus interface and the I3C kernel sub-parts, without modifying the content of the I3C APB registers (excepted the I3C_CFGR.EN bit). b) reset fully the I3C peripheral including all its registers via a write and set to the I3C reset control bit of the RCC (Reset and Clock Controller) register. a system reset. This has the same impact as a pin reset (i.e. NRST=0) (refer to RCC functional description - Reset part): – the software writes and set the AICR.SYSRESETREQ register control bit, when the device is controlled by a CortexTM-M. – the software writes and set the RCC_GRSTCSETR.SYSRST=1, when the device is controlled by a CortexTM-A. + RSTACT: packed union { + raw: u2, + value: RSTACT, + }, + /// reset action is valid (when the I3C is acting as target) This read bit is asserted by hardware to indicate that the RTSACT[1:0] field has been updated on the reception of a broadcast or direct write RSTACT CCC (target reset action) and is valid. This field is cleared by hardware when the target receives a frame start. If RSTVAL=1: when the RSTF is asserted (and/or the corresponding interrupt if enabled), I3C_DEVR0.RSTACT[1:0] dictates the reset action to be performed by the software if any. If RSTVAL=0: when the RSTF is asserted (and/or the corresponding interrupt if enabled), the software should issue an I3C reset after a first detected reset pattern, and a system reset on the second one. + RSTVAL: u1, + padding: u7, + }), + /// I3C device 1 characteristics register. + DEVR: [4]mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// assigned I3C dynamic address to target x (when the I3C is acting as controller) When the I3C is acting as controller, this field should be written by software to store the 7-bit dynamic address that the controller sends via a broadcast ENTDAA or a direct SETNEWDA CCC which has been acknowledged by the target x. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1. + DA: u7, + reserved16: u8, + /// IBI request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a IBI request from target x: - After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another IBI request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the controller logs the IBI payload data, if any, depending on I3C_DEVRx.IBIDEN. - The software is notified by the IBI flag (i.e. I3C_EVR.IBIF=1) and/or the corresponding interrupt if enabled; - Independently from IBIACK configuration for this or other devices, further IBI request(s) are NACKed until IBI request flag (i.e. I3C_EVR.IBIF) and controller-role request flag (i.e. I3C_EVR.CRF) are both cleared. + IBIACK: packed union { + raw: u1, + value: ACK, + }, + /// controller-role request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a controller-role request from target x: After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another controller-role request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the message continues as initially programmed. The software is notified by the controller-role request flag (i.e. I3C_EVR.CRF=1) and/or the corresponding interrupt if enabled; For effectively granting the controller-role to the requesting secondary controller, software should issue a GETACCCR (formerly known as GETACCMST), followed by a STOP. - Independently of CRACK configuration for this or other devices, further controller-role request(s) are NACKed until controller-role request flag (i.e. I3C_EVR.CRF) and IBI flag (i.e. I3C_EVR.IBIF) are both cleared. + CRACK: packed union { + raw: u1, + value: ACK, + }, + /// IBI data enable (when the I3C is acting as controller) When the I3C is acting as controller, this bit should be written by software to store the BCR[2] bit as received from the target x during broadcast ENTDAA or direct GETBCR CCC via the received I3C_RDR. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1. + IBIDEN: u1, + /// suspend/stop I3C transfer on received IBI (when the I3C is acting as controller) When the I3C is acting as controller, this bit is used to receive an IBI from target x with pending read notification feature (i.e. with received MDB[7:5]=3’b101). If this bit is set, when an IBI is received (i.e. I3C_EVR.IBIF=1), a Stop is emitted on the I3C bus and the C-FIFO is automatically flushed by hardware; to avoid a next private read communication issue if a previous private read message to the target x was stored in the C-FIFO. + SUSP: u1, + reserved31: u11, + /// DA[6:0] write disabled (when the I3C is acting as controller) When the I3C is acting as controller, once that software set IBIACK=1 or CRACK=1, this read bit is set by hardware (i.e. DIS=1) to lock the configured DA[6:0] and IBIDEN values. Then, to be able to next modify DA[6:0] or IBIDEN, the software must wait for this field DIS to be de-asserted by hardware (i.e. polling on DIS=0) before modifying these two assigned values to the target x. Indeed, the target may be requesting an IBI or a controller-role meanwhile the controller intends to modify DA[6:0] or IBIDEN. + DIS: packed union { + raw: u1, + value: DIS, + }, + }), + reserved144: [28]u8, + /// I3C maximum read length register. + MAXRLR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// IBI payload data size, in bytes (when I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0 to set the number of data bytes to be sent to the controller after an IBI request has been acknowledged.This field may be updated by hardware on the reception of SETMRL command (which potentially also updated IBIP[2:0]). Software is notified of a MRL update by the I3C_EVR.MRLUPF and the corresponding interrupt if enabled. others: same as 100. + IBIP: u3, + padding: u13, + }), + /// I3C maximum write length register. + MAXWLR: mmio.Mmio(packed struct(u32) { + /// maximum data write length (when I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0 and updated by hardware on the reception of SETMWL command. Software is notified of a MWL update by the I3C_EVR.MWLUPF and the corresponding interrupt if enabled. This field is used by hardware to return the value on the I3C bus when the target receives a GETMWL CCC. + ML: u16, + padding: u16, + }), + reserved160: [8]u8, + /// I3C timing register 0. + TIMINGR0: mmio.Mmio(packed struct(u32) { + /// SCL low duration in I3C push-pull phases, in number of kernel clocks cycles: tSCLL_PP = (SCLL_PP + 1) x tI3CCLK SCLL_PP is used to generate tLOW (I3C) timing. + SCLL_PP: u8, + /// SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles: tSCLH_I3C = (SCLH_I3C + 1) x tI3CCLK SCLH_I3C is used to generate both tHIGH (I3C) and tHIGH_MIXED timings. + SCLH_I3C: u8, + /// SCL low duration in open-drain phases, used for legacy I2C commands and for I3C open-drain phases (address header phase following a START, not a Repeated START), in number of kernel clocks cycles: tSCLL_OD = (SCLL_OD + 1) x tI3CCLK SCLL_OD is used to generate both tLOW (I2C) and tLOW_OD timings (max. of the two). + SCLL_OD: u8, + /// SCL high duration, used for legacy I2C commands, in number of kernel clocks cycles: tSCLH_I2C = (SCLH_I2C + 1) x tI3CCLK SCLH_I2C is used to generate tHIGH (I2C) timing. + SCLH_I2C: u8, + }), + /// I3C timing register 1. + TIMINGR1: mmio.Mmio(packed struct(u32) { + /// number of kernel clock cycles, that is used whatever I3C is acting as controller or target, to set the following MIPI I3C timings, like bus available condition time: When the I3C is acting as target: for bus available condition time: it must wait for (bus available condition) time to be elapsed after a stop and before issuing a start request for an IBI or a controller-role request (i.e. bus free condition is sustained for at least tAVAL). refer to MIPI timing tAVAL = 1 �s. This timing is defined by: tAVAL = (AVAL[7:0] + 2) x tI3CCLK for bus idle condition time: it must wait for (bus idle condition) time to be elapsed after that both SDA and SCL are continuously high and stable before issuing a hot-join event. Refer to MIPI v1.1 timing tIDLE = 200 �s . This timing is defined by: tIDLE = (AVAL[7:0] + 2) x 200 x tI3CCLK When the I3C is acting as controller, it can not stall the clock beyond a maximum stall time (i.e. stall the SCL clock low), as follows: on first bit of assigned address during dynamic address assignment: it can not stall the clock beyond the MIPI timing tSTALLDAA = 15 ms. This timing is defined by: tSTALLDAA = (AVAL[7:0] + 1) x 15000 x tI3CCLK on ACK/NACK phase of I3C/I2C transfer, on parity bit of write data transfer, on transition bit of I3C read transfer: it can not stall the clock beyond the MIPI timing tSTALL = 100 �s. This timing is defined by: tSTALL = (AVAL[7:0] + 1) x 100 x tI3CCLK Whatever the I3C is acting as controller or as (controller-capable) target, during a controller-role hand-off procedure: The new controller must wait for a time (refer to MIPI timing tNEWCRLock) before pulling SDA low (i.e. issuing a start). And the active controller must wait for the same time while monitoring new controller and before testing the new controller by pulling SDA low. This time to wait is dependent on the defined I3C_TIMINGR1.ANSCR[1:0], as follows: If ASNCR[1:0]=00: tNEWCRLock = (AVAL[7:0] + 1) x tI3CCLK If ASNCR[1:0]=01: tNEWCRLock = (AVAL[7:0] + 1) x 100 x tI3CCLK If ASNCR[1:0]=10: tNEWCRLock = (AVAL[7:0] + 1) x 2000 x tI3CCLK If ASNCR[1:0]=11: tNEWCRLock = (AVAL[7:0] + 1) x 50000 x tI3CCLK. + AVAL: u8, + /// activity state of the new controller (when I3C is acting as - active- controller) This field indicates the time to wait before being accessed as new target, refer to the other field AVAL[7:0]. This field can be modified only when the I3C is acting as controller. + ASNCR: u2, + reserved16: u6, + /// number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C is acting as controller) When the I3C is acting as controller: for I3C start timing: it must wait for (bus free condition) time to be elapsed after a stop and before a start, refer to MIPI timings (I3C) tCAS and (I2C) tBUF. These timings are defined by: tBUF= tCAS = [ (FREE[6:0] + 1) x 2 - (0,5 + SDA_HD)] x tI3CCLK Note: for pure I3C bus: tCASmin= 38,4 ns. Note: for pure I3C bus: tCASmax=1�s, 100�s, 2ms, 50ms for respectively ENTAS0,1,2, and 3. Note: for mixed bus with I2C fm+ device: tBUFmin = 0,5 �s. Note: for mixed bus with I2C fm device: tBUFmin = 1,3 �s. for I3C repeated start timing: it must wait for time to be elapsed after a repeated start (i.e. SDA is de-asserted) and before driving SCL low, refer to. MIPI timing tCASr. This timing is defined by: tCASr = [ (FREE[6:0] + 1) x 2 - (0,5 + SDA_HD)] x tI3CCLK for I3C stop timing: it must wait for time to be elapsed after that the SCL clock is driven high and before the stop condition (i.e. SDA is asserted). This timing is defined by: tCBP = (FREE[6:0] + 1) x tI3CCLK for I3C repeated start timing (T-bit when controller ends read with repeated start followed by stop): it must wait for time to be elapsed after that the SCL clock is driven high and before the repeated start condition (i.e. SDA is de-asserted). This timing is defined by: tCBSr = (FREE[6:0] + 1) x tI3CCLK. + FREE: u7, + reserved28: u5, + /// SDA hold time (when the I3C is acting as controller), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull tHD_PP):. + SDA_HD: u1, + padding: u3, + }), + /// I3C timing register 2. + TIMINGR2: mmio.Mmio(packed struct(u32) { + /// Controller clock stall on T-bit phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to prepare data to be sent. + STALLT: u1, + /// controller clock stall on PAR phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to read received data. + STALLD: u1, + /// controller clock stall on PAR phase of CCC enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase of common command code (before 9th bit). This allows the target to decode the command. + STALLC: u1, + /// controller clock stall enable on ACK phase The SCL is stalled (during tSCLL_STALLas defined by STALL) in the address ACK/NACK phase (before 9th bit). This allows the target to prepare data or the controller to respond to target interrupt. + STALLA: u1, + reserved8: u4, + /// controller clock stall time, in number of kernel clock cycles tSCLL_STALL = STALL x tI3CCLK. + STALL: u8, + padding: u16, + }), + reserved192: [20]u8, + /// I3C bus characteristics register. + BCR: mmio.Mmio(packed struct(u32) { + /// max data speed limitation. + BCR0: u1, + reserved2: u1, + /// in-band interrupt (IBI) payload. + BCR2: u1, + reserved6: u3, + /// controller capable. + BCR6: u1, + padding: u25, + }), + /// I3C device characteristics register. + DCR: mmio.Mmio(packed struct(u32) { + /// device characteristics ID others: ID to describe the type of the I3C sensor/device Note: The latest MIPI DCR ID assignments are available at: https://www.mipi.org/MIPI_I3C_device_characteristics_register. + DCR: u8, + padding: u24, + }), + /// I3C get capability register. + GETCAPR: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// IBI MDB support for pending read notification This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates the support (or not) of the pending read notification via the IBI MDB[7:0] value. This bit is used to return the GETCAP3 byte in response to the GETCAPS CCC format 1. + CAPPEND: u1, + padding: u17, + }), + /// I3C controller-role capability register. + CRCAPR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// delayed controller-role hand-off This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates if this target I3C may need additional time to process a controller-role hand-off requested by the current controller. This bit is used to return the CRCAP2 byte in response to the GETCAPS CCC format 2. + CAPDHOFF: u1, + reserved9: u5, + /// group management support (when acting as controller) This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates if the I3C is able to support group management when it acts as a controller (after controller-role hand-off) via emitted DEFGRPA, RSTGRPA, and SETGRPA CCC. This bit is used to return the CRCAP1 byte in response to the GETCAPS CCC format 2. + CAPGRP: u1, + padding: u22, + }), + /// I3C get capability register. + GETMXDSR: mmio.Mmio(packed struct(u32) { + /// controller hand-off activity state This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates in which initial activity state the (other) current controller should expect the I3C bus after a controller-role hand-off to this controller-capable I3C, when returning the defining byte CRHDLY (0x91) to a GETMXDS CCC. This 2-bit field is used to return the CRHDLY1 byte in response to the GETCAPS CCC format 3, in order to state which is the activity state of this I3C when becoming controller after a controller-role hand-off, and consequently the time the former controller should wait before testing this I3C to be confirmed its ownership. + HOFFAS: u2, + reserved8: u6, + /// GETMXDS CCC format. + FMT: u2, + reserved16: u6, + /// programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte) This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and writes the value of the selected byte (via the FMT[1:0] field) of the 3-byte MaxRdTurn which is returned in response to the GETMXDS CCC format 2 to encode the maximum read turnaround time. + RDTURN: u8, + /// clock-to-data turnaround time (tSCO) This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and is used to specify the clock-to-data turnaround time tSCO (vs the value of 12 ns). This bit is used by the hardware in response to the GETMXDS CCC to return the encoded clock-to-data turnaround time via the returned MaxRd[5:3] bits. + TSCO: u1, + padding: u7, + }), + /// I3C extended provisioned ID register. + EPIDR: mmio.Mmio(packed struct(u32) { + reserved12: u12, + /// 4-bit MIPI Instance ID This field is written by software to set and identify individually each instance of this I3C IP with a specific number on a single I3C bus. This field represents the bits[15:12] of the 48-bit provisioned ID. Note: The bits[11:0] of the provisioned ID may be 0. + MIPIID: u4, + /// provisioned ID type selector This field is set as 0 i.e. vendor fixed value. This field represents the bit[32] of the 48-bit provisioned ID. Note: The bits[31:16] of the provisioned ID may be 0. + IDTSEL: u1, + /// 15-bit MIPI manufacturer ID This read field is the 15-bit STMicroelectronics MIPI ID i.e. 0x0104. This field represents the bits[47:33] of the 48-bit provisioned ID. + MIPIMID: u15, }), - /// DMA channel 1 peripheral address register - PAR: u32, - /// DMA channel 1 memory address register - MAR: u32, }; + }; - /// DMA controller - pub const DMA = extern struct { - /// DMA interrupt status register (DMA_ISR) - ISR: mmio.Mmio(packed struct(u32) { - /// Channel 1 Global interrupt flag - GIF: u1, - /// Channel 1 Transfer Complete flag - TCIF: u1, - /// Channel 1 Half Transfer Complete flag - HTIF: u1, - /// Channel 1 Transfer Error flag - TEIF: u1, - padding: u28, + pub const icache_v1_0crr = struct { + pub const WAYSEL = enum(u1) { + /// direct mapped cache (1-way cache) + DirectMapped = 0x0, + /// n-way set associative cache (reset value) + NWaySetAssociative = 0x1, + }; + + /// Instruction Cache Control Registers. + pub const ICACHE = extern struct { + /// ICACHE control register. + CR: mmio.Mmio(packed struct(u32) { + /// EN. + EN: u1, + /// Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. + CACHEINV: u1, + /// This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). + WAYSEL: packed union { + raw: u1, + value: WAYSEL, + }, + reserved16: u13, + /// Hit monitor enable. + HITMEN: u1, + /// Miss monitor enable. + MISSMEN: u1, + /// Hit monitor reset. + HITMRST: u1, + /// Miss monitor reset. + MISSMRST: u1, + padding: u12, }), - /// DMA interrupt flag clear register (DMA_IFCR) - IFCR: mmio.Mmio(packed struct(u32) { - /// Channel 1 Global interrupt flag - GIF: u1, - /// Channel 1 Transfer Complete flag - TCIF: u1, - /// Channel 1 Half Transfer Complete flag - HTIF: u1, - /// Channel 1 Transfer Error flag - TEIF: u1, - padding: u28, + /// ICACHE status register. + SR: mmio.Mmio(packed struct(u32) { + /// cache busy executing a full invalidate CACHEINV operation. + BUSYF: u1, + /// full invalidate CACHEINV operation finished. + BSYENDF: u1, + /// an error occurred during the operation. + ERRF: u1, + padding: u29, + }), + /// ICACHE interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Interrupt enable on busy end. + BSYENDIE: u1, + /// Error interrupt on cache error. + ERRIE: u1, + padding: u29, + }), + /// ICACHE flag clear register. + FCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clear busy end flag. + CBSYENDF: u1, + /// Clear ERRF flag in SR. + CERRF: u1, + padding: u29, + }), + /// ICACHE hit monitor register. + HMONR: u32, + /// ICACHE miss monitor register. + MMONR: mmio.Mmio(packed struct(u32) { + /// Miss monitor register. + MISSMON: u16, + padding: u16, }), - /// Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers - CH: u32, }; }; - pub const rcc_g0 = struct { - pub const ADCSEL = enum(u2) { - /// SYSCLK used as ADC clock source - SYS = 0x0, - /// PLLPCLK used as ADC clock source - PLL1_P = 0x1, - /// HSI used as ADC clock source - HSI = 0x2, - _, + pub const icache_v1_3crr = struct { + pub const HBURST = enum(u1) { + Wrap = 0x0, + Increment = 0x1, }; - pub const CECSEL = enum(u1) { - /// HSI divided by 488 used as CEC clock - HSI_DIV_488 = 0x0, - /// LSE used as CEC clock - LSE = 0x1, + pub const MSTSEL = enum(u1) { + Master1Selected = 0x0, + Master2Selected = 0x1, }; - pub const FDCANSEL = enum(u2) { - /// PCLK used as FDCAN clock source - PCLK1 = 0x0, - /// PLLQCLK used as FDCAN clock source - PLL1_Q = 0x1, - /// HSE used as FDCAN clock source - HSE = 0x2, + pub const RSIZE = enum(u3) { + MegaBytes2 = 0x1, + MegaBytes4 = 0x2, + MegaBytes8 = 0x3, + MegaBytes16 = 0x4, + MegaBytes32 = 0x5, + MegaBytes64 = 0x6, + MegaBytes128 = 0x7, _, }; - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK is divided by 2 - Div2 = 0x8, - /// SYSCLK is divided by 4 - Div4 = 0x9, - /// SYSCLK is divided by 8 - Div8 = 0xa, - /// SYSCLK is divided by 16 - Div16 = 0xb, - /// SYSCLK is divided by 64 - Div64 = 0xc, - /// SYSCLK is divided by 128 - Div128 = 0xd, - /// SYSCLK is divided by 256 - Div256 = 0xe, - /// SYSCLK is divided by 512 - Div512 = 0xf, - _, + pub const WAYSEL = enum(u1) { + /// direct mapped cache (1-way cache) + DirectMapped = 0x0, + /// n-way set associative cache (reset value) + NWaySetAssociative = 0x1, }; - pub const HSIDIV = enum(u3) { - /// HSI clock is not divided - Div1 = 0x0, - /// HSI clock is divided by 2 - Div2 = 0x1, - /// HSI clock is divided by 4 - Div4 = 0x2, - /// HSI clock is divided by 8 - Div8 = 0x3, - /// HSI clock is divided by 16 - Div16 = 0x4, - /// HSI clock is divided by 32 - Div32 = 0x5, - /// HSI clock is divided by 64 - Div64 = 0x6, - /// HSI clock is divided by 128 - Div128 = 0x7, + /// Instruction Cache Control Registers. + pub const ICACHE = extern struct { + /// ICACHE control register. + CR: mmio.Mmio(packed struct(u32) { + /// EN. + EN: u1, + /// Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. + CACHEINV: u1, + /// This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). + WAYSEL: packed union { + raw: u1, + value: WAYSEL, + }, + reserved16: u13, + /// Hit monitor enable. + HITMEN: u1, + /// Miss monitor enable. + MISSMEN: u1, + /// Hit monitor reset. + HITMRST: u1, + /// Miss monitor reset. + MISSMRST: u1, + padding: u12, + }), + /// ICACHE status register. + SR: mmio.Mmio(packed struct(u32) { + /// cache busy executing a full invalidate CACHEINV operation. + BUSYF: u1, + /// full invalidate CACHEINV operation finished. + BSYENDF: u1, + /// an error occurred during the operation. + ERRF: u1, + padding: u29, + }), + /// ICACHE interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Interrupt enable on busy end. + BSYENDIE: u1, + /// Error interrupt on cache error. + ERRIE: u1, + padding: u29, + }), + /// ICACHE flag clear register. + FCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clear busy end flag. + CBSYENDF: u1, + /// Clear ERRF flag in SR. + CERRF: u1, + padding: u29, + }), + /// ICACHE hit monitor register. + HMONR: u32, + /// ICACHE miss monitor register. + MMONR: mmio.Mmio(packed struct(u32) { + /// Miss monitor register. + MISSMON: u16, + padding: u16, + }), + reserved32: [8]u8, + /// Cluster CRR%s, container region configuration registers. + CRR: [3]mmio.Mmio(packed struct(u32) { + /// base address for region. + BASEADDR: u8, + reserved9: u1, + /// size for region. + RSIZE: packed union { + raw: u3, + value: RSIZE, + }, + reserved15: u3, + /// enable for region. + REN: u1, + /// remapped address for region. + REMAPADDR: u11, + reserved28: u1, + /// AHB cache master selection for region. + MSTSEL: packed union { + raw: u1, + value: MSTSEL, + }, + reserved31: u2, + /// output burst type for region. + HBURST: packed union { + raw: u1, + value: HBURST, + }, + }), }; + }; - pub const I2C1SEL = enum(u2) { - /// PCLK used as I2C1 clock source - PCLK1 = 0x0, - /// SYSCLK used as I2C1 clock source - SYS = 0x1, - /// HSI used as I2C1 clock source - HSI = 0x2, - _, + pub const icache_v1_4crr = struct { + pub const HBURST = enum(u1) { + Wrap = 0x0, + Increment = 0x1, }; - pub const I2C2I2S1SEL = enum(u2) { - /// PCLK used as I2C2/I2S2 clock source - PCLK1 = 0x0, - /// SYSCLK used as I2C2/I2S2 clock source - SYS = 0x1, - /// HSI used as I2C2/I2S2 clock source - HSI = 0x2, - /// External clock used as I2C2/I2S2 clock source - I2S_CKIN = 0x3, + pub const MSTSEL = enum(u1) { + Master1Selected = 0x0, + Master2Selected = 0x1, }; - pub const I2S1SEL = enum(u2) { - /// SYSCLK used as I2S1 clock source - SYS = 0x0, - /// PLLPCLK used as I2S1 clock source - PLL1_P = 0x1, - /// HSI used as I2S1 clock source - HSI = 0x2, - /// External clock used as I2S1 clock source - I2S_CKIN = 0x3, + pub const RSIZE = enum(u3) { + MegaBytes2 = 0x1, + MegaBytes4 = 0x2, + MegaBytes8 = 0x3, + MegaBytes16 = 0x4, + MegaBytes32 = 0x5, + MegaBytes64 = 0x6, + MegaBytes128 = 0x7, + _, }; - pub const I2S2SEL = enum(u2) { - /// SYSCLK used as I2S2 clock source - SYS = 0x0, - /// PLLPCLK used as I2S2 clock source - PLL1_P = 0x1, - /// HSI used as I2S2 clock source - HSI = 0x2, - /// External clock used as I2S2 clock source - I2S_CKIN = 0x3, + pub const WAYSEL = enum(u1) { + /// direct mapped cache (1-way cache) + DirectMapped = 0x0, + /// n-way set associative cache (reset value) + NWaySetAssociative = 0x1, }; - pub const LPTIM1SEL = enum(u2) { - /// PCLK used as LPTIM1 clock source - PCLK1 = 0x0, - /// LSI used as LPTIM1 clock source - LSI = 0x1, - /// HSI used as LPTIM1 clock source - HSI = 0x2, - /// LSE used as LPTIM1 clock source - LSE = 0x3, + /// Instruction Cache Control Registers. + pub const ICACHE = extern struct { + /// ICACHE control register. + CR: mmio.Mmio(packed struct(u32) { + /// EN. + EN: u1, + /// Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. + CACHEINV: u1, + /// This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). + WAYSEL: packed union { + raw: u1, + value: WAYSEL, + }, + reserved16: u13, + /// Hit monitor enable. + HITMEN: u1, + /// Miss monitor enable. + MISSMEN: u1, + /// Hit monitor reset. + HITMRST: u1, + /// Miss monitor reset. + MISSMRST: u1, + padding: u12, + }), + /// ICACHE status register. + SR: mmio.Mmio(packed struct(u32) { + /// cache busy executing a full invalidate CACHEINV operation. + BUSYF: u1, + /// full invalidate CACHEINV operation finished. + BSYENDF: u1, + /// an error occurred during the operation. + ERRF: u1, + padding: u29, + }), + /// ICACHE interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Interrupt enable on busy end. + BSYENDIE: u1, + /// Error interrupt on cache error. + ERRIE: u1, + padding: u29, + }), + /// ICACHE flag clear register. + FCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clear busy end flag. + CBSYENDF: u1, + /// Clear ERRF flag in SR. + CERRF: u1, + padding: u29, + }), + /// ICACHE hit monitor register. + HMONR: u32, + /// ICACHE miss monitor register. + MMONR: mmio.Mmio(packed struct(u32) { + /// Miss monitor register. + MISSMON: u16, + padding: u16, + }), + reserved32: [8]u8, + /// Cluster CRR%s, container region configuration registers. + CRR: [4]mmio.Mmio(packed struct(u32) { + /// base address for region. + BASEADDR: u8, + reserved9: u1, + /// size for region. + RSIZE: packed union { + raw: u3, + value: RSIZE, + }, + reserved15: u3, + /// enable for region. + REN: u1, + /// remapped address for region. + REMAPADDR: u11, + reserved28: u1, + /// AHB cache master selection for region. + MSTSEL: packed union { + raw: u1, + value: MSTSEL, + }, + reserved31: u2, + /// output burst type for region. + HBURST: packed union { + raw: u1, + value: HBURST, + }, + }), }; + }; - pub const LPTIM2SEL = enum(u2) { - /// PCLK used as LPTIM2 clock source - PCLK1 = 0x0, - /// LSI used as LPTIM2 clock source - LSI = 0x1, - /// HSI used as LPTIM2 clock source - HSI = 0x2, - /// LSE used as LPTIM2 clock source - LSE = 0x3, + pub const ipcc_v1 = struct { + /// IPCC + pub const IPCC = extern struct { + /// CPU specific registers + CPU: u32, }; - pub const LPUART1SEL = enum(u2) { - /// PCLK used as LPUART1 clock source - PCLK1 = 0x0, - /// SYSCLK used as LPUART1 clock source - SYS = 0x1, - /// HSI used as LPUART1 clock source - HSI = 0x2, - /// LSE used as LPUART1 clock source - LSE = 0x3, + /// IPCC + pub const IPCC_CPU = extern struct { + /// Control register CPUx + CR: mmio.Mmio(packed struct(u32) { + /// processor x Receive channel occupied interrupt enable + RXOIE: u1, + reserved16: u15, + /// processor x Transmit channel free interrupt enable + TXFIE: u1, + padding: u15, + }), + /// Mask register CPUx + MR: mmio.Mmio(packed struct(u32) { + /// processor x Receive channel y occupied interrupt enable + CHOM: u1, + reserved16: u15, + /// processor x Transmit channel y free interrupt mask + CHFM: u1, + padding: u15, + }), + /// Status Set or Clear register CPUx + SCR: mmio.Mmio(packed struct(u32) { + /// processor x Receive channel y status clear + CHC: u1, + reserved16: u15, + /// processor x Transmit channel y status set + CHS: u1, + padding: u15, + }), + /// CPUx to CPUy status register + SR: mmio.Mmio(packed struct(u32) { + /// processor x transmit to process y Receive channel z status flag + CHF: u1, + padding: u31, + }), }; + }; - pub const LPUART2SEL = enum(u2) { - /// PCLK used as LPUART2 clock source - PCLK1 = 0x0, - /// SYSCLK used as LPUART2 clock source - SYS = 0x1, - /// HSI used as LPUART2 clock source - HSI = 0x2, - /// LSE used as LPUART2 clock source - LSE = 0x3, + pub const iwdg_v1 = struct { + pub const KEY = enum(u16) { + /// Enable access to PR, RLR and WINR registers (0x5555) + Enable = 0x5555, + /// Reset the watchdog value (0xAAAA) + Reset = 0xaaaa, + /// Start the watchdog (0xCCCC) + Start = 0xcccc, + _, }; - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, + pub const PR = enum(u3) { + /// Divider /4 + DivideBy4 = 0x0, + /// Divider /8 + DivideBy8 = 0x1, + /// Divider /16 + DivideBy16 = 0x2, + /// Divider /32 + DivideBy32 = 0x3, + /// Divider /64 + DivideBy64 = 0x4, + /// Divider /128 + DivideBy128 = 0x5, + /// Divider /256 + DivideBy256 = 0x6, + /// Divider /256 + DivideBy256bis = 0x7, }; - pub const MCOPRE = enum(u4) { - /// MCO1 not divided - Div1 = 0x0, - /// MCO clock is divided by 2 - Div2 = 0x1, - /// MCO clock is divided by 4 - Div4 = 0x2, - /// MCO clock is divided by 8 - Div8 = 0x3, - /// MCO clock is divided divided by 16 - Div16 = 0x4, - /// MCO clock is divided divided by 32 - Div32 = 0x5, - /// MCO clock is divided divided by 64 - Div64 = 0x6, - /// MCO clock is divided divided by 128 - Div128 = 0x7, - /// MCO clock is divided divided by 256 - Div256 = 0x8, - /// MCO clock is divided divided by 512 - Div512 = 0x9, - /// MCO clock is divided divided by 1024 - Div1024 = 0xa, - _, + /// Independent watchdog + pub const IWDG = extern struct { + /// Key register + KR: mmio.Mmio(packed struct(u32) { + /// Key value (write only, read 0000h) + KEY: packed union { + raw: u16, + value: KEY, + }, + padding: u16, + }), + /// Prescaler register + PR: mmio.Mmio(packed struct(u32) { + /// Prescaler divider + PR: packed union { + raw: u3, + value: PR, + }, + padding: u29, + }), + /// Reload register + RLR: mmio.Mmio(packed struct(u32) { + /// Watchdog counter reload value + RL: u12, + padding: u20, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Watchdog prescaler value update + PVU: u1, + /// Watchdog counter reload value update + RVU: u1, + padding: u30, + }), }; + }; - pub const MCOSEL = enum(u4) { - /// No clock, MCO output disabled - DISABLE = 0x0, - /// SYSCLK selected as MCO source - SYS = 0x1, - /// HSI48 selected as MCO source - HSI48 = 0x2, - /// HSI selected as MCO source - HSI = 0x3, - /// HSE selected as MCO source - HSE = 0x4, - /// PLLRCLK selected as MCO source - PLLRCLK = 0x5, - /// LSI selected as MCO source - LSI = 0x6, - /// LSE selected as MCO source - LSE = 0x7, - /// PLLPCLK selected as MCO source - PLL1_P = 0x8, - /// PLLQCLK selected as MCO source - PLL1_Q = 0x9, - /// RTCCLK selected as MCO source - RTCCLK = 0xa, - /// RTC_Wakeup selected as MCO source - RTC_WKUP = 0xb, + pub const iwdg_v2 = struct { + pub const KEY = enum(u16) { + /// Enable access to PR, RLR and WINR registers (0x5555) + Enable = 0x5555, + /// Reset the watchdog value (0xAAAA) + Reset = 0xaaaa, + /// Start the watchdog (0xCCCC) + Start = 0xcccc, _, }; - pub const PLLM = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, + pub const PR = enum(u3) { + /// Divider /4 + DivideBy4 = 0x0, + /// Divider /8 + DivideBy8 = 0x1, + /// Divider /16 + DivideBy16 = 0x2, + /// Divider /32 + DivideBy32 = 0x3, + /// Divider /64 + DivideBy64 = 0x4, + /// Divider /128 + DivideBy128 = 0x5, + /// Divider /256 + DivideBy256 = 0x6, + /// Divider /256 + DivideBy256bis = 0x7, }; - pub const PLLN = enum(u7) { - Mul8 = 0x8, - Mul9 = 0x9, - Mul10 = 0xa, - Mul11 = 0xb, - Mul12 = 0xc, - Mul13 = 0xd, - Mul14 = 0xe, - Mul15 = 0xf, - Mul16 = 0x10, - Mul17 = 0x11, - Mul18 = 0x12, - Mul19 = 0x13, - Mul20 = 0x14, - Mul21 = 0x15, - Mul22 = 0x16, - Mul23 = 0x17, - Mul24 = 0x18, - Mul25 = 0x19, - Mul26 = 0x1a, - Mul27 = 0x1b, - Mul28 = 0x1c, - Mul29 = 0x1d, - Mul30 = 0x1e, - Mul31 = 0x1f, - Mul32 = 0x20, - Mul33 = 0x21, - Mul34 = 0x22, - Mul35 = 0x23, - Mul36 = 0x24, - Mul37 = 0x25, - Mul38 = 0x26, - Mul39 = 0x27, - Mul40 = 0x28, - Mul41 = 0x29, - Mul42 = 0x2a, - Mul43 = 0x2b, - Mul44 = 0x2c, - Mul45 = 0x2d, - Mul46 = 0x2e, - Mul47 = 0x2f, - Mul48 = 0x30, - Mul49 = 0x31, - Mul50 = 0x32, - Mul51 = 0x33, - Mul52 = 0x34, - Mul53 = 0x35, - Mul54 = 0x36, - Mul55 = 0x37, - Mul56 = 0x38, - Mul57 = 0x39, - Mul58 = 0x3a, - Mul59 = 0x3b, - Mul60 = 0x3c, - Mul61 = 0x3d, - Mul62 = 0x3e, - Mul63 = 0x3f, - Mul64 = 0x40, - Mul65 = 0x41, - Mul66 = 0x42, - Mul67 = 0x43, - Mul68 = 0x44, - Mul69 = 0x45, - Mul70 = 0x46, - Mul71 = 0x47, - Mul72 = 0x48, - Mul73 = 0x49, - Mul74 = 0x4a, - Mul75 = 0x4b, - Mul76 = 0x4c, - Mul77 = 0x4d, - Mul78 = 0x4e, - Mul79 = 0x4f, - Mul80 = 0x50, - Mul81 = 0x51, - Mul82 = 0x52, - Mul83 = 0x53, - Mul84 = 0x54, - Mul85 = 0x55, - Mul86 = 0x56, - _, - }; - - pub const PLLP = enum(u5) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, - Div17 = 0x10, - Div18 = 0x11, - Div19 = 0x12, - Div20 = 0x13, - Div21 = 0x14, - Div22 = 0x15, - Div23 = 0x16, - Div24 = 0x17, - Div25 = 0x18, - Div26 = 0x19, - Div27 = 0x1a, - Div28 = 0x1b, - Div29 = 0x1c, - Div30 = 0x1d, - Div31 = 0x1e, - Div32 = 0x1f, - _, - }; - - pub const PLLQ = enum(u3) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - _, - }; - - pub const PLLR = enum(u3) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - _, - }; - - pub const PLLSRC = enum(u2) { - /// No clock selected as PLL entry clock source - DISABLE = 0x0, - /// HSI selected as PLL entry clock source - HSI = 0x2, - /// HSE selected as PLL entry clock source - HSE = 0x3, - _, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK is divided by 2 - Div2 = 0x4, - /// HCLK is divided by 4 - Div4 = 0x5, - /// HCLK is divided by 8 - Div8 = 0x6, - /// HCLK is divided by 16 - Div16 = 0x7, - _, - }; - - pub const RNGDIV = enum(u2) { - /// RNG clock is not divided - Div1 = 0x0, - /// RNG clock is divided by 2 - Div2 = 0x1, - /// RNG clock is divided by 4 - Div4 = 0x2, - /// RNG clock is divided by 8 - Div8 = 0x3, - }; - - pub const RNGSEL = enum(u2) { - /// No clock used as RNG clock source - DISABLE = 0x0, - /// HSI divided by 8 used as RNG clock source - HSI_DIV_8 = 0x1, - /// SYSCLK used as RNG clock source - SYS = 0x2, - /// PLLQCLK used as RNG clock source - PLL1_Q = 0x3, - }; - - pub const RTCSEL = enum(u2) { - /// No clock used as RTC clock - DISABLE = 0x0, - /// LSE used as RTC clock - LSE = 0x1, - /// LSI used as RTC clock - LSI = 0x2, - /// HSE divided by 32 used as RTC clock - HSE_Div32 = 0x3, + /// Independent watchdog + pub const IWDG = extern struct { + /// Key register + KR: mmio.Mmio(packed struct(u32) { + /// Key value (write only, read 0000h) + KEY: packed union { + raw: u16, + value: KEY, + }, + padding: u16, + }), + /// Prescaler register + PR: mmio.Mmio(packed struct(u32) { + /// Prescaler divider + PR: packed union { + raw: u3, + value: PR, + }, + padding: u29, + }), + /// Reload register + RLR: mmio.Mmio(packed struct(u32) { + /// Watchdog counter reload value + RL: u12, + padding: u20, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Watchdog prescaler value update + PVU: u1, + /// Watchdog counter reload value update + RVU: u1, + /// Watchdog counter window value update + WVU: u1, + padding: u29, + }), + /// Window register + WINR: mmio.Mmio(packed struct(u32) { + /// Watchdog counter window value + WIN: u12, + padding: u20, + }), }; + }; - pub const SW = enum(u3) { - /// HSI selected as system clock - HSI = 0x0, - /// HSE selected as system clock - HSE = 0x1, - /// PLLRCLK selected as system clock - PLL1_R = 0x2, - /// LSI selected as system clock - LSI = 0x3, - /// LSE selected as system clock - LSE = 0x4, + pub const iwdg_v3 = struct { + pub const KEY = enum(u16) { + /// Enable access to PR, RLR and WINR registers (0x5555) + Enable = 0x5555, + /// Reset the watchdog value (0xAAAA) + Reset = 0xaaaa, + /// Start the watchdog (0xCCCC) + Start = 0xcccc, _, }; - pub const TIM15SEL = enum(u1) { - /// TIMPCLK used as TIM15 clock source - PCLK1_TIM = 0x0, - /// PLLQCLK used as TIM15 clock source - PLL1_Q = 0x1, - }; - - pub const TIM1SEL = enum(u1) { - /// TIMPCLK used as TIM1 clock source - PCLK1_TIM = 0x0, - /// PLLQCLK used as TIM1 clock source - PLL1_Q = 0x1, - }; - - pub const USARTSEL = enum(u2) { - /// PCLK used as USART clock source - PCLK1 = 0x0, - /// SYSCLK used as USART clock source - SYS = 0x1, - /// HSI used as USART clock source - HSI = 0x2, - /// LSE used as USART clock source - LSE = 0x3, - }; - - pub const USBSEL = enum(u2) { - /// HSI48 used as USB clock source - HSI48 = 0x0, - /// HSE used as USB clock source - HSE = 0x1, - /// PLLQCLK used as USB clock source - PLL1_Q = 0x2, + pub const PR = enum(u4) { + /// Divider /4 + DivideBy4 = 0x0, + /// Divider /8 + DivideBy8 = 0x1, + /// Divider /16 + DivideBy16 = 0x2, + /// Divider /32 + DivideBy32 = 0x3, + /// Divider /64 + DivideBy64 = 0x4, + /// Divider /128 + DivideBy128 = 0x5, + /// Divider /256 + DivideBy256 = 0x6, + /// Divider /512 + DivideBy512 = 0x7, + /// Divider /1024 + DivideBy1024 = 0x8, _, }; - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// HSI clock enable - HSION: u1, - /// HSI always enable for peripheral kernels - HSIKERON: u1, - /// HSI clock ready flag - HSIRDY: u1, - /// HSI clock division factor - HSIDIV: packed union { - raw: u3, - value: HSIDIV, + /// Independent watchdog + pub const IWDG = extern struct { + /// Key register + KR: mmio.Mmio(packed struct(u32) { + /// Key value (write only, read 0000h) + KEY: packed union { + raw: u16, + value: KEY, }, - reserved16: u2, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE crystal oscillator bypass - HSEBYP: u1, - /// Clock security system enable - CSSON: u1, - reserved22: u2, - /// HSI48ON - HSI48ON: u1, - /// HSI48RDY - HSI48RDY: u1, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding: u6, - }), - /// Internal clock sources calibration register - ICSCR: mmio.Mmio(packed struct(u32) { - /// HSI clock calibration - HSICAL: u8, - /// HSI clock trimming - HSITRIM: u7, - padding: u17, + padding: u16, }), - /// Clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u3, - value: SW, - }, - /// System clock switch status - SWS: packed union { - raw: u3, - value: SW, - }, - reserved8: u2, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// APB prescaler - PPRE: packed union { - raw: u3, - value: PPRE, - }, - reserved16: u1, - /// MCO2SEL - MCO2SEL: packed union { - raw: u4, - value: MCOSEL, - }, - /// MCO2PRE - MCO2PRE: packed union { - raw: u4, - value: MCOPRE, - }, - /// Microcontroller clock output - MCO1SEL: packed union { - raw: u4, - value: MCOSEL, - }, - /// Microcontroller clock output prescaler - MCO1PRE: packed union { + /// Prescaler register + PR: mmio.Mmio(packed struct(u32) { + /// Prescaler divider + PR: packed union { raw: u4, - value: MCOPRE, + value: PR, }, + padding: u28, }), - /// PLL configuration register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// PLL input clock source - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - reserved4: u2, - /// Division factor M of the PLL input clock divider - PLLM: packed union { - raw: u3, - value: PLLM, - }, - reserved8: u1, - /// PLL frequency multiplication factor N - PLLN: packed union { - raw: u7, - value: PLLN, - }, - reserved16: u1, - /// PLLPCLK clock output enable - PLLPEN: u1, - /// PLL VCO division factor P for PLLPCLK clock output - PLLP: packed union { - raw: u5, - value: PLLP, - }, - reserved24: u2, - /// PLLQCLK clock output enable - PLLQEN: u1, - /// PLL VCO division factor Q for PLLQCLK clock output - PLLQ: packed union { - raw: u3, - value: PLLQ, - }, - /// PLLRCLK clock output enable - PLLREN: u1, - /// PLL VCO division factor R for PLLRCLK clock output - PLLR: packed union { - raw: u3, - value: PLLR, - }, + /// Reload register + RLR: mmio.Mmio(packed struct(u32) { + /// Watchdog counter reload value + RL: u12, + padding: u20, }), - reserved20: [4]u8, - /// RCC clock recovery RC register - CRRCR: mmio.Mmio(packed struct(u32) { - /// HSI48 clock calibration - HSI48CAL: u9, - padding: u23, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Watchdog prescaler value update + PVU: u1, + /// Watchdog counter reload value update + RVU: u1, + /// Watchdog counter window value update + WVU: u1, + /// Watchdog interrupt comparator value update This bit is set by hardware to indicate that an update of the interrupt comparator value (EWIT[11:0]) or an update of the EWIE is ongoing. It is reset by hardware when the update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The EWIT[11:0] and EWIE fields can be updated only when EWU bit is reset. + EWU: u1, + reserved14: u10, + /// Watchdog early interrupt flag This bit is set to ‘1’ by hardware in order to indicate that an early interrupt is pending. This bit must be cleared by the software by writing the bit EWIC of IWDG_EWCR register to ‘1’. + EWIF: u1, + padding: u17, }), - /// Clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - reserved3: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// PLL ready interrupt enable - PLLSYSRDYIE: u1, - padding: u26, + /// Window register + WINR: mmio.Mmio(packed struct(u32) { + /// Watchdog counter window value + WIN: u12, + padding: u20, }), - /// Clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// HSI48RDYF - HSI48RDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// PLL ready interrupt flag - PLLSYSRDYF: u1, - reserved8: u2, - /// Clock security system interrupt flag - CSSF: u1, - /// LSE Clock security system interrupt flag - LSECSSF: u1, - padding: u22, + /// IWDG early wakeup interrupt register. + EWCR: mmio.Mmio(packed struct(u32) { + /// Watchdog counter window value These bits are write access protected (see ). They are written by software to define at which position of the IWDCNT down-counter the early wakeup interrupt must be generated. The early interrupt is generated when the IWDCNT is lower or equal to EWIT[11:0] - 1. EWIT[11:0] must be bigger than 1. An interrupt is generated only if EWIE = 1. The EWU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the Early wakeup comparator value and the Interrupt enable bit from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the EWU bit in the is reset. + EWIT: u12, + reserved14: u2, + /// Watchdog early interrupt acknowledge The software must write a 1 into this bit in order to acknowledge the early wakeup interrupt and to clear the EWIF flag. Writing 0 has not effect, reading this flag returns a 0. + EWIC: u1, + /// Watchdog early interrupt enable Set and reset by software. The EWU bit in the must be reset to be able to change the value of this bit. + EWIE: u1, + padding: u16, }), - /// Clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// HSI48RDYC - HSI48RDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// PLL ready interrupt clear - PLLSYSRDYC: u1, - reserved8: u2, - /// Clock security system interrupt clear - CSSC: u1, - /// LSE Clock security system interrupt clear - LSECSSC: u1, - padding: u22, + }; + }; + + pub const jpeg_v1 = struct { + /// JPEG codec + pub const JPEG = extern struct { + /// JPEG codec configuration register 0 + JPEG_CONFR0: mmio.Mmio(packed struct(u32) { + /// Start + START: u1, + padding: u31, }), - /// GPIO reset register - GPIORSTR: mmio.Mmio(packed struct(u32) { - /// I/O port A reset - GPIOARST: u1, - /// I/O port B reset - GPIOBRST: u1, - /// I/O port C reset - GPIOCRST: u1, - /// I/O port D reset - GPIODRST: u1, - reserved5: u1, - /// I/O port F reset - GPIOFRST: u1, - padding: u26, + /// JPEG codec configuration register 1 + JPEG_CONFR1: mmio.Mmio(packed struct(u32) { + /// Number of color components + NF: u2, + reserved3: u1, + /// Decoding Enable + DE: u1, + /// Color Space + COLORSPACE: u2, + /// Number of components for Scan + NS: u2, + /// Header Processing + HDR: u1, + reserved16: u7, + /// Y Size + YSIZE: u16, }), - /// AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 reset - DMA1RST: u1, - /// DMA1 reset - DMA2RST: u1, - reserved8: u6, - /// FLASH reset - FLASHRST: u1, - reserved12: u3, - /// CRC reset - CRCRST: u1, - reserved16: u3, - /// AES hardware accelerator reset - AESRST: u1, - reserved18: u1, - /// Random number generator reset - RNGRST: u1, - padding: u13, + /// JPEG codec configuration register 2 + JPEG_CONFR2: mmio.Mmio(packed struct(u32) { + /// Number of MCU + NMCU: u26, + padding: u6, }), - /// APB peripheral reset register 1 - APBRSTR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer reset - TIM2RST: u1, - /// TIM3 timer reset - TIM3RST: u1, - /// TIM4 timer reset - TIM4RST: u1, - reserved4: u1, - /// TIM6 timer reset - TIM6RST: u1, - /// TIM7 timer reset - TIM7RST: u1, - reserved7: u1, - /// LPUART2RST - LPUART2RST: u1, - /// USART5RST - USART5RST: u1, - /// USART6RST - USART6RST: u1, - reserved12: u2, - /// FDCANRST - FDCANRST: u1, - /// USBRST - USBRST: u1, - /// SPI2 reset - SPI2RST: u1, - /// SPI3 reset - SPI3RST: u1, - /// CRSRST - CRSRST: u1, - /// USART2 reset - USART2RST: u1, - /// USART3 reset - USART3RST: u1, - /// USART4 reset - USART4RST: u1, - /// LPUART1 reset - LPUART1RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// I2C3RST reset - I2C3RST: u1, - /// HDMI CEC reset - CECRST: u1, - /// UCPD1 reset - UCPD1RST: u1, - /// UCPD2 reset - UCPD2RST: u1, - /// Debug support reset - DBGRST: u1, - /// Power interface reset - PWRRST: u1, - /// DAC1 interface reset - DAC1RST: u1, - /// Low Power Timer 2 reset - LPTIM2RST: u1, - /// Low Power Timer 1 reset - LPTIM1RST: u1, + /// JPEG codec configuration register 3 + JPEG_CONFR3: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// X size + XSIZE: u16, }), - /// APB peripheral reset register 2 - APBRSTR2: mmio.Mmio(packed struct(u32) { - /// SYSCFG, COMP and VREFBUF reset - SYSCFGRST: u1, - reserved11: u10, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI1 reset - SPI1RST: u1, - reserved14: u1, - /// USART1 reset - USART1RST: u1, - /// TIM14 timer reset - TIM14RST: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - reserved20: u1, - /// ADC reset - ADCRST: u1, - padding: u11, + /// JPEG codec configuration register 4 + JPEG_CONFR4: mmio.Mmio(packed struct(u32) { + /// Huffman DC + HD: u1, + /// Huffman AC + HA: u1, + /// Quantization Table + QT: u2, + /// Number of Block + NB: u4, + /// Vertical Sampling Factor + VSF: u4, + /// Horizontal Sampling Factor + HSF: u4, + padding: u16, }), - /// GPIO clock enable register - GPIOENR: mmio.Mmio(packed struct(u32) { - /// I/O port A clock enable - GPIOAEN: u1, - /// I/O port B clock enable - GPIOBEN: u1, - /// I/O port C clock enable - GPIOCEN: u1, - /// I/O port D clock enable - GPIODEN: u1, - reserved5: u1, - /// I/O port F clock enable - GPIOFEN: u1, - padding: u26, + /// JPEG codec configuration register 5 + JPEG_CONFR5: mmio.Mmio(packed struct(u32) { + /// Huffman DC + HD: u1, + /// Huffman AC + HA: u1, + /// Quantization Table + QT: u2, + /// Number of Block + NB: u4, + /// Vertical Sampling Factor + VSF: u4, + /// Horizontal Sampling Factor + HSF: u4, + padding: u16, }), - /// AHB peripheral clock enable register - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - reserved8: u6, - /// Flash memory interface clock enable - FLASHEN: u1, - reserved12: u3, - /// CRC clock enable - CRCEN: u1, - reserved16: u3, - /// AES hardware accelerator - AESEN: u1, - reserved18: u1, - /// Random number generator clock enable - RNGEN: u1, - padding: u13, + /// JPEG codec configuration register 6 + JPEG_CONFR6: mmio.Mmio(packed struct(u32) { + /// Huffman DC + HD: u1, + /// Huffman AC + HA: u1, + /// Quantization Table + QT: u2, + /// Number of Block + NB: u4, + /// Vertical Sampling Factor + VSF: u4, + /// Horizontal Sampling Factor + HSF: u4, + padding: u16, }), - /// APB peripheral clock enable register 1 - APBENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clock enable - TIM2EN: u1, - /// TIM3 timer clock enable - TIM3EN: u1, - /// TIM4 timer clock enable - TIM4EN: u1, - reserved4: u1, - /// TIM6 timer clock enable - TIM6EN: u1, - /// TIM7 timer clock enable - TIM7EN: u1, - reserved7: u1, - /// LPUART2 clock enable - LPUART2EN: u1, - /// USART5EN - USART5EN: u1, - /// USART6EN - USART6EN: u1, - /// RTC APB clock enable - RTCAPBEN: u1, - /// WWDG clock enable - WWDGEN: u1, - /// USBEN - FDCANEN: u1, - /// USBEN - USBEN: u1, - /// SPI2 clock enable - SPI2EN: u1, - /// SPI3 clock enable - SPI3EN: u1, - /// CRSEN - CRSEN: u1, - /// USART2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// USART4 clock enable - USART4EN: u1, - /// LPUART1 clock enable - LPUART1EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - /// I2C2 clock enable - I2C2EN: u1, - /// I2C3 clock enable - I2C3EN: u1, - /// HDMI CEC clock enable - CECEN: u1, - /// UCPD1 clock enable - UCPD1EN: u1, - /// UCPD2 clock enable - UCPD2EN: u1, - /// Debug support clock enable - DBGEN: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC1 interface clock enable - DAC1EN: u1, - /// LPTIM2 clock enable - LPTIM2EN: u1, - /// LPTIM1 clock enable - LPTIM1EN: u1, + /// JPEG codec configuration register 7 + JPEG_CONFR7: mmio.Mmio(packed struct(u32) { + /// Huffman DC + HD: u1, + /// Huffman AC + HA: u1, + /// Quantization Table + QT: u2, + /// Number of Block + NB: u4, + /// Vertical Sampling Factor + VSF: u4, + /// Horizontal Sampling Factor + HSF: u4, + padding: u16, }), - /// APB peripheral clock enable register 2 - APBENR2: mmio.Mmio(packed struct(u32) { - /// SYSCFG, COMP and VREFBUF clock enable - SYSCFGEN: u1, - reserved11: u10, - /// TIM1 timer clock enable - TIM1EN: u1, - /// SPI1 clock enable - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable - USART1EN: u1, - /// TIM14 timer clock enable - TIM14EN: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM16 timer clock enable - TIM17EN: u1, - reserved20: u1, - /// ADC clock enable - ADCEN: u1, - padding: u11, + reserved48: [16]u8, + /// JPEG control register + JPEG_CR: mmio.Mmio(packed struct(u32) { + /// JPEG Core Enable + JCEN: u1, + /// Input FIFO Threshold Interrupt Enable + IFTIE: u1, + /// Input FIFO Not Full Interrupt Enable + IFNFIE: u1, + /// Output FIFO Threshold Interrupt Enable + OFTIE: u1, + /// Output FIFO Not Empty Interrupt Enable + OFNEIE: u1, + /// End of Conversion Interrupt Enable + EOCIE: u1, + /// Header Parsing Done Interrupt Enable + HPDIE: u1, + reserved11: u4, + /// Input DMA Enable + IDMAEN: u1, + /// Output DMA Enable + ODMAEN: u1, + /// Input FIFO Flush + IFF: u1, + /// Output FIFO Flush + OFF: u1, + padding: u17, }), - /// GPIO in Sleep mode clock enable register - GPIOSMENR: mmio.Mmio(packed struct(u32) { - /// I/O port A clock enable during Sleep mode - GPIOASMEN: u1, - /// I/O port B clock enable during Sleep mode - GPIOBSMEN: u1, - /// I/O port C clock enable during Sleep mode - GPIOCSMEN: u1, - /// I/O port D clock enable during Sleep mode - GPIODSMEN: u1, - reserved5: u1, - /// I/O port F clock enable during Sleep mode - GPIOFSMEN: u1, - padding: u26, + /// JPEG status register + JPEG_SR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Input FIFO Threshold Flag + IFTF: u1, + /// Input FIFO Not Full Flag + IFNFF: u1, + /// Output FIFO Threshold Flag + OFTF: u1, + /// Output FIFO Not Empty Flag + OFNEF: u1, + /// End of Conversion Flag + EOCF: u1, + /// Header Parsing Done Flag + HPDF: u1, + /// Codec Operation Flag + COF: u1, + padding: u24, }), - /// AHB peripheral clock enable in Sleep mode register - AHBSMENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable during Sleep mode - DMA1SMEN: u1, - /// DMA2 clock enable during Sleep mode - DMA2SMEN: u1, - reserved8: u6, - /// Flash memory interface clock enable during Sleep mode - FLASHSMEN: u1, - /// SRAM clock enable during Sleep mode - SRAMSMEN: u1, - reserved12: u2, - /// CRC clock enable during Sleep mode - CRCSMEN: u1, - reserved16: u3, - /// AES hardware accelerator clock enable during Sleep mode - AESSMEN: u1, - reserved18: u1, - /// Random number generator clock enable during Sleep mode - RNGSMEN: u1, - padding: u13, + /// JPEG clear flag register + JPEG_CFR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Clear End of Conversion Flag + CEOCF: u1, + /// Clear Header Parsing Done Flag + CHPDF: u1, + padding: u25, }), - /// APB peripheral clock enable in Sleep mode register 1 - APBSMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clock enable during Sleep mode - TIM2SMEN: u1, - /// TIM3 timer clock enable during Sleep mode - TIM3SMEN: u1, - /// TIM4 timer clock enable during Sleep mode - TIM4SMEN: u1, - reserved4: u1, - /// TIM6 timer clock enable during Sleep mode - TIM6SMEN: u1, - /// TIM7 timer clock enable during Sleep mode - TIM7SMEN: u1, - reserved7: u1, - /// LPUART2 clock enable - LPUART2SMEN: u1, - /// USART5 clock enable - USART5SMEN: u1, - /// USART6 clock enable - USART6SMEN: u1, - /// RTC APB clock enable during Sleep mode - RTCAPBSMEN: u1, - /// WWDG clock enable during Sleep mode - WWDGSMEN: u1, - /// FDCAN clock enable during Sleep mode - FDCANSMEN: u1, - /// USB clock enable during Sleep mode - USBSMEN: u1, - /// SPI2 clock enable during Sleep mode - SPI2SMEN: u1, - /// SPI3 clock enable during Sleep mode - SPI3SMEN: u1, - /// CRSS clock enable during Sleep mode - CRSSSMEN: u1, - /// USART2 clock enable during Sleep mode - USART2SMEN: u1, - /// USART3 clock enable during Sleep mode - USART3SMEN: u1, - /// USART4 clock enable during Sleep mode - USART4SMEN: u1, - /// LPUART1 clock enable during Sleep mode - LPUART1SMEN: u1, - /// I2C1 clock enable during Sleep mode - I2C1SMEN: u1, - /// I2C2 clock enable during Sleep mode - I2C2SMEN: u1, - /// I2C3 clock enable during Sleep mode - I2C3SMEN: u1, - /// HDMI CEC clock enable during Sleep mode - CECSMEN: u1, - /// UCPD1 clock enable during Sleep mode - UCPD1SMEN: u1, - /// UCPD2 clock enable during Sleep mode - UCPD2SMEN: u1, - /// Debug support clock enable during Sleep mode - DBGSMEN: u1, - /// Power interface clock enable during Sleep mode - PWRSMEN: u1, - /// DAC1 interface clock enable during Sleep mode - DAC1SMEN: u1, - /// Low Power Timer 2 clock enable during Sleep mode - LPTIM2SMEN: u1, - /// Low Power Timer 1 clock enable during Sleep mode - LPTIM1SMEN: u1, + reserved64: [4]u8, + /// JPEG data input register + JPEG_DIR: mmio.Mmio(packed struct(u32) { + /// Data Input FIFO + DATAIN: u32, }), - /// APB peripheral clock enable in Sleep mode register 2 - APBSMENR2: mmio.Mmio(packed struct(u32) { - /// SYSCFG, COMP and VREFBUF clock enable during Sleep mode - SYSCFGSMEN: u1, - reserved11: u10, - /// TIM1 timer clock enable during Sleep mode - TIM1SMEN: u1, - /// SPI1 clock enable during Sleep mode - SPI1SMEN: u1, - reserved14: u1, - /// USART1 clock enable during Sleep mode - USART1SMEN: u1, - /// TIM14 timer clock enable during Sleep mode - TIM14SMEN: u1, - /// TIM15 timer clock enable during Sleep mode - TIM15SMEN: u1, - /// TIM16 timer clock enable during Sleep mode - TIM16SMEN: u1, - /// TIM16 timer clock enable during Sleep mode - TIM17SMEN: u1, - reserved20: u1, - /// ADC clock enable during Sleep mode - ADCSMEN: u1, - padding: u11, + /// JPEG data output register + JPEG_DOR: mmio.Mmio(packed struct(u32) { + /// Data Output FIFO + DATAOUT: u32, }), - /// Peripherals independent clock configuration register - CCIPR: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// USART2 clock source selection - USART2SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// USART3 clock source selection - USART3SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// HDMI CEC clock source selection - CECSEL: packed union { - raw: u1, - value: CECSEL, - }, - reserved8: u1, - /// LPUART2 clock source selection - LPUART2SEL: packed union { - raw: u2, - value: LPUART2SEL, - }, - /// LPUART1 clock source selection - LPUART1SEL: packed union { - raw: u2, - value: LPUART1SEL, - }, - /// I2C1 clock source selection - I2C1SEL: packed union { - raw: u2, - value: I2C1SEL, - }, - /// I2C2 or I2S1 clock source selection - I2C2I2S1SEL: packed union { - raw: u2, - value: I2C2I2S1SEL, - }, - reserved18: u2, - /// LPTIM1 clock source selection - LPTIM1SEL: packed union { - raw: u2, - value: LPTIM1SEL, - }, - /// LPTIM2 clock source selection - LPTIM2SEL: packed union { - raw: u2, - value: LPTIM2SEL, - }, - /// TIM1 clock source selection - TIM1SEL: packed union { - raw: u1, - value: TIM1SEL, - }, - reserved24: u1, - /// TIM15 clock source selection - TIM15SEL: packed union { - raw: u1, - value: TIM15SEL, - }, - reserved26: u1, - /// RNG clock source selection - RNGSEL: packed union { - raw: u2, - value: RNGSEL, - }, - /// Division factor of RNG clock divider - RNGDIV: packed union { - raw: u2, - value: RNGDIV, - }, - /// ADCs clock source selection - ADCSEL: packed union { - raw: u2, - value: ADCSEL, - }, + reserved80: [8]u8, + /// JPEG quantization tables + QMEM0_0: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Peripherals independent clock configuration register 2 - CCIPR2: mmio.Mmio(packed struct(u32) { - /// I2S1SEL - I2S1SEL: packed union { - raw: u2, - value: I2S1SEL, - }, - /// I2S2SEL - I2S2SEL: packed union { - raw: u2, - value: I2S2SEL, - }, - reserved8: u4, - /// FDCANSEL - FDCANSEL: packed union { - raw: u2, - value: FDCANSEL, - }, - reserved12: u2, - /// USBSEL - USBSEL: packed union { - raw: u2, - value: USBSEL, - }, - padding: u18, + /// JPEG quantization tables + QMEM0_1: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// RTC domain control register - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enable - LSEON: u1, - /// LSE oscillator ready - LSERDY: u1, - /// LSE oscillator bypass - LSEBYP: u1, - /// LSE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// CSS on LSE enable - LSECSSON: u1, - /// CSS on LSE failure Detection - LSECSSD: u1, - reserved8: u1, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// RTC domain software reset - BDRST: u1, - reserved24: u7, - /// Low-speed clock output (LSCO) enable - LSCOEN: u1, - /// Low-speed clock output selection - LSCOSEL: u1, - padding: u6, + /// JPEG quantization tables + QMEM0_2: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Control/status register - CSR: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable - LSION: u1, - /// LSI oscillator ready - LSIRDY: u1, - reserved23: u21, - /// Remove reset flags - RMVF: u1, - reserved25: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// Pin reset flag - PINRSTF: u1, - /// BOR or POR/PDR flag - PWRRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent window watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// JPEG quantization tables + QMEM0_3: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - }; - }; - - pub const rcc_f0v4 = struct { - pub const CECSW = enum(u1) { - /// HSI clock divided by 244 selected as CEC clock source - HSI_DIV_244 = 0x0, - /// LSE clock selected as CEC clock source - LSE = 0x1, - }; - - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, - _, - }; - - pub const ICSW = enum(u1) { - /// HSI clock selected as I2C clock source - HSI = 0x0, - /// SYSCLK clock selected as I2C clock source - SYS = 0x1, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium high driving capability - MediumHigh = 0x1, - /// Medium low driving capability - MediumLow = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCOPRE = enum(u3) { - /// MCO is divided by 1 - Div1 = 0x0, - /// MCO is divided by 2 - Div2 = 0x1, - /// MCO is divided by 4 - Div4 = 0x2, - /// MCO is divided by 8 - Div8 = 0x3, - /// MCO is divided by 16 - Div16 = 0x4, - /// MCO is divided by 32 - Div32 = 0x5, - /// MCO is divided by 64 - Div64 = 0x6, - /// MCO is divided by 128 - Div128 = 0x7, - }; - - pub const MCOSEL = enum(u4) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// Internal RC 14 MHz (HSI14) oscillator clock selected - HSI14 = 0x1, - /// Internal low speed (LSI) oscillator clock selected - LSI = 0x2, - /// External low speed (LSE) oscillator clock selected - LSE = 0x3, - /// System clock selected - SYS = 0x4, - /// Internal RC 8 MHz (HSI) oscillator clock selected - HSI = 0x5, - /// External 4-32 MHz (HSE) oscillator clock selected - HSE = 0x6, - /// PLL clock selected (divided by 1 or 2, depending en PLLMCODIV) - PLL = 0x7, - /// Internal RC 48 MHz (HSI48) oscillator clock selected - HSI48 = 0x8, - _, - }; - - pub const PLLMCODIV = enum(u1) { - /// PLL is divided by 2 for MCO - Div2 = 0x0, - /// PLL is not divided for MCO - Div1 = 0x1, - }; - - pub const PLLMUL = enum(u4) { - /// PLL input clock x2 - Mul2 = 0x0, - /// PLL input clock x3 - Mul3 = 0x1, - /// PLL input clock x4 - Mul4 = 0x2, - /// PLL input clock x5 - Mul5 = 0x3, - /// PLL input clock x6 - Mul6 = 0x4, - /// PLL input clock x7 - Mul7 = 0x5, - /// PLL input clock x8 - Mul8 = 0x6, - /// PLL input clock x9 - Mul9 = 0x7, - /// PLL input clock x10 - Mul10 = 0x8, - /// PLL input clock x11 - Mul11 = 0x9, - /// PLL input clock x12 - Mul12 = 0xa, - /// PLL input clock x13 - Mul13 = 0xb, - /// PLL input clock x14 - Mul14 = 0xc, - /// PLL input clock x15 - Mul15 = 0xd, - /// PLL input clock x16 - Mul16 = 0xe, - _, - }; - - pub const PLLSRC = enum(u2) { - /// HSI divided by 2 selected as PLL input clock - HSI_Div2 = 0x0, - /// HSI divided by PREDIV selected as PLL input clock - HSI_Div_PREDIV = 0x1, - /// HSE divided by PREDIV selected as PLL input clock - HSE_Div_PREDIV = 0x2, - /// HSI48 divided by PREDIV selected as PLL input clock - HSI48_Div_PREDIV = 0x3, - }; - - pub const PLLXTPRE = enum(u1) { - /// HSE clock not divided - Div1 = 0x0, - /// HSE clock divided by 2 - Div2 = 0x1, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const PREDIV = enum(u4) { - /// PREDIV input clock not divided - Div1 = 0x0, - /// PREDIV input clock divided by 2 - Div2 = 0x1, - /// PREDIV input clock divided by 3 - Div3 = 0x2, - /// PREDIV input clock divided by 4 - Div4 = 0x3, - /// PREDIV input clock divided by 5 - Div5 = 0x4, - /// PREDIV input clock divided by 6 - Div6 = 0x5, - /// PREDIV input clock divided by 7 - Div7 = 0x6, - /// PREDIV input clock divided by 8 - Div8 = 0x7, - /// PREDIV input clock divided by 9 - Div9 = 0x8, - /// PREDIV input clock divided by 10 - Div10 = 0x9, - /// PREDIV input clock divided by 11 - Div11 = 0xa, - /// PREDIV input clock divided by 12 - Div12 = 0xb, - /// PREDIV input clock divided by 13 - Div13 = 0xc, - /// PREDIV input clock divided by 14 - Div14 = 0xd, - /// PREDIV input clock divided by 15 - Div15 = 0xe, - /// PREDIV input clock divided by 16 - Div16 = 0xf, - }; - - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, - }; - - pub const SW = enum(u2) { - /// HSI oscillator used as system clock - HSI = 0x0, - /// HSE oscillator used as system clock - HSE = 0x1, - /// PLL used as system clock - PLL1_P = 0x2, - /// HSI48 used as system clock - HSI48 = 0x3, - }; - - pub const USART1SW = enum(u2) { - /// PCLK selected as USART clock source - PCLK2 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, - }; - - pub const USARTSW = enum(u2) { - /// PCLK selected as USART clock source - PCLK1 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, - }; - - pub const USBSW = enum(u1) { - /// HSI48 selected as USB clock source - HSI48 = 0x0, - /// PLL clock selected as USB clock source - PLL1_P = 0x1, - }; - - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal High Speed clock enable - HSION: u1, - /// Internal High Speed clock ready flag - HSIRDY: u1, - reserved3: u1, - /// Internal High Speed clock trimming - HSITRIM: u5, - /// Internal High Speed clock Calibration - HSICAL: u8, - /// External High Speed clock enable - HSEON: u1, - /// External High Speed clock ready flag - HSERDY: u1, - /// External High Speed clock Bypass - HSEBYP: u1, - /// Clock Security System enable - CSSON: u1, - reserved24: u4, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding: u6, + /// JPEG quantization tables + QMEM0_4: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Clock configuration register (RCC_CFGR) - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock Switch - SW: packed union { - raw: u2, - value: SW, - }, - /// System Clock Switch Status - SWS: packed union { - raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// APB Low speed prescaler (APB1) - PPRE: packed union { - raw: u3, - value: PPRE, - }, - reserved14: u3, - /// APCPRE is deprecated. See ADC field in CFGR2 register. - ADCPRE: u1, - /// PLL input clock source - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - /// HSE divider for PLL entry. Same bit as PREDIV[0] from CFGR2 register. Refer to it for its meaning - PLLXTPRE: packed union { - raw: u1, - value: PLLXTPRE, - }, - /// PLL Multiplication Factor - PLLMUL: packed union { - raw: u4, - value: PLLMUL, - }, - reserved24: u2, - /// Microcontroller clock output - MCOSEL: packed union { - raw: u4, - value: MCOSEL, - }, - /// Microcontroller Clock Output Prescaler - MCOPRE: packed union { - raw: u3, - value: MCOPRE, - }, - /// PLL clock not divided for MCO - PLLMCODIV: packed union { - raw: u1, - value: PLLMCODIV, - }, + /// JPEG quantization tables + QMEM0_5: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Clock interrupt register (RCC_CIR) - CIR: mmio.Mmio(packed struct(u32) { - /// LSI Ready Interrupt flag - LSIRDYF: u1, - /// LSE Ready Interrupt flag - LSERDYF: u1, - /// HSI Ready Interrupt flag - HSIRDYF: u1, - /// HSE Ready Interrupt flag - HSERDYF: u1, - /// PLL Ready Interrupt flag - PLLRDYF: u1, - /// HSI14 ready interrupt flag - HSI14RDYF: u1, - /// HSI48 ready interrupt flag - HSI48RDYF: u1, - /// Clock Security System Interrupt flag - CSSF: u1, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1, - /// LSE Ready Interrupt Enable - LSERDYIE: u1, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1, - /// HSE Ready Interrupt Enable - HSERDYIE: u1, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1, - /// HSI14 ready interrupt enable - HSI14RDYIE: u1, - /// HSI48 ready interrupt enable - HSI48RDYIE: u1, - reserved16: u1, - /// LSI Ready Interrupt Clear - LSIRDYC: u1, - /// LSE Ready Interrupt Clear - LSERDYC: u1, - /// HSI Ready Interrupt Clear - HSIRDYC: u1, - /// HSE Ready Interrupt Clear - HSERDYC: u1, - /// PLL Ready Interrupt Clear - PLLRDYC: u1, - /// HSI 14 MHz Ready Interrupt Clear - HSI14RDYC: u1, - /// HSI48 Ready Interrupt Clear - HSI48RDYC: u1, - /// Clock security system interrupt clear - CSSC: u1, - padding: u8, + /// JPEG quantization tables + QMEM0_6: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// APB2 peripheral reset register (RCC_APB2RSTR) - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// SYSCFG and COMP reset - SYSCFGRST: u1, - reserved5: u4, - /// USART6 reset - USART6RST: u1, - /// USART7 reset - USART7RST: u1, - /// USART8 reset - USART8RST: u1, - reserved9: u1, - /// ADC interface reset - ADCRST: u1, - reserved11: u1, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI 1 reset - SPI1RST: u1, - reserved14: u1, - /// USART1 reset - USART1RST: u1, - reserved16: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - reserved22: u3, - /// Debug MCU reset - DBGMCURST: u1, - padding: u9, + /// JPEG quantization tables + QMEM0_7: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// APB1 peripheral reset register (RCC_APB1RSTR) - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - reserved4: u2, - /// Timer 6 reset - TIM6RST: u1, - /// TIM7 timer reset - TIM7RST: u1, - reserved8: u2, - /// Timer 14 reset - TIM14RST: u1, - reserved11: u2, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI2 reset - SPI2RST: u1, - reserved17: u2, - /// USART 2 reset - USART2RST: u1, - /// USART3 reset - USART3RST: u1, - /// USART4 reset - USART4RST: u1, - /// USART5 reset - USART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// USB interface reset - USBRST: u1, - reserved25: u1, - /// CAN interface reset - CANRST: u1, - reserved27: u1, - /// Clock Recovery System interface reset - CRSRST: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - /// HDMI CEC reset - CECRST: u1, - padding: u1, + /// JPEG quantization tables + QMEM0_8: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// AHB Peripheral Clock enable register (RCC_AHBENR) - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA clock enable - DMAEN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// SRAM interface clock enable - SRAMEN: u1, - reserved4: u1, - /// FLASH clock enable - FLASHEN: u1, - reserved6: u1, - /// CRC clock enable - CRCEN: u1, - reserved17: u10, - /// I/O port A clock enable - GPIOAEN: u1, - /// I/O port B clock enable - GPIOBEN: u1, - /// I/O port C clock enable - GPIOCEN: u1, - /// I/O port D clock enable - GPIODEN: u1, - /// I/O port E clock enable - GPIOEEN: u1, - /// I/O port F clock enable - GPIOFEN: u1, - reserved24: u1, - /// Touch sensing controller clock enable - TSCEN: u1, - padding: u7, + /// JPEG quantization tables + QMEM0_9: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// APB2 peripheral clock enable register (RCC_APB2ENR) - APB2ENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved5: u4, - /// USART6 clock enable - USART6EN: u1, - /// USART7 clock enable - USART7EN: u1, - /// USART8 clock enable - USART8EN: u1, - reserved9: u1, - /// ADC 1 interface clock enable - ADCEN: u1, - reserved11: u1, - /// TIM1 Timer clock enable - TIM1EN: u1, - /// SPI 1 clock enable - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable - USART1EN: u1, - reserved16: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - reserved22: u3, - /// MCU debug module clock enable - DBGMCUEN: u1, - padding: u9, + /// JPEG quantization tables + QMEM0_10: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// APB1 peripheral clock enable register (RCC_APB1ENR) - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer 2 clock enable - TIM2EN: u1, - /// Timer 3 clock enable - TIM3EN: u1, - reserved4: u2, - /// Timer 6 clock enable - TIM6EN: u1, - /// TIM7 timer clock enable - TIM7EN: u1, - reserved8: u2, - /// Timer 14 clock enable - TIM14EN: u1, - reserved11: u2, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI 2 clock enable - SPI2EN: u1, - reserved17: u2, - /// USART 2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// USART4 clock enable - USART4EN: u1, - /// USART5 clock enable - USART5EN: u1, - /// I2C 1 clock enable - I2C1EN: u1, - /// I2C 2 clock enable - I2C2EN: u1, - /// USB interface clock enable - USBEN: u1, - reserved25: u1, - /// CAN interface clock enable - CANEN: u1, - reserved27: u1, - /// Clock Recovery System interface clock enable - CRSEN: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - /// HDMI CEC interface clock enable - CECEN: u1, - padding: u1, + /// JPEG quantization tables + QMEM0_11: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Backup domain control register (RCC_BDCR) - BDCR: mmio.Mmio(packed struct(u32) { - /// External Low Speed oscillator enable - LSEON: u1, - /// External Low Speed oscillator ready - LSERDY: u1, - /// External Low Speed oscillator bypass - LSEBYP: u1, - /// LSE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - reserved8: u3, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - padding: u15, + /// JPEG quantization tables + QMEM0_12: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Control/status register (RCC_CSR) - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low speed oscillator enable - LSION: u1, - /// Internal low speed oscillator ready - LSIRDY: u1, - reserved23: u21, - /// 1.8 V domain reset flag - V18PWRRSTF: u1, - /// Remove reset flag - RMVF: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// JPEG quantization tables + QMEM0_13: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - reserved17: u17, - /// I/O port A reset - GPIOARST: u1, - /// I/O port B reset - GPIOBRST: u1, - /// I/O port C reset - GPIOCRST: u1, - /// I/O port D reset - GPIODRST: u1, - /// I/O port E reset - GPIOERST: u1, - /// I/O port F reset - GPIOFRST: u1, - reserved24: u1, - /// Touch sensing controller reset - TSCRST: u1, - padding: u7, + /// JPEG quantization tables + QMEM0_14: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// PREDIV division factor - PREDIV: packed union { - raw: u4, - value: PREDIV, - }, - padding: u28, + /// JPEG quantization tables + QMEM0_15: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Clock configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SW: packed union { - raw: u2, - value: USART1SW, - }, - reserved4: u2, - /// I2C1 clock source selection - I2C1SW: packed union { - raw: u1, - value: ICSW, - }, - reserved6: u1, - /// HDMI CEC clock source selection - CECSW: packed union { - raw: u1, - value: CECSW, - }, - /// USB clock source selection - USBSW: packed union { - raw: u1, - value: USBSW, - }, - /// ADCSW is deprecated. See ADC field in CFGR2 register. - ADCSW: u1, - reserved16: u7, - /// USART2 clock source selection - USART2SW: packed union { - raw: u2, - value: USARTSW, - }, - /// USART3 clock source - USART3SW: packed union { - raw: u2, - value: USARTSW, - }, - padding: u12, + /// JPEG quantization tables + QMEM1_0: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Clock control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// HSI14 clock enable - HSI14ON: u1, - /// HR14 clock ready flag - HSI14RDY: u1, - /// HSI14 clock request from ADC disable - HSI14DIS: u1, - /// HSI14 clock trimming - HSI14TRIM: u5, - /// HSI14 clock calibration - HSI14CAL: u8, - /// HSI48 clock enable - HSI48ON: u1, - /// HSI48 clock ready flag - HSI48RDY: u1, - reserved24: u6, - /// HSI48 factory clock calibration - HSI48CAL: u8, + /// JPEG quantization tables + QMEM1_1: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - }; - }; - - pub const pwr_f1 = struct { - pub const PDDS = enum(u1) { - /// Enter Stop mode when the CPU enters deepsleep - STOP_MODE = 0x0, - /// Enter Standby mode when the CPU enters deepsleep - STANDBY_MODE = 0x1, - }; - - /// Power control - pub const PWR = extern struct { - /// Power control register (PWR_CR) - CR: mmio.Mmio(packed struct(u32) { - /// Low Power Deep Sleep - LPDS: u1, - /// Power Down Deep Sleep - PDDS: packed union { - raw: u1, - value: PDDS, - }, - /// Clear Wake-up Flag - CWUF: u1, - /// Clear STANDBY Flag - CSBF: u1, - /// Power Voltage Detector Enable - PVDE: u1, - /// PVD Level Selection - PLS: u3, - /// Disable Backup Domain write protection - DBP: u1, - padding: u23, + /// JPEG quantization tables + QMEM1_2: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Power control register (PWR_CR) - CSR: mmio.Mmio(packed struct(u32) { - /// Wake-Up Flag - WUF: u1, - /// STANDBY Flag - SBF: u1, - /// PVD Output - PVDO: u1, - reserved8: u5, - /// Enable WKUP pin - EWUP: u1, - padding: u23, + /// JPEG quantization tables + QMEM1_3: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - }; - }; - - pub const tamp_wl = struct { - pub const BKERASE = enum(u1) { - /// Reset backup registers - Reset = 0x1, - _, - }; - - pub const TAMPFLT = enum(u2) { - /// Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input)" - NoFilter = 0x0, - /// Tamper event is activated after 2 consecutive samples at the active level" - Filter2 = 0x1, - /// Tamper event is activated after 4 consecutive samples at the active level" - Filter4 = 0x2, - /// Tamper event is activated after 8 consecutive samples at the active level" - Filter8 = 0x3, - }; - - pub const TAMPFREQ = enum(u3) { - /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - Hz_1 = 0x0, - /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - Hz_2 = 0x1, - /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - Hz_4 = 0x2, - /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - Hz_8 = 0x3, - /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - Hz_16 = 0x4, - /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - Hz_32 = 0x5, - /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - Hz_64 = 0x6, - /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - Hz_128 = 0x7, - }; - - pub const TAMPMSK = enum(u1) { - /// Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection - ResetBySoftware = 0x0, - /// Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased. The tamper x interrupt must not be enabled when TAMP3MSK is set - ResetByHardware = 0x1, - }; - - pub const TAMPPRCH = enum(u2) { - /// 1 RTCCLK cycle - Cycles1 = 0x0, - /// 2 RTCCLK cycles - Cycles2 = 0x1, - /// 4 RTCCLK cycles - Cycles4 = 0x2, - /// 8 RTCCLK cycles - Cycles8 = 0x3, - }; - - pub const TAMPTRG = enum(u1) { - /// If TAMPFLT != 00 Tamper x input staying low triggers a tamper detection event. If TAMPFLT = 00 Tamper x input rising edge and high level triggers a tamper detection event - FilteredLowOrUnfilteredHigh = 0x0, - /// If TAMPFLT != 00 Tamper x input staying high triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge and low level triggers a tamper detection event - FilteredHighOrUnfilteredLow = 0x1, - }; - - /// Tamper and backup registers - pub const TAMP = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Tamper detection on IN X enable - TAMPE: u1, - reserved16: u15, - /// Internal tamper X enable - ITAMPE: u1, - padding: u15, + /// JPEG quantization tables + QMEM1_4: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Tamper X no erase - TAMPNOER: u1, - reserved16: u15, - /// Tamper X mask. The tamper X interrupt must not be enabled when TAMPMSK is set. - TAMPMSK: packed union { - raw: u1, - value: TAMPMSK, - }, - reserved23: u6, - /// Backup registers erase - BKERASE: packed union { - raw: u1, - value: BKERASE, - }, - /// Active level for tamper X input - TAMPTRG: packed union { - raw: u1, - value: TAMPTRG, - }, - padding: u7, + /// JPEG quantization tables + QMEM1_5: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// TAMP control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Internal Tamper X no erase - ITAMPNOER: u1, - padding: u31, + /// JPEG quantization tables + QMEM1_6: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// TAMP filter control register - FLTCR: mmio.Mmio(packed struct(u32) { - /// Tamper sampling frequency. Determines the frequency at which each of the INx inputs are sampled. - TAMPFREQ: packed union { - raw: u3, - value: TAMPFREQ, - }, - /// INx filter count. These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the INx inputs. - TAMPFLT: packed union { - raw: u2, - value: TAMPFLT, - }, - /// INx precharge duration. These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the INx inputs. - TAMPPRCH: packed union { - raw: u2, - value: TAMPPRCH, - }, - /// INx pull-up disable. This bit determines if each of the TAMPx pins are precharged before each sample. - TAMPPUDIS: u1, - padding: u24, + /// JPEG quantization tables + QMEM1_7: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - reserved44: [28]u8, - /// TAMP interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt enable - TAMPIE: u1, - reserved16: u15, - /// Internal tamper X interrupt enable - ITAMPIE: u1, - padding: u15, + /// JPEG quantization tables + QMEM1_8: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// TAMP status register - SR: mmio.Mmio(packed struct(u32) { - /// Tamper X detection flag - TAMPF: u1, - reserved16: u15, - /// Internal tamper X detection flag - ITAMPF: u1, - padding: u15, + /// JPEG quantization tables + QMEM1_9: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// TAMP masked interrupt status register - MISR: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt masked flag - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X interrupt masked flag - ITAMPMF: u1, - padding: u15, + /// JPEG quantization tables + QMEM1_10: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - reserved60: [4]u8, - /// TAMP status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear tamper X detection flag - CTAMPF: u1, - reserved16: u15, - /// Clear internal tamper X detection flag - CITAMPF: u1, - padding: u15, + /// JPEG quantization tables + QMEM1_11: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// monotonic counter register - COUNTR: mmio.Mmio(packed struct(u32) { - /// COUNT - COUNT: u32, + /// JPEG quantization tables + QMEM1_12: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - reserved256: [188]u8, - /// TAMP backup register - BKPR: [20]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, + /// JPEG quantization tables + QMEM1_13: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - }; - }; - - pub const hash_v4 = struct { - /// Hash processor. - pub const HASH = extern struct { - /// control register. - CR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Initialize message digest calculation. - INIT: u1, - /// DMA enable. - DMAE: u1, - /// Data type selection. - DATATYPE: u2, - /// Mode selection. - MODE: u1, - reserved8: u1, - /// Number of words already pushed. - NBW: u4, - /// DIN not empty. - DINNE: u1, - /// Multiple DMA Transfers. - MDMAT: u1, - reserved16: u2, - /// Long key selection. - LKEY: u1, - /// Algorithm selection. - ALGO: u2, - padding: u13, + /// JPEG quantization tables + QMEM1_14: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// data input register. - DIN: u32, - /// start register. - STR: mmio.Mmio(packed struct(u32) { - /// Number of valid bits in the last word of the message. - NBLW: u5, - reserved8: u3, - /// Digest calculation. - DCAL: u1, - padding: u23, + /// JPEG quantization tables + QMEM1_15: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// digest registers. - HRA: [5]u32, - /// interrupt enable register. - IMR: mmio.Mmio(packed struct(u32) { - /// Data input interrupt enable. - DINIE: u1, - /// Digest calculation completion interrupt enable. - DCIE: u1, - padding: u30, + /// JPEG quantization tables + QMEM2_0: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// status register. - SR: mmio.Mmio(packed struct(u32) { - /// Data input interrupt status. - DINIS: u1, - /// Digest calculation completion interrupt status. - DCIS: u1, - /// DMA Status. - DMAS: u1, - /// Busy bit. - BUSY: u1, - reserved9: u5, - /// Number of words already pushed. - NBWP: u5, - reserved15: u1, - /// DIN not empty. - DINNE: u1, - /// Number of words expected. - NBWE: u5, - padding: u11, + /// JPEG quantization tables + QMEM2_1: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - reserved248: [208]u8, - /// context swap registers. - CSR: [54]u32, - reserved784: [320]u8, - /// HASH digest register. - HR: [8]u32, - }; - }; - - pub const uid_v1 = struct { - /// Device Factory programmed 96-bit unique device identifier - pub const UID = extern struct { - /// Factory programmed 96-bit unique device identifier word 0 - UID: [3]u32, - }; - }; - - pub const hsem_v4 = struct { - /// Hardware semaphore. - pub const HSEM = extern struct { - /// HSEM register HSEM_R%s HSEM_R31. - R: [16]mmio.Mmio(packed struct(u32) { - /// Semaphore ProcessID. - PROCID: u8, - /// Semaphore COREID. - COREID: u4, - reserved31: u19, - /// Lock indication. - LOCK: u1, + /// JPEG quantization tables + QMEM2_2: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - reserved128: [64]u8, - /// HSEM Read lock register. - RLR: [16]mmio.Mmio(packed struct(u32) { - /// Semaphore ProcessID. - PROCID: u8, - /// Semaphore COREID. - COREID: u4, - reserved31: u19, - /// Lock indication. - LOCK: u1, + /// JPEG quantization tables + QMEM2_3: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - reserved256: [64]u8, - /// HSEM Interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore n enable bit. - ISE: u1, - padding: u31, + /// JPEG quantization tables + QMEM2_4: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// HSEM Interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Interrupt(N) semaphore n clear bit. - ISC: u1, - padding: u31, + /// JPEG quantization tables + QMEM2_5: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// HSEM Interrupt status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Interrupt(N) semaphore n status bit before enable (mask). - ISF: u1, - padding: u31, + /// JPEG quantization tables + QMEM2_6: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// HSEM Masked interrupt status register. - MISR: mmio.Mmio(packed struct(u32) { - /// masked interrupt(N) semaphore n status bit after enable (mask). - MISF: u1, - padding: u31, + /// JPEG quantization tables + QMEM2_7: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - reserved320: [48]u8, - /// HSEM Clear register. - CR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// COREID. - COREID: u4, - reserved16: u4, - /// Semaphore clear Key. - KEY: u16, + /// JPEG quantization tables + QMEM2_8: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// HSEM Interrupt clear register. - KEYR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Semaphore Clear Key. - KEY: u16, + /// JPEG quantization tables + QMEM2_9: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - }; - }; - - pub const dbgmcu_l1 = struct { - /// debug support - pub const DBGMCU = extern struct { - /// DBGMCU_IDCODE - IDCODE: mmio.Mmio(packed struct(u32) { - /// Device identifier - DEV_ID: u12, - reserved16: u4, - /// Revision identifie - REV_ID: u16, + /// JPEG quantization tables + QMEM2_10: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Debug MCU configuration register - CR: mmio.Mmio(packed struct(u32) { - /// Debug Sleep mode - DBG_SLEEP: u1, - /// Debug Stop mode - DBG_STOP: u1, - /// Debug Standby mode - DBG_STANDBY: u1, - reserved5: u2, - /// Trace pin assignment control - TRACE_IOEN: u1, - /// Trace pin assignment control - TRACE_MODE: u2, - padding: u24, + /// JPEG quantization tables + QMEM2_11: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Debug MCU APB1 freeze register1 - APB1_FZ: mmio.Mmio(packed struct(u32) { - /// TIM2 counter stopped when core is halted - DBG_TIM2_STOP: u1, - /// TIM3 counter stopped when core is halted - DBG_TIM3_STOP: u1, - /// TIM4 counter stopped when core is halted - DBG_TIM4_STOP: u1, - /// TIM5 counter stopped when core is halted - DBG_TIM5_STOP: u1, - /// TIM6 counter stopped when core is halted - DBG_TIM6_STOP: u1, - /// TIM7 counter stopped when core is halted - DBG_TIM7_STOP: u1, - reserved10: u4, - /// Debug RTC stopped when core is halted - DBG_RTC_STOP: u1, - /// Debug window watchdog stopped when core is halted - DBG_WWDG_STOP: u1, - /// Debug independent watchdog stopped when core is halted - DBG_IWDG_STOP: u1, - reserved21: u8, - /// SMBUS timeout mode stopped when core is halted - DBG_I2C1_SMBUS_TIMEOUT: u1, - /// SMBUS timeout mode stopped when core is halted - DBG_I2C2_SMBUS_TIMEOUT: u1, - padding: u9, + /// JPEG quantization tables + QMEM2_12: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// Debug MCU APB1 freeze register 2 - APB2_FZ: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// TIM counter stopped when core is halted - DBG_TIM9_STOP: u1, - /// TIM counter stopped when core is halted - DBG_TIM10_STOP: u1, - /// TIM counter stopped when core is halted - DBG_TIM11_STOP: u1, - padding: u27, + /// JPEG quantization tables + QMEM2_13: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - }; - }; - - pub const adc_v4 = struct { - pub const ADCALDIF = enum(u1) { - /// Calibration for single-ended mode - SingleEnded = 0x0, - /// Calibration for differential mode - Differential = 0x1, - }; - - pub const ADSTP = enum(u1) { - /// Stop conversion of channel - Stop = 0x1, - _, - }; - - pub const AWD1SGL = enum(u1) { - /// Analog watchdog 1 enabled on all channels - All = 0x0, - /// Analog watchdog 1 enabled on single channel selected in AWD1CH - Single = 0x1, - }; - - pub const BOOST = enum(u2) { - /// Boost mode used when clock ≤ 6.25 MHz - LT6_25 = 0x0, - /// Boost mode used when 6.25 MHz < clock ≤ 12.5 MHz - LT12_5 = 0x1, - /// Boost mode used when 12.5 MHz < clock ≤ 25.0 MHz - LT25 = 0x2, - /// Boost mode used when 25.0 MHz < clock ≤ 50.0 MHz - LT50 = 0x3, - }; - - pub const DIFSEL = enum(u1) { - /// Input channel is configured in single-ended mode - SingleEnded = 0x0, - /// Input channel is configured in differential mode - Differential = 0x1, - }; - - pub const DMNGT = enum(u2) { - /// Store output data in DR only - DR = 0x0, - /// DMA One Shot Mode selected - DMA_OneShot = 0x1, - /// DFSDM mode selected - DFSDM = 0x2, - /// DMA Circular Mode selected - DMA_Circular = 0x3, - }; - - pub const EXTEN = enum(u2) { - /// Trigger detection disabled - Disabled = 0x0, - /// Trigger detection on the rising edge - RisingEdge = 0x1, - /// Trigger detection on the falling edge - FallingEdge = 0x2, - /// Trigger detection on both the rising and falling edges - BothEdges = 0x3, - }; - - pub const JEXTEN = enum(u2) { - /// Trigger detection disabled - Disabled = 0x0, - /// Trigger detection on the rising edge - RisingEdge = 0x1, - /// Trigger detection on the falling edge - FallingEdge = 0x2, - /// Trigger detection on both the rising and falling edges - BothEdges = 0x3, - }; - - pub const JQM = enum(u1) { - /// JSQR Mode 0: Queue maintains the last written configuration into JSQR - Mode0 = 0x0, - /// JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence - Mode1 = 0x1, - }; - - pub const OVRMOD = enum(u1) { - /// Preserve DR register when an overrun is detected - Preserve = 0x0, - /// Overwrite DR register when an overrun is detected - Overwrite = 0x1, - }; - - pub const PCSEL = enum(u1) { - /// Input channel x is not pre-selected - NotPreselected = 0x0, - /// Pre-select input channel x - Preselected = 0x1, - }; - - pub const RES = enum(u3) { - /// 16-bit resolution - Bits16 = 0x0, - /// 14-bit resolution in legacy mode (not optimized power consumption) - Bits14 = 0x1, - /// 12-bit resolution in legacy mode (not optimized power consumption) - Bits12 = 0x2, - /// 10-bit resolution - Bits10 = 0x3, - /// 14-bit resolution - Bits14V = 0x5, - /// 12-bit resolution - Bits12V = 0x6, - /// 8-bit resolution - Bits8 = 0x7, - _, - }; - - pub const ROVSM = enum(u1) { - /// Oversampling is temporary stopped and continued after injection sequence - Continued = 0x0, - /// Oversampling is aborted and resumed from start after injection sequence - Resumed = 0x1, - }; - - pub const SAMPLE_TIME = enum(u3) { - /// 1.5 clock cycles - Cycles1_5 = 0x0, - /// 2.5 clock cycles - Cycles2_5 = 0x1, - /// 8.5 clock cycles - Cycles8_5 = 0x2, - /// 16.5 clock cycles - Cycles16_5 = 0x3, - /// 32.5 clock cycles - Cycles32_5 = 0x4, - /// 64.5 clock cycles - Cycles64_5 = 0x5, - /// 387.5 clock cycles - Cycles387_5 = 0x6, - /// 810.5 clock cycles - Cycles810_5 = 0x7, - }; - - pub const TROVS = enum(u1) { - /// All oversampled conversions for a channel are run following a trigger - Automatic = 0x0, - /// Each oversampled conversion for a channel needs a new trigger - Triggered = 0x1, - }; - - /// Analog to Digital Converter - pub const ADC = extern struct { - /// interrupt and status register - ISR: mmio.Mmio(packed struct(u32) { - /// ready flag - ADRDY: u1, - /// group regular end of sampling flag - EOSMP: u1, - /// group regular end of unitary conversion flag - EOC: u1, - /// group regular end of sequence conversions flag - EOS: u1, - /// group regular overrun flag - OVR: u1, - /// group injected end of unitary conversion flag - JEOC: u1, - /// group injected end of sequence conversions flag - JEOS: u1, - /// analog watchdog 1 flag - AWD1: u1, - /// analog watchdog 2 flag - AWD2: u1, - /// analog watchdog 3 flag - AWD3: u1, - /// group injected contexts queue overflow flag - JQOVF: u1, - reserved12: u1, - /// ADC LDO output voltage ready (not always available) - LDORDY: u1, - padding: u19, + /// JPEG quantization tables + QMEM2_14: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// ready interrupt - ADRDYIE: u1, - /// group regular end of sampling interrupt - EOSMPIE: u1, - /// group regular end of unitary conversion interrupt - EOCIE: u1, - /// group regular end of sequence conversions interrupt - EOSIE: u1, - /// group regular overrun interrupt - OVRIE: u1, - /// group injected end of unitary conversion interrupt - JEOCIE: u1, - /// group injected end of sequence conversions interrupt - JEOSIE: u1, - /// analog watchdog 1 interrupt - AWD1IE: u1, - /// analog watchdog 2 interrupt - AWD2IE: u1, - /// analog watchdog 3 interrupt - AWD3IE: u1, - /// group injected contexts queue overflow interrupt - JQOVFIE: u1, - padding: u21, + /// JPEG quantization tables + QMEM2_15: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// enable - ADEN: u1, - /// disable - ADDIS: u1, - /// group regular conversion start - ADSTART: u1, - /// group injected conversion start - JADSTART: u1, - /// group regular conversion stop - ADSTP: packed union { - raw: u1, - value: ADSTP, - }, - /// group injected conversion stop - JADSTP: packed union { - raw: u1, - value: ADSTP, - }, - reserved8: u2, - /// Boost mode control - BOOST: packed union { - raw: u2, - value: BOOST, - }, - reserved16: u6, - /// Linearity calibration - ADCALLIN: u1, - reserved22: u5, - /// Linearity calibration ready Word 1 - LINCALRDYW1: u1, - /// Linearity calibration ready Word 2 - LINCALRDYW2: u1, - /// Linearity calibration ready Word 3 - LINCALRDYW3: u1, - /// Linearity calibration ready Word 4 - LINCALRDYW4: u1, - /// Linearity calibration ready Word 5 - LINCALRDYW5: u1, - /// Linearity calibration ready Word 6 - LINCALRDYW6: u1, - /// voltage regulator enable - ADVREGEN: u1, - /// deep power down enable - DEEPPWD: u1, - /// differential mode for calibration - ADCALDIF: packed union { - raw: u1, - value: ADCALDIF, - }, - /// calibration - ADCAL: u1, + /// JPEG quantization tables + QMEM3_0: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// configuration register 1 - CFGR: mmio.Mmio(packed struct(u32) { - /// DMA transfer enable - DMNGT: packed union { - raw: u2, - value: DMNGT, - }, - /// data resolution - RES: packed union { - raw: u3, - value: RES, - }, - /// group regular external trigger source - EXTSEL: u5, - /// group regular external trigger polarity - EXTEN: packed union { - raw: u2, - value: EXTEN, - }, - /// group regular overrun configuration - OVRMOD: packed union { - raw: u1, - value: OVRMOD, - }, - /// Continuous conversion - CONT: u1, - /// low power auto wait - AUTDLY: u1, - reserved16: u1, - /// group regular sequencer discontinuous mode - DISCEN: u1, - /// group regular sequencer discontinuous number of ranks - DISCNUM: u3, - /// group injected sequencer discontinuous mode - JDISCEN: u1, - /// group injected contexts queue mode - JQM: packed union { - raw: u1, - value: JQM, - }, - /// analog watchdog 1 monitoring a single channel or all channels - AWD1SGL: packed union { - raw: u1, - value: AWD1SGL, - }, - /// analog watchdog 1 enable on scope group regular - AWD1EN: u1, - /// analog watchdog 1 enable on scope group injected - JAWD1EN: u1, - /// group injected automatic trigger mode - JAUTO: u1, - /// analog watchdog 1 monitored channel selection - AWD1CH: u5, - /// group injected contexts queue disable - JQDIS: u1, + /// JPEG quantization tables + QMEM3_1: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// oversampler enable on scope group regular - ROVSE: u1, - /// oversampler enable on scope group injected - JOVSE: u1, - reserved5: u3, - /// oversampling shift - OVSS: u4, - /// oversampling discontinuous mode (triggered mode) for group regular - TROVS: packed union { - raw: u1, - value: TROVS, - }, - /// Regular Oversampling mode - ROVSM: packed union { - raw: u1, - value: ROVSM, - }, - /// Right-shift data after Offset 1 correction - RSHIFT1: u1, - /// Right-shift data after Offset 2 correction - RSHIFT2: u1, - /// Right-shift data after Offset 3 correction - RSHIFT3: u1, - /// Right-shift data after Offset 4 correction - RSHIFT4: u1, - reserved16: u1, - /// Oversampling ratio - OSVR: u10, - reserved28: u2, - /// Left shift factor - LSHIFT: u4, + /// JPEG quantization tables + QMEM3_2: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// sampling time register 1-2 - SMPR: [2]mmio.Mmio(packed struct(u32) { - /// channel n * 10 + x sampling time - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - padding: u29, + /// JPEG quantization tables + QMEM3_3: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// pre channel selection register - PCSEL: mmio.Mmio(packed struct(u32) { - /// Channel x (VINP[i]) pre selection - PCSEL: packed union { - raw: u1, - value: PCSEL, - }, - padding: u31, + /// JPEG quantization tables + QMEM3_4: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// analog watchdog 1 threshold register - LTR1: mmio.Mmio(packed struct(u32) { - /// analog watchdog 1 threshold low - LTR1: u26, - padding: u6, + /// JPEG quantization tables + QMEM3_5: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// analog watchdog 2 threshold register - HTR1: mmio.Mmio(packed struct(u32) { - /// analog watchdog 2 threshold low - HTR1: u26, - padding: u6, + /// JPEG quantization tables + QMEM3_6: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - reserved48: [8]u8, - /// group regular sequencer ranks register 1 - SQR1: mmio.Mmio(packed struct(u32) { - /// L3 - L: u4, - reserved6: u2, - /// group regular sequencer rank 1-4 - SQ: u5, - padding: u21, + /// JPEG quantization tables + QMEM3_7: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// group regular sequencer ranks register 2 - SQR2: mmio.Mmio(packed struct(u32) { - /// group regular sequencer rank 5-9 - SQ: u5, - padding: u27, + /// JPEG quantization tables + QMEM3_8: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// group regular sequencer ranks register 3 - SQR3: mmio.Mmio(packed struct(u32) { - /// group regular sequencer rank 10-14 - SQ: u5, - padding: u27, + /// JPEG quantization tables + QMEM3_9: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// group regular sequencer ranks register 4 - SQR4: mmio.Mmio(packed struct(u32) { - /// group regular sequencer rank 15-16 - SQ: u5, - padding: u27, + /// JPEG quantization tables + QMEM3_10: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// group regular conversion data register - DR: mmio.Mmio(packed struct(u32) { - /// group regular conversion data - RDATA: u16, - padding: u16, + /// JPEG quantization tables + QMEM3_11: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - reserved76: [8]u8, - /// group injected sequencer register - JSQR: mmio.Mmio(packed struct(u32) { - /// group injected sequencer scan length - JL: u2, - /// group injected external trigger source - JEXTSEL: u5, - /// group injected external trigger polarity - JEXTEN: packed union { - raw: u2, - value: JEXTEN, - }, - /// group injected sequencer rank 1-4 - JSQ1: u5, - padding: u18, + /// JPEG quantization tables + QMEM3_12: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - reserved96: [16]u8, - /// offset number 1-4 register - OFR: [4]mmio.Mmio(packed struct(u32) { - /// offset number x offset level - OFFSET1: u26, - /// offset number x channel selection - OFFSET1_CH: u5, - /// Signed saturation enable - SSATE: u1, + /// JPEG quantization tables + QMEM3_13: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - reserved128: [16]u8, - /// group injected sequencer rank 1-4 register - JDR: [4]mmio.Mmio(packed struct(u32) { - /// group injected sequencer rank 1 conversion data - JDATA: u32, + /// JPEG quantization tables + QMEM3_14: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - reserved160: [16]u8, - /// analog watchdog 2 configuration register - AWD2CR: mmio.Mmio(packed struct(u32) { - /// analog watchdog 2 monitored channel selection - AWD2CH: u1, - padding: u31, + /// JPEG quantization tables + QMEM3_15: mmio.Mmio(packed struct(u32) { + /// QMem RAM + QMem_RAM: u32, }), - /// analog watchdog 3 configuration register - AWD3CR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// analog watchdog 3 monitored channel selection - AWD3CH: u1, - padding: u30, + /// JPEG HuffMin tables + HUFFMIN_0: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - reserved176: [8]u8, - /// watchdog lower threshold register 2 - LTR2: mmio.Mmio(packed struct(u32) { - /// Analog watchdog 2 lower threshold - LTR2: u26, - padding: u6, + /// JPEG HuffMin tables + HUFFMIN_1: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - /// watchdog higher threshold register 2 - HTR2: mmio.Mmio(packed struct(u32) { - /// Analog watchdog 2 higher threshold - HTR2: u26, - padding: u6, + /// JPEG HuffMin tables + HUFFMIN_2: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - /// watchdog lower threshold register 3 - LTR3: mmio.Mmio(packed struct(u32) { - /// Analog watchdog 3 lower threshold - LTR3: u26, - padding: u6, + /// JPEG HuffMin tables + HUFFMIN_3: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - /// watchdog higher threshold register 3 - HTR3: mmio.Mmio(packed struct(u32) { - /// Analog watchdog 3 higher threshold - HTR3: u26, - padding: u6, + /// JPEG HuffMin tables + HUFFMIN_4: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - /// channel differential or single-ended mode selection register - DIFSEL: mmio.Mmio(packed struct(u32) { - /// channel differential or single-ended mode for channel - DIFSEL: packed union { - raw: u1, - value: DIFSEL, - }, - padding: u31, + /// JPEG HuffMin tables + HUFFMIN_5: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - /// calibration factors register - CALFACT: mmio.Mmio(packed struct(u32) { - /// calibration factor in single-ended mode - CALFACT_S: u11, - reserved16: u5, - /// calibration factor in differential mode - CALFACT_D: u11, - padding: u5, + /// JPEG HuffMin tables + HUFFMIN_6: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - /// Calibration Factor register 2 - CALFACT2: mmio.Mmio(packed struct(u32) { - /// Linearity Calibration Factor - LINCALFACT: u30, - padding: u2, + /// JPEG HuffMin tables + HUFFMIN_7: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - }; - }; - - pub const dcache_v1 = struct { - /// Data cache. - pub const DCACHE = extern struct { - /// DCACHE control register. - CR: mmio.Mmio(packed struct(u32) { - /// enable. - EN: u1, - /// full cache invalidation Can be set by software, only when EN = 1. Cleared by hardware when the BUSYF flag is set (during full cache invalidation operation). Writing 0 has no effect. - CACHEINV: u1, - reserved8: u6, - /// cache command maintenance operation (cleans and/or invalidates an address range) Can be set and cleared by software, only when no maintenance command is ongoing (BUSYCMDF = 0). others: reserved. - CACHECMD: u3, - /// starts maintenance command (maintenance operation defined in CACHECMD). Can be set by software, only when EN = 1, BUSYCMDF = 0, BUSYF = 0 and CACHECMD = 0b001, 0b010 or 0b011. Cleared by hardware when the BUSYCMDF flag is set (during cache maintenance operation). Writing 0 has no effect. - STARTCMD: u1, - reserved16: u4, - /// read-hit monitor enable. - RHITMEN: u1, - /// read-miss monitor enable. - RMISSMEN: u1, - /// read-hit monitor reset. - RHITMRST: u1, - /// read-miss monitor reset. - RMISSMRST: u1, - /// write-hit monitor enable. - WHITMEN: u1, - /// write-miss monitor enable. - WMISSMEN: u1, - /// write-hit monitor reset. - WHITMRST: u1, - /// write-miss monitor reset. - WMISSMRST: u1, - reserved31: u7, - /// output burst type for cache master port read accesses Write access is always done in INCR burst type. - HBURST: u1, + /// JPEG HuffMin tables + HUFFMIN_8: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - /// DCACHE status register. - SR: mmio.Mmio(packed struct(u32) { - /// full invalidate busy flag. - BUSYF: u1, - /// full invalidate busy end flag Cleared by writing DCACHE_FCR.CBSYENDF = 1. - BSYENDF: u1, - /// cache error flag Cleared by writing DCACHE_FCR.CERRF = 1. - ERRF: u1, - /// command busy flag. - BUSYCMDF: u1, - /// command end flag Cleared by writing DCACHE_FCR.CCMDENDF = 1. - CMDENDF: u1, - padding: u27, + /// JPEG HuffMin tables + HUFFMIN_9: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - /// DCACHE interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// interrupt enable on busy end Set by SW to enable an interrupt generation at the end of a cache full invalidate operation. - BSYENDIE: u1, - /// interrupt enable on cache error Set by software to enable an interrupt generation in case of cache functional error (eviction or clean operation write-back error). - ERRIE: u1, - reserved4: u1, - /// interrupt enable on command end Set by software to enable an interrupt generation at the end of a cache command (clean and/or invalidate an address range). - CMDENDIE: u1, - padding: u27, + /// JPEG HuffMin tables + HUFFMIN_10: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - /// DCACHE flag clear register. - FCR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// clear full invalidate busy end flag Set by software. - CBSYENDF: u1, - /// clear cache error flag Set by software. - CERRF: u1, - reserved4: u1, - /// clear command end flag Set by software. - CCMDENDF: u1, - padding: u27, + /// JPEG HuffMin tables + HUFFMIN_11: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - /// DCACHE read-hit monitor register. - RHMONR: u32, - /// DCACHE read-miss monitor register. - RMMONR: mmio.Mmio(packed struct(u32) { - /// cache read-miss monitor counter. - RMISSMON: u16, - padding: u16, + /// JPEG HuffMin tables + HUFFMIN_12: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - reserved32: [8]u8, - /// DCACHE write-hit monitor register. - WHMONR: u32, - /// DCACHE write-miss monitor register. - WMMONR: mmio.Mmio(packed struct(u32) { - /// cache write-miss monitor counter. - WMISSMON: u16, - padding: u16, + /// JPEG HuffMin tables + HUFFMIN_13: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - /// DCACHE command range start address register. - CMDRSADDRR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// start address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written.. - CMDSTARTADDR: u28, + /// JPEG HuffMin tables + HUFFMIN_14: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - /// DCACHE command range end address register. - CMDREADDRR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// end address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written. - CMDENDADDR: u28, + /// JPEG HuffMin tables + HUFFMIN_15: mmio.Mmio(packed struct(u32) { + /// HuffMin RAM + HuffMin_RAM: u32, }), - }; - }; - - pub const bkp_v1 = struct { - pub const ASOS = enum(u1) { - /// RTC Alarm pulse output selected - Alarm = 0x0, - /// RTC Second pulse output selected - Second = 0x1, - }; - - pub const TPAL = enum(u1) { - /// A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) - High = 0x0, - /// A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) - Low = 0x1, - }; - - /// Backup registers - pub const BKP = extern struct { - /// Data register - DR: mmio.Mmio(packed struct(u32) { - /// Backup data - D: u16, - padding: u16, + /// JPEG HuffSymb tables + HUFFBASE0: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - reserved44: [40]u8, - /// RTC clock calibration register - RTCCR: mmio.Mmio(packed struct(u32) { - /// Calibration value - CAL: u7, - /// Calibration Clock Output - CCO: u1, - /// Alarm or second output enable - ASOE: u1, - /// Alarm or second output selection - ASOS: packed union { - raw: u1, - value: ASOS, - }, - padding: u22, + /// JPEG HuffSymb tables + HUFFBASE1: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Tamper pin enable - TPE: u1, - /// Tamper pin active level - TPAL: packed union { - raw: u1, - value: TPAL, - }, - padding: u30, + /// JPEG HuffSymb tables + HUFFBASE2: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// Control/status register - CSR: mmio.Mmio(packed struct(u32) { - /// Clear Tamper event - CTE: u1, - /// Clear Tamper Interrupt - CTI: u1, - /// Tamper Pin interrupt enable - TPIE: u1, - reserved8: u5, - /// Tamper Event Flag - TEF: u1, - /// Tamper Interrupt Flag - TIF: u1, - padding: u22, + /// JPEG HuffSymb tables + HUFFBASE3: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - }; - }; - - pub const lptim_v1b_g4 = struct { - pub const CKPOL = enum(u2) { - /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. - Rising = 0x0, - /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. - Falling = 0x1, - /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. - Both = 0x2, - _, - }; - - pub const ClockSource = enum(u1) { - /// clocked by internal clock source (APB clock or any of the embedded oscillators) - Internal = 0x0, - /// clocked by an external clock source through the LPTIM external Input1 - External = 0x1, - }; - - pub const Filter = enum(u2) { - Count1 = 0x0, - Count2 = 0x1, - Count4 = 0x2, - Count8 = 0x3, - }; - - pub const PRESC = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div4 = 0x2, - Div8 = 0x3, - Div16 = 0x4, - Div32 = 0x5, - Div64 = 0x6, - Div128 = 0x7, - }; - - pub const TRIGEN = enum(u2) { - /// software trigger (counting start is initiated by software) - Software = 0x0, - /// rising edge is the active edge - RisingEdge = 0x1, - /// falling edge is the active edge - FallingEdge = 0x2, - /// both edges are active edges - BothEdge = 0x3, - }; - - pub const WAVPOL = enum(u1) { - /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. - Positive = 0x0, - /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. - Negative = 0x1, - }; - - /// Low power timer with Output Compare - pub const LPTIM = extern struct { - /// LPTIM interrupt and status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, - /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. - ARRM: u1, - /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. - EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, - /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. - ARROK: u1, - /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UP: u1, - /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWN: u1, - padding: u25, + /// JPEG HuffSymb tables + HUFFBASE4: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// LPTIM interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, - /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. - ARRMCF: u1, - /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. - EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, - /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. - ARROKCF: u1, - /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPCF: u1, - /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNCF: u1, - padding: u25, + /// JPEG HuffSymb tables + HUFFBASE5: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// LPTIM interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, - /// Autoreload match Interrupt Enable. - ARRMIE: u1, - /// External trigger valid edge Interrupt Enable. - EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, - /// Autoreload register update OK Interrupt Enable. - ARROKIE: u1, - /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPIE: u1, - /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNIE: u1, - padding: u25, + /// JPEG HuffSymb tables + HUFFBASE6: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// LPTIM configuration register. - CFGR: mmio.Mmio(packed struct(u32) { - /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. - CKSEL: packed union { - raw: u1, - value: ClockSource, - }, - /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. - CKPOL: packed union { - raw: u2, - value: CKPOL, - }, - /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - CKFLT: packed union { - raw: u2, - value: Filter, - }, - reserved6: u1, - /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. - TRGFLT: packed union { - raw: u2, - value: Filter, - }, - reserved9: u1, - /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. - PRESC: packed union { - raw: u3, - value: PRESC, - }, - padding: u20, + /// JPEG HuffSymb tables + HUFFBASE7: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// LPTIM control register. - CR: mmio.Mmio(packed struct(u32) { - /// LPTIM enable The ENABLE bit is set and cleared by software. - ENABLE: u1, - /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. - SNGSTRT: u1, - /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. - CNTSTRT: u1, - /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. - COUNTRST: u1, - /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. - RSTARE: u1, - padding: u27, + /// JPEG HuffSymb tables + HUFFBASE8: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// LPTIM compare register 1. - CMP: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. - CMP: u16, - padding: u16, + /// JPEG HuffSymb tables + HUFFBASE9: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// LPTIM autoreload register. - ARR: mmio.Mmio(packed struct(u32) { - /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. - ARR: u16, - padding: u16, + /// JPEG HuffSymb tables + HUFFBASE10: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// LPTIM counter register. - CNT: mmio.Mmio(packed struct(u32) { - /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. - CNT: u16, - padding: u16, + /// JPEG HuffSymb tables + HUFFBASE11: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// LPTIM option register. - OR: u32, - }; - }; - - pub const opamp_h_v1 = struct { - pub const CALON = enum(u1) { - /// Normal mode - Normal = 0x0, - /// Calibration mode (all switches opened by HW) - Calibration = 0x1, - }; - - pub const CALOUT = enum(u1) { - /// Non-inverting < inverting - Less = 0x0, - /// Non-inverting > inverting - Greater = 0x1, - }; - - pub const CALSEL = enum(u2) { - /// VREFOPAMP=3.3% VDDA. - Percent3_3 = 0x0, - /// VREFOPAMP=10% VDDA. - Percent10 = 0x1, - /// VREFOPAMP=50% VDDA. - Percent50 = 0x2, - /// VREFOPAMP=90% VDDA. - Percent90 = 0x3, - }; - - pub const FORCE_VP = enum(u1) { - /// Normal operating mode. Non-inverting input connected to inputs. - NormalOperating = 0x0, - /// Calibration verification mode. Non-inverting input connected to calibration reference voltage. - CalibrationVerification = 0x1, - }; - - pub const OPAHSM = enum(u1) { - /// operational amplifier in normal mode - Normal = 0x0, - /// operational amplifier in high-speed mode - HighSpeed = 0x1, - }; - - pub const PGA_GAIN = enum(u4) { - /// Non-inverting internal Gain 2, VREF- referenced - Gain2 = 0x0, - /// Non-inverting internal Gain 4, VREF- referenced - Gain4 = 0x1, - /// Non-inverting internal Gain 8, VREF- referenced - Gain8 = 0x2, - /// Non-inverting internal Gain 16, VREF- referenced - Gain16 = 0x3, - /// Non-inverting internal Gain 2 with filtering on INM0, VREF- referenced - Gain2_FilteringVINM0 = 0x4, - /// Non-inverting internal Gain 4 with filtering on INM0, VREF- referenced - Gain4_FilteringVINM0 = 0x5, - /// Non-inverting internal Gain 8 with filtering on INM0, VREF- referenced - Gain8_FilteringVINM0 = 0x6, - /// Non-inverting internal Gain 8 with filtering on INM0, VREF- referenced - Gain16_FilteringVINM0 = 0x7, - /// Inverting gain=-1/ Non-inverting gain =2 with INM0 node for input or bias - Gain2InvGainNeg1_InputVINM0 = 0x8, - /// Inverting gain=-3/ Non-inverting gain =4 with INM0 node for input or bias - Gain4InvGainNeg3_InputVINM0 = 0x9, - /// Inverting gain=-7/ Non-inverting gain =8 with INM0 node for input or bias - Gain8InvGainNeg7_InputVINM0 = 0xa, - /// Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias - Gain16InvGainNeg15_InputVINM0 = 0xb, - /// Inverting gain=-1/ Non-inverting gain =2 with INM0 node for input or bias, INM1 node for filtering - Gain2InvGainNeg1_InputVINM0FilteringVINM1 = 0xc, - /// Inverting gain=-3/ Non-inverting gain =4 with INM0 node for input or bias, INM1 node for filtering - Gain4InvGainNeg3_InputVINM0FilteringVINM1 = 0xd, - /// Inverting gain=-7/ Non-inverting gain =8 with INM0 node for input or bias, INM1 node for filtering - Gain8InvGainNeg7_InputVINM0FilteringVINM1 = 0xe, - /// Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias, INM1 node for filtering - Gain16InvGainNeg15_InputVINM0FilteringVINM1 = 0xf, - }; - - pub const USERTRIM = enum(u1) { - /// \'factory\' trim code used - Factory = 0x0, - /// \'user\' trim code used - User = 0x1, - }; - - pub const VM_SEL = enum(u2) { - /// INM0 connected to OPAMP_VINM input - Inm0 = 0x0, - /// INM1 connected to OPAMP_VINM input - Inm1 = 0x1, - /// Feedback resistor is connected to the OPAMP_VINM input (PGA mode), Inverting input selection depends on the PGA_GAIN setting - Pga = 0x2, - /// opamp_out connected to OPAMP_VINM input (Follower mode) - Follower = 0x3, - }; - - pub const VP_SEL = enum(u2) { - /// GPIO connected to OPAMPx_VINP - Gpio = 0x0, - /// dac_outx connected to OPAMPx_VINP - DacOut = 0x1, - _, - }; - - /// Operational amplifiers. - pub const OPAMP = extern struct { - /// OPAMP1 control/status register. - CSR: mmio.Mmio(packed struct(u32) { - /// Operational amplifier Enable. - OPAMPEN: u1, - /// Force internal reference on VP (reserved for test. - FORCE_VP: packed union { - raw: u1, - value: FORCE_VP, - }, - /// Operational amplifier PGA mode. - VP_SEL: packed union { - raw: u2, - value: VP_SEL, - }, - reserved5: u1, - /// Inverting input selection. - VM_SEL: packed union { - raw: u2, - value: VM_SEL, - }, - reserved8: u1, - /// Operational amplifier high-speed mode. - OPAHSM: packed union { - raw: u1, - value: OPAHSM, - }, - reserved11: u2, - /// Calibration mode enabled. - CALON: packed union { - raw: u1, - value: CALON, - }, - /// Calibration selection. - CALSEL: packed union { - raw: u2, - value: CALSEL, - }, - /// allows to switch from AOP offset trimmed values to AOP offset. - PGA_GAIN: packed union { - raw: u4, - value: PGA_GAIN, - }, - /// User trimming enable. - USERTRIM: packed union { - raw: u1, - value: USERTRIM, - }, - reserved29: u10, - /// OPAMP calibration reference voltage output control (reserved for test). - TSTREF: u1, - /// Operational amplifier calibration output. - CALOUT: packed union { - raw: u1, - value: CALOUT, - }, - padding: u1, + /// JPEG HuffSymb tables + HUFFBASE12: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// OPAMP1 offset trimming register in normal mode. - OTR: mmio.Mmio(packed struct(u32) { - /// Trim for NMOS differential pairs. - TRIMOFFSETN: u5, - reserved8: u3, - /// Trim for PMOS differential pairs. - TRIMOFFSETP: u5, - padding: u19, + /// JPEG HuffSymb tables + HUFFBASE13: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// OPAMP1 offset trimming register in low-power mode. - HSOTR: mmio.Mmio(packed struct(u32) { - /// Trim for NMOS differential pairs. - TRIMLPOFFSETN: u5, - reserved8: u3, - /// Trim for PMOS differential pairs. - TRIMLPOFFSETP: u5, - padding: u19, + /// JPEG HuffSymb tables + HUFFBASE14: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - }; - }; - - pub const sai_v4_4pdm = struct { - pub const CKSTR = enum(u1) { - /// Data strobing edge is falling edge of SCK - FallingEdge = 0x0, - /// Data strobing edge is rising edge of SCK - RisingEdge = 0x1, - }; - - pub const CNRDY = enum(u1) { - /// External AC’97 Codec is ready - Ready = 0x0, - /// External AC’97 Codec is not ready - NotReady = 0x1, - }; - - pub const COMP = enum(u2) { - /// No companding algorithm - NoCompanding = 0x0, - /// μ-Law algorithm - MuLaw = 0x2, - /// A-Law algorithm - ALaw = 0x3, - _, - }; - - pub const CPL = enum(u1) { - /// 1’s complement representation - OnesComplement = 0x0, - /// 2’s complement representation - TwosComplement = 0x1, - }; - - pub const DS = enum(u3) { - /// 8 bits - Bit8 = 0x2, - /// 10 bits - Bit10 = 0x3, - /// 16 bits - Bit16 = 0x4, - /// 20 bits - Bit20 = 0x5, - /// 24 bits - Bit24 = 0x6, - /// 32 bits - Bit32 = 0x7, - _, - }; - - pub const FLVL = enum(u3) { - /// FIFO empty - Empty = 0x0, - /// FIFO <= 1⁄4 but not empty - Quarter1 = 0x1, - /// 1⁄4 < FIFO <= 1⁄2 - Quarter2 = 0x2, - /// 1⁄2 < FIFO <= 3⁄4 - Quarter3 = 0x3, - /// 3⁄4 < FIFO but not full - Quarter4 = 0x4, - /// FIFO full - Full = 0x5, - _, - }; - - pub const FSOFF = enum(u1) { - /// FS is asserted on the first bit of the slot 0 - OnFirst = 0x0, - /// FS is asserted one bit before the first bit of the slot 0 - BeforeFirst = 0x1, - }; - - pub const FSPOL = enum(u1) { - /// FS is active low (falling edge) - FallingEdge = 0x0, - /// FS is active high (rising edge) - RisingEdge = 0x1, - }; - - pub const FTH = enum(u3) { - /// FIFO empty - Empty = 0x0, - /// 1⁄4 FIFO - Quarter1 = 0x1, - /// 1⁄2 FIFO - Quarter2 = 0x2, - /// 3⁄4 FIFO - Quarter3 = 0x3, - /// FIFO full - Full = 0x4, - _, - }; - - pub const LSBFIRST = enum(u1) { - /// Data are transferred with MSB first - MsbFirst = 0x0, - /// Data are transferred with LSB first - LsbFirst = 0x1, - }; - - pub const MODE = enum(u2) { - /// Master transmitter - MasterTx = 0x0, - /// Master receiver - MasterRx = 0x1, - /// Slave transmitter - SlaveTx = 0x2, - /// Slave receiver - SlaveRx = 0x3, - }; - - pub const MONO = enum(u1) { - /// Stereo mode - Stereo = 0x0, - /// Mono mode - Mono = 0x1, - }; - - pub const MUTEVAL = enum(u1) { - /// Bit value 0 is sent during the mute mode - SendZero = 0x0, - /// Last values are sent during the mute mode - SendLast = 0x1, - }; - - pub const NODIV = enum(u1) { - /// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value - MasterClock = 0x0, - /// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. - NoDiv = 0x1, - }; - - pub const OUTDRIV = enum(u1) { - /// Audio block output driven when SAIEN is set - OnStart = 0x0, - /// Audio block output driven immediately after the setting of this bit - Immediately = 0x1, - }; - - pub const PRTCFG = enum(u2) { - /// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol - Free = 0x0, - /// SPDIF protocol - Spdif = 0x1, - /// AC’97 protocol - Ac97 = 0x2, - _, - }; - - pub const SLOTEN = enum(u16) { - /// Inactive slot - Inactive = 0x0, - /// Active slot - Active = 0x1, - _, - }; - - pub const SLOTSZ = enum(u2) { - /// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) - DataSize = 0x0, - /// 16-bit - Bit16 = 0x1, - /// 32-bit - Bit32 = 0x2, - _, - }; - - pub const SYNCEN = enum(u2) { - /// audio sub-block in asynchronous mode - Asynchronous = 0x0, - /// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode - Internal = 0x1, - /// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode - External = 0x2, - _, - }; - - pub const WCKCFG = enum(u1) { - /// Clock configuration is correct - Correct = 0x0, - /// Clock configuration does not respect the rule concerning the frame length specification - Wrong = 0x1, - }; - - /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - pub const CH = extern struct { - /// Configuration register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// SAIx audio block mode immediately - MODE: packed union { - raw: u2, - value: MODE, - }, - /// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. - PRTCFG: packed union { - raw: u2, - value: PRTCFG, - }, - reserved5: u1, - /// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. - DS: packed union { - raw: u3, - value: DS, - }, - /// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. - LSBFIRST: packed union { - raw: u1, - value: LSBFIRST, - }, - /// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. - CKSTR: packed union { - raw: u1, - value: CKSTR, - }, - /// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. - SYNCEN: packed union { - raw: u2, - value: SYNCEN, - }, - /// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. - MONO: packed union { - raw: u1, - value: MONO, - }, - /// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. - OUTDRIV: packed union { - raw: u1, - value: OUTDRIV, - }, - reserved16: u2, - /// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. - SAIEN: u1, - /// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. - DMAEN: u1, - reserved19: u1, - /// No fixed divider between MCLK and FS - NODIV: packed union { - raw: u1, - value: NODIV, - }, - /// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: - MCKDIV: u6, - /// Oversampling ratio for master clock - OSR: u1, - /// Master clock generation enable - MCKEN: u1, - padding: u4, + /// JPEG HuffSymb tables + HUFFBASE15: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// Configuration register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// FIFO threshold. This bit is set and cleared by software. - FTH: packed union { - raw: u3, - value: FTH, - }, - /// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. - FFLUSH: u1, - /// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. - TRIS: u1, - /// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. - MUTE: u1, - /// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. - MUTEVAL: packed union { - raw: u1, - value: MUTEVAL, - }, - /// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. - MUTECNT: u6, - /// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. - CPL: packed union { - raw: u1, - value: CPL, - }, - /// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. - COMP: packed union { - raw: u2, - value: COMP, - }, - padding: u16, + /// JPEG HuffSymb tables + HUFFBASE16: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// This register has no meaning in AC97 and SPDIF audio protocol - FRCR: mmio.Mmio(packed struct(u32) { - /// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. - FRL: u8, - /// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. - FSALL: u7, - reserved16: u1, - /// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. - FSDEF: u1, - /// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - FSPOL: packed union { - raw: u1, - value: FSPOL, - }, - /// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - FSOFF: packed union { - raw: u1, - value: FSOFF, - }, - padding: u13, + /// JPEG HuffSymb tables + HUFFBASE17: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// This register has no meaning in AC97 and SPDIF audio protocol - SLOTR: mmio.Mmio(packed struct(u32) { - /// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - FBOFF: u5, - reserved6: u1, - /// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - SLOTSZ: packed union { - raw: u2, - value: SLOTSZ, - }, - /// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - NBSLOT: u4, - reserved16: u4, - /// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - SLOTEN: packed union { - raw: u16, - value: SLOTEN, - }, + /// JPEG HuffSymb tables + HUFFBASE18: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// Interrupt mask register 2 - IM: mmio.Mmio(packed struct(u32) { - /// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. - OVRUDRIE: u1, - /// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. - MUTEDETIE: u1, - /// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. - WCKCFGIE: u1, - /// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, - FREQIE: u1, - /// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. - CNRDYIE: u1, - /// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. - AFSDETIE: u1, - /// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. - LFSDETIE: u1, - padding: u25, + /// JPEG HuffSymb tables + HUFFBASE19: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. - OVRUDR: u1, - /// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. - MUTEDET: u1, - /// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. - WCKCFG: packed union { - raw: u1, - value: WCKCFG, - }, - /// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. - FREQ: u1, - /// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. - CNRDY: packed union { - raw: u1, - value: CNRDY, - }, - /// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. - AFSDET: u1, - /// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register - LFSDET: u1, - reserved16: u9, - /// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: - FLVL: packed union { - raw: u3, - value: FLVL, - }, - padding: u13, + /// JPEG HuffSymb tables + HUFFBASE20: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// Clear flag register - CLRFR: mmio.Mmio(packed struct(u32) { - /// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. - COVRUDR: u1, - /// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. - CMUTEDET: u1, - /// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. - CWCKCFG: u1, - reserved4: u1, - /// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. - CCNRDY: u1, - /// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. - CAFSDET: u1, - /// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. - CLFSDET: u1, - padding: u25, + /// JPEG HuffSymb tables + HUFFBASE21: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// Data register - DR: mmio.Mmio(packed struct(u32) { - /// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. - DATA: u32, + /// JPEG HuffSymb tables + HUFFBASE22: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - }; - - /// Serial audio interface - pub const SAI = extern struct { - /// Global configuration register - GCR: mmio.Mmio(packed struct(u32) { - /// Synchronization inputs - SYNCIN: u2, - reserved4: u2, - /// Synchronization outputs These bits are set and cleared by software. - SYNCOUT: u2, - padding: u26, + /// JPEG HuffSymb tables + HUFFBASE23: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - CH: u32, - reserved68: [60]u8, - /// PDM control register - PDMCR: mmio.Mmio(packed struct(u32) { - /// PDM enable - PDMEN: u1, - reserved4: u3, - /// Number of microphones - MICNBR: u2, - reserved8: u2, - /// Clock enable of bitstream clock number 1 - CKEN: u1, - padding: u23, + /// JPEG HuffSymb tables + HUFFBASE24: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// PDM delay register - PDMDLY: mmio.Mmio(packed struct(u32) { - /// Delay line adjust for first microphone of pair 1 - DLYML: u3, - reserved4: u1, - /// Delay line adjust for second microphone of pair 1 - DLYMR: u3, - padding: u25, + /// JPEG HuffSymb tables + HUFFBASE25: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - }; - }; - - pub const rcc_wba = struct { - pub const ADCSEL = enum(u3) { - /// hclk4 clock selected - HCLK4 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// pll1pclk selected - PLL1_P = 0x2, - /// HSE clock selected - HSE = 0x3, - /// HSI clock selected - HSI = 0x4, - _, - }; - - pub const HDIV5 = enum(u1) { - /// hclk5 = SYSCLK not divided - Div1 = 0x0, - /// hclk5 = SYSCLK divided by 2 - Div2 = 0x1, - }; - - pub const HPRE = enum(u3) { - /// DCLK not divided - Div1 = 0x0, - /// hclk = SYSCLK divided by 2 - Div2 = 0x4, - /// hclk = SYSCLK divided by 4 - Div4 = 0x5, - /// hclk = SYSCLK divided by 8 - Div8 = 0x6, - /// hclk = SYSCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const HPRE5 = enum(u3) { - /// DCLK not divided - Div1 = 0x0, - /// hclk5 = SYSCLK divided by 2 - Div2 = 0x4, - /// hclk5 = SYSCLK divided by 3 - Div3 = 0x5, - /// hclk5 = SYSCLK divided by 4 - Div4 = 0x6, - /// hclk5 = SYSCLK divided by 6 - Div6 = 0x7, - _, - }; - - pub const HSEPRE = enum(u1) { - /// HSE not divided, SYSCLK = HSE - Div1 = 0x0, - /// HSE divided, SYSCLK = HSE/2 - Div2 = 0x1, - }; - - pub const I2C1SEL = enum(u2) { - /// pclk1 selected - PCLK1 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - _, - }; - - pub const I2C3SEL = enum(u2) { - /// pclk7 selected - PCLK7 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - _, - }; - - pub const LPTIM1SEL = enum(u2) { - /// pclk7 selected. - PCLK7 = 0x0, - /// LSI selected - LSI = 0x1, - /// HSI selected - HSI = 0x2, - /// LSE selected - LSE = 0x3, - }; - - pub const LPTIM2SEL = enum(u2) { - /// pclk7 selected. - PCLK1 = 0x0, - /// LSI selected - LSI = 0x1, - /// HSI selected - HSI = 0x2, - /// LSE selected - LSE = 0x3, - }; - - pub const LPUARTSEL = enum(u2) { - /// pclk7 selected - PCLK7 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - /// LSE selected - LSE = 0x3, - }; - - pub const LSCOSEL = enum(u1) { - /// LSI clock selected - LSI = 0x0, - /// LSE clock selected - LSE = 0x1, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const LSETRIM = enum(u2) { - /// current source resistance 5/4 x R - R5_4 = 0x0, - /// current source resistance R - R = 0x1, - /// current source resistance 3/4 x R - R3_4 = 0x2, - /// current source resistance 2/3 x R - R2_3 = 0x3, - }; - - pub const LSIPREDIV = enum(u1) { - /// LSI not divided - Div1 = 0x0, - /// LSI divided by 128 - Div128 = 0x1, - }; - - pub const MCOPRE = enum(u3) { - /// MCO divided by 1 - Div1 = 0x0, - /// MCO divided by 2 - Div2 = 0x1, - /// MCO divided by 4 - Div4 = 0x2, - /// MCO divided by 8 - Div8 = 0x3, - /// MCO divided by 16 - Div16 = 0x4, - _, - }; - - pub const MCOSEL = enum(u4) { - /// MCO output disabled, no clock on MCO - DISABLED = 0x0, - /// sysclkpre system clock after PLL1RCLKPRE division selected - SYSCLKPRE = 0x1, - /// HSI clock selected - HSI = 0x3, - /// HSE clock selected - HSE = 0x4, - /// pll1rclk clock selected - PLL1_R = 0x5, - /// LSI clock selected - LSI = 0x6, - /// LSE clock selected - LSE = 0x7, - /// pll1pclk clock selected - PLL1_P = 0x8, - /// pll1qclk clock selected - PLL1_Q = 0x9, - /// hclk5 clock selected - HCLK5 = 0xa, - _, - }; - - pub const PLLRCLKPRE = enum(u1) { - /// pll1rclk not divided, sysclkpre = pll1rclk - Div1 = 0x0, - /// pll1rclk divided, sysclkpre = pll1rclk divided - Divided = 0x1, - }; - - pub const PLLRCLKPRESTEP = enum(u1) { - /// pll1rclk 2-step division - STEP2 = 0x0, - /// pll1rclk 3-step division - STEP3 = 0x1, - }; - - pub const PLLRGE = enum(u2) { - /// PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz - FREQ_4TO8MHZ = 0x0, - /// PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz - FREQ_8TO16MHZ = 0x3, - _, - }; - - pub const PLLSRC = enum(u2) { - /// no clock sent to PLL1 - DISABLE = 0x0, - /// HSI clock selected as PLL1 clock entry - HSI = 0x2, - /// HSE clock after HSEPRE divider selected as PLL1 clock entry - HSE = 0x3, - _, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const RADIOSTSEL = enum(u2) { - /// no clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled - DISABLE = 0x0, - /// LSE oscillator clock selected - LSE = 0x1, - /// HSE oscillator clock divided by 1000 selected - HSE = 0x3, - _, - }; - - pub const RNGSEL = enum(u2) { - /// LSE selected - LSE = 0x0, - /// LSI selected - LSI = 0x1, - /// HSI selected - HSI = 0x2, - /// pll1qclk divide by 2 selected - PLL1_Q = 0x3, - }; - - pub const RTCSEL = enum(u2) { - /// no clock selected, RTC and TAMP kernel clock disabled - DISABLE = 0x0, - /// LSE oscillator clock selected, and enabled - LSE = 0x1, - /// LSI oscillator clock selected, and enabled - LSI = 0x2, - /// HSE oscillator clock divided by 32 selected, and enabled - HSE = 0x3, - }; - - pub const SPI1SEL = enum(u2) { - /// pclk2 selected - PCLK2 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - _, - }; - - pub const SPI3SEL = enum(u2) { - /// pclk2 selected - PCLK7 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - _, - }; - - pub const SW = enum(u2) { - /// HSI selected as system clock - HSI = 0x0, - /// HSE or HSE/2, as defined by HSEPRE, selected as system clock - HSE = 0x2, - /// pll1rclk selected as system clock - PLL1_R = 0x3, - _, - }; - - pub const SYSTICKSEL = enum(u2) { - /// hclk1 divided by 8 selected - HCLK1_DIV_8 = 0x0, - /// LSI selected - LSI = 0x1, - /// LSE selected - LSE = 0x2, - _, - }; - - pub const TIMICSEL = enum(u1) { - /// HSI divider disabled - HSI = 0x0, - /// HSI/256 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture - HSI_DIV_256 = 0x1, - }; - - pub const USART1SEL = enum(u2) { - /// pclk2 selected - PCLK2 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - /// LSE selected - LSE = 0x3, - }; - - pub const USARTSEL = enum(u2) { - /// pclk1 selected - PCLK1 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - /// LSE selected - LSE = 0x3, - }; - - /// Reset and clock control - pub const RCC = extern struct { - /// RCC clock control register - CR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// HSI clock enable Set and cleared by software. Cleared by hardware when entering Stop and Standby modes. Set by hardware to force the HSI oscillator on when exiting Stop and Standby modes. Set by hardware to force the HSI oscillator on in case of clock security failure of the HSE crystal oscillator. This bit is set by hardware if the HSI is used directly or indirectly as system clock. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSION: u1, - /// HSI enable for some peripheral kernels Set and cleared by software to force HSI oscillator on even in Stop modes. Keeping the HSI oscillator on in Stop modes allows the communication speed not to be reduced by the HSI oscillator startup time. This bit has no effect on register bit HSION value. Cleared by hardware when entering Standby modes. Refer to Peripherals clock gating and autonomous mode for more details. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSIKERON: u1, - /// HSI clock ready flag Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI clock cycles. - HSIRDY: u1, - reserved16: u5, - /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE clock for the CPU when entering Stop and Standby modes and on a HSECSS failure. When the HSE is used as 2.4 GHz RADIO kernel clock, enabled by RADIOEN and RADIOSMEN and the 2.4 GHz RADIO is active, HSEON is not be cleared when entering low power mode. In this case only Stop 0 mode is entered as low power mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSEON: u1, - /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. This bit is set both when HSE is enabled by software by setting HSEON and when requested as kernel clock by the 2.4 GHz RADIO. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSERDY: u1, - reserved19: u1, - /// HSE clock security system enable Set by software to enable the HSE clock security system. When HSECSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSECSSON: u1, - /// HSE clock for SYSCLK prescaler Set and cleared by software to control the division factor of the HSE clock for SYSCLK. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSEPRE: packed union { - raw: u1, - value: HSEPRE, - }, - reserved24: u3, - /// PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop or Standby modes and when PLL1 on HSE is selected as sysclk, on a HSECSS failure. This bit cannot be reset if the PLL1 clock is used as the system clock. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - PLLON: u1, - /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - PLLRDY: u1, - padding: u6, + /// JPEG HuffSymb tables + HUFFBASE26: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - reserved16: [12]u8, - /// RCC internal clock sources calibration register 3 - ICSCR3: mmio.Mmio(packed struct(u32) { - /// HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration value. When HSITRIM[4:0] is written, HSICAL[11:0] is updated with the sum of HSITRIM[4:0] and the initial factory trim value. - HSICAL: u12, - reserved16: u4, - /// HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI. - HSITRIM: u5, - padding: u11, + /// JPEG HuffSymb tables + HUFFBASE27: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - reserved28: [8]u8, - /// RCC clock configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// system clock switch Set and cleared by software to select system clock source (SYSCLK). Cleared by hardware when entering Stop and Standby modes When selecting HSE directly or indirectly as system clock and HSE oscillator clock security fails, cleared by hardware. - SW: packed union { - raw: u2, - value: SW, - }, - /// system clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. - SWS: packed union { - raw: u2, - value: SW, - }, - reserved24: u20, - /// microcontroller clock output Set and cleared by software. others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. - MCOSEL: packed union { - raw: u4, - value: MCOSEL, - }, - /// microcontroller clock output prescaler Set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. others: not allowed - MCOPRE: packed union { - raw: u3, - value: MCOPRE, - }, - padding: u1, + /// JPEG HuffSymb tables + HUFFBASE28: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// RCC clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// AHB1, AHB2 and AHB4 prescaler Set and cleared by software to control the division factor of the AHB1, AHB2 and AHB4 clock (hclk1). The software must limit the incremental frequency step by setting these bits correctly to ensure that the hclk1 maximum incremental frequency step does not exceed the maximum allowed incremental frequency step (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xx: hclk1 = SYSCLK not divided - HPRE: packed union { - raw: u3, - value: HPRE, - }, - reserved4: u1, - /// APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (pclk1). 0xx: pclk1 = hclk1 not divided - PPRE1: packed union { - raw: u3, - value: PPRE, - }, - reserved8: u1, - /// APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (pclk2). 0xx: pclk2 = hclk1 not divided - PPRE2: packed union { - raw: u3, - value: PPRE, - }, - padding: u21, + /// JPEG HuffSymb tables + HUFFBASE29: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// RCC clock configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// APB7 prescaler Set and cleared by software to control the division factor of the APB7 clock (pclk7). 0xx: hclk1 not divided - PPRE7: packed union { - raw: u3, - value: PPRE, - }, - padding: u25, + /// JPEG HuffSymb tables + HUFFBASE30: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - /// RCC PLL1 configuration register - PLL1CFGR: mmio.Mmio(packed struct(u32) { - /// PLL1 entry clock source Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled. Cleared by hardware when entering Stop or Standby modes. Note: In order to save power, when no PLL1 clock is used, the value of PLL1SRC must be 0. - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - /// PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz - PLLRGE: packed union { - raw: u2, - value: PLLRGE, - }, - /// PLL1 fractional latch enable Set and reset by software to latch the content of PLL1FRACN into the ΣΔ modulator. In order to latch the PLL1FRACN value into the ΣΔ modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL1 initialization phase for details). - PLLFRACEN: u1, - reserved8: u3, - /// Prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLM: u3, - reserved16: u5, - /// PLL1 DIVP divider output enable Set and reset by software to enable the pll1pclk output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1pclk is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). - PLLPEN: u1, - /// PLL1 DIVQ divider output enable Set and reset by software to enable the pll1qclk output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1qclk is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). - PLLQEN: u1, - /// PLL1 DIVR divider output enable Set and cleared by software to enable the pll1rclk output of the PLL1. To save power, PLL1REN and PLL1R bits must be set to 0 when the pll1rclk is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). - PLLREN: u1, - reserved20: u1, - /// pll1rclk clock for SYSCLK prescaler division enable Set and cleared by software to control the division of the pll1rclk clock for SYSCLK. - PLLRCLKPRE: packed union { - raw: u1, - value: PLLRCLKPRE, - }, - /// pll1rclk clock for SYSCLK prescaler division step selection Set and cleared by software to control the division step of the pll1rclk clock for SYSCLK. - PLLRCLKPRESTEP: packed union { - raw: u1, - value: PLLRCLKPRESTEP, - }, - /// pll1rclkpre not divided ready. Set by hardware after PLL1RCLKPRE has been set from divided to not divide, to indicate that the pll1rclk not divided is available on sysclkpre. - PLLRCLKPRERDY: u1, - padding: u9, + /// JPEG HuffSymb tables + HUFFBASE31: mmio.Mmio(packed struct(u32) { + /// HuffBase RAM + HuffBase_RAM_0: u9, + reserved16: u7, + /// HuffBase RAM + HuffBase_RAM_1: u9, + padding: u7, }), - reserved52: [8]u8, - /// RCC PLL1 dividers register - PLL1DIVR: mmio.Mmio(packed struct(u32) { - /// Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... others: reserved VCO output frequency = Fref1_ck x multiplication factor for PLL1 VCO, when fractional value 0 has been loaded into PLL1FRACN, with: Multiplication factor for PLL1 VCO between 4 and 512 input frequency Fref1_ck between 4 and 16�MHz - PLLN: u9, - /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1pclk clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... - PLLP: u7, - /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the PLl1QCLK clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLQ: u7, - reserved24: u1, - /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1rclk clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLR: u7, - padding: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB0: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC PLL1 fractional divider register - PLL1FRACR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x [multiplication factor for PLL1 VCO + (PLL1FRACN / 213)], with: Multiplication factor for PLL1 VCO must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the used fractional value on-the-fly even if the PLL1 is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1. - PLLFRACN: u13, - padding: u16, + /// JPEG HUFFSYMB tables + HUFFSYMB1: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved80: [20]u8, - /// RCC clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI1 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI1 oscillator stabilization. Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSI1RDYIE: u1, - /// LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSERDYIE: u1, - reserved3: u1, - /// HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSIRDYIE: u1, - /// HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSERDYIE: u1, - reserved6: u1, - /// PLL1 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - PLLRDYIE: u1, - padding: u25, + /// JPEG HUFFSYMB tables + HUFFSYMB2: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI1 ready interrupt flag Set by hardware when the LSI1 clock becomes stable and LSI1RDYIE is set. Cleared by software setting the LSI1RDYC bit. Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSI1RDYF: u1, - /// LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYIE is set. Cleared by software setting the LSERDYC bit. Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSERDYF: u1, - reserved3: u1, - /// HSI ready interrupt flag Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see CR). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Cleared by software setting the HSIRDYC bit. - HSIRDYF: u1, - /// HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSERDYF: u1, - reserved6: u1, - /// PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - PLLRDYF: u1, - reserved10: u3, - /// HSE clock security system interrupt flag Set by hardware when a clock security failure is detected in the HSE oscillator. Cleared by software setting the HSECSSC bit. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSECSSF: u1, - padding: u21, + /// JPEG HUFFSYMB tables + HUFFSYMB3: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI1 ready interrupt clear Writing this bit to 1 clears the LSI1RDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSI1RDYC: u1, - /// LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSERDYC: u1, - reserved3: u1, - /// HSI ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.\ Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSIRDYC: u1, - /// HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSERDYC: u1, - reserved6: u1, - /// PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - PLLRDYC: u1, - reserved10: u3, - /// High speed external clock security system interrupt clear Writing this bit to 1 clears the HSECSSF flag. Writing 0 has no effect. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSECSSC: u1, - padding: u21, + /// JPEG HUFFSYMB tables + HUFFSYMB4: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved96: [4]u8, - /// RCC AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 reset Set and cleared by software. Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPDMA1RST: u1, - reserved12: u11, - /// CRC reset Set and cleared by software. Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - CRCRST: u1, - reserved16: u3, - /// TSC reset Set and cleared by software. Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TSCRST: u1, - padding: u15, + /// JPEG HUFFSYMB tables + HUFFSYMB5: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset Set and cleared by software. Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPIOARST: u1, - /// IO port B reset Set and cleared by software. Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPIOBRST: u1, - /// IO port C reset Set and cleared by software. Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPIOCRST: u1, - reserved7: u4, - /// IO port H reset Set and cleared by software. Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPIOHRST: u1, - reserved16: u8, - /// AES hardware accelerator reset Set and cleared by software. Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - AESRST: u1, - /// Hash reset Set and cleared by software. Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HASHRST: u1, - /// Random number generator reset Set and cleared by software. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - RNGRST: u1, - /// SAES hardware accelerator reset Set and cleared by software. Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SAESRST: u1, - /// HSEM hardware accelerator reset Set and cleared by software. Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSEMRST: u1, - /// PKA reset Set and cleared by software. Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - PKARST: u1, - padding: u10, + /// JPEG HUFFSYMB tables + HUFFSYMB6: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved108: [4]u8, - /// RCC AHB4 peripheral reset register - AHB4RSTR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// ADC4 reset Set and cleared by software. Access can be secred by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - ADC4RST: u1, - padding: u26, + /// JPEG HUFFSYMB tables + HUFFSYMB7: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC AHB5 peripheral reset register - AHB5RSTR: mmio.Mmio(packed struct(u32) { - /// 2.4 GHz RADIO reset Set and cleared by software. Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - RADIORST: u1, - padding: u31, + /// JPEG HUFFSYMB tables + HUFFSYMB8: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC APB1 peripheral reset register 1 - APB1RSTR1: mmio.Mmio(packed struct(u32) { - /// TIM2 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM2RST: u1, - /// TIM3 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM3RST: u1, - reserved17: u15, - /// USART2 reset Set and cleared by software. Access can be secured by GTZC_TZSC UART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - USART2RST: u1, - reserved21: u3, - /// I2C1 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - I2C1RST: u1, - padding: u10, + /// JPEG HUFFSYMB tables + HUFFSYMB9: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC APB1 peripheral reset register 2 - APB1RSTR2: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// LPTIM2 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LPTIM2RST: u1, - padding: u26, + /// JPEG HUFFSYMB tables + HUFFSYMB10: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM1RST: u1, - /// SPI1 reset Set and cleared by software. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SPI1RST: u1, - reserved14: u1, - /// USART1 reset Set and cleared by software. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - USART1RST: u1, - reserved17: u2, - /// TIM16 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM16RST: u1, - /// TIM17 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM17RST: u1, - padding: u13, + /// JPEG HUFFSYMB tables + HUFFSYMB11: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC APB7 peripheral reset register - APB7RSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG reset Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SYSCFGRST: u1, - reserved5: u3, - /// SPI3 reset Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SPI3RST: u1, - /// LPUART1 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LPUART1RST: u1, - /// I2C3 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - I2C3RST: u1, - reserved11: u3, - /// LPTIM1 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LPTIM1RST: u1, - padding: u20, + /// JPEG HUFFSYMB tables + HUFFSYMB12: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved136: [4]u8, - /// RCC AHB1 peripheral clock enable register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 bus clock enable Set and cleared by software. Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPDMA1EN: u1, - reserved8: u7, - /// FLASH bus clock enable Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode. Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - FLASHEN: u1, - reserved12: u3, - /// CRC bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - CRCEN: u1, - reserved16: u3, - /// Touch sensing controller bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TSCEN: u1, - /// RAMCFG bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - RAMCFGEN: u1, - reserved24: u6, - /// GTZC1 bus clock enable Set and reset by software. Can only be accessed secure when device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GTZC1EN: u1, - reserved31: u6, - /// SRAM1 bus clock enable Set and reset by software. Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SRAM1EN: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB13: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC AHB2 peripheral clock enable register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// IO port A bus clock enable Set and cleared by software. Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPIOAEN: u1, - /// IO port B bus clock enable Set and cleared by software. Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPIOBEN: u1, - /// IO port C bus clock enable Set and cleared by software. Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPIOCEN: u1, - reserved7: u4, - /// IO port H bus clock enable Set and cleared by software. Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPIOHEN: u1, - reserved16: u8, - /// AES bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - AESEN: u1, - /// HASH bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HASHEN: u1, - /// RNG bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - RNGEN: u1, - /// SAES bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SAESEN: u1, - /// HSEM bus clock enable Set and cleared by software. Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HSEMEN: u1, - /// PKA bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - PKAEN: u1, - reserved30: u8, - /// SRAM2 bus clock enable Set and cleared by software. Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SRAM2EN: u1, - padding: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB14: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved148: [4]u8, - /// RCC AHB4 peripheral clock enable register - AHB4ENR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// PWR bus clock enable Set and cleared by software. Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - PWREN: u1, - reserved5: u2, - /// ADC4 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - ADC4EN: u1, - padding: u26, + /// JPEG HUFFSYMB tables + HUFFSYMB15: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC AHB5 peripheral clock enable register - AHB5ENR: mmio.Mmio(packed struct(u32) { - /// 2.4 GHz RADIO bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Before accessing the 2.4 GHz RADIO sleep timers registers the RADIOCLKRDY bit must be checked. Note: When RADIOSMEN and STRADIOCLKON are both cleared, RADIOCLKRDY bit must be re-checked when exiting low-power modes (Sleep and Stop). - RADIOEN: u1, - padding: u31, + /// JPEG HUFFSYMB tables + HUFFSYMB16: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC APB1 peripheral clock enable register 1 - APB1ENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM2EN: u1, - /// TIM3 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM3EN: u1, - reserved11: u9, - /// WWDG bus clock enable Set by software to enable the window watchdog bus clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - WWDGEN: u1, - reserved17: u5, - /// USART2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC USART2SEC When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.. - USART2EN: u1, - reserved21: u3, - /// I2C1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - I2C1EN: u1, - padding: u10, + /// JPEG HUFFSYMB tables + HUFFSYMB17: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC APB1 peripheral clock enable register 2 - APB1ENR2: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// LPTIM2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LPTIM2EN: u1, - padding: u26, + /// JPEG HUFFSYMB tables + HUFFSYMB18: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC APB2 peripheral clock enable register - APB2ENR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM1EN: u1, - /// SPI1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SPI1EN: u1, - reserved14: u1, - /// USART1bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - USART1EN: u1, - reserved17: u2, - /// TIM16 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM16EN: u1, - /// TIM17 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM17EN: u1, - padding: u13, + /// JPEG HUFFSYMB tables + HUFFSYMB19: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC APB7 peripheral clock enable register - APB7ENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG bus clock enable Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SYSCFGEN: u1, - reserved5: u3, - /// SPI3 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SPI3EN: u1, - /// LPUART1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LPUART1EN: u1, - /// I2C3 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - I2C3EN: u1, - reserved11: u3, - /// LPTIM1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LPTIM1EN: u1, - reserved21: u9, - /// RTC and TAMP bus clock enable Set and cleared by software. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - RTCAPBEN: u1, - padding: u10, - }), - reserved176: [4]u8, - /// RCC AHB1 peripheral clocks enable in Sleep and Stop modes register - AHB1SMENR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - GPDMA1SMEN: u1, - reserved8: u7, - /// FLASH bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - FLASHSMEN: u1, - reserved12: u3, - /// CRC bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - CRCSMEN: u1, - reserved16: u3, - /// TSC bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.. - TSCSMEN: u1, - /// RAMCFG bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - RAMCFGSMEN: u1, - reserved24: u6, - /// GTZC1 bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GTZC1SMEN: u1, - reserved29: u4, - /// ICACHE bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC ICACHE_REGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.. - ICACHESMEN: u1, - reserved31: u1, - /// SRAM1 bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SRAM1SMEN: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB20: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC AHB2 peripheral clocks enable in Sleep and Stop modes register - AHB2SMENR: mmio.Mmio(packed struct(u32) { - /// IO port A bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPIOASMEN: u1, - /// IO port B bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPIOBSMEN: u1, - /// IO port C bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPIOCSMEN: u1, - reserved7: u4, - /// IO port H bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - GPIOHSMEN: u1, - reserved16: u8, - /// AES bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - AESSMEN: u1, - /// HASH bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - HASHSMEN: u1, - /// Random number generator (RNG) bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - RNGSMEN: u1, - /// SAES accelerator bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SAESSMEN: u1, - reserved21: u1, - /// PKA bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - PKASMEN: u1, - reserved30: u8, - /// SRAM2 bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SRAM2SMEN: u1, - padding: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB21: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved188: [4]u8, - /// RCC AHB4 peripheral clocks enable in Sleep and Stop modes register - AHB4SMENR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// PWR bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - PWRSMEN: u1, - reserved5: u2, - /// ADC4 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - ADC4SMEN: u1, - padding: u26, + /// JPEG HUFFSYMB tables + HUFFSYMB22: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC AHB5 peripheral clocks enable in Sleep and Stop modes register - AHB5SMENR: mmio.Mmio(packed struct(u32) { - /// 2.4 GHz RADIO bus clock enable during Sleep and Stop modes when the 2.4 GHz RADIO is active. Set and cleared by software. Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - RADIOSMEN: u1, - padding: u31, + /// JPEG HUFFSYMB tables + HUFFSYMB23: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1 - APB1SMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM2SMEN: u1, - /// TIM3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM3SMEN: u1, - reserved11: u9, - /// Window watchdog bus clock enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated. Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - WWDGSMEN: u1, - reserved17: u5, - /// USART2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - USART2SMEN: u1, - reserved21: u3, - /// I2C1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - I2C1SMEN: u1, - padding: u10, + /// JPEG HUFFSYMB tables + HUFFSYMB24: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 - APB1SMENR2: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// LPTIM2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPTIM2SMEN: u1, - padding: u26, + /// JPEG HUFFSYMB tables + HUFFSYMB25: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC APB2 peripheral clocks enable in Sleep and Stop modes register - APB2SMENR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM1SMEN: u1, - /// SPI1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - SPI1SMEN: u1, - reserved14: u1, - /// USART1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - USART1SMEN: u1, - reserved17: u2, - /// TIM16 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM16SMEN: u1, - /// TIM17 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - TIM17SMEN: u1, - padding: u13, + /// JPEG HUFFSYMB tables + HUFFSYMB26: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC APB7 peripheral clock enable in Sleep and Stop modes register - APB7SMENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - SYSCFGSMEN: u1, - reserved5: u3, - /// SPI3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - SPI3SMEN: u1, - /// LPUART1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPUART1SMEN: u1, - /// I2C3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - I2C3SMEN: u1, - reserved11: u3, - /// LPTIM1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPTIM1SMEN: u1, - reserved21: u9, - /// RTC and TAMP APB clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - RTCAPBSMEN: u1, - padding: u10, + /// JPEG HUFFSYMB tables + HUFFSYMB27: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved224: [12]u8, - /// RCC peripherals independent clock configuration register 1 - CCIPR1: mmio.Mmio(packed struct(u32) { - /// USART1 kernel clock source selection This bits are used to select the USART1 kernel clock source. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. - USART1SEL: packed union { - raw: u2, - value: USART1SEL, - }, - /// USART2 kernel clock source selection This bits are used to select the USART2 kernel clock source. Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. - USART2SEL: packed union { - raw: u2, - value: USARTSEL, - }, - reserved10: u6, - /// I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI. - I2C1SEL: packed union { - raw: u2, - value: I2C1SEL, - }, - reserved18: u6, - /// Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1. - LPTIM2SEL: packed union { - raw: u2, - value: LPTIM2SEL, - }, - /// SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI. - SPI1SEL: packed union { - raw: u2, - value: SPI1SEL, - }, - /// SysTick clock source selection These bits are used to select the SysTick clock source. Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one hclk1 cycle is introduced, due to the LSE or LSI sampling with hclk1 in the SysTick circuitry. - SYSTICKSEL: packed union { - raw: u2, - value: SYSTICKSEL, - }, - reserved31: u7, - /// Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture When the TIMICSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI/256. When TIMICSEL is cleared, the HSI, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture. Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The clock division must be disabled (TIMICSEL configured to 0) before selecting or changing a clock sources division. - TIMICSEL: packed union { - raw: u1, - value: TIMICSEL, - }, + /// JPEG HUFFSYMB tables + HUFFSYMB28: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC peripherals independent clock configuration register 2 - CCIPR2: mmio.Mmio(packed struct(u32) { - reserved12: u12, - /// RNGSEL kernel clock source selection These bits allow to select the RNG kernel clock source. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - RNGSEL: packed union { - raw: u2, - value: RNGSEL, - }, - padding: u18, + /// JPEG HUFFSYMB tables + HUFFSYMB29: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC peripherals independent clock configuration register 3 - CCIPR3: mmio.Mmio(packed struct(u32) { - /// LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The LPUART1 is functional in Stop modes only when the kernel clock is HSI or LSE. - LPUART1SEL: packed union { - raw: u2, - value: LPUARTSEL, - }, - reserved3: u1, - /// SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The SPI3 is functional in Stop modes only when the kernel clock is HSI. - SPI3SEL: packed union { - raw: u2, - value: SPI3SEL, - }, - reserved6: u1, - /// I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The I2C3 is functional in Stop modes only when the kernel clock is HSI - I2C3SEL: packed union { - raw: u2, - value: I2C3SEL, - }, - reserved10: u2, - /// LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The LPTIM1 is functional in Stop modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1. - LPTIM1SEL: packed union { - raw: u2, - value: LPTIM1SEL, - }, - /// ADC4 kernel clock source selection These bits are used to select the ADC4 kernel clock source. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. others: reserved Note: The ADC4 is functional in Stop modes only when the kernel clock is HSI. - ADCSEL: packed union { - raw: u3, - value: ADCSEL, - }, - padding: u17, + /// JPEG HUFFSYMB tables + HUFFSYMB30: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved240: [4]u8, - /// RCC backup domain control register - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enable Set and cleared by software. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSEON: u1, - /// LSE oscillator ready Set and cleared by hardware to indicate when the external 32�kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSERDY: u1, - /// LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32�kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSEBYP: u1, - /// LSE oscillator drive capability Set by software to modulate the drive capability of the LSE oscillator. LSEDRV must be programmed to a different value than 0 before enabling the LSE oscillator in ‘Xtal’ mode. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The oscillator is in ‘Xtal mode’ when it is not in bypass mode. - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// Low speed external clock security enable Set by software to enable the LSECSS. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware) and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD�=�1). In that case, the software must disable the LSECSSON bit. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSECSSON: u1, - /// Low speed external clock security, LSE failure Detection Set by hardware to indicate when a failure is detected by the LSECCS on the external 32�kHz oscillator. Reset when LSCSSON bit is cleared. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSECSSD: u1, - /// LSE system clock (LSESYS) enable Set by software to enable the LSE system clock generated by RCC. The lsesys clock is used for peripherals (USART, LPUART, LPTIM, RNG, 2.4 GHz RADIO) and functions (LSCO, MCO, TIM triggers, LPTIM trigger) excluding the RTC, TAMP and LSECSS. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSESYSEN: u1, - /// RTC and TAMP kernel clock source enable and selection Set by software to enable and select the clock source for the RTC. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved11: u1, - /// LSE system clock (LSESYS) ready Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSESYSRDY: u1, - /// LSE clock glitch filter enable Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0). Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSEGFON: u1, - /// LSE trimming These bits are initialized at startup and after OBL_LAUNCH with SBF cleared with the factory-programmed LSE calibration value. Set and cleared by software. These bits must be modified only once after a BOR reset or an OBL_LAUNCH and before enabling LSE with LSEON (when both LSEON = 0 and LSERDY�= 0). Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: OBL_LAUNCH of this field occurs only when SBF is cleared and must then only be started by software when LSE oscillator is disabled, LSEON = 0 and LSERDY = 0. - LSETRIM: packed union { - raw: u2, - value: LSETRIM, - }, - reserved16: u1, - /// Backup domain software reset Set and cleared by software. Can only be accessed secure when one or more features in the RTC or TAMP is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - BDRST: u1, - reserved18: u1, - /// 2.4 GHz RADIO sleep timer kernel clock enable and selection Set and cleared by software. Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - RADIOSTSEL: packed union { - raw: u2, - value: RADIOSTSEL, - }, - reserved24: u4, - /// Low-speed clock output (LSCO) enable Set and cleared by software. Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSCOEN: u1, - /// Low-speed clock output selection Set and cleared by software. Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSCOSEL: packed union { - raw: u1, - value: LSCOSEL, - }, - /// LSI1 oscillator enable Set and cleared by software. Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSI1ON: u1, - /// LSI1 oscillator ready Set and cleared by hardware to indicate when the LSI1 oscillator is stable. After the LSI1ON bit is cleared, LSI1RDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI1 is used by IWDG or RTC, even if LSI1ON = 0. Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSI1RDY: u1, - /// LSI1 Low-speed clock divider configuration Set and cleared by software to enable the LSI1 division. This bit can be written only when the LSI1 is disabled (LSI1ON = 0 and LSI1RDY = 0). The LSI1PREDIV cannot be changed if the LSI1 is used by the IWDG or by the RTC. Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - LSI1PREDIV: packed union { - raw: u1, - value: LSIPREDIV, - }, - padding: u3, + /// JPEG HUFFSYMB tables + HUFFSYMB31: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC control/status register - CSR: mmio.Mmio(packed struct(u32) { - reserved23: u23, - /// Remove reset flag Set by software to clear the reset flags. Access can be secured by RCC RMVFSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. - RMVF: u1, - reserved25: u1, - /// Option byte loader reset flag Set by hardware when a reset from the option byte loading occurs. Cleared by writing to the RMVF bit. - OBLRSTF: u1, - /// NRST pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. - PINRSTF: u1, - /// BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit. - BORRSTF: u1, - /// Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. - SFTRSTF: u1, - /// Independent watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit. - IWDGRSTF: u1, - /// Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. - WWDGRSTF: u1, - /// Low-power reset flag Set by hardware when a reset occurs due to illegal Stop and Standby modes entry. Cleared by writing to the RMVF bit. - LPWRRSTF: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB32: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved272: [24]u8, - /// RCC secure configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// HSI clock configuration and status bits security Set and reset by software. - HSISEC: u1, - /// HSE clock configuration bits, status bits and HSECSS security Set and reset by software. - HSESEC: u1, - reserved3: u1, - /// LSI clock configuration and status bits security Set and reset by software. - LSISEC: u1, - /// LSE clock configuration and status bits security Set and reset by software. - LSESEC: u1, - /// SYSCLK selection, clock output on MCO configuration security Set and reset by software. - SYSCLKSEC: u1, - /// AHBx/APBx prescaler configuration bits security Set and reset by software. - PRESCSEC: u1, - /// PLL1 clock configuration and status bits security Set and reset by software. - PLLSEC: u1, - reserved12: u4, - /// Remove reset flag security Set and reset by software. - RMVFSEC: u1, - padding: u19, + /// JPEG HUFFSYMB tables + HUFFSYMB33: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// RCC privilege configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access. - SPRIV: u1, - /// RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure. - NSPRIV: u1, - padding: u30, + /// JPEG HUFFSYMB tables + HUFFSYMB34: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved512: [232]u8, - /// RCC clock configuration register 2 - CFGR4: mmio.Mmio(packed struct(u32) { - /// AHB5 prescaler when SWS select PLL1 Set and cleared by software to control the division factor of the AHB5 clock (hclk5). Must not be changed when SYSCLK source indicated by SWS is PLL1. When SYSCLK source indicated by SWS is not PLL1: HPRE5 is not taken into account. When SYSCLK source indicated by SWS is PLL1: HPRE5 is taken into account, from the moment the system clock switch occurs Depending on the device voltage range, the software must set these bits correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xx: hclk5 = SYSCLK not divided - HPRE5: packed union { - raw: u3, - value: HPRE5, - }, - reserved4: u1, - /// AHB5 divider when SWS select HSI or HSE Set and reset by software. Set to 1 by hardware when entering Stop 1 mode. When SYSCLK source indicated by SWS is HSI or HSE: HDIV5 is taken into account When SYSCLK source indicated by SWS is PLL1: HDIV5 is taken not taken into account Depending on the device voltage range, the software must set this bit correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table�99). After a write operation to this bit and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. - HDIV5: packed union { - raw: u1, - value: HDIV5, - }, - padding: u27, + /// JPEG HUFFSYMB tables + HUFFSYMB35: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved520: [4]u8, - /// RCC RADIO peripheral clock enable register - RADIOENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// 2.4 GHz RADIO baseband kernel clock (aclk) enable Set and cleared by software. Note: The HSE oscillator needs to be enabled by either HSEON or STRADIOCLKON. - BBCLKEN: u1, - reserved16: u14, - /// 2.4 GHz RADIO bus clock enable and HSE oscillator enable by 2.4 GHz RADIO sleep timer wakeup event Set by hardware on a 2.4 GHz RADIO sleep timer wakeup event. Cleared by software writing zero to this bit. Note: Before accessing the 2.4 GHz RADIO registers the RADIOCLKRDY bit must be checked. - STRADIOCLKON: u1, - /// 2.4 GHz RADIO bus clock ready. Set and cleared by hardware to indicate that the 2.4 GHz RADIO bus clock is ready and the 2.4 GHz RADIO registers can be accessed. Note: Once both RADIOEN and STRADIOCLKON are cleared, RADIOCLKRDY goes low after three hclk5 clock cycles. - RADIOCLKRDY: u1, - padding: u14, + /// JPEG HUFFSYMB tables + HUFFSYMB36: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved528: [4]u8, - /// RCC external clock sources calibration register 1 - ECSCR1: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// HSE clock trimming These bits provide user-programmable capacitor trimming value. It can be programmed to adjust the HSE oscillator frequency. - HSETRIM: u6, - padding: u10, + /// JPEG HUFFSYMB tables + HUFFSYMB37: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - }; - }; - - pub const rcc_f3v1 = struct { - pub const ADCPRE = enum(u2) { - /// PCLK divided by 2 - Div2 = 0x0, - /// PCLK divided by 4 - Div4 = 0x1, - /// PCLK divided by 6 - Div6 = 0x2, - /// PCLK divided by 8 - Div8 = 0x3, - }; - - pub const ADCPRES = enum(u5) { - /// PLL clock not divided - Div1 = 0x10, - /// PLL clock divided by 2 - Div2 = 0x11, - /// PLL clock divided by 4 - Div4 = 0x12, - /// PLL clock divided by 6 - Div6 = 0x13, - /// PLL clock divided by 8 - Div8 = 0x14, - /// PLL clock divided by 10 - Div10 = 0x15, - /// PLL clock divided by 12 - Div12 = 0x16, - /// PLL clock divided by 16 - Div16 = 0x17, - /// PLL clock divided by 32 - Div32 = 0x18, - /// PLL clock divided by 64 - Div64 = 0x19, - /// PLL clock divided by 128 - Div128 = 0x1a, - /// PLL clock divided by 256 - Div256 = 0x1b, - _, - }; - - pub const CECSW = enum(u1) { - /// HSI clock divided by 244 selected as CEC clock source - HSI_DIV_244 = 0x0, - /// LSE clock selected as CEC clock source - LSE = 0x1, - }; - - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, - _, - }; - - pub const ICSW = enum(u1) { - /// HSI clock selected as I2C clock source - HSI = 0x0, - /// SYSCLK clock selected as I2C clock source - SYS = 0x1, - }; - - pub const ISSRC = enum(u1) { - /// System clock used as I2S clock source - SYS = 0x0, - /// External clock mapped on the I2S_CKIN pin used as I2S clock source - CKIN = 0x1, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium high driving capability - MediumHigh = 0x1, - /// Medium low driving capability - MediumLow = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCOSEL = enum(u3) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// Internal low speed (LSI) oscillator clock selected - LSI = 0x2, - /// External low speed (LSE) oscillator clock selected - LSE = 0x3, - /// System clock selected - SYS = 0x4, - /// Internal RC 8 MHz (HSI) oscillator clock selected - HSI = 0x5, - /// External 4-32 MHz (HSE) oscillator clock selected - HSE = 0x6, - /// PLL clock divided by 2 - PLL_DIV_2 = 0x7, - _, - }; - - pub const PLLMUL = enum(u4) { - /// PLL input clock x2 - Mul2 = 0x0, - /// PLL input clock x3 - Mul3 = 0x1, - /// PLL input clock x4 - Mul4 = 0x2, - /// PLL input clock x5 - Mul5 = 0x3, - /// PLL input clock x6 - Mul6 = 0x4, - /// PLL input clock x7 - Mul7 = 0x5, - /// PLL input clock x8 - Mul8 = 0x6, - /// PLL input clock x9 - Mul9 = 0x7, - /// PLL input clock x10 - Mul10 = 0x8, - /// PLL input clock x11 - Mul11 = 0x9, - /// PLL input clock x12 - Mul12 = 0xa, - /// PLL input clock x13 - Mul13 = 0xb, - /// PLL input clock x14 - Mul14 = 0xc, - /// PLL input clock x15 - Mul15 = 0xd, - /// PLL input clock x16 - Mul16 = 0xe, - _, - }; - - pub const PLLSRC = enum(u1) { - /// HSI divided by 2 selected as PLL input clock - HSI_Div2 = 0x0, - /// HSE divided by PREDIV selected as PLL input clock - HSE_Div_PREDIV = 0x1, - }; - - pub const PLLXTPRE = enum(u1) { - /// HSE clock not divided - Div1 = 0x0, - /// HSE clock divided by 2 - Div2 = 0x1, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const PREDIV = enum(u4) { - /// PREDIV input clock not divided - Div1 = 0x0, - /// PREDIV input clock divided by 2 - Div2 = 0x1, - /// PREDIV input clock divided by 3 - Div3 = 0x2, - /// PREDIV input clock divided by 4 - Div4 = 0x3, - /// PREDIV input clock divided by 5 - Div5 = 0x4, - /// PREDIV input clock divided by 6 - Div6 = 0x5, - /// PREDIV input clock divided by 7 - Div7 = 0x6, - /// PREDIV input clock divided by 8 - Div8 = 0x7, - /// PREDIV input clock divided by 9 - Div9 = 0x8, - /// PREDIV input clock divided by 10 - Div10 = 0x9, - /// PREDIV input clock divided by 11 - Div11 = 0xa, - /// PREDIV input clock divided by 12 - Div12 = 0xb, - /// PREDIV input clock divided by 13 - Div13 = 0xc, - /// PREDIV input clock divided by 14 - Div14 = 0xd, - /// PREDIV input clock divided by 15 - Div15 = 0xe, - /// PREDIV input clock divided by 16 - Div16 = 0xf, - }; - - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, - }; - - pub const SW = enum(u2) { - /// HSI oscillator used as system clock - HSI = 0x0, - /// HSE oscillator used as system clock - HSE = 0x1, - /// PLL used as system clock - PLL1_P = 0x2, - _, - }; - - pub const TIM2SW = enum(u1) { - /// PCLK2 clock (doubled frequency when prescaled) - PCLK1_TIM = 0x0, - /// PLL vco output (running up to 144 MHz) - PLL1_P = 0x1, - }; - - pub const TIMSW = enum(u1) { - /// PCLK2 clock (doubled frequency when prescaled) - PCLK2_TIM = 0x0, - /// PLL vco output (running up to 144 MHz) - PLL1_P = 0x1, - }; - - pub const USART1SW = enum(u2) { - /// PCLK selected as USART clock source - PCLK2 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, - }; - - pub const USARTSW = enum(u2) { - /// PCLK selected as USART clock source - PCLK1 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, - }; - - pub const USBPRE = enum(u1) { - /// PLL clock is divided by 1.5 - Div1_5 = 0x0, - /// PLL clock is not divided - Div1 = 0x1, - }; - - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal High Speed clock enable - HSION: u1, - /// Internal High Speed clock ready flag - HSIRDY: u1, - reserved3: u1, - /// Internal High Speed clock trimming - HSITRIM: u5, - /// Internal High Speed clock Calibration - HSICAL: u8, - /// External High Speed clock enable - HSEON: u1, - /// External High Speed clock ready flag - HSERDY: u1, - /// External High Speed clock Bypass - HSEBYP: u1, - /// Clock Security System enable - CSSON: u1, - reserved24: u4, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding: u6, + /// JPEG HUFFSYMB tables + HUFFSYMB38: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// Clock configuration register (RCC_CFGR) - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock Switch - SW: packed union { - raw: u2, - value: SW, - }, - /// System Clock Switch Status - SWS: packed union { - raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// APB Low speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, - }, - /// APB high speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, - }, - /// ADC prescaler - ADCPRE: packed union { - raw: u2, - value: ADCPRE, - }, - /// PLL entry clock source - PLLSRC: packed union { - raw: u1, - value: PLLSRC, - }, - /// HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products. - PLLXTPRE: packed union { - raw: u1, - value: PLLXTPRE, - }, - /// PLL Multiplication Factor - PLLMUL: packed union { - raw: u4, - value: PLLMUL, - }, - /// USB prescaler - USBPRE: packed union { - raw: u1, - value: USBPRE, - }, - /// I2S external clock source selection - I2SSRC: packed union { - raw: u1, - value: ISSRC, - }, - /// Microcontroller clock output - MCOSEL: packed union { - raw: u3, - value: MCOSEL, - }, - reserved28: u1, - /// Microcontroller Clock Output Flag. Set and reset by hardware. It is reset by hardware when MCO field is written with a new value. It is set by hardware when the switch to the new MCO source is effective. - MCOF: u1, - padding: u3, + /// JPEG HUFFSYMB tables + HUFFSYMB39: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// Clock interrupt register (RCC_CIR) - CIR: mmio.Mmio(packed struct(u32) { - /// LSI Ready Interrupt flag - LSIRDYF: u1, - /// LSE Ready Interrupt flag - LSERDYF: u1, - /// HSI Ready Interrupt flag - HSIRDYF: u1, - /// HSE Ready Interrupt flag - HSERDYF: u1, - /// PLL Ready Interrupt flag - PLLRDYF: u1, - reserved7: u2, - /// Clock Security System Interrupt flag - CSSF: u1, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1, - /// LSE Ready Interrupt Enable - LSERDYIE: u1, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1, - /// HSE Ready Interrupt Enable - HSERDYIE: u1, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1, - reserved16: u3, - /// LSI Ready Interrupt Clear - LSIRDYC: u1, - /// LSE Ready Interrupt Clear - LSERDYC: u1, - /// HSI Ready Interrupt Clear - HSIRDYC: u1, - /// HSE Ready Interrupt Clear - HSERDYC: u1, - /// PLL Ready Interrupt Clear - PLLRDYC: u1, - reserved23: u2, - /// Clock security system interrupt clear - CSSC: u1, - padding: u8, + /// JPEG HUFFSYMB tables + HUFFSYMB40: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB2 peripheral reset register (RCC_APB2RSTR) - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// SYSCFG and COMP reset - SYSCFGRST: u1, - reserved11: u10, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI 1 reset - SPI1RST: u1, - /// TIM8 timer reset - TIM8RST: u1, - /// USART1 reset - USART1RST: u1, - /// SPI4 reset - SPI4RST: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - /// TIM19 timer reset - TIM19RST: u1, - /// TIM20 timer reset - TIM20RST: u1, - reserved22: u1, - /// Debug MCU reset - DBGMCURST: u1, - reserved29: u6, - /// High Resolution Timer1 reset - HRTIM1RST: u1, - padding: u2, + /// JPEG HUFFSYMB tables + HUFFSYMB41: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB1 peripheral reset register (RCC_APB1RSTR) - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - /// Timer 14 reset - TIM4RST: u1, - reserved4: u1, - /// Timer 6 reset - TIM6RST: u1, - /// Timer 7 reset - TIM7RST: u1, - reserved11: u5, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI2 reset - SPI2RST: u1, - /// SPI3 reset - SPI3RST: u1, - reserved17: u1, - /// USART 2 reset - USART2RST: u1, - /// USART3 reset - USART3RST: u1, - /// UART 4 reset - UART4RST: u1, - /// UART 5 reset - UART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// USB reset - USBRST: u1, - reserved25: u1, - /// CAN reset - CANRST: u1, - /// DAC2 interface reset - DAC2RST: u1, - reserved28: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - /// I2C3 reset - I2C3RST: u1, - padding: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB42: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// AHB Peripheral Clock enable register (RCC_AHBENR) - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// SRAM interface clock enable - SRAMEN: u1, - reserved4: u1, - /// FLASH clock enable - FLASHEN: u1, - /// FMC clock enable - FMCEN: u1, - /// CRC clock enable - CRCEN: u1, - reserved16: u9, - /// IO port H clock enable - GPIOHEN: u1, - /// I/O port A clock enable - GPIOAEN: u1, - /// I/O port B clock enable - GPIOBEN: u1, - /// I/O port C clock enable - GPIOCEN: u1, - /// I/O port D clock enable - GPIODEN: u1, - /// I/O port E clock enable - GPIOEEN: u1, - /// I/O port F clock enable - GPIOFEN: u1, - /// IO port G clock enable - GPIOGEN: u1, - /// Touch sensing controller clock enable - TSCEN: u1, - reserved28: u3, - /// ADC1 and ADC2 clock enable - ADC12EN: u1, - /// ADC3 and ADC4 clock enable - ADC34EN: u1, - padding: u2, + /// JPEG HUFFSYMB tables + HUFFSYMB43: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB2 peripheral clock enable register (RCC_APB2ENR) - APB2ENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved11: u10, - /// TIM1 Timer clock enable - TIM1EN: u1, - /// SPI 1 clock enable - SPI1EN: u1, - /// TIM8 Timer clock enable - TIM8EN: u1, - /// USART1 clock enable - USART1EN: u1, - /// SPI4 clock enable - SPI4EN: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - /// TIM19 timer clock enable - TIM19EN: u1, - /// TIM20 timer clock enable - TIM20EN: u1, - reserved22: u1, - /// MCU debug module clock enable - DBGMCUEN: u1, - reserved29: u6, - /// High Resolution Timer 1 clock enable - HRTIM1EN: u1, - padding: u2, + /// JPEG HUFFSYMB tables + HUFFSYMB44: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB1 peripheral clock enable register (RCC_APB1ENR) - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer 2 clock enable - TIM2EN: u1, - /// Timer 3 clock enable - TIM3EN: u1, - /// Timer 4 clock enable - TIM4EN: u1, - reserved4: u1, - /// Timer 6 clock enable - TIM6EN: u1, - /// Timer 7 clock enable - TIM7EN: u1, - reserved11: u5, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI 2 clock enable - SPI2EN: u1, - /// SPI 3 clock enable - SPI3EN: u1, - reserved17: u1, - /// USART 2 clock enable - USART2EN: u1, - /// USART 3 clock enable - USART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// UART5 clock enable - UART5EN: u1, - /// I2C 1 clock enable - I2C1EN: u1, - /// I2C 2 clock enable - I2C2EN: u1, - /// USB clock enable - USBEN: u1, - reserved25: u1, - /// CAN clock enable - CANEN: u1, - /// DAC2 interface clock enable - DAC2EN: u1, - reserved28: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - /// I2C3 clock enable - I2C3EN: u1, - padding: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB45: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// Backup domain control register (RCC_BDCR) - BDCR: mmio.Mmio(packed struct(u32) { - /// External Low Speed oscillator enable - LSEON: u1, - /// External Low Speed oscillator ready - LSERDY: u1, - /// External Low Speed oscillator bypass - LSEBYP: u1, - /// LSE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - reserved8: u3, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - padding: u15, + /// JPEG HUFFSYMB tables + HUFFSYMB46: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// Control/status register (RCC_CSR) - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low speed oscillator enable - LSION: u1, - /// Internal low speed oscillator ready - LSIRDY: u1, - reserved23: u21, - /// Reset flag of the 1.8 V domain - V18PWRRSTF: u1, - /// Remove reset flag - RMVF: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB47: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// FMC reset - FMCRST: u1, - reserved16: u10, - /// IO port H reset - GPIOHRST: u1, - /// I/O port A reset - GPIOARST: u1, - /// I/O port B reset - GPIOBRST: u1, - /// I/O port C reset - GPIOCRST: u1, - /// I/O port D reset - GPIODRST: u1, - /// I/O port E reset - GPIOERST: u1, - /// I/O port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// Touch sensing controller reset - TSCRST: u1, - reserved28: u3, - /// ADC1 and ADC2 reset - ADC12RST: u1, - /// ADC3 and ADC4 reset - ADC34RST: u1, - padding: u2, + /// JPEG HUFFSYMB tables + HUFFSYMB48: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// Clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// PREDIV division factor - PREDIV: packed union { - raw: u4, - value: PREDIV, - }, - /// ADC1 and ADC2 prescaler - ADC12PRES: packed union { - raw: u5, - value: ADCPRES, - }, - /// ADC3 and ADC4 prescaler - ADC34PRES: packed union { - raw: u5, - value: ADCPRES, - }, - padding: u18, + /// JPEG HUFFSYMB tables + HUFFSYMB49: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// Clock configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SW: packed union { - raw: u2, - value: USART1SW, - }, - reserved4: u2, - /// I2C1 clock source selection - I2C1SW: packed union { - raw: u1, - value: ICSW, - }, - /// I2C2 clock source selection - I2C2SW: packed union { - raw: u1, - value: ICSW, - }, - /// HDMI CEC clock source selection - CECSW: packed union { - raw: u1, - value: CECSW, - }, - reserved8: u1, - /// Timer1 clock source selection - TIM1SW: packed union { - raw: u1, - value: TIMSW, - }, - /// Timer8 clock source selection - TIM8SW: packed union { - raw: u1, - value: TIMSW, - }, - /// Timer15 clock source selection - TIM15SW: packed union { - raw: u1, - value: TIMSW, - }, - /// Timer16 clock source selection - TIM16SW: packed union { - raw: u1, - value: TIMSW, - }, - /// Hrtim1 clock source selection - HRTIM1SW: packed union { - raw: u1, - value: TIMSW, - }, - /// Timer17 clock source selection - TIM17SW: packed union { - raw: u1, - value: TIMSW, - }, - reserved15: u1, - /// Timer20 clock source selection - TIM20SW: packed union { - raw: u1, - value: TIMSW, - }, - /// USART2 clock source selection - USART2SW: packed union { - raw: u2, - value: USARTSW, - }, - /// USART3 clock source selection - USART3SW: packed union { - raw: u2, - value: USARTSW, - }, - /// UART4 clock source selection - UART4SW: packed union { - raw: u2, - value: USARTSW, - }, - /// UART5 clock source selection - UART5SW: packed union { - raw: u2, - value: USARTSW, - }, - /// Timer2 clock source selection - TIM2SW: packed union { - raw: u1, - value: TIM2SW, - }, - /// Timer34 clock source selection - TIM34SW: packed union { - raw: u1, - value: TIMSW, - }, - padding: u6, + /// JPEG HUFFSYMB tables + HUFFSYMB50: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - }; - }; - - pub const rcc_wl5 = struct { - pub const ADCSEL = enum(u2) { - /// HSI used as ADC clock source - HSI = 0x1, - /// PLLPCLK used as ADC clock source - PLL1_P = 0x2, - /// SYSCLK used as ADC clock source - SYS = 0x3, - _, - }; - - pub const HPRE = enum(u4) { - /// DCLK not divided - Div1 = 0x0, - /// hclk = SYSCLK divided by 3 - Div3 = 0x1, - /// hclk = SYSCLK divided by 5 - Div5 = 0x2, - /// hclk = SYSCLK divided by 6 - Div6 = 0x5, - /// hclk = SYSCLK divided by 8 - Div10 = 0x6, - /// hclk = SYSCLK divided by 32 - Div32 = 0x7, - /// hclk = SYSCLK divided by 2 - Div2 = 0x8, - /// hclk = SYSCLK divided by 4 - Div4 = 0x9, - /// hclk = SYSCLK divided by 8 - Div8 = 0xa, - /// hclk = SYSCLK divided by 16 - Div16 = 0xb, - /// hclk = SYSCLK divided by 64 - Div64 = 0xc, - /// hclk = SYSCLK divided by 128 - Div128 = 0xd, - /// hclk = SYSCLK divided by 256 - Div256 = 0xe, - /// hclk = SYSCLK divided by 256 - Div512 = 0xf, - _, - }; - - pub const HSEPRE = enum(u1) { - Div1 = 0x0, - Div2 = 0x1, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCOPRE = enum(u3) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x1, - /// Division by 4 - Div4 = 0x2, - /// Division by 8 - Div8 = 0x3, - /// Division by 16 - Div16 = 0x4, - _, - }; - - pub const MCOSEL = enum(u4) { - /// No clock - DISABLE = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// MSI oscillator clock selected - MSI = 0x2, - /// HSI oscillator clock selected - HSI = 0x3, - /// HSE oscillator clock selected - HSE = 0x4, - /// Main PLLRCLK clock selected - PLL1_R = 0x5, - /// LSI oscillator clock selected - LSI = 0x6, - /// LSE oscillator clock selected - LSE = 0x8, - /// Main PLLCLK oscillator clock selected - PLL1_P = 0xd, - /// Main PLLQCLK oscillator clock selected - PLL1_Q = 0xe, - _, - }; - - pub const MSIRANGE = enum(u4) { - /// range 0 around 100 kHz - Range100K = 0x0, - /// range 1 around 200 kHz - Range200K = 0x1, - /// range 2 around 400 kHz - Range400K = 0x2, - /// range 3 around 800 kHz - Range800K = 0x3, - /// range 4 around 1 MHz - Range1M = 0x4, - /// range 5 around 2 MHz - Range2M = 0x5, - /// range 6 around 4 MHz - Range4M = 0x6, - /// range 7 around 8 MHz - Range8M = 0x7, - /// range 8 around 16 MHz - Range16M = 0x8, - /// range 9 around 24 MHz - Range24M = 0x9, - /// range 10 around 32 MHz - Range32M = 0xa, - /// range 11 around 48 MHz - Range48M = 0xb, - _, - }; - - pub const MSIRGSEL = enum(u1) { - /// MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register - CSR = 0x0, - /// MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register - CR = 0x1, - }; - - pub const PLLM = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - }; - - pub const PLLN = enum(u7) { - Mul6 = 0x6, - Mul7 = 0x7, - Mul8 = 0x8, - Mul9 = 0x9, - Mul10 = 0xa, - Mul11 = 0xb, - Mul12 = 0xc, - Mul13 = 0xd, - Mul14 = 0xe, - Mul15 = 0xf, - Mul16 = 0x10, - Mul17 = 0x11, - Mul18 = 0x12, - Mul19 = 0x13, - Mul20 = 0x14, - Mul21 = 0x15, - Mul22 = 0x16, - Mul23 = 0x17, - Mul24 = 0x18, - Mul25 = 0x19, - Mul26 = 0x1a, - Mul27 = 0x1b, - Mul28 = 0x1c, - Mul29 = 0x1d, - Mul30 = 0x1e, - Mul31 = 0x1f, - Mul32 = 0x20, - Mul33 = 0x21, - Mul34 = 0x22, - Mul35 = 0x23, - Mul36 = 0x24, - Mul37 = 0x25, - Mul38 = 0x26, - Mul39 = 0x27, - Mul40 = 0x28, - Mul41 = 0x29, - Mul42 = 0x2a, - Mul43 = 0x2b, - Mul44 = 0x2c, - Mul45 = 0x2d, - Mul46 = 0x2e, - Mul47 = 0x2f, - Mul48 = 0x30, - Mul49 = 0x31, - Mul50 = 0x32, - Mul51 = 0x33, - Mul52 = 0x34, - Mul53 = 0x35, - Mul54 = 0x36, - Mul55 = 0x37, - Mul56 = 0x38, - Mul57 = 0x39, - Mul58 = 0x3a, - Mul59 = 0x3b, - Mul60 = 0x3c, - Mul61 = 0x3d, - Mul62 = 0x3e, - Mul63 = 0x3f, - Mul64 = 0x40, - Mul65 = 0x41, - Mul66 = 0x42, - Mul67 = 0x43, - Mul68 = 0x44, - Mul69 = 0x45, - Mul70 = 0x46, - Mul71 = 0x47, - Mul72 = 0x48, - Mul73 = 0x49, - Mul74 = 0x4a, - Mul75 = 0x4b, - Mul76 = 0x4c, - Mul77 = 0x4d, - Mul78 = 0x4e, - Mul79 = 0x4f, - Mul80 = 0x50, - Mul81 = 0x51, - Mul82 = 0x52, - Mul83 = 0x53, - Mul84 = 0x54, - Mul85 = 0x55, - Mul86 = 0x56, - Mul87 = 0x57, - Mul88 = 0x58, - Mul89 = 0x59, - Mul90 = 0x5a, - Mul91 = 0x5b, - Mul92 = 0x5c, - Mul93 = 0x5d, - Mul94 = 0x5e, - Mul95 = 0x5f, - Mul96 = 0x60, - Mul97 = 0x61, - Mul98 = 0x62, - Mul99 = 0x63, - Mul100 = 0x64, - Mul101 = 0x65, - Mul102 = 0x66, - Mul103 = 0x67, - Mul104 = 0x68, - Mul105 = 0x69, - Mul106 = 0x6a, - Mul107 = 0x6b, - Mul108 = 0x6c, - Mul109 = 0x6d, - Mul110 = 0x6e, - Mul111 = 0x6f, - Mul112 = 0x70, - Mul113 = 0x71, - Mul114 = 0x72, - Mul115 = 0x73, - Mul116 = 0x74, - Mul117 = 0x75, - Mul118 = 0x76, - Mul119 = 0x77, - Mul120 = 0x78, - Mul121 = 0x79, - Mul122 = 0x7a, - Mul123 = 0x7b, - Mul124 = 0x7c, - Mul125 = 0x7d, - Mul126 = 0x7e, - Mul127 = 0x7f, - _, - }; - - pub const PLLP = enum(u5) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, - Div17 = 0x10, - Div18 = 0x11, - Div19 = 0x12, - Div20 = 0x13, - Div21 = 0x14, - Div22 = 0x15, - Div23 = 0x16, - Div24 = 0x17, - Div25 = 0x18, - Div26 = 0x19, - Div27 = 0x1a, - Div28 = 0x1b, - Div29 = 0x1c, - Div30 = 0x1d, - Div31 = 0x1e, - _, - }; - - pub const PLLQ = enum(u3) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - _, - }; - - pub const PLLR = enum(u3) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - _, - }; - - pub const PLLSRC = enum(u2) { - /// No clock selected as PLL entry clock source - DISABLE = 0x0, - /// MSI selected as PLL entry clock source - MSI = 0x1, - /// HSI selected as PLL entry clock source - HSI = 0x2, - /// HSE selected as PLL entry clock source - HSE = 0x3, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const RNGSEL = enum(u2) { - PLL1_Q = 0x0, - LSI = 0x1, - LSE = 0x2, - MSI = 0x3, - }; - - pub const RTCSEL = enum(u2) { - /// No clock selected - DISABLE = 0x0, - /// LSE oscillator clock selected - LSE = 0x1, - /// LSI oscillator clock selected - LSI = 0x2, - /// HSE oscillator clock divided by 32 selected - HSE = 0x3, - }; - - pub const SW = enum(u2) { - MSI = 0x0, - HSI = 0x1, - HSE = 0x2, - PLL1_R = 0x3, - }; - - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// MSI clock enable - MSION: u1, - /// MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) - MSIRDY: u1, - /// MSI clock PLL enable - MSIPLLEN: u1, - /// MSI range control selection - MSIRGSEL: packed union { - raw: u1, - value: MSIRGSEL, - }, - /// MSI clock ranges - MSIRANGE: packed union { - raw: u4, - value: MSIRANGE, - }, - /// HSI clock enable - HSION: u1, - /// HSI always enable for peripheral kernel clocks. - HSIKERON: u1, - /// HSI clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI is ready) - HSIRDY: u1, - /// HSI automatic start from Stop - HSIASFS: u1, - /// HSI kernel clock ready flag for peripherals requests. - HSIKERDY: u1, - reserved16: u3, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - reserved19: u1, - /// HSE Clock security system enable - CSSON: u1, - /// HSE sysclk prescaler - HSEPRE: packed union { - raw: u1, - value: HSEPRE, - }, - /// Enable HSE VDDTCXO output on package pin PB0-VDDTCXO. - HSEBYPPWR: u1, - reserved24: u2, - /// Main PLL enable - PLLON: u1, - /// Main PLL clock ready flag - PLLRDY: u1, - padding: u6, + /// JPEG HUFFSYMB tables + HUFFSYMB51: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// Internal clock sources calibration register - ICSCR: mmio.Mmio(packed struct(u32) { - /// MSI clock calibration - MSICAL: u8, - /// MSI clock trimming - MSITRIM: u8, - /// HSI clock calibration - HSICAL: u8, - /// HSI clock trimming - HSITRIM: u7, - padding: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB52: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// Clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u2, - value: SW, - }, - /// System clock switch status - SWS: packed union { - raw: u2, - value: SW, - }, - /// HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.) - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// PCLK1 low-speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, - }, - /// PCLK2 high-speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, - }, - reserved15: u1, - /// Wakeup from Stop and CSS backup clock selection - STOPWUCK: u1, - /// HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1) - HPREF: u1, - /// PCLK1 prescaler flag (APB1) - PPRE1F: u1, - /// PCLK2 prescaler flag (APB2) - PPRE2F: u1, - reserved24: u5, - /// Microcontroller clock output - MCOSEL: packed union { - raw: u4, - value: MCOSEL, - }, - /// Microcontroller clock output prescaler - MCOPRE: packed union { - raw: u3, - value: MCOPRE, - }, - padding: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB53: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// PLL configuration register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// Main PLL entry clock source - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - reserved4: u2, - /// Division factor for the main PLL input clock - PLLM: packed union { - raw: u3, - value: PLLM, - }, - reserved8: u1, - /// Main PLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, - }, - reserved16: u1, - /// Main PLL PLLPCLK output enable - PLLPEN: u1, - /// Main PLL division factor for PLLPCLK. - PLLP: packed union { - raw: u5, - value: PLLP, - }, - reserved24: u2, - /// Main PLL PLLQCLK output enable - PLLQEN: u1, - /// Main PLL division factor for PLLQCLK - PLLQ: packed union { - raw: u3, - value: PLLQ, - }, - /// Main PLL PLLRCLK output enable - PLLREN: u1, - /// Main PLL division factor for PLLRCLK - PLLR: packed union { - raw: u3, - value: PLLR, - }, + /// JPEG HUFFSYMB tables + HUFFSYMB54: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved24: [8]u8, - /// Clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - /// MSI ready interrupt enable - MSIRDYIE: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// PLL ready interrupt enable - PLLRDYIE: u1, - reserved9: u3, - /// LSE clock security system interrupt enable - LSECSSIE: u1, - padding: u22, + /// JPEG HUFFSYMB tables + HUFFSYMB55: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// Clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// MSI ready interrupt flag - MSIRDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// PLL ready interrupt flag - PLLRDYF: u1, - reserved8: u2, - /// HSE Clock security system interrupt flag - CSSF: u1, - /// LSE Clock security system interrupt flag - LSECSSF: u1, - padding: u22, + /// JPEG HUFFSYMB tables + HUFFSYMB56: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// Clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// MSI ready interrupt clear - MSIRDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// PLL ready interrupt clear - PLLRDYC: u1, - reserved8: u2, - /// HSE Clock security system interrupt clear - CSSC: u1, - /// LSE Clock security system interrupt clear - LSECSSC: u1, - padding: u22, + /// JPEG HUFFSYMB tables + HUFFSYMB57: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved40: [4]u8, - /// AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - /// DMAMUX1 reset - DMAMUX1RST: u1, - reserved12: u9, - /// CRC reset - CRCRST: u1, - padding: u19, + /// JPEG HUFFSYMB tables + HUFFSYMB58: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - reserved7: u4, - /// IO port H reset - GPIOHRST: u1, - padding: u24, + /// JPEG HUFFSYMB tables + HUFFSYMB59: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// AHB3 peripheral reset register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// PKARST - PKARST: u1, - /// AESRST - AESRST: u1, - /// RNGRST - RNGRST: u1, - /// HSEMRST - HSEMRST: u1, - /// IPCCRST - IPCCRST: u1, - reserved25: u4, - /// Flash interface reset - FLASHRST: u1, - padding: u6, + /// JPEG HUFFSYMB tables + HUFFSYMB60: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved56: [4]u8, - /// APB1 peripheral reset register 1 - APB1RSTR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer reset - TIM2RST: u1, - reserved14: u13, - /// SPI2 reset - SPI2RST: u1, - reserved17: u2, - /// USART2 reset - USART2RST: u1, - reserved21: u3, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// I2C3 reset - I2C3RST: u1, - reserved29: u5, - /// DAC reset - DACRST: u1, - reserved31: u1, - /// Low Power Timer 1 reset - LPTIM1RST: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB61: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB1 peripheral reset register 2 - APB1RSTR2: mmio.Mmio(packed struct(u32) { - /// Low-power UART 1 reset - LPUART1RST: u1, - reserved5: u4, - /// Low-power timer 2 reset - LPTIM2RST: u1, - /// Low-power timer 3 reset - LPTIM3RST: u1, - padding: u25, + /// JPEG HUFFSYMB tables + HUFFSYMB62: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - reserved9: u9, - /// ADC reset - ADCRST: u1, - reserved11: u1, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI1 reset - SPI1RST: u1, - reserved14: u1, - /// USART1 reset - USART1RST: u1, - reserved17: u2, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - padding: u13, + /// JPEG HUFFSYMB tables + HUFFSYMB63: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB3 peripheral reset register - APB3RSTR: mmio.Mmio(packed struct(u32) { - /// Sub-GHz radio SPI reset - SUBGHZSPIRST: u1, - padding: u31, + /// JPEG HUFFSYMB tables + HUFFSYMB64: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// AHB1 peripheral clock enable register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// CPU1 DMA1 clock enable - DMA1EN: u1, - /// CPU1 DMA2 clock enable - DMA2EN: u1, - /// CPU1 DMAMUX1 clock enable - DMAMUX1EN: u1, - reserved12: u9, - /// CPU1 CRC clock enable - CRCEN: u1, - padding: u19, + /// JPEG HUFFSYMB tables + HUFFSYMB65: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// AHB2 peripheral clock enable register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// CPU1 IO port A clock enable - GPIOAEN: u1, - /// CPU1 IO port B clock enable - GPIOBEN: u1, - /// CPU1 IO port C clock enable - GPIOCEN: u1, - reserved7: u4, - /// CPU1 IO port H clock enable - GPIOHEN: u1, - padding: u24, + /// JPEG HUFFSYMB tables + HUFFSYMB66: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// AHB3 peripheral clock enable register - AHB3ENR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// PKAEN - PKAEN: u1, - /// AESEN - AESEN: u1, - /// RNGEN - RNGEN: u1, - /// HSEMEN - HSEMEN: u1, - /// IPCCEN - IPCCEN: u1, - reserved25: u4, - /// CPU1 Flash interface clock enable - FLASHEN: u1, - padding: u6, + /// JPEG HUFFSYMB tables + HUFFSYMB67: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved88: [4]u8, - /// APB1 peripheral clock enable register 1 - APB1ENR1: mmio.Mmio(packed struct(u32) { - /// CPU1 TIM2 timer clock enable - TIM2EN: u1, - reserved10: u9, - /// CPU1 RTC APB clock enable - RTCAPBEN: u1, - /// CPU1 Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// CPU1 SPI2 clock enable - SPI2EN: u1, - reserved17: u2, - /// CPU1 USART2 clock enable - USART2EN: u1, - reserved21: u3, - /// CPU1 I2C1 clocks enable - I2C1EN: u1, - /// CPU1 I2C2 clocks enable - I2C2EN: u1, - /// CPU1 I2C3 clocks enable - I2C3EN: u1, - reserved29: u5, - /// CPU1 DAC clock enable - DACEN: u1, - reserved31: u1, - /// CPU1 Low power timer 1 clocks enable - LPTIM1EN: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB68: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB1 peripheral clock enable register 2 - APB1ENR2: mmio.Mmio(packed struct(u32) { - /// CPU1 Low power UART 1 clocks enable - LPUART1EN: u1, - reserved5: u4, - /// CPU1 Low power timer 2 clocks enable - LPTIM2EN: u1, - /// CPU1 Low power timer 3 clocks enable - LPTIM3EN: u1, - padding: u25, + /// JPEG HUFFSYMB tables + HUFFSYMB69: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB2 peripheral clock enable register - APB2ENR: mmio.Mmio(packed struct(u32) { - reserved9: u9, - /// CPU1 ADC clocks enable - ADCEN: u1, - reserved11: u1, - /// CPU1 TIM1 timer clock enable - TIM1EN: u1, - /// CPU1 SPI1 clock enable - SPI1EN: u1, - reserved14: u1, - /// CPU1 USART1clocks enable - USART1EN: u1, - reserved17: u2, - /// CPU1 TIM16 timer clock enable - TIM16EN: u1, - /// CPU1 TIM17 timer clock enable - TIM17EN: u1, - padding: u13, + /// JPEG HUFFSYMB tables + HUFFSYMB70: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB3 peripheral clock enable register - APB3ENR: mmio.Mmio(packed struct(u32) { - /// sub-GHz radio SPI clock enable - SUBGHZSPIEN: u1, - padding: u31, + /// JPEG HUFFSYMB tables + HUFFSYMB71: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// AHB1 peripheral clocks enable in Sleep modes register - AHB1SMENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable during CPU1 CSleep mode. - DMA1SMEN: u1, - /// DMA2 clock enable during CPU1 CSleep mode - DMA2SMEN: u1, - /// DMAMUX1 clock enable during CPU1 CSleep mode. - DMAMUX1SMEN: u1, - reserved12: u9, - /// CRC clock enable during CPU1 CSleep mode. - CRCSMEN: u1, - padding: u19, + /// JPEG HUFFSYMB tables + HUFFSYMB72: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// AHB2 peripheral clocks enable in Sleep modes register - AHB2SMENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable during CPU1 CSleep mode. - GPIOASMEN: u1, - /// IO port B clock enable during CPU1 CSleep mode. - GPIOBSMEN: u1, - /// IO port C clock enable during CPU1 CSleep mode. - GPIOCSMEN: u1, - reserved7: u4, - /// IO port H clock enable during CPU1 CSleep mode. - GPIOHSMEN: u1, - padding: u24, + /// JPEG HUFFSYMB tables + HUFFSYMB73: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// AHB3 peripheral clocks enable in Sleep and Stop modes register - AHB3SMENR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// PKA accelerator clock enable during CPU1 CSleep mode. - PKASMEN: u1, - /// AES accelerator clock enable during CPU1 CSleep mode. - AESSMEN: u1, - /// True RNG clocks enable during CPU1 Csleep and CStop modes - RNGSMEN: u1, - reserved23: u4, - /// SRAM1 interface clock enable during CPU1 CSleep mode. - SRAM1SMEN: u1, - /// SRAM2 memory interface clock enable during CPU1 CSleep mode - SRAM2SMEN: u1, - /// Flash interface clock enable during CPU1 CSleep mode. - FLASHSMEN: u1, - padding: u6, + /// JPEG HUFFSYMB tables + HUFFSYMB74: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved120: [4]u8, - /// APB1 peripheral clocks enable in Sleep mode register 1 - APB1SMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clock enable during CPU1 CSleep mode. - TIM2SMEN: u1, - reserved10: u9, - /// RTC bus clock enable during CPU1 CSleep mode. - RTCAPBSMEN: u1, - /// Window watchdog clocks enable during CPU1 CSleep mode. - WWDGSMEN: u1, - reserved14: u2, - /// SPI2 clock enable during CPU1 CSleep mode. - SPI2SMEN: u1, - reserved17: u2, - /// USART2 clock enable during CPU1 CSleep mode. - USART2SMEN: u1, - reserved21: u3, - /// I2C1 clock enable during CPU1 Csleep and CStop modes - I2C1SMEN: u1, - /// I2C2 clock enable during CPU1 Csleep and CStop modes - I2C2SMEN: u1, - /// I2C3 clock enable during CPU1 Csleep and CStop modes - I2C3SMEN: u1, - reserved29: u5, - /// DAC clock enable during CPU1 CSleep mode. - DACSMEN: u1, - reserved31: u1, - /// Low power timer 1 clock enable during CPU1 Csleep and CStop mode - LPTIM1SMEN: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB75: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB1 peripheral clocks enable in Sleep mode register 2 - APB1SMENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clock enable during CPU1 Csleep and CStop modes. - LPUART1SMEN: u1, - reserved5: u4, - /// Low power timer 2 clock enable during CPU1 Csleep and CStop modes - LPTIM2SMEN: u1, - /// Low power timer 3 clock enable during CPU1 Csleep and CStop modes - LPTIM3SMEN: u1, - padding: u25, + /// JPEG HUFFSYMB tables + HUFFSYMB76: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB2 peripheral clocks enable in Sleep mode register - APB2SMENR: mmio.Mmio(packed struct(u32) { - reserved9: u9, - /// ADC clocks enable during CPU1 Csleep and CStop modes - ADCSMEN: u1, - reserved11: u1, - /// TIM1 timer clock enable during CPU1 CSleep mode. - TIM1SMEN: u1, - /// SPI1 clock enable during CPU1 CSleep mode. - SPI1SMEN: u1, - reserved14: u1, - /// USART1 clock enable during CPU1 Csleep and CStop modes. - USART1SMEN: u1, - reserved17: u2, - /// TIM16 timer clock enable during CPU1 CSleep mode. - TIM16SMEN: u1, - /// TIM17 timer clock enable during CPU1 CSleep mode. - TIM17SMEN: u1, - padding: u13, + /// JPEG HUFFSYMB tables + HUFFSYMB77: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// APB3 peripheral clock enable in Sleep mode register - APB3SMENR: mmio.Mmio(packed struct(u32) { - /// Sub-GHz radio SPI clock enable during Sleep and Stop modes - SUBGHZSPISMEN: u1, - padding: u31, + /// JPEG HUFFSYMB tables + HUFFSYMB78: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// Peripherals independent clock configuration register - CCIPR: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SEL: u2, - /// USART2 clock source selection - USART2SEL: u2, - reserved8: u4, - /// SPI2 I2S clock source selection - SPI2SEL: u2, - /// LPUART1 clock source selection - LPUART1SEL: u2, - /// I2C1 clock source selection - I2C1SEL: u2, - /// I2C2 clock source selection - I2C2SEL: u2, - /// I2C3 clock source selection - I2C3SEL: u2, - /// Low power timer 1 clock source selection - LPTIM1SEL: u2, - /// Low power timer 2 clock source selection - LPTIM2SEL: u2, - /// Low power timer 3 clock source selection - LPTIM3SEL: u2, - reserved28: u4, - /// ADC clock source selection - ADCSEL: packed union { - raw: u2, - value: ADCSEL, - }, - /// RNG clock source selection - RNGSEL: packed union { - raw: u2, - value: RNGSEL, - }, + /// JPEG HUFFSYMB tables + HUFFSYMB79: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved144: [4]u8, - /// Backup domain control register - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enable - LSEON: u1, - /// LSE oscillator ready - LSERDY: u1, - /// LSE oscillator bypass - LSEBYP: u1, - /// LSE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// CSS on LSE enable - LSECSSON: u1, - /// CSS on LSE failure Detection - LSECSSD: u1, - /// LSE system clock enable - LSESYSEN: u1, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved11: u1, - /// LSE system clock ready - LSESYSRDY: u1, - reserved15: u3, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - reserved24: u7, - /// Low speed clock output enable - LSCOEN: u1, - /// Low speed clock output selection - LSCOSEL: u1, - padding: u6, + /// JPEG HUFFSYMB tables + HUFFSYMB80: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// Control/status register - CSR: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable - LSION: u1, - /// LSI oscillator ready - LSIRDY: u1, - reserved4: u2, - /// LSI frequency prescaler - LSIPRE: u1, - reserved8: u3, - /// MSI clock ranges - MSISRANGE: u4, - reserved14: u2, - /// Radio in reset status flag - RFRSTF: u1, - /// Radio reset - RFRST: u1, - reserved23: u7, - /// Remove reset flag - RMVF: u1, - /// Radio illegal access flag - RFILARSTF: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// Pin reset flag - PINRSTF: u1, - /// BOR flag - BORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent window watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// JPEG HUFFSYMB tables + HUFFSYMB81: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved264: [112]u8, - /// Extended clock recovery register - EXTCFGR: mmio.Mmio(packed struct(u32) { - /// HCLK3 shared prescaler (AHB3, Flash, and SRAM2) - SHDHPRE: packed union { - raw: u4, - value: HPRE, - }, - /// [dual core device only] HCLK2 prescaler (CPU2) - C2HPRE: packed union { - raw: u4, - value: HPRE, - }, - reserved16: u8, - /// HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2) - SHDHPREF: u1, - /// CLK2 prescaler flag (CPU2) - C2HPREF: u1, - padding: u14, + /// JPEG HUFFSYMB tables + HUFFSYMB82: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - reserved328: [60]u8, - /// CPU2 AHB1 peripheral clock enable register - C2AHB1ENR: mmio.Mmio(packed struct(u32) { - /// CPU2 DMA1 clock enable - DMA1EN: u1, - /// CPU2 DMA2 clock enable - DMA2EN: u1, - /// CPU2 DMAMUX1 clock enable - DMAMUX1EN: u1, - reserved12: u9, - /// CPU2 CRC clock enable - CRCEN: u1, - padding: u19, + /// JPEG HUFFSYMB tables + HUFFSYMB83: mmio.Mmio(packed struct(u32) { + /// DHTSymb RAM + HuffSymb_RAM: u32, }), - /// CPU2 AHB2 peripheral clock enable register - C2AHB2ENR: mmio.Mmio(packed struct(u32) { - /// CPU2 IO port A clock enable - GPIOAEN: u1, - /// CPU2 IO port B clock enable - GPIOBEN: u1, - /// CPU2 IO port C clock enable - GPIOCEN: u1, - reserved7: u4, - /// CPU2 IO port H clock enable - GPIOHEN: u1, - padding: u24, + /// JPEG DHTMem tables + DHTMEM0: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// CPU2 AHB3 peripheral clock enable register [dual core device only] - C2AHB3ENR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// CPU2 PKA accelerator clock enable - PKAEN: u1, - /// CPU2 AES accelerator clock enable - AESEN: u1, - /// CPU2 True RNG clocks enable - RNGEN: u1, - /// CPU2 HSEM clock enable - HSEMEN: u1, - /// CPU2 IPCC interface clock enable - IPCCEN: u1, - reserved25: u4, - /// CPU2 Flash interface clock enable - FLASHEN: u1, - padding: u6, + /// JPEG DHTMem tables + DHTMEM2: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved344: [4]u8, - /// CPU2 APB1 peripheral clock enable register 1 [dual core device only] - C2APB1ENR1: mmio.Mmio(packed struct(u32) { - /// CPU2 TIM2 timer clock enable - TIM2EN: u1, - reserved10: u9, - /// CPU2 RTC APB clock enable - RTCAPBEN: u1, - reserved14: u3, - /// CPU2 SPI2 clock enable - SPI2EN: u1, - reserved17: u2, - /// CPU2 USART2 clock enable - USART2EN: u1, - reserved21: u3, - /// CPU2 I2C1 clocks enable - I2C1EN: u1, - /// CPU2 I2C2 clocks enable - I2C2EN: u1, - /// CPU2 I2C3 clocks enable - I2C3EN: u1, - reserved29: u5, - /// CPU2 DAC clock enable - DACEN: u1, - reserved31: u1, - /// CPU2 Low power timer 1 clocks enable - LPTIM1EN: u1, + /// JPEG DHTMem tables + DHTMEM3: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// CPU2 APB1 peripheral clock enable register 2 [dual core device only] - C2APB1ENR2: mmio.Mmio(packed struct(u32) { - /// CPU2 Low power UART 1 clocks enable - LPUART1EN: u1, - reserved5: u4, - /// CPU2 Low power timer 2 clocks enable - LPTIM2EN: u1, - /// CPU2 Low power timer 3 clocks enable - LPTIM3EN: u1, - padding: u25, + /// JPEG DHTMem tables + DHTMEM4: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// CPU2 APB2 peripheral clock enable register [dual core device only] - C2APB2ENR: mmio.Mmio(packed struct(u32) { - reserved9: u9, - /// ADC clocks enable - ADCEN: u1, - reserved11: u1, - /// CPU2 TIM1 timer clock enable - TIM1EN: u1, - /// CPU2 SPI1 clock enable - SPI1EN: u1, - reserved14: u1, - /// CPU2 USART1clocks enable - USART1EN: u1, - reserved17: u2, - /// CPU2 TIM16 timer clock enable - TIM16EN: u1, - /// CPU2 TIM17 timer clock enable - TIM17EN: u1, - padding: u13, + /// JPEG DHTMem tables + DHTMEM5: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// CPU2 APB3 peripheral clock enable register [dual core device only] - C2APB3ENR: mmio.Mmio(packed struct(u32) { - /// CPU2 sub-GHz radio SPI clock enable - SUBGHZSPIEN: u1, - padding: u31, + /// JPEG DHTMem tables + DHTMEM6: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only] - C2AHB1SMENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable during CPU2 CSleep mode. - DMA1SMEN: u1, - /// DMA2 clock enable during CPU2 CSleep mode. - DMA2SMEN: u1, - /// DMAMUX1 clock enable during CPU2 CSleep mode. - DMAMUX1SMEN: u1, - reserved12: u9, - /// CRC clock enable during CPU2 CSleep mode. - CRCSMEN: u1, - padding: u19, + /// JPEG DHTMem tables + DHTMEM7: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only] - C2AHB2SMENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable during CPU2 CSleep mode. - GPIOASMEN: u1, - /// IO port B clock enable during CPU2 CSleep mode. - GPIOBSMEN: u1, - /// IO port C clock enable during CPU2 CSleep mode. - GPIOCSMEN: u1, - reserved7: u4, - /// IO port H clock enable during CPU2 CSleep mode. - GPIOHSMEN: u1, - padding: u24, + /// JPEG DHTMem tables + DHTMEM8: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only] - C2AHB3SMENR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// PKA accelerator clock enable during CPU2 CSleep mode. - PKASMEN: u1, - /// AES accelerator clock enable during CPU2 CSleep mode. - AESSMEN: u1, - /// True RNG clock enable during CPU2 CSleep and CStop mode. - RNGSMEN: u1, - reserved23: u4, - /// SRAM1 interface clock enable during CPU2 CSleep mode. - SRAM1SMEN: u1, - /// SRAM2 memory interface clock enable during CPU2 CSleep mode. - SRAM2SMEN: u1, - /// Flash interface clock enable during CPU2 CSleep mode. - FLASHSMEN: u1, - padding: u6, + /// JPEG DHTMem tables + DHTMEM9: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved376: [4]u8, - /// CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only] - C2APB1SMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clock enable during CPU2 CSleep mode. - TIM2SMEN: u1, - reserved10: u9, - /// RTC bus clock enable during CPU2 CSleep mode. - RTCAPBSMEN: u1, - reserved14: u3, - /// SPI2 clock enable during CPU2 CSleep mode. - SPI2SMEN: u1, - reserved17: u2, - /// USART2 clock enable during CPU2 CSleep mode. - USART2SMEN: u1, - reserved21: u3, - /// I2C1 clock enable during CPU2 CSleep and CStop modes - I2C1SMEN: u1, - /// I2C2 clock enable during CPU2 CSleep and CStop modes - I2C2SMEN: u1, - /// I2C3 clock enable during CPU2 CSleep and CStop modes - I2C3SMEN: u1, - reserved29: u5, - /// DAC clock enable during CPU2 CSleep mode. - DACSMEN: u1, - reserved31: u1, - /// Low power timer 1 clock enable during CPU2 CSleep and CStop mode - LPTIM1SMEN: u1, + /// JPEG DHTMem tables + DHTMEM10: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only] - C2APB1SMENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clock enable during CPU2 CSleep and CStop mode - LPUART1SMEN: u1, - reserved5: u4, - /// Low power timer 2 clocks enable during CPU2 CSleep and CStop modes. - LPTIM2SMEN: u1, - /// Low power timer 3 clocks enable during CPU2 CSleep and CStop modes. - LPTIM3SMEN: u1, - padding: u25, + /// JPEG DHTMem tables + DHTMEM11: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only] - C2APB2SMENR: mmio.Mmio(packed struct(u32) { - reserved9: u9, - /// ADC clocks enable during CPU2 Csleep and CStop modes - ADCSMEN: u1, - reserved11: u1, - /// TIM1 timer clock enable during CPU2 CSleep mode - TIM1SMEN: u1, - /// SPI1 clock enable during CPU2 CSleep mode - SPI1SMEN: u1, - reserved14: u1, - /// USART1clock enable during CPU2 CSleep and CStop mode - USART1SMEN: u1, - reserved17: u2, - /// TIM16 timer clock enable during CPU2 CSleep mode - TIM16SMEN: u1, - /// TIM17 timer clock enable during CPU2 CSleep mode - TIM17SMEN: u1, - padding: u13, + /// JPEG DHTMem tables + DHTMEM12: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only] - C2APB3SMENR: mmio.Mmio(packed struct(u32) { - /// sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes - SUBGHZSPISMEN: u1, - padding: u31, + /// JPEG DHTMem tables + DHTMEM13: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const spi_v4 = struct { - pub const COMM = enum(u2) { - /// Full duplex - FullDuplex = 0x0, - /// Simplex transmitter only - Transmitter = 0x1, - /// Simplex receiver only - Receiver = 0x2, - /// Half duplex - HalfDuplex = 0x3, - }; - - pub const CPHA = enum(u1) { - /// The first clock transition is the first data capture edge - FirstEdge = 0x0, - /// The second clock transition is the first data capture edge - SecondEdge = 0x1, - }; - - pub const CPOL = enum(u1) { - /// CK to 0 when idle - IdleLow = 0x0, - /// CK to 1 when idle - IdleHigh = 0x1, - }; - - pub const FTHLV = enum(u4) { - /// 1 frame - OneFrame = 0x0, - /// 2 frames - TwoFrames = 0x1, - /// 3 frames - ThreeFrames = 0x2, - /// 4 frames - FourFrames = 0x3, - /// 5 frames - FiveFrames = 0x4, - /// 6 frames - SixFrames = 0x5, - /// 7 frames - SevenFrames = 0x6, - /// 8 frames - EightFrames = 0x7, - /// 9 frames - NineFrames = 0x8, - /// 10 frames - TenFrames = 0x9, - /// 11 frames - ElevenFrames = 0xa, - /// 12 frames - TwelveFrames = 0xb, - /// 13 frames - ThirteenFrames = 0xc, - /// 14 frames - FourteenFrames = 0xd, - /// 15 frames - FifteenFrames = 0xe, - /// 16 frames - SixteenFrames = 0xf, - }; - - pub const HDDIR = enum(u1) { - /// Receiver in half duplex mode - Receiver = 0x0, - /// Transmitter in half duplex mode - Transmitter = 0x1, - }; - - pub const LSBFIRST = enum(u1) { - /// Data is transmitted/received with the MSB first - MSBFirst = 0x0, - /// Data is transmitted/received with the LSB first - LSBFirst = 0x1, - }; - - pub const MASTER = enum(u1) { - /// Slave configuration - Slave = 0x0, - /// Master configuration - Master = 0x1, - }; - - pub const MBR = enum(u3) { - /// f_spi_ker_ck / 2 - Div2 = 0x0, - /// f_spi_ker_ck / 4 - Div4 = 0x1, - /// f_spi_ker_ck / 8 - Div8 = 0x2, - /// f_spi_ker_ck / 16 - Div16 = 0x3, - /// f_spi_ker_ck / 32 - Div32 = 0x4, - /// f_spi_ker_ck / 64 - Div64 = 0x5, - /// f_spi_ker_ck / 128 - Div128 = 0x6, - /// f_spi_ker_ck / 256 - Div256 = 0x7, - }; - - pub const RCRCINI = enum(u1) { - /// All zeros RX CRC initialization pattern - AllZeros = 0x0, - /// All ones RX CRC initialization pattern - AllOnes = 0x1, - }; - - pub const RDIOM = enum(u1) { - /// RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) - PermanentlyActive = 0x0, - /// RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) - FromInput = 0x1, - }; - - pub const RDIOP = enum(u1) { - /// high level of the signal means the slave is ready for communication - ReadyHigh = 0x0, - /// low level of the signal means the slave is ready for communication - ReadyLow = 0x1, - }; - - pub const RXPLVL = enum(u2) { - /// Zero frames beyond packing ratio available - ZeroFrames = 0x0, - /// One frame beyond packing ratio available - OneFrame = 0x1, - /// Two frame beyond packing ratio available - TwoFrames = 0x2, - /// Three frame beyond packing ratio available - ThreeFrames = 0x3, - }; - - pub const RXWNE = enum(u1) { - /// Less than 32-bit data frame received - LessThan32 = 0x0, - /// At least 32-bit data frame received - AtLeast32 = 0x1, - }; - - pub const SP = enum(u3) { - /// Motorola SPI protocol - Motorola = 0x0, - /// TI SPI protocol - TI = 0x1, - _, - }; - - pub const SSIOP = enum(u1) { - /// Low level is active for SS signal - ActiveLow = 0x0, - /// High level is active for SS signal - ActiveHigh = 0x1, - }; - - pub const SSOM = enum(u1) { - /// SS is asserted until data transfer complete - Asserted = 0x0, - /// Data frames interleaved with SS not asserted during MIDI - NotAsserted = 0x1, - }; - - pub const TCRCINI = enum(u1) { - /// All zeros TX CRC initialization pattern - AllZeros = 0x0, - /// All ones TX CRC initialization pattern - AllOnes = 0x1, - }; - - pub const UDRCFG = enum(u2) { - /// Slave sends a constant underrun pattern - Constant = 0x0, - /// Slave repeats last received data frame from master - RepeatReceived = 0x1, - /// Slave repeats last transmitted data frame - RepeatTransmitted = 0x2, - _, - }; - - /// Serial peripheral interface - pub const SPI = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Serial Peripheral Enable - SPE: u1, - reserved8: u7, - /// Master automatic SUSP in Receive mode - MASRX: u1, - /// Master transfer start - CSTART: u1, - /// Master SUSPend request - CSUSP: u1, - /// Rx/Tx direction at Half-duplex mode - HDDIR: packed union { - raw: u1, - value: HDDIR, - }, - /// Internal SS signal input level - SSI: u1, - /// Full size (33-bit or 17-bit) CRC polynomial is used - CRC33_17: u1, - /// CRC calculation initialization pattern control for receiver - RCRCINI: packed union { - raw: u1, - value: RCRCINI, - }, - /// CRC calculation initialization pattern control for transmitter - TCRCINI: packed union { - raw: u1, - value: TCRCINI, - }, - /// Locking the AF configuration of associated IOs - IOLOCK: u1, - padding: u15, + /// JPEG DHTMem tables + DHTMEM14: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Number of data at current transfer - TSIZE: u16, - padding: u16, + /// JPEG DHTMem tables + DHTMEM15: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// configuration register 1 - CFG1: mmio.Mmio(packed struct(u32) { - /// Number of bits in at single SPI data frame - DSIZE: u5, - /// threshold level - FTHLV: packed union { - raw: u4, - value: FTHLV, - }, - /// Behavior of slave transmitter at underrun condition - UDRCFG: packed union { - raw: u2, - value: UDRCFG, - }, - reserved14: u3, - /// Rx DMA stream enable - RXDMAEN: u1, - /// Tx DMA stream enable - TXDMAEN: u1, - /// Length of CRC frame to be transacted and compared - CRCSIZE: u5, - reserved22: u1, - /// Hardware CRC computation enable - CRCEN: u1, - reserved28: u5, - /// Master baud rate - MBR: packed union { - raw: u3, - value: MBR, - }, - /// bypass of the prescaler at master baud rate clock generator - BPASS: u1, + /// JPEG DHTMem tables + DHTMEM16: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// configuration register 2 - CFG2: mmio.Mmio(packed struct(u32) { - /// Master SS Idleness - MSSI: u4, - /// Master Inter-Data Idleness - MIDI: u4, - reserved13: u5, - /// RDY signal input/output management Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero. - RDIOM: packed union { - raw: u1, - value: RDIOM, - }, - /// RDY signal input/output polarity - RDIOP: packed union { - raw: u1, - value: RDIOP, - }, - /// Swap functionality of MISO and MOSI pins - IOSWP: u1, - reserved17: u1, - /// SPI Communication Mode - COMM: packed union { - raw: u2, - value: COMM, - }, - /// Serial Protocol - SP: packed union { - raw: u3, - value: SP, - }, - /// SPI Master - MASTER: packed union { - raw: u1, - value: MASTER, - }, - /// Data frame format - LSBFIRST: packed union { - raw: u1, - value: LSBFIRST, - }, - /// Clock phase - CPHA: packed union { - raw: u1, - value: CPHA, - }, - /// Clock polarity - CPOL: packed union { - raw: u1, - value: CPOL, - }, - /// Software management of SS signal input - SSM: u1, - reserved28: u1, - /// SS input/output polarity - SSIOP: packed union { - raw: u1, - value: SSIOP, - }, - /// SS output enable - SSOE: u1, - /// SS output management in master mode - SSOM: packed union { - raw: u1, - value: SSOM, - }, - /// Alternate function always control GPIOs - AFCNTR: u1, + /// JPEG DHTMem tables + DHTMEM17: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Interrupt Enable Register - IER: mmio.Mmio(packed struct(u32) { - /// RXP Interrupt Enable - RXPIE: u1, - /// TXP interrupt enable - TXPIE: u1, - /// DXP interrupt enabled - DXPIE: u1, - /// EOT, SUSP and TXC interrupt enable - EOTIE: u1, - /// TXTFIE interrupt enable - TXTFIE: u1, - /// UDR interrupt enable - UDRIE: u1, - /// OVR interrupt enable - OVRIE: u1, - /// CRC Interrupt enable - CRCEIE: u1, - /// TIFRE interrupt enable - TIFREIE: u1, - /// Mode Fault interrupt enable - MODFIE: u1, - padding: u22, + /// JPEG DHTMem tables + DHTMEM18: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Status Register - SR: mmio.Mmio(packed struct(u32) { - /// Rx-Packet available - RXP: u1, - /// Tx-Packet space available - TXP: u1, - /// Duplex Packet - DXP: u1, - /// End Of Transfer - EOT: u1, - /// Transmission Transfer Filled - TXTF: u1, - /// Underrun at slave transmission mode - UDR: u1, - /// Overrun - OVR: u1, - /// CRC Error - CRCE: u1, - /// TI frame format error - TIFRE: u1, - /// Mode Fault - MODF: u1, - reserved11: u1, - /// SUSPend - SUSP: u1, - /// TxFIFO transmission complete - TXC: u1, - /// RxFIFO Packing LeVeL - RXPLVL: packed union { - raw: u2, - value: RXPLVL, - }, - /// RxFIFO Word Not Empty - RXWNE: packed union { - raw: u1, - value: RXWNE, - }, - /// Number of data frames remaining in current TSIZE session - CTSIZE: u16, + /// JPEG DHTMem tables + DHTMEM19: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Interrupt/Status Flags Clear Register - IFCR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// End Of Transfer flag clear - EOTC: u1, - /// Transmission Transfer Filled flag clear - TXTFC: u1, - /// Underrun flag clear - UDRC: u1, - /// Overrun flag clear - OVRC: u1, - /// CRC Error flag clear - CRCEC: u1, - /// TI frame format error flag clear - TIFREC: u1, - /// Mode Fault flag clear - MODFC: u1, - reserved11: u1, - /// SUSPend flag clear - SUSPC: u1, - padding: u20, + /// JPEG DHTMem tables + DHTMEM20: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved32: [4]u8, - /// Transmit Data Register - half-word sized - TXDR16: u32, - reserved48: [12]u8, - /// Receive Data Register - half-word sized - RXDR16: u32, - reserved64: [12]u8, - /// Polynomial Register - CRCPOLY: mmio.Mmio(packed struct(u32) { - /// CRC polynomial register - CRCPOLY: u32, + /// JPEG DHTMem tables + DHTMEM21: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Transmitter CRC Register - TXCRC: mmio.Mmio(packed struct(u32) { - /// CRC register for transmitter - TXCRC: u32, + /// JPEG DHTMem tables + DHTMEM22: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Receiver CRC Register - RXCRC: mmio.Mmio(packed struct(u32) { - /// CRC register for receiver - RXCRC: u32, + /// JPEG DHTMem tables + DHTMEM23: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Underrun Data Register - UDRDR: mmio.Mmio(packed struct(u32) { - /// Data at slave underrun condition - UDRDR: u32, + /// JPEG DHTMem tables + DHTMEM24: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const dac_v5 = struct { - pub const MODE = enum(u3) { - /// Normal mode, external pin only, buffer enabled - NORMAL_EXT_BUFEN = 0x0, - /// Normal mode, external pin and internal peripherals, buffer enabled - NORMAL_EXT_INT_BUFEN = 0x1, - /// Normal mode, external pin only, buffer disabled - NORMAL_EXT_BUFDIS = 0x2, - /// Normal mode, internal peripherals only, buffer disabled - NORMAL_INT_BUFDIS = 0x3, - /// Sample and hold mode, external pin only, buffer enabled - SAMPHOLD_EXT_BUFEN = 0x4, - /// Sample and hold mode, external pin and internal peripherals, buffer enabled - SAMPHOLD_EXT_INT_BUFEN = 0x5, - /// Sample and hold mode, external pin and internal peripherals, buffer disabled - SAMPHOLD_EXT_INT_BUFDIS = 0x6, - /// Sample and hold mode, internal peripherals only, buffer disabled - SAMPHOLD_INT_BUFDIS = 0x7, - }; - - pub const WAVE = enum(u2) { - /// Wave generation disabled - Disabled = 0x0, - /// Noise wave generation enabled - Noise = 0x1, - /// Triangle wave generation enabled - Triangle = 0x2, - _, - }; - - /// Digital-to-analog converter - pub const DAC = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u4, - /// channel noise/triangle wave generation enable - WAVE: packed union { - raw: u2, - value: WAVE, - }, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - /// channel DMA Underrun Interrupt enable - DMAUDRIE: u1, - /// DAC channel calibration enable - CEN: u1, - /// high frequency interface mode enable - HFSEL: u1, - padding: u16, + /// JPEG DHTMem tables + DHTMEM25: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// software trigger register - SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - padding: u31, + /// JPEG DHTMem tables + DHTMEM26: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// channel 12-bit right-aligned data holding register - DHR12R: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// JPEG DHTMem tables + DHTMEM27: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// channel 12-bit left-aligned data holding register - DHR12L: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + /// JPEG DHTMem tables + DHTMEM28: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// channel 8-bit right-aligned data holding register - DHR8R: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// JPEG DHTMem tables + DHTMEM29: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved32: [12]u8, - /// dual 12-bit right-aligned data holding register - DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// JPEG DHTMem tables + DHTMEM30: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// dual 12-bit left aligned data holding register - DHR12LD: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + /// JPEG DHTMem tables + DHTMEM31: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// dual 8-bit right aligned data holding register - DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// JPEG DHTMem tables + DHTMEM32: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// channel data output register - DOR: [2]mmio.Mmio(packed struct(u32) { - /// channel data output - DOR: u12, - padding: u20, + /// JPEG DHTMem tables + DHTMEM33: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved13: u13, - /// channel DMA underrun flag - DMAUDR: u1, - /// channel calibration offset status - CAL_FLAG: u1, - /// channel busy writing sample time flag - BWST: u1, - padding: u16, + /// JPEG DHTMem tables + DHTMEM34: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// calibration control register - CCR: mmio.Mmio(packed struct(u32) { - /// channel offset trimming value - OTRIM: u5, - padding: u27, + /// JPEG DHTMem tables + DHTMEM35: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// mode control register - MCR: mmio.Mmio(packed struct(u32) { - /// DAC channel mode - MODE: packed union { - raw: u3, - value: MODE, - }, - padding: u29, + /// JPEG DHTMem tables + DHTMEM36: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// sample and hold sample time register - SHSR: [2]mmio.Mmio(packed struct(u32) { - /// channel sample time - TSAMPLE: u10, - padding: u22, + /// JPEG DHTMem tables + DHTMEM37: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// sample and hold hold time register - SHHR: mmio.Mmio(packed struct(u32) { - /// channel hold time - THOLD: u10, - padding: u22, + /// JPEG DHTMem tables + DHTMEM38: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// sample and hold refresh time register - SHRR: mmio.Mmio(packed struct(u32) { - /// channel refresh time - TREFRESH: u8, - padding: u24, + /// JPEG DHTMem tables + DHTMEM39: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const flash_f1 = struct { - pub const LATENCY = enum(u3) { - /// Zero wait state, if 0 < SYSCLK≤ 24 MHz - WS0 = 0x0, - /// One wait state, if 24 MHz < SYSCLK ≤ 48 MHz - WS1 = 0x1, - /// Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz - WS2 = 0x2, - _, - }; - - /// FLASH - pub const FLASH = extern struct { - /// Flash access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: packed union { - raw: u3, - value: LATENCY, - }, - /// Flash half cycle access enable - HLFCYA: u1, - /// Prefetch buffer enable - PRFTBE: u1, - /// Prefetch buffer status - PRFTBS: u1, - padding: u26, + /// JPEG DHTMem tables + DHTMEM40: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Flash key register - KEYR: u32, - /// Flash option key register - OPTKEYR: u32, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Busy - BSY: u1, - reserved2: u1, - /// Programming error - PGERR: u1, - reserved4: u1, - /// Write protection error - WRPRTERR: u1, - /// End of operation - EOP: u1, - padding: u26, + /// JPEG DHTMem tables + DHTMEM41: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Page Erase - PER: u1, - /// Mass Erase - MER: u1, - reserved4: u1, - /// Option byte programming - OPTPG: u1, - /// Option byte erase - OPTER: u1, - /// Start - STRT: u1, - /// Lock - LOCK: u1, - reserved9: u1, - /// Option bytes write enable - OPTWRE: u1, - /// Error interrupt enable - ERRIE: u1, - reserved12: u1, - /// End of operation interrupt enable - EOPIE: u1, - padding: u19, + /// JPEG DHTMem tables + DHTMEM42: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Flash address register - AR: mmio.Mmio(packed struct(u32) { - /// Flash Address - FAR: u32, + /// JPEG DHTMem tables + DHTMEM43: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved28: [4]u8, - /// Option byte register - OBR: mmio.Mmio(packed struct(u32) { - /// Option byte error - OPTERR: u1, - /// Read protection - RDPRT: u1, - /// WDG_SW - WDG_SW: u1, - /// nRST_STOP - nRST_STOP: u1, - /// nRST_STDBY - nRST_STDBY: u1, - reserved10: u5, - /// Data0 - Data0: u8, - /// Data1 - Data1: u8, - padding: u6, + /// JPEG DHTMem tables + DHTMEM44: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Write protection register - WRPR: mmio.Mmio(packed struct(u32) { - /// Write protect - WRP: u32, + /// JPEG DHTMem tables + DHTMEM45: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const dac_v4 = struct { - pub const MODE = enum(u3) { - /// Normal mode, external pin only, buffer enabled - NORMAL_EXT_BUFEN = 0x0, - /// Normal mode, external pin and internal peripherals, buffer enabled - NORMAL_EXT_INT_BUFEN = 0x1, - /// Normal mode, external pin only, buffer disabled - NORMAL_EXT_BUFDIS = 0x2, - /// Normal mode, internal peripherals only, buffer disabled - NORMAL_INT_BUFDIS = 0x3, - /// Sample and hold mode, external pin only, buffer enabled - SAMPHOLD_EXT_BUFEN = 0x4, - /// Sample and hold mode, external pin and internal peripherals, buffer enabled - SAMPHOLD_EXT_INT_BUFEN = 0x5, - /// Sample and hold mode, external pin and internal peripherals, buffer disabled - SAMPHOLD_EXT_INT_BUFDIS = 0x6, - /// Sample and hold mode, internal peripherals only, buffer disabled - SAMPHOLD_INT_BUFDIS = 0x7, - }; - - pub const WAVE = enum(u2) { - /// Wave generation disabled - Disabled = 0x0, - /// Noise wave generation enabled - Noise = 0x1, - /// Triangle wave generation enabled - Triangle = 0x2, - _, - }; - - /// Digital-to-analog converter - pub const DAC = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u4, - /// channel noise/triangle wave generation enable - WAVE: packed union { - raw: u2, - value: WAVE, - }, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - /// channel DMA Underrun Interrupt enable - DMAUDRIE: u1, - /// DAC channel calibration enable - CEN: u1, - padding: u17, + /// JPEG DHTMem tables + DHTMEM46: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// software trigger register - SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - padding: u31, + /// JPEG DHTMem tables + DHTMEM47: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// channel 12-bit right-aligned data holding register - DHR12R: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// JPEG DHTMem tables + DHTMEM48: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// channel 12-bit left-aligned data holding register - DHR12L: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + /// JPEG DHTMem tables + DHTMEM49: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// channel 8-bit right-aligned data holding register - DHR8R: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// JPEG DHTMem tables + DHTMEM50: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved32: [12]u8, - /// dual 12-bit right-aligned data holding register - DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// JPEG DHTMem tables + DHTMEM51: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// dual 12-bit left aligned data holding register - DHR12LD: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + /// JPEG DHTMem tables + DHTMEM52: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// dual 8-bit right aligned data holding register - DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// JPEG DHTMem tables + DHTMEM53: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// channel data output register - DOR: [2]mmio.Mmio(packed struct(u32) { - /// channel data output - DOR: u12, - padding: u20, + /// JPEG DHTMem tables + DHTMEM54: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved13: u13, - /// channel DMA underrun flag - DMAUDR: u1, - /// channel calibration offset status - CAL_FLAG: u1, - /// channel busy writing sample time flag - BWST: u1, - padding: u16, + /// JPEG DHTMem tables + DHTMEM55: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// calibration control register - CCR: mmio.Mmio(packed struct(u32) { - /// channel offset trimming value - OTRIM: u5, - padding: u27, + /// JPEG DHTMem tables + DHTMEM56: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// mode control register - MCR: mmio.Mmio(packed struct(u32) { - /// DAC channel mode - MODE: packed union { - raw: u3, - value: MODE, - }, - padding: u29, + /// JPEG DHTMem tables + DHTMEM57: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// sample and hold sample time register - SHSR: [2]mmio.Mmio(packed struct(u32) { - /// channel sample time - TSAMPLE: u10, - padding: u22, + /// JPEG DHTMem tables + DHTMEM58: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// sample and hold hold time register - SHHR: mmio.Mmio(packed struct(u32) { - /// channel hold time - THOLD: u10, - padding: u22, + /// JPEG DHTMem tables + DHTMEM59: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// sample and hold refresh time register - SHRR: mmio.Mmio(packed struct(u32) { - /// channel refresh time - TREFRESH: u8, - padding: u24, + /// JPEG DHTMem tables + DHTMEM60: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const flash_f0 = struct { - pub const BOOT_SEL = enum(u1) { - /// BOOT0 signal is defined by nBOOT0 option bit - nBOOT0 = 0x0, - /// BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 = 0x1, - }; - - pub const LATENCY = enum(u3) { - /// 0 wait states - WS0 = 0x0, - /// 1 wait state - WS1 = 0x1, - _, - }; - - pub const RAM_PARITY_CHECK = enum(u1) { - /// RAM parity check enabled - Enabled = 0x0, - /// RAM parity check disabled - Disabled = 0x1, - }; - - pub const RDPRT = enum(u2) { - /// Level 0 - Level0 = 0x0, - /// Level 1 - Level1 = 0x1, - /// Level 2 - Level2 = 0x3, - _, - }; - - pub const WDG_SW = enum(u1) { - /// Hardware watchdog - Hardware = 0x0, - /// Software watchdog - Software = 0x1, - }; - - pub const nRST_STDBY = enum(u1) { - /// Reset generated when entering Standby mode - Reset = 0x0, - /// No reset generated - NoReset = 0x1, - }; - - pub const nRST_STOP = enum(u1) { - /// Reset generated when entering Stop mode - Reset = 0x0, - /// No reset generated - NoReset = 0x1, - }; - - /// Flash - pub const FLASH = extern struct { - /// Flash access control register - ACR: mmio.Mmio(packed struct(u32) { - /// LATENCY - LATENCY: packed union { - raw: u3, - value: LATENCY, - }, - reserved4: u1, - /// Prefetch buffer enable - PRFTBE: u1, - /// Prefetch buffer status - PRFTBS: u1, - padding: u26, + /// JPEG DHTMem tables + DHTMEM61: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Flash key register - KEYR: u32, - /// Flash option key register - OPTKEYR: u32, - /// Flash status register - SR: mmio.Mmio(packed struct(u32) { - /// Busy - BSY: u1, - reserved2: u1, - /// Programming error - PGERR: u1, - reserved4: u1, - /// Write protection error - WRPRT: u1, - /// End of operation - EOP: u1, - padding: u26, + /// JPEG DHTMem tables + DHTMEM62: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Flash control register - CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Page erase - PER: u1, - /// Mass erase - MER: u1, - reserved4: u1, - /// Option byte programming - OPTPG: u1, - /// Option byte erase - OPTER: u1, - /// Start - STRT: u1, - /// Lock - LOCK: u1, - reserved9: u1, - /// Option bytes write enable - OPTWRE: u1, - /// Error interrupt enable - ERRIE: u1, - reserved12: u1, - /// End of operation interrupt enable - EOPIE: u1, - /// Force option byte loading - FORCE_OPTLOAD: u1, - padding: u18, + /// JPEG DHTMem tables + DHTMEM63: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Flash address register - AR: mmio.Mmio(packed struct(u32) { - /// Flash address - FAR: u32, + /// JPEG DHTMem tables + DHTMEM64: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved28: [4]u8, - /// Option byte register - OBR: mmio.Mmio(packed struct(u32) { - /// Option byte error - OPTERR: u1, - /// Read protection level status - RDPRT: packed union { - raw: u2, - value: RDPRT, - }, - reserved8: u5, - /// WDG_SW - WDG_SW: packed union { - raw: u1, - value: WDG_SW, - }, - /// nRST_STOP - nRST_STOP: packed union { - raw: u1, - value: nRST_STOP, - }, - /// nRST_STDBY - nRST_STDBY: packed union { - raw: u1, - value: nRST_STDBY, - }, - /// nBOOT0 - nBOOT0: u1, - /// BOOT1 - nBOOT1: u1, - /// VDDA power supply supervisor enabled - VDDA_MONITOR: u1, - /// RAM_PARITY_CHECK - RAM_PARITY_CHECK: packed union { - raw: u1, - value: RAM_PARITY_CHECK, - }, - /// BOOT_SEL - BOOT_SEL: packed union { - raw: u1, - value: BOOT_SEL, - }, - /// Data0 - Data0: u8, - /// Data1 - Data1: u8, + /// JPEG DHTMem tables + DHTMEM65: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Write protection register - WRPR: mmio.Mmio(packed struct(u32) { - /// Write protect - WRP: u32, + /// JPEG DHTMem tables + DHTMEM66: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const tsc_v1 = struct { - /// Touch sensing controller. - pub const TSC = extern struct { - /// control register. - CR: mmio.Mmio(packed struct(u32) { - /// Touch sensing controller enable. - TSCE: u1, - /// Start a new acquisition. - START: u1, - /// Acquisition mode. - AM: u1, - /// Synchronization pin polarity. - SYNCPOL: u1, - /// I/O Default mode. - IODEF: u1, - /// Max count value. - MCV: u3, - reserved12: u4, - /// pulse generator prescaler. - PGPSC: u3, - /// Spread spectrum prescaler. - SSPSC: u1, - /// Spread spectrum enable. - SSE: u1, - /// Spread spectrum deviation. - SSD: u7, - /// Charge transfer pulse low. - CTPL: u4, - /// Charge transfer pulse high. - CTPH: u4, + /// JPEG DHTMem tables + DHTMEM67: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// End of acquisition interrupt enable. - EOAIE: u1, - /// Max count error interrupt enable. - MCEIE: u1, - padding: u30, + /// JPEG DHTMem tables + DHTMEM68: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// End of acquisition interrupt clear. - EOAIC: u1, - /// Max count error interrupt clear. - MCEIC: u1, - padding: u30, + /// JPEG DHTMem tables + DHTMEM69: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// interrupt status register. - ISR: mmio.Mmio(packed struct(u32) { - /// End of acquisition flag. - EOAF: u1, - /// Max count error flag. - MCEF: u1, - padding: u30, + /// JPEG DHTMem tables + DHTMEM70: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// I/O hysteresis control register. - IOHCR: mmio.Mmio(packed struct(u32) { - /// G1_IO1 Schmitt trigger hysteresis mode. - G1_IO1: u1, - /// G1_IO2 Schmitt trigger hysteresis mode. - G1_IO2: u1, - /// G1_IO3 Schmitt trigger hysteresis mode. - G1_IO3: u1, - /// G1_IO4 Schmitt trigger hysteresis mode. - G1_IO4: u1, - /// G2_IO1 Schmitt trigger hysteresis mode. - G2_IO1: u1, - /// G2_IO2 Schmitt trigger hysteresis mode. - G2_IO2: u1, - /// G2_IO3 Schmitt trigger hysteresis mode. - G2_IO3: u1, - /// G2_IO4 Schmitt trigger hysteresis mode. - G2_IO4: u1, - /// G3_IO1 Schmitt trigger hysteresis mode. - G3_IO1: u1, - /// G3_IO2 Schmitt trigger hysteresis mode. - G3_IO2: u1, - /// G3_IO3 Schmitt trigger hysteresis mode. - G3_IO3: u1, - /// G3_IO4 Schmitt trigger hysteresis mode. - G3_IO4: u1, - /// G4_IO1 Schmitt trigger hysteresis mode. - G4_IO1: u1, - /// G4_IO2 Schmitt trigger hysteresis mode. - G4_IO2: u1, - /// G4_IO3 Schmitt trigger hysteresis mode. - G4_IO3: u1, - /// G4_IO4 Schmitt trigger hysteresis mode. - G4_IO4: u1, - /// G5_IO1 Schmitt trigger hysteresis mode. - G5_IO1: u1, - /// G5_IO2 Schmitt trigger hysteresis mode. - G5_IO2: u1, - /// G5_IO3 Schmitt trigger hysteresis mode. - G5_IO3: u1, - /// G5_IO4 Schmitt trigger hysteresis mode. - G5_IO4: u1, - /// G6_IO1 Schmitt trigger hysteresis mode. - G6_IO1: u1, - /// G6_IO2 Schmitt trigger hysteresis mode. - G6_IO2: u1, - /// G6_IO3 Schmitt trigger hysteresis mode. - G6_IO3: u1, - /// G6_IO4 Schmitt trigger hysteresis mode. - G6_IO4: u1, - padding: u8, + /// JPEG DHTMem tables + DHTMEM71: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved24: [4]u8, - /// I/O analog switch control register. - IOASCR: mmio.Mmio(packed struct(u32) { - /// G1_IO1 analog switch enable. - G1_IO1: u1, - /// G1_IO2 analog switch enable. - G1_IO2: u1, - /// G1_IO3 analog switch enable. - G1_IO3: u1, - /// G1_IO4 analog switch enable. - G1_IO4: u1, - /// G2_IO1 analog switch enable. - G2_IO1: u1, - /// G2_IO2 analog switch enable. - G2_IO2: u1, - /// G2_IO3 analog switch enable. - G2_IO3: u1, - /// G2_IO4 analog switch enable. - G2_IO4: u1, - /// G3_IO1 analog switch enable. - G3_IO1: u1, - /// G3_IO2 analog switch enable. - G3_IO2: u1, - /// G3_IO3 analog switch enable. - G3_IO3: u1, - /// G3_IO4 analog switch enable. - G3_IO4: u1, - /// G4_IO1 analog switch enable. - G4_IO1: u1, - /// G4_IO2 analog switch enable. - G4_IO2: u1, - /// G4_IO3 analog switch enable. - G4_IO3: u1, - /// G4_IO4 analog switch enable. - G4_IO4: u1, - /// G5_IO1 analog switch enable. - G5_IO1: u1, - /// G5_IO2 analog switch enable. - G5_IO2: u1, - /// G5_IO3 analog switch enable. - G5_IO3: u1, - /// G5_IO4 analog switch enable. - G5_IO4: u1, - /// G6_IO1 analog switch enable. - G6_IO1: u1, - /// G6_IO2 analog switch enable. - G6_IO2: u1, - /// G6_IO3 analog switch enable. - G6_IO3: u1, - /// G6_IO4 analog switch enable. - G6_IO4: u1, - padding: u8, + /// JPEG DHTMem tables + DHTMEM72: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved32: [4]u8, - /// I/O sampling control register. - IOSCR: mmio.Mmio(packed struct(u32) { - /// G1_IO1 sampling mode. - G1_IO1: u1, - /// G1_IO2 sampling mode. - G1_IO2: u1, - /// G1_IO3 sampling mode. - G1_IO3: u1, - /// G1_IO4 sampling mode. - G1_IO4: u1, - /// G2_IO1 sampling mode. - G2_IO1: u1, - /// G2_IO2 sampling mode. - G2_IO2: u1, - /// G2_IO3 sampling mode. - G2_IO3: u1, - /// G2_IO4 sampling mode. - G2_IO4: u1, - /// G3_IO1 sampling mode. - G3_IO1: u1, - /// G3_IO2 sampling mode. - G3_IO2: u1, - /// G3_IO3 sampling mode. - G3_IO3: u1, - /// G3_IO4 sampling mode. - G3_IO4: u1, - /// G4_IO1 sampling mode. - G4_IO1: u1, - /// G4_IO2 sampling mode. - G4_IO2: u1, - /// G4_IO3 sampling mode. - G4_IO3: u1, - /// G4_IO4 sampling mode. - G4_IO4: u1, - /// G5_IO1 sampling mode. - G5_IO1: u1, - /// G5_IO2 sampling mode. - G5_IO2: u1, - /// G5_IO3 sampling mode. - G5_IO3: u1, - /// G5_IO4 sampling mode. - G5_IO4: u1, - /// G6_IO1 sampling mode. - G6_IO1: u1, - /// G6_IO2 sampling mode. - G6_IO2: u1, - /// G6_IO3 sampling mode. - G6_IO3: u1, - /// G6_IO4 sampling mode. - G6_IO4: u1, - padding: u8, + /// JPEG DHTMem tables + DHTMEM73: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved40: [4]u8, - /// I/O channel control register. - IOCCR: mmio.Mmio(packed struct(u32) { - /// G1_IO1 channel mode. - G1_IO1: u1, - /// G1_IO2 channel mode. - G1_IO2: u1, - /// G1_IO3 channel mode. - G1_IO3: u1, - /// G1_IO4 channel mode. - G1_IO4: u1, - /// G2_IO1 channel mode. - G2_IO1: u1, - /// G2_IO2 channel mode. - G2_IO2: u1, - /// G2_IO3 channel mode. - G2_IO3: u1, - /// G2_IO4 channel mode. - G2_IO4: u1, - /// G3_IO1 channel mode. - G3_IO1: u1, - /// G3_IO2 channel mode. - G3_IO2: u1, - /// G3_IO3 channel mode. - G3_IO3: u1, - /// G3_IO4 channel mode. - G3_IO4: u1, - /// G4_IO1 channel mode. - G4_IO1: u1, - /// G4_IO2 channel mode. - G4_IO2: u1, - /// G4_IO3 channel mode. - G4_IO3: u1, - /// G4_IO4 channel mode. - G4_IO4: u1, - /// G5_IO1 channel mode. - G5_IO1: u1, - /// G5_IO2 channel mode. - G5_IO2: u1, - /// G5_IO3 channel mode. - G5_IO3: u1, - /// G5_IO4 channel mode. - G5_IO4: u1, - /// G6_IO1 channel mode. - G6_IO1: u1, - /// G6_IO2 channel mode. - G6_IO2: u1, - /// G6_IO3 channel mode. - G6_IO3: u1, - /// G6_IO4 channel mode. - G6_IO4: u1, - padding: u8, + /// JPEG DHTMem tables + DHTMEM74: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved48: [4]u8, - /// I/O group control status register. - IOGCSR: mmio.Mmio(packed struct(u32) { - /// Analog I/O group x enable. - G1E: u1, - /// Analog I/O group x enable. - G2E: u1, - /// Analog I/O group x enable. - G3E: u1, - /// Analog I/O group x enable. - G4E: u1, - /// Analog I/O group x enable. - G5E: u1, - /// Analog I/O group x enable. - G6E: u1, - /// Analog I/O group x enable. - G7E: u1, - /// Analog I/O group x enable. - G8E: u1, - reserved16: u8, - /// Analog I/O group x status. - G1S: u1, - /// Analog I/O group x status. - G2S: u1, - /// Analog I/O group x status. - G3S: u1, - /// Analog I/O group x status. - G4S: u1, - /// Analog I/O group x status. - G5S: u1, - /// Analog I/O group x status. - G6S: u1, - /// Analog I/O group x status. - G7S: u1, - /// Analog I/O group x status. - G8S: u1, - padding: u8, + /// JPEG DHTMem tables + DHTMEM75: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// I/O group x counter register. - IOGCR: [6]mmio.Mmio(packed struct(u32) { - /// Counter value. - CNT: u14, - padding: u18, + /// JPEG DHTMem tables + DHTMEM76: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const rcc_u5 = struct { - pub const ADCDACSEL = enum(u3) { - /// HCLK clock selected - HCLK1 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// PLL2 R (pll2_r_ck) selected - PLL2_R = 0x2, - /// HSE clock selected - HSE = 0x3, - /// HSI clock selected - HSI = 0x4, - /// MSIK clock selected - MSIK = 0x5, - _, - }; - - pub const ADFSEL = enum(u3) { - /// HCLK selected - HCLK3 = 0x0, - /// PLL1 P (pll1_p_ck) selected - PLL1_P = 0x1, - /// PLL3 Q (pll3_q_ck) selected - PLL3_Q = 0x2, - /// input pin AUDIOCLK selected - AUDIOCLK = 0x3, - /// MSIK clock selected - MSIK = 0x4, - _, - }; - - pub const DACSEL = enum(u1) { - /// LSE selected - LSE = 0x0, - /// LSI selected - LSI = 0x1, - }; - - pub const DPRE = enum(u3) { - /// DCLK not divided - Div1 = 0x0, - /// DCLK divided by 2 - Div2 = 0x4, - /// DCLK divided by 4 - Div4 = 0x5, - /// DCLK divided by 8 - Div8 = 0x6, - /// DCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const DSISEL = enum(u1) { - /// PLL3 “P” (pll3_p_ck) selected - PLL3_P = 0x0, - /// DSI PHY PLL output selected (formerly called DCLK, renamed to DSI_PHY to match other chip families) - DSI_PHY = 0x1, - }; - - pub const FDCANSEL = enum(u2) { - /// HSE clock selected - HSE = 0x0, - /// PLL1 Q (pll1_q_ck) selected - PLL1_Q = 0x1, - /// PLL2 P (pll2_p_ck) selected - PLL2_P = 0x2, - _, - }; - - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, - _, - }; - - pub const HSEEXT = enum(u1) { - /// external HSE clock analog mode - ANALOG = 0x0, - /// external HSE clock digital mode (through I/O Schmitt trigger) - DIGITAL = 0x1, - }; - - pub const HSPISEL = enum(u2) { - /// SYSCLK selected - SYS = 0x0, - /// PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz - PLL1_Q = 0x1, - /// PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz - PLL2_Q = 0x2, - /// PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz - PLL3_R = 0x3, - }; - - pub const I2C3SEL = enum(u2) { - /// PCLK3 selected - PCLK3 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - /// MSIK selected - MSIK = 0x3, - }; - - pub const I2CSEL = enum(u2) { - /// PCLK1 selected - PCLK1 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - /// MSIK selected - MSIK = 0x3, - }; - - pub const ICLKSEL = enum(u2) { - /// HSI48 clock selected - HSI48 = 0x0, - /// PLL2 Q (pll2_q_ck) selected - PLL2_Q = 0x1, - /// PLL1 Q (pll1_q_ck) selected - PLL1_Q = 0x2, - /// MSIK clock selected - MSIK = 0x3, - }; - - pub const LPTIM2SEL = enum(u2) { - /// PCLK1 selected - PCLK1 = 0x0, - /// LSI selected - LSI = 0x1, - /// HSI selected - HSI = 0x2, - /// LSE selected - LSE = 0x3, - }; - - pub const LPTIMSEL = enum(u2) { - /// PCLK3 selected - PCLK3 = 0x0, - /// LSI selected - LSI = 0x1, - /// HSI selected - HSI = 0x2, - /// LSE selected - LSE = 0x3, - }; - - pub const LPUSARTSEL = enum(u3) { - /// PCLK3 selected - PCLK3 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - /// LSE selected - LSE = 0x3, - /// MSIK selected - MSIK = 0x4, - _, - }; - - pub const LSCOSEL = enum(u1) { - /// LSI clock selected - LSI = 0x0, - /// LSE clock selected - LSE = 0x1, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const LSIPREDIV = enum(u1) { - /// LSI not divided - Div1 = 0x0, - /// LSI divided by 128 - Div128 = 0x1, - }; - - pub const LTDCSEL = enum(u1) { - /// PLL3 “R” (pll3_r_ck) selected - PLL3_R = 0x0, - /// PLL2 “R” (pll2_r_ck) selected - PLL2_R = 0x1, - }; - - pub const MCOPRE = enum(u3) { - /// MCO divided by 1 - Div1 = 0x0, - /// MCO divided by 2 - Div2 = 0x1, - /// MCO divided by 4 - Div4 = 0x2, - /// MCO divided by 8 - Div8 = 0x3, - /// MCO divided by 16 - Div16 = 0x4, - _, - }; - - pub const MCOSEL = enum(u4) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// SYSCLK system clock selected - SYS = 0x1, - /// MSIS clock selected - MSIS = 0x2, - /// HSI clock selected - HSI = 0x3, - /// HSE clock selected - HSE = 0x4, - /// Main PLL clock pll1_r_ck selected - PLL1_R = 0x5, - /// LSI clock selected - LSI = 0x6, - /// LSE clock selected - LSE = 0x7, - /// Internal HSI48 clock selected - HSI48 = 0x8, - /// MSIK clock selected - MSIK = 0x9, - _, - }; - - pub const MDFSEL = enum(u3) { - /// HCLK selected - HCLK1 = 0x0, - /// PLL1 P (pll1_p_ck) selected - PLL1_P = 0x1, - /// PLL3 Q (pll3_q_ck) selected - PLL3_Q = 0x2, - /// input pin AUDIOCLK selected - AUDIOCLK = 0x3, - /// MSIK clock selected - MSIK = 0x4, - _, - }; - - pub const MSIBIAS = enum(u1) { - /// MSI bias continuous mode (clock accuracy fast settling time) - CONTINUOUS = 0x0, - /// MSI bias sampling mode (ultra-low-power mode) - SAMPLING = 0x1, - }; - - pub const MSIPLLFAST = enum(u1) { - /// MSI PLL normal start-up - NORMAL = 0x0, - /// MSI PLL fast start-up - FAST = 0x1, - }; - - pub const MSIPLLSEL = enum(u1) { - /// PLL mode applied to MSIK (MSI kernel) clock output - MSIK = 0x0, - /// PLL mode applied to MSIS (MSI system) clock output - MSIS = 0x1, - }; - - pub const MSIRANGE = enum(u4) { - /// range 0 around 48 MHz - RANGE_48MHZ = 0x0, - /// range 1 around 24 MHz - RANGE_24MHZ = 0x1, - /// range 2 around 16 MHz - RANGE_16MHZ = 0x2, - /// range 3 around 12 MHz - RANGE_12MHZ = 0x3, - /// range 4 around 4 MHz (reset value) - RANGE_4MHZ = 0x4, - /// range 5 around 2 MHz - RANGE_2MHZ = 0x5, - /// range 6 around 1.33 MHz - RANGE_1_33MHZ = 0x6, - /// range 7 around 1 MHz - RANGE_1MHZ = 0x7, - /// range 8 around 3.072 MHz - RANGE_3_072MHZ = 0x8, - /// range 9 around 1.536 MHz - RANGE_1_536MHZ = 0x9, - /// range 10 around 1.024 MHz - RANGE_1_024MHZ = 0xa, - /// range 11 around 768 kHz - RANGE_768KHZ = 0xb, - /// range 12 around 400 kHz - RANGE_400KHZ = 0xc, - /// range 13 around 200 kHz - RANGE_200KHZ = 0xd, - /// range 14 around 133 kHz - RANGE_133KHZ = 0xe, - /// range 15 around 100 kHz - RANGE_100KHZ = 0xf, - }; - - pub const MSIRGSEL = enum(u1) { - /// MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR - CSR = 0x0, - /// MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1 - ICSCR1 = 0x1, - }; - - pub const MSIXSRANGE = enum(u4) { - /// range 4 around 4M Hz (reset value) - RANGE_4MHZ = 0x4, - /// range 5 around 2 MHz - RANGE_2MHZ = 0x5, - /// range 6 around 1.5 MHz - RANGE_1_5MHZ = 0x6, - /// range 7 around 1 MHz - RANGE_1MHZ = 0x7, - /// range 8 around 3.072 MHz - RANGE_3_072MHZ = 0x8, - _, - }; - - pub const OCTOSPISEL = enum(u2) { - /// SYSCLK selected - SYS = 0x0, - /// MSIK selected - MSIK = 0x1, - /// PLL1 Q (pll1_q_ck) selected, can be up to 200 MHz - PLL1_Q = 0x2, - /// PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz - PLL2_Q = 0x3, - }; - - pub const OTGHSSEL = enum(u2) { - /// HSE selected - HSE = 0x0, - /// PLL1 “P” (pll1_q_ck) selected, - PLL1_P = 0x1, - /// HSE/2 selected - HSE_DIV_2 = 0x2, - /// PLL1 “P” divided by 2 (pll1_p_ck/2) selected - PLL1_P_DIV_2 = 0x3, - }; - - pub const PLLDIV = enum(u7) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, - Div17 = 0x10, - Div18 = 0x11, - Div19 = 0x12, - Div20 = 0x13, - Div21 = 0x14, - Div22 = 0x15, - Div23 = 0x16, - Div24 = 0x17, - Div25 = 0x18, - Div26 = 0x19, - Div27 = 0x1a, - Div28 = 0x1b, - Div29 = 0x1c, - Div30 = 0x1d, - Div31 = 0x1e, - Div32 = 0x1f, - Div33 = 0x20, - Div34 = 0x21, - Div35 = 0x22, - Div36 = 0x23, - Div37 = 0x24, - Div38 = 0x25, - Div39 = 0x26, - Div40 = 0x27, - Div41 = 0x28, - Div42 = 0x29, - Div43 = 0x2a, - Div44 = 0x2b, - Div45 = 0x2c, - Div46 = 0x2d, - Div47 = 0x2e, - Div48 = 0x2f, - Div49 = 0x30, - Div50 = 0x31, - Div51 = 0x32, - Div52 = 0x33, - Div53 = 0x34, - Div54 = 0x35, - Div55 = 0x36, - Div56 = 0x37, - Div57 = 0x38, - Div58 = 0x39, - Div59 = 0x3a, - Div60 = 0x3b, - Div61 = 0x3c, - Div62 = 0x3d, - Div63 = 0x3e, - Div64 = 0x3f, - Div65 = 0x40, - Div66 = 0x41, - Div67 = 0x42, - Div68 = 0x43, - Div69 = 0x44, - Div70 = 0x45, - Div71 = 0x46, - Div72 = 0x47, - Div73 = 0x48, - Div74 = 0x49, - Div75 = 0x4a, - Div76 = 0x4b, - Div77 = 0x4c, - Div78 = 0x4d, - Div79 = 0x4e, - Div80 = 0x4f, - Div81 = 0x50, - Div82 = 0x51, - Div83 = 0x52, - Div84 = 0x53, - Div85 = 0x54, - Div86 = 0x55, - Div87 = 0x56, - Div88 = 0x57, - Div89 = 0x58, - Div90 = 0x59, - Div91 = 0x5a, - Div92 = 0x5b, - Div93 = 0x5c, - Div94 = 0x5d, - Div95 = 0x5e, - Div96 = 0x5f, - Div97 = 0x60, - Div98 = 0x61, - Div99 = 0x62, - Div100 = 0x63, - Div101 = 0x64, - Div102 = 0x65, - Div103 = 0x66, - Div104 = 0x67, - Div105 = 0x68, - Div106 = 0x69, - Div107 = 0x6a, - Div108 = 0x6b, - Div109 = 0x6c, - Div110 = 0x6d, - Div111 = 0x6e, - Div112 = 0x6f, - Div113 = 0x70, - Div114 = 0x71, - Div115 = 0x72, - Div116 = 0x73, - Div117 = 0x74, - Div118 = 0x75, - Div119 = 0x76, - Div120 = 0x77, - Div121 = 0x78, - Div122 = 0x79, - Div123 = 0x7a, - Div124 = 0x7b, - Div125 = 0x7c, - Div126 = 0x7d, - Div127 = 0x7e, - Div128 = 0x7f, - }; - - pub const PLLM = enum(u4) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, - }; - - pub const PLLMBOOST = enum(u4) { - /// division by 1 (bypass) - Div1 = 0x0, - /// division by 2 - Div2 = 0x1, - /// division by 4 - Div4 = 0x2, - /// division by 6 - Div6 = 0x3, - /// division by 8 - Div8 = 0x4, - /// division by 10 - Div10 = 0x5, - /// division by 12 - Div12 = 0x6, - /// division by 14 - Div14 = 0x7, - /// division by 16 - Div16 = 0x8, - _, - }; - - pub const PLLN = enum(u9) { - Mul4 = 0x3, - Mul5 = 0x4, - Mul6 = 0x5, - Mul7 = 0x6, - Mul8 = 0x7, - Mul9 = 0x8, - Mul10 = 0x9, - Mul11 = 0xa, - Mul12 = 0xb, - Mul13 = 0xc, - Mul14 = 0xd, - Mul15 = 0xe, - Mul16 = 0xf, - Mul17 = 0x10, - Mul18 = 0x11, - Mul19 = 0x12, - Mul20 = 0x13, - Mul21 = 0x14, - Mul22 = 0x15, - Mul23 = 0x16, - Mul24 = 0x17, - Mul25 = 0x18, - Mul26 = 0x19, - Mul27 = 0x1a, - Mul28 = 0x1b, - Mul29 = 0x1c, - Mul30 = 0x1d, - Mul31 = 0x1e, - Mul32 = 0x1f, - Mul33 = 0x20, - Mul34 = 0x21, - Mul35 = 0x22, - Mul36 = 0x23, - Mul37 = 0x24, - Mul38 = 0x25, - Mul39 = 0x26, - Mul40 = 0x27, - Mul41 = 0x28, - Mul42 = 0x29, - Mul43 = 0x2a, - Mul44 = 0x2b, - Mul45 = 0x2c, - Mul46 = 0x2d, - Mul47 = 0x2e, - Mul48 = 0x2f, - Mul49 = 0x30, - Mul50 = 0x31, - Mul51 = 0x32, - Mul52 = 0x33, - Mul53 = 0x34, - Mul54 = 0x35, - Mul55 = 0x36, - Mul56 = 0x37, - Mul57 = 0x38, - Mul58 = 0x39, - Mul59 = 0x3a, - Mul60 = 0x3b, - Mul61 = 0x3c, - Mul62 = 0x3d, - Mul63 = 0x3e, - Mul64 = 0x3f, - Mul65 = 0x40, - Mul66 = 0x41, - Mul67 = 0x42, - Mul68 = 0x43, - Mul69 = 0x44, - Mul70 = 0x45, - Mul71 = 0x46, - Mul72 = 0x47, - Mul73 = 0x48, - Mul74 = 0x49, - Mul75 = 0x4a, - Mul76 = 0x4b, - Mul77 = 0x4c, - Mul78 = 0x4d, - Mul79 = 0x4e, - Mul80 = 0x4f, - Mul81 = 0x50, - Mul82 = 0x51, - Mul83 = 0x52, - Mul84 = 0x53, - Mul85 = 0x54, - Mul86 = 0x55, - Mul87 = 0x56, - Mul88 = 0x57, - Mul89 = 0x58, - Mul90 = 0x59, - Mul91 = 0x5a, - Mul92 = 0x5b, - Mul93 = 0x5c, - Mul94 = 0x5d, - Mul95 = 0x5e, - Mul96 = 0x5f, - Mul97 = 0x60, - Mul98 = 0x61, - Mul99 = 0x62, - Mul100 = 0x63, - Mul101 = 0x64, - Mul102 = 0x65, - Mul103 = 0x66, - Mul104 = 0x67, - Mul105 = 0x68, - Mul106 = 0x69, - Mul107 = 0x6a, - Mul108 = 0x6b, - Mul109 = 0x6c, - Mul110 = 0x6d, - Mul111 = 0x6e, - Mul112 = 0x6f, - Mul113 = 0x70, - Mul114 = 0x71, - Mul115 = 0x72, - Mul116 = 0x73, - Mul117 = 0x74, - Mul118 = 0x75, - Mul119 = 0x76, - Mul120 = 0x77, - Mul121 = 0x78, - Mul122 = 0x79, - Mul123 = 0x7a, - Mul124 = 0x7b, - Mul125 = 0x7c, - Mul126 = 0x7d, - Mul127 = 0x7e, - Mul128 = 0x7f, - Mul129 = 0x80, - Mul130 = 0x81, - Mul131 = 0x82, - Mul132 = 0x83, - Mul133 = 0x84, - Mul134 = 0x85, - Mul135 = 0x86, - Mul136 = 0x87, - Mul137 = 0x88, - Mul138 = 0x89, - Mul139 = 0x8a, - Mul140 = 0x8b, - Mul141 = 0x8c, - Mul142 = 0x8d, - Mul143 = 0x8e, - Mul144 = 0x8f, - Mul145 = 0x90, - Mul146 = 0x91, - Mul147 = 0x92, - Mul148 = 0x93, - Mul149 = 0x94, - Mul150 = 0x95, - Mul151 = 0x96, - Mul152 = 0x97, - Mul153 = 0x98, - Mul154 = 0x99, - Mul155 = 0x9a, - Mul156 = 0x9b, - Mul157 = 0x9c, - Mul158 = 0x9d, - Mul159 = 0x9e, - Mul160 = 0x9f, - Mul161 = 0xa0, - Mul162 = 0xa1, - Mul163 = 0xa2, - Mul164 = 0xa3, - Mul165 = 0xa4, - Mul166 = 0xa5, - Mul167 = 0xa6, - Mul168 = 0xa7, - Mul169 = 0xa8, - Mul170 = 0xa9, - Mul171 = 0xaa, - Mul172 = 0xab, - Mul173 = 0xac, - Mul174 = 0xad, - Mul175 = 0xae, - Mul176 = 0xaf, - Mul177 = 0xb0, - Mul178 = 0xb1, - Mul179 = 0xb2, - Mul180 = 0xb3, - Mul181 = 0xb4, - Mul182 = 0xb5, - Mul183 = 0xb6, - Mul184 = 0xb7, - Mul185 = 0xb8, - Mul186 = 0xb9, - Mul187 = 0xba, - Mul188 = 0xbb, - Mul189 = 0xbc, - Mul190 = 0xbd, - Mul191 = 0xbe, - Mul192 = 0xbf, - Mul193 = 0xc0, - Mul194 = 0xc1, - Mul195 = 0xc2, - Mul196 = 0xc3, - Mul197 = 0xc4, - Mul198 = 0xc5, - Mul199 = 0xc6, - Mul200 = 0xc7, - Mul201 = 0xc8, - Mul202 = 0xc9, - Mul203 = 0xca, - Mul204 = 0xcb, - Mul205 = 0xcc, - Mul206 = 0xcd, - Mul207 = 0xce, - Mul208 = 0xcf, - Mul209 = 0xd0, - Mul210 = 0xd1, - Mul211 = 0xd2, - Mul212 = 0xd3, - Mul213 = 0xd4, - Mul214 = 0xd5, - Mul215 = 0xd6, - Mul216 = 0xd7, - Mul217 = 0xd8, - Mul218 = 0xd9, - Mul219 = 0xda, - Mul220 = 0xdb, - Mul221 = 0xdc, - Mul222 = 0xdd, - Mul223 = 0xde, - Mul224 = 0xdf, - Mul225 = 0xe0, - Mul226 = 0xe1, - Mul227 = 0xe2, - Mul228 = 0xe3, - Mul229 = 0xe4, - Mul230 = 0xe5, - Mul231 = 0xe6, - Mul232 = 0xe7, - Mul233 = 0xe8, - Mul234 = 0xe9, - Mul235 = 0xea, - Mul236 = 0xeb, - Mul237 = 0xec, - Mul238 = 0xed, - Mul239 = 0xee, - Mul240 = 0xef, - Mul241 = 0xf0, - Mul242 = 0xf1, - Mul243 = 0xf2, - Mul244 = 0xf3, - Mul245 = 0xf4, - Mul246 = 0xf5, - Mul247 = 0xf6, - Mul248 = 0xf7, - Mul249 = 0xf8, - Mul250 = 0xf9, - Mul251 = 0xfa, - Mul252 = 0xfb, - Mul253 = 0xfc, - Mul254 = 0xfd, - Mul255 = 0xfe, - Mul256 = 0xff, - Mul257 = 0x100, - Mul258 = 0x101, - Mul259 = 0x102, - Mul260 = 0x103, - Mul261 = 0x104, - Mul262 = 0x105, - Mul263 = 0x106, - Mul264 = 0x107, - Mul265 = 0x108, - Mul266 = 0x109, - Mul267 = 0x10a, - Mul268 = 0x10b, - Mul269 = 0x10c, - Mul270 = 0x10d, - Mul271 = 0x10e, - Mul272 = 0x10f, - Mul273 = 0x110, - Mul274 = 0x111, - Mul275 = 0x112, - Mul276 = 0x113, - Mul277 = 0x114, - Mul278 = 0x115, - Mul279 = 0x116, - Mul280 = 0x117, - Mul281 = 0x118, - Mul282 = 0x119, - Mul283 = 0x11a, - Mul284 = 0x11b, - Mul285 = 0x11c, - Mul286 = 0x11d, - Mul287 = 0x11e, - Mul288 = 0x11f, - Mul289 = 0x120, - Mul290 = 0x121, - Mul291 = 0x122, - Mul292 = 0x123, - Mul293 = 0x124, - Mul294 = 0x125, - Mul295 = 0x126, - Mul296 = 0x127, - Mul297 = 0x128, - Mul298 = 0x129, - Mul299 = 0x12a, - Mul300 = 0x12b, - Mul301 = 0x12c, - Mul302 = 0x12d, - Mul303 = 0x12e, - Mul304 = 0x12f, - Mul305 = 0x130, - Mul306 = 0x131, - Mul307 = 0x132, - Mul308 = 0x133, - Mul309 = 0x134, - Mul310 = 0x135, - Mul311 = 0x136, - Mul312 = 0x137, - Mul313 = 0x138, - Mul314 = 0x139, - Mul315 = 0x13a, - Mul316 = 0x13b, - Mul317 = 0x13c, - Mul318 = 0x13d, - Mul319 = 0x13e, - Mul320 = 0x13f, - Mul321 = 0x140, - Mul322 = 0x141, - Mul323 = 0x142, - Mul324 = 0x143, - Mul325 = 0x144, - Mul326 = 0x145, - Mul327 = 0x146, - Mul328 = 0x147, - Mul329 = 0x148, - Mul330 = 0x149, - Mul331 = 0x14a, - Mul332 = 0x14b, - Mul333 = 0x14c, - Mul334 = 0x14d, - Mul335 = 0x14e, - Mul336 = 0x14f, - Mul337 = 0x150, - Mul338 = 0x151, - Mul339 = 0x152, - Mul340 = 0x153, - Mul341 = 0x154, - Mul342 = 0x155, - Mul343 = 0x156, - Mul344 = 0x157, - Mul345 = 0x158, - Mul346 = 0x159, - Mul347 = 0x15a, - Mul348 = 0x15b, - Mul349 = 0x15c, - Mul350 = 0x15d, - Mul351 = 0x15e, - Mul352 = 0x15f, - Mul353 = 0x160, - Mul354 = 0x161, - Mul355 = 0x162, - Mul356 = 0x163, - Mul357 = 0x164, - Mul358 = 0x165, - Mul359 = 0x166, - Mul360 = 0x167, - Mul361 = 0x168, - Mul362 = 0x169, - Mul363 = 0x16a, - Mul364 = 0x16b, - Mul365 = 0x16c, - Mul366 = 0x16d, - Mul367 = 0x16e, - Mul368 = 0x16f, - Mul369 = 0x170, - Mul370 = 0x171, - Mul371 = 0x172, - Mul372 = 0x173, - Mul373 = 0x174, - Mul374 = 0x175, - Mul375 = 0x176, - Mul376 = 0x177, - Mul377 = 0x178, - Mul378 = 0x179, - Mul379 = 0x17a, - Mul380 = 0x17b, - Mul381 = 0x17c, - Mul382 = 0x17d, - Mul383 = 0x17e, - Mul384 = 0x17f, - Mul385 = 0x180, - Mul386 = 0x181, - Mul387 = 0x182, - Mul388 = 0x183, - Mul389 = 0x184, - Mul390 = 0x185, - Mul391 = 0x186, - Mul392 = 0x187, - Mul393 = 0x188, - Mul394 = 0x189, - Mul395 = 0x18a, - Mul396 = 0x18b, - Mul397 = 0x18c, - Mul398 = 0x18d, - Mul399 = 0x18e, - Mul400 = 0x18f, - Mul401 = 0x190, - Mul402 = 0x191, - Mul403 = 0x192, - Mul404 = 0x193, - Mul405 = 0x194, - Mul406 = 0x195, - Mul407 = 0x196, - Mul408 = 0x197, - Mul409 = 0x198, - Mul410 = 0x199, - Mul411 = 0x19a, - Mul412 = 0x19b, - Mul413 = 0x19c, - Mul414 = 0x19d, - Mul415 = 0x19e, - Mul416 = 0x19f, - Mul417 = 0x1a0, - Mul418 = 0x1a1, - Mul419 = 0x1a2, - Mul420 = 0x1a3, - Mul421 = 0x1a4, - Mul422 = 0x1a5, - Mul423 = 0x1a6, - Mul424 = 0x1a7, - Mul425 = 0x1a8, - Mul426 = 0x1a9, - Mul427 = 0x1aa, - Mul428 = 0x1ab, - Mul429 = 0x1ac, - Mul430 = 0x1ad, - Mul431 = 0x1ae, - Mul432 = 0x1af, - Mul433 = 0x1b0, - Mul434 = 0x1b1, - Mul435 = 0x1b2, - Mul436 = 0x1b3, - Mul437 = 0x1b4, - Mul438 = 0x1b5, - Mul439 = 0x1b6, - Mul440 = 0x1b7, - Mul441 = 0x1b8, - Mul442 = 0x1b9, - Mul443 = 0x1ba, - Mul444 = 0x1bb, - Mul445 = 0x1bc, - Mul446 = 0x1bd, - Mul447 = 0x1be, - Mul448 = 0x1bf, - Mul449 = 0x1c0, - Mul450 = 0x1c1, - Mul451 = 0x1c2, - Mul452 = 0x1c3, - Mul453 = 0x1c4, - Mul454 = 0x1c5, - Mul455 = 0x1c6, - Mul456 = 0x1c7, - Mul457 = 0x1c8, - Mul458 = 0x1c9, - Mul459 = 0x1ca, - Mul460 = 0x1cb, - Mul461 = 0x1cc, - Mul462 = 0x1cd, - Mul463 = 0x1ce, - Mul464 = 0x1cf, - Mul465 = 0x1d0, - Mul466 = 0x1d1, - Mul467 = 0x1d2, - Mul468 = 0x1d3, - Mul469 = 0x1d4, - Mul470 = 0x1d5, - Mul471 = 0x1d6, - Mul472 = 0x1d7, - Mul473 = 0x1d8, - Mul474 = 0x1d9, - Mul475 = 0x1da, - Mul476 = 0x1db, - Mul477 = 0x1dc, - Mul478 = 0x1dd, - Mul479 = 0x1de, - Mul480 = 0x1df, - Mul481 = 0x1e0, - Mul482 = 0x1e1, - Mul483 = 0x1e2, - Mul484 = 0x1e3, - Mul485 = 0x1e4, - Mul486 = 0x1e5, - Mul487 = 0x1e6, - Mul488 = 0x1e7, - Mul489 = 0x1e8, - Mul490 = 0x1e9, - Mul491 = 0x1ea, - Mul492 = 0x1eb, - Mul493 = 0x1ec, - Mul494 = 0x1ed, - Mul495 = 0x1ee, - Mul496 = 0x1ef, - Mul497 = 0x1f0, - Mul498 = 0x1f1, - Mul499 = 0x1f2, - Mul500 = 0x1f3, - Mul501 = 0x1f4, - Mul502 = 0x1f5, - Mul503 = 0x1f6, - Mul504 = 0x1f7, - Mul505 = 0x1f8, - Mul506 = 0x1f9, - Mul507 = 0x1fa, - Mul508 = 0x1fb, - Mul509 = 0x1fc, - Mul510 = 0x1fd, - Mul511 = 0x1fe, - Mul512 = 0x1ff, - _, - }; - - pub const PLLRGE = enum(u2) { - /// PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz - FREQ_4TO8MHZ = 0x0, - /// PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz - FREQ_8TO16MHZ = 0x3, - _, - }; - - pub const PLLSRC = enum(u2) { - /// No clock sent to PLL3 - DISABLE = 0x0, - /// MSIS clock selected as PLL3 clock entry - MSIS = 0x1, - /// HSI clock selected as PLL3 clock entry - HSI = 0x2, - /// HSE clock selected as PLL3 clock entry - HSE = 0x3, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const RNGSEL = enum(u2) { - /// HSI48 selected - HSI48 = 0x0, - /// HSI48 / 2 selected, can be used in Range 4 - HSI48_DIV_2 = 0x1, - /// HSI selected - HSI = 0x2, - _, - }; - - pub const RTCSEL = enum(u2) { - /// No clock selected - DISABLE = 0x0, - /// LSE oscillator clock selected - LSE = 0x1, - /// LSI oscillator clock selected - LSI = 0x2, - /// HSE oscillator clock divided by 32 selected - HSE = 0x3, - }; - - pub const SAESSEL = enum(u1) { - /// SHSI selected - SHSI = 0x0, - /// SHSI / 2 selected, can be used in Range 4 - SHSI_DIV_2 = 0x1, - }; - - pub const SAISEL = enum(u3) { - /// PLL2 P (pll2_p_ck) selected - PLL2_P = 0x0, - /// PLL3 P (pll3_p_ck) selected - PLL3_P = 0x1, - /// PLL1 P (pll1_p_ck) selected - PLL1_P = 0x2, - /// input pin AUDIOCLK selected - AUDIOCLK = 0x3, - /// HSI clock selected - HSI = 0x4, - _, - }; - - pub const SDMMCSEL = enum(u1) { - /// ICLK clock selected - ICLK = 0x0, - /// PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) - PLL1_P = 0x1, - }; - - pub const SECURITY = enum(u1) { - /// non secure - NON_SECURE = 0x0, - /// secure - SECURE = 0x1, - }; - - pub const SPI1SEL = enum(u2) { - /// PCLK2 selected - PCLK2 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - /// MSIK selected - MSIK = 0x3, - }; - - pub const SPI2SEL = enum(u2) { - /// PCLK2 selected - PCLK1 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - /// MSIK selected - MSIK = 0x3, - }; - - pub const SPI3SEL = enum(u2) { - /// PCLK2 selected - PCLK3 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - /// MSIK selected - MSIK = 0x3, - }; - - pub const STOPKERWUCK = enum(u1) { - /// MSIK oscillator automatically enabled when exiting Stop mode - MSIK = 0x0, - /// HSI oscillator automatically enabled when exiting Stop mode - HSI = 0x1, - }; - - pub const STOPWUCK = enum(u1) { - /// MSIS oscillator selected as wakeup from stop clock and CSS backup clock - MSIS = 0x0, - /// HSI oscillator selected as wakeup from stop clock and CSS backup clock - HSI = 0x1, - }; - - pub const SW = enum(u2) { - /// MSIS selected as system clock - MSIS = 0x0, - /// HSI selected as system clock - HSI = 0x1, - /// HSE selected as system clock - HSE = 0x2, - /// PLL pll1_r_ck selected as system clock - PLL1_R = 0x3, - }; - - pub const SYSTICKSEL = enum(u2) { - /// HCLK/8 selected - HCLK1_DIV_8 = 0x0, - /// LSI selected - LSI = 0x1, - /// LSE selected - LSE = 0x2, - _, - }; - - pub const TIMICSEL = enum(u3) { - /// No sources can be selected by TIM16, TIM17 and LPTIM2 as internal input capture - DISABLE = 0x0, - /// HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture - HSI256_MSIS1024_MSIS4 = 0x4, - /// HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture - HSI256_MSIS1024_MSIK4 = 0x5, - /// HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture - HSI256_MSIK1024_MSIS4 = 0x6, - /// HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture - HSI256_MSIK1024_MSIK4 = 0x7, - _, - }; - - pub const USART1SEL = enum(u2) { - /// PCLK2 selected - PCLK2 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - /// LSE selected - LSE = 0x3, - }; - - pub const USARTSEL = enum(u2) { - /// PCLK1 selected - PCLK1 = 0x0, - /// SYSCLK selected - SYS = 0x1, - /// HSI selected - HSI = 0x2, - /// LSE selected - LSE = 0x3, - }; - - /// Reset and clock control - pub const RCC = extern struct { - /// RCC clock control register - CR: mmio.Mmio(packed struct(u32) { - /// MSIS clock enable Set and cleared by software. Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator. Set by hardware when used directly or indirectly as system clock. - MSISON: u1, - /// MSI enable for some peripheral kernels Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details). The MSIKERON must be configured at 0 before entering Stop 3 mode. - MSIKERON: u1, - /// MSIS clock ready flag Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON. Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles. - MSISRDY: u1, - /// MSI clock PLL-mode enable Set and cleared by software to enable/disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR). - MSIPLLEN: u1, - /// MSIK clock enable Set and cleared by software. Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator. - MSIKON: u1, - /// MSIK clock ready flag Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON. Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles. - MSIKRDY: u1, - /// MSI clock with PLL mode selection Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0). Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs. - MSIPLLSEL: packed union { - raw: u1, - value: MSIPLLSEL, - }, - /// MSI PLL mode fast startup Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock source. This bit is used only if PLL mode is selected (MSIPLLEN = 1). The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off. - MSIPLLFAST: packed union { - raw: u1, - value: MSIPLLFAST, - }, - /// HSI clock enable Set and cleared by software. Cleared by hardware to stop the HSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI is used directly or indirectly as system clock. - HSION: u1, - /// HSI enable for some peripheral kernels Set and cleared by software to force HSI ON even in Stop modes. Keeping the HSI ON in Stop mode allows the communication speed not to be reduced by the HSI startup time. This bit has no effect on HSION value. Refer to for more details. The HSIKERON must be configured at 0 before entering Stop 3 mode. - HSIKERON: u1, - /// HSI clock ready flag Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI clock cycles. - HSIRDY: u1, - reserved12: u1, - /// HSI48 clock enable Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes. - HSI48ON: u1, - /// HSI48 clock ready flag Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON. - HSI48RDY: u1, - /// SHSI clock enable Set and cleared by software. Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes. - SHSION: u1, - /// SHSI clock ready flag Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION. Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles. - SHSIRDY: u1, - /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. - HSEON: u1, - /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles. - HSERDY: u1, - /// HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. - HSEBYP: u1, - /// Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. - CSSON: u1, - /// HSE external clock bypass mode Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled. - HSEEXT: packed union { - raw: u1, - value: HSEEXT, - }, - reserved24: u3, - /// PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock. - PLLON: u1, - /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. - PLLRDY: u1, - padding: u6, + /// JPEG DHTMem tables + DHTMEM77: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved8: [4]u8, - /// RCC internal clock sources calibration register 1 - ICSCR1: mmio.Mmio(packed struct(u32) { - /// MSIRC3 clock calibration for MSI ranges 12 to 15 These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. - MSICAL3: u5, - /// MSIRC2 clock calibration for MSI ranges 8 to 11 These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. - MSICAL2: u5, - /// MSIRC1 clock calibration for MSI ranges 4 to 7 These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. - MSICAL1: u5, - /// MSIRC0 clock calibration for MSI ranges 0 to 3 These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]. - MSICAL0: u5, - reserved22: u2, - /// MSI bias mode selection Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy. - MSIBIAS: packed union { - raw: u1, - value: MSIBIAS, - }, - /// MSI clock range selection Set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect. After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR. - MSIRGSEL: packed union { - raw: u1, - value: MSIRGSEL, - }, - /// MSIK clock ranges These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0) MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz). - MSIKRANGE: packed union { - raw: u4, - value: MSIRANGE, - }, - /// MSIS clock ranges These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0) MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz). - MSISRANGE: packed union { - raw: u4, - value: MSIRANGE, - }, + /// JPEG DHTMem tables + DHTMEM78: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC internal clock sources calibration register 2 - ICSCR2: mmio.Mmio(packed struct(u32) { - /// MSI clock trimming for ranges 12 to 15 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. - MSITRIM3: u5, - /// MSI clock trimming for ranges 8 to 11 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. - MSITRIM2: u5, - /// MSI clock trimming for ranges 4 to 7 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. - MSITRIM1: u5, - /// MSI clock trimming for ranges 0 to 3 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. - MSITRIM0: u5, - padding: u12, + /// JPEG DHTMem tables + DHTMEM79: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC internal clock sources calibration register 3 - ICSCR3: mmio.Mmio(packed struct(u32) { - /// HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. - HSICAL: u12, - reserved16: u4, - /// HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI. - HSITRIM: u5, - padding: u11, + /// JPEG DHTMem tables + DHTMEM80: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC clock recovery RC register - CRRCR: mmio.Mmio(packed struct(u32) { - /// HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. - HSI48CAL: u9, - padding: u23, + /// JPEG DHTMem tables + DHTMEM81: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved28: [4]u8, - /// RCC clock configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// system clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value. - SW: packed union { - raw: u2, - value: SW, - }, - /// system clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. - SWS: packed union { - raw: u2, - value: SW, - }, - /// wakeup from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW = 10). - STOPWUCK: packed union { - raw: u1, - value: STOPWUCK, - }, - /// wakeup from Stop kernel clock automatic enable selection Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals. - STOPKERWUCK: packed union { - raw: u1, - value: STOPKERWUCK, - }, - reserved24: u18, - /// microcontroller clock output Set and cleared by software. Others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. - MCOSEL: packed union { - raw: u4, - value: MCOSEL, - }, - /// microcontroller clock output prescaler Set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed - MCOPRE: packed union { - raw: u3, - value: MCOPRE, - }, - padding: u1, + /// JPEG DHTMem tables + DHTMEM82: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// AHB prescaler Set and cleared by software to control the division factor of the AHB clock (HCLK). Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xxx: SYSCLK not divided - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (PCLK1). 0xx: HCLK not divided - PPRE1: packed union { - raw: u3, - value: PPRE, - }, - reserved8: u1, - /// APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (PCLK2). 0xx: HCLK not divided - PPRE2: packed union { - raw: u3, - value: PPRE, - }, - reserved12: u1, - /// DSI PHY prescaler This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK). 0xx: DCLK not divided Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. - DPRE: packed union { - raw: u3, - value: DPRE, - }, - reserved16: u1, - /// AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1. - AHB1DIS: u1, - /// AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3. - AHB2DIS1: u1, - /// AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off. - AHB2DIS2: u1, - /// APB1 clock disable This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. - APB1DIS: u1, - /// APB2 clock disable This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off. - APB2DIS: u1, - padding: u11, + /// JPEG DHTMem tables + DHTMEM83: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC clock configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// APB3 prescaler Set and cleared by software to control the division factor of the APB3 clock (PCLK3). 0xx: HCLK not divided - PPRE3: packed union { - raw: u3, - value: PPRE, - }, - reserved16: u9, - /// AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4. - AHB3DIS: u1, - /// APB3 clock disable This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. - APB3DIS: u1, - padding: u14, + /// JPEG DHTMem tables + DHTMEM84: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC PLL1 configuration register - PLL1CFGR: mmio.Mmio(packed struct(u32) { - /// PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC must be 0. - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - /// PLL input frequency range Set and reset by software to select the proper reference frequency range used for PLL. This bit must be written before enabling the PLL. 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz - PLLRGE: packed union { - raw: u2, - value: PLLRGE, - }, - /// PLL fractional latch enable Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator. In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details). - PLLFRACEN: u1, - reserved8: u3, - /// Prescaler for PLL Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). ... - PLLM: packed union { - raw: u4, - value: PLLM, - }, - /// Prescaler for EPOD booster input clock Set and cleared by software to configure the prescaler of the PLL, used for the EPOD booster. The EPOD booster input frequency is PLL input clock frequency/PLLMBOOST. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0) and EPOD Boost mode is disabled (see ). others: reserved - PLLMBOOST: packed union { - raw: u4, - value: PLLMBOOST, - }, - /// PLL DIVP divider output enable Set and reset by software to enable the PLL_p_ck output of the PLL. To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). - PLLPEN: u1, - /// PLL DIVQ divider output enable Set and reset by software to enable the PLL_q_ck output of the PLL. To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). - PLLQEN: u1, - /// PLL DIVR divider output enable Set and reset by software to enable the PLL_r_ck output of the PLL. To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). - PLLREN: u1, - padding: u13, + /// JPEG DHTMem tables + DHTMEM85: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC PLL2 configuration register - PLL2CFGR: mmio.Mmio(packed struct(u32) { - /// PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC must be 0. - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - /// PLL input frequency range Set and reset by software to select the proper reference frequency range used for PLL. This bit must be written before enabling the PLL. 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz - PLLRGE: packed union { - raw: u2, - value: PLLRGE, - }, - /// PLL fractional latch enable Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator. In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details). - PLLFRACEN: u1, - reserved8: u3, - /// Prescaler for PLL Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). ... - PLLM: packed union { - raw: u4, - value: PLLM, - }, - reserved16: u4, - /// PLL DIVP divider output enable Set and reset by software to enable the PLL_p_ck output of the PLL. To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). - PLLPEN: u1, - /// PLL DIVQ divider output enable Set and reset by software to enable the PLL_q_ck output of the PLL. To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). - PLLQEN: u1, - /// PLL DIVR divider output enable Set and reset by software to enable the PLL_r_ck output of the PLL. To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). - PLLREN: u1, - padding: u13, + /// JPEG DHTMem tables + DHTMEM86: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC PLL3 configuration register - PLL3CFGR: mmio.Mmio(packed struct(u32) { - /// PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC must be 0. - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - /// PLL input frequency range Set and reset by software to select the proper reference frequency range used for PLL. This bit must be written before enabling the PLL. 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz - PLLRGE: packed union { - raw: u2, - value: PLLRGE, - }, - /// PLL fractional latch enable Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator. In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details). - PLLFRACEN: u1, - reserved8: u3, - /// Prescaler for PLL Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). ... - PLLM: packed union { - raw: u4, - value: PLLM, - }, - reserved16: u4, - /// PLL DIVP divider output enable Set and reset by software to enable the PLL_p_ck output of the PLL. To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). - PLLPEN: u1, - /// PLL DIVQ divider output enable Set and reset by software to enable the PLL_q_ck output of the PLL. To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). - PLLQEN: u1, - /// PLL DIVR divider output enable Set and reset by software to enable the PLL_r_ck output of the PLL. To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). - PLLREN: u1, - padding: u13, + /// JPEG DHTMem tables + DHTMEM87: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC PLL1 dividers register - PLL1DIVR: mmio.Mmio(packed struct(u32) { - /// Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16 MHz - PLLN: packed union { - raw: u9, - value: PLLN, - }, - /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... - PLLP: packed union { - raw: u7, - value: PLLDIV, - }, - /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLQ: packed union { - raw: u7, - value: PLLDIV, - }, - reserved24: u1, - /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLR: packed union { - raw: u7, - value: PLLDIV, - }, - padding: u1, + /// JPEG DHTMem tables + DHTMEM88: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC PLL1 fractional divider register - PLL1FRACR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1. - PLLFRACN: u13, - padding: u16, + /// JPEG DHTMem tables + DHTMEM89: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC PLL2 dividers configuration register - PLL2DIVR: mmio.Mmio(packed struct(u32) { - /// Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16 MHz - PLLN: packed union { - raw: u9, - value: PLLN, - }, - /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... - PLLP: packed union { - raw: u7, - value: PLLDIV, - }, - /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLQ: packed union { - raw: u7, - value: PLLDIV, - }, - reserved24: u1, - /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLR: packed union { - raw: u7, - value: PLLDIV, - }, - padding: u1, + /// JPEG DHTMem tables + DHTMEM90: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC PLL2 fractional divider register - PLL2FRACR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1. - PLLFRACN: u13, - padding: u16, + /// JPEG DHTMem tables + DHTMEM91: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC PLL3 dividers configuration register - PLL3DIVR: mmio.Mmio(packed struct(u32) { - /// Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16 MHz - PLLN: packed union { - raw: u9, - value: PLLN, - }, - /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... - PLLP: packed union { - raw: u7, - value: PLLDIV, - }, - /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLQ: packed union { - raw: u7, - value: PLLDIV, - }, - reserved24: u1, - /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... - PLLR: packed union { - raw: u7, - value: PLLDIV, - }, - padding: u1, + /// JPEG DHTMem tables + DHTMEM92: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC PLL3 fractional divider register - PLL3FRACR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1. - PLLFRACN: u13, - padding: u16, + /// JPEG DHTMem tables + DHTMEM93: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved80: [4]u8, - /// RCC clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. - LSIRDYIE: u1, - /// LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. - LSERDYIE: u1, - /// MSIS ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization. - MSISRDYIE: u1, - /// HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization. - HSIRDYIE: u1, - /// HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. - HSERDYIE: u1, - /// HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. - HSI48RDYIE: u1, - /// PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock. - PLLRDYIE: u1, - reserved11: u4, - /// MSIK ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization. - MSIKRDYIE: u1, - /// SHSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization. - SHSIRDYIE: u1, - padding: u19, + /// JPEG DHTMem tables + DHTMEM94: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. Cleared by software setting the LSIRDYC bit. - LSIRDYF: u1, - /// LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYIE is set. Cleared by software setting the LSERDYC bit. - LSERDYF: u1, - /// MSIS ready interrupt flag Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set. Cleared by software setting the MSISRDYC bit. - MSISRDYF: u1, - /// HSI ready interrupt flag Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. - HSIRDYF: u1, - /// HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit. - HSERDYF: u1, - /// HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. Cleared by software setting the HSI48RDYC bit. - HSI48RDYF: u1, - /// PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit. - PLLRDYF: u1, - reserved10: u3, - /// Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. - CSSF: u1, - /// MSIK ready interrupt flag Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. Cleared by software setting the MSIKRDYC bit. - MSIKRDYF: u1, - /// SHSI ready interrupt flag Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set. Cleared by software setting the SHSIRDYC bit. - SHSIRDYF: u1, - padding: u19, + /// JPEG DHTMem tables + DHTMEM95: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect. - LSIRDYC: u1, - /// LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect. - LSERDYC: u1, - /// MSIS ready interrupt clear Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect. - MSISRDYC: u1, - /// HSI ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect. - HSIRDYC: u1, - /// HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect. - HSERDYC: u1, - /// HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect. - HSI48RDYC: u1, - /// PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect. - PLLRDYC: u1, - reserved10: u3, - /// Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect. - CSSC: u1, - /// MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect. - MSIKRDYC: u1, - /// SHSI oscillator ready interrupt clear Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect. - SHSIRDYC: u1, - padding: u19, + /// JPEG DHTMem tables + DHTMEM96: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved96: [4]u8, - /// RCC AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 reset Set and cleared by software. - GPDMA1RST: u1, - /// CORDIC reset Set and cleared by software. - CORDICRST: u1, - /// FMAC reset Set and cleared by software. - FMACRST: u1, - /// MDF1 reset Set and cleared by software. - MDF1RST: u1, - reserved12: u8, - /// CRC reset Set and cleared by software. - CRCRST: u1, - reserved15: u2, - /// JPEG reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - JPEGRST: u1, - /// TSC reset Set and cleared by software. - TSCRST: u1, - /// RAMCFG reset Set and cleared by software. - RAMCFGRST: u1, - /// DMA2D reset Set and cleared by software. - DMA2DRST: u1, - /// GFXMMU reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - GFXMMURST: u1, - /// GPU2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - GPU2DRST: u1, - padding: u11, + /// JPEG DHTMem tables + DHTMEM97: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC AHB2 peripheral reset register 1 - AHB2RSTR1: mmio.Mmio(packed struct(u32) { - /// IO port A reset Set and cleared by software. - GPIOARST: u1, - /// IO port B reset Set and cleared by software. - GPIOBRST: u1, - /// IO port C reset Set and cleared by software. - GPIOCRST: u1, - /// IO port D reset Set and cleared by software. - GPIODRST: u1, - /// IO port E reset Set and cleared by software. - GPIOERST: u1, - /// IO port F reset Set and cleared by software. - GPIOFRST: u1, - /// IO port G reset Set and cleared by software. - GPIOGRST: u1, - /// IO port H reset Set and cleared by software. - GPIOHRST: u1, - /// IO port I reset Set and cleared by software. - GPIOIRST: u1, - /// I/O port J reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - GPIOJRST: u1, - /// ADC1 and ADC2 reset This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. - ADC12RST: u1, - reserved12: u1, - /// DCMI and PSSI reset Set and cleared by software. - DCMIRST: u1, - reserved14: u1, - /// OTG_FS reset Set and cleared by software. - USB_OTG_FSRST: u1, - reserved16: u1, - /// AES hardware accelerator reset Set and cleared by software. - AESRST: u1, - /// Hash reset Set and cleared by software. - HASHRST: u1, - /// Random number generator reset Set and cleared by software. - RNGRST: u1, - /// PKA reset Set and cleared by software. - PKARST: u1, - /// SAES hardware accelerator reset Set and cleared by software. - SAESRST: u1, - /// OCTOSPIM reset Set and cleared by software. - OCTOSPIMRST: u1, - reserved23: u1, - /// OTFDEC1 reset Set and cleared by software. - OTFDEC1RST: u1, - /// OTFDEC2 reset Set and cleared by software. - OTFDEC2RST: u1, - reserved27: u2, - /// SDMMC1 reset Set and cleared by software. - SDMMC1RST: u1, - /// SDMMC2 reset Set and cleared by software. - SDMMC2RST: u1, - padding: u3, + /// JPEG DHTMem tables + DHTMEM98: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC AHB2 peripheral reset register 2 - AHB2RSTR2: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller reset Set and cleared by software. - FSMCRST: u1, - reserved4: u3, - /// OCTOSPI1 reset Set and cleared by software. - OCTOSPI1RST: u1, - reserved8: u3, - /// OCTOSPI2 reset Set and cleared by software. - OCTOSPI2RST: u1, - reserved12: u3, - /// HSPI1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - HSPI1RST: u1, - padding: u19, + /// JPEG DHTMem tables + DHTMEM99: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC AHB3 peripheral reset register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - /// LPGPIO1 reset Set and cleared by software. - LPGPIO1RST: u1, - reserved5: u4, - /// ADC4 reset Set and cleared by software. - ADC4RST: u1, - /// DAC1 reset Set and cleared by software. - DAC1RST: u1, - reserved9: u2, - /// LPDMA1 reset Set and cleared by software. - LPDMA1RST: u1, - /// ADF1 reset Set and cleared by software. - ADF1RST: u1, - padding: u21, + /// JPEG DHTMem tables + DHTMEM100: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved116: [4]u8, - /// RCC APB1 peripheral reset register 1 - APB1RSTR1: mmio.Mmio(packed struct(u32) { - /// TIM2 reset Set and cleared by software. - TIM2RST: u1, - /// TIM3 reset Set and cleared by software. - TIM3RST: u1, - /// TIM4 reset Set and cleared by software. - TIM4RST: u1, - /// TIM5 reset Set and cleared by software. - TIM5RST: u1, - /// TIM6 reset Set and cleared by software. - TIM6RST: u1, - /// TIM7 reset Set and cleared by software. - TIM7RST: u1, - reserved14: u8, - /// SPI2 reset Set and cleared by software. - SPI2RST: u1, - reserved17: u2, - /// USART2 reset Set and cleared by software. - USART2RST: u1, - /// USART3 reset Set and cleared by software. - USART3RST: u1, - /// UART4 reset Set and cleared by software. - UART4RST: u1, - /// UART5 reset Set and cleared by software. - UART5RST: u1, - /// I2C1 reset Set and cleared by software. - I2C1RST: u1, - /// I2C2 reset Set and cleared by software. - I2C2RST: u1, - reserved24: u1, - /// CRS reset Set and cleared by software. - CRSRST: u1, - /// USART6 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - USART6RST: u1, - padding: u6, + /// JPEG DHTMem tables + DHTMEM101: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC APB1 peripheral reset register 2 - APB1RSTR2: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// I2C4 reset Set and cleared by software - I2C4RST: u1, - reserved5: u3, - /// LPTIM2 reset Set and cleared by software. - LPTIM2RST: u1, - /// I2C5 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - I2C5RST: u1, - /// I2C6 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - I2C6RST: u1, - reserved9: u1, - /// FDCAN1 reset Set and cleared by software. - FDCAN1RST: u1, - reserved23: u13, - /// UCPD1 reset Set and cleared by software. - UCPD1RST: u1, - padding: u8, + /// JPEG DHTMem tables + DHTMEM102: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 reset Set and cleared by software. - TIM1RST: u1, - /// SPI1 reset Set and cleared by software. - SPI1RST: u1, - /// TIM8 reset Set and cleared by software. - TIM8RST: u1, - /// USART1 reset Set and cleared by software. - USART1RST: u1, - reserved16: u1, - /// TIM15 reset Set and cleared by software. - TIM15RST: u1, - /// TIM16 reset Set and cleared by software. - TIM16RST: u1, - /// TIM17 reset Set and cleared by software. - TIM17RST: u1, - reserved21: u2, - /// SAI1 reset Set and cleared by software. - SAI1RST: u1, - /// SAI2 reset Set and cleared by software. - SAI2RST: u1, - reserved24: u1, - /// USB reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - USBRST: u1, - /// GFXTIM reset This bit is set and cleared by software. Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - GFXTIMRST: u1, - /// LTDC reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - LTDCRST: u1, - /// DSI reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - DSIRST: u1, - padding: u4, + /// JPEG DHTMem tables + DHTMEM103: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC APB3 peripheral reset register - APB3RSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG reset Set and cleared by software. - SYSCFGRST: u1, - reserved5: u3, - /// SPI3 reset Set and cleared by software. - SPI3RST: u1, - /// LPUART1 reset Set and cleared by software. - LPUART1RST: u1, - /// I2C3 reset Set and cleared by software. - I2C3RST: u1, - reserved11: u3, - /// LPTIM1 reset Set and cleared by software. - LPTIM1RST: u1, - /// LPTIM3 reset Set and cleared by software. - LPTIM3RST: u1, - /// LPTIM4 reset Set and cleared by software. - LPTIM4RST: u1, - /// OPAMP reset Set and cleared by software. - OPAMPRST: u1, - /// COMP reset Set and cleared by software. - COMPRST: u1, - reserved20: u4, - /// VREFBUF reset Set and cleared by software. - VREFRST: u1, - padding: u11, + reserved1280: [4]u8, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_0: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved136: [4]u8, - /// RCC AHB1 peripheral clock enable register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 clock enable Set and cleared by software. - GPDMA1EN: u1, - /// CORDIC clock enable Set and cleared by software. - CORDICEN: u1, - /// FMAC clock enable Set and reset by software. - FMACEN: u1, - /// MDF1 clock enable Set and reset by software. - MDF1EN: u1, - reserved8: u4, - /// FLASH clock enable Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode. - FLASHEN: u1, - reserved12: u3, - /// CRC clock enable Set and cleared by software. - CRCEN: u1, - reserved15: u2, - /// JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - JPEGEN: u1, - /// Touch sensing controller clock enable Set and cleared by software. - TSCEN: u1, - /// RAMCFG clock enable Set and cleared by software. - RAMCFGEN: u1, - /// DMA2D clock enable Set and cleared by software. - DMA2DEN: u1, - /// GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - GFXMMUEN: u1, - /// GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - GPU2DEN: u1, - /// DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - DCACHE2EN: u1, - reserved24: u2, - /// GTZC1 clock enable Set and reset by software. - GTZC1EN: u1, - reserved28: u3, - /// BKPSRAM clock enable Set and reset by software. - BKPSRAMEN: u1, - reserved30: u1, - /// DCACHE1 clock enable Set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed. - DCACHE1EN: u1, - /// SRAM1 clock enable Set and reset by software. - SRAM1EN: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_1: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC AHB2 peripheral clock enable register 1 - AHB2ENR1: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable Set and cleared by software. - GPIOAEN: u1, - /// IO port B clock enable Set and cleared by software. - GPIOBEN: u1, - /// IO port C clock enable Set and cleared by software. - GPIOCEN: u1, - /// IO port D clock enable Set and cleared by software. - GPIODEN: u1, - /// IO port E clock enable Set and cleared by software. - GPIOEEN: u1, - /// IO port F clock enable Set and cleared by software. - GPIOFEN: u1, - /// IO port G clock enable Set and cleared by software. - GPIOGEN: u1, - /// IO port H clock enable Set and cleared by software. - GPIOHEN: u1, - /// IO port I clock enable Set and cleared by software. - GPIOIEN: u1, - /// I/O port J clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - GPIOJEN: u1, - /// ADC1 and ADC2 clock enable This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. - ADC12EN: u1, - reserved12: u1, - /// DCMI and PSSI clock enable Set and cleared by software. - DCMIEN: u1, - reserved14: u1, - /// OTG_FS clock enable Set and cleared by software. - USB_OTG_FSEN: u1, - /// OTG_HS PHY clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - USB_OTG_HS_PHYEN: u1, - /// AES clock enable Set and cleared by software. - AESEN: u1, - /// HASH clock enable Set and cleared by software - HASHEN: u1, - /// RNG clock enable Set and cleared by software. - RNGEN: u1, - /// PKA clock enable Set and cleared by software. - PKAEN: u1, - /// SAES clock enable Set and cleared by software. - SAESEN: u1, - /// OCTOSPIM clock enable Set and cleared by software. - OCTOSPIMEN: u1, - reserved23: u1, - /// OTFDEC1 clock enable Set and cleared by software. - OTFDEC1EN: u1, - /// OTFDEC2 clock enable Set and cleared by software. - OTFDEC2EN: u1, - reserved27: u2, - /// SDMMC1 clock enable Set and cleared by software. - SDMMC1EN: u1, - /// SDMMC2 clock enable Set and cleared by software. - SDMMC2EN: u1, - reserved30: u1, - /// SRAM2 clock enable Set and reset by software. - SRAM2EN: u1, - /// SRAM3 clock enable Set and reset by software. - SRAM3EN: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_2: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC AHB2 peripheral clock enable register 2 - AHB2ENR2: mmio.Mmio(packed struct(u32) { - /// FSMC clock enable Set and cleared by software. - FSMCEN: u1, - reserved4: u3, - /// OCTOSPI1 clock enable Set and cleared by software. - OCTOSPI1EN: u1, - reserved8: u3, - /// OCTOSPI2 clock enable Set and cleared by software. - OCTOSPI2EN: u1, - reserved12: u3, - /// HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - HSPI1EN: u1, - reserved30: u17, - /// SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - SRAM6EN: u1, - /// SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - SRAM5EN: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_3: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC AHB3 peripheral clock enable register - AHB3ENR: mmio.Mmio(packed struct(u32) { - /// LPGPIO1 enable Set and cleared by software. - LPGPIO1EN: u1, - reserved2: u1, - /// PWR clock enable Set and cleared by software. - PWREN: u1, - reserved5: u2, - /// ADC4 clock enable Set and cleared by software. - ADC4EN: u1, - /// DAC1 clock enable Set and cleared by software. - DAC1EN: u1, - reserved9: u2, - /// LPDMA1 clock enable Set and cleared by software. - LPDMA1EN: u1, - /// ADF1 clock enable Set and cleared by software. - ADF1EN: u1, - reserved12: u1, - /// GTZC2 clock enable Set and cleared by software. - GTZC2EN: u1, - reserved31: u18, - /// SRAM4 clock enable Set and reset by software. - SRAM4EN: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_4: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved156: [4]u8, - /// RCC APB1 peripheral clock enable register 1 - APB1ENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 clock enable Set and cleared by software. - TIM2EN: u1, - /// TIM3 clock enable Set and cleared by software. - TIM3EN: u1, - /// TIM4 clock enable Set and cleared by software. - TIM4EN: u1, - /// TIM5 clock enable Set and cleared by software. - TIM5EN: u1, - /// TIM6 clock enable Set and cleared by software. - TIM6EN: u1, - /// TIM7 clock enable Set and cleared by software. - TIM7EN: u1, - reserved11: u5, - /// WWDG clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. - WWDGEN: u1, - reserved14: u2, - /// SPI2 clock enable Set and cleared by software. - SPI2EN: u1, - reserved17: u2, - /// USART2 clock enable Set and cleared by software. - USART2EN: u1, - /// USART3 clock enable Set and cleared by software. - USART3EN: u1, - /// UART4 clock enable Set and cleared by software. - UART4EN: u1, - /// UART5 clock enable Set and cleared by software. - UART5EN: u1, - /// I2C1 clock enable Set and cleared by software. - I2C1EN: u1, - /// I2C2 clock enable Set and cleared by software. - I2C2EN: u1, - reserved24: u1, - /// CRS clock enable Set and cleared by software. - CRSEN: u1, - /// USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - USART6EN: u1, - padding: u6, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_5: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC APB1 peripheral clock enable register 2 - APB1ENR2: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// I2C4 clock enable Set and cleared by software - I2C4EN: u1, - reserved5: u3, - /// LPTIM2 clock enable Set and cleared by software. - LPTIM2EN: u1, - /// I2C5 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - I2C5EN: u1, - /// I2C6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - I2C6EN: u1, - reserved9: u1, - /// FDCAN1 clock enable Set and cleared by software. - FDCAN1EN: u1, - reserved23: u13, - /// UCPD1 clock enable Set and cleared by software. - UCPD1EN: u1, - padding: u8, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_6: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC APB2 peripheral clock enable register - APB2ENR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 clock enable Set and cleared by software. - TIM1EN: u1, - /// SPI1 clock enable Set and cleared by software. - SPI1EN: u1, - /// TIM8 clock enable Set and cleared by software. - TIM8EN: u1, - /// USART1clock enable Set and cleared by software. - USART1EN: u1, - reserved16: u1, - /// TIM15 clock enable Set and cleared by software. - TIM15EN: u1, - /// TIM16 clock enable Set and cleared by software. - TIM16EN: u1, - /// TIM17 clock enable Set and cleared by software. - TIM17EN: u1, - reserved21: u2, - /// SAI1 clock enable Set and cleared by software. - SAI1EN: u1, - /// SAI2 clock enable Set and cleared by software. - SAI2EN: u1, - reserved24: u1, - /// USB clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - USBEN: u1, - /// GFXTIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - GFXTIMEN: u1, - /// LTDC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - LTDCEN: u1, - /// DSI clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - DSIEN: u1, - padding: u4, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_7: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC APB3 peripheral clock enable register - APB3ENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG clock enable Set and cleared by software. - SYSCFGEN: u1, - reserved5: u3, - /// SPI3 clock enable Set and cleared by software. - SPI3EN: u1, - /// LPUART1 clock enable Set and cleared by software. - LPUART1EN: u1, - /// I2C3 clock enable Set and cleared by software. - I2C3EN: u1, - reserved11: u3, - /// LPTIM1 clock enable Set and cleared by software. - LPTIM1EN: u1, - /// LPTIM3 clock enable Set and cleared by software. - LPTIM3EN: u1, - /// LPTIM4 clock enable Set and cleared by software. - LPTIM4EN: u1, - /// OPAMP clock enable Set and cleared by software. - OPAMPEN: u1, - /// COMP clock enable Set and cleared by software. - COMPEN: u1, - reserved20: u4, - /// VREFBUF clock enable Set and cleared by software. - VREFEN: u1, - /// RTC and TAMP APB clock enable Set and cleared by software. - RTCAPBEN: u1, - padding: u10, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_8: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved176: [4]u8, - /// RCC AHB1 peripheral clocks enable in Sleep and Stop modes register - AHB1SMENR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - GPDMA1SMEN: u1, - /// CORDIC clocks enable during Sleep and Stop modes Set and cleared by software during Sleep mode. - CORDICSMEN: u1, - /// FMAC clocks enable during Sleep and Stop modes. Set and cleared by software. - FMACSMEN: u1, - /// MDF1 clocks enable during Sleep and Stop modes. Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - MDF1SMEN: u1, - reserved8: u4, - /// FLASH clocks enable during Sleep and Stop modes Set and cleared by software. - FLASHSMEN: u1, - reserved12: u3, - /// CRC clocks enable during Sleep and Stop modes Set and cleared by software. - CRCSMEN: u1, - reserved15: u2, - /// JPEG clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - JPEGSMEN: u1, - /// TSC clocks enable during Sleep and Stop modes Set and cleared by software. - TSCSMEN: u1, - /// RAMCFG clocks enable during Sleep and Stop modes Set and cleared by software. - RAMCFGSMEN: u1, - /// DMA2D clocks enable during Sleep and Stop modes Set and cleared by software. - DMA2DSMEN: u1, - /// GFXMMU clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - GFXMMUSMEN: u1, - /// GPU2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - GPU2DSMEN: u1, - /// DCACHE2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - DCACHE2SMEN: u1, - reserved24: u2, - /// GTZC1 clocks enable during Sleep and Stop modes Set and cleared by software. - GTZC1SMEN: u1, - reserved28: u3, - /// BKPSRAM clocks enable during Sleep and Stop modes Set and cleared by software - BKPSRAMSMEN: u1, - /// ICACHE clocks enable during Sleep and Stop modes Set and cleared by software. - ICACHESMEN: u1, - /// DCACHE1 clocks enable during Sleep and Stop modes Set and cleared by software. - DCACHE1SMEN: u1, - /// SRAM1 clocks enable during Sleep and Stop modes Set and cleared by software. - SRAM1SMEN: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_9: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 1 - AHB2SMENR1: mmio.Mmio(packed struct(u32) { - /// IO port A clocks enable during Sleep and Stop modes Set and cleared by software. - GPIOASMEN: u1, - /// IO port B clocks enable during Sleep and Stop modes Set and cleared by software. - GPIOBSMEN: u1, - /// IO port C clocks enable during Sleep and Stop modes Set and cleared by software. - GPIOCSMEN: u1, - /// IO port D clocks enable during Sleep and Stop modes Set and cleared by software. - GPIODSMEN: u1, - /// IO port E clocks enable during Sleep and Stop modes Set and cleared by software. - GPIOESMEN: u1, - /// IO port F clocks enable during Sleep and Stop modes Set and cleared by software. - GPIOFSMEN: u1, - /// IO port G clocks enable during Sleep and Stop modes Set and cleared by software. - GPIOGSMEN: u1, - /// IO port H clocks enable during Sleep and Stop modes Set and cleared by software. - GPIOHSMEN: u1, - /// IO port I clocks enable during Sleep and Stop modes Set and cleared by software. - GPIOISMEN: u1, - /// I/O port J clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - GPIOJSMEN: u1, - /// ADC1 and ADC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. - ADC12SMEN: u1, - reserved12: u1, - /// DCMI and PSSI clocks enable during Sleep and Stop modes Set and cleared by software. - DCMISMEN: u1, - reserved14: u1, - /// OTG_FS clocks enable during Sleep and Stop modes Set and cleared by software. - USB_OTG_FSSMEN: u1, - /// OTG_HS PHY clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - USB_OTG_HS_PHYSMEN: u1, - /// AES clock enable during Sleep and Stop modes Set and cleared by software - AESSMEN: u1, - /// HASH clock enable during Sleep and Stop modes Set and cleared by software - HASHSMEN: u1, - /// Random number generator (RNG) clocks enable during Sleep and Stop modes Set and cleared by software. - RNGSMEN: u1, - /// PKA clocks enable during Sleep and Stop modes Set and cleared by software. - PKASMEN: u1, - /// SAES accelerator clocks enable during Sleep and Stop modes Set and cleared by software. - SAESSMEN: u1, - /// OCTOSPIM clocks enable during Sleep and Stop modes Set and cleared by software. - OCTOSPIMSMEN: u1, - reserved23: u1, - /// OTFDEC1 clocks enable during Sleep and Stop modes Set and cleared by software. - OTFDEC1SMEN: u1, - /// OTFDEC2 clocks enable during Sleep and Stop modes Set and cleared by software. - OTFDEC2SMEN: u1, - reserved27: u2, - /// SDMMC1 clocks enable during Sleep and Stop modes Set and cleared by software. - SDMMC1SMEN: u1, - /// SDMMC2 clocks enable during Sleep and Stop modes Set and cleared by software. - SDMMC2SMEN: u1, - reserved30: u1, - /// SRAM2 clocks enable during Sleep and Stop modes Set and cleared by software. - SRAM2SMEN: u1, - /// SRAM3 clocks enable during Sleep and Stop modes Set and cleared by software. - SRAM3SMEN: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_10: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 2 - AHB2SMENR2: mmio.Mmio(packed struct(u32) { - /// FSMC clocks enable during Sleep and Stop modes Set and cleared by software. - FSMCSMEN: u1, - reserved4: u3, - /// OCTOSPI1 clocks enable during Sleep and Stop modes Set and cleared by software. - OCTOSPI1SMEN: u1, - reserved8: u3, - /// OCTOSPI2 clocks enable during Sleep and Stop modes Set and cleared by software. - OCTOSPI2SMEN: u1, - reserved12: u3, - /// HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - HSPI1SMEN: u1, - reserved30: u17, - /// SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - SRAM6SMEN: u1, - /// SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - SRAM5SMEN: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_11: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC AHB3 peripheral clocks enable in Sleep and Stop modes register - AHB3SMENR: mmio.Mmio(packed struct(u32) { - /// LPGPIO1 enable during Sleep and Stop modes Set and cleared by software. - LPGPIO1SMEN: u1, - reserved2: u1, - /// PWR clock enable during Sleep and Stop modes Set and cleared by software. - PWRSMEN: u1, - reserved5: u2, - /// ADC4 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - ADC4SMEN: u1, - /// DAC1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - DAC1SMEN: u1, - reserved9: u2, - /// LPDMA1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPDMA1SMEN: u1, - /// ADF1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - ADF1SMEN: u1, - reserved12: u1, - /// GTZC2 clock enable during Sleep and Stop modes Set and cleared by software. - GTZC2SMEN: u1, - reserved31: u18, - /// SRAM4 clocks enable during Sleep and Stop modes Set and cleared by software. - SRAM4SMEN: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_12: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved196: [4]u8, - /// RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1 - APB1SMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 clocks enable during Sleep and Stop modes Set and cleared by software. - TIM2SMEN: u1, - /// TIM3 clocks enable during Sleep and Stop modes Set and cleared by software. - TIM3SMEN: u1, - /// TIM4 clocks enable during Sleep and Stop modes Set and cleared by software. - TIM4SMEN: u1, - /// TIM5 clocks enable during Sleep and Stop modes Set and cleared by software. - TIM5SMEN: u1, - /// TIM6 clocks enable during Sleep and Stop modes Set and cleared by software. - TIM6SMEN: u1, - /// TIM7 clocks enable during Sleep and Stop modes Set and cleared by software. - TIM7SMEN: u1, - reserved11: u5, - /// Window watchdog clocks enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated. - WWDGSMEN: u1, - reserved14: u2, - /// SPI2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - SPI2SMEN: u1, - reserved17: u2, - /// USART2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - USART2SMEN: u1, - /// USART3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - USART3SMEN: u1, - /// UART4 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - UART4SMEN: u1, - /// UART5 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - UART5SMEN: u1, - /// I2C1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - I2C1SMEN: u1, - /// I2C2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - I2C2SMEN: u1, - reserved24: u1, - /// CRS clock enable during Sleep and Stop modes Set and cleared by software. - CRSSMEN: u1, - /// USART6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - USART6SMEN: u1, - padding: u6, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_13: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 - APB1SMENR2: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// I2C4 clocks enable during Sleep and Stop modes Set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. - I2C4SMEN: u1, - reserved5: u3, - /// LPTIM2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPTIM2SMEN: u1, - /// I2C5 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - I2C5SMEN: u1, - /// I2C6 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - I2C6SMEN: u1, - reserved9: u1, - /// FDCAN1 clocks enable during Sleep and Stop modes Set and cleared by software. - FDCAN1SMEN: u1, - reserved23: u13, - /// UCPD1 clocks enable during Sleep and Stop modes Set and cleared by software. - UCPD1SMEN: u1, - padding: u8, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_14: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC APB2 peripheral clocks enable in Sleep and Stop modes register - APB2SMENR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 clocks enable during Sleep and Stop modes Set and cleared by software. - TIM1SMEN: u1, - /// SPI1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - SPI1SMEN: u1, - /// TIM8 clocks enable during Sleep and Stop modes Set and cleared by software. - TIM8SMEN: u1, - /// USART1clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - USART1SMEN: u1, - reserved16: u1, - /// TIM15 clocks enable during Sleep and Stop modes Set and cleared by software. - TIM15SMEN: u1, - /// TIM16 clocks enable during Sleep and Stop modes Set and cleared by software. - TIM16SMEN: u1, - /// TIM17 clocks enable during Sleep and Stop modes Set and cleared by software. - TIM17SMEN: u1, - reserved21: u2, - /// SAI1 clocks enable during Sleep and Stop modes Set and cleared by software. - SAI1SMEN: u1, - /// SAI2 clocks enable during Sleep and Stop modes Set and cleared by software. - SAI2SMEN: u1, - reserved24: u1, - /// USB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - USBSMEN: u1, - /// GFXTIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - GFXTIMSMEN: u1, - /// LTDC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - LTDCSMEN: u1, - /// DSI clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - DSISMEN: u1, - padding: u4, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_15: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC APB3 peripheral clock enable in Sleep and Stop modes register - APB3SMENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG clocks enable during Sleep and Stop modes Set and cleared by software. - SYSCFGSMEN: u1, - reserved5: u3, - /// SPI3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - SPI3SMEN: u1, - /// LPUART1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPUART1SMEN: u1, - /// I2C3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - I2C3SMEN: u1, - reserved11: u3, - /// LPTIM1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPTIM1SMEN: u1, - /// LPTIM3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPTIM3SMEN: u1, - /// LPTIM4 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPTIM4SMEN: u1, - /// OPAMP clocks enable during Sleep and Stop modes Set and cleared by software. - OPAMPSMEN: u1, - /// COMP clocks enable during Sleep and Stop modes Set and cleared by software. - COMPSMEN: u1, - reserved20: u4, - /// VREFBUF clocks enable during Sleep and Stop modes Set and cleared by software. - VREFSMEN: u1, - /// RTC and TAMP APB clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - RTCAPBSMEN: u1, - padding: u10, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_16: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved216: [4]u8, - /// RCC SmartRun domain peripheral autonomous mode register - SRDAMR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// SPI3 autonomous mode enable in Stop 0,1, 2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - SPI3AMEN: u1, - /// LPUART1 autonomous mode enable in Stop 0,1, 2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPUART1AMEN: u1, - /// I2C3 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - I2C3AMEN: u1, - reserved11: u3, - /// LPTIM1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPTIM1AMEN: u1, - /// LPTIM3 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPTIM3AMEN: u1, - /// LPTIM4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPTIM4AMEN: u1, - /// OPAMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. - OPAMPAMEN: u1, - /// COMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. - COMPAMEN: u1, - reserved20: u4, - /// VREFBUF autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. - VREFAMEN: u1, - /// RTC and TAMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - RTCAPBAMEN: u1, - reserved25: u3, - /// ADC4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - ADC4AMEN: u1, - /// LPGPIO1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. - LPGPIO1AMEN: u1, - /// DAC1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - DAC1AMEN: u1, - /// LPDMA1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - LPDMA1AMEN: u1, - /// ADF1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. - ADF1AMEN: u1, - reserved31: u1, - /// SRAM4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. - SRAM4AMEN: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_17: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved224: [4]u8, - /// RCC peripherals independent clock configuration register 1 - CCIPR1: mmio.Mmio(packed struct(u32) { - /// USART1 kernel clock source selection This bits are used to select the USART1 kernel clock source. Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. - USART1SEL: packed union { - raw: u2, - value: USART1SEL, - }, - /// USART2 kernel clock source selection This bits are used to select the USART2 kernel clock source. Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. - USART2SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// USART3 kernel clock source selection This bits are used to select the USART3 kernel clock source. Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. - USART3SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// UART4 kernel clock source selection This bits are used to select the UART4 kernel clock source. Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. - UART4SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. - UART5SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK. - I2C1SEL: packed union { - raw: u2, - value: I2CSEL, - }, - /// I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK. - I2C2SEL: packed union { - raw: u2, - value: I2CSEL, - }, - /// I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK. - I2C4SEL: packed union { - raw: u2, - value: I2CSEL, - }, - /// SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK. - SPI2SEL: packed union { - raw: u2, - value: SPI2SEL, - }, - /// Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1. - LPTIM2SEL: packed union { - raw: u2, - value: LPTIM2SEL, - }, - /// SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK. - SPI1SEL: packed union { - raw: u2, - value: SPI1SEL, - }, - /// SysTick clock source selection These bits are used to select the SysTick clock source. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry. - SYSTICKSEL: packed union { - raw: u2, - value: SYSTICKSEL, - }, - /// FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source. - FDCAN1SEL: packed union { - raw: u2, - value: FDCANSEL, - }, - /// intermediate clock source selection These bits are used to select the clock source used by OTG_FS and SDMMC. - ICLKSEL: packed union { - raw: u2, - value: ICLKSEL, - }, - reserved29: u1, - /// Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS. When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture. 0xx: HSI, MSIK and MSIS dividers disabled Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division. - TIMICSEL: packed union { - raw: u3, - value: TIMICSEL, - }, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_18: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC peripherals independent clock configuration register 2 - CCIPR2: mmio.Mmio(packed struct(u32) { - /// MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. others: reserved - MDF1SEL: packed union { - raw: u3, - value: MDFSEL, - }, - reserved5: u2, - /// SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. - SAI1SEL: packed union { - raw: u3, - value: SAISEL, - }, - /// SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. - SAI2SEL: packed union { - raw: u3, - value: SAISEL, - }, - /// SAES kernel clock source selection This bit is used to select the SAES kernel clock source. - SAESSEL: packed union { - raw: u1, - value: SAESSEL, - }, - /// RNGSEL kernel clock source selection These bits are used to select the RNG kernel clock source. - RNGSEL: packed union { - raw: u2, - value: RNGSEL, - }, - /// SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC. - SDMMCSEL: packed union { - raw: u1, - value: SDMMCSEL, - }, - /// DSI kernel clock source selection This bit is used to select the DSI kernel clock source. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value. - DSISEL: packed union { - raw: u1, - value: DSISEL, - }, - /// USART6 kernel clock source selection These bits are used to select the USART6 kernel clock source. The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. - USART6SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// LTDC kernel clock source selection This bit is used to select the LTDC kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. - LTDCSEL: packed union { - raw: u1, - value: LTDCSEL, - }, - reserved20: u1, - /// OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source. - OCTOSPISEL: packed union { - raw: u2, - value: OCTOSPISEL, - }, - /// HSPI1 kernel clock source selection These bits are used to select the HSPI1 kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. - HSPI1SEL: packed union { - raw: u2, - value: HSPISEL, - }, - /// I2C5 kernel clock source selection These bits are used to select the I2C5 kernel clock source. The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. - I2C5SEL: packed union { - raw: u2, - value: I2CSEL, - }, - /// I2C6 kernel clock source selection These bits are used to select the I2C6 kernel clock source. The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. - I2C6SEL: packed union { - raw: u2, - value: I2CSEL, - }, - reserved30: u2, - /// OTG_HS PHY kernel clock source selection These bits are used to select the OTG_HS PHY kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. - OTGHSSEL: packed union { - raw: u2, - value: OTGHSSEL, - }, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_19: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC peripherals independent clock configuration register 3 - CCIPR3: mmio.Mmio(packed struct(u32) { - /// LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. others: reserved Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI, LSE or MSIK. - LPUART1SEL: packed union { - raw: u3, - value: LPUSARTSEL, - }, - /// SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK. - SPI3SEL: packed union { - raw: u2, - value: SPI3SEL, - }, - reserved6: u1, - /// I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK. - I2C3SEL: packed union { - raw: u2, - value: I2C3SEL, - }, - /// LPTIM3 and LPTIM4 kernel clock source selection These bits are used to select the LPTIM3 and LPTIM4 kernel clock source. Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1. - LPTIM34SEL: packed union { - raw: u2, - value: LPTIMSEL, - }, - /// LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1. - LPTIM1SEL: packed union { - raw: u2, - value: LPTIMSEL, - }, - /// ADC1, ADC4 and DAC1 kernel clock source selection These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source. others: reserved Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode). - ADCDACSEL: packed union { - raw: u3, - value: ADCDACSEL, - }, - /// DAC1 sample and hold clock source selection This bit is used to select the DAC1 sample and hold clock source. - DAC1SEL: packed union { - raw: u1, - value: DACSEL, - }, - /// ADF1 kernel clock source selection These bits are used to select the ADF1 kernel clock source. others: reserved Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK. - ADF1SEL: packed union { - raw: u3, - value: ADFSEL, - }, - padding: u13, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_20: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved240: [4]u8, - /// RCC Backup domain control register - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enable Set and cleared by software. - LSEON: u1, - /// LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. - LSERDY: u1, - /// LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). - LSEBYP: u1, - /// LSE oscillator drive capability Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in 'Xtal mode when it is not in bypass mode. - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// CSS on LSE enable Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit. - LSECSSON: u1, - /// CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE). - LSECSSD: u1, - /// LSE system clock (LSESYS) enable Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE. - LSESYSEN: u1, - /// RTC and TAMP clock source selection Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them. - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved11: u1, - /// LSE system clock (LSESYS) ready Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. - LSESYSRDY: u1, - /// LSE clock glitch filter enable Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0) - LSEGFON: u1, - reserved15: u2, - /// RTC and TAMP clock enable Set and cleared by software. - RTCEN: u1, - /// Backup domain software reset Set and cleared by software. - BDRST: u1, - reserved24: u7, - /// Low-speed clock output (LSCO) enable Set and cleared by software. - LSCOEN: u1, - /// Low-speed clock output selection Set and cleared by software. - LSCOSEL: packed union { - raw: u1, - value: LSCOSEL, - }, - /// LSI oscillator enable Set and cleared by software. - LSION: u1, - /// LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0. - LSIRDY: u1, - /// Low-speed clock divider configuration Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. - LSIPREDIV: packed union { - raw: u1, - value: LSIPREDIV, - }, - padding: u3, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_21: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC control/status register - CSR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// MSIK range after Standby mode Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing the MSIKSRANGE does not change the current MSIK frequency. - MSIKSRANGE: packed union { - raw: u4, - value: MSIXSRANGE, - }, - /// MSIS range after Standby mode Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing the MSISSRANGE does not change the current MSIS frequency. - MSISSRANGE: packed union { - raw: u4, - value: MSIXSRANGE, - }, - reserved23: u7, - /// Remove reset flag Set by software to clear the reset flags. - RMVF: u1, - reserved25: u1, - /// Option byte loader reset flag Set by hardware when a reset from the option byte loading occurs. Cleared by writing to the RMVF bit. - OBLRSTF: u1, - /// NRST pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. - PINRSTF: u1, - /// BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit. - BORRSTF: u1, - /// Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. - SFTRSTF: u1, - /// Independent watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit. - IWDGRSTF: u1, - /// Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. - WWDGRSTF: u1, - /// Low-power reset flag Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared. Cleared by writing to the RMVF bit. - LPWRRSTF: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_22: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved272: [24]u8, - /// RCC secure configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// HSI clock configuration and status bits security Set and reset by software. - HSISEC: packed union { - raw: u1, - value: SECURITY, - }, - /// HSE clock configuration bits, status bits and HSE_CSS security Set and reset by software. - HSESEC: packed union { - raw: u1, - value: SECURITY, - }, - /// MSI clock configuration and status bits security Set and reset by software. - MSISEC: packed union { - raw: u1, - value: SECURITY, - }, - /// LSI clock configuration and status bits security Set and reset by software. - LSISEC: packed union { - raw: u1, - value: SECURITY, - }, - /// LSE clock configuration and status bits security Set and reset by software. - LSESEC: packed union { - raw: u1, - value: SECURITY, - }, - /// SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security Set and reset by software. - SYSCLKSEC: packed union { - raw: u1, - value: SECURITY, - }, - /// AHBx/APBx prescaler configuration bits security Set and reset by software. - PRESCSEC: packed union { - raw: u1, - value: SECURITY, - }, - /// PLL1 clock configuration and status bits security Set and reset by software. - PLLSEC: packed union { - raw: u1, - value: SECURITY, - }, - reserved10: u2, - /// intermediate clock source selection security Set and reset by software. - ICLKSEC: packed union { - raw: u1, - value: SECURITY, - }, - /// HSI48 clock configuration and status bits security Set and reset by software. - HSI48SEC: packed union { - raw: u1, - value: SECURITY, - }, - /// Remove reset flag security Set and reset by software. - RMVFSEC: packed union { - raw: u1, - value: SECURITY, - }, - padding: u19, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_23: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// RCC privilege configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access. - SPRIV: u1, - /// RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure. - NSPRIV: u1, - padding: u30, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_24: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const spi_v5 = struct { - pub const COMM = enum(u2) { - /// Full duplex - FullDuplex = 0x0, - /// Simplex transmitter only - Transmitter = 0x1, - /// Simplex receiver only - Receiver = 0x2, - /// Half duplex - HalfDuplex = 0x3, - }; - - pub const CPHA = enum(u1) { - /// The first clock transition is the first data capture edge - FirstEdge = 0x0, - /// The second clock transition is the first data capture edge - SecondEdge = 0x1, - }; - - pub const CPOL = enum(u1) { - /// CK to 0 when idle - IdleLow = 0x0, - /// CK to 1 when idle - IdleHigh = 0x1, - }; - - pub const FTHLV = enum(u4) { - /// 1 frame - OneFrame = 0x0, - /// 2 frames - TwoFrames = 0x1, - /// 3 frames - ThreeFrames = 0x2, - /// 4 frames - FourFrames = 0x3, - /// 5 frames - FiveFrames = 0x4, - /// 6 frames - SixFrames = 0x5, - /// 7 frames - SevenFrames = 0x6, - /// 8 frames - EightFrames = 0x7, - /// 9 frames - NineFrames = 0x8, - /// 10 frames - TenFrames = 0x9, - /// 11 frames - ElevenFrames = 0xa, - /// 12 frames - TwelveFrames = 0xb, - /// 13 frames - ThirteenFrames = 0xc, - /// 14 frames - FourteenFrames = 0xd, - /// 15 frames - FifteenFrames = 0xe, - /// 16 frames - SixteenFrames = 0xf, - }; - - pub const HDDIR = enum(u1) { - /// Receiver in half duplex mode - Receiver = 0x0, - /// Transmitter in half duplex mode - Transmitter = 0x1, - }; - - pub const LSBFIRST = enum(u1) { - /// Data is transmitted/received with the MSB first - MSBFirst = 0x0, - /// Data is transmitted/received with the LSB first - LSBFirst = 0x1, - }; - - pub const MASTER = enum(u1) { - /// Slave configuration - Slave = 0x0, - /// Master configuration - Master = 0x1, - }; - - pub const MBR = enum(u3) { - /// f_spi_ker_ck / 2 - Div2 = 0x0, - /// f_spi_ker_ck / 4 - Div4 = 0x1, - /// f_spi_ker_ck / 8 - Div8 = 0x2, - /// f_spi_ker_ck / 16 - Div16 = 0x3, - /// f_spi_ker_ck / 32 - Div32 = 0x4, - /// f_spi_ker_ck / 64 - Div64 = 0x5, - /// f_spi_ker_ck / 128 - Div128 = 0x6, - /// f_spi_ker_ck / 256 - Div256 = 0x7, - }; - - pub const RCRCINI = enum(u1) { - /// All zeros RX CRC initialization pattern - AllZeros = 0x0, - /// All ones RX CRC initialization pattern - AllOnes = 0x1, - }; - - pub const RDIOM = enum(u1) { - /// RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) - PermanentlyActive = 0x0, - /// RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) - FromInput = 0x1, - }; - - pub const RDIOP = enum(u1) { - /// high level of the signal means the slave is ready for communication - ReadyHigh = 0x0, - /// low level of the signal means the slave is ready for communication - ReadyLow = 0x1, - }; - - pub const RXPLVL = enum(u2) { - /// Zero frames beyond packing ratio available - ZeroFrames = 0x0, - /// One frame beyond packing ratio available - OneFrame = 0x1, - /// Two frame beyond packing ratio available - TwoFrames = 0x2, - /// Three frame beyond packing ratio available - ThreeFrames = 0x3, - }; - - pub const RXWNE = enum(u1) { - /// Less than 32-bit data frame received - LessThan32 = 0x0, - /// At least 32-bit data frame received - AtLeast32 = 0x1, - }; - - pub const SP = enum(u3) { - /// Motorola SPI protocol - Motorola = 0x0, - /// TI SPI protocol - TI = 0x1, - _, - }; - - pub const SSIOP = enum(u1) { - /// Low level is active for SS signal - ActiveLow = 0x0, - /// High level is active for SS signal - ActiveHigh = 0x1, - }; - - pub const SSOM = enum(u1) { - /// SS is asserted until data transfer complete - Asserted = 0x0, - /// Data frames interleaved with SS not asserted during MIDI - NotAsserted = 0x1, - }; - - pub const TCRCINI = enum(u1) { - /// All zeros TX CRC initialization pattern - AllZeros = 0x0, - /// All ones TX CRC initialization pattern - AllOnes = 0x1, - }; - - pub const TRIGPOL = enum(u1) { - /// trigger is active on raising edge - RisingEdge = 0x0, - /// trigger is active on falling edge - FallingEdge = 0x1, - }; - - pub const UDRCFG = enum(u2) { - /// Slave sends a constant underrun pattern - Constant = 0x0, - /// Slave repeats last received data frame from master - RepeatReceived = 0x1, - /// Slave repeats last transmitted data frame - RepeatTransmitted = 0x2, - _, - }; - - /// Serial peripheral interface - pub const SPI = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Serial Peripheral Enable - SPE: u1, - reserved8: u7, - /// Master automatic SUSP in Receive mode - MASRX: u1, - /// Master transfer start - CSTART: u1, - /// Master SUSPend request - CSUSP: u1, - /// Rx/Tx direction at Half-duplex mode - HDDIR: packed union { - raw: u1, - value: HDDIR, - }, - /// Internal SS signal input level - SSI: u1, - /// Full size (33-bit or 17-bit) CRC polynomial is used - CRC33_17: u1, - /// CRC calculation initialization pattern control for receiver - RCRCINI: packed union { - raw: u1, - value: RCRCINI, - }, - /// CRC calculation initialization pattern control for transmitter - TCRCINI: packed union { - raw: u1, - value: TCRCINI, - }, - /// Locking the AF configuration of associated IOs - IOLOCK: u1, - padding: u15, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_25: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Number of data at current transfer - TSIZE: u16, - padding: u16, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_26: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// configuration register 1 - CFG1: mmio.Mmio(packed struct(u32) { - /// Number of bits in at single SPI data frame - DSIZE: u5, - /// threshold level - FTHLV: packed union { - raw: u4, - value: FTHLV, - }, - /// Behavior of slave transmitter at underrun condition - UDRCFG: packed union { - raw: u2, - value: UDRCFG, - }, - reserved14: u3, - /// Rx DMA stream enable - RXDMAEN: u1, - /// Tx DMA stream enable - TXDMAEN: u1, - /// Length of CRC frame to be transacted and compared - CRCSIZE: u5, - reserved22: u1, - /// Hardware CRC computation enable - CRCEN: u1, - reserved28: u5, - /// Master baud rate - MBR: packed union { - raw: u3, - value: MBR, - }, - /// bypass of the prescaler at master baud rate clock generator - BPASS: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_27: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// configuration register 2 - CFG2: mmio.Mmio(packed struct(u32) { - /// Master SS Idleness - MSSI: u4, - /// Master Inter-Data Idleness - MIDI: u4, - reserved13: u5, - /// RDY signal input/output management Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero. - RDIOM: packed union { - raw: u1, - value: RDIOM, - }, - /// RDY signal input/output polarity - RDIOP: packed union { - raw: u1, - value: RDIOP, - }, - /// Swap functionality of MISO and MOSI pins - IOSWP: u1, - reserved17: u1, - /// SPI Communication Mode - COMM: packed union { - raw: u2, - value: COMM, - }, - /// Serial Protocol - SP: packed union { - raw: u3, - value: SP, - }, - /// SPI Master - MASTER: packed union { - raw: u1, - value: MASTER, - }, - /// Data frame format - LSBFIRST: packed union { - raw: u1, - value: LSBFIRST, - }, - /// Clock phase - CPHA: packed union { - raw: u1, - value: CPHA, - }, - /// Clock polarity - CPOL: packed union { - raw: u1, - value: CPOL, - }, - /// Software management of SS signal input - SSM: u1, - reserved28: u1, - /// SS input/output polarity - SSIOP: packed union { - raw: u1, - value: SSIOP, - }, - /// SS output enable - SSOE: u1, - /// SS output management in master mode - SSOM: packed union { - raw: u1, - value: SSOM, - }, - /// Alternate function always control GPIOs - AFCNTR: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_28: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Interrupt Enable Register - IER: mmio.Mmio(packed struct(u32) { - /// RXP Interrupt Enable - RXPIE: u1, - /// TXP interrupt enable - TXPIE: u1, - /// DXP interrupt enabled - DXPIE: u1, - /// EOT, SUSP and TXC interrupt enable - EOTIE: u1, - /// TXTFIE interrupt enable - TXTFIE: u1, - /// UDR interrupt enable - UDRIE: u1, - /// OVR interrupt enable - OVRIE: u1, - /// CRC Interrupt enable - CRCEIE: u1, - /// TIFRE interrupt enable - TIFREIE: u1, - /// Mode Fault interrupt enable - MODFIE: u1, - padding: u22, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_29: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Status Register - SR: mmio.Mmio(packed struct(u32) { - /// Rx-Packet available - RXP: u1, - /// Tx-Packet space available - TXP: u1, - /// Duplex Packet - DXP: u1, - /// End Of Transfer - EOT: u1, - /// Transmission Transfer Filled - TXTF: u1, - /// Underrun at slave transmission mode - UDR: u1, - /// Overrun - OVR: u1, - /// CRC Error - CRCE: u1, - /// TI frame format error - TIFRE: u1, - /// Mode Fault - MODF: u1, - reserved11: u1, - /// SUSPend - SUSP: u1, - /// TxFIFO transmission complete - TXC: u1, - /// RxFIFO Packing LeVeL - RXPLVL: packed union { - raw: u2, - value: RXPLVL, - }, - /// RxFIFO Word Not Empty - RXWNE: packed union { - raw: u1, - value: RXWNE, - }, - /// Number of data frames remaining in current TSIZE session - CTSIZE: u16, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_30: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Interrupt/Status Flags Clear Register - IFCR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// End Of Transfer flag clear - EOTC: u1, - /// Transmission Transfer Filled flag clear - TXTFC: u1, - /// Underrun flag clear - UDRC: u1, - /// Overrun flag clear - OVRC: u1, - /// CRC Error flag clear - CRCEC: u1, - /// TI frame format error flag clear - TIFREC: u1, - /// Mode Fault flag clear - MODFC: u1, - reserved11: u1, - /// SUSPend flag clear - SUSPC: u1, - padding: u20, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_31: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - AUTOCR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// trigger selection (refer ). ... Note: these bits can be written only when SPE = 0. - TRIGSEL: u4, - /// trigger polarity Note: This bit can be written only when SPE = 0. - TRIGPOL: packed union { - raw: u1, - value: TRIGPOL, - }, - /// trigger of CSTART control enable Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled - TRIGEN: u1, - padding: u10, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_32: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Transmit Data Register - half-word sized - TXDR16: u32, - reserved48: [12]u8, - /// Receive Data Register - half-word sized - RXDR16: u32, - reserved64: [12]u8, - /// Polynomial Register - CRCPOLY: mmio.Mmio(packed struct(u32) { - /// CRC polynomial register - CRCPOLY: u32, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_33: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Transmitter CRC Register - TXCRC: mmio.Mmio(packed struct(u32) { - /// CRC register for transmitter - TXCRC: u32, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_34: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Receiver CRC Register - RXCRC: mmio.Mmio(packed struct(u32) { - /// CRC register for receiver - RXCRC: u32, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_35: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Underrun Data Register - UDRDR: mmio.Mmio(packed struct(u32) { - /// Data at slave underrun condition - UDRDR: u32, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_36: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const fmac_v1 = struct { - /// Filter math accelerator - pub const FMAC = extern struct { - /// X1 buffer configuration register - X1BUFCFG: mmio.Mmio(packed struct(u32) { - /// Base address of X1 buffer - X1_BASE: u8, - /// Allocated size of X1 buffer in 16-bit words - X1_BUF_SIZE: u8, - reserved24: u8, - /// Watermark for buffer full flag - FULL_WM: u2, - padding: u6, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_37: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// X2 buffer configuration register - X2BUFCFG: mmio.Mmio(packed struct(u32) { - /// Base address of X2 buffer - X2_BASE: u8, - /// Size of X2 buffer in 16-bit words - X2_BUF_SIZE: u8, - padding: u16, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_38: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Y buffer configuration register - YBUFCFG: mmio.Mmio(packed struct(u32) { - /// Base address of Y buffer - Y_BASE: u8, - /// Size of Y buffer in 16-bit words - Y_BUF_SIZE: u8, - reserved24: u8, - /// Watermark for buffer empty flag - EMPTY_WM: u2, - padding: u6, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_39: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Parameter register - PARAM: mmio.Mmio(packed struct(u32) { - /// Input parameter P - P: u8, - /// Input parameter Q - Q: u8, - /// Input parameter R - R: u8, - /// Function - FUNC: u7, - /// Enable execution - START: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_40: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Enable read interrupt - RIEN: u1, - /// Enable write interrupt - WIEN: u1, - /// Enable overflow error interrupts - OVFLIEN: u1, - /// Enable underflow error interrupts - UNFLIEN: u1, - /// Enable saturation error interrupts - SATIEN: u1, - reserved8: u3, - /// Enable DMA read channel requests - DMAREN: u1, - /// Enable DMA write channel requests - DMAWEN: u1, - reserved15: u5, - /// Enable clipping - CLIPEN: u1, - /// Reset FMAC unit - RESET: u1, - padding: u15, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_41: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Y buffer empty flag - YEMPTY: u1, - /// X1 buffer full flag - X1FULL: u1, - reserved8: u6, - /// Overflow error flag - OVFL: u1, - /// Underflow error flag - UNFL: u1, - /// Saturation error flag - SAT: u1, - padding: u21, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_42: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Write data register - WDATA: mmio.Mmio(packed struct(u32) { - /// Write data (write data are transferred to the address indicated by the write pointer) - WDATA: u16, - padding: u16, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_43: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Read data register - RDATA: mmio.Mmio(packed struct(u32) { - /// Read data (contents of the Y output buffer at the address indicated by the READ pointer) - RES: u16, - padding: u16, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_44: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const fmc_v3x1 = struct { - pub const ACCMOD = enum(u2) { - /// Access mode A - A = 0x0, - /// Access mode B - B = 0x1, - /// Access mode C - C = 0x2, - /// Access mode D - D = 0x3, - }; - - pub const CAS = enum(u2) { - /// 1 cycle - Clocks1 = 0x1, - /// 2 cycles - Clocks2 = 0x2, - /// 3 cycles - Clocks3 = 0x3, - _, - }; - - pub const CPSIZE = enum(u3) { - /// No burst split when crossing page boundary - NoBurstSplit = 0x0, - /// 128 bytes CRAM page size - Bytes128 = 0x1, - /// 256 bytes CRAM page size - Bytes256 = 0x2, - /// 512 bytes CRAM page size - Bytes512 = 0x3, - /// 1024 bytes CRAM page size - Bytes1024 = 0x4, - _, - }; - - pub const ECCPS = enum(u3) { - /// ECC page size 256 bytes - Bytes256 = 0x0, - /// ECC page size 512 bytes - Bytes512 = 0x1, - /// ECC page size 1024 bytes - Bytes1024 = 0x2, - /// ECC page size 2048 bytes - Bytes2048 = 0x3, - /// ECC page size 4096 bytes - Bytes4096 = 0x4, - /// ECC page size 8192 bytes - Bytes8192 = 0x5, - _, - }; - - pub const MODE = enum(u3) { - /// Normal Mode - Normal = 0x0, - /// Clock Configuration Enable - ClockConfigurationEnable = 0x1, - /// PALL (All Bank Precharge) command - PALL = 0x2, - /// Auto-refresh command - AutoRefreshCommand = 0x3, - /// Load Mode Resgier - LoadModeRegister = 0x4, - /// Self-refresh command - SelfRefreshCommand = 0x5, - /// Power-down command - PowerDownCommand = 0x6, - _, - }; - - pub const MODES = enum(u2) { - /// Normal Mode - Normal = 0x0, - /// Self-refresh mode - SelfRefresh = 0x1, - /// Power-down mode - PowerDown = 0x2, - _, - }; - - pub const MTYP = enum(u2) { - /// SRAM memory type - SRAM = 0x0, - /// PSRAM (CRAM) memory type - PSRAM = 0x1, - /// NOR Flash/OneNAND Flash - Flash = 0x2, - _, - }; - - pub const MWID = enum(u2) { - /// Memory data bus width 8 bits - Bits8 = 0x0, - /// Memory data bus width 16 bits - Bits16 = 0x1, - /// Memory data bus width 32 bits - Bits32 = 0x2, - _, - }; - - pub const NB = enum(u1) { - /// Two internal Banks - NB2 = 0x0, - /// Four internal Banks - NB4 = 0x1, - }; - - pub const NC = enum(u2) { - /// 8 bits - Bits8 = 0x0, - /// 9 bits - Bits9 = 0x1, - /// 10 bits - Bits10 = 0x2, - /// 11 bits - Bits11 = 0x3, - }; - - pub const NR = enum(u2) { - /// 11 bits - Bits11 = 0x0, - /// 12 bits - Bits12 = 0x1, - /// 13 bits - Bits13 = 0x2, - _, - }; - - pub const PWID = enum(u2) { - /// External memory device width 8 bits - Bits8 = 0x0, - /// External memory device width 16 bits - Bits16 = 0x1, - _, - }; - - pub const RPIPE = enum(u2) { - /// No clock cycle delay - NoDelay = 0x0, - /// One clock cycle delay - Clocks1 = 0x1, - /// Two clock cycles delay - Clocks2 = 0x2, - _, - }; - - pub const SDCLK = enum(u2) { - /// SDCLK clock disabled - Disabled = 0x0, - /// SDCLK period = 2 x HCLK period - Div2 = 0x2, - /// SDCLK period = 3 x HCLK period - Div3 = 0x3, - _, - }; - - pub const WAITCFG = enum(u1) { - /// NWAIT signal is active one data cycle before wait state - BeforeWaitState = 0x0, - /// NWAIT signal is active during wait state - DuringWaitState = 0x1, - }; - - pub const WAITPOL = enum(u1) { - /// NWAIT active low - ActiveLow = 0x0, - /// NWAIT active high - ActiveHigh = 0x1, - }; - - /// Flexible memory controller - pub const FMC = extern struct { - /// SRAM/NOR-Flash chip-select control register 1 - BCR1: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { - raw: u2, - value: MTYP, - }, - /// Memory data bus width - MWID: packed union { - raw: u2, - value: MWID, - }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { - raw: u1, - value: WAITPOL, - }, - reserved11: u1, - /// Wait timing configuration - WAITCFG: packed union { - raw: u1, - value: WAITCFG, - }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - /// CRAM page size - CPSIZE: packed union { - raw: u3, - value: CPSIZE, - }, - /// Write burst enable - CBURSTRW: u1, - /// Continuous clock enable - CCLKEN: u1, - /// Write FIFO disable - WFDIS: u1, - reserved24: u2, - /// FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register. - BMAP: u2, - reserved31: u5, - /// FMC controller enable - FMCEN: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_45: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// SRAM/NOR-Flash chip-select timing register 1-4 - BTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - /// Clock divide ratio (for FMC_CLK signal) - CLKDIV: u4, - /// Data latency for synchronous memory - DATLAT: u4, - /// Access mode - ACCMOD: packed union { - raw: u2, - value: ACCMOD, - }, - padding: u2, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_46: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// SRAM/NOR-Flash chip-select control register 2-4 - BCR: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { - raw: u2, - value: MTYP, - }, - /// Memory data bus width - MWID: packed union { - raw: u2, - value: MWID, - }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { - raw: u1, - value: WAITPOL, - }, - reserved11: u1, - /// Wait timing configuration - WAITCFG: packed union { - raw: u1, - value: WAITCFG, - }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - /// CRAM page size - CPSIZE: packed union { - raw: u3, - value: CPSIZE, - }, - /// Write burst enable - CBURSTRW: u1, - padding: u12, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_47: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved128: [116]u8, - /// PC Card/NAND Flash control register - PCR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Wait feature enable bit - PWAITEN: u1, - /// NAND Flash memory bank enable bit - PBKEN: u1, - reserved4: u1, - /// Data bus width - PWID: packed union { - raw: u2, - value: PWID, - }, - /// ECC computation logic enable bit - ECCEN: u1, - reserved9: u2, - /// CLE to RE delay - TCLR: u4, - /// ALE to RE delay - TAR: u4, - /// ECC page size - ECCPS: packed union { - raw: u3, - value: ECCPS, - }, - padding: u12, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_48: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// FIFO status and interrupt register - SR: mmio.Mmio(packed struct(u32) { - /// Interrupt rising edge status - IRS: u1, - /// Interrupt high-level status - ILS: u1, - /// Interrupt falling edge status - IFS: u1, - /// Interrupt rising edge detection enable bit - IREN: u1, - /// Interrupt high-level detection enable bit - ILEN: u1, - /// Interrupt falling edge detection enable bit - IFEN: u1, - /// FIFO empty status - FEMPT: u1, - padding: u25, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_49: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Common memory space timing register - PMEM: mmio.Mmio(packed struct(u32) { - /// Common memory x setup time - MEMSET: u8, - /// Common memory wait time - MEMWAIT: u8, - /// Common memory hold time - MEMHOLD: u8, - /// Common memory x data bus Hi-Z time - MEMHIZ: u8, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_50: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Attribute memory space timing register - PATT: mmio.Mmio(packed struct(u32) { - /// Attribute memory setup time - ATTSET: u8, - /// Attribute memory wait time - ATTWAIT: u8, - /// Attribute memory hold time - ATTHOLD: u8, - /// Attribute memory data bus Hi-Z time - ATTHIZ: u8, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_51: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved148: [4]u8, - /// ECC result register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC computation result value - ECC: u32, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_52: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved260: [108]u8, - /// SRAM/NOR-Flash write timing registers 1-4 - BWTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - reserved28: u8, - /// Access mode - ACCMOD: packed union { - raw: u2, - value: ACCMOD, - }, - padding: u2, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_53: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved320: [56]u8, - /// SDRAM Control Register 1-2 - SDCR: [2]mmio.Mmio(packed struct(u32) { - /// Number of column address bits - NC: packed union { - raw: u2, - value: NC, - }, - /// Number of row address bits - NR: packed union { - raw: u2, - value: NR, - }, - /// Memory data bus width - MWID: packed union { - raw: u2, - value: MWID, - }, - /// Number of internal banks - NB: packed union { - raw: u1, - value: NB, - }, - /// CAS latency - CAS: packed union { - raw: u2, - value: CAS, - }, - /// Write protection - WP: u1, - /// SDRAM clock configuration - SDCLK: packed union { - raw: u2, - value: SDCLK, - }, - /// Burst read - RBURST: u1, - /// Read pipe - RPIPE: packed union { - raw: u2, - value: RPIPE, - }, - padding: u17, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_54: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// SDRAM Timing register 1-2 - SDTR: [2]mmio.Mmio(packed struct(u32) { - /// Load Mode Register to Active - TMRD: u4, - /// Exit self-refresh delay - TXSR: u4, - /// Self refresh time - TRAS: u4, - /// Row cycle delay - TRC: u4, - /// Recovery delay - TWR: u4, - /// Row precharge delay - TRP: u4, - /// Row to column delay - TRCD: u4, - padding: u4, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_55: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// SDRAM Command Mode register - SDCMR: mmio.Mmio(packed struct(u32) { - /// Command mode - MODE: packed union { - raw: u3, - value: MODE, - }, - /// Command target bank 2 - CTB2: u1, - /// Command target bank 1 - CTB1: u1, - /// Number of Auto-refresh - NRFS: u4, - /// Mode Register definition - MRD: u13, - padding: u10, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_56: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// SDRAM Refresh Timer register - SDRTR: mmio.Mmio(packed struct(u32) { - /// Clear Refresh error flag - CRE: u1, - /// Refresh Timer Count - COUNT: u13, - /// RES Interrupt Enable - REIE: u1, - padding: u17, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_57: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// SDRAM Status register - SDSR: mmio.Mmio(packed struct(u32) { - /// Refresh error flag - RE: u1, - /// Status Mode for Bank 1 - MODES1: packed union { - raw: u2, - value: MODES, - }, - /// Status Mode for Bank 2 - MODES2: packed union { - raw: u2, - value: MODES, - }, - padding: u27, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_58: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const rtc_v2wb = struct { - pub const ALRMR_MSK = enum(u1) { - /// Alarm set if the date/day match - ToMatch = 0x0, - /// Date/day don’t care in Alarm comparison - NotMatch = 0x1, - }; - - pub const ALRMR_PM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, - }; - - pub const ALRMR_WDSEL = enum(u1) { - /// DU[3:0] represents the date units - DateUnits = 0x0, - /// DU[3:0] represents the week day. DT[1:0] is don’t care - WeekDay = 0x1, - }; - - pub const AMPM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, - }; - - pub const CALP = enum(u1) { - /// No RTCCLK pulses are added - NoChange = 0x0, - /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - IncreaseFreq = 0x1, - }; - - pub const CALW16 = enum(u1) { - /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 - Sixteen_Second = 0x1, - _, - }; - - pub const CALW8 = enum(u1) { - /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected - Eight_Second = 0x1, - _, - }; - - pub const COSEL = enum(u1) { - /// Calibration output is 512 Hz (with default prescaler setting) - CalFreq_512Hz = 0x0, - /// Calibration output is 1 Hz (with default prescaler setting) - CalFreq_1Hz = 0x1, - }; - - pub const FMT = enum(u1) { - /// 24 hour/day format - Twenty_Four_Hour = 0x0, - /// AM/PM hour format - AM_PM = 0x1, - }; - - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Alarm B output enabled - AlarmB = 0x2, - /// Wakeup output enabled - Wakeup = 0x3, - }; - - pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - Low = 0x1, - }; - - pub const RECALPF = enum(u1) { - /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 - Pending = 0x1, - _, - }; - - pub const TAMPFLT = enum(u2) { - /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - Immediate = 0x0, - /// Tamper event is activated after 2 consecutive samples at the active level - Samples2 = 0x1, - /// Tamper event is activated after 4 consecutive samples at the active level - Samples4 = 0x2, - /// Tamper event is activated after 8 consecutive samples at the active level - Samples8 = 0x3, - }; - - pub const TAMPFREQ = enum(u3) { - /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - Div32768 = 0x0, - /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - Div16384 = 0x1, - /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - Div8192 = 0x2, - /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - Div4096 = 0x3, - /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - Div2048 = 0x4, - /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - Div1024 = 0x5, - /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - Div512 = 0x6, - /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - Div256 = 0x7, - }; - - pub const TAMPPRCH = enum(u2) { - /// 1 RTCCLK cycle - Cycles1 = 0x0, - /// 2 RTCCLK cycles - Cycles2 = 0x1, - /// 4 RTCCLK cycles - Cycles4 = 0x2, - /// 8 RTCCLK cycles - Cycles8 = 0x3, - }; - - pub const TAMPPUDIS = enum(u1) { - /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - Enabled = 0x0, - /// Disable precharge of RTC_TAMPx pins - Disabled = 0x1, - }; - - pub const TAMPTRG = enum(u1) { - /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. - RisingEdge = 0x0, - /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event - FallingEdge = 0x1, - }; - - pub const TSEDGE = enum(u1) { - /// RTC_TS input rising edge generates a time-stamp event - RisingEdge = 0x0, - /// RTC_TS input falling edge generates a time-stamp event - FallingEdge = 0x1, - }; - - pub const WUCKSEL = enum(u3) { - /// RTC/16 clock is selected - Div16 = 0x0, - /// RTC/8 clock is selected - Div8 = 0x1, - /// RTC/4 clock is selected - Div4 = 0x2, - /// RTC/2 clock is selected - Div2 = 0x3, - /// ck_spre (usually 1 Hz) clock is selected - ClockSpare = 0x4, - /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - ClockSpareWithOffset = 0x6, - _, - }; - - /// Real-time clock - pub const RTC = extern struct { - /// Time register - TR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_59: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Date register - DR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding: u8, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_60: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Wakeup clock selection - WUCKSEL: packed union { - raw: u3, - value: WUCKSEL, - }, - /// Timestamp event active edge - TSEDGE: packed union { - raw: u1, - value: TSEDGE, - }, - /// Reference clock detection enable (50 or 60 Hz) - REFCKON: u1, - /// Bypass the shadow registers - BYPSHAD: u1, - /// Hour format - FMT: packed union { - raw: u1, - value: FMT, - }, - reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, - /// Wakeup timer enable - WUTE: u1, - /// Timestamp enable - TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, - /// Wakeup timer interrupt enable - WUTIE: u1, - /// Timestamp interrupt enable - TSIE: u1, - /// Add 1 hour (summer time change) - ADD1H: u1, - /// Subtract 1 hour (winter time change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output selection - COSEL: packed union { - raw: u1, - value: COSEL, - }, - /// Output polarity - POL: packed union { - raw: u1, - value: POL, - }, - /// Output selection - OSEL: packed union { - raw: u2, - value: OSEL, - }, - /// Calibration output enable - COE: u1, - /// Timestamp on internal event enable - ITSE: u1, - padding: u7, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_61: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Initialization and status register - ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, - /// Wakeup timer write enabled - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Enter Initialization mode - INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, - /// Wakeup timer flag - WUTF: u1, - /// Timestamp flag - TSF: u1, - /// Timestamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, - /// Recalibration pending flag - RECALPF: packed union { - raw: u1, - value: RECALPF, - }, - /// Internal time-stamp flag - ITSF: u1, - padding: u14, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_62: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, - padding: u9, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_63: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, - padding: u16, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_64: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved28: [4]u8, - /// Alarm register - ALRMR: [2]mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm seconds mask - MSK1: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm minutes mask - MSK2: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: ALRMR_PM, - }, - /// Alarm hours mask - MSK3: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { - raw: u1, - value: ALRMR_WDSEL, - }, - /// Alarm date mask - MSK4: packed union { - raw: u1, - value: ALRMR_MSK, - }, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_65: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: u8, - padding: u24, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_66: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Sub second register - SSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_67: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Shift control register - SHIFTR: mmio.Mmio(packed struct(u32) { - /// Subtract a fraction of a second - SUBFS: u15, - reserved31: u16, - /// Add one second - ADD1S: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_68: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_69: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding: u16, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_70: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Timestamp sub second register - TSSSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_71: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Calibration register - CALR: mmio.Mmio(packed struct(u32) { - /// Calibration minus - CALM: u9, - reserved13: u4, - /// Use a 16-second calibration cycle period - CALW16: packed union { - raw: u1, - value: CALW16, - }, - /// Use an 8-second calibration cycle period - CALW8: packed union { - raw: u1, - value: CALW8, - }, - /// Increase frequency of RTC by 488.5 ppm - CALP: packed union { - raw: u1, - value: CALP, - }, - padding: u16, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_72: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Tamper configuration register - TAMPCR: mmio.Mmio(packed struct(u32) { - /// Tamper detection enable - TAMPE: u1, - /// Active level for tamper - TAMPTRG: packed union { - raw: u1, - value: TAMPTRG, - }, - /// Tamper interrupt enable - TAMPIE: u1, - reserved7: u4, - /// Activate timestamp on tamper detection event - TAMPTS: u1, - /// Tamper sampling frequency - TAMPFREQ: packed union { - raw: u3, - value: TAMPFREQ, - }, - /// Tamper filter count - TAMPFLT: packed union { - raw: u2, - value: TAMPFLT, - }, - /// Tamper precharge duration - TAMPPRCH: packed union { - raw: u2, - value: TAMPPRCH, - }, - /// Tamper pull-up disable - TAMPPUDIS: packed union { - raw: u1, - value: TAMPPUDIS, - }, - /// Tamper interrupt enable - TAMPXIE: u1, - /// Tamper no erase - TAMPXNOERASE: u1, - /// Tamper mask flag - TAMPXMF: u1, - padding: u13, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_73: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Alarm sub second register - ALRMSSR: [2]mmio.Mmio(packed struct(u32) { - /// Sub seconds value - SS: u15, - reserved24: u9, - /// Mask the most-significant bits starting at this bit - MASKSS: u4, - padding: u4, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_74: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Option register - OR: mmio.Mmio(packed struct(u32) { - /// RTC_ALARM on PC13 output type - RTC_ALARM_TYPE: u1, - /// RTC_OUT remap - RTC_OUT_RMP: u1, - padding: u30, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_75: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// Backup register - BKPR: [20]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_76: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const rcc_f7 = struct { - pub const ADFSDMSEL = enum(u1) { - /// SAI1 clock selected as DFSDM1 Audio clock source - SAI1 = 0x0, - /// SAI2 clock selected as DFSDM1 Audio clock source - SAI2 = 0x1, - }; - - pub const CECSEL = enum(u1) { - /// LSE clock is selected as HDMI-CEC clock - LSE = 0x0, - /// HSI divided by 488 clock is selected as HDMI-CEC clock - HSI_Div488 = 0x1, - }; - - pub const CLK48SEL = enum(u1) { - /// 48MHz clock from PLL is selected - PLL1_Q = 0x0, - /// 48MHz clock from PLLSAI is selected - PLLSAI1_P = 0x1, - }; - - pub const DFSDMSEL = enum(u1) { - /// APB2 clock (PCLK2) selected as DFSDM1 Kernel clock source - PCLK2 = 0x0, - /// System clock (SYSCLK) clock selected as DFSDM1 Kernel clock source - SYS = 0x1, - }; - - pub const DSISEL = enum(u1) { - /// DSI-PHY used as DSI byte lane clock source (usual case) - DSI_PHY = 0x0, - /// PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode) - PLL1_R = 0x1, - }; - - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, - _, - }; - - pub const I2CSEL = enum(u2) { - /// APB clock selected as I2C clock - PCLK1 = 0x0, - /// System clock selected as I2C clock - SYS = 0x1, - /// HSI clock selected as I2C clock - HSI = 0x2, - _, - }; - - pub const ISSRC = enum(u1) { - /// PLLI2S clock used as I2S clock source - PLLI2S = 0x0, - /// External clock mapped on the I2S_CKIN pin used as I2S clock source - CKIN = 0x1, - }; - - pub const LPTIMSEL = enum(u2) { - /// APB1 clock (PCLK1) selected as LPTILM1 clock - PCLK1 = 0x0, - /// LSI clock is selected as LPTILM1 clock - LSI = 0x1, - /// HSI clock is selected as LPTILM1 clock - HSI = 0x2, - /// LSE clock is selected as LPTILM1 clock - LSE = 0x3, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium high driving capability - MediumHigh = 0x1, - /// Medium low driving capability - MediumLow = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCO1SEL = enum(u2) { - /// HSI clock selected - HSI = 0x0, - /// LSE oscillator selected - LSE = 0x1, - /// HSE oscillator clock selected - HSE = 0x2, - /// PLL clock selected - PLL = 0x3, - }; - - pub const MCO2SEL = enum(u2) { - /// System clock (SYSCLK) selected - SYS = 0x0, - /// PLLI2S clock selected - PLLI2S = 0x1, - /// HSE oscillator clock selected - HSE = 0x2, - /// PLL clock selected - PLL = 0x3, - }; - - pub const MCOPRE = enum(u3) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x4, - /// Division by 3 - Div3 = 0x5, - /// Division by 4 - Div4 = 0x6, - /// Division by 5 - Div5 = 0x7, - _, - }; - - pub const PLLI2SDIVQ = enum(u5) { - /// PLLI2SDIVQ = /1 - Div1 = 0x0, - /// PLLI2SDIVQ = /2 - Div2 = 0x1, - /// PLLI2SDIVQ = /3 - Div3 = 0x2, - /// PLLI2SDIVQ = /4 - Div4 = 0x3, - /// PLLI2SDIVQ = /5 - Div5 = 0x4, - /// PLLI2SDIVQ = /6 - Div6 = 0x5, - /// PLLI2SDIVQ = /7 - Div7 = 0x6, - /// PLLI2SDIVQ = /8 - Div8 = 0x7, - /// PLLI2SDIVQ = /9 - Div9 = 0x8, - /// PLLI2SDIVQ = /10 - Div10 = 0x9, - /// PLLI2SDIVQ = /11 - Div11 = 0xa, - /// PLLI2SDIVQ = /12 - Div12 = 0xb, - /// PLLI2SDIVQ = /13 - Div13 = 0xc, - /// PLLI2SDIVQ = /14 - Div14 = 0xd, - /// PLLI2SDIVQ = /15 - Div15 = 0xe, - /// PLLI2SDIVQ = /16 - Div16 = 0xf, - /// PLLI2SDIVQ = /17 - Div17 = 0x10, - /// PLLI2SDIVQ = /18 - Div18 = 0x11, - /// PLLI2SDIVQ = /19 - Div19 = 0x12, - /// PLLI2SDIVQ = /20 - Div20 = 0x13, - /// PLLI2SDIVQ = /21 - Div21 = 0x14, - /// PLLI2SDIVQ = /22 - Div22 = 0x15, - /// PLLI2SDIVQ = /23 - Div23 = 0x16, - /// PLLI2SDIVQ = /24 - Div24 = 0x17, - /// PLLI2SDIVQ = /25 - Div25 = 0x18, - /// PLLI2SDIVQ = /26 - Div26 = 0x19, - /// PLLI2SDIVQ = /27 - Div27 = 0x1a, - /// PLLI2SDIVQ = /28 - Div28 = 0x1b, - /// PLLI2SDIVQ = /29 - Div29 = 0x1c, - /// PLLI2SDIVQ = /30 - Div30 = 0x1d, - /// PLLI2SDIVQ = /31 - Div31 = 0x1e, - /// PLLI2SDIVQ = /32 - Div32 = 0x1f, - }; - - pub const PLLM = enum(u6) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - Div16 = 0x10, - Div17 = 0x11, - Div18 = 0x12, - Div19 = 0x13, - Div20 = 0x14, - Div21 = 0x15, - Div22 = 0x16, - Div23 = 0x17, - Div24 = 0x18, - Div25 = 0x19, - Div26 = 0x1a, - Div27 = 0x1b, - Div28 = 0x1c, - Div29 = 0x1d, - Div30 = 0x1e, - Div31 = 0x1f, - Div32 = 0x20, - Div33 = 0x21, - Div34 = 0x22, - Div35 = 0x23, - Div36 = 0x24, - Div37 = 0x25, - Div38 = 0x26, - Div39 = 0x27, - Div40 = 0x28, - Div41 = 0x29, - Div42 = 0x2a, - Div43 = 0x2b, - Div44 = 0x2c, - Div45 = 0x2d, - Div46 = 0x2e, - Div47 = 0x2f, - Div48 = 0x30, - Div49 = 0x31, - Div50 = 0x32, - Div51 = 0x33, - Div52 = 0x34, - Div53 = 0x35, - Div54 = 0x36, - Div55 = 0x37, - Div56 = 0x38, - Div57 = 0x39, - Div58 = 0x3a, - Div59 = 0x3b, - Div60 = 0x3c, - Div61 = 0x3d, - Div62 = 0x3e, - Div63 = 0x3f, - _, - }; - - pub const PLLN = enum(u9) { - Mul50 = 0x32, - Mul51 = 0x33, - Mul52 = 0x34, - Mul53 = 0x35, - Mul54 = 0x36, - Mul55 = 0x37, - Mul56 = 0x38, - Mul57 = 0x39, - Mul58 = 0x3a, - Mul59 = 0x3b, - Mul60 = 0x3c, - Mul61 = 0x3d, - Mul62 = 0x3e, - Mul63 = 0x3f, - Mul64 = 0x40, - Mul65 = 0x41, - Mul66 = 0x42, - Mul67 = 0x43, - Mul68 = 0x44, - Mul69 = 0x45, - Mul70 = 0x46, - Mul71 = 0x47, - Mul72 = 0x48, - Mul73 = 0x49, - Mul74 = 0x4a, - Mul75 = 0x4b, - Mul76 = 0x4c, - Mul77 = 0x4d, - Mul78 = 0x4e, - Mul79 = 0x4f, - Mul80 = 0x50, - Mul81 = 0x51, - Mul82 = 0x52, - Mul83 = 0x53, - Mul84 = 0x54, - Mul85 = 0x55, - Mul86 = 0x56, - Mul87 = 0x57, - Mul88 = 0x58, - Mul89 = 0x59, - Mul90 = 0x5a, - Mul91 = 0x5b, - Mul92 = 0x5c, - Mul93 = 0x5d, - Mul94 = 0x5e, - Mul95 = 0x5f, - Mul96 = 0x60, - Mul97 = 0x61, - Mul98 = 0x62, - Mul99 = 0x63, - Mul100 = 0x64, - Mul101 = 0x65, - Mul102 = 0x66, - Mul103 = 0x67, - Mul104 = 0x68, - Mul105 = 0x69, - Mul106 = 0x6a, - Mul107 = 0x6b, - Mul108 = 0x6c, - Mul109 = 0x6d, - Mul110 = 0x6e, - Mul111 = 0x6f, - Mul112 = 0x70, - Mul113 = 0x71, - Mul114 = 0x72, - Mul115 = 0x73, - Mul116 = 0x74, - Mul117 = 0x75, - Mul118 = 0x76, - Mul119 = 0x77, - Mul120 = 0x78, - Mul121 = 0x79, - Mul122 = 0x7a, - Mul123 = 0x7b, - Mul124 = 0x7c, - Mul125 = 0x7d, - Mul126 = 0x7e, - Mul127 = 0x7f, - Mul128 = 0x80, - Mul129 = 0x81, - Mul130 = 0x82, - Mul131 = 0x83, - Mul132 = 0x84, - Mul133 = 0x85, - Mul134 = 0x86, - Mul135 = 0x87, - Mul136 = 0x88, - Mul137 = 0x89, - Mul138 = 0x8a, - Mul139 = 0x8b, - Mul140 = 0x8c, - Mul141 = 0x8d, - Mul142 = 0x8e, - Mul143 = 0x8f, - Mul144 = 0x90, - Mul145 = 0x91, - Mul146 = 0x92, - Mul147 = 0x93, - Mul148 = 0x94, - Mul149 = 0x95, - Mul150 = 0x96, - Mul151 = 0x97, - Mul152 = 0x98, - Mul153 = 0x99, - Mul154 = 0x9a, - Mul155 = 0x9b, - Mul156 = 0x9c, - Mul157 = 0x9d, - Mul158 = 0x9e, - Mul159 = 0x9f, - Mul160 = 0xa0, - Mul161 = 0xa1, - Mul162 = 0xa2, - Mul163 = 0xa3, - Mul164 = 0xa4, - Mul165 = 0xa5, - Mul166 = 0xa6, - Mul167 = 0xa7, - Mul168 = 0xa8, - Mul169 = 0xa9, - Mul170 = 0xaa, - Mul171 = 0xab, - Mul172 = 0xac, - Mul173 = 0xad, - Mul174 = 0xae, - Mul175 = 0xaf, - Mul176 = 0xb0, - Mul177 = 0xb1, - Mul178 = 0xb2, - Mul179 = 0xb3, - Mul180 = 0xb4, - Mul181 = 0xb5, - Mul182 = 0xb6, - Mul183 = 0xb7, - Mul184 = 0xb8, - Mul185 = 0xb9, - Mul186 = 0xba, - Mul187 = 0xbb, - Mul188 = 0xbc, - Mul189 = 0xbd, - Mul190 = 0xbe, - Mul191 = 0xbf, - Mul192 = 0xc0, - Mul193 = 0xc1, - Mul194 = 0xc2, - Mul195 = 0xc3, - Mul196 = 0xc4, - Mul197 = 0xc5, - Mul198 = 0xc6, - Mul199 = 0xc7, - Mul200 = 0xc8, - Mul201 = 0xc9, - Mul202 = 0xca, - Mul203 = 0xcb, - Mul204 = 0xcc, - Mul205 = 0xcd, - Mul206 = 0xce, - Mul207 = 0xcf, - Mul208 = 0xd0, - Mul209 = 0xd1, - Mul210 = 0xd2, - Mul211 = 0xd3, - Mul212 = 0xd4, - Mul213 = 0xd5, - Mul214 = 0xd6, - Mul215 = 0xd7, - Mul216 = 0xd8, - Mul217 = 0xd9, - Mul218 = 0xda, - Mul219 = 0xdb, - Mul220 = 0xdc, - Mul221 = 0xdd, - Mul222 = 0xde, - Mul223 = 0xdf, - Mul224 = 0xe0, - Mul225 = 0xe1, - Mul226 = 0xe2, - Mul227 = 0xe3, - Mul228 = 0xe4, - Mul229 = 0xe5, - Mul230 = 0xe6, - Mul231 = 0xe7, - Mul232 = 0xe8, - Mul233 = 0xe9, - Mul234 = 0xea, - Mul235 = 0xeb, - Mul236 = 0xec, - Mul237 = 0xed, - Mul238 = 0xee, - Mul239 = 0xef, - Mul240 = 0xf0, - Mul241 = 0xf1, - Mul242 = 0xf2, - Mul243 = 0xf3, - Mul244 = 0xf4, - Mul245 = 0xf5, - Mul246 = 0xf6, - Mul247 = 0xf7, - Mul248 = 0xf8, - Mul249 = 0xf9, - Mul250 = 0xfa, - Mul251 = 0xfb, - Mul252 = 0xfc, - Mul253 = 0xfd, - Mul254 = 0xfe, - Mul255 = 0xff, - Mul256 = 0x100, - Mul257 = 0x101, - Mul258 = 0x102, - Mul259 = 0x103, - Mul260 = 0x104, - Mul261 = 0x105, - Mul262 = 0x106, - Mul263 = 0x107, - Mul264 = 0x108, - Mul265 = 0x109, - Mul266 = 0x10a, - Mul267 = 0x10b, - Mul268 = 0x10c, - Mul269 = 0x10d, - Mul270 = 0x10e, - Mul271 = 0x10f, - Mul272 = 0x110, - Mul273 = 0x111, - Mul274 = 0x112, - Mul275 = 0x113, - Mul276 = 0x114, - Mul277 = 0x115, - Mul278 = 0x116, - Mul279 = 0x117, - Mul280 = 0x118, - Mul281 = 0x119, - Mul282 = 0x11a, - Mul283 = 0x11b, - Mul284 = 0x11c, - Mul285 = 0x11d, - Mul286 = 0x11e, - Mul287 = 0x11f, - Mul288 = 0x120, - Mul289 = 0x121, - Mul290 = 0x122, - Mul291 = 0x123, - Mul292 = 0x124, - Mul293 = 0x125, - Mul294 = 0x126, - Mul295 = 0x127, - Mul296 = 0x128, - Mul297 = 0x129, - Mul298 = 0x12a, - Mul299 = 0x12b, - Mul300 = 0x12c, - Mul301 = 0x12d, - Mul302 = 0x12e, - Mul303 = 0x12f, - Mul304 = 0x130, - Mul305 = 0x131, - Mul306 = 0x132, - Mul307 = 0x133, - Mul308 = 0x134, - Mul309 = 0x135, - Mul310 = 0x136, - Mul311 = 0x137, - Mul312 = 0x138, - Mul313 = 0x139, - Mul314 = 0x13a, - Mul315 = 0x13b, - Mul316 = 0x13c, - Mul317 = 0x13d, - Mul318 = 0x13e, - Mul319 = 0x13f, - Mul320 = 0x140, - Mul321 = 0x141, - Mul322 = 0x142, - Mul323 = 0x143, - Mul324 = 0x144, - Mul325 = 0x145, - Mul326 = 0x146, - Mul327 = 0x147, - Mul328 = 0x148, - Mul329 = 0x149, - Mul330 = 0x14a, - Mul331 = 0x14b, - Mul332 = 0x14c, - Mul333 = 0x14d, - Mul334 = 0x14e, - Mul335 = 0x14f, - Mul336 = 0x150, - Mul337 = 0x151, - Mul338 = 0x152, - Mul339 = 0x153, - Mul340 = 0x154, - Mul341 = 0x155, - Mul342 = 0x156, - Mul343 = 0x157, - Mul344 = 0x158, - Mul345 = 0x159, - Mul346 = 0x15a, - Mul347 = 0x15b, - Mul348 = 0x15c, - Mul349 = 0x15d, - Mul350 = 0x15e, - Mul351 = 0x15f, - Mul352 = 0x160, - Mul353 = 0x161, - Mul354 = 0x162, - Mul355 = 0x163, - Mul356 = 0x164, - Mul357 = 0x165, - Mul358 = 0x166, - Mul359 = 0x167, - Mul360 = 0x168, - Mul361 = 0x169, - Mul362 = 0x16a, - Mul363 = 0x16b, - Mul364 = 0x16c, - Mul365 = 0x16d, - Mul366 = 0x16e, - Mul367 = 0x16f, - Mul368 = 0x170, - Mul369 = 0x171, - Mul370 = 0x172, - Mul371 = 0x173, - Mul372 = 0x174, - Mul373 = 0x175, - Mul374 = 0x176, - Mul375 = 0x177, - Mul376 = 0x178, - Mul377 = 0x179, - Mul378 = 0x17a, - Mul379 = 0x17b, - Mul380 = 0x17c, - Mul381 = 0x17d, - Mul382 = 0x17e, - Mul383 = 0x17f, - Mul384 = 0x180, - Mul385 = 0x181, - Mul386 = 0x182, - Mul387 = 0x183, - Mul388 = 0x184, - Mul389 = 0x185, - Mul390 = 0x186, - Mul391 = 0x187, - Mul392 = 0x188, - Mul393 = 0x189, - Mul394 = 0x18a, - Mul395 = 0x18b, - Mul396 = 0x18c, - Mul397 = 0x18d, - Mul398 = 0x18e, - Mul399 = 0x18f, - Mul400 = 0x190, - Mul401 = 0x191, - Mul402 = 0x192, - Mul403 = 0x193, - Mul404 = 0x194, - Mul405 = 0x195, - Mul406 = 0x196, - Mul407 = 0x197, - Mul408 = 0x198, - Mul409 = 0x199, - Mul410 = 0x19a, - Mul411 = 0x19b, - Mul412 = 0x19c, - Mul413 = 0x19d, - Mul414 = 0x19e, - Mul415 = 0x19f, - Mul416 = 0x1a0, - Mul417 = 0x1a1, - Mul418 = 0x1a2, - Mul419 = 0x1a3, - Mul420 = 0x1a4, - Mul421 = 0x1a5, - Mul422 = 0x1a6, - Mul423 = 0x1a7, - Mul424 = 0x1a8, - Mul425 = 0x1a9, - Mul426 = 0x1aa, - Mul427 = 0x1ab, - Mul428 = 0x1ac, - Mul429 = 0x1ad, - Mul430 = 0x1ae, - Mul431 = 0x1af, - Mul432 = 0x1b0, - _, - }; - - pub const PLLP = enum(u2) { - /// PLLP=2 - Div2 = 0x0, - /// PLLP=4 - Div4 = 0x1, - /// PLLP=6 - Div6 = 0x2, - /// PLLP=8 - Div8 = 0x3, - }; - - pub const PLLQ = enum(u4) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - _, - }; - - pub const PLLR = enum(u3) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - _, - }; - - pub const PLLSAIDIVQ = enum(u5) { - /// PLLSAIDIVQ = /1 - Div1 = 0x0, - /// PLLSAIDIVQ = /2 - Div2 = 0x1, - /// PLLSAIDIVQ = /3 - Div3 = 0x2, - /// PLLSAIDIVQ = /4 - Div4 = 0x3, - /// PLLSAIDIVQ = /5 - Div5 = 0x4, - /// PLLSAIDIVQ = /6 - Div6 = 0x5, - /// PLLSAIDIVQ = /7 - Div7 = 0x6, - /// PLLSAIDIVQ = /8 - Div8 = 0x7, - /// PLLSAIDIVQ = /9 - Div9 = 0x8, - /// PLLSAIDIVQ = /10 - Div10 = 0x9, - /// PLLSAIDIVQ = /11 - Div11 = 0xa, - /// PLLSAIDIVQ = /12 - Div12 = 0xb, - /// PLLSAIDIVQ = /13 - Div13 = 0xc, - /// PLLSAIDIVQ = /14 - Div14 = 0xd, - /// PLLSAIDIVQ = /15 - Div15 = 0xe, - /// PLLSAIDIVQ = /16 - Div16 = 0xf, - /// PLLSAIDIVQ = /17 - Div17 = 0x10, - /// PLLSAIDIVQ = /18 - Div18 = 0x11, - /// PLLSAIDIVQ = /19 - Div19 = 0x12, - /// PLLSAIDIVQ = /20 - Div20 = 0x13, - /// PLLSAIDIVQ = /21 - Div21 = 0x14, - /// PLLSAIDIVQ = /22 - Div22 = 0x15, - /// PLLSAIDIVQ = /23 - Div23 = 0x16, - /// PLLSAIDIVQ = /24 - Div24 = 0x17, - /// PLLSAIDIVQ = /25 - Div25 = 0x18, - /// PLLSAIDIVQ = /26 - Div26 = 0x19, - /// PLLSAIDIVQ = /27 - Div27 = 0x1a, - /// PLLSAIDIVQ = /28 - Div28 = 0x1b, - /// PLLSAIDIVQ = /29 - Div29 = 0x1c, - /// PLLSAIDIVQ = /30 - Div30 = 0x1d, - /// PLLSAIDIVQ = /31 - Div31 = 0x1e, - /// PLLSAIDIVQ = /32 - Div32 = 0x1f, - }; - - pub const PLLSAIDIVR = enum(u2) { - /// PLLSAIDIVR = /2 - Div2 = 0x0, - /// PLLSAIDIVR = /4 - Div4 = 0x1, - /// PLLSAIDIVR = /8 - Div8 = 0x2, - /// PLLSAIDIVR = /16 - Div16 = 0x3, - }; - - pub const PLLSRC = enum(u1) { - /// HSI clock selected as PLL and PLLI2S clock entry - HSI = 0x0, - /// HSE oscillator clock selected as PLL and PLLI2S clock entry - HSE = 0x1, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, - }; - - pub const SAISEL = enum(u2) { - /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - PLLSAI1_Q = 0x0, - /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - PLLI2S1_Q = 0x1, - /// SAI2 clock frequency = Alternate function input frequency - AFIF = 0x2, - /// SAI2 clock frequency = HSI or HSE - HSI_HSE = 0x3, - }; - - pub const SDMMCSEL = enum(u1) { - /// 48 MHz clock is selected as SD clock - CLK48 = 0x0, - /// System clock is selected as SD clock - SYS = 0x1, - }; - - pub const SPREADSEL = enum(u1) { - /// Center spread - Center = 0x0, - /// Down spread - Down = 0x1, - }; - - pub const SW = enum(u2) { - /// HSI oscillator used as system clock - HSI = 0x0, - /// HSE oscillator used as system clock - HSE = 0x1, - /// PLL used as system clock - PLL1_P = 0x2, - _, - }; - - pub const TIMPRE = enum(u1) { - /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx - Mul2 = 0x0, - /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx - Mul4 = 0x1, - }; - - pub const USART1SEL = enum(u2) { - /// APB2 clock (PCLK2) is selected as USART clock - PCLK2 = 0x0, - /// System clock is selected as USART clock - SYS = 0x1, - /// HSI clock is selected as USART clock - HSI = 0x2, - /// LSE clock is selected as USART clock - LSE = 0x3, - }; - - pub const USART2SEL = enum(u2) { - /// APB1 clock (PCLK1) is selected as USART clock - PCLK1 = 0x0, - /// System clock is selected as USART clock - SYS = 0x1, - /// HSI clock is selected as USART clock - HSI = 0x2, - /// LSE clock is selected as USART clock - LSE = 0x3, - }; - - /// Reset and clock control - pub const RCC = extern struct { - /// clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal high-speed clock enable - HSION: u1, - /// Internal high-speed clock ready flag - HSIRDY: u1, - reserved3: u1, - /// Internal high-speed clock trimming - HSITRIM: u5, - /// Internal high-speed clock calibration - HSICAL: u8, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE clock bypass - HSEBYP: u1, - /// Clock security system enable - CSSON: u1, - reserved24: u4, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - /// PLLI2S enable - PLLI2SON: u1, - /// PLLI2S clock ready flag - PLLI2SRDY: u1, - /// PLLSAI enable - PLLSAION: u1, - /// PLLSAI clock ready flag - PLLSAIRDY: u1, - padding: u2, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_77: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// PLL configuration register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// Division factor for the PLL and audio PLL (PLLI2S) input clock - PLLM: packed union { - raw: u6, - value: PLLM, - }, - /// PLL multiplication factor for VCO - PLLN: packed union { - raw: u9, - value: PLLN, - }, - reserved16: u1, - /// PLL division factor for main system clock - PLLP: packed union { - raw: u2, - value: PLLP, - }, - reserved22: u4, - /// PLL and audio PLL (PLLI2S, PLLSAI) entry clock source - PLLSRC: packed union { - raw: u1, - value: PLLSRC, - }, - reserved24: u1, - /// PLL division factor for USB OTG FS, SDIO and random number generator clocks - PLLQ: packed union { - raw: u4, - value: PLLQ, - }, - /// PLL division factor for DSI clock - PLLR: packed union { - raw: u3, - value: PLLR, - }, - padding: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_78: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u2, - value: SW, - }, - /// System clock switch status - SWS: packed union { - raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, - }, - reserved10: u2, - /// APB Low speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, - }, - /// APB high-speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, - }, - /// HSE division factor for RTC clock - RTCPRE: u5, - /// Microcontroller clock output 1 - MCO1SEL: packed union { - raw: u2, - value: MCO1SEL, - }, - /// I2S clock selection - I2SSRC: packed union { - raw: u1, - value: ISSRC, - }, - /// MCO1 prescaler - MCO1PRE: packed union { - raw: u3, - value: MCOPRE, - }, - /// MCO2 prescaler - MCO2PRE: packed union { - raw: u3, - value: MCOPRE, - }, - /// Microcontroller clock output 2 - MCO2SEL: packed union { - raw: u2, - value: MCO2SEL, - }, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_79: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// clock interrupt register - CIR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// PLL ready interrupt flag - PLLRDYF: u1, - /// PLLI2S ready interrupt flag - PLLI2SRDYF: u1, - /// PLLSAI ready interrupt flag - PLLSAIRDYF: u1, - /// Clock security system interrupt flag - CSSF: u1, - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// PLL ready interrupt enable - PLLRDYIE: u1, - /// PLLI2S ready interrupt enable - PLLI2SRDYIE: u1, - /// PLLSAI Ready Interrupt Enable - PLLSAIRDYIE: u1, - reserved16: u1, - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// Main PLL(PLL) ready interrupt clear - PLLRDYC: u1, - /// PLLI2S ready interrupt clear - PLLI2SRDYC: u1, - /// PLLSAI Ready Interrupt Clear - PLLSAIRDYC: u1, - /// Clock security system interrupt clear - CSSC: u1, - padding: u8, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_80: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - /// IO port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// IO port H reset - GPIOHRST: u1, - /// IO port I reset - GPIOIRST: u1, - /// IO port J reset - GPIOJRST: u1, - /// IO port K reset - GPIOKRST: u1, - reserved12: u1, - /// CRC reset - CRCRST: u1, - reserved21: u8, - /// DMA2 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - /// DMA2D reset - DMA2DRST: u1, - reserved25: u1, - /// Ethernet MAC reset - ETHRST: u1, - reserved29: u3, - /// USB OTG HS module reset - USB_OTG_HSRST: u1, - padding: u2, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_81: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// Camera interface reset - DCMIRST: u1, - reserved4: u3, - /// AES module reset - AESRST: u1, - /// Hash module reset - HSAHRST: u1, - /// Random number generator module reset - RNGRST: u1, - /// USB OTG FS module reset - USB_OTG_FSRST: u1, - padding: u24, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_82: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// AHB3 peripheral reset register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller module reset - FMCRST: u1, - /// Quad SPI memory controller reset - QUADSPIRST: u1, - padding: u30, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_83: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved32: [4]u8, - /// APB1 peripheral reset register - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// TIM2 reset - TIM2RST: u1, - /// TIM3 reset - TIM3RST: u1, - /// TIM4 reset - TIM4RST: u1, - /// TIM5 reset - TIM5RST: u1, - /// TIM6 reset - TIM6RST: u1, - /// TIM7 reset - TIM7RST: u1, - /// TIM12 reset - TIM12RST: u1, - /// TIM13 reset - TIM13RST: u1, - /// TIM14 reset - TIM14RST: u1, - /// Low power timer 1 reset - LPTIM1RST: u1, - reserved11: u1, - /// Window watchdog reset - WWDGRST: u1, - reserved13: u1, - /// CAN 3 reset - CAN3RST: u1, - /// SPI 2 reset - SPI2RST: u1, - /// SPI 3 reset - SPI3RST: u1, - /// SPDIF-RX reset - SPDIFRXRST: u1, - /// USART 2 reset - USART2RST: u1, - /// USART 3 reset - USART3RST: u1, - /// USART 4 reset - UART4RST: u1, - /// USART 5 reset - UART5RST: u1, - /// I2C 1 reset - I2C1RST: u1, - /// I2C 2 reset - I2C2RST: u1, - /// I2C3 reset - I2C3RST: u1, - /// I2C 4 reset - I2C4RST: u1, - /// CAN1 reset - CAN1RST: u1, - /// CAN2 reset - CAN2RST: u1, - /// HDMI-CEC reset - CECRST: u1, - /// Power interface reset - PWRRST: u1, - /// DAC reset - DACRST: u1, - /// UART7 reset - UART7RST: u1, - /// UART8 reset - UART8RST: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_84: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// TIM1 reset - TIM1RST: u1, - /// TIM8 reset - TIM8RST: u1, - reserved4: u2, - /// USART1 reset - USART1RST: u1, - /// USART6 reset - USART6RST: u1, - reserved7: u1, - /// SDMMC2 reset - SDMMC2RST: u1, - /// ADC interface reset (common to all ADCs) - ADCRST: u1, - reserved11: u2, - /// SDMMC1 reset - SDMMC1RST: u1, - /// SPI 1 reset - SPI1RST: u1, - /// SPI4 reset - SPI4RST: u1, - /// System configuration controller reset - SYSCFGRST: u1, - reserved16: u1, - /// TIM9 reset - TIM9RST: u1, - /// TIM10 reset - TIM10RST: u1, - /// TIM11 reset - TIM11RST: u1, - reserved20: u1, - /// SPI5 reset - SPI5RST: u1, - /// SPI6 reset - SPI6RST: u1, - /// SAI1 reset - SAI1RST: u1, - /// SAI2 reset - SAI2RST: u1, - reserved26: u2, - /// LTDC reset - LTDCRST: u1, - /// DSI reset - DSIRST: u1, - reserved29: u1, - /// DFSDM 1 reset - DFSDM1RST: u1, - /// MDIOS reset - MDIOSRST: u1, - /// USB OTG HS PHY controller reset - USBPHYCRST: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_85: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved48: [8]u8, - /// AHB1 peripheral clock register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port C clock enable - GPIOCEN: u1, - /// IO port D clock enable - GPIODEN: u1, - /// IO port E clock enable - GPIOEEN: u1, - /// IO port F clock enable - GPIOFEN: u1, - /// IO port G clock enable - GPIOGEN: u1, - /// IO port H clock enable - GPIOHEN: u1, - /// IO port I clock enable - GPIOIEN: u1, - /// IO port J clock enable - GPIOJEN: u1, - /// IO port K clock enable - GPIOKEN: u1, - reserved12: u1, - /// CRC clock enable - CRCEN: u1, - reserved18: u5, - /// Backup SRAM interface clock enable - BKPSRAMEN: u1, - reserved20: u1, - /// CCM data RAM clock enable - DTCMRAMEN: u1, - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// DMA2D clock enable - DMA2DEN: u1, - reserved25: u1, - /// Ethernet MAC clock enable - ETHEN: u1, - /// Ethernet Transmission clock enable - ETHTXEN: u1, - /// Ethernet Reception clock enable - ETHRXEN: u1, - /// Ethernet PTP clock enable - ETHPTPEN: u1, - /// USB OTG HS clock enable - USB_OTG_HSEN: u1, - /// USB OTG HSULPI clock enable - USB_OTG_HSULPIEN: u1, - padding: u1, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_86: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// AHB2 peripheral clock enable register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// Camera interface enable - DCMIEN: u1, - /// JPEG enable - JPEGEN: u1, - reserved4: u2, - /// AES module clock enable - AESEN: u1, - /// Hash modules clock enable - HASHEN: u1, - /// Random number generator clock enable - RNGEN: u1, - /// USB OTG FS clock enable - USB_OTG_FSEN: u1, - padding: u24, + /// JPEG encoder, AC Huffman table 0 + HUFFENC_AC0_87: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// AHB3 peripheral clock enable register - AHB3ENR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller module clock enable - FMCEN: u1, - /// Quad SPI memory controller clock enable - QUADSPIEN: u1, - padding: u30, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_0: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved64: [4]u8, - /// APB1 peripheral clock enable register - APB1ENR: mmio.Mmio(packed struct(u32) { - /// TIM2 clock enable - TIM2EN: u1, - /// TIM3 clock enable - TIM3EN: u1, - /// TIM4 clock enable - TIM4EN: u1, - /// TIM5 clock enable - TIM5EN: u1, - /// TIM6 clock enable - TIM6EN: u1, - /// TIM7 clock enable - TIM7EN: u1, - /// TIM12 clock enable - TIM12EN: u1, - /// TIM13 clock enable - TIM13EN: u1, - /// TIM14 clock enable - TIM14EN: u1, - /// Low power timer 1 clock enable - LPTIM1EN: u1, - /// RTCAPB clock enable - RTCEN: u1, - /// Window watchdog clock enable - WWDGEN: u1, - reserved13: u1, - /// CAN 3 enable - CAN3EN: u1, - /// SPI2 clock enable - SPI2EN: u1, - /// SPI3 clock enable - SPI3EN: u1, - /// SPDIF-RX clock enable - SPDIFRXEN: u1, - /// USART 2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// UART5 clock enable - UART5EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - /// I2C2 clock enable - I2C2EN: u1, - /// I2C3 clock enable - I2C3EN: u1, - /// I2C4 clock enable - I2C4EN: u1, - /// CAN 1 clock enable - CAN1EN: u1, - /// CAN 2 clock enable - CAN2EN: u1, - /// HDMI-CEN clock enable - CECEN: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - /// UART7 clock enable - UART7EN: u1, - /// UART8 clock enable - UART8EN: u1, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_1: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// APB2 peripheral clock enable register - APB2ENR: mmio.Mmio(packed struct(u32) { - /// TIM1 clock enable - TIM1EN: u1, - /// TIM8 clock enable - TIM8EN: u1, - reserved4: u2, - /// USART1 clock enable - USART1EN: u1, - /// USART6 clock enable - USART6EN: u1, - reserved7: u1, - /// SDMMC2 clock enable - SDMMC2EN: u1, - /// ADC1 clock enable - ADC1EN: u1, - /// ADC2 clock enable - ADC2EN: u1, - /// ADC3 clock enable - ADC3EN: u1, - /// SDMMC1 clock enable - SDMMC1EN: u1, - /// SPI1 clock enable - SPI1EN: u1, - /// SPI4 clock enable - SPI4EN: u1, - /// System configuration controller clock enable - SYSCFGEN: u1, - reserved16: u1, - /// TIM9 clock enable - TIM9EN: u1, - /// TIM10 clock enable - TIM10EN: u1, - /// TIM11 clock enable - TIM11EN: u1, - reserved20: u1, - /// SPI5 clock enable - SPI5EN: u1, - /// SPI6 clock enable - SPI6EN: u1, - /// SAI1 clock enable - SAI1EN: u1, - /// SAI2 clock enable - SAI2EN: u1, - reserved26: u2, - /// LTDC clock enable - LTDCEN: u1, - /// DSI clock enable - DSIEN: u1, - reserved29: u1, - /// DFSDM1 clock enable - DFSDM1EN: u1, - /// MDIO clock enable - MDIOSEN: u1, - /// USB OTG HS PHY controller clock enable - USBPHYCEN: u1, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_2: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved80: [8]u8, - /// AHB1 peripheral clock enable in low power mode register - AHB1LPENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable during sleep mode - GPIOALPEN: u1, - /// IO port B clock enable during Sleep mode - GPIOBLPEN: u1, - /// IO port C clock enable during Sleep mode - GPIOCLPEN: u1, - /// IO port D clock enable during Sleep mode - GPIODLPEN: u1, - /// IO port E clock enable during Sleep mode - GPIOELPEN: u1, - /// IO port F clock enable during Sleep mode - GPIOFLPEN: u1, - /// IO port G clock enable during Sleep mode - GPIOGLPEN: u1, - /// IO port H clock enable during Sleep mode - GPIOHLPEN: u1, - /// IO port I clock enable during Sleep mode - GPIOILPEN: u1, - /// IO port J clock enable during Sleep mode - GPIOJLPEN: u1, - /// IO port K clock enable during Sleep mode - GPIOKLPEN: u1, - reserved12: u1, - /// CRC clock enable during Sleep mode - CRCLPEN: u1, - /// AXI to AHB bridge clock enable during Sleep mode - AXILPEN: u1, - reserved15: u1, - /// Flash interface clock enable during Sleep mode - FLASHLPEN: u1, - /// SRAM 1interface clock enable during Sleep mode - SRAM1LPEN: u1, - /// SRAM 2 interface clock enable during Sleep mode - SRAM2LPEN: u1, - /// Backup SRAM interface clock enable during Sleep mode - BKPSRAMLPEN: u1, - /// SRAM 3 interface clock enable during Sleep mode - SRAM3LPEN: u1, - /// DTCM RAM interface clock enable during Sleep mode - DTCMLPEN: u1, - /// DMA1 clock enable during Sleep mode - DMA1LPEN: u1, - /// DMA2 clock enable during Sleep mode - DMA2LPEN: u1, - /// DMA2D clock enable during Sleep mode - DMA2DLPEN: u1, - reserved25: u1, - /// Ethernet MAC clock enable during Sleep mode - ETHLPEN: u1, - /// Ethernet transmission clock enable during Sleep mode - ETHTXLPEN: u1, - /// Ethernet reception clock enable during Sleep mode - ETHRXLPEN: u1, - /// Ethernet PTP clock enable during Sleep mode - ETHPTPLPEN: u1, - /// USB OTG HS clock enable during Sleep mode - USB_OTG_HSLPEN: u1, - /// USB OTG HS ULPI clock enable during Sleep mode - USB_OTG_HSULPILPEN: u1, - padding: u1, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_3: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// AHB2 peripheral clock enable in low power mode register - AHB2LPENR: mmio.Mmio(packed struct(u32) { - /// Camera interface enable during Sleep mode - DCMILPEN: u1, - /// JPEG module enabled during Sleep mode - JPEGLPEN: u1, - reserved4: u2, - /// AES module clock enable during Sleep mode - AESLPEN: u1, - /// Hash modules clock enable during Sleep mode - HASHLPEN: u1, - /// Random number generator clock enable during Sleep mode - RNGLPEN: u1, - /// USB OTG FS clock enable during Sleep mode - USB_OTG_FSLPEN: u1, - padding: u24, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_4: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// AHB3 peripheral clock enable in low power mode register - AHB3LPENR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller module clock enable during Sleep mode - FMCLPEN: u1, - /// Quand SPI memory controller clock enable during Sleep mode - QUADSPILPEN: u1, - padding: u30, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_5: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved96: [4]u8, - /// APB1 peripheral clock enable in low power mode register - APB1LPENR: mmio.Mmio(packed struct(u32) { - /// TIM2 clock enable during Sleep mode - TIM2LPEN: u1, - /// TIM3 clock enable during Sleep mode - TIM3LPEN: u1, - /// TIM4 clock enable during Sleep mode - TIM4LPEN: u1, - /// TIM5 clock enable during Sleep mode - TIM5LPEN: u1, - /// TIM6 clock enable during Sleep mode - TIM6LPEN: u1, - /// TIM7 clock enable during Sleep mode - TIM7LPEN: u1, - /// TIM12 clock enable during Sleep mode - TIM12LPEN: u1, - /// TIM13 clock enable during Sleep mode - TIM13LPEN: u1, - /// TIM14 clock enable during Sleep mode - TIM14LPEN: u1, - /// low power timer 1 clock enable during Sleep mode - LPTIM1LPEN: u1, - /// RTCAPB clock enable during Sleep mode - RTCLPEN: u1, - /// Window watchdog clock enable during Sleep mode - WWDGLPEN: u1, - reserved13: u1, - /// CAN 3 clock enable during Sleep mode - CAN3LPEN: u1, - /// SPI2 clock enable during Sleep mode - SPI2LPEN: u1, - /// SPI3 clock enable during Sleep mode - SPI3LPEN: u1, - /// SPDIF-RX clock enable during sleep mode - SPDIFRXLPEN: u1, - /// USART2 clock enable during Sleep mode - USART2LPEN: u1, - /// USART3 clock enable during Sleep mode - USART3LPEN: u1, - /// UART4 clock enable during Sleep mode - UART4LPEN: u1, - /// UART5 clock enable during Sleep mode - UART5LPEN: u1, - /// I2C1 clock enable during Sleep mode - I2C1LPEN: u1, - /// I2C2 clock enable during Sleep mode - I2C2LPEN: u1, - /// I2C3 clock enable during Sleep mode - I2C3LPEN: u1, - /// I2C4 clock enable during Sleep mode - I2C4LPEN: u1, - /// CAN 1 clock enable during Sleep mode - CAN1LPEN: u1, - /// CAN 2 clock enable during Sleep mode - CAN2LPEN: u1, - /// HDMI-CEN clock enable during Sleep mode - CECLPEN: u1, - /// Power interface clock enable during Sleep mode - PWRLPEN: u1, - /// DAC interface clock enable during Sleep mode - DACLPEN: u1, - /// UART7 clock enable during Sleep mode - UART7LPEN: u1, - /// UART8 clock enable during Sleep mode - UART8LPEN: u1, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_6: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// APB2 peripheral clock enabled in low power mode register - APB2LPENR: mmio.Mmio(packed struct(u32) { - /// TIM1 clock enable during Sleep mode - TIM1LPEN: u1, - /// TIM8 clock enable during Sleep mode - TIM8LPEN: u1, - reserved4: u2, - /// USART1 clock enable during Sleep mode - USART1LPEN: u1, - /// USART6 clock enable during Sleep mode - USART6LPEN: u1, - reserved7: u1, - /// SDMMC2 clock enable during Sleep mode - SDMMC2LPEN: u1, - /// ADC1 clock enable during Sleep mode - ADC1LPEN: u1, - /// ADC2 clock enable during Sleep mode - ADC2LPEN: u1, - /// ADC 3 clock enable during Sleep mode - ADC3LPEN: u1, - /// SDMMC1 clock enable during Sleep mode - SDMMC1LPEN: u1, - /// SPI 1 clock enable during Sleep mode - SPI1LPEN: u1, - /// SPI 4 clock enable during Sleep mode - SPI4LPEN: u1, - /// System configuration controller clock enable during Sleep mode - SYSCFGLPEN: u1, - reserved16: u1, - /// TIM9 clock enable during sleep mode - TIM9LPEN: u1, - /// TIM10 clock enable during Sleep mode - TIM10LPEN: u1, - /// TIM11 clock enable during Sleep mode - TIM11LPEN: u1, - reserved20: u1, - /// SPI 5 clock enable during Sleep mode - SPI5LPEN: u1, - /// SPI 6 clock enable during Sleep mode - SPI6LPEN: u1, - /// SAI1 clock enable during sleep mode - SAI1LPEN: u1, - /// SAI2 clock enable during sleep mode - SAI2LPEN: u1, - reserved26: u2, - /// LTDC clock enable during sleep mode - LTDCLPEN: u1, - /// DSI clock enable during Sleep mode - DSILPEN: u1, - reserved29: u1, - /// DFSDM1 clock enable during Sleep mode - DFSDM1LPEN: u1, - /// MDIO clock enable during Sleep mode - MDIOSLPEN: u1, - padding: u1, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_7: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved112: [8]u8, - /// Backup domain control register - BDCR: mmio.Mmio(packed struct(u32) { - /// External low-speed oscillator enable - LSEON: u1, - /// External low-speed oscillator ready - LSERDY: u1, - /// External low-speed oscillator bypass - LSEBYP: u1, - /// LSE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - reserved8: u3, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - padding: u15, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_8: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// clock control & status register - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low-speed oscillator enable - LSION: u1, - /// Internal low-speed oscillator ready - LSIRDY: u1, - reserved24: u22, - /// Remove reset flag - RMVF: u1, - /// BOR reset flag - BORRSTF: u1, - /// PIN reset flag - PADRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - WDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_9: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - reserved128: [8]u8, - /// spread spectrum clock generation register - SSCGR: mmio.Mmio(packed struct(u32) { - /// Modulation period - MODPER: u13, - /// Incrementation step - INCSTEP: u15, - reserved30: u2, - /// Spread Select - SPREADSEL: packed union { - raw: u1, - value: SPREADSEL, - }, - /// Spread spectrum modulation enable - SSCGEN: u1, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_10: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// PLLI2S configuration register - PLLI2SCFGR: mmio.Mmio(packed struct(u32) { - reserved6: u6, - /// PLL multiplication factor for VCO - PLLN: packed union { - raw: u9, - value: PLLN, - }, - reserved16: u1, - /// PLL division factor for main system clock - PLLP: packed union { - raw: u2, - value: PLLP, - }, - reserved24: u6, - /// PLL division factor for USB OTG FS, SDIO and random number generator clocks - PLLQ: packed union { - raw: u4, - value: PLLQ, - }, - /// PLL division factor for DSI clock - PLLR: packed union { - raw: u3, - value: PLLR, - }, - padding: u1, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_11: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// PLL configuration register - PLLSAICFGR: mmio.Mmio(packed struct(u32) { - reserved6: u6, - /// PLL multiplication factor for VCO - PLLN: packed union { - raw: u9, - value: PLLN, - }, - reserved16: u1, - /// PLL division factor for main system clock - PLLP: packed union { - raw: u2, - value: PLLP, - }, - reserved24: u6, - /// PLL division factor for USB OTG FS, SDIO and random number generator clocks - PLLQ: packed union { - raw: u4, - value: PLLQ, - }, - /// PLL division factor for DSI clock - PLLR: packed union { - raw: u3, - value: PLLR, - }, - padding: u1, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_12: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// dedicated clocks configuration register - DCKCFGR1: mmio.Mmio(packed struct(u32) { - /// PLLI2S division factor for SAI1 clock - PLLI2SDIVQ: packed union { - raw: u5, - value: PLLI2SDIVQ, - }, - reserved8: u3, - /// PLLSAI division factor for SAI1 clock - PLLSAIDIVQ: packed union { - raw: u5, - value: PLLSAIDIVQ, - }, - reserved16: u3, - /// division factor for LCD_CLK - PLLSAIDIVR: packed union { - raw: u2, - value: PLLSAIDIVR, - }, - reserved20: u2, - /// SAI1 clock source selection - SAI1SEL: packed union { - raw: u2, - value: SAISEL, - }, - /// SAI2 clock source selection - SAI2SEL: packed union { - raw: u2, - value: SAISEL, - }, - /// Timers clocks prescalers selection - TIMPRE: packed union { - raw: u1, - value: TIMPRE, - }, - /// DFSDM1 clock source selection - DFSDM1SEL: packed union { - raw: u1, - value: DFSDMSEL, - }, - /// DFSDM1 AUDIO clock source selection - ADFSDM1SEL: packed union { - raw: u1, - value: ADFSDMSEL, - }, - padding: u5, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_13: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - /// dedicated clocks configuration register - DCKCFGR2: mmio.Mmio(packed struct(u32) { - /// USART 1 clock source selection - USART1SEL: packed union { - raw: u2, - value: USART1SEL, - }, - /// USART 2 clock source selection - USART2SEL: packed union { - raw: u2, - value: USART2SEL, - }, - /// USART 3 clock source selection - USART3SEL: packed union { - raw: u2, - value: USART2SEL, - }, - /// UART 4 clock source selection - UART4SEL: packed union { - raw: u2, - value: USART2SEL, - }, - /// UART 5 clock source selection - UART5SEL: packed union { - raw: u2, - value: USART2SEL, - }, - /// USART 6 clock source selection - USART6SEL: packed union { - raw: u2, - value: USART1SEL, - }, - /// UART 7 clock source selection - UART7SEL: packed union { - raw: u2, - value: USART2SEL, - }, - /// UART 8 clock source selection - UART8SEL: packed union { - raw: u2, - value: USART2SEL, - }, - /// I2C1 clock source selection - I2C1SEL: packed union { - raw: u2, - value: I2CSEL, - }, - /// I2C2 clock source selection - I2C2SEL: packed union { - raw: u2, - value: I2CSEL, - }, - /// I2C3 clock source selection - I2C3SEL: packed union { - raw: u2, - value: I2CSEL, - }, - /// I2C4 clock source selection - I2C4SEL: packed union { - raw: u2, - value: I2CSEL, - }, - /// Low power timer 1 clock source selection - LPTIM1SEL: packed union { - raw: u2, - value: LPTIMSEL, - }, - /// HDMI-CEC clock source selection - CECSEL: packed union { - raw: u1, - value: CECSEL, - }, - /// 48MHz clock source selection - CLK48SEL: packed union { - raw: u1, - value: CLK48SEL, - }, - /// SDMMC1 clock source selection - SDMMC1SEL: packed union { - raw: u1, - value: SDMMCSEL, - }, - /// SDMMC2 clock source selection - SDMMC2SEL: packed union { - raw: u1, - value: SDMMCSEL, - }, - /// DSI clock source selection - DSISEL: packed union { - raw: u1, - value: DSISEL, - }, - padding: u1, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_14: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, }), - }; - }; - - pub const rcc_f37 = struct { - pub const ADCPRE = enum(u2) { - /// PCLK divided by 2 - Div2 = 0x0, - /// PCLK divided by 4 - Div4 = 0x1, - /// PCLK divided by 6 - Div6 = 0x2, - /// PCLK divided by 8 - Div8 = 0x3, - }; - - pub const ADCPRES = enum(u5) { - /// PLL clock not divided - Div1 = 0x10, - /// PLL clock divided by 2 - Div2 = 0x11, - /// PLL clock divided by 4 - Div4 = 0x12, - /// PLL clock divided by 6 - Div6 = 0x13, - /// PLL clock divided by 8 - Div8 = 0x14, - /// PLL clock divided by 10 - Div10 = 0x15, - /// PLL clock divided by 12 - Div12 = 0x16, - /// PLL clock divided by 16 - Div16 = 0x17, - /// PLL clock divided by 32 - Div32 = 0x18, - /// PLL clock divided by 64 - Div64 = 0x19, - /// PLL clock divided by 128 - Div128 = 0x1a, - /// PLL clock divided by 256 - Div256 = 0x1b, - _, - }; - - pub const CECSW = enum(u1) { - /// HSI clock divided by 244 selected as CEC clock source - HSI_DIV_244 = 0x0, - /// LSE clock selected as CEC clock source - LSE = 0x1, - }; - - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, - _, - }; - - pub const ICSW = enum(u1) { - /// HSI clock selected as I2C clock source - HSI = 0x0, - /// SYSCLK clock selected as I2C clock source - SYS = 0x1, - }; - - pub const ISSRC = enum(u1) { - /// System clock used as I2S clock source - SYS = 0x0, - /// External clock mapped on the I2S_CKIN pin used as I2S clock source - CKIN = 0x1, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium high driving capability - MediumHigh = 0x1, - /// Medium low driving capability - MediumLow = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCOSEL = enum(u3) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// Internal low speed (LSI) oscillator clock selected - LSI = 0x2, - /// External low speed (LSE) oscillator clock selected - LSE = 0x3, - /// System clock selected - SYS = 0x4, - /// Internal RC 8 MHz (HSI) oscillator clock selected - HSI = 0x5, - /// External 4-32 MHz (HSE) oscillator clock selected - HSE = 0x6, - /// PLL clock divided by 2 - PLL_DIV_2 = 0x7, - _, - }; - - pub const PLLMUL = enum(u4) { - /// PLL input clock x2 - Mul2 = 0x0, - /// PLL input clock x3 - Mul3 = 0x1, - /// PLL input clock x4 - Mul4 = 0x2, - /// PLL input clock x5 - Mul5 = 0x3, - /// PLL input clock x6 - Mul6 = 0x4, - /// PLL input clock x7 - Mul7 = 0x5, - /// PLL input clock x8 - Mul8 = 0x6, - /// PLL input clock x9 - Mul9 = 0x7, - /// PLL input clock x10 - Mul10 = 0x8, - /// PLL input clock x11 - Mul11 = 0x9, - /// PLL input clock x12 - Mul12 = 0xa, - /// PLL input clock x13 - Mul13 = 0xb, - /// PLL input clock x14 - Mul14 = 0xc, - /// PLL input clock x15 - Mul15 = 0xd, - /// PLL input clock x16 - Mul16 = 0xe, - _, - }; - - pub const PLLSRC = enum(u1) { - /// HSI divided by 2 selected as PLL input clock - HSI_Div2 = 0x0, - /// HSE divided by PREDIV selected as PLL input clock - HSE_Div_PREDIV = 0x1, - }; - - pub const PLLXTPRE = enum(u1) { - /// HSE clock not divided - Div1 = 0x0, - /// HSE clock divided by 2 - Div2 = 0x1, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const PREDIV = enum(u4) { - /// PREDIV input clock not divided - Div1 = 0x0, - /// PREDIV input clock divided by 2 - Div2 = 0x1, - /// PREDIV input clock divided by 3 - Div3 = 0x2, - /// PREDIV input clock divided by 4 - Div4 = 0x3, - /// PREDIV input clock divided by 5 - Div5 = 0x4, - /// PREDIV input clock divided by 6 - Div6 = 0x5, - /// PREDIV input clock divided by 7 - Div7 = 0x6, - /// PREDIV input clock divided by 8 - Div8 = 0x7, - /// PREDIV input clock divided by 9 - Div9 = 0x8, - /// PREDIV input clock divided by 10 - Div10 = 0x9, - /// PREDIV input clock divided by 11 - Div11 = 0xa, - /// PREDIV input clock divided by 12 - Div12 = 0xb, - /// PREDIV input clock divided by 13 - Div13 = 0xc, - /// PREDIV input clock divided by 14 - Div14 = 0xd, - /// PREDIV input clock divided by 15 - Div15 = 0xe, - /// PREDIV input clock divided by 16 - Div16 = 0xf, - }; - - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, - }; - - pub const SDPRE = enum(u5) { - /// SYSCLK divided by 2 - Div2 = 0x0, - /// SYSCLK divided by 4 - Div4 = 0x11, - /// SYSCLK divided by 6 - Div6 = 0x12, - /// SYSCLK divided by 8 - Div8 = 0x13, - /// SYSCLK divided by 10 - Div10 = 0x14, - /// SYSCLK divided by 12 - Div12 = 0x15, - /// SYSCLK divided by 14 - Div14 = 0x16, - /// SYSCLK divided by 16 - Div16 = 0x17, - /// SYSCLK divided by 20 - Div20 = 0x18, - /// SYSCLK divided by 24 - Div24 = 0x19, - /// SYSCLK divided by 28 - Div28 = 0x1a, - /// SYSCLK divided by 32 - Div32 = 0x1b, - /// SYSCLK divided by 36 - Div36 = 0x1c, - /// SYSCLK divided by 40 - Div40 = 0x1d, - /// SYSCLK divided by 44 - Div44 = 0x1e, - /// SYSCLK divided by 48 - Div48 = 0x1f, - _, - }; - - pub const SW = enum(u2) { - /// HSI oscillator used as system clock - HSI = 0x0, - /// HSE oscillator used as system clock - HSE = 0x1, - /// PLL used as system clock - PLL1_P = 0x2, + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_15: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_16: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_17: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_18: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_19: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_20: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_21: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_22: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_23: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_24: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_25: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_26: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_27: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_28: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_29: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_30: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_31: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_32: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_33: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_34: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_35: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_36: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_37: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_38: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_39: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_40: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_41: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_42: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_43: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_44: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_45: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_46: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_47: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_48: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_49: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_50: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_51: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_52: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_53: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_54: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_55: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_56: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_57: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_58: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_59: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_60: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_61: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_62: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_63: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_64: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_65: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_66: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_67: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_68: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_69: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_70: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_71: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_72: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_73: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_74: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_75: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_76: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_77: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_78: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_79: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_80: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_81: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_82: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_83: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_84: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_85: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_86: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, AC Huffman table 1 + HUFFENC_AC1_87: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 0 + HUFFENC_DC0_0: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 0 + HUFFENC_DC0_1: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 0 + HUFFENC_DC0_2: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 0 + HUFFENC_DC0_3: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 0 + HUFFENC_DC0_4: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 0 + HUFFENC_DC0_5: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 0 + HUFFENC_DC0_6: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 0 + HUFFENC_DC0_7: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 1 + HUFFENC_DC1_0: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 1 + HUFFENC_DC1_1: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 1 + HUFFENC_DC1_2: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 1 + HUFFENC_DC1_3: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 1 + HUFFENC_DC1_4: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 1 + HUFFENC_DC1_5: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 1 + HUFFENC_DC1_6: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + /// JPEG encoder, DC Huffman table 1 + HUFFENC_DC1_7: mmio.Mmio(packed struct(u32) { + /// DHTMem RAM + DHTMem_RAM: u32, + }), + }; + }; + + pub const lcd_v1 = struct { + /// Liquid crystal display controller + pub const LCD = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// LCD controller enable + LCDEN: u1, + /// Voltage source selection + VSEL: u1, + /// Duty selection + DUTY: u3, + /// Bias selector + BIAS: u2, + /// Mux segment enable + MUX_SEG: u1, + padding: u24, + }), + /// frame control register + FCR: mmio.Mmio(packed struct(u32) { + /// High drive enable + HD: u1, + /// Start of frame interrupt enable + SOFIE: u1, + reserved3: u1, + /// Update display done interrupt enable + UDDIE: u1, + /// Pulse ON duration + PON: u3, + /// Dead time duration + DEAD: u3, + /// Contrast control + CC: u3, + /// Blink frequency selection + BLINKF: u3, + /// Blink mode selection + BLINK: u2, + /// DIV clock divider + DIV: u4, + /// PS 16-bit prescaler + PS: u4, + padding: u6, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// LCD enabled status + ENS: u1, + /// Start of frame flag + SOF: u1, + /// Update display request + UDR: u1, + /// Update Display Done + UDD: u1, + /// Ready flag + RDY: u1, + /// LCD Frame Control Register Synchronization flag + FCRSF: u1, + padding: u26, + }), + /// clear register + CLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Start of frame flag clear + SOFC: u1, + reserved3: u1, + /// Update display done clear + UDDC: u1, + padding: u28, + }), + reserved20: [4]u8, + /// display memory + RAM_COM: u32, + }; + + /// display memory + pub const RAM_COM = extern struct { + /// display memory low word + LOW: u32, + /// display memory high word + HIGH: u32, + }; + }; + + pub const lcd_v2 = struct { + /// Liquid crystal display controller + pub const LCD = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// LCD controller enable + LCDEN: u1, + /// Voltage source selection + VSEL: u1, + /// Duty selection + DUTY: u3, + /// Bias selector + BIAS: u2, + /// Mux segment enable + MUX_SEG: u1, + /// Voltage output buffer enable + BUFEN: u1, + padding: u23, + }), + /// frame control register + FCR: mmio.Mmio(packed struct(u32) { + /// High drive enable + HD: u1, + /// Start of frame interrupt enable + SOFIE: u1, + reserved3: u1, + /// Update display done interrupt enable + UDDIE: u1, + /// Pulse ON duration + PON: u3, + /// Dead time duration + DEAD: u3, + /// Contrast control + CC: u3, + /// Blink frequency selection + BLINKF: u3, + /// Blink mode selection + BLINK: u2, + /// DIV clock divider + DIV: u4, + /// PS 16-bit prescaler + PS: u4, + padding: u6, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// LCD enabled status + ENS: u1, + /// Start of frame flag + SOF: u1, + /// Update display request + UDR: u1, + /// Update Display Done + UDD: u1, + /// Ready flag + RDY: u1, + /// LCD Frame Control Register Synchronization flag + FCRSF: u1, + padding: u26, + }), + /// clear register + CLR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Start of frame flag clear + SOFC: u1, + reserved3: u1, + /// Update display done clear + UDDC: u1, + padding: u28, + }), + reserved20: [4]u8, + /// display memory + RAM_COM: u32, + }; + + /// display memory + pub const RAM_COM = extern struct { + /// display memory low word + LOW: u32, + /// display memory high word + HIGH: u32, + }; + }; + + pub const lpdma_v1 = struct { + pub const BREQ = enum(u1) { + /// the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + Burst = 0x0, + /// the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ). + Block = 0x1, + }; + + pub const DEC = enum(u1) { + /// The address is incremented by the programmed offset. + Add = 0x0, + /// The address is decremented by the programmed offset. + Subtract = 0x1, + }; + + pub const DREQ = enum(u1) { + /// selected hardware request driven by a source peripheral (request signal taken into account by the LPDMA transfer scheduler over the source/read port) + SourcePeripheral = 0x0, + /// selected hardware request driven by a destination peripheral (request signal taken into account by the LPDMA transfer scheduler over the destination/write port) + DestinationPeripheral = 0x1, + }; + + pub const DW = enum(u2) { + /// byte + Byte = 0x0, + /// half-word (2 bytes) + HalfWord = 0x1, + /// word (4 bytes) + Word = 0x2, _, }; - pub const TIM2SW = enum(u1) { - /// PCLK2 clock (doubled frequency when prescaled) - PCLK1_TIM = 0x0, - /// PLL vco output (running up to 144 MHz) - PLL1_P = 0x1, + pub const LSM = enum(u1) { + /// channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. + RunToCompletion = 0x0, + /// channel executed once for the current LLI + LinkStep = 0x1, }; - pub const TIMSW = enum(u1) { - /// PCLK2 clock (doubled frequency when prescaled) - PCLK2_TIM = 0x0, - /// PLL vco output (running up to 144 MHz) - PLL1_P = 0x1, + pub const PAM = enum(u2) { + /// If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width If source is wider: source data is transferred as right aligned, left-truncated down to the destination data width + ZeroExtendOrLeftTruncate = 0x0, + /// If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width If source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width + SignExtendOrRightTruncate = 0x1, + /// source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination + Pack = 0x2, + _, }; - pub const USART1SW = enum(u2) { - /// PCLK selected as USART clock source - PCLK2 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, + pub const PRIO = enum(u2) { + /// low priority, low weight + LowWithLowhWeight = 0x0, + /// low priority, mid weight + LowWithMidWeight = 0x1, + /// low priority, high weight + LowWithHighWeight = 0x2, + /// high priority + High = 0x3, }; - pub const USARTSW = enum(u2) { - /// PCLK selected as USART clock source - PCLK1 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, + pub const SWREQ = enum(u1) { + /// no software request. The selected hardware request REQSEL[6:0] is taken into account. + Hardware = 0x0, + /// software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored. + Software = 0x1, }; - pub const USBPRE = enum(u1) { - /// PLL clock is divided by 1.5 - Div1_5 = 0x0, - /// PLL clock is not divided - Div1 = 0x1, + pub const TCEM = enum(u2) { + /// at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. + EachBlock = 0x0, + /// channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block. + Each2DBlock = 0x1, + /// at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer. + EachLinkedListItem = 0x2, + /// at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated. + LastLinkedListItem = 0x3, }; - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal High Speed clock enable - HSION: u1, - /// Internal High Speed clock ready flag - HSIRDY: u1, - reserved3: u1, - /// Internal High Speed clock trimming - HSITRIM: u5, - /// Internal High Speed clock Calibration - HSICAL: u8, - /// External High Speed clock enable - HSEON: u1, - /// External High Speed clock ready flag - HSERDY: u1, - /// External High Speed clock Bypass - HSEBYP: u1, - /// Clock Security System enable - CSSON: u1, - reserved24: u4, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding: u6, + pub const TRIGM = enum(u2) { + /// at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0). + Block = 0x0, + /// channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the + @"2DBlock" = 0x1, + /// at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned. + LinkedListItem = 0x2, + /// at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger. + Burst = 0x3, + }; + + pub const TRIGPOL = enum(u2) { + /// no trigger (masked trigger event) + None = 0x0, + /// trigger on the rising edge + RisingEdge = 0x1, + /// trigger on the falling edge + FallingEdge = 0x2, + /// same as 00 + NoneAlt = 0x3, + }; + + pub const Channel = extern struct { + /// LPDMA channel 15 linked-list base address register + LBAR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// linked-list base address of LPDMA channel x + LBA: u16, }), - /// Clock configuration register (RCC_CFGR) - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock Switch - SW: packed union { - raw: u2, - value: SW, + reserved12: [8]u8, + /// LPDMA channel 15 flag clear register + FCR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// transfer complete flag clear + TCF: u1, + /// half transfer flag clear + HTF: u1, + /// data transfer error flag clear + DTEF: u1, + /// update link transfer error flag clear + ULEF: u1, + /// user setting error flag clear + USEF: u1, + /// completed suspension flag clear + SUSPF: u1, + /// trigger overrun flag clear + TOF: u1, + padding: u17, + }), + /// LPDMA channel 15 status register + SR: mmio.Mmio(packed struct(u32) { + /// idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state). + IDLEF: u1, + reserved8: u7, + /// transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). + TCF: u1, + /// half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination. + HTF: u1, + /// data transfer error flag + DTEF: u1, + /// update link transfer error flag + ULEF: u1, + /// user setting error flag + USEF: u1, + /// completed suspension flag + SUSPF: u1, + /// trigger overrun flag + TOF: u1, + padding: u17, + }), + /// LPDMA channel 15 control register + CR: mmio.Mmio(packed struct(u32) { + /// enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + EN: u1, + /// reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in ). + RESET: u1, + /// suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going LPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in . + SUSP: u1, + reserved8: u5, + /// transfer complete interrupt enable + TCIE: u1, + /// half transfer complete interrupt enable + HTIE: u1, + /// data transfer error interrupt enable + DTEIE: u1, + /// update link transfer error interrupt enable + ULEIE: u1, + /// user setting error interrupt enable + USEIE: u1, + /// completed suspension interrupt enable + SUSPIE: u1, + /// trigger overrun interrupt enable + TOIE: u1, + reserved16: u1, + /// Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1. + LSM: packed union { + raw: u1, + value: LSM, }, - /// System Clock Switch Status - SWS: packed union { + reserved22: u5, + /// priority level of the channel x LPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. + PRIO: packed union { raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, + value: PRIO, }, - /// APB Low speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, + padding: u8, + }), + reserved64: [40]u8, + /// LPDMA channel 15 transfer register 1 + TR1: mmio.Mmio(packed struct(u32) { + /// binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued. + SDW: packed union { + raw: u2, + value: DW, }, - /// APB high speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, + reserved3: u1, + /// source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + SINC: u1, + reserved11: u7, + /// padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note: + PAM: packed union { + raw: u2, + value: PAM, }, - /// ADC prescaler - ADCPRE: packed union { + reserved15: u2, + /// security attribute of the LPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure. + SSEC: u1, + /// binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued. + DDW: packed union { raw: u2, - value: ADCPRE, + value: DW, }, - /// PLL entry clock source - PLLSRC: packed union { + reserved19: u1, + /// destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + DINC: u1, + reserved31: u11, + /// security attribute of the LPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure. + DSEC: u1, + }), + /// LPDMA channel 15 transfer register 2 + TR2: mmio.Mmio(packed struct(u32) { + /// LPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active LPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). LPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. + REQSEL: u7, + reserved9: u2, + /// software request. This bit is internally taken into account when CH[x].CR.EN is asserted. + SWREQ: packed union { raw: u1, - value: PLLSRC, + value: SWREQ, }, - /// HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products. - PLLXTPRE: packed union { + /// destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note: + DREQ: packed union { raw: u1, - value: PLLXTPRE, + value: DREQ, }, - /// PLL Multiplication Factor - PLLMUL: packed union { - raw: u4, - value: PLLMUL, + /// Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: + BREQ: packed union { + raw: u1, + value: BREQ, }, - /// USB prescaler - USBPRE: packed union { + reserved14: u2, + /// trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a LPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger. + TRIGM: packed union { + raw: u2, + value: TRIGM, + }, + /// trigger event input selection. These bits select the trigger event input of the LPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00. + TRIGSEL: u6, + reserved24: u2, + /// trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]. + TRIGPOL: packed union { + raw: u2, + value: TRIGPOL, + }, + reserved30: u4, + /// transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. + TCEM: packed union { + raw: u2, + value: TCEM, + }, + }), + /// LPDMA channel 15 alternate block register 1 + BR1: mmio.Mmio(packed struct(u32) { + /// block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued. + BNDT: u16, + /// Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer. + BRC: u11, + reserved28: u1, + /// source address decrement + SDEC: packed union { raw: u1, - value: USBPRE, + value: DEC, }, - /// I2S external clock source selection - I2SSRC: packed union { + /// destination address decrement + DDEC: packed union { raw: u1, - value: ISSRC, + value: DEC, }, - /// Microcontroller clock output - MCOSEL: packed union { - raw: u3, - value: MCOSEL, + /// Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer. + BRSDEC: packed union { + raw: u1, + value: DEC, }, - /// SDADC prescaler - SDPRE: packed union { - raw: u5, - value: SDPRE, + /// Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer. + BRDDEC: packed union { + raw: u1, + value: DEC, }, }), - /// Clock interrupt register (RCC_CIR) - CIR: mmio.Mmio(packed struct(u32) { - /// LSI Ready Interrupt flag - LSIRDYF: u1, - /// LSE Ready Interrupt flag - LSERDYF: u1, - /// HSI Ready Interrupt flag - HSIRDYF: u1, - /// HSE Ready Interrupt flag - HSERDYF: u1, - /// PLL Ready Interrupt flag - PLLRDYF: u1, - reserved7: u2, - /// Clock Security System Interrupt flag - CSSF: u1, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1, - /// LSE Ready Interrupt Enable - LSERDYIE: u1, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1, - /// HSE Ready Interrupt Enable - HSERDYIE: u1, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1, + /// LPDMA channel 15 source address register + SAR: u32, + /// LPDMA channel 15 destination address register + DAR: u32, + /// LPDMA channel 15 transfer register 3 + TR3: mmio.Mmio(packed struct(u32) { + /// source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied. + SAO: u13, reserved16: u3, - /// LSI Ready Interrupt Clear - LSIRDYC: u1, - /// LSE Ready Interrupt Clear - LSERDYC: u1, - /// HSI Ready Interrupt Clear - HSIRDYC: u1, - /// HSE Ready Interrupt Clear - HSERDYC: u1, - /// PLL Ready Interrupt Clear - PLLRDYC: u1, - reserved23: u2, - /// Clock security system interrupt clear - CSSC: u1, - padding: u8, + /// destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued. + DAO: u13, + padding: u3, }), - /// APB2 peripheral reset register (RCC_APB2RSTR) - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// SYSCFG and COMP reset - SYSCFGRST: u1, - reserved9: u8, - /// ADC interface reset - ADCRST: u1, - reserved12: u2, - /// SPI 1 reset - SPI1RST: u1, - reserved14: u1, - /// USART1 reset - USART1RST: u1, - reserved16: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - /// TIM19 timer reset - TIM19RST: u1, - reserved22: u2, - /// MCU debug module clock enable - DBGMCURST: u1, - reserved24: u1, - /// SDADC1 (Sigma delta ADC 1) reset - SDADC1RST: u1, - /// SDADC2 (Sigma delta ADC 2) reset - SDADC2RST: u1, - /// SDADC3 (Sigma delta ADC 3) reset - SDADC3RST: u1, - padding: u5, + /// LPDMA channel 15 block register 2 + BR2: mmio.Mmio(packed struct(u32) { + /// Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. + BRSAO: u16, + /// Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued. + BRDAO: u16, }), - /// APB1 peripheral reset register (RCC_APB1RSTR) - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - /// Timer 14 reset - TIM4RST: u1, - /// Timer 5 reset - TIM5RST: u1, - /// Timer 6 reset - TIM6RST: u1, - /// Timer 7 reset - TIM7RST: u1, - /// Timer 12 reset - TIM12RST: u1, - /// Timer 13 reset - TIM13RST: u1, - /// Timer 14 reset - TIM14RST: u1, - /// Timer 18 reset - TIM18RST: u1, - reserved11: u1, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI2 reset - SPI2RST: u1, - /// SPI3 reset - SPI3RST: u1, - reserved17: u1, - /// USART 2 reset - USART2RST: u1, - /// USART3 reset - USART3RST: u1, - reserved21: u2, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// USB reset - USBRST: u1, - reserved25: u1, - /// CAN reset - CANRST: u1, - /// DAC2 interface reset - DAC2RST: u1, - reserved28: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - /// HDMI CEC reset - CECRST: u1, - padding: u1, + reserved124: [32]u8, + /// LPDMA channel 15 alternate linked-list address register + LLR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list LPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list LPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. + LA: u14, + /// Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer. + ULL: u1, + reserved25: u8, + /// Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer. + UB2: u1, + /// Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer. + UT3: u1, + /// Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer. + UDA: u1, + /// update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer. + USA: u1, + /// Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. + UB1: u1, + /// Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer. + UT2: u1, + /// Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer. + UT1: u1, }), - /// AHB Peripheral Clock enable register (RCC_AHBENR) - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// SRAM interface clock enable - SRAMEN: u1, - reserved4: u1, - /// FLASH clock enable - FLASHEN: u1, - reserved6: u1, - /// CRC clock enable - CRCEN: u1, - reserved17: u10, - /// I/O port A clock enable - GPIOAEN: u1, - /// I/O port B clock enable - GPIOBEN: u1, - /// I/O port C clock enable - GPIOCEN: u1, - /// I/O port D clock enable - GPIODEN: u1, - /// I/O port E clock enable - GPIOEEN: u1, - /// I/O port F clock enable - GPIOFEN: u1, - reserved24: u1, - /// Touch sensing controller clock enable - TSCEN: u1, - padding: u7, + }; + + /// LPDMA + pub const LPDMA = extern struct { + /// LPDMA secure configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// SEC0 + SEC: u1, + padding: u31, }), - /// APB2 peripheral clock enable register (RCC_APB2ENR) - APB2ENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved9: u8, - /// ADC 1 interface clock enable - ADCEN: u1, - reserved12: u2, - /// SPI 1 clock enable - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable - USART1EN: u1, - reserved16: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - /// TIM19 timer clock enable - TIM19EN: u1, - reserved22: u2, - /// MCU debug module clock enable - DBGMCUEN: u1, - reserved24: u1, - /// SDADC1 (Sigma Delta ADC 1) clock enable - SDADC1EN: u1, - /// SDADC2 (Sigma Delta ADC 2) clock enable - SDADC2EN: u1, - /// SDADC3 (Sigma Delta ADC 3) clock enable - SDADC3EN: u1, - padding: u5, + /// LPDMA privileged configuration register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// PRIV0 + PRIV: u1, + padding: u31, }), - /// APB1 peripheral clock enable register (RCC_APB1ENR) - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer 2 clock enable - TIM2EN: u1, - /// Timer 3 clock enable - TIM3EN: u1, - /// Timer 4 clock enable - TIM4EN: u1, - /// Timer 5 clock enable - TIM5EN: u1, - /// Timer 6 clock enable - TIM6EN: u1, - /// Timer 7 clock enable - TIM7EN: u1, - /// Timer 12 clock enable - TIM12EN: u1, - /// Timer 13 clock enable - TIM13EN: u1, - /// Timer 14 clock enable - TIM14EN: u1, - /// Timer 18 clock enable - TIM18EN: u1, - reserved11: u1, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI 2 clock enable - SPI2EN: u1, - /// SPI 3 clock enable - SPI3EN: u1, - reserved17: u1, - /// USART 2 clock enable - USART2EN: u1, - /// USART 3 clock enable - USART3EN: u1, - reserved21: u2, - /// I2C 1 clock enable - I2C1EN: u1, - /// I2C 2 clock enable - I2C2EN: u1, - /// USB clock enable - USBEN: u1, - reserved25: u1, - /// CAN clock enable - CANEN: u1, - /// DAC2 interface clock enable - DAC2EN: u1, - reserved28: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - /// HDMI CEC interface clock enable - CECEN: u1, - padding: u1, + /// LPDMA configuration lock register + RCFGLOCKR: mmio.Mmio(packed struct(u32) { + /// LOCK0 + LOCK: u1, + padding: u31, }), - /// Backup domain control register (RCC_BDCR) - BDCR: mmio.Mmio(packed struct(u32) { - /// External Low Speed oscillator enable - LSEON: u1, - /// External Low Speed oscillator ready - LSERDY: u1, - /// External Low Speed oscillator bypass - LSEBYP: u1, - /// LSE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - reserved8: u3, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - padding: u15, + /// LPDMA non-secure masked interrupt status register + MISR: mmio.Mmio(packed struct(u32) { + /// MIS0 + MIS: u1, + padding: u31, }), - /// Control/status register (RCC_CSR) - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low speed oscillator enable - LSION: u1, - /// Internal low speed oscillator ready - LSIRDY: u1, - reserved23: u21, - /// Reset flag of the 1.8 V domain - V18PWRRSTF: u1, - /// Remove reset flag - RMVF: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// LPDMA secure masked interrupt status register + SMISR: mmio.Mmio(packed struct(u32) { + /// MIS0 + MIS: u1, + padding: u31, }), - /// AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - reserved17: u17, - /// I/O port A reset - GPIOARST: u1, - /// I/O port B reset - GPIOBRST: u1, - /// I/O port C reset - GPIOCRST: u1, - /// I/O port D reset - GPIODRST: u1, - /// I/O port E reset - GPIOERST: u1, - /// I/O port F reset - GPIOFRST: u1, - reserved24: u1, - /// Touch sensing controller reset - TSCRST: u1, - padding: u7, + reserved80: [60]u8, + CH: u32, + }; + }; + + pub const lptim_v1 = struct { + pub const CKPOL = enum(u2) { + /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + Rising = 0x0, + /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + Falling = 0x1, + /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + Both = 0x2, + _, + }; + + pub const ClockSource = enum(u1) { + /// clocked by internal clock source (APB clock or any of the embedded oscillators) + Internal = 0x0, + /// clocked by an external clock source through the LPTIM external Input1 + External = 0x1, + }; + + pub const Filter = enum(u2) { + Count1 = 0x0, + Count2 = 0x1, + Count4 = 0x2, + Count8 = 0x3, + }; + + pub const PRESC = enum(u3) { + Div1 = 0x0, + Div2 = 0x1, + Div4 = 0x2, + Div8 = 0x3, + Div16 = 0x4, + Div32 = 0x5, + Div64 = 0x6, + Div128 = 0x7, + }; + + pub const TRIGEN = enum(u2) { + /// software trigger (counting start is initiated by software) + Software = 0x0, + /// rising edge is the active edge + RisingEdge = 0x1, + /// falling edge is the active edge + FallingEdge = 0x2, + /// both edges are active edges + BothEdge = 0x3, + }; + + pub const WAVPOL = enum(u1) { + /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + Positive = 0x0, + /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + Negative = 0x1, + }; + + /// Low power timer with Output Compare + pub const LPTIM = extern struct { + /// LPTIM interrupt and status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + CCIF: u1, + /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + ARRM: u1, + /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + EXTTRIG: u1, + /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + CMPOK: u1, + /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + ARROK: u1, + /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UP: u1, + /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWN: u1, + padding: u25, }), - /// Clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// PREDIV division factor - PREDIV: packed union { - raw: u4, - value: PREDIV, - }, - /// ADC1 and ADC2 prescaler - ADC12PRES: packed union { - raw: u5, - value: ADCPRES, - }, - /// ADC3 and ADC4 prescaler - ADC34PRES: packed union { - raw: u5, - value: ADCPRES, - }, - padding: u18, + /// LPTIM interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + CCCF: u1, + /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + ARRMCF: u1, + /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + EXTTRIGCF: u1, + /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + CMPOKCF: u1, + /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + ARROKCF: u1, + /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPCF: u1, + /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNCF: u1, + padding: u25, }), - /// Clock configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SW: packed union { - raw: u2, - value: USART1SW, - }, - reserved4: u2, - /// I2C1 clock source selection - I2C1SW: packed union { - raw: u1, - value: ICSW, - }, - /// I2C2 clock source selection - I2C2SW: packed union { - raw: u1, - value: ICSW, - }, - /// HDMI CEC clock source selection - CECSW: packed union { - raw: u1, - value: CECSW, - }, - reserved8: u1, - /// Timer1 clock source selection - TIM1SW: packed union { - raw: u1, - value: TIMSW, - }, - /// Timer8 clock source selection - TIM8SW: packed union { - raw: u1, - value: TIMSW, - }, - /// Timer15 clock source selection - TIM15SW: packed union { - raw: u1, - value: TIMSW, - }, - /// Timer16 clock source selection - TIM16SW: packed union { - raw: u1, - value: TIMSW, - }, - /// Hrtim1 clock source selection - HRTIM1SW: packed union { - raw: u1, - value: TIMSW, - }, - /// Timer17 clock source selection - TIM17SW: packed union { - raw: u1, - value: TIMSW, - }, - reserved15: u1, - /// Timer20 clock source selection - TIM20SW: packed union { + /// LPTIM interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 interrupt enable. + CCIE: u1, + /// Autoreload match Interrupt Enable. + ARRMIE: u1, + /// External trigger valid edge Interrupt Enable. + EXTTRIGIE: u1, + /// Compare register 1 update OK interrupt enable. + CMPOKIE: u1, + /// Autoreload register update OK Interrupt Enable. + ARROKIE: u1, + /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPIE: u1, + /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNIE: u1, + padding: u25, + }), + /// LPTIM configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + CKSEL: packed union { raw: u1, - value: TIMSW, + value: ClockSource, }, - /// USART2 clock source selection - USART2SW: packed union { + /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. + CKPOL: packed union { raw: u2, - value: USARTSW, + value: CKPOL, }, - /// USART3 clock source selection - USART3SW: packed union { + /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + CKFLT: packed union { raw: u2, - value: USARTSW, + value: Filter, }, - /// UART4 clock source selection - UART4SW: packed union { + reserved6: u1, + /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + TRGFLT: packed union { raw: u2, - value: USARTSW, + value: Filter, }, - /// UART5 clock source selection - UART5SW: packed union { + reserved9: u1, + /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + PRESC: packed union { + raw: u3, + value: PRESC, + }, + reserved13: u1, + /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. + TRIGSEL: u3, + reserved17: u1, + /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + TRIGEN: packed union { raw: u2, - value: USARTSW, + value: TRIGEN, }, - /// Timer2 clock source selection - TIM2SW: packed union { + /// Timeout enable The TIMOUT bit controls the Timeout feature. + TIMOUT: u1, + /// Waveform shape The WAVE bit controls the output shape. + WAVE: u1, + /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. + WAVPOL: packed union { raw: u1, - value: TIM2SW, + value: WAVPOL, }, - /// Timer34 clock source selection - TIM34SW: packed union { + /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + PRELOAD: u1, + /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + COUNTMODE: packed union { raw: u1, - value: TIMSW, + value: ClockSource, }, - padding: u6, - }), - }; - }; - - pub const dbgmcu_l0 = struct { - /// Debug support - pub const DBGMCU = extern struct { - /// MCU Device ID Code Register - IDCODE: mmio.Mmio(packed struct(u32) { - /// Device Identifier - DEV_ID: u12, - reserved16: u4, - /// Revision Identifier - REV_ID: u16, + /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + ENC: u1, + padding: u7, }), - /// Debug MCU Configuration Register + /// LPTIM control register. CR: mmio.Mmio(packed struct(u32) { - /// Debug Sleep Mode - DBG_SLEEP: u1, - /// Debug Stop Mode - DBG_STOP: u1, - /// Debug Standby Mode - DBG_STANDBY: u1, + /// LPTIM enable The ENABLE bit is set and cleared by software. + ENABLE: u1, + /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + SNGSTRT: u1, + /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + CNTSTRT: u1, padding: u29, }), - /// APB Low Freeze Register - APB1FZR: mmio.Mmio(packed struct(u32) { - /// Debug Timer 2 stopped when Core is halted - TIM2: u1, - reserved4: u3, - /// Debug Timer 6 stopped when Core is halted - TIM6: u1, - reserved10: u5, - /// Debug RTC stopped when Core is halted - RTC: u1, - /// Debug Window Wachdog stopped when Core is halted - WWDG: u1, - /// Debug Independent Wachdog stopped when Core is halted - IWDG: u1, - reserved21: u8, - /// I2C1 SMBUS timeout mode stopped when core is halted - I2C1: u1, - /// I2C2 SMBUS timeout mode stopped when core is halted - I2C2: u1, - reserved31: u8, - /// LPTIM1 counter stopped when core is halted - LPTIM: u1, + /// LPTIM compare register 1. + CMP: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. + CMP: u16, + padding: u16, }), - /// APB High Freeze Register - APB2FZR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Debug Timer 21 stopped when Core is halted - TIM21: u1, - reserved6: u3, - /// Debug Timer 22 stopped when Core is halted - TIM22: u1, - padding: u25, + /// LPTIM autoreload register. + ARR: mmio.Mmio(packed struct(u32) { + /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + ARR: u16, + padding: u16, + }), + /// LPTIM counter register. + CNT: mmio.Mmio(packed struct(u32) { + /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + CNT: u16, + padding: u16, }), }; }; - pub const rcc_c0 = struct { - pub const ADCSEL = enum(u2) { - /// System clock - SYS = 0x0, - /// HSIKER - HSIKER = 0x2, + pub const lptim_v1a = struct { + pub const CKPOL = enum(u2) { + /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + Rising = 0x0, + /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + Falling = 0x1, + /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + Both = 0x2, _, }; - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK is divided by 2 - Div2 = 0x8, - /// SYSCLK is divided by 4 - Div4 = 0x9, - /// SYSCLK is divided by 8 - Div8 = 0xa, - /// SYSCLK is divided by 16 - Div16 = 0xb, - /// SYSCLK is divided by 64 - Div64 = 0xc, - /// SYSCLK is divided by 128 - Div128 = 0xd, - /// SYSCLK is divided by 256 - Div256 = 0xe, - /// SYSCLK is divided by 512 - Div512 = 0xf, - _, + pub const ClockSource = enum(u1) { + /// clocked by internal clock source (APB clock or any of the embedded oscillators) + Internal = 0x0, + /// clocked by an external clock source through the LPTIM external Input1 + External = 0x1, }; - pub const HSIDIV = enum(u3) { - /// HSI clock is not divided + pub const Filter = enum(u2) { + Count1 = 0x0, + Count2 = 0x1, + Count4 = 0x2, + Count8 = 0x3, + }; + + pub const PRESC = enum(u3) { Div1 = 0x0, - /// HSI clock is divided by 2 Div2 = 0x1, - /// HSI clock is divided by 4 Div4 = 0x2, - /// HSI clock is divided by 8 Div8 = 0x3, - /// HSI clock is divided by 16 Div16 = 0x4, - /// HSI clock is divided by 32 Div32 = 0x5, - /// HSI clock is divided by 64 Div64 = 0x6, - /// HSI clock is divided by 128 Div128 = 0x7, }; - pub const HSIKERDIV = enum(u3) { - /// 1 - Div1 = 0x0, - /// 2 - Div2 = 0x1, - /// 3 (reset value) - Div3 = 0x2, - /// 4 - Div4 = 0x3, - /// 5 - Div5 = 0x4, - /// 6 - Div6 = 0x5, - /// 7 - Div7 = 0x6, - /// 8 - Div8 = 0x7, + pub const TRIGEN = enum(u2) { + /// software trigger (counting start is initiated by software) + Software = 0x0, + /// rising edge is the active edge + RisingEdge = 0x1, + /// falling edge is the active edge + FallingEdge = 0x2, + /// both edges are active edges + BothEdge = 0x3, }; - pub const I2C1SEL = enum(u2) { - /// PCLK - PCLK1 = 0x0, - /// SYSCLK - SYS = 0x1, - /// HSIKER - HSIKER = 0x2, - _, + pub const WAVPOL = enum(u1) { + /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + Positive = 0x0, + /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + Negative = 0x1, }; - pub const I2S1SEL = enum(u2) { - /// SYSCLK - SYS = 0x0, - /// HSIKER - HSIKER = 0x2, - /// I2S_CKIN - I2S_CKIN = 0x3, + /// Low power timer with Output Compare + pub const LPTIM = extern struct { + /// LPTIM interrupt and status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + CCIF: u1, + /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + ARRM: u1, + /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + EXTTRIG: u1, + /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + CMPOK: u1, + /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + ARROK: u1, + /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UP: u1, + /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWN: u1, + padding: u25, + }), + /// LPTIM interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + CCCF: u1, + /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + ARRMCF: u1, + /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + EXTTRIGCF: u1, + /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + CMPOKCF: u1, + /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + ARROKCF: u1, + /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPCF: u1, + /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNCF: u1, + padding: u25, + }), + /// LPTIM interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 interrupt enable. + CCIE: u1, + /// Autoreload match Interrupt Enable. + ARRMIE: u1, + /// External trigger valid edge Interrupt Enable. + EXTTRIGIE: u1, + /// Compare register 1 update OK interrupt enable. + CMPOKIE: u1, + /// Autoreload register update OK Interrupt Enable. + ARROKIE: u1, + /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPIE: u1, + /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNIE: u1, + padding: u25, + }), + /// LPTIM configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + CKSEL: packed union { + raw: u1, + value: ClockSource, + }, + /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. + CKPOL: packed union { + raw: u2, + value: CKPOL, + }, + /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + CKFLT: packed union { + raw: u2, + value: Filter, + }, + reserved6: u1, + /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + TRGFLT: packed union { + raw: u2, + value: Filter, + }, + reserved9: u1, + /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + PRESC: packed union { + raw: u3, + value: PRESC, + }, + reserved13: u1, + /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. + TRIGSEL: u3, + reserved17: u1, + /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + TRIGEN: packed union { + raw: u2, + value: TRIGEN, + }, + /// Timeout enable The TIMOUT bit controls the Timeout feature. + TIMOUT: u1, + /// Waveform shape The WAVE bit controls the output shape. + WAVE: u1, + /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. + WAVPOL: packed union { + raw: u1, + value: WAVPOL, + }, + /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + PRELOAD: u1, + /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + COUNTMODE: packed union { + raw: u1, + value: ClockSource, + }, + /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + ENC: u1, + padding: u7, + }), + /// LPTIM control register. + CR: mmio.Mmio(packed struct(u32) { + /// LPTIM enable The ENABLE bit is set and cleared by software. + ENABLE: u1, + /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + SNGSTRT: u1, + /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + CNTSTRT: u1, + padding: u29, + }), + /// LPTIM compare register 1. + CMP: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. + CMP: u16, + padding: u16, + }), + /// LPTIM autoreload register. + ARR: mmio.Mmio(packed struct(u32) { + /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + ARR: u16, + padding: u16, + }), + /// LPTIM counter register. + CNT: mmio.Mmio(packed struct(u32) { + /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + CNT: u16, + padding: u16, + }), + /// LPTIM option register. + OR: u32, + }; + }; + + pub const lptim_v1b = struct { + pub const CKPOL = enum(u2) { + /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + Rising = 0x0, + /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + Falling = 0x1, + /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + Both = 0x2, _, }; - pub const LSCOSEL = enum(u1) { - /// LSI - LSI = 0x0, - /// LSE - LSE = 0x1, + pub const ClockSource = enum(u1) { + /// clocked by internal clock source (APB clock or any of the embedded oscillators) + Internal = 0x0, + /// clocked by an external clock source through the LPTIM external Input1 + External = 0x1, }; - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, + pub const Filter = enum(u2) { + Count1 = 0x0, + Count2 = 0x1, + Count4 = 0x2, + Count8 = 0x3, }; - pub const MCOPRE = enum(u4) { - /// MCO2 not divided + pub const PRESC = enum(u3) { Div1 = 0x0, - /// MCO clock is divided by 2 Div2 = 0x1, - /// MCO clock is divided by 4 Div4 = 0x2, - /// MCO clock is divided by 8 Div8 = 0x3, - /// MCO clock is divided divided by 16 Div16 = 0x4, - /// MCO clock is divided divided by 32 Div32 = 0x5, - /// MCO clock is divided divided by 64 Div64 = 0x6, - /// MCO clock is divided divided by 128 Div128 = 0x7, - _, - }; - - pub const MCOSEL = enum(u4) { - /// No clock, MCO output disabled - DISABLE = 0x0, - /// SYSCLK selected as MCO source - SYS = 0x1, - /// HSI selected as MCO source - HSI = 0x3, - /// HSE selected as MCO source - HSE = 0x4, - /// LSI selected as MCO source - LSI = 0x6, - /// LSE selected as MCO source - LSE = 0x7, - _, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK is divided by 2 - Div2 = 0x4, - /// HCLK is divided by 4 - Div4 = 0x5, - /// HCLK is divided by 8 - Div8 = 0x6, - /// HCLK is divided by 16 - Div16 = 0x7, - _, }; - pub const RTCSEL = enum(u2) { - /// No clock used as RTC clock - DISABLE = 0x0, - /// LSE used as RTC clock - LSE = 0x1, - /// LSI used as RTC clock - LSI = 0x2, - /// HSE divided by 32 used as RTC clock - HSE_Div32 = 0x3, + pub const TRIGEN = enum(u2) { + /// software trigger (counting start is initiated by software) + Software = 0x0, + /// rising edge is the active edge + RisingEdge = 0x1, + /// falling edge is the active edge + FallingEdge = 0x2, + /// both edges are active edges + BothEdge = 0x3, }; - pub const SW = enum(u3) { - /// HSISYS (HSI divided by HSIDIV) selected as system clock - HSISYS = 0x0, - /// HSE selected as system clock - HSE = 0x1, - /// LSI selected as system clock - LSI = 0x3, - /// LSE selected as system clock - LSE = 0x4, - _, + pub const WAVPOL = enum(u1) { + /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + Positive = 0x0, + /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + Negative = 0x1, }; - pub const USART1SEL = enum(u2) { - /// PCLK - PCLK1 = 0x0, - /// SYSCLK - SYS = 0x1, - /// HSIKER - HSIKER = 0x2, - /// LSE - LSE = 0x3, - }; - - /// RCC address block description - pub const RCC = extern struct { - /// RCC clock control register - CR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// HSI kernel clock division factor This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock: - HSIKERDIV: packed union { - raw: u3, - value: HSIKERDIV, - }, - /// HSI clock enable Set and cleared by software and hardware, with hardware taking priority. Kept low by hardware as long as the device is in a low-power mode. Kept high by hardware as long as the system is clocked with a clock derived from HSI. This includes the exit from low-power modes and the system clock fall-back to HSI upon failing HSE oscillator clock selected as system clock source. - HSION: u1, - /// HSI always-enable for peripheral kernels. Set and cleared by software. Setting the bit activates the HSI oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI as kernel clock. Note: Keeping the HSI active in Stop mode allows speeding up the serial interface communication as the HSI clock is ready immediately upon exiting Stop mode. - HSIKERON: u1, - /// HSI clock ready flag Set by hardware when the HSI oscillator is enabled through HSION and ready to use (stable). Note: Upon clearing HSION, HSIRDY goes low after six HSI clock cycles. - HSIRDY: u1, - /// HSI clock division factor This bitfield controlled by software sets the division factor of the HSI clock divider to produce HSISYS clock: - HSIDIV: packed union { - raw: u3, - value: HSIDIV, - }, - reserved16: u2, - /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock. - HSEON: u1, - /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable and ready for use. Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles. - HSERDY: u1, - /// HSE crystal oscillator bypass Set and cleared by software. When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled. - HSEBYP: u1, - /// Clock security system enable Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset. - CSSON: u1, - padding: u12, + /// Low power timer with Output Compare + pub const LPTIM = extern struct { + /// LPTIM interrupt and status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + CCIF: u1, + /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + ARRM: u1, + /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + EXTTRIG: u1, + /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + CMPOK: u1, + /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + ARROK: u1, + /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UP: u1, + /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWN: u1, + padding: u25, }), - /// RCC internal clock source calibration register - ICSCR: mmio.Mmio(packed struct(u32) { - /// HSI clock calibration This bitfield directly acts on the HSI clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI calibration accuracy and for the frequency trimming granularity. Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64. - HSICAL: u8, - /// HSI clock trimming The value of this bitfield contributes to the HSICAL[7:0] bitfield value. It allows HSI clock frequency user trimming. The HSI frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value. - HSITRIM: u7, - padding: u17, + /// LPTIM interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + CCCF: u1, + /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + ARRMCF: u1, + /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + EXTTRIGCF: u1, + /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + CMPOKCF: u1, + /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + ARROKCF: u1, + /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPCF: u1, + /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNCF: u1, + padding: u25, }), - /// RCC clock configuration register + /// LPTIM interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 interrupt enable. + CCIE: u1, + /// Autoreload match Interrupt Enable. + ARRMIE: u1, + /// External trigger valid edge Interrupt Enable. + EXTTRIGIE: u1, + /// Compare register 1 update OK interrupt enable. + CMPOKIE: u1, + /// Autoreload register update OK Interrupt Enable. + ARROKIE: u1, + /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPIE: u1, + /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNIE: u1, + padding: u25, + }), + /// LPTIM configuration register. CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected. - SW: packed union { - raw: u3, - value: SW, + /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + CKSEL: packed union { + raw: u1, + value: ClockSource, }, - /// System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved - SWS: packed union { - raw: u3, - value: SW, + /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. + CKPOL: packed union { + raw: u2, + value: CKPOL, }, - reserved8: u2, - /// AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1 - HPRE: packed union { - raw: u4, - value: HPRE, + /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + CKFLT: packed union { + raw: u2, + value: Filter, }, - /// APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1 - PPRE: packed union { - raw: u3, - value: PPRE, + reserved6: u1, + /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + TRGFLT: packed union { + raw: u2, + value: Filter, }, - reserved16: u1, - /// Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching. - MCO2SEL: packed union { - raw: u4, - value: MCOSEL, + reserved9: u1, + /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + PRESC: packed union { + raw: u3, + value: PRESC, }, - /// Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: ... It is highly recommended to set this field before the MCO2 output is enabled. - MCO2PRE: packed union { - raw: u4, - value: MCOPRE, + reserved13: u1, + /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. + TRIGSEL: u3, + reserved17: u1, + /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + TRIGEN: packed union { + raw: u2, + value: TRIGEN, }, - /// Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO. - MCO1SEL: packed union { - raw: u4, - value: MCOSEL, + /// Timeout enable The TIMOUT bit controls the Timeout feature. + TIMOUT: u1, + /// Waveform shape The WAVE bit controls the output shape. + WAVE: u1, + /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. + WAVPOL: packed union { + raw: u1, + value: WAVPOL, }, - /// Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: ... It is highly recommended to set this field before the MCO output is enabled. - MCO1PRE: packed union { - raw: u4, - value: MCOPRE, + /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + PRELOAD: u1, + /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + COUNTMODE: packed union { + raw: u1, + value: ClockSource, }, + /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + ENC: u1, + padding: u7, }), - reserved24: [12]u8, - /// RCC clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization: - LSIRDYIE: u1, - /// LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization: - LSERDYIE: u1, - reserved3: u1, - /// HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization: - HSIRDYIE: u1, - /// HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization: - HSERDYIE: u1, + /// LPTIM control register. + CR: mmio.Mmio(packed struct(u32) { + /// LPTIM enable The ENABLE bit is set and cleared by software. + ENABLE: u1, + /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + SNGSTRT: u1, + /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + CNTSTRT: u1, + /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + COUNTRST: u1, + /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + RSTARE: u1, padding: u27, }), - /// RCC clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. - LSIRDYF: u1, - /// LSE ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. - LSERDYF: u1, - reserved3: u1, - /// HSI ready interrupt flag This flag indicates a pending interrupt upon HSI clock getting ready. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. - HSIRDYF: u1, - /// HSE ready interrupt flag This flag indicates a pending interrupt upon HSE clock getting ready. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit. - HSERDYF: u1, - reserved8: u3, - /// HSE clock security system interrupt flag This flag indicates a pending interrupt upon HSE clock failure. Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. - CSSF: u1, - /// LSE clock security system interrupt flag This flag indicates a pending interrupt upon LSE clock failure. Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit. - LSECSSF: u1, - padding: u22, + /// LPTIM compare register 1. + CMP: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. + CMP: u16, + padding: u16, }), - /// RCC clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. - LSIRDYC: u1, - /// LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. - LSERDYC: u1, - reserved3: u1, - /// HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag. - HSIRDYC: u1, - /// HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. - HSERDYC: u1, - reserved8: u3, - /// Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag. - CSSC: u1, - /// LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag. - LSECSSC: u1, - padding: u22, + /// LPTIM autoreload register. + ARR: mmio.Mmio(packed struct(u32) { + /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + ARR: u16, + padding: u16, }), - /// RCC I/O port reset register - GPIORSTR: mmio.Mmio(packed struct(u32) { - /// I/O port A reset This bit is set and cleared by software. - GPIOARST: u1, - /// I/O port B reset This bit is set and cleared by software. - GPIOBRST: u1, - /// I/O port C reset This bit is set and cleared by software. - GPIOCRST: u1, - /// I/O port D reset This bit is set and cleared by software. - GPIODRST: u1, - reserved5: u1, - /// I/O port F reset This bit is set and cleared by software. - GPIOFRST: u1, - padding: u26, + /// LPTIM counter register. + CNT: mmio.Mmio(packed struct(u32) { + /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + CNT: u16, + padding: u16, }), - /// RCC AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 and DMAMUX reset Set and cleared by software. - DMA1RST: u1, - reserved8: u7, - /// Flash memory interface reset Set and cleared by software. This bit can only be set when the Flash memory is in power down mode. - FLASHRST: u1, - reserved12: u3, - /// CRC reset Set and cleared by software. - CRCRST: u1, - padding: u19, + /// LPTIM option register. + OR: u32, + }; + }; + + pub const lptim_v1b_g4 = struct { + pub const CKPOL = enum(u2) { + /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + Rising = 0x0, + /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + Falling = 0x1, + /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + Both = 0x2, + _, + }; + + pub const ClockSource = enum(u1) { + /// clocked by internal clock source (APB clock or any of the embedded oscillators) + Internal = 0x0, + /// clocked by an external clock source through the LPTIM external Input1 + External = 0x1, + }; + + pub const Filter = enum(u2) { + Count1 = 0x0, + Count2 = 0x1, + Count4 = 0x2, + Count8 = 0x3, + }; + + pub const PRESC = enum(u3) { + Div1 = 0x0, + Div2 = 0x1, + Div4 = 0x2, + Div8 = 0x3, + Div16 = 0x4, + Div32 = 0x5, + Div64 = 0x6, + Div128 = 0x7, + }; + + pub const TRIGEN = enum(u2) { + /// software trigger (counting start is initiated by software) + Software = 0x0, + /// rising edge is the active edge + RisingEdge = 0x1, + /// falling edge is the active edge + FallingEdge = 0x2, + /// both edges are active edges + BothEdge = 0x3, + }; + + pub const WAVPOL = enum(u1) { + /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + Positive = 0x0, + /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + Negative = 0x1, + }; + + /// Low power timer with Output Compare + pub const LPTIM = extern struct { + /// LPTIM interrupt and status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + CCIF: u1, + /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + ARRM: u1, + /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + EXTTRIG: u1, + /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + CMPOK: u1, + /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + ARROK: u1, + /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UP: u1, + /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWN: u1, + padding: u25, }), - /// RCC APB peripheral reset register 1 - APBRSTR1: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// TIM3 timer reset Set and cleared by software. - TIM3RST: u1, - reserved17: u15, - /// USART2 reset Set and cleared by software. - USART2RST: u1, - reserved21: u3, - /// I2C1 reset Set and cleared by software. - I2C1RST: u1, - reserved27: u5, - /// Debug support reset Set and cleared by software. - DBGRST: u1, - /// Power interface reset Set and cleared by software. - PWRRST: u1, - padding: u3, + /// LPTIM interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + CCCF: u1, + /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + ARRMCF: u1, + /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + EXTTRIGCF: u1, + /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + CMPOKCF: u1, + /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + ARROKCF: u1, + /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPCF: u1, + /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNCF: u1, + padding: u25, }), - /// RCC APB peripheral reset register 2 - APBRSTR2: mmio.Mmio(packed struct(u32) { - /// SYSCFG reset Set and cleared by software. - SYSCFGRST: u1, - reserved11: u10, - /// TIM1 timer reset Set and cleared by software. - TIM1RST: u1, - /// SPI1 reset Set and cleared by software. - SPI1RST: u1, - reserved14: u1, - /// USART1 reset Set and cleared by software. - USART1RST: u1, - /// TIM14 timer reset Set and cleared by software. - TIM14RST: u1, - reserved17: u1, - /// TIM16 timer reset Set and cleared by software. - TIM16RST: u1, - /// TIM16 timer reset Set and cleared by software. - TIM17RST: u1, - reserved20: u1, - /// ADC reset Set and cleared by software. - ADCRST: u1, - padding: u11, + /// LPTIM interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 interrupt enable. + CCIE: u1, + /// Autoreload match Interrupt Enable. + ARRMIE: u1, + /// External trigger valid edge Interrupt Enable. + EXTTRIGIE: u1, + /// Compare register 1 update OK interrupt enable. + CMPOKIE: u1, + /// Autoreload register update OK Interrupt Enable. + ARROKIE: u1, + /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPIE: u1, + /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNIE: u1, + padding: u25, }), - /// RCC I/O port clock enable register - GPIOENR: mmio.Mmio(packed struct(u32) { - /// I/O port A clock enable This bit is set and cleared by software. - GPIOAEN: u1, - /// I/O port B clock enable This bit is set and cleared by software. - GPIOBEN: u1, - /// I/O port C clock enable This bit is set and cleared by software. - GPIOCEN: u1, - /// I/O port D clock enable This bit is set and cleared by software. - GPIODEN: u1, - reserved5: u1, - /// I/O port F clock enable This bit is set and cleared by software. - GPIOFEN: u1, - padding: u26, + /// LPTIM configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + CKSEL: packed union { + raw: u1, + value: ClockSource, + }, + /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. + CKPOL: packed union { + raw: u2, + value: CKPOL, + }, + /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + CKFLT: packed union { + raw: u2, + value: Filter, + }, + reserved6: u1, + /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + TRGFLT: packed union { + raw: u2, + value: Filter, + }, + reserved9: u1, + /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + PRESC: packed union { + raw: u3, + value: PRESC, + }, + padding: u20, }), - /// RCC AHB peripheral clock enable register - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled. - DMA1EN: u1, - reserved8: u7, - /// Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the Flash memory is in power down mode. - FLASHEN: u1, - reserved12: u3, - /// CRC clock enable Set and cleared by software. - CRCEN: u1, - padding: u19, + /// LPTIM control register. + CR: mmio.Mmio(packed struct(u32) { + /// LPTIM enable The ENABLE bit is set and cleared by software. + ENABLE: u1, + /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + SNGSTRT: u1, + /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + CNTSTRT: u1, + /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + COUNTRST: u1, + /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + RSTARE: u1, + padding: u27, }), - /// RCC APB peripheral clock enable register 1 - APBENR1: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// TIM3 timer clock enable Set and cleared by software. - TIM3EN: u1, - reserved10: u8, - /// RTC APB clock enable Set and cleared by software. - RTCAPBEN: u1, - /// WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0. - WWDGEN: u1, - reserved17: u5, - /// USART2 clock enable Set and cleared by software. - USART2EN: u1, - reserved21: u3, - /// I2C1 clock enable Set and cleared by software. - I2C1EN: u1, - reserved27: u5, - /// Debug support clock enable Set and cleared by software. - DBGEN: u1, - /// Power interface clock enable Set and cleared by software. - PWREN: u1, - padding: u3, + /// LPTIM compare register 1. + CMP: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. + CMP: u16, + padding: u16, }), - /// RCC APB peripheral clock enable register 2 - APBENR2: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable Set and cleared by software. - SYSCFGEN: u1, - reserved11: u10, - /// TIM1 timer clock enable Set and cleared by software. - TIM1EN: u1, - /// SPI1 clock enable Set and cleared by software. - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable Set and cleared by software. - USART1EN: u1, - /// TIM14 timer clock enable Set and cleared by software. - TIM14EN: u1, - reserved17: u1, - /// TIM16 timer clock enable Set and cleared by software. - TIM16EN: u1, - /// TIM16 timer clock enable Set and cleared by software. - TIM17EN: u1, - reserved20: u1, - /// ADC clock enable Set and cleared by software. - ADCEN: u1, - padding: u11, + /// LPTIM autoreload register. + ARR: mmio.Mmio(packed struct(u32) { + /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + ARR: u16, + padding: u16, }), - /// RCC I/O port in Sleep mode clock enable register - GPIOSMENR: mmio.Mmio(packed struct(u32) { - /// I/O port A clock enable during Sleep mode Set and cleared by software. - GPIOASMEN: u1, - /// I/O port B clock enable during Sleep mode Set and cleared by software. - GPIOBSMEN: u1, - /// I/O port C clock enable during Sleep mode Set and cleared by software. - GPIOCSMEN: u1, - /// I/O port D clock enable during Sleep mode Set and cleared by software. - GPIODSMEN: u1, - reserved5: u1, - /// I/O port F clock enable during Sleep mode Set and cleared by software. - GPIOFSMEN: u1, - padding: u26, + /// LPTIM counter register. + CNT: mmio.Mmio(packed struct(u32) { + /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + CNT: u16, + padding: u16, }), - /// RCC AHB peripheral clock enable in Sleep/Stop mode register - AHBSMENR: mmio.Mmio(packed struct(u32) { - /// DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. - DMA1SMEN: u1, - reserved8: u7, - /// Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode. - FLASHSMEN: u1, - /// SRAM clock enable during Sleep mode Set and cleared by software. - SRAMSMEN: u1, - reserved12: u2, - /// CRC clock enable during Sleep mode Set and cleared by software. - CRCSMEN: u1, - padding: u19, + /// LPTIM option register. + OR: u32, + }; + }; + + pub const lptim_v1b_h7 = struct { + pub const CKPOL = enum(u2) { + /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + Rising = 0x0, + /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + Falling = 0x1, + /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + Both = 0x2, + _, + }; + + pub const ClockSource = enum(u1) { + /// clocked by internal clock source (APB clock or any of the embedded oscillators) + Internal = 0x0, + /// clocked by an external clock source through the LPTIM external Input1 + External = 0x1, + }; + + pub const Filter = enum(u2) { + Count1 = 0x0, + Count2 = 0x1, + Count4 = 0x2, + Count8 = 0x3, + }; + + pub const PRESC = enum(u3) { + Div1 = 0x0, + Div2 = 0x1, + Div4 = 0x2, + Div8 = 0x3, + Div16 = 0x4, + Div32 = 0x5, + Div64 = 0x6, + Div128 = 0x7, + }; + + pub const TRIGEN = enum(u2) { + /// software trigger (counting start is initiated by software) + Software = 0x0, + /// rising edge is the active edge + RisingEdge = 0x1, + /// falling edge is the active edge + FallingEdge = 0x2, + /// both edges are active edges + BothEdge = 0x3, + }; + + pub const WAVPOL = enum(u1) { + /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + Positive = 0x0, + /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + Negative = 0x1, + }; + + /// Low power timer with Output Compare + pub const LPTIM = extern struct { + /// LPTIM interrupt and status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + CCIF: u1, + /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + ARRM: u1, + /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + EXTTRIG: u1, + /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + CMPOK: u1, + /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + ARROK: u1, + /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UP: u1, + /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWN: u1, + padding: u25, }), - /// RCC APB peripheral clock enable in Sleep/Stop mode register 1 - APBSMENR1: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// TIM3 timer clock enable during Sleep mode Set and cleared by software. - TIM3SMEN: u1, - reserved10: u8, - /// RTC APB clock enable during Sleep mode Set and cleared by software. - RTCAPBSMEN: u1, - /// WWDG clock enable during Sleep and Stop modes Set and cleared by software. - WWDGSMEN: u1, - reserved17: u5, - /// USART2 clock enable during Sleep and Stop modes Set and cleared by software. - USART2SMEN: u1, - reserved21: u3, - /// I2C1 clock enable during Sleep and Stop modes Set and cleared by software. - I2C1SMEN: u1, - reserved27: u5, - /// Debug support clock enable during Sleep mode Set and cleared by software. - DBGSMEN: u1, - /// Power interface clock enable during Sleep mode Set and cleared by software. - PWRSMEN: u1, - padding: u3, + /// LPTIM interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + CCCF: u1, + /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + ARRMCF: u1, + /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + EXTTRIGCF: u1, + /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + CMPOKCF: u1, + /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + ARROKCF: u1, + /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPCF: u1, + /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNCF: u1, + padding: u25, }), - /// RCC APB peripheral clock enable in Sleep/Stop mode register 2 - APBSMENR2: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable during Sleep and Stop modes Set and cleared by software. - SYSCFGSMEN: u1, - reserved11: u10, - /// TIM1 timer clock enable during Sleep mode Set and cleared by software. - TIM1SMEN: u1, - /// SPI1 clock enable during Sleep mode Set and cleared by software. - SPI1SMEN: u1, - reserved14: u1, - /// USART1 clock enable during Sleep and Stop modes Set and cleared by software. - USART1SMEN: u1, - /// TIM14 timer clock enable during Sleep mode Set and cleared by software. - TIM14SMEN: u1, - reserved17: u1, - /// TIM16 timer clock enable during Sleep mode Set and cleared by software. - TIM16SMEN: u1, - /// TIM16 timer clock enable during Sleep mode Set and cleared by software. - TIM17SMEN: u1, - reserved20: u1, - /// ADC clock enable during Sleep mode Set and cleared by software. - ADCSMEN: u1, - padding: u11, + /// LPTIM interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 interrupt enable. + CCIE: u1, + /// Autoreload match Interrupt Enable. + ARRMIE: u1, + /// External trigger valid edge Interrupt Enable. + EXTTRIGIE: u1, + /// Compare register 1 update OK interrupt enable. + CMPOKIE: u1, + /// Autoreload register update OK Interrupt Enable. + ARROKIE: u1, + /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPIE: u1, + /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNIE: u1, + padding: u25, }), - /// RCC peripherals independent clock configuration register - CCIPR: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows: - USART1SEL: packed union { - raw: u2, - value: USART1SEL, + /// LPTIM configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + CKSEL: packed union { + raw: u1, + value: ClockSource, }, - reserved12: u10, - /// I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows: - I2C1SEL: packed union { + /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. + CKPOL: packed union { raw: u2, - value: I2C1SEL, + value: CKPOL, }, - /// I2S1 clock source selection This bitfield is controlled by software to select I2S1 clock source as follows: - I2S1SEL: packed union { + /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + CKFLT: packed union { raw: u2, - value: I2S1SEL, + value: Filter, }, - reserved30: u14, - /// ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC: - ADCSEL: packed union { + reserved6: u1, + /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + TRGFLT: packed union { raw: u2, - value: ADCSEL, + value: Filter, }, - }), - reserved92: [4]u8, - /// RCC control/status register 1 - CSR1: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enable Set and cleared by software to enable LSE oscillator: - LSEON: u1, - /// LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. - LSERDY: u1, - /// LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). - LSEBYP: u1, - /// LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode. - LSEDRV: packed union { - raw: u2, - value: LSEDRV, + reserved9: u1, + /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + PRESC: packed union { + raw: u3, + value: PRESC, }, - /// CSS on LSE enable Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit. - LSECSSON: u1, - /// CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 32 kHz oscillator (LSE): - LSECSSD: u1, - reserved8: u1, - /// RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00. - RTCSEL: packed union { + reserved13: u1, + /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. + TRIGSEL: u3, + reserved17: u1, + /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + TRIGEN: packed union { raw: u2, - value: RTCSEL, + value: TRIGEN, }, - reserved15: u5, - /// RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP. - RTCEN: u1, - /// RTC domain software reset Set and cleared by software to reset the RTC domain: - RTCRST: u1, - reserved24: u7, - /// Low-speed clock output (LSCO) enable Set and cleared by software. - LSCOEN: u1, - /// Low-speed clock output selection Set and cleared by software to select the low-speed output clock: - LSCOSEL: packed union { + /// Timeout enable The TIMOUT bit controls the Timeout feature. + TIMOUT: u1, + /// Waveform shape The WAVE bit controls the output shape. + WAVE: u1, + /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. + WAVPOL: packed union { raw: u1, - value: LSCOSEL, + value: WAVPOL, }, - padding: u6, + /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + PRELOAD: u1, + /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + COUNTMODE: packed union { + raw: u1, + value: ClockSource, + }, + /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + ENC: u1, + padding: u7, }), - /// RCC control/status register 2 - CSR2: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable Set and cleared by software to enable/disable the LSI oscillator: - LSION: u1, - /// LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. - LSIRDY: u1, - reserved23: u21, - /// Remove reset flags Set by software to clear the reset flags. - RMVF: u1, - reserved25: u1, - /// Option byte loader reset flag Set by hardware when a reset from the Option byte loading occurs. Cleared by setting the RMVF bit. - OBLRSTF: u1, - /// Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by setting the RMVF bit. - PINRSTF: u1, - /// BOR or POR/PDR flag Set by hardware when a BOR or POR/PDR occurs. Cleared by setting the RMVF bit. - PWRRSTF: u1, - /// Software reset flag Set by hardware when a software reset occurs. Cleared by setting the RMVF bit. - SFTRSTF: u1, - /// Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by setting the RMVF bit. - IWDGRSTF: u1, - /// Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by setting the RMVF bit. - WWDGRSTF: u1, - /// Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared. - LPWRRSTF: u1, + /// LPTIM control register. + CR: mmio.Mmio(packed struct(u32) { + /// LPTIM enable The ENABLE bit is set and cleared by software. + ENABLE: u1, + /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + SNGSTRT: u1, + /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + CNTSTRT: u1, + /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + COUNTRST: u1, + /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + RSTARE: u1, + padding: u27, + }), + /// LPTIM compare register 1. + CMP: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. + CMP: u16, + padding: u16, + }), + /// LPTIM autoreload register. + ARR: mmio.Mmio(packed struct(u32) { + /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + ARR: u16, + padding: u16, + }), + /// LPTIM counter register. + CNT: mmio.Mmio(packed struct(u32) { + /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + CNT: u16, + padding: u16, + }), + reserved36: [4]u8, + /// LPTIM configuration register 2. + CFGR2: mmio.Mmio(packed struct(u32) { + /// LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + INSEL: u2, + padding: u30, }), }; }; - pub const timer_l0 = struct { - pub const CCDS = enum(u1) { - /// CCx DMA request sent when CCx event occurs - OnCompare = 0x0, - /// CCx DMA request sent when update event occurs - OnUpdate = 0x1, + pub const lptim_v1c = struct { + pub const CKPOL = enum(u2) { + /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + Rising = 0x0, + /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + Falling = 0x1, + /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + Both = 0x2, + _, }; - pub const CCMR_Input_CCS = enum(u2) { - /// CCx channel is configured as input, normal mapping: ICx mapped to TIx - TI4 = 0x1, - /// CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) - TI3 = 0x2, - /// CCx channel is configured as input, ICx is mapped on TRC - TRC = 0x3, - _, + pub const ClockSource = enum(u1) { + /// clocked by internal clock source (APB clock or any of the embedded oscillators) + Internal = 0x0, + /// clocked by an external clock source through the LPTIM external Input1 + External = 0x1, }; - pub const CCMR_Output_CCS = enum(u2) { - /// CCx channel is configured as output - Output = 0x0, - _, + pub const Filter = enum(u2) { + Count1 = 0x0, + Count2 = 0x1, + Count4 = 0x2, + Count8 = 0x3, }; - pub const CKD = enum(u2) { - /// t_DTS = t_CK_INT + pub const PRESC = enum(u3) { Div1 = 0x0, - /// t_DTS = 2 × t_CK_INT Div2 = 0x1, - /// t_DTS = 4 × t_CK_INT Div4 = 0x2, - _, - }; - - pub const CMS = enum(u2) { - /// The counter counts up or down depending on the direction bit - EdgeAligned = 0x0, - /// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. - CenterAligned1 = 0x1, - /// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. - CenterAligned2 = 0x2, - /// The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. - CenterAligned3 = 0x3, - }; - - pub const DIR = enum(u1) { - /// Counter used as upcounter - Up = 0x0, - /// Counter used as downcounter - Down = 0x1, + Div8 = 0x3, + Div16 = 0x4, + Div32 = 0x5, + Div64 = 0x6, + Div128 = 0x7, }; - pub const ETP = enum(u1) { - /// ETR is noninverted, active at high level or rising edge - NotInverted = 0x0, - /// ETR is inverted, active at low level or falling edge - Inverted = 0x1, + pub const TRIGEN = enum(u2) { + /// software trigger (counting start is initiated by software) + Software = 0x0, + /// rising edge is the active edge + RisingEdge = 0x1, + /// falling edge is the active edge + FallingEdge = 0x2, + /// both edges are active edges + BothEdge = 0x3, }; - pub const ETPS = enum(u2) { - /// Prescaler OFF - Div1 = 0x0, - /// ETRP frequency divided by 2 - Div2 = 0x1, - /// ETRP frequency divided by 4 - Div4 = 0x2, - /// ETRP frequency divided by 8 - Div8 = 0x3, + pub const WAVPOL = enum(u1) { + /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + Positive = 0x0, + /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + Negative = 0x1, }; - pub const FilterValue = enum(u4) { - /// No filter, sampling is done at fDTS - NoFilter = 0x0, - /// fSAMPLING=fCK_INT, N=2 - FCK_INT_N2 = 0x1, - /// fSAMPLING=fCK_INT, N=4 - FCK_INT_N4 = 0x2, - /// fSAMPLING=fCK_INT, N=8 - FCK_INT_N8 = 0x3, - /// fSAMPLING=fDTS/2, N=6 - FDTS_Div2_N6 = 0x4, - /// fSAMPLING=fDTS/2, N=8 - FDTS_Div2_N8 = 0x5, - /// fSAMPLING=fDTS/4, N=6 - FDTS_Div4_N6 = 0x6, - /// fSAMPLING=fDTS/4, N=8 - FDTS_Div4_N8 = 0x7, - /// fSAMPLING=fDTS/8, N=6 - FDTS_Div8_N6 = 0x8, - /// fSAMPLING=fDTS/8, N=8 - FDTS_Div8_N8 = 0x9, - /// fSAMPLING=fDTS/16, N=5 - FDTS_Div16_N5 = 0xa, - /// fSAMPLING=fDTS/16, N=6 - FDTS_Div16_N6 = 0xb, - /// fSAMPLING=fDTS/16, N=8 - FDTS_Div16_N8 = 0xc, - /// fSAMPLING=fDTS/32, N=5 - FDTS_Div32_N5 = 0xd, - /// fSAMPLING=fDTS/32, N=6 - FDTS_Div32_N6 = 0xe, - /// fSAMPLING=fDTS/32, N=8 - FDTS_Div32_N8 = 0xf, + /// Low power timer with Output Compare + pub const LPTIM = extern struct { + /// LPTIM interrupt and status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + CCIF: u1, + /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + ARRM: u1, + /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + EXTTRIG: u1, + /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + CMPOK: u1, + /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + ARROK: u1, + /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UP: u1, + /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWN: u1, + /// LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + UE: u1, + /// Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + REPOK: u1, + padding: u23, + }), + /// LPTIM interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + CCCF: u1, + /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + ARRMCF: u1, + /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + EXTTRIGCF: u1, + /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + CMPOKCF: u1, + /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + ARROKCF: u1, + /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPCF: u1, + /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNCF: u1, + /// Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + UECF: u1, + /// Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + REPOKCF: u1, + padding: u23, + }), + /// LPTIM interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 interrupt enable. + CCIE: u1, + /// Autoreload match Interrupt Enable. + ARRMIE: u1, + /// External trigger valid edge Interrupt Enable. + EXTTRIGIE: u1, + /// Compare register 1 update OK interrupt enable. + CMPOKIE: u1, + /// Autoreload register update OK Interrupt Enable. + ARROKIE: u1, + /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPIE: u1, + /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNIE: u1, + /// Update event interrupt enable. + UEIE: u1, + /// Repetition register update OK interrupt Enable. + REPOKIE: u1, + padding: u23, + }), + /// LPTIM configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + CKSEL: packed union { + raw: u1, + value: ClockSource, + }, + /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. + CKPOL: packed union { + raw: u2, + value: CKPOL, + }, + /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + CKFLT: packed union { + raw: u2, + value: Filter, + }, + reserved6: u1, + /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + TRGFLT: packed union { + raw: u2, + value: Filter, + }, + reserved9: u1, + /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + PRESC: packed union { + raw: u3, + value: PRESC, + }, + reserved13: u1, + /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. + TRIGSEL: u3, + reserved17: u1, + /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + TRIGEN: packed union { + raw: u2, + value: TRIGEN, + }, + /// Timeout enable The TIMOUT bit controls the Timeout feature. + TIMOUT: u1, + /// Waveform shape The WAVE bit controls the output shape. + WAVE: u1, + /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. + WAVPOL: packed union { + raw: u1, + value: WAVPOL, + }, + /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + PRELOAD: u1, + /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + COUNTMODE: packed union { + raw: u1, + value: ClockSource, + }, + /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + ENC: u1, + padding: u7, + }), + /// LPTIM control register. + CR: mmio.Mmio(packed struct(u32) { + /// LPTIM enable The ENABLE bit is set and cleared by software. + ENABLE: u1, + /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + SNGSTRT: u1, + /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + CNTSTRT: u1, + /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + COUNTRST: u1, + /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + RSTARE: u1, + padding: u27, + }), + /// LPTIM compare register 1. + CMP: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. + CMP: u16, + padding: u16, + }), + /// LPTIM autoreload register. + ARR: mmio.Mmio(packed struct(u32) { + /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + ARR: u16, + padding: u16, + }), + /// LPTIM counter register. + CNT: mmio.Mmio(packed struct(u32) { + /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + CNT: u16, + padding: u16, + }), + /// LPTIM option register. + OR: u32, + reserved40: [4]u8, + /// LPTIM repetition register. + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition register value REP is the repetition value for the LPTIM. + REP: u8, + padding: u24, + }), }; + }; - pub const MMS = enum(u3) { - /// The UG bit from the TIMx_EGR register is used as trigger output - Reset = 0x0, - /// The counter enable signal, CNT_EN, is used as trigger output - Enable = 0x1, - /// The update event is selected as trigger output - Update = 0x2, - /// The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - ComparePulse = 0x3, - /// OC1REF signal is used as trigger output - CompareOC1 = 0x4, - /// OC2REF signal is used as trigger output - CompareOC2 = 0x5, - /// OC3REF signal is used as trigger output - CompareOC3 = 0x6, - /// OC4REF signal is used as trigger output - CompareOC4 = 0x7, + pub const lptim_v2a = struct { + pub const CCP_Input = enum(u2) { + Rising = 0x0, + Falling = 0x1, + Both = 0x3, + _, }; - pub const MSM = enum(u1) { - /// No action - NoSync = 0x0, - /// The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - Sync = 0x1, + pub const CCP_Output = enum(u2) { + ActiveHigh = 0x0, + ActiveLow = 0x1, + _, }; - pub const OCM = enum(u3) { - /// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs - Frozen = 0x0, - /// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register - ActiveOnMatch = 0x1, - /// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register - InactiveOnMatch = 0x2, - /// OCyREF toggles when TIMx_CNT=TIMx_CCRy - Toggle = 0x3, - /// OCyREF is forced low - ForceInactive = 0x4, - /// OCyREF is forced high - ForceActive = 0x5, - /// In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active - PwmMode1 = 0x6, - /// Inversely to PwmMode1 - PwmMode2 = 0x7, + pub const CCSEL = enum(u1) { + /// channel is configured in output PWM mode + OutputCompare = 0x0, + /// channel is configured in input capture mode + InputCapture = 0x1, }; - pub const SMS = enum(u3) { - /// Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock. - Disabled = 0x0, - /// Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - Encoder_Mode_1 = 0x1, - /// Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - Encoder_Mode_2 = 0x2, - /// Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - Encoder_Mode_3 = 0x3, - /// Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - Reset_Mode = 0x4, - /// Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - Gated_Mode = 0x5, - /// Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - Trigger_Mode = 0x6, - /// External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - Ext_Clock_Mode = 0x7, + pub const CKPOL = enum(u2) { + /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + Rising = 0x0, + /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + Falling = 0x1, + /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + Both = 0x2, + _, }; - pub const TI1S = enum(u1) { - /// The TIMx_CH1 pin is connected to TI1 input - Normal = 0x0, - /// The TIMx_CH1, CH2, CH3 pins are connected to TI1 input - XOR = 0x1, + pub const ClockSource = enum(u1) { + /// clocked by internal clock source (APB clock or any of the embedded oscillators) + Internal = 0x0, + /// clocked by an external clock source through the LPTIM external Input1 + External = 0x1, }; - pub const TS = enum(u3) { - /// Internal Trigger 0 (ITR0) - ITR0 = 0x0, - /// Internal Trigger 1 (ITR1) - ITR1 = 0x1, - /// Internal Trigger 2 (ITR2) - ITR2 = 0x2, - /// Internal Trigger 3 (ITR3) - ITR3 = 0x3, - /// TI1 Edge Detector (TI1F_ED) - TI1F_ED = 0x4, - /// Filtered Timer Input 1 (TI1FP1) - TI1FP1 = 0x5, - /// Filtered Timer Input 2 (TI2FP2) - TI2FP2 = 0x6, - /// External Trigger input (ETRF) - ETRF = 0x7, + pub const Filter = enum(u2) { + Count1 = 0x0, + Count2 = 0x1, + Count4 = 0x2, + Count8 = 0x3, }; - pub const URS = enum(u1) { - /// Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - AnyEvent = 0x0, - /// Only counter overflow/underflow generates an update interrupt or DMA request - CounterOnly = 0x1, + pub const PRESC = enum(u3) { + Div1 = 0x0, + Div2 = 0x1, + Div4 = 0x2, + Div8 = 0x3, + Div16 = 0x4, + Div32 = 0x5, + Div64 = 0x6, + Div128 = 0x7, }; - /// Virtual 1-channel timers - pub const TIM_1CH = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Clock division - CKD: packed union { - raw: u2, - value: CKD, - }, - padding: u22, - }), - reserved12: [8]u8, - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/Compare x (x=1) interrupt enable - CCIE: u1, - padding: u30, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1) interrupt flag + pub const TRIGEN = enum(u2) { + /// software trigger (counting start is initiated by software) + Software = 0x0, + /// rising edge is the active edge + RisingEdge = 0x1, + /// falling edge is the active edge + FallingEdge = 0x2, + /// both edges are active edges + BothEdge = 0x3, + }; + + pub const WAVPOL = enum(u1) { + /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + Positive = 0x0, + /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + Negative = 0x1, + }; + + /// Low power timer with Output Compare + pub const LPTIM = extern struct { + /// LPTIM interrupt and status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. CCIF: u1, - reserved9: u7, - /// Capture/Compare x (x=1) overcapture flag + reserved3: u2, + /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + CMPOK: u1, + reserved12: u8, + /// Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. CCOF: u1, - padding: u22, - }), - /// event generation register - EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1) generation - CCG: u1, - padding: u30, + padding: u19, }), - /// capture/compare mode register 1 (input mode) - CCMR_Input: [1]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: packed union { - raw: u2, - value: CCMR_Input_CCS, - }, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: packed union { - raw: u4, - value: FilterValue, - }, - padding: u24, + /// LPTIM interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + CCCF: u1, + reserved3: u2, + /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + CMPOKCF: u1, + reserved12: u8, + /// Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + CCOCF: u1, + padding: u19, }), - reserved32: [4]u8, - /// capture/compare enable register - CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1) output enable - CCE: u1, - /// Capture/Compare x (x=1) output Polarity - CCP: u1, - reserved3: u1, - /// Capture/Compare x (x=1) output Polarity - CCNP: u1, - padding: u28, + /// LPTIM interrupt enable register. + DIER: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 interrupt enable. + CCIE: u1, + reserved3: u2, + /// Compare register 1 update OK interrupt enable. + CMPOKIE: u1, + reserved12: u8, + /// Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + CCOIE: u1, + reserved16: u3, + /// Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + CCDE: u1, + padding: u15, }), - reserved52: [16]u8, - /// capture/compare register x (x=1) - CCR: [1]mmio.Mmio(packed struct(u32) { - /// capture/compare x (x=1-4,6) value + reserved20: [8]u8, + /// LPTIM compare register 1. + CCR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. CCR: u16, padding: u16, }), - reserved80: [24]u8, - /// Option register 1 Note: Check Reference Manual to parse this register content - OR: u32, - }; - - /// 2-channel timers - pub const TIM_2CH = extern struct { - reserved4: [4]u8, - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Master mode selection - MMS: packed union { - raw: u3, - value: MMS, - }, - /// TI1 selection - TI1S: packed union { - raw: u1, - value: TI1S, - }, - padding: u24, - }), - /// slave mode control register - SMCR: mmio.Mmio(packed struct(u32) { - /// Slave mode selection - SMS: packed union { - raw: u3, - value: SMS, - }, - reserved4: u1, - /// Trigger selection - TS: packed union { - raw: u3, - value: TS, - }, - /// Master/Slave mode - MSM: packed union { + reserved44: [20]u8, + /// LPTIM capture/compare mode register 1. + CCMR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. + CCSEL: packed union { raw: u1, - value: MSM, - }, - /// External trigger filter - ETF: packed union { - raw: u4, - value: FilterValue, + value: CCSEL, }, - /// External trigger prescaler - ETPS: packed union { + /// Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. + CCE: u1, + /// Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + CCP_Input: packed union { raw: u2, - value: ETPS, - }, - /// External clock mode 2 enable - ECE: u1, - /// External trigger polarity - ETP: packed union { - raw: u1, - value: ETP, + value: CCP_Input, }, - padding: u16, - }), - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/Compare x (x=1-2) interrupt enable - CCIE: u1, - reserved6: u4, - /// Trigger interrupt enable - TIE: u1, - padding: u25, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1-2) interrupt flag - CCIF: u1, - reserved6: u4, - /// Trigger interrupt flag - TIF: u1, - reserved9: u2, - /// Capture/Compare x (x=1-2) overcapture flag - CCOF: u1, - padding: u22, - }), - /// event generation register - EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1-2) generation - CCG: u1, - reserved6: u4, - /// Trigger generation - TG: u1, - padding: u25, - }), - /// capture/compare mode register 1 (input mode) - CCMR_Input: [1]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: packed union { + reserved8: u4, + /// Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + ICPSC: packed union { raw: u2, - value: CCMR_Input_CCS, + value: Filter, }, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter + reserved12: u2, + /// Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. ICF: packed union { - raw: u4, - value: FilterValue, - }, - padding: u24, - }), - reserved32: [4]u8, - /// capture/compare enable register - CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-2) output enable - CCE: u1, - /// Capture/Compare x (x=1-2) output Polarity - CCP: u1, - reserved3: u1, - /// Capture/Compare x (x=1-2) output Polarity - CCNP: u1, - padding: u28, - }), - reserved52: [16]u8, - /// capture/compare register x (x=1-2) - CCR: [2]mmio.Mmio(packed struct(u32) { - /// capture/compare x (x=1-4,6) value - CCR: u16, - padding: u16, - }), - }; - - /// Basic timers - pub const TIM_BASIC = extern struct { - reserved4: [4]u8, - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Master mode selection - MMS: packed union { - raw: u3, - value: MMS, + raw: u2, + value: Filter, }, - padding: u25, + padding: u18, }), }; - /// Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP - pub const TIM_BASIC_NO_CR2 = extern struct { - reserved12: [12]u8, - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Update DMA request enable - UDE: u1, - padding: u23, + /// Low power timer with Output Compare + pub const LPTIM_BASIC = extern struct { + /// LPTIM interrupt and status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + CCIF: u1, + /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + ARRM: u1, + /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + EXTTRIG: u1, + /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + CMPOK: u1, + /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + ARROK: u1, + /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UP: u1, + /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWN: u1, + /// LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + UE: u1, + /// Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + REPOK: u1, + reserved24: u15, + /// Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + DIEROK: u1, + padding: u7, }), - }; - - /// Virtual timer for common part of TIM_BASIC and TIM_1CH - pub const TIM_CORE = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: packed union { - raw: u1, - value: URS, - }, - /// One-pulse mode enbaled - OPM: u1, - reserved7: u3, - /// Auto-reload preload enable - ARPE: u1, - reserved11: u3, - /// UIF status bit remapping enable - UIFREMAP: u1, - padding: u20, + /// LPTIM interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + CCCF: u1, + /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + ARRMCF: u1, + /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + EXTTRIGCF: u1, + /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + CMPOKCF: u1, + /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + ARROKCF: u1, + /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPCF: u1, + /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNCF: u1, + /// Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + UECF: u1, + /// Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + REPOKCF: u1, + reserved24: u15, + /// Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + DIEROKCF: u1, + padding: u7, }), - reserved12: [8]u8, - /// DMA/Interrupt enable register + /// LPTIM interrupt enable register. DIER: mmio.Mmio(packed struct(u32) { - /// Update interrupt enable - UIE: u1, - padding: u31, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Update interrupt flag - UIF: u1, - padding: u31, - }), - /// event generation register - EGR: mmio.Mmio(packed struct(u32) { - /// Update generation - UG: u1, - padding: u31, - }), - reserved36: [12]u8, - /// counter - CNT: mmio.Mmio(packed struct(u32) { - /// counter value - CNT: u16, - reserved31: u15, - /// UIF copy - UIFCPY: u1, - }), - /// prescaler - PSC: u32, - /// auto-reload register - ARR: mmio.Mmio(packed struct(u32) { - /// Auto-reload value - ARR: u16, - padding: u16, + /// Capture/compare 1 interrupt enable. + CCIE: u1, + /// Autoreload match Interrupt Enable. + ARRMIE: u1, + /// External trigger valid edge Interrupt Enable. + EXTTRIGIE: u1, + /// Compare register 1 update OK interrupt enable. + CMPOKIE: u1, + /// Autoreload register update OK Interrupt Enable. + ARROKIE: u1, + /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPIE: u1, + /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNIE: u1, + /// Update event interrupt enable. + UEIE: u1, + /// Repetition register update OK interrupt Enable. + REPOKIE: u1, + padding: u23, }), - }; - - /// General purpose 16-bit timers - pub const TIM_GP16 = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Direction - DIR: packed union { + /// LPTIM configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + CKSEL: packed union { raw: u1, - value: DIR, + value: ClockSource, }, - /// Center-aligned mode selection - CMS: packed union { + /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. + CKPOL: packed union { raw: u2, - value: CMS, + value: CKPOL, }, - reserved8: u1, - /// Clock division - CKD: packed union { + /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + CKFLT: packed union { raw: u2, - value: CKD, - }, - padding: u22, - }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Capture/compare DMA selection - CCDS: packed union { - raw: u1, - value: CCDS, - }, - reserved7: u3, - /// TI1 selection - TI1S: packed union { - raw: u1, - value: TI1S, + value: Filter, }, - padding: u24, - }), - /// slave mode control register - SMCR: mmio.Mmio(packed struct(u32) { - /// Slave mode selection - SMS: packed union { - raw: u3, - value: SMS, + reserved6: u1, + /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + TRGFLT: packed union { + raw: u2, + value: Filter, }, - reserved4: u1, - /// Trigger selection - TS: packed union { + reserved9: u1, + /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + PRESC: packed union { raw: u3, - value: TS, - }, - /// Master/Slave mode - MSM: packed union { - raw: u1, - value: MSM, - }, - /// External trigger filter - ETF: packed union { - raw: u4, - value: FilterValue, + value: PRESC, }, - /// External trigger prescaler - ETPS: packed union { + reserved13: u1, + /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. + TRIGSEL: u3, + reserved17: u1, + /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + TRIGEN: packed union { raw: u2, - value: ETPS, + value: TRIGEN, }, - /// External clock mode 2 enable - ECE: u1, - /// External trigger polarity - ETP: packed union { + /// Timeout enable The TIMOUT bit controls the Timeout feature. + TIMOUT: u1, + /// Waveform shape The WAVE bit controls the output shape. + WAVE: u1, + /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. + WAVPOL: packed union { raw: u1, - value: ETP, - }, - padding: u16, - }), - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/Compare x (x=1-4) interrupt enable - CCIE: u1, - reserved6: u4, - /// Trigger interrupt enable - TIE: u1, - reserved9: u2, - /// Capture/Compare x (x=1-4) DMA request enable - CCDE: u1, - reserved14: u4, - /// Trigger DMA request enable - TDE: u1, - padding: u17, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1-4) interrupt flag - CCIF: u1, - reserved6: u4, - /// Trigger interrupt flag - TIF: u1, - reserved9: u2, - /// Capture/Compare x (x=1-4) overcapture flag - CCOF: u1, - padding: u22, - }), - /// event generation register - EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Capture/compare x (x=1-4) generation - CCG: u1, - reserved6: u4, - /// Trigger generation - TG: u1, - padding: u25, - }), - /// capture/compare mode register 1-2 (input mode) - CCMR_Input: [2]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: packed union { - raw: u2, - value: CCMR_Input_CCS, + value: WAVPOL, }, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: packed union { - raw: u4, - value: FilterValue, + /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + PRELOAD: u1, + /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + COUNTMODE: packed union { + raw: u1, + value: ClockSource, }, - padding: u24, + /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + ENC: u1, + padding: u7, }), - /// capture/compare enable register - CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-4) output enable - CCE: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCP: u1, - reserved3: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCNP: u1, - padding: u28, + /// LPTIM control register. + CR: mmio.Mmio(packed struct(u32) { + /// LPTIM enable The ENABLE bit is set and cleared by software. + ENABLE: u1, + /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + SNGSTRT: u1, + /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + CNTSTRT: u1, + /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + COUNTRST: u1, + /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + RSTARE: u1, + padding: u27, }), - reserved52: [16]u8, - /// capture/compare register x (x=1-4) - CCR: [4]mmio.Mmio(packed struct(u32) { - /// capture/compare x (x=1-4,6) value + /// LPTIM compare register 1. + CCR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. CCR: u16, padding: u16, }), - reserved72: [4]u8, - /// DMA control register - DCR: mmio.Mmio(packed struct(u32) { - /// DMA base address - DBA: u5, - reserved8: u3, - /// DMA burst length - DBL: u5, - padding: u19, + /// LPTIM autoreload register. + ARR: mmio.Mmio(packed struct(u32) { + /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + ARR: u16, + padding: u16, }), - /// DMA address for full transfer - DMAR: mmio.Mmio(packed struct(u32) { - /// DMA register for burst accesses - DMAB: u16, + /// LPTIM counter register. + CNT: mmio.Mmio(packed struct(u32) { + /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + CNT: u16, padding: u16, }), + reserved36: [4]u8, + /// LPTIM configuration register 2. + CFGR2: mmio.Mmio(packed struct(u32) { + /// LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + INSEL: u2, + reserved16: u14, + /// LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. + ICSEL: u2, + padding: u14, + }), + /// LPTIM repetition register. + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition register value REP is the repetition value for the LPTIM. + REP: u8, + padding: u24, + }), }; }; - pub const otfdec_v1 = struct { - pub const ENC = enum(u1) { - /// OTFDEC working in decryption mode - Decryption = 0x0, - /// OTFDEC working in encryption mode - Encryption = 0x1, + pub const lptim_v2b = struct { + pub const CCP_Input = enum(u2) { + Rising = 0x0, + Falling = 0x1, + Both = 0x3, + _, }; - pub const MODE = enum(u2) { - /// All read accesses are decrypted (instruction or data). - Standard = 0x2, - /// Enhanced encryption mode is activated, and only instruction accesses are decrypted - Enhanced = 0x3, + pub const CCP_Output = enum(u2) { + ActiveHigh = 0x0, + ActiveLow = 0x1, _, }; - /// On-The-Fly Decryption engine. - pub const OTFDEC = extern struct { - /// OTFDEC control register. - CR: mmio.Mmio(packed struct(u32) { - /// Encryption mode bit When this bit is set, OTFDEC is used in encryption mode, during which application can write clear text data then read back encrypted data. When this bit is cleared (default), OTFDEC is used in decryption mode, during which application only read back decrypted data. For both modes, cryptographic context (keys, nonces, firmware versions) must be properly initialized. When this bit is set, only data accesses are allowed (zeros are returned otherwise, and XONEIF is set). When MODE = 11, enhanced encryption mode is automatically selected. Note: When ENC bit is set, no access to OCTOSPI must be done (registers and Memory‑mapped region). - ENC: packed union { - raw: u1, - value: ENC, - }, - padding: u31, - }), - reserved16: [12]u8, - /// OTFDEC_PRIVCFGR. - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// Privileged access protection. Unprivileged read accesses to registers return zeros Unprivileged write accesses to registers are ignored. Note: This bit can only be written in privileged mode. There is no limitations on reads. - PRIV: u1, - padding: u31, - }), - reserved32: [12]u8, - Region: u32, - reserved768: [732]u8, - /// OTFDEC interrupt status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Security error interrupt flag status This bit is set by hardware and read only by application. This bit is set when at least one security error has been detected. This bit is cleared when application sets in OTFDEC_ICR the corresponding bit to 1. - SEIF: u1, - /// Execute-only execute-never error interrupt flag status This bit is set by hardware and read only by application. This bit is set when a read access and not an instruction fetch is detected on any encrypted region with MODE bits set to 11. Lastly, XONEIF is also set when an execute access is detected while encryption mode is enabled. This bit is cleared when application sets in OTFDEC_ICR the corresponding bit to 1. - XONEIF: u1, - /// Key error interrupt flag status This bit is set by hardware and read only by application. The bit is set when a read access occurs on an encrypted region, while its key registers is null or not properly initialized (KEYCRC = 0x0). This bit is cleared when the application sets in OTFDEC_ICR the corresponding bit to 1. After KEIF is set any subsequent read to the region with bad key registers returns a zeroed value. This state remains until those key registers are properly initialized (KEYCRC not zero). - KEIF: u1, - padding: u29, - }), - /// OTFDEC interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Security error interrupt flag clear This bit is written by application, and always read as 0. - SEIF: u1, - /// Execute-only execute-never error interrupt flag clear This bit is written by application, and always read as 0. - XONEIF: u1, - /// Key error interrupt flag clear This bit is written by application, and always read as 0. Note: Clearing KEIF does not solve the source of the problem (bad key registers). To be able to access again any encrypted region, OTFDEC key registers must be properly initialized again. - KEIF: u1, - padding: u29, - }), - /// OTFDEC interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Security error interrupt enable This bit is read and written by application. It controls the OTFDEC interrupt generation when SEIF flag status is set. - SEIE: u1, - /// Execute-only execute-never error interrupt enable This bit is read and written by application. It controls the OTFDEC interrupt generation when XONEIF flag status is set. - XONEIE: u1, - /// Key error interrupt enable This bit is read and written by application. It controls the OTFDEC interrupt generation when KEIF flag status is set. - KEIE: u1, - padding: u29, - }), + pub const CCSEL = enum(u1) { + /// channel is configured in output PWM mode + OutputCompare = 0x0, + /// channel is configured in input capture mode + InputCapture = 0x1, }; - pub const Region = extern struct { - /// OTFDEC region 3 configuration register. - CFGR: mmio.Mmio(packed struct(u32) { - /// region on-the-fly decryption enable Note: Garbage is decrypted if region context (version, key, nonce) is not valid when this bit is set. - REG_EN: u1, - /// region config lock Note: This bit is set once. If this bit is set, it can only be reset to 0 if OTFDEC is reset. Setting this bit forces KEYLOCK bit to 1. - CONFIGLOCK: u1, - /// region key lock Note: This bit is set once: if this bit is set, it can only be reset to 0 if the OTFDEC is reset. - KEYLOCK: u1, - reserved4: u1, - /// operating mode This bitfield selects the OTFDEC operating mode for this region: Others: Reserved When MODE ≠ 11, the standard AES encryption mode is activated. When either of the MODE bits are changed, the region key and associated CRC are zeroed. - MODE: packed union { - raw: u2, - value: MODE, - }, - reserved8: u2, - /// region key 8-bit CRC When KEYLOCK = 0, KEYCRC bitfield is automatically computed by hardware while loading the key of this region in this exact sequence: KEYR0 then KEYR1 then KEYR2 then finally KEYR3 (all written once). A new computation starts as soon as a new valid sequence is initiated, and KEYCRC is read as zero until a valid sequence is completed. When KEYLOCK = 1, KEYCRC remains unchanged until the next reset. CRC computation is an 8-bit checksum using the standard CRC-8-CCITT algorithm X8 + X2 + X + 1 (according the convention). Source code is available in . This field is read only. Note: CRC information is updated only after the last bit of the key has been written. - KEYCRC: u8, - /// region firmware version This 16-bit bitfield must be correctly initialized before the region corresponding REG_EN bit is set in OTFDEC_RxCFGR. - REG_VERSION: u16, - }), - /// OTFDEC region 3 start address register. - STARTADDR: u32, - /// OTFDEC region 3 end address register. - ENDADDR: u32, - /// OTFDEC region 3 nonce register 0. - NONCER: [2]u32, - /// OTFDEC region 3 key register 0. - KEYR: [4]u32, + pub const CKPOL = enum(u2) { + /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + Rising = 0x0, + /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + Falling = 0x1, + /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + Both = 0x2, + _, }; - }; - pub const rtc_v2f7 = struct { - pub const ALRMR_MSK = enum(u1) { - /// Alarm set if the date/day match - ToMatch = 0x0, - /// Date/day don’t care in Alarm comparison - NotMatch = 0x1, + pub const ClockSource = enum(u1) { + /// clocked by internal clock source (APB clock or any of the embedded oscillators) + Internal = 0x0, + /// clocked by an external clock source through the LPTIM external Input1 + External = 0x1, }; - pub const ALRMR_PM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const Filter = enum(u2) { + Count1 = 0x0, + Count2 = 0x1, + Count4 = 0x2, + Count8 = 0x3, }; - pub const ALRMR_WDSEL = enum(u1) { - /// DU[3:0] represents the date units - DateUnits = 0x0, - /// DU[3:0] represents the week day. DT[1:0] is don’t care - WeekDay = 0x1, + pub const PRESC = enum(u3) { + Div1 = 0x0, + Div2 = 0x1, + Div4 = 0x2, + Div8 = 0x3, + Div16 = 0x4, + Div32 = 0x5, + Div64 = 0x6, + Div128 = 0x7, }; - pub const AMPM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const TRIGEN = enum(u2) { + /// software trigger (counting start is initiated by software) + Software = 0x0, + /// rising edge is the active edge + RisingEdge = 0x1, + /// falling edge is the active edge + FallingEdge = 0x2, + /// both edges are active edges + BothEdge = 0x3, }; - pub const CALP = enum(u1) { - /// No RTCCLK pulses are added - NoChange = 0x0, - /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - IncreaseFreq = 0x1, + /// Low power timer with Output Compare + pub const LPTIM = extern struct { + /// LPTIM interrupt and status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + CCIF: u1, + /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + ARRM: u1, + /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + EXTTRIG: u1, + /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + CMPOK: u1, + /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + ARROK: u1, + /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UP: u1, + /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWN: u1, + /// LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + UE: u1, + /// Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + REPOK: u1, + reserved12: u3, + /// Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + CCOF: u1, + reserved24: u11, + /// Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + DIEROK: u1, + padding: u7, + }), + /// LPTIM interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + CCCF: u1, + /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + ARRMCF: u1, + /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + EXTTRIGCF: u1, + /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + CMPOKCF: u1, + /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + ARROKCF: u1, + /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPCF: u1, + /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNCF: u1, + /// Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + UECF: u1, + /// Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + REPOKCF: u1, + reserved12: u3, + /// Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + CCOCF: u1, + reserved24: u11, + /// Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + DIEROKCF: u1, + padding: u7, + }), + /// LPTIM interrupt enable register. + DIER: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 interrupt enable. + CCIE: u1, + /// Autoreload match Interrupt Enable. + ARRMIE: u1, + /// External trigger valid edge Interrupt Enable. + EXTTRIGIE: u1, + /// Compare register 1 update OK interrupt enable. + CMPOKIE: u1, + /// Autoreload register update OK Interrupt Enable. + ARROKIE: u1, + /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPIE: u1, + /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNIE: u1, + /// Update event interrupt enable. + UEIE: u1, + /// Repetition register update OK interrupt Enable. + REPOKIE: u1, + reserved12: u3, + /// Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + CCOIE: u1, + reserved16: u3, + /// Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + CCDE: u1, + padding: u15, + }), + /// LPTIM configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + CKSEL: packed union { + raw: u1, + value: ClockSource, + }, + /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. + CKPOL: packed union { + raw: u2, + value: CKPOL, + }, + /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + CKFLT: packed union { + raw: u2, + value: Filter, + }, + reserved6: u1, + /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + TRGFLT: packed union { + raw: u2, + value: Filter, + }, + reserved9: u1, + /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + PRESC: packed union { + raw: u3, + value: PRESC, + }, + reserved13: u1, + /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. + TRIGSEL: u3, + reserved17: u1, + /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + TRIGEN: packed union { + raw: u2, + value: TRIGEN, + }, + /// Timeout enable The TIMOUT bit controls the Timeout feature. + TIMOUT: u1, + /// Waveform shape The WAVE bit controls the output shape. + WAVE: u1, + reserved22: u1, + /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + PRELOAD: u1, + /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + COUNTMODE: packed union { + raw: u1, + value: ClockSource, + }, + /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + ENC: u1, + padding: u7, + }), + /// LPTIM control register. + CR: mmio.Mmio(packed struct(u32) { + /// LPTIM enable The ENABLE bit is set and cleared by software. + ENABLE: u1, + /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + SNGSTRT: u1, + /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + CNTSTRT: u1, + /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + COUNTRST: u1, + /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + RSTARE: u1, + padding: u27, + }), + /// LPTIM compare register 1. + CCR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. + CCR: u16, + padding: u16, + }), + /// LPTIM autoreload register. + ARR: mmio.Mmio(packed struct(u32) { + /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + ARR: u16, + padding: u16, + }), + /// LPTIM counter register. + CNT: mmio.Mmio(packed struct(u32) { + /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + CNT: u16, + padding: u16, + }), + reserved36: [4]u8, + /// LPTIM configuration register 2. + CFGR2: mmio.Mmio(packed struct(u32) { + /// LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + INSEL: u2, + reserved16: u14, + /// LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. + ICSEL: u2, + padding: u14, + }), + /// LPTIM repetition register. + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition register value REP is the repetition value for the LPTIM. + REP: u8, + padding: u24, + }), + /// LPTIM capture/compare mode register. + CCMR: mmio.Mmio(packed struct(u32) { + /// Capture/compare selection. This bitfield defines the direction of the channel input (capture) or output mode. + CCSEL: packed union { + raw: u1, + value: CCSEL, + }, + /// Capture/compare output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. + CCE: u1, + /// Capture/compare output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + CCP_Input: packed union { + raw: u2, + value: CCP_Input, + }, + reserved8: u4, + /// Input capture prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + ICPSC: packed union { + raw: u2, + value: Filter, + }, + reserved12: u2, + /// Input capture filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + ICF: packed union { + raw: u2, + value: Filter, + }, + padding: u18, + }), }; + }; - pub const CALW16 = enum(u1) { - /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 - Sixteen_Second = 0x1, + pub const ltdc_v1 = struct { + pub const BF1 = enum(u3) { + /// BF1 = constant alpha + Constant = 0x4, + /// BF1 = pixel alpha * constant alpha + Pixel = 0x7, _, }; - pub const CALW8 = enum(u1) { - /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected - Eight_Second = 0x1, + pub const BF2 = enum(u3) { + /// BF2 = 1 - constant alpha + Constant = 0x5, + /// BF2 = 1 - pixel alpha * constant alpha + Pixel = 0x7, _, }; - pub const COSEL = enum(u1) { - /// Calibration output is 512 Hz (with default prescaler setting) - CalFreq_512Hz = 0x0, - /// Calibration output is 1 Hz (with default prescaler setting) - CalFreq_1Hz = 0x1, - }; - - pub const FMT = enum(u1) { - /// 24 hour/day format - Twenty_Four_Hour = 0x0, - /// AM/PM hour format - AM_PM = 0x1, - }; - - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Alarm B output enabled - AlarmB = 0x2, - /// Wakeup output enabled - Wakeup = 0x3, + pub const CFUIF = enum(u1) { + /// Clears the FUIF flag in the ISR register + Clear = 0x1, + _, }; - pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - Low = 0x1, + pub const CLIF = enum(u1) { + /// Clears the LIF flag in the ISR register + Clear = 0x1, + _, }; - pub const RECALPF = enum(u1) { - /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 - Pending = 0x1, + pub const CRRIF = enum(u1) { + /// Clears the RRIF flag in the ISR register + Clear = 0x1, _, }; - pub const TAMPFLT = enum(u2) { - /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - Immediate = 0x0, - /// Tamper event is activated after 2 consecutive samples at the active level - Samples2 = 0x1, - /// Tamper event is activated after 4 consecutive samples at the active level - Samples4 = 0x2, - /// Tamper event is activated after 8 consecutive samples at the active level - Samples8 = 0x3, + pub const CTERRIF = enum(u1) { + /// Clears the TERRIF flag in the ISR register + Clear = 0x1, + _, }; - pub const TAMPFREQ = enum(u3) { - /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - Div32768 = 0x0, - /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - Div16384 = 0x1, - /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - Div8192 = 0x2, - /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - Div4096 = 0x3, - /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - Div2048 = 0x4, - /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - Div1024 = 0x5, - /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - Div512 = 0x6, - /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - Div256 = 0x7, + pub const DEPOL = enum(u1) { + /// Data enable polarity is active low + ActiveLow = 0x0, + /// Data enable polarity is active high + ActiveHigh = 0x1, }; - pub const TAMPPRCH = enum(u2) { - /// 1 RTCCLK cycle - Cycles1 = 0x0, - /// 2 RTCCLK cycles - Cycles2 = 0x1, - /// 4 RTCCLK cycles - Cycles4 = 0x2, - /// 8 RTCCLK cycles - Cycles8 = 0x3, + pub const HSPOL = enum(u1) { + /// Horizontal synchronization polarity is active low + ActiveLow = 0x0, + /// Horizontal synchronization polarity is active high + ActiveHigh = 0x1, }; - pub const TAMPPUDIS = enum(u1) { - /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - Enabled = 0x0, - /// Disable precharge of RTC_TAMPx pins - Disabled = 0x1, + pub const IMR = enum(u1) { + /// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) + NoEffect = 0x0, + /// The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload + Reload = 0x1, }; - pub const TAMPTRG = enum(u1) { - /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. + pub const PCPOL = enum(u1) { + /// Pixel clock on rising edge RisingEdge = 0x0, - /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event + /// Pixel clock on falling edge FallingEdge = 0x1, }; - pub const TSEDGE = enum(u1) { - /// RTC_TS input rising edge generates a time-stamp event - RisingEdge = 0x0, - /// RTC_TS input falling edge generates a time-stamp event - FallingEdge = 0x1, + pub const PF = enum(u3) { + /// ARGB8888 + ARGB8888 = 0x0, + /// RGB888 + RGB888 = 0x1, + /// RGB565 + RGB565 = 0x2, + /// ARGB1555 + ARGB1555 = 0x3, + /// ARGB4444 + ARGB4444 = 0x4, + /// L8 (8-bit luminance) + L8 = 0x5, + /// AL44 (4-bit alpha, 4-bit luminance) + AL44 = 0x6, + /// AL88 (8-bit alpha, 8-bit luminance) + AL88 = 0x7, }; - pub const WUCKSEL = enum(u3) { - /// RTC/16 clock is selected - Div16 = 0x0, - /// RTC/8 clock is selected - Div8 = 0x1, - /// RTC/4 clock is selected - Div4 = 0x2, - /// RTC/2 clock is selected - Div2 = 0x3, - /// ck_spre (usually 1 Hz) clock is selected - ClockSpare = 0x4, - /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - ClockSpareWithOffset = 0x6, - _, + pub const VBR = enum(u1) { + /// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) + NoEffect = 0x0, + /// The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). + Reload = 0x1, }; - /// Real-time clock - pub const RTC = extern struct { - /// Time register - TR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, + pub const VSPOL = enum(u1) { + /// Vertical synchronization polarity is active low + ActiveLow = 0x0, + /// Vertical synchronization polarity is active high + ActiveHigh = 0x1, + }; + + /// Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR + pub const LAYER = extern struct { + /// Layerx Control Register + CR: mmio.Mmio(packed struct(u32) { + /// Layer Enable + LEN: u1, + /// Color Keying Enable + COLKEN: u1, + reserved4: u2, + /// Color Look-Up Table Enable + CLUTEN: u1, + padding: u27, }), - /// Date register - DR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, + /// Layerx Window Horizontal Position Configuration Register + WHPCR: mmio.Mmio(packed struct(u32) { + /// Window Horizontal Start Position + WHSTPOS: u12, + reserved16: u4, + /// Window Horizontal Stop Position + WHSPPOS: u12, + padding: u4, + }), + /// Layerx Window Vertical Position Configuration Register + WVPCR: mmio.Mmio(packed struct(u32) { + /// Window Vertical Start Position + WVSTPOS: u11, + reserved16: u5, + /// Window Vertical Stop Position + WVSPPOS: u11, + padding: u5, + }), + /// Layerx Color Keying Configuration Register + CKCR: mmio.Mmio(packed struct(u32) { + /// Color Key Blue value + CKBLUE: u8, + /// Color Key Green value + CKGREEN: u8, + /// Color Key Red value + CKRED: u8, padding: u8, }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Wakeup clock selection - WUCKSEL: packed union { + /// Layerx Pixel Format Configuration Register + PFCR: mmio.Mmio(packed struct(u32) { + /// Pixel Format + PF: packed union { raw: u3, - value: WUCKSEL, - }, - /// Timestamp event active edge - TSEDGE: packed union { - raw: u1, - value: TSEDGE, - }, - /// Reference clock detection enable (50 or 60 Hz) - REFCKON: u1, - /// Bypass the shadow registers - BYPSHAD: u1, - /// Hour format - FMT: packed union { - raw: u1, - value: FMT, - }, - reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, - /// Wakeup timer enable - WUTE: u1, - /// Timestamp enable - TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, - /// Wakeup timer interrupt enable - WUTIE: u1, - /// Timestamp interrupt enable - TSIE: u1, - /// Add 1 hour (summer time change) - ADD1H: u1, - /// Subtract 1 hour (winter time change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output selection - COSEL: packed union { - raw: u1, - value: COSEL, + value: PF, }, - /// Output polarity - POL: packed union { - raw: u1, - value: POL, + padding: u29, + }), + /// Layerx Constant Alpha Configuration Register + CACR: mmio.Mmio(packed struct(u32) { + /// Constant Alpha + CONSTA: u8, + padding: u24, + }), + /// Layerx Default Color Configuration Register + DCCR: mmio.Mmio(packed struct(u32) { + /// Default Color Blue + DCBLUE: u8, + /// Default Color Green + DCGREEN: u8, + /// Default Color Red + DCRED: u8, + /// Default Color Alpha + DCALPHA: u8, + }), + /// Layerx Blending Factors Configuration Register + BFCR: mmio.Mmio(packed struct(u32) { + /// Blending Factor 2 + BF2: packed union { + raw: u3, + value: BF2, }, - /// Output selection - OSEL: packed union { - raw: u2, - value: OSEL, + reserved8: u5, + /// Blending Factor 1 + BF1: packed union { + raw: u3, + value: BF1, }, - /// Calibration output enable - COE: u1, - /// Timestamp on internal event enable - ITSE: u1, - padding: u7, + padding: u21, }), - /// Initialization and status register - ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, - /// Wakeup timer write enabled - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Enter Initialization mode - INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, - /// Wakeup timer flag - WUTF: u1, - /// Timestamp flag - TSF: u1, - /// Timestamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, - /// Recalibration pending flag - RECALPF: packed union { - raw: u1, - value: RECALPF, - }, - /// Internal time-stamp flag - ITSF: u1, - padding: u14, + reserved40: [8]u8, + /// Layerx Color Frame Buffer Address Register + CFBAR: mmio.Mmio(packed struct(u32) { + /// Color Frame Buffer Start Address + CFBADD: u32, }), - /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, - padding: u9, + /// Layerx Color Frame Buffer Length Register + CFBLR: mmio.Mmio(packed struct(u32) { + /// Color Frame Buffer Line Length + CFBLL: u13, + reserved16: u3, + /// Color Frame Buffer Pitch in bytes + CFBP: u13, + padding: u3, }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, - padding: u16, + /// Layerx ColorFrame Buffer Line Number Register + CFBLNR: mmio.Mmio(packed struct(u32) { + /// Frame Buffer Line Number + CFBLNBR: u11, + padding: u21, }), - reserved28: [4]u8, - /// Alarm register - ALRMR: [2]mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm seconds mask - MSK1: packed union { + reserved64: [12]u8, + /// Layerx CLUT Write Register + CLUTWR: mmio.Mmio(packed struct(u32) { + /// Blue value + BLUE: u8, + /// Green value + GREEN: u8, + /// Red value + RED: u8, + /// CLUT Address + CLUTADD: u8, + }), + }; + + /// LCD-TFT Controller + pub const LTDC = extern struct { + reserved8: [8]u8, + /// Synchronization Size Configuration Register + SSCR: mmio.Mmio(packed struct(u32) { + /// Vertical Synchronization Height (in units of horizontal scan line) + VSH: u11, + reserved16: u5, + /// Horizontal Synchronization Width (in units of pixel clock period) + HSW: u12, + padding: u4, + }), + /// Back Porch Configuration Register + BPCR: mmio.Mmio(packed struct(u32) { + /// Accumulated Vertical back porch (in units of horizontal scan line) + AVBP: u11, + reserved16: u5, + /// Accumulated Horizontal back porch (in units of pixel clock period) + AHBP: u12, + padding: u4, + }), + /// Active Width Configuration Register + AWCR: mmio.Mmio(packed struct(u32) { + /// Accumulated Active Height (in units of horizontal scan line) + AAH: u11, + reserved16: u5, + /// Accumulated Active Width (in units of pixel clock period) + AAW: u12, + padding: u4, + }), + /// Total Width Configuration Register + TWCR: mmio.Mmio(packed struct(u32) { + /// Total Height (in units of horizontal scan line) + TOTALH: u11, + reserved16: u5, + /// Total Width (in units of pixel clock period) + TOTALW: u12, + padding: u4, + }), + /// Global Control Register + GCR: mmio.Mmio(packed struct(u32) { + /// LCD-TFT controller enable bit + LTDCEN: u1, + reserved4: u3, + /// Dither Blue Width + DBW: u3, + reserved8: u1, + /// Dither Green Width + DGW: u3, + reserved12: u1, + /// Dither Red Width + DRW: u3, + reserved16: u1, + /// Dither Enable + DEN: u1, + reserved28: u11, + /// Pixel Clock Polarity + PCPOL: packed union { raw: u1, - value: ALRMR_MSK, + value: PCPOL, }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm minutes mask - MSK2: packed union { + /// Data Enable Polarity + DEPOL: packed union { raw: u1, - value: ALRMR_MSK, + value: DEPOL, }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { + /// Vertical Synchronization Polarity + VSPOL: packed union { raw: u1, - value: ALRMR_PM, + value: VSPOL, }, - /// Alarm hours mask - MSK3: packed union { + /// Horizontal Synchronization Polarity + HSPOL: packed union { raw: u1, - value: ALRMR_MSK, + value: HSPOL, }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { + }), + reserved36: [8]u8, + /// Shadow Reload Configuration Register + SRCR: mmio.Mmio(packed struct(u32) { + /// Immediate Reload + IMR: packed union { raw: u1, - value: ALRMR_WDSEL, + value: IMR, }, - /// Alarm date mask - MSK4: packed union { + /// Vertical Blanking Reload + VBR: packed union { raw: u1, - value: ALRMR_MSK, + value: VBR, }, + padding: u30, }), - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: u8, - padding: u24, + reserved44: [4]u8, + /// Background Color Configuration Register + BCCR: mmio.Mmio(packed struct(u32) { + /// Background color blue value + BCBLUE: u8, + /// Background color green value + BCGREEN: u8, + /// Background color red value + BCRED: u8, + padding: u8, }), - /// Sub second register - SSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, + reserved52: [4]u8, + /// Interrupt Enable Register + IER: mmio.Mmio(packed struct(u32) { + /// Line Interrupt Enable + LIE: u1, + /// FIFO Underrun Interrupt Enable + FUIE: u1, + /// Transfer Error Interrupt Enable + TERRIE: u1, + /// Register Reload interrupt enable + RRIE: u1, + padding: u28, }), - /// Shift control register - SHIFTR: mmio.Mmio(packed struct(u32) { - /// Subtract a fraction of a second - SUBFS: u15, - reserved31: u16, - /// Add one second - ADD1S: u1, + /// Interrupt Status Register + ISR: mmio.Mmio(packed struct(u32) { + /// Line Interrupt flag + LIF: u1, + /// FIFO Underrun Interrupt flag + FUIF: u1, + /// Transfer Error interrupt flag + TERRIF: u1, + /// Register Reload Interrupt Flag + RRIF: u1, + padding: u28, }), - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { + /// Interrupt Clear Register + ICR: mmio.Mmio(packed struct(u32) { + /// Clears the Line Interrupt Flag + CLIF: packed union { raw: u1, - value: AMPM, + value: CLIF, }, - padding: u9, - }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding: u16, - }), - /// Timestamp sub second register - TSSSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, - }), - /// Calibration register - CALR: mmio.Mmio(packed struct(u32) { - /// Calibration minus - CALM: u9, - reserved13: u4, - /// Use a 16-second calibration cycle period - CALW16: packed union { + /// Clears the FIFO Underrun Interrupt flag + CFUIF: packed union { raw: u1, - value: CALW16, + value: CFUIF, }, - /// Use an 8-second calibration cycle period - CALW8: packed union { + /// Clears the Transfer Error Interrupt Flag + CTERRIF: packed union { raw: u1, - value: CALW8, + value: CTERRIF, }, - /// Increase frequency of RTC by 488.5 ppm - CALP: packed union { + /// Clears Register Reload Interrupt Flag + CRRIF: packed union { raw: u1, - value: CALP, + value: CRRIF, }, - padding: u16, + padding: u28, }), - /// Tamper configuration register - TAMPCR: mmio.Mmio(packed struct(u32) { - /// Tamper detection enable - TAMPE: u1, - /// Active level for tamper - TAMPTRG: packed union { - raw: u1, - value: TAMPTRG, - }, - /// Tamper interrupt enable - TAMPIE: u1, - reserved7: u4, - /// Activate timestamp on tamper detection event - TAMPTS: u1, - /// Tamper sampling frequency - TAMPFREQ: packed union { - raw: u3, - value: TAMPFREQ, - }, - /// Tamper filter count - TAMPFLT: packed union { - raw: u2, - value: TAMPFLT, - }, - /// Tamper precharge duration - TAMPPRCH: packed union { - raw: u2, - value: TAMPPRCH, - }, - /// Tamper pull-up disable - TAMPPUDIS: packed union { - raw: u1, - value: TAMPPUDIS, - }, - /// Tamper interrupt enable - TAMPXIE: u1, - /// Tamper no erase - TAMPXNOERASE: u1, - /// Tamper mask flag - TAMPXMF: u1, - padding: u13, + /// Line Interrupt Position Configuration Register + LIPCR: mmio.Mmio(packed struct(u32) { + /// Line Interrupt Position + LIPOS: u11, + padding: u21, }), - /// Alarm sub second register - ALRMSSR: [2]mmio.Mmio(packed struct(u32) { - /// Sub seconds value - SS: u15, - reserved24: u9, - /// Mask the most-significant bits starting at this bit - MASKSS: u4, - padding: u4, + /// Current Position Status Register + CPSR: mmio.Mmio(packed struct(u32) { + /// Current Y Position + CYPOS: u16, + /// Current X Position + CXPOS: u16, }), - /// Option register - OR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Timestamp mapping - TSINSEL: u2, - /// RTC_ALARM on PC13 output type - RTC_ALARM_TYPE: u1, + /// Current Display Status Register + CDSR: mmio.Mmio(packed struct(u32) { + /// Vertical Data Enable display Status + VDES: u1, + /// Horizontal Data Enable display Status + HDES: u1, + /// Vertical Synchronization display Status + VSYNCS: u1, + /// Horizontal Synchronization display Status + HSYNCS: u1, padding: u28, }), - /// Backup register - BKPR: [32]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, - }), + reserved132: [56]u8, + /// Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR + LAYER: u32, }; }; - pub const pwr_f0 = struct { - pub const PDDS = enum(u1) { - /// Enter Stop mode when the CPU enters deepsleep - STOP_MODE = 0x0, - /// Enter Standby mode when the CPU enters deepsleep - STANDBY_MODE = 0x1, - }; - - /// Power control - pub const PWR = extern struct { - /// power control register + pub const mdios_v1 = struct { + /// Management data input/output slave + pub const MDIOS = extern struct { + /// MDIOS configuration register CR: mmio.Mmio(packed struct(u32) { - /// Low-power deep sleep - LPDS: u1, - /// Power down deepsleep - PDDS: packed union { - raw: u1, - value: PDDS, - }, - /// Clear wakeup flag - CWUF: u1, - /// Clear standby flag - CSBF: u1, - /// Power voltage detector enable - PVDE: u1, - /// PVD level selection - PLS: u3, - /// Disable backup domain write protection - DBP: u1, - padding: u23, + /// Peripheral enable + EN: u1, + /// Register write interrupt enable + WRIE: u1, + /// Register Read Interrupt Enable + RDIE: u1, + /// Error interrupt enable + EIE: u1, + reserved7: u3, + /// Disable Preamble Check + DPC: u1, + /// Slaves's address + PORT_ADDRESS: u5, + padding: u19, }), - /// power control/status register - CSR: mmio.Mmio(packed struct(u32) { - /// Wakeup flag - WUF: u1, - /// Standby flag - SBF: u1, - /// PVD output - PVDO: u1, - /// VREFINT reference voltage ready - VREFINTRDY: u1, - reserved8: u4, - /// Enable WKUP pin 1 - EWUP: u1, - padding: u23, + /// MDIOS write flag register + WRFR: mmio.Mmio(packed struct(u32) { + /// Write flags for MDIO registers 0 to 31 + WRF: u32, + }), + /// MDIOS clear write flag register + CWRFR: mmio.Mmio(packed struct(u32) { + /// Clear the write flag + CWRF: u32, + }), + /// MDIOS read flag register + RDFR: mmio.Mmio(packed struct(u32) { + /// Read flags for MDIO registers 0 to 31 + RDF: u32, + }), + /// MDIOS clear read flag register + CRDFR: mmio.Mmio(packed struct(u32) { + /// Clear the read flag + CRDF: u32, + }), + /// MDIOS status register + SR: mmio.Mmio(packed struct(u32) { + /// Preamble error flag + PERF: u1, + /// Start error flag + SERF: u1, + /// Turnaround error flag + TERF: u1, + padding: u29, + }), + /// MDIOS clear flag register + CLRFR: mmio.Mmio(packed struct(u32) { + /// Clear the preamble error flag + CPERF: u1, + /// Clear the start error flag + CSERF: u1, + /// Clear the turnaround error flag + CTERF: u1, + padding: u29, + }), + reserved256: [228]u8, + /// MDIOS input data register %s + DINR: [32]mmio.Mmio(packed struct(u32) { + /// Input data received from MDIO Master during write frames + DIN: u16, + padding: u16, + }), + /// MDIOS output data register %s + DOUTR: [32]mmio.Mmio(packed struct(u32) { + /// Output data sent to MDIO Master during read frames + DOUT: u16, + padding: u16, }), }; }; - pub const rcc_wb = struct { - pub const ADCSEL = enum(u2) { - /// No clock selected - DISABLE = 0x0, - PLLSAI1_R = 0x1, - PLL1_P = 0x2, - /// SYSCLK clock selected - SYS = 0x3, - }; - - pub const CLK48SEL = enum(u2) { - /// HSI48 clock selected - HSI48 = 0x0, - /// PLLSAI1_Q aka PLL48M1CLK clock selected - PLLSAI1_Q = 0x1, - /// PLL_Q aka PLL48M2CLK clock selected - PLL1_Q = 0x2, - /// MSI clock selected - MSI = 0x3, - }; - - pub const HPRE = enum(u4) { - /// DCLK not divided - Div1 = 0x0, - /// hclk = SYSCLK divided by 3 - Div3 = 0x1, - /// hclk = SYSCLK divided by 5 - Div5 = 0x2, - /// hclk = SYSCLK divided by 6 - Div6 = 0x5, - /// hclk = SYSCLK divided by 8 - Div10 = 0x6, - /// hclk = SYSCLK divided by 32 - Div32 = 0x7, - /// hclk = SYSCLK divided by 2 - Div2 = 0x8, - /// hclk = SYSCLK divided by 4 - Div4 = 0x9, - /// hclk = SYSCLK divided by 8 - Div8 = 0xa, - /// hclk = SYSCLK divided by 16 - Div16 = 0xb, - /// hclk = SYSCLK divided by 64 - Div64 = 0xc, - /// hclk = SYSCLK divided by 128 - Div128 = 0xd, - /// hclk = SYSCLK divided by 256 - Div256 = 0xe, - /// hclk = SYSCLK divided by 256 - Div512 = 0xf, - _, - }; - - pub const HSEPRE = enum(u1) { - Div1 = 0x0, - Div2 = 0x1, - }; - - pub const I2C1SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - _, - }; - - pub const I2C3SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - _, - }; - - pub const LPTIM1SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// LSI clock selected - LSI = 0x1, - /// HSI clock selected - HSI = 0x2, - /// LSE clock selected - LSE = 0x3, - }; - - pub const LPTIM2SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// LSI clock selected - LSI = 0x1, - /// HSI clock selected - HSI = 0x2, - /// LSE clock selected - LSE = 0x3, - }; - - pub const LPUART1SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - HSE = 0x3, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCOPRE = enum(u3) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x1, - /// Division by 4 - Div4 = 0x2, - /// Division by 8 - Div8 = 0x3, - /// Division by 16 - Div16 = 0x4, - _, - }; - - pub const MCOSEL = enum(u4) { - /// No clock - DISABLE = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// MSI oscillator clock selected - MSI = 0x2, - /// HSI oscillator clock selected - HSI = 0x3, - /// HSE clock selected (after stabilization, after HSERDY = 1) - HSE = 0x4, - /// PLL clock selected - PLL_R = 0x5, - /// LSI1 oscillator clock selected - LSI1 = 0x6, - /// LSI2 oscillator clock selected - LSI2 = 0x7, - /// LSE oscillator clock selected - LSE = 0x8, - /// HSI48 oscillator clock selected - HSI48 = 0x9, - /// HSE clock selected (before stabilization, after HSEON = 1) - HSE_UNSTABLE = 0xc, - _, - }; - - pub const MSIRANGE = enum(u4) { - /// range 0 around 100 kHz - Range100K = 0x0, - /// range 1 around 200 kHz - Range200K = 0x1, - /// range 2 around 400 kHz - Range400K = 0x2, - /// range 3 around 800 kHz - Range800K = 0x3, - /// range 4 around 1 MHz - Range1M = 0x4, - /// range 5 around 2 MHz - Range2M = 0x5, - /// range 6 around 4 MHz - Range4M = 0x6, - /// range 7 around 8 MHz - Range8M = 0x7, - /// range 8 around 16 MHz - Range16M = 0x8, - /// range 9 around 24 MHz - Range24M = 0x9, - /// range 10 around 32 MHz - Range32M = 0xa, - /// range 11 around 48 MHz - Range48M = 0xb, - _, + pub const octospi_v1 = struct { + pub const FlashSelect = enum(u1) { + /// FLASH 1 selected (data exchanged over IO[3:0]) + FlashOne = 0x0, + /// FLASH 2 selected (data exchanged over IO[7:4]) + FlashTwo = 0x1, }; - pub const PLLM = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, + pub const FunctionalMode = enum(u2) { + /// Indirect-write mode + IndirectWrite = 0x0, + /// Indirect-read mode + IndirectRead = 0x1, + /// Automatic status-polling mode + AutoStatusPolling = 0x2, + /// Memory-mapped mode + MemoryMapped = 0x3, }; - pub const PLLN = enum(u7) { - Mul6 = 0x6, - Mul7 = 0x7, - Mul8 = 0x8, - Mul9 = 0x9, - Mul10 = 0xa, - Mul11 = 0xb, - Mul12 = 0xc, - Mul13 = 0xd, - Mul14 = 0xe, - Mul15 = 0xf, - Mul16 = 0x10, - Mul17 = 0x11, - Mul18 = 0x12, - Mul19 = 0x13, - Mul20 = 0x14, - Mul21 = 0x15, - Mul22 = 0x16, - Mul23 = 0x17, - Mul24 = 0x18, - Mul25 = 0x19, - Mul26 = 0x1a, - Mul27 = 0x1b, - Mul28 = 0x1c, - Mul29 = 0x1d, - Mul30 = 0x1e, - Mul31 = 0x1f, - Mul32 = 0x20, - Mul33 = 0x21, - Mul34 = 0x22, - Mul35 = 0x23, - Mul36 = 0x24, - Mul37 = 0x25, - Mul38 = 0x26, - Mul39 = 0x27, - Mul40 = 0x28, - Mul41 = 0x29, - Mul42 = 0x2a, - Mul43 = 0x2b, - Mul44 = 0x2c, - Mul45 = 0x2d, - Mul46 = 0x2e, - Mul47 = 0x2f, - Mul48 = 0x30, - Mul49 = 0x31, - Mul50 = 0x32, - Mul51 = 0x33, - Mul52 = 0x34, - Mul53 = 0x35, - Mul54 = 0x36, - Mul55 = 0x37, - Mul56 = 0x38, - Mul57 = 0x39, - Mul58 = 0x3a, - Mul59 = 0x3b, - Mul60 = 0x3c, - Mul61 = 0x3d, - Mul62 = 0x3e, - Mul63 = 0x3f, - Mul64 = 0x40, - Mul65 = 0x41, - Mul66 = 0x42, - Mul67 = 0x43, - Mul68 = 0x44, - Mul69 = 0x45, - Mul70 = 0x46, - Mul71 = 0x47, - Mul72 = 0x48, - Mul73 = 0x49, - Mul74 = 0x4a, - Mul75 = 0x4b, - Mul76 = 0x4c, - Mul77 = 0x4d, - Mul78 = 0x4e, - Mul79 = 0x4f, - Mul80 = 0x50, - Mul81 = 0x51, - Mul82 = 0x52, - Mul83 = 0x53, - Mul84 = 0x54, - Mul85 = 0x55, - Mul86 = 0x56, - Mul87 = 0x57, - Mul88 = 0x58, - Mul89 = 0x59, - Mul90 = 0x5a, - Mul91 = 0x5b, - Mul92 = 0x5c, - Mul93 = 0x5d, - Mul94 = 0x5e, - Mul95 = 0x5f, - Mul96 = 0x60, - Mul97 = 0x61, - Mul98 = 0x62, - Mul99 = 0x63, - Mul100 = 0x64, - Mul101 = 0x65, - Mul102 = 0x66, - Mul103 = 0x67, - Mul104 = 0x68, - Mul105 = 0x69, - Mul106 = 0x6a, - Mul107 = 0x6b, - Mul108 = 0x6c, - Mul109 = 0x6d, - Mul110 = 0x6e, - Mul111 = 0x6f, - Mul112 = 0x70, - Mul113 = 0x71, - Mul114 = 0x72, - Mul115 = 0x73, - Mul116 = 0x74, - Mul117 = 0x75, - Mul118 = 0x76, - Mul119 = 0x77, - Mul120 = 0x78, - Mul121 = 0x79, - Mul122 = 0x7a, - Mul123 = 0x7b, - Mul124 = 0x7c, - Mul125 = 0x7d, - Mul126 = 0x7e, - Mul127 = 0x7f, - _, + pub const LatencyMode = enum(u1) { + /// Variable initial latency + Variable = 0x0, + /// Fixed latency + Fixed = 0x1, }; - pub const PLLP = enum(u5) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, - Div17 = 0x10, - Div18 = 0x11, - Div19 = 0x12, - Div20 = 0x13, - Div21 = 0x14, - Div22 = 0x15, - Div23 = 0x16, - Div24 = 0x17, - Div25 = 0x18, - Div26 = 0x19, - Div27 = 0x1a, - Div28 = 0x1b, - Div29 = 0x1c, - Div30 = 0x1d, - Div31 = 0x1e, - _, + pub const MatchMode = enum(u1) { + /// AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register. + MatchAnd = 0x0, + /// OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register. + MatchOr = 0x1, }; - pub const PLLQ = enum(u3) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, + pub const MemType = enum(u3) { + /// Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes. + Micron = 0x0, + /// Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes. + Macronix = 0x1, + /// Standard mode + B_Standard = 0x2, + /// Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping. + MacronixRam = 0x3, + /// HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected. + HyperBusMemory = 0x4, + /// HyperBus register mode, addressing register space. The memory-mapped accesses in. this mode must be non-cacheable, or Indirect read/write modes must be used. + HyperBusRegister = 0x5, _, }; - pub const PLLR = enum(u3) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, + pub const PhaseMode = enum(u3) { + /// No alternate bytes + None = 0x0, + /// Alternate bytes on a single line + OneLine = 0x1, + /// Alternate bytes on two lines + TwoLines = 0x2, + /// Alternate bytes on four lines + FourLines = 0x3, + /// Alternate bytes on eight lines + EightLines = 0x4, _, }; - pub const PLLSRC = enum(u2) { - /// No clock selected as PLL entry clock source - DISABLE = 0x0, - /// MSI selected as PLL entry clock source - MSI = 0x1, - /// HSI selected as PLL entry clock source - HSI = 0x2, - /// HSE selected as PLL entry clock source - HSE = 0x3, + pub const SampleShift = enum(u1) { + /// No shift + None = 0x0, + /// 1/2 cycle shift + HalfCycle = 0x1, }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, + pub const SizeInBits = enum(u2) { + /// 8-bit alternate bytes + @"8Bit" = 0x0, + /// 16-bit alternate bytes + @"16Bit" = 0x1, + /// 24-bit alternate bytes + @"24Bit" = 0x2, + /// 32-bit alternate bytes + @"32Bit" = 0x3, }; - pub const RNGSEL = enum(u2) { - /// CLK48 - CLK48 = 0x0, - /// LSI clock selected - LSI = 0x1, - /// LSE clock selected - LSE = 0x2, + pub const Threshold = enum(u5) { + /// FTF is set if there are one or more free bytes available to be written to in the FIFO in Indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in Indirect-read mode. + NeedOneByte = 0x0, + /// FTF is set if there are two or more free bytes available to be written to in the FIFO in Indirect‑write mode, or if there are two or more valid bytes can be read from the FIFO in Indirect-read mode. + NeedTwoBytes = 0x1, + /// FTF is set if there are 32 free bytes available to be written to in the FIFO in Indirect-write mode, or if there are 32 valid bytes can be read from the FIFO in Indirect-read mode. + NeedThirtyTwoBytes = 0x1f, _, }; - pub const RTCSEL = enum(u2) { - /// No clock selected - DISABLE = 0x0, - /// LSE oscillator clock selected - LSE = 0x1, - /// LSI oscillator clock selected - LSI = 0x2, - /// HSE oscillator clock divided by 32 selected - HSE = 0x3, - }; - - pub const SAI1SEL = enum(u2) { - PLLSAI1_P = 0x0, - PLL1_P = 0x1, - HSI = 0x2, - SAI1_EXTCLK = 0x3, - }; - - pub const SW = enum(u2) { - MSI = 0x0, - HSI = 0x1, - HSE = 0x2, - PLL1_R = 0x3, - }; - - pub const USART1SEL = enum(u2) { - /// PCLK clock selected - PCLK2 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - HSE = 0x3, - }; - - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register + /// OctoSPI + pub const OCTOSPI = extern struct { + /// control register CR: mmio.Mmio(packed struct(u32) { - /// MSI clock enable - MSION: u1, - /// MSI clock ready flag - MSIRDY: u1, - /// MSI clock PLL enable - MSIPLLEN: u1, - reserved4: u1, - /// MSI clock ranges - MSIRANGE: packed union { - raw: u4, - value: MSIRANGE, + /// Enable This bit enables the OCTOSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case. this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active. + EN: u1, + /// Abort request. This bit aborts the ongoing command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0. + ABORT: u1, + /// DMA enable In Indirect mode, the DMA can be used to input or output data via DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write. this bit during DMA operation. + DMAEN: u1, + /// Timeout counter enable. This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter. + TCEN: u1, + reserved6: u2, + /// Dual-memory configuration. This bit activates the dual-memory configuration, where two external devices are used simultaneously to double the throughput and the capacity + DMM: u1, + /// Flash select. This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in single-memory configuration (when DMM = 0). This bit is ignored when DMM = 1 or when Octal-SPI mode is selected. + FSEL: packed union { + raw: u1, + value: FlashSelect, + }, + /// FIFO threshold level. This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[4:0] value. + FTHRES: packed union { + raw: u5, + value: Threshold, }, - /// HSI clock enabled - HSION: u1, - /// HSI always enable for peripheral kernels - HSIKERON: u1, - /// HSI clock ready flag - HSIRDY: u1, - /// HSI automatic start from Stop - HSIASFS: u1, - /// HSI kernel clock ready flag for peripherals requests - HSIKERDY: u1, reserved16: u3, - /// HSE clock enabled - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE crystal oscillator bypass - HSEBYP: u1, - /// HSE Clock security system enable - CSSON: u1, - /// HSE sysclk and PLL M divider prescaler - HSEPRE: packed union { + /// Transfer error interrupt enable. This bit enables the transfer error interrupt. + TEIE: u1, + /// Transfer complete interrupt enable. This bit enables the transfer complete interrupt. + TCIE: u1, + /// FIFO threshold interrupt enable. This bit enables the FIFO threshold interrupt. + FTIE: u1, + /// Status match interrupt enable. This bit enables the status match interrupt. + SMIE: u1, + /// Timeout interrupt enable. This bit enables the timeout interrupt. + TOIE: u1, + reserved22: u1, + /// Automatic status-polling mode stop. This bit determines if the Automatic status-polling mode is stopped after a match. + APMS: u1, + /// Polling match mode. This bit indicates which method must be used to determine a match during the Automatic status-polling mode. + PMM: packed union { raw: u1, - value: HSEPRE, + value: MatchMode, + }, + reserved28: u4, + /// Functional mode. This field defines the OCTOSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state. + FMODE: packed union { + raw: u2, + value: FunctionalMode, }, + padding: u2, + }), + reserved8: [4]u8, + /// device configuration register 1 + DCR1: mmio.Mmio(packed struct(u32) { + /// Mode 0/Mode 3 This bit indicates the level taken by the CLK between commands (when NCS = 1). + CKMODE: u1, + /// Free running clock. This bit configures the free running clock. + FRCK: u1, + reserved3: u1, + /// Delay block bypass + DLYBYP: u1, + reserved8: u4, + /// Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (NCS) must remain high between commands issued to the external device. ... + CSHT: u6, + reserved16: u2, + /// Device size. This field defines the size of the external device using the following formula: Number of bytes in device = 2[DEVSIZE+1]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes. In Regular-command protocol, if DMM = 1, DEVSIZE[4:0] indicates the total capacity of the two devices together. + DEVSIZE: u5, reserved24: u3, - /// Main PLL enable - PLLON: u1, - /// Main PLL clock ready flag - PLLRDY: u1, - /// SAI1 PLL enable - PLLSAI1ON: u1, - /// SAI1 PLL clock ready flag - PLLSAI1RDY: u1, - padding: u4, + /// Memory type. This bit indicates the type of memory to be supported. Note: In. this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP[2:0] for memories different from Micron. Others: Reserved + MTYP: packed union { + raw: u3, + value: MemType, + }, + padding: u5, }), - /// Internal clock sources calibration register - ICSCR: mmio.Mmio(packed struct(u32) { - /// MSI clock calibration - MSICAL: u8, - /// MSI clock trimming - MSITRIM: u8, - /// HSI clock calibration - HSICAL: u8, - /// HSI clock trimming - HSITRIM: u7, - padding: u1, + /// device configuration register 2 + DCR2: mmio.Mmio(packed struct(u32) { + /// Clock prescaler. This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). 2: FCLK = FKERNEL/3 ... 255: FCLK = FKERNEL/256 For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low one cycle longer than it stays high. + PRESCALER: u8, + reserved16: u8, + /// Wrap size. This field indicates the wrap size to which the memory is configured. For memories which have a separate command for wrapped instructions, this field indicates the wrap-size associated with the command held in the OCTOSPI1_WPIR register. 110-111: Reserved + WRAPSIZE: u3, + padding: u13, }), - /// Clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u2, - value: SW, + /// device configuration register 3 + DCR3: mmio.Mmio(packed struct(u32) { + /// Maximum transfer + MAXTRAN: u8, + reserved16: u8, + /// NCS boundary. This field enables the transaction boundary feature. When active, a minimum value of 3 is recommended. The NCS is released on each boundary of 2CSBOUND bytes. others: NCS boundary set to 2CSBOUND bytes + CSBOUND: u5, + padding: u11, + }), + /// device configuration register 4 + DCR4: mmio.Mmio(packed struct(u32) { + /// Refresh rate. This field enables the refresh rate feature. The NCS is released every REFRESH + 1 clock cycles for writes, and REFRESH + 4 clock cycles for reads. Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in Single-, Dual- or Quad-SPI mode, because the byte transmission must be completed. others: Maximum communication length is set to REFRESH + 1 clock cycles. + REFRESH: u32, + }), + reserved32: [8]u8, + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Transfer error flag. This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode. It is cleared by writing 1 to CTEF. + TEF: u1, + /// Transfer complete flag. This bit is set in Indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF. + TCF: u1, + /// FIFO threshold flag In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete. It is cleared automatically as soon as the threshold condition is no longer true. In Automatic status-polling mode, this bit is set every time the status register is read, and the bit is cleared when the data register is read. + FTF: u1, + /// Status match flag. This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (PSMAR). It is cleared by writing 1 to CSMF. + SMF: u1, + /// Timeout flag. This bit is set when timeout occurs. It is cleared by writing 1 to CTOF. + TOF: u1, + /// Busy. This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty. + BUSY: u1, + reserved8: u2, + /// FIFO level. This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 32 when it is full. In Automatic status-polling mode, FLEVEL is zero. + FLEVEL: u6, + padding: u18, + }), + /// flag clear register + FCR: mmio.Mmio(packed struct(u32) { + /// Clear transfer error flag Writing 1 clears the TEF flag in the SR register. + CTEF: u1, + /// Clear transfer complete flag Writing 1 clears the TCF flag in the SR register. + CTCF: u1, + reserved3: u1, + /// Clear status match flag Writing 1 clears the SMF flag in the SR register. + CSMF: u1, + /// Clear timeout flag Writing 1 clears the TOF flag in the SR register. + CTOF: u1, + padding: u27, + }), + reserved64: [24]u8, + /// data length register + DLR: mmio.Mmio(packed struct(u32) { + /// [31: 0]: Data length Number of data to be retrieved (value+1) in Indirect and Automatic status-polling modes. A value not greater than three (indicating 4 bytes) must be used for Automatic status-polling mode. All 1’s in Indirect mode means undefined length, where OCTOSPI continues until the end of the memory, as defined by DEVSIZE. 0x0000_0000: 1 byte is to be transferred. 0x0000_0001: 2 bytes are to be transferred. 0x0000_0002: 3 bytes are to be transferred. 0x0000_0003: 4 bytes are to be transferred. ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred. 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred. 0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F. DL[0] is stuck at 1 in dual-memory configuration (DMM = 1) even when 0 is written to. this bit, thus assuring that each access transfers an even number of bytes. This field has no effect in Memory-mapped mode. + DL: u32, + }), + reserved72: [4]u8, + /// address register + AR: mmio.Mmio(packed struct(u32) { + /// Address to be sent to the external device. In HyperBus protocol, this field must be even as this protocol is 16-bit word oriented. In dual-memory configuration, AR[0] is forced to 1. Writes to. this field are ignored when BUSY = 1 or when FMODE = 11 (Memory-mapped mode). + ADDRESS: u32, + }), + reserved80: [4]u8, + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// [31: 0]: Data Data to be sent/received to/from the external SPI device In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In Indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In Automatic status-polling mode, this register contains the last data read from the external device (without masking). Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes. Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read 2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom of. this register: A byte read must read DATA[7:0] and a half-word read must read DATA[15:0]. + DATA: u32, + }), + reserved128: [44]u8, + /// polling status mask register + PSMKR: mmio.Mmio(packed struct(u32) { + /// Status mask Mask to be applied to the status bytes received in Automatic status-polling mode For bit n: + MASK: u32, + }), + reserved136: [4]u8, + /// polling status match register + PSMAR: mmio.Mmio(packed struct(u32) { + /// [31: 0]: Status match Value to be compared with the masked status register to get a match + MATCH: u32, + }), + reserved144: [4]u8, + /// polling interval register + PIR: mmio.Mmio(packed struct(u32) { + /// [15: 0]: Polling interval Number of CLK cycle between a read during the Automatic status-polling phases + INTERVAL: u16, + padding: u16, + }), + reserved256: [108]u8, + /// communication configuration register + CCR: mmio.Mmio(packed struct(u32) { + /// Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved + IMODE: packed union { + raw: u3, + value: PhaseMode, }, - /// System clock switch status - SWS: packed union { + /// Instruction double transfer rate. This bit sets the DTR mode for the instruction phase. + IDTR: u1, + /// Instruction size. This bit defines instruction size. + ISIZE: packed union { raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, + value: SizeInBits, }, - /// PB low-speed prescaler (APB1) - PPRE1: packed union { + reserved8: u2, + /// Address mode. This field defines the address phase mode of operation. 101-111: Reserved + ADMODE: packed union { raw: u3, - value: PPRE, + value: PhaseMode, }, - /// APB high-speed prescaler (APB2) - PPRE2: packed union { + /// Address double transfer rate. This bit sets the DTR mode for the address phase. + ADDTR: u1, + /// Address size. This field defines address size. + ADSIZE: packed union { + raw: u2, + value: SizeInBits, + }, + reserved16: u2, + /// Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved + ABMODE: packed union { raw: u3, - value: PPRE, + value: PhaseMode, }, - reserved15: u1, - /// Wakeup from Stop and CSS backup clock selection - STOPWUCK: u1, - /// AHB prescaler flag - HPREF: u1, - /// APB1 prescaler flag - PPRE1F: u1, - /// APB2 prescaler flag - PPRE2F: u1, - reserved24: u5, - /// Microcontroller clock output - MCOSEL: packed union { - raw: u4, - value: MCOSEL, + /// Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase. This field can be written only when BUSY = 0. + ABDTR: u1, + /// Alternate bytes size. This bit defines alternate bytes size. + ABSIZE: packed union { + raw: u2, + value: SizeInBits, }, - /// Microcontroller clock output prescaler - MCOPRE: packed union { + reserved24: u2, + /// Data mode. This field defines the data phase mode of operation. 101-111: Reserved + DMODE: packed union { raw: u3, - value: MCOPRE, + value: PhaseMode, + }, + /// Data double transfer rate. This bit sets the DTR mode for the data phase. + DDTR: u1, + reserved29: u1, + /// DQS enable. This bit enables the data strobe management. + DQSE: u1, + reserved31: u1, + /// Send instruction only once mode. This bit has no effect when IMODE = 00 (see ). + SIOO: u1, + }), + reserved264: [4]u8, + /// timing configuration register + TCR: mmio.Mmio(packed struct(u32) { + /// Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least six dummy cycles when using memories with DQS activated. + DCYC: u5, + reserved28: u23, + /// Delay hold quarter cycle + DHQC: u1, + reserved30: u1, + /// Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.) + SSHIFT: packed union { + raw: u1, + value: SampleShift, }, padding: u1, }), - /// PLLSYS configuration register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// Main PLL, PLLSAI1 and PLLSAI2 entry clock source - PLLSRC: packed union { + reserved272: [4]u8, + /// instruction register + IR: mmio.Mmio(packed struct(u32) { + /// Instruction to be sent to the external SPI device + INSTRUCTION: u32, + }), + reserved288: [12]u8, + /// alternate bytes register + ABR: mmio.Mmio(packed struct(u32) { + /// Alternate bytes + ALTERNATE: u32, + }), + reserved304: [12]u8, + /// low-power timeout register + LPTR: mmio.Mmio(packed struct(u32) { + /// [15: 0]: Timeout period After each access in Memory-mapped mode, the OCTOSPI prefetches the subsequent bytes and hold them in the FIFO. This field indicates how many CLK cycles the OCTOSPI waits after the clock becomes inactive and until it raises the NCS, putting the external device in a lower-consumption state. + TIMEOUT: u16, + padding: u16, + }), + reserved320: [12]u8, + /// wrap communication configuration register + WPCCR: mmio.Mmio(packed struct(u32) { + /// Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved + IMODE: packed union { + raw: u3, + value: PhaseMode, + }, + /// Instruction double transfer rate. This bit sets the DTR mode for the instruction phase. + IDTR: u1, + /// Instruction size. This field defines instruction size. + ISIZE: packed union { raw: u2, - value: PLLSRC, + value: SizeInBits, }, - reserved4: u2, - /// Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock - PLLM: packed union { + reserved8: u2, + /// Address mode. This field defines the address phase mode of operation. 101-111: Reserved + ADMODE: packed union { raw: u3, - value: PLLM, + value: PhaseMode, }, - reserved8: u1, - /// Main PLLSYS multiplication factor N - PLLN: packed union { - raw: u7, - value: PLLN, + /// Address double transfer rate. This bit sets the DTR mode for the address phase. + ADDTR: u1, + /// Address size. This field defines address size. + ADSIZE: packed union { + raw: u2, + value: SizeInBits, }, - reserved16: u1, - /// Main PLLSYSP output enable - PLLPEN: u1, - /// Main PLL division factor P for PPLSYSSAICLK - PLLP: packed union { - raw: u5, - value: PLLP, + reserved16: u2, + /// Alternate-byte mode. This field defines the alternate byte phase mode of operation. 101-111: Reserved + ABMODE: packed union { + raw: u3, + value: PhaseMode, + }, + /// Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase. + ABDTR: u1, + /// Alternate bytes size. This bit defines alternate bytes size. + ABSIZE: packed union { + raw: u2, + value: SizeInBits, }, reserved24: u2, - /// Main PLLSYSQ output enable - PLLQEN: u1, - /// Main PLLSYS division factor Q for PLLSYSUSBCLK - PLLQ: packed union { + /// Data mode. This field defines the data phase mode of operation. 101-111: Reserved + DMODE: packed union { raw: u3, - value: PLLQ, + value: PhaseMode, }, - /// Main PLLSYSR PLLCLK output enable - PLLREN: u1, - /// Main PLLSYS division factor R for SYSCLK (system clock) - PLLR: packed union { - raw: u3, - value: PLLR, + /// Data double transfer rate. This bit sets the DTR mode for the data phase. + DDTR: u1, + reserved29: u1, + /// DQS enable. This bit enables the data strobe management. + DQSE: u1, + padding: u2, + }), + reserved328: [4]u8, + /// wrap timing configuration register + WPTCR: mmio.Mmio(packed struct(u32) { + /// Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. + DCYC: u5, + reserved28: u23, + /// Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement. + DHQC: u1, + reserved30: u1, + /// Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1). + SSHIFT: packed union { + raw: u1, + value: SampleShift, }, + padding: u1, }), - /// PLLSAI1 configuration register - PLLSAI1CFGR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// SAIPLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, + reserved336: [4]u8, + /// wrap instruction register + WPIR: mmio.Mmio(packed struct(u32) { + /// [31: 0]: Instruction Instruction to be sent to the external SPI device + INSTRUCTION: u32, + }), + reserved352: [12]u8, + /// wrap alternate bytes register + WPABR: mmio.Mmio(packed struct(u32) { + /// [31: 0]: Alternate bytes Optional data to be sent to the external SPI device right after the address + ALTERNATE: u32, + }), + reserved384: [28]u8, + /// write communication configuration register + WCCR: mmio.Mmio(packed struct(u32) { + /// Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved + IMODE: packed union { + raw: u3, + value: PhaseMode, }, - reserved16: u1, - /// SAIPLL PLLSAI1CLK output enable - PLLPEN: u1, - /// SAI1PLL division factor P for PLLSAICLK (SAI1clock) - PLLP: packed union { - raw: u5, - value: PLLP, + /// Instruction double transfer rate. This bit sets the DTR mode for the instruction phase. + IDTR: u1, + /// Instruction size. This bit defines instruction size: + ISIZE: packed union { + raw: u2, + value: SizeInBits, }, - reserved24: u2, - /// SAIPLL PLLSAIUSBCLK output enable - PLLQEN: u1, - /// SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock) - PLLQ: packed union { + reserved8: u2, + /// Address mode. This field defines the address phase mode of operation. 101-111: Reserved + ADMODE: packed union { raw: u3, - value: PLLQ, + value: PhaseMode, }, - /// PLLSAI PLLADC1CLK output enable - PLLREN: u1, - /// PLLSAI division factor R for PLLADC1CLK (ADC clock) - PLLR: packed union { + /// Address double transfer rate. This bit sets the DTR mode for the address phase. + ADDTR: u1, + /// Address size. This field defines address size. + ADSIZE: packed union { + raw: u2, + value: SizeInBits, + }, + reserved16: u2, + /// Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved + ABMODE: packed union { raw: u3, - value: PLLR, + value: PhaseMode, + }, + /// Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate-bytes phase. + ABDTR: u1, + /// Alternate bytes size. This field defines alternate bytes size: + ABSIZE: packed union { + raw: u2, + value: SizeInBits, + }, + reserved24: u2, + /// Data mode. This field defines the data phase mode of operation. 101-111: Reserved + DMODE: packed union { + raw: u3, + value: PhaseMode, }, + /// data double transfer rate. This bit sets the DTR mode for the data phase. + DDTR: u1, + reserved29: u1, + /// DQS enable. This bit enables the data strobe management. + DQSE: u1, + padding: u2, }), - reserved24: [4]u8, - /// Clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI1 ready interrupt enable - LSI1RDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - /// MSI ready interrupt enable - MSIRDYIE: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// PLLSYS ready interrupt enable - PLLRDYIE: u1, - /// PLLSAI1 ready interrupt enable - PLLSAI1RDYIE: u1, - reserved9: u2, - /// LSE clock security system interrupt enable - LSECSSIE: u1, - /// HSI48 ready interrupt enable - HSI48RDYIE: u1, - /// LSI2 ready interrupt enable - LSI2RDYIE: u1, - padding: u20, + reserved392: [4]u8, + /// write timing configuration register + WTCR: mmio.Mmio(packed struct(u32) { + /// Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. + DCYC: u5, + padding: u27, }), - /// Clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI1 ready interrupt flag - LSI1RDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// MSI ready interrupt flag - MSIRDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// PLL ready interrupt flag - PLLRDYF: u1, - /// PLLSAI1 ready interrupt flag - PLLSAI1RDYF: u1, - reserved8: u1, - /// HSE Clock security system interrupt flag - HSECSSF: u1, - /// LSE Clock security system interrupt flag - LSECSSF: u1, - /// HSI48 ready interrupt flag - HSI48RDYF: u1, - /// LSI2 ready interrupt flag - LSI2RDYF: u1, - padding: u20, + reserved400: [4]u8, + /// write instruction register + WIR: mmio.Mmio(packed struct(u32) { + /// Instruction Instruction to be sent to the external SPI device + INSTRUCTION: u32, }), - /// Clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI1 ready interrupt clear - LSI1RDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// MSI ready interrupt clear - MSIRDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// PLL ready interrupt clear - PLLRDYC: u1, - /// PLLSAI1 ready interrupt clear - PLLSAI1RDYC: u1, - reserved8: u1, - /// HSE Clock security system interrupt clear - HSECSSC: u1, - /// LSE Clock security system interrupt clear - LSECSSC: u1, - /// HSI48 ready interrupt clear - HSI48RDYC: u1, - /// LSI2 ready interrupt clear - LSI2RDYC: u1, - padding: u20, + reserved416: [12]u8, + /// write alternate bytes register + WABR: mmio.Mmio(packed struct(u32) { + /// [31: 0]: Alternate bytes. Optional data to be sent to the external SPI device right after the address + ALTERNATE: u32, }), - /// Step Down converter control register - SMPSCR: mmio.Mmio(packed struct(u32) { - /// Step Down converter clock selection - SMPSSEL: u2, - reserved4: u2, - /// Step Down converter clock prescaler - SMPSDIV: u2, - reserved8: u2, - /// Step Down converter clock switch status - SMPSSWS: u2, - padding: u22, + reserved512: [92]u8, + /// OCTOSPI HyperBus latency configuration register + HLCR: mmio.Mmio(packed struct(u32) { + /// Latency mode. This bit selects the Latency mode. + LM: packed union { + raw: u1, + value: LatencyMode, + }, + /// Write zero latency. This bit enables zero latency on write operations. + WZL: u1, + reserved8: u6, + /// [7: 0]: Access time. Device access time expressed in number of communication clock cycles + TACC: u8, + /// Read write recovery time Device read write recovery time expressed in number of communication clock cycles + TRWR: u8, + padding: u8, }), - /// AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - /// DMAMUX reset - DMAMUX1RST: u1, - reserved12: u9, - /// CRC reset - CRCRST: u1, + }; + }; + + pub const octospi_v2 = struct { + pub const FlashSelect = enum(u1) { + /// FLASH 1 selected (data exchanged over IO[3:0]) + FlashOne = 0x0, + /// FLASH 2 selected (data exchanged over IO[7:4]) + FlashTwo = 0x1, + }; + + pub const FunctionalMode = enum(u2) { + /// Indirect-write mode + IndirectWrite = 0x0, + /// Indirect-read mode + IndirectRead = 0x1, + /// Automatic status-polling mode + AutoStatusPolling = 0x2, + /// Memory-mapped mode + MemoryMapped = 0x3, + }; + + pub const LatencyMode = enum(u1) { + /// Variable initial latency + Variable = 0x0, + /// Fixed latency + Fixed = 0x1, + }; + + pub const MatchMode = enum(u1) { + /// AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register. + MatchAnd = 0x0, + /// OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register. + MatchOr = 0x1, + }; + + pub const MemType = enum(u3) { + /// Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes. + Micron = 0x0, + /// Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes. + Macronix = 0x1, + /// Standard mode + B_Standard = 0x2, + /// Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping. + MacronixRam = 0x3, + /// HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected. + HyperBusMemory = 0x4, + /// HyperBus register mode, addressing register space. The memory-mapped accesses in. this mode must be non-cacheable, or Indirect read/write modes must be used. + HyperBusRegister = 0x5, + _, + }; + + pub const PhaseMode = enum(u3) { + /// No alternate bytes + None = 0x0, + /// Alternate bytes on a single line + OneLine = 0x1, + /// Alternate bytes on two lines + TwoLines = 0x2, + /// Alternate bytes on four lines + FourLines = 0x3, + /// Alternate bytes on eight lines + EightLines = 0x4, + _, + }; + + pub const SampleShift = enum(u1) { + /// No shift + None = 0x0, + /// 1/2 cycle shift + HalfCycle = 0x1, + }; + + pub const SizeInBits = enum(u2) { + /// 8-bit alternate bytes + @"8Bit" = 0x0, + /// 16-bit alternate bytes + @"16Bit" = 0x1, + /// 24-bit alternate bytes + @"24Bit" = 0x2, + /// 32-bit alternate bytes + @"32Bit" = 0x3, + }; + + pub const Threshold = enum(u5) { + /// FTF is set if there are one or more free bytes available to be written to in the FIFO in Indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in Indirect-read mode. + NeedOneByte = 0x0, + /// FTF is set if there are two or more free bytes available to be written to in the FIFO in Indirect‑write mode, or if there are two or more valid bytes can be read from the FIFO in Indirect-read mode. + NeedTwoBytes = 0x1, + /// FTF is set if there are 32 free bytes available to be written to in the FIFO in Indirect-write mode, or if there are 32 valid bytes can be read from the FIFO in Indirect-read mode. + NeedThirtyTwoBytes = 0x1f, + _, + }; + + /// OctoSPI + pub const OCTOSPI = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// Enable This bit enables the OCTOSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case. this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active. + EN: u1, + /// Abort request. This bit aborts the ongoing command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0. + ABORT: u1, + /// DMA enable In Indirect mode, the DMA can be used to input or output data via DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write. this bit during DMA operation. + DMAEN: u1, + /// Timeout counter enable. This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter. + TCEN: u1, + reserved6: u2, + /// Dual-memory configuration. This bit activates the dual-memory configuration, where two external devices are used simultaneously to double the throughput and the capacity + DMM: u1, + /// Flash select. This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in single-memory configuration (when DMM = 0). This bit is ignored when DMM = 1 or when Octal-SPI mode is selected. + FSEL: packed union { + raw: u1, + value: FlashSelect, + }, + /// FIFO threshold level. This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[4:0] value. + FTHRES: packed union { + raw: u5, + value: Threshold, + }, reserved16: u3, - /// Touch Sensing Controller reset - TSCRST: u1, - padding: u15, + /// Transfer error interrupt enable. This bit enables the transfer error interrupt. + TEIE: u1, + /// Transfer complete interrupt enable. This bit enables the transfer complete interrupt. + TCIE: u1, + /// FIFO threshold interrupt enable. This bit enables the FIFO threshold interrupt. + FTIE: u1, + /// Status match interrupt enable. This bit enables the status match interrupt. + SMIE: u1, + /// Timeout interrupt enable. This bit enables the timeout interrupt. + TOIE: u1, + reserved22: u1, + /// Automatic status-polling mode stop. This bit determines if the Automatic status-polling mode is stopped after a match. + APMS: u1, + /// Polling match mode. This bit indicates which method must be used to determine a match during the Automatic status-polling mode. + PMM: packed union { + raw: u1, + value: MatchMode, + }, + reserved28: u4, + /// Functional mode. This field defines the OCTOSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state. + FMODE: packed union { + raw: u2, + value: FunctionalMode, + }, + padding: u2, }), - /// AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - reserved7: u2, - /// IO port H reset - GPIOHRST: u1, - reserved13: u5, - /// ADC reset - ADCRST: u1, + reserved8: [4]u8, + /// device configuration register 1 + DCR1: mmio.Mmio(packed struct(u32) { + /// Mode 0/Mode 3 This bit indicates the level taken by the CLK between commands (when NCS = 1). + CKMODE: u1, + /// Free running clock. This bit configures the free running clock. + FRCK: u1, + reserved3: u1, + /// Delay block bypass + DLYBYP: u1, + reserved8: u4, + /// Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (NCS) must remain high between commands issued to the external device. ... + CSHT: u6, reserved16: u2, - /// AES1 hardware accelerator reset - AES1RST: u1, - padding: u15, - }), - /// AHB3 peripheral reset register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Quad SPI memory interface reset - QUADSPIRST: u1, - reserved16: u7, - /// PKA interface reset - PKARST: u1, - /// AES2 interface reset - AES2RST: u1, - /// RNG interface reset - RNGRST: u1, - /// HSEM interface reset - HSEMRST: u1, - /// IPCC interface reset - IPCCRST: u1, - reserved25: u4, - /// Flash interface reset - FLASHRST: u1, - padding: u6, - }), - reserved56: [4]u8, - /// APB1 peripheral reset register 1 - APB1RSTR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer reset - TIM2RST: u1, - reserved9: u8, - /// LCD interface reset - LCDRST: u1, - reserved14: u4, - /// SPI2 reset - SPI2RST: u1, - reserved21: u6, - /// I2C1 reset - I2C1RST: u1, - reserved23: u1, - /// I2C3 reset - I2C3RST: u1, - /// CRS reset - CRSRST: u1, - reserved26: u1, - /// USB FS reset - USBRST: u1, - reserved31: u4, - /// Low Power Timer 1 reset - LPTIM1RST: u1, - }), - /// APB1 peripheral reset register 2 - APB1RSTR2: mmio.Mmio(packed struct(u32) { - /// Low-power UART 1 reset - LPUART1RST: u1, - reserved5: u4, - /// Low-power timer 2 reset - LPTIM2RST: u1, - padding: u26, - }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI1 reset - SPI1RST: u1, - reserved14: u1, - /// USART1 reset - USART1RST: u1, - reserved17: u2, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - reserved21: u2, - /// Serial audio interface 1 (SAI1) reset - SAI1RST: u1, - padding: u10, - }), - /// APB3 peripheral reset register - APB3RSTR: mmio.Mmio(packed struct(u32) { - /// Radio system BLE reset - RFRST: u1, - padding: u31, - }), - /// AHB1 peripheral clock enable register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// DMAMUX clock enable - DMAMUX1EN: u1, - reserved12: u9, - /// CPU1 CRC clock enable - CRCEN: u1, - reserved16: u3, - /// Touch Sensing Controller clock enable - TSCEN: u1, - padding: u15, + /// Device size. This field defines the size of the external device using the following formula: Number of bytes in device = 2[DEVSIZE+1]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes. In Regular-command protocol, if DMM = 1, DEVSIZE[4:0] indicates the total capacity of the two devices together. + DEVSIZE: u5, + reserved24: u3, + /// Memory type. This bit indicates the type of memory to be supported. Note: In. this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP[2:0] for memories different from Micron. Others: Reserved + MTYP: packed union { + raw: u3, + value: MemType, + }, + padding: u5, }), - /// AHB2 peripheral clock enable register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port C clock enable - GPIOCEN: u1, - /// IO port D clock enable - GPIODEN: u1, - /// IO port E clock enable - GPIOEEN: u1, - reserved7: u2, - /// IO port H clock enable - GPIOHEN: u1, - reserved13: u5, - /// ADC clock enable - ADCEN: u1, - reserved16: u2, - /// AES1 accelerator clock enable - AES1EN: u1, - padding: u15, + /// device configuration register 2 + DCR2: mmio.Mmio(packed struct(u32) { + /// Clock prescaler. This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). 2: FCLK = FKERNEL/3 ... 255: FCLK = FKERNEL/256 For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low one cycle longer than it stays high. + PRESCALER: u8, + reserved16: u8, + /// Wrap size. This field indicates the wrap size to which the memory is configured. For memories which have a separate command for wrapped instructions, this field indicates the wrap-size associated with the command held in the OCTOSPI1_WPIR register. 110-111: Reserved + WRAPSIZE: u3, + padding: u13, }), - /// AHB3 peripheral clock enable register - AHB3ENR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// QUADSPIEN - QUADSPIEN: u1, - reserved16: u7, - /// PKAEN - PKAEN: u1, - /// AES2EN - AES2EN: u1, - /// RNGEN - RNGEN: u1, - /// HSEMEN - HSEMEN: u1, - /// IPCCEN - IPCCEN: u1, - reserved25: u4, - /// FLASHEN - FLASHEN: u1, - padding: u6, + /// device configuration register 3 + DCR3: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// NCS boundary. This field enables the transaction boundary feature. When active, a minimum value of 3 is recommended. The NCS is released on each boundary of 2CSBOUND bytes. others: NCS boundary set to 2CSBOUND bytes + CSBOUND: u5, + padding: u11, }), - reserved88: [4]u8, - /// APB1ENR1 - APB1ENR1: mmio.Mmio(packed struct(u32) { - /// CPU1 TIM2 timer clock enable - TIM2EN: u1, - reserved9: u8, - /// CPU1 LCD clock enable - LCDEN: u1, - /// CPU1 RTC APB clock enable - RTCAPBEN: u1, - /// CPU1 Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// CPU1 SPI2 clock enable - SPI2EN: u1, - reserved21: u6, - /// CPU1 I2C1 clock enable - I2C1EN: u1, - reserved23: u1, - /// CPU1 I2C3 clock enable - I2C3EN: u1, - /// CPU1 CRS clock enable - CRSEN: u1, - reserved26: u1, - /// CPU1 USB clock enable - USBEN: u1, - reserved31: u4, - /// CPU1 Low power timer 1 clock enable - LPTIM1EN: u1, + /// device configuration register 4 + DCR4: mmio.Mmio(packed struct(u32) { + /// Refresh rate. This field enables the refresh rate feature. The NCS is released every REFRESH + 1 clock cycles for writes, and REFRESH + 4 clock cycles for reads. Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in Single-, Dual- or Quad-SPI mode, because the byte transmission must be completed. others: Maximum communication length is set to REFRESH + 1 clock cycles. + REFRESH: u32, }), - /// APB1 peripheral clock enable register 2 - APB1ENR2: mmio.Mmio(packed struct(u32) { - /// CPU1 Low power UART 1 clock enable - LPUART1EN: u1, - reserved5: u4, - /// CPU1 LPTIM2EN - LPTIM2EN: u1, - padding: u26, + reserved32: [8]u8, + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Transfer error flag. This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode. It is cleared by writing 1 to CTEF. + TEF: u1, + /// Transfer complete flag. This bit is set in Indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF. + TCF: u1, + /// FIFO threshold flag In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete. It is cleared automatically as soon as the threshold condition is no longer true. In Automatic status-polling mode, this bit is set every time the status register is read, and the bit is cleared when the data register is read. + FTF: u1, + /// Status match flag. This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (PSMAR). It is cleared by writing 1 to CSMF. + SMF: u1, + /// Timeout flag. This bit is set when timeout occurs. It is cleared by writing 1 to CTOF. + TOF: u1, + /// Busy. This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty. + BUSY: u1, + reserved8: u2, + /// FIFO level. This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 32 when it is full. In Automatic status-polling mode, FLEVEL is zero. + FLEVEL: u6, + padding: u18, }), - /// APB2ENR - APB2ENR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// CPU1 TIM1 timer clock enable - TIM1EN: u1, - /// CPU1 SPI1 clock enable - SPI1EN: u1, - reserved14: u1, - /// CPU1 USART1clock enable - USART1EN: u1, - reserved17: u2, - /// CPU1 TIM16 timer clock enable - TIM16EN: u1, - /// CPU1 TIM17 timer clock enable - TIM17EN: u1, - reserved21: u2, - /// CPU1 SAI1 clock enable - SAI1EN: u1, - padding: u10, + /// flag clear register + FCR: mmio.Mmio(packed struct(u32) { + /// Clear transfer error flag Writing 1 clears the TEF flag in the SR register. + CTEF: u1, + /// Clear transfer complete flag Writing 1 clears the TCF flag in the SR register. + CTCF: u1, + reserved3: u1, + /// Clear status match flag Writing 1 clears the SMF flag in the SR register. + CSMF: u1, + /// Clear timeout flag Writing 1 clears the TOF flag in the SR register. + CTOF: u1, + padding: u27, }), - reserved104: [4]u8, - /// AHB1 peripheral clocks enable in Sleep and Stop modes register - AHB1SMENR: mmio.Mmio(packed struct(u32) { - /// CPU1 DMA1 clocks enable during Sleep and Stop modes - DMA1SMEN: u1, - /// CPU1 DMA2 clocks enable during Sleep and Stop modes - DMA2SMEN: u1, - /// CPU1 DMAMUX clocks enable during Sleep and Stop modes - DMAMUX1SMEN: u1, - reserved9: u6, - /// CPU1 SRAM1 interface clocks enable during Sleep and Stop modes - SRAM1SMEN: u1, - reserved12: u2, - /// CPU1 CRCSMEN - CRCSMEN: u1, - reserved16: u3, - /// CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes - TSCSMEN: u1, - padding: u15, + reserved64: [24]u8, + /// data length register + DLR: mmio.Mmio(packed struct(u32) { + /// [31: 0]: Data length Number of data to be retrieved (value+1) in Indirect and Automatic status-polling modes. A value not greater than three (indicating 4 bytes) must be used for Automatic status-polling mode. All 1’s in Indirect mode means undefined length, where OCTOSPI continues until the end of the memory, as defined by DEVSIZE. 0x0000_0000: 1 byte is to be transferred. 0x0000_0001: 2 bytes are to be transferred. 0x0000_0002: 3 bytes are to be transferred. 0x0000_0003: 4 bytes are to be transferred. ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred. 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred. 0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F. DL[0] is stuck at 1 in dual-memory configuration (DMM = 1) even when 0 is written to. this bit, thus assuring that each access transfers an even number of bytes. This field has no effect in Memory-mapped mode. + DL: u32, }), - /// AHB2 peripheral clocks enable in Sleep and Stop modes register - AHB2SMENR: mmio.Mmio(packed struct(u32) { - /// CPU1 IO port A clocks enable during Sleep and Stop modes - GPIOASMEN: u1, - /// CPU1 IO port B clocks enable during Sleep and Stop modes - GPIOBSMEN: u1, - /// CPU1 IO port C clocks enable during Sleep and Stop modes - GPIOCSMEN: u1, - /// CPU1 IO port D clocks enable during Sleep and Stop modes - GPIODSMEN: u1, - /// CPU1 IO port E clocks enable during Sleep and Stop modes - GPIOESMEN: u1, - reserved7: u2, - /// CPU1 IO port H clocks enable during Sleep and Stop modes - GPIOHSMEN: u1, - reserved13: u5, - /// CPU1 ADC clocks enable during Sleep and Stop modes - ADCFSSMEN: u1, - reserved16: u2, - /// CPU1 AES1 accelerator clocks enable during Sleep and Stop modes - AES1SMEN: u1, - padding: u15, + reserved72: [4]u8, + /// address register + AR: mmio.Mmio(packed struct(u32) { + /// Address to be sent to the external device. In HyperBus protocol, this field must be even as this protocol is 16-bit word oriented. In dual-memory configuration, AR[0] is forced to 1. Writes to. this field are ignored when BUSY = 1 or when FMODE = 11 (Memory-mapped mode). + ADDRESS: u32, }), - /// AHB3 peripheral clocks enable in Sleep and Stop modes register - AHB3SMENR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// QUADSPISMEN - QUADSPISMEN: u1, - reserved16: u7, - /// PKA accelerator clocks enable during CPU1 sleep mode - PKASMEN: u1, - /// AES2 accelerator clocks enable during CPU1 sleep mode - AES2SMEN: u1, - /// True RNG clocks enable during CPU1 sleep mode - RNGSMEN: u1, - reserved24: u5, - /// SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode - SRAM2SMEN: u1, - /// Flash interface clocks enable during CPU1 sleep mode - FLASHSMEN: u1, - padding: u6, + reserved80: [4]u8, + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// [31: 0]: Data Data to be sent/received to/from the external SPI device In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In Indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In Automatic status-polling mode, this register contains the last data read from the external device (without masking). Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes. Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read 2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom of. this register: A byte read must read DATA[7:0] and a half-word read must read DATA[15:0]. + DATA: u32, }), - reserved120: [4]u8, - /// APB1SMENR1 - APB1SMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clocks enable during CPU1 Sleep mode - TIM2SMEN: u1, - reserved9: u8, - /// LCD clocks enable during CPU1 Sleep mode - LCDSMEN: u1, - /// RTC APB clocks enable during CPU1 Sleep mode - RTCAPBSMEN: u1, - /// Window watchdog clocks enable during CPU1 Sleep mode - WWDGSMEN: u1, - reserved14: u2, - /// SPI2 clocks enable during CPU1 Sleep mode - SPI2SMEN: u1, - reserved21: u6, - /// I2C1 clocks enable during CPU1 Sleep mode - I2C1SMEN: u1, - reserved23: u1, - /// I2C3 clocks enable during CPU1 Sleep mode - I2C3SMEN: u1, - /// CRS clocks enable during CPU1 Sleep mode - CRSMEN: u1, - reserved26: u1, - /// USB FS clocks enable during CPU1 Sleep mode - USBSMEN: u1, - reserved31: u4, - /// Low power timer 1 clocks enable during CPU1 Sleep mode - LPTIM1SMEN: u1, + reserved128: [44]u8, + /// polling status mask register + PSMKR: mmio.Mmio(packed struct(u32) { + /// Status mask Mask to be applied to the status bytes received in Automatic status-polling mode For bit n: + MASK: u32, }), - /// APB1 peripheral clocks enable in Sleep and Stop modes register 2 - APB1SMENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clocks enable during CPU1 Sleep mode - LPUART1SMEN: u1, - reserved5: u4, - /// Low power timer 2 clocks enable during CPU1 Sleep mode - LPTIM2SMEN: u1, - padding: u26, + reserved136: [4]u8, + /// polling status match register + PSMAR: mmio.Mmio(packed struct(u32) { + /// [31: 0]: Status match Value to be compared with the masked status register to get a match + MATCH: u32, }), - /// APB2SMENR - APB2SMENR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 timer clocks enable during CPU1 Sleep mode - TIM1SMEN: u1, - /// SPI1 clocks enable during CPU1 Sleep mode - SPI1SMEN: u1, - reserved14: u1, - /// USART1clocks enable during CPU1 Sleep mode - USART1SMEN: u1, - reserved17: u2, - /// TIM16 timer clocks enable during CPU1 Sleep mode - TIM16SMEN: u1, - /// TIM17 timer clocks enable during CPU1 Sleep mode - TIM17SMEN: u1, - reserved21: u2, - /// SAI1 clocks enable during CPU1 Sleep mode - SAI1SMEN: u1, - padding: u10, + reserved144: [4]u8, + /// polling interval register + PIR: mmio.Mmio(packed struct(u32) { + /// [15: 0]: Polling interval Number of CLK cycle between a read during the Automatic status-polling phases + INTERVAL: u16, + padding: u16, }), - reserved136: [4]u8, - /// CCIPR - CCIPR: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SEL: packed union { - raw: u2, - value: USART1SEL, + reserved256: [108]u8, + /// communication configuration register + CCR: mmio.Mmio(packed struct(u32) { + /// Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved + IMODE: packed union { + raw: u3, + value: PhaseMode, }, - reserved10: u8, - /// LPUART1 clock source selection - LPUART1SEL: packed union { + /// Instruction double transfer rate. This bit sets the DTR mode for the instruction phase. + IDTR: u1, + /// Instruction size. This bit defines instruction size. + ISIZE: packed union { raw: u2, - value: LPUART1SEL, + value: SizeInBits, }, - /// I2C1 clock source selection - I2C1SEL: packed union { + reserved8: u2, + /// Address mode. This field defines the address phase mode of operation. 101-111: Reserved + ADMODE: packed union { + raw: u3, + value: PhaseMode, + }, + /// Address double transfer rate. This bit sets the DTR mode for the address phase. + ADDTR: u1, + /// Address size. This field defines address size. + ADSIZE: packed union { raw: u2, - value: I2C1SEL, + value: SizeInBits, }, reserved16: u2, - /// I2C3 clock source selection - I2C3SEL: packed union { - raw: u2, - value: I2C3SEL, + /// Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved + ABMODE: packed union { + raw: u3, + value: PhaseMode, }, - /// Low power timer 1 clock source selection - LPTIM1SEL: packed union { + /// Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase. This field can be written only when BUSY = 0. + ABDTR: u1, + /// Alternate bytes size. This bit defines alternate bytes size. + ABSIZE: packed union { raw: u2, - value: LPTIM1SEL, + value: SizeInBits, }, - /// Low power timer 2 clock source selection - LPTIM2SEL: packed union { - raw: u2, - value: LPTIM2SEL, + reserved24: u2, + /// Data mode. This field defines the data phase mode of operation. 101-111: Reserved + DMODE: packed union { + raw: u3, + value: PhaseMode, }, - /// SAI1 clock source selection - SAI1SEL: packed union { - raw: u2, - value: SAI1SEL, + /// Data double transfer rate. This bit sets the DTR mode for the data phase. + DDTR: u1, + reserved29: u1, + /// DQS enable. This bit enables the data strobe management. + DQSE: u1, + reserved31: u1, + /// Send instruction only once mode. This bit has no effect when IMODE = 00 (see ). + SIOO: u1, + }), + reserved264: [4]u8, + /// timing configuration register + TCR: mmio.Mmio(packed struct(u32) { + /// Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least six dummy cycles when using memories with DQS activated. + DCYC: u5, + reserved28: u23, + /// Delay hold quarter cycle + DHQC: u1, + reserved30: u1, + /// Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.) + SSHIFT: packed union { + raw: u1, + value: SampleShift, }, - reserved26: u2, - /// 48 MHz clock source selection - CLK48SEL: packed union { - raw: u2, - value: CLK48SEL, + padding: u1, + }), + reserved272: [4]u8, + /// instruction register + IR: mmio.Mmio(packed struct(u32) { + /// Instruction to be sent to the external SPI device + INSTRUCTION: u32, + }), + reserved288: [12]u8, + /// alternate bytes register + ABR: mmio.Mmio(packed struct(u32) { + /// Alternate bytes + ALTERNATE: u32, + }), + reserved304: [12]u8, + /// low-power timeout register + LPTR: mmio.Mmio(packed struct(u32) { + /// [15: 0]: Timeout period After each access in Memory-mapped mode, the OCTOSPI prefetches the subsequent bytes and hold them in the FIFO. This field indicates how many CLK cycles the OCTOSPI waits after the clock becomes inactive and until it raises the NCS, putting the external device in a lower-consumption state. + TIMEOUT: u16, + padding: u16, + }), + reserved320: [12]u8, + /// wrap communication configuration register + WPCCR: mmio.Mmio(packed struct(u32) { + /// Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved + IMODE: packed union { + raw: u3, + value: PhaseMode, }, - /// ADCs clock source selection - ADCSEL: packed union { + /// Instruction double transfer rate. This bit sets the DTR mode for the instruction phase. + IDTR: u1, + /// Instruction size. This field defines instruction size. + ISIZE: packed union { raw: u2, - value: ADCSEL, + value: SizeInBits, }, - /// RNG clock source selection - RNGSEL: packed union { - raw: u2, - value: RNGSEL, + reserved8: u2, + /// Address mode. This field defines the address phase mode of operation. 101-111: Reserved + ADMODE: packed union { + raw: u3, + value: PhaseMode, }, - }), - reserved144: [4]u8, - /// BDCR - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enable - LSEON: u1, - /// LSE oscillator ready - LSERDY: u1, - /// LSE oscillator bypass - LSEBYP: u1, - /// SE oscillator drive capability - LSEDRV: packed union { + /// Address double transfer rate. This bit sets the DTR mode for the address phase. + ADDTR: u1, + /// Address size. This field defines address size. + ADSIZE: packed union { raw: u2, - value: LSEDRV, + value: SizeInBits, }, - /// LSECSSON - LSECSSON: u1, - /// CSS on LSE failure detection - LSECSSD_: u1, - reserved8: u1, - /// RTC clock source selection - RTCSEL: packed union { + reserved16: u2, + /// Alternate-byte mode. This field defines the alternate byte phase mode of operation. 101-111: Reserved + ABMODE: packed union { + raw: u3, + value: PhaseMode, + }, + /// Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase. + ABDTR: u1, + /// Alternate bytes size. This bit defines alternate bytes size. + ABSIZE: packed union { raw: u2, - value: RTCSEL, + value: SizeInBits, }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - reserved24: u7, - /// Low speed clock output enable - LSCOEN: u1, - /// Low speed clock output selection - LSCOSEL: u2, - padding: u5, + reserved24: u2, + /// Data mode. This field defines the data phase mode of operation. 101-111: Reserved + DMODE: packed union { + raw: u3, + value: PhaseMode, + }, + /// Data double transfer rate. This bit sets the DTR mode for the data phase. + DDTR: u1, + reserved29: u1, + /// DQS enable. This bit enables the data strobe management. + DQSE: u1, + padding: u2, }), - /// CSR - CSR: mmio.Mmio(packed struct(u32) { - /// LSI1 oscillator enabled - LSI1ON: u1, - /// LSI1 oscillator ready - LSI1RDY: u1, - /// LSI2 oscillator enabled - LSI2ON: u1, - /// LSI2 oscillator ready - LSI2RDY: u1, - /// LSI2 oscillator trimming enable - LSI2TRIMEN: u1, - /// LSI2 oscillator trim OK - LSI2TRIMOK: u1, - reserved8: u2, - /// LSI2 oscillator bias configuration - LSI2BW: u4, - reserved14: u2, - /// RF system wakeup clock source selection - RFWKPSEL: u2, - /// Radio system BLE and 802.15.4 reset status - RFRSTS: u1, - reserved23: u6, - /// Remove reset flag - RMVF: u1, - reserved25: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// Pin reset flag - PINRSTF: u1, - /// BOR flag - BORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent window watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + reserved328: [4]u8, + /// wrap timing configuration register + WPTCR: mmio.Mmio(packed struct(u32) { + /// Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. + DCYC: u5, + reserved28: u23, + /// Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement. + DHQC: u1, + reserved30: u1, + /// Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1). + SSHIFT: packed union { + raw: u1, + value: SampleShift, + }, + padding: u1, }), - /// Clock recovery RC register - CRRCR: mmio.Mmio(packed struct(u32) { - /// HSI48 oscillator enabled - HSI48ON: u1, - /// HSI48 clock ready - HSI48RDY: u1, - reserved7: u5, - /// HSI48 clock calibration - HSI48CAL: u9, - padding: u16, + reserved336: [4]u8, + /// wrap instruction register + WPIR: mmio.Mmio(packed struct(u32) { + /// [31: 0]: Instruction Instruction to be sent to the external SPI device + INSTRUCTION: u32, }), - /// Clock HSE register - HSECR: mmio.Mmio(packed struct(u32) { - /// Register lock system - UNLOCKED: u1, - reserved3: u2, - /// HSE Sense amplifier threshold - HSES: u1, - /// HSE current control - HSEGMC: u3, - reserved8: u1, - /// HSE capacitor tuning - HSETUNE: u6, - padding: u18, + reserved352: [12]u8, + /// wrap alternate bytes register + WPABR: mmio.Mmio(packed struct(u32) { + /// [31: 0]: Alternate bytes Optional data to be sent to the external SPI device right after the address + ALTERNATE: u32, }), - reserved264: [104]u8, - /// Extended clock recovery register - EXTCFGR: mmio.Mmio(packed struct(u32) { - /// Shared AHB prescaler - SHDHPRE: packed union { - raw: u4, - value: HPRE, + reserved384: [28]u8, + /// write communication configuration register + WCCR: mmio.Mmio(packed struct(u32) { + /// Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved + IMODE: packed union { + raw: u3, + value: PhaseMode, }, - /// CPU2 AHB prescaler - C2HPRE: packed union { - raw: u4, - value: HPRE, + /// Instruction double transfer rate. This bit sets the DTR mode for the instruction phase. + IDTR: u1, + /// Instruction size. This bit defines instruction size: + ISIZE: packed union { + raw: u2, + value: SizeInBits, }, - reserved16: u8, - /// Shared AHB prescaler flag - SHDHPREF: u1, - /// CPU2 AHB prescaler flag - C2HPREF: u1, - reserved20: u2, - /// RF clock source selected - RFCSS: u1, - padding: u11, - }), - reserved328: [60]u8, - /// CPU2 AHB1 peripheral clock enable register - C2AHB1ENR: mmio.Mmio(packed struct(u32) { - /// CPU2 DMA1 clock enable - DMA1EN: u1, - /// CPU2 DMA2 clock enable - DMA2EN: u1, - /// CPU2 DMAMUX clock enable - DMAMUX1EN: u1, - reserved9: u6, - /// CPU2 SRAM1 clock enable - SRAM1EN: u1, - reserved12: u2, - /// CPU2 CRC clock enable - CRCEN: u1, - reserved16: u3, - /// CPU2 Touch Sensing Controller clock enable - TSCEN: u1, - padding: u15, - }), - /// CPU2 AHB2 peripheral clock enable register - C2AHB2ENR: mmio.Mmio(packed struct(u32) { - /// CPU2 IO port A clock enable - GPIOAEN: u1, - /// CPU2 IO port B clock enable - GPIOBEN: u1, - /// CPU2 IO port C clock enable - GPIOCEN: u1, - /// CPU2 IO port D clock enable - GPIODEN: u1, - /// CPU2 IO port E clock enable - GPIOEEN: u1, - reserved7: u2, - /// CPU2 IO port H clock enable - GPIOHEN: u1, - reserved13: u5, - /// CPU2 ADC clock enable - ADCEN: u1, - reserved16: u2, - /// CPU2 AES1 accelerator clock enable - AES1EN: u1, - padding: u15, - }), - /// CPU2 AHB3 peripheral clock enable register - C2AHB3ENR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// CPU2 PKAEN - PKAEN: u1, - /// CPU2 AES2EN - AES2EN: u1, - /// CPU2 RNGEN - RNGEN: u1, - /// CPU2 HSEMEN - HSEMEN: u1, - /// CPU2 IPCCEN - IPCCEN: u1, - reserved25: u4, - /// CPU2 FLASHEN - FLASHEN: u1, - padding: u6, - }), - reserved344: [4]u8, - /// CPU2 APB1ENR1 - C2APB1ENR1: mmio.Mmio(packed struct(u32) { - /// CPU2 TIM2 timer clock enable - TIM2EN: u1, - reserved9: u8, - /// CPU2 LCD clock enable - LCDEN: u1, - /// CPU2 RTC APB clock enable - RTCAPBEN: u1, - reserved14: u3, - /// CPU2 SPI2 clock enable - SPI2EN: u1, - reserved21: u6, - /// CPU2 I2C1 clock enable - I2C1EN: u1, - reserved23: u1, - /// CPU2 I2C3 clock enable - I2C3EN: u1, - /// CPU2 CRS clock enable - CRSEN: u1, - reserved26: u1, - /// CPU2 USB clock enable - USBEN: u1, - reserved31: u4, - /// CPU2 Low power timer 1 clock enable - LPTIM1EN: u1, - }), - /// CPU2 APB1 peripheral clock enable register 2 - C2APB1ENR2: mmio.Mmio(packed struct(u32) { - /// CPU2 Low power UART 1 clock enable - LPUART1EN: u1, - reserved5: u4, - /// CPU2 LPTIM2EN - LPTIM2EN: u1, - padding: u26, - }), - /// CPU2 APB2ENR - C2APB2ENR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// CPU2 TIM1 timer clock enable - TIM1EN: u1, - /// CPU2 SPI1 clock enable - SPI1EN: u1, - reserved14: u1, - /// CPU2 USART1clock enable - USART1EN: u1, - reserved17: u2, - /// CPU2 TIM16 timer clock enable - TIM16EN: u1, - /// CPU2 TIM17 timer clock enable - TIM17EN: u1, - reserved21: u2, - /// CPU2 SAI1 clock enable - SAI1EN: u1, - padding: u10, - }), - /// CPU2 APB3ENR - C2APB3ENR: mmio.Mmio(packed struct(u32) { - /// CPU2 BLE interface clock enable - BLEEN: u1, - /// CPU2 802.15.4 interface clock enable - EN802: u1, - padding: u30, - }), - /// CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register - C2AHB1SMENR: mmio.Mmio(packed struct(u32) { - /// CPU2 DMA1 clocks enable during Sleep and Stop modes - DMA1SMEN: u1, - /// CPU2 DMA2 clocks enable during Sleep and Stop modes - DMA2SMEN: u1, - /// CPU2 DMAMUX clocks enable during Sleep and Stop modes - DMAMUX1SMEN: u1, - reserved9: u6, - /// SRAM1 interface clock enable during CPU1 CSleep mode - SRAM1SMEN: u1, - reserved12: u2, - /// CPU2 CRCSMEN - CRCSMEN: u1, - reserved16: u3, - /// CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes - TSCSMEN: u1, - padding: u15, - }), - /// CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register - C2AHB2SMENR: mmio.Mmio(packed struct(u32) { - /// CPU2 IO port A clocks enable during Sleep and Stop modes - GPIOASMEN: u1, - /// CPU2 IO port B clocks enable during Sleep and Stop modes - GPIOBSMEN: u1, - /// CPU2 IO port C clocks enable during Sleep and Stop modes - GPIOCSMEN: u1, - /// CPU2 IO port D clocks enable during Sleep and Stop modes - GPIODSMEN: u1, - /// CPU2 IO port E clocks enable during Sleep and Stop modes - GPIOESMEN: u1, - reserved7: u2, - /// CPU2 IO port H clocks enable during Sleep and Stop modes - GPIOHSMEN: u1, - reserved13: u5, - /// CPU2 ADC clocks enable during Sleep and Stop modes - ADCFSSMEN: u1, - reserved16: u2, - /// CPU2 AES1 accelerator clocks enable during Sleep and Stop modes - AES1SMEN: u1, - padding: u15, - }), - /// CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register - C2AHB3SMENR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// PKA accelerator clocks enable during CPU2 sleep modes - PKASMEN: u1, - /// AES2 accelerator clocks enable during CPU2 sleep modes - AES2SMEN: u1, - /// True RNG clocks enable during CPU2 sleep modes - RNGSMEN: u1, - reserved24: u5, - /// SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes - SRAM2SMEN: u1, - /// Flash interface clocks enable during CPU2 sleep modes - FLASHSMEN: u1, - padding: u6, - }), - reserved376: [4]u8, - /// CPU2 APB1SMENR1 - C2APB1SMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clocks enable during CPU2 Sleep mode - TIM2SMEN: u1, - reserved9: u8, - /// LCD clocks enable during CPU2 Sleep mode - LCDSMEN: u1, - /// RTC APB clocks enable during CPU2 Sleep mode - RTCAPBSMEN: u1, - reserved14: u3, - /// SPI2 clocks enable during CPU2 Sleep mode - SPI2SMEN: u1, - reserved21: u6, - /// I2C1 clocks enable during CPU2 Sleep mode - I2C1SMEN: u1, - reserved23: u1, - /// I2C3 clocks enable during CPU2 Sleep mode - I2C3SMEN: u1, - /// CRS clocks enable during CPU2 Sleep mode - CRSMEN: u1, - reserved26: u1, - /// USB FS clocks enable during CPU2 Sleep mode - USBSMEN: u1, - reserved31: u4, - /// Low power timer 1 clocks enable during CPU2 Sleep mode - LPTIM1SMEN: u1, - }), - /// CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 - C2APB1SMENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clocks enable during CPU2 Sleep mode - LPUART1SMEN: u1, - reserved5: u4, - /// Low power timer 2 clocks enable during CPU2 Sleep mode - LPTIM2SMEN: u1, - padding: u26, - }), - /// CPU2 APB2SMENR - C2APB2SMENR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 timer clocks enable during CPU2 Sleep mode - TIM1SMEN: u1, - /// SPI1 clocks enable during CPU2 Sleep mode - SPI1SMEN: u1, - reserved14: u1, - /// USART1clocks enable during CPU2 Sleep mode - USART1SMEN: u1, - reserved17: u2, - /// TIM16 timer clocks enable during CPU2 Sleep mode - TIM16SMEN: u1, - /// TIM17 timer clocks enable during CPU2 Sleep mode - TIM17SMEN: u1, - reserved21: u2, - /// SAI1 clocks enable during CPU2 Sleep mode - SAI1SMEN: u1, - padding: u10, - }), - /// CPU2 APB3SMENR - C2APB3SMENR: mmio.Mmio(packed struct(u32) { - /// BLE interface clocks enable during CPU2 Sleep mode - BLESMEN: u1, - /// 802.15.4 interface clocks enable during CPU2 Sleep modes - SMEN802: u1, - padding: u30, - }), - }; - }; - - pub const gpio_v1 = struct { - pub const CNF_IN = enum(u2) { - /// Analog mode - Analog = 0x0, - /// Floating input (reset state) - Floating = 0x1, - /// Input with pull-up/pull-down - Pull = 0x2, - _, - }; - - pub const CNF_OUT = enum(u2) { - /// Push-Pull mode - PushPull = 0x0, - /// Open Drain-Mode - OpenDrain = 0x1, - /// Alternate Function Push-Pull Mode - AltPushPull = 0x2, - /// Alternate Function Open-Drain Mode - AltOpenDrain = 0x3, - }; - - pub const IDR = enum(u1) { - /// Input is logic low - Low = 0x0, - /// Input is logic high - High = 0x1, - }; - - pub const MODE = enum(u2) { - /// Input mode (reset state) - Input = 0x0, - /// Output mode 10 MHz - Output10Mhz = 0x1, - /// Output mode 2 MHz - Output2Mhz = 0x2, - /// Output mode 50 MHz - Output50Mhz = 0x3, - }; - - pub const ODR = enum(u1) { - /// Set output to logic low - Low = 0x0, - /// Set output to logic high - High = 0x1, - }; - - /// General purpose I/O - pub const GPIO = extern struct { - /// Port configuration register low (GPIOn_CRL) - CR: [2]mmio.Mmio(packed struct(u32) { - /// Port n mode bits - MODE: packed union { + reserved8: u2, + /// Address mode. This field defines the address phase mode of operation. 101-111: Reserved + ADMODE: packed union { + raw: u3, + value: PhaseMode, + }, + /// Address double transfer rate. This bit sets the DTR mode for the address phase. + ADDTR: u1, + /// Address size. This field defines address size. + ADSIZE: packed union { raw: u2, - value: MODE, + value: SizeInBits, }, - /// Port n configuration bits, for input mode - CNF_IN: packed union { + reserved16: u2, + /// Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved + ABMODE: packed union { + raw: u3, + value: PhaseMode, + }, + /// Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate-bytes phase. + ABDTR: u1, + /// Alternate bytes size. This field defines alternate bytes size: + ABSIZE: packed union { raw: u2, - value: CNF_IN, + value: SizeInBits, }, - padding: u28, - }), - /// Port input data register (GPIOn_IDR) - IDR: mmio.Mmio(packed struct(u32) { - /// Port input data - IDR: packed union { - raw: u1, - value: IDR, + reserved24: u2, + /// Data mode. This field defines the data phase mode of operation. 101-111: Reserved + DMODE: packed union { + raw: u3, + value: PhaseMode, }, - padding: u31, + /// data double transfer rate. This bit sets the DTR mode for the data phase. + DDTR: u1, + reserved29: u1, + /// DQS enable. This bit enables the data strobe management. + DQSE: u1, + padding: u2, }), - /// Port output data register (GPIOn_ODR) - ODR: mmio.Mmio(packed struct(u32) { - /// Port output data - ODR: packed union { - raw: u1, - value: ODR, - }, - padding: u31, + reserved392: [4]u8, + /// write timing configuration register + WTCR: mmio.Mmio(packed struct(u32) { + /// Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. + DCYC: u5, + padding: u27, }), - /// Port bit set/reset register (GPIOn_BSRR) - BSRR: mmio.Mmio(packed struct(u32) { - /// Set bit - BS: u1, - reserved16: u15, - /// Reset bit - BR: u1, - padding: u15, + reserved400: [4]u8, + /// write instruction register + WIR: mmio.Mmio(packed struct(u32) { + /// Instruction Instruction to be sent to the external SPI device + INSTRUCTION: u32, }), - /// Port bit reset register (GPIOn_BRR) - BRR: mmio.Mmio(packed struct(u32) { - /// Reset bit - BR: u1, - padding: u31, + reserved416: [12]u8, + /// write alternate bytes register + WABR: mmio.Mmio(packed struct(u32) { + /// [31: 0]: Alternate bytes. Optional data to be sent to the external SPI device right after the address + ALTERNATE: u32, }), - /// Port configuration lock register - LCKR: mmio.Mmio(packed struct(u32) { - /// Port configuration locked - LCK: u1, - reserved16: u15, - /// Port configuration lock key active - LCKK: u1, - padding: u15, + reserved512: [92]u8, + /// OCTOSPI HyperBus latency configuration register + HLCR: mmio.Mmio(packed struct(u32) { + /// Latency mode. This bit selects the Latency mode. + LM: packed union { + raw: u1, + value: LatencyMode, + }, + /// Write zero latency. This bit enables zero latency on write operations. + WZL: u1, + reserved8: u6, + /// [7: 0]: Access time. Device access time expressed in number of communication clock cycles + TACC: u8, + /// Read write recovery time Device read write recovery time expressed in number of communication clock cycles + TRWR: u8, + padding: u8, }), }; }; - pub const ipcc_v1 = struct { - /// IPCC - pub const IPCC = extern struct { - /// CPU specific registers - CPU: u32, - }; - - /// IPCC - pub const IPCC_CPU = extern struct { - /// Control register CPUx + pub const octospim_v1 = struct { + /// OctoSPI IO Manager + pub const OCTOSPIM = extern struct { + /// control register CR: mmio.Mmio(packed struct(u32) { - /// processor x Receive channel occupied interrupt enable - RXOIE: u1, - reserved16: u15, - /// processor x Transmit channel free interrupt enable - TXFIE: u1, - padding: u15, - }), - /// Mask register CPUx - MR: mmio.Mmio(packed struct(u32) { - /// processor x Receive channel y occupied interrupt enable - CHOM: u1, + /// Multiplexed mode enable + MUXEN: u1, reserved16: u15, - /// processor x Transmit channel y free interrupt mask - CHFM: u1, - padding: u15, + /// REQ to ACK time + REQ2ACK_TIME: u8, + padding: u8, }), - /// Status Set or Clear register CPUx - SCR: mmio.Mmio(packed struct(u32) { - /// processor x Receive channel y status clear - CHC: u1, - reserved16: u15, - /// processor x Transmit channel y status set - CHS: u1, - padding: u15, + /// OctoSPI IO Manager Port 1 Configuration Register + P1CR: mmio.Mmio(packed struct(u32) { + /// CLK/CLK Enable for Port + CLKEN: u1, + /// CLK/CLK Source for Port + CLKSRC: u1, + reserved4: u2, + /// DQS Enable for Port + DQSEN: u1, + /// DQS Source for Port + DQSSRC: u1, + reserved8: u2, + /// CS Enable for Port + NCSEN: u1, + /// CS Source for Port + NCSSRC: u1, + reserved16: u6, + /// Enable for Port + IOLEN: u1, + /// Source for Port + IOLSRC: u2, + reserved24: u5, + /// Enable for Port n + IOHEN: u1, + /// Source for Port + IOHSRC: u2, + padding: u5, }), - /// CPUx to CPUy status register - SR: mmio.Mmio(packed struct(u32) { - /// processor x transmit to process y Receive channel z status flag - CHF: u1, - padding: u31, + /// OctoSPI IO Manager Port 2 Configuration Register + P2CR: mmio.Mmio(packed struct(u32) { + /// CLK/CLK Enable for Port + CLKEN: u1, + /// CLK/CLK Source for Port + CLKSRC: u1, + reserved4: u2, + /// DQS Enable for Port + DQSEN: u1, + /// DQS Source for Port + DQSSRC: u1, + reserved8: u2, + /// CS Enable for Port + NCSEN: u1, + /// CS Source for Port + NCSSRC: u1, + reserved16: u6, + /// Enable for Port + IOLEN: u1, + /// Source for Port + IOLSRC: u2, + reserved24: u5, + /// Enable for Port n + IOHEN: u1, + /// Source for Port + IOHSRC: u2, + padding: u5, }), }; }; - pub const lptim_v1a = struct { - pub const CKPOL = enum(u2) { - /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. - Rising = 0x0, - /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. - Falling = 0x1, - /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. - Both = 0x2, - _, + pub const opamp_f3 = struct { + pub const CALSEL = enum(u2) { + /// VREFOPAMP=3.3% VDDA + Percent3_3 = 0x0, + /// VREFOPAMP=10% VDDA + Percent10 = 0x1, + /// VREFOPAMP=50% VDDA + Percent50 = 0x2, + /// VREFOPAMP=90% VDDA + Percent90 = 0x3, }; - pub const ClockSource = enum(u1) { - /// clocked by internal clock source (APB clock or any of the embedded oscillators) - Internal = 0x0, - /// clocked by an external clock source through the LPTIM external Input1 - External = 0x1, + pub const FORCE_VP = enum(u1) { + /// Normal operating mode + Normal = 0x0, + /// Calibration mode. Non-inverting input connected to calibration reference + Calibration = 0x1, }; - pub const Filter = enum(u2) { - Count1 = 0x0, - Count2 = 0x1, - Count4 = 0x2, - Count8 = 0x3, + pub const OUTCAL = enum(u1) { + /// Non-inverting < inverting + Low = 0x0, + /// Non-inverting > inverting + High = 0x1, }; - pub const PRESC = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div4 = 0x2, - Div8 = 0x3, - Div16 = 0x4, - Div32 = 0x5, - Div64 = 0x6, - Div128 = 0x7, + pub const PGA_GAIN = enum(u4) { + /// Gain 2 + Gain2 = 0x0, + /// Gain 4 + Gain4 = 0x1, + /// Gain 8 + Gain8 = 0x2, + /// Gain 16 + Gain16 = 0x4, + /// Gain 2, feedback connected to VM0 + Gain2_VM0 = 0x8, + /// Gain 4, feedback connected to VM0 + Gain4_VM0 = 0x9, + /// Gain 8, feedback connected to VM0 + Gain8_VM0 = 0xa, + /// Gain 16, feedback connected to VM0 + Gain16_VM0 = 0xb, + /// Gain 2, feedback connected to VM1 + Gain2_VM1 = 0xc, + /// Gain 4, feedback connected to VM1 + Gain4_VM1 = 0xd, + /// Gain 8, feedback connected to VM1 + Gain8_VM1 = 0xe, + /// Gain 16, feedback connected to VM1 + Gain16_VM1 = 0xf, + _, }; - pub const TRIGEN = enum(u2) { - /// software trigger (counting start is initiated by software) - Software = 0x0, - /// rising edge is the active edge - RisingEdge = 0x1, - /// falling edge is the active edge - FallingEdge = 0x2, - /// both edges are active edges - BothEdge = 0x3, + pub const VMS_SEL = enum(u1) { + /// PC5 (VM0) used as OPAMP2 inverting input when TCM_EN=1 + PC5 = 0x0, + /// PA5 (VM1) used as OPAMP2 inverting input when TCM_EN=1 + PA5 = 0x1, }; - pub const WAVPOL = enum(u1) { - /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. - Positive = 0x0, - /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. - Negative = 0x1, + pub const VM_SEL = enum(u2) { + /// PC5 (VM0) used as OPAMP2 inverting input + PC5 = 0x0, + /// PA5 (VM1) used as OPAMP2 inverting input + PA5 = 0x1, + /// Resistor feedback output (PGA mode) + PGA = 0x2, + /// Follower mode + Follower = 0x3, }; - /// Low power timer with Output Compare - pub const LPTIM = extern struct { - /// LPTIM interrupt and status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, - /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. - ARRM: u1, - /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. - EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, - /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. - ARROK: u1, - /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UP: u1, - /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWN: u1, - padding: u25, - }), - /// LPTIM interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, - /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. - ARRMCF: u1, - /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. - EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, - /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. - ARROKCF: u1, - /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPCF: u1, - /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNCF: u1, - padding: u25, - }), - /// LPTIM interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, - /// Autoreload match Interrupt Enable. - ARRMIE: u1, - /// External trigger valid edge Interrupt Enable. - EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, - /// Autoreload register update OK Interrupt Enable. - ARROKIE: u1, - /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPIE: u1, - /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNIE: u1, - padding: u25, - }), - /// LPTIM configuration register. - CFGR: mmio.Mmio(packed struct(u32) { - /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. - CKSEL: packed union { + pub const VPS_SEL = enum(u2) { + /// PB14 used as OPAMP2 non-inverting input when TCM_EN=1 + PB14 = 0x1, + /// PB0 used as OPAMP2 non-inverting input when TCM_EN=1 + PB0 = 0x2, + /// PA7 used as OPAMP2 non-inverting input when TCM_EN=1 + PA7 = 0x3, + _, + }; + + pub const VP_SEL = enum(u2) { + /// PB14 used as OPAMP2 non-inverting input + PB14 = 0x1, + /// PB0 used as OPAMP2 non-inverting input + PB0 = 0x2, + /// PA7 used as OPAMP2 non-inverting input + PA7 = 0x3, + _, + }; + + /// Operational Amplifier + pub const OPAMP = extern struct { + /// OPAMP control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// OPAMP enable + OPAMPEN: u1, + /// Forces a calibration reference voltage on non-inverting input and disables external connections. + FORCE_VP: packed union { raw: u1, - value: ClockSource, + value: FORCE_VP, }, - /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. - CKPOL: packed union { + /// OPAMP Non inverting input selection + VP_SEL: packed union { raw: u2, - value: CKPOL, + value: VP_SEL, }, - /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - CKFLT: packed union { + reserved5: u1, + /// OPAMP inverting input selection + VM_SEL: packed union { raw: u2, - value: Filter, + value: VM_SEL, }, - reserved6: u1, - /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. - TRGFLT: packed union { - raw: u2, - value: Filter, + /// Timer controlled Mux mode enable + TCM_EN: u1, + /// OPAMP inverting input secondary selection + VMS_SEL: packed union { + raw: u1, + value: VMS_SEL, }, - reserved9: u1, - /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. - PRESC: packed union { - raw: u3, - value: PRESC, + /// OPAMP Non inverting input secondary selection + VPS_SEL: packed union { + raw: u2, + value: VPS_SEL, }, - reserved13: u1, - /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. - TRIGSEL: u3, - reserved17: u1, - /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. - TRIGEN: packed union { + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CALSEL: packed union { raw: u2, - value: TRIGEN, + value: CALSEL, }, - /// Timeout enable The TIMOUT bit controls the Timeout feature. - TIMOUT: u1, - /// Waveform shape The WAVE bit controls the output shape. - WAVE: u1, - /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. - WAVPOL: packed union { - raw: u1, - value: WAVPOL, + /// Gain in PGA mode + PGA_GAIN: packed union { + raw: u4, + value: PGA_GAIN, }, - /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. - PRELOAD: u1, - /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. - COUNTMODE: packed union { + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5, + /// Output the internal reference voltage + TSTREF: u1, + /// OPAMP ouput status flag + OUTCAL: packed union { raw: u1, - value: ClockSource, + value: OUTCAL, }, - /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - ENC: u1, - padding: u7, - }), - /// LPTIM control register. - CR: mmio.Mmio(packed struct(u32) { - /// LPTIM enable The ENABLE bit is set and cleared by software. - ENABLE: u1, - /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. - SNGSTRT: u1, - /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. - CNTSTRT: u1, - padding: u29, - }), - /// LPTIM compare register 1. - CMP: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. - CMP: u16, - padding: u16, - }), - /// LPTIM autoreload register. - ARR: mmio.Mmio(packed struct(u32) { - /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. - ARR: u16, - padding: u16, - }), - /// LPTIM counter register. - CNT: mmio.Mmio(packed struct(u32) { - /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. - CNT: u16, - padding: u16, + /// OPAMP lock + LOCK: u1, }), - /// LPTIM option register. - OR: u32, }; }; - pub const pssi_v1 = struct { - pub const CKPOL = enum(u1) { - /// Falling edge active for inputs or rising edge active for outputs. - FallingEdge = 0x0, - /// Rising edge active for inputs or falling edge active for outputs. - RisingEdge = 0x1, - }; - - pub const DEPOL = enum(u1) { - /// PSSI_DE active low (0 indicates that data is valid). - ActiveLow = 0x0, - /// PSSI_DE active high (1 indicates that data is valid). - ActiveHigh = 0x1, + pub const opamp_g4 = struct { + pub const CALSEL = enum(u2) { + /// VREFOPAMP=3.3% VDDA + Percent3_3 = 0x0, + /// VREFOPAMP=10% VDDA + Percent10 = 0x1, + /// VREFOPAMP=50% VDDA + Percent50 = 0x2, + /// VREFOPAMP=90% VDDA + Percent90 = 0x3, }; - pub const DERDYCFG = enum(u3) { - /// PSSI_DE and PSSI_RDY both disabled. - Disabled = 0x0, - /// Only PSSI_RDY enabled. - Rdy = 0x1, - /// Only PSSI_DE enabled. - De = 0x2, - /// Both PSSI_RDY and PSSI_DE alternate functions enabled. - RdyDeAlt = 0x3, - /// Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin. - RdyDe = 0x4, - /// Only PSSI_RDY function enabled, but mapped to PSSI_DE pin. - RdyRemapped = 0x5, - /// Only PSSI_DE function enabled, but mapped to PSSI_RDY pin. - DeRemapped = 0x6, - /// Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin. - RdyDeBidi = 0x7, + pub const FORCE_VP = enum(u1) { + /// Normal operating mode + Normal = 0x0, + /// Calibration mode. Non-inverting input connected to calibration reference + Calibration = 0x1, }; - pub const EDM = enum(u2) { - /// Interface captures 8-bit data on every parallel data clock. - BitWidth8 = 0x0, - /// The interface captures 16-bit data on every parallel data clock. - BitWidth16 = 0x3, - _, + pub const OPAHSM = enum(u1) { + /// OpAmp in normal mode + Normal = 0x0, + /// OpAmp in high speed mode + HighSpeed = 0x1, }; - pub const OUTEN = enum(u1) { - /// Data is input synchronously with PSSI_PDCK. - ReceiveMode = 0x0, - /// Data is output synchronously with PSSI_PDCK. - TransmitMode = 0x1, + pub const OPAINTOEN = enum(u1) { + /// Output is connected to the output Pin + OutputPin = 0x0, + /// Output is connected internally to ADC channel + ADCChannel = 0x1, }; - pub const RDYPOL = enum(u1) { - /// PSSI_RDY active low (0 indicates that the receiver is ready to receive). - ActiveLow = 0x0, - /// PSSI_RDY active high (1 indicates that the receiver is ready to receive). - ActiveHigh = 0x1, + pub const OUTCAL = enum(u1) { + /// Non-inverting < inverting + Low = 0x0, + /// Non-inverting > inverting + High = 0x1, }; - /// Parallel synchronous slave interface. - pub const PSSI = extern struct { - /// PSSI control register. - CR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN. - CKPOL: packed union { + pub const PGA_GAIN = enum(u5) { + /// Gain 2 + Gain2 = 0x0, + /// Gain 4 + Gain4 = 0x1, + /// Gain 8 + Gain8 = 0x2, + /// Gain 16 + Gain16 = 0x3, + /// Gain 32 + Gain32 = 0x4, + /// Gain 64 + Gain64 = 0x5, + /// Gain 2, input/bias connected to VINM0 or inverting gain + Gain2_InputVINM0 = 0x8, + /// Gain 4, input/bias connected to VINM0 or inverting gain + Gain4_InputVINM0 = 0x9, + /// Gain 8, input/bias connected to VINM0 or inverting gain + Gain8_InputVINM0 = 0xa, + /// Gain 16, input/bias connected to VINM0 or inverting gain + Gain16_InputVINM0 = 0xb, + /// Gain 32, input/bias connected to VINM0 or inverting gain + Gain32_InputVINM0 = 0xc, + /// Gain 64, input/bias connected to VINM0 or inverting gain + Gain64_InputVINM0 = 0xd, + /// Gain 2, with filtering on VINM0 + Gain2_FilteringVINM0 = 0x10, + /// Gain 4, with filtering on VINM0 + Gain4_FilteringVINM0 = 0x11, + /// Gain 8, with filtering on VINM0 + Gain8_FilteringVINM0 = 0x12, + /// Gain 16, with filtering on VINM0 + Gain16_FilteringVINM0 = 0x13, + /// Gain 32, with filtering on VINM0 + Gain32_FilteringVINM0 = 0x14, + /// Gain 64, with filtering on VINM0 + Gain64_FilteringVINM0 = 0x15, + /// Gain 2, input/bias connected to VINM0 with filtering on VINM1 or inverting gain + Gain2_InputVINM0FilteringVINM1 = 0x18, + /// Gain 4, input/bias connected to VINM0 with filtering on VINM1 or inverting gain + Gain4_InputVINM0FilteringVINM1 = 0x19, + /// Gain 8, input/bias connected to VINM0 with filtering on VINM1 or inverting gain + Gain8_InputVINM0FilteringVINM1 = 0x1a, + /// Gain 16, input/bias connected to VINM0 with filtering on VINM1 or inverting gain + Gain16_InputVINM0FilteringVINM1 = 0x1b, + /// Gain 32, input/bias connected to VINM0 with filtering on VINM1 or inverting gain + Gain32_InputVINM0FilteringVINM1 = 0x1c, + /// Gain 64, input/bias connected to VINM0 with filtering on VINM1 or inverting gain + Gain64_InputVINM0FilteringVINM1 = 0x1d, + _, + }; + + pub const USERTRIM = enum(u1) { + /// Factory trim used + Factory = 0x0, + /// User trim used + User = 0x1, + }; + + pub const VM_SEL = enum(u2) { + /// VINM0 connected to VINM input + VINM0 = 0x0, + /// VINM1 connected to VINM input + VINM1 = 0x1, + /// Feedback resistor connected to VINM (PGA mode) + PGA = 0x2, + /// OpAmp output connected to VINM (Follower mode) + Output = 0x3, + }; + + pub const VPS_SEL = enum(u2) { + /// VINP0 connected to VINP input + VINP0 = 0x0, + /// VINP1 connected to VINP input + VINP1 = 0x1, + /// VINP2 connected to VINP input + VINP2 = 0x2, + /// DAC3_CH1 connected to VINP input + DAC3_CH1 = 0x3, + }; + + pub const VP_SEL = enum(u2) { + /// VINP0 connected to VINP input + VINP0 = 0x0, + /// VINP1 connected to VINP input + VINP1 = 0x1, + /// VINP2 connected to VINP input + VINP2 = 0x2, + /// DAC3_CH1 connected to VINP input + DAC3_CH1 = 0x3, + }; + + /// Operational Amplifier + pub const OPAMP = extern struct { + /// OPAMP control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// OPAMP enable + OPAMPEN: u1, + /// Forces a calibration reference voltage on non-inverting input and disables external connections. + FORCE_VP: packed union { raw: u1, - value: CKPOL, + value: FORCE_VP, }, - /// Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface. - DEPOL: packed union { + /// VP_SEL + VP_SEL: packed union { + raw: u2, + value: VP_SEL, + }, + /// USERTRIM + USERTRIM: packed union { raw: u1, - value: DEPOL, + value: USERTRIM, }, - reserved8: u1, - /// Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface. - RDYPOL: packed union { + /// OPAMP inverting input selection + VM_SEL: packed union { + raw: u2, + value: VM_SEL, + }, + /// OPAHSM + OPAHSM: packed union { raw: u1, - value: RDYPOL, + value: OPAHSM, }, - reserved10: u1, - /// Extended data mode. - EDM: packed union { + /// OPAINTOEN + OPAINTOEN: packed union { + raw: u1, + value: OPAINTOEN, + }, + reserved11: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CALSEL: packed union { raw: u2, - value: EDM, + value: CALSEL, }, - reserved14: u2, - /// PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time. - ENABLE: u1, - reserved18: u3, - /// Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity. - DERDYCFG: packed union { - raw: u3, - value: DERDYCFG, + /// Gain in PGA mode + PGA_GAIN: packed union { + raw: u5, + value: PGA_GAIN, }, - reserved30: u9, - /// DMA enable bit. - DMAEN: u1, - /// Data direction selection bit. - OUTEN: packed union { + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5, + reserved30: u1, + /// OPAMP ouput status flag + OUTCAL: packed union { raw: u1, - value: OUTEN, + value: OUTCAL, }, + /// LOCK + LOCK: u1, }), - /// PSSI status register. - SR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// FIFO is ready to transfer four bytes. - RTT4B: u1, - /// FIFO is ready to transfer one byte. - RTT1B: u1, - padding: u28, - }), - /// PSSI raw interrupt status register. - RIS: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Data buffer overrun/underrun raw interrupt status This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR. - OVR_RIS: u1, - padding: u30, - }), - /// PSSI interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Data buffer overrun/underrun interrupt enable. - OVR_IE: u1, - padding: u30, - }), - /// PSSI masked interrupt status register. - MIS: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Data buffer overrun/underrun masked interrupt status This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are both set to 1. - OVR_MIS: u1, - padding: u30, - }), - /// PSSI interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Data buffer overrun/underrun interrupt status clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS. - OVR_ISC: u1, - padding: u30, - }), - reserved40: [16]u8, - /// PSSI data register. - DR: mmio.Mmio(packed struct(u32) { - /// Data byte 0. - BYTE: u8, - padding: u24, + reserved24: [20]u8, + /// OPAMP control/status register + TCMR: mmio.Mmio(packed struct(u32) { + /// VMS_SEL + VMS_SEL: u1, + /// VPS_SEL + VPS_SEL: packed union { + raw: u2, + value: VPS_SEL, + }, + /// T1CM_EN + T1CM_EN: u1, + /// T8CM_EN + T8CM_EN: u1, + /// T20CM_EN + T20CM_EN: u1, + reserved31: u25, + /// TCMR LOCK + LOCK: u1, }), }; }; - pub const spi_f1 = struct { - pub const BIDIMODE = enum(u1) { - /// 2-line unidirectional data mode selected - Unidirectional = 0x0, - /// 1-line bidirectional data mode selected - Bidirectional = 0x1, + pub const opamp_h_v1 = struct { + pub const CALON = enum(u1) { + /// Normal mode + Normal = 0x0, + /// Calibration mode (all switches opened by HW) + Calibration = 0x1, }; - pub const BIDIOE = enum(u1) { - /// Output disabled (receive-only mode) - Receive = 0x0, - /// Output enabled (transmit-only mode) - Transmit = 0x1, + pub const CALOUT = enum(u1) { + /// Non-inverting < inverting + Less = 0x0, + /// Non-inverting > inverting + Greater = 0x1, }; - pub const BR = enum(u3) { - /// f_PCLK / 2 - Div2 = 0x0, - /// f_PCLK / 4 - Div4 = 0x1, - /// f_PCLK / 8 - Div8 = 0x2, - /// f_PCLK / 16 - Div16 = 0x3, - /// f_PCLK / 32 - Div32 = 0x4, - /// f_PCLK / 64 - Div64 = 0x5, - /// f_PCLK / 128 - Div128 = 0x6, - /// f_PCLK / 256 - Div256 = 0x7, + pub const CALSEL = enum(u2) { + /// VREFOPAMP=3.3% VDDA. + Percent3_3 = 0x0, + /// VREFOPAMP=10% VDDA. + Percent10 = 0x1, + /// VREFOPAMP=50% VDDA. + Percent50 = 0x2, + /// VREFOPAMP=90% VDDA. + Percent90 = 0x3, }; - pub const CHLEN = enum(u1) { - /// 16-bit wide - Bits16 = 0x0, - /// 32-bit wide - Bits32 = 0x1, + pub const FORCE_VP = enum(u1) { + /// Normal operating mode. Non-inverting input connected to inputs. + NormalOperating = 0x0, + /// Calibration verification mode. Non-inverting input connected to calibration reference voltage. + CalibrationVerification = 0x1, }; - pub const CHSIDE = enum(u1) { - /// Channel left has to be transmitted or has been received - Left = 0x0, - /// Channel right has to be transmitted or has been received - Right = 0x1, + pub const OPAHSM = enum(u1) { + /// operational amplifier in normal mode + Normal = 0x0, + /// operational amplifier in high-speed mode + HighSpeed = 0x1, }; - pub const CKPOL = enum(u1) { - /// I2S clock inactive state is low level - IdleLow = 0x0, - /// I2S clock inactive state is high level - IdleHigh = 0x1, + pub const PGA_GAIN = enum(u4) { + /// Non-inverting internal Gain 2, VREF- referenced + Gain2 = 0x0, + /// Non-inverting internal Gain 4, VREF- referenced + Gain4 = 0x1, + /// Non-inverting internal Gain 8, VREF- referenced + Gain8 = 0x2, + /// Non-inverting internal Gain 16, VREF- referenced + Gain16 = 0x3, + /// Non-inverting internal Gain 2 with filtering on INM0, VREF- referenced + Gain2_FilteringVINM0 = 0x4, + /// Non-inverting internal Gain 4 with filtering on INM0, VREF- referenced + Gain4_FilteringVINM0 = 0x5, + /// Non-inverting internal Gain 8 with filtering on INM0, VREF- referenced + Gain8_FilteringVINM0 = 0x6, + /// Non-inverting internal Gain 8 with filtering on INM0, VREF- referenced + Gain16_FilteringVINM0 = 0x7, + /// Inverting gain=-1/ Non-inverting gain =2 with INM0 node for input or bias + Gain2InvGainNeg1_InputVINM0 = 0x8, + /// Inverting gain=-3/ Non-inverting gain =4 with INM0 node for input or bias + Gain4InvGainNeg3_InputVINM0 = 0x9, + /// Inverting gain=-7/ Non-inverting gain =8 with INM0 node for input or bias + Gain8InvGainNeg7_InputVINM0 = 0xa, + /// Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias + Gain16InvGainNeg15_InputVINM0 = 0xb, + /// Inverting gain=-1/ Non-inverting gain =2 with INM0 node for input or bias, INM1 node for filtering + Gain2InvGainNeg1_InputVINM0FilteringVINM1 = 0xc, + /// Inverting gain=-3/ Non-inverting gain =4 with INM0 node for input or bias, INM1 node for filtering + Gain4InvGainNeg3_InputVINM0FilteringVINM1 = 0xd, + /// Inverting gain=-7/ Non-inverting gain =8 with INM0 node for input or bias, INM1 node for filtering + Gain8InvGainNeg7_InputVINM0FilteringVINM1 = 0xe, + /// Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias, INM1 node for filtering + Gain16InvGainNeg15_InputVINM0FilteringVINM1 = 0xf, }; - pub const CPHA = enum(u1) { - /// The first clock transition is the first data capture edge - FirstEdge = 0x0, - /// The second clock transition is the first data capture edge - SecondEdge = 0x1, + pub const USERTRIM = enum(u1) { + /// \'factory\' trim code used + Factory = 0x0, + /// \'user\' trim code used + User = 0x1, }; - pub const CPOL = enum(u1) { - /// CK to 0 when idle - IdleLow = 0x0, - /// CK to 1 when idle - IdleHigh = 0x1, + pub const VM_SEL = enum(u2) { + /// INM0 connected to OPAMP_VINM input + Inm0 = 0x0, + /// INM1 connected to OPAMP_VINM input + Inm1 = 0x1, + /// Feedback resistor is connected to the OPAMP_VINM input (PGA mode), Inverting input selection depends on the PGA_GAIN setting + Pga = 0x2, + /// opamp_out connected to OPAMP_VINM input (Follower mode) + Follower = 0x3, }; - pub const CRCNEXT = enum(u1) { - /// Next transmit value is from Tx buffer - TxBuffer = 0x0, - /// Next transmit value is from Tx CRC register - CRC = 0x1, + pub const VP_SEL = enum(u2) { + /// GPIO connected to OPAMPx_VINP + Gpio = 0x0, + /// dac_outx connected to OPAMPx_VINP + DacOut = 0x1, + _, }; - pub const DATLEN = enum(u2) { - /// 16-bit data length - Bits16 = 0x0, - /// 24-bit data length - Bits24 = 0x1, - /// 32-bit data length - Bits32 = 0x2, - _, + /// Operational amplifiers. + pub const OPAMP = extern struct { + /// OPAMP1 control/status register. + CSR: mmio.Mmio(packed struct(u32) { + /// Operational amplifier Enable. + OPAMPEN: u1, + /// Force internal reference on VP (reserved for test. + FORCE_VP: packed union { + raw: u1, + value: FORCE_VP, + }, + /// Operational amplifier PGA mode. + VP_SEL: packed union { + raw: u2, + value: VP_SEL, + }, + reserved5: u1, + /// Inverting input selection. + VM_SEL: packed union { + raw: u2, + value: VM_SEL, + }, + reserved8: u1, + /// Operational amplifier high-speed mode. + OPAHSM: packed union { + raw: u1, + value: OPAHSM, + }, + reserved11: u2, + /// Calibration mode enabled. + CALON: packed union { + raw: u1, + value: CALON, + }, + /// Calibration selection. + CALSEL: packed union { + raw: u2, + value: CALSEL, + }, + /// allows to switch from AOP offset trimmed values to AOP offset. + PGA_GAIN: packed union { + raw: u4, + value: PGA_GAIN, + }, + /// User trimming enable. + USERTRIM: packed union { + raw: u1, + value: USERTRIM, + }, + reserved29: u10, + /// OPAMP calibration reference voltage output control (reserved for test). + TSTREF: u1, + /// Operational amplifier calibration output. + CALOUT: packed union { + raw: u1, + value: CALOUT, + }, + padding: u1, + }), + /// OPAMP1 offset trimming register in normal mode. + OTR: mmio.Mmio(packed struct(u32) { + /// Trim for NMOS differential pairs. + TRIMOFFSETN: u5, + reserved8: u3, + /// Trim for PMOS differential pairs. + TRIMOFFSETP: u5, + padding: u19, + }), + /// OPAMP1 offset trimming register in low-power mode. + HSOTR: mmio.Mmio(packed struct(u32) { + /// Trim for NMOS differential pairs. + TRIMLPOFFSETN: u5, + reserved8: u3, + /// Trim for PMOS differential pairs. + TRIMLPOFFSETP: u5, + padding: u19, + }), }; + }; - pub const DFF = enum(u1) { - /// 8-bit data frame format is selected for transmission/reception - Bits8 = 0x0, - /// 16-bit data frame format is selected for transmission/reception - Bits16 = 0x1, + pub const opamp_h_v2 = struct { + pub const CALON = enum(u1) { + /// Normal mode + Normal = 0x0, + /// Calibration mode (all switches opened by HW) + Calibration = 0x1, }; - pub const I2SCFG = enum(u2) { - /// Slave - transmit - SlaveTx = 0x0, - /// Slave - receive - SlaveRx = 0x1, - /// Master - transmit - MasterTx = 0x2, - /// Master - receive - MasterRx = 0x3, + pub const CALOUT = enum(u1) { + /// Non-inverting < inverting + Less = 0x0, + /// Non-inverting > inverting + Greater = 0x1, }; - pub const I2SSTD = enum(u2) { - /// I2S Philips standard - Philips = 0x0, - /// MSB justified standard - MSB = 0x1, - /// LSB justified standard - LSB = 0x2, - /// PCM standard - PCM = 0x3, + pub const CALSEL = enum(u2) { + /// VREFOPAMP=3.3% VDDA. + Percent3_3 = 0x0, + /// VREFOPAMP=10% VDDA. + Percent10 = 0x1, + /// VREFOPAMP=50% VDDA. + Percent50 = 0x2, + /// VREFOPAMP=90% VDDA. + Percent90 = 0x3, }; - pub const LSBFIRST = enum(u1) { - /// Data is transmitted/received with the MSB first - MSBFirst = 0x0, - /// Data is transmitted/received with the LSB first - LSBFirst = 0x1, + pub const FORCE_VP = enum(u1) { + /// Normal operating mode. Non-inverting input connected to inputs. + NormalOperating = 0x0, + /// Calibration verification mode. Non-inverting input connected to calibration reference voltage. + CalibrationVerification = 0x1, }; - pub const MSTR = enum(u1) { - /// Slave configuration - Slave = 0x0, - /// Master configuration - Master = 0x1, + pub const OPAHSM = enum(u1) { + /// operational amplifier in normal mode + Normal = 0x0, + /// operational amplifier in high-speed mode + HighSpeed = 0x1, }; - pub const ODD = enum(u1) { - /// Real divider value is I2SDIV * 2 - Even = 0x0, - /// Real divider value is (I2SDIV * 2) + 1 - Odd = 0x1, + pub const PGA_GAIN = enum(u4) { + /// Non-inverting internal Gain 2, VREF- referenced + Gain2 = 0x0, + /// Non-inverting internal Gain 4, VREF- referenced + Gain4 = 0x1, + /// Non-inverting internal Gain 8, VREF- referenced + Gain8 = 0x2, + /// Non-inverting internal Gain 16, VREF- referenced + Gain16 = 0x3, + /// Non-inverting internal Gain 2 with filtering on INM0, VREF- referenced + Gain2_FilteringVINM0 = 0x4, + /// Non-inverting internal Gain 4 with filtering on INM0, VREF- referenced + Gain4_FilteringVINM0 = 0x5, + /// Non-inverting internal Gain 8 with filtering on INM0, VREF- referenced + Gain8_FilteringVINM0 = 0x6, + /// Non-inverting internal Gain 8 with filtering on INM0, VREF- referenced + Gain16_FilteringVINM0 = 0x7, + /// Inverting gain=-1/ Non-inverting gain =2 with INM0 node for input or bias + Gain2InvGainNeg1_InputVINM0 = 0x8, + /// Inverting gain=-3/ Non-inverting gain =4 with INM0 node for input or bias + Gain4InvGainNeg3_InputVINM0 = 0x9, + /// Inverting gain=-7/ Non-inverting gain =8 with INM0 node for input or bias + Gain8InvGainNeg7_InputVINM0 = 0xa, + /// Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias + Gain16InvGainNeg15_InputVINM0 = 0xb, + /// Inverting gain=-1/ Non-inverting gain =2 with INM0 node for input or bias, INM1 node for filtering + Gain2InvGainNeg1_InputVINM0FilteringVINM1 = 0xc, + /// Inverting gain=-3/ Non-inverting gain =4 with INM0 node for input or bias, INM1 node for filtering + Gain4InvGainNeg3_InputVINM0FilteringVINM1 = 0xd, + /// Inverting gain=-7/ Non-inverting gain =8 with INM0 node for input or bias, INM1 node for filtering + Gain8InvGainNeg7_InputVINM0FilteringVINM1 = 0xe, + /// Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias, INM1 node for filtering + Gain16InvGainNeg15_InputVINM0FilteringVINM1 = 0xf, }; - pub const PCMSYNC = enum(u1) { - /// Short frame synchronisation - Short = 0x0, - /// Long frame synchronisation - Long = 0x1, + pub const USERTRIM = enum(u1) { + /// \'factory\' trim code used + Factory = 0x0, + /// \'user\' trim code used + User = 0x1, }; - pub const RXONLY = enum(u1) { - /// Full duplex (Transmit and receive) - FullDuplex = 0x0, - /// Output disabled (Receive-only mode) - OutputDisabled = 0x1, + pub const VM_SEL = enum(u2) { + /// INM0 connected to OPAMP_VINM input + Inm0 = 0x0, + /// INM1 connected to OPAMP_VINM input + Inm1 = 0x1, + /// Feedback resistor is connected to the OPAMP_VINM input (PGA mode), Inverting input selection depends on the PGA_GAIN setting + Pga = 0x2, + /// opamp_out connected to OPAMP_VINM input (Follower mode) + Follower = 0x3, }; - /// Serial peripheral interface - pub const SPI = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Clock phase - CPHA: packed union { - raw: u1, - value: CPHA, - }, - /// Clock polarity - CPOL: packed union { - raw: u1, - value: CPOL, - }, - /// Master selection - MSTR: packed union { + pub const VP_SEL = enum(u2) { + /// GPIO INP0 connected to OPAMP_VINP + GpioInp0 = 0x0, + /// dac_outx connected to OPAMPx_VINP + DacOut = 0x1, + /// GPIO INP2 is connected to OPAMP_VINP + GpioInp2 = 0x2, + _, + }; + + /// Operational amplifiers. + pub const OPAMP = extern struct { + /// OPAMP1 control/status register. + CSR: mmio.Mmio(packed struct(u32) { + /// Operational amplifier Enable. + OPAMPEN: u1, + /// Force internal reference on VP (reserved for test. + FORCE_VP: packed union { raw: u1, - value: MSTR, + value: FORCE_VP, }, - /// Baud rate control - BR: packed union { - raw: u3, - value: BR, + /// Operational amplifier PGA mode. + VP_SEL: packed union { + raw: u2, + value: VP_SEL, }, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: packed union { - raw: u1, - value: LSBFIRST, + reserved5: u1, + /// Inverting input selection. + VM_SEL: packed union { + raw: u2, + value: VM_SEL, }, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: packed union { + reserved8: u1, + /// Operational amplifier high-speed mode. + OPAHSM: packed union { raw: u1, - value: RXONLY, + value: OPAHSM, }, - /// Data frame format - DFF: packed union { + reserved11: u2, + /// Calibration mode enabled. + CALON: packed union { raw: u1, - value: DFF, + value: CALON, }, - /// CRC transfer next - CRCNEXT: packed union { - raw: u1, - value: CRCNEXT, + /// Calibration selection. + CALSEL: packed union { + raw: u2, + value: CALSEL, }, - /// Hardware CRC calculation enable - CRCEN: u1, - /// Select the direction of transfer in bidirectional mode - BIDIOE: packed union { - raw: u1, - value: BIDIOE, + /// allows to switch from AOP offset trimmed values to AOP offset. + PGA_GAIN: packed union { + raw: u4, + value: PGA_GAIN, }, - /// Bidirectional data mode enable - BIDIMODE: packed union { + /// User trimming enable. + USERTRIM: packed union { raw: u1, - value: BIDIMODE, + value: USERTRIM, }, - padding: u16, - }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved5: u2, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt enable - RXNEIE: u1, - /// Tx buffer empty interrupt enable - TXEIE: u1, - padding: u24, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: packed union { + reserved29: u10, + /// OPAMP calibration reference voltage output control (reserved for test). + TSTREF: u1, + /// Operational amplifier calibration output. + CALOUT: packed union { raw: u1, - value: CHSIDE, + value: CALOUT, }, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - padding: u24, - }), - /// data register - DR: mmio.Mmio(packed struct(u32) { - /// Data register - DR: u16, - padding: u16, - }), - /// CRC polynomial register - CRCPR: mmio.Mmio(packed struct(u32) { - /// CRC polynomial register - CRCPOLY: u16, - padding: u16, + padding: u1, }), - /// RX CRC register - RXCRCR: mmio.Mmio(packed struct(u32) { - /// Rx CRC register - RxCRC: u16, - padding: u16, + /// OPAMP1 offset trimming register in normal mode. + OTR: mmio.Mmio(packed struct(u32) { + /// Trim for NMOS differential pairs. + TRIMOFFSETN: u5, + reserved8: u3, + /// Trim for PMOS differential pairs. + TRIMOFFSETP: u5, + padding: u19, }), - /// TX CRC register - TXCRCR: mmio.Mmio(packed struct(u32) { - /// Tx CRC register - TxCRC: u16, - padding: u16, + /// OPAMP1 offset trimming register in low-power mode. + HSOTR: mmio.Mmio(packed struct(u32) { + /// Trim for NMOS differential pairs. + TRIMLPOFFSETN: u5, + reserved8: u3, + /// Trim for PMOS differential pairs. + TRIMLPOFFSETP: u5, + padding: u19, }), - /// I2S configuration register - I2SCFGR: mmio.Mmio(packed struct(u32) { - /// Channel length (number of bits per audio channel) - CHLEN: packed union { + }; + }; + + pub const opamp_u0 = struct { + pub const CALON = enum(u1) { + /// Normal mode. + Normal = 0x0, + /// Calibration mode (all switches opened by HW). + Calibration = 0x1, + }; + + pub const CALSEL = enum(u1) { + /// NMOS calibration (200mV applied on OPAMP inputs). + NMOS = 0x0, + /// PMOS calibration (VDDA-200mV applied on OPAMP inputs). + PMOS = 0x1, + }; + + pub const OPALPM = enum(u1) { + /// operational amplifier in normal mode. + Normal = 0x0, + /// operational amplifier in low-power mode. + LowPower = 0x1, + }; + + pub const OPAMODE = enum(u2) { + /// internal PGA disable. + Disable = 0x0, + /// internal PGA disable. (Duplicate) + Disable2 = 0x1, + /// internal PGA enable, gain programmed in PGA_GAIN. + Enable = 0x2, + /// internal follower. + Follower = 0x3, + }; + + pub const OPA_RANGE = enum(u1) { + /// Low range (VDDA < 2.4V). + Low = 0x0, + /// High range (VDDA > 2.4V). + High = 0x1, + }; + + pub const PGA_GAIN = enum(u2) { + /// internal PGA Gain 2. + Gain2 = 0x0, + /// internal PGA Gain 4. + Gain4 = 0x1, + /// internal PGA Gain 8. + Gain8 = 0x2, + /// internal PGA Gain 16. + Gain16 = 0x3, + }; + + pub const USERTRIM = enum(u1) { + /// Factory trim code used. + Factory = 0x0, + /// User trim code used. + User = 0x1, + }; + + pub const VM_SEL = enum(u2) { + /// GPIO connected to VINM (valid also in PGA mode for filtering). + VINM = 0x0, + /// Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode) + NotConnected = 0x2, + _, + }; + + pub const VP_SEL = enum(u1) { + /// GPIO connected to VINP. + VINP = 0x0, + /// DAC connected to VINP. + DAC = 0x1, + }; + + /// OPAMP address block description. + pub const OPAMP = extern struct { + /// OPAMP control/status register. + CSR: mmio.Mmio(packed struct(u32) { + /// Operational amplifier Enable. + OPAMPEN: u1, + /// Operational amplifier Low Power Mode. The operational amplifier must be disable to change this configuration. + OPALPM: packed union { raw: u1, - value: CHLEN, + value: OPALPM, }, - /// Data length to be transferred - DATLEN: packed union { + /// Operational amplifier PGA mode. + OPAMODE: packed union { raw: u2, - value: DATLEN, + value: OPAMODE, }, - /// Steady state clock polarity - CKPOL: packed union { - raw: u1, - value: CKPOL, + /// Operational amplifier Programmable amplifier gain value. + PGA_GAIN: packed union { + raw: u2, + value: PGA_GAIN, }, - /// I2S standard selection - I2SSTD: packed union { + reserved8: u2, + /// Inverting input selection. These bits are used only when OPAMODE = 00, 01 or 10. 1x: Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode). + VM_SEL: packed union { raw: u2, - value: I2SSTD, + value: VM_SEL, }, - reserved7: u1, - /// PCM frame synchronization - PCMSYNC: packed union { + /// Non inverted input selection. + VP_SEL: packed union { raw: u1, - value: PCMSYNC, + value: VP_SEL, }, - /// I2S configuration mode - I2SCFG: packed union { - raw: u2, - value: I2SCFG, + reserved12: u1, + /// Calibration mode enabled. + CALON: packed union { + raw: u1, + value: CALON, }, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding: u20, - }), - /// I2S prescaler register - I2SPR: mmio.Mmio(packed struct(u32) { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the prescaler - ODD: packed union { + /// Calibration selection. + CALSEL: packed union { raw: u1, - value: ODD, + value: CALSEL, }, - /// Master clock output enable - MCKOE: u1, - padding: u22, + /// allows to switch from factory AOP offset trimmed values to AOP offset user trimmed values This bit is active for both mode normal and low-power. + USERTRIM: packed union { + raw: u1, + value: USERTRIM, + }, + /// Operational amplifier calibration output During calibration mode offset is trimmed when this signal toggle. + CALOUT: u1, + reserved31: u15, + /// Operational amplifier power supply range for stability All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP embedded in the product. + OPA_RANGE: packed union { + raw: u1, + value: OPA_RANGE, + }, + }), + /// OPAMP offset trimming register in normal mode. + OTR: mmio.Mmio(packed struct(u32) { + /// Trim for NMOS differential pairs. + TRIMOFFSETN: u5, + reserved8: u3, + /// Trim for PMOS differential pairs. + TRIMOFFSETP: u5, + padding: u19, + }), + /// OPAMP offset trimming register in low-power mode. + LPOTR: mmio.Mmio(packed struct(u32) { + /// Low-power mode trim for NMOS differential pairs. + TRIMLPOFFSETN: u5, + reserved8: u3, + /// Low-power mode trim for PMOS differential pairs. + TRIMLPOFFSETP: u5, + padding: u19, }), }; }; - pub const cryp_v4 = struct { - pub const KMOD = enum(u2) { - /// Normal-key mode. Key registers are freely usable. - Normal = 0x0, - /// Shared-key mode. If shared-key mode is properly initialized in SAES peripheral, the CRYP peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in CRYP key registers when BUSY bit is cleared and KEYVALID is set in the CRYP_SR register. Key error flag KERF is set otherwise in the CRYP_SR register. - Shared = 0x2, + pub const otfdec_v1 = struct { + pub const ENC = enum(u1) { + /// OTFDEC working in decryption mode + Decryption = 0x0, + /// OTFDEC working in encryption mode + Encryption = 0x1, + }; + + pub const MODE = enum(u2) { + /// All read accesses are decrypted (instruction or data). + Standard = 0x2, + /// Enhanced encryption mode is activated, and only instruction accesses are decrypted + Enhanced = 0x3, _, }; - /// Cryptographic processor. - pub const CRYP = extern struct { - /// control register. + /// On-The-Fly Decryption engine. + pub const OTFDEC = extern struct { + /// OTFDEC control register. CR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Algorithm direction. - ALGODIR: u1, - /// Algorithm mode. - ALGOMODE0: u3, - /// Data type selection. - DATATYPE: u2, - /// Key size selection (AES mode only). - KEYSIZE: u2, - reserved14: u4, - /// FIFO flush. - FFLUSH: u1, - /// Cryptographic processor enable. - CRYPEN: u1, - /// GCM_CCMPH. - GCM_CCMPH: u2, - reserved19: u1, - /// ALGOMODE. - ALGOMODE3: u1, - /// Number of Padding Bytes in Last Block of payload. - NPBLB: u4, - /// Key mode selection This bitfield defines how the CRYP key can be used by the application. KEYSIZE must be correctly initialized when setting KMOD[1:0] different from zero. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set. - KMOD: packed union { - raw: u2, - value: KMOD, + /// Encryption mode bit When this bit is set, OTFDEC is used in encryption mode, during which application can write clear text data then read back encrypted data. When this bit is cleared (default), OTFDEC is used in decryption mode, during which application only read back decrypted data. For both modes, cryptographic context (keys, nonces, firmware versions) must be properly initialized. When this bit is set, only data accesses are allowed (zeros are returned otherwise, and XONEIF is set). When MODE = 11, enhanced encryption mode is automatically selected. Note: When ENC bit is set, no access to OCTOSPI must be done (registers and Memory‑mapped region). + ENC: packed union { + raw: u1, + value: ENC, }, - reserved31: u5, - /// CRYP peripheral software reset Setting the bit resets the CRYP peripheral, putting all registers to their default values, except the IPRST bit itself. This bit must be kept cleared while writing any configuration registers. - IPRST: u1, - }), - /// status register. - SR: mmio.Mmio(packed struct(u32) { - /// Input FIFO empty. - IFEM: u1, - /// Input FIFO not full. - IFNF: u1, - /// Output FIFO not empty. - OFNE: u1, - /// Output FIFO full. - OFFU: u1, - /// Busy bit. - BUSY: u1, - reserved6: u1, - /// Key error flag This read-only bit is set by hardware when key information failed to load into key registers. KERF is triggered upon any of the following errors: CRYP_KxR/LR register write does not respect the correct order (refer to Section 60.4.16: CRYP key registers for details). CRYP fails to load the key shared by SAES peripheral (KMOD = 0x2). KERF must be cleared by the application software, otherwise KEYVALID cannot be set. It can be done through IPRST bit of CRYP_CR, or when a correct key writing sequence starts. - KERF: u1, - /// Key valid flag This read-only bit is set by hardware when the key of size defined by KEYSIZE is loaded in CRYP_KxR/LR key registers. The CRYPEN bit can only be set when KEYVALID is set. In normal mode when KMOD[1:0] is at zero, the key must be written in the key registers in the correct sequence, otherwise the KERF flag is set and KEYVALID remains cleared. When KMOD[1:0] is different from zero, the BUSY flag is automatically set by CRYP. When the key is loaded successfully, BUSY is cleared and KEYVALID set. Upon an error, KERF is set, BUSY cleared and KEYVALID remains cleared. If set, KERF must be cleared, otherwise KEYVALID cannot be set. For further information on key loading, refer to Section 60.4.16: CRYP key registers. - KEYVALID: u1, - padding: u24, + padding: u31, }), - /// data input register. - DIN: u32, - /// data output register. - DOUT: u32, - /// DMA control register. - DMACR: mmio.Mmio(packed struct(u32) { - /// DMA input enable. - DIEN: u1, - /// DMA output enable. - DOEN: u1, - padding: u30, + reserved16: [12]u8, + /// OTFDEC_PRIVCFGR. + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// Privileged access protection. Unprivileged read accesses to registers return zeros Unprivileged write accesses to registers are ignored. Note: This bit can only be written in privileged mode. There is no limitations on reads. + PRIV: u1, + padding: u31, }), - /// interrupt mask set/clear register. - IMSCR: mmio.Mmio(packed struct(u32) { - /// Input FIFO service interrupt mask. - INIM: u1, - /// Output FIFO service interrupt mask. - OUTIM: u1, - padding: u30, + reserved32: [12]u8, + Region: u32, + reserved768: [732]u8, + /// OTFDEC interrupt status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Security error interrupt flag status This bit is set by hardware and read only by application. This bit is set when at least one security error has been detected. This bit is cleared when application sets in OTFDEC_ICR the corresponding bit to 1. + SEIF: u1, + /// Execute-only execute-never error interrupt flag status This bit is set by hardware and read only by application. This bit is set when a read access and not an instruction fetch is detected on any encrypted region with MODE bits set to 11. Lastly, XONEIF is also set when an execute access is detected while encryption mode is enabled. This bit is cleared when application sets in OTFDEC_ICR the corresponding bit to 1. + XONEIF: u1, + /// Key error interrupt flag status This bit is set by hardware and read only by application. The bit is set when a read access occurs on an encrypted region, while its key registers is null or not properly initialized (KEYCRC = 0x0). This bit is cleared when the application sets in OTFDEC_ICR the corresponding bit to 1. After KEIF is set any subsequent read to the region with bad key registers returns a zeroed value. This state remains until those key registers are properly initialized (KEYCRC not zero). + KEIF: u1, + padding: u29, }), - /// raw interrupt status register. - RISR: mmio.Mmio(packed struct(u32) { - /// Input FIFO service raw interrupt status. - INRIS: u1, - /// Output FIFO service raw interrupt status. - OUTRIS: u1, - padding: u30, + /// OTFDEC interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Security error interrupt flag clear This bit is written by application, and always read as 0. + SEIF: u1, + /// Execute-only execute-never error interrupt flag clear This bit is written by application, and always read as 0. + XONEIF: u1, + /// Key error interrupt flag clear This bit is written by application, and always read as 0. Note: Clearing KEIF does not solve the source of the problem (bad key registers). To be able to access again any encrypted region, OTFDEC key registers must be properly initialized again. + KEIF: u1, + padding: u29, }), - /// masked interrupt status register. - MISR: mmio.Mmio(packed struct(u32) { - /// Input FIFO service masked interrupt status. - INMIS: u1, - /// Output FIFO service masked interrupt status. - OUTMIS: u1, - padding: u30, + /// OTFDEC interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Security error interrupt enable This bit is read and written by application. It controls the OTFDEC interrupt generation when SEIF flag status is set. + SEIE: u1, + /// Execute-only execute-never error interrupt enable This bit is read and written by application. It controls the OTFDEC interrupt generation when XONEIF flag status is set. + XONEIE: u1, + /// Key error interrupt enable This bit is read and written by application. It controls the OTFDEC interrupt generation when KEIF flag status is set. + KEIE: u1, + padding: u29, }), - /// Cluster KEY%s, containing K?LR, K?RR. - KEY: u32, - reserved64: [28]u8, - /// Cluster INIT%s, containing IV?LR, IV?RR. - INIT: u32, - reserved80: [12]u8, - /// context swap register. - CSGCMCCMR: [8]u32, - /// context swap register. - CSGCMR: [8]u32, - }; - - /// Cluster INIT%s, containing IV?LR, IV?RR. - pub const INIT = extern struct { - /// initialization vector registers. - IVLR: u32, - /// initialization vector registers. - IVRR: u32, }; - /// Cluster KEY%s, containing K?LR, K?RR. - pub const KEY = extern struct { - /// key registers. - KLR: u32, - /// key registers. - KRR: u32, + pub const Region = extern struct { + /// OTFDEC region 3 configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// region on-the-fly decryption enable Note: Garbage is decrypted if region context (version, key, nonce) is not valid when this bit is set. + REG_EN: u1, + /// region config lock Note: This bit is set once. If this bit is set, it can only be reset to 0 if OTFDEC is reset. Setting this bit forces KEYLOCK bit to 1. + CONFIGLOCK: u1, + /// region key lock Note: This bit is set once: if this bit is set, it can only be reset to 0 if the OTFDEC is reset. + KEYLOCK: u1, + reserved4: u1, + /// operating mode This bitfield selects the OTFDEC operating mode for this region: Others: Reserved When MODE ≠ 11, the standard AES encryption mode is activated. When either of the MODE bits are changed, the region key and associated CRC are zeroed. + MODE: packed union { + raw: u2, + value: MODE, + }, + reserved8: u2, + /// region key 8-bit CRC When KEYLOCK = 0, KEYCRC bitfield is automatically computed by hardware while loading the key of this region in this exact sequence: KEYR0 then KEYR1 then KEYR2 then finally KEYR3 (all written once). A new computation starts as soon as a new valid sequence is initiated, and KEYCRC is read as zero until a valid sequence is completed. When KEYLOCK = 1, KEYCRC remains unchanged until the next reset. CRC computation is an 8-bit checksum using the standard CRC-8-CCITT algorithm X8 + X2 + X + 1 (according the convention). Source code is available in . This field is read only. Note: CRC information is updated only after the last bit of the key has been written. + KEYCRC: u8, + /// region firmware version This 16-bit bitfield must be correctly initialized before the region corresponding REG_EN bit is set in OTFDEC_RxCFGR. + REG_VERSION: u16, + }), + /// OTFDEC region 3 start address register. + STARTADDR: u32, + /// OTFDEC region 3 end address register. + ENDADDR: u32, + /// OTFDEC region 3 nonce register 0. + NONCER: [2]u32, + /// OTFDEC region 3 key register 0. + KEYR: [4]u32, }; }; - pub const i2c_v3 = struct { - pub const ADDMODE = enum(u1) { - /// 7-bit addressing mode - Bit7 = 0x0, - /// 10-bit addressing mode - Bit10 = 0x1, - }; - - pub const AUTOEND = enum(u1) { - /// Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low - Software = 0x0, - /// Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred - Automatic = 0x1, + pub const otg_v1 = struct { + pub const DPID = enum(u2) { + DATA0 = 0x0, + DATA2 = 0x1, + DATA1 = 0x2, + MDATA = 0x3, }; - pub const DIR = enum(u1) { - /// Write transfer, slave enters receiver mode - Write = 0x0, - /// Read transfer, slave enters transmitter mode - Read = 0x1, + pub const DSPD = enum(u2) { + /// High speed + HIGH_SPEED = 0x0, + /// Full speed using external ULPI PHY + FULL_SPEED_EXTERNAL = 0x1, + /// Full speed using internal embedded PHY + FULL_SPEED_INTERNAL = 0x3, + _, }; - pub const DNF = enum(u4) { - /// Digital filter disabled - NoFilter = 0x0, - /// Digital filter enabled and filtering capability up to 1 tI2CCLK - Filter1 = 0x1, - /// Digital filter enabled and filtering capability up to 2 tI2CCLK - Filter2 = 0x2, - /// Digital filter enabled and filtering capability up to 3 tI2CCLK - Filter3 = 0x3, - /// Digital filter enabled and filtering capability up to 4 tI2CCLK - Filter4 = 0x4, - /// Digital filter enabled and filtering capability up to 5 tI2CCLK - Filter5 = 0x5, - /// Digital filter enabled and filtering capability up to 6 tI2CCLK - Filter6 = 0x6, - /// Digital filter enabled and filtering capability up to 7 tI2CCLK - Filter7 = 0x7, - /// Digital filter enabled and filtering capability up to 8 tI2CCLK - Filter8 = 0x8, - /// Digital filter enabled and filtering capability up to 9 tI2CCLK - Filter9 = 0x9, - /// Digital filter enabled and filtering capability up to 10 tI2CCLK - Filter10 = 0xa, - /// Digital filter enabled and filtering capability up to 11 tI2CCLK - Filter11 = 0xb, - /// Digital filter enabled and filtering capability up to 12 tI2CCLK - Filter12 = 0xc, - /// Digital filter enabled and filtering capability up to 13 tI2CCLK - Filter13 = 0xd, - /// Digital filter enabled and filtering capability up to 14 tI2CCLK - Filter14 = 0xe, - /// Digital filter enabled and filtering capability up to 15 tI2CCLK - Filter15 = 0xf, + pub const EPTYP = enum(u2) { + CONTROL = 0x0, + ISOCHRONOUS = 0x1, + BULK = 0x2, + INTERRUPT = 0x3, }; - pub const HEADR = enum(u1) { - /// The master sends the complete 10 bit slave address read sequence - Complete = 0x0, - /// The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction - Partial = 0x1, + pub const PFIVL = enum(u2) { + /// 80% of the frame interval + FRAME_INTERVAL_80 = 0x0, + /// 85% of the frame interval + FRAME_INTERVAL_85 = 0x1, + /// 90% of the frame interval + FRAME_INTERVAL_90 = 0x2, + /// 95% of the frame interval + FRAME_INTERVAL_95 = 0x3, }; - pub const OAMSK = enum(u3) { - /// No mask - NoMask = 0x0, - /// OA2[1] is masked and don’t care. Only OA2[7:2] are compared - Mask1 = 0x1, - /// OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared - Mask2 = 0x2, - /// OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared - Mask3 = 0x3, - /// OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared - Mask4 = 0x4, - /// OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared - Mask5 = 0x5, - /// OA2[6:1] are masked and don’t care. Only OA2[7] is compared. - Mask6 = 0x6, - /// OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged - Mask7 = 0x7, + pub const PKTSTSD = enum(u4) { + /// Global OUT NAK (triggers an interrupt) + OUT_NAK = 0x1, + /// OUT data packet received + OUT_DATA_RX = 0x2, + /// OUT transfer completed (triggers an interrupt) + OUT_DATA_DONE = 0x3, + /// SETUP transaction completed (triggers an interrupt) + SETUP_DATA_DONE = 0x4, + /// SETUP data packet received + SETUP_DATA_RX = 0x6, + _, }; - pub const RELOAD = enum(u1) { - /// The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) - Completed = 0x0, - /// The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) - NotCompleted = 0x1, + pub const PKTSTSH = enum(u4) { + /// IN data packet received + IN_DATA_RX = 0x2, + /// IN transfer completed (triggers an interrupt) + IN_DATA_DONE = 0x3, + /// Data toggle error (triggers an interrupt) + DATA_TOGGLE_ERR = 0x5, + /// Channel halted (triggers an interrupt) + CHANNEL_HALTED = 0x7, + _, }; - /// Inter-integrated circuit - pub const I2C = extern struct { - /// Control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Peripheral enable - PE: u1, - /// TX Interrupt enable - TXIE: u1, - /// RX Interrupt enable - RXIE: u1, - /// Address match interrupt enable (slave only) - ADDRIE: u1, - /// Not acknowledge received interrupt enable - NACKIE: u1, - /// STOP detection Interrupt enable - STOPIE: u1, - /// Transfer Complete interrupt enable - TCIE: u1, - /// Error interrupts enable - ERRIE: u1, - /// Digital noise filter - DNF: packed union { - raw: u4, - value: DNF, - }, - /// Analog noise filter OFF - ANFOFF: u1, - reserved14: u1, - /// DMA transmission requests enable - TXDMAEN: u1, - /// DMA reception requests enable - RXDMAEN: u1, - /// Slave byte control - SBC: u1, - /// Clock stretching disable - NOSTRETCH: u1, - reserved19: u1, - /// General call enable - GCEN: u1, - /// SMBus Host address enable - SMBHEN: u1, - /// SMBus Device Default address enable - SMBDEN: u1, - /// SMBUS alert enable - ALERTEN: u1, - /// PEC enable - PECEN: u1, - /// Fast-mode Plus 20 mA drive enable. - FMP: u1, - reserved30: u5, - /// Address match flag (ADDR) automatic clear. - ADDRACLR: u1, - /// STOP detection flag (STOPF) automatic clear. - STOPFACLR: u1, - }), - /// Control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Slave address bit (master mode) - SADD: u10, - /// Transfer direction (master mode) - DIR: packed union { - raw: u1, - value: DIR, - }, - /// 10-bit addressing mode (master mode) - ADD10: packed union { - raw: u1, - value: ADDMODE, - }, - /// 10-bit address header only read direction (master receiver mode) - HEAD10R: packed union { - raw: u1, - value: HEADR, - }, - /// Start generation - START: u1, - /// Stop generation (master mode) - STOP: u1, - /// NACK generation (slave mode) - NACK: u1, - /// Number of bytes - NBYTES: u8, - /// NBYTES reload mode - RELOAD: packed union { - raw: u1, - value: RELOAD, - }, - /// Automatic end mode (master mode) - AUTOEND: packed union { - raw: u1, - value: AUTOEND, - }, - /// Packet error checking byte - PECBYTE: u1, - padding: u5, - }), - /// Own address register 1 - OAR1: mmio.Mmio(packed struct(u32) { - /// Interface address - OA1: u10, - /// Own Address 1 10-bit mode - OA1MODE: packed union { - raw: u1, - value: ADDMODE, - }, - reserved15: u4, - /// Own Address 1 enable - OA1EN: u1, - padding: u16, - }), - /// Own address register 2 - OAR2: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Interface address - OA2: u7, - /// Own Address 2 masks - OA2MSK: packed union { - raw: u3, - value: OAMSK, - }, - reserved15: u4, - /// Own Address 2 enable - OA2EN: u1, - padding: u16, + /// USB on the go + pub const OTG = extern struct { + /// Control and status register + GOTGCTL: mmio.Mmio(packed struct(u32) { + /// Session request success + SRQSCS: u1, + /// Session request + SRQ: u1, + /// VBUS valid override enable + VBVALOEN: u1, + /// VBUS valid override value + VBVALOVAL: u1, + /// A-peripheral session valid override enable + AVALOEN: u1, + /// A-peripheral session valid override value + AVALOVAL: u1, + /// B-peripheral session valid override enable + BVALOEN: u1, + /// B-peripheral session valid override value + BVALOVAL: u1, + /// Host negotiation success + HNGSCS: u1, + /// HNP request + HNPRQ: u1, + /// Host set HNP enable + HSHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + /// Embedded host enable + EHEN: u1, + reserved16: u3, + /// Connector ID status + CIDSTS: u1, + /// Long/short debounce time + DBCT: u1, + /// A-session valid + ASVLD: u1, + /// B-session valid + BSVLD: u1, + padding: u12, }), - /// Timing register - TIMINGR: mmio.Mmio(packed struct(u32) { - /// SCL low period (master mode) - SCLL: u8, - /// SCL high period (master mode) - SCLH: u8, - /// Data hold time - SDADEL: u4, - /// Data setup time - SCLDEL: u4, - reserved28: u4, - /// Timing prescaler - PRESC: u4, + /// Interrupt register + GOTGINT: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Session end detected + SEDET: u1, + reserved8: u5, + /// Session request success status change + SRSSCHG: u1, + /// Host negotiation success status change + HNSSCHG: u1, + reserved17: u7, + /// Host negotiation detected + HNGDET: u1, + /// A-device timeout change + ADTOCHG: u1, + /// Debounce done + DBCDNE: u1, + /// ID input pin changed + IDCHNG: u1, + padding: u11, }), - /// Timeout register - TIMEOUTR: mmio.Mmio(packed struct(u32) { - /// Bus timeout A - TIMEOUTA: u12, - /// Idle clock timeout detection - TIDLE: u1, - reserved15: u2, - /// Clock timeout enable - TIMOUTEN: u1, - /// Bus timeout B - TIMEOUTB: u12, - reserved31: u3, - /// Extended clock timeout enable - TEXTEN: u1, + /// AHB configuration register + GAHBCFG: mmio.Mmio(packed struct(u32) { + /// Global interrupt mask + GINT: u1, + /// Burst length/type + HBSTLEN: u4, + /// DMA enable + DMAEN: u1, + reserved7: u1, + /// TxFIFO empty level + TXFELVL: u1, + /// Periodic TxFIFO empty level + PTXFELVL: u1, + padding: u23, }), - /// Interrupt and Status register - ISR: mmio.Mmio(packed struct(u32) { - /// Transmit data register empty (transmitters) - TXE: u1, - /// Transmit interrupt status (transmitters) - TXIS: u1, - /// Receive data register not empty (receivers) - RXNE: u1, - /// Address matched (slave mode) - ADDR: u1, - /// Not acknowledge received flag - NACKF: u1, - /// Stop detection flag - STOPF: u1, - /// Transfer Complete (master mode) - TC: u1, - /// Transfer Complete Reload - TCR: u1, - /// Bus error - BERR: u1, - /// Arbitration lost - ARLO: u1, - /// Overrun/Underrun (slave mode) - OVR: u1, - /// PEC Error in reception - PECERR: u1, - /// Timeout or t_low detection flag - TIMEOUT: u1, - /// SMBus alert - ALERT: u1, + /// USB configuration register + GUSBCFG: mmio.Mmio(packed struct(u32) { + /// FS timeout calibration + TOCAL: u3, + reserved6: u3, + /// Full-speed internal serial transceiver enable + PHYSEL: u1, + reserved8: u1, + /// SRP-capable + SRPCAP: u1, + /// HNP-capable + HNPCAP: u1, + /// USB turnaround time + TRDT: u4, reserved15: u1, - /// Bus busy - BUSY: u1, - /// Transfer direction (Slave mode) - DIR: packed union { - raw: u1, - value: DIR, - }, - /// Address match code (Slave mode) - ADDCODE: u7, - padding: u8, - }), - /// Interrupt clear register - ICR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Address Matched flag clear - ADDRCF: u1, - /// Not Acknowledge flag clear - NACKCF: u1, - /// Stop detection flag clear - STOPCF: u1, - reserved8: u2, - /// Bus error flag clear - BERRCF: u1, - /// Arbitration lost flag clear - ARLOCF: u1, - /// Overrun/Underrun flag clear - OVRCF: u1, - /// PEC Error flag clear - PECCF: u1, - /// Timeout detection flag clear - TIMOUTCF: u1, - /// Alert flag clear - ALERTCF: u1, - padding: u18, + /// PHY Low-power clock select + PHYLPCS: u1, + reserved17: u1, + /// ULPI FS/LS select + ULPIFSLS: u1, + /// ULPI Auto-resume + ULPIAR: u1, + /// ULPI Clock SuspendM + ULPICSM: u1, + /// ULPI External VBUS Drive + ULPIEVBUSD: u1, + /// ULPI external VBUS indicator + ULPIEVBUSI: u1, + /// TermSel DLine pulsing selection + TSDPS: u1, + /// Indicator complement + PCCI: u1, + /// Indicator pass through + PTCI: u1, + /// ULPI interface protect disable + ULPIIPD: u1, + reserved29: u3, + /// Force host mode + FHMOD: u1, + /// Force device mode + FDMOD: u1, + /// Corrupt Tx packet + CTXPKT: u1, }), - /// PEC register - PECR: mmio.Mmio(packed struct(u32) { - /// Packet error checking register - PEC: u8, - padding: u24, + /// Reset register + GRSTCTL: mmio.Mmio(packed struct(u32) { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HSRST: u1, + /// Host frame counter reset + FCRST: u1, + reserved4: u1, + /// RxFIFO flush + RXFFLSH: u1, + /// TxFIFO flush + TXFFLSH: u1, + /// TxFIFO number + TXFNUM: u5, + reserved30: u19, + /// DMA request signal enabled for USB OTG HS + DMAREQ: u1, + /// AHB master idle + AHBIDL: u1, }), - /// Receive data register - RXDR: mmio.Mmio(packed struct(u32) { - /// 8-bit receive data - RXDATA: u8, - padding: u24, + /// Core interrupt register + GINTSTS: mmio.Mmio(packed struct(u32) { + /// Current mode of operation + CMOD: u1, + /// Mode mismatch interrupt + MMIS: u1, + /// OTG interrupt + OTGINT: u1, + /// Start of frame + SOF: u1, + /// RxFIFO non-empty + RXFLVL: u1, + /// Non-periodic TxFIFO empty + NPTXFE: u1, + /// Global IN non-periodic NAK effective + GINAKEFF: u1, + /// Global OUT NAK effective + GOUTNAKEFF: u1, + reserved10: u2, + /// Early suspend + ESUSP: u1, + /// USB suspend + USBSUSP: u1, + /// USB reset + USBRST: u1, + /// Enumeration done + ENUMDNE: u1, + /// Isochronous OUT packet dropped interrupt + ISOODRP: u1, + /// End of periodic frame interrupt + EOPF: u1, + reserved18: u2, + /// IN endpoint interrupt + IEPINT: u1, + /// OUT endpoint interrupt + OEPINT: u1, + /// Incomplete isochronous IN transfer + IISOIXFR: u1, + /// Incomplete periodic transfer (host mode) / Incomplete isochronous OUT transfer (device mode) + IPXFR_INCOMPISOOUT: u1, + /// Data fetch suspended + DATAFSUSP: u1, + reserved24: u1, + /// Host port interrupt + HPRTINT: u1, + /// Host channels interrupt + HCINT: u1, + /// Periodic TxFIFO empty + PTXFE: u1, + reserved28: u1, + /// Connector ID status change + CIDSCHG: u1, + /// Disconnect detected interrupt + DISCINT: u1, + /// Session request/new session detected interrupt + SRQINT: u1, + /// Resume/remote wakeup detected interrupt + WKUPINT: u1, }), - /// Transmit data register - TXDR: mmio.Mmio(packed struct(u32) { - /// 8-bit transmit data - TXDATA: u8, - padding: u24, + /// Interrupt mask register + GINTMSK: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Mode mismatch interrupt mask + MMISM: u1, + /// OTG interrupt mask + OTGINT: u1, + /// Start of frame mask + SOFM: u1, + /// Receive FIFO non-empty mask + RXFLVLM: u1, + /// Non-periodic TxFIFO empty mask + NPTXFEM: u1, + /// Global non-periodic IN NAK effective mask + GINAKEFFM: u1, + /// Global OUT NAK effective mask + GONAKEFFM: u1, + reserved10: u2, + /// Early suspend mask + ESUSPM: u1, + /// USB suspend mask + USBSUSPM: u1, + /// USB reset mask + USBRST: u1, + /// Enumeration done mask + ENUMDNEM: u1, + /// Isochronous OUT packet dropped interrupt mask + ISOODRPM: u1, + /// End of periodic frame interrupt mask + EOPFM: u1, + reserved17: u1, + /// Endpoint mismatch interrupt mask + EPMISM: u1, + /// IN endpoints interrupt mask + IEPINT: u1, + /// OUT endpoints interrupt mask + OEPINT: u1, + /// Incomplete isochronous IN transfer mask + IISOIXFRM: u1, + /// Incomplete periodic transfer mask (host mode) / Incomplete isochronous OUT transfer mask (device mode) + IPXFRM_IISOOXFRM: u1, + /// Data fetch suspended mask + FSUSPM: u1, + /// Reset detected interrupt mask + RSTDE: u1, + /// Host port interrupt mask + PRTIM: u1, + /// Host channels interrupt mask + HCIM: u1, + /// Periodic TxFIFO empty mask + PTXFEM: u1, + /// LPM interrupt mask + LPMINTM: u1, + /// Connector ID status change mask + CIDSCHGM: u1, + /// Disconnect detected interrupt mask + DISCINT: u1, + /// Session request/new session detected interrupt mask + SRQIM: u1, + /// Resume/remote wakeup detected interrupt mask + WUIM: u1, }), - }; - }; - - pub const comp_u0 = struct { - pub const BLANKING = enum(u5) { - /// No blanking. - NoBlanking = 0x0, - /// TIM1 OC4 enabled as blanking source - TIM1OC4 = 0x1, - /// TIM1 OC5 enabled as blanking source - TIM1OC5 = 0x2, - /// TIM5 OC3 enabled as blanking source - TIM2OC3 = 0x4, - /// TIM3 OC3 enabled as blanking source - TIM3OC3 = 0x8, - /// TIM15 OC2 enabled as blanking source - TIM15OC2 = 0x10, - _, - }; - - pub const HYST = enum(u2) { - None = 0x0, - Low = 0x1, - Medium = 0x2, - High = 0x3, - }; - - pub const PWRMODE = enum(u2) { - /// High speed / full power. - HighSpeed = 0x0, - /// Medium speed / medium power. - MediumSpeed = 0x1, - /// Very-low speed / ultra-low power. - LowSpeed = 0x3, - _, - }; - - pub const Polarity = enum(u1) { - /// Output is not inverted. - NotInverted = 0x0, - /// Output is inverted. - Inverted = 0x1, - }; - - pub const WindowMode = enum(u1) { - /// Signal selected with INPSEL[2:0] bitfield of this register. - ThisInpsel = 0x0, - /// Signal selected with INPSEL[2:0] bitfield of the other register (required for window mode). - OtherInpsel = 0x1, - }; - - pub const WindowOut = enum(u1) { - /// Comparator 1 value. - COMP1_VALUE = 0x0, - /// Comparator 1 value XOR comparator 2 value (required for window mode). - @"COMP1_VALUE XOR COMP2_VALUE" = 0x1, - }; - - /// Comparator. - pub const COMP = extern struct { - /// Comparator control and status register. - CSR: mmio.Mmio(packed struct(u32) { - /// Enable - EN: u1, - reserved4: u3, - /// Input minus selection bits. - INMSEL: u4, - /// Input plus selection bit. - INPSEL: u3, - /// Comparator 1 noninverting input selector for window mode. - WINMODE: packed union { - raw: u1, - value: WindowMode, - }, - reserved14: u2, - /// Comparator 1 output selector. - WINOUT: packed union { - raw: u1, - value: WindowOut, - }, - /// Polarity selection bit. - POLARITY: packed union { - raw: u1, - value: Polarity, - }, - /// Hysteresis selection bits. - HYST: packed union { - raw: u2, - value: HYST, - }, - /// Power Mode. - PWRMODE: packed union { + /// Receive status debug read register + GRXSTSR: mmio.Mmio(packed struct(u32) { + /// Endpoint number (device mode) / Channel number (host mode) + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: packed union { raw: u2, - value: PWRMODE, + value: DPID, }, - /// Blanking source selection bits. - BLANKSEL: packed union { - raw: u5, - value: BLANKING, + /// Packet status (device mode) + PKTSTSD: packed union { + raw: u4, + value: PKTSTSD, }, - reserved30: u5, - /// Output status bit. - VALUE: u1, - /// Register lock bit. - LOCK: u1, + /// Frame number (device mode) + FRMNUM: u4, + padding: u7, }), - }; - }; - - pub const iwdg_v3 = struct { - pub const KEY = enum(u16) { - /// Enable access to PR, RLR and WINR registers (0x5555) - Enable = 0x5555, - /// Reset the watchdog value (0xAAAA) - Reset = 0xaaaa, - /// Start the watchdog (0xCCCC) - Start = 0xcccc, - _, - }; - - pub const PR = enum(u4) { - /// Divider /4 - DivideBy4 = 0x0, - /// Divider /8 - DivideBy8 = 0x1, - /// Divider /16 - DivideBy16 = 0x2, - /// Divider /32 - DivideBy32 = 0x3, - /// Divider /64 - DivideBy64 = 0x4, - /// Divider /128 - DivideBy128 = 0x5, - /// Divider /256 - DivideBy256 = 0x6, - /// Divider /512 - DivideBy512 = 0x7, - /// Divider /1024 - DivideBy1024 = 0x8, - _, - }; - - /// Independent watchdog - pub const IWDG = extern struct { - /// Key register - KR: mmio.Mmio(packed struct(u32) { - /// Key value (write only, read 0000h) - KEY: packed union { - raw: u16, - value: KEY, + /// Status read and pop register + GRXSTSP: mmio.Mmio(packed struct(u32) { + /// Endpoint number (device mode) / Channel number (host mode) + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: packed union { + raw: u2, + value: DPID, }, - padding: u16, - }), - /// Prescaler register - PR: mmio.Mmio(packed struct(u32) { - /// Prescaler divider - PR: packed union { + /// Packet status (device mode) + PKTSTSD: packed union { raw: u4, - value: PR, + value: PKTSTSD, }, - padding: u28, + /// Frame number (device mode) + FRMNUM: u4, + padding: u7, }), - /// Reload register - RLR: mmio.Mmio(packed struct(u32) { - /// Watchdog counter reload value - RL: u12, - padding: u20, + /// Receive FIFO size register + GRXFSIZ: mmio.Mmio(packed struct(u32) { + /// RxFIFO depth + RXFD: u16, + padding: u16, }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Watchdog prescaler value update - PVU: u1, - /// Watchdog counter reload value update - RVU: u1, - /// Watchdog counter window value update - WVU: u1, - /// Watchdog interrupt comparator value update This bit is set by hardware to indicate that an update of the interrupt comparator value (EWIT[11:0]) or an update of the EWIE is ongoing. It is reset by hardware when the update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The EWIT[11:0] and EWIE fields can be updated only when EWU bit is reset. - EWU: u1, - reserved14: u10, - /// Watchdog early interrupt flag This bit is set to ‘1’ by hardware in order to indicate that an early interrupt is pending. This bit must be cleared by the software by writing the bit EWIC of IWDG_EWCR register to ‘1’. - EWIF: u1, - padding: u17, + /// Endpoint 0 transmit FIFO size register (device mode) + DIEPTXF0: mmio.Mmio(packed struct(u32) { + /// RAM start address + SA: u16, + /// FIFO depth + FD: u16, }), - /// Window register - WINR: mmio.Mmio(packed struct(u32) { - /// Watchdog counter window value - WIN: u12, - padding: u20, + /// Non-periodic transmit FIFO/queue status register (host mode) + HNPTXSTS: mmio.Mmio(packed struct(u32) { + /// Non-periodic TxFIFO space available + NPTXFSAV: u16, + /// Non-periodic transmit request queue space available + NPTQXSAV: u8, + /// Top of the non-periodic transmit request queue + NPTXQTOP: u7, + padding: u1, }), - /// IWDG early wakeup interrupt register. - EWCR: mmio.Mmio(packed struct(u32) { - /// Watchdog counter window value These bits are write access protected (see ). They are written by software to define at which position of the IWDCNT down-counter the early wakeup interrupt must be generated. The early interrupt is generated when the IWDCNT is lower or equal to EWIT[11:0] - 1. EWIT[11:0] must be bigger than 1. An interrupt is generated only if EWIE = 1. The EWU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the Early wakeup comparator value and the Interrupt enable bit from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the EWU bit in the is reset. - EWIT: u12, - reserved14: u2, - /// Watchdog early interrupt acknowledge The software must write a 1 into this bit in order to acknowledge the early wakeup interrupt and to clear the EWIF flag. Writing 0 has not effect, reading this flag returns a 0. - EWIC: u1, - /// Watchdog early interrupt enable Set and reset by software. The EWU bit in the must be reset to be able to change the value of this bit. - EWIE: u1, - padding: u16, + /// OTG I2C access register + GI2CCTL: mmio.Mmio(packed struct(u32) { + /// I2C Read/Write Data + RWDATA: u8, + /// I2C Register Address + REGADDR: u8, + /// I2C Address + ADDR: u7, + /// I2C Enable + I2CEN: u1, + /// I2C ACK + ACK: u1, + reserved26: u1, + /// I2C Device Address + I2CDEVADR: u2, + /// I2C DatSe0 USB mode + I2CDATSE0: u1, + reserved30: u1, + /// Read/Write Indicator + RW: u1, + /// I2C Busy/Done + BSYDNE: u1, }), - }; - }; - - pub const dbgmcu_g4 = struct { - /// Debug support - pub const DBGMCU = extern struct { - /// MCU Device ID Code Register - IDCODE: mmio.Mmio(packed struct(u32) { - /// Device Identifier - DEV_ID: u16, - /// Revision Identifier - REV_ID: u16, + reserved56: [4]u8, + /// General core configuration register, for core_id 0x0000_1xxx + GCCFG_V1: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Power down + PWRDWN: u1, + reserved18: u1, + /// Enable the VBUS "A" sensing device + VBUSASEN: u1, + /// Enable the VBUS "B" sensing device + VBUSBSEN: u1, + /// SOF output enable + SOFOUTEN: u1, + /// VBUS sensing disable + NOVBUSSENS: u1, + padding: u10, }), - /// Debug MCU Configuration Register - CR: mmio.Mmio(packed struct(u32) { - /// Debug Sleep Mode - DBG_SLEEP: u1, - /// Debug Stop Mode - DBG_STOP: u1, - /// Debug Standby Mode - DBG_STANDBY: u1, - reserved5: u2, - /// Trace pin assignment control - TRACE_IOEN: u1, - /// Trace pin assignment control - TRACE_MODE: u2, - padding: u24, + /// Core ID register + CID: mmio.Mmio(packed struct(u32) { + /// Product ID field + PRODUCT_ID: u32, }), - /// APB Low Freeze Register 1 - APB1LFZR: mmio.Mmio(packed struct(u32) { - /// Debug Timer 2 stopped when Core is halted - TIM2: u1, - /// TIM3 counter stopped when core is halted - TIM3: u1, - /// TIM4 counter stopped when core is halted - TIM4: u1, - /// TIM5 counter stopped when core is halted - TIM5: u1, - /// Debug Timer 6 stopped when Core is halted - TIM6: u1, - /// TIM7 counter stopped when core is halted - TIM7: u1, - reserved10: u4, - /// Debug RTC stopped when Core is halted - RTC: u1, - /// Debug Window Wachdog stopped when Core is halted - WWDG: u1, - /// Debug Independent Wachdog stopped when Core is halted - IWDG: u1, - reserved21: u8, - /// I2C1 SMBUS timeout mode stopped when core is halted - I2C1: u1, - /// I2C2 SMBUS timeout mode stopped when core is halted - I2C2: u1, - reserved30: u7, - /// I2C3 SMBUS timeout mode stopped when core is halted - I2C3: u1, - /// LPTIM1 counter stopped when core is halted - LPTIMER: u1, + reserved84: [20]u8, + /// OTG core LPM configuration register + GLPMCFG: mmio.Mmio(packed struct(u32) { + /// LPM support enable + LPMEN: u1, + /// LPM token acknowledge enable + LPMACK: u1, + /// Best effort service latency + BESL: u4, + /// bRemoteWake value + REMWAKE: u1, + /// L1 Shallow Sleep enable + L1SSEN: u1, + /// BESL threshold + BESLTHRS: u4, + /// L1 deep sleep enable + L1DSEN: u1, + /// LPM response + LPMRST: u2, + /// Port sleep status + SLPSTS: u1, + /// Sleep State Resume OK + L1RSMOK: u1, + /// LPM Channel Index + LPMCHIDX: u4, + /// LPM retry count + LPMRCNT: u3, + /// Send LPM transaction + SNDLPM: u1, + /// LPM retry count status + LPMRCNTSTS: u3, + /// Enable best effort service latency + ENBESL: u1, + padding: u3, }), - /// APB Low Freeze Register 2 - APB1HFZR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// I2C4 - I2C4: u1, - padding: u30, + reserved256: [168]u8, + /// Host periodic transmit FIFO size register + HPTXFSIZ: mmio.Mmio(packed struct(u32) { + /// RAM start address + SA: u16, + /// FIFO depth + FD: u16, }), - /// APB High Freeze Register - APB2FZR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 counter stopped when core is halted - TIM1: u1, - reserved13: u1, - /// TIM8 counter stopped when core is halted - TIM8: u1, - reserved16: u2, - /// TIM15 counter stopped when core is halted - TIM15: u1, - /// TIM16 counter stopped when core is halted - TIM16: u1, - /// TIM17 counter stopped when core is halted - TIM17: u1, - reserved20: u1, - /// TIM20counter stopped when core is halted - TIM20: u1, - reserved26: u5, - /// HRTIM0 - HRTIM0: u1, - /// HRTIM0 - HRTIM1: u1, - /// HRTIM0 - HRTIM2: u1, - /// HRTIM0 - HRTIM3: u1, - padding: u2, + /// Device IN endpoint transmit FIFO size register + DIEPTXF: [7]mmio.Mmio(packed struct(u32) { + /// RAM start address + SA: u16, + /// FIFO depth + FD: u16, }), - }; - }; - - pub const sdmmc_v2 = struct { - /// SDMMC - pub const SDMMC = extern struct { - /// SDMMC power control register - POWER: mmio.Mmio(packed struct(u32) { - /// SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11. - PWRCTRL: u2, - /// Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence: - VSWITCH: u1, - /// Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response: - VSWITCHEN: u1, - /// Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). - DIRPOL: u1, - padding: u27, + reserved1024: [736]u8, + /// Host configuration register + HCFG: mmio.Mmio(packed struct(u32) { + /// FS/LS PHY clock select + FSLSPCS: u2, + /// FS- and LS-only support + FSLSS: u1, + padding: u29, }), - /// The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width. - CLKCR: mmio.Mmio(packed struct(u32) { - /// Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.. - CLKDIV: u10, - reserved12: u2, - /// Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: - PWRSAV: u1, - reserved14: u1, - /// Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) - WIDBUS: u2, - /// SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - NEGEDGE: u1, - /// Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11. - HWFC_EN: u1, - /// Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0) - DDR: u1, - /// Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) - BUSSPEED: u1, - /// Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) - SELCLKRX: u2, - padding: u10, + /// Host frame interval register + HFIR: mmio.Mmio(packed struct(u32) { + /// Frame interval + FRIVL: u16, + padding: u16, }), - /// The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. - ARGR: mmio.Mmio(packed struct(u32) { - /// Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. - CMDARG: u32, + /// Host frame number/frame time remaining register + HFNUM: mmio.Mmio(packed struct(u32) { + /// Frame number + FRNUM: u16, + /// Frame time remaining + FTREM: u16, }), - /// The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). - CMDR: mmio.Mmio(packed struct(u32) { - /// Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. - CMDINDEX: u6, - /// The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent. - CMDTRANS: u1, - /// The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent. - CMDSTOP: u1, - /// Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. - WAITRESP: u2, - /// CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode. - WAITINT: u1, - /// CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card. - WAITPEND: u1, - /// Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0. - CPSMEN: u1, - /// Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state. - DTHOLD: u1, - /// Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) - BOOTMODE: u1, - /// Enable boot mode procedure. - BOOTEN: u1, - /// The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1. - CMDSUSPEND: u1, - padding: u15, + reserved1040: [4]u8, + /// Periodic transmit FIFO/queue status register + HPTXSTS: mmio.Mmio(packed struct(u32) { + /// Periodic transmit data FIFO space available + PTXFSAVL: u16, + /// Periodic transmit request queue space available + PTXQSAV: u8, + /// Top of the periodic transmit request queue + PTXQTOP: u8, }), - /// SDMMC command response register - RESPCMDR: mmio.Mmio(packed struct(u32) { - /// Response command index - RESPCMD: u6, - padding: u26, + /// Host all channels interrupt register + HAINT: mmio.Mmio(packed struct(u32) { + /// Channel interrupts + HAINT: u16, + padding: u16, }), - /// The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. - RESPR: [4]mmio.Mmio(packed struct(u32) { - /// see Table 432 - CARDSTATUS: u32, + /// Host all channels interrupt mask register + HAINTMSK: mmio.Mmio(packed struct(u32) { + /// Channel interrupt mask + HAINTM: u16, + padding: u16, }), - /// The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. - DTIMER: mmio.Mmio(packed struct(u32) { - /// Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods. - DATATIME: u32, + reserved1088: [36]u8, + /// Host port control and status register + HPRT: mmio.Mmio(packed struct(u32) { + /// Port connect status + PCSTS: u1, + /// Port connect detected + PCDET: u1, + /// Port enable + PENA: u1, + /// Port enable/disable change + PENCHNG: u1, + /// Port overcurrent active + POCA: u1, + /// Port overcurrent change + POCCHNG: u1, + /// Port resume + PRES: u1, + /// Port suspend + PSUSP: u1, + /// Port reset + PRST: u1, + reserved10: u1, + /// Port line status + PLSTS: u2, + /// Port power + PPWR: u1, + /// Port test control + PTCTL: u4, + /// Port speed + PSPD: u2, + padding: u13, }), - /// The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. - DLENR: mmio.Mmio(packed struct(u32) { - /// Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0. - DATALENGTH: u25, - padding: u7, + reserved1280: [188]u8, + /// Host channel characteristics register + HCCHAR: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: packed union { + raw: u2, + value: EPTYP, + }, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, }), - /// The SDMMC_DCTRL register control the data path state machine (DPSM). - DCTRL: mmio.Mmio(packed struct(u32) { - /// Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards. - DTEN: u1, - /// Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). - DTDIR: u1, - /// Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). - DTMODE: u2, - /// Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered) - DBLOCKSIZE: u4, - /// Read wait start. If this bit is set, read wait operation starts. - RWSTART: u1, - /// Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state. - RWSTOP: u1, - /// Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). - RWMOD: u1, - /// SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. - SDIOEN: u1, - /// Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). - BOOTACKEN: u1, - /// FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs. - FIFORST: u1, - padding: u18, + /// Host channel split control register + HCSPLT: u32, + /// Host channel interrupt register + HCINT: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, }), - /// The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. - DCNTR: mmio.Mmio(packed struct(u32) { - /// Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect. - DATACOUNT: u25, - padding: u7, + /// Host channel mask register + HCINTMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// Response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, }), - /// The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) - STAR: mmio.Mmio(packed struct(u32) { - /// Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - CCRCFAIL: u1, - /// Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - DCRCFAIL: u1, - /// Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. - CTIMEOUT: u1, - /// Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - DTIMEOUT: u1, - /// Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - TXUNDERR: u1, - /// Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - RXOVERR: u1, - /// Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - CMDREND: u1, - /// Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - CMDSENT: u1, - /// Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - DATAEND: u1, - /// Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - DHOLD: u1, - /// Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - DBCKEND: u1, - /// Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - DABORT: u1, - /// Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. - DPSMACT: u1, - /// Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. - CPSMACT: u1, - /// Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. - TXFIFOHE: u1, - /// Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. - RXFIFOHF: u1, - /// Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty. - TXFIFOF: u1, - /// Receive FIFO full This bit is cleared when one FIFO location becomes empty. - RXFIFOF: u1, - /// Transmit FIFO empty This bit is cleared when one FIFO location becomes full. - TXFIFOE: u1, - /// Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full. - RXFIFOE: u1, - /// Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt. - BUSYD0: u1, - /// end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - BUSYD0END: u1, - /// SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - SDIOIT: u1, - /// Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - ACKFAIL: u1, - /// Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - ACKTIMEOUT: u1, - /// Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - VSWEND: u1, - /// SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - CKSTOP: u1, - /// IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - IDMATE: u1, - /// IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. - IDMABTC: u1, - padding: u3, + /// Host channel transfer size register + HCTSIZ: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, }), - /// The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. - ICR: mmio.Mmio(packed struct(u32) { - /// CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. - CCRCFAILC: u1, - /// DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. - DCRCFAILC: u1, - /// CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. - CTIMEOUTC: u1, - /// DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. - DTIMEOUTC: u1, - /// TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. - TXUNDERRC: u1, - /// RXOVERR flag clear bit Set by software to clear the RXOVERR flag. - RXOVERRC: u1, - /// CMDREND flag clear bit Set by software to clear the CMDREND flag. - CMDRENDC: u1, - /// CMDSENT flag clear bit Set by software to clear the CMDSENT flag. - CMDSENTC: u1, - /// DATAEND flag clear bit Set by software to clear the DATAEND flag. - DATAENDC: u1, - /// DHOLD flag clear bit Set by software to clear the DHOLD flag. - DHOLDC: u1, - /// DBCKEND flag clear bit Set by software to clear the DBCKEND flag. - DBCKENDC: u1, - /// DABORT flag clear bit Set by software to clear the DABORT flag. - DABORTC: u1, - reserved21: u9, - /// BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag. - BUSYD0ENDC: u1, - /// SDIOIT flag clear bit Set by software to clear the SDIOIT flag. - SDIOITC: u1, - /// ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag. - ACKFAILC: u1, - /// ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag. - ACKTIMEOUTC: u1, - /// VSWEND flag clear bit Set by software to clear the VSWEND flag. - VSWENDC: u1, - /// CKSTOP flag clear bit Set by software to clear the CKSTOP flag. - CKSTOPC: u1, - /// IDMA transfer error clear bit Set by software to clear the IDMATE flag. - IDMATEC: u1, - /// IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag. - IDMABTCC: u1, - padding: u3, + reserved2048: [748]u8, + /// Device configuration register + DCFG: mmio.Mmio(packed struct(u32) { + /// Device speed + DSPD: packed union { + raw: u2, + value: DSPD, + }, + /// Non-zero-length status OUT handshake + NZLSOHSK: u1, + reserved4: u1, + /// Device address + DAD: u7, + /// Periodic frame interval + PFIVL: packed union { + raw: u2, + value: PFIVL, + }, + reserved14: u1, + /// Transceiver delay + XCVRDLY: u1, + padding: u17, }), - /// The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. - MASKR: mmio.Mmio(packed struct(u32) { - /// Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. - CCRCFAILIE: u1, - /// Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. - DCRCFAILIE: u1, - /// Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. - CTIMEOUTIE: u1, - /// Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. - DTIMEOUTIE: u1, - /// Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. - TXUNDERRIE: u1, - /// Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. - RXOVERRIE: u1, - /// Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. - CMDRENDIE: u1, - /// Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. - CMDSENTIE: u1, - /// Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. - DATAENDIE: u1, - /// Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. - DHOLDIE: u1, - /// Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. - DBCKENDIE: u1, - /// Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. - DABORTIE: u1, - reserved14: u2, - /// Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. - TXFIFOHEIE: u1, - /// Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. - RXFIFOHFIE: u1, - reserved17: u1, - /// Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. - RXFIFOFIE: u1, - /// Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. - TXFIFOEIE: u1, - reserved21: u2, - /// BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. - BUSYD0ENDIE: u1, - /// SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. - SDIOITIE: u1, - /// Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. - ACKFAILIE: u1, - /// Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. - ACKTIMEOUTIE: u1, - /// Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. - VSWENDIE: u1, - /// Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. - CKSTOPIE: u1, - reserved28: u1, - /// IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. - IDMABTCIE: u1, - padding: u3, + /// Device control register + DCTL: mmio.Mmio(packed struct(u32) { + /// Remote wakeup signaling + RWUSIG: u1, + /// Soft disconnect + SDIS: u1, + /// Global IN NAK status + GINSTS: u1, + /// Global OUT NAK status + GONSTS: u1, + /// Test control + TCTL: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on programming done + POPRGDNE: u1, + padding: u20, }), - /// The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. - ACKTIMER: mmio.Mmio(packed struct(u32) { - /// Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods. - ACKTIME: u25, - padding: u7, + /// Device status register + DSTS: mmio.Mmio(packed struct(u32) { + /// Suspend status + SUSPSTS: u1, + /// Enumerated speed + ENUMSPD: packed union { + raw: u2, + value: DSPD, + }, + /// Erratic error + EERR: u1, + reserved8: u4, + /// Frame number of the received SOF + FNSOF: u14, + padding: u10, }), - reserved80: [12]u8, - /// The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. - IDMACTRLR: mmio.Mmio(packed struct(u32) { - /// IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). - IDMAEN: u1, - /// Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). - IDMABMODE: u1, - /// Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware. - IDMABACT: u1, - padding: u29, + reserved2064: [4]u8, + /// Device IN endpoint common interrupt mask register + DIEPMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// Timeout condition mask (Non-isochronous endpoints) + TOM: u1, + /// IN token received when TxFIFO empty mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch mask + INEPNMM: u1, + /// IN endpoint NAK effective mask + INEPNEM: u1, + padding: u25, }), - /// The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration. - IDMABSIZER: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). - IDMABNDT: u8, - padding: u19, + /// Device OUT endpoint common interrupt mask register + DOEPMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// SETUP phase done mask + STUPM: u1, + /// OUT token received when endpoint disabled mask + OTEPDM: u1, + padding: u27, }), - /// The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration. - IDMABASE0R: mmio.Mmio(packed struct(u32) { - /// Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1). - IDMABASE0: u32, + /// Device all endpoints interrupt register + DAINT: mmio.Mmio(packed struct(u32) { + /// IN endpoint interrupt bits + IEPINT: u16, + /// OUT endpoint interrupt bits + OEPINT: u16, }), - /// The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address. - IDMABASE1R: mmio.Mmio(packed struct(u32) { - /// Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0). - IDMABASE1: u32, + /// All endpoints interrupt mask register + DAINTMSK: mmio.Mmio(packed struct(u32) { + /// IN EP interrupt mask bits + IEPM: u16, + /// OUT EP interrupt mask bits + OEPM: u16, }), - reserved128: [32]u8, - /// The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. - FIFOR: mmio.Mmio(packed struct(u32) { - /// Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words. - FIFODATA: u32, + reserved2088: [8]u8, + /// Device VBUS discharge time register + DVBUSDIS: mmio.Mmio(packed struct(u32) { + /// Device VBUS discharge time + VBUSDT: u16, + padding: u16, }), - reserved1012: [880]u8, - /// SDMMC IP version register - VER: mmio.Mmio(packed struct(u32) { - /// IP minor revision number. - MINREV: u4, - /// IP major revision number. - MAJREV: u4, + /// Device VBUS pulsing time register + DVBUSPULSE: mmio.Mmio(packed struct(u32) { + /// Device VBUS pulsing time + DVBUSP: u12, + padding: u20, + }), + reserved2100: [4]u8, + /// Device IN endpoint FIFO empty interrupt mask register + DIEPEMPMSK: mmio.Mmio(packed struct(u32) { + /// IN EP Tx FIFO empty interrupt mask bits + INEPTXFEM: u16, + padding: u16, + }), + reserved2304: [200]u8, + /// Device IN endpoint control register + DIEPCTL: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: packed union { + raw: u2, + value: EPTYP, + }, + /// SNPM + SNPM: u1, + /// STALL + STALL: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM/SD1PID + SODDFRM_SD1PID: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved2312: [4]u8, + /// Device IN endpoint interrupt register + DIEPINT: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, padding: u24, }), - /// SDMMC IP identification register - ID: mmio.Mmio(packed struct(u32) { - /// SDMMC IP identification. - IP_ID: u32, + reserved2320: [4]u8, + /// Device IN endpoint transfer size register + DIEPTSIZ: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + reserved2328: [4]u8, + /// Device IN endpoint transmit FIFO status register + DTXFSTS: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved2816: [484]u8, + /// Device OUT endpoint control register + DOEPCTL: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: packed union { + raw: u2, + value: EPTYP, + }, + /// SNPM + SNPM: u1, + /// STALL + STALL: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved2824: [4]u8, + /// Device OUT endpoint interrupt register + DOEPINT: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved2832: [4]u8, + /// Device OUT endpoint transfer size register + DOEPTSIZ: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved3584: [748]u8, + /// Power and clock gating control register + PCGCCTL: mmio.Mmio(packed struct(u32) { + /// Stop PHY clock + STPPCLK: u1, + /// Gate HCLK + GATEHCLK: u1, + reserved4: u2, + /// PHY Suspended + PHYSUSP: u1, + padding: u27, + }), + reserved4096: [508]u8, + /// Device endpoint / host channel FIFO register + FIFO: mmio.Mmio(packed struct(u32) { + /// Data + DATA: u32, }), }; }; - pub const dma2d_v1 = struct { - pub const ABORT = enum(u1) { - /// Transfer abort requested - AbortRequest = 0x1, - _, + pub const pka_v1a = struct { + pub const LMF = enum(u1) { + /// All values documented in MODE bitfield can be used. + All = 0x0, + /// Only ECDSA verification (MODE = 0x26) is supported by the PKA. + Limited = 0x1, }; - pub const BGPFCCR_AM = enum(u2) { - /// No modification of alpha channel - NoModify = 0x0, - /// Replace with value in ALPHA[7:0] - Replace = 0x1, - /// Multiply with value in ALPHA[7:0] - Multiply = 0x2, - _, + /// Public key accelerator. + pub const PKA = extern struct { + /// PKA control register. + CR: mmio.Mmio(packed struct(u32) { + /// PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application. + EN: u1, + /// start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy. + START: u1, + reserved8: u6, + /// PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. + MODE: u6, + reserved17: u3, + /// End of operation interrupt enable. + PROCENDIE: u1, + reserved19: u1, + /// RAM error interrupt enable. + RAMERRIE: u1, + /// Address error interrupt enable. + ADDRERRIE: u1, + /// Operation error interrupt enable. + OPERRIE: u1, + padding: u10, + }), + /// PKA status register. + SR: mmio.Mmio(packed struct(u32) { + /// PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. + INITOK: u1, + /// Limited mode flag This bit is updated when EN bit in PKA_CR is set. + LMF: packed union { + raw: u1, + value: LMF, + }, + reserved16: u14, + /// PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). + BUSY: u1, + /// PKA End of Operation flag. + PROCENDF: u1, + reserved19: u1, + /// PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. + RAMERRF: u1, + /// Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. + ADDRERRF: u1, + /// Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. + OPERRF: u1, + padding: u10, + }), + /// PKA clear flag register. + CLRFR: mmio.Mmio(packed struct(u32) { + reserved17: u17, + /// Clear PKA End of Operation flag. + PROCENDFC: u1, + reserved19: u1, + /// Clear PKA RAM error flag. + RAMERRFC: u1, + /// Clear address error flag. + ADDRERRFC: u1, + /// Clear operation error flag. + OPERRFC: u1, + padding: u10, + }), + reserved1024: [1012]u8, + /// PKA internal memeory. + RAM: [1334]u32, }; + }; - pub const BGPFCCR_CCM = enum(u1) { - /// CLUT color format ARGB8888 - ARGB8888 = 0x0, - /// CLUT color format RGB888 - RGB888 = 0x1, + pub const pka_v1b = struct { + /// Public key accelerator. + pub const PKA = extern struct { + /// PKA control register. + CR: mmio.Mmio(packed struct(u32) { + /// PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application. + EN: u1, + /// start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy. + START: u1, + reserved8: u6, + /// PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. + MODE: u6, + reserved17: u3, + /// End of operation interrupt enable. + PROCENDIE: u1, + reserved19: u1, + /// RAM error interrupt enable. + RAMERRIE: u1, + /// Address error interrupt enable. + ADDRERRIE: u1, + /// Operation error interrupt enable. + OPERRIE: u1, + padding: u10, + }), + /// PKA status register. + SR: mmio.Mmio(packed struct(u32) { + /// PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. + INITOK: u1, + reserved16: u15, + /// PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). + BUSY: u1, + /// PKA End of Operation flag. + PROCENDF: u1, + reserved19: u1, + /// PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. + RAMERRF: u1, + /// Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. + ADDRERRF: u1, + /// Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. + OPERRF: u1, + padding: u10, + }), + /// PKA clear flag register. + CLRFR: mmio.Mmio(packed struct(u32) { + reserved17: u17, + /// Clear PKA End of Operation flag. + PROCENDFC: u1, + reserved19: u1, + /// Clear PKA RAM error flag. + RAMERRFC: u1, + /// Clear address error flag. + ADDRERRFC: u1, + /// Clear operation error flag. + OPERRFC: u1, + padding: u10, + }), + reserved1024: [1012]u8, + /// PKA internal memeory. + RAM: [1334]u32, }; + }; - pub const BGPFCCR_CM = enum(u4) { - /// Color mode ARGB8888 - ARGB8888 = 0x0, - /// Color mode RGB888 - RGB888 = 0x1, - /// Color mode RGB565 - RGB565 = 0x2, - /// Color mode ARGB1555 - ARGB1555 = 0x3, - /// Color mode ARGB4444 - ARGB4444 = 0x4, - /// Color mode L8 - L8 = 0x5, - /// Color mode AL44 - AL44 = 0x6, - /// Color mode AL88 - AL88 = 0x7, - /// Color mode L4 - L4 = 0x8, - /// Color mode A8 - A8 = 0x9, - /// Color mode A4 - A4 = 0xa, - _, - }; - - pub const BGPFCCR_START = enum(u1) { - /// Start the automatic loading of the CLUT - Start = 0x1, - _, - }; - - pub const CAECIF = enum(u1) { - /// Clear the CAEIF flag in the ISR register - Clear = 0x1, - _, - }; - - pub const CCEIF = enum(u1) { - /// Clear the CEIF flag in the ISR register - Clear = 0x1, - _, - }; - - pub const CCTCIF = enum(u1) { - /// Clear the CTCIF flag in the ISR register - Clear = 0x1, - _, - }; - - pub const CR_START = enum(u1) { - /// Launch the DMA2D - Start = 0x1, - _, - }; - - pub const CTCIF = enum(u1) { - /// Clear the TCIF flag in the ISR register - Clear = 0x1, - _, - }; - - pub const CTEIF = enum(u1) { - /// Clear the TEIF flag in the ISR register - Clear = 0x1, - _, - }; - - pub const CTWIF = enum(u1) { - /// Clear the TWIF flag in the ISR register - Clear = 0x1, - _, + pub const pka_v1c = struct { + /// Public key accelerator. + pub const PKA = extern struct { + /// PKA control register. + CR: mmio.Mmio(packed struct(u32) { + /// PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application. + EN: u1, + /// start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy. + START: u1, + reserved8: u6, + /// PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. + MODE: u6, + reserved17: u3, + /// End of operation interrupt enable. + PROCENDIE: u1, + reserved19: u1, + /// RAM error interrupt enable. + RAMERRIE: u1, + /// Address error interrupt enable. + ADDRERRIE: u1, + padding: u11, + }), + /// PKA status register. + SR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). + BUSY: u1, + /// PKA End of Operation flag. + PROCENDF: u1, + reserved19: u1, + /// PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. + RAMERRF: u1, + /// Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. + ADDRERRF: u1, + padding: u11, + }), + /// PKA clear flag register. + CLRFR: mmio.Mmio(packed struct(u32) { + reserved17: u17, + /// Clear PKA End of Operation flag. + PROCENDFC: u1, + reserved19: u1, + /// Clear PKA RAM error flag. + RAMERRFC: u1, + /// Clear address error flag. + ADDRERRFC: u1, + padding: u11, + }), + reserved1024: [1012]u8, + /// PKA internal memeory. + RAM: [894]u32, }; + }; - pub const FGPFCCR_AM = enum(u2) { - /// No modification of alpha channel - NoModify = 0x0, - /// Replace with value in ALPHA[7:0] - Replace = 0x1, - /// Multiply with value in ALPHA[7:0] - Multiply = 0x2, - _, + pub const pssi_v1 = struct { + pub const CKPOL = enum(u1) { + /// Falling edge active for inputs or rising edge active for outputs. + FallingEdge = 0x0, + /// Rising edge active for inputs or falling edge active for outputs. + RisingEdge = 0x1, }; - pub const FGPFCCR_CCM = enum(u1) { - /// CLUT color format ARGB8888 - ARGB8888 = 0x0, - /// CLUT color format RGB888 - RGB888 = 0x1, + pub const DEPOL = enum(u1) { + /// PSSI_DE active low (0 indicates that data is valid). + ActiveLow = 0x0, + /// PSSI_DE active high (1 indicates that data is valid). + ActiveHigh = 0x1, }; - pub const FGPFCCR_CM = enum(u4) { - /// Color mode ARGB8888 - ARGB8888 = 0x0, - /// Color mode RGB888 - RGB888 = 0x1, - /// Color mode RGB565 - RGB565 = 0x2, - /// Color mode ARGB1555 - ARGB1555 = 0x3, - /// Color mode ARGB4444 - ARGB4444 = 0x4, - /// Color mode L8 - L8 = 0x5, - /// Color mode AL44 - AL44 = 0x6, - /// Color mode AL88 - AL88 = 0x7, - /// Color mode L4 - L4 = 0x8, - /// Color mode A8 - A8 = 0x9, - /// Color mode A4 - A4 = 0xa, - _, + pub const DERDYCFG = enum(u3) { + /// PSSI_DE and PSSI_RDY both disabled. + Disabled = 0x0, + /// Only PSSI_RDY enabled. + Rdy = 0x1, + /// Only PSSI_DE enabled. + De = 0x2, + /// Both PSSI_RDY and PSSI_DE alternate functions enabled. + RdyDeAlt = 0x3, + /// Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin. + RdyDe = 0x4, + /// Only PSSI_RDY function enabled, but mapped to PSSI_DE pin. + RdyRemapped = 0x5, + /// Only PSSI_DE function enabled, but mapped to PSSI_RDY pin. + DeRemapped = 0x6, + /// Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin. + RdyDeBidi = 0x7, }; - pub const FGPFCCR_START = enum(u1) { - /// Start the automatic loading of the CLUT - Start = 0x1, + pub const EDM = enum(u2) { + /// Interface captures 8-bit data on every parallel data clock. + BitWidth8 = 0x0, + /// The interface captures 16-bit data on every parallel data clock. + BitWidth16 = 0x3, _, }; - pub const MODE = enum(u2) { - /// Memory-to-memory (FG fetch only) - MemoryToMemory = 0x0, - /// Memory-to-memory with PFC (FG fetch only with FG PFC active) - MemoryToMemoryPFC = 0x1, - /// Memory-to-memory with blending (FG and BG fetch with PFC and blending) - MemoryToMemoryPFCBlending = 0x2, - /// Register-to-memory - RegisterToMemory = 0x3, + pub const OUTEN = enum(u1) { + /// Data is input synchronously with PSSI_PDCK. + ReceiveMode = 0x0, + /// Data is output synchronously with PSSI_PDCK. + TransmitMode = 0x1, }; - pub const OPFCCR_CM = enum(u3) { - /// ARGB8888 - ARGB8888 = 0x0, - /// RGB888 - RGB888 = 0x1, - /// RGB565 - RGB565 = 0x2, - /// ARGB1555 - ARGB1555 = 0x3, - /// ARGB4444 - ARGB4444 = 0x4, - _, + pub const RDYPOL = enum(u1) { + /// PSSI_RDY active low (0 indicates that the receiver is ready to receive). + ActiveLow = 0x0, + /// PSSI_RDY active high (1 indicates that the receiver is ready to receive). + ActiveHigh = 0x1, }; - /// DMA2D controller - pub const DMA2D = extern struct { - /// control register + /// Parallel synchronous slave interface. + pub const PSSI = extern struct { + /// PSSI control register. CR: mmio.Mmio(packed struct(u32) { - /// Start - START: packed union { - raw: u1, - value: CR_START, - }, - /// Suspend - SUSP: u1, - /// Abort - ABORT: packed union { - raw: u1, - value: ABORT, - }, - reserved8: u5, - /// Transfer error interrupt enable - TEIE: u1, - /// Transfer complete interrupt enable - TCIE: u1, - /// Transfer watermark interrupt enable - TWIE: u1, - /// CLUT access error interrupt enable - CAEIE: u1, - /// CLUT transfer complete interrupt enable - CTCIE: u1, - /// Configuration Error Interrupt Enable - CEIE: u1, - reserved16: u2, - /// DMA2D mode - MODE: packed union { - raw: u2, - value: MODE, - }, - padding: u14, - }), - /// Interrupt Status Register - ISR: mmio.Mmio(packed struct(u32) { - /// Transfer error interrupt flag - TEIF: u1, - /// Transfer complete interrupt flag - TCIF: u1, - /// Transfer watermark interrupt flag - TWIF: u1, - /// CLUT access error interrupt flag - CAEIF: u1, - /// CLUT transfer complete interrupt flag - CTCIF: u1, - /// Configuration error interrupt flag - CEIF: u1, - padding: u26, - }), - /// interrupt flag clear register - IFCR: mmio.Mmio(packed struct(u32) { - /// Clear Transfer error interrupt flag - CTEIF: packed union { - raw: u1, - value: CTEIF, - }, - /// Clear transfer complete interrupt flag - CTCIF: packed union { - raw: u1, - value: CTCIF, - }, - /// Clear transfer watermark interrupt flag - CTWIF: packed union { - raw: u1, - value: CTWIF, - }, - /// Clear CLUT access error interrupt flag - CAECIF: packed union { - raw: u1, - value: CAECIF, - }, - /// Clear CLUT transfer complete interrupt flag - CCTCIF: packed union { - raw: u1, - value: CCTCIF, - }, - /// Clear configuration error interrupt flag - CCEIF: packed union { + reserved5: u5, + /// Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN. + CKPOL: packed union { raw: u1, - value: CCEIF, - }, - padding: u26, - }), - /// foreground memory address register - FGMAR: mmio.Mmio(packed struct(u32) { - /// Memory address - MA: u32, - }), - /// foreground offset register - FGOR: mmio.Mmio(packed struct(u32) { - /// Line offset - LO: u14, - padding: u18, - }), - /// background memory address register - BGMAR: mmio.Mmio(packed struct(u32) { - /// Memory address - MA: u32, - }), - /// background offset register - BGOR: mmio.Mmio(packed struct(u32) { - /// Line offset - LO: u14, - padding: u18, - }), - /// foreground PFC control register - FGPFCCR: mmio.Mmio(packed struct(u32) { - /// Color mode - CM: packed union { - raw: u4, - value: FGPFCCR_CM, + value: CKPOL, }, - /// CLUT color mode - CCM: packed union { + /// Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface. + DEPOL: packed union { raw: u1, - value: FGPFCCR_CCM, + value: DEPOL, }, - /// Start - START: packed union { + reserved8: u1, + /// Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface. + RDYPOL: packed union { raw: u1, - value: FGPFCCR_START, + value: RDYPOL, }, - reserved8: u2, - /// CLUT size - CS: u8, - /// Alpha mode - AM: packed union { + reserved10: u1, + /// Extended data mode. + EDM: packed union { raw: u2, - value: FGPFCCR_AM, - }, - reserved24: u6, - /// Alpha value - ALPHA: u8, - }), - /// foreground color register - FGCOLR: mmio.Mmio(packed struct(u32) { - /// Blue Value - BLUE: u8, - /// Green Value - GREEN: u8, - /// Red Value - RED: u8, - padding: u8, - }), - /// background PFC control register - BGPFCCR: mmio.Mmio(packed struct(u32) { - /// Color mode - CM: packed union { - raw: u4, - value: BGPFCCR_CM, + value: EDM, }, - /// CLUT Color mode - CCM: packed union { - raw: u1, - value: BGPFCCR_CCM, + reserved14: u2, + /// PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time. + ENABLE: u1, + reserved18: u3, + /// Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity. + DERDYCFG: packed union { + raw: u3, + value: DERDYCFG, }, - /// Start - START: packed union { + reserved30: u9, + /// DMA enable bit. + DMAEN: u1, + /// Data direction selection bit. + OUTEN: packed union { raw: u1, - value: BGPFCCR_START, - }, - reserved8: u2, - /// CLUT size - CS: u8, - /// Alpha mode - AM: packed union { - raw: u2, - value: BGPFCCR_AM, + value: OUTEN, }, - reserved24: u6, - /// Alpha value - ALPHA: u8, - }), - /// background color register - BGCOLR: mmio.Mmio(packed struct(u32) { - /// Blue Value - BLUE: u8, - /// Green Value - GREEN: u8, - /// Red Value - RED: u8, - padding: u8, }), - /// foreground CLUT memory address register - FGCMAR: mmio.Mmio(packed struct(u32) { - /// Memory Address - MA: u32, + /// PSSI status register. + SR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// FIFO is ready to transfer four bytes. + RTT4B: u1, + /// FIFO is ready to transfer one byte. + RTT1B: u1, + padding: u28, }), - /// background CLUT memory address register - BGCMAR: mmio.Mmio(packed struct(u32) { - /// Memory address - MA: u32, + /// PSSI raw interrupt status register. + RIS: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Data buffer overrun/underrun raw interrupt status This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR. + OVR_RIS: u1, + padding: u30, }), - /// output PFC control register - OPFCCR: mmio.Mmio(packed struct(u32) { - /// Color mode - CM: packed union { - raw: u3, - value: OPFCCR_CM, - }, - padding: u29, + /// PSSI interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Data buffer overrun/underrun interrupt enable. + OVR_IE: u1, + padding: u30, }), - /// output color register - OCOLR: mmio.Mmio(packed struct(u32) { - /// Blue Value - BLUE: u8, - /// Green Value - GREEN: u8, - /// Red Value - RED: u8, - /// Alpha Channel Value - APLHA: u8, + /// PSSI masked interrupt status register. + MIS: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Data buffer overrun/underrun masked interrupt status This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are both set to 1. + OVR_MIS: u1, + padding: u30, }), - /// output memory address register - OMAR: mmio.Mmio(packed struct(u32) { - /// Memory Address - MA: u32, + /// PSSI interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Data buffer overrun/underrun interrupt status clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS. + OVR_ISC: u1, + padding: u30, }), - /// output offset register - OOR: mmio.Mmio(packed struct(u32) { - /// Line Offset - LO: u14, - padding: u18, + reserved40: [16]u8, + /// PSSI data register. + DR: mmio.Mmio(packed struct(u32) { + /// Data byte 0. + BYTE: u8, + padding: u24, }), - /// number of line register - NLR: mmio.Mmio(packed struct(u32) { - /// Number of lines - NL: u16, - /// Pixel per lines - PL: u14, - padding: u2, + }; + }; + + pub const pwr_c0 = struct { + /// PWR address block description + pub const PWR = extern struct { + /// PWR control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection These bits select the low-power mode entered when CPU enters deepsleep mode. 1XX: Shutdown mode + LPMS: u3, + /// Flash memory powered down during Stop mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode. + FPD_STOP: u1, + reserved5: u1, + /// Flash memory powered down during Sleep mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Sleep mode. + FPD_SLP: u1, + padding: u26, }), - /// line watermark register - LWR: mmio.Mmio(packed struct(u32) { - /// Line watermark - LW: u16, + reserved8: [4]u8, + /// PWR control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup pin + EWUP: u1, + reserved10: u9, + /// Apply pull-up and pull-down configuration This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. + APC: u1, + reserved15: u4, + /// Enable internal wakeup line When set, a rising edge on the internal wakeup line triggers a wakeup event. + EIWUL: u1, padding: u16, }), - /// AHB master timer configuration register - AMTCR: mmio.Mmio(packed struct(u32) { - /// Enable - EN: u1, + /// PWR control register 4 + CR4: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP1 polarity + WP: u1, + padding: u31, + }), + /// PWR status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, reserved8: u7, - /// Dead Time - DT: u8, + /// Standby/Shutdown flag This bit is set by hardware when the device enters Standby or Shutdown mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. + SBF: u1, + reserved15: u6, + /// Wakeup flag internal This bit is set when a wakeup condition is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. + WUFI: u1, padding: u16, }), - reserved1024: [944]u8, - /// FGCLUT - FGCLUT: mmio.Mmio(packed struct(u32) { - /// BLUE - BLUE: u8, - /// GREEN - GREEN: u8, - /// RED - RED: u8, - /// APLHA - APLHA: u8, + /// PWR status register 2 + SR2: mmio.Mmio(packed struct(u32) { + reserved7: u7, + /// Flash ready flag This bit is set by hardware to indicate when the Flash memory is ready to be accessed after wakeup from power-down. To place the Flash memory in power-down, set either FPD_SLP or FPD_STP bit. Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to Flash memory. + FLASH_RDY: u1, + padding: u24, }), - reserved2048: [1020]u8, - /// BGCLUT - BGCLUT: mmio.Mmio(packed struct(u32) { - /// BLUE - BLUE: u8, - /// GREEN - GREEN: u8, - /// RED - RED: u8, - /// APLHA - APLHA: u8, + /// PWR status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear Wakeup flag + CWUF: u1, + reserved8: u7, + /// Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register. + CSBF: u1, + padding: u23, + }), + reserved32: [4]u8, + /// PWR Port pull-up control register + PUCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, + padding: u31, + }), + /// PWR Port pull-down control register + PDCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, + padding: u31, }), }; }; - pub const vrefbuf_v2a2 = struct { - pub const HIZ = enum(u1) { - /// VREF+ pin is internally connected to the voltage reference buffer output. - Connected = 0x0, - /// VREF+ pin is high impedance. - HighZ = 0x1, - }; - - pub const VRS = enum(u3) { - /// Voltage reference set to VREF_OUT1 (around 2.048 V). - Vref0 = 0x0, - /// Voltage reference set to VREF_OUT2 (around 2.5 V). - Vref1 = 0x1, - /// Voltage reference set to VREF_OUT2 (around 2.5 V). - Vref2 = 0x2, - _, + pub const pwr_f0 = struct { + pub const PDDS = enum(u1) { + /// Enter Stop mode when the CPU enters deepsleep + STOP_MODE = 0x0, + /// Enter Standby mode when the CPU enters deepsleep + STANDBY_MODE = 0x1, }; - /// Voltage reference buffer. - pub const VREFBUF = extern struct { - /// VREFBUF control and status register. - CSR: mmio.Mmio(packed struct(u32) { - /// Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. - ENVR: u1, - /// High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration. - HIZ: packed union { + /// Power control + pub const PWR = extern struct { + /// power control register + CR: mmio.Mmio(packed struct(u32) { + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: packed union { raw: u1, - value: HIZ, - }, - reserved3: u1, - /// Voltage reference buffer ready. - VRR: u1, - /// Voltage reference scale These bits select the value generated by the voltage reference buffer. VRS = 000: VREFBUF0 voltage selected. VRS = 001: VREFBUF1 voltage selected. VRS = 010: VREFBUF2 voltage selected. VRS = 011: VREFBUF3 voltage selected. Others: Reserved Note: Refer to the product datasheet for each VREFBUFx voltage setting value. The software can program this bitfield only when the VREFBUF is disabled (ENVR=0). - VRS: packed union { - raw: u3, - value: VRS, + value: PDDS, }, - padding: u25, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write protection + DBP: u1, + padding: u23, }), - /// VREFBUF calibration control register. - CCR: mmio.Mmio(packed struct(u32) { - /// Trimming code The TRIM code is a 6-bit unsigned data (minimum 000000, maximum 111111) that is set and updated according the mechanism described below. Reset: TRIM[5:0] is automatically initialized with the VRS = 0 trimming value stored in the Flash memory during the production test. VRS change: TRIM[5:0] is automatically initialized with the trimming value (corresponding to VRS setting) stored in the Flash memory during the production test. Write in TRIM[5:0]: User can modify the TRIM[5:0] with an arbitrary value. This is permanently disabling the control of the trimming value with VRS (until the device is reset). Note: If the user application performs the trimming, the trimming code must start from 000000 to 111111 in ascending order. - TRIM: u6, - padding: u26, + /// power control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + /// VREFINT reference voltage ready + VREFINTRDY: u1, + reserved8: u4, + /// Enable WKUP pin 1 + EWUP: u1, + padding: u23, }), }; }; - pub const sdadc_v1 = struct { - /// Sigma-delta analog-to-digital converter. - pub const SDADC = extern struct { - /// control register 1. - CR1: mmio.Mmio(packed struct(u32) { - /// End of calibration interrupt enable. - EOCALIE: u1, - /// Injected end of conversion interrupt enable. - JEOCIE: u1, - /// Injected data overrun interrupt enable. - JOVRIE: u1, - /// Regular end of conversion interrupt enable. - REOCIE: u1, - /// Regular data overrun interrupt enable. - ROVRIE: u1, - reserved8: u3, - /// Reference voltage selection. - REFV: u2, - /// Slow clock mode enable. - SLOWCK: u1, - /// Enter Standby mode when idle. - SBI: u1, - /// Enter power down mode when idle. - PDI: u1, - reserved14: u1, - /// Launch a injected conversion synchronously with SDADC1. - JSYNC: u1, - /// Launch regular conversion synchronously with SDADC1. - RSYNC: u1, - /// DMA channel enabled to read data for the injected channel group. - JDMAEN: u1, - /// DMA channel enabled to read data for the regular channel. - RDMAEN: u1, - reserved31: u13, - /// Initialization mode request. - INIT: u1, - }), - /// control register 2. - CR2: mmio.Mmio(packed struct(u32) { - /// SDADC enable. - ADON: u1, - /// Number of calibration sequences to be performed (number of valid configurations). - CALIBCNT: u2, - reserved4: u1, - /// Start calibration. - STARTCALIB: u1, - /// Continuous mode selection for injected conversions. - JCONT: u1, - /// Delay start of injected conversions. - JDS: u1, - reserved8: u1, - /// Trigger signal selection for launching injected conversions. - JEXTSEL: u4, - reserved13: u1, - /// Trigger enable and trigger edge selection for injected conversions. - JEXTEN: u2, - /// Start a conversion of the injected group of channels. - JSWSTART: u1, - /// Regular channel selection. - RCH: u4, - reserved22: u2, - /// Continuous mode selection for regular conversions. - RCONT: u1, - /// Software start of a conversion on the regular channel. - RSWSTART: u1, - /// Fast conversion mode selection. - FAST: u1, - padding: u7, - }), - /// interrupt and status register. - ISR: mmio.Mmio(packed struct(u32) { - /// End of calibration flag. - EOCALF: u1, - /// End of injected conversion flag. - JEOCF: u1, - /// Injected conversion overrun flag. - JOVRF: u1, - /// End of regular conversion flag. - REOCF: u1, - /// Regular conversion overrun flag. - ROVRF: u1, - reserved12: u7, - /// Calibration in progress status. - CALIBIP: u1, - /// Injected conversion in progress status. - JCIP: u1, - /// Regular conversion in progress status. - RCIP: u1, - /// Stabilization in progress status. - STABIP: u1, - reserved31: u15, - /// Initialization mode is ready. - INITRDY: u1, - }), - /// interrupt and status clear register. - CLRISR: mmio.Mmio(packed struct(u32) { - /// Clear the end of calibration flag. - CLREOCALF: u1, - reserved2: u1, - /// Clear the injected conversion overrun flag. - CLRJOVRF: u1, - reserved4: u1, - /// Clear the regular conversion overrun flag. - CLRROVRF: u1, - padding: u27, - }), - reserved20: [4]u8, - /// injected channel group selection register. - JCHGR: mmio.Mmio(packed struct(u32) { - /// Injected channel group selection. - JCHG: u9, + pub const pwr_f0x0 = struct { + pub const PDDS = enum(u1) { + /// Enter Stop mode when the CPU enters deepsleep + STOP_MODE = 0x0, + /// Enter Standby mode when the CPU enters deepsleep + STANDBY_MODE = 0x1, + }; + + /// Power control + pub const PWR = extern struct { + /// power control register + CR: mmio.Mmio(packed struct(u32) { + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: packed union { + raw: u1, + value: PDDS, + }, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + reserved8: u4, + /// Disable backup domain write protection + DBP: u1, padding: u23, }), - reserved32: [8]u8, - /// configuration 0 register. - CONFR: [3]mmio.Mmio(packed struct(u32) { - /// Twelve-bit calibration offset for configuration 0. - OFFSET: u12, - reserved20: u8, - /// Gain setting for configuration 0. - GAIN: u3, - reserved26: u3, - /// Single-ended mode for configuration 0. - SE: u2, - reserved30: u2, - /// Common mode for configuration 0. - COMMON: u2, - }), - reserved64: [20]u8, - /// channel configuration register 1. - CONFCHR1: mmio.Mmio(packed struct(u32) { - /// CONFCH0. - CONFCH: u2, - padding: u30, - }), - /// channel configuration register 2. - CONFCHR2: mmio.Mmio(packed struct(u32) { - /// Channel 8 configuration. - CONFCH: u2, - padding: u30, + /// power control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + reserved8: u6, + /// Enable WKUP pin 1 + EWUP: u1, + padding: u23, }), - reserved96: [24]u8, - /// data register for injected group. - JDATAR: mmio.Mmio(packed struct(u32) { - /// Injected group conversion data. - JDATA: u16, - reserved24: u8, - /// Injected channel most recently converted. - JDATACH: u4, - padding: u4, + }; + }; + + pub const pwr_f1 = struct { + pub const PDDS = enum(u1) { + /// Enter Stop mode when the CPU enters deepsleep + STOP_MODE = 0x0, + /// Enter Standby mode when the CPU enters deepsleep + STANDBY_MODE = 0x1, + }; + + /// Power control + pub const PWR = extern struct { + /// Power control register (PWR_CR) + CR: mmio.Mmio(packed struct(u32) { + /// Low Power Deep Sleep + LPDS: u1, + /// Power Down Deep Sleep + PDDS: packed union { + raw: u1, + value: PDDS, + }, + /// Clear Wake-up Flag + CWUF: u1, + /// Clear STANDBY Flag + CSBF: u1, + /// Power Voltage Detector Enable + PVDE: u1, + /// PVD Level Selection + PLS: u3, + /// Disable Backup Domain write protection + DBP: u1, + padding: u23, }), - /// data register for the regular channel. - RDATAR: mmio.Mmio(packed struct(u32) { - /// Regular channel conversion data. - RDATA: u16, - padding: u16, + /// Power control register (PWR_CR) + CSR: mmio.Mmio(packed struct(u32) { + /// Wake-Up Flag + WUF: u1, + /// STANDBY Flag + SBF: u1, + /// PVD Output + PVDO: u1, + reserved8: u5, + /// Enable WKUP pin + EWUP: u1, + padding: u23, }), - reserved112: [8]u8, - /// SDADC1 and SDADC2 injected data register. - JDATA12R: u32, - /// SDADC1 and SDADC2 regular data register. - RDATA12R: u32, - /// SDADC1 and SDADC3 injected data register. - JDATA13R: u32, - /// SDADC1 and SDADC3 regular data register. - RDATA13R: u32, }; }; - pub const adc_f1 = struct { - pub const DUALMOD = enum(u4) { - /// Independent mode. - Independent = 0x0, - /// Combined regular simultaneous + injected simultaneous mode - RegularInjected = 0x1, - /// Combined regular simultaneous + alternate trigger mode - RegularAlternateTrigger = 0x2, - /// Combined injected simultaneous + fast interleaved mode - InjectedFastInterleaved = 0x3, - /// Combined injected simultaneous + slow Interleaved mode - InjectedSlowInterleaved = 0x4, - /// Injected simultaneous mode only - Injected = 0x5, - /// Regular simultaneous mode only - Regular = 0x6, - /// Fast interleaved mode only - FastInterleaved = 0x7, - /// Slow interleaved mode only - SlowInterleaved = 0x8, - /// Alternate trigger mode only - AlternateTrigger = 0x9, - _, + pub const pwr_f2 = struct { + pub const PDDS = enum(u1) { + /// Enter Stop mode when the CPU enters deepsleep + STOP_MODE = 0x0, + /// Enter Standby mode when the CPU enters deepsleep + STANDBY_MODE = 0x1, }; - pub const SAMPLE_TIME = enum(u3) { - /// 1.5 cycles - Cycles1_5 = 0x0, - /// 7.5 cycles - Cycles7_5 = 0x1, - /// 13.5 cycles - Cycles13_5 = 0x2, - /// 28.5 cycles - Cycles28_5 = 0x3, - /// 41.5 cycles - Cycles41_5 = 0x4, - /// 55.5 cycles - Cycles55_5 = 0x5, - /// 71.5 cycles - Cycles71_5 = 0x6, - /// 239.5 cycles - Cycles239_5 = 0x7, + /// Power control + pub const PWR = extern struct { + /// power control register + CR: mmio.Mmio(packed struct(u32) { + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: packed union { + raw: u1, + value: PDDS, + }, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write protection + DBP: u1, + /// Flash power down in Stop mode + FPDS: u1, + padding: u22, + }), + /// power control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + /// Backup regulator ready + BRR: u1, + reserved8: u4, + /// Enable WKUP pin + EWUP: u1, + /// Backup regulator enable + BRE: u1, + padding: u22, + }), }; + }; - /// Analog-to-digital converter - pub const ADC = extern struct { - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog flag - AWD: u1, - /// Regular channel end of conversion - EOC: u1, - /// Injected channel end of conversion - JEOC: u1, - /// Injected channel start flag - JSTRT: u1, - /// Regular channel start flag - STRT: u1, - padding: u27, - }), - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Analog watchdog channel select bits - AWDCH: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Analog watchdog interrupt enable - AWDIE: u1, - /// Interrupt enable for injected channels - JEOCIE: u1, - /// Scan mode - SCAN: u1, - /// Enable the watchdog on a single channel in scan mode - AWDSGL: u1, - /// Automatic injected group conversion - JAUTO: u1, - /// Discontinuous mode on regular channels - DISCEN: u1, - /// Discontinuous mode on injected channels - JDISCEN: u1, - /// Discontinuous mode channel count - DISCNUM: u3, - /// Dual mode selection - DUALMOD: packed union { - raw: u4, - value: DUALMOD, + pub const pwr_f3 = struct { + pub const PDDS = enum(u1) { + /// Enter Stop mode when the CPU enters deepsleep + STOP_MODE = 0x0, + /// Enter Standby mode when the CPU enters deepsleep + STANDBY_MODE = 0x1, + }; + + /// Power control + pub const PWR = extern struct { + /// power control register + CR: mmio.Mmio(packed struct(u32) { + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: packed union { + raw: u1, + value: PDDS, }, - reserved22: u2, - /// Analog watchdog enable on injected channels - JAWDEN: u1, - /// Analog watchdog enable on regular channels - AWDEN: u1, - padding: u8, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write protection + DBP: u1, + /// ENable SD1 ADC + ENSD: u1, + padding: u22, }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// A/D Converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - /// A/D Calibration - CAL: u1, - /// Reset calibration - RSTCAL: u1, + /// power control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + /// Internal voltage reference ready flag + VREFINTRDYF: u1, reserved8: u4, - /// Direct memory access mode (for single ADC mode) - DMA: u1, - reserved11: u2, - /// Data alignment - ALIGN: u1, - /// External event select for injected group - JEXTSEL: u3, - /// External trigger conversion mode for injected channels - JEXTTRIG: u1, - reserved17: u1, - /// External event select for regular group - EXTSEL: u3, - /// External trigger conversion mode for regular channels - EXTTRIG: u1, - /// Start conversion of injected channels - JSWSTART: u1, - /// Start conversion of regular channels - SWSTART: u1, - /// Temperature sensor and VREFINT enable - TSVREFE: u1, - padding: u8, + /// Enable WKUP1 pin + EWUP: u1, + padding: u23, }), - /// sample time register 1 - SMPR1: mmio.Mmio(packed struct(u32) { - /// Channel x sample time selection - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, + }; + }; + + pub const pwr_f4 = struct { + pub const PDDS = enum(u1) { + /// Enter Stop mode when the CPU enters deepsleep + STOP_MODE = 0x0, + /// Enter Standby mode when the CPU enters deepsleep + STANDBY_MODE = 0x1, + }; + + pub const VOS = enum(u2) { + /// Scale 3 mode (STM32F4[23] ONLY) + SCALE3 = 0x1, + /// Scale 2 mode + SCALE2 = 0x2, + /// Scale 1 mode (reset value) + SCALE1 = 0x3, + _, + }; + + /// Power control + pub const PWR = extern struct { + /// power control register + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: packed union { + raw: u1, + value: PDDS, }, - padding: u29, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write protection + DBP: u1, + /// Flash power down in Stop mode + FPDS: u1, + /// Low-Power Regulator Low Voltage in deepsleep + LPLVDS: u1, + /// Main regulator low voltage in deepsleep mode + MRLVDS: u1, + reserved13: u1, + /// ADCDC1 + ADCDC1: u1, + /// Regulator voltage scaling output selection + VOS: packed union { + raw: u2, + value: VOS, + }, + /// Over-drive enable (STM32F4[23] ONLY) + ODEN: u1, + /// Over-drive switching enabled (STM32F4[23] ONLY) + ODSWEN: u1, + /// Under-drive enable in stop mode (STM32F4[23] ONLY) + UDEN: u2, + /// Flash Memory Stop while System Run + FMSSR: u1, + /// Flash Interface Stop while System Run + FISSR: u1, + padding: u10, }), - /// sample time register 2 - SMPR2: mmio.Mmio(packed struct(u32) { - /// Channel 0 sampling time selection - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, + /// power control/status register + CSR1: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + /// Backup regulator ready + BRR: u1, + reserved7: u3, + /// Enable WKUP2 pin + EWUP2: u1, + /// Enable WKUP pin + EWUP: u1, + /// Backup regulator enable + BRE: u1, + reserved14: u4, + /// Regulator voltage scaling output selection ready bit (STM32F4[23] ONLY) + VOSRDY: u1, + reserved16: u1, + /// Over-drive mode ready (STM32F4[23] ONLY) + ODRDY: u1, + /// Over-drive mode switching ready (STM32F4[23] ONLY) + ODSWRDY: u1, + /// Under-drive ready flag + UDRDY: u2, + padding: u12, + }), + }; + }; + + pub const pwr_f7 = struct { + pub const PDDS = enum(u1) { + /// Enter Stop mode when the CPU enters deepsleep + STOP_MODE = 0x0, + /// Enter Standby mode when the CPU enters deepsleep + STANDBY_MODE = 0x1, + }; + + pub const VOS = enum(u2) { + /// Scale 3 mode + SCALE3 = 0x1, + /// Scale 2 mode + SCALE2 = 0x2, + /// Scale 1 mode (reset value) + SCALE1 = 0x3, + _, + }; + + /// Power control + pub const PWR = extern struct { + /// power control register + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: packed union { + raw: u1, + value: PDDS, }, - padding: u29, + reserved3: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write protection + DBP: u1, + /// Flash power down in Stop mode + FPDS: u1, + /// Low-power regulator in deepsleep under-drive mode + LPUDS: u1, + /// Main regulator in deepsleep under-drive mode + MRUDS: u1, + reserved13: u1, + /// ADCDC1 + ADCDC1: u1, + /// Regulator voltage scaling output selection + VOS: packed union { + raw: u2, + value: VOS, + }, + /// Over-drive enable + ODEN: u1, + /// Over-drive switching enabled + ODSWEN: u1, + /// Under-drive enable in stop mode + UDEN: u2, + padding: u12, }), - /// injected channel data offset register x - JOFR: [4]mmio.Mmio(packed struct(u32) { - /// Data offset for injected channel x - JOFFSET: u12, - padding: u20, + /// power control/status register + CSR1: mmio.Mmio(packed struct(u32) { + /// Wakeup internal flag + WUIF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + /// Backup regulator ready + BRR: u1, + reserved8: u4, + /// Enable internal wakeup + EIWUP: u1, + /// Backup regulator enable + BRE: u1, + reserved14: u4, + /// Regulator voltage scaling output selection ready bit + VOSRDY: u1, + reserved16: u1, + /// Over-drive mode ready + ODRDY: u1, + /// Over-drive mode switching ready + ODSWRDY: u1, + /// Under-drive ready flag + UDRDY: u2, + padding: u12, }), - /// watchdog higher threshold register - HTR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog higher threshold - HT: u12, - padding: u20, + /// power control register + CR2: mmio.Mmio(packed struct(u32) { + /// Clear Wakeup Pin flag for PA0 + CWUPF: u1, + reserved8: u7, + /// Wakeup pin polarity bit for PA0 + WUPP: u1, + padding: u23, }), - /// watchdog lower threshold register - LTR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog lower threshold - LT: u12, - padding: u20, + /// power control/status register + CSR2: mmio.Mmio(packed struct(u32) { + /// Wakeup Pin flag for PA0 + WUPF: u1, + reserved8: u7, + /// Enable Wakeup pin for PA0 + EWUP: u1, + padding: u23, }), - /// regular sequence register 1 - SQR1: mmio.Mmio(packed struct(u32) { - /// 13th to 16th conversion in regular sequence - SQ: u5, - reserved20: u15, - /// Regular channel sequence length - L: u4, - padding: u8, + }; + }; + + pub const pwr_g0 = struct { + pub const VOS = enum(u2) { + Range1 = 0x1, + Range2 = 0x2, + _, + }; + + /// Power control + pub const PWR = extern struct { + /// Power control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection + LPMS: u3, + /// Flash memory powered down during Stop mode + FPD_STOP: u1, + /// Flash memory powered down during Low-power run mode + FPD_LPRUN: u1, + /// Flash memory powered down during Low-power sleep mode + FPD_LPSLP: u1, + reserved8: u2, + /// Disable backup domain write protection + DBP: u1, + /// Voltage scaling range selection + VOS: packed union { + raw: u2, + value: VOS, + }, + reserved14: u3, + /// Low-power run + LPR: u1, + padding: u17, }), - /// regular sequence register 2 - SQR2: mmio.Mmio(packed struct(u32) { - /// 7th to 12th conversion in regular sequence - SQ: u5, - padding: u27, + /// Power control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Power voltage detector enable + PVDE: u1, + /// Power voltage detector falling threshold selection + PVDFT: u3, + /// Power voltage detector rising threshold selection + PVDRT: u3, + padding: u25, }), - /// regular sequence register 3 - SQR3: mmio.Mmio(packed struct(u32) { - /// 1st to 6th conversion in regular sequence - SQ: u5, - padding: u27, + /// Power control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup pin + EWUP: u1, + reserved8: u7, + /// SRAM retention in Standby mode + RRS: u1, + /// Enable the periodical sampling mode for PDR detection + ULPEN: u1, + /// Apply pull-up and pull-down configuration + APC: u1, + reserved15: u4, + /// Enable internal wakeup line + EIWUL: u1, + padding: u16, }), - /// injected sequence register - JSQR: mmio.Mmio(packed struct(u32) { - /// 1st conversion in injected sequence - JSQ: u5, - reserved20: u15, - /// Injected sequence length - JL: u2, - padding: u10, + /// Power control register 4 + CR4: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP1 polarity + WP: u1, + reserved8: u7, + /// VBAT battery charging enable + VBE: u1, + /// VBAT battery charging resistor selection + VBRS: u1, + padding: u22, }), - /// injected data register x - JDR: [4]mmio.Mmio(packed struct(u32) { - /// Injected data - JDATA: u16, + /// Power status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, + reserved8: u7, + /// Standby flag + SBF: u1, + reserved15: u6, + /// Wakeup flag internal + WUFI: u1, padding: u16, }), - /// regular data register - DR: mmio.Mmio(packed struct(u32) { - /// Regular data - DATA: u16, - /// ADC2 data - ADC2DATA: u16, + /// Power status register 2 + SR2: mmio.Mmio(packed struct(u32) { + reserved7: u7, + /// Flash ready flag + FLASH_RDY: u1, + /// Low-power regulator started + REGLPS: u1, + /// Low-power regulator flag + REGLPF: u1, + /// Voltage scaling flag + VOSF: u1, + /// Power voltage detector output + PVDO: u1, + padding: u20, + }), + /// Power status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear Wakeup flag + CWUF: u1, + reserved8: u7, + /// Clear standby flag + CSBF: u1, + padding: u23, + }), + reserved32: [4]u8, + /// Power Port pull-up control register + PUCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, + padding: u31, + }), + /// Power Port pull-down control register + PDCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, + padding: u31, }), }; }; - pub const rcc_l5 = struct { - pub const ADCSEL = enum(u2) { - /// No clock selected - DISABLE = 0x0, - /// PLLADC1CLK clock selected - PLLSAI1_R = 0x1, - /// SYSCLK clock selected - SYS = 0x3, + pub const pwr_g4 = struct { + pub const VOS = enum(u2) { + Range1 = 0x1, + Range2 = 0x2, _, }; - pub const CLK48SEL = enum(u2) { - /// HSI48 clock selected - HSI48 = 0x0, - /// PLLSAI1_Q aka PLL48M1CLK clock selected - PLLSAI1_Q = 0x1, - /// PLL_Q aka PLL48M2CLK clock selected - PLL1_Q = 0x2, - /// MSI clock selected - MSI = 0x3, + /// Power control + pub const PWR = extern struct { + /// Power control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection + LPMS: u3, + reserved8: u5, + /// Disable backup domain write protection + DBP: u1, + /// Voltage scaling range selection + VOS: packed union { + raw: u2, + value: VOS, + }, + reserved14: u3, + /// Low-power run + LPR: u1, + padding: u17, + }), + /// Power control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Power voltage detector enable + PVDE: u1, + /// Power voltage detector level selection + PLS: u3, + /// Peripheral voltage monitoring 1 enable: VDDA vs. COMP min voltage + PVMEN1: u1, + /// Peripheral voltage monitoring 2 enable: VDDA vs. Fast DAC min voltage + PVMEN2: u1, + /// Peripheral voltage monitoring 3 enable: VDDA vs. ADC min voltage 1.62V + PVMEN3: u1, + /// Peripheral voltage monitoring 4 enable: VDDA vs. OPAMP/DAC min voltage + PVMEN4: u1, + padding: u24, + }), + /// Power control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup pin WKUP1 + EWUP1: u1, + /// Enable Wakeup pin WKUP2 + EWUP2: u1, + /// Enable Wakeup pin WKUP3 + EWUP3: u1, + /// Enable Wakeup pin WKUP4 + EWUP4: u1, + /// Enable Wakeup pin WKUP5 + EWUP5: u1, + reserved8: u3, + /// SRAM2 retention in Standby mode + RRS: u1, + reserved10: u1, + /// Apply pull-up and pull-down configuration + APC: u1, + reserved13: u2, + /// STDBY + UCPD1_STDBY: u1, + /// DBDIS + UCPD1_DBDIS: u1, + /// Enable external WakeUp line + EIWUL: u1, + padding: u16, + }), + /// Power control register 4 + CR4: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP1 polarity + WP1: u1, + /// Wakeup pin WKUP2 polarity + WP2: u1, + /// Wakeup pin WKUP3 polarity + WP3: u1, + /// Wakeup pin WKUP4 polarity + WP4: u1, + /// Wakeup pin WKUP5 polarity + WP5: u1, + reserved8: u3, + /// VBAT battery charging enable + VBE: u1, + /// VBAT battery charging resistor selection + VBRS: u1, + padding: u22, + }), + /// Power status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Wakeup flag 1 + WUF1: u1, + /// Wakeup flag 2 + WUF2: u1, + /// Wakeup flag 3 + WUF3: u1, + /// Wakeup flag 4 + WUF4: u1, + /// Wakeup flag 5 + WUF5: u1, + reserved8: u3, + /// Standby flag + SBF: u1, + reserved15: u6, + /// Wakeup flag internal + WUFI: u1, + padding: u16, + }), + /// Power status register 2 + SR2: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// Low-power regulator started + REGLPS: u1, + /// Low-power regulator flag + REGLPF: u1, + /// Voltage scaling flag + VOSF: u1, + /// Power voltage detector output + PVDO: u1, + /// Peripheral voltage monitoring output: VDDUSB vs. 1.2 V + PVMO1: u1, + /// Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V + PVMO2: u1, + /// Peripheral voltage monitoring output: VDDA vs. 1.62 V + PVMO3: u1, + /// Peripheral voltage monitoring output: VDDA vs. 2.2 V + PVMO4: u1, + padding: u16, + }), + /// Power status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear wakeup flag 1 + CWUF1: u1, + /// Clear wakeup flag 2 + CWUF2: u1, + /// Clear wakeup flag 3 + CWUF3: u1, + /// Clear wakeup flag 4 + CWUF4: u1, + /// Clear wakeup flag 5 + CWUF5: u1, + reserved8: u3, + /// Clear standby flag + CSBF: u1, + padding: u23, + }), + reserved32: [4]u8, + /// Power Port pull-up control register + PUCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, + padding: u31, + }), + /// Power Port pull-down control register + PDCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, + padding: u31, + }), + reserved128: [88]u8, + /// Power control register 5 + CR5: mmio.Mmio(packed struct(u32) { + /// Main regular range 1 mode + R1MODE: u1, + padding: u31, + }), }; + }; - pub const FDCANSEL = enum(u2) { - /// HSE clock selected - HSE = 0x0, - /// PLL "Q" clock selected - PLL1_Q = 0x1, - /// PLLSAI "P" clock selected - PLLSAI1_P = 0x2, - _, + pub const pwr_h5 = struct { + pub const ALS = enum(u2) { + /// AVD level0 (VAVD0 ~ 1.7 V) + Level0 = 0x0, + /// AVD level1 (VAVD1 ~ 2.1 V) + Level1 = 0x1, + /// AVD level2 (VAVD2 ~ 2.5 V) + Level2 = 0x2, + /// AVD level3 (VAVD3 ~ 2.8 V) + Level3 = 0x3, }; - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, - _, + pub const LPMS = enum(u1) { + /// Keeps Stop mode when entering DeepSleep. + Stop = 0x0, + /// Allows Standby mode when entering DeepSleep. + Standby = 0x1, }; - pub const LSCOSEL = enum(u1) { - /// LSI clock selected" - LSI = 0x0, - /// LSE clock selected - LSE = 0x1, + pub const PLS = enum(u3) { + /// PVD level0 (VPVD0 ~ 1.95 V) + Level0 = 0x0, + /// PVD level1 (VPVD1 ~ 2.10 V) + Level1 = 0x1, + /// PVD level2 (VPVD2 ~ 2.25 V) + Level2 = 0x2, + /// PVD level3 (VPVD3 ~ 2.40 V) + Level3 = 0x3, + /// PVD level4 (VPVD4 ~ 2.55 V) + Level4 = 0x4, + /// PVD level5 (VPVD5 ~ 2.70 V) + Level5 = 0x5, + /// PVD level6 (VPVD6 ~ 2.85 V) + Level6 = 0x6, + /// PVD_IN pin + PVDInPin = 0x7, }; - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, + pub const PowerModeInStopMode = enum(u1) { + /// Remains in normal mode when the system enters Stop mode (quick restart time). + Normal = 0x0, + /// Enters low-power mode when the system enters Stop mode (low-power consumption). + LowPower = 0x1, }; - pub const MCOPRE = enum(u3) { - /// MCO divided by 1 - Div1 = 0x0, - /// MCO divided by 2 - Div2 = 0x1, - /// MCO divided by 4 - Div4 = 0x2, - /// MCO divided by 8 - Div8 = 0x3, - /// MCO divided by 16 - Div16 = 0x4, - _, + pub const Retention = enum(u1) { + /// Content is lost. + Lost = 0x0, + /// Content is preserved. + Preserved = 0x1, }; - pub const MCOSEL = enum(u4) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// SYSCLK system clock selected - SYS = 0x1, - /// MSI clock selected - MSI = 0x2, - /// HSI clock selected - HSI = 0x3, - /// HSE clock selected - HSE = 0x4, - /// Main PLL clock selected - PLL = 0x5, - /// LSI clock selected - LSI = 0x6, - /// LSE clock selected - LSE = 0x7, - /// Internal HSI48 clock selected - HSI48 = 0x8, + pub const SVOS = enum(u2) { + /// SVOS5 scale 5 + Scale5 = 0x1, + /// SVOS4 scale 4 + Scale4 = 0x2, + /// SVOS3 scale 3 (default) + Scale3 = 0x3, _, }; - pub const MSIRANGE = enum(u4) { - /// range 0 around 100 kHz - Range100K = 0x0, - /// range 1 around 200 kHz - Range200K = 0x1, - /// range 2 around 400 kHz - Range400K = 0x2, - /// range 3 around 800 kHz - Range800K = 0x3, - /// range 4 around 1 MHz - Range1M = 0x4, - /// range 5 around 2 MHz - Range2M = 0x5, - /// range 6 around 4 MHz - Range4M = 0x6, - /// range 7 around 8 MHz - Range8M = 0x7, - /// range 8 around 16 MHz - Range16M = 0x8, - /// range 9 around 24 MHz - Range24M = 0x9, - /// range 10 around 32 MHz - Range32M = 0xa, - /// range 11 around 48 MHz - Range48M = 0xb, - _, + pub const ShutOff = enum(u1) { + /// Content is kept. + Kept = 0x0, + /// Content is lost. + Lost = 0x1, }; - pub const MSIRGSEL = enum(u1) { - /// MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register - CSR = 0x0, - /// MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register - CR = 0x1, + pub const VBRS = enum(u1) { + /// Charge VBAT through a 5 kΩ resistor. + R5kOhm = 0x0, + /// Charge VBAT through a 1.5 kΩ resistor. + R1_5kOhm = 0x1, }; - pub const PLLM = enum(u4) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, + pub const VOS = enum(u2) { + Scale3 = 0x0, + Scale2 = 0x1, + Scale1 = 0x2, + Scale0 = 0x3, }; - pub const PLLN = enum(u7) { - Mul8 = 0x8, - Mul9 = 0x9, - Mul10 = 0xa, - Mul11 = 0xb, - Mul12 = 0xc, - Mul13 = 0xd, - Mul14 = 0xe, - Mul15 = 0xf, - Mul16 = 0x10, - Mul17 = 0x11, - Mul18 = 0x12, - Mul19 = 0x13, - Mul20 = 0x14, - Mul21 = 0x15, - Mul22 = 0x16, - Mul23 = 0x17, - Mul24 = 0x18, - Mul25 = 0x19, - Mul26 = 0x1a, - Mul27 = 0x1b, - Mul28 = 0x1c, - Mul29 = 0x1d, - Mul30 = 0x1e, - Mul31 = 0x1f, - Mul32 = 0x20, - Mul33 = 0x21, - Mul34 = 0x22, - Mul35 = 0x23, - Mul36 = 0x24, - Mul37 = 0x25, - Mul38 = 0x26, - Mul39 = 0x27, - Mul40 = 0x28, - Mul41 = 0x29, - Mul42 = 0x2a, - Mul43 = 0x2b, - Mul44 = 0x2c, - Mul45 = 0x2d, - Mul46 = 0x2e, - Mul47 = 0x2f, - Mul48 = 0x30, - Mul49 = 0x31, - Mul50 = 0x32, - Mul51 = 0x33, - Mul52 = 0x34, - Mul53 = 0x35, - Mul54 = 0x36, - Mul55 = 0x37, - Mul56 = 0x38, - Mul57 = 0x39, - Mul58 = 0x3a, - Mul59 = 0x3b, - Mul60 = 0x3c, - Mul61 = 0x3d, - Mul62 = 0x3e, - Mul63 = 0x3f, - Mul64 = 0x40, - Mul65 = 0x41, - Mul66 = 0x42, - Mul67 = 0x43, - Mul68 = 0x44, - Mul69 = 0x45, - Mul70 = 0x46, - Mul71 = 0x47, - Mul72 = 0x48, - Mul73 = 0x49, - Mul74 = 0x4a, - Mul75 = 0x4b, - Mul76 = 0x4c, - Mul77 = 0x4d, - Mul78 = 0x4e, - Mul79 = 0x4f, - Mul80 = 0x50, - Mul81 = 0x51, - Mul82 = 0x52, - Mul83 = 0x53, - Mul84 = 0x54, - Mul85 = 0x55, - Mul86 = 0x56, - Mul87 = 0x57, - Mul88 = 0x58, - Mul89 = 0x59, - Mul90 = 0x5a, - Mul91 = 0x5b, - Mul92 = 0x5c, - Mul93 = 0x5d, - Mul94 = 0x5e, - Mul95 = 0x5f, - Mul96 = 0x60, - Mul97 = 0x61, - Mul98 = 0x62, - Mul99 = 0x63, - Mul100 = 0x64, - Mul101 = 0x65, - Mul102 = 0x66, - Mul103 = 0x67, - Mul104 = 0x68, - Mul105 = 0x69, - Mul106 = 0x6a, - Mul107 = 0x6b, - Mul108 = 0x6c, - Mul109 = 0x6d, - Mul110 = 0x6e, - Mul111 = 0x6f, - Mul112 = 0x70, - Mul113 = 0x71, - Mul114 = 0x72, - Mul115 = 0x73, - Mul116 = 0x74, - Mul117 = 0x75, - Mul118 = 0x76, - Mul119 = 0x77, - Mul120 = 0x78, - Mul121 = 0x79, - Mul122 = 0x7a, - Mul123 = 0x7b, - Mul124 = 0x7c, - Mul125 = 0x7d, - Mul126 = 0x7e, - Mul127 = 0x7f, - _, + pub const WUPP = enum(u1) { + /// detection on high level (rising edge) + High = 0x0, + /// detection on low level (falling edge) + Low = 0x1, }; - pub const PLLP = enum(u5) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - Div16 = 0x10, - Div17 = 0x11, - Div18 = 0x12, - Div19 = 0x13, - Div20 = 0x14, - Div21 = 0x15, - Div22 = 0x16, - Div23 = 0x17, - Div24 = 0x18, - Div25 = 0x19, - Div26 = 0x1a, - Div27 = 0x1b, - Div28 = 0x1c, - Div29 = 0x1d, - Div30 = 0x1e, - Div31 = 0x1f, + pub const WUPPUPD = enum(u2) { + NoPullUp = 0x0, + PullUp = 0x1, + PullDown = 0x2, _, }; - pub const PLLPBIT = enum(u1) { - Div7 = 0x0, - Div17 = 0x1, - }; - - pub const PLLQ = enum(u2) { - Div2 = 0x0, - Div4 = 0x1, - Div6 = 0x2, - Div8 = 0x3, - }; - - pub const PLLR = enum(u2) { - Div2 = 0x0, - Div4 = 0x1, - Div6 = 0x2, - Div8 = 0x3, - }; - - pub const PLLSRC = enum(u2) { - /// No clock sent to PLL - DISABLE = 0x0, - /// MSI selected as PLL input clock - MSI = 0x1, - /// HSI selected as PLL input clock - HSI = 0x2, - /// HSE selected as PLL input clock - HSE = 0x3, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, - }; - - pub const STOPWUCK = enum(u1) { - /// MSI oscillator selected as wake-up from Stop clock and CSS backup clock - MSI = 0x0, - /// HSI oscillator selected as wake-up from stop clock and CSS backup clock - HSI = 0x1, - }; - - pub const SW = enum(u2) { - /// MSI selected as system clock - MSI = 0x0, - /// HSI selected as system clock - HSI = 0x1, - /// HSE selected as system clock - HSE = 0x2, - /// PLL selected as system clock - PLL1_R = 0x3, - }; - - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// MSI clock enable - MSION: u1, - /// MSI clock ready flag - MSIRDY: u1, - /// MSI clock PLL enable - MSIPLLEN: u1, - /// MSI clock range selection - MSIRGSEL: packed union { + /// Power control. + pub const PWR = extern struct { + /// PWR power mode control register. + PMCR: mmio.Mmio(packed struct(u32) { + /// low-power mode selection This bit defines the Deepsleep mode. + LPMS: packed union { raw: u1, - value: MSIRGSEL, - }, - /// MSI clock ranges - MSIRANGE: packed union { - raw: u4, - value: MSIRANGE, - }, - /// HSI clock enable - HSION: u1, - /// HSI always enable for peripheral kernels - HSIKERON: u1, - /// HSI clock ready flag - HSIRDY: u1, - /// HSI automatic start from Stop - HSIASFS: u1, - reserved16: u4, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE crystal oscillator bypass - HSEBYP: u1, - /// Clock security system enable - CSSON: u1, - reserved24: u4, - /// Main PLL enable - PLLON: u1, - /// Main PLL clock ready flag - PLLRDY: u1, - /// SAI1 PLL enable - PLLSAI1ON: u1, - /// SAI1 PLL clock ready flag - PLLSAI1RDY: u1, - /// SAI2 PLL enable - PLLSAI2ON: u1, - /// SAI2 PLL clock ready flag - PLLSAI2RDY: u1, - reserved31: u1, - /// PRIV - PRIV: u1, - }), - /// Internal clock sources calibration register - ICSCR: mmio.Mmio(packed struct(u32) { - /// MSI clock calibration - MSICAL: u8, - /// MSI clock trimming - MSITRIM: u8, - /// HSI clock calibration - HSICAL: u8, - /// HSI clock trimming - HSITRIM: u7, - padding: u1, - }), - /// Clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u2, - value: SW, + value: LPMS, }, - /// System clock switch status - SWS: packed union { + reserved2: u1, + /// system Stop mode voltage scaling selection These bits control the V_CORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. + SVOS: packed union { raw: u2, - value: SW, + value: SVOS, }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, + reserved7: u3, + /// clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware. + CSSF: u1, + reserved9: u1, + /// Flash memory low-power mode in Stop mode This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode. Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode. + FLPS: packed union { + raw: u1, + value: PowerModeInStopMode, }, - /// APB low-speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, + reserved12: u2, + /// analog switch V_BOOST control This bit enables the booster to guarantee the analog switch AC performance when the V_DD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V_DD supply voltage can be monitored through the PVD and the PLS bits. + BOOSTE: u1, + /// analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected V_DDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored. (ALS bits). + AVD_READY: u1, + reserved16: u2, + /// ETHERNET RAM shut-off in Stop mode. + ETHERNETSO: packed union { + raw: u1, + value: ShutOff, }, - /// APB high-speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, + reserved23: u6, + /// AHB SRAM3 shut-off in Stop mode. + SRAM3SO: packed union { + raw: u1, + value: ShutOff, }, - reserved15: u1, - /// Wakeup from Stop and CSS backup clock selection - STOPWUCK: packed union { + /// AHB SRAM2 16-Kbyte shut-off in Stop mode. + SRAM2_16SO: packed union { raw: u1, - value: STOPWUCK, + value: ShutOff, }, - reserved24: u8, - /// Microcontroller clock output selection - MCOSEL: packed union { - raw: u4, - value: MCOSEL, + /// AHB SRAM2 48-Kbyte shut-off in Stop mode. + SRAM2_48SO: packed union { + raw: u1, + value: ShutOff, }, - /// Microcontroller clock output prescaler - MCOPRE: packed union { - raw: u3, - value: MCOPRE, + /// AHB SRAM1 shut-off in Stop mode. + SRAM1SO: packed union { + raw: u1, + value: ShutOff, }, - padding: u1, + padding: u5, }), - /// PLL configuration register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// PLL clock source - PLLSRC: packed union { + /// PWR status register. + PMSR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Stop flag This bit is set by hardware and cleared only by any reset or by setting the CSSF bit. + STOPF: u1, + /// System standby flag This bit is set by hardware and cleared only by a POR or by setting the CSSF bit. + SBF: u1, + padding: u25, + }), + reserved16: [8]u8, + /// PWR voltage scaling control register. + VOSCR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// voltage scaling selection according to performance These bits control the V_CORE voltage level and allow to obtain the best trade-off between power consumption and performance: - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance. - When increasing the performance, the voltage scaling must be changed before increasing the system frequency. - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling. + VOS: packed union { raw: u2, - value: PLLSRC, + value: VOS, }, - reserved4: u2, - /// Division factor for the PLL input clock - PLLM: packed union { - raw: u4, - value: PLLM, + padding: u26, + }), + /// PWR voltage scaling status register. + VOSSR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Ready bit for V_CORE voltage scaling output selection. + VOSRDY: u1, + reserved13: u9, + /// Voltage level ready for currently used VOS. + ACTVOSRDY: u1, + /// voltage output scaling currently applied to V_CORE This field provides the last VOS value. + ACTVOS: packed union { + raw: u2, + value: VOS, }, - /// PLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, + padding: u16, + }), + reserved32: [8]u8, + /// PWR Backup domain control register. + BDCR: mmio.Mmio(packed struct(u32) { + /// Backup RAM retention in Standby and V_BAT modes When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and V_BAT modes) is enabled. If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in. Run and Stop modes. However its content is lost in Standby and V_BAT modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and V_BAT modes. + BREN: packed union { + raw: u1, + value: Retention, }, - reserved16: u1, - /// PLL PLLSAI3CLK output enable - PLLPEN: u1, - /// PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) - PLLPBIT: packed union { + /// Backup domain voltage and temperature monitoring enable. + MONEN: u1, + reserved8: u6, + /// V_BAT charging enable Note: Reset only by POR,. + VBE: u1, + /// V_BAT charging resistor selection. + VBRS: packed union { raw: u1, - value: PLLPBIT, + value: VBRS, }, - reserved20: u2, - /// PLL PLLUSB1CLK output enable - PLLQEN: u1, - /// PLL division factor for PLLUSB1CLK(48 MHz clock) - PLLQ: packed union { - raw: u2, - value: PLLQ, + padding: u22, + }), + /// PWR Backup domain control register. + DBPCR: mmio.Mmio(packed struct(u32) { + /// Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write. access. This bit must be set to enable write access to these registers. + DBP: u1, + padding: u31, + }), + /// PWR Backup domain status register. + BDSR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready. + BRRDY: u1, + reserved20: u3, + /// V_BAT level monitoring versus low threshold. + VBATL: u1, + /// V_BAT level monitoring versus high threshold. + VBATH: u1, + /// temperature level monitoring versus low threshold. + TEMPL: u1, + /// temperature level monitoring versus high threshold. + TEMPH: u1, + padding: u8, + }), + /// PWR USB Type-C power delivery register. + UCPDR: mmio.Mmio(packed struct(u32) { + /// USB Type-C and power delivery dead battery disable After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all case, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable). + UCPD_DBDIS: u1, + /// USB Type-c and Power delivery Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD, and it must be written to 0 after exiting the standby mode and before writing any UCPD register. + UCPD_STBY: u1, + padding: u30, + }), + /// PWR supply configuration control register. + SCCR: mmio.Mmio(packed struct(u32) { + /// power management unit bypass. + BYPASS: u1, + reserved8: u7, + /// LDO enable The value is set by hardware when the package uses the LDO regulator. + LDOEN: u1, + /// SMPS enable The value is set by hardware when the package uses the SMPS regulator. + SMPSEN: u1, + padding: u22, + }), + /// PWR voltage monitor control register. + VMCR: mmio.Mmio(packed struct(u32) { + /// PVD enable. + PVDE: u1, + /// programmable voltage detector (PVD) level selection These bits select the voltage threshold detected by the PVD. + PLS: packed union { + raw: u3, + value: PLS, }, - reserved24: u1, - /// PLL PLLCLK output enable - PLLREN: u1, - /// PLL division factor for PLLCLK (system clock) - PLLR: packed union { + reserved8: u4, + /// peripheral voltage monitor on V_DDA enable. + AVDEN: u1, + /// analog voltage detector (AVD) level selection These bits select the voltage threshold detected by the AVD. + ALS: packed union { raw: u2, - value: PLLR, - }, - /// PLL division factor for PLLSAI2CLK - PLLP: packed union { - raw: u5, - value: PLLP, + value: ALS, }, + padding: u21, }), - /// PLLSAI1 configuration register - PLLSAI1CFGR: mmio.Mmio(packed struct(u32) { - /// PLL clock source - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - reserved4: u2, - /// Division factor for the PLL input clock - PLLM: packed union { - raw: u4, - value: PLLM, - }, - /// PLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, - }, - reserved16: u1, - /// PLL PLLSAI3CLK output enable - PLLPEN: u1, - /// PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) - PLLPBIT: packed union { + /// PWR USB supply control register. + USBSCR: mmio.Mmio(packed struct(u32) { + reserved24: u24, + /// V_DDUSB voltage level detector enable. + USB33DEN: u1, + /// independent USB supply valid This bit is used to validate the V_DDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USBFS peripheral. If V_DDUSB is not always present in the application, the V_DDUSB voltage monitor can be used to determine whether this supply is ready or not. + USB33SV: u1, + padding: u6, + }), + /// PWR voltage monitor status register. + VMSR: mmio.Mmio(packed struct(u32) { + reserved19: u19, + /// analog voltage detector output on V_DDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set. + AVDO: u1, + /// voltage detector output on V_DDIO2 This bit is set and cleared by hardware. + VDDIO2RDY: u1, + reserved22: u1, + /// programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. + PVDO: u1, + reserved24: u1, + /// V_DDUSB ready. + USB33RDY: u1, + padding: u7, + }), + /// PWR wakeup status clear register. + WUSCR: mmio.Mmio(packed struct(u32) { + /// clear wakeup pin flag for WUFx These bits are always read as 0. + CWUF: u1, + padding: u31, + }), + /// PWR wakeup status register. + WUSR: mmio.Mmio(packed struct(u32) { + /// wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + WUF: u1, + padding: u31, + }), + /// PWR wakeup configuration register. + WUCR: mmio.Mmio(packed struct(u32) { + /// enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + WUPEN: u1, + reserved8: u7, + /// wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + WUPP: packed union { raw: u1, - value: PLLPBIT, - }, - reserved20: u2, - /// PLL PLLUSB1CLK output enable - PLLQEN: u1, - /// PLL division factor for PLLUSB1CLK(48 MHz clock) - PLLQ: packed union { - raw: u2, - value: PLLQ, + value: WUPP, }, - reserved24: u1, - /// PLL PLLCLK output enable - PLLREN: u1, - /// PLL division factor for PLLCLK (system clock) - PLLR: packed union { + reserved16: u7, + /// wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + WUPPUPD: packed union { raw: u2, - value: PLLR, - }, - /// PLL division factor for PLLSAI2CLK - PLLP: packed union { - raw: u5, - value: PLLP, + value: WUPPUPD, }, + padding: u14, }), - /// PLLSAI2 configuration register - PLLSAI2CFGR: mmio.Mmio(packed struct(u32) { - /// PLL clock source - PLLSRC: packed union { + reserved80: [4]u8, + /// PWR I/O retention register. + IORETR: mmio.Mmio(packed struct(u32) { + /// IO retention enable: When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register. + IORETEN: u1, + reserved16: u15, + /// IO retention enable for JTAG IOs when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. + JTAGIORETEN: u1, + padding: u15, + }), + reserved256: [172]u8, + /// PWR security configuration register. + SECCFGR: mmio.Mmio(packed struct(u32) { + /// WUPx secure protection. + WUPSEC: u1, + reserved11: u10, + /// retention secure protection. + RETSEC: u1, + /// low-power modes secure protection. + LPMSEC: u1, + /// supply configuration and monitoring secure protection. + SCMSEC: u1, + /// backup domain secure protection. + VBSEC: u1, + /// voltage USB secure protection. + VUSBSEC: u1, + padding: u16, + }), + /// PWR privilege configuration register. + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// PWR secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access. + SPRIV: u1, + /// PWR non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure. + NSPRIV: u1, + padding: u30, + }), + }; + }; + + pub const pwr_h50 = struct { + pub const ALS = enum(u2) { + /// AVD level0 (VAVD0 ~ 1.7 V) + Level0 = 0x0, + /// AVD level1 (VAVD1 ~ 2.1 V) + Level1 = 0x1, + /// AVD level2 (VAVD2 ~ 2.5 V) + Level2 = 0x2, + /// AVD level3 (VAVD3 ~ 2.8 V) + Level3 = 0x3, + }; + + pub const LPMS = enum(u1) { + /// Keeps Stop mode when entering DeepSleep. + Stop = 0x0, + /// Allows Standby mode when entering DeepSleep. + Standby = 0x1, + }; + + pub const PLS = enum(u3) { + /// PVD level0 (VPVD0 ~ 1.95 V) + Level0 = 0x0, + /// PVD level1 (VPVD1 ~ 2.10 V) + Level1 = 0x1, + /// PVD level2 (VPVD2 ~ 2.25 V) + Level2 = 0x2, + /// PVD level3 (VPVD3 ~ 2.40 V) + Level3 = 0x3, + /// PVD level4 (VPVD4 ~ 2.55 V) + Level4 = 0x4, + /// PVD level5 (VPVD5 ~ 2.70 V) + Level5 = 0x5, + /// PVD level6 (VPVD6 ~ 2.85 V) + Level6 = 0x6, + /// PVD_IN pin + PVDInPin = 0x7, + }; + + pub const PowerModeInStopMode = enum(u1) { + /// Remains in normal mode when the system enters Stop mode (quick restart time). + Normal = 0x0, + /// Enters low-power mode when the system enters Stop mode (low-power consumption). + LowPower = 0x1, + }; + + pub const Retention = enum(u1) { + /// Content is lost. + Lost = 0x0, + /// Content is preserved. + Preserved = 0x1, + }; + + pub const SVOS = enum(u2) { + /// SVOS5 scale 5 + Scale5 = 0x1, + /// SVOS4 scale 4 + Scale4 = 0x2, + /// SVOS3 scale 3 (default) + Scale3 = 0x3, + _, + }; + + pub const ShutOff = enum(u1) { + /// Content is kept. + Kept = 0x0, + /// Content is lost. + Lost = 0x1, + }; + + pub const VBRS = enum(u1) { + /// Charge VBAT through a 5 kΩ resistor. + R5kOhm = 0x0, + /// Charge VBAT through a 1.5 kΩ resistor. + R1_5kOhm = 0x1, + }; + + pub const VOS = enum(u2) { + Scale3 = 0x0, + Scale2 = 0x1, + Scale1 = 0x2, + Scale0 = 0x3, + }; + + pub const WUPP = enum(u1) { + /// detection on high level (rising edge) + High = 0x0, + /// detection on low level (falling edge) + Low = 0x1, + }; + + pub const WUPPUPD = enum(u2) { + NoPullUp = 0x0, + PullUp = 0x1, + PullDown = 0x2, + _, + }; + + /// Power control. + pub const PWR = extern struct { + /// PWR power mode control register. + PMCR: mmio.Mmio(packed struct(u32) { + /// low-power mode selection This bit defines the Deepsleep mode. + LPMS: packed union { + raw: u1, + value: LPMS, + }, + reserved2: u1, + /// system Stop mode voltage scaling selection These bits control the V_CORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. + SVOS: packed union { raw: u2, - value: PLLSRC, + value: SVOS, }, - reserved4: u2, - /// Division factor for the PLL input clock - PLLM: packed union { - raw: u4, - value: PLLM, + reserved7: u3, + /// clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware. + CSSF: u1, + reserved9: u1, + /// Flash memory low-power mode in Stop mode This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode. Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode. + FLPS: packed union { + raw: u1, + value: PowerModeInStopMode, }, - /// PLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, + reserved12: u2, + /// analog switch V_BOOST control This bit enables the booster to guarantee the analog switch AC performance when the V_DD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V_DD supply voltage can be monitored through the PVD and the PLS bits. + BOOSTE: u1, + /// analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected V_DDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored. (ALS bits). + AVD_READY: u1, + reserved25: u11, + /// AHB SRAM2 shut-off in Stop mode. + SRAM2SO: packed union { + raw: u1, + value: ShutOff, }, - reserved16: u1, - /// PLL PLLSAI3CLK output enable - PLLPEN: u1, - /// PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) - PLLPBIT: packed union { + /// AHB SRAM1 shut-off in Stop mode. + SRAM1SO: packed union { raw: u1, - value: PLLPBIT, + value: ShutOff, }, - reserved20: u2, - /// PLL PLLUSB1CLK output enable - PLLQEN: u1, - /// PLL division factor for PLLUSB1CLK(48 MHz clock) - PLLQ: packed union { + padding: u5, + }), + /// PWR status register. + PMSR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Stop flag This bit is set by hardware and cleared only by any reset or by setting the CSSF bit. + STOPF: u1, + /// System standby flag This bit is set by hardware and cleared only by a POR or by setting the CSSF bit. + SBF: u1, + padding: u25, + }), + reserved16: [8]u8, + /// PWR voltage scaling control register. + VOSCR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// voltage scaling selection according to performance These bits control the V_CORE voltage level and allow to obtain the best trade-off between power consumption and performance: - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance. - When increasing the performance, the voltage scaling must be changed before increasing the system frequency. - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling. + VOS: packed union { raw: u2, - value: PLLQ, + value: VOS, }, - reserved24: u1, - /// PLL PLLCLK output enable - PLLREN: u1, - /// PLL division factor for PLLCLK (system clock) - PLLR: packed union { + padding: u26, + }), + /// PWR voltage scaling status register. + VOSSR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Ready bit for V_CORE voltage scaling output selection. + VOSRDY: u1, + reserved13: u9, + /// Voltage level ready for currently used VOS. + ACTVOSRDY: u1, + /// voltage output scaling currently applied to V_CORE This field provides the last VOS value. + ACTVOS: packed union { raw: u2, - value: PLLR, + value: VOS, }, - /// PLL division factor for PLLSAI2CLK - PLLP: packed union { - raw: u5, - value: PLLP, + padding: u16, + }), + reserved32: [8]u8, + /// PWR Backup domain control register. + BDCR: mmio.Mmio(packed struct(u32) { + /// Backup RAM retention in Standby and V_BAT modes When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and V_BAT modes) is enabled. If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in. Run and Stop modes. However its content is lost in Standby and V_BAT modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and V_BAT modes. + BREN: packed union { + raw: u1, + value: Retention, + }, + /// Backup domain voltage and temperature monitoring enable. + MONEN: u1, + reserved8: u6, + /// V_BAT charging enable Note: Reset only by POR,. + VBE: u1, + /// V_BAT charging resistor selection. + VBRS: packed union { + raw: u1, + value: VBRS, }, + padding: u22, }), - /// Clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - /// MSI ready interrupt enable - MSIRDYIE: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// PLL ready interrupt enable - PLLRDYIE: u1, - /// PLLSAI1 ready interrupt enable - PLLSAI1RDYIE: u1, - /// PLLSAI2 ready interrupt enable - PLLSAI2RDYIE: u1, - reserved9: u1, - /// LSE clock security system interrupt enable - LSECSSIE: u1, - /// HSI48 ready interrupt enable - HSI48RDYIE: u1, - padding: u21, + /// PWR Backup domain control register. + DBPCR: mmio.Mmio(packed struct(u32) { + /// Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write. access. This bit must be set to enable write access to these registers. + DBP: u1, + padding: u31, }), - /// Clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// MSI ready interrupt flag - MSIRDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// PLL ready interrupt flag - PLLRDYF: u1, - /// PLLSAI1 ready interrupt flag - PLLSAI1RDYF: u1, - /// PLLSAI2 ready interrupt flag - PLLSAI2RDYF: u1, - /// Clock security system interrupt flag - CSSF: u1, - /// LSE Clock security system interrupt flag - LSECSSF: u1, - /// HSI48 ready interrupt flag - HSI48RDYF: u1, - padding: u21, + /// PWR Backup domain status register. + BDSR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready. + BRRDY: u1, + reserved20: u3, + /// V_BAT level monitoring versus low threshold. + VBATL: u1, + /// V_BAT level monitoring versus high threshold. + VBATH: u1, + /// temperature level monitoring versus low threshold. + TEMPL: u1, + /// temperature level monitoring versus high threshold. + TEMPH: u1, + padding: u8, }), - /// Clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// MSI ready interrupt clear - MSIRDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// PLL ready interrupt clear - PLLRDYC: u1, - /// PLLSAI1 ready interrupt clear - PLLSAI1RDYC: u1, - /// PLLSAI2 ready interrupt clear - PLLSAI2RDYC: u1, - /// Clock security system interrupt clear - CSSC: u1, - /// LSE Clock security system interrupt clear - LSECSSC: u1, - /// HSI48 oscillator ready interrupt clear - HSI48RDYC: u1, + reserved48: [4]u8, + /// PWR supply configuration control register. + SCCR: mmio.Mmio(packed struct(u32) { + /// power management unit bypass. + BYPASS: u1, + reserved8: u7, + /// LDO enable The value is set by hardware when the package uses the LDO regulator. + LDOEN: u1, + padding: u23, + }), + /// PWR voltage monitor control register. + VMCR: mmio.Mmio(packed struct(u32) { + /// PVD enable. + PVDE: u1, + /// programmable voltage detector (PVD) level selection These bits select the voltage threshold detected by the PVD. + PLS: packed union { + raw: u3, + value: PLS, + }, + reserved8: u4, + /// peripheral voltage monitor on V_DDA enable. + AVDEN: u1, + /// analog voltage detector (AVD) level selection These bits select the voltage threshold detected by the AVD. + ALS: packed union { + raw: u2, + value: ALS, + }, padding: u21, }), - reserved40: [4]u8, - /// AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - /// DMAMUX1RST - DMAMUX1RST: u1, - reserved8: u5, - /// Flash memory interface reset - FLASHRST: u1, - reserved12: u3, - /// CRC reset - CRCRST: u1, - reserved16: u3, - /// Touch Sensing Controller reset - TSCRST: u1, - reserved22: u5, - /// GTZC reset - GTZCRST: u1, + reserved60: [4]u8, + /// PWR voltage monitor status register. + VMSR: mmio.Mmio(packed struct(u32) { + reserved19: u19, + /// analog voltage detector output on V_DDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set. + AVDO: u1, + /// voltage detector output on V_DDIO2 This bit is set and cleared by hardware. + VDDIO2RDY: u1, + reserved22: u1, + /// programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. + PVDO: u1, padding: u9, }), - /// AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - /// IO port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// IO port H reset - GPIOHRST: u1, - reserved13: u5, - /// ADC reset - ADCRST: u1, - reserved16: u2, - /// AES hardware accelerator reset - AESRST: u1, - /// Hash reset - HASHRST: u1, - /// Random number generator reset - RNGRST: u1, - /// PKARST - PKARST: u1, - reserved21: u1, - /// OTFDEC1RST - OTFDEC1RST: u1, - /// SDMMC1 reset - SDMMC1RST: u1, - padding: u9, + /// PWR wakeup status clear register. + WUSCR: mmio.Mmio(packed struct(u32) { + /// clear wakeup pin flag for WUFx These bits are always read as 0. + CWUF: u1, + padding: u31, }), - /// AHB3 peripheral reset register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller reset - FMCRST: u1, + /// PWR wakeup status register. + WUSR: mmio.Mmio(packed struct(u32) { + /// wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + WUF: u1, + padding: u31, + }), + /// PWR wakeup configuration register. + WUCR: mmio.Mmio(packed struct(u32) { + /// enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + WUPEN: u1, reserved8: u7, - /// OCTOSPI1RST - OCTOSPI1RST: u1, - padding: u23, + /// wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + WUPP: packed union { + raw: u1, + value: WUPP, + }, + reserved16: u7, + /// wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + WUPPUPD: packed union { + raw: u2, + value: WUPPUPD, + }, + padding: u14, }), - reserved56: [4]u8, - /// APB1 peripheral reset register 1 - APB1RSTR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer reset - TIM2RST: u1, - /// TIM3 timer reset - TIM3RST: u1, - /// TIM3 timer reset - TIM4RST: u1, - /// TIM5 timer reset - TIM5RST: u1, - /// TIM6 timer reset - TIM6RST: u1, - /// TIM7 timer reset - TIM7RST: u1, - reserved14: u8, - /// SPI2 reset - SPI2RST: u1, - /// SPI3 reset - SPI3RST: u1, - reserved17: u1, - /// USART2 reset - USART2RST: u1, - /// USART3 reset - USART3RST: u1, - /// UART4 reset - UART4RST: u1, - /// UART5 reset - UART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// I2C3 reset - I2C3RST: u1, - /// CRS reset - CRSRST: u1, - reserved28: u3, - /// Power interface reset - PWRRST: u1, - /// DAC1 interface reset - DAC1RST: u1, - /// OPAMP interface reset - OPAMPRST: u1, - /// Low Power Timer 1 reset - LPTIM1RST: u1, + reserved80: [4]u8, + /// PWR I/O retention register. + IORETR: mmio.Mmio(packed struct(u32) { + /// IO retention enable: When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register. + IORETEN: u1, + reserved16: u15, + /// IO retention enable for JTAG IOs when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. + JTAGIORETEN: u1, + padding: u15, }), - /// APB1 peripheral reset register 2 - APB1RSTR2: mmio.Mmio(packed struct(u32) { - /// Low-power UART 1 reset - LPUART1RST: u1, - /// I2C4 reset - I2C4RST: u1, - reserved5: u3, - /// Low-power timer 2 reset - LPTIM2RST: u1, - /// LPTIM3RST - LPTIM3RST: u1, - reserved9: u2, - /// FDCAN1RST - FDCAN1RST: u1, - reserved21: u11, - /// USBRST - USBRST: u1, - reserved23: u1, - /// UCPD1RST - UCPD1RST: u1, - padding: u8, + reserved260: [176]u8, + /// PWR privilege configuration register. + PRIVCFGR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWR non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure. + NSPRIV: u1, + padding: u30, }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// System configuration (SYSCFG) reset - SYSCFGRST: u1, - reserved11: u10, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI1 reset - SPI1RST: u1, - /// TIM8 timer reset - TIM8RST: u1, - /// USART1 reset - USART1RST: u1, - reserved16: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - reserved21: u2, - /// Serial audio interface 1 (SAI1) reset - SAI1RST: u1, - /// Serial audio interface 2 (SAI2) reset - SAI2RST: u1, - reserved24: u1, - /// Digital filters for sigma-delata modulators (DFSDM) reset - DFSDM1RST: u1, - padding: u7, - }), - reserved72: [4]u8, - /// AHB1 peripheral clock enable register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// DMAMUX clock enable - DMAMUX1EN: u1, - reserved8: u5, - /// Flash memory interface clock enable - FLASHEN: u1, - reserved12: u3, - /// CRC clock enable - CRCEN: u1, - reserved16: u3, - /// Touch Sensing Controller clock enable - TSCEN: u1, - reserved22: u5, - /// GTZCEN - GTZCEN: u1, - padding: u9, + }; + }; + + pub const pwr_h7rm0399 = struct { + pub const SDLEVEL = enum(u2) { + Reset = 0x0, + V1_8 = 0x1, + V2_5 = 0x2, + V2_5_ALT = 0x3, + }; + + pub const VOS = enum(u2) { + Scale3 = 0x1, + Scale2 = 0x2, + Scale1 = 0x3, + _, + }; + + pub const WKUPPUPD = enum(u2) { + /// No pull-up. + NoPull = 0x0, + /// Pull-up. + PullUp = 0x1, + /// Pull-down. + PullDown = 0x2, + _, + }; + + /// PWR + pub const PWR = extern struct { + /// PWR control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) + LPDS: u1, + reserved4: u3, + /// Programmable voltage detector enable + PVDE: u1, + /// Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. + PLS: u3, + /// Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. + DBP: u1, + /// Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. + FLPS: u1, + reserved14: u4, + /// System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. + SVOS: u2, + /// Peripheral voltage monitor on VDDA enable + AVDEN: u1, + /// Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. + ALS: u2, + padding: u13, }), - /// AHB2 peripheral clock enable register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port C clock enable - GPIOCEN: u1, - /// IO port D clock enable - GPIODEN: u1, - /// IO port E clock enable - GPIOEEN: u1, - /// IO port F clock enable - GPIOFEN: u1, - /// IO port G clock enable - GPIOGEN: u1, - /// IO port H clock enable - GPIOHEN: u1, - reserved13: u5, - /// ADC clock enable - ADCEN: u1, - reserved16: u2, - /// AES accelerator clock enable - AESEN: u1, - /// HASH clock enable - HASHEN: u1, - /// Random Number Generator clock enable - RNGEN: u1, - /// PKAEN - PKAEN: u1, - reserved21: u1, - /// OTFDEC1EN - OTFDEC1EN: u1, - /// SDMMC1 clock enable - SDMMC1EN: u1, - padding: u9, + /// PWR control status register 1 + CSR1: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. + PVDO: u1, + reserved13: u8, + /// Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). + ACTVOSRDY: u1, + /// VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. + ACTVOS: u2, + /// Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set. + AVDO: u1, + padding: u15, }), - /// AHB3 peripheral clock enable register - AHB3ENR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller clock enable - FMCEN: u1, - reserved8: u7, - /// OCTOSPI1EN - OCTOSPI1EN: u1, - padding: u23, + /// This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. + CR2: mmio.Mmio(packed struct(u32) { + /// Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. + BREN: u1, + reserved4: u3, + /// VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. + MONEN: u1, + reserved16: u11, + /// Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. + BRRDY: u1, + reserved20: u3, + /// VBAT level monitoring versus low threshold + VBATL: u1, + /// VBAT level monitoring versus high threshold + VBATH: u1, + /// Temperature level monitoring versus low threshold + TEMPL: u1, + /// Temperature level monitoring versus high threshold + TEMPH: u1, + padding: u8, }), - reserved88: [4]u8, - /// APB1ENR1 - APB1ENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clock enable - TIM2EN: u1, - /// TIM3 timer clock enable - TIM3EN: u1, - /// TIM4 timer clock enable - TIM4EN: u1, - /// TIM5 timer clock enable - TIM5EN: u1, - /// TIM6 timer clock enable - TIM6EN: u1, - /// TIM7 timer clock enable - TIM7EN: u1, - reserved10: u4, - /// RTC APB clock enable - RTCAPBEN: u1, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI2 clock enable - SPI2EN: u1, - /// SPI3 clock enable - SPI3EN: u1, - reserved17: u1, - /// USART2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// UART5 clock enable - UART5EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - /// I2C2 clock enable - I2C2EN: u1, - /// I2C3 clock enable - I2C3EN: u1, - /// Clock Recovery System clock enable - CRSEN: u1, - reserved28: u3, - /// Power interface clock enable - PWREN: u1, - /// DAC1 interface clock enable - DAC1EN: u1, - /// OPAMP interface clock enable - OPAMPEN: u1, - /// Low power timer 1 clock enable - LPTIM1EN: u1, + /// Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value. + CR3: mmio.Mmio(packed struct(u32) { + /// Power management unit bypass + BYPASS: u1, + /// Low drop-out regulator enable + LDOEN: u1, + /// SD converter Enable + SDEN: u1, + /// Step-down converter forced ON and in High Power MR mode + SDEXTHP: u1, + /// Step-down converter voltage output level selection + SDLEVEL: packed union { + raw: u2, + value: SDLEVEL, + }, + reserved8: u2, + /// VBAT charging enable + VBE: u1, + /// VBAT charging resistor selection + VBRS: u1, + reserved16: u6, + /// SMPS step-down converter external supply ready + SDEXTRDY: u1, + reserved24: u7, + /// VDD33USB voltage level detector enable. + USB33DEN: u1, + /// USB regulator enable. + USBREGEN: u1, + /// USB supply ready. + USB33RDY: u1, + padding: u5, }), - /// APB1 peripheral clock enable register 2 - APB1ENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clock enable - LPUART1EN: u1, - /// I2C4 clock enable - I2C4EN: u1, - reserved5: u3, - /// LPTIM2EN - LPTIM2EN: u1, - /// LPTIM3EN - LPTIM3EN: u1, - reserved9: u2, - /// FDCAN1EN - FDCAN1EN: u1, - reserved21: u11, - /// USBEN - USBEN: u1, - reserved23: u1, - /// UCPD1EN - UCPD1EN: u1, - padding: u8, + /// This register allows controlling CPU1 power. + CPUCR: mmio.Mmio(packed struct(u32) { + /// D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. + PDDS_D1: u1, + /// D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. + PDDS_D2: u1, + /// System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. + PDDS_D3: u1, + reserved5: u2, + /// STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. + STOPF: u1, + /// System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit + SBF: u1, + /// D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. + SBF_D1: u1, + /// D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. + SBF_D2: u1, + /// Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. + CSSF: u1, + reserved11: u1, + /// Keep system D3 domain in Run mode regardless of the CPU sub-systems modes + RUN_D3: u1, + padding: u20, }), - /// APB2ENR - APB2ENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved11: u10, - /// TIM1 timer clock enable - TIM1EN: u1, - /// SPI1 clock enable - SPI1EN: u1, - /// TIM8 timer clock enable - TIM8EN: u1, - /// USART1clock enable - USART1EN: u1, - reserved16: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - reserved21: u2, - /// SAI1 clock enable - SAI1EN: u1, - /// SAI2 clock enable - SAI2EN: u1, - reserved24: u1, - /// DFSDM timer clock enable - DFSDM1EN: u1, - padding: u7, + reserved24: [4]u8, + /// This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + D3CR: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). + VOSRDY: u1, + /// Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling. + VOS: packed union { + raw: u2, + value: VOS, + }, + padding: u16, }), - reserved104: [4]u8, - /// AHB1 peripheral clocks enable in Sleep and Stop modes register - AHB1SMENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clocks enable during Sleep and Stop modes - DMA1SMEN: u1, - /// DMA2 clocks enable during Sleep and Stop modes - DMA2SMEN: u1, - /// DMAMUX clock enable during Sleep and Stop modes - DMAMUX1SMEN: u1, - reserved8: u5, - /// Flash memory interface clocks enable during Sleep and Stop modes - FLASHSMEN: u1, - /// SRAM1 interface clocks enable during Sleep and Stop modes - SRAM1SMEN: u1, - reserved12: u2, - /// CRCSMEN - CRCSMEN: u1, - reserved16: u3, - /// Touch Sensing Controller clocks enable during Sleep and Stop modes - TSCSMEN: u1, - reserved22: u5, - /// GTZCSMEN - GTZCSMEN: u1, - /// ICACHESMEN - ICACHESMEN: u1, - padding: u8, + reserved32: [4]u8, + /// reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). + WKUPCR: mmio.Mmio(packed struct(u32) { + /// Clear Wakeup pin flag for WKUP. These bits are always read as 0. + WKUPC: u6, + padding: u26, }), - /// AHB2 peripheral clocks enable in Sleep and Stop modes register - AHB2SMENR: mmio.Mmio(packed struct(u32) { - /// IO port A clocks enable during Sleep and Stop modes - GPIOASMEN: u1, - /// IO port B clocks enable during Sleep and Stop modes - GPIOBSMEN: u1, - /// IO port C clocks enable during Sleep and Stop modes - GPIOCSMEN: u1, - /// IO port D clocks enable during Sleep and Stop modes - GPIODSMEN: u1, - /// IO port E clocks enable during Sleep and Stop modes - GPIOESMEN: u1, - /// IO port F clocks enable during Sleep and Stop modes - GPIOFSMEN: u1, - /// IO port G clocks enable during Sleep and Stop modes - GPIOGSMEN: u1, - /// IO port H clocks enable during Sleep and Stop modes - GPIOHSMEN: u1, - reserved9: u1, - /// SRAM2 interface clocks enable during Sleep and Stop modes - SRAM2SMEN: u1, - reserved13: u3, - /// ADC clocks enable during Sleep and Stop modes - ADCFSSMEN: u1, - reserved16: u2, - /// AES accelerator clocks enable during Sleep and Stop modes - AESSMEN: u1, - /// HASH clock enable during Sleep and Stop modes - HASHSMEN: u1, - /// Random Number Generator clocks enable during Sleep and Stop modes - RNGSMEN: u1, - /// PKASMEN - PKASMEN: u1, - reserved21: u1, - /// OTFDEC1SMEN - OTFDEC1SMEN: u1, - /// SDMMC1 clocks enable during Sleep and Stop modes - SDMMC1SMEN: u1, - padding: u9, + /// reset only by system reset, not reset by wakeup from Standby mode + WKUPFR: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + WKUPF: u1, + padding: u31, }), - /// AHB3 peripheral clocks enable in Sleep and Stop modes register - AHB3SMENR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller clocks enable during Sleep and Stop modes - FMCSMEN: u1, + /// Reset only by system reset, not reset by wakeup from Standby mode + WKUPEPR: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + WKUPEN: u1, reserved8: u7, - /// OCTOSPI1SMEN - OCTOSPI1SMEN: u1, - padding: u23, + /// Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + WKUPP: u1, + reserved16: u7, + /// Wakeup pin pull configuration + WKUPPUPD: packed union { + raw: u2, + value: WKUPPUPD, + }, + padding: u14, }), - reserved120: [4]u8, - /// APB1SMENR1 - APB1SMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clocks enable during Sleep and Stop modes - TIM2SMEN: u1, - /// TIM3 timer clocks enable during Sleep and Stop modes - TIM3SMEN: u1, - /// TIM4 timer clocks enable during Sleep and Stop modes - TIM4SMEN: u1, - /// TIM5 timer clocks enable during Sleep and Stop modes - TIM5SMEN: u1, - /// TIM6 timer clocks enable during Sleep and Stop modes - TIM6SMEN: u1, - /// TIM7 timer clocks enable during Sleep and Stop modes - TIM7SMEN: u1, - reserved10: u4, - /// RTC APB clock enable during Sleep and Stop modes - RTCAPBSMEN: u1, - /// Window watchdog clocks enable during Sleep and Stop modes - WWDGSMEN: u1, - reserved14: u2, - /// SPI2 clocks enable during Sleep and Stop modes - SPI2SMEN: u1, - /// SPI3 clocks enable during Sleep and Stop modes - SP3SMEN: u1, - reserved17: u1, - /// USART2 clocks enable during Sleep and Stop modes - USART2SMEN: u1, - /// USART3 clocks enable during Sleep and Stop modes - USART3SMEN: u1, - /// UART4 clocks enable during Sleep and Stop modes - UART4SMEN: u1, - /// UART5 clocks enable during Sleep and Stop modes - UART5SMEN: u1, - /// I2C1 clocks enable during Sleep and Stop modes - I2C1SMEN: u1, - /// I2C2 clocks enable during Sleep and Stop modes - I2C2SMEN: u1, - /// I2C3 clocks enable during Sleep and Stop modes - I2C3SMEN: u1, - /// CRS clock enable during Sleep and Stop modes - CRSSMEN: u1, - reserved28: u3, - /// Power interface clocks enable during Sleep and Stop modes - PWRSMEN: u1, - /// DAC1 interface clocks enable during Sleep and Stop modes - DAC1SMEN: u1, - /// OPAMP interface clocks enable during Sleep and Stop modes - OPAMPSMEN: u1, - /// Low power timer 1 clocks enable during Sleep and Stop modes - LPTIM1SMEN: u1, + }; + }; + + pub const pwr_h7rm0433 = struct { + pub const VOS = enum(u2) { + Scale3 = 0x1, + Scale2 = 0x2, + Scale1 = 0x3, + _, + }; + + pub const WKUPPUPD = enum(u2) { + /// No pull-up. + NoPull = 0x0, + /// Pull-up. + PullUp = 0x1, + /// Pull-down. + PullDown = 0x2, + _, + }; + + /// PWR + pub const PWR = extern struct { + /// PWR control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) + LPDS: u1, + reserved4: u3, + /// Programmable voltage detector enable + PVDE: u1, + /// Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. + PLS: u3, + /// Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. + DBP: u1, + /// Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. + FLPS: u1, + reserved14: u4, + /// System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. + SVOS: u2, + /// Peripheral voltage monitor on VDDA enable + AVDEN: u1, + /// Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. + ALS: u2, + padding: u13, }), - /// APB1 peripheral clocks enable in Sleep and Stop modes register 2 - APB1SMENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clocks enable during Sleep and Stop modes - LPUART1SMEN: u1, - /// I2C4 clocks enable during Sleep and Stop modes - I2C4SMEN: u1, - reserved5: u3, - /// LPTIM2SMEN - LPTIM2SMEN: u1, - /// LPTIM3SMEN - LPTIM3SMEN: u1, - reserved9: u2, - /// FDCAN1SMEN - FDCAN1SMEN: u1, - reserved21: u11, - /// USBSMEN - USBSMEN: u1, - reserved23: u1, - /// UCPD1SMEN - UCPD1SMEN: u1, + /// PWR control status register 1 + CSR1: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. + PVDO: u1, + reserved13: u8, + /// Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). + ACTVOSRDY: u1, + /// VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. + ACTVOS: u2, + /// Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set. + AVDO: u1, + padding: u15, + }), + /// This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. + CR2: mmio.Mmio(packed struct(u32) { + /// Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. + BREN: u1, + reserved4: u3, + /// VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. + MONEN: u1, + reserved16: u11, + /// Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. + BRRDY: u1, + reserved20: u3, + /// VBAT level monitoring versus low threshold + VBATL: u1, + /// VBAT level monitoring versus high threshold + VBATH: u1, + /// Temperature level monitoring versus low threshold + TEMPL: u1, + /// Temperature level monitoring versus high threshold + TEMPH: u1, padding: u8, }), - /// APB2SMENR - APB2SMENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clocks enable during Sleep and Stop modes - SYSCFGSMEN: u1, - reserved11: u10, - /// TIM1 timer clocks enable during Sleep and Stop modes - TIM1SMEN: u1, - /// SPI1 clocks enable during Sleep and Stop modes - SPI1SMEN: u1, - /// TIM8 timer clocks enable during Sleep and Stop modes - TIM8SMEN: u1, - /// USART1clocks enable during Sleep and Stop modes - USART1SMEN: u1, - reserved16: u1, - /// TIM15 timer clocks enable during Sleep and Stop modes - TIM15SMEN: u1, - /// TIM16 timer clocks enable during Sleep and Stop modes - TIM16SMEN: u1, - /// TIM17 timer clocks enable during Sleep and Stop modes - TIM17SMEN: u1, - reserved21: u2, - /// SAI1 clocks enable during Sleep and Stop modes - SAI1SMEN: u1, - /// SAI2 clocks enable during Sleep and Stop modes - SAI2SMEN: u1, - reserved24: u1, - /// DFSDM timer clocks enable during Sleep and Stop modes - DFSDM1SMEN: u1, - padding: u7, + /// Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value. + CR3: mmio.Mmio(packed struct(u32) { + /// Power management unit bypass + BYPASS: u1, + /// Low drop-out regulator enable + LDOEN: u1, + /// Supply configuration update enable + SCUEN: u1, + reserved8: u5, + /// VBAT charging enable + VBE: u1, + /// VBAT charging resistor selection + VBRS: u1, + reserved24: u14, + /// VDD33USB voltage level detector enable. + USB33DEN: u1, + /// USB regulator enable. + USBREGEN: u1, + /// USB supply ready. + USB33RDY: u1, + padding: u5, }), - reserved136: [4]u8, - /// CCIPR - CCIPR: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SEL: u2, - /// USART2 clock source selection - USART2SEL: u2, - /// USART3 clock source selection - USART3SEL: u2, - /// UART4 clock source selection - UART4SEL: u2, - /// UART5 clock source selection - UART5SEL: u2, - /// LPUART1 clock source selection - LPUART1SEL: u2, - /// I2C1 clock source selection - I2C1SEL: u2, - /// I2C2 clock source selection - I2C2SEL: u2, - /// I2C3 clock source selection - I2C3SEL: u2, - /// Low power timer 1 clock source selection - LPTIM1SEL: u2, - /// Low power timer 2 clock source selection - LPTIM2SEL: u2, - /// Low-power timer 3 clock source selection - LPTIM3SEL: u2, - /// FDCAN clock source selection - FDCANSEL: packed union { - raw: u2, - value: FDCANSEL, - }, - /// 48 MHz clock source selection - CLK48SEL: packed union { - raw: u2, - value: CLK48SEL, - }, - /// ADCs clock source selection - ADCSEL: packed union { + /// This register allows controlling CPU1 power. + CPUCR: mmio.Mmio(packed struct(u32) { + /// D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. + PDDS_D1: u1, + /// D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. + PDDS_D2: u1, + /// System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. + PDDS_D3: u1, + reserved5: u2, + /// STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. + STOPF: u1, + /// System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit + SBF: u1, + /// D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. + SBF_D1: u1, + /// D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. + SBF_D2: u1, + /// Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. + CSSF: u1, + reserved11: u1, + /// Keep system D3 domain in Run mode regardless of the CPU sub-systems modes + RUN_D3: u1, + padding: u20, + }), + reserved24: [4]u8, + /// This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + D3CR: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). + VOSRDY: u1, + /// Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling. + VOS: packed union { raw: u2, - value: ADCSEL, + value: VOS, }, - padding: u2, + padding: u16, }), - reserved144: [4]u8, - /// BDCR - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enable - LSEON: u1, - /// LSE oscillator ready - LSERDY: u1, - /// LSE oscillator bypass - LSEBYP: u1, - /// SE oscillator drive capability - LSEDRV: packed union { + reserved32: [4]u8, + /// reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). + WKUPCR: mmio.Mmio(packed struct(u32) { + /// Clear Wakeup pin flag for WKUP. These bits are always read as 0. + WKUPC: u6, + padding: u26, + }), + /// reset only by system reset, not reset by wakeup from Standby mode + WKUPFR: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + WKUPF: u1, + padding: u31, + }), + /// Reset only by system reset, not reset by wakeup from Standby mode + WKUPEPR: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + WKUPEN: u1, + reserved8: u7, + /// Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + WKUPP: u1, + reserved16: u7, + /// Wakeup pin pull configuration + WKUPPUPD: packed union { raw: u2, - value: LSEDRV, + value: WKUPPUPD, }, - /// LSECSSON - LSECSSON: u1, - /// LSECSSD - LSECSSD: u1, - /// LSESYSEN - LSESYSEN: u1, - /// RTC clock source selection - RTCSEL: packed union { + padding: u14, + }), + }; + }; + + pub const pwr_h7rm0455 = struct { + pub const SDLEVEL = enum(u2) { + Reset = 0x0, + V1_8 = 0x1, + V2_5 = 0x2, + V2_5_ALT = 0x3, + }; + + pub const VOS = enum(u2) { + Scale3 = 0x0, + Scale2 = 0x1, + Scale1 = 0x2, + Scale0 = 0x3, + }; + + pub const WKUPPUPD = enum(u2) { + /// No pull-up. + NoPull = 0x0, + /// Pull-up. + PullUp = 0x1, + /// Pull-down. + PullDown = 0x2, + _, + }; + + /// PWR + pub const PWR = extern struct { + /// PWR control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) + LPDS: u1, + reserved4: u3, + /// Programmable voltage detector enable + PVDE: u1, + /// Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. + PLS: u3, + /// Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. + DBP: u1, + /// Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. + FLPS: u1, + reserved14: u4, + /// System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. + SVOS: u2, + /// Peripheral voltage monitor on VDDA enable + AVDEN: u1, + /// Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. + ALS: u2, + padding: u13, + }), + /// PWR control status register 1 + CSR1: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. + PVDO: u1, + reserved13: u8, + /// Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). + ACTVOSRDY: u1, + /// VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. + ACTVOS: u2, + /// Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set. + AVDO: u1, + padding: u15, + }), + /// This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. + CR2: mmio.Mmio(packed struct(u32) { + /// Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. + BREN: u1, + reserved4: u3, + /// VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. + MONEN: u1, + reserved16: u11, + /// Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. + BRRDY: u1, + reserved20: u3, + /// VBAT level monitoring versus low threshold + VBATL: u1, + /// VBAT level monitoring versus high threshold + VBATH: u1, + /// Temperature level monitoring versus low threshold + TEMPL: u1, + /// Temperature level monitoring versus high threshold + TEMPH: u1, + padding: u8, + }), + /// Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value. + CR3: mmio.Mmio(packed struct(u32) { + /// Power management unit bypass + BYPASS: u1, + /// Low drop-out regulator enable + LDOEN: u1, + /// SD converter Enable + SDEN: u1, + /// Step-down converter forced ON and in High Power MR mode + SDEXTHP: u1, + /// Step-down converter voltage output level selection + SDLEVEL: packed union { raw: u2, - value: RTCSEL, + value: SDLEVEL, }, - reserved11: u1, - /// LSESYSRDY - LSESYSRDY: u1, - reserved15: u3, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, + reserved8: u2, + /// VBAT charging enable + VBE: u1, + /// VBAT charging resistor selection + VBRS: u1, + reserved16: u6, + /// SMPS step-down converter external supply ready + SDEXTRDY: u1, reserved24: u7, - /// Low speed clock output enable - LSCOEN: u1, - /// Low speed clock output selection - LSCOSEL: packed union { - raw: u1, - value: LSCOSEL, - }, - padding: u6, + /// VDD33USB voltage level detector enable. + USB33DEN: u1, + /// USB regulator enable. + USBREGEN: u1, + /// USB supply ready. + USB33RDY: u1, + padding: u5, }), - /// CSR - CSR: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable - LSION: u1, - /// LSI oscillator ready - LSIRDY: u1, - reserved4: u2, - /// LSIPREDIV - LSIPREDIV: u1, - reserved8: u3, - /// SI range after Standby mode - MSISRANGE: u4, - reserved23: u11, - /// Remove reset flag - RMVF: u1, - reserved25: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// Pin reset flag - PINRSTF: u1, - /// BOR flag - BORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent window watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// This register allows controlling CPU1 power. + CPUCR: mmio.Mmio(packed struct(u32) { + /// D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. + PDDS_D1: u1, + /// D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. + PDDS_D2: u1, + /// System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. + PDDS_D3: u1, + reserved5: u2, + /// STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. + STOPF: u1, + /// System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit + SBF: u1, + /// D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. + SBF_D1: u1, + /// D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. + SBF_D2: u1, + /// Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. + CSSF: u1, + reserved11: u1, + /// Keep system D3 domain in Run mode regardless of the CPU sub-systems modes + RUN_D3: u1, + padding: u20, }), - /// Clock recovery RC register - CRRCR: mmio.Mmio(packed struct(u32) { - /// HSI48 clock enable - HSI48ON: u1, - /// HSI48 clock ready flag - HSI48RDY: u1, - reserved7: u5, - /// HSI48 clock calibration - HSI48CAL: u9, + reserved24: [4]u8, + /// This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + D3CR: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). + VOSRDY: u1, + /// Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling. + VOS: packed union { + raw: u2, + value: VOS, + }, padding: u16, }), - /// Peripherals independent clock configuration register - CCIPR2: mmio.Mmio(packed struct(u32) { - /// I2C4 clock source selection - I2C4SEL: u2, - /// Digital filter for sigma delta modulator kernel clock source selection - DFSDMSEL: u1, - /// Digital filter for sigma delta modulator audio clock source selection - ADFSDMSEL: u2, - /// SAI1 clock source selection - SAI1SEL: u3, - /// SAI2 clock source selection - SAI2SEL: u3, - reserved14: u3, - /// SDMMC clock selection - SDMMCSEL: u1, - reserved20: u5, - /// Octospi clock source selection - OCTOSPISEL: u2, - padding: u10, + reserved32: [4]u8, + /// reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). + WKUPCR: mmio.Mmio(packed struct(u32) { + /// Clear Wakeup pin flag for WKUP. These bits are always read as 0. + WKUPC: u6, + padding: u26, }), - reserved184: [24]u8, - /// RCC secure configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// HSISEC - HSISEC: u1, - /// HSESEC - HSESEC: u1, - /// MSISEC - MSISEC: u1, - /// LSISEC - LSISEC: u1, - /// LSESEC - LSESEC: u1, - /// SYSCLKSEC - SYSCLKSEC: u1, - /// PRESCSEC - PRESCSEC: u1, - /// PLLSEC - PLLSEC: u1, - /// PLLSAI1SEC - PLLSAI1SEC: u1, - /// PLLSAI2SEC - PLLSAI2SEC: u1, - /// CLK48SEC - CLK48SEC: u1, - /// HSI48SEC - HSI48SEC: u1, - /// RMVFSEC - RMVFSEC: u1, - padding: u19, + /// reset only by system reset, not reset by wakeup from Standby mode + WKUPFR: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + WKUPF: u1, + padding: u31, }), - /// RCC secure status register - SECSR: mmio.Mmio(packed struct(u32) { - /// HSISECF - HSISECF: u1, - /// HSESECF - HSESECF: u1, - /// MSISECF - MSISECF: u1, - /// LSISECF - LSISECF: u1, - /// LSESECF - LSESECF: u1, - /// SYSCLKSECF - SYSCLKSECF: u1, - /// PRESCSECF - PRESCSECF: u1, - /// PLLSECF - PLLSECF: u1, - /// PLLSAI1SECF - PLLSAI1SECF: u1, - /// PLLSAI2SECF - PLLSAI2SECF: u1, - /// CLK48SECF - CLK48SECF: u1, - /// HSI48SECF - HSI48SECF: u1, - /// RMVFSECF - RMVFSECF: u1, - padding: u19, - }), - reserved232: [40]u8, - /// RCC AHB1 security status register - AHB1SECSR: mmio.Mmio(packed struct(u32) { - /// DMA1SECF - DMA1SECF: u1, - /// DMA2SECF - DMA2SECF: u1, - /// DMAMUX1SECF - DMAMUX1SECF: u1, - reserved8: u5, - /// FLASHSECF - FLASHSECF: u1, - /// SRAM1SECF - SRAM1SECF: u1, - reserved12: u2, - /// CRCSECF - CRCSECF: u1, - reserved16: u3, - /// TSCSECF - TSCSECF: u1, - reserved22: u5, - /// GTZCSECF - GTZCSECF: u1, - /// ICACHESECF - ICACHESECF: u1, - padding: u8, - }), - /// RCC AHB2 security status register - AHB2SECSR: mmio.Mmio(packed struct(u32) { - /// GPIOASECF - GPIOASECF: u1, - /// GPIOBSECF - GPIOBSECF: u1, - /// GPIOCSECF - GPIOCSECF: u1, - /// GPIODSECF - GPIODSECF: u1, - /// GPIOESECF - GPIOESECF: u1, - /// GPIOFSECF - GPIOFSECF: u1, - /// GPIOGSECF - GPIOGSECF: u1, - /// GPIOHSECF - GPIOHSECF: u1, - reserved9: u1, - /// SRAM2SECF - SRAM2SECF: u1, - reserved21: u11, - /// OTFDEC1SECF - OTFDEC1SECF: u1, - /// SDMMC1SECF - SDMMC1SECF: u1, - padding: u9, - }), - /// RCC AHB3 security status register - AHB3SECSR: mmio.Mmio(packed struct(u32) { - /// FSMCSECF - FSMCSECF: u1, + /// Reset only by system reset, not reset by wakeup from Standby mode + WKUPEPR: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + WKUPEN: u1, reserved8: u7, - /// OCTOSPI1SECF - OCTOSPI1SECF: u1, - padding: u23, - }), - reserved248: [4]u8, - /// RCC APB1 security status register 1 - APB1SECSR1: mmio.Mmio(packed struct(u32) { - /// TIM2SECF - TIM2SECF: u1, - /// TIM3SECF - TIM3SECF: u1, - /// TIM4SECF - TIM4SECF: u1, - /// TIM5SECF - TIM5SECF: u1, - /// TIM6SECF - TIM6SECF: u1, - /// TIM7SECF - TIM7SECF: u1, - reserved10: u4, - /// RTCAPBSECF - RTCAPBSECF: u1, - /// WWDGSECF - WWDGSECF: u1, - reserved14: u2, - /// SPI2SECF - SPI2SECF: u1, - /// SPI3SECF - SPI3SECF: u1, - reserved17: u1, - /// UART2SECF - UART2SECF: u1, - /// UART3SECF - UART3SECF: u1, - /// UART4SECF - UART4SECF: u1, - /// UART5SECF - UART5SECF: u1, - /// I2C1SECF - I2C1SECF: u1, - /// I2C2SECF - I2C2SECF: u1, - /// I2C3SECF - I2C3SECF: u1, - /// CRSSECF - CRSSECF: u1, - reserved28: u3, - /// PWRSECF - PWRSECF: u1, - /// DACSECF - DACSECF: u1, - /// OPAMPSECF - OPAMPSECF: u1, - /// LPTIM1SECF - LPTIM1SECF: u1, - }), - /// RCC APB1 security status register 2 - APB1SECSR2: mmio.Mmio(packed struct(u32) { - /// LPUART1SECF - LPUART1SECF: u1, - /// I2C4SECF - I2C4SECF: u1, - reserved5: u3, - /// LPTIM2SECF - LPTIM2SECF: u1, - /// LPTIM3SECF - LPTIM3SECF: u1, - reserved9: u2, - /// FDCAN1SECF - FDCAN1SECF: u1, - reserved21: u11, - /// USBSECF - USBSECF: u1, - reserved23: u1, - /// UCPD1SECF - UCPD1SECF: u1, - padding: u8, - }), - /// RCC APB2 security status register - APB2SECSR: mmio.Mmio(packed struct(u32) { - /// SYSCFGSECF - SYSCFGSECF: u1, - reserved11: u10, - /// TIM1SECF - TIM1SECF: u1, - /// SPI1SECF - SPI1SECF: u1, - /// TIM8SECF - TIM8SECF: u1, - /// USART1SECF - USART1SECF: u1, - reserved16: u1, - /// TIM15SECF - TIM15SECF: u1, - /// TIM16SECF - TIM16SECF: u1, - /// TIM17SECF - TIM17SECF: u1, - reserved21: u2, - /// SAI1SECF - SAI1SECF: u1, - /// SAI2SECF - SAI2SECF: u1, - reserved24: u1, - /// DFSDM1SECF - DFSDM1SECF: u1, - padding: u7, + /// Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + WKUPP: u1, + reserved16: u7, + /// Wakeup pin pull configuration + WKUPPUPD: packed union { + raw: u2, + value: WKUPPUPD, + }, + padding: u14, }), }; }; - pub const adccommon_v3 = struct { - pub const DMACFG = enum(u1) { - /// DMA One Shot mode selected - OneShot = 0x0, - /// DMA Circular mode selected - Circular = 0x1, + pub const pwr_h7rm0468 = struct { + pub const SDLEVEL = enum(u2) { + Reset = 0x0, + V1_8 = 0x1, + V2_5 = 0x2, + V2_5_ALT = 0x3, }; - /// Analog-to-Digital Converter - pub const ADC_COMMON = extern struct { - /// ADC Common status register - CSR: mmio.Mmio(packed struct(u32) { - /// ADDRDY_MST - ADDRDY_MST: u1, - /// EOSMP_MST - EOSMP_MST: u1, - /// EOC_MST - EOC_MST: u1, - /// EOS_MST - EOS_MST: u1, - /// OVR_MST - OVR_MST: u1, - /// JEOC_MST - JEOC_MST: u1, - /// JEOS_MST - JEOS_MST: u1, - /// Analog watchdog flag of the master ADC - AWD_MST: u1, - reserved10: u2, - /// JQOVF_MST - JQOVF_MST: u1, - reserved16: u5, - /// ADRDY_SLV - ADRDY_SLV: u1, - /// EOSMP_SLV - EOSMP_SLV: u1, - /// End of regular conversion of the slave ADC - EOC_SLV: u1, - /// End of regular sequence flag of the slave ADC - EOS_SLV: u1, - /// Overrun flag of the slave ADC - OVR_SLV: u1, - /// End of injected conversion flag of the slave ADC - JEOC_SLV: u1, - /// End of injected sequence flag of the slave ADC - JEOS_SLV: u1, - /// Analog watchdog 1 flag of the slave ADC - AWD_SLV: u1, - reserved26: u2, - /// Injected Context Queue Overflow flag of the slave ADC - JQOVF_SLV: u1, - padding: u5, - }), - reserved8: [4]u8, - /// ADC common control register - CCR: mmio.Mmio(packed struct(u32) { - /// Multi ADC mode selection - MULT: u5, - reserved8: u3, - /// Delay between 2 sampling phases - DELAY: u4, - reserved13: u1, - /// Direct memory access configuration - DMACFG: packed union { - raw: u1, - value: DMACFG, - }, - /// Direct memory access mode for multi ADC mode - MDMA: u2, - /// ADC clock mode - CKMODE: u2, - reserved22: u4, - /// VREFINT enable - VREFEN: u1, - /// CH18 selection (Vbat) - CH18SEL: u1, - /// CH17 selection (temperature) - CH17SEL: u1, - padding: u7, - }), - /// ADC common regular data register for dual and triple modes - CDR: mmio.Mmio(packed struct(u32) { - /// Regular data of the master ADC - RDATA_MST: u16, - /// Regular data of the slave ADC - RDATA_SLV: u16, - }), + pub const VOS = enum(u2) { + Scale0 = 0x0, + Scale3 = 0x1, + Scale2 = 0x2, + Scale1 = 0x3, }; - }; - pub const cec_v1 = struct { - /// HDMI-CEC controller. - pub const CEC = extern struct { - /// configuration register. - CFGR: mmio.Mmio(packed struct(u32) { - /// Peripheral enable. - PE: u1, - /// Interrupt enable. - IE: u1, - /// Bit timing error mode. - BTEM: u1, - /// Bit period error mode. - BPEM: u1, - padding: u28, - }), - /// CEC own address register. - OAR: mmio.Mmio(packed struct(u32) { - /// Own address. - OA: u4, - padding: u28, - }), - /// Rx Data Register. - PRES: mmio.Mmio(packed struct(u32) { - /// CEC Rx Data Register. - PRESC: u14, - padding: u18, + pub const WKUPPUPD = enum(u2) { + /// No pull-up. + NoPull = 0x0, + /// Pull-up. + PullUp = 0x1, + /// Pull-down. + PullDown = 0x2, + _, + }; + + /// PWR + pub const PWR = extern struct { + /// PWR control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) + LPDS: u1, + reserved4: u3, + /// Programmable voltage detector enable + PVDE: u1, + /// Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. + PLS: u3, + /// Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. + DBP: u1, + /// Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. + FLPS: u1, + reserved14: u4, + /// System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. + SVOS: u2, + /// Peripheral voltage monitor on VDDA enable + AVDEN: u1, + /// Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. + ALS: u2, + padding: u13, }), - /// CEC error status register. - ESR: mmio.Mmio(packed struct(u32) { - /// Bit timing error. - BTE: u1, - /// Bit period error. - BPE: u1, - /// Rx block transfer finished error. - RBTFE: u1, - /// Start bit error. - SBE: u1, - /// Block acknowledge error. - ACKE: u1, - /// Line error. - LINE: u1, - /// Tx block transfer finished error. - TBTFE: u1, - padding: u25, + /// PWR control status register 1 + CSR1: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. + PVDO: u1, + reserved13: u8, + /// Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). + ACTVOSRDY: u1, + /// VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. + ACTVOS: u2, + /// Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set. + AVDO: u1, + padding: u15, }), - /// CEC control and status register. - CSR: mmio.Mmio(packed struct(u32) { - /// Tx start of message. - TSOM: u1, - /// Tx end of message. - TEOM: u1, - /// Tx error. - TERR: u1, - /// Tx byte transfer request or block transfer finished. - TBTRF: u1, - /// Rx start of message. - RSOM: u1, - /// Rx end of message. - REOM: u1, - /// Rx error. - RERR: u1, - /// Rx byte/block transfer finished. - RBTF: u1, - padding: u24, + /// This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. + CR2: mmio.Mmio(packed struct(u32) { + /// Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. + BREN: u1, + reserved4: u3, + /// VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. + MONEN: u1, + reserved16: u11, + /// Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. + BRRDY: u1, + reserved20: u3, + /// VBAT level monitoring versus low threshold + VBATL: u1, + /// VBAT level monitoring versus high threshold + VBATH: u1, + /// Temperature level monitoring versus low threshold + TEMPL: u1, + /// Temperature level monitoring versus high threshold + TEMPH: u1, + padding: u8, }), - /// CEC Tx data register. - TXD: mmio.Mmio(packed struct(u32) { - /// Tx Data register. - TXD: u8, - padding: u24, + /// Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value. + CR3: mmio.Mmio(packed struct(u32) { + /// Power management unit bypass + BYPASS: u1, + /// Low drop-out regulator enable + LDOEN: u1, + /// SD converter Enable + SDEN: u1, + /// Step-down converter forced ON and in High Power MR mode + SDEXTHP: u1, + /// Step-down converter voltage output level selection + SDLEVEL: packed union { + raw: u2, + value: SDLEVEL, + }, + reserved8: u2, + /// VBAT charging enable + VBE: u1, + /// VBAT charging resistor selection + VBRS: u1, + reserved16: u6, + /// SMPS step-down converter external supply ready + SDEXTRDY: u1, + reserved24: u7, + /// VDD33USB voltage level detector enable. + USB33DEN: u1, + /// USB regulator enable. + USBREGEN: u1, + /// USB supply ready. + USB33RDY: u1, + padding: u5, }), - /// CEC Rx data register. - RXD: mmio.Mmio(packed struct(u32) { - /// Rx data. - RXD: u8, - padding: u24, + /// This register allows controlling CPU1 power. + CPUCR: mmio.Mmio(packed struct(u32) { + /// D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. + PDDS_D1: u1, + /// D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. + PDDS_D2: u1, + /// System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. + PDDS_D3: u1, + reserved5: u2, + /// STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. + STOPF: u1, + /// System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit + SBF: u1, + /// D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. + SBF_D1: u1, + /// D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. + SBF_D2: u1, + /// Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. + CSSF: u1, + reserved11: u1, + /// Keep system D3 domain in Run mode regardless of the CPU sub-systems modes + RUN_D3: u1, + padding: u20, }), - }; - }; - - pub const dbgmcu_f2 = struct { - /// Debug support - pub const DBGMCU = extern struct { - /// IDCODE - IDCODE: mmio.Mmio(packed struct(u32) { - /// DEV_ID - DEV_ID: u12, - reserved16: u4, - /// REV_ID - REV_ID: u16, + reserved24: [4]u8, + /// This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + D3CR: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). + VOSRDY: u1, + /// Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling. + VOS: packed union { + raw: u2, + value: VOS, + }, + padding: u16, }), - /// Control Register - CR: mmio.Mmio(packed struct(u32) { - /// DBG_SLEEP - DBG_SLEEP: u1, - /// DBG_STOP - DBG_STOP: u1, - /// DBG_STANDBY - DBG_STANDBY: u1, - reserved5: u2, - /// TRACE_IOEN - TRACE_IOEN: u1, - /// TRACE_MODE - TRACE_MODE: u2, - padding: u24, + reserved32: [4]u8, + /// reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). + WKUPCR: mmio.Mmio(packed struct(u32) { + /// Clear Wakeup pin flag for WKUP. These bits are always read as 0. + WKUPC: u6, + padding: u26, }), - /// Debug MCU APB1 Freeze registe - APB1_FZ: mmio.Mmio(packed struct(u32) { - /// TIM2 - TIM2: u1, - /// TIM3 - TIM3: u1, - /// TIM4 - TIM4: u1, - /// TIM5 - TIM5: u1, - /// TIM6 - TIM6: u1, - /// TIM7 - TIM7: u1, - /// TIM12 - TIM12: u1, - /// TIM13 - TIM13: u1, - /// TIM14 - TIM14: u1, - reserved10: u1, - /// RTC - RTC: u1, - /// WWDG - WWDG: u1, - /// IWDEG - IWDG: u1, - reserved21: u8, - /// I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT: u1, - /// I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT: u1, - /// I2C3_SMBUS_TIMEOUT - I2C3_SMBUS_TIMEOUT: u1, - reserved25: u1, - /// CAN1 - CAN1: u1, - /// CAN2 - CAN2: u1, - padding: u5, + /// reset only by system reset, not reset by wakeup from Standby mode + WKUPFR: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + WKUPF: u1, + padding: u31, }), - /// Debug MCU APB2 Freeze registe - APB2_FZ: mmio.Mmio(packed struct(u32) { - /// TIM1 counter stopped when core is halted - TIM1: u1, - /// TIM8 counter stopped when core is halted - TIM8: u1, - reserved16: u14, - /// TIM9 counter stopped when core is halted - TIM9: u1, - /// TIM10 counter stopped when core is halted - TIM10: u1, - /// TIM11 counter stopped when core is halted - TIM11: u1, - padding: u13, + /// Reset only by system reset, not reset by wakeup from Standby mode + WKUPEPR: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + WKUPEN: u1, + reserved8: u7, + /// Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + WKUPP: u1, + reserved16: u7, + /// Wakeup pin pull configuration + WKUPPUPD: packed union { + raw: u2, + value: WKUPPUPD, + }, + padding: u14, }), }; }; - pub const rcc_l4plus = struct { - pub const ADCSEL = enum(u2) { - /// No clock selected - DISABLE = 0x0, - /// PLLADC1CLK clock selected - PLLSAI1_R = 0x1, - /// SYSCLK clock selected - SYS = 0x3, - _, - }; - - pub const ADFSDMSEL = enum(u2) { - /// SAI1clock selected as DFSDM audio clock - PLLSAI1_P = 0x0, - /// HSI clock selected as DFSDM audio clock - HSI = 0x1, - /// MSI clock selected as DFSDM audio clock - MSI = 0x2, - _, - }; - - pub const CLK48SEL = enum(u2) { - /// HSI48 clock selected - HSI48 = 0x0, - /// PLLSAI1_Q aka PLL48M1CLK clock selected - PLLSAI1_Q = 0x1, - /// PLL_Q aka PLL48M2CLK clock selected - PLL1_Q = 0x2, - /// MSI clock selected - MSI = 0x3, - }; - - pub const DFSDMSEL = enum(u1) { - /// APB2 clock (PCLK2) selected as DFSDM kernel clock - PCLK2 = 0x0, - /// System clock selected as DFSDM kernel clock - SYS = 0x1, + pub const pwr_h7rs = struct { + pub const ALS = enum(u2) { + /// AVD level 1. + Level1 = 0x0, + /// AVD level 2. + Level2 = 0x1, + /// AVD level 3. + Level3 = 0x2, + /// AVD level 4. + Level4 = 0x3, }; - pub const DSISEL = enum(u1) { - /// DSI-PHY is selected as DSI byte lane clock source (usual case) - DSI_PHY = 0x0, - /// PLLDSICLK is selected as DSI byte lane clock source, used in case DSI PLL and DSIPHY are off (low-power mode) - PLLSAI2_Q = 0x1, + pub const AVDO = enum(u1) { + /// VDDA is equal or higher than the AVD threshold selected with the ALS[1:0] bits. + AboveOrEqual = 0x0, + /// VDDA is lower than the AVD threshold selected with the ALS[1:0] bits. + Below = 0x1, }; - pub const HPRE = enum(u4) { - /// system clock not divided - Div1 = 0x0, - /// system clock divided by 2 - Div2 = 0x8, - /// system clock divided by 4 - Div4 = 0x9, - /// system clock divided by 8 - Div8 = 0xa, - /// system clock divided by 16 - Div16 = 0xb, - /// system clock divided by 64 - Div64 = 0xc, - /// system clock divided by 128 - Div128 = 0xd, - /// system clock divided by 256 - Div256 = 0xe, - /// system clock divided by 512 - Div512 = 0xf, - _, + pub const PDDS = enum(u1) { + /// Stop mode when device enters Deepsleep. + Stop = 0x0, + /// Standby mode when device enters Deepsleep. + Standby = 0x1, }; - pub const I2C1SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - _, + pub const PLS = enum(u3) { + /// PVD level 1. + Level1 = 0x0, + /// PVD level 2. + Level2 = 0x1, + /// PVD level 3. + Level3 = 0x2, + /// PVD level 4. + Level4 = 0x3, + /// PVD level 5. + Level5 = 0x4, + /// PVD level 6. + Level6 = 0x5, + /// PVD level 7. + Level7 = 0x6, + /// External voltage level on PVD_IN pin, compared to internal VREFINT level. + External = 0x7, }; - pub const I2C2SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - _, + pub const PVDO = enum(u1) { + /// VDD or PVD_IN voltage is equal or higher than the PVD threshold selected through the. + AboveOrEqual = 0x0, + /// VDD or PVD_IN voltage is lower than the PVD threshold selected through the PLS[2:0]. + Below = 0x1, }; - pub const I2C3SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - _, + pub const RLPSN = enum(u1) { + /// RAM enters to low power mode when system enters to STOP. + LowPower = 0x0, + /// RAM remains in normal mode when system enters to STOP. + Normal = 0x1, }; - pub const I2C4SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - _, + pub const SDLEVEL = enum(u1) { + Reset = 0x0, + V1_8 = 0x1, }; - pub const LPTIM1SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// LSI clock selected - LSI = 0x1, - /// HSI clock selected - HSI = 0x2, - /// LSE clock selected - LSE = 0x3, + pub const SVOS = enum(u1) { + /// SVOS Low. + Low = 0x0, + /// SVOS High (default). + High = 0x1, }; - pub const LPTIM2SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// LSI clock selected - LSI = 0x1, - /// HSI clock selected - HSI = 0x2, - /// LSE clock selected - LSE = 0x3, + pub const SYNC_ADC = enum(u1) { + /// SD_Converter clock free running. + FreeRunning = 0x0, + /// SD_Converter clock synchronised to ADC. + Synchronized = 0x1, }; - pub const LPUART1SEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - /// LSE clock selected - LSE = 0x3, + pub const UNLOCKED = enum(u1) { + /// accessed locked: key was not written and after each register write access. + Locked = 0x0, + /// after key 0xCAFECAFE was written in this register. + Unlocked = 0x1, }; - pub const LSCOSEL = enum(u1) { - /// LSI clock selected - LSI = 0x0, - /// LSE clock selected - LSE = 0x1, + pub const VBRS = enum(u1) { + /// Charge VBAT through a 5 k resistor. + Ohm5k = 0x0, + /// Charge VBAT through a 1.5 k resistor. + Ohm1_5k = 0x1, }; - pub const LSEDRV = enum(u2) { - /// Low driving capability + pub const VOS = enum(u1) { + /// VOS Low level (default). Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCOPRE = enum(u3) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x1, - /// Division by 4 - Div4 = 0x2, - /// Division by 8 - Div8 = 0x3, - /// Division by 16 - Div16 = 0x4, - _, - }; - - pub const MCOSEL = enum(u4) { - /// No clock - DISABLE = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// MSI oscillator clock selected - MSI = 0x2, - /// HSI oscillator clock selected - HSI = 0x3, - /// HSE oscillator clock selected - HSE = 0x4, - /// PLL clock selected - PLL = 0x5, - /// LSI oscillator clock selected - LSI = 0x6, - /// LSE oscillator clock selected - LSE = 0x7, - /// HSI48 oscillator clock selected - HSI48 = 0x8, - _, - }; - - pub const MSIRANGE = enum(u4) { - /// range 0 around 100 kHz - Range100K = 0x0, - /// range 1 around 200 kHz - Range200K = 0x1, - /// range 2 around 400 kHz - Range400K = 0x2, - /// range 3 around 800 kHz - Range800K = 0x3, - /// range 4 around 1 MHz - Range1M = 0x4, - /// range 5 around 2 MHz - Range2M = 0x5, - /// range 6 around 4 MHz - Range4M = 0x6, - /// range 7 around 8 MHz - Range8M = 0x7, - /// range 8 around 16 MHz - Range16M = 0x8, - /// range 9 around 24 MHz - Range24M = 0x9, - /// range 10 around 32 MHz - Range32M = 0xa, - /// range 11 around 48 MHz - Range48M = 0xb, - _, + /// VOS High level. + High = 0x1, }; - pub const MSIRGSEL = enum(u1) { - /// MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register - CSR = 0x0, - /// MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register - CR = 0x1, + pub const WKUPP = enum(u1) { + /// Detection on high level (rising edge). + High = 0x0, + /// Detection on low level (falling edge). + Low = 0x1, }; - pub const OCTOSPISEL = enum(u2) { - /// System clock selected as OctoSPI kernel clock - SYS = 0x0, - /// MSI clock selected as OctoSPI kernel clock - MSI = 0x1, - /// PLL48M1CLK clock selected as OctoSPI kernel clock - PLL1_Q = 0x2, + pub const WKUPPUPD = enum(u2) { + /// No pull-up. + NoPull = 0x0, + /// Pull-up. + PullUp = 0x1, + /// Pull-down. + PullDown = 0x2, _, }; - pub const PLLM = enum(u4) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, + pub const XSPICAP = enum(u2) { + /// XSPI Capacitor OFF (default) note: to confirm with analog design. + Disabled = 0x0, + /// XSPI Capacitor set to 1/3. + OneThird = 0x1, + /// XSPI Capacitor set to 2/3. + TwoThirds = 0x2, + /// XSPI Capacitor set to full capacitance. + Full = 0x3, }; - pub const PLLN = enum(u7) { - Mul8 = 0x8, - Mul9 = 0x9, - Mul10 = 0xa, - Mul11 = 0xb, - Mul12 = 0xc, - Mul13 = 0xd, - Mul14 = 0xe, - Mul15 = 0xf, - Mul16 = 0x10, - Mul17 = 0x11, - Mul18 = 0x12, - Mul19 = 0x13, - Mul20 = 0x14, - Mul21 = 0x15, - Mul22 = 0x16, - Mul23 = 0x17, - Mul24 = 0x18, - Mul25 = 0x19, - Mul26 = 0x1a, - Mul27 = 0x1b, - Mul28 = 0x1c, - Mul29 = 0x1d, - Mul30 = 0x1e, - Mul31 = 0x1f, - Mul32 = 0x20, - Mul33 = 0x21, - Mul34 = 0x22, - Mul35 = 0x23, - Mul36 = 0x24, - Mul37 = 0x25, - Mul38 = 0x26, - Mul39 = 0x27, - Mul40 = 0x28, - Mul41 = 0x29, - Mul42 = 0x2a, - Mul43 = 0x2b, - Mul44 = 0x2c, - Mul45 = 0x2d, - Mul46 = 0x2e, - Mul47 = 0x2f, - Mul48 = 0x30, - Mul49 = 0x31, - Mul50 = 0x32, - Mul51 = 0x33, - Mul52 = 0x34, - Mul53 = 0x35, - Mul54 = 0x36, - Mul55 = 0x37, - Mul56 = 0x38, - Mul57 = 0x39, - Mul58 = 0x3a, - Mul59 = 0x3b, - Mul60 = 0x3c, - Mul61 = 0x3d, - Mul62 = 0x3e, - Mul63 = 0x3f, - Mul64 = 0x40, - Mul65 = 0x41, - Mul66 = 0x42, - Mul67 = 0x43, - Mul68 = 0x44, - Mul69 = 0x45, - Mul70 = 0x46, - Mul71 = 0x47, - Mul72 = 0x48, - Mul73 = 0x49, - Mul74 = 0x4a, - Mul75 = 0x4b, - Mul76 = 0x4c, - Mul77 = 0x4d, - Mul78 = 0x4e, - Mul79 = 0x4f, - Mul80 = 0x50, - Mul81 = 0x51, - Mul82 = 0x52, - Mul83 = 0x53, - Mul84 = 0x54, - Mul85 = 0x55, - Mul86 = 0x56, - Mul87 = 0x57, - Mul88 = 0x58, - Mul89 = 0x59, - Mul90 = 0x5a, - Mul91 = 0x5b, - Mul92 = 0x5c, - Mul93 = 0x5d, - Mul94 = 0x5e, - Mul95 = 0x5f, - Mul96 = 0x60, - Mul97 = 0x61, - Mul98 = 0x62, - Mul99 = 0x63, - Mul100 = 0x64, - Mul101 = 0x65, - Mul102 = 0x66, - Mul103 = 0x67, - Mul104 = 0x68, - Mul105 = 0x69, - Mul106 = 0x6a, - Mul107 = 0x6b, - Mul108 = 0x6c, - Mul109 = 0x6d, - Mul110 = 0x6e, - Mul111 = 0x6f, - Mul112 = 0x70, - Mul113 = 0x71, - Mul114 = 0x72, - Mul115 = 0x73, - Mul116 = 0x74, - Mul117 = 0x75, - Mul118 = 0x76, - Mul119 = 0x77, - Mul120 = 0x78, - Mul121 = 0x79, - Mul122 = 0x7a, - Mul123 = 0x7b, - Mul124 = 0x7c, - Mul125 = 0x7d, - Mul126 = 0x7e, - Mul127 = 0x7f, - _, - }; - - pub const PLLP = enum(u5) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - Div16 = 0x10, - Div17 = 0x11, - Div18 = 0x12, - Div19 = 0x13, - Div20 = 0x14, - Div21 = 0x15, - Div22 = 0x16, - Div23 = 0x17, - Div24 = 0x18, - Div25 = 0x19, - Div26 = 0x1a, - Div27 = 0x1b, - Div28 = 0x1c, - Div29 = 0x1d, - Div30 = 0x1e, - Div31 = 0x1f, - _, - }; - - pub const PLLPBIT = enum(u1) { - Div7 = 0x0, - Div17 = 0x1, - }; - - pub const PLLQ = enum(u2) { - Div2 = 0x0, - Div4 = 0x1, - Div6 = 0x2, - Div8 = 0x3, - }; - - pub const PLLR = enum(u2) { - Div2 = 0x0, - Div4 = 0x1, - Div6 = 0x2, - Div8 = 0x3, - }; - - pub const PLLSRC = enum(u2) { - /// No clock sent to PLL - DISABLE = 0x0, - /// MSI selected as PLL input clock - MSI = 0x1, - /// HSI selected as PLL input clock - HSI = 0x2, - /// HSE selected as PLL input clock - HSE = 0x3, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const RTCSEL = enum(u2) { - /// No clock - Disable = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by 32 used as the RTC clock - HSE = 0x3, - }; - - pub const SAI1SEL = enum(u3) { - /// PLLSAI1CLK clock is selected as SAIx clock - PLLSAI1_P = 0x0, - /// PLLSAI2CLK clock is selected as SAIx clock - PLLSAI2_P = 0x1, - /// PLLSAI3CLK clock is selected as SAIx clock - PLL1_P = 0x2, - /// External clock SAIx_EXTCLK clock selected as SAIx clock - SAI1_EXTCLK = 0x3, - /// HSI clock selected as SAIx clock - HSI = 0x4, - _, - }; - - pub const SAI2SEL = enum(u3) { - /// PLLSAI1CLK clock is selected as SAIx clock - PLLSAI1_P = 0x0, - /// PLLSAI2CLK clock is selected as SAIx clock - PLLSAI2_P = 0x1, - /// PLLSAI3CLK clock is selected as SAIx clock - PLL1_P = 0x2, - /// External clock SAIx_EXTCLK clock selected as SAIx clock - SAI2_EXTCLK = 0x3, - /// HSI clock selected as SAIx clock - HSI = 0x4, - _, - }; - - pub const SDMMCSEL = enum(u1) { - /// 48 MHz clock is selected as SDMMC kernel clock - HSI48 = 0x0, - /// PLLSAI3CLK is selected as SDMMC kernel clock, used in case higher frequency than 48MHz is needed (for SDR50 mode) - PLL1_P = 0x1, - }; - - pub const STOPWUCK = enum(u1) { - /// MSI oscillator selected as wake-up from Stop clock - MSI = 0x0, - /// HSI oscillator selected as wake-up from Stop clock - HSI = 0x1, - }; - - pub const SW = enum(u2) { - /// MSI selected as system clock - MSI = 0x0, - /// HSI selected as system clock - HSI = 0x1, - /// HSE selected as system clock - HSE = 0x2, - /// PLL selected as system clock - PLL1_R = 0x3, - }; - - pub const USART1SEL = enum(u2) { - /// PCLK clock selected - PCLK2 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - /// LSE clock selected - LSE = 0x3, - }; - - pub const USARTSEL = enum(u2) { - /// PCLK clock selected - PCLK1 = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI clock selected - HSI = 0x2, - /// LSE clock selected - LSE = 0x3, - }; - - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// MSI clock enable - MSION: u1, - /// MSI clock ready flag - MSIRDY: u1, - /// MSI clock PLL enable - MSIPLLEN: u1, - /// MSI clock range selection - MSIRGSEL: packed union { + /// Power control. + pub const PWR = extern struct { + /// PWR control register 1. + CR1: mmio.Mmio(packed struct(u32) { + /// System Stop mode voltage scaling selection. + SVOS: packed union { raw: u1, - value: MSIRGSEL, + value: SVOS, }, - /// MSI clock ranges - MSIRANGE: packed union { - raw: u4, - value: MSIRANGE, + reserved4: u3, + /// Programmable voltage detector enable. + PVDE: u1, + /// Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. + PLS: packed union { + raw: u3, + value: PLS, }, - /// HSI clock enable - HSION: u1, - /// HSI always enable for peripheral kernels - HSIKERON: u1, - /// HSI clock ready flag - HSIRDY: u1, - /// HSI automatic start from Stop - HSIASFS: u1, - reserved16: u4, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE crystal oscillator bypass - HSEBYP: u1, - /// Clock security system enable - CSSON: u1, - reserved24: u4, - /// Main PLL enable - PLLON: u1, - /// Main PLL clock ready flag - PLLRDY: u1, - /// SAI1 PLL enable - PLLSAI1ON: u1, - /// SAI1 PLL clock ready flag - PLLSAI1RDY: u1, - /// SAI2 PLL enable - PLLSAI2ON: u1, - /// SAI2 PLL clock ready flag - PLLSAI2RDY: u1, - padding: u2, - }), - /// Internal clock sources calibration register - ICSCR: mmio.Mmio(packed struct(u32) { - /// MSI clock calibration - MSICAL: u8, - /// MSI clock trimming - MSITRIM: u8, - /// HSI clock calibration - HSICAL: u8, - /// HSI clock trimming - HSITRIM: u7, - padding: u1, - }), - /// Clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u2, - value: SW, + /// Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in the PWR_CSR1 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. + DBP: u1, + /// Flash low-power mode in Stop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when device is in Stop mode. consumption). + FLPS: u1, + /// RAM low power mode disable in STOP. When set the RAMs will not enter to low power mode when the system enters to STOP. + RLPSN: packed union { + raw: u1, + value: RLPSN, }, - /// System clock switch status - SWS: packed union { + /// analog switch VBoost control This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits. + BOOSTE: u1, + /// analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected VDDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_CSR1 register) after setting the AVDEN bit and selecting the supply level to be monitored (ALS bits). + AVDREADY: u1, + /// Peripheral voltage monitor on VDDA enable. + AVDEN: u1, + /// Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. + ALS: packed union { raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, + value: ALS, }, - /// APB low-speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, + padding: u16, + }), + /// PWR control status register 1. + SR1: mmio.Mmio(packed struct(u32) { + /// VOS currently applied for VCORE voltage scaling selection. These bit reflect the last VOS value applied to the PMU. + ACTVOS: u1, + /// Voltage levels ready bit for currently used ACTVOS and SDHILEVEL This bit is set to 1 by hardware when the voltage regulator and the SMPS step-down converter are both disabled and Bypass mode is selected in PWR control register 2 (PWR_CSR2). + ACTVOSRDY: u1, + reserved4: u2, + /// Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. PLS[2:0] bits. bits. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. + PVDO: packed union { + raw: u1, + value: PVDO, }, - /// APB high-speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, + reserved13: u8, + /// Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set. + AVDO: packed union { + raw: u1, + value: AVDO, }, - reserved15: u1, - /// Wakeup from Stop and CSS backup clock selection - STOPWUCK: packed union { + padding: u18, + }), + /// PWR control status register 1. + CSR1: mmio.Mmio(packed struct(u32) { + /// Backup regulator enable When set, the backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. + BREN: u1, + reserved4: u3, + /// VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. Note: VBAT and temperature monitoring are only available when the backup regulator is enabled (BREN bit set to 1). + MONEN: u1, + reserved16: u11, + /// Backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready. + BRRDY: u1, + reserved20: u3, + /// VBAT level monitoring versus low threshold. + VBATL: u1, + /// VBAT level monitoring versus high threshold. + VBATH: u1, + /// Temperature level monitoring versus low threshold. + TEMPL: u1, + /// Temperature level monitoring versus high threshold. + TEMPH: u1, + padding: u8, + }), + /// PWR control register 2. + CSR2: mmio.Mmio(packed struct(u32) { + /// Power management unit bypass Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41. + BYPASS: u1, + /// Low drop-out regulator enable Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41. + LDOEN: u1, + /// SMPS step-down converter enable Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41. + SDEN: u1, + /// SMPS external power delivery selection Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41. + SDEXTHP: u1, + /// SMPS step-down converter voltage output for LDO or external supply This bit is used when both the LDO and SMPS step-down converter are enabled with SDEN and LDOEN enabled or when SMPSEXTHP is enabled. In this case SDHILEVEL has to be set to 1 to confirm the regulator settings. + SDLEVEL: packed union { raw: u1, - value: STOPWUCK, + value: SDLEVEL, }, - reserved24: u8, - /// Microcontroller clock output selection - MCOSEL: packed union { - raw: u4, - value: MCOSEL, + reserved8: u3, + /// VBAT charging enable. + VBE: u1, + /// VBAT charging resistor selection. + VBRS: packed union { + raw: u1, + value: VBRS, }, - /// Microcontroller clock output prescaler - MCOPRE: packed union { - raw: u3, - value: MCOPRE, + /// XSPI port 1 capacitor control bits see the product datasheet for more details. + XSPICAP1: packed union { + raw: u2, + value: XSPICAP, }, - padding: u1, - }), - /// PLL configuration register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// Main PLL, PLLSAI1 and PLLSAI2 entry clock source - PLLSRC: packed union { + /// XSPI port 2 capacitor control bits see the product datasheet for more details. + XSPICAP2: packed union { raw: u2, - value: PLLSRC, + value: XSPICAP, }, - reserved4: u2, - /// Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock - PLLM: packed union { - raw: u4, - value: PLLM, + /// EN_XSPIM1: this bit allow the SW to enable the XSPI interface. The XSPIM_P1 supply must be stable prior to setting this bit. + EN_XSPIM1: u1, + /// EN_XSPIM2: this bit allows the SW to enable the XSPI interface, when available. The XSPIM_P2 supply must be stable prior to setting this bit. It should also be set when FMC is used. + EN_XSPIM2: u1, + /// SMPS step-down converter external supply ready This bit is set by hardware to indicate that the external supply from the SMPS step-down converter is ready. + SDEXTRDY: u1, + reserved24: u7, + /// VDD33_USB voltage level detector enable. + USB33DEN: u1, + /// USB regulator enable. + USBREGEN: u1, + /// USB supply ready. + USB33RDY: u1, + /// USB HS regulator enable. + USBHSREGEN: u1, + padding: u4, + }), + /// PWR CPU control register 3. + CSR3: mmio.Mmio(packed struct(u32) { + /// Power Down Deepsleep. This bit allows CPU to define the Deepsleep mode. + PDDS: packed union { + raw: u1, + value: PDDS, }, - /// Main PLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, + /// Clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware. + CSSF: u1, + reserved8: u6, + /// STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU CSSF bit. + STOPF: u1, + /// System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU CSSF bit. + SBF: u1, + padding: u22, + }), + /// PWR control status register 4. + CSR4: mmio.Mmio(packed struct(u32) { + /// Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling must be changed before increasing the system frequency. When decreasing performance, the system frequency must first be decreased before changing the voltage scaling. Note: Refer to Section Electrical characteristics of the product datasheet for more details. + VOS: packed union { + raw: u1, + value: VOS, }, - reserved16: u1, - /// Main PLL PLLSAI3CLK output enable - PLLPEN: u1, - /// Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) - PLLPBIT: packed union { + /// VOS Ready bit. + VOSRDY: u1, + padding: u30, + }), + reserved32: [8]u8, + /// PWR wakeup clear register. + WKUPCR: mmio.Mmio(packed struct(u32) { + /// Clear Wakeup pin flag for WKUP1 These bits are always read as 0. + WKUPC: u1, + padding: u31, + }), + /// PWR wakeup flag register. + WKUPFR: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC1 bit in the PWR wakeup clear register (PWR_WKUPCR). + WKUPF: u1, + padding: u31, + }), + /// PWR wakeup enable and polarity register. + WKUPEPR: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge. + WKUPEN: u1, + reserved8: u7, + /// Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin. + WKUPP: packed union { raw: u1, - value: PLLPBIT, + value: WKUPP, }, - reserved20: u2, - /// Main PLL PLLUSB1CLK output enable - PLLQEN: u1, - /// Main PLL division factor for PLLUSB1CLK(48 MHz clock) - PLLQ: packed union { + reserved16: u7, + /// Wakeup pin pull configuration + WKUPPUPD: packed union { raw: u2, - value: PLLQ, + value: WKUPPUPD, }, - reserved24: u1, - /// Main PLL PLLCLK output enable - PLLREN: u1, - /// Main PLL division factor for PLLCLK (system clock) - PLLR: packed union { - raw: u2, - value: PLLR, + padding: u14, + }), + /// PWR USB Type-C and Power Delivery register. + UCPDR: mmio.Mmio(packed struct(u32) { + /// UCPD dead battery disable. + UCPD_DBDIS: u1, + /// UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers. + UCPD_STBY: u1, + padding: u30, + }), + /// PWR apply pull configuration register. + APCR: mmio.Mmio(packed struct(u32) { + /// Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx, PDCRx registers are applied in Standby mode even after wakeup until APC bit is reset to 0. When this bit is cleared, the I/O pull-up or pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx and PDCRx registers are not applied in Standby mode and IO becomes Hi-Z. + APC: u1, + reserved16: u15, + /// Port N bit 7 pull-up/down configuration When this bit is set, a weak pull-up or pull-down resistor is applied on PN7 following inverse logic applied on PN6. If the PUN6 bit in PWR_PUCRN register is set and APC bit is set the week pull-down is applied on PN7. If the PDN6 bit in PWR_PDCRN register is set and APC bit is set the week pull-up is applied on PN7. + PN7_PUPD: u1, + /// Port O bit 5 pull-up/down configuration When this bit is set, a weak pull-up or pull down resistor is applied on PO5 following inverse logic applied on PO4. If the PUO4 bit in PWR_PUCRO register is set and APC bit is set the week pull-down is applied on PO5. If the PDO4 bit in PWR_PDCRO register is set and APC bit is set the week pull-up is applied on PO5.. + PO5_PUPD: u1, + reserved28: u10, + /// Port PB6 I3C pull-up bit When I3C is used on PB6, when set, this bit activates the pull-up on I3C1_SCL (PB6) in standby mode. + I3CPB6_PU: u1, + /// Port PB7 I3C pull-up bit When I3C is used on PB7, when set, this bit activates the pull-up on I3C1_SDA (PB7) in standby mode. + I3CPB7_PU: u1, + /// Port PB8 I3C pull-up bit When I3C is used on PB8, when set, this bit activates the pull-up on I3C1_SCL (PB8) in standby mode. + I3CPB8_PU: u1, + /// Port PB9 I3C pull-up bit When I3C is used on PB9, when set, this bit activates the pull-up on I3C1_SDA (PB9) in standby mode. + I3CPB9_PU: u1, + }), + /// PWR port N pull-up control register. + PUCRN: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Port N pull-up bit 1 When set, each bit activates the pull-up on PN1 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD1 bit is also set. + PUN1: u1, + reserved6: u4, + /// Port N pull-up bit 6 When set activates the pull-up on PN6 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PDN6 bit is also set. + PUN6: u1, + reserved12: u5, + /// Port N pull-up bit 12 When set, each bit activates the pull-up on PN12 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD12 bit is also set. + PUN12: u1, + padding: u19, + }), + /// PWR port N pull-down control register. + PDCRN: mmio.Mmio(packed struct(u32) { + /// Port N pull-down bit 0 When set activates the pull-down on PN0 when the APC bit is set in PWR_APCR. + PDN0: u1, + /// Port N pull-down bit 1 When set activates the pull-down on PN1 when the APC bit is set in PWR_APCR. + PDN1: u1, + /// Port N PN2 to PN5 pull-down activation When set, four pull-down resistors are activated on PN2 to PN5 when the APC bit is set in PWR_APCR. + PDN2N5: u1, + reserved6: u3, + /// Port N pull-down bit 6 When set activates the pull-down on PN6 when the APC bit is set in PWR_APCR. + PDN6: u1, + reserved8: u1, + /// Port N - PN8 to PN11 pull-down activation When set, four pull-down resistors are activated on PN8 to PN11 when the APC bit is set in PWR_APCR. + PDN8N11: u1, + reserved12: u3, + /// Port N pull-down bit 12 When set activates the pull-down on PN12 when the APC bit is set in PWR_APCR. + PDN12: u1, + padding: u19, + }), + /// PWR port O pull-up control register. + PUCRO: mmio.Mmio(packed struct(u32) { + /// (n = 1 to 0) Port O pull-up bits When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set. + PUO0: u1, + /// (n = 1 to 0) Port O pull-up bits When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set. + PUO1: u1, + reserved4: u2, + /// Port O pull-up bit 4 When set activates the pull-up on PO4 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits PDO4 in PWR_PDCRO is also set. + PUO4: u1, + padding: u27, + }), + /// PWR port O pull-down control register. + PDCRO: mmio.Mmio(packed struct(u32) { + /// Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. + PDO0: u1, + /// Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. + PDO1: u1, + /// Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. + PDO2: u1, + /// Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. + PDO3: u1, + /// Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. + PDO4: u1, + padding: u27, + }), + /// PWR port P pull-down control register. + PDCRP: mmio.Mmio(packed struct(u32) { + /// Port P0-P3 pull-down activation When set, four pull-down resistors are activated on P0 to P3 when the APC bit is set in PWR_APCR. + PDP0P3: u1, + reserved4: u3, + /// Port P4-P7 pull-down activation When set, four pull-down resitors are activated on P4 to P7 when the APC bit is set in PWR_APCR. + PDP4P7: u1, + reserved8: u3, + /// Port P8-P11 pull-down activation When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR. + PDP8P11: u1, + reserved12: u3, + /// Port P12-P15 pull-down activation When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR. + PDP12P15: u1, + padding: u19, + }), + reserved80: [8]u8, + /// PWR debug register 1. + PDR1: mmio.Mmio(packed struct(u32) { + /// Debug Register Unlocked. + UNLOCKED: packed union { + raw: u1, + value: UNLOCKED, }, - /// Main PLL division factor for PLLSAI2CLK - PLLP: packed union { - raw: u5, - value: PLLP, + reserved3: u2, + /// Step down converter force PWM mode. + SDFPWMEN: u1, + reserved16: u12, + /// (Non-User bit). + SYNC_ADC: packed union { + raw: u1, + value: SYNC_ADC, }, + padding: u15, }), - /// PLLSAI1 configuration register - PLLSAI1CFGR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Division factor for PLLSAI input clock - PLLM: packed union { - raw: u4, - value: PLLM, - }, - /// SAI1PLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, + }; + }; + + pub const pwr_l0 = struct { + pub const DS_EE_KOFF = enum(u1) { + /// NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set + NVMWakeUp = 0x0, + /// NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set) + NVMSleep = 0x1, + }; + + pub const MODE = enum(u1) { + /// Voltage regulator in Main mode + MAIN_MODE = 0x0, + /// Voltage regulator switches to low-power mode + LOW_POWER_MODE = 0x1, + }; + + pub const PDDS = enum(u1) { + /// Enter Stop mode when the CPU enters deepsleep + STOP_MODE = 0x0, + /// Enter Standby mode when the CPU enters deepsleep + STANDBY_MODE = 0x1, + }; + + pub const PLS = enum(u3) { + /// 1.9 V + V1_9 = 0x0, + /// 2.1 V + V2_1 = 0x1, + /// 2.3 V + V2_3 = 0x2, + /// 2.5 V + V2_5 = 0x3, + /// 2.7 V + V2_7 = 0x4, + /// 2.9 V + V2_9 = 0x5, + /// 3.1 V + V3_1 = 0x6, + /// External input analog voltage (Compare internally to VREFINT) + External = 0x7, + }; + + pub const VOS = enum(u2) { + /// 1.8 V (range 1) + Range1 = 0x1, + /// 1.5 V (range 2) + Range2 = 0x2, + /// 1.2 V (range 3) + Range3 = 0x3, + _, + }; + + /// Power control + pub const PWR = extern struct { + /// power control register + CR: mmio.Mmio(packed struct(u32) { + /// Low-power deepsleep/Sleep/Low-power run + LPSDSR: packed union { + raw: u1, + value: MODE, }, - reserved16: u1, - /// SAI1PLL PLLSAICLK output enable - PLLPEN: u1, - /// SAI1PLL division factor for PLLSAICLK - PLLPBIT: packed union { + /// Power down deepsleep + PDDS: packed union { raw: u1, - value: PLLPBIT, + value: PDDS, }, - reserved20: u2, - /// SAI1PLL PLLUSB2CLK output enable - PLLQEN: u1, - /// SAI1PLL division factor for PLLUSB2CLK - PLLQ: packed union { - raw: u2, - value: PLLQ, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector enable + PVDE: u1, + /// PVD level selection + PLS: packed union { + raw: u3, + value: PLS, }, - reserved24: u1, - /// PLLSAI PLLADC1CLK output enable - PLLREN: u1, - /// PLLSAI division factor for PLLADC1CLK - PLLR: packed union { + /// Disable backup domain write protection + DBP: u1, + /// Ultra-low-power mode + ULP: u1, + /// Fast wakeup + FWU: u1, + /// Voltage scaling range selection + VOS: packed union { raw: u2, - value: PLLR, - }, - /// PLLSAI division factor for PLLSAICLK - PLLP: packed union { - raw: u5, - value: PLLP, + value: VOS, }, - }), - /// PLLSAI2 configuration register - PLLSAI2CFGR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Division factor for PLLSAI input clock - PLLM: packed union { - raw: u4, - value: PLLM, + /// Deep sleep mode with Flash memory kept off + DS_EE_KOFF: packed union { + raw: u1, + value: DS_EE_KOFF, }, - /// SAI1PLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, + /// Low power run mode + LPRUN: packed union { + raw: u1, + value: MODE, }, reserved16: u1, - /// SAI1PLL PLLSAICLK output enable - PLLPEN: u1, - /// SAI1PLL division factor for PLLSAICLK - PLLPBIT: packed union { + /// Regulator in Low-power deepsleep mode + LPDS: packed union { raw: u1, - value: PLLPBIT, + value: MODE, }, - reserved20: u2, - /// SAI1PLL PLLUSB2CLK output enable - PLLQEN: u1, - /// SAI1PLL division factor for PLLUSB2CLK - PLLQ: packed union { + padding: u15, + }), + /// power control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + /// Internal voltage reference ready flag + VREFINTRDYF: u1, + /// Voltage Scaling select flag + VOSF: u1, + /// Regulator LP flag + REGLPF: u1, + reserved8: u2, + /// Enable WKUP pin 1 + EWUP1: u1, + /// Enable WKUP pin 2 + EWUP2: u1, + /// Enable WKUP pin 3 + EWUP3: u1, + padding: u21, + }), + }; + }; + + pub const pwr_l1 = struct { + pub const PDDS = enum(u1) { + /// Enter Stop mode when the CPU enters deepsleep + STOP_MODE = 0x0, + /// Enter Standby mode when the CPU enters deepsleep + STANDBY_MODE = 0x1, + }; + + pub const VOS = enum(u2) { + /// Range 1 + Range1 = 0x1, + /// Range 2 + Range2 = 0x2, + /// Range 3 + Range3 = 0x3, + _, + }; + + /// Power control + pub const PWR = extern struct { + /// power control register + CR: mmio.Mmio(packed struct(u32) { + /// Low-power deep sleep + LPSDSR: u1, + /// Power down deepsleep + PDDS: packed union { + raw: u1, + value: PDDS, + }, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write protection + DBP: u1, + /// Ultralow power mode + ULP: u1, + /// Fast wakeup + FWU: u1, + /// Voltage scaling range selection + VOS: packed union { raw: u2, - value: PLLQ, + value: VOS, }, - reserved24: u1, - /// PLLSAI PLLADC1CLK output enable - PLLREN: u1, - /// PLLSAI division factor for PLLADC1CLK - PLLR: packed union { + reserved14: u1, + /// Low power run mode + LPRUN: u1, + padding: u17, + }), + /// power control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + /// Internal voltage reference (VREFINT) ready flag + VREFINTRDYF: u1, + /// Voltage Scaling select flag + VOSF: u1, + /// Regulator LP flag + REGLPF: u1, + reserved8: u2, + /// Enable WKUP pin 1 + EWUP: u1, + padding: u23, + }), + }; + }; + + pub const pwr_l4 = struct { + pub const LPMS = enum(u3) { + /// Stop 0 mode + Stop0 = 0x0, + /// Stop 1 mode + Stop1 = 0x1, + /// Stop 2 mode + Stop2 = 0x2, + /// Standby mode + Standby = 0x3, + /// Shutdown mode + Shutdown = 0x4, + _, + }; + + pub const LPR = enum(u1) { + /// Voltage regulator in Main mode + MainMode = 0x0, + /// Voltage regulator in low-power mode + LowPowerMode = 0x1, + }; + + pub const PLS = enum(u3) { + /// 2.0V + V2_0 = 0x0, + /// 2.2V + V2_2 = 0x1, + /// 2.4V + V2_4 = 0x2, + /// 2.5V + V2_5 = 0x3, + /// 2.6V + V2_6 = 0x4, + /// 2.8V + V2_8 = 0x5, + /// 2.9V + V2_9 = 0x6, + /// External input analog voltage PVD_IN (compared internally to VREFINT) + External = 0x7, + }; + + pub const RRS = enum(u1) { + /// SRAM2 powered off in Standby mode (SRAM2 content lost) + PowerOff = 0x0, + /// SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) + OnLPR = 0x1, + }; + + pub const VOS = enum(u2) { + /// Range 1 + Range1 = 0x1, + /// Range 2 + Range2 = 0x2, + _, + }; + + /// Power control + pub const PWR = extern struct { + /// Power control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection + LPMS: packed union { + raw: u3, + value: LPMS, + }, + reserved8: u5, + /// Disable backup domain write protection + DBP: u1, + /// Voltage scaling range selection + VOS: packed union { raw: u2, - value: PLLR, + value: VOS, }, - /// PLLSAI division factor for PLLSAICLK - PLLP: packed union { - raw: u5, - value: PLLP, + reserved14: u3, + /// Low-power run + LPR: packed union { + raw: u1, + value: LPR, }, + padding: u17, }), - /// Clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - /// MSI ready interrupt enable - MSIRDYIE: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// PLL ready interrupt enable - PLLRDYIE: u1, - /// PLLSAI1 ready interrupt enable - PLLSAI1RDYIE: u1, - /// PLLSAI2 ready interrupt enable - PLLSAI2RDYIE: u1, + /// Power control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Power voltage detector enable + PVDE: u1, + /// Power voltage detector level selection + PLS: packed union { + raw: u3, + value: PLS, + }, + /// Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V + PVME1: u1, + /// Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V + PVME2: u1, + /// Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V + PVME3: u1, + /// Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V + PVME4: u1, reserved9: u1, - /// LSE clock security system interrupt enable - LSECSSIE: u1, - /// HSI48 ready interrupt enable - HSI48RDYIE: u1, - padding: u21, - }), - /// Clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// MSI ready interrupt flag - MSIRDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// PLL ready interrupt flag - PLLRDYF: u1, - /// PLLSAI1 ready interrupt flag - PLLSAI1RDYF: u1, - /// PLLSAI2 ready interrupt flag - PLLSAI2RDYF: u1, - /// Clock security system interrupt flag - CSSF: u1, - /// LSE Clock security system interrupt flag - LSECSSF: u1, - /// HSI48 ready interrupt flag - HSI48RDYF: u1, + /// VDDIO2 Independent I/Os supply valid + IOSV: u1, + /// VDDUSB USB supply valid + USV: u1, padding: u21, }), - /// Clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// MSI ready interrupt clear - MSIRDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// PLL ready interrupt clear - PLLRDYC: u1, - /// PLLSAI1 ready interrupt clear - PLLSAI1RDYC: u1, - /// PLLSAI2 ready interrupt clear - PLLSAI2RDYC: u1, - /// Clock security system interrupt clear - CSSC: u1, - /// LSE Clock security system interrupt clear - LSECSSC: u1, - /// HSI48 oscillator ready interrupt clear - HSI48RDYC: u1, - padding: u21, - }), - reserved40: [4]u8, - /// AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - /// DMAMUX1RST - DMAMUX1RST: u1, - reserved8: u5, - /// Flash memory interface reset - FLASHRST: u1, - reserved12: u3, - /// CRC reset - CRCRST: u1, - reserved16: u3, - /// Touch Sensing Controller reset - TSCRST: u1, - /// DMA2D reset - DMA2DRST: u1, - /// GFXMMU reset - GFXMMURST: u1, - padding: u13, - }), - /// AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - /// IO port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// IO port H reset - GPIOHRST: u1, - /// IO port I reset - GPIOIRST: u1, - reserved12: u3, - /// USB OTG FS reset - USB_OTG_FSRST: u1, - /// ADC reset - ADCRST: u1, - /// Digital Camera Interface reset - DCMIRST: u1, - /// PKA reset - PKARST: u1, - /// AES hardware accelerator reset - AESRST: u1, - /// Hash reset - HASHRST: u1, - /// Random number generator reset - RNGRST: u1, - reserved20: u1, - /// OCTOSPI IO manager reset - OCTOSPIMRST: u1, - reserved22: u1, - /// SDMMC1 reset - SDMMC1RST: u1, - /// SDMMC2 reset - SDMMC2RST: u1, - padding: u8, - }), - /// AHB3 peripheral reset register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller reset - FMCRST: u1, - reserved8: u7, - /// OctoSPI1 memory interface reset - OCTOSPI1RST: u1, - /// OctOSPI2 memory interface reset - OCTOSPI2RST: u1, - padding: u22, - }), - reserved56: [4]u8, - /// APB1 peripheral reset register 1 - APB1RSTR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer reset - TIM2RST: u1, - /// TIM3 timer reset - TIM3RST: u1, - /// TIM3 timer reset - TIM4RST: u1, - /// TIM5 timer reset - TIM5RST: u1, - /// TIM6 timer reset - TIM6RST: u1, - /// TIM7 timer reset - TIM7RST: u1, - reserved14: u8, - /// SPI2 reset - SPI2RST: u1, - /// SPI3 reset - SPI3RST: u1, - reserved17: u1, - /// USART2 reset - USART2RST: u1, - /// USART3 reset - USART3RST: u1, - /// UART4 reset - UART4RST: u1, - /// UART5 reset - UART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// I2C3 reset - I2C3RST: u1, - /// CRS reset - CRSRST: u1, - /// CAN1 reset - CAN1RST: u1, - reserved28: u2, - /// Power interface reset - PWRRST: u1, - /// DAC1 interface reset - DAC1RST: u1, - /// OPAMP interface reset - OPAMPRST: u1, - /// Low Power Timer 1 reset - LPTIM1RST: u1, - }), - /// APB1 peripheral reset register 2 - APB1RSTR2: mmio.Mmio(packed struct(u32) { - /// Low-power UART 1 reset - LPUART1RST: u1, - /// I2C4 reset - I2C4RST: u1, - reserved5: u3, - /// Low-power timer 2 reset - LPTIM2RST: u1, - padding: u26, - }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// System configuration (SYSCFG) reset - SYSCFGRST: u1, - reserved11: u10, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI1 reset - SPI1RST: u1, - /// TIM8 timer reset - TIM8RST: u1, - /// USART1 reset - USART1RST: u1, - reserved16: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - reserved21: u2, - /// Serial audio interface 1 (SAI1) reset - SAI1RST: u1, - /// Serial audio interface 2 (SAI2) reset - SAI2RST: u1, - reserved24: u1, - /// Digital filters for sigma-delata modulators (DFSDM) reset - DFSDM1RST: u1, - reserved26: u1, - /// LCD-TFT reset - LTDCRST: u1, - /// DSI reset - DSIRST: u1, - padding: u4, - }), - reserved72: [4]u8, - /// AHB1 peripheral clock enable register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// DMAMUX clock enable - DMAMUX1EN: u1, - reserved8: u5, - /// Flash memory interface clock enable - FLASHEN: u1, - reserved12: u3, - /// CRC clock enable - CRCEN: u1, - reserved16: u3, - /// Touch Sensing Controller clock enable - TSCEN: u1, - /// DMA2D clock enable - DMA2DEN: u1, - /// Graphic MMU clock enable - GFXMMUEN: u1, - padding: u13, - }), - /// AHB2 peripheral clock enable register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port C clock enable - GPIOCEN: u1, - /// IO port D clock enable - GPIODEN: u1, - /// IO port E clock enable - GPIOEEN: u1, - /// IO port F clock enable - GPIOFEN: u1, - /// IO port G clock enable - GPIOGEN: u1, - /// IO port H clock enable - GPIOHEN: u1, - /// IO port I clock enable - GPIOIEN: u1, - reserved12: u3, - /// OTG full speed clock enable - USB_OTG_FSEN: u1, - /// ADC clock enable - ADCEN: u1, - /// DCMI clock enable - DCMIEN: u1, - /// PKA clock enable - PKAEN: u1, - /// AES accelerator clock enable - AESEN: u1, - /// HASH clock enable - HASHEN: u1, - /// Random Number Generator clock enable - RNGEN: u1, - reserved20: u1, - /// OctoSPI IO manager clock enable - OCTOSPIMEN: u1, - reserved22: u1, - /// SDMMC1 clock enable - SDMMC1EN: u1, - /// SDMMC2 clock enable - SDMMC2EN: u1, - padding: u8, - }), - /// AHB3 peripheral clock enable register - AHB3ENR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller clock enable - FMCEN: u1, - reserved8: u7, - /// OctoSPI1 memory interface clock enable - OCTOSPI1EN: u1, - /// OSPI2EN memory interface clock enable - OCTOSPI2EN: u1, - padding: u22, - }), - reserved88: [4]u8, - /// APB1ENR1 - APB1ENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clock enable - TIM2EN: u1, - /// TIM3 timer clock enable - TIM3EN: u1, - /// TIM4 timer clock enable - TIM4EN: u1, - /// TIM5 timer clock enable - TIM5EN: u1, - /// TIM6 timer clock enable - TIM6EN: u1, - /// TIM7 timer clock enable - TIM7EN: u1, - reserved10: u4, - /// RTC APB clock enable - RTCAPBEN: u1, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI2 clock enable - SPI2EN: u1, - /// SPI3 clock enable - SPI3EN: u1, - reserved17: u1, - /// USART2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// UART5 clock enable - UART5EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - /// I2C2 clock enable - I2C2EN: u1, - /// I2C3 clock enable - I2C3EN: u1, - /// Clock Recovery System clock enable - CRSEN: u1, - /// CAN1 clock enable - CAN1EN: u1, - reserved28: u2, - /// Power interface clock enable - PWREN: u1, - /// DAC1 interface clock enable - DAC1EN: u1, - /// OPAMP interface clock enable - OPAMPEN: u1, - /// Low power timer 1 clock enable - LPTIM1EN: u1, - }), - /// APB1 peripheral clock enable register 2 - APB1ENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clock enable - LPUART1EN: u1, - /// I2C4 clock enable - I2C4EN: u1, - reserved5: u3, - /// LPTIM2EN - LPTIM2EN: u1, - padding: u26, - }), - /// APB2ENR - APB2ENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved7: u6, - /// Firewall clock enable - FWEN: u1, - reserved11: u3, - /// TIM1 timer clock enable - TIM1EN: u1, - /// SPI1 clock enable - SPI1EN: u1, - /// TIM8 timer clock enable - TIM8EN: u1, - /// USART1clock enable - USART1EN: u1, - reserved16: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - reserved21: u2, - /// SAI1 clock enable - SAI1EN: u1, - /// SAI2 clock enable - SAI2EN: u1, - reserved24: u1, - /// DFSDM timer clock enable - DFSDM1EN: u1, - reserved26: u1, - /// LCD-TFT clock enable - LTDCEN: u1, - /// DSI clock enable - DSIEN: u1, - padding: u4, - }), - reserved104: [4]u8, - /// AHB1 peripheral clocks enable in Sleep and Stop modes register - AHB1SMENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clocks enable during Sleep and Stop modes - DMA1SMEN: u1, - /// DMA2 clocks enable during Sleep and Stop modes - DMA2SMEN: u1, - /// DMAMUX clock enable during Sleep and Stop modes - DMAMUX1SMEN: u1, - reserved8: u5, - /// Flash memory interface clocks enable during Sleep and Stop modes - FLASHSMEN: u1, - /// SRAM1 interface clocks enable during Sleep and Stop modes - SRAM1SMEN: u1, - reserved12: u2, - /// CRCSMEN - CRCSMEN: u1, - reserved16: u3, - /// Touch Sensing Controller clocks enable during Sleep and Stop modes - TSCSMEN: u1, - /// DMA2D clock enable during Sleep and Stop modes - DMA2DSMEN: u1, - /// GFXMMU clock enable during Sleep and Stop modes - GFXMMUSMEN: u1, - padding: u13, - }), - /// AHB2 peripheral clocks enable in Sleep and Stop modes register - AHB2SMENR: mmio.Mmio(packed struct(u32) { - /// IO port A clocks enable during Sleep and Stop modes - GPIOASMEN: u1, - /// IO port B clocks enable during Sleep and Stop modes - GPIOBSMEN: u1, - /// IO port C clocks enable during Sleep and Stop modes - GPIOCSMEN: u1, - /// IO port D clocks enable during Sleep and Stop modes - GPIODSMEN: u1, - /// IO port E clocks enable during Sleep and Stop modes - GPIOESMEN: u1, - /// IO port F clocks enable during Sleep and Stop modes - GPIOFSMEN: u1, - /// IO port G clocks enable during Sleep and Stop modes - GPIOGSMEN: u1, - /// IO port H clocks enable during Sleep and Stop modes - GPIOHSMEN: u1, - /// IO port I clocks enable during Sleep and Stop modes - GPIOISMEN: u1, - /// SRAM2 interface clocks enable during Sleep and Stop modes - SRAM2SMEN: u1, - /// SRAM2 interface clocks enable during Sleep and Stop modes - SRAM3SMEN: u1, - reserved12: u1, - /// OTG full speed clocks enable during Sleep and Stop modes - USB_OTG_FSSMEN: u1, - /// ADC clocks enable during Sleep and Stop modes - ADCFSSMEN: u1, - /// DCMI clock enable during Sleep and Stop modes - DCMISMEN: u1, - /// PKA clocks enable during Sleep and Stop modes - PKASMEN: u1, - /// AES accelerator clocks enable during Sleep and Stop modes - AESSMEN: u1, - /// HASH clock enable during Sleep and Stop modes - HASH1SMEN: u1, - /// Random Number Generator clocks enable during Sleep and Stop modes - RNGSMEN: u1, - reserved20: u1, - /// OctoSPI IO manager clocks enable during Sleep and Stop modes - OCTOSPIMSMEN: u1, - reserved22: u1, - /// SDMMC1 clocks enable during Sleep and Stop modes - SDMMC1SMEN: u1, - /// SDMMC2 clocks enable during Sleep and Stop modes - SDMMC2SMEN: u1, - padding: u8, - }), - /// AHB3 peripheral clocks enable in Sleep and Stop modes register - AHB3SMENR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller clocks enable during Sleep and Stop modes - FMCSMEN: u1, + /// Power control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup pin WKUP + EWUP: u1, reserved8: u7, - /// OctoSPI1 memory interface clocks enable during Sleep and Stop modes - OCTOSPI1SMEN: u1, - /// OctoSPI2 memory interface clocks enable during Sleep and Stop modes - OCTOSPI2SMEN: u1, - padding: u22, - }), - reserved120: [4]u8, - /// APB1SMENR1 - APB1SMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clocks enable during Sleep and Stop modes - TIM2SMEN: u1, - /// TIM3 timer clocks enable during Sleep and Stop modes - TIM3SMEN: u1, - /// TIM4 timer clocks enable during Sleep and Stop modes - TIM4SMEN: u1, - /// TIM5 timer clocks enable during Sleep and Stop modes - TIM5SMEN: u1, - /// TIM6 timer clocks enable during Sleep and Stop modes - TIM6SMEN: u1, - /// TIM7 timer clocks enable during Sleep and Stop modes - TIM7SMEN: u1, - reserved10: u4, - /// RTC APB clock enable during Sleep and Stop modes - RTCAPBSMEN: u1, - /// Window watchdog clocks enable during Sleep and Stop modes - WWDGSMEN: u1, - reserved14: u2, - /// SPI2 clocks enable during Sleep and Stop modes - SPI2SMEN: u1, - /// SPI3 clocks enable during Sleep and Stop modes - SP3SMEN: u1, - reserved17: u1, - /// USART2 clocks enable during Sleep and Stop modes - USART2SMEN: u1, - /// USART3 clocks enable during Sleep and Stop modes - USART3SMEN: u1, - /// UART4 clocks enable during Sleep and Stop modes - UART4SMEN: u1, - /// UART5 clocks enable during Sleep and Stop modes - UART5SMEN: u1, - /// I2C1 clocks enable during Sleep and Stop modes - I2C1SMEN: u1, - /// I2C2 clocks enable during Sleep and Stop modes - I2C2SMEN: u1, - /// I2C3 clocks enable during Sleep and Stop modes - I2C3SMEN: u1, - /// CRS clock enable during Sleep and Stop modes - CRSSMEN: u1, - /// CAN1 clocks enable during Sleep and Stop modes - CAN1SMEN: u1, - reserved28: u2, - /// Power interface clocks enable during Sleep and Stop modes - PWRSMEN: u1, - /// DAC1 interface clocks enable during Sleep and Stop modes - DAC1SMEN: u1, - /// OPAMP interface clocks enable during Sleep and Stop modes - OPAMPSMEN: u1, - /// Low power timer 1 clocks enable during Sleep and Stop modes - LPTIM1SMEN: u1, - }), - /// APB1 peripheral clocks enable in Sleep and Stop modes register 2 - APB1SMENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clocks enable during Sleep and Stop modes - LPUART1SMEN: u1, - /// I2C4 clocks enable during Sleep and Stop modes - I2C4SMEN: u1, - reserved5: u3, - /// LPTIM2SMEN - LPTIM2SMEN: u1, - padding: u26, - }), - /// APB2SMENR - APB2SMENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clocks enable during Sleep and Stop modes - SYSCFGSMEN: u1, - reserved11: u10, - /// TIM1 timer clocks enable during Sleep and Stop modes - TIM1SMEN: u1, - /// SPI1 clocks enable during Sleep and Stop modes - SPI1SMEN: u1, - /// TIM8 timer clocks enable during Sleep and Stop modes - TIM8SMEN: u1, - /// USART1clocks enable during Sleep and Stop modes - USART1SMEN: u1, - reserved16: u1, - /// TIM15 timer clocks enable during Sleep and Stop modes - TIM15SMEN: u1, - /// TIM16 timer clocks enable during Sleep and Stop modes - TIM16SMEN: u1, - /// TIM17 timer clocks enable during Sleep and Stop modes - TIM17SMEN: u1, - reserved21: u2, - /// SAI1 clocks enable during Sleep and Stop modes - SAI1SMEN: u1, - /// SAI2 clocks enable during Sleep and Stop modes - SAI2SMEN: u1, - reserved24: u1, - /// DFSDM timer clocks enable during Sleep and Stop modes - DFSDM1SMEN: u1, - reserved26: u1, - /// LCD-TFT timer clocks enable during Sleep and Stop modes - LTDCSMEN: u1, - /// DSI clocks enable during Sleep and Stop modes - DSISMEN: u1, - padding: u4, - }), - reserved136: [4]u8, - /// CCIPR - CCIPR: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SEL: packed union { - raw: u2, - value: USART1SEL, - }, - /// USART2 clock source selection - USART2SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// USART3 clock source selection - USART3SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// UART4 clock source selection - UART4SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// UART5 clock source selection - UART5SEL: packed union { - raw: u2, - value: USARTSEL, - }, - /// LPUART1 clock source selection - LPUART1SEL: packed union { - raw: u2, - value: LPUART1SEL, - }, - /// I2C1 clock source selection - I2C1SEL: packed union { - raw: u2, - value: I2C1SEL, - }, - /// I2C2 clock source selection - I2C2SEL: packed union { - raw: u2, - value: I2C2SEL, - }, - /// I2C3 clock source selection - I2C3SEL: packed union { - raw: u2, - value: I2C3SEL, - }, - /// Low power timer 1 clock source selection - LPTIM1SEL: packed union { - raw: u2, - value: LPTIM1SEL, - }, - /// Low power timer 2 clock source selection - LPTIM2SEL: packed union { - raw: u2, - value: LPTIM2SEL, - }, - reserved26: u4, - /// 48 MHz clock source selection - CLK48SEL: packed union { - raw: u2, - value: CLK48SEL, - }, - /// ADCs clock source selection - ADCSEL: packed union { - raw: u2, - value: ADCSEL, - }, - padding: u2, - }), - reserved144: [4]u8, - /// BDCR - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enable - LSEON: u1, - /// LSE oscillator ready - LSERDY: u1, - /// LSE oscillator bypass - LSEBYP: u1, - /// SE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// LSECSSON - LSECSSON: u1, - /// LSECSSD - LSECSSD: u1, - /// Disable the Clock LSE propagation to the system - LSESYSDIS: u1, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - reserved24: u7, - /// Low speed clock output enable - LSCOEN: u1, - /// Low speed clock output selection - LSCOSEL: packed union { + /// SRAM2 retention in Standby mode + RRS: packed union { raw: u1, - value: LSCOSEL, + value: RRS, }, - padding: u6, + reserved10: u1, + /// Apply pull-up and pull-down configuration + APC: u1, + reserved15: u4, + /// Enable internal wakeup line + EWF: u1, + padding: u16, }), - /// CSR - CSR: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable - LSION: u1, - /// LSI oscillator ready - LSIRDY: u1, - reserved4: u2, - /// Internal low-speed oscillator predivided by 128. Note - This bit is available only on STM32L4P5xx and STM32L4Q5xx devices. - LSIPREDIV: u1, + /// Power control register 4 + CR4: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP1 polarity + WP1: u1, + /// Wakeup pin WKUP2 polarity + WP2: u1, + /// Wakeup pin WKUP3 polarity + WP3: u1, + /// Wakeup pin WKUP4 polarity + WP4: u1, + /// Wakeup pin WKUP5 polarity + WP5: u1, reserved8: u3, - /// SI range after Standby mode - MSISRANGE: u4, - reserved23: u11, - /// Remove reset flag - RMVF: u1, - /// Firewall reset flag - FWRSTF: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// Pin reset flag - PINRSTF: u1, - /// BOR flag - BORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent window watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// VBAT battery charging enable + VBE: u1, + /// VBAT battery charging resistor selection + VBRS: u1, + padding: u22, }), - /// Clock recovery RC register - CRRCR: mmio.Mmio(packed struct(u32) { - /// HSI48 clock enable - HSI48ON: u1, - /// HSI48 clock ready flag - HSI48RDY: u1, - reserved7: u5, - /// HSI48 clock calibration - HSI48CAL: u9, + /// Power status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Wakeup flag 1 + CWUF1: u1, + /// Wakeup flag 2 + CWUF2: u1, + /// Wakeup flag 3 + CWUF3: u1, + /// Wakeup flag 4 + CWUF4: u1, + /// Wakeup flag 5 + CWUF5: u1, + reserved8: u3, + /// Standby flag + CSBF: u1, + reserved15: u6, + /// Wakeup flag internal + WUFI: u1, padding: u16, }), - /// Peripherals independent clock configuration register - CCIPR2: mmio.Mmio(packed struct(u32) { - /// I2C4 clock source selection - I2C4SEL: packed union { - raw: u2, - value: I2C4SEL, - }, - /// Digital filter for sigma delta modulator kernel clock source selection - DFSDMSEL: packed union { - raw: u1, - value: DFSDMSEL, - }, - /// Digital filter for sigma delta modulator audio clock source selection - ADFSDMSEL: packed union { - raw: u2, - value: ADFSDMSEL, - }, - /// SAI1 clock source selection - SAI1SEL: packed union { - raw: u3, - value: SAI1SEL, - }, - /// SAI2 clock source selection - SAI2SEL: packed union { - raw: u3, - value: SAI2SEL, - }, - reserved12: u1, - /// clock selection - DSISEL: packed union { - raw: u1, - value: DSISEL, - }, - reserved14: u1, - /// SDMMC clock selection - SDMMCSEL: packed union { - raw: u1, - value: SDMMCSEL, - }, - reserved16: u1, - /// division factor for LTDC clock - LTDCDIV: u2, - reserved20: u2, - /// Octospi clock source selection - OCTOSPISEL: packed union { - raw: u2, - value: OCTOSPISEL, - }, - padding: u10, - }), - reserved164: [4]u8, - /// delay configuration register - DLYCFGR: mmio.Mmio(packed struct(u32) { - /// Delay sampling configuration on OCTOSPI1 to be used for internal sampling clock (called feedback clock) or for DQS data strobe - OCTOSPI1_DLY: u4, - /// Delay sampling configuration on OCTOSPI2 to be used for internal sampling clock (called feedback clock) or for DQS data strobe - OCTOSPI2_DLY: u4, - padding: u24, - }), - }; - }; - - pub const syscfg_f2 = struct { - pub const MEM_MODE = enum(u2) { - /// Main Flash memory mapped at 0x0000_0000 - MainFlash = 0x0, - /// System Flash memory mapped at 0x0000_0000 - SystemFlash = 0x1, - /// FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000_0000 - FSMC = 0x2, - /// Embedded SRAM mapped at 0x0000_0000 - SRAM = 0x3, - }; - - /// System configuration controller - pub const SYSCFG = extern struct { - /// memory remap register - MEMRMP: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection - MEM_MODE: packed union { - raw: u2, - value: MEM_MODE, - }, - padding: u30, - }), - /// peripheral mode configuration register - PMC: mmio.Mmio(packed struct(u32) { - reserved23: u23, - /// Ethernet PHY interface selection - MII_RMII_SEL: u1, - padding: u8, - }), - /// external interrupt configuration register 1 - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration (x = 0 to 3) - EXTI: u4, - padding: u28, + /// Power status register 2 + SR2: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// Low-power regulator started + REGLPS: u1, + /// Low-power regulator flag + REGLPF: u1, + /// Voltage scaling flag + VOSF: u1, + /// Power voltage detector output + PVDO: u1, + /// Peripheral voltage monitoring output: VDDUSB vs. 1.2 V + PVMO1: u1, + /// Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V + PVMO2: u1, + /// Peripheral voltage monitoring output: VDDA vs. 1.62 V + PVMO3: u1, + /// Peripheral voltage monitoring output: VDDA vs. 2.2 V + PVMO4: u1, + padding: u16, }), - reserved32: [8]u8, - /// Compensation cell control register - CMPCR: mmio.Mmio(packed struct(u32) { - /// Compensation cell power-down - CMP_PD: u1, + /// Power status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear wakeup flag + CWUF: u1, reserved8: u7, - /// Compensation cell ready flag - READY: u1, + /// Clear standby flag + SBF: u1, padding: u23, }), + reserved32: [4]u8, + /// Power Port A pull-up control register + PUCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, + padding: u31, + }), + /// Power Port A pull-down control register + PDCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, + padding: u31, + }), }; }; - pub const lptim_v1b = struct { - pub const CKPOL = enum(u2) { - /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. - Rising = 0x0, - /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. - Falling = 0x1, - /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. - Both = 0x2, + pub const pwr_l5 = struct { + pub const LPMS = enum(u3) { + /// Stop 0 mode + Stop0 = 0x0, + /// Stop 1 mode + Stop1 = 0x1, + /// Stop 2 mode + Stop2 = 0x2, + /// Standby mode + Standby = 0x3, + /// Shutdown mode + Shutdown = 0x4, _, }; - pub const ClockSource = enum(u1) { - /// clocked by internal clock source (APB clock or any of the embedded oscillators) - Internal = 0x0, - /// clocked by an external clock source through the LPTIM external Input1 - External = 0x1, - }; - - pub const Filter = enum(u2) { - Count1 = 0x0, - Count2 = 0x1, - Count4 = 0x2, - Count8 = 0x3, + pub const LPR = enum(u1) { + /// Voltage regulator in Main mode + MainMode = 0x0, + /// Voltage regulator in low-power mode + LowPowerMode = 0x1, }; - pub const PRESC = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div4 = 0x2, - Div8 = 0x3, - Div16 = 0x4, - Div32 = 0x5, - Div64 = 0x6, - Div128 = 0x7, + pub const PLS = enum(u3) { + /// 2.0V + V2_0 = 0x0, + /// 2.2V + V2_2 = 0x1, + /// 2.4V + V2_4 = 0x2, + /// 2.5V + V2_5 = 0x3, + /// 2.6V + V2_6 = 0x4, + /// 2.8V + V2_8 = 0x5, + /// 2.9V + V2_9 = 0x6, + /// External input analog voltage PVD_IN (compared internally to VREFINT) + External = 0x7, }; - pub const TRIGEN = enum(u2) { - /// software trigger (counting start is initiated by software) - Software = 0x0, - /// rising edge is the active edge - RisingEdge = 0x1, - /// falling edge is the active edge - FallingEdge = 0x2, - /// both edges are active edges - BothEdge = 0x3, + pub const RRS = enum(u2) { + /// SRAM2 powered off in Standby mode (SRAM2 content lost) + PowerOff = 0x0, + /// SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) + OnLPR = 0x1, + /// Only the upper 4 Kbytes of SRAM2 are powered by the low-power regulator in Standby mode (upper 4 Kbytes of SRAM2 content 0x2003 F000 - 0x2003 FFFF is kept). + OnLPRTop4kb = 0x2, + _, }; - pub const WAVPOL = enum(u1) { - /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. - Positive = 0x0, - /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. - Negative = 0x1, + pub const VOS = enum(u2) { + /// Range 0 + Range0 = 0x0, + /// Range 1 + Range1 = 0x1, + /// Range 2 + Range2 = 0x2, + _, }; - /// Low power timer with Output Compare - pub const LPTIM = extern struct { - /// LPTIM interrupt and status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, - /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. - ARRM: u1, - /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. - EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, - /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. - ARROK: u1, - /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UP: u1, - /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWN: u1, - padding: u25, - }), - /// LPTIM interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, - /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. - ARRMCF: u1, - /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. - EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, - /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. - ARROKCF: u1, - /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPCF: u1, - /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNCF: u1, - padding: u25, - }), - /// LPTIM interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, - /// Autoreload match Interrupt Enable. - ARRMIE: u1, - /// External trigger valid edge Interrupt Enable. - EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, - /// Autoreload register update OK Interrupt Enable. - ARROKIE: u1, - /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPIE: u1, - /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNIE: u1, - padding: u25, - }), - /// LPTIM configuration register. - CFGR: mmio.Mmio(packed struct(u32) { - /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. - CKSEL: packed union { - raw: u1, - value: ClockSource, - }, - /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. - CKPOL: packed union { - raw: u2, - value: CKPOL, - }, - /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - CKFLT: packed union { - raw: u2, - value: Filter, - }, - reserved6: u1, - /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. - TRGFLT: packed union { - raw: u2, - value: Filter, - }, - reserved9: u1, - /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. - PRESC: packed union { + /// Power control + pub const PWR = extern struct { + /// Power control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection + LPMS: packed union { raw: u3, - value: PRESC, + value: LPMS, }, - reserved13: u1, - /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. - TRIGSEL: u3, - reserved17: u1, - /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. - TRIGEN: packed union { + reserved8: u5, + /// Disable backup domain write protection + DBP: u1, + /// Voltage scaling range selection + VOS: packed union { raw: u2, - value: TRIGEN, + value: VOS, }, - /// Timeout enable The TIMOUT bit controls the Timeout feature. - TIMOUT: u1, - /// Waveform shape The WAVE bit controls the output shape. - WAVE: u1, - /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. - WAVPOL: packed union { + reserved14: u3, + /// Low-power run + LPR: packed union { raw: u1, - value: WAVPOL, + value: LPR, }, - /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. - PRELOAD: u1, - /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. - COUNTMODE: packed union { - raw: u1, - value: ClockSource, + padding: u17, + }), + /// Power control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Power voltage detector enable + PVDE: u1, + /// Power voltage detector level selection + PLS: packed union { + raw: u3, + value: PLS, }, - /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - ENC: u1, - padding: u7, + /// Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V + PVME1: u1, + /// Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V + PVME2: u1, + /// Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V + PVME3: u1, + /// Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V + PVME4: u1, + reserved9: u1, + /// VDDIO2 Independent I/Os supply valid + IOSV: u1, + /// VDDUSB USB supply valid + USV: u1, + padding: u21, }), - /// LPTIM control register. - CR: mmio.Mmio(packed struct(u32) { - /// LPTIM enable The ENABLE bit is set and cleared by software. - ENABLE: u1, - /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. - SNGSTRT: u1, - /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. - CNTSTRT: u1, - /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. - COUNTRST: u1, - /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. - RSTARE: u1, - padding: u27, + /// Power control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup pin WKUP + EWUP: u1, + reserved8: u7, + /// SRAM2 retention in Standby mode + RRS: packed union { + raw: u2, + value: RRS, + }, + /// Apply pull-up and pull-down configuration + APC: u1, + /// ULPMEN + ULPMEN: u1, + reserved13: u1, + /// UCPD_STDBY + UCPD_STDBY: u1, + /// UCPD_DBDIS + UCPD_DBDIS: u1, + padding: u17, }), - /// LPTIM compare register 1. - CMP: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. - CMP: u16, + /// Power control register 4 + CR4: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP1 polarity + WP1: u1, + /// Wakeup pin WKUP2 polarity + WP2: u1, + /// Wakeup pin WKUP3 polarity + WP3: u1, + /// Wakeup pin WKUP4 polarity + WP4: u1, + /// Wakeup pin WKUP5 polarity + WP5: u1, + reserved8: u3, + /// VBAT battery charging enable + VBE: u1, + /// VBAT battery charging resistor selection + VBRS: u1, + reserved12: u2, + /// SMPSBYP + SMPSBYP: u1, + /// EXTSMPSEN + EXTSMPSEN: u1, + /// SMPSFSTEN + SMPSFSTEN: u1, + /// SMPSLPEN + SMPSLPEN: u1, padding: u16, }), - /// LPTIM autoreload register. - ARR: mmio.Mmio(packed struct(u32) { - /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. - ARR: u16, + /// Power status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Wakeup flag 1 + CWUF1: u1, + /// Wakeup flag 2 + CWUF2: u1, + /// Wakeup flag 3 + CWUF3: u1, + /// Wakeup flag 4 + CWUF4: u1, + /// Wakeup flag 5 + CWUF5: u1, + reserved8: u3, + /// Standby flag + CSBF: u1, + reserved15: u6, + /// Wakeup flag internal + WUFI: u1, padding: u16, }), - /// LPTIM counter register. - CNT: mmio.Mmio(packed struct(u32) { - /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. - CNT: u16, + /// Power status register 2 + SR2: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// Low-power regulator started + REGLPS: u1, + /// Low-power regulator flag + REGLPF: u1, + /// Voltage scaling flag + VOSF: u1, + /// Power voltage detector output + PVDO: u1, + /// Peripheral voltage monitoring output: VDDUSB vs. 1.2 V + PVMO1: u1, + /// Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V + PVMO2: u1, + /// Peripheral voltage monitoring output: VDDA vs. 1.62 V + PVMO3: u1, + /// Peripheral voltage monitoring output: VDDA vs. 2.2 V + PVMO4: u1, padding: u16, }), - /// LPTIM option register. - OR: u32, - }; - }; - - pub const adc_u0 = struct { - pub const DMACFG = enum(u1) { - /// DMA One Shot mode selected - OneShot = 0x0, - /// DMA Circular mode selected - Circular = 0x1, - }; - - pub const RES = enum(u2) { - /// 12-bit resolution - Bits12 = 0x0, - /// 10-bit resolution - Bits10 = 0x1, - /// 8-bit resolution - Bits8 = 0x2, - /// 6-bit resolution - Bits6 = 0x3, - }; - - pub const SAMPLE_TIME = enum(u3) { - /// 1.5 ADC cycles - Cycles1_5 = 0x0, - /// 3.5 ADC cycles - Cycles3_5 = 0x1, - /// 7.5 ADC cycles - Cycles7_5 = 0x2, - /// 12.5 ADC cycles - Cycles12_5 = 0x3, - /// 19.5 ADC cycles - Cycles19_5 = 0x4, - /// 39.5 ADC cycles - Cycles39_5 = 0x5, - /// 79.5 ADC cycles - Cycles79_5 = 0x6, - /// 160.5 ADC cycles - Cycles160_5 = 0x7, - }; - - /// Analog to Digital Converter - pub const ADC = extern struct { - /// ADC interrupt and status register - ISR: mmio.Mmio(packed struct(u32) { - /// ADC ready flag - ADRDY: u1, - /// ADC group regular end of sampling flag - EOSMP: u1, - /// ADC group regular end of unitary conversion flag - EOC: u1, - /// ADC group regular end of sequence conversions flag - EOS: u1, - /// ADC group regular overrun flag - OVR: u1, - reserved7: u2, - /// ADC analog watchdog 1 flag - AWD1: u1, - /// ADC analog watchdog 2 flag - AWD2: u1, - /// ADC analog watchdog 3 flag - AWD3: u1, - reserved11: u1, - /// End Of Calibration flag - EOCAL: u1, - reserved13: u1, - /// Channel Configuration Ready flag - CCRDY: u1, - padding: u18, - }), - /// ADC interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// ADC ready interrupt - ADRDYIE: u1, - /// ADC group regular end of sampling interrupt - EOSMPIE: u1, - /// ADC group regular end of unitary conversion interrupt - EOCIE: u1, - /// ADC group regular end of sequence conversions interrupt - EOSIE: u1, - /// ADC group regular overrun interrupt - OVRIE: u1, - reserved7: u2, - /// ADC analog watchdog 1 interrupt - AWD1IE: u1, - /// ADC analog watchdog 2 interrupt - AWD2IE: u1, - /// ADC analog watchdog 3 interrupt - AWD3IE: u1, - reserved11: u1, - /// End of calibration interrupt enable - EOCALIE: u1, - reserved13: u1, - /// Channel Configuration Ready Interrupt enable - CCRDYIE: u1, - padding: u18, - }), - /// ADC control register - CR: mmio.Mmio(packed struct(u32) { - /// ADC enable - ADEN: u1, - /// ADC disable - ADDIS: u1, - /// ADC group regular conversion start - ADSTART: u1, - reserved4: u1, - /// ADC group regular conversion stop - ADSTP: u1, - reserved28: u23, - /// ADC voltage regulator enable - ADVREGEN: u1, - reserved31: u2, - /// ADC calibration - ADCAL: u1, - }), - /// ADC configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// ADC DMA transfer enable - DMAEN: u1, - /// Direct memory access configuration - DMACFG: packed union { - raw: u1, - value: DMACFG, - }, - /// Scan sequence direction - SCANDIR: u1, - /// ADC data resolution - RES: packed union { - raw: u2, - value: RES, - }, - /// ADC data alignement - ALIGN: u1, - /// ADC group regular external trigger source - EXTSEL: u3, - reserved10: u1, - /// ADC group regular external trigger polarity - EXTEN: u2, - /// ADC group regular overrun configuration - OVRMOD: u1, - /// Continuous conversion - CONT: u1, - /// Wait conversion mode - WAIT: u1, - /// Auto-off mode - AUTOFF: u1, - /// ADC group regular sequencer discontinuous mode - DISCEN: u1, - reserved21: u4, - /// Mode selection of the ADC_CHSELR register - CHSELRMOD: u1, - /// ADC analog watchdog 1 monitoring a single channel or all channels - AWD1SGL: u1, - /// ADC analog watchdog 1 enable on scope ADC group regular - AWD1EN: u1, - reserved26: u2, - /// ADC analog watchdog 1 monitored channel selection - AWDCH1CH: u5, - padding: u1, - }), - /// ADC configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// ADC oversampler enable on scope ADC group regular - OVSE: u1, - reserved2: u1, - /// ADC oversampling ratio - OVSR: u3, - /// ADC oversampling shift - OVSS: u4, - /// ADC oversampling discontinuous mode (triggered mode) for ADC group regular - TOVS: u1, - reserved29: u19, - /// Low frequency trigger mode enable - LFTRIG: u1, - /// ADC clock mode - CKMODE: u2, - }), - /// ADC sampling time register - SMPR: mmio.Mmio(packed struct(u32) { - /// Sampling time selection - SMP1: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - reserved4: u1, - /// Sampling time selection - SMP2: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - reserved8: u1, - /// Channel sampling time selection - SMPSEL: u1, + /// Power status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear wakeup flag + CWUF: u1, + reserved8: u7, + /// Clear standby flag + SBF: u1, padding: u23, }), - reserved32: [8]u8, - /// watchdog threshold register - AWD1TR: mmio.Mmio(packed struct(u32) { - /// ADC analog watchdog 1 threshold low - LT1: u12, - reserved16: u4, - /// ADC analog watchdog 1 threshold high - HT1: u12, - padding: u4, - }), - /// watchdog threshold register - AWD2TR: mmio.Mmio(packed struct(u32) { - /// ADC analog watchdog 2 threshold low - LT2: u12, - reserved16: u4, - /// ADC analog watchdog 2 threshold high - HT2: u12, - padding: u4, - }), - /// channel selection register - CHSELR: mmio.Mmio(packed struct(u32) { - /// Channel-x selection - CHSEL: u19, - padding: u13, - }), - /// watchdog threshold register - AWD3TR: mmio.Mmio(packed struct(u32) { - /// ADC analog watchdog 3 threshold high - LT3: u12, - reserved16: u4, - /// ADC analog watchdog 3 threshold high - HT3: u12, - padding: u4, - }), - reserved64: [16]u8, - /// ADC group regular conversion data register - DR: mmio.Mmio(packed struct(u32) { - /// ADC group regular conversion data - regularDATA: u16, - padding: u16, - }), - reserved160: [92]u8, - /// ADC analog watchdog 2 configuration register - AWD2CR: mmio.Mmio(packed struct(u32) { - /// ADC analog watchdog 2 monitored channel selection - AWD2CH: u19, - padding: u13, - }), - /// ADC analog watchdog 3 configuration register - AWD3CR: mmio.Mmio(packed struct(u32) { - /// ADC analog watchdog 3 monitored channel selection - AWD3CH: u19, - padding: u13, - }), - reserved180: [12]u8, - /// ADC calibration factors register - CALFACT: mmio.Mmio(packed struct(u32) { - /// ADC calibration factor in single-ended mode - CALFACT: u7, - padding: u25, - }), - reserved776: [592]u8, - /// ADC common control register - CCR: mmio.Mmio(packed struct(u32) { - reserved18: u18, - /// ADC prescaler - PRESC: u4, - /// VREFINT enable - VREFEN: u1, - /// Temperature sensor enable - TSEN: u1, - /// VBAT enable - VBATEN: u1, - padding: u7, - }), - }; - }; - - pub const gpio_v2 = struct { - pub const IDR = enum(u1) { - /// Input is logic low - Low = 0x0, - /// Input is logic high - High = 0x1, - }; - - pub const MODER = enum(u2) { - /// Input mode (reset state) - Input = 0x0, - /// General purpose output mode - Output = 0x1, - /// Alternate function mode - Alternate = 0x2, - /// Analog mode - Analog = 0x3, - }; - - pub const ODR = enum(u1) { - /// Set output to logic low - Low = 0x0, - /// Set output to logic high - High = 0x1, - }; - - pub const OSPEEDR = enum(u2) { - /// Low speed - LowSpeed = 0x0, - /// Medium speed - MediumSpeed = 0x1, - /// High speed - HighSpeed = 0x2, - /// Very high speed - VeryHighSpeed = 0x3, - }; - - pub const OT = enum(u1) { - /// Output push-pull (reset state) - PushPull = 0x0, - /// Output open-drain - OpenDrain = 0x1, - }; - - pub const PUPDR = enum(u2) { - /// No pull-up, pull-down - Floating = 0x0, - /// Pull-up - PullUp = 0x1, - /// Pull-down - PullDown = 0x2, - _, - }; - - /// General-purpose I/Os - pub const GPIO = extern struct { - /// GPIO port mode register - MODER: mmio.Mmio(packed struct(u32) { - /// Port x configuration bits (y = 0..15) - MODER: packed union { - raw: u2, - value: MODER, - }, - padding: u30, - }), - /// GPIO port output type register - OTYPER: mmio.Mmio(packed struct(u32) { - /// Port x configuration bits (y = 0..15) - OT: packed union { - raw: u1, - value: OT, - }, - padding: u31, - }), - /// GPIO port output speed register - OSPEEDR: mmio.Mmio(packed struct(u32) { - /// Port x configuration bits (y = 0..15) - OSPEEDR: packed union { - raw: u2, - value: OSPEEDR, - }, - padding: u30, - }), - /// GPIO port pull-up/pull-down register - PUPDR: mmio.Mmio(packed struct(u32) { - /// Port x configuration bits (y = 0..15) - PUPDR: packed union { - raw: u2, - value: PUPDR, - }, - padding: u30, - }), - /// GPIO port input data register - IDR: mmio.Mmio(packed struct(u32) { - /// Port input data (y = 0..15) - IDR: packed union { - raw: u1, - value: IDR, - }, + reserved32: [4]u8, + /// Power Port A pull-up control register + PUCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, padding: u31, }), - /// GPIO port output data register - ODR: mmio.Mmio(packed struct(u32) { - /// Port output data (y = 0..15) - ODR: packed union { - raw: u1, - value: ODR, - }, + /// Power Port A pull-down control register + PDCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, padding: u31, }), - /// GPIO port bit set/reset register - BSRR: mmio.Mmio(packed struct(u32) { - /// Port x set bit y (y= 0..15) - BS: u1, - reserved16: u15, - /// Port x set bit y (y= 0..15) - BR: u1, - padding: u15, - }), - /// GPIO port configuration lock register - LCKR: mmio.Mmio(packed struct(u32) { - /// Port configuration locked - LCK: u1, - reserved16: u15, - /// Port configuration lock key active - LCKK: u1, - padding: u15, + reserved120: [80]u8, + /// Power secure configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// WKUP1 pin security + WUP1SEC: u1, + /// WKUP2 pin security + WUP2SEC: u1, + /// WKUP3 pin security + WUP3SEC: u1, + /// WKUP4 pin security + WUP4SEC: u1, + /// WKUP5 pin security + WUP5SEC: u1, + reserved8: u3, + /// LPMSEC + LPMSEC: u1, + /// VDMSEC + VDMSEC: u1, + /// VBSEC + VBSEC: u1, + /// APCSEC + APCSEC: u1, + padding: u20, }), - /// GPIO alternate function registers. The register described in the datasheet as AFRL is index 0 in this array, and AFRH is index 1. Note that when operating on AFRH, you need to subtract 8 from any operations on the field array it contains -- the alternate function for pin 9 is at index 1, for instance. - AFR: [2]mmio.Mmio(packed struct(u32) { - /// Alternate function selection for one of the pins controlled by this register (0-7). - AFR: u4, - padding: u28, + reserved128: [4]u8, + /// Power privilege configuration register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// PRIV + PRIV: u1, + padding: u31, }), }; }; - pub const tamp_u5 = struct { - pub const ATCKSEL = enum(u3) { - /// RTCCLK is selected - Div1 = 0x0, - /// RTCCLK/2 is selected when (PREDIV_A+1) = 128 (actually selects 1st flip flop output) - Div2 = 0x1, - /// RTCCLK/4 is selected when (PREDIV_A+1) = 128 (actually selects 2nd flip flop output) - Div4 = 0x2, - /// RTCCLK/128 is selected when (PREDIV_A+1) = 128 (actually selects 7th flip flop output) - Div128 = 0x7, + pub const pwr_u0 = struct { + pub const LPMS = enum(u3) { + /// Stop 0 mode + Stop0 = 0x0, + /// Stop 1 mode + Stop1 = 0x1, + /// Stop 2 mode + Stop2 = 0x2, + /// Standby mode + Standby = 0x3, _, }; - pub const TAMPFLT = enum(u2) { - /// Tamper event is activated on edge of INx input transitions to the active level (no internal pull-up on INx input). - NoFilter = 0x0, - /// Tamper event is activated after 2 consecutive samples at the active level. - Filter2 = 0x1, - /// Tamper event is activated after 4 consecutive samples at the active level. - Filter4 = 0x2, - /// Tamper event is activated after 8 consecutive samples at the active level. - Filter8 = 0x3, - }; - - pub const TAMPFREQ = enum(u3) { - /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - Hz_1 = 0x0, - /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - Hz_2 = 0x1, - /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - Hz_4 = 0x2, - /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - Hz_8 = 0x3, - /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - Hz_16 = 0x4, - /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - Hz_32 = 0x5, - /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - Hz_64 = 0x6, - /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - Hz_128 = 0x7, + pub const PLS = enum(u3) { + /// VPVD0 around 2.01V + B_0x0 = 0x0, + /// VPVD1 around 2.21V + B_0x1 = 0x1, + /// VPVD2 around 2.41V + B_0x2 = 0x2, + /// VPVD3 around 2.51V + B_0x3 = 0x3, + /// VPVD4 around 2.61V + B_0x4 = 0x4, + /// VPVD5 around 2.81V + B_0x5 = 0x5, + /// VPVD6 around 2.91V + B_0x6 = 0x6, + /// External input analog voltage PVD_IN (compared internally to VREFINT) + B_0x7 = 0x7, }; - pub const TAMPPRCH = enum(u2) { - /// 1 RTCCLK cycle - Cycles1 = 0x0, - /// 2 RTCCLK cycles - Cycles2 = 0x1, - /// 4 RTCCLK cycles - Cycles4 = 0x2, - /// 8 RTCCLK cycles - Cycles8 = 0x3, + pub const STOPF = enum(u3) { + /// The device did not enter any Stop mode. + None = 0x0, + /// The device entered in Stop 0 mode. + Stop0 = 0x4, + /// The device entered in Stop 1 mode. + Stop1 = 0x5, + /// The device entered in Stop 2 mode. + Stop2 = 0x6, + _, }; - pub const TAMPTRG = enum(u1) { - /// If TAMPFLT 00 Tamper 2 input staying low triggers a tamper detection event. - FilteredLowOrUnfilteredHigh = 0x0, - /// If TAMPFLT 00 Tamper 2 input staying high triggers a tamper detection event. - FilteredHighOrUnfilteredLow = 0x1, + pub const VOS = enum(u2) { + /// Range 1 + Range1 = 0x1, + /// Range 2 + Range2 = 0x2, + _, }; - /// Tamper and backup registers - pub const TAMP = extern struct { - /// TAMP control register 1 + /// PWR register block + pub const PWR = extern struct { + /// Power control register 1 CR1: mmio.Mmio(packed struct(u32) { - /// Tamper detection on INx enable - TAMPE: u1, - reserved16: u15, - /// Internal tamper X enable - ITAMPE: u1, - padding: u15, - }), - /// TAMP control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Tamper X no erase - TAMPNOER: u1, - reserved16: u15, - /// Tamper X mask. The tamper 1 interrupt must not be enabled when TAMP1MSK is set. - TAMPMSK: u1, - reserved22: u5, - /// Backup registers and device secrets access blocked - BKBLOCK: u1, - /// Backup registers and device secrets erase. Writing '1 to this bit reset the backup registers and device secrets(1). Writing 0 has no effect. This bit is always read as 0. - BKERASE: u1, - /// Active level for tamper 1 input. - TAMPTRG: packed union { - raw: u1, - value: TAMPTRG, - }, - padding: u7, - }), - /// TAMP control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Internal Tamper X no erase - ITAMPNOER: u1, - padding: u31, - }), - /// TAMP filter control register - FLTCR: mmio.Mmio(packed struct(u32) { - /// Tamper sampling frequency. Determines the frequency at which each of the INx inputs are sampled. - TAMPFREQ: packed union { + /// Low-power mode selection These bits select the low-power mode entered when CPU enters the deepsleep mode. 1xx: Shutdown mode Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2. Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. + LPMS: packed union { raw: u3, - value: TAMPFREQ, - }, - /// INx filter count. These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the INx inputs. - TAMPFLT: packed union { - raw: u2, - value: TAMPFLT, + value: LPMS, }, - /// INx precharge duration. These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the INx inputs. - TAMPPRCH: packed union { + /// Flash memory powered down during Stop mode. This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode. + FPD_STOP: u1, + /// Flash memory powered down during Low-power run mode. This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode. + FPD_LPRUN: u1, + /// Flash memory powered down during Low-power sleep mode. This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode. + FPD_LPSLP: u1, + reserved8: u2, + /// Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. + DBP: u1, + /// Voltage scaling range selection + VOS: packed union { raw: u2, - value: TAMPPRCH, + value: VOS, }, - /// INx pull-up disable. This bit determines if each of the TAMPx pins are precharged before each sample. - TAMPPUDIS: u1, - padding: u24, + reserved14: u3, + /// Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead. + LPR: u1, + padding: u17, }), - /// TAMP active tamper control register 1 - ATCR1: mmio.Mmio(packed struct(u32) { - /// Tamper X active mode - TAMPAM: u1, - reserved8: u7, - /// Active tamper shared output X selection. The selected output must be available in the package pinout - ATOSEL: u2, - reserved16: u6, - /// Active tamper RTC asynchronous prescaler clock selection. These bits selects the RTC asynchronous prescaler stage output.The selected clock is CK_ATPRE.. fCK_ATPRE = fRTCCLK / 2ATCKSEL when (PREDIV_A+1) = 128.. .... These bits can be written only when all active tampers are disabled. The write protection remains for up to 1.5 ck_atpre cycles after all the active tampers are disable. - ATCKSEL: packed union { + /// Power control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Programmable voltage detector enable Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: This bit is reset only by a system reset. + PVDE: u1, + /// Programmable voltage detector level selection. These bits select the voltage threshold detected by the programmable voltage detector: Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: These bits are reset only by a system reset. + PLS: packed union { raw: u3, - value: ATCKSEL, + value: PLS, }, - reserved24: u5, - /// Active tamper output change period. The tamper output is changed every CK_ATPER = (2ATPER x CK_ATPRE) cycles. Refer to . - ATPER: u3, - reserved30: u3, - /// Active tamper output sharing. IN1 is compared with TAMPOUTSEL1. IN2 is compared with TAMPOUTSEL2. IN3 is compared with TAMPOUTSEL3. IN4 is compared with TAMPOUTSEL4. IN5 is compared with TAMPOUTSEL5. IN6 is compared with TAMPOUTSEL6. IN7 is compared with TAMPOUTSEL7. IN8 is compared with TAMPOUTSEL8 - ATOSHARE: u1, - /// Active tamper filter enable - FLTEN: u1, - }), - /// TAMP active tamper seed register - ATSEEDR: mmio.Mmio(packed struct(u32) { - /// Pseudo-random generator seed value. This register must be written four times with 32-bit values to provide the 128-bit seed to the PRNG. Writing to this register automatically sends the seed value to the PRNG. - SEED: u32, + /// Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.21V + PVME1: u1, + /// Peripheral voltage monitoring 3 enable: VDDA vs. 1.621V + PVME3: u1, + /// Peripheral voltage monitoring 4 enable: VDDA vs. 1.861V + PVME4: u1, + reserved10: u3, + /// VDDUSB USB supply valid This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB FS peripheral. If VDDUSB is not always present in the application, the PVM can be used to determine whether this supply is ready or not. + USV: u1, + padding: u21, }), - /// TAMP active tamper output register - ATOR: mmio.Mmio(packed struct(u32) { - /// Pseudo-random generator value. This field provides the values of the PRNG output. Because of potential inconsistencies due to synchronization delays, PRNG must be read at least twice. The read value is correct if it is equal to previous read value. This field can only be read when the APB is in secure mode. - PRNG: u8, - reserved14: u6, - /// Seed running flag. This flag is set by hardware when a new seed is written in the ATSEEDR. It is cleared by hardware when the PRNG has absorbed this new seed, and by system reset. The TAMP APB cock must not be switched off as long as SEEDF is set. - SEEDF: u1, - /// Active tamper initialization status. This flag is set by hardware when the PRNG has absorbed the first 128-bit seed, meaning that the enabled active tampers are functional. This flag is cleared when the active tampers are disabled. - INITS: u1, + /// Power control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Enable Wake-up pin WKUP1 When this bit is set, the external wake-up pin WKUP1 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register. + EWUP1: u1, + /// Enable Wake-up pin WKUP2 When this bit is set, the external wake-up pin WKUP2 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register. + EWUP2: u1, + /// Enable Wake-up pin WKUP3 When this bit is set, the external wake-up pin WKUP3 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register. + EWUP3: u1, + /// Enable Wake-up pin WKUP4 When this bit is set, the external wake-up pin WKUP4 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. + EWUP4: u1, + /// Enable Wake-up pin WKUP5 When this bit is set, the external wake-up pin WKUP5 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register. + EWUP5: u1, + reserved6: u1, + /// Enable Wake-up pin WKUP7. When this bit is set, the external wake-up pin WKUP7 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP7 bit in the PWR_CR4 register. + EWUP7: u1, + reserved8: u1, + /// SRAM2 retention in Standby mode + RRS: u1, + /// Enable ULP sampling When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases is not detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes. + ENULP: u1, + /// Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os are in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during RUN mode. + APC: u1, + reserved15: u4, + /// Enable internal wake-up line + EIWUL: u1, padding: u16, }), - /// TAMP active tamper control register 2 - ATCR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Active tamper shared output X selection. The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the ATCR1, and so can also be read or. written through ATCR1. - ATOSEL: u3, - padding: u21, + /// Power control register 4 + CR4: mmio.Mmio(packed struct(u32) { + /// Wake-up pin WKUP1 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP1 + WP1: u1, + /// Wake-up pin WKUP2 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 + WP2: u1, + /// Wake-up pin WKUP3 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 + WP3: u1, + /// Wake-up pin WKUP4 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 + WP4: u1, + /// Wake-up pin WKUP5 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 + WP5: u1, + reserved6: u1, + /// Wake-up pin WKUP7 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP7 + WP7: u1, + reserved8: u1, + /// VBAT battery charging enable + VBE: u1, + /// VBAT battery charging resistor selection + VBRS: u1, + padding: u22, }), - /// TAMP secure mode register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// Backup registers read/write protection offset. Protection zone 1 is defined for backup registers from BKP0R to BKPxR (x = BKPRWSEC-1, from 0 to 128). if TZEN=1, these backup registers can be read and written only with secure access. If TZEN=0: the protection zone 1 can be read and written with non-secure access. If BKPRWSEC = 0: there is no protection zone 1. If BKPRWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode. - BKPRWSEC: u8, - reserved15: u7, - /// Monotonic counter 1 secure protection - CNT1SEC: u1, - /// Backup registers write protection offset. Protection zone 2 is defined for backup registers from BKPyR (y = BKPRWSEC, from 0 to 128) to BKPzR (z = BKPWSEC-1, from 0 to 128, BKPWSECBKPRWSEC): if TZEN=1, these backup registers can be written only with secure access. They can be read with secure or non-secure access. Protection zone 3 defined for backup registers from BKPtR (t = BKPWSEC, from 0 to 127). They can be read or written with secure or non-secure access. If TZEN=0: the protection zone 2 can be read and written with non-secure access. If BKPWSEC = 0 or if BKPWSEC BKPRWSEC: there is no protection zone 2. If BKPWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode. - BKPWSEC: u8, - reserved30: u6, - /// Boot hardware key lock. This bit can be read and can only be written to 1 by software. It is cleared by hardware together with the backup registers following a tamper detection event or when the readout protection (RDP) is disabled. - BHKLOCK: u1, - /// Tamper protection (excluding monotonic counters and backup registers). Note: Refer to for details on the read protection. - TAMPSEC: u1, + /// Power status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Wake-up flag 1 This bit is set when a wake-up event is detected on wake-up pin, WKUP1. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register. + WUF1: u1, + /// Wake-up flag 2 This bit is set when a wake-up event is detected on wake-up pin, WKUP2. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register. + WUF2: u1, + /// Wake-up flag 3 This bit is set when a wake-up event is detected on wake-up pin, WKUP3. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register. + WUF3: u1, + /// Wake-up flag 4 This bit is set when a wake-up event is detected on wake-up pin,WKUP4. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register. + WUF4: u1, + /// Wake-up flag 5 This bit is set when a wake-up event is detected on wake-up pin, WKUP5. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register. + WUF5: u1, + reserved6: u1, + /// Wake-up flag 7 This bit is set when a wake-up event is detected on wake-up pin, WKUP7. It is cleared by writing 1 in the CWUF7 bit of the PWR_SCR register. + WUF7: u1, + reserved8: u1, + /// Standby flag This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. + SBF: u1, + /// Stop Flags These bits are set by hardware when the device enters any stop mode and are cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. + STOPF: packed union { + raw: u3, + value: STOPF, + }, + reserved15: u3, + /// Wake-up flag internal This bit is set when a wake-up is detected on the internal wake-up line. It is cleared when all internal wake-up sources are cleared. + WUFI: u1, + padding: u16, }), - /// TAMP privilege mode control register - PRIVCR: mmio.Mmio(packed struct(u32) { - reserved15: u15, - /// Monotonic counter 1 privilege protection - CNT1PRIV: u1, - reserved29: u13, - /// Backup registers zone 1 privilege protection - BKPRWPRIV: u1, - /// Backup registers zone 2 privilege protection - BKPWPRIV: u1, - /// Tamper privilege protection (excluding backup registers). Note: Refer to for details on the read protection. - TAMPPRIV: u1, + /// Power status register 2 + SR2: mmio.Mmio(packed struct(u32) { + reserved7: u7, + /// Flash ready flag This bit is set by hardware to indicate when the flash memory is readey to be accessed after wake-up from power-down. To place the flash memory in power-down, set either FPD_LPRUN, FPD_LPSLP or FPD_STP bits. Note : If the system boots from SRAM, the user application must wait until the FLASH_RDY bit is set, prior to jumping to flash memory. + FLASH_RDY: u1, + /// Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wake-up from Standby mode time may be increased. + REGLPS: u1, + /// Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready. + REGLPF: u1, + /// Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. + VOSF: u1, + /// Programmable voltage detector output + PVDO: u1, + /// Peripheral voltage monitoring output: VDDUSB vs. 1.2 V Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wake-up time. + PVMO1: u1, + reserved14: u1, + /// Peripheral voltage monitoring output: VDDA vs. 1.621V Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wake-up time. + PVMO3: u1, + /// Peripheral voltage monitoring output: VDDA vs. 2.21V Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wake-up time. + PVMO4: u1, + padding: u16, }), - reserved44: [4]u8, - /// TAMP interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt enable - TAMPIE: u1, - reserved16: u15, - /// Internal tamper X interrupt enable - ITAMPIE: u1, - padding: u15, + /// Power status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear wake-up flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register. + CWUF1: u1, + /// Clear wake-up flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register. + CWUF2: u1, + /// Clear wake-up flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register. + CWUF3: u1, + /// Clear wake-up flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register. + CWUF4: u1, + /// Clear wake-up flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register. + CWUF5: u1, + reserved6: u1, + /// Clear wake-up flag 7 Setting this bit clears the WUF7 flag in the PWR_SR1 register. + CWUF7: u1, + reserved8: u1, + /// Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register. + CSBF: u1, + padding: u23, }), - /// TAMP status register - SR: mmio.Mmio(packed struct(u32) { - /// TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. - TAMPF: u1, - reserved16: u15, - /// Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. - ITAMPF: u1, - padding: u15, + reserved32: [4]u8, + /// Power Port A pull-up control register + PUCRA: mmio.Mmio(packed struct(u32) { + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU0: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU1: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU2: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU3: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU4: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU5: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU6: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU7: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU8: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU9: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU10: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU11: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU12: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU13: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU14: u1, + /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU15: u1, + padding: u16, }), - /// TAMP non-secure masked interrupt status register - MISR: mmio.Mmio(packed struct(u32) { - /// TAMPx non-secure interrupt masked flag. This flag is set by hardware when the tamper X non-secure interrupt is raised. - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. - ITAMPMF: u1, - padding: u15, + /// Power Port A pull-down control register + PDCRA: mmio.Mmio(packed struct(u32) { + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD0: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD1: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD2: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD3: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD4: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD5: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD6: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD7: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD8: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD9: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD10: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD11: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD12: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD13: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD14: u1, + /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + PD15: u1, + padding: u16, }), - /// TAMP secure masked interrupt status register - SMISR: mmio.Mmio(packed struct(u32) { - /// TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper X secure interrupt is raised. - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. - ITAMPMF: u1, - padding: u15, + /// Power Port B pull-up control register + PUCRB: mmio.Mmio(packed struct(u32) { + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU0: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU1: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU2: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU3: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU4: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU5: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU6: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU7: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU8: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU9: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU10: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU11: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU12: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU13: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU14: u1, + /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + PU15: u1, + padding: u16, }), - /// TAMP status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the SR register. - CTAMPF: u1, - reserved16: u15, - /// Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. - CITAMPF: u1, - padding: u15, + /// Power Port B pull-down control register + PDCRB: mmio.Mmio(packed struct(u32) { + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD0: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD1: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD2: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD3: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD4: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD5: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD6: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD7: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD8: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD9: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD10: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD11: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD12: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD13: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD14: u1, + /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + PD15: u1, + padding: u16, }), - /// TAMP monotonic counter 1 register - COUNTR: mmio.Mmio(packed struct(u32) { - /// This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value. - COUNT: u32, + /// Power Port C pull-up control register + PUCRC: mmio.Mmio(packed struct(u32) { + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU0: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU1: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU2: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU3: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU4: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU5: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU6: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU7: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU8: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU9: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU10: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU11: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU12: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU13: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU14: u1, + /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU15: u1, + padding: u16, }), - reserved84: [16]u8, - /// TAMP erase configuration register - ERCFGR: mmio.Mmio(packed struct(u32) { - /// Configurable device secrets configuration - ERCFG0: u1, - padding: u31, + /// Power Port C pull-down control register + PDCRC: mmio.Mmio(packed struct(u32) { + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD0: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD1: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD2: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD3: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD4: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD5: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD6: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD7: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD8: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD9: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD10: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD11: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD12: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD13: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD14: u1, + /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + PD15: u1, + padding: u16, }), - reserved256: [168]u8, - /// TAMP backup X register - BKPR: [32]mmio.Mmio(packed struct(u32) { - /// The application can write or read data to and from these registers. In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. - BKP: u32, + /// Power Port D pull-up control register + PUCRD: mmio.Mmio(packed struct(u32) { + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU0: u1, + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU1: u1, + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU2: u1, + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU3: u1, + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU4: u1, + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU5: u1, + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU6: u1, + reserved8: u1, + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU8: u1, + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU9: u1, + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU10: u1, + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU11: u1, + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU12: u1, + /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU13: u1, + padding: u18, + }), + /// Power Port D pull-down control register + PDCRD: mmio.Mmio(packed struct(u32) { + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD0: u1, + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD1: u1, + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD2: u1, + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD3: u1, + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD4: u1, + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD5: u1, + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD6: u1, + reserved8: u1, + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD8: u1, + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD9: u1, + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD10: u1, + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD11: u1, + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD12: u1, + /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + PD13: u1, + padding: u18, + }), + /// Power Port E pull-up control register + PUCRE: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Port E pull-up bit 3 When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU3: u1, + reserved7: u3, + /// Port E pull-up bit y When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU7: u1, + /// Port E pull-up bit y When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU8: u1, + /// Port E pull-up bit y When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU9: u1, + padding: u22, + }), + /// Power Port E pull-down control register + PDCRE: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Port E pull-down bit 3 When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + PD3: u1, + reserved7: u3, + /// Port E pull-down bit y When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + PD7: u1, + /// Port E pull-down bit y When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + PD8: u1, + /// Port E pull-down bit y When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + PD9: u1, + padding: u22, + }), + /// Power Port F pull-up control register + PUCRF: mmio.Mmio(packed struct(u32) { + /// Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU0: u1, + /// Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU1: u1, + /// Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU2: u1, + /// Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + PU3: u1, + padding: u28, + }), + /// Power Port F pull-down control register + PDCRF: mmio.Mmio(packed struct(u32) { + /// Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + PD0: u1, + /// Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + PD1: u1, + /// Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + PD2: u1, + /// Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + PD3: u1, + padding: u28, }), }; }; - pub const flash_g4c2 = struct { - pub const LATENCY = enum(u4) { - /// Zero wait states - WS0 = 0x0, - /// One wait state - WS1 = 0x1, - /// Two wait states - WS2 = 0x2, - /// Three wait states - WS3 = 0x3, - /// Four wait states - WS4 = 0x4, - _, + pub const pwr_u5 = struct { + pub const ACTVOS = enum(u2) { + /// Range 4 (lowest power) + Range4 = 0x0, + /// Range 3 + Range3 = 0x1, + /// Range 2 + Range2 = 0x2, + /// Range 1 (highest frequency) + Range1 = 0x3, }; - pub const NRST_MODE = enum(u2) { - /// Reset pin is in reset input mode only - INPUT_ONLY = 0x1, - /// Reset pin is in GPIO mode only - GPIO = 0x2, - /// Reset pin is in reset input and output mode - INPUT_OUTPUT = 0x3, - _, + pub const FLASHFWU = enum(u1) { + /// Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption). + LowPower = 0x0, + /// Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time). + Normal = 0x1, }; - pub const RDP = enum(u8) { - /// Read protection not active - LEVEL_0 = 0xaa, - /// Memories read protection active - LEVEL_1 = 0xbb, - /// Chip read protection active - LEVEL_2 = 0xcc, + pub const LPMS = enum(u3) { + /// Stop 0 mode + Stop0 = 0x0, + /// Stop 1 mode + Stop1 = 0x1, + /// Stop 2 mode + Stop2 = 0x2, + /// Stop 3 mode + Stop3 = 0x3, _, }; - /// Flash - pub const FLASH = extern struct { - /// Access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: packed union { - raw: u4, - value: LATENCY, - }, - reserved8: u4, - /// Prefetch enable - PRFTEN: u1, - /// Instruction cache enable - ICEN: u1, - /// Data cache enable - DCEN: u1, - /// Instruction cache reset - ICRST: u1, - /// Data cache reset - DCRST: u1, - /// Flash Power-down mode during Low-power run mode - RUN_PD: u1, - /// Flash Power-down mode during Low-power sleep mode - SLEEP_PD: u1, - reserved18: u3, - /// Debug software enable - DBG_SWEN: u1, - padding: u13, - }), - /// Power down key register - PDKEYR: u32, - /// Flash key register - KEYR: u32, - /// Option byte key register - OPTKEYR: u32, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved3: u1, - /// Programming error - PROGERR: u1, - /// Write protected error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Size error - SIZERR: u1, - /// Programming sequence error - PGSERR: u1, - /// Fast programming data miss error - MISERR: u1, - /// Fast programming error - FASTERR: u1, - reserved14: u4, - /// PCROP read error - RDERR: u1, - /// Option validity error - OPTVERR: u1, - /// Busy - BSY: u1, - padding: u15, - }), - /// Flash control register - CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Page erase - PER: u1, - /// Bank 1 Mass erase - MER1: u1, - /// Page number - PNB: u7, - reserved16: u6, - /// Start - STRT: u1, - /// Options modification start - OPTSTRT: u1, - /// Fast programming - FSTPG: u1, - reserved24: u5, - /// End of operation interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// PCROP read error interrupt enable - RDERRIE: u1, - /// Force the option byte loading - OBL_LAUNCH: u1, - /// Securable memory area protection enable - SEC_PROT1: u1, - reserved30: u1, - /// Options Lock - OPTLOCK: u1, - /// FLASH_CR Lock - LOCK: u1, - }), - /// Flash ECC register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC fail address - ADDR_ECC: u19, - reserved21: u2, - /// ECC fail for Corrected ECC Error or Double ECC Error in info block - BK_ECC: u1, - /// ECC fail for Corrected ECC Error or Double ECC Error in info block - SYSF_ECC: u1, - reserved24: u1, - /// ECC correction interrupt enable - ECCIE: u1, - reserved28: u3, - /// ECC correction - ECCC2: u1, - /// ECC2 detection - ECCD2: u1, - /// ECC correction - ECCC: u1, - /// ECC detection - ECCD: u1, - }), - reserved32: [4]u8, - /// Flash option register - OPTR: mmio.Mmio(packed struct(u32) { - /// Read protection level - RDP: packed union { - raw: u8, - value: RDP, - }, - /// BOR reset Level - BOR_LEV: u3, - reserved12: u1, - /// nRST_STOP - nRST_STOP: u1, - /// nRST_STDBY - nRST_STDBY: u1, - /// nRST_SHDW - nRST_SHDW: u1, - reserved16: u1, - /// Independent watchdog selection - IDWG_SW: u1, - /// Independent watchdog counter freeze in Stop mode - IWDG_STOP: u1, - /// Independent watchdog counter freeze in Standby mode - IWDG_STDBY: u1, - /// Window watchdog selection - WWDG_SW: u1, - reserved23: u3, - /// Boot configuration - nBOOT1: u1, - /// SRAM2 parity check enable - SRAM2_PE: u1, - /// SRAM2 Erase when system reset - SRAM2_RST: u1, - /// nSWBOOT0 - nSWBOOT0: u1, - /// nBOOT0 option bit - nBOOT0: u1, - /// NRST_MODE - NRST_MODE: packed union { - raw: u2, - value: NRST_MODE, - }, - /// Internal reset holder enable bit - IRHEN: u1, - padding: u1, - }), - /// Flash Bank 1 PCROP Start address register - PCROP1SR: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area start offset - PCROP1_STRT: u15, - padding: u17, - }), - /// Flash Bank 1 PCROP End address register - PCROP1ER: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area end offset - PCROP1_END: u15, - reserved31: u16, - /// PCROP area preserved when RDP level decreased - PCROP_RDP: u1, - }), - /// Flash Bank 1 WRP area A address register - WRP1AR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP first area start offset - WRP1A_STRT: u7, - reserved16: u9, - /// Bank 1 WRP first area A end offset - WRP1A_END: u7, - padding: u9, - }), - /// Flash Bank 1 WRP area B address register - WRP1BR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP second area B end offset - WRP1B_STRT: u7, - reserved16: u9, - /// Bank 1 WRP second area B start offset - WRP1B_END: u7, - padding: u9, - }), - reserved112: [60]u8, - /// securable area bank1 register - SEC1R: mmio.Mmio(packed struct(u32) { - /// SEC_SIZE1 - SEC_SIZE1: u8, - reserved16: u8, - /// used to force boot from user area - BOOT_LOCK: u1, - padding: u15, - }), + pub const PDS = enum(u1) { + /// Content retained in Stop modes + Retained = 0x0, + /// Content lost in Stop modes + Lost = 0x1, }; - }; - pub const ltdc_v1 = struct { - pub const BF1 = enum(u3) { - /// BF1 = constant alpha - Constant = 0x4, - /// BF1 = pixel alpha * constant alpha - Pixel = 0x7, - _, + pub const PVDLS = enum(u3) { + /// VPVD0 around 2.0 V + v20 = 0x0, + /// VPVD1 around 2.2 V + v22 = 0x1, + /// VPVD2 around 2.4 V + v24 = 0x2, + /// VPVD3 around 2.5 V + v25 = 0x3, + /// VPVD4 around 2.6 V + v26 = 0x4, + /// VPVD5 around 2.8 V + v28 = 0x5, + /// VPVD6 around 2.9 V + v29 = 0x6, + /// External input analog voltage PVD_IN (compared internally to VREFINT) + pvd_in = 0x7, }; - pub const BF2 = enum(u3) { - /// BF2 = 1 - constant alpha - Constant = 0x5, - /// BF2 = 1 - pixel alpha * constant alpha - Pixel = 0x7, - _, + pub const PVDO = enum(u1) { + /// VDD is equal or above the PVD threshold selected by PVDLS[2:0]. + AboveOrEqual = 0x0, + /// VDD is below the PVD threshold selected by PVDLS[2:0]. + Below = 0x1, }; - pub const CFUIF = enum(u1) { - /// Clears the FUIF flag in the ISR register - Clear = 0x1, - _, + pub const REGSEL = enum(u1) { + /// LDO selected + LDO = 0x0, + /// SMPS selected + SMPS = 0x1, }; - pub const CLIF = enum(u1) { - /// Clears the LIF flag in the ISR register - Clear = 0x1, - _, + pub const SRAMFWU = enum(u1) { + /// SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption). + B_0x0 = 0x0, + /// SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time). + B_0x1 = 0x1, }; - pub const CRRIF = enum(u1) { - /// Clears the RRIF flag in the ISR register - Clear = 0x1, - _, + pub const SRAMPD = enum(u1) { + /// SRAM1 powered on + PoweredOn = 0x0, + /// SRAM1 powered off + PoweredOff = 0x1, }; - pub const CTERRIF = enum(u1) { - /// Clears the TERRIF flag in the ISR register - Clear = 0x1, - _, + pub const TEMPH = enum(u1) { + /// Temperature < high threshold + B_0x0 = 0x0, + /// Temperature ≥ high threshold + B_0x1 = 0x1, }; - pub const DEPOL = enum(u1) { - /// Data enable polarity is active low - ActiveLow = 0x0, - /// Data enable polarity is active high - ActiveHigh = 0x1, + pub const TEMPL = enum(u1) { + /// Temperature > low threshold + B_0x0 = 0x0, + /// Temperature ≤ low threshold + B_0x1 = 0x1, }; - pub const HSPOL = enum(u1) { - /// Horizontal synchronization polarity is active low - ActiveLow = 0x0, - /// Horizontal synchronization polarity is active high - ActiveHigh = 0x1, + pub const VBATH = enum(u1) { + /// Backup domain voltage level < high threshold + B_0x0 = 0x0, + /// Backup domain voltage level ≥ high threshold + B_0x1 = 0x1, }; - pub const IMR = enum(u1) { - /// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) - NoEffect = 0x0, - /// The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload - Reload = 0x1, + pub const VBE = enum(u1) { + /// VBAT battery charging disabled + B_0x0 = 0x0, + /// VBAT battery charging enabled + B_0x1 = 0x1, }; - pub const PCPOL = enum(u1) { - /// Pixel clock on rising edge - RisingEdge = 0x0, - /// Pixel clock on falling edge - FallingEdge = 0x1, + pub const VBRS = enum(u1) { + /// Charge VBAT through a 5 kΩ resistor + B_0x0 = 0x0, + /// Charge VBAT through a 1.5 kΩ resistor + B_0x1 = 0x1, }; - pub const PF = enum(u3) { - /// ARGB8888 - ARGB8888 = 0x0, - /// RGB888 - RGB888 = 0x1, - /// RGB565 - RGB565 = 0x2, - /// ARGB1555 - ARGB1555 = 0x3, - /// ARGB4444 - ARGB4444 = 0x4, - /// L8 (8-bit luminance) - L8 = 0x5, - /// AL44 (4-bit alpha, 4-bit luminance) - AL44 = 0x6, - /// AL88 (8-bit alpha, 8-bit luminance) - AL88 = 0x7, + pub const VOS = enum(u2) { + /// Range 4 (lowest power) + Range4 = 0x0, + /// Range 3 + Range3 = 0x1, + /// Range 2 + Range2 = 0x2, + /// Range 1 (highest frequency). This value cannot be written when VCOREMEN = 1 in TAMP_OR register. + Range1 = 0x3, }; - pub const VBR = enum(u1) { - /// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) - NoEffect = 0x0, - /// The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). - Reload = 0x1, + pub const WUPP = enum(u1) { + /// Detection on high level (rising edge) + High = 0x0, + /// Detection on low level (falling edge) + Low = 0x1, }; - pub const VSPOL = enum(u1) { - /// Vertical synchronization polarity is active low - ActiveLow = 0x0, - /// Vertical synchronization polarity is active high - ActiveHigh = 0x1, + pub const WUSEL = enum(u2) { + /// WKUP7_0 + B_0x0 = 0x0, + /// WKUP7_1 + B_0x1 = 0x1, + /// WKUP7_2 + B_0x2 = 0x2, + /// WKUP7_3 + B_0x3 = 0x3, }; - /// Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR - pub const LAYER = extern struct { - /// Layerx Control Register - CR: mmio.Mmio(packed struct(u32) { - /// Layer Enable - LEN: u1, - /// Color Keying Enable - COLKEN: u1, - reserved4: u2, - /// Color Look-Up Table Enable - CLUTEN: u1, - padding: u27, - }), - /// Layerx Window Horizontal Position Configuration Register - WHPCR: mmio.Mmio(packed struct(u32) { - /// Window Horizontal Start Position - WHSTPOS: u12, - reserved16: u4, - /// Window Horizontal Stop Position - WHSPPOS: u12, - padding: u4, - }), - /// Layerx Window Vertical Position Configuration Register - WVPCR: mmio.Mmio(packed struct(u32) { - /// Window Vertical Start Position - WVSTPOS: u11, - reserved16: u5, - /// Window Vertical Stop Position - WVSPPOS: u11, - padding: u5, - }), - /// Layerx Color Keying Configuration Register - CKCR: mmio.Mmio(packed struct(u32) { - /// Color Key Blue value - CKBLUE: u8, - /// Color Key Green value - CKGREEN: u8, - /// Color Key Red value - CKRED: u8, - padding: u8, - }), - /// Layerx Pixel Format Configuration Register - PFCR: mmio.Mmio(packed struct(u32) { - /// Pixel Format - PF: packed union { - raw: u3, - value: PF, - }, - padding: u29, - }), - /// Layerx Constant Alpha Configuration Register - CACR: mmio.Mmio(packed struct(u32) { - /// Constant Alpha - CONSTA: u8, - padding: u24, - }), - /// Layerx Default Color Configuration Register - DCCR: mmio.Mmio(packed struct(u32) { - /// Default Color Blue - DCBLUE: u8, - /// Default Color Green - DCGREEN: u8, - /// Default Color Red - DCRED: u8, - /// Default Color Alpha - DCALPHA: u8, - }), - /// Layerx Blending Factors Configuration Register - BFCR: mmio.Mmio(packed struct(u32) { - /// Blending Factor 2 - BF2: packed union { - raw: u3, - value: BF2, - }, - reserved8: u5, - /// Blending Factor 1 - BF1: packed union { + /// Power control + pub const PWR = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection These bits select the low-power mode entered when the CPU enters the Deepsleep mode. 10x: Standby mode (Standby mode also entered if LPMS=11X in CR1 with BREN=1 in BDCR1) 11x: Shutdown mode if BREN = 0 in BDCR1 + LPMS: packed union { raw: u3, - value: BF1, + value: LPMS, }, - padding: u21, - }), - reserved40: [8]u8, - /// Layerx Color Frame Buffer Address Register - CFBAR: mmio.Mmio(packed struct(u32) { - /// Color Frame Buffer Start Address - CFBADD: u32, - }), - /// Layerx Color Frame Buffer Length Register - CFBLR: mmio.Mmio(packed struct(u32) { - /// Color Frame Buffer Line Length - CFBLL: u13, - reserved16: u3, - /// Color Frame Buffer Pitch in bytes - CFBP: u13, - padding: u3, - }), - /// Layerx ColorFrame Buffer Line Number Register - CFBLNR: mmio.Mmio(packed struct(u32) { - /// Frame Buffer Line Number - CFBLNBR: u11, - padding: u21, - }), - reserved64: [12]u8, - /// Layerx CLUT Write Register - CLUTWR: mmio.Mmio(packed struct(u32) { - /// Blue value - BLUE: u8, - /// Green value - GREEN: u8, - /// Red value - RED: u8, - /// CLUT Address - CLUTADD: u8, - }), - }; - - /// LCD-TFT Controller - pub const LTDC = extern struct { - reserved8: [8]u8, - /// Synchronization Size Configuration Register - SSCR: mmio.Mmio(packed struct(u32) { - /// Vertical Synchronization Height (in units of horizontal scan line) - VSH: u11, - reserved16: u5, - /// Horizontal Synchronization Width (in units of pixel clock period) - HSW: u12, - padding: u4, - }), - /// Back Porch Configuration Register - BPCR: mmio.Mmio(packed struct(u32) { - /// Accumulated Vertical back porch (in units of horizontal scan line) - AVBP: u11, - reserved16: u5, - /// Accumulated Horizontal back porch (in units of pixel clock period) - AHBP: u12, - padding: u4, - }), - /// Active Width Configuration Register - AWCR: mmio.Mmio(packed struct(u32) { - /// Accumulated Active Height (in units of horizontal scan line) - AAH: u11, - reserved16: u5, - /// Accumulated Active Width (in units of pixel clock period) - AAW: u12, - padding: u4, - }), - /// Total Width Configuration Register - TWCR: mmio.Mmio(packed struct(u32) { - /// Total Height (in units of horizontal scan line) - TOTALH: u11, - reserved16: u5, - /// Total Width (in units of pixel clock period) - TOTALW: u12, - padding: u4, - }), - /// Global Control Register - GCR: mmio.Mmio(packed struct(u32) { - /// LCD-TFT controller enable bit - LTDCEN: u1, - reserved4: u3, - /// Dither Blue Width - DBW: u3, - reserved8: u1, - /// Dither Green Width - DGW: u3, - reserved12: u1, - /// Dither Red Width - DRW: u3, - reserved16: u1, - /// Dither Enable - DEN: u1, - reserved28: u11, - /// Pixel Clock Polarity - PCPOL: packed union { + reserved5: u2, + /// SRAM2 page 1 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2 (from SRAM2 base address to SRAM2 base address + 0x1FFF). Note: This bit has no effect in Shutdown mode. + RRSB1: u1, + /// SRAM2 page 2 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2 (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF). Note: This bit has no effect in Shutdown mode. + RRSB2: u1, + /// BOR ultra-low power mode This bit is used to reduce the consumption by configuring the BOR in discontinuous mode. This bit must be set to reach the lowest power consumption in the low-power modes. + ULPMEN: u1, + /// SRAM1 power down This bit is used to reduce the consumption by powering off the SRAM1. + SRAM1PD: packed union { raw: u1, - value: PCPOL, + value: SRAMPD, }, - /// Data Enable Polarity - DEPOL: packed union { + /// SRAM2 power down This bit is used to reduce the consumption by powering off the SRAM2. + SRAM2PD: packed union { raw: u1, - value: DEPOL, + value: SRAMPD, }, - /// Vertical Synchronization Polarity - VSPOL: packed union { + /// SRAM3 power down This bit is used to reduce the consumption by powering off the SRAM3. + SRAM3PD: packed union { raw: u1, - value: VSPOL, + value: SRAMPD, }, - /// Horizontal Synchronization Polarity - HSPOL: packed union { + /// SRAM4 power down This bit is used to reduce the consumption by powering off the SRAM4. + SRAM4PD: packed union { raw: u1, - value: HSPOL, + value: SRAMPD, }, + padding: u20, }), - reserved36: [8]u8, - /// Shadow Reload Configuration Register - SRCR: mmio.Mmio(packed struct(u32) { - /// Immediate Reload - IMR: packed union { + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + SRAM1PDS1: packed union { raw: u1, - value: IMR, + value: PDS, }, - /// Vertical Blanking Reload - VBR: packed union { + /// SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + SRAM1PDS2: packed union { raw: u1, - value: VBR, + value: PDS, + }, + /// SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + SRAM1PDS3: packed union { + raw: u1, + value: PDS, + }, + reserved4: u1, + /// SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in CR1. + SRAM2PDS1: packed union { + raw: u1, + value: PDS, + }, + /// SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in CR1. + SRAM2PDS2: packed union { + raw: u1, + value: PDS, + }, + /// SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3) + SRAM4PDS: packed union { + raw: u1, + value: PDS, + }, + reserved8: u1, + /// ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3) + ICRAMPDS: packed union { + raw: u1, + value: PDS, + }, + /// DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3) + DC1RAMPDS: packed union { + raw: u1, + value: PDS, + }, + /// DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3) + DMA2DRAMPDS: packed union { + raw: u1, + value: PDS, + }, + /// FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop0,1,2,3) + PRAMPDS: packed union { + raw: u1, + value: PDS, + }, + /// PKA SRAM power-down + PKARAMPDS: packed union { + raw: u1, + value: PDS, + }, + /// SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes. + SRAM4FWU: packed union { + raw: u1, + value: SRAMFWU, + }, + /// Flash memory fast wakeup from Stop 0 and Stop 1 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption. + FLASHFWU: packed union { + raw: u1, + value: FLASHFWU, + }, + reserved16: u1, + /// SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + SRAM3PDS1: packed union { + raw: u1, + value: PDS, + }, + /// SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + SRAM3PDS2: packed union { + raw: u1, + value: PDS, + }, + /// SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + SRAM3PDS3: packed union { + raw: u1, + value: PDS, + }, + /// SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + SRAM3PDS4: packed union { + raw: u1, + value: PDS, + }, + /// SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + SRAM3PDS5: packed union { + raw: u1, + value: PDS, + }, + /// SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + SRAM3PDS6: packed union { + raw: u1, + value: PDS, + }, + /// SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + SRAM3PDS7: packed union { + raw: u1, + value: PDS, + }, + /// SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + SRAM3PDS8: packed union { + raw: u1, + value: PDS, + }, + reserved31: u7, + /// SmartRun domain in Run mode + SRDRUN: u1, + }), + /// control register 3 + CR3: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Regulator selection Note: REGSEL is reserved and must be kept at reset value in packages without SMPS. + REGSEL: packed union { + raw: u1, + value: REGSEL, + }, + /// Fast soft start + FSTEN: u1, + padding: u29, + }), + /// voltage scaling register + VOSR: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set. + BOOSTRDY: u1, + /// Ready bit for VCORE voltage scaling output selection + VOSRDY: u1, + /// Voltage scaling range selection This field is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1. + VOS: packed union { + raw: u2, + value: VOS, + }, + /// EPOD booster enable + BOOSTEN: u1, + padding: u13, + }), + /// supply voltage monitoring control register + SVMCR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Power voltage detector enable + PVDE: u1, + /// Power voltage detector level selection These bits select the voltage threshold detected by the power voltage detector: + PVDLS: packed union { + raw: u3, + value: PVDLS, + }, + reserved24: u16, + /// VDDUSB independent USB voltage monitor enable + UVMEN: u1, + /// VDDIO2 independent I/Os voltage monitor enable + IO2VMEN: u1, + /// VDDA independent analog supply voltage monitor 1 enable (1.6V threshold) + AVM1EN: u1, + /// VDDA independent analog supply voltage monitor 2 enable (1.8V threshold) + AVM2EN: u1, + /// VDDUSB independent USB supply valid + USV: u1, + /// VDDIO2 independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not. + IO2SV: u1, + /// VDDA independent analog supply valid + ASV: u1, + padding: u1, + }), + /// wakeup control register 1 + WUCR1: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP1 enable + WUPEN: u1, + padding: u31, + }), + /// wakeup control register 2 + WUCR2: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. + WUPP: packed union { + raw: u1, + value: WUPP, + }, + padding: u31, + }), + /// wakeup control register 3 + WUCR3: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP1 selection This field must be configured when WUPEN1 = 0. + WUSEL1: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup pin WKUP2 selection This field must be configured when WUPEN2 = 0. + WUSEL2: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup pin WKUP3 selection This field must be configured when WUPEN3 = 0. + WUSEL3: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup pin WKUP4 selection This field must be configured when WUPEN4 = 0. + WUSEL4: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup pin WKUP5 selection This field must be configured when WUPEN5 = 0. + WUSEL5: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup pin WKUP6 selection This field must be configured when WUPEN6 = 0. + WUSEL6: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup pin WKUP7 selection This field must be configured when WUPEN7 = 0. + WUSEL7: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup pin WKUP8 selection This field must be configured when WUPEN8 = 0. + WUSEL8: packed union { + raw: u2, + value: WUSEL, + }, + padding: u16, + }), + /// Backup domain control register 1 + BDCR1: mmio.Mmio(packed struct(u32) { + /// Backup RAM retention in Standby and VBAT modes When this bit is set, the backup RAM content is kept in Standby and VBAT modes. If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS. Note: Backup RAM cannot be preserved in Shutdown mode. + BREN: u1, + reserved4: u3, + /// Backup domain voltage and temperature monitoring enable + MONEN: u1, + padding: u27, + }), + /// Backup domain control register 2 + BDCR2: mmio.Mmio(packed struct(u32) { + /// VBAT charging enable + VBE: packed union { + raw: u1, + value: VBE, + }, + /// VBAT charging resistor selection + VBRS: packed union { + raw: u1, + value: VBRS, }, padding: u30, }), - reserved44: [4]u8, - /// Background Color Configuration Register - BCCR: mmio.Mmio(packed struct(u32) { - /// Background color blue value - BCBLUE: u8, - /// Background color green value - BCGREEN: u8, - /// Background color red value - BCRED: u8, - padding: u8, + /// disable Backup domain register + DBPCR: mmio.Mmio(packed struct(u32) { + /// Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers. + DBP: u1, + padding: u31, }), - reserved52: [4]u8, - /// Interrupt Enable Register - IER: mmio.Mmio(packed struct(u32) { - /// Line Interrupt Enable - LIE: u1, - /// FIFO Underrun Interrupt Enable - FUIE: u1, - /// Transfer Error Interrupt Enable - TERRIE: u1, - /// Register Reload interrupt enable - RRIE: u1, - padding: u28, + /// USB Type-C™ and Power Delivery register + UCPDR: mmio.Mmio(packed struct(u32) { + /// UCPD dead battery disable After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable). + UCPD_DBDIS: u1, + /// UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers. + UCPD_STBY: u1, + padding: u30, }), - /// Interrupt Status Register - ISR: mmio.Mmio(packed struct(u32) { - /// Line Interrupt flag - LIF: u1, - /// FIFO Underrun Interrupt flag - FUIF: u1, - /// Transfer Error interrupt flag - TERRIF: u1, - /// Register Reload Interrupt Flag - RRIF: u1, - padding: u28, + /// security configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// WUP1 secure protection + WUP1SEC: u1, + reserved12: u11, + /// Low-power modes secure protection + LPMSEC: u1, + /// Voltage detection and monitoring secure protection + VDMSEC: u1, + /// Backup domain secure protection + VBSEC: u1, + /// Pull-up/pull-down secure protection + APCSEC: u1, + padding: u16, }), - /// Interrupt Clear Register - ICR: mmio.Mmio(packed struct(u32) { - /// Clears the Line Interrupt Flag - CLIF: packed union { + /// privilege control register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// secure functions privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access. + SPRIV: u1, + /// non-secure functions privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. + NSPRIV: u1, + padding: u30, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Clear Stop and Standby flags This bit is protected against non-secure access when LPMSEC=1 in SECCFGR. This bit is protected against unprivileged access when LPMSEC=1 and SPRIV=1 in PRIVCFGR, or when LPMSEC=0 and NSPRIV=1. Writing 1 to this bit clears the STOPF and SBF flags. + CSSF: u1, + /// Stop flag This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit. + STOPF: u1, + /// Standby flag This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset. + SBF: u1, + padding: u29, + }), + SVMSR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Regulator selection + REGS: packed union { raw: u1, - value: CLIF, + value: REGSEL, }, - /// Clears the FIFO Underrun Interrupt flag - CFUIF: packed union { + reserved4: u2, + /// VDD voltage detector output + PVDO: packed union { raw: u1, - value: CFUIF, + value: PVDO, }, - /// Clears the Transfer Error Interrupt Flag - CTERRIF: packed union { + reserved15: u10, + /// Voltage level ready for currently used VOS + ACTVOSRDY: u1, + /// VOS currently applied to VCORE This field provides the last VOS value. + ACTVOS: packed union { + raw: u2, + value: ACTVOS, + }, + reserved24: u6, + /// VDDUSB ready + VDDUSBRDY: u1, + /// VDDIO2 ready + VDDIO2RDY: u1, + /// VDDA ready versus 1.6V voltage monitor + VDDA1RDY: u1, + /// VDDA ready versus 1.8V voltage monitor + VDDA2RDY: u1, + padding: u4, + }), + /// Backup domain status register + BDSR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Backup domain voltage level monitoring versus high threshold + VBATH: packed union { raw: u1, - value: CTERRIF, + value: VBATH, }, - /// Clears Register Reload Interrupt Flag - CRRIF: packed union { + /// Temperature level monitoring versus low threshold + TEMPL: packed union { raw: u1, - value: CRRIF, + value: TEMPL, + }, + /// Temperature level monitoring versus high threshold + TEMPH: packed union { + raw: u1, + value: TEMPH, }, padding: u28, }), - /// Line Interrupt Position Configuration Register - LIPCR: mmio.Mmio(packed struct(u32) { - /// Line Interrupt Position - LIPOS: u11, - padding: u21, + /// wakeup status register + WUSR: mmio.Mmio(packed struct(u32) { + /// Wakeup flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1=0. + WUF1: u1, + /// Wakeup flag 2 This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2=0. + WUF2: u1, + /// Wakeup flag 3 This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3=0. + WUF3: u1, + /// Wakeup flag 4 This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4=0. + WUF4: u1, + /// Wakeup flag 5 This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5=0. + WUF5: u1, + /// Wakeup flag 6 This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6=0. If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared. + WUF6: u1, + /// Wakeup flag 7 This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7=0. If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared. + WUF7: u1, + /// Wakeup flag 8 This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8=0. If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared. + WUF8: u1, + padding: u24, }), - /// Current Position Status Register - CPSR: mmio.Mmio(packed struct(u32) { - /// Current Y Position - CYPOS: u16, - /// Current X Position - CXPOS: u16, + /// wakeup status clear register + WUSCR: mmio.Mmio(packed struct(u32) { + /// Wakeup flag 1 Writing 1 to this bit clears the WUF1 flag in WUSR. + CWUF1: u1, + /// Wakeup flag 2 Writing 1 to this bit clears the WUF2 flag in WUSR. + CWUF2: u1, + /// Wakeup flag 3 Writing 1 to this bit clears the WUF3 flag in WUSR. + CWUF3: u1, + /// Wakeup flag 4 Writing 1 to this bit clears the WUF4 flag in WUSR. + CWUF4: u1, + /// Wakeup flag 5 Writing 1 to this bit clears the WUF5 flag in WUSR. + CWUF5: u1, + /// Wakeup flag 6 Writing 1 to this bit clears the WUF6 flag in WUSR. + CWUF6: u1, + /// Wakeup flag 7 Writing 1 to this bit clears the WUF7 flag in WUSR. + CWUF7: u1, + /// Wakeup flag 8 Writing 1 to this bit clears the WUF8 flag in WUSR. + CWUF8: u1, + padding: u24, }), - /// Current Display Status Register - CDSR: mmio.Mmio(packed struct(u32) { - /// Vertical Data Enable display Status - VDES: u1, - /// Horizontal Data Enable display Status - HDES: u1, - /// Vertical Synchronization display Status - VSYNCS: u1, - /// Horizontal Synchronization display Status - HSYNCS: u1, - padding: u28, + /// apply pull configuration register + APCR: mmio.Mmio(packed struct(u32) { + /// Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PUCRx and PDCRx are applied. When this bit is cleared, PUCRx and PDCRx are not applied to the I/Os. + APC: u1, + padding: u31, + }), + /// Power Port pull-up control register + PUCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, + padding: u31, + }), + /// Power Port pull-down control register + PDCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, + padding: u31, }), - reserved132: [56]u8, - /// Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR - LAYER: u32, }; }; - pub const flash_l1 = struct { - /// Flash - pub const FLASH = extern struct { - /// Access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: u1, - /// Prefetch enable - PRFTEN: u1, - /// 64-bit access - ACC64: u1, - /// Flash mode during Sleep - SLEEP_PD: u1, - /// Flash mode during Run - RUN_PD: u1, - padding: u27, + pub const pwr_wb = struct { + /// Power control + pub const PWR = extern struct { + /// Power control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection for CPU1 + LPMS: u3, + reserved4: u1, + /// Flash power down mode during LPRun for CPU1 + FPDR: u1, + /// Flash power down mode during LPsSleep for CPU1 + FPDS: u1, + reserved8: u2, + /// Disable backup domain write protection + DBP: u1, + reserved14: u5, + /// Low-power run + LPR: u1, + padding: u17, }), - /// Program/erase control register - PECR: mmio.Mmio(packed struct(u32) { - /// FLASH_PECR and data EEPROM lock - PELOCK: u1, - /// Program memory lock - PRGLOCK: u1, - /// Option bytes block lock - OPTLOCK: u1, - /// Program memory selection - PROG: u1, - /// Data EEPROM selection - DATA: u1, - reserved8: u3, - /// Fixed time data write for Byte, Half Word and Word programming - FTDW: u1, - /// Page or Double Word erase mode - ERASE: u1, - /// Half Page/Double Word programming mode - FPRG: u1, - reserved15: u4, - /// Parallel bank mode - PARALLELBANK: u1, - /// End of programming interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// Launch the option byte loading - OBL_LAUNCH: u1, - padding: u13, + /// Power control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Power voltage detector enable + PVDE: u1, + /// Power voltage detector level selection + PLS: u3, + padding: u28, }), - /// Power down key register - PDKEYR: u32, - /// Program/erase key register - PEKEYR: u32, - /// Program memory key register - PRGKEYR: u32, - /// Option byte key register - OPTKEYR: u32, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Write/erase operations in progress - BSY: u1, - /// End of operation - EOP: u1, - /// End of high voltage - ENDHV: u1, - /// Flash memory module ready after low power mode - READY: u1, - reserved8: u4, - /// Write protected error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Size error - SIZERR: u1, - /// Option validity error - OPTVERR: u1, - /// Option UserValidity Error - OPTVERRUSR: u1, - padding: u19, + /// Power control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup pin + EWUP: u1, + reserved8: u7, + /// Enable BORH and Step Down counverter forced in Bypass interrups for CPU1 + EBORHSDFB: u1, + /// SRAM2a retention in Standby mode + RRS: u1, + /// Apply pull-up and pull-down configuration + APC: u1, + /// Enable BLE end of activity interrupt for CPU1 + EBLEA: u1, + /// Enable critical radio phase end of activity interrupt for CPU1 + ECRPE: u1, + /// Enable end of activity interrupt for CPU1 + E802A: u1, + /// Enable CPU2 Hold interrupt for CPU1 + EC2H: u1, + /// Enable internal wakeup line for CPU1 + EIWUL: u1, + padding: u16, }), - /// Option byte register - OBR: mmio.Mmio(packed struct(u32) { - /// Read protection - RDPRT: u8, - reserved16: u8, - /// BOR_LEV - BOR_LEV: u4, - /// IWDG_SW - IWDG_SW: u1, - /// nRTS_STOP - nRTS_STOP: u1, - /// nRST_STDBY - nRST_STDBY: u1, - /// Boot From Bank 2 - BFB2: u1, - padding: u8, + /// Power control register 4 + CR4: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP1 polarity + WP1: u1, + reserved8: u7, + /// VBAT battery charging enable + VBE: u1, + /// VBAT battery charging resistor selection + VBRS: u1, + reserved15: u5, + /// BOOT CPU2 after reset or wakeup from Stop or Standby modes + C2BOOT: u1, + padding: u16, }), - /// Write protection register - WRPR1: mmio.Mmio(packed struct(u32) { - /// Write protection - WRP1: u32, + /// Power status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Wakeup flag 1 + CWUF: u1, + reserved7: u6, + /// Step Down converter forced in Bypass interrupt flag + SDFBF: u1, + /// BORH interrupt flag + BORHF: u1, + /// BLE wakeup interrupt flag + BLEWUF: u1, + /// 802.15.4 wakeup interrupt flag + _802WUF: u1, + /// Enable critical radio phase end of activity interrupt flag + CRPEF: u1, + /// BLE end of activity interrupt flag + BLEAF: u1, + /// 802.15.4 end of activity interrupt flag + AF802: u1, + /// CPU2 Hold interrupt flag + C2HF: u1, + /// Internal Wakeup interrupt flag + WUFI: u1, + padding: u16, }), - reserved128: [92]u8, - /// Write protection register - WRPR2: mmio.Mmio(packed struct(u32) { - /// WRP2 - WRP2: u32, + /// Power status register 2 + SR2: mmio.Mmio(packed struct(u32) { + /// Step Down converter Bypass mode flag + SDBF: u1, + /// Step Down converter SMPS mode flag + SDSMPSF: u1, + reserved8: u6, + /// Low-power regulator started + REGLPS: u1, + /// Low-power regulator flag + REGLPF: u1, + /// Voltage scaling flag + VOSF: u1, + /// Power voltage detector output + PVDO: u1, + /// Peripheral voltage monitoring output: VDDUSB vs. 1.2 V + PVMO1: u1, + reserved14: u1, + /// Peripheral voltage monitoring output: VDDA vs. 1.62 V + PVMO3: u1, + padding: u17, }), - /// Write protection register - WRPR3: mmio.Mmio(packed struct(u32) { - /// WRP3 - WRP3: u32, + /// Power status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear wakeup flag 1 + CWUF: u1, + reserved7: u6, + /// Clear SMPS Step Down converter forced in Bypass interrupt flag + CSMPSFBF: u1, + /// Clear BORH interrupt flag + CBORHF: u1, + /// Clear BLE wakeup interrupt flag + CBLEWUF: u1, + /// Clear 802.15.4 wakeup interrupt flag + C802WUF: u1, + /// Clear critical radio phase end of activity interrupt flag + CCRPEF: u1, + /// Clear BLE end of activity interrupt flag + CBLEAF: u1, + /// Clear 802.15.4 end of activity interrupt flag + C802AF: u1, + /// Clear CPU2 Hold interrupt flag + CC2HF: u1, + padding: u17, }), - }; - }; - - pub const vrefintcal_v1 = struct { - /// VREFINT Factory Calibration - pub const VREFINTCAL = extern struct { - /// Factory calibration - DATA: u32, - }; - }; - - pub const syscfg_g4 = struct { - /// System configuration controller - pub const SYSCFG = extern struct { - /// Remap Memory register - MEMRMP: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection - MEM_MODE: u3, - reserved8: u5, - /// User Flash Bank mode - FB_mode: u1, - padding: u23, + /// Power control register 5 + CR5: mmio.Mmio(packed struct(u32) { + /// Step Down converter voltage output scaling + SDVOS: u4, + /// Step Down converter supplt startup current selection + SDSC: u3, + reserved8: u1, + /// BORH configuration selection + BORHC: u1, + /// VOS configuration selection (non user) + SMPSCFG: u1, + reserved14: u4, + /// Enable Step Down converter Bypass mode enabled + SDBEN: u1, + /// Enable Step Down converter SMPS mode enabled + SDEB: u1, + padding: u16, }), - /// peripheral mode configuration register - CFGR1: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// BOOSTEN - BOOSTEN: u1, - /// GPIO analog switch control voltage selection - ANASWVDD: u1, - reserved16: u6, - /// FM+ drive capability on PB6 - I2C_PB6_FMP: u1, - /// FM+ drive capability on PB6 - I2C_PB7_FMP: u1, - /// FM+ drive capability on PB6 - I2C_PB8_FMP: u1, - /// FM+ drive capability on PB6 - I2C_PB9_FMP: u1, - /// I2C1 FM+ drive capability enable - I2C1_FMP: u1, - /// I2C1 FM+ drive capability enable - I2C2_FMP: u1, - /// I2C1 FM+ drive capability enable - I2C3_FMP: u1, - /// I2C1 FM+ drive capability enable - I2C4_FMP: u1, - reserved26: u2, - /// FPU Interrupts Enable - FPU_IE: u6, + /// Power Port A pull-up control register + PUCRA: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, }), - /// external interrupt configuration register 1 - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration - EXTI: u4, - padding: u28, + /// Power Port A pull-down control register + PDCRA: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, }), - /// CCM SRAM control and status register - SCSR: mmio.Mmio(packed struct(u32) { - /// CCM SRAM Erase - CCMER: u1, - /// CCM SRAM busy by erase operation - CCMBSY: u1, - padding: u30, + /// Power Port B pull-up control register + PUCRB: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, }), - /// configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// Core Lockup Lock - CLL: u1, - /// SRAM Parity Lock - SPL: u1, - /// PVD Lock - PVDL: u1, - /// ECC Lock - ECCL: u1, - reserved8: u4, - /// SRAM Parity Flag - SPF: u1, - padding: u23, + /// Power Port B pull-down control register + PDCRB: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, }), - /// SRAM Write protection register 1 - SWPR: mmio.Mmio(packed struct(u32) { - /// Write protection - Page_WP: u1, + /// Power Port C pull-up control register + PUCRC: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, padding: u31, }), - /// SRAM2 Key Register - SKR: mmio.Mmio(packed struct(u32) { - /// SRAM2 Key for software erase - KEY: u8, - padding: u24, + /// Power Port C pull-down control register + PDCRC: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port D pull-up control register + PUCRD: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port D pull-down control register + PDCRD: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port E pull-up control register + PUCRE: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port E pull-down control register + PDCRE: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + reserved88: [16]u8, + /// Power Port H pull-up control register + PUCRH: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port H pull-down control register + PDCRH: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + reserved128: [32]u8, + /// CPU2 Power control register 1 + C2CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection for CPU2 + LPMS: u3, + reserved4: u1, + /// Flash power down mode during LPRun for CPU2 + FPDR: u1, + /// Flash power down mode during LPSleep for CPU2 + FPDS: u1, + reserved14: u8, + /// BLE external wakeup signal + BLEEWKUP: u1, + /// 802.15.4 external wakeup signal + _802EWKUP: u1, + padding: u16, + }), + /// CPU2 Power control register 3 + C2CR3: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup pin + EWUP: u1, + reserved9: u8, + /// Enable BLE host wakeup interrupt for CPU2 + EBLEWUP: u1, + /// Enable 802.15.4 host wakeup interrupt for CPU2 + E802WUP: u1, + reserved12: u1, + /// Apply pull-up and pull-down configuration for CPU2 + APC: u1, + reserved15: u2, + /// Enable internal wakeup line for CPU2 + EIWUL: u1, + padding: u16, + }), + /// Power status clear register + EXTSCR: mmio.Mmio(packed struct(u32) { + /// Clear CPU1 Stop Standby flags + C1CSSF: u1, + /// Clear CPU2 Stop Standby flags + C2CSSF: u1, + /// Clear Critical Radio system phase + CCRPF: u1, + reserved8: u5, + /// System Standby flag for CPU1 + C1SBF: u1, + /// System Stop flag for CPU1 + C1STOPF: u1, + /// System Standby flag for CPU2 + C2SBF: u1, + /// System Stop flag for CPU2 + C2STOPF: u1, + reserved13: u1, + /// Critical Radio system phase + CRPF: u1, + /// CPU1 deepsleep mode + C1DS: u1, + /// CPU2 deepsleep mode + C2DS: u1, + padding: u16, }), }; }; - pub const rcc_h7 = struct { - pub const ADCSEL = enum(u2) { - /// pll2_p selected as peripheral clock - PLL2_P = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// PER selected as peripheral clock - PER = 0x2, - _, - }; - - pub const CECSEL = enum(u2) { - /// LSE selected as peripheral clock - LSE = 0x0, - /// LSI selected as peripheral clock - LSI = 0x1, - /// csi_ker selected as peripheral clock - CSI = 0x2, - _, - }; - - pub const DFSDMSEL = enum(u1) { - /// rcc_pclk2 selected as peripheral clock - PCLK2 = 0x0, - /// System clock selected as peripheral clock - SYS = 0x1, - }; - - pub const DSISEL = enum(u1) { - /// DSI-PHY used as DSI byte lane clock source (usual case) - DSI_PHY = 0x0, - /// PLL2_Q used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode) - PLL2_Q = 0x1, - }; - - pub const FDCANSEL = enum(u2) { - /// HSE selected as peripheral clock - HSE = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x2, - _, - }; - - pub const FMCSEL = enum(u2) { - /// AHB3 selected as peripheral clock - HCLK3 = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// pll2_r selected as peripheral clock - PLL2_R = 0x2, - /// PER selected as peripheral clock - PER = 0x3, - }; - - pub const HPRE = enum(u4) { - /// sys_ck not divided - Div1 = 0x0, - /// sys_ck divided by 2 - Div2 = 0x8, - /// sys_ck divided by 4 - Div4 = 0x9, - /// sys_ck divided by 8 - Div8 = 0xa, - /// sys_ck divided by 16 - Div16 = 0xb, - /// sys_ck divided by 64 - Div64 = 0xc, - /// sys_ck divided by 128 - Div128 = 0xd, - /// sys_ck divided by 256 - Div256 = 0xe, - /// sys_ck divided by 512 - Div512 = 0xf, + pub const pwr_wb55 = struct { + pub const VOS = enum(u2) { + /// Range 1 + Range1 = 0x1, + /// Range 2 + Range2 = 0x2, _, }; - pub const HRTIMSEL = enum(u1) { - /// The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) - TIMY_KER = 0x0, - /// The HRTIM prescaler clock source is the CPU clock (c_ck) - C_CK = 0x1, - }; + /// Power control + pub const PWR = extern struct { + /// Power control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection for CPU1 + LPMS: u3, + reserved4: u1, + /// Flash power down mode during LPRun for CPU1 + FPDR: u1, + /// Flash power down mode during LPsSleep for CPU1 + FPDS: u1, + reserved8: u2, + /// Disable backup domain write protection + DBP: u1, + /// Voltage scaling range selection + VOS: packed union { + raw: u2, + value: VOS, + }, + reserved14: u3, + /// Low-power run + LPR: u1, + padding: u17, + }), + /// Power control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Power voltage detector enable + PVDE: u1, + /// Power voltage detector level selection + PLS: u3, + /// Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V + PVME1: u1, + reserved6: u1, + /// Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V + PVME3: u1, + reserved10: u3, + /// VDDUSB USB supply valid + USV: u1, + padding: u21, + }), + /// Power control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup pin + EWUP: u1, + reserved8: u7, + /// Enable BORH and Step Down counverter forced in Bypass interrups for CPU1 + EBORHSDFB: u1, + /// SRAM2a retention in Standby mode + RRS: u1, + /// Apply pull-up and pull-down configuration + APC: u1, + /// Enable BLE end of activity interrupt for CPU1 + EBLEA: u1, + /// Enable critical radio phase end of activity interrupt for CPU1 + ECRPE: u1, + /// Enable end of activity interrupt for CPU1 + E802A: u1, + /// Enable CPU2 Hold interrupt for CPU1 + EC2H: u1, + /// Enable internal wakeup line for CPU1 + EIWUL: u1, + padding: u16, + }), + /// Power control register 4 + CR4: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP1 polarity + WP1: u1, + reserved8: u7, + /// VBAT battery charging enable + VBE: u1, + /// VBAT battery charging resistor selection + VBRS: u1, + reserved15: u5, + /// BOOT CPU2 after reset or wakeup from Stop or Standby modes + C2BOOT: u1, + padding: u16, + }), + /// Power status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Wakeup flag 1 + CWUF: u1, + reserved7: u6, + /// Step Down converter forced in Bypass interrupt flag + SDFBF: u1, + /// BORH interrupt flag + BORHF: u1, + /// BLE wakeup interrupt flag + BLEWUF: u1, + /// 802.15.4 wakeup interrupt flag + _802WUF: u1, + /// Enable critical radio phase end of activity interrupt flag + CRPEF: u1, + /// BLE end of activity interrupt flag + BLEAF: u1, + /// 802.15.4 end of activity interrupt flag + AF802: u1, + /// CPU2 Hold interrupt flag + C2HF: u1, + /// Internal Wakeup interrupt flag + WUFI: u1, + padding: u16, + }), + /// Power status register 2 + SR2: mmio.Mmio(packed struct(u32) { + /// Step Down converter Bypass mode flag + SDBF: u1, + /// Step Down converter SMPS mode flag + SDSMPSF: u1, + reserved8: u6, + /// Low-power regulator started + REGLPS: u1, + /// Low-power regulator flag + REGLPF: u1, + /// Voltage scaling flag + VOSF: u1, + /// Power voltage detector output + PVDO: u1, + /// Peripheral voltage monitoring output: VDDUSB vs. 1.2 V + PVMO1: u1, + reserved14: u1, + /// Peripheral voltage monitoring output: VDDA vs. 1.62 V + PVMO3: u1, + padding: u17, + }), + /// Power status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear wakeup flag 1 + CWUF: u1, + reserved7: u6, + /// Clear SMPS Step Down converter forced in Bypass interrupt flag + CSMPSFBF: u1, + /// Clear BORH interrupt flag + CBORHF: u1, + /// Clear BLE wakeup interrupt flag + CBLEWUF: u1, + /// Clear 802.15.4 wakeup interrupt flag + C802WUF: u1, + /// Clear critical radio phase end of activity interrupt flag + CCRPEF: u1, + /// Clear BLE end of activity interrupt flag + CBLEAF: u1, + /// Clear 802.15.4 end of activity interrupt flag + C802AF: u1, + /// Clear CPU2 Hold interrupt flag + CC2HF: u1, + padding: u17, + }), + /// Power control register 5 + CR5: mmio.Mmio(packed struct(u32) { + /// Step Down converter voltage output scaling + SDVOS: u4, + /// Step Down converter supplt startup current selection + SDSC: u3, + reserved8: u1, + /// BORH configuration selection + BORHC: u1, + /// VOS configuration selection (non user) + SMPSCFG: u1, + reserved14: u4, + /// Enable Step Down converter Bypass mode enabled + SDBEN: u1, + /// Enable Step Down converter SMPS mode enabled + SDEB: u1, + padding: u16, + }), + /// Power Port A pull-up control register + PUCRA: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port A pull-down control register + PDCRA: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port B pull-up control register + PUCRB: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port B pull-down control register + PDCRB: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port C pull-up control register + PUCRC: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port C pull-down control register + PDCRC: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port D pull-up control register + PUCRD: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port D pull-down control register + PDCRD: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port E pull-up control register + PUCRE: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port E pull-down control register + PDCRE: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + reserved88: [16]u8, + /// Power Port H pull-up control register + PUCRH: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + /// Power Port H pull-down control register + PDCRH: mmio.Mmio(packed struct(u32) { + /// Port A pull-up/down bit y (y=0..15) + PD: u1, + padding: u31, + }), + reserved128: [32]u8, + /// CPU2 Power control register 1 + C2CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection for CPU2 + LPMS: u3, + reserved4: u1, + /// Flash power down mode during LPRun for CPU2 + FPDR: u1, + /// Flash power down mode during LPSleep for CPU2 + FPDS: u1, + reserved14: u8, + /// BLE external wakeup signal + BLEEWKUP: u1, + /// 802.15.4 external wakeup signal + _802EWKUP: u1, + padding: u16, + }), + /// CPU2 Power control register 3 + C2CR3: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup pin + EWUP: u1, + reserved9: u8, + /// Enable BLE host wakeup interrupt for CPU2 + EBLEWUP: u1, + /// Enable 802.15.4 host wakeup interrupt for CPU2 + E802WUP: u1, + reserved12: u1, + /// Apply pull-up and pull-down configuration for CPU2 + APC: u1, + reserved15: u2, + /// Enable internal wakeup line for CPU2 + EIWUL: u1, + padding: u16, + }), + /// Power status clear register + EXTSCR: mmio.Mmio(packed struct(u32) { + /// Clear CPU1 Stop Standby flags + C1CSSF: u1, + /// Clear CPU2 Stop Standby flags + C2CSSF: u1, + /// Clear Critical Radio system phase + CCRPF: u1, + reserved8: u5, + /// System Standby flag for CPU1 + C1SBF: u1, + /// System Stop flag for CPU1 + C1STOPF: u1, + /// System Standby flag for CPU2 + C2SBF: u1, + /// System Stop flag for CPU2 + C2STOPF: u1, + reserved13: u1, + /// Critical Radio system phase + CRPF: u1, + /// CPU1 deepsleep mode + C1DS: u1, + /// CPU2 deepsleep mode + C2DS: u1, + padding: u16, + }), + }; + }; - pub const HSIDIV = enum(u2) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x1, - /// Division by 4 - Div4 = 0x2, - /// Division by 8 - Div8 = 0x3, + pub const pwr_wba = struct { + pub const ACTVOS = enum(u1) { + /// Range 2 (lowest power) + Range2 = 0x0, + /// Range 1 (highest frequency) + Range1 = 0x1, }; - pub const I2C1235SEL = enum(u2) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// hsi_ker selected as peripheral clock - HSI = 0x2, - /// csi_ker selected as peripheral clock - CSI = 0x3, + pub const FLASHFWU = enum(u1) { + /// Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption). + LowPower = 0x0, + /// Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time). + Normal = 0x1, }; - pub const I2C4SEL = enum(u2) { - /// rcc_pclk4 selected as peripheral clock - PCLK4 = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// hsi_ker selected as peripheral clock - HSI = 0x2, - /// csi_ker selected as peripheral clock - CSI = 0x3, + pub const ICRAMPDS = enum(u1) { + /// ICACHE SRAM content retained in Stop modes + Retained = 0x0, + /// ICACHE SRAM content lost in Stop modes + NotRetained = 0x1, }; - pub const LPTIM1SEL = enum(u3) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_r selected as peripheral clock - PLL3_R = 0x2, - /// LSE selected as peripheral clock - LSE = 0x3, - /// LSI selected as peripheral clock - LSI = 0x4, - /// PER selected as peripheral clock - PER = 0x5, + pub const LPMS = enum(u3) { + /// Stop 0 mode + Stop0 = 0x0, + /// Stop 1 mode + Stop1 = 0x1, _, }; - pub const LPTIM2SEL = enum(u3) { - /// rcc_pclk4 selected as peripheral clock - PCLK4 = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_r selected as peripheral clock - PLL3_R = 0x2, - /// LSE selected as peripheral clock - LSE = 0x3, - /// LSI selected as peripheral clock - LSI = 0x4, - /// PER selected as peripheral clock - PER = 0x5, + pub const MODE = enum(u2) { + /// 2.4 GHz RADIO deep sleep mode + DeepSleep = 0x0, + /// 2.4 GHz RADIO sleep mode + Sleep = 0x1, _, }; - pub const LPUARTSEL = enum(u3) { - /// rcc_pclk_d4 selected as peripheral clock - PCLK4 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, - _, + pub const PVDLS = enum(u3) { + /// VPVD0 around 2.0 V + v20 = 0x0, + /// VPVD1 around 2.2 V + v22 = 0x1, + /// VPVD2 around 2.4 V + v24 = 0x2, + /// VPVD3 around 2.5 V + v25 = 0x3, + /// VPVD4 around 2.6 V + v26 = 0x4, + /// VPVD5 around 2.8 V + v28 = 0x5, + /// VPVD6 around 2.9 V + v29 = 0x6, + /// External input analog voltage PVD_IN (compared internally to VREFINT) + pvd_in = 0x7, }; - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, + pub const PVDO = enum(u1) { + /// VDD is equal or above the PVD threshold selected by PVDLS[2:0]. + AboveOrEqual = 0x0, + /// VDD is below the PVD threshold selected by PVDLS[2:0]. + Below = 0x1, }; - pub const MCO1SEL = enum(u3) { - /// HSI selected for micro-controller clock output - HSI = 0x0, - /// LSE selected for micro-controller clock output - LSE = 0x1, - /// HSE selected for micro-controller clock output - HSE = 0x2, - /// pll1_q selected for micro-controller clock output - PLL1_Q = 0x3, - /// HSI48 selected for micro-controller clock output - HSI48 = 0x4, - _, + pub const SRAMPDS = enum(u1) { + /// SRAM1 content retained in Stop modes + PoweredOn = 0x0, + /// SRAM1 content lost in Stop modes + PoweredOff = 0x1, }; - pub const MCO2SEL = enum(u3) { - /// System clock selected for micro-controller clock output - SYS = 0x0, - /// pll2_p selected for micro-controller clock output - PLL2_P = 0x1, - /// HSE selected for micro-controller clock output - HSE = 0x2, - /// pll1_p selected for micro-controller clock output - PLL1_P = 0x3, - /// CSI selected for micro-controller clock output - CSI = 0x4, - /// LSI selected for micro-controller clock output - LSI = 0x5, - _, + pub const VOS = enum(u1) { + /// Range 2 (lowest power) + Range2 = 0x0, + /// Range 1 (highest frequency). + Range1 = 0x1, }; - pub const MCOPRE = enum(u4) { - /// Divide by 1 - Div1 = 0x1, - /// Divide by 2 - Div2 = 0x2, - /// Divide by 3 - Div3 = 0x3, - /// Divide by 4 - Div4 = 0x4, - /// Divide by 5 - Div5 = 0x5, - /// Divide by 6 - Div6 = 0x6, - /// Divide by 7 - Div7 = 0x7, - /// Divide by 8 - Div8 = 0x8, - /// Divide by 9 - Div9 = 0x9, - /// Divide by 10 - Div10 = 0xa, - /// Divide by 11 - Div11 = 0xb, - /// Divide by 12 - Div12 = 0xc, - /// Divide by 13 - Div13 = 0xd, - /// Divide by 14 - Div14 = 0xe, - /// Divide by 15 - Div15 = 0xf, - _, + pub const WUPP = enum(u1) { + /// Detection on high level (rising edge) + High = 0x0, + /// Detection on low level (falling edge) + Low = 0x1, }; - pub const PERSEL = enum(u2) { - /// HSI selected as peripheral clock - HSI = 0x0, - /// CSI selected as peripheral clock - CSI = 0x1, - /// HSE selected as peripheral clock - HSE = 0x2, - _, + pub const WUSEL = enum(u2) { + /// reserved + B_0x0 = 0x0, + /// WKUP3_1 + B_0x1 = 0x1, + /// WKUP3_2 + B_0x2 = 0x2, + /// reserved + B_0x3 = 0x3, }; - pub const PLLDIV = enum(u7) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, - Div17 = 0x10, - Div18 = 0x11, - Div19 = 0x12, - Div20 = 0x13, - Div21 = 0x14, - Div22 = 0x15, - Div23 = 0x16, - Div24 = 0x17, - Div25 = 0x18, - Div26 = 0x19, - Div27 = 0x1a, - Div28 = 0x1b, - Div29 = 0x1c, - Div30 = 0x1d, - Div31 = 0x1e, - Div32 = 0x1f, - Div33 = 0x20, - Div34 = 0x21, - Div35 = 0x22, - Div36 = 0x23, - Div37 = 0x24, - Div38 = 0x25, - Div39 = 0x26, - Div40 = 0x27, - Div41 = 0x28, - Div42 = 0x29, - Div43 = 0x2a, - Div44 = 0x2b, - Div45 = 0x2c, - Div46 = 0x2d, - Div47 = 0x2e, - Div48 = 0x2f, - Div49 = 0x30, - Div50 = 0x31, - Div51 = 0x32, - Div52 = 0x33, - Div53 = 0x34, - Div54 = 0x35, - Div55 = 0x36, - Div56 = 0x37, - Div57 = 0x38, - Div58 = 0x39, - Div59 = 0x3a, - Div60 = 0x3b, - Div61 = 0x3c, - Div62 = 0x3d, - Div63 = 0x3e, - Div64 = 0x3f, - Div65 = 0x40, - Div66 = 0x41, - Div67 = 0x42, - Div68 = 0x43, - Div69 = 0x44, - Div70 = 0x45, - Div71 = 0x46, - Div72 = 0x47, - Div73 = 0x48, - Div74 = 0x49, - Div75 = 0x4a, - Div76 = 0x4b, - Div77 = 0x4c, - Div78 = 0x4d, - Div79 = 0x4e, - Div80 = 0x4f, - Div81 = 0x50, - Div82 = 0x51, - Div83 = 0x52, - Div84 = 0x53, - Div85 = 0x54, - Div86 = 0x55, - Div87 = 0x56, - Div88 = 0x57, - Div89 = 0x58, - Div90 = 0x59, - Div91 = 0x5a, - Div92 = 0x5b, - Div93 = 0x5c, - Div94 = 0x5d, - Div95 = 0x5e, - Div96 = 0x5f, - Div97 = 0x60, - Div98 = 0x61, - Div99 = 0x62, - Div100 = 0x63, - Div101 = 0x64, - Div102 = 0x65, - Div103 = 0x66, - Div104 = 0x67, - Div105 = 0x68, - Div106 = 0x69, - Div107 = 0x6a, - Div108 = 0x6b, - Div109 = 0x6c, - Div110 = 0x6d, - Div111 = 0x6e, - Div112 = 0x6f, - Div113 = 0x70, - Div114 = 0x71, - Div115 = 0x72, - Div116 = 0x73, - Div117 = 0x74, - Div118 = 0x75, - Div119 = 0x76, - Div120 = 0x77, - Div121 = 0x78, - Div122 = 0x79, - Div123 = 0x7a, - Div124 = 0x7b, - Div125 = 0x7c, - Div126 = 0x7d, - Div127 = 0x7e, - Div128 = 0x7f, + /// Power control + pub const PWR = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection These bits select the low-power mode entered when the CPU enters the SleepDeep mode. 10x: Standby mode others reserved + LPMS: packed union { + raw: u3, + value: LPMS, + }, + reserved5: u2, + /// SRAM2 retention in Standby mode This bit is used to keep the SRAM2 content in Standby retention mode. + R2RSB1: u1, + reserved7: u1, + /// BOR0 ultra-low-power mode. This bit is used to reduce the consumption by configuring the BOR0 in discontinuous mode for Stop 1 and Standby modes. Discontinuous mode is only available when BOR levels 1 to 4 and PVD are disabled. Note: This bit must be set to reach the lowest power consumption in the low-power modes. Note: This bit must not be set together with autonomous peripherals using HSI as kernel clock. Note: When BOR level 1 to 4 or PVD is enabled continuous mode applies independent from ULPMEN. + ULPMEN: u1, + reserved9: u1, + /// 2.4 GHz RADIO SRAMs (RXTXRAM and Sequence RAM) and Sleep clock retention in Standby mode. This bit is used to keep the 2.4 GHz RADIO SRAMs content in Standby retention mode and the 2.4 GHz RADIO sleep timer counter operational. + RADIORSB: u1, + reserved12: u2, + /// SRAM1 retention in Standby mode This bit is used to keep the SRAM1 content in Standby retention mode. + R1RSB1: u1, + padding: u19, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// SRAM1 power-down in Stop modes (Stop 0, 1) Note: The SRAM1 retention in Standby mode is controlled by R1RSB1 bit in CR1. + SRAM1PDS1: packed union { + raw: u1, + value: SRAMPDS, + }, + reserved4: u3, + /// SRAM2 power-down in Stop modes (Stop 0, 1) Note: The SRAM2 retention in Standby mode is controlled by R2RSB1 bit in CR1. + SRAM2PDS1: packed union { + raw: u1, + value: SRAMPDS, + }, + reserved8: u3, + /// ICACHE SRAM power-down in Stop modes (Stop 0, 1) + ICRAMPDS: packed union { + raw: u1, + value: ICRAMPDS, + }, + reserved14: u5, + /// Flash memory fast wakeup from Stop modes (Stop 0, 1) This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption. + FLASHFWU: packed union { + raw: u1, + value: FLASHFWU, + }, + padding: u17, + }), + /// control register 3 + CR3: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Fast soft start + FSTEN: u1, + padding: u29, + }), + /// voltage scaling register + VOSR: mmio.Mmio(packed struct(u32) { + reserved15: u15, + /// Ready bit for VCORE voltage scaling output selection Set and cleared by hardware. When decreasing the voltage scaling range, VOSRDY must be one before increasing the SYSCLK frequency. + VOSRDY: u1, + /// Voltage scaling range selection Set a and cleared by software. Cleared by hardware when entering Stop 1 mode. Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + VOS: packed union { + raw: u1, + value: VOS, + }, + padding: u15, + }), + /// supply voltage monitoring control register + SVMCR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Programmable voltage detector enable + PVDE: u1, + /// Programmable voltage detector level selection These bits select the voltage threshold detected by the programmable voltage detector: + PVDLS: packed union { + raw: u3, + value: PVDLS, + }, + padding: u24, + }), + /// wakeup control register 1 + WUCR1: mmio.Mmio(packed struct(u32) { + /// Wakeup and interrupt pin WKUP1 enable Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + WUPEN: u1, + padding: u31, + }), + /// wakeup control register 2 + WUCR2: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + WUPP: packed union { + raw: u1, + value: WUPP, + }, + padding: u31, + }), + /// wakeup control register 3 + WUCR3: mmio.Mmio(packed struct(u32) { + /// Wakeup and interrupt pin WKUP1 selection This field must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + WUSEL1: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup and interrupt pin WKUP2 selection This field must be configured when WUPEN2 = 0. Access can be secured by WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + WUSEL2: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup and interrupt pin WKUP3 selection This field must be configured when WUPEN3 = 0. Access can be secured by WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + WUSEL3: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup and interrupt pin WKUP4 selection This field must be configured when WUPEN4 = 0. Access can be secured by WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + WUSEL4: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup and interrupt pin WKUP5 selection This field must be configured when WUPEN5 = 0. Access can be secured by WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + WUSEL5: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup and interrupt pin WKUP6 selection This field must be configured when WUPEN6 = 0. Access can be secured by WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + WUSEL6: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup and interrupt pin WKUP7 selection This field must be configured when WUPEN7 = 0. Access can be secured by WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + WUSEL7: packed union { + raw: u2, + value: WUSEL, + }, + /// Wakeup and interrupt pin WKUP8 selection This field must be configured when WUPEN8 = 0. Access can be secured by WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + WUSEL8: packed union { + raw: u2, + value: WUSEL, + }, + padding: u16, + }), + reserved40: [8]u8, + /// disable Backup domain register + DBPCR: mmio.Mmio(packed struct(u32) { + /// Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers. + DBP: u1, + padding: u31, + }), + reserved48: [4]u8, + /// security configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// WUP1 secure protection + WUP1SEC: u1, + reserved12: u11, + /// Low-power modes secure protection + LPMSEC: u1, + /// Voltage detection secure protection + VDMSEC: u1, + /// Backup domain secure protection + VBSEC: u1, + padding: u17, + }), + /// privilege control register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// secure functions privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access. + SPRIV: u1, + /// non-secure functions privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. + NSPRIV: u1, + padding: u30, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Clear Stop and Standby flags Access can be secured by LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the STOPF and SBF flags. + CSSF: u1, + /// Stop flag This bit is set by hardware when the device enters a Stop or Standby mode at the same time as the sysclk has been set by hardware to select HSI. It’s cleared by software by writing 1 to the CSSF bit and by hardware when SBF is set. + STOPF: u1, + /// Standby flag This bit is set by hardware when the device enters the Standby mode and the CPU restart from its reset vector. It’s cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset. + SBF: u1, + padding: u29, + }), + /// supply voltage monitoring status register + SVMSR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Programmable voltage detector output + PVDO: packed union { + raw: u1, + value: PVDO, + }, + reserved15: u10, + /// Voltage level ready for currently used VOS + ACTVOSRDY: u1, + /// VOS currently applied to VCORE This field provides the last VOS value. + ACTVOS: packed union { + raw: u1, + value: ACTVOS, + }, + padding: u15, + }), + reserved68: [4]u8, + /// wakeup status register + WUSR: mmio.Mmio(packed struct(u32) { + /// Wakeup and interrupt pending flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0. + WUF: u1, + padding: u31, + }), + /// wakeup status clear register + WUSCR: mmio.Mmio(packed struct(u32) { + /// Clear wakeup flag 1 Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the WUF1 flag in WUSR. + CWUF: u1, + padding: u31, + }), + reserved80: [4]u8, + /// port Standby IO retention enable register + IORETENR: mmio.Mmio(packed struct(u32) { + /// Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + EN: u1, + padding: u31, + }), + /// port Standby IO retention status register + IORETRA: mmio.Mmio(packed struct(u32) { + /// Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + RET: u1, + padding: u31, + }), + reserved256: [168]u8, + /// 2.4 GHz RADIO status and control register + RADIOSCR: mmio.Mmio(packed struct(u32) { + /// 2.4 GHz RADIO operating mode. 1x: 2.4 GHz RADIO active mode + MODE: packed union { + raw: u2, + value: MODE, + }, + /// 2.4 GHz RADIO PHY operating mode + PHYMODE: u1, + /// 2.4 GHz RADIO encryption function operating mode + ENCMODE: u1, + reserved8: u4, + /// 2.4 GHz RADIO VDDHPA control word. Bits [3:0] see Table 81: PA output power table format for definition. Bit [4] rf_event. + RFVDDHPA: u5, + reserved15: u2, + /// Ready bit for VDDHPA voltage level when selecting VDDRFPA input. Note: REGPARDYVDDRFPA does not allow to detect correct VDDHPA voltage level when request to lower the level. + REGPARDYVDDRFPA: u1, + padding: u16, + }), }; + }; - pub const PLLM = enum(u6) { - Div1 = 0x1, - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - Div16 = 0x10, - Div17 = 0x11, - Div18 = 0x12, - Div19 = 0x13, - Div20 = 0x14, - Div21 = 0x15, - Div22 = 0x16, - Div23 = 0x17, - Div24 = 0x18, - Div25 = 0x19, - Div26 = 0x1a, - Div27 = 0x1b, - Div28 = 0x1c, - Div29 = 0x1d, - Div30 = 0x1e, - Div31 = 0x1f, - Div32 = 0x20, - Div33 = 0x21, - Div34 = 0x22, - Div35 = 0x23, - Div36 = 0x24, - Div37 = 0x25, - Div38 = 0x26, - Div39 = 0x27, - Div40 = 0x28, - Div41 = 0x29, - Div42 = 0x2a, - Div43 = 0x2b, - Div44 = 0x2c, - Div45 = 0x2d, - Div46 = 0x2e, - Div47 = 0x2f, - Div48 = 0x30, - Div49 = 0x31, - Div50 = 0x32, - Div51 = 0x33, - Div52 = 0x34, - Div53 = 0x35, - Div54 = 0x36, - Div55 = 0x37, - Div56 = 0x38, - Div57 = 0x39, - Div58 = 0x3a, - Div59 = 0x3b, - Div60 = 0x3c, - Div61 = 0x3d, - Div62 = 0x3e, + pub const pwr_wl5 = struct { + pub const CDS = enum(u1) { + /// CPU is running or in sleep + RunningOrSleep = 0x0, + /// CPU is in Deep-Sleep + DeepSleep = 0x1, + }; + + pub const FPDR = enum(u1) { + /// Flash memory in Idle mode when system is in LPRun mode + Idle = 0x0, + /// Flash memory in Power-down mode when system is in LPRun mode + PowerDown = 0x1, + }; + + pub const FPDS = enum(u1) { + /// Flash memory in Idle mode when system is in LPSleep mode + Idle = 0x0, + /// Flash memory in Power-down mode when system is in LPSleep mode + PowerDown = 0x1, + }; + + pub const LPMS = enum(u3) { + /// Stop 0 mode + Stop0 = 0x0, + /// Stop 1 mode + Stop1 = 0x1, + /// Stop 2 mode + Stop2 = 0x2, + /// Standby mode + Standby = 0x3, + /// Shutdown mode + Shutdown = 0x4, _, }; - pub const PLLN = enum(u9) { - Mul4 = 0x3, - Mul5 = 0x4, - Mul6 = 0x5, - Mul7 = 0x6, - Mul8 = 0x7, - Mul9 = 0x8, - Mul10 = 0x9, - Mul11 = 0xa, - Mul12 = 0xb, - Mul13 = 0xc, - Mul14 = 0xd, - Mul15 = 0xe, - Mul16 = 0xf, - Mul17 = 0x10, - Mul18 = 0x11, - Mul19 = 0x12, - Mul20 = 0x13, - Mul21 = 0x14, - Mul22 = 0x15, - Mul23 = 0x16, - Mul24 = 0x17, - Mul25 = 0x18, - Mul26 = 0x19, - Mul27 = 0x1a, - Mul28 = 0x1b, - Mul29 = 0x1c, - Mul30 = 0x1d, - Mul31 = 0x1e, - Mul32 = 0x1f, - Mul33 = 0x20, - Mul34 = 0x21, - Mul35 = 0x22, - Mul36 = 0x23, - Mul37 = 0x24, - Mul38 = 0x25, - Mul39 = 0x26, - Mul40 = 0x27, - Mul41 = 0x28, - Mul42 = 0x29, - Mul43 = 0x2a, - Mul44 = 0x2b, - Mul45 = 0x2c, - Mul46 = 0x2d, - Mul47 = 0x2e, - Mul48 = 0x2f, - Mul49 = 0x30, - Mul50 = 0x31, - Mul51 = 0x32, - Mul52 = 0x33, - Mul53 = 0x34, - Mul54 = 0x35, - Mul55 = 0x36, - Mul56 = 0x37, - Mul57 = 0x38, - Mul58 = 0x39, - Mul59 = 0x3a, - Mul60 = 0x3b, - Mul61 = 0x3c, - Mul62 = 0x3d, - Mul63 = 0x3e, - Mul64 = 0x3f, - Mul65 = 0x40, - Mul66 = 0x41, - Mul67 = 0x42, - Mul68 = 0x43, - Mul69 = 0x44, - Mul70 = 0x45, - Mul71 = 0x46, - Mul72 = 0x47, - Mul73 = 0x48, - Mul74 = 0x49, - Mul75 = 0x4a, - Mul76 = 0x4b, - Mul77 = 0x4c, - Mul78 = 0x4d, - Mul79 = 0x4e, - Mul80 = 0x4f, - Mul81 = 0x50, - Mul82 = 0x51, - Mul83 = 0x52, - Mul84 = 0x53, - Mul85 = 0x54, - Mul86 = 0x55, - Mul87 = 0x56, - Mul88 = 0x57, - Mul89 = 0x58, - Mul90 = 0x59, - Mul91 = 0x5a, - Mul92 = 0x5b, - Mul93 = 0x5c, - Mul94 = 0x5d, - Mul95 = 0x5e, - Mul96 = 0x5f, - Mul97 = 0x60, - Mul98 = 0x61, - Mul99 = 0x62, - Mul100 = 0x63, - Mul101 = 0x64, - Mul102 = 0x65, - Mul103 = 0x66, - Mul104 = 0x67, - Mul105 = 0x68, - Mul106 = 0x69, - Mul107 = 0x6a, - Mul108 = 0x6b, - Mul109 = 0x6c, - Mul110 = 0x6d, - Mul111 = 0x6e, - Mul112 = 0x6f, - Mul113 = 0x70, - Mul114 = 0x71, - Mul115 = 0x72, - Mul116 = 0x73, - Mul117 = 0x74, - Mul118 = 0x75, - Mul119 = 0x76, - Mul120 = 0x77, - Mul121 = 0x78, - Mul122 = 0x79, - Mul123 = 0x7a, - Mul124 = 0x7b, - Mul125 = 0x7c, - Mul126 = 0x7d, - Mul127 = 0x7e, - Mul128 = 0x7f, - Mul129 = 0x80, - Mul130 = 0x81, - Mul131 = 0x82, - Mul132 = 0x83, - Mul133 = 0x84, - Mul134 = 0x85, - Mul135 = 0x86, - Mul136 = 0x87, - Mul137 = 0x88, - Mul138 = 0x89, - Mul139 = 0x8a, - Mul140 = 0x8b, - Mul141 = 0x8c, - Mul142 = 0x8d, - Mul143 = 0x8e, - Mul144 = 0x8f, - Mul145 = 0x90, - Mul146 = 0x91, - Mul147 = 0x92, - Mul148 = 0x93, - Mul149 = 0x94, - Mul150 = 0x95, - Mul151 = 0x96, - Mul152 = 0x97, - Mul153 = 0x98, - Mul154 = 0x99, - Mul155 = 0x9a, - Mul156 = 0x9b, - Mul157 = 0x9c, - Mul158 = 0x9d, - Mul159 = 0x9e, - Mul160 = 0x9f, - Mul161 = 0xa0, - Mul162 = 0xa1, - Mul163 = 0xa2, - Mul164 = 0xa3, - Mul165 = 0xa4, - Mul166 = 0xa5, - Mul167 = 0xa6, - Mul168 = 0xa7, - Mul169 = 0xa8, - Mul170 = 0xa9, - Mul171 = 0xaa, - Mul172 = 0xab, - Mul173 = 0xac, - Mul174 = 0xad, - Mul175 = 0xae, - Mul176 = 0xaf, - Mul177 = 0xb0, - Mul178 = 0xb1, - Mul179 = 0xb2, - Mul180 = 0xb3, - Mul181 = 0xb4, - Mul182 = 0xb5, - Mul183 = 0xb6, - Mul184 = 0xb7, - Mul185 = 0xb8, - Mul186 = 0xb9, - Mul187 = 0xba, - Mul188 = 0xbb, - Mul189 = 0xbc, - Mul190 = 0xbd, - Mul191 = 0xbe, - Mul192 = 0xbf, - Mul193 = 0xc0, - Mul194 = 0xc1, - Mul195 = 0xc2, - Mul196 = 0xc3, - Mul197 = 0xc4, - Mul198 = 0xc5, - Mul199 = 0xc6, - Mul200 = 0xc7, - Mul201 = 0xc8, - Mul202 = 0xc9, - Mul203 = 0xca, - Mul204 = 0xcb, - Mul205 = 0xcc, - Mul206 = 0xcd, - Mul207 = 0xce, - Mul208 = 0xcf, - Mul209 = 0xd0, - Mul210 = 0xd1, - Mul211 = 0xd2, - Mul212 = 0xd3, - Mul213 = 0xd4, - Mul214 = 0xd5, - Mul215 = 0xd6, - Mul216 = 0xd7, - Mul217 = 0xd8, - Mul218 = 0xd9, - Mul219 = 0xda, - Mul220 = 0xdb, - Mul221 = 0xdc, - Mul222 = 0xdd, - Mul223 = 0xde, - Mul224 = 0xdf, - Mul225 = 0xe0, - Mul226 = 0xe1, - Mul227 = 0xe2, - Mul228 = 0xe3, - Mul229 = 0xe4, - Mul230 = 0xe5, - Mul231 = 0xe6, - Mul232 = 0xe7, - Mul233 = 0xe8, - Mul234 = 0xe9, - Mul235 = 0xea, - Mul236 = 0xeb, - Mul237 = 0xec, - Mul238 = 0xed, - Mul239 = 0xee, - Mul240 = 0xef, - Mul241 = 0xf0, - Mul242 = 0xf1, - Mul243 = 0xf2, - Mul244 = 0xf3, - Mul245 = 0xf4, - Mul246 = 0xf5, - Mul247 = 0xf6, - Mul248 = 0xf7, - Mul249 = 0xf8, - Mul250 = 0xf9, - Mul251 = 0xfa, - Mul252 = 0xfb, - Mul253 = 0xfc, - Mul254 = 0xfd, - Mul255 = 0xfe, - Mul256 = 0xff, - Mul257 = 0x100, - Mul258 = 0x101, - Mul259 = 0x102, - Mul260 = 0x103, - Mul261 = 0x104, - Mul262 = 0x105, - Mul263 = 0x106, - Mul264 = 0x107, - Mul265 = 0x108, - Mul266 = 0x109, - Mul267 = 0x10a, - Mul268 = 0x10b, - Mul269 = 0x10c, - Mul270 = 0x10d, - Mul271 = 0x10e, - Mul272 = 0x10f, - Mul273 = 0x110, - Mul274 = 0x111, - Mul275 = 0x112, - Mul276 = 0x113, - Mul277 = 0x114, - Mul278 = 0x115, - Mul279 = 0x116, - Mul280 = 0x117, - Mul281 = 0x118, - Mul282 = 0x119, - Mul283 = 0x11a, - Mul284 = 0x11b, - Mul285 = 0x11c, - Mul286 = 0x11d, - Mul287 = 0x11e, - Mul288 = 0x11f, - Mul289 = 0x120, - Mul290 = 0x121, - Mul291 = 0x122, - Mul292 = 0x123, - Mul293 = 0x124, - Mul294 = 0x125, - Mul295 = 0x126, - Mul296 = 0x127, - Mul297 = 0x128, - Mul298 = 0x129, - Mul299 = 0x12a, - Mul300 = 0x12b, - Mul301 = 0x12c, - Mul302 = 0x12d, - Mul303 = 0x12e, - Mul304 = 0x12f, - Mul305 = 0x130, - Mul306 = 0x131, - Mul307 = 0x132, - Mul308 = 0x133, - Mul309 = 0x134, - Mul310 = 0x135, - Mul311 = 0x136, - Mul312 = 0x137, - Mul313 = 0x138, - Mul314 = 0x139, - Mul315 = 0x13a, - Mul316 = 0x13b, - Mul317 = 0x13c, - Mul318 = 0x13d, - Mul319 = 0x13e, - Mul320 = 0x13f, - Mul321 = 0x140, - Mul322 = 0x141, - Mul323 = 0x142, - Mul324 = 0x143, - Mul325 = 0x144, - Mul326 = 0x145, - Mul327 = 0x146, - Mul328 = 0x147, - Mul329 = 0x148, - Mul330 = 0x149, - Mul331 = 0x14a, - Mul332 = 0x14b, - Mul333 = 0x14c, - Mul334 = 0x14d, - Mul335 = 0x14e, - Mul336 = 0x14f, - Mul337 = 0x150, - Mul338 = 0x151, - Mul339 = 0x152, - Mul340 = 0x153, - Mul341 = 0x154, - Mul342 = 0x155, - Mul343 = 0x156, - Mul344 = 0x157, - Mul345 = 0x158, - Mul346 = 0x159, - Mul347 = 0x15a, - Mul348 = 0x15b, - Mul349 = 0x15c, - Mul350 = 0x15d, - Mul351 = 0x15e, - Mul352 = 0x15f, - Mul353 = 0x160, - Mul354 = 0x161, - Mul355 = 0x162, - Mul356 = 0x163, - Mul357 = 0x164, - Mul358 = 0x165, - Mul359 = 0x166, - Mul360 = 0x167, - Mul361 = 0x168, - Mul362 = 0x169, - Mul363 = 0x16a, - Mul364 = 0x16b, - Mul365 = 0x16c, - Mul366 = 0x16d, - Mul367 = 0x16e, - Mul368 = 0x16f, - Mul369 = 0x170, - Mul370 = 0x171, - Mul371 = 0x172, - Mul372 = 0x173, - Mul373 = 0x174, - Mul374 = 0x175, - Mul375 = 0x176, - Mul376 = 0x177, - Mul377 = 0x178, - Mul378 = 0x179, - Mul379 = 0x17a, - Mul380 = 0x17b, - Mul381 = 0x17c, - Mul382 = 0x17d, - Mul383 = 0x17e, - Mul384 = 0x17f, - Mul385 = 0x180, - Mul386 = 0x181, - Mul387 = 0x182, - Mul388 = 0x183, - Mul389 = 0x184, - Mul390 = 0x185, - Mul391 = 0x186, - Mul392 = 0x187, - Mul393 = 0x188, - Mul394 = 0x189, - Mul395 = 0x18a, - Mul396 = 0x18b, - Mul397 = 0x18c, - Mul398 = 0x18d, - Mul399 = 0x18e, - Mul400 = 0x18f, - Mul401 = 0x190, - Mul402 = 0x191, - Mul403 = 0x192, - Mul404 = 0x193, - Mul405 = 0x194, - Mul406 = 0x195, - Mul407 = 0x196, - Mul408 = 0x197, - Mul409 = 0x198, - Mul410 = 0x199, - Mul411 = 0x19a, - Mul412 = 0x19b, - Mul413 = 0x19c, - Mul414 = 0x19d, - Mul415 = 0x19e, - Mul416 = 0x19f, - Mul417 = 0x1a0, - Mul418 = 0x1a1, - Mul419 = 0x1a2, - Mul420 = 0x1a3, - Mul421 = 0x1a4, - Mul422 = 0x1a5, - Mul423 = 0x1a6, - Mul424 = 0x1a7, - Mul425 = 0x1a8, - Mul426 = 0x1a9, - Mul427 = 0x1aa, - Mul428 = 0x1ab, - Mul429 = 0x1ac, - Mul430 = 0x1ad, - Mul431 = 0x1ae, - Mul432 = 0x1af, - Mul433 = 0x1b0, - Mul434 = 0x1b1, - Mul435 = 0x1b2, - Mul436 = 0x1b3, - Mul437 = 0x1b4, - Mul438 = 0x1b5, - Mul439 = 0x1b6, - Mul440 = 0x1b7, - Mul441 = 0x1b8, - Mul442 = 0x1b9, - Mul443 = 0x1ba, - Mul444 = 0x1bb, - Mul445 = 0x1bc, - Mul446 = 0x1bd, - Mul447 = 0x1be, - Mul448 = 0x1bf, - Mul449 = 0x1c0, - Mul450 = 0x1c1, - Mul451 = 0x1c2, - Mul452 = 0x1c3, - Mul453 = 0x1c4, - Mul454 = 0x1c5, - Mul455 = 0x1c6, - Mul456 = 0x1c7, - Mul457 = 0x1c8, - Mul458 = 0x1c9, - Mul459 = 0x1ca, - Mul460 = 0x1cb, - Mul461 = 0x1cc, - Mul462 = 0x1cd, - Mul463 = 0x1ce, - Mul464 = 0x1cf, - Mul465 = 0x1d0, - Mul466 = 0x1d1, - Mul467 = 0x1d2, - Mul468 = 0x1d3, - Mul469 = 0x1d4, - Mul470 = 0x1d5, - Mul471 = 0x1d6, - Mul472 = 0x1d7, - Mul473 = 0x1d8, - Mul474 = 0x1d9, - Mul475 = 0x1da, - Mul476 = 0x1db, - Mul477 = 0x1dc, - Mul478 = 0x1dd, - Mul479 = 0x1de, - Mul480 = 0x1df, - Mul481 = 0x1e0, - Mul482 = 0x1e1, - Mul483 = 0x1e2, - Mul484 = 0x1e3, - Mul485 = 0x1e4, - Mul486 = 0x1e5, - Mul487 = 0x1e6, - Mul488 = 0x1e7, - Mul489 = 0x1e8, - Mul490 = 0x1e9, - Mul491 = 0x1ea, - Mul492 = 0x1eb, - Mul493 = 0x1ec, - Mul494 = 0x1ed, - Mul495 = 0x1ee, - Mul496 = 0x1ef, - Mul497 = 0x1f0, - Mul498 = 0x1f1, - Mul499 = 0x1f2, - Mul500 = 0x1f3, - Mul501 = 0x1f4, - Mul502 = 0x1f5, - Mul503 = 0x1f6, - Mul504 = 0x1f7, - Mul505 = 0x1f8, - Mul506 = 0x1f9, - Mul507 = 0x1fa, - Mul508 = 0x1fb, - Mul509 = 0x1fc, - Mul510 = 0x1fd, - Mul511 = 0x1fe, - Mul512 = 0x1ff, - _, - }; - - pub const PLLRGE = enum(u2) { - /// Frequency is between 1 and 2 MHz - Range1 = 0x0, - /// Frequency is between 2 and 4 MHz - Range2 = 0x1, - /// Frequency is between 4 and 8 MHz - Range4 = 0x2, - /// Frequency is between 8 and 16 MHz - Range8 = 0x3, - }; - - pub const PLLSRC = enum(u2) { - /// HSI selected as PLL clock - HSI = 0x0, - /// CSI selected as PLL clock - CSI = 0x1, - /// HSE selected as PLL clock - HSE = 0x2, - /// No clock sent to DIVMx dividers and PLLs - DISABLE = 0x3, - }; - - pub const PLLVCOSEL = enum(u1) { - /// VCO frequency range 192 to 836 MHz - WideVCO = 0x0, - /// VCO frequency range 150 to 420 MHz - MediumVCO = 0x1, - }; - - pub const PPRE = enum(u3) { - /// rcc_hclk not divided - Div1 = 0x0, - /// rcc_hclk divided by 2 - Div2 = 0x4, - /// rcc_hclk divided by 4 - Div4 = 0x5, - /// rcc_hclk divided by 8 - Div8 = 0x6, - /// rcc_hclk divided by 16 - Div16 = 0x7, - _, - }; - - pub const RNGSEL = enum(u2) { - /// HSI48 selected as peripheral clock - HSI48 = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// LSE selected as peripheral clock - LSE = 0x2, - /// LSI selected as peripheral clock - LSI = 0x3, - }; - - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, - }; - - pub const SAIASEL = enum(u3) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_p selected as peripheral clock - PLL3_P = 0x2, - /// i2s_ckin selected as peripheral clock - I2S_CKIN = 0x3, - /// PER selected as peripheral clock - PER = 0x4, - _, - }; - - pub const SAISEL = enum(u3) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_p selected as peripheral clock - PLL3_P = 0x2, - /// I2S_CKIN selected as peripheral clock - I2S_CKIN = 0x3, - /// PER selected as peripheral clock - PER = 0x4, - _, - }; - - pub const SDMMCSEL = enum(u1) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_r selected as peripheral clock - PLL2_R = 0x1, - }; - - pub const SPDIFRXSEL = enum(u2) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_r selected as peripheral clock - PLL2_R = 0x1, - /// pll3_r selected as peripheral clock - PLL3_R = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - }; - - pub const SPI45SEL = enum(u3) { - /// APB2 clock selected as peripheral clock - PCLK2 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// HSE selected as peripheral clock - HSE = 0x5, - _, - }; - - pub const SPI6SEL = enum(u3) { - /// rcc_pclk4 selected as peripheral clock - PCLK4 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// HSE selected as peripheral clock - HSE = 0x5, - _, - }; - - pub const STOPWUCK = enum(u1) { - /// HSI selected as wake up clock from system Stop - HSI = 0x0, - /// CSI selected as wake up clock from system Stop - CSI = 0x1, - }; - - pub const SW = enum(u3) { - /// HSI selected as system clock - HSI = 0x0, - /// CSI selected as system clock - CSI = 0x1, - /// HSE selected as system clock - HSE = 0x2, - /// PLL1 selected as system clock - PLL1_P = 0x3, - _, + pub const LPR = enum(u1) { + /// Voltage regulator in Main mode in Low-power run mode + MainMode = 0x0, + /// Voltage regulator in low-power mode in Low-power run mode + LowPowerMode = 0x1, }; - pub const SWPMISEL = enum(u1) { - /// pclk selected as peripheral clock - PCLK1 = 0x0, - /// hsi_ker selected as peripheral clock - HSI = 0x1, + pub const PLS = enum(u3) { + /// 2.0V + V2_0 = 0x0, + /// 2.2V + V2_2 = 0x1, + /// 2.4V + V2_4 = 0x2, + /// 2.5V + V2_5 = 0x3, + /// 2.6V + V2_6 = 0x4, + /// 2.8V + V2_8 = 0x5, + /// 2.9V + V2_9 = 0x6, + /// External input analog voltage PVD_IN (compared internally to VREFINT) + External = 0x7, }; - pub const TIMPRE = enum(u1) { - /// Timer kernel clock equal to 2x pclk by default - DefaultX2 = 0x0, - /// Timer kernel clock equal to 4x pclk by default - DefaultX4 = 0x1, + pub const SUBGHZSPINSSSEL = enum(u1) { + /// sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS functionality enabled) + SUBGHZSPICR = 0x0, + /// sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled) + LPTIM3 = 0x1, }; - pub const USART16910SEL = enum(u3) { - /// rcc_pclk2 selected as peripheral clock - PCLK2 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, - _, + pub const VBRS = enum(u1) { + /// VBAT charging through a 5 kΩ resistor + R5k = 0x0, + /// VBAT charging through a 1.5 kΩ resistor + R1_5k = 0x1, }; - pub const USART234578SEL = enum(u3) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, + pub const VOS = enum(u2) { + /// 1.2 V (range 1) + Range1 = 0x1, + /// 1.0 V (range 2) + Range2 = 0x2, _, }; - pub const USBSEL = enum(u2) { - /// Disable the kernel clock - DISABLE = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// HSI48 selected as peripheral clock - HSI48 = 0x3, + pub const WP = enum(u1) { + /// Detection on high level (rising edge) + RisingEdge = 0x0, + /// Detection on low level (falling edge) + FallingEdge = 0x1, }; - /// Reset and clock control - pub const RCC = extern struct { - /// clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal high-speed clock enable - HSION: u1, - /// High Speed Internal clock enable in Stop mode - HSIKERON: u1, - /// HSI clock ready flag - HSIRDY: u1, - /// HSI clock divider - HSIDIV: packed union { - raw: u2, - value: HSIDIV, - }, - /// HSI divider flag - HSIDIVF: u1, - reserved7: u1, - /// CSI clock enable - CSION: u1, - /// CSI clock ready flag - CSIRDY: u1, - /// CSI clock enable in Stop mode - CSIKERON: u1, - reserved12: u2, - /// RC48 clock enable - HSI48ON: u1, - /// RC48 clock ready flag - HSI48RDY: u1, - /// D1 domain clocks ready flag - D1CKRDY: u1, - /// D2 domain clocks ready flag - D2CKRDY: u1, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE clock bypass - HSEBYP: u1, - /// HSE Clock Security System enable - HSECSSON: u1, - reserved24: u4, - /// PLL1 enable - PLLON: u1, - /// PLL1 clock ready flag - PLLRDY: u1, - padding: u6, - }), - /// RCC HSI configuration register - HSICFGR: mmio.Mmio(packed struct(u32) { - /// HSI clock calibration - HSICAL: u12, - reserved24: u12, - /// HSI clock trimming - HSITRIM: u7, - padding: u1, - }), - /// RCC Clock Recovery RC Register - CRRCR: mmio.Mmio(packed struct(u32) { - /// Internal RC 48 MHz clock calibration - HSI48CAL: u10, - padding: u22, - }), - /// RCC CSI configuration register - CSICFGR: mmio.Mmio(packed struct(u32) { - /// CSI clock calibration - CSICAL: u9, - reserved24: u15, - /// CSI clock trimming - CSITRIM: u6, - padding: u2, - }), - /// RCC Clock Configuration Register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u3, - value: SW, - }, - /// System clock switch status - SWS: packed union { + /// Power control + pub const PWR = extern struct { + /// Power control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection for CPU1 + LPMS: packed union { raw: u3, - value: SW, - }, - /// System clock selection after a wake up from system Stop - STOPWUCK: packed union { - raw: u1, - value: STOPWUCK, + value: LPMS, }, - /// Kernel clock selection after a wake up from system Stop - STOPKERWUCK: packed union { + /// sub-GHz SPI NSS source select + SUBGHZSPINSSSEL: packed union { raw: u1, - value: STOPWUCK, + value: SUBGHZSPINSSSEL, }, - /// HSE division factor for RTC clock - RTCPRE: u6, - /// High Resolution Timer clock prescaler selection - HRTIMSEL: packed union { + /// Flash memory power down mode during LPRun for CPU1 + FPDR: packed union { raw: u1, - value: HRTIMSEL, + value: FPDR, }, - /// Timers clocks prescaler selection - TIMPRE: packed union { + /// Flash memory power down mode during LPSleep for CPU1 + FPDS: packed union { raw: u1, - value: TIMPRE, - }, - reserved18: u2, - /// MCO1 prescaler - MCO1PRE: packed union { - raw: u4, - value: MCOPRE, - }, - /// Micro-controller clock output 1 - MCO1SEL: packed union { - raw: u3, - value: MCO1SEL, - }, - /// MCO2 prescaler - MCO2PRE: packed union { - raw: u4, - value: MCOPRE, - }, - /// Micro-controller clock output 2 - MCO2SEL: packed union { - raw: u3, - value: MCO2SEL, - }, - }), - reserved24: [4]u8, - /// RCC Domain 1 Clock Configuration Register - D1CFGR: mmio.Mmio(packed struct(u32) { - /// D1 domain AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// D1 domain APB3 prescaler - D1PPRE: packed union { - raw: u3, - value: PPRE, - }, - reserved8: u1, - /// D1 domain Core prescaler - D1CPRE: packed union { - raw: u4, - value: HPRE, + value: FPDS, }, - padding: u20, - }), - /// RCC Domain 2 Clock Configuration Register - D2CFGR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// D2 domain APB1 prescaler - D2PPRE1: packed union { - raw: u3, - value: PPRE, + reserved8: u2, + /// Disable backup domain write protection + DBP: u1, + /// Voltage scaling range selection + VOS: packed union { + raw: u2, + value: VOS, }, - reserved8: u1, - /// D2 domain APB2 prescaler - D2PPRE2: packed union { - raw: u3, - value: PPRE, + reserved14: u3, + /// Low-power run + LPR: packed union { + raw: u1, + value: LPR, }, - padding: u21, + padding: u17, }), - /// RCC Domain 3 Clock Configuration Register - D3CFGR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// D3 domain APB4 prescaler - D3PPRE: packed union { + /// Power control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Power voltage detector enable + PVDE: u1, + /// Power voltage detector level selection. + PLS: packed union { raw: u3, - value: PPRE, + value: PLS, }, + reserved6: u2, + /// Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V + PVME: u1, padding: u25, }), - reserved40: [4]u8, - /// RCC PLLs Clock Source Selection Register - PLLCKSELR: mmio.Mmio(packed struct(u32) { - /// DIVMx and PLLs clock source selection - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - reserved4: u2, - /// Prescaler for PLL1 - DIVM: packed union { - raw: u6, - value: PLLM, - }, - padding: u22, + /// Power control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup pin WKUP1 for CPU1 + EWUP: u1, + reserved7: u6, + /// Ultra-low-power enable + EULPEN: u1, + /// Enable wakeup PVD for CPU1 + EWPVD: u1, + /// SRAM2 retention in Standby mode + RRS: u1, + /// Apply pull-up and pull-down configuration from CPU1 + APC: u1, + /// Enable Radio BUSY Wakeup from Standby for CPU1 + EWRFBUSY: u1, + reserved13: u1, + /// Wakeup for CPU1 + EWRFIRQ: u1, + /// nable CPU2 Hold interrupt for CPU1 + EC2H: u1, + /// Enable internal wakeup line for CPU1 + EIWUL: u1, + padding: u16, }), - /// RCC PLLs Configuration Register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// PLL1 fractional latch enable - PLLFRACEN: u1, - /// PLL1 VCO selection - PLLVCOSEL: packed union { + /// Power control register 4 + CR4: mmio.Mmio(packed struct(u32) { + /// Wakeup pin WKUP1 polarity + WP: packed union { raw: u1, - value: PLLVCOSEL, - }, - /// PLL1 input frequency range - PLLRGE: packed union { - raw: u2, - value: PLLRGE, - }, - reserved16: u12, - /// PLL1 DIVP divider output enable - DIVPEN: u1, - /// PLL1 DIVQ divider output enable - DIVQEN: u1, - /// PLL1 DIVR divider output enable - DIVREN: u1, - padding: u13, - }), - /// RCC PLL1 Dividers Configuration Register - PLLDIVR: mmio.Mmio(packed struct(u32) { - /// Multiplication factor for PLL1 VCO - PLLN: packed union { - raw: u9, - value: PLLN, - }, - /// PLL DIVP division factor - PLLP: packed union { - raw: u7, - value: PLLDIV, - }, - /// PLL DIVQ division factor - PLLQ: packed union { - raw: u7, - value: PLLDIV, + value: WP, }, - reserved24: u1, - /// PLL DIVR division factor - PLLR: packed union { - raw: u7, - value: PLLDIV, + reserved8: u7, + /// VBAT battery charging enable + VBE: u1, + /// VBAT battery charging resistor selection + VBRS: packed union { + raw: u1, + value: VBRS, }, - padding: u1, + reserved11: u1, + /// Wakeup Radio BUSY polarity + WRFBUSYP: u1, + reserved15: u3, + /// oot CPU2 after reset or wakeup from Stop or Standby modes. + C2BOOT: u1, + padding: u16, }), - /// RCC PLL1 Fractional Divider Register - PLLFRACR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Fractional part of the multiplication factor for PLL VCO - FRACN: u13, + /// Power status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Wakeup flag 1 + WUF: u1, + reserved8: u7, + /// Wakeup PVD flag + WPVDF: u1, + reserved11: u2, + /// Radio BUSY wakeup flag + WRFBUSYF: u1, + reserved14: u2, + /// PU2 Hold interrupt flag + C2HF: u1, + /// Internal wakeup interrupt flag + WUFI: u1, padding: u16, }), - reserved76: [20]u8, - /// RCC Domain 1 Kernel Clock Configuration Register - D1CCIPR: mmio.Mmio(packed struct(u32) { - /// FMC kernel clock source selection - FMCSEL: packed union { - raw: u2, - value: FMCSEL, - }, - reserved4: u2, - /// OCTOSPI kernel clock source selection - OCTOSPISEL: packed union { - raw: u2, - value: FMCSEL, - }, - reserved8: u2, - /// DSI clock source selection (not available on all chips) - DSISEL: packed union { - raw: u1, - value: DSISEL, - }, - reserved16: u7, - /// SDMMC kernel clock source selection - SDMMCSEL: packed union { + /// Power status register 2 + SR2: mmio.Mmio(packed struct(u32) { + /// PU2 boot/wakeup request source information + C2BOOTS: u1, + /// Radio BUSY signal status + RFBUSYS: u1, + /// Radio BUSY masked signal status + RFBUSYMS: u1, + /// SMPS ready flag + SMPSRDY: u1, + /// LDO ready flag + LDORDY: u1, + /// Radio end of life flag + RFEOLF: u1, + /// regulator2 low power flag + REGMRS: u1, + /// Flash ready + FLASHRDY: u1, + /// regulator1 started + REGLPS: u1, + /// regulator1 low power flag + REGLPF: u1, + /// Voltage scaling flag + VOSF: u1, + /// Power voltage detector output + PVDO: u1, + reserved14: u2, + /// Peripheral voltage monitoring output: VDDA vs. 1.62 V + PVMO: u1, + padding: u17, + }), + /// Power status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear wakeup flag 1 + CWUF: u1, + reserved8: u7, + /// Clear wakeup PVD interrupt flag + CWPVDF: u1, + reserved11: u2, + /// Clear wakeup Radio BUSY flag + CWRFBUSYF: u1, + reserved14: u2, + /// lear CPU2 Hold interrupt flag + CC2HF: u1, + padding: u17, + }), + /// Power control register 5 + CR5: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// Enable Radio End Of Life detector enabled + RFEOLEN: u1, + /// Enable SMPS Step Down converter SMPS mode enabled. + SMPSEN: u1, + padding: u16, + }), + /// Power Port pull-up control register + PUCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, + padding: u31, + }), + /// Power Port pull-down control register + PDCR: mmio.Mmio(packed struct(u32) { + /// Port pull bit y (y=0..15) + P: u1, + padding: u31, + }), + reserved128: [88]u8, + /// Power CPU2 control register 1 [dual core device only] + C2CR1: mmio.Mmio(packed struct(u32) { + /// Low-power mode selection for CPU2 + LPMS: u3, + reserved4: u1, + /// Flash memory power down mode during LPRun for CPU2 + FPDR: u1, + /// Flash memory power down mode during LPSleep for CPU2 + FPDS: u1, + padding: u26, + }), + /// Power CPU2 control register 3 [dual core device only] + C2CR3: mmio.Mmio(packed struct(u32) { + /// Enable Wakeup pin WKUP1 for CPU2 + EWUP: u1, + reserved8: u7, + /// Enable wakeup PVD for CPU2 + EWPVD: u1, + reserved10: u1, + /// Apply pull-up and pull-down configuration for CPU2 + APC: u1, + /// EWRFBUSY + EWRFBUSY: u1, + reserved13: u1, + /// akeup for CPU2 + EWRFIRQ: u1, + reserved15: u1, + /// Enable internal wakeup line for CPU2 + EIWUL: u1, + padding: u16, + }), + /// Power extended status and status clear register + EXTSCR: mmio.Mmio(packed struct(u32) { + /// Clear CPU1 Stop Standby flags + C1CSSF: u1, + /// lear CPU2 Stop Standby flags + C2CSSF: u1, + reserved8: u6, + /// System Standby flag for CPU1. (no core states retained) + C1SBF: u1, + /// System Stop2 flag for CPU1. (partial core states retained) + C1STOP2F: u1, + /// System Stop0, 1 flag for CPU1. (All core states retained) + C1STOPF: u1, + /// ystem Standby flag for CPU2. (no core states retained) + C2SBF: u1, + /// ystem Stop2 flag for CPU2. (partial core states retained) + C2STOP2F: u1, + /// ystem Stop0, 1 flag for CPU2. (All core states retained) + C2STOPF: u1, + /// CPU1 deepsleep mode + C1DS: packed union { raw: u1, - value: SDMMCSEL, - }, - reserved28: u11, - /// per_ck clock source selection - PERSEL: packed union { - raw: u2, - value: PERSEL, + value: CDS, }, - padding: u2, + /// PU2 deepsleep mode + C2DS: u1, + padding: u16, }), - /// RCC Domain 2 Kernel Clock Configuration Register - D2CCIP1R: mmio.Mmio(packed struct(u32) { - /// SAI1 and DFSDM1 kernel Aclk clock source selection - SAI1SEL: packed union { - raw: u3, - value: SAISEL, - }, - reserved6: u3, - /// SAI2 and SAI3 kernel clock source selection - SAI23SEL: packed union { - raw: u3, - value: SAISEL, - }, - reserved12: u3, - /// SPI/I2S1,2 and 3 kernel clock source selection - SPI123SEL: packed union { + /// Power security configuration register [dual core device only] + SECCFGR: mmio.Mmio(packed struct(u32) { + reserved15: u15, + /// wakeup on CPU2 illegal access interrupt enable + C2EWILA: u1, + padding: u16, + }), + /// Power SPI3 control register + SUBGHZSPICR: mmio.Mmio(packed struct(u32) { + reserved15: u15, + /// sub-GHz SPI NSS control + NSS: u1, + padding: u16, + }), + reserved152: [4]u8, + /// RSS Command register [dual core device only] + RSSCMDR: mmio.Mmio(packed struct(u32) { + /// RSS command + RSSCMD: u8, + padding: u24, + }), + }; + }; + + pub const quadspi_v1 = struct { + /// QuadSPI interface + pub const QUADSPI = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// Enable + EN: u1, + /// Abort request + ABORT: u1, + /// DMA enable (not available on all chips!) + DMAEN: u1, + /// Timeout counter enable + TCEN: u1, + /// Sample shift + SSHIFT: u1, + reserved6: u1, + /// Dual-flash mode + DFM: u1, + /// FLASH memory selection + FSEL: u1, + /// IFO threshold level + FTHRES: u4, + reserved16: u4, + /// Transfer error interrupt enable + TEIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// FIFO threshold interrupt enable + FTIE: u1, + /// Status match interrupt enable + SMIE: u1, + /// TimeOut interrupt enable + TOIE: u1, + reserved22: u1, + /// Automatic poll mode stop + APMS: u1, + /// Polling match mode + PMM: u1, + /// Clock prescaler + PRESCALER: u8, + }), + /// device configuration register + DCR: mmio.Mmio(packed struct(u32) { + /// Mode 0 / mode 3 + CKMODE: u1, + reserved8: u7, + /// Chip select high time + CSHT: u3, + reserved16: u5, + /// FLASH memory size + FSIZE: u5, + padding: u11, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Transfer error flag + TEF: u1, + /// Transfer complete flag + TCF: u1, + /// FIFO threshold flag + FTF: u1, + /// Status match flag + SMF: u1, + /// Timeout flag + TOF: u1, + /// Busy + BUSY: u1, + reserved8: u2, + /// FIFO level + FLEVEL: u7, + padding: u17, + }), + /// flag clear register + FCR: mmio.Mmio(packed struct(u32) { + /// Clear transfer error flag + CTEF: u1, + /// Clear transfer complete flag + CTCF: u1, + reserved3: u1, + /// Clear status match flag + CSMF: u1, + /// Clear timeout flag + CTOF: u1, + padding: u27, + }), + /// data length register + DLR: mmio.Mmio(packed struct(u32) { + /// Data length + DL: u32, + }), + /// communication configuration register + CCR: mmio.Mmio(packed struct(u32) { + /// Instruction + INSTRUCTION: u8, + /// Instruction mode + IMODE: u2, + /// Address mode + ADMODE: u2, + /// Address size + ADSIZE: u2, + /// Alternate bytes mode + ABMODE: u2, + /// Alternate bytes size + ABSIZE: u2, + /// Number of dummy cycles + DCYC: u5, + reserved24: u1, + /// Data mode + DMODE: u2, + /// Functional mode + FMODE: u2, + /// Send instruction only once mode + SIOO: u1, + /// Free-running clock mode (not available on all chips!) + FRCM: u1, + /// DDR hold half cycle + DHHC: u1, + /// Double data rate mode + DDRM: u1, + }), + /// address register + AR: mmio.Mmio(packed struct(u32) { + /// Address + ADDRESS: u32, + }), + /// ABR + ABR: mmio.Mmio(packed struct(u32) { + /// ALTERNATE + ALTERNATE: u32, + }), + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Data + DATA: u32, + }), + /// polling status mask register + PSMKR: mmio.Mmio(packed struct(u32) { + /// Status mask + MASK: u32, + }), + /// polling status match register + PSMAR: mmio.Mmio(packed struct(u32) { + /// Status match + MATCH: u32, + }), + /// polling interval register + PIR: mmio.Mmio(packed struct(u32) { + /// Polling interval + INTERVAL: u16, + padding: u16, + }), + /// low-power timeout register + LPTR: mmio.Mmio(packed struct(u32) { + /// Timeout period + TIMEOUT: u16, + padding: u16, + }), + }; + }; + + pub const rcc_c0 = struct { + pub const ADCSEL = enum(u2) { + /// System clock + SYS = 0x0, + /// HSIKER + HSIKER = 0x2, + _, + }; + + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK is divided by 2 + Div2 = 0x8, + /// SYSCLK is divided by 4 + Div4 = 0x9, + /// SYSCLK is divided by 8 + Div8 = 0xa, + /// SYSCLK is divided by 16 + Div16 = 0xb, + /// SYSCLK is divided by 64 + Div64 = 0xc, + /// SYSCLK is divided by 128 + Div128 = 0xd, + /// SYSCLK is divided by 256 + Div256 = 0xe, + /// SYSCLK is divided by 512 + Div512 = 0xf, + _, + }; + + pub const HSIDIV = enum(u3) { + /// HSI clock is not divided + Div1 = 0x0, + /// HSI clock is divided by 2 + Div2 = 0x1, + /// HSI clock is divided by 4 + Div4 = 0x2, + /// HSI clock is divided by 8 + Div8 = 0x3, + /// HSI clock is divided by 16 + Div16 = 0x4, + /// HSI clock is divided by 32 + Div32 = 0x5, + /// HSI clock is divided by 64 + Div64 = 0x6, + /// HSI clock is divided by 128 + Div128 = 0x7, + }; + + pub const HSIKERDIV = enum(u3) { + /// 1 + Div1 = 0x0, + /// 2 + Div2 = 0x1, + /// 3 (reset value) + Div3 = 0x2, + /// 4 + Div4 = 0x3, + /// 5 + Div5 = 0x4, + /// 6 + Div6 = 0x5, + /// 7 + Div7 = 0x6, + /// 8 + Div8 = 0x7, + }; + + pub const I2C1SEL = enum(u2) { + /// PCLK + PCLK1 = 0x0, + /// SYSCLK + SYS = 0x1, + /// HSIKER + HSIKER = 0x2, + _, + }; + + pub const I2S1SEL = enum(u2) { + /// SYSCLK + SYS = 0x0, + /// HSIKER + HSIKER = 0x2, + /// I2S_CKIN + I2S_CKIN = 0x3, + _, + }; + + pub const LSCOSEL = enum(u1) { + /// LSI + LSI = 0x0, + /// LSE + LSE = 0x1, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const MCOPRE = enum(u4) { + /// MCO2 not divided + Div1 = 0x0, + /// MCO clock is divided by 2 + Div2 = 0x1, + /// MCO clock is divided by 4 + Div4 = 0x2, + /// MCO clock is divided by 8 + Div8 = 0x3, + /// MCO clock is divided divided by 16 + Div16 = 0x4, + /// MCO clock is divided divided by 32 + Div32 = 0x5, + /// MCO clock is divided divided by 64 + Div64 = 0x6, + /// MCO clock is divided divided by 128 + Div128 = 0x7, + _, + }; + + pub const MCOSEL = enum(u4) { + /// No clock, MCO output disabled + DISABLE = 0x0, + /// SYSCLK selected as MCO source + SYS = 0x1, + /// HSI selected as MCO source + HSI = 0x3, + /// HSE selected as MCO source + HSE = 0x4, + /// LSI selected as MCO source + LSI = 0x6, + /// LSE selected as MCO source + LSE = 0x7, + _, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK is divided by 2 + Div2 = 0x4, + /// HCLK is divided by 4 + Div4 = 0x5, + /// HCLK is divided by 8 + Div8 = 0x6, + /// HCLK is divided by 16 + Div16 = 0x7, + _, + }; + + pub const RTCSEL = enum(u2) { + /// No clock used as RTC clock + DISABLE = 0x0, + /// LSE used as RTC clock + LSE = 0x1, + /// LSI used as RTC clock + LSI = 0x2, + /// HSE divided by 32 used as RTC clock + HSE_Div32 = 0x3, + }; + + pub const SW = enum(u3) { + /// HSISYS (HSI divided by HSIDIV) selected as system clock + HSISYS = 0x0, + /// HSE selected as system clock + HSE = 0x1, + /// LSI selected as system clock + LSI = 0x3, + /// LSE selected as system clock + LSE = 0x4, + _, + }; + + pub const USART1SEL = enum(u2) { + /// PCLK + PCLK1 = 0x0, + /// SYSCLK + SYS = 0x1, + /// HSIKER + HSIKER = 0x2, + /// LSE + LSE = 0x3, + }; + + /// RCC address block description + pub const RCC = extern struct { + /// RCC clock control register + CR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// HSI kernel clock division factor This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock: + HSIKERDIV: packed union { raw: u3, - value: SAISEL, + value: HSIKERDIV, }, - reserved16: u1, - /// SPI4 and 5 kernel clock source selection - SPI45SEL: packed union { + /// HSI clock enable Set and cleared by software and hardware, with hardware taking priority. Kept low by hardware as long as the device is in a low-power mode. Kept high by hardware as long as the system is clocked with a clock derived from HSI. This includes the exit from low-power modes and the system clock fall-back to HSI upon failing HSE oscillator clock selected as system clock source. + HSION: u1, + /// HSI always-enable for peripheral kernels. Set and cleared by software. Setting the bit activates the HSI oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI as kernel clock. Note: Keeping the HSI active in Stop mode allows speeding up the serial interface communication as the HSI clock is ready immediately upon exiting Stop mode. + HSIKERON: u1, + /// HSI clock ready flag Set by hardware when the HSI oscillator is enabled through HSION and ready to use (stable). Note: Upon clearing HSION, HSIRDY goes low after six HSI clock cycles. + HSIRDY: u1, + /// HSI clock division factor This bitfield controlled by software sets the division factor of the HSI clock divider to produce HSISYS clock: + HSIDIV: packed union { raw: u3, - value: SPI45SEL, - }, - reserved20: u1, - /// SPDIFRX kernel clock source selection - SPDIFRXSEL: packed union { - raw: u2, - value: SPDIFRXSEL, - }, - reserved24: u2, - /// DFSDM1 kernel Clk clock source selection - DFSDM1SEL: packed union { - raw: u1, - value: DFSDMSEL, - }, - reserved28: u3, - /// FDCAN kernel clock source selection - FDCANSEL: packed union { - raw: u2, - value: FDCANSEL, - }, - reserved31: u1, - /// SWPMI kernel clock source selection - SWPMISEL: packed union { - raw: u1, - value: SWPMISEL, + value: HSIDIV, }, + reserved16: u2, + /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock. + HSEON: u1, + /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable and ready for use. Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles. + HSERDY: u1, + /// HSE crystal oscillator bypass Set and cleared by software. When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled. + HSEBYP: u1, + /// Clock security system enable Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset. + CSSON: u1, + padding: u12, }), - /// RCC Domain 2 Kernel Clock Configuration Register - D2CCIP2R: mmio.Mmio(packed struct(u32) { - /// USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection - USART234578SEL: packed union { + /// RCC internal clock source calibration register + ICSCR: mmio.Mmio(packed struct(u32) { + /// HSI clock calibration This bitfield directly acts on the HSI clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI calibration accuracy and for the frequency trimming granularity. Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64. + HSICAL: u8, + /// HSI clock trimming The value of this bitfield contributes to the HSICAL[7:0] bitfield value. It allows HSI clock frequency user trimming. The HSI frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value. + HSITRIM: u7, + padding: u17, + }), + /// RCC clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected. + SW: packed union { raw: u3, - value: USART234578SEL, + value: SW, }, - /// USART1, 6, 9 and 10 kernel clock source selection - USART16910SEL: packed union { + /// System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved + SWS: packed union { raw: u3, - value: USART16910SEL, + value: SW, }, reserved8: u2, - /// RNG kernel clock source selection - RNGSEL: packed union { - raw: u2, - value: RNGSEL, - }, - reserved12: u2, - /// I2C1,2,3 kernel clock source selection - I2C1235SEL: packed union { - raw: u2, - value: I2C1235SEL, - }, - reserved20: u6, - /// USBOTG 1 and 2 kernel clock source selection - USBSEL: packed union { - raw: u2, - value: USBSEL, - }, - /// HDMI-CEC kernel clock source selection - CECSEL: packed union { - raw: u2, - value: CECSEL, - }, - reserved28: u4, - /// LPTIM1 kernel clock source selection - LPTIM1SEL: packed union { - raw: u3, - value: LPTIM1SEL, - }, - padding: u1, - }), - /// RCC Domain 3 Kernel Clock Configuration Register - D3CCIPR: mmio.Mmio(packed struct(u32) { - /// LPUART1 kernel clock source selection - LPUART1SEL: packed union { - raw: u3, - value: LPUARTSEL, - }, - reserved8: u5, - /// I2C4 kernel clock source selection - I2C4SEL: packed union { - raw: u2, - value: I2C4SEL, - }, - /// LPTIM2 kernel clock source selection - LPTIM2SEL: packed union { - raw: u3, - value: LPTIM2SEL, + /// AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1 + HPRE: packed union { + raw: u4, + value: HPRE, }, - /// LPTIM3,4,5 kernel clock source selection - LPTIM345SEL: packed union { + /// APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1 + PPRE: packed union { raw: u3, - value: LPTIM2SEL, + value: PPRE, }, - /// SAR ADC kernel clock source selection - ADCSEL: packed union { - raw: u2, - value: ADCSEL, + reserved16: u1, + /// Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching. + MCO2SEL: packed union { + raw: u4, + value: MCOSEL, }, - reserved21: u3, - /// Sub-Block A of SAI4 kernel clock source selection - SAI4ASEL: packed union { - raw: u3, - value: SAIASEL, + /// Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: ... It is highly recommended to set this field before the MCO2 output is enabled. + MCO2PRE: packed union { + raw: u4, + value: MCOPRE, }, - /// Sub-Block B of SAI4 kernel clock source selection - SAI4BSEL: packed union { - raw: u3, - value: SAIASEL, + /// Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO. + MCO1SEL: packed union { + raw: u4, + value: MCOSEL, }, - /// DFSDM2 kernel clock source selection - DFSDM2SEL: u1, - /// SPI6 kernel clock source selection - SPI6SEL: packed union { - raw: u3, - value: SPI6SEL, + /// Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: ... It is highly recommended to set this field before the MCO output is enabled. + MCO1PRE: packed union { + raw: u4, + value: MCOPRE, }, - padding: u1, }), - reserved96: [4]u8, - /// RCC Clock Source Interrupt Enable Register + reserved24: [12]u8, + /// RCC clock interrupt enable register CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready Interrupt Enable + /// LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization: LSIRDYIE: u1, - /// LSE ready Interrupt Enable + /// LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization: LSERDYIE: u1, - /// HSI ready Interrupt Enable + reserved3: u1, + /// HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization: HSIRDYIE: u1, - /// HSE ready Interrupt Enable + /// HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization: HSERDYIE: u1, - /// CSI ready Interrupt Enable - CSIRDYIE: u1, - /// RC48 ready Interrupt Enable - HSI48RDYIE: u1, - /// PLL1 ready Interrupt Enable - PLLRDYIE: u1, - reserved9: u2, - /// LSE clock security system Interrupt Enable - LSECSSIE: u1, - padding: u22, + padding: u27, }), - /// RCC Clock Source Interrupt Flag Register + /// RCC clock interrupt flag register CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready Interrupt Flag + /// LSI ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. LSIRDYF: u1, - /// LSE ready Interrupt Flag + /// LSE ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. LSERDYF: u1, - /// HSI ready Interrupt Flag + reserved3: u1, + /// HSI ready interrupt flag This flag indicates a pending interrupt upon HSI clock getting ready. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. HSIRDYF: u1, - /// HSE ready Interrupt Flag + /// HSE ready interrupt flag This flag indicates a pending interrupt upon HSE clock getting ready. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit. HSERDYF: u1, - /// CSI ready Interrupt Flag - CSIRDY: u1, - /// RC48 ready Interrupt Flag - HSI48RDYF: u1, - /// PLL1 ready Interrupt Flag - PLLRDYF: u1, - reserved9: u2, - /// LSE clock security system Interrupt Flag + reserved8: u3, + /// HSE clock security system interrupt flag This flag indicates a pending interrupt upon HSE clock failure. Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. + CSSF: u1, + /// LSE clock security system interrupt flag This flag indicates a pending interrupt upon LSE clock failure. Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit. LSECSSF: u1, - /// HSE clock security system Interrupt Flag - HSECSSF: u1, - padding: u21, + padding: u22, }), - /// RCC Clock Source Interrupt Clear Register + /// RCC clock interrupt clear register CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready Interrupt Clear + /// LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. LSIRDYC: u1, - /// LSE ready Interrupt Clear + /// LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. LSERDYC: u1, - /// HSI ready Interrupt Clear + reserved3: u1, + /// HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag. HSIRDYC: u1, - /// HSE ready Interrupt Clear + /// HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. HSERDYC: u1, - /// CSI ready Interrupt Clear - HSE_ready_Interrupt_Clear: u1, - /// RC48 ready Interrupt Clear - HSI48RDYC: u1, - /// PLL1 ready Interrupt Clear - PLLRDYC: u1, - reserved9: u2, - /// LSE clock security system Interrupt Clear + reserved8: u3, + /// Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag. + CSSC: u1, + /// LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag. LSECSSC: u1, - /// HSE clock security system Interrupt Clear - HSECSSC: u1, - padding: u21, - }), - reserved112: [4]u8, - /// RCC Backup Domain Control Register - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enabled - LSEON: u1, - /// LSE oscillator ready - LSERDY: u1, - /// LSE oscillator bypass - LSEBYP: u1, - /// LSE oscillator driving capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// LSE clock security system enable - LSECSSON: u1, - /// LSE clock security system failure detection - LSECSSD: u1, - reserved8: u1, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// VSwitch domain software reset - BDRST: u1, - padding: u15, - }), - /// RCC Clock Control and Status Register - CSR: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable - LSION: u1, - /// LSI oscillator ready - LSIRDY: u1, - padding: u30, - }), - reserved124: [4]u8, - /// RCC AHB3 Reset Register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - /// MDMA block reset - MDMARST: u1, - reserved4: u3, - /// DMA2D block reset - DMA2DRST: u1, - /// JPGDEC block reset - JPGDECRST: u1, - reserved12: u6, - /// FMC block reset - FMCRST: u1, - reserved14: u1, - /// OCTOSPI1 and OCTOSPI1 delay block reset - OCTOSPI1RST: u1, - reserved16: u1, - /// SDMMC1 and SDMMC1 delay block reset - SDMMC1RST: u1, - reserved19: u2, - /// OCTOSPI2 and OCTOSPI2 delay block reset - OCTOSPI2RST: u1, - reserved21: u1, - /// OCTOSPI IO manager reset - IOMNGRRST: u1, - /// OTFDEC1 reset - OTFD1RST: u1, - /// OTFDEC2 reset - OTFD2RST: u1, - reserved31: u7, - /// CPU reset - CPURST: u1, - }), - /// RCC AHB1 Peripheral Reset Register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 block reset - DMA1RST: u1, - /// DMA2 block reset - DMA2RST: u1, - reserved5: u3, - /// ADC1&2 block reset - ADC12RST: u1, - reserved14: u8, - /// ART block reset - ARTRST: u1, - /// ETH block reset - ETHRST: u1, - reserved25: u9, - /// USB_OTG_HS block reset - USB_OTG_HSRST: u1, - reserved27: u1, - /// USB_OTG_FS block reset - USB_OTG_FSRST: u1, - padding: u4, - }), - /// RCC AHB2 Peripheral Reset Register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// DCMI block reset - DCMIRST: u1, - reserved4: u3, - /// CRYPography block reset - CRYPRST: u1, - /// Hash block reset - HASHRST: u1, - /// Random Number Generator block reset - RNGRST: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 Delay block reset - SDMMC2RST: u1, - reserved16: u6, - /// FMAC reset - FMACRST: u1, - /// CORDIC reset - CORDICRST: u1, - padding: u14, + padding: u22, }), - /// RCC AHB4 Peripheral Reset Register - AHB4RSTR: mmio.Mmio(packed struct(u32) { - /// GPIO block reset + /// RCC I/O port reset register + GPIORSTR: mmio.Mmio(packed struct(u32) { + /// I/O port A reset This bit is set and cleared by software. GPIOARST: u1, - /// GPIO block reset + /// I/O port B reset This bit is set and cleared by software. GPIOBRST: u1, - /// GPIO block reset + /// I/O port C reset This bit is set and cleared by software. GPIOCRST: u1, - /// GPIO block reset + /// I/O port D reset This bit is set and cleared by software. GPIODRST: u1, - /// GPIO block reset - GPIOERST: u1, - /// GPIO block reset + reserved5: u1, + /// I/O port F reset This bit is set and cleared by software. GPIOFRST: u1, - /// GPIO block reset - GPIOGRST: u1, - /// GPIO block reset - GPIOHRST: u1, - /// GPIO block reset - GPIOIRST: u1, - /// GPIO block reset - GPIOJRST: u1, - /// GPIO block reset - GPIOKRST: u1, - reserved19: u8, - /// CRC block reset - CRCRST: u1, - reserved21: u1, - /// BDMA block reset - BDMARST: u1, - reserved24: u2, - /// ADC3 block reset - ADC3RST: u1, - /// HSEM block reset - HSEMRST: u1, - padding: u6, + padding: u26, }), - /// RCC APB3 Peripheral Reset Register - APB3RSTR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// LTDC block reset - LTDCRST: u1, - /// DSI block reset - DSIRST: u1, - padding: u27, + /// RCC AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + /// DMA1 and DMAMUX reset Set and cleared by software. + DMA1RST: u1, + reserved8: u7, + /// Flash memory interface reset Set and cleared by software. This bit can only be set when the Flash memory is in power down mode. + FLASHRST: u1, + reserved12: u3, + /// CRC reset Set and cleared by software. + CRCRST: u1, + padding: u19, }), - /// RCC APB1 Peripheral Reset Register - APB1LRSTR: mmio.Mmio(packed struct(u32) { - /// TIM block reset - TIM2RST: u1, - /// TIM block reset + /// RCC APB peripheral reset register 1 + APBRSTR1: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// TIM3 timer reset Set and cleared by software. TIM3RST: u1, - /// TIM block reset - TIM4RST: u1, - /// TIM block reset - TIM5RST: u1, - /// TIM block reset - TIM6RST: u1, - /// TIM block reset - TIM7RST: u1, - /// TIM block reset - TIM12RST: u1, - /// TIM block reset - TIM13RST: u1, - /// TIM block reset - TIM14RST: u1, - /// TIM block reset - LPTIM1RST: u1, - reserved14: u4, - /// SPI2 block reset - SPI2RST: u1, - /// SPI3 block reset - SPI3RST: u1, - /// SPDIFRX block reset - SPDIFRXRST: u1, - /// USART2 block reset + reserved17: u15, + /// USART2 reset Set and cleared by software. USART2RST: u1, - /// USART3 block reset - USART3RST: u1, - /// UART4 block reset - UART4RST: u1, - /// UART5 block reset - UART5RST: u1, - /// I2C1 block reset + reserved21: u3, + /// I2C1 reset Set and cleared by software. I2C1RST: u1, - /// I2C2 block reset - I2C2RST: u1, - /// I2C3 block reset - I2C3RST: u1, - reserved25: u1, - /// I2C5 block reset - I2C5RST: u1, - reserved27: u1, - /// HDMI-CEC block reset - CECRST: u1, - reserved29: u1, - /// DAC1 and 2 Blocks Reset - DAC12RST: u1, - /// UART7 block reset - UART7RST: u1, - /// UART8 block reset - UART8RST: u1, - }), - /// RCC APB1 Peripheral Reset Register - APB1HRSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System reset - CRSRST: u1, - /// SWPMI block reset - SWPMIRST: u1, - reserved4: u1, - /// OPAMP block reset - OPAMPRST: u1, - /// MDIOS block reset - MDIOSRST: u1, - reserved8: u2, - /// FDCAN block reset - FDCANRST: u1, - reserved24: u15, - /// TIM23 block reset - TIM23RST: u1, - /// TIM24 block reset - TIM24RST: u1, - padding: u6, + reserved27: u5, + /// Debug support reset Set and cleared by software. + DBGRST: u1, + /// Power interface reset Set and cleared by software. + PWRRST: u1, + padding: u3, }), - /// RCC APB2 Peripheral Reset Register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// TIM1 block reset + /// RCC APB peripheral reset register 2 + APBRSTR2: mmio.Mmio(packed struct(u32) { + /// SYSCFG reset Set and cleared by software. + SYSCFGRST: u1, + reserved11: u10, + /// TIM1 timer reset Set and cleared by software. TIM1RST: u1, - /// TIM8 block reset - TIM8RST: u1, - reserved4: u2, - /// USART1 block reset - USART1RST: u1, - /// USART6 block reset - USART6RST: u1, - /// UART9 block reset - UART9RST: u1, - /// USART10 block reset - USART10RST: u1, - reserved12: u4, - /// SPI1 block reset + /// SPI1 reset Set and cleared by software. SPI1RST: u1, - /// SPI4 block reset - SPI4RST: u1, - reserved16: u2, - /// TIM15 block reset - TIM15RST: u1, - /// TIM16 block reset + reserved14: u1, + /// USART1 reset Set and cleared by software. + USART1RST: u1, + /// TIM14 timer reset Set and cleared by software. + TIM14RST: u1, + reserved17: u1, + /// TIM16 timer reset Set and cleared by software. TIM16RST: u1, - /// TIM17 block reset + /// TIM16 timer reset Set and cleared by software. TIM17RST: u1, reserved20: u1, - /// SPI5 block reset - SPI5RST: u1, - reserved22: u1, - /// SAI1 block reset - SAI1RST: u1, - /// SAI2 block reset - SAI2RST: u1, - /// SAI3 block reset - SAI3RST: u1, - reserved28: u3, - /// DFSDM1 block reset - DFSDM1RST: u1, - /// HRTIM block reset - HRTIMRST: u1, - padding: u2, - }), - /// RCC APB4 Peripheral Reset Register - APB4RSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG block reset - SYSCFGRST: u1, - reserved3: u1, - /// LPUART1 block reset - LPUART1RST: u1, - reserved5: u1, - /// SPI6 block reset - SPI6RST: u1, - reserved7: u1, - /// I2C4 block reset - I2C4RST: u1, - reserved9: u1, - /// LPTIM2 block reset - LPTIM2RST: u1, - /// LPTIM3 block reset - LPTIM3RST: u1, - /// LPTIM4 block reset - LPTIM4RST: u1, - /// LPTIM5 block reset - LPTIM5RST: u1, - /// DAC2 (containing one converter) reset - DAC2RST: u1, - /// COMP12 Blocks Reset - COMP12RST: u1, - /// VREF block reset - VREFRST: u1, - reserved21: u5, - /// SAI4 block reset - SAI4RST: u1, - reserved26: u4, - /// Digital temperature sensor block reset - DTSRST: u1, - padding: u5, - }), - /// Global Control Register - GCR: mmio.Mmio(packed struct(u32) { - /// WWDG1 reset scope control - WW1RSC: u1, - /// WWDG2 reset scope control - WW2RSC: u1, - /// Force allow CPU1 to boot - BOOT_C1: u1, - /// Force allow CPU2 to boot - BOOT_C2: u1, - padding: u28, - }), - reserved168: [4]u8, - /// RCC D3 Autonomous mode Register - D3AMR: mmio.Mmio(packed struct(u32) { - /// BDMA and DMAMUX Autonomous mode enable - BDMAAMEN: u1, - reserved3: u2, - /// LPUART1 Autonomous mode enable - LPUART1AMEN: u1, - reserved5: u1, - /// SPI6 Autonomous mode enable - SPI6AMEN: u1, - reserved7: u1, - /// I2C4 Autonomous mode enable - I2C4AMEN: u1, - reserved9: u1, - /// LPTIM2 Autonomous mode enable - LPTIM2AMEN: u1, - /// LPTIM3 Autonomous mode enable - LPTIM3AMEN: u1, - /// LPTIM4 Autonomous mode enable - LPTIM4AMEN: u1, - /// LPTIM5 Autonomous mode enable - LPTIM5AMEN: u1, - /// DAC2 (containing one converter) Autonomous mode enable - DAC2AMEN: u1, - /// COMP12 Autonomous mode enable - COMP12AMEN: u1, - /// VREF Autonomous mode enable - VREFAMEN: u1, - /// RTC Autonomous mode enable - RTCAMEN: u1, - reserved19: u2, - /// CRC Autonomous mode enable - CRCAMEN: u1, - reserved21: u1, - /// SAI4 Autonomous mode enable - SAI4AMEN: u1, - reserved24: u2, - /// ADC3 Autonomous mode enable - ADC3AMEN: u1, - reserved26: u1, - /// Digital temperature sensor Autonomous mode enable - DTSAMEN: u1, - reserved28: u1, - /// Backup RAM Autonomous mode enable - BKPSRAMAMEN: u1, - /// SRAM4 Autonomous mode enable - SRAM4AMEN: u1, - padding: u2, - }), - reserved208: [36]u8, - /// RCC Reset Status Register - RSR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Remove reset flag - RMVF: u1, - /// CPU reset flag - CPURSTF: u1, - reserved19: u1, - /// D1 domain power switch reset flag - D1RSTF: u1, - /// D2 domain power switch reset flag - D2RSTF: u1, - /// BOR reset flag - BORRSTF: u1, - /// Pin reset flag (NRST) - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// System reset from CPU reset flag - SFTRSTF: u1, - reserved26: u1, - /// Independent Watchdog reset flag - IWDG1RSTF: u1, - reserved28: u1, - /// Window Watchdog reset flag - WWDG1RSTF: u1, - reserved30: u1, - /// Reset due to illegal D1 DStandby or CPU CStop flag - LPWRRSTF: u1, - padding: u1, - }), - /// RCC AHB3 Clock Register - AHB3ENR: mmio.Mmio(packed struct(u32) { - /// MDMA Peripheral Clock Enable - MDMAEN: u1, - reserved4: u3, - /// DMA2D Peripheral Clock Enable - DMA2DEN: u1, - /// JPGDEC Peripheral Clock Enable - JPGDECEN: u1, - reserved12: u6, - /// FMC Peripheral Clocks Enable - FMCEN: u1, - reserved14: u1, - /// OCTOSPI2 and OCTOSPI2 delay block enable - OCTOSPI1EN: u1, - reserved16: u1, - /// SDMMC1 and SDMMC1 Delay Clock Enable - SDMMC1EN: u1, - reserved19: u2, - /// OCTOSPI2 and OCTOSPI2 delay block enable - OCTOSPI2EN: u1, - reserved21: u1, - /// OCTOSPI IO manager enable - IOMNGREN: u1, - /// OTFDEC1 enable - OTFD1EN: u1, - /// OTFDEC2 enable - OTFD2EN: u1, - reserved28: u4, - /// D1 DTCM1 block enable - DTCM1EN: u1, - /// D1 DTCM2 block enable - DTCM2EN: u1, - /// D1 ITCM block enable - ITCM1EN: u1, - /// AXISRAM block enable - AXISRAMEN: u1, - }), - /// RCC AHB1 Clock Register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// DMA1 Clock Enable - DMA1EN: u1, - /// DMA2 Clock Enable - DMA2EN: u1, - reserved5: u3, - /// ADC1/2 Peripheral Clocks Enable - ADC12EN: u1, - reserved14: u8, - /// ART Clock Enable - ARTEN: u1, - /// Ethernet MAC bus interface Clock Enable - ETHEN: u1, - /// Ethernet Transmission Clock Enable - ETHTXEN: u1, - /// Ethernet Reception Clock Enable - ETHRXEN: u1, - reserved25: u7, - /// USB_OTG_HS Peripheral Clocks Enable - USB_OTG_HSEN: u1, - /// USB_OTG_HS ULPI clock enable - USB_OTG_HS_ULPIEN: u1, - /// USB_OTG_FS Peripheral Clocks Enable - USB_OTG_FSEN: u1, - /// USB_OTG_FS ULPI clock enable - USB_OTG_FS_ULPIEN: u1, - padding: u3, - }), - /// RCC AHB2 Clock Register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// DCMI peripheral clock - DCMIEN: u1, - reserved4: u3, - /// CRYP peripheral clock enable - CRYPEN: u1, - /// HASH peripheral clock enable - HASHEN: u1, - /// RNG peripheral clocks enable - RNGEN: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 delay clock enable - SDMMC2EN: u1, - reserved16: u6, - /// FMAC enable - FMACEN: u1, - /// CORDIC enable - CORDICEN: u1, - reserved29: u11, - /// SRAM1 block enable - SRAM1EN: u1, - /// SRAM2 block enable - SRAM2EN: u1, - /// SRAM3 block enable - SRAM3EN: u1, + /// ADC reset Set and cleared by software. + ADCRST: u1, + padding: u11, }), - /// RCC AHB4 Clock Register - AHB4ENR: mmio.Mmio(packed struct(u32) { - /// 0GPIO peripheral clock enable + /// RCC I/O port clock enable register + GPIOENR: mmio.Mmio(packed struct(u32) { + /// I/O port A clock enable This bit is set and cleared by software. GPIOAEN: u1, - /// 0GPIO peripheral clock enable + /// I/O port B clock enable This bit is set and cleared by software. GPIOBEN: u1, - /// 0GPIO peripheral clock enable + /// I/O port C clock enable This bit is set and cleared by software. GPIOCEN: u1, - /// 0GPIO peripheral clock enable + /// I/O port D clock enable This bit is set and cleared by software. GPIODEN: u1, - /// 0GPIO peripheral clock enable - GPIOEEN: u1, - /// 0GPIO peripheral clock enable + reserved5: u1, + /// I/O port F clock enable This bit is set and cleared by software. GPIOFEN: u1, - /// 0GPIO peripheral clock enable - GPIOGEN: u1, - /// 0GPIO peripheral clock enable - GPIOHEN: u1, - /// 0GPIO peripheral clock enable - GPIOIEN: u1, - /// 0GPIO peripheral clock enable - GPIOJEN: u1, - /// 0GPIO peripheral clock enable - GPIOKEN: u1, - reserved19: u8, - /// CRC peripheral clock enable - CRCEN: u1, - reserved21: u1, - /// BDMA and DMAMUX2 Clock Enable - BDMAEN: u1, - reserved24: u2, - /// ADC3 Peripheral Clocks Enable - ADC3EN: u1, - /// HSEM peripheral clock enable - HSEMEN: u1, - reserved28: u2, - /// Backup RAM Clock Enable - BKPSRAMEN: u1, - padding: u3, + padding: u26, }), - /// RCC APB3 Clock Register - APB3ENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// LTDC peripheral clock enable - LTDCEN: u1, - /// DSI Peripheral clocks enable - DSIEN: u1, - reserved6: u1, - /// WWDG1 Clock Enable - WWDG1EN: u1, - padding: u25, + /// RCC AHB peripheral clock enable register + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled. + DMA1EN: u1, + reserved8: u7, + /// Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the Flash memory is in power down mode. + FLASHEN: u1, + reserved12: u3, + /// CRC clock enable Set and cleared by software. + CRCEN: u1, + padding: u19, }), - /// RCC APB1 Clock Register - APB1LENR: mmio.Mmio(packed struct(u32) { - /// TIM peripheral clock enable - TIM2EN: u1, - /// TIM peripheral clock enable + /// RCC APB peripheral clock enable register 1 + APBENR1: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// TIM3 timer clock enable Set and cleared by software. TIM3EN: u1, - /// TIM peripheral clock enable - TIM4EN: u1, - /// TIM peripheral clock enable - TIM5EN: u1, - /// TIM peripheral clock enable - TIM6EN: u1, - /// TIM peripheral clock enable - TIM7EN: u1, - /// TIM peripheral clock enable - TIM12EN: u1, - /// TIM peripheral clock enable - TIM13EN: u1, - /// TIM peripheral clock enable - TIM14EN: u1, - /// LPTIM1 Peripheral Clocks Enable - LPTIM1EN: u1, - reserved11: u1, - /// WWDG2 peripheral clock enable - WWDG2EN: u1, - reserved14: u2, - /// SPI2 Peripheral Clocks Enable - SPI2EN: u1, - /// SPI3 Peripheral Clocks Enable - SPI3EN: u1, - /// SPDIFRX Peripheral Clocks Enable - SPDIFRXEN: u1, - /// USART2 Peripheral Clocks Enable + reserved10: u8, + /// RTC APB clock enable Set and cleared by software. + RTCAPBEN: u1, + /// WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0. + WWDGEN: u1, + reserved17: u5, + /// USART2 clock enable Set and cleared by software. USART2EN: u1, - /// USART3 Peripheral Clocks Enable - USART3EN: u1, - /// UART4 Peripheral Clocks Enable - UART4EN: u1, - /// UART5 Peripheral Clocks Enable - UART5EN: u1, - /// I2C1 Peripheral Clocks Enable + reserved21: u3, + /// I2C1 clock enable Set and cleared by software. I2C1EN: u1, - /// I2C2 Peripheral Clocks Enable - I2C2EN: u1, - /// I2C3 Peripheral Clocks Enable - I2C3EN: u1, - reserved25: u1, - /// I2C5 Peripheral Clocks Enable - I2C5EN: u1, - reserved27: u1, - /// HDMI-CEC peripheral clock enable - CECEN: u1, - reserved29: u1, - /// DAC1&2 peripheral clock enable - DAC12EN: u1, - /// UART7 Peripheral Clocks Enable - UART7EN: u1, - /// UART8 Peripheral Clocks Enable - UART8EN: u1, - }), - /// RCC APB1 Clock Register - APB1HENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System peripheral clock enable - CRSEN: u1, - /// SWPMI Peripheral Clocks Enable - SWPMIEN: u1, - reserved4: u1, - /// OPAMP peripheral clock enable - OPAMPEN: u1, - /// MDIOS peripheral clock enable - MDIOSEN: u1, - reserved8: u2, - /// FDCAN Peripheral Clocks Enable - FDCANEN: u1, - reserved24: u15, - /// TIM23 block enable - TIM23EN: u1, - /// TIM24 block enable - TIM24EN: u1, - padding: u6, + reserved27: u5, + /// Debug support clock enable Set and cleared by software. + DBGEN: u1, + /// Power interface clock enable Set and cleared by software. + PWREN: u1, + padding: u3, }), - /// RCC APB2 Clock Register - APB2ENR: mmio.Mmio(packed struct(u32) { - /// TIM1 peripheral clock enable + /// RCC APB peripheral clock enable register 2 + APBENR2: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable Set and cleared by software. + SYSCFGEN: u1, + reserved11: u10, + /// TIM1 timer clock enable Set and cleared by software. TIM1EN: u1, - /// TIM8 peripheral clock enable - TIM8EN: u1, - reserved4: u2, - /// USART1 Peripheral Clocks Enable - USART1EN: u1, - /// USART6 Peripheral Clocks Enable - USART6EN: u1, - /// UART9 Peripheral Clocks Enable - UART9EN: u1, - /// USART10 Peripheral Clocks Enable - USART10EN: u1, - reserved12: u4, - /// SPI1 Peripheral Clocks Enable + /// SPI1 clock enable Set and cleared by software. SPI1EN: u1, - /// SPI4 Peripheral Clocks Enable - SPI4EN: u1, - reserved16: u2, - /// TIM15 peripheral clock enable - TIM15EN: u1, - /// TIM16 peripheral clock enable + reserved14: u1, + /// USART1 clock enable Set and cleared by software. + USART1EN: u1, + /// TIM14 timer clock enable Set and cleared by software. + TIM14EN: u1, + reserved17: u1, + /// TIM16 timer clock enable Set and cleared by software. TIM16EN: u1, - /// TIM17 peripheral clock enable + /// TIM16 timer clock enable Set and cleared by software. TIM17EN: u1, reserved20: u1, - /// SPI5 Peripheral Clocks Enable - SPI5EN: u1, - reserved22: u1, - /// SAI1 Peripheral Clocks Enable - SAI1EN: u1, - /// SAI2 Peripheral Clocks Enable - SAI2EN: u1, - /// SAI3 Peripheral Clocks Enable - SAI3EN: u1, - reserved28: u3, - /// DFSDM1 Peripheral Clocks Enable - DFSDM1EN: u1, - /// HRTIM peripheral clock enable - HRTIMEN: u1, - padding: u2, + /// ADC clock enable Set and cleared by software. + ADCEN: u1, + padding: u11, }), - /// RCC APB4 Clock Register - APB4ENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG peripheral clock enable - SYSCFGEN: u1, - reserved3: u1, - /// LPUART1 Peripheral Clocks Enable - LPUART1EN: u1, + /// RCC I/O port in Sleep mode clock enable register + GPIOSMENR: mmio.Mmio(packed struct(u32) { + /// I/O port A clock enable during Sleep mode Set and cleared by software. + GPIOASMEN: u1, + /// I/O port B clock enable during Sleep mode Set and cleared by software. + GPIOBSMEN: u1, + /// I/O port C clock enable during Sleep mode Set and cleared by software. + GPIOCSMEN: u1, + /// I/O port D clock enable during Sleep mode Set and cleared by software. + GPIODSMEN: u1, reserved5: u1, - /// SPI6 Peripheral Clocks Enable - SPI6EN: u1, - reserved7: u1, - /// I2C4 Peripheral Clocks Enable - I2C4EN: u1, - reserved9: u1, - /// LPTIM2 Peripheral Clocks Enable - LPTIM2EN: u1, - /// LPTIM3 Peripheral Clocks Enable - LPTIM3EN: u1, - /// LPTIM4 Peripheral Clocks Enable - LPTIM4EN: u1, - /// LPTIM5 Peripheral Clocks Enable - LPTIM5EN: u1, - /// DAC2 (containing one converter) peripheral clock enable - DAC2EN: u1, - /// COMP1/2 peripheral clock enable - COMP12EN: u1, - /// VREF peripheral clock enable - VREFEN: u1, - /// RTC APB Clock Enable - RTCAPBEN: u1, - reserved21: u4, - /// SAI4 Peripheral Clocks Enable - SAI4EN: u1, - reserved26: u4, - /// Digital temperature sensor block enable - DTSEN: u1, - padding: u5, + /// I/O port F clock enable during Sleep mode Set and cleared by software. + GPIOFSMEN: u1, + padding: u26, }), - reserved252: [4]u8, - /// RCC AHB3 Sleep Clock Register - AHB3LPENR: mmio.Mmio(packed struct(u32) { - /// MDMA Clock Enable During CSleep Mode - MDMALPEN: u1, - reserved4: u3, - /// DMA2D Clock Enable During CSleep Mode - DMA2DLPEN: u1, - /// JPGDEC Clock Enable During CSleep Mode - JPGDECLPEN: u1, - reserved8: u2, - /// FLASH Clock Enable During CSleep Mode - FLASHLPEN: u1, - reserved12: u3, - /// FMC Peripheral Clocks Enable During CSleep Mode - FMCLPEN: u1, - reserved14: u1, - /// OCTOSPI1 and OCTOSPI1 delay block enable during CSleep Mode - OCTOSPI1LPEN: u1, - reserved16: u1, - /// SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - SDMMC1LPEN: u1, - reserved19: u2, - /// OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode - OCTOSPI2LPEN: u1, - reserved21: u1, - /// OCTOSPI IO manager enable during CSleep Mode - IOMNGRLPEN: u1, - /// OTFDEC1 enable during CSleep Mode - OTFD1LPEN: u1, - /// OTFDEC2 enable during CSleep Mode - OTFD2LPEN: u1, - reserved28: u4, - /// D1DTCM1 Block Clock Enable During CSleep mode - D1DTCM1LPEN: u1, - /// D1 DTCM2 Block Clock Enable During CSleep mode - DTCM2LPEN: u1, - /// D1ITCM Block Clock Enable During CSleep mode - ITCMLPEN: u1, - /// AXISRAM Block Clock Enable During CSleep mode - AXISRAMLPEN: u1, + /// RCC AHB peripheral clock enable in Sleep/Stop mode register + AHBSMENR: mmio.Mmio(packed struct(u32) { + /// DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. + DMA1SMEN: u1, + reserved8: u7, + /// Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode. + FLASHSMEN: u1, + /// SRAM clock enable during Sleep mode Set and cleared by software. + SRAMSMEN: u1, + reserved12: u2, + /// CRC clock enable during Sleep mode Set and cleared by software. + CRCSMEN: u1, + padding: u19, }), - /// RCC AHB1 Sleep Clock Register - AHB1LPENR: mmio.Mmio(packed struct(u32) { - /// DMA1 Clock Enable During CSleep Mode - DMA1LPEN: u1, - /// DMA2 Clock Enable During CSleep Mode - DMA2LPEN: u1, - reserved5: u3, - /// ADC1/2 Peripheral Clocks Enable During CSleep Mode - ADC12LPEN: u1, - reserved14: u8, - /// ART Clock Enable During CSleep Mode - ARTLPEN: u1, - /// Ethernet MAC bus interface Clock Enable During CSleep Mode - ETHLPEN: u1, - /// Ethernet Transmission Clock Enable During CSleep Mode - ETHTXLPEN: u1, - /// Ethernet Reception Clock Enable During CSleep Mode - ETHRXLPEN: u1, - reserved25: u7, - /// USB_OTG_HS peripheral clock enable during CSleep mode - USB_OTG_HSLPEN: u1, - /// USB_PHY1 clock enable during CSleep mode - USB_OTG_HS_ULPILPEN: u1, - /// USB_OTG_FS peripheral clock enable during CSleep mode - USB_OTG_FSLPEN: u1, - /// USB_PHY2 clocks enable during CSleep mode - USB_OTG_FS_ULPILPEN: u1, + /// RCC APB peripheral clock enable in Sleep/Stop mode register 1 + APBSMENR1: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// TIM3 timer clock enable during Sleep mode Set and cleared by software. + TIM3SMEN: u1, + reserved10: u8, + /// RTC APB clock enable during Sleep mode Set and cleared by software. + RTCAPBSMEN: u1, + /// WWDG clock enable during Sleep and Stop modes Set and cleared by software. + WWDGSMEN: u1, + reserved17: u5, + /// USART2 clock enable during Sleep and Stop modes Set and cleared by software. + USART2SMEN: u1, + reserved21: u3, + /// I2C1 clock enable during Sleep and Stop modes Set and cleared by software. + I2C1SMEN: u1, + reserved27: u5, + /// Debug support clock enable during Sleep mode Set and cleared by software. + DBGSMEN: u1, + /// Power interface clock enable during Sleep mode Set and cleared by software. + PWRSMEN: u1, padding: u3, }), - /// RCC AHB2 Sleep Clock Register - AHB2LPENR: mmio.Mmio(packed struct(u32) { - /// DCMI peripheral clock enable during csleep mode - DCMILPEN: u1, - reserved4: u3, - /// CRYP peripheral clock enable during CSleep mode - CRYPLPEN: u1, - /// HASH peripheral clock enable during CSleep mode - HASHLPEN: u1, - /// RNG peripheral clock enable during CSleep mode - RNGLPEN: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - SDMMC2LPEN: u1, - reserved16: u6, - /// FMAC enable during CSleep Mode - FMACLPEN: u1, - /// CORDIC enable during CSleep Mode - CORDICLPEN: u1, - reserved29: u11, - /// SRAM1 Clock Enable During CSleep Mode - SRAM1LPEN: u1, - /// SRAM2 Clock Enable During CSleep Mode - SRAM2LPEN: u1, - /// SRAM3 Clock Enable During CSleep Mode - SRAM3LPEN: u1, - }), - /// RCC AHB4 Sleep Clock Register - AHB4LPENR: mmio.Mmio(packed struct(u32) { - /// GPIO peripheral clock enable during CSleep mode - GPIOALPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOBLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOCLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIODLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOELPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOFLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOGLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOHLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOILPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOJLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOKLPEN: u1, - reserved19: u8, - /// CRC peripheral clock enable during CSleep mode - CRCLPEN: u1, - reserved21: u1, - /// BDMA Clock Enable During CSleep Mode - BDMALPEN: u1, - reserved24: u2, - /// ADC3 Peripheral Clocks Enable During CSleep Mode - ADC3LPEN: u1, - reserved28: u3, - /// Backup RAM Clock Enable During CSleep Mode - BKPSRAMLPEN: u1, - /// SRAM4 Clock Enable During CSleep Mode - SRAM4LPEN: u1, - padding: u2, - }), - /// RCC APB3 Sleep Clock Register - APB3LPENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// LTDC peripheral clock enable during CSleep mode - LTDCLPEN: u1, - /// DSI Peripheral Clock Enable During CSleep Mode - DSILPEN: u1, - reserved6: u1, - /// WWDG1 Clock Enable During CSleep Mode - WWDG1LPEN: u1, - padding: u25, + /// RCC APB peripheral clock enable in Sleep/Stop mode register 2 + APBSMENR2: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable during Sleep and Stop modes Set and cleared by software. + SYSCFGSMEN: u1, + reserved11: u10, + /// TIM1 timer clock enable during Sleep mode Set and cleared by software. + TIM1SMEN: u1, + /// SPI1 clock enable during Sleep mode Set and cleared by software. + SPI1SMEN: u1, + reserved14: u1, + /// USART1 clock enable during Sleep and Stop modes Set and cleared by software. + USART1SMEN: u1, + /// TIM14 timer clock enable during Sleep mode Set and cleared by software. + TIM14SMEN: u1, + reserved17: u1, + /// TIM16 timer clock enable during Sleep mode Set and cleared by software. + TIM16SMEN: u1, + /// TIM16 timer clock enable during Sleep mode Set and cleared by software. + TIM17SMEN: u1, + reserved20: u1, + /// ADC clock enable during Sleep mode Set and cleared by software. + ADCSMEN: u1, + padding: u11, }), - /// RCC APB1 Low Sleep Clock Register - APB1LLPENR: mmio.Mmio(packed struct(u32) { - /// TIM2 peripheral clock enable during CSleep mode - TIM2LPEN: u1, - /// TIM3 peripheral clock enable during CSleep mode - TIM3LPEN: u1, - /// TIM4 peripheral clock enable during CSleep mode - TIM4LPEN: u1, - /// TIM5 peripheral clock enable during CSleep mode - TIM5LPEN: u1, - /// TIM6 peripheral clock enable during CSleep mode - TIM6LPEN: u1, - /// TIM7 peripheral clock enable during CSleep mode - TIM7LPEN: u1, - /// TIM12 peripheral clock enable during CSleep mode - TIM12LPEN: u1, - /// TIM13 peripheral clock enable during CSleep mode - TIM13LPEN: u1, - /// TIM14 peripheral clock enable during CSleep mode - TIM14LPEN: u1, - /// LPTIM1 Peripheral Clocks Enable During CSleep Mode - LPTIM1LPEN: u1, - reserved11: u1, - /// WWDG2 peripheral Clocks Enable During CSleep Mode - WWDG2LPEN: u1, - reserved14: u2, - /// SPI2 Peripheral Clocks Enable During CSleep Mode - SPI2LPEN: u1, - /// SPI3 Peripheral Clocks Enable During CSleep Mode - SPI3LPEN: u1, - /// SPDIFRX Peripheral Clocks Enable During CSleep Mode - SPDIFRXLPEN: u1, - /// USART2 Peripheral Clocks Enable During CSleep Mode - USART2LPEN: u1, - /// USART3 Peripheral Clocks Enable During CSleep Mode - USART3LPEN: u1, - /// UART4 Peripheral Clocks Enable During CSleep Mode - UART4LPEN: u1, - /// UART5 Peripheral Clocks Enable During CSleep Mode - UART5LPEN: u1, - /// I2C1 Peripheral Clocks Enable During CSleep Mode - I2C1LPEN: u1, - /// I2C2 Peripheral Clocks Enable During CSleep Mode - I2C2LPEN: u1, - /// I2C3 Peripheral Clocks Enable During CSleep Mode - I2C3LPEN: u1, - reserved25: u1, - /// I2C5 block enable during CSleep Mode - I2C5LPEN: u1, - reserved27: u1, - /// HDMI-CEC Peripheral Clocks Enable During CSleep Mode - CECLPEN: u1, - reserved29: u1, - /// DAC1/2 peripheral clock enable during CSleep mode - DAC12LPEN: u1, - /// UART7 Peripheral Clocks Enable During CSleep Mode - UART7LPEN: u1, - /// UART8 Peripheral Clocks Enable During CSleep Mode - UART8LPEN: u1, + /// RCC peripherals independent clock configuration register + CCIPR: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows: + USART1SEL: packed union { + raw: u2, + value: USART1SEL, + }, + reserved12: u10, + /// I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows: + I2C1SEL: packed union { + raw: u2, + value: I2C1SEL, + }, + /// I2S1 clock source selection This bitfield is controlled by software to select I2S1 clock source as follows: + I2S1SEL: packed union { + raw: u2, + value: I2S1SEL, + }, + reserved30: u14, + /// ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC: + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, }), - /// RCC APB1 High Sleep Clock Register - APB1HLPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System peripheral clock enable during CSleep mode - CRSLPEN: u1, - /// SWPMI Peripheral Clocks Enable During CSleep Mode - SWPMILPEN: u1, - reserved4: u1, - /// OPAMP peripheral clock enable during CSleep mode - OPAMPLPEN: u1, - /// MDIOS peripheral clock enable during CSleep mode - MDIOSLPEN: u1, - reserved8: u2, - /// FDCAN Peripheral Clocks Enable During CSleep Mode - FDCANLPEN: u1, - reserved24: u15, - /// TIM23 block enable during CSleep Mode - TIM23LPEN: u1, - /// TIM24 block enable during CSleep Mode - TIM24LPEN: u1, + reserved92: [4]u8, + /// RCC control/status register 1 + CSR1: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enable Set and cleared by software to enable LSE oscillator: + LSEON: u1, + /// LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. + LSERDY: u1, + /// LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). + LSEBYP: u1, + /// LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode. + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// CSS on LSE enable Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit. + LSECSSON: u1, + /// CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 32 kHz oscillator (LSE): + LSECSSD: u1, + reserved8: u1, + /// RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00. + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP. + RTCEN: u1, + /// RTC domain software reset Set and cleared by software to reset the RTC domain: + RTCRST: u1, + reserved24: u7, + /// Low-speed clock output (LSCO) enable Set and cleared by software. + LSCOEN: u1, + /// Low-speed clock output selection Set and cleared by software to select the low-speed output clock: + LSCOSEL: packed union { + raw: u1, + value: LSCOSEL, + }, padding: u6, }), - /// RCC APB2 Sleep Clock Register - APB2LPENR: mmio.Mmio(packed struct(u32) { - /// TIM1 peripheral clock enable during CSleep mode - TIM1LPEN: u1, - /// TIM8 peripheral clock enable during CSleep mode - TIM8LPEN: u1, - reserved4: u2, - /// USART1 Peripheral Clocks Enable During CSleep Mode - USART1LPEN: u1, - /// USART6 Peripheral Clocks Enable During CSleep Mode - USART6LPEN: u1, - reserved12: u6, - /// SPI1 Peripheral Clocks Enable During CSleep Mode - SPI1LPEN: u1, - /// SPI4 Peripheral Clocks Enable During CSleep Mode - SPI4LPEN: u1, - reserved16: u2, - /// TIM15 peripheral clock enable during CSleep mode - TIM15LPEN: u1, - /// TIM16 peripheral clock enable during CSleep mode - TIM16LPEN: u1, - /// TIM17 peripheral clock enable during CSleep mode - TIM17LPEN: u1, - reserved20: u1, - /// SPI5 Peripheral Clocks Enable During CSleep Mode - SPI5LPEN: u1, - reserved22: u1, - /// SAI1 Peripheral Clocks Enable During CSleep Mode - SAI1LPEN: u1, - /// SAI2 Peripheral Clocks Enable During CSleep Mode - SAI2LPEN: u1, - /// SAI3 Peripheral Clocks Enable During CSleep Mode - SAI3LPEN: u1, - reserved28: u3, - /// DFSDM1 Peripheral Clocks Enable During CSleep Mode - DFSDM1LPEN: u1, - /// HRTIM peripheral clock enable during CSleep mode - HRTIMLPEN: u1, - padding: u2, - }), - /// RCC APB4 Sleep Clock Register - APB4LPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG peripheral clock enable during CSleep mode - SYSCFGLPEN: u1, - reserved3: u1, - /// LPUART1 Peripheral Clocks Enable During CSleep Mode - LPUART1LPEN: u1, - reserved5: u1, - /// SPI6 Peripheral Clocks Enable During CSleep Mode - SPI6LPEN: u1, - reserved7: u1, - /// I2C4 Peripheral Clocks Enable During CSleep Mode - I2C4LPEN: u1, - reserved9: u1, - /// LPTIM2 Peripheral Clocks Enable During CSleep Mode - LPTIM2LPEN: u1, - /// LPTIM3 Peripheral Clocks Enable During CSleep Mode - LPTIM3LPEN: u1, - /// LPTIM4 Peripheral Clocks Enable During CSleep Mode - LPTIM4LPEN: u1, - /// LPTIM5 Peripheral Clocks Enable During CSleep Mode - LPTIM5LPEN: u1, - /// DAC2 (containing one converter) peripheral clock enable during CSleep mode - DAC2LPEN: u1, - /// COMP1/2 peripheral clock enable during CSleep mode - COMP12LPEN: u1, - /// VREF peripheral clock enable during CSleep mode - VREFLPEN: u1, - /// RTC APB Clock Enable During CSleep Mode - RTCAPBLPEN: u1, - reserved21: u4, - /// SAI4 Peripheral Clocks Enable During CSleep Mode - SAI4LPEN: u1, - reserved26: u4, - /// Digital temperature sensor block enable during CSleep Mode - DTSLPEN: u1, - padding: u5, - }), - reserved304: [16]u8, - /// RCC Reset Status Register - C1_RSR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Remove reset flag - RMVF: u1, - /// CPU reset flag - CPURSTF: u1, - reserved19: u1, - /// D1 domain power switch reset flag - D1RSTF: u1, - /// D2 domain power switch reset flag - D2RSTF: u1, - /// BOR reset flag - BORRSTF: u1, - /// Pin reset flag (NRST) - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// System reset from CPU reset flag - SFTRSTF: u1, - reserved26: u1, - /// Independent Watchdog reset flag - IWDG1RSTF: u1, - reserved28: u1, - /// Window Watchdog reset flag - WWDG1RSTF: u1, - reserved30: u1, - /// Reset due to illegal D1 DStandby or CPU CStop flag - LPWRRSTF: u1, - padding: u1, - }), - /// RCC AHB3 Clock Register - C1_AHB3ENR: mmio.Mmio(packed struct(u32) { - /// MDMA Peripheral Clock Enable - MDMAEN: u1, - reserved4: u3, - /// DMA2D Peripheral Clock Enable - DMA2DEN: u1, - /// JPGDEC Peripheral Clock Enable - JPGDECEN: u1, - reserved12: u6, - /// FMC Peripheral Clocks Enable - FMCEN: u1, - reserved14: u1, - /// QUADSPI and QUADSPI Delay Clock Enable - QUADSPIEN: u1, - reserved16: u1, - /// SDMMC1 and SDMMC1 Delay Clock Enable - SDMMC1EN: u1, - padding: u15, - }), - /// RCC AHB1 Clock Register - C1_AHB1ENR: mmio.Mmio(packed struct(u32) { - /// DMA1 Clock Enable - DMA1EN: u1, - /// DMA2 Clock Enable - DMA2EN: u1, - reserved5: u3, - /// ADC1/2 Peripheral Clocks Enable - ADC12EN: u1, - reserved14: u8, - /// ART Clock Enable - ARTEN: u1, - /// Ethernet MAC bus interface Clock Enable - ETHEN: u1, - /// Ethernet Transmission Clock Enable - ETHTXEN: u1, - /// Ethernet Reception Clock Enable - ETHRXEN: u1, - reserved25: u7, - /// USB_OTG_HS Peripheral Clocks Enable - USB_OTG_HSEN: u1, - /// USB_PHY1 Clocks Enable - USB_OTG_HS_ULPIEN: u1, - /// USB_OTG_FS Peripheral Clocks Enable - USB_OTG_FSEN: u1, - /// USB_PHY2 Clocks Enable - USB_OTG_FS_ULPIEN: u1, - padding: u3, - }), - /// RCC AHB2 Clock Register - C1_AHB2ENR: mmio.Mmio(packed struct(u32) { - /// DCMI peripheral clock - DCMIEN: u1, - reserved4: u3, - /// CRYP peripheral clock enable - CRYPEN: u1, - /// HASH peripheral clock enable - HASHEN: u1, - /// RNG peripheral clocks enable - RNGEN: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 delay clock enable - SDMMC2EN: u1, - reserved29: u19, - /// SRAM1 block enable - SRAM1EN: u1, - /// SRAM2 block enable - SRAM2EN: u1, - /// SRAM3 block enable - SRAM3EN: u1, - }), - /// RCC AHB4 Clock Register - C1_AHB4ENR: mmio.Mmio(packed struct(u32) { - /// 0GPIO peripheral clock enable - GPIOAEN: u1, - /// 0GPIO peripheral clock enable - GPIOBEN: u1, - /// 0GPIO peripheral clock enable - GPIOCEN: u1, - /// 0GPIO peripheral clock enable - GPIODEN: u1, - /// 0GPIO peripheral clock enable - GPIOEEN: u1, - /// 0GPIO peripheral clock enable - GPIOFEN: u1, - /// 0GPIO peripheral clock enable - GPIOGEN: u1, - /// 0GPIO peripheral clock enable - GPIOHEN: u1, - /// 0GPIO peripheral clock enable - GPIOIEN: u1, - /// 0GPIO peripheral clock enable - GPIOJEN: u1, - /// 0GPIO peripheral clock enable - GPIOKEN: u1, - reserved19: u8, - /// CRC peripheral clock enable - CRCEN: u1, - reserved21: u1, - /// BDMA and DMAMUX2 Clock Enable - BDMAEN: u1, - reserved24: u2, - /// ADC3 Peripheral Clocks Enable - ADC3EN: u1, - /// HSEM peripheral clock enable - HSEMEN: u1, - reserved28: u2, - /// Backup RAM Clock Enable - BKPSRAMEN: u1, - padding: u3, - }), - /// RCC APB3 Clock Register - C1_APB3ENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// LTDC peripheral clock enable - LTDCEN: u1, - /// DSI Peripheral clocks enable - DSIEN: u1, - reserved6: u1, - /// WWDG1 Clock Enable - WWDG1EN: u1, - padding: u25, - }), - /// RCC APB1 Clock Register - C1_APB1LENR: mmio.Mmio(packed struct(u32) { - /// TIM peripheral clock enable - TIM2EN: u1, - /// TIM peripheral clock enable - TIM3EN: u1, - /// TIM peripheral clock enable - TIM4EN: u1, - /// TIM peripheral clock enable - TIM5EN: u1, - /// TIM peripheral clock enable - TIM6EN: u1, - /// TIM peripheral clock enable - TIM7EN: u1, - /// TIM peripheral clock enable - TIM12EN: u1, - /// TIM peripheral clock enable - TIM13EN: u1, - /// TIM peripheral clock enable - TIM14EN: u1, - /// LPTIM1 Peripheral Clocks Enable - LPTIM1EN: u1, - reserved11: u1, - /// WWDG2 peripheral clock enable - WWDG2EN: u1, - reserved14: u2, - /// SPI2 Peripheral Clocks Enable - SPI2EN: u1, - /// SPI3 Peripheral Clocks Enable - SPI3EN: u1, - /// SPDIFRX Peripheral Clocks Enable - SPDIFRXEN: u1, - /// USART2 Peripheral Clocks Enable - USART2EN: u1, - /// USART3 Peripheral Clocks Enable - USART3EN: u1, - /// UART4 Peripheral Clocks Enable - UART4EN: u1, - /// UART5 Peripheral Clocks Enable - UART5EN: u1, - /// I2C1 Peripheral Clocks Enable - I2C1EN: u1, - /// I2C2 Peripheral Clocks Enable - I2C2EN: u1, - /// I2C3 Peripheral Clocks Enable - I2C3EN: u1, - reserved25: u1, - /// I2C5 Peripheral Clocks Enable - I2C5EN: u1, - reserved27: u1, - /// HDMI-CEC peripheral clock enable - CECEN: u1, - reserved29: u1, - /// DAC1&2 peripheral clock enable - DAC12EN: u1, - /// UART7 Peripheral Clocks Enable - UART7EN: u1, - /// UART8 Peripheral Clocks Enable - UART8EN: u1, - }), - /// RCC APB1 Clock Register - C1_APB1HENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System peripheral clock enable - CRSEN: u1, - /// SWPMI Peripheral Clocks Enable - SWPMIEN: u1, - reserved4: u1, - /// OPAMP peripheral clock enable - OPAMPEN: u1, - /// MDIOS peripheral clock enable - MDIOSEN: u1, - reserved8: u2, - /// FDCAN Peripheral Clocks Enable - FDCANEN: u1, - padding: u23, - }), - /// RCC APB2 Clock Register - C1_APB2ENR: mmio.Mmio(packed struct(u32) { - /// TIM1 peripheral clock enable - TIM1EN: u1, - /// TIM8 peripheral clock enable - TIM8EN: u1, - reserved4: u2, - /// USART1 Peripheral Clocks Enable - USART1EN: u1, - /// USART6 Peripheral Clocks Enable - USART6EN: u1, - /// UART9 Peripheral Clocks Enable - UART9EN: u1, - /// USART10 Peripheral Clocks Enable - USART10EN: u1, - reserved12: u4, - /// SPI1 Peripheral Clocks Enable - SPI1EN: u1, - /// SPI4 Peripheral Clocks Enable - SPI4EN: u1, - reserved16: u2, - /// TIM15 peripheral clock enable - TIM15EN: u1, - /// TIM16 peripheral clock enable - TIM16EN: u1, - /// TIM17 peripheral clock enable - TIM17EN: u1, - reserved20: u1, - /// SPI5 Peripheral Clocks Enable - SPI5EN: u1, - reserved22: u1, - /// SAI1 Peripheral Clocks Enable - SAI1EN: u1, - /// SAI2 Peripheral Clocks Enable - SAI2EN: u1, - /// SAI3 Peripheral Clocks Enable - SAI3EN: u1, - reserved28: u3, - /// DFSDM1 Peripheral Clocks Enable - DFSDM1EN: u1, - /// HRTIM peripheral clock enable - HRTIMEN: u1, - padding: u2, - }), - /// RCC APB4 Clock Register - C1_APB4ENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG peripheral clock enable - SYSCFGEN: u1, - reserved3: u1, - /// LPUART1 Peripheral Clocks Enable - LPUART1EN: u1, - reserved5: u1, - /// SPI6 Peripheral Clocks Enable - SPI6EN: u1, - reserved7: u1, - /// I2C4 Peripheral Clocks Enable - I2C4EN: u1, - reserved9: u1, - /// LPTIM2 Peripheral Clocks Enable - LPTIM2EN: u1, - /// LPTIM3 Peripheral Clocks Enable - LPTIM3EN: u1, - /// LPTIM4 Peripheral Clocks Enable - LPTIM4EN: u1, - /// LPTIM5 Peripheral Clocks Enable - LPTIM5EN: u1, - reserved14: u1, - /// COMP1/2 peripheral clock enable - COMP12EN: u1, - /// VREF peripheral clock enable - VREFEN: u1, - /// RTC APB Clock Enable - RTCAPBEN: u1, - reserved21: u4, - /// SAI4 Peripheral Clocks Enable - SAI4EN: u1, - padding: u10, - }), - reserved348: [4]u8, - /// RCC AHB3 Sleep Clock Register - C1_AHB3LPENR: mmio.Mmio(packed struct(u32) { - /// MDMA Clock Enable During CSleep Mode - MDMALPEN: u1, - reserved4: u3, - /// DMA2D Clock Enable During CSleep Mode - DMA2DLPEN: u1, - /// JPGDEC Clock Enable During CSleep Mode - JPGDECLPEN: u1, - reserved8: u2, - /// Flash interface clock enable during csleep mode - FLASHPREN: u1, - reserved12: u3, - /// FMC Peripheral Clocks Enable During CSleep Mode - FMCLPEN: u1, - reserved14: u1, - /// QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - QUADSPILPEN: u1, - reserved16: u1, - /// SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - SDMMC1LPEN: u1, - reserved19: u2, - /// OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode - OCTOSPI2LPEN: u1, - reserved21: u1, - /// OCTOSPI IO manager enable during CSleep Mode - IOMNGRLPEN: u1, - /// OTFDEC1 enable during CSleep Mode - OTFD1LPEN: u1, - /// OTFDEC2 enable during CSleep Mode - OTFD2LPEN: u1, - reserved28: u4, - /// D1DTCM1 Block Clock Enable During CSleep mode - D1DTCM1LPEN: u1, - /// D1 DTCM2 Block Clock Enable During CSleep mode - DTCM2LPEN: u1, - /// D1ITCM Block Clock Enable During CSleep mode - ITCMLPEN: u1, - /// AXISRAM Block Clock Enable During CSleep mode - AXISRAMLPEN: u1, - }), - /// RCC AHB1 Sleep Clock Register - C1_AHB1LPENR: mmio.Mmio(packed struct(u32) { - /// DMA1 Clock Enable During CSleep Mode - DMA1LPEN: u1, - /// DMA2 Clock Enable During CSleep Mode - DMA2LPEN: u1, - reserved5: u3, - /// ADC1/2 Peripheral Clocks Enable During CSleep Mode - ADC12LPEN: u1, - reserved14: u8, - /// ART Clock Enable During CSleep Mode - ARTLPEN: u1, - /// Ethernet MAC bus interface Clock Enable During CSleep Mode - ETHLPEN: u1, - /// Ethernet Transmission Clock Enable During CSleep Mode - ETHTXLPEN: u1, - /// Ethernet Reception Clock Enable During CSleep Mode - ETHRXLPEN: u1, - reserved25: u7, - /// USB_OTG_HS peripheral clock enable during CSleep mode - USB_OTG_HSLPEN: u1, - /// USB_PHY1 clock enable during CSleep mode - USB_OTG_HS_ULPILPEN: u1, - /// USB_OTG_FS peripheral clock enable during CSleep mode - USB_OTG_FSLPEN: u1, - /// USB_PHY2 clocks enable during CSleep mode - USB_OTG_FS_ULPILPEN: u1, - padding: u3, - }), - /// RCC AHB2 Sleep Clock Register - C1_AHB2LPENR: mmio.Mmio(packed struct(u32) { - /// DCMI peripheral clock enable during csleep mode - DCMILPEN: u1, - reserved4: u3, - /// CRYP peripheral clock enable during CSleep mode - CRYPLPEN: u1, - /// HASH peripheral clock enable during CSleep mode - HASHLPEN: u1, - /// RNG peripheral clock enable during CSleep mode - RNGLPEN: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - SDMMC2LPEN: u1, - reserved16: u6, - /// FMAC enable during CSleep Mode - FMACLPEN: u1, - /// CORDIC enable during CSleep Mode - CORDICLPEN: u1, - reserved29: u11, - /// SRAM1 Clock Enable During CSleep Mode - SRAM1LPEN: u1, - /// SRAM2 Clock Enable During CSleep Mode - SRAM2LPEN: u1, - /// SRAM3 Clock Enable During CSleep Mode - SRAM3LPEN: u1, - }), - /// RCC AHB4 Sleep Clock Register - C1_AHB4LPENR: mmio.Mmio(packed struct(u32) { - /// GPIO peripheral clock enable during CSleep mode - GPIOALPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOBLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOCLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIODLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOELPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOFLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOGLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOHLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOILPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOJLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOKLPEN: u1, - reserved19: u8, - /// CRC peripheral clock enable during CSleep mode - CRCLPEN: u1, - reserved21: u1, - /// BDMA Clock Enable During CSleep Mode - BDMALPEN: u1, - reserved24: u2, - /// ADC3 Peripheral Clocks Enable During CSleep Mode - ADC3LPEN: u1, - reserved28: u3, - /// Backup RAM Clock Enable During CSleep Mode - BKPSRAMLPEN: u1, - /// SRAM4 Clock Enable During CSleep Mode - SRAM4LPEN: u1, - padding: u2, - }), - /// RCC APB3 Sleep Clock Register - C1_APB3LPENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// LTDC peripheral clock enable during CSleep mode - LTDCLPEN: u1, - /// DSI Peripheral Clock Enable During CSleep Mode - DSILPEN: u1, - reserved6: u1, - /// WWDG1 Clock Enable During CSleep Mode - WWDG1LPEN: u1, - padding: u25, - }), - /// RCC APB1 Low Sleep Clock Register - C1_APB1LLPENR: mmio.Mmio(packed struct(u32) { - /// TIM2 peripheral clock enable during CSleep mode - TIM2LPEN: u1, - /// TIM3 peripheral clock enable during CSleep mode - TIM3LPEN: u1, - /// TIM4 peripheral clock enable during CSleep mode - TIM4LPEN: u1, - /// TIM5 peripheral clock enable during CSleep mode - TIM5LPEN: u1, - /// TIM6 peripheral clock enable during CSleep mode - TIM6LPEN: u1, - /// TIM7 peripheral clock enable during CSleep mode - TIM7LPEN: u1, - /// TIM12 peripheral clock enable during CSleep mode - TIM12LPEN: u1, - /// TIM13 peripheral clock enable during CSleep mode - TIM13LPEN: u1, - /// TIM14 peripheral clock enable during CSleep mode - TIM14LPEN: u1, - /// LPTIM1 Peripheral Clocks Enable During CSleep Mode - LPTIM1LPEN: u1, - reserved11: u1, - /// WWDG2 peripheral Clocks Enable During CSleep Mode - WWDG2LPEN: u1, - reserved14: u2, - /// SPI2 Peripheral Clocks Enable During CSleep Mode - SPI2LPEN: u1, - /// SPI3 Peripheral Clocks Enable During CSleep Mode - SPI3LPEN: u1, - /// SPDIFRX Peripheral Clocks Enable During CSleep Mode - SPDIFRXLPEN: u1, - /// USART2 Peripheral Clocks Enable During CSleep Mode - USART2LPEN: u1, - /// USART3 Peripheral Clocks Enable During CSleep Mode - USART3LPEN: u1, - /// UART4 Peripheral Clocks Enable During CSleep Mode - UART4LPEN: u1, - /// UART5 Peripheral Clocks Enable During CSleep Mode - UART5LPEN: u1, - /// I2C1 Peripheral Clocks Enable During CSleep Mode - I2C1LPEN: u1, - /// I2C2 Peripheral Clocks Enable During CSleep Mode - I2C2LPEN: u1, - /// I2C3 Peripheral Clocks Enable During CSleep Mode - I2C3LPEN: u1, - reserved25: u1, - /// I2C5 block enable during CSleep Mode - I2C5LPEN: u1, - reserved27: u1, - /// HDMI-CEC Peripheral Clocks Enable During CSleep Mode - CECLPEN: u1, - reserved29: u1, - /// DAC1/2 peripheral clock enable during CSleep mode - DAC12LPEN: u1, - /// UART7 Peripheral Clocks Enable During CSleep Mode - UART7LPEN: u1, - /// UART8 Peripheral Clocks Enable During CSleep Mode - UART8LPEN: u1, - }), - /// RCC APB1 High Sleep Clock Register - C1_APB1HLPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System peripheral clock enable during CSleep mode - CRSLPEN: u1, - /// SWPMI Peripheral Clocks Enable During CSleep Mode - SWPMILPEN: u1, - reserved4: u1, - /// OPAMP peripheral clock enable during CSleep mode - OPAMPLPEN: u1, - /// MDIOS peripheral clock enable during CSleep mode - MDIOSLPEN: u1, - reserved8: u2, - /// FDCAN Peripheral Clocks Enable During CSleep Mode - FDCANLPEN: u1, - reserved24: u15, - /// TIM23 block enable during CSleep Mode - TIM23LPEN: u1, - /// TIM24 block enable during CSleep Mode - TIM24LPEN: u1, - padding: u6, - }), - /// RCC APB2 Sleep Clock Register - C1_APB2LPENR: mmio.Mmio(packed struct(u32) { - /// TIM1 peripheral clock enable during CSleep mode - TIM1LPEN: u1, - /// TIM8 peripheral clock enable during CSleep mode - TIM8LPEN: u1, - reserved4: u2, - /// USART1 Peripheral Clocks Enable During CSleep Mode - USART1LPEN: u1, - /// USART6 Peripheral Clocks Enable During CSleep Mode - USART6LPEN: u1, - reserved12: u6, - /// SPI1 Peripheral Clocks Enable During CSleep Mode - SPI1LPEN: u1, - /// SPI4 Peripheral Clocks Enable During CSleep Mode - SPI4LPEN: u1, - reserved16: u2, - /// TIM15 peripheral clock enable during CSleep mode - TIM15LPEN: u1, - /// TIM16 peripheral clock enable during CSleep mode - TIM16LPEN: u1, - /// TIM17 peripheral clock enable during CSleep mode - TIM17LPEN: u1, - reserved20: u1, - /// SPI5 Peripheral Clocks Enable During CSleep Mode - SPI5LPEN: u1, - reserved22: u1, - /// SAI1 Peripheral Clocks Enable During CSleep Mode - SAI1LPEN: u1, - /// SAI2 Peripheral Clocks Enable During CSleep Mode - SAI2LPEN: u1, - /// SAI3 Peripheral Clocks Enable During CSleep Mode - SAI3LPEN: u1, - reserved28: u3, - /// DFSDM1 Peripheral Clocks Enable During CSleep Mode - DFSDM1LPEN: u1, - /// HRTIM peripheral clock enable during CSleep mode - HRTIMLPEN: u1, - padding: u2, - }), - /// RCC APB4 Sleep Clock Register - C1_APB4LPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG peripheral clock enable during CSleep mode - SYSCFGLPEN: u1, - reserved3: u1, - /// LPUART1 Peripheral Clocks Enable During CSleep Mode - LPUART1LPEN: u1, - reserved5: u1, - /// SPI6 Peripheral Clocks Enable During CSleep Mode - SPI6LPEN: u1, - reserved7: u1, - /// I2C4 Peripheral Clocks Enable During CSleep Mode - I2C4LPEN: u1, - reserved9: u1, - /// LPTIM2 Peripheral Clocks Enable During CSleep Mode - LPTIM2LPEN: u1, - /// LPTIM3 Peripheral Clocks Enable During CSleep Mode - LPTIM3LPEN: u1, - /// LPTIM4 Peripheral Clocks Enable During CSleep Mode - LPTIM4LPEN: u1, - /// LPTIM5 Peripheral Clocks Enable During CSleep Mode - LPTIM5LPEN: u1, - reserved14: u1, - /// COMP1/2 peripheral clock enable during CSleep mode - COMP12LPEN: u1, - /// VREF peripheral clock enable during CSleep mode - VREFLPEN: u1, - /// RTC APB Clock Enable During CSleep Mode - RTCAPBLPEN: u1, - reserved21: u4, - /// SAI4 Peripheral Clocks Enable During CSleep Mode - SAI4LPEN: u1, - reserved26: u4, - /// Digital temperature sensor block enable during CSleep Mode - DTSLPEN: u1, - padding: u5, - }), - }; - }; - - pub const vrefbuf_v2a1 = struct { - pub const HIZ = enum(u1) { - /// VREF+ pin is internally connected to the voltage reference buffer output. - Connected = 0x0, - /// VREF+ pin is high impedance. - HighZ = 0x1, - }; - - pub const VRS = enum(u3) { - /// Voltage reference set to VREF_OUT1 (around 2.048 V). - Vref0 = 0x0, - /// Voltage reference set to VREF_OUT2 (around 2.5 V). - Vref1 = 0x1, - /// Voltage reference set to VREF_OUT2 (around 2.5 V). - Vref2 = 0x2, - /// Voltage reference set to VREF_OUT2 (around 2.5 V). - Vref3 = 0x3, - _, - }; - - /// Voltage reference buffer. - pub const VREFBUF = extern struct { - /// VREFBUF control and status register. - CSR: mmio.Mmio(packed struct(u32) { - /// Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. - ENVR: u1, - /// High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration. - HIZ: packed union { - raw: u1, - value: HIZ, - }, - reserved3: u1, - /// Voltage reference buffer ready. - VRR: u1, - /// Voltage reference scale These bits select the value generated by the voltage reference buffer. VRS = 000: VREFBUF0 voltage selected. VRS = 001: VREFBUF1 voltage selected. VRS = 010: VREFBUF2 voltage selected. VRS = 011: VREFBUF3 voltage selected. Others: Reserved Note: Refer to the product datasheet for each VREFBUFx voltage setting value. The software can program this bitfield only when the VREFBUF is disabled (ENVR=0). - VRS: packed union { - raw: u3, - value: VRS, - }, - padding: u25, - }), - /// VREFBUF calibration control register. - CCR: mmio.Mmio(packed struct(u32) { - /// Trimming code The TRIM code is a 6-bit unsigned data (minimum 000000, maximum 111111) that is set and updated according the mechanism described below. Reset: TRIM[5:0] is automatically initialized with the VRS = 0 trimming value stored in the Flash memory during the production test. VRS change: TRIM[5:0] is automatically initialized with the trimming value (corresponding to VRS setting) stored in the Flash memory during the production test. Write in TRIM[5:0]: User can modify the TRIM[5:0] with an arbitrary value. This is permanently disabling the control of the trimming value with VRS (until the device is reset). Note: If the user application performs the trimming, the trimming code must start from 000000 to 111111 in ascending order. - TRIM: u6, - padding: u26, + /// RCC control/status register 2 + CSR2: mmio.Mmio(packed struct(u32) { + /// LSI oscillator enable Set and cleared by software to enable/disable the LSI oscillator: + LSION: u1, + /// LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. + LSIRDY: u1, + reserved23: u21, + /// Remove reset flags Set by software to clear the reset flags. + RMVF: u1, + reserved25: u1, + /// Option byte loader reset flag Set by hardware when a reset from the Option byte loading occurs. Cleared by setting the RMVF bit. + OBLRSTF: u1, + /// Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by setting the RMVF bit. + PINRSTF: u1, + /// BOR or POR/PDR flag Set by hardware when a BOR or POR/PDR occurs. Cleared by setting the RMVF bit. + PWRRSTF: u1, + /// Software reset flag Set by hardware when a software reset occurs. Cleared by setting the RMVF bit. + SFTRSTF: u1, + /// Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by setting the RMVF bit. + IWDGRSTF: u1, + /// Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by setting the RMVF bit. + WWDGRSTF: u1, + /// Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared. + LPWRRSTF: u1, }), }; }; - pub const dma2d_v2 = struct { - pub const ABORT = enum(u1) { - /// Transfer abort requested - AbortRequest = 0x1, - _, - }; - - pub const BGPFCCR_AI = enum(u1) { - /// Regular alpha - RegularAlpha = 0x0, - /// Inverted alpha - InvertedAlpha = 0x1, - }; - - pub const BGPFCCR_AM = enum(u2) { - /// No modification of alpha channel - NoModify = 0x0, - /// Replace with value in ALPHA[7:0] - Replace = 0x1, - /// Multiply with value in ALPHA[7:0] - Multiply = 0x2, - _, - }; - - pub const BGPFCCR_CCM = enum(u1) { - /// CLUT color format ARGB8888 - ARGB8888 = 0x0, - /// CLUT color format RGB888 - RGB888 = 0x1, + pub const rcc_f0v1 = struct { + pub const CECSW = enum(u1) { + /// HSI clock divided by 244 selected as CEC clock source + HSI_DIV_244 = 0x0, + /// LSE clock selected as CEC clock source + LSE = 0x1, }; - pub const BGPFCCR_CM = enum(u4) { - /// Color mode ARGB8888 - ARGB8888 = 0x0, - /// Color mode RGB888 - RGB888 = 0x1, - /// Color mode RGB565 - RGB565 = 0x2, - /// Color mode ARGB1555 - ARGB1555 = 0x3, - /// Color mode ARGB4444 - ARGB4444 = 0x4, - /// Color mode L8 - L8 = 0x5, - /// Color mode AL44 - AL44 = 0x6, - /// Color mode AL88 - AL88 = 0x7, - /// Color mode L4 - L4 = 0x8, - /// Color mode A8 - A8 = 0x9, - /// Color mode A4 - A4 = 0xa, + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, _, }; - pub const BGPFCCR_RBS = enum(u1) { - /// No Red Blue Swap (RGB or ARGB) - Regular = 0x0, - /// Red Blue Swap (BGR or ABGR) - Swap = 0x1, - }; - - pub const BGPFCCR_START = enum(u1) { - /// Start the automatic loading of the CLUT - Start = 0x1, - _, + pub const ICSW = enum(u1) { + /// HSI clock selected as I2C clock source + HSI = 0x0, + /// SYSCLK clock selected as I2C clock source + SYS = 0x1, }; - pub const CAECIF = enum(u1) { - /// Clear the CAEIF flag in the ISR register - Clear = 0x1, - _, + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium high driving capability + MediumHigh = 0x1, + /// Medium low driving capability + MediumLow = 0x2, + /// High driving capability + High = 0x3, }; - pub const CCEIF = enum(u1) { - /// Clear the CEIF flag in the ISR register - Clear = 0x1, + pub const MCOSEL = enum(u4) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// Internal RC 14 MHz (HSI14) oscillator clock selected + HSI14 = 0x1, + /// Internal low speed (LSI) oscillator clock selected + LSI = 0x2, + /// External low speed (LSE) oscillator clock selected + LSE = 0x3, + /// System clock selected + SYS = 0x4, + /// Internal RC 8 MHz (HSI) oscillator clock selected + HSI = 0x5, + /// External 4-32 MHz (HSE) oscillator clock selected + HSE = 0x6, + /// PLL clock selected divided by 2 + PLL = 0x7, _, }; - pub const CCTCIF = enum(u1) { - /// Clear the CTCIF flag in the ISR register - Clear = 0x1, + pub const PLLMUL = enum(u4) { + /// PLL input clock x2 + Mul2 = 0x0, + /// PLL input clock x3 + Mul3 = 0x1, + /// PLL input clock x4 + Mul4 = 0x2, + /// PLL input clock x5 + Mul5 = 0x3, + /// PLL input clock x6 + Mul6 = 0x4, + /// PLL input clock x7 + Mul7 = 0x5, + /// PLL input clock x8 + Mul8 = 0x6, + /// PLL input clock x9 + Mul9 = 0x7, + /// PLL input clock x10 + Mul10 = 0x8, + /// PLL input clock x11 + Mul11 = 0x9, + /// PLL input clock x12 + Mul12 = 0xa, + /// PLL input clock x13 + Mul13 = 0xb, + /// PLL input clock x14 + Mul14 = 0xc, + /// PLL input clock x15 + Mul15 = 0xd, + /// PLL input clock x16 + Mul16 = 0xe, _, }; - pub const CR_START = enum(u1) { - /// Launch the DMA2D - Start = 0x1, - _, + pub const PLLSRC = enum(u1) { + /// HSI divided by 2 selected as PLL input clock + HSI_Div2 = 0x0, + /// HSE divided by PREDIV selected as PLL input clock + HSE_Div_PREDIV = 0x1, }; - pub const CTCIF = enum(u1) { - /// Clear the TCIF flag in the ISR register - Clear = 0x1, - _, + pub const PLLXTPRE = enum(u1) { + /// HSE clock not divided + Div1 = 0x0, + /// HSE clock divided by 2 + Div2 = 0x1, }; - pub const CTEIF = enum(u1) { - /// Clear the TEIF flag in the ISR register - Clear = 0x1, + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, _, }; - pub const CTWIF = enum(u1) { - /// Clear the TWIF flag in the ISR register - Clear = 0x1, - _, + pub const PREDIV = enum(u4) { + /// PREDIV input clock not divided + Div1 = 0x0, + /// PREDIV input clock divided by 2 + Div2 = 0x1, + /// PREDIV input clock divided by 3 + Div3 = 0x2, + /// PREDIV input clock divided by 4 + Div4 = 0x3, + /// PREDIV input clock divided by 5 + Div5 = 0x4, + /// PREDIV input clock divided by 6 + Div6 = 0x5, + /// PREDIV input clock divided by 7 + Div7 = 0x6, + /// PREDIV input clock divided by 8 + Div8 = 0x7, + /// PREDIV input clock divided by 9 + Div9 = 0x8, + /// PREDIV input clock divided by 10 + Div10 = 0x9, + /// PREDIV input clock divided by 11 + Div11 = 0xa, + /// PREDIV input clock divided by 12 + Div12 = 0xb, + /// PREDIV input clock divided by 13 + Div13 = 0xc, + /// PREDIV input clock divided by 14 + Div14 = 0xd, + /// PREDIV input clock divided by 15 + Div15 = 0xe, + /// PREDIV input clock divided by 16 + Div16 = 0xf, }; - pub const FGPFCCR_AI = enum(u1) { - /// Regular alpha - RegularAlpha = 0x0, - /// Inverted alpha - InvertedAlpha = 0x1, + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, }; - pub const FGPFCCR_AM = enum(u2) { - /// No modification of alpha channel - NoModify = 0x0, - /// Replace with value in ALPHA[7:0] - Replace = 0x1, - /// Multiply with value in ALPHA[7:0] - Multiply = 0x2, + pub const SW = enum(u2) { + /// HSI oscillator used as system clock + HSI = 0x0, + /// HSE oscillator used as system clock + HSE = 0x1, + /// PLL used as system clock + PLL1_P = 0x2, _, }; - pub const FGPFCCR_CCM = enum(u1) { - /// CLUT color format ARGB8888 - ARGB8888 = 0x0, - /// CLUT color format RGB888 - RGB888 = 0x1, - }; - - pub const FGPFCCR_CM = enum(u4) { - /// Color mode ARGB8888 - ARGB8888 = 0x0, - /// Color mode RGB888 - RGB888 = 0x1, - /// Color mode RGB565 - RGB565 = 0x2, - /// Color mode ARGB1555 - ARGB1555 = 0x3, - /// Color mode ARGB4444 - ARGB4444 = 0x4, - /// Color mode L8 - L8 = 0x5, - /// Color mode AL44 - AL44 = 0x6, - /// Color mode AL88 - AL88 = 0x7, - /// Color mode L4 - L4 = 0x8, - /// Color mode A8 - A8 = 0x9, - /// Color mode A4 - A4 = 0xa, - /// Color mode YCbCr - YCbCr = 0xb, - _, + pub const USART1SW = enum(u2) { + /// PCLK selected as USART clock source + PCLK2 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const FGPFCCR_RBS = enum(u1) { - /// No Red Blue Swap (RGB or ARGB) - Regular = 0x0, - /// Red Blue Swap (BGR or ABGR) - Swap = 0x1, + pub const USARTSW = enum(u2) { + /// PCLK selected as USART clock source + PCLK1 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const FGPFCCR_START = enum(u1) { - /// Start the automatic loading of the CLUT - Start = 0x1, + pub const USBSW = enum(u1) { + /// PLL clock selected as USB clock source + PLL1_P = 0x1, _, }; - pub const MODE = enum(u2) { - /// Memory-to-memory (FG fetch only) - MemoryToMemory = 0x0, - /// Memory-to-memory with PFC (FG fetch only with FG PFC active) - MemoryToMemoryPFC = 0x1, - /// Memory-to-memory with blending (FG and BG fetch with PFC and blending) - MemoryToMemoryPFCBlending = 0x2, - /// Register-to-memory - RegisterToMemory = 0x3, - }; - - pub const OPFCCR_AI = enum(u1) { - /// Regular alpha - RegularAlpha = 0x0, - /// Inverted alpha - InvertedAlpha = 0x1, - }; - - pub const OPFCCR_CM = enum(u3) { - /// ARGB8888 - ARGB8888 = 0x0, - /// RGB888 - RGB888 = 0x1, - /// RGB565 - RGB565 = 0x2, - /// ARGB1555 - ARGB1555 = 0x3, - /// ARGB4444 - ARGB4444 = 0x4, - _, - }; - - pub const OPFCCR_RBS = enum(u1) { - /// No Red Blue Swap (RGB or ARGB) - Regular = 0x0, - /// Red Blue Swap (BGR or ABGR) - Swap = 0x1, - }; - - pub const SB = enum(u1) { - /// Regular byte order - Regular = 0x0, - /// Bytes are swapped two by two - SwapBytes = 0x1, - }; - - /// DMA2D - pub const DMA2D = extern struct { - /// DMA2D control register + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register CR: mmio.Mmio(packed struct(u32) { - /// Start This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers - START: packed union { - raw: u1, - value: CR_START, - }, - /// Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset. - SUSP: u1, - /// Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset. - ABORT: packed union { - raw: u1, - value: ABORT, + /// Internal High Speed clock enable + HSION: u1, + /// Internal High Speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal High Speed clock trimming + HSITRIM: u5, + /// Internal High Speed clock Calibration + HSICAL: u8, + /// External High Speed clock enable + HSEON: u1, + /// External High Speed clock ready flag + HSERDY: u1, + /// External High Speed clock Bypass + HSEBYP: u1, + /// Clock Security System enable + CSSON: u1, + reserved24: u4, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding: u6, + }), + /// Clock configuration register (RCC_CFGR) + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock Switch + SW: packed union { + raw: u2, + value: SW, }, - reserved8: u5, - /// Transfer error interrupt enable This bit is set and cleared by software. - TEIE: u1, - /// Transfer complete interrupt enable This bit is set and cleared by software. - TCIE: u1, - /// Transfer watermark interrupt enable This bit is set and cleared by software. - TWIE: u1, - /// CLUT access error interrupt enable This bit is set and cleared by software. - CAEIE: u1, - /// CLUT transfer complete interrupt enable This bit is set and cleared by software. - CTCIE: u1, - /// Configuration Error Interrupt Enable This bit is set and cleared by software. - CEIE: u1, - reserved16: u2, - /// DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing. - MODE: packed union { + /// System Clock Switch Status + SWS: packed union { raw: u2, - value: MODE, + value: SW, }, - padding: u14, - }), - /// DMA2D Interrupt Status Register - ISR: mmio.Mmio(packed struct(u32) { - /// Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading). - TEIF: u1, - /// Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only). - TCIF: u1, - /// Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred. - TWIF: u1, - /// CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D. - CAEIF: u1, - /// CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete. - CTCIF: u1, - /// Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed. - CEIF: u1, - padding: u26, - }), - /// DMA2D interrupt flag clear register - IFCR: mmio.Mmio(packed struct(u32) { - /// Clear Transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register - CTEIF: packed union { - raw: u1, - value: CTEIF, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, }, - /// Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register - CTCIF: packed union { - raw: u1, - value: CTCIF, + /// APB Low speed prescaler (APB1) + PPRE: packed union { + raw: u3, + value: PPRE, }, - /// Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register - CTWIF: packed union { + reserved14: u3, + /// APCPRE is deprecated. See ADC field in CFGR2 register. + ADCPRE: u1, + reserved16: u1, + /// PLL input clock source + PLLSRC: packed union { raw: u1, - value: CTWIF, + value: PLLSRC, }, - /// Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register - CAECIF: packed union { + /// HSE divider for PLL entry. Same bit as PREDIV[0] from CFGR2 register. Refer to it for its meaning + PLLXTPRE: packed union { raw: u1, - value: CAECIF, + value: PLLXTPRE, }, - /// Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register - CCTCIF: packed union { - raw: u1, - value: CCTCIF, + /// PLL Multiplication Factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, }, - /// Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register - CCEIF: packed union { - raw: u1, - value: CCEIF, + reserved24: u2, + /// Microcontroller clock output + MCOSEL: packed union { + raw: u4, + value: MCOSEL, }, - padding: u26, + padding: u4, }), - /// DMA2D foreground memory address register - FGMAR: mmio.Mmio(packed struct(u32) { - /// Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned. - MA: u32, + /// Clock interrupt register (RCC_CIR) + CIR: mmio.Mmio(packed struct(u32) { + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + /// HSI14 ready interrupt flag + HSI14RDYF: u1, + reserved7: u1, + /// Clock Security System Interrupt flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + /// HSI14 ready interrupt enable + HSI14RDYIE: u1, + reserved16: u2, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + /// HSI 14 MHz Ready Interrupt Clear + HSI14RDYC: u1, + reserved23: u1, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, }), - /// DMA2D foreground offset register - FGOR: mmio.Mmio(packed struct(u32) { - /// Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even. - LO: u16, - padding: u16, + /// APB2 peripheral reset register (RCC_APB2RSTR) + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// SYSCFG and COMP reset + SYSCFGRST: u1, + reserved5: u4, + /// USART6 reset + USART6RST: u1, + /// USART7 reset + USART7RST: u1, + /// USART8 reset + USART8RST: u1, + reserved9: u1, + /// ADC interface reset + ADCRST: u1, + reserved11: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// USART1 reset + USART1RST: u1, + reserved16: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + reserved22: u3, + /// Debug MCU reset + DBGMCURST: u1, + padding: u9, }), - /// DMA2D background memory address register - BGMAR: mmio.Mmio(packed struct(u32) { - /// Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned. - MA: u32, + /// APB1 peripheral reset register (RCC_APB1RSTR) + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + reserved4: u2, + /// Timer 6 reset + TIM6RST: u1, + /// TIM7 timer reset + TIM7RST: u1, + reserved8: u2, + /// Timer 14 reset + TIM14RST: u1, + reserved11: u2, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + reserved17: u2, + /// USART 2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// USART4 reset + USART4RST: u1, + /// USART5 reset + USART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB interface reset + USBRST: u1, + reserved25: u1, + /// CAN interface reset + CANRST: u1, + reserved27: u1, + /// Clock Recovery System interface reset + CRSRST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// HDMI CEC reset + CECRST: u1, + padding: u1, }), - /// DMA2D background offset register - BGOR: mmio.Mmio(packed struct(u32) { - /// Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even. - LO: u16, - padding: u16, + /// AHB Peripheral Clock enable register (RCC_AHBENR) + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA clock enable + DMAEN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock enable + SRAMEN: u1, + reserved4: u1, + /// FLASH clock enable + FLASHEN: u1, + reserved6: u1, + /// CRC clock enable + CRCEN: u1, + reserved17: u10, + /// I/O port A clock enable + GPIOAEN: u1, + /// I/O port B clock enable + GPIOBEN: u1, + /// I/O port C clock enable + GPIOCEN: u1, + /// I/O port D clock enable + GPIODEN: u1, + /// I/O port E clock enable + GPIOEEN: u1, + /// I/O port F clock enable + GPIOFEN: u1, + reserved24: u1, + /// Touch sensing controller clock enable + TSCEN: u1, + padding: u7, }), - /// DMA2D foreground PFC control register - FGPFCCR: mmio.Mmio(packed struct(u32) { - /// Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless - CM: packed union { - raw: u4, - value: FGPFCCR_CM, - }, - /// CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only. - CCM: packed union { - raw: u1, - value: FGPFCCR_CCM, - }, - /// Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer). - START: packed union { - raw: u1, - value: FGPFCCR_START, - }, + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved5: u4, + /// USART6 clock enable + USART6EN: u1, + /// USART7 clock enable + USART7EN: u1, + /// USART8 clock enable + USART8EN: u1, + reserved9: u1, + /// ADC 1 interface clock enable + ADCEN: u1, + reserved11: u1, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + reserved14: u1, + /// USART1 clock enable + USART1EN: u1, + reserved16: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + reserved22: u3, + /// MCU debug module clock enable + DBGMCUEN: u1, + padding: u9, + }), + /// APB1 peripheral clock enable register (RCC_APB1ENR) + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + reserved4: u2, + /// Timer 6 clock enable + TIM6EN: u1, + /// TIM7 timer clock enable + TIM7EN: u1, reserved8: u2, - /// CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1. - CS: u8, - /// Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless - AM: packed union { + /// Timer 14 clock enable + TIM14EN: u1, + reserved11: u2, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI 2 clock enable + SPI2EN: u1, + reserved17: u2, + /// USART 2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// USART4 clock enable + USART4EN: u1, + /// USART5 clock enable + USART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB interface clock enable + USBEN: u1, + reserved25: u1, + /// CAN interface clock enable + CANEN: u1, + reserved27: u1, + /// Clock Recovery System interface clock enable + CRSEN: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// HDMI CEC interface clock enable + CECEN: u1, + padding: u1, + }), + /// Backup domain control register (RCC_BDCR) + BDCR: mmio.Mmio(packed struct(u32) { + /// External Low Speed oscillator enable + LSEON: u1, + /// External Low Speed oscillator ready + LSERDY: u1, + /// External Low Speed oscillator bypass + LSEBYP: u1, + /// LSE oscillator drive capability + LSEDRV: packed union { raw: u2, - value: FGPFCCR_AM, - }, - /// Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless - CSS: u2, - /// Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. - AI: packed union { - raw: u1, - value: FGPFCCR_AI, + value: LSEDRV, }, - /// Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. - RBS: packed union { - raw: u1, - value: FGPFCCR_RBS, + reserved8: u3, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, }, - reserved24: u2, - /// Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only. - ALPHA: u8, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, }), - /// DMA2D foreground color register - FGCOLR: mmio.Mmio(packed struct(u32) { - /// Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only. - BLUE: u8, - /// Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only. - GREEN: u8, - /// Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. - RED: u8, - padding: u8, + /// Control/status register (RCC_CSR) + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low speed oscillator enable + LSION: u1, + /// Internal low speed oscillator ready + LSIRDY: u1, + reserved23: u21, + /// 1.8 V domain reset flag + V18PWRRSTF: u1, + /// Remove reset flag + RMVF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, }), - /// DMA2D background PFC control register - BGPFCCR: mmio.Mmio(packed struct(u32) { - /// Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless - CM: packed union { + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + reserved17: u17, + /// I/O port A reset + GPIOARST: u1, + /// I/O port B reset + GPIOBRST: u1, + /// I/O port C reset + GPIOCRST: u1, + /// I/O port D reset + GPIODRST: u1, + /// I/O port E reset + GPIOERST: u1, + /// I/O port F reset + GPIOFRST: u1, + reserved24: u1, + /// Touch sensing controller reset + TSCRST: u1, + padding: u7, + }), + /// Clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// PREDIV division factor + PREDIV: packed union { raw: u4, - value: BGPFCCR_CM, - }, - /// CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only. - CCM: packed union { - raw: u1, - value: BGPFCCR_CCM, - }, - /// Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer). - START: packed union { - raw: u1, - value: BGPFCCR_START, + value: PREDIV, }, - reserved8: u2, - /// CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1. - CS: u8, - /// Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless - AM: packed union { + padding: u28, + }), + /// Clock configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SW: packed union { raw: u2, - value: BGPFCCR_AM, + value: USART1SW, }, - reserved20: u2, - /// Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. - AI: packed union { + reserved4: u2, + /// I2C1 clock source selection + I2C1SW: packed union { raw: u1, - value: BGPFCCR_AI, + value: ICSW, }, - /// Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. - RBS: packed union { + reserved6: u1, + /// HDMI CEC clock source selection + CECSW: packed union { raw: u1, - value: BGPFCCR_RBS, - }, - reserved24: u2, - /// Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. - ALPHA: u8, - }), - /// DMA2D background color register - BGCOLR: mmio.Mmio(packed struct(u32) { - /// Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. - BLUE: u8, - /// Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. - GREEN: u8, - /// Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. - RED: u8, - padding: u8, - }), - /// DMA2D foreground CLUT memory address register - FGCMAR: mmio.Mmio(packed struct(u32) { - /// Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned. - MA: u32, - }), - /// DMA2D background CLUT memory address register - BGCMAR: mmio.Mmio(packed struct(u32) { - /// Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned. - MA: u32, - }), - /// DMA2D output PFC control register - OPFCCR: mmio.Mmio(packed struct(u32) { - /// Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless - CM: packed union { - raw: u3, - value: OPFCCR_CM, + value: CECSW, }, - reserved8: u5, - /// Swap Bytes - SB: packed union { + /// USB clock source selection + USBSW: packed union { raw: u1, - value: SB, + value: USBSW, }, - reserved20: u11, - /// Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. - AI: packed union { - raw: u1, - value: OPFCCR_AI, + /// ADCSW is deprecated. See ADC field in CFGR2 register. + ADCSW: u1, + reserved16: u7, + /// USART2 clock source selection + USART2SW: packed union { + raw: u2, + value: USARTSW, }, - /// Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. - RBS: packed union { - raw: u1, - value: OPFCCR_RBS, + /// USART3 clock source + USART3SW: packed union { + raw: u2, + value: USARTSW, }, - padding: u10, - }), - /// DMA2D output color register - OCOLR: mmio.Mmio(packed struct(u32) { - /// Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. - BLUE: u8, - /// Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. - GREEN: u8, - /// Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. - RED: u8, - /// Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. - ALPHA: u8, - }), - /// DMA2D output memory address register - OMAR: mmio.Mmio(packed struct(u32) { - /// Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned. - MA: u32, - }), - /// DMA2D output offset register - OOR: mmio.Mmio(packed struct(u32) { - /// Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. - LO: u16, - padding: u16, - }), - /// DMA2D number of line register - NLR: mmio.Mmio(packed struct(u32) { - /// Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. - NL: u16, - /// Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even. - PL: u14, - padding: u2, - }), - /// DMA2D line watermark register - LWR: mmio.Mmio(packed struct(u32) { - /// Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. - LW: u16, - padding: u16, + padding: u12, }), - /// DMA2D AXI master timer configuration register - AMTCR: mmio.Mmio(packed struct(u32) { - /// Enable Enables the dead time functionality. - EN: u1, - reserved8: u7, - /// Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses. - DT: u8, + /// Clock control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// HSI14 clock enable + HSI14ON: u1, + /// HR14 clock ready flag + HSI14RDY: u1, + /// HSI14 clock request from ADC disable + HSI14DIS: u1, + /// HSI14 clock trimming + HSI14TRIM: u5, + /// HSI14 clock calibration + HSI14CAL: u8, padding: u16, }), }; }; - pub const sdmmc_v1 = struct { - /// Secure digital input/output interface - pub const SDMMC = extern struct { - /// power control register - POWER: mmio.Mmio(packed struct(u32) { - /// PWRCTRL - PWRCTRL: u2, - padding: u30, - }), - /// SDI clock control register - CLKCR: mmio.Mmio(packed struct(u32) { - /// Clock divide factor - CLKDIV: u8, - /// Clock enable bit - CLKEN: u1, - /// Power saving configuration bit - PWRSAV: u1, - /// Clock divider bypass enable bit - BYPASS: u1, - /// Wide bus mode enable bit - WIDBUS: u2, - /// SDIO_CK dephasing selection bit - NEGEDGE: u1, - /// HW Flow Control enable - HWFC_EN: u1, - padding: u17, - }), - /// argument register - ARGR: mmio.Mmio(packed struct(u32) { - /// Command argument - CMDARG: u32, - }), - /// command register - CMDR: mmio.Mmio(packed struct(u32) { - /// Command index - CMDINDEX: u6, - /// Wait for response bits - WAITRESP: u2, - /// CPSM waits for interrupt request - WAITINT: u1, - /// CPSM Waits for ends of data transfer (CmdPend internal signal) - WAITPEND: u1, - /// Command path state machine (CPSM) Enable bit - CPSMEN: u1, - /// SD I/O suspend command - SDIOSuspend: u1, - padding: u20, - }), - /// command response register - RESPCMDR: mmio.Mmio(packed struct(u32) { - /// Response command index - RESPCMD: u6, - padding: u26, - }), - /// response 1..4 register - RESPR: [4]mmio.Mmio(packed struct(u32) { - /// see Table 132 - CARDSTATUS: u32, - }), - /// data timer register - DTIMER: mmio.Mmio(packed struct(u32) { - /// Data timeout period - DATATIME: u32, - }), - /// data length register - DLENR: mmio.Mmio(packed struct(u32) { - /// Data length value - DATALENGTH: u25, - padding: u7, - }), - /// data control register - DCTRL: mmio.Mmio(packed struct(u32) { - /// DTEN - DTEN: u1, - /// Data transfer direction selection - DTDIR: u1, - /// Data transfer mode selection 1: Stream or SDIO multibyte data transfer - DTMODE: u1, - /// DMA enable bit - DMAEN: u1, - /// Data block size - DBLOCKSIZE: u4, - /// Read wait start - RWSTART: u1, - /// Read wait stop - RWSTOP: u1, - /// Read wait mode - RWMOD: u1, - /// SD I/O enable functions - SDIOEN: u1, - padding: u20, - }), - /// data counter register - DCNTR: mmio.Mmio(packed struct(u32) { - /// Data count value - DATACOUNT: u25, - padding: u7, - }), - /// status register - STAR: mmio.Mmio(packed struct(u32) { - /// Command response received (CRC check failed) - CCRCFAIL: u1, - /// Data block sent/received (CRC check failed) - DCRCFAIL: u1, - /// Command response timeout - CTIMEOUT: u1, - /// Data timeout - DTIMEOUT: u1, - /// Transmit FIFO underrun error - TXUNDERR: u1, - /// Received FIFO overrun error - RXOVERR: u1, - /// Command response received (CRC check passed) - CMDREND: u1, - /// Command sent (no response required) - CMDSENT: u1, - /// Data end (data counter, SDIDCOUNT, is zero) - DATAEND: u1, - /// Start bit not detected on all data signals in wide bus mode - STBITERR: u1, - /// Data block sent/received (CRC check passed) - DBCKEND: u1, - /// Command transfer in progress - CMDACT: u1, - /// Data transmit in progress - TXACT: u1, - /// Data receive in progress - RXACT: u1, - /// Transmit FIFO half empty: at least 8 words can be written into the FIFO - TXFIFOHE: u1, - /// Receive FIFO half full: there are at least 8 words in the FIFO - RXFIFOHF: u1, - /// Transmit FIFO full - TXFIFOF: u1, - /// Receive FIFO full - RXFIFOF: u1, - /// Transmit FIFO empty - TXFIFOE: u1, - /// Receive FIFO empty - RXFIFOE: u1, - /// Data available in transmit FIFO - TXDAVL: u1, - /// Data available in receive FIFO - RXDAVL: u1, - /// SDIO interrupt received - SDIOIT: u1, - padding: u9, - }), - /// interrupt clear register - ICR: mmio.Mmio(packed struct(u32) { - /// CCRCFAIL flag clear bit - CCRCFAILC: u1, - /// DCRCFAIL flag clear bit - DCRCFAILC: u1, - /// CTIMEOUT flag clear bit - CTIMEOUTC: u1, - /// DTIMEOUT flag clear bit - DTIMEOUTC: u1, - /// TXUNDERR flag clear bit - TXUNDERRC: u1, - /// RXOVERR flag clear bit - RXOVERRC: u1, - /// CMDREND flag clear bit - CMDRENDC: u1, - /// CMDSENT flag clear bit - CMDSENTC: u1, - /// DATAEND flag clear bit - DATAENDC: u1, - /// STBITERR flag clear bit - STBITERRC: u1, - /// DBCKEND flag clear bit - DBCKENDC: u1, - reserved22: u11, - /// SDIOIT flag clear bit - SDIOITC: u1, - padding: u9, - }), - /// mask register - MASKR: mmio.Mmio(packed struct(u32) { - /// Command CRC fail interrupt enable - CCRCFAILIE: u1, - /// Data CRC fail interrupt enable - DCRCFAILIE: u1, - /// Command timeout interrupt enable - CTIMEOUTIE: u1, - /// Data timeout interrupt enable - DTIMEOUTIE: u1, - /// Tx FIFO underrun error interrupt enable - TXUNDERRIE: u1, - /// Rx FIFO overrun error interrupt enable - RXOVERRIE: u1, - /// Command response received interrupt enable - CMDRENDIE: u1, - /// Command sent interrupt enable - CMDSENTIE: u1, - /// Data end interrupt enable - DATAENDIE: u1, - /// STBITERR interrupt enable - STBITERRE: u1, - /// Data block end interrupt enable - DBCKENDIE: u1, - /// Command acting interrupt enable - CMDACTIE: u1, - /// Data transmit acting interrupt enable - TXACTIE: u1, - /// Data receive acting interrupt enable - RXACTIE: u1, - /// Tx FIFO half empty interrupt enable - TXFIFOHEIE: u1, - /// Rx FIFO half full interrupt enable - RXFIFOHFIE: u1, - /// Tx FIFO full interrupt enable - TXFIFOFIE: u1, - /// Rx FIFO full interrupt enable - RXFIFOFIE: u1, - /// Tx FIFO empty interrupt enable - TXFIFOEIE: u1, - /// Rx FIFO empty interrupt enable - RXFIFOEIE: u1, - /// Data available in Tx FIFO interrupt enable - TXDAVLIE: u1, - /// Data available in Rx FIFO interrupt enable - RXDAVLIE: u1, - /// SDIO mode interrupt received interrupt enable - SDIOITIE: u1, - padding: u9, - }), - reserved72: [8]u8, - /// FIFO counter register - FIFOCNT: mmio.Mmio(packed struct(u32) { - /// Remaining number of words to be written to or read from the FIFO - FIFOCOUNT: u24, - padding: u8, - }), - reserved128: [52]u8, - /// data FIFO register - FIFOR: mmio.Mmio(packed struct(u32) { - /// Receive and transmit FIFO data - FIFOData: u32, - }), + pub const rcc_f0v2 = struct { + pub const CECSW = enum(u1) { + /// HSI clock divided by 244 selected as CEC clock source + HSI_DIV_244 = 0x0, + /// LSE clock selected as CEC clock source + LSE = 0x1, }; - }; - pub const pwr_l1 = struct { - pub const PDDS = enum(u1) { - /// Enter Stop mode when the CPU enters deepsleep - STOP_MODE = 0x0, - /// Enter Standby mode when the CPU enters deepsleep - STANDBY_MODE = 0x1, + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, + _, }; - pub const VOS = enum(u2) { - /// Range 1 - Range1 = 0x1, - /// Range 2 - Range2 = 0x2, - /// Range 3 - Range3 = 0x3, - _, + pub const ICSW = enum(u1) { + /// HSI clock selected as I2C clock source + HSI = 0x0, + /// SYSCLK clock selected as I2C clock source + SYS = 0x1, }; - /// Power control - pub const PWR = extern struct { - /// power control register - CR: mmio.Mmio(packed struct(u32) { - /// Low-power deep sleep - LPSDSR: u1, - /// Power down deepsleep - PDDS: packed union { - raw: u1, - value: PDDS, - }, - /// Clear wakeup flag - CWUF: u1, - /// Clear standby flag - CSBF: u1, - /// Power voltage detector enable - PVDE: u1, - /// PVD level selection - PLS: u3, - /// Disable backup domain write protection - DBP: u1, - /// Ultralow power mode - ULP: u1, - /// Fast wakeup - FWU: u1, - /// Voltage scaling range selection - VOS: packed union { - raw: u2, - value: VOS, - }, - reserved14: u1, - /// Low power run mode - LPRUN: u1, - padding: u17, - }), - /// power control/status register - CSR: mmio.Mmio(packed struct(u32) { - /// Wakeup flag - WUF: u1, - /// Standby flag - SBF: u1, - /// PVD output - PVDO: u1, - /// Internal voltage reference (VREFINT) ready flag - VREFINTRDYF: u1, - /// Voltage Scaling select flag - VOSF: u1, - /// Regulator LP flag - REGLPF: u1, - reserved8: u2, - /// Enable WKUP pin 1 - EWUP: u1, - padding: u23, - }), - }; - }; - - pub const usbram_32_1024 = struct { - /// USB Endpoint memory - pub const USBRAM = extern struct { - /// USB Endpoint memory - MEM: [256]u32, - }; - }; - - pub const usart_v3 = struct { - pub const ABRMOD = enum(u2) { - /// Measurement of the start bit is used to detect the baud rate - Start = 0x0, - /// Falling edge to falling edge measurement - Edge = 0x1, - /// 0x7F frame detection - Frame7F = 0x2, - /// 0x55 frame detection - Frame55 = 0x3, - }; - - pub const ADDM = enum(u1) { - /// 4-bit address detection - Bit4 = 0x0, - /// 7-bit address detection - Bit7 = 0x1, - }; - - pub const CPHA = enum(u1) { - /// The first clock transition is the first data capture edge - First = 0x0, - /// The second clock transition is the first data capture edge - Second = 0x1, + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium high driving capability + MediumHigh = 0x1, + /// Medium low driving capability + MediumLow = 0x2, + /// High driving capability + High = 0x3, }; - pub const CPOL = enum(u1) { - /// Steady low value on CK pin outside transmission window - Low = 0x0, - /// Steady high value on CK pin outside transmission window - High = 0x1, + pub const MCOPRE = enum(u3) { + /// MCO is divided by 1 + Div1 = 0x0, + /// MCO is divided by 2 + Div2 = 0x1, + /// MCO is divided by 4 + Div4 = 0x2, + /// MCO is divided by 8 + Div8 = 0x3, + /// MCO is divided by 16 + Div16 = 0x4, + /// MCO is divided by 32 + Div32 = 0x5, + /// MCO is divided by 64 + Div64 = 0x6, + /// MCO is divided by 128 + Div128 = 0x7, }; - pub const DEP = enum(u1) { - /// DE signal is active high - High = 0x0, - /// DE signal is active low - Low = 0x1, + pub const MCOSEL = enum(u4) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// Internal RC 14 MHz (HSI14) oscillator clock selected + HSI14 = 0x1, + /// Internal low speed (LSI) oscillator clock selected + LSI = 0x2, + /// External low speed (LSE) oscillator clock selected + LSE = 0x3, + /// System clock selected + SYS = 0x4, + /// Internal RC 8 MHz (HSI) oscillator clock selected + HSI = 0x5, + /// External 4-32 MHz (HSE) oscillator clock selected + HSE = 0x6, + /// PLL clock selected (divided by 1 or 2, depending en PLLMCODIV) + PLL = 0x7, + _, }; - pub const IRLP = enum(u1) { - /// Normal mode - Normal = 0x0, - /// Low-power mode - LowPower = 0x1, + pub const PLLMCODIV = enum(u1) { + /// PLL is divided by 2 for MCO + Div2 = 0x0, + /// PLL is not divided for MCO + Div1 = 0x1, }; - pub const LBDL = enum(u1) { - /// 10-bit break detection - Bit10 = 0x0, - /// 11-bit break detection - Bit11 = 0x1, + pub const PLLMUL = enum(u4) { + /// PLL input clock x2 + Mul2 = 0x0, + /// PLL input clock x3 + Mul3 = 0x1, + /// PLL input clock x4 + Mul4 = 0x2, + /// PLL input clock x5 + Mul5 = 0x3, + /// PLL input clock x6 + Mul6 = 0x4, + /// PLL input clock x7 + Mul7 = 0x5, + /// PLL input clock x8 + Mul8 = 0x6, + /// PLL input clock x9 + Mul9 = 0x7, + /// PLL input clock x10 + Mul10 = 0x8, + /// PLL input clock x11 + Mul11 = 0x9, + /// PLL input clock x12 + Mul12 = 0xa, + /// PLL input clock x13 + Mul13 = 0xb, + /// PLL input clock x14 + Mul14 = 0xc, + /// PLL input clock x15 + Mul15 = 0xd, + /// PLL input clock x16 + Mul16 = 0xe, + _, }; - pub const M0 = enum(u1) { - /// 1 start bit, 8 data bits, n stop bits - Bit8 = 0x0, - /// 1 start bit, 9 data bits, n stop bits - Bit9 = 0x1, + pub const PLLSRC = enum(u1) { + /// HSI divided by 2 selected as PLL input clock + HSI_Div2 = 0x0, + /// HSE divided by PREDIV selected as PLL input clock + HSE_Div_PREDIV = 0x1, }; - pub const M1 = enum(u1) { - /// Use M0 to set the data bits - M0 = 0x0, - /// 1 start bit, 7 data bits, n stop bits - Bit7 = 0x1, + pub const PLLXTPRE = enum(u1) { + /// HSE clock not divided + Div1 = 0x0, + /// HSE clock divided by 2 + Div2 = 0x1, }; - pub const MSBFIRST = enum(u1) { - /// data is transmitted/received with data bit 0 first, following the start bit - LSB = 0x0, - /// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit - MSB = 0x1, + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, }; - pub const OVER8 = enum(u1) { - /// Oversampling by 16 - Oversampling16 = 0x0, - /// Oversampling by 8 - Oversampling8 = 0x1, + pub const PREDIV = enum(u4) { + /// PREDIV input clock not divided + Div1 = 0x0, + /// PREDIV input clock divided by 2 + Div2 = 0x1, + /// PREDIV input clock divided by 3 + Div3 = 0x2, + /// PREDIV input clock divided by 4 + Div4 = 0x3, + /// PREDIV input clock divided by 5 + Div5 = 0x4, + /// PREDIV input clock divided by 6 + Div6 = 0x5, + /// PREDIV input clock divided by 7 + Div7 = 0x6, + /// PREDIV input clock divided by 8 + Div8 = 0x7, + /// PREDIV input clock divided by 9 + Div9 = 0x8, + /// PREDIV input clock divided by 10 + Div10 = 0x9, + /// PREDIV input clock divided by 11 + Div11 = 0xa, + /// PREDIV input clock divided by 12 + Div12 = 0xb, + /// PREDIV input clock divided by 13 + Div13 = 0xc, + /// PREDIV input clock divided by 14 + Div14 = 0xd, + /// PREDIV input clock divided by 15 + Div15 = 0xe, + /// PREDIV input clock divided by 16 + Div16 = 0xf, }; - pub const PS = enum(u1) { - /// Even parity - Even = 0x0, - /// Odd parity - Odd = 0x1, + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, }; - pub const RWU = enum(u1) { - /// Receiver in active mode - Active = 0x0, - /// Receiver in mute mode - Mute = 0x1, + pub const SW = enum(u2) { + /// HSI oscillator used as system clock + HSI = 0x0, + /// HSE oscillator used as system clock + HSE = 0x1, + /// PLL used as system clock + PLL1_P = 0x2, + _, }; - pub const STOP = enum(u2) { - /// 1 stop bit - Stop1 = 0x0, - /// 0.5 stop bits - Stop0p5 = 0x1, - /// 2 stop bits - Stop2 = 0x2, - /// 1.5 stop bits - Stop1p5 = 0x3, + pub const USART1SW = enum(u2) { + /// PCLK selected as USART clock source + PCLK2 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const WAKE = enum(u1) { - /// USART wakeup on idle line - IdleLine = 0x0, - /// USART wakeup on address mark - AddressMark = 0x1, + pub const USARTSW = enum(u2) { + /// PCLK selected as USART clock source + PCLK1 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const WUS = enum(u2) { - /// WUF active on address match - Address = 0x0, - /// WuF active on Start bit detection - Start = 0x2, - /// WUF active on RXNE - RXNE = 0x3, + pub const USBSW = enum(u1) { + /// PLL clock selected as USB clock source + PLL1_P = 0x1, _, }; - /// Low-power Universal synchronous asynchronous receiver transmitter - pub const LPUART = extern struct { - /// Control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// USART enable - UE: u1, - /// USART enable in Stop mode - UESM: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: packed union { - raw: u1, - value: PS, - }, - /// Parity control enable - PCE: u1, - /// Receiver wakeup method - WAKE: packed union { - raw: u1, - value: WAKE, + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal High Speed clock enable + HSION: u1, + /// Internal High Speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal High Speed clock trimming + HSITRIM: u5, + /// Internal High Speed clock Calibration + HSICAL: u8, + /// External High Speed clock enable + HSEON: u1, + /// External High Speed clock ready flag + HSERDY: u1, + /// External High Speed clock Bypass + HSEBYP: u1, + /// Clock Security System enable + CSSON: u1, + reserved24: u4, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding: u6, + }), + /// Clock configuration register (RCC_CFGR) + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock Switch + SW: packed union { + raw: u2, + value: SW, }, - /// Word length - M0: packed union { - raw: u1, - value: M0, + /// System Clock Switch Status + SWS: packed union { + raw: u2, + value: SW, }, - /// Mute mode enable - MME: u1, - /// Character match interrupt enable - CMIE: u1, - /// Oversampling mode - OVER8: packed union { - raw: u1, - value: OVER8, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, }, - /// Driver Enable deassertion time - DEDT: u5, - /// Driver Enable assertion time - DEAT: u5, - /// Receiver timeout interrupt enable - RTOIE: u1, - /// End of Block interrupt enable - EOBIE: u1, - /// Word length - M1: packed union { - raw: u1, - value: M1, + /// APB Low speed prescaler (APB1) + PPRE: packed union { + raw: u3, + value: PPRE, }, - padding: u3, - }), - /// Control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// 7-bit Address Detection/4-bit Address Detection - ADDM: packed union { + reserved14: u3, + /// APCPRE is deprecated. See ADC field in CFGR2 register. + ADCPRE: u1, + reserved16: u1, + /// PLL input clock source + PLLSRC: packed union { raw: u1, - value: ADDM, + value: PLLSRC, }, - /// Line break detection length - LBDL: packed union { + /// HSE divider for PLL entry. Same bit as PREDIV[0] from CFGR2 register. Refer to it for its meaning + PLLXTPRE: packed union { raw: u1, - value: LBDL, + value: PLLXTPRE, }, - /// LIN break detection interrupt enable - LBDIE: u1, - reserved8: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: packed union { - raw: u1, - value: CPHA, + /// PLL Multiplication Factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, }, - /// Clock polarity - CPOL: packed union { - raw: u1, - value: CPOL, + reserved24: u2, + /// Microcontroller clock output + MCOSEL: packed union { + raw: u4, + value: MCOSEL, }, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: packed union { - raw: u2, - value: STOP, + /// Microcontroller Clock Output Prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, }, - /// LIN mode enable - LINEN: u1, - /// Swap TX/RX pins - SWAP: u1, - /// RX pin active level inversion - RXINV: u1, - /// TX pin active level inversion - TXINV: u1, - /// Binary data inversion - DATAINV: u1, - /// Most significant bit first - MSBFIRST: packed union { + /// PLL clock not divided for MCO + PLLMCODIV: packed union { raw: u1, - value: MSBFIRST, - }, - /// Auto baud rate enable - ABREN: u1, - /// Auto baud rate mode - ABRMOD: packed union { - raw: u2, - value: ABRMOD, + value: PLLMCODIV, }, - /// Receiver timeout enable - RTOEN: u1, - /// Address of the USART node - ADD: u8, }), - /// Control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: packed union { - raw: u1, - value: IRLP, - }, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method enable - ONEBIT: u1, - /// Overrun Disable - OVRDIS: u1, - /// DMA Disable on Reception Error - DDRE: u1, - /// Driver enable mode - DEM: u1, - /// Driver enable polarity selection - DEP: packed union { - raw: u1, - value: DEP, - }, - reserved17: u1, - /// Smartcard auto-retry count - SCARCNT: u3, - /// Wakeup from Stop mode interrupt flag selection - WUS: packed union { - raw: u2, - value: WUS, - }, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1, + /// Clock interrupt register (RCC_CIR) + CIR: mmio.Mmio(packed struct(u32) { + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + /// HSI14 ready interrupt flag + HSI14RDYF: u1, + reserved7: u1, + /// Clock Security System Interrupt flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + /// HSI14 ready interrupt enable + HSI14RDYIE: u1, + reserved16: u2, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + /// HSI 14 MHz Ready Interrupt Clear + HSI14RDYC: u1, + reserved23: u1, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, + }), + /// APB2 peripheral reset register (RCC_APB2RSTR) + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// SYSCFG and COMP reset + SYSCFGRST: u1, + reserved5: u4, + /// USART6 reset + USART6RST: u1, + /// USART7 reset + USART7RST: u1, + /// USART8 reset + USART8RST: u1, + reserved9: u1, + /// ADC interface reset + ADCRST: u1, + reserved11: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// USART1 reset + USART1RST: u1, + reserved16: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + reserved22: u3, + /// Debug MCU reset + DBGMCURST: u1, padding: u9, }), - /// Baud rate register - BRR: mmio.Mmio(packed struct(u32) { - /// USARTDIV - BRR: u16, - padding: u16, + /// APB1 peripheral reset register (RCC_APB1RSTR) + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + reserved4: u2, + /// Timer 6 reset + TIM6RST: u1, + /// TIM7 timer reset + TIM7RST: u1, + reserved8: u2, + /// Timer 14 reset + TIM14RST: u1, + reserved11: u2, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + reserved17: u2, + /// USART 2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// USART4 reset + USART4RST: u1, + /// USART5 reset + USART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB interface reset + USBRST: u1, + reserved25: u1, + /// CAN interface reset + CANRST: u1, + reserved27: u1, + /// Clock Recovery System interface reset + CRSRST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// HDMI CEC reset + CECRST: u1, + padding: u1, }), - reserved24: [8]u8, - /// Request register - RQR: mmio.Mmio(packed struct(u32) { - /// Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. - ABRRQ: u1, - /// Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available - SBKRQ: u1, - /// Mute mode request. Puts the USART in mute mode and sets the RWU flag. - MMRQ: u1, - /// Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition - RXFRQ: u1, - /// Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data. - TXFRQ: u1, - padding: u27, + /// AHB Peripheral Clock enable register (RCC_AHBENR) + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA clock enable + DMAEN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock enable + SRAMEN: u1, + reserved4: u1, + /// FLASH clock enable + FLASHEN: u1, + reserved6: u1, + /// CRC clock enable + CRCEN: u1, + reserved17: u10, + /// I/O port A clock enable + GPIOAEN: u1, + /// I/O port B clock enable + GPIOBEN: u1, + /// I/O port C clock enable + GPIOCEN: u1, + /// I/O port D clock enable + GPIODEN: u1, + /// I/O port E clock enable + GPIOEEN: u1, + /// I/O port F clock enable + GPIOFEN: u1, + reserved24: u1, + /// Touch sensing controller clock enable + TSCEN: u1, + padding: u7, }), - /// Interrupt & status register - ISR: mmio.Mmio(packed struct(u32) { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise error flag - NE: u1, - /// Overrun error - ORE: u1, - /// Idle line detected - IDLE: u1, - /// Read data register not empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS interrupt flag - CTSIF: u1, - /// CTS flag - CTS: u1, - /// Receiver timeout - RTOF: u1, - /// End of block flag - EOBF: u1, + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved5: u4, + /// USART6 clock enable + USART6EN: u1, + /// USART7 clock enable + USART7EN: u1, + /// USART8 clock enable + USART8EN: u1, + reserved9: u1, + /// ADC 1 interface clock enable + ADCEN: u1, + reserved11: u1, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, reserved14: u1, - /// Auto baud rate error - ABRE: u1, - /// Auto baud rate flag - ABRF: u1, - /// Busy flag - BUSY: u1, - /// character match flag - CMF: u1, - /// Send break flag - SBKF: u1, - /// Receiver wakeup from Mute mode - RWU: packed union { - raw: u1, - value: RWU, - }, - /// Wakeup from Stop mode flag - WUF: u1, - /// Transmit enable acknowledge flag - TEACK: u1, - /// Receive enable acknowledge flag - REACK: u1, + /// USART1 clock enable + USART1EN: u1, + reserved16: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + reserved22: u3, + /// MCU debug module clock enable + DBGMCUEN: u1, padding: u9, }), - /// Interrupt flag clear register - ICR: mmio.Mmio(packed struct(u32) { - /// Parity error clear flag - PE: u1, - /// Framing error clear flag - FE: u1, - /// Noise error clear flag - NE: u1, - /// Overrun error clear flag - ORE: u1, - /// Idle line detected clear flag - IDLE: u1, - reserved6: u1, - /// Transmission complete clear flag - TC: u1, - reserved8: u1, - /// LIN break detection clear flag - LBD: u1, - /// CTS clear flag - CTS: u1, - reserved11: u1, - /// Receiver timeout clear flag - RTOF: u1, - /// End of block clear flag - EOBF: u1, - reserved17: u4, - /// Character match clear flag - CMF: u1, - reserved20: u2, - /// Wakeup from Stop mode clear flag - WUF: u1, - padding: u11, + /// APB1 peripheral clock enable register (RCC_APB1ENR) + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + reserved4: u2, + /// Timer 6 clock enable + TIM6EN: u1, + /// TIM7 timer clock enable + TIM7EN: u1, + reserved8: u2, + /// Timer 14 clock enable + TIM14EN: u1, + reserved11: u2, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI 2 clock enable + SPI2EN: u1, + reserved17: u2, + /// USART 2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// USART4 clock enable + USART4EN: u1, + /// USART5 clock enable + USART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB interface clock enable + USBEN: u1, + reserved25: u1, + /// CAN interface clock enable + CANEN: u1, + reserved27: u1, + /// Clock Recovery System interface clock enable + CRSEN: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// HDMI CEC interface clock enable + CECEN: u1, + padding: u1, }), - /// Receive data register - RDR: mmio.Mmio(packed struct(u32) { - /// Data value - DR: u9, - padding: u23, + /// Backup domain control register (RCC_BDCR) + BDCR: mmio.Mmio(packed struct(u32) { + /// External Low Speed oscillator enable + LSEON: u1, + /// External Low Speed oscillator ready + LSERDY: u1, + /// External Low Speed oscillator bypass + LSEBYP: u1, + /// LSE oscillator drive capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + reserved8: u3, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, }), - /// Transmit data register - TDR: mmio.Mmio(packed struct(u32) { - /// Data value - DR: u9, - padding: u23, + /// Control/status register (RCC_CSR) + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low speed oscillator enable + LSION: u1, + /// Internal low speed oscillator ready + LSIRDY: u1, + reserved23: u21, + /// 1.8 V domain reset flag + V18PWRRSTF: u1, + /// Remove reset flag + RMVF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, }), - }; - - /// Universal synchronous asynchronous receiver transmitter - pub const USART = extern struct { - /// Control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// USART enable - UE: u1, - /// USART enable in Stop mode - UESM: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: packed union { - raw: u1, - value: PS, + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + reserved17: u17, + /// I/O port A reset + GPIOARST: u1, + /// I/O port B reset + GPIOBRST: u1, + /// I/O port C reset + GPIOCRST: u1, + /// I/O port D reset + GPIODRST: u1, + /// I/O port E reset + GPIOERST: u1, + /// I/O port F reset + GPIOFRST: u1, + reserved24: u1, + /// Touch sensing controller reset + TSCRST: u1, + padding: u7, + }), + /// Clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// PREDIV division factor + PREDIV: packed union { + raw: u4, + value: PREDIV, }, - /// Parity control enable - PCE: u1, - /// Receiver wakeup method - WAKE: packed union { + padding: u28, + }), + /// Clock configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SW: packed union { + raw: u2, + value: USART1SW, + }, + reserved4: u2, + /// I2C1 clock source selection + I2C1SW: packed union { raw: u1, - value: WAKE, + value: ICSW, }, - /// Word length - M0: packed union { + reserved6: u1, + /// HDMI CEC clock source selection + CECSW: packed union { raw: u1, - value: M0, + value: CECSW, }, - /// Mute mode enable - MME: u1, - /// Character match interrupt enable - CMIE: u1, - /// Oversampling mode - OVER8: packed union { + /// USB clock source selection + USBSW: packed union { raw: u1, - value: OVER8, + value: USBSW, }, - /// Driver Enable deassertion time - DEDT: u5, - /// Driver Enable assertion time - DEAT: u5, - /// Receiver timeout interrupt enable - RTOIE: u1, - /// End of Block interrupt enable - EOBIE: u1, - /// Word length - M1: packed union { - raw: u1, - value: M1, - }, - padding: u3, - }), - /// Control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// 7-bit Address Detection/4-bit Address Detection - ADDM: packed union { - raw: u1, - value: ADDM, - }, - /// Line break detection length - LBDL: packed union { - raw: u1, - value: LBDL, - }, - /// LIN break detection interrupt enable - LBDIE: u1, - reserved8: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: packed union { - raw: u1, - value: CPHA, - }, - /// Clock polarity - CPOL: packed union { - raw: u1, - value: CPOL, - }, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: packed union { - raw: u2, - value: STOP, - }, - /// LIN mode enable - LINEN: u1, - /// Swap TX/RX pins - SWAP: u1, - /// RX pin active level inversion - RXINV: u1, - /// TX pin active level inversion - TXINV: u1, - /// Binary data inversion - DATAINV: u1, - /// Most significant bit first - MSBFIRST: packed union { - raw: u1, - value: MSBFIRST, - }, - /// Auto baud rate enable - ABREN: u1, - /// Auto baud rate mode - ABRMOD: packed union { + /// ADCSW is deprecated. See ADC field in CFGR2 register. + ADCSW: u1, + reserved16: u7, + /// USART2 clock source selection + USART2SW: packed union { raw: u2, - value: ABRMOD, - }, - /// Receiver timeout enable - RTOEN: u1, - /// Address of the USART node - ADD: u8, - }), - /// Control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: packed union { - raw: u1, - value: IRLP, - }, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method enable - ONEBIT: u1, - /// Overrun Disable - OVRDIS: u1, - /// DMA Disable on Reception Error - DDRE: u1, - /// Driver enable mode - DEM: u1, - /// Driver enable polarity selection - DEP: packed union { - raw: u1, - value: DEP, + value: USARTSW, }, - reserved17: u1, - /// Smartcard auto-retry count - SCARCNT: u3, - /// Wakeup from Stop mode interrupt flag selection - WUS: packed union { + /// USART3 clock source + USART3SW: packed union { raw: u2, - value: WUS, + value: USARTSW, }, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1, - padding: u9, - }), - /// Baud rate register - BRR: mmio.Mmio(packed struct(u32) { - /// USARTDIV - BRR: u16, - padding: u16, + padding: u12, }), - /// Guard time and prescaler register - GTPR: mmio.Mmio(packed struct(u32) { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, + /// Clock control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// HSI14 clock enable + HSI14ON: u1, + /// HR14 clock ready flag + HSI14RDY: u1, + /// HSI14 clock request from ADC disable + HSI14DIS: u1, + /// HSI14 clock trimming + HSI14TRIM: u5, + /// HSI14 clock calibration + HSI14CAL: u8, padding: u16, }), - /// Receiver timeout register - RTOR: mmio.Mmio(packed struct(u32) { - /// Receiver timeout value - RTO: u24, - /// Block Length - BLEN: u8, - }), - /// Request register - RQR: mmio.Mmio(packed struct(u32) { - /// Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. - ABRRQ: u1, - /// Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available - SBKRQ: u1, - /// Mute mode request. Puts the USART in mute mode and sets the RWU flag. - MMRQ: u1, - /// Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition - RXFRQ: u1, - /// Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data. - TXFRQ: u1, - padding: u27, - }), - /// Interrupt & status register - ISR: mmio.Mmio(packed struct(u32) { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise error flag - NE: u1, - /// Overrun error - ORE: u1, - /// Idle line detected - IDLE: u1, - /// Read data register not empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS interrupt flag - CTSIF: u1, - /// CTS flag - CTS: u1, - /// Receiver timeout - RTOF: u1, - /// End of block flag - EOBF: u1, - reserved14: u1, - /// Auto baud rate error - ABRE: u1, - /// Auto baud rate flag - ABRF: u1, - /// Busy flag - BUSY: u1, - /// character match flag - CMF: u1, - /// Send break flag - SBKF: u1, - /// Receiver wakeup from Mute mode - RWU: packed union { - raw: u1, - value: RWU, - }, - /// Wakeup from Stop mode flag - WUF: u1, - /// Transmit enable acknowledge flag - TEACK: u1, - /// Receive enable acknowledge flag - REACK: u1, - padding: u9, - }), - /// Interrupt flag clear register - ICR: mmio.Mmio(packed struct(u32) { - /// Parity error clear flag - PE: u1, - /// Framing error clear flag - FE: u1, - /// Noise error clear flag - NE: u1, - /// Overrun error clear flag - ORE: u1, - /// Idle line detected clear flag - IDLE: u1, - reserved6: u1, - /// Transmission complete clear flag - TC: u1, - reserved8: u1, - /// LIN break detection clear flag - LBD: u1, - /// CTS clear flag - CTS: u1, - reserved11: u1, - /// Receiver timeout clear flag - RTOF: u1, - /// End of block clear flag - EOBF: u1, - reserved17: u4, - /// Character match clear flag - CMF: u1, - reserved20: u2, - /// Wakeup from Stop mode clear flag - WUF: u1, - padding: u11, - }), - /// Receive data register - RDR: mmio.Mmio(packed struct(u32) { - /// Data value - DR: u9, - padding: u23, - }), - /// Transmit data register - TDR: mmio.Mmio(packed struct(u32) { - /// Data value - DR: u9, - padding: u23, - }), }; }; - pub const syscfg_u0 = struct { - pub const IR_MOD = enum(u2) { - /// TIM16 - TIM16 = 0x0, - /// USART1 - USART1 = 0x1, - /// USART2 - USART2 = 0x2, - _, + pub const rcc_f0v3 = struct { + pub const CECSW = enum(u1) { + /// HSI clock divided by 244 selected as CEC clock source + HSI_DIV_244 = 0x0, + /// LSE clock selected as CEC clock source + LSE = 0x1, }; - pub const MEM_MODE = enum(u2) { - /// System flash memory mapped at 0x000010000 - System_Flash = 0x1, - /// Embedded SRAM mapped at 0x000010000 - SRAM = 0x3, + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, _, }; - /// SYSCFG register block - pub const SYSCFG = extern struct { - /// SYSCFG configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection bits These bits are set and cleared by software. They control the memory internal mapping at address 0x000010000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section12.5: Boot configuration for more details. X0: Main flash memory mapped at 0x000010000 - MEM_MODE: packed union { - raw: u2, - value: MEM_MODE, - }, - reserved3: u1, - /// PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. 0: No remap (PA11) 1: Remap (PA9) - PA11_RMP: u1, - /// PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. 0: No remap (PA12) 1: Remap (PA10) - PA12_RMP: u1, - /// IR output polarity selection - IR_POL: u1, - /// IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope: - IR_MOD: packed union { - raw: u2, - value: IR_MOD, - }, - /// I/O analog switch voltage booster enable This bit selects the way of supplying I/O analog switches: When using the analog inputs , setting to 0 is recommended for high VDD, setting to 1 for low VDD (less than 2.4 V). - BOOSTEN: u1, - reserved16: u7, - /// Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable - I2C_PB6_FMP: u1, - /// Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable - I2C_PB7_FMP: u1, - /// Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable - I2C_PB8_FMP: u1, - /// Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable - I2C_PB9_FMP: u1, - reserved22: u2, - /// Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable - I2C_PA9_FMP: u1, - /// Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable - I2C_PA10_FMP: u1, - /// Fast Mode Plus (FM+) enable for I2C3 This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers. With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C3 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable - I2C3_FMP: u1, - padding: u7, - }), - reserved24: [20]u8, - /// SYSCFG configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// Cortex1-M0+ LOCKUP bit enable bit This bit is set by software and cleared by a system reset. It can be use to enable and lock the connection of Cortex1-M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input. - CCL: u1, - /// SRAM1 parity lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM1 parity error signal connection to TIM1/15/16 Break input. - SPL: u1, - /// PVD lock enable bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register. - PVDL: u1, - /// ECC error lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash ECC 2-bit error detection signal connection to TIM1/15/16 Break input. - ECCL: u1, - /// Backup SRAM2 parity lock This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break input. - BKPL: u1, - reserved7: u2, - /// Backup SRAM2 parity error flag This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1. - BKPF: u1, - /// SRAM1 parity error flag This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software by writing 1. - SPF: u1, - padding: u23, - }), - /// SYSCFG SRAM2 control and status register - SCSR: mmio.Mmio(packed struct(u32) { - /// SRAM2 erase Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation. Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register. - SRAM2ER: u1, - /// SRAM2 busy by erase operation - SRAM2BSY: u1, - padding: u30, - }), - /// SYSCFG SRAM2 key register - SKR: mmio.Mmio(packed struct(u32) { - /// SRAM2 write protection key for software erase The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register: Write 0xCA into KEY[7:0] Write 0x53 into KEY[7:0] Writing a wrong key reactivates the write protection. - KEY: u8, - padding: u24, - }), - /// SYSCFG TSC comparator register - TSCCR: mmio.Mmio(packed struct(u32) { - /// Comparator mode for group 2 on I/O 1 - G2_IO1: u1, - /// Comparator mode for group 2 on I/O 3 - G2_IO3: u1, - /// Comparator mode for group 4 on I/O 3 - G4_IO3: u1, - /// Comparator mode for group 6 on I/O 1 - G6_IO1: u1, - /// Comparator mode for group 7 on I/O 1 - G7_IO1: u1, - /// I/O control in comparator mode The I/O control in comparator mode can be overwritten by hardware. - TSC_IOCTRL: u1, - padding: u26, - }), - reserved128: [88]u8, - /// SYSCFG interrupt line 0 status register - ITLINE0: mmio.Mmio(packed struct(u32) { - /// Window watchdog interrupt pending flag - WWDG: u1, - padding: u31, - }), - /// SYSCFG interrupt line 1 status register - ITLINE1: mmio.Mmio(packed struct(u32) { - /// PVD supply monitoring interrupt request pending (EXTI line 16). - PVDOUT: u1, - /// VDDUSB supply monitoring interrupt request pending (EXTI line 19) - PVMOUT1: u1, - /// ADC supply monitoring interrupt request pending (EXTI line 20) - PVMOUT3: u1, - /// DAC supply monitoring interrupt request pending (EXTI line 21) - PVMOUT4: u1, - padding: u28, - }), - /// SYSCFG interrupt line 2 status register - ITLINE2: mmio.Mmio(packed struct(u32) { - /// Tamper interrupt request pending (EXTI line 21) - TAMP: u1, - /// RTC interrupt request pending (EXTI line 19) - RTC: u1, - padding: u30, - }), - /// SYSCFG interrupt line 3 status register - ITLINE3: mmio.Mmio(packed struct(u32) { - /// Flash interface interrupt request pending - FLASH_ITF: u1, - /// Flash interface ECC interrupt request pending - FLASH_ECC: u1, - padding: u30, - }), - /// SYSCFG interrupt line 4 status register - ITLINE4: mmio.Mmio(packed struct(u32) { - /// Reset and clock control interrupt request pending - RCC: u1, - /// CRS interrupt request pending - CRS: u1, - padding: u30, - }), - /// SYSCFG interrupt line 5 status register - ITLINE5: mmio.Mmio(packed struct(u32) { - /// EXTI line 0 interrupt request pending - EXTI0: u1, - /// EXTI line 1 interrupt request pending - EXTI1: u1, - padding: u30, - }), - /// SYSCFG interrupt line 6 status register - ITLINE6: mmio.Mmio(packed struct(u32) { - /// EXTI line 2 interrupt request pending - EXTI2: u1, - /// EXTI line 3 interrupt request pending - EXTI3: u1, - padding: u30, - }), - /// SYSCFG interrupt line 7 status register - ITLINE7: mmio.Mmio(packed struct(u32) { - /// EXTI line 4 interrupt request pending - EXTI4: u1, - /// EXTI line 5 interrupt request pending - EXTI5: u1, - /// EXTI line 6 interrupt request pending - EXTI6: u1, - /// EXTI line 7 interrupt request pending - EXTI7: u1, - /// EXTI line 8 interrupt request pending - EXTI8: u1, - /// EXTI line 9 interrupt request pending - EXTI9: u1, - /// EXTI line 10 interrupt request pending - EXTI10: u1, - /// EXTI line 11 interrupt request pending - EXTI11: u1, - /// EXTI line 12 interrupt request pending - EXTI12: u1, - /// EXTI line 13 interrupt request pending - EXTI13: u1, - /// EXTI line 14 interrupt request pending - EXTI14: u1, - /// EXTI line 15 interrupt request pending - EXTI15: u1, - padding: u20, - }), - /// SYSCFG interrupt line 8 status register - ITLINE8: mmio.Mmio(packed struct(u32) { - /// USB interrupt request pending - USB: u1, - padding: u31, - }), - /// SYSCFG interrupt line 9 status register - ITLINE9: mmio.Mmio(packed struct(u32) { - /// DMA1 channel 1 interrupt request pending - DMA1_CH1: u1, - padding: u31, - }), - /// SYSCFG interrupt line 10 status register - ITLINE10: mmio.Mmio(packed struct(u32) { - /// DMA1 channel 2 interrupt request pending - DMA1_CH2: u1, - /// DMA1 channel 3 interrupt request pending - DMA1_CH3: u1, - padding: u30, - }), - /// SYSCFG interrupt line 11 status register - ITLINE11: mmio.Mmio(packed struct(u32) { - /// DMAMUX interrupt request pending - DMAMUX: u1, - /// DMA1 channel 4 interrupt request pending - DMA1_CH4: u1, - /// DMA1 channel 5 interrupt request pending - DMA1_CH5: u1, - /// DMA1 channel 6 interrupt request pending - DMA1_CH6: u1, - /// DMA1 channel 7 interrupt request pending - DMA1_CH7: u1, - /// DMA2 channel 1 interrupt request pending - DMA2_CH1: u1, - /// DMA2 channel 2 interrupt request pending - DMA2_CH2: u1, - /// DMA2 channel 3 interrupt request pending - DMA2_CH3: u1, - /// DMA2 channel 4 interrupt request pending - DMA2_CH4: u1, - /// DMA2 channel 5 interrupt request pending - DMA2_CH5: u1, - padding: u22, - }), - /// SYSCFG interrupt line 12 status register - ITLINE12: mmio.Mmio(packed struct(u32) { - /// ADC interrupt request pending - ADC: u1, - /// Comparator 1 interrupt request pending (EXTI line 17) - COMP1: u1, - /// Comparator 2 interrupt request pending (EXTI line 18) - COMP2: u1, - padding: u29, - }), - /// SYSCFG interrupt line 13 status register - ITLINE13: mmio.Mmio(packed struct(u32) { - /// Timer 1 commutation interrupt request pending - TIM1_CCU: u1, - /// Timer 1 trigger interrupt request pending - TIM1_TRG: u1, - /// Timer 1 update interrupt request pending - TIM1_UPD: u1, - /// Timer 1 break interrupt request pending - TIM1_BRK: u1, - padding: u28, - }), - /// SYSCFG interrupt line 14 status register - ITLINE14: mmio.Mmio(packed struct(u32) { - /// Timer 1 capture compare 1 interrupt request pending - TIM1_CC1: u1, - /// Timer 1 capture compare 2 interrupt request pending - TIM1_CC2: u1, - /// Timer 1 capture compare 3 interrupt request pending - TIM1_CC3: u1, - /// Timer 1 capture compare 4 interrupt request pending - TIM1_CC4: u1, - padding: u28, - }), - /// SYSCFG interrupt line 15 status register - ITLINE15: mmio.Mmio(packed struct(u32) { - /// Timer 2 interrupt request pending - TIM2: u1, - padding: u31, - }), - /// SYSCFG interrupt line 16 status register - ITLINE16: mmio.Mmio(packed struct(u32) { - /// Timer 3 interrupt request pending - TIM3: u1, - padding: u31, - }), - /// SYSCFG interrupt line 17 status register - ITLINE17: mmio.Mmio(packed struct(u32) { - /// Timer 6 interrupt request pending - TIM6: u1, - /// DAC underrun interrupt request pending - DAC: u1, - /// Low-power timer 1 interrupt request pending (EXTI line 29) - LPTIM1: u1, - padding: u29, - }), - /// SYSCFG interrupt line 18 status register - ITLINE18: mmio.Mmio(packed struct(u32) { - /// Timer 7 interrupt request pending - TIM7: u1, - /// Low-power timer 2 interrupt request pending (EXTI line 30) - LPTIM2: u1, - padding: u30, - }), - /// SYSCFG interrupt line 19 status register - ITLINE19: mmio.Mmio(packed struct(u32) { - /// Timer 15 interrupt request pending - TIM15: u1, - /// Low-power timer 3 interrupt request pending - LPTIM3: u1, - padding: u30, - }), - /// SYSCFG interrupt line 20 status register - ITLINE20: mmio.Mmio(packed struct(u32) { - /// Timer 16 interrupt request pending - TIM16: u1, - padding: u31, - }), - /// SYSCFG interrupt line 21 status register - ITLINE21: mmio.Mmio(packed struct(u32) { - /// TSC max count error interrupt request pending - TSC_MCE: u1, - /// TSC end of acquisition interrupt request pending - TSC_EOA: u1, - padding: u30, - }), - /// SYSCFG interrupt line 22 status register - ITLINE22: mmio.Mmio(packed struct(u32) { - /// LCD interrupt request pending - LCD: u1, - padding: u31, - }), - /// SYSCFG interrupt line 23 status register - ITLINE23: mmio.Mmio(packed struct(u32) { - /// I2C1 interrupt request pending (EXTI line 33) - I2C1: u1, - padding: u31, - }), - /// SYSCFG interrupt line 24 status register - ITLINE24: mmio.Mmio(packed struct(u32) { - /// I2C2 interrupt request pending - I2C2: u1, - /// I2C4 interrupt request pending - I2C4: u1, - /// I2C3 interrupt request pending (EXTI line 23) - I2C3: u1, - padding: u29, - }), - /// SYSCFG interrupt line 25 status register - ITLINE25: mmio.Mmio(packed struct(u32) { - /// SPI1 interrupt request pending - SPI1: u1, - padding: u31, - }), - /// SYSCFG interrupt line 26 status register - ITLINE26: mmio.Mmio(packed struct(u32) { - /// SPI2 interrupt request pending - SPI2: u1, - /// SPI3 interrupt request pending - SPI3: u1, - padding: u30, - }), - /// SYSCFG interrupt line 27 status register - ITLINE27: mmio.Mmio(packed struct(u32) { - /// USART1 interrupt request pending, combined with EXTI line 25 - USART1: u1, - padding: u31, - }), - /// SYSCFG interrupt line 28 status register - ITLINE28: mmio.Mmio(packed struct(u32) { - /// USART2 interrupt request pending (EXTI line 35) - USART2: u1, - /// LPUART2 interrupt request pending (EXTI line 31) - LPUART2: u1, - padding: u30, - }), - /// SYSCFG interrupt line 29 status register - ITLINE29: mmio.Mmio(packed struct(u32) { - /// USART3 interrupt request pending - USART3: u1, - /// LPUART1 interrupt request pending (EXTI line 30) - LPUART1: u1, - padding: u30, - }), - /// SYSCFG interrupt line 30 status register - ITLINE30: mmio.Mmio(packed struct(u32) { - /// USART4 interrupt request pending - USART4: u1, - /// LPUART3 interrupt request pending (EXTI line 32) - LPUART3: u1, - padding: u30, - }), - /// SYSCFG interrupt line 31 status register - ITLINE31: mmio.Mmio(packed struct(u32) { - /// RNG interrupt request pending - RNG: u1, - /// AES interrupt request pending - AES: u1, - padding: u30, - }), + pub const ICSW = enum(u1) { + /// HSI clock selected as I2C clock source + HSI = 0x0, + /// SYSCLK clock selected as I2C clock source + SYS = 0x1, }; - }; - pub const cec_v2 = struct { - /// CEC. - pub const CEC = extern struct { - /// CEC control register. - CR: mmio.Mmio(packed struct(u32) { - /// CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission. - CECEN: u1, - /// Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception. - TXSOM: u1, - /// Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message). - TXEOM: u1, - padding: u29, - }), - /// This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0. - CFGR: mmio.Mmio(packed struct(u32) { - /// Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods. - SFT: u3, - /// Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall. - RXTOL: u1, - /// Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software. - BRESTP: u1, - /// Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0. - BREGEN: u1, - /// Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0. - LBPEGEN: u1, - /// Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software. - BRDNOGEN: u1, - /// SFT Option Bit The SFTOPT bit is set and cleared by software. - SFTOPT: u1, - reserved16: u7, - /// Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received. - OAR: u15, - /// Listen mode LSTN bit is set and cleared by software. - LSTN: u1, - }), - /// CEC Tx data register. - TXDR: mmio.Mmio(packed struct(u32) { - /// Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1. - TXD: u8, - padding: u24, - }), - /// CEC Rx Data Register. - RXDR: mmio.Mmio(packed struct(u32) { - /// Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line. - RXD: u8, - padding: u24, - }), - /// CEC Interrupt and Status Register. - ISR: mmio.Mmio(packed struct(u32) { - /// Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1. - RXBR: u1, - /// End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1. - RXEND: u1, - /// Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1. - RXOVR: u1, - /// Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1. - BRE: u1, - /// Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1. - SBPE: u1, - /// Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1. - LBPE: u1, - /// Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1. - RXACKE: u1, - /// Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1. - ARBLST: u1, - /// Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1. - TXBR: u1, - /// End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1. - TXEND: u1, - /// Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1. - TXUDR: u1, - /// Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1. - TXERR: u1, - /// Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1. - TXACKE: u1, - padding: u19, - }), - /// CEC interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software. - RXBRIE: u1, - /// End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software. - RXENDIE: u1, - /// Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software. - RXOVRIE: u1, - /// Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software. - BREIE: u1, - /// Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software. - SBPEIE: u1, - /// Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software. - LBPEIE: u1, - /// Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software. - RXACKIE: u1, - /// Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software. - ARBLSTIE: u1, - /// Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software. - TXBRIE: u1, - /// Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software. - TXENDIE: u1, - /// Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software. - TXUDRIE: u1, - /// Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software. - TXERRIE: u1, - /// Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software. - TXACKIE: u1, - padding: u19, - }), + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium high driving capability + MediumHigh = 0x1, + /// Medium low driving capability + MediumLow = 0x2, + /// High driving capability + High = 0x3, }; - }; - pub const adc_g4 = struct { - pub const ADCALDIF = enum(u1) { - /// Calibration for single-ended mode - SingleEnded = 0x0, - /// Calibration for differential mode - Differential = 0x1, + pub const MCOPRE = enum(u3) { + /// MCO is divided by 1 + Div1 = 0x0, + /// MCO is divided by 2 + Div2 = 0x1, + /// MCO is divided by 4 + Div4 = 0x2, + /// MCO is divided by 8 + Div8 = 0x3, + /// MCO is divided by 16 + Div16 = 0x4, + /// MCO is divided by 32 + Div32 = 0x5, + /// MCO is divided by 64 + Div64 = 0x6, + /// MCO is divided by 128 + Div128 = 0x7, }; - pub const ADSTP = enum(u1) { - /// Stop conversion of channel - Stop = 0x1, + pub const MCOSEL = enum(u4) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// Internal RC 14 MHz (HSI14) oscillator clock selected + HSI14 = 0x1, + /// Internal low speed (LSI) oscillator clock selected + LSI = 0x2, + /// External low speed (LSE) oscillator clock selected + LSE = 0x3, + /// System clock selected + SYS = 0x4, + /// Internal RC 8 MHz (HSI) oscillator clock selected + HSI = 0x5, + /// External 4-32 MHz (HSE) oscillator clock selected + HSE = 0x6, + /// PLL clock selected (divided by 1 or 2, depending en PLLMCODIV) + PLL = 0x7, _, }; - pub const AWD1SGL = enum(u1) { - /// Analog watchdog 1 enabled on all channels - All = 0x0, - /// Analog watchdog 1 enabled on single channel selected in AWD1CH - Single = 0x1, + pub const PLLMCODIV = enum(u1) { + /// PLL is divided by 2 for MCO + Div2 = 0x0, + /// PLL is not divided for MCO + Div1 = 0x1, }; - pub const DIFSEL = enum(u1) { - /// Input channel is configured in single-ended mode - SingleEnded = 0x0, - /// Input channel is configured in differential mode - Differential = 0x1, + pub const PLLMUL = enum(u4) { + /// PLL input clock x2 + Mul2 = 0x0, + /// PLL input clock x3 + Mul3 = 0x1, + /// PLL input clock x4 + Mul4 = 0x2, + /// PLL input clock x5 + Mul5 = 0x3, + /// PLL input clock x6 + Mul6 = 0x4, + /// PLL input clock x7 + Mul7 = 0x5, + /// PLL input clock x8 + Mul8 = 0x6, + /// PLL input clock x9 + Mul9 = 0x7, + /// PLL input clock x10 + Mul10 = 0x8, + /// PLL input clock x11 + Mul11 = 0x9, + /// PLL input clock x12 + Mul12 = 0xa, + /// PLL input clock x13 + Mul13 = 0xb, + /// PLL input clock x14 + Mul14 = 0xc, + /// PLL input clock x15 + Mul15 = 0xd, + /// PLL input clock x16 + Mul16 = 0xe, + _, }; - pub const DMACFG = enum(u1) { - /// DMA One Shot mode selected - OneShot = 0x0, - /// DMA Circular mode selected - Circular = 0x1, + pub const PLLSRC = enum(u2) { + /// HSI divided by 2 selected as PLL input clock + HSI_Div2 = 0x0, + /// HSI divided by PREDIV selected as PLL input clock + HSI_Div_PREDIV = 0x1, + /// HSE divided by PREDIV selected as PLL input clock + HSE_Div_PREDIV = 0x2, + _, }; - pub const DMAEN = enum(u1) { - /// DMA disable - Disable = 0x0, - /// DMA enable - Enable = 0x1, + pub const PLLXTPRE = enum(u1) { + /// HSE clock not divided + Div1 = 0x0, + /// HSE clock divided by 2 + Div2 = 0x1, }; - pub const EXTEN = enum(u2) { - /// Trigger detection disabled - Disabled = 0x0, - /// Trigger detection on the rising edge - RisingEdge = 0x1, - /// Trigger detection on the falling edge - FallingEdge = 0x2, - /// Trigger detection on both the rising and falling edges - BothEdges = 0x3, + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, }; - pub const JEXTEN = enum(u2) { - /// Trigger detection disabled - Disabled = 0x0, - /// Trigger detection on the rising edge - RisingEdge = 0x1, - /// Trigger detection on the falling edge - FallingEdge = 0x2, - /// Trigger detection on both the rising and falling edges - BothEdges = 0x3, + pub const PREDIV = enum(u4) { + /// PREDIV input clock not divided + Div1 = 0x0, + /// PREDIV input clock divided by 2 + Div2 = 0x1, + /// PREDIV input clock divided by 3 + Div3 = 0x2, + /// PREDIV input clock divided by 4 + Div4 = 0x3, + /// PREDIV input clock divided by 5 + Div5 = 0x4, + /// PREDIV input clock divided by 6 + Div6 = 0x5, + /// PREDIV input clock divided by 7 + Div7 = 0x6, + /// PREDIV input clock divided by 8 + Div8 = 0x7, + /// PREDIV input clock divided by 9 + Div9 = 0x8, + /// PREDIV input clock divided by 10 + Div10 = 0x9, + /// PREDIV input clock divided by 11 + Div11 = 0xa, + /// PREDIV input clock divided by 12 + Div12 = 0xb, + /// PREDIV input clock divided by 13 + Div13 = 0xc, + /// PREDIV input clock divided by 14 + Div14 = 0xd, + /// PREDIV input clock divided by 15 + Div15 = 0xe, + /// PREDIV input clock divided by 16 + Div16 = 0xf, }; - pub const JQM = enum(u1) { - /// JSQR Mode 0: Queue maintains the last written configuration into JSQR - Mode0 = 0x0, - /// JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence - Mode1 = 0x1, + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, }; - pub const OVRMOD = enum(u1) { - /// Preserve DR register when an overrun is detected - Preserve = 0x0, - /// Overwrite DR register when an overrun is detected - Overwrite = 0x1, + pub const SW = enum(u2) { + /// HSI oscillator used as system clock + HSI = 0x0, + /// HSE oscillator used as system clock + HSE = 0x1, + /// PLL used as system clock + PLL1_P = 0x2, + _, }; - pub const RES = enum(u2) { - /// 12-bit resolution - Bits12 = 0x0, - /// 10-bit resolution - Bits10 = 0x1, - /// 8-bit resolution - Bits8 = 0x2, - /// 6-bit resolution - Bits6 = 0x3, - }; - - pub const ROVSM = enum(u1) { - /// Oversampling is temporary stopped and continued after injection sequence - Continued = 0x0, - /// Oversampling is aborted and resumed from start after injection sequence - Resumed = 0x1, + pub const USART1SW = enum(u2) { + /// PCLK selected as USART clock source + PCLK2 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const SAMPLE_TIME = enum(u3) { - /// 2.5 clock cycles - Cycles2_5 = 0x0, - /// 6.5 clock cycles - Cycles6_5 = 0x1, - /// 12.5 clock cycles - Cycles12_5 = 0x2, - /// 24.5 clock cycles - Cycles24_5 = 0x3, - /// 47.5 clock cycles - Cycles47_5 = 0x4, - /// 92.5 clock cycles - Cycles92_5 = 0x5, - /// 247.5 clock cycles - Cycles247_5 = 0x6, - /// 640.5 clock cycles - Cycles640_5 = 0x7, + pub const USARTSW = enum(u2) { + /// PCLK selected as USART clock source + PCLK1 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const TROVS = enum(u1) { - /// All oversampled conversions for a channel are done consecutively following a trigger - Automatic = 0x0, - /// Each oversampled conversion for a channel needs a new trigger - Triggered = 0x1, + pub const USBSW = enum(u1) { + /// PLL clock selected as USB clock source + PLL1_P = 0x1, + _, }; - /// Analog to Digital Converter - pub const ADC = extern struct { - /// interrupt and status register - ISR: mmio.Mmio(packed struct(u32) { - /// ready flag - ADRDY: u1, - /// group regular end of sampling flag - EOSMP: u1, - /// group regular end of unitary conversion flag - EOC: u1, - /// group regular end of sequence conversions flag - EOS: u1, - /// group regular overrun flag - OVR: u1, - /// group injected end of unitary conversion flag - JEOC: u1, - /// group injected end of sequence conversions flag - JEOS: u1, - /// analog watchdog 1 flag - AWD1: u1, - /// analog watchdog 2 flag - AWD2: u1, - /// analog watchdog 3 flag - AWD3: u1, - /// group injected contexts queue overflow flag - JQOVF: u1, - padding: u21, - }), - /// interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// ready interrupt - ADRDYIE: u1, - /// group regular end of sampling interrupt - EOSMPIE: u1, - /// group regular end of unitary conversion interrupt - EOCIE: u1, - /// group regular end of sequence conversions interrupt - EOSIE: u1, - /// group regular overrun interrupt - OVRIE: u1, - /// group injected end of unitary conversion interrupt - JEOCIE: u1, - /// group injected end of sequence conversions interrupt - JEOSIE: u1, - /// analog watchdog 1 interrupt - AWD1IE: u1, - /// analog watchdog 2 interrupt - AWD2IE: u1, - /// analog watchdog 3 interrupt - AWD3IE: u1, - /// group injected contexts queue overflow interrupt - JQOVFIE: u1, - padding: u21, - }), - /// control register + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register CR: mmio.Mmio(packed struct(u32) { - /// enable - ADEN: u1, - /// disable - ADDIS: u1, - /// group regular conversion start - ADSTART: u1, - /// group injected conversion start - JADSTART: u1, - /// group regular conversion stop - ADSTP: packed union { - raw: u1, - value: ADSTP, - }, - /// group injected conversion stop - JADSTP: packed union { - raw: u1, - value: ADSTP, - }, - reserved28: u22, - /// voltage regulator enable - ADVREGEN: u1, - /// deep power down enable - DEEPPWD: u1, - /// differential mode for calibration - ADCALDIF: packed union { - raw: u1, - value: ADCALDIF, - }, - /// calibration - ADCAL: u1, + /// Internal High Speed clock enable + HSION: u1, + /// Internal High Speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal High Speed clock trimming + HSITRIM: u5, + /// Internal High Speed clock Calibration + HSICAL: u8, + /// External High Speed clock enable + HSEON: u1, + /// External High Speed clock ready flag + HSERDY: u1, + /// External High Speed clock Bypass + HSEBYP: u1, + /// Clock Security System enable + CSSON: u1, + reserved24: u4, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding: u6, }), - /// configuration register 1 + /// Clock configuration register (RCC_CFGR) CFGR: mmio.Mmio(packed struct(u32) { - /// Direct memory access configuration - DMACFG: packed union { - raw: u1, - value: DMACFG, - }, - reserved3: u2, - /// data resolution - RES: packed union { + /// System clock Switch + SW: packed union { raw: u2, - value: RES, + value: SW, }, - /// external trigger selection for regular group - EXTSEL: u5, - /// external trigger enable and polarity selection for regular channels - EXTEN: packed union { + /// System Clock Switch Status + SWS: packed union { raw: u2, - value: EXTEN, + value: SW, }, - /// overrun mode - OVRMOD: packed union { - raw: u1, - value: OVRMOD, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, }, - /// Continuous conversion - CONT: u1, - /// delayed conversion mode - AUTDLY: u1, - /// data alignment - ALIGN: u1, - /// discontinuous mode for regular channels - DISCEN: u1, - /// discontinuous mode channel count - DISCNUM: u3, - /// discontinuous mode on injected channels - JDISCEN: u1, - /// JSQR queue mode - JQM: packed union { - raw: u1, - value: JQM, + /// APB Low speed prescaler (APB1) + PPRE: packed union { + raw: u3, + value: PPRE, }, - /// enable the watchdog 1 on a single channel or on all channels - AWD1SGL: packed union { - raw: u1, - value: AWD1SGL, + reserved14: u3, + /// APCPRE is deprecated. See ADC field in CFGR2 register. + ADCPRE: u1, + /// PLL input clock source + PLLSRC: packed union { + raw: u2, + value: PLLSRC, }, - /// analog watchdog 1 enable on regular channels - AWD1EN: u1, - /// analog watchdog 1 enable on injected channels - JAWD1EN: u1, - /// automatic injected group conversion - JAUTO: u1, - /// analog watchdog 1 channel selection - AWD1CH: u5, - /// injected queue disable - JQDIS: u1, - }), - /// configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// Regular Oversampling Enable - ROVSE: u1, - /// Injected Oversampling Enable - JOVSE: u1, - /// Oversampling ratio - OVSR: u3, - /// Oversampling shift - OVSS: u4, - /// Triggered Regular Oversampling - TROVS: packed union { + /// HSE divider for PLL entry. Same bit as PREDIV[0] from CFGR2 register. Refer to it for its meaning + PLLXTPRE: packed union { raw: u1, - value: TROVS, + value: PLLXTPRE, }, - /// Regular Oversampling mode - ROVSM: packed union { - raw: u1, - value: ROVSM, + /// PLL Multiplication Factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, }, - reserved16: u5, - /// Gain compensation mode - GCOMP: u1, - reserved25: u8, - /// Software trigger bit for sampling time control trigger mode - SWTRIG: u1, - /// Bulb sampling mode - BULB: u1, - /// Sampling time control trigger mode - SMPTRIG: u1, - padding: u4, - }), - /// sampling time register 1 - SMPR: mmio.Mmio(packed struct(u32) { - /// channel n * 10 + x sampling time - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, + reserved24: u2, + /// Microcontroller clock output + MCOSEL: packed union { + raw: u4, + value: MCOSEL, }, - reserved31: u28, - /// Addition of one clock cycle to the sampling time - SMPPLUS: u1, - }), - /// sampling time register 2 - SMPR2: mmio.Mmio(packed struct(u32) { - /// channel n * 10 + x sampling time - SMP: packed union { + /// Microcontroller Clock Output Prescaler + MCOPRE: packed union { raw: u3, - value: SAMPLE_TIME, + value: MCOPRE, + }, + /// PLL clock not divided for MCO + PLLMCODIV: packed union { + raw: u1, + value: PLLMCODIV, }, - padding: u29, - }), - reserved32: [4]u8, - /// analog watchdog threshold register 1 - TR1: mmio.Mmio(packed struct(u32) { - /// analog watchdog 1 lower threshold - LT1: u12, - /// analog watchdog filtering parameter - AWDFILT: u3, - reserved16: u1, - /// analog watchdog 1 higher threshold - HT1: u12, - padding: u4, - }), - /// analog watchdog threshold register 2 - TR2: mmio.Mmio(packed struct(u32) { - /// analog watchdog 2 lower threshold - LT2: u8, - reserved16: u8, - /// analog watchdog 2 higher threshold - HT2: u8, - padding: u8, }), - /// analog watchdog threshold register 3 - TR3: mmio.Mmio(packed struct(u32) { - /// analog watchdog 3 lower threshold - LT3: u8, - reserved16: u8, - /// analog watchdog 3 higher threshold - HT3: u8, + /// Clock interrupt register (RCC_CIR) + CIR: mmio.Mmio(packed struct(u32) { + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + /// HSI14 ready interrupt flag + HSI14RDYF: u1, + reserved7: u1, + /// Clock Security System Interrupt flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + /// HSI14 ready interrupt enable + HSI14RDYIE: u1, + reserved16: u2, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + /// HSI 14 MHz Ready Interrupt Clear + HSI14RDYC: u1, + reserved23: u1, + /// Clock security system interrupt clear + CSSC: u1, padding: u8, }), - reserved48: [4]u8, - /// group regular sequencer ranks register 1 - SQR1: mmio.Mmio(packed struct(u32) { - /// L - L: u4, - reserved6: u2, - /// group regular sequencer rank 1-4 - SQ: u5, - padding: u21, + /// APB2 peripheral reset register (RCC_APB2RSTR) + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// SYSCFG and COMP reset + SYSCFGRST: u1, + reserved5: u4, + /// USART6 reset + USART6RST: u1, + /// USART7 reset + USART7RST: u1, + /// USART8 reset + USART8RST: u1, + reserved9: u1, + /// ADC interface reset + ADCRST: u1, + reserved11: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// USART1 reset + USART1RST: u1, + reserved16: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + reserved22: u3, + /// Debug MCU reset + DBGMCURST: u1, + padding: u9, }), - /// group regular sequencer ranks register 2 - SQR2: mmio.Mmio(packed struct(u32) { - /// group regular sequencer rank 5-9 - SQ: u5, - padding: u27, + /// APB1 peripheral reset register (RCC_APB1RSTR) + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + reserved4: u2, + /// Timer 6 reset + TIM6RST: u1, + /// TIM7 timer reset + TIM7RST: u1, + reserved8: u2, + /// Timer 14 reset + TIM14RST: u1, + reserved11: u2, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + reserved17: u2, + /// USART 2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// USART4 reset + USART4RST: u1, + /// USART5 reset + USART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB interface reset + USBRST: u1, + reserved25: u1, + /// CAN interface reset + CANRST: u1, + reserved27: u1, + /// Clock Recovery System interface reset + CRSRST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// HDMI CEC reset + CECRST: u1, + padding: u1, }), - /// group regular sequencer ranks register 3 - SQR3: mmio.Mmio(packed struct(u32) { - /// group regular sequencer rank 10-14 - SQ: u5, - padding: u27, + /// AHB Peripheral Clock enable register (RCC_AHBENR) + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA clock enable + DMAEN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock enable + SRAMEN: u1, + reserved4: u1, + /// FLASH clock enable + FLASHEN: u1, + reserved6: u1, + /// CRC clock enable + CRCEN: u1, + reserved17: u10, + /// I/O port A clock enable + GPIOAEN: u1, + /// I/O port B clock enable + GPIOBEN: u1, + /// I/O port C clock enable + GPIOCEN: u1, + /// I/O port D clock enable + GPIODEN: u1, + /// I/O port E clock enable + GPIOEEN: u1, + /// I/O port F clock enable + GPIOFEN: u1, + reserved24: u1, + /// Touch sensing controller clock enable + TSCEN: u1, + padding: u7, }), - /// group regular sequencer ranks register 4 - SQR4: mmio.Mmio(packed struct(u32) { - /// group regular sequencer rank 15-16 - SQ: u5, - padding: u27, + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved5: u4, + /// USART6 clock enable + USART6EN: u1, + /// USART7 clock enable + USART7EN: u1, + /// USART8 clock enable + USART8EN: u1, + reserved9: u1, + /// ADC 1 interface clock enable + ADCEN: u1, + reserved11: u1, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + reserved14: u1, + /// USART1 clock enable + USART1EN: u1, + reserved16: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + reserved22: u3, + /// MCU debug module clock enable + DBGMCUEN: u1, + padding: u9, }), - /// group regular conversion data register - DR: mmio.Mmio(packed struct(u32) { - /// group regular conversion data - RDATA: u16, - padding: u16, + /// APB1 peripheral clock enable register (RCC_APB1ENR) + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + reserved4: u2, + /// Timer 6 clock enable + TIM6EN: u1, + /// TIM7 timer clock enable + TIM7EN: u1, + reserved8: u2, + /// Timer 14 clock enable + TIM14EN: u1, + reserved11: u2, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI 2 clock enable + SPI2EN: u1, + reserved17: u2, + /// USART 2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// USART4 clock enable + USART4EN: u1, + /// USART5 clock enable + USART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB interface clock enable + USBEN: u1, + reserved25: u1, + /// CAN interface clock enable + CANEN: u1, + reserved27: u1, + /// Clock Recovery System interface clock enable + CRSEN: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// HDMI CEC interface clock enable + CECEN: u1, + padding: u1, }), - reserved76: [8]u8, - /// group injected sequencer register - JSQR: mmio.Mmio(packed struct(u32) { - /// group injected sequencer scan length - JL: u2, - /// group injected external trigger source - JEXTSEL: u5, - /// group injected external trigger polarity - JEXTEN: packed union { + /// Backup domain control register (RCC_BDCR) + BDCR: mmio.Mmio(packed struct(u32) { + /// External Low Speed oscillator enable + LSEON: u1, + /// External Low Speed oscillator ready + LSERDY: u1, + /// External Low Speed oscillator bypass + LSEBYP: u1, + /// LSE oscillator drive capability + LSEDRV: packed union { raw: u2, - value: JEXTEN, + value: LSEDRV, }, - /// group injected sequencer rank 1-4 - JSQ: u5, - padding: u18, - }), - reserved96: [16]u8, - /// offset number 1-4 register - OFR: [4]mmio.Mmio(packed struct(u32) { - /// data offset - OFFSET: u12, - reserved24: u12, - /// Positive offset - OFFSETPOS: u1, - /// Saturation enable - SATEN: u1, - /// Channel selection for the data offset - OFFSET1_CH: u5, - /// Offset enable - OFFSET_EN: u1, + reserved8: u3, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, }), - reserved128: [16]u8, - /// group injected sequencer rank 1-4 register - JDR: [4]mmio.Mmio(packed struct(u32) { - /// group injected sequencer rank conversion data - JDATA: u16, - padding: u16, + /// Control/status register (RCC_CSR) + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low speed oscillator enable + LSION: u1, + /// Internal low speed oscillator ready + LSIRDY: u1, + reserved23: u21, + /// 1.8 V domain reset flag + V18PWRRSTF: u1, + /// Remove reset flag + RMVF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, }), - reserved160: [16]u8, - /// analog watchdog 2 configuration register - AWD2CR: mmio.Mmio(packed struct(u32) { - /// analog watchdog 2 channel selection - AWD2CH: u19, - padding: u13, + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + reserved17: u17, + /// I/O port A reset + GPIOARST: u1, + /// I/O port B reset + GPIOBRST: u1, + /// I/O port C reset + GPIOCRST: u1, + /// I/O port D reset + GPIODRST: u1, + /// I/O port E reset + GPIOERST: u1, + /// I/O port F reset + GPIOFRST: u1, + reserved24: u1, + /// Touch sensing controller reset + TSCRST: u1, + padding: u7, }), - /// analog watchdog 3 configuration register - AWD3CR: mmio.Mmio(packed struct(u32) { - /// analog watchdog 3 channel selection - AWD3CH: u19, - padding: u13, + /// Clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// PREDIV division factor + PREDIV: packed union { + raw: u4, + value: PREDIV, + }, + padding: u28, }), - reserved176: [8]u8, - /// channel differential or single-ended mode selection register - DIFSEL: mmio.Mmio(packed struct(u32) { - /// channel differential or single-ended mode for channel - DIFSEL: packed union { + /// Clock configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SW: packed union { + raw: u2, + value: USART1SW, + }, + reserved4: u2, + /// I2C1 clock source selection + I2C1SW: packed union { raw: u1, - value: DIFSEL, + value: ICSW, }, - padding: u31, - }), - /// calibration factors register - CALFACT: mmio.Mmio(packed struct(u32) { - /// calibration factor in single-ended mode - CALFACT_S: u7, - reserved16: u9, - /// calibration factor in differential mode - CALFACT_D: u7, - padding: u9, - }), - reserved192: [8]u8, - /// Gain compensation register - GCOMP: mmio.Mmio(packed struct(u32) { - /// Gain compensation coefficient - GCOMPCOEFF: u14, - padding: u18, - }), - }; - }; - - pub const dbgmcu_f1 = struct { - /// Debug support - pub const DBGMCU = extern struct { - /// DBGMCU_IDCODE - IDCODE: mmio.Mmio(packed struct(u32) { - /// DEV_ID - DEV_ID: u12, - reserved16: u4, - /// REV_ID - REV_ID: u16, + reserved6: u1, + /// HDMI CEC clock source selection + CECSW: packed union { + raw: u1, + value: CECSW, + }, + /// USB clock source selection + USBSW: packed union { + raw: u1, + value: USBSW, + }, + /// ADCSW is deprecated. See ADC field in CFGR2 register. + ADCSW: u1, + reserved16: u7, + /// USART2 clock source selection + USART2SW: packed union { + raw: u2, + value: USARTSW, + }, + /// USART3 clock source + USART3SW: packed union { + raw: u2, + value: USARTSW, + }, + padding: u12, }), - /// DBGMCU_CR - CR: mmio.Mmio(packed struct(u32) { - /// DBG_SLEEP - DBG_SLEEP: u1, - /// DBG_STOP - DBG_STOP: u1, - /// DBG_STANDBY - DBG_STANDBY: u1, - reserved5: u2, - /// TRACE_IOEN - TRACE_IOEN: u1, - /// TRACE_MODE - TRACE_MODE: u2, - /// IWDG - IWDG: u1, - /// WWDG - WWDG: u1, - /// TIM1 - TIM1: u1, - /// TIM2 - TIM2: u1, - /// TIM3 - TIM3: u1, - /// TIM4 - TIM4: u1, - /// CAN1 - CAN1: u1, - /// DBG_I2C1_SMBUS_TIMEOUT - DBG_I2C1_SMBUS_TIMEOUT: u1, - /// DBG_I2C2_SMBUS_TIMEOUT - DBG_I2C2_SMBUS_TIMEOUT: u1, - /// TIM8 - TIM8: u1, - /// TIM5 - TIM5: u1, - /// TIM6 - TIM6: u1, - /// TIM7 - TIM7: u1, - /// CAN2 - CAN2: u1, - /// TIM15 - TIM15: u1, - /// TIM16 - TIM16: u1, - /// TIM17 - TIM17: u1, - /// TIM12 - TIM12: u1, - /// TIM13 - TIM13: u1, - /// TIM14 - TIM14: u1, - padding: u4, + /// Clock control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// HSI14 clock enable + HSI14ON: u1, + /// HR14 clock ready flag + HSI14RDY: u1, + /// HSI14 clock request from ADC disable + HSI14DIS: u1, + /// HSI14 clock trimming + HSI14TRIM: u5, + /// HSI14 clock calibration + HSI14CAL: u8, + padding: u16, }), }; }; - pub const rtc_v2h7 = struct { - pub const ALRMR_MSK = enum(u1) { - /// Alarm set if the date/day match - ToMatch = 0x0, - /// Date/day don’t care in Alarm comparison - NotMatch = 0x1, + pub const rcc_f0v4 = struct { + pub const CECSW = enum(u1) { + /// HSI clock divided by 244 selected as CEC clock source + HSI_DIV_244 = 0x0, + /// LSE clock selected as CEC clock source + LSE = 0x1, }; - pub const ALRMR_PM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, + _, }; - pub const ALRMR_WDSEL = enum(u1) { - /// DU[3:0] represents the date units - DateUnits = 0x0, - /// DU[3:0] represents the week day. DT[1:0] is don’t care - WeekDay = 0x1, + pub const ICSW = enum(u1) { + /// HSI clock selected as I2C clock source + HSI = 0x0, + /// SYSCLK clock selected as I2C clock source + SYS = 0x1, }; - pub const AMPM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium high driving capability + MediumHigh = 0x1, + /// Medium low driving capability + MediumLow = 0x2, + /// High driving capability + High = 0x3, }; - pub const CALP = enum(u1) { - /// No RTCCLK pulses are added - NoChange = 0x0, - /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - IncreaseFreq = 0x1, + pub const MCOPRE = enum(u3) { + /// MCO is divided by 1 + Div1 = 0x0, + /// MCO is divided by 2 + Div2 = 0x1, + /// MCO is divided by 4 + Div4 = 0x2, + /// MCO is divided by 8 + Div8 = 0x3, + /// MCO is divided by 16 + Div16 = 0x4, + /// MCO is divided by 32 + Div32 = 0x5, + /// MCO is divided by 64 + Div64 = 0x6, + /// MCO is divided by 128 + Div128 = 0x7, }; - pub const CALW16 = enum(u1) { - /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 - Sixteen_Second = 0x1, + pub const MCOSEL = enum(u4) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// Internal RC 14 MHz (HSI14) oscillator clock selected + HSI14 = 0x1, + /// Internal low speed (LSI) oscillator clock selected + LSI = 0x2, + /// External low speed (LSE) oscillator clock selected + LSE = 0x3, + /// System clock selected + SYS = 0x4, + /// Internal RC 8 MHz (HSI) oscillator clock selected + HSI = 0x5, + /// External 4-32 MHz (HSE) oscillator clock selected + HSE = 0x6, + /// PLL clock selected (divided by 1 or 2, depending en PLLMCODIV) + PLL = 0x7, + /// Internal RC 48 MHz (HSI48) oscillator clock selected + HSI48 = 0x8, _, }; - pub const CALW8 = enum(u1) { - /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected - Eight_Second = 0x1, - _, + pub const PLLMCODIV = enum(u1) { + /// PLL is divided by 2 for MCO + Div2 = 0x0, + /// PLL is not divided for MCO + Div1 = 0x1, }; - pub const COSEL = enum(u1) { - /// Calibration output is 512 Hz (with default prescaler setting) - CalFreq_512Hz = 0x0, - /// Calibration output is 1 Hz (with default prescaler setting) - CalFreq_1Hz = 0x1, + pub const PLLMUL = enum(u4) { + /// PLL input clock x2 + Mul2 = 0x0, + /// PLL input clock x3 + Mul3 = 0x1, + /// PLL input clock x4 + Mul4 = 0x2, + /// PLL input clock x5 + Mul5 = 0x3, + /// PLL input clock x6 + Mul6 = 0x4, + /// PLL input clock x7 + Mul7 = 0x5, + /// PLL input clock x8 + Mul8 = 0x6, + /// PLL input clock x9 + Mul9 = 0x7, + /// PLL input clock x10 + Mul10 = 0x8, + /// PLL input clock x11 + Mul11 = 0x9, + /// PLL input clock x12 + Mul12 = 0xa, + /// PLL input clock x13 + Mul13 = 0xb, + /// PLL input clock x14 + Mul14 = 0xc, + /// PLL input clock x15 + Mul15 = 0xd, + /// PLL input clock x16 + Mul16 = 0xe, + _, }; - pub const FMT = enum(u1) { - /// 24 hour/day format - Twenty_Four_Hour = 0x0, - /// AM/PM hour format - AM_PM = 0x1, + pub const PLLSRC = enum(u2) { + /// HSI divided by 2 selected as PLL input clock + HSI_Div2 = 0x0, + /// HSI divided by PREDIV selected as PLL input clock + HSI_Div_PREDIV = 0x1, + /// HSE divided by PREDIV selected as PLL input clock + HSE_Div_PREDIV = 0x2, + /// HSI48 divided by PREDIV selected as PLL input clock + HSI48_Div_PREDIV = 0x3, }; - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Alarm B output enabled - AlarmB = 0x2, - /// Wakeup output enabled - Wakeup = 0x3, - }; - - pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - Low = 0x1, + pub const PLLXTPRE = enum(u1) { + /// HSE clock not divided + Div1 = 0x0, + /// HSE clock divided by 2 + Div2 = 0x1, }; - pub const RECALPF = enum(u1) { - /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 - Pending = 0x1, + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, _, }; - pub const TAMPFLT = enum(u2) { - /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - Immediate = 0x0, - /// Tamper event is activated after 2 consecutive samples at the active level - Samples2 = 0x1, - /// Tamper event is activated after 4 consecutive samples at the active level - Samples4 = 0x2, - /// Tamper event is activated after 8 consecutive samples at the active level - Samples8 = 0x3, - }; - - pub const TAMPFREQ = enum(u3) { - /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - Div32768 = 0x0, - /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - Div16384 = 0x1, - /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - Div8192 = 0x2, - /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - Div4096 = 0x3, - /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - Div2048 = 0x4, - /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - Div1024 = 0x5, - /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - Div512 = 0x6, - /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - Div256 = 0x7, + pub const PREDIV = enum(u4) { + /// PREDIV input clock not divided + Div1 = 0x0, + /// PREDIV input clock divided by 2 + Div2 = 0x1, + /// PREDIV input clock divided by 3 + Div3 = 0x2, + /// PREDIV input clock divided by 4 + Div4 = 0x3, + /// PREDIV input clock divided by 5 + Div5 = 0x4, + /// PREDIV input clock divided by 6 + Div6 = 0x5, + /// PREDIV input clock divided by 7 + Div7 = 0x6, + /// PREDIV input clock divided by 8 + Div8 = 0x7, + /// PREDIV input clock divided by 9 + Div9 = 0x8, + /// PREDIV input clock divided by 10 + Div10 = 0x9, + /// PREDIV input clock divided by 11 + Div11 = 0xa, + /// PREDIV input clock divided by 12 + Div12 = 0xb, + /// PREDIV input clock divided by 13 + Div13 = 0xc, + /// PREDIV input clock divided by 14 + Div14 = 0xd, + /// PREDIV input clock divided by 15 + Div15 = 0xe, + /// PREDIV input clock divided by 16 + Div16 = 0xf, }; - pub const TAMPPRCH = enum(u2) { - /// 1 RTCCLK cycle - Cycles1 = 0x0, - /// 2 RTCCLK cycles - Cycles2 = 0x1, - /// 4 RTCCLK cycles - Cycles4 = 0x2, - /// 8 RTCCLK cycles - Cycles8 = 0x3, + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, }; - pub const TAMPPUDIS = enum(u1) { - /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - Enabled = 0x0, - /// Disable precharge of RTC_TAMPx pins - Disabled = 0x1, + pub const SW = enum(u2) { + /// HSI oscillator used as system clock + HSI = 0x0, + /// HSE oscillator used as system clock + HSE = 0x1, + /// PLL used as system clock + PLL1_P = 0x2, + /// HSI48 used as system clock + HSI48 = 0x3, }; - pub const TAMPTRG = enum(u1) { - /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. - RisingEdge = 0x0, - /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event - FallingEdge = 0x1, + pub const USART1SW = enum(u2) { + /// PCLK selected as USART clock source + PCLK2 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const TSEDGE = enum(u1) { - /// RTC_TS input rising edge generates a time-stamp event - RisingEdge = 0x0, - /// RTC_TS input falling edge generates a time-stamp event - FallingEdge = 0x1, + pub const USARTSW = enum(u2) { + /// PCLK selected as USART clock source + PCLK1 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const WUCKSEL = enum(u3) { - /// RTC/16 clock is selected - Div16 = 0x0, - /// RTC/8 clock is selected - Div8 = 0x1, - /// RTC/4 clock is selected - Div4 = 0x2, - /// RTC/2 clock is selected - Div2 = 0x3, - /// ck_spre (usually 1 Hz) clock is selected - ClockSpare = 0x4, - /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - ClockSpareWithOffset = 0x6, - _, + pub const USBSW = enum(u1) { + /// HSI48 selected as USB clock source + HSI48 = 0x0, + /// PLL clock selected as USB clock source + PLL1_P = 0x1, }; - /// Real-time clock - pub const RTC = extern struct { - /// Time register - TR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, - }), - /// Date register - DR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding: u8, - }), - /// Control register + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register CR: mmio.Mmio(packed struct(u32) { - /// Wakeup clock selection - WUCKSEL: packed union { - raw: u3, - value: WUCKSEL, - }, - /// Timestamp event active edge - TSEDGE: packed union { - raw: u1, - value: TSEDGE, + /// Internal High Speed clock enable + HSION: u1, + /// Internal High Speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal High Speed clock trimming + HSITRIM: u5, + /// Internal High Speed clock Calibration + HSICAL: u8, + /// External High Speed clock enable + HSEON: u1, + /// External High Speed clock ready flag + HSERDY: u1, + /// External High Speed clock Bypass + HSEBYP: u1, + /// Clock Security System enable + CSSON: u1, + reserved24: u4, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding: u6, + }), + /// Clock configuration register (RCC_CFGR) + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock Switch + SW: packed union { + raw: u2, + value: SW, }, - /// Reference clock detection enable (50 or 60 Hz) - REFCKON: u1, - /// Bypass the shadow registers - BYPSHAD: u1, - /// Hour format - FMT: packed union { - raw: u1, - value: FMT, + /// System Clock Switch Status + SWS: packed union { + raw: u2, + value: SW, }, - reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, - /// Wakeup timer enable - WUTE: u1, - /// Timestamp enable - TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, - /// Wakeup timer interrupt enable - WUTIE: u1, - /// Timestamp interrupt enable - TSIE: u1, - /// Add 1 hour (summer time change) - ADD1H: u1, - /// Subtract 1 hour (winter time change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output selection - COSEL: packed union { - raw: u1, - value: COSEL, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, }, - /// Output polarity - POL: packed union { - raw: u1, - value: POL, + /// APB Low speed prescaler (APB1) + PPRE: packed union { + raw: u3, + value: PPRE, }, - /// Output selection - OSEL: packed union { + reserved14: u3, + /// APCPRE is deprecated. See ADC field in CFGR2 register. + ADCPRE: u1, + /// PLL input clock source + PLLSRC: packed union { raw: u2, - value: OSEL, - }, - /// Calibration output enable - COE: u1, - /// Timestamp on internal event enable - ITSE: u1, - padding: u7, - }), - /// Initialization and status register - ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, - /// Wakeup timer write enabled - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Enter Initialization mode - INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, - /// Wakeup timer flag - WUTF: u1, - /// Timestamp flag - TSF: u1, - /// Timestamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, - /// Recalibration pending flag - RECALPF: packed union { - raw: u1, - value: RECALPF, - }, - /// Internal time-stamp flag - ITSF: u1, - padding: u14, - }), - /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, - padding: u9, - }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, - padding: u16, - }), - reserved28: [4]u8, - /// Alarm register - ALRMR: [2]mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm seconds mask - MSK1: packed union { - raw: u1, - value: ALRMR_MSK, + value: PLLSRC, }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm minutes mask - MSK2: packed union { + /// HSE divider for PLL entry. Same bit as PREDIV[0] from CFGR2 register. Refer to it for its meaning + PLLXTPRE: packed union { raw: u1, - value: ALRMR_MSK, + value: PLLXTPRE, }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: ALRMR_PM, + /// PLL Multiplication Factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, }, - /// Alarm hours mask - MSK3: packed union { - raw: u1, - value: ALRMR_MSK, + reserved24: u2, + /// Microcontroller clock output + MCOSEL: packed union { + raw: u4, + value: MCOSEL, }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { - raw: u1, - value: ALRMR_WDSEL, + /// Microcontroller Clock Output Prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, }, - /// Alarm date mask - MSK4: packed union { + /// PLL clock not divided for MCO + PLLMCODIV: packed union { raw: u1, - value: ALRMR_MSK, + value: PLLMCODIV, }, }), - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: u8, - padding: u24, + /// Clock interrupt register (RCC_CIR) + CIR: mmio.Mmio(packed struct(u32) { + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + /// HSI14 ready interrupt flag + HSI14RDYF: u1, + /// HSI48 ready interrupt flag + HSI48RDYF: u1, + /// Clock Security System Interrupt flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + /// HSI14 ready interrupt enable + HSI14RDYIE: u1, + /// HSI48 ready interrupt enable + HSI48RDYIE: u1, + reserved16: u1, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + /// HSI 14 MHz Ready Interrupt Clear + HSI14RDYC: u1, + /// HSI48 Ready Interrupt Clear + HSI48RDYC: u1, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, }), - /// Sub second register - SSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, + /// APB2 peripheral reset register (RCC_APB2RSTR) + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// SYSCFG and COMP reset + SYSCFGRST: u1, + reserved5: u4, + /// USART6 reset + USART6RST: u1, + /// USART7 reset + USART7RST: u1, + /// USART8 reset + USART8RST: u1, + reserved9: u1, + /// ADC interface reset + ADCRST: u1, + reserved11: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// USART1 reset + USART1RST: u1, + reserved16: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + reserved22: u3, + /// Debug MCU reset + DBGMCURST: u1, + padding: u9, }), - /// Shift control register - SHIFTR: mmio.Mmio(packed struct(u32) { - /// Subtract a fraction of a second - SUBFS: u15, - reserved31: u16, - /// Add one second - ADD1S: u1, + /// APB1 peripheral reset register (RCC_APB1RSTR) + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + reserved4: u2, + /// Timer 6 reset + TIM6RST: u1, + /// TIM7 timer reset + TIM7RST: u1, + reserved8: u2, + /// Timer 14 reset + TIM14RST: u1, + reserved11: u2, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + reserved17: u2, + /// USART 2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// USART4 reset + USART4RST: u1, + /// USART5 reset + USART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB interface reset + USBRST: u1, + reserved25: u1, + /// CAN interface reset + CANRST: u1, + reserved27: u1, + /// Clock Recovery System interface reset + CRSRST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// HDMI CEC reset + CECRST: u1, + padding: u1, }), - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, + /// AHB Peripheral Clock enable register (RCC_AHBENR) + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA clock enable + DMAEN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock enable + SRAMEN: u1, + reserved4: u1, + /// FLASH clock enable + FLASHEN: u1, + reserved6: u1, + /// CRC clock enable + CRCEN: u1, + reserved17: u10, + /// I/O port A clock enable + GPIOAEN: u1, + /// I/O port B clock enable + GPIOBEN: u1, + /// I/O port C clock enable + GPIOCEN: u1, + /// I/O port D clock enable + GPIODEN: u1, + /// I/O port E clock enable + GPIOEEN: u1, + /// I/O port F clock enable + GPIOFEN: u1, + reserved24: u1, + /// Touch sensing controller clock enable + TSCEN: u1, + padding: u7, + }), + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved5: u4, + /// USART6 clock enable + USART6EN: u1, + /// USART7 clock enable + USART7EN: u1, + /// USART8 clock enable + USART8EN: u1, + reserved9: u1, + /// ADC 1 interface clock enable + ADCEN: u1, + reserved11: u1, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + reserved14: u1, + /// USART1 clock enable + USART1EN: u1, reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + reserved22: u3, + /// MCU debug module clock enable + DBGMCUEN: u1, padding: u9, }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, + /// APB1 peripheral clock enable register (RCC_APB1ENR) + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + reserved4: u2, + /// Timer 6 clock enable + TIM6EN: u1, + /// TIM7 timer clock enable + TIM7EN: u1, reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding: u16, + /// Timer 14 clock enable + TIM14EN: u1, + reserved11: u2, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI 2 clock enable + SPI2EN: u1, + reserved17: u2, + /// USART 2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// USART4 clock enable + USART4EN: u1, + /// USART5 clock enable + USART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB interface clock enable + USBEN: u1, + reserved25: u1, + /// CAN interface clock enable + CANEN: u1, + reserved27: u1, + /// Clock Recovery System interface clock enable + CRSEN: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// HDMI CEC interface clock enable + CECEN: u1, + padding: u1, }), - /// Timestamp sub second register - TSSSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, + /// Backup domain control register (RCC_BDCR) + BDCR: mmio.Mmio(packed struct(u32) { + /// External Low Speed oscillator enable + LSEON: u1, + /// External Low Speed oscillator ready + LSERDY: u1, + /// External Low Speed oscillator bypass + LSEBYP: u1, + /// LSE oscillator drive capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + reserved8: u3, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, }), - /// Calibration register - CALR: mmio.Mmio(packed struct(u32) { - /// Calibration minus - CALM: u9, - reserved13: u4, - /// Use a 16-second calibration cycle period - CALW16: packed union { - raw: u1, - value: CALW16, + /// Control/status register (RCC_CSR) + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low speed oscillator enable + LSION: u1, + /// Internal low speed oscillator ready + LSIRDY: u1, + reserved23: u21, + /// 1.8 V domain reset flag + V18PWRRSTF: u1, + /// Remove reset flag + RMVF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + reserved17: u17, + /// I/O port A reset + GPIOARST: u1, + /// I/O port B reset + GPIOBRST: u1, + /// I/O port C reset + GPIOCRST: u1, + /// I/O port D reset + GPIODRST: u1, + /// I/O port E reset + GPIOERST: u1, + /// I/O port F reset + GPIOFRST: u1, + reserved24: u1, + /// Touch sensing controller reset + TSCRST: u1, + padding: u7, + }), + /// Clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// PREDIV division factor + PREDIV: packed union { + raw: u4, + value: PREDIV, }, - /// Use an 8-second calibration cycle period - CALW8: packed union { - raw: u1, - value: CALW8, + padding: u28, + }), + /// Clock configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SW: packed union { + raw: u2, + value: USART1SW, }, - /// Increase frequency of RTC by 488.5 ppm - CALP: packed union { + reserved4: u2, + /// I2C1 clock source selection + I2C1SW: packed union { raw: u1, - value: CALP, + value: ICSW, }, - padding: u16, - }), - /// Tamper configuration register - TAMPCR: mmio.Mmio(packed struct(u32) { - /// Tamper detection enable - TAMPE: u1, - /// Active level for tamper - TAMPTRG: packed union { + reserved6: u1, + /// HDMI CEC clock source selection + CECSW: packed union { raw: u1, - value: TAMPTRG, + value: CECSW, }, - /// Tamper interrupt enable - TAMPIE: u1, - reserved7: u4, - /// Activate timestamp on tamper detection event - TAMPTS: u1, - /// Tamper sampling frequency - TAMPFREQ: packed union { - raw: u3, - value: TAMPFREQ, + /// USB clock source selection + USBSW: packed union { + raw: u1, + value: USBSW, }, - /// Tamper filter count - TAMPFLT: packed union { + /// ADCSW is deprecated. See ADC field in CFGR2 register. + ADCSW: u1, + reserved16: u7, + /// USART2 clock source selection + USART2SW: packed union { raw: u2, - value: TAMPFLT, + value: USARTSW, }, - /// Tamper precharge duration - TAMPPRCH: packed union { + /// USART3 clock source + USART3SW: packed union { raw: u2, - value: TAMPPRCH, - }, - /// Tamper pull-up disable - TAMPPUDIS: packed union { - raw: u1, - value: TAMPPUDIS, + value: USARTSW, }, - /// Tamper interrupt enable - TAMPXIE: u1, - /// Tamper no erase - TAMPXNOERASE: u1, - /// Tamper mask flag - TAMPXMF: u1, - padding: u13, - }), - /// Alarm sub second register - ALRMSSR: [2]mmio.Mmio(packed struct(u32) { - /// Sub seconds value - SS: u15, - reserved24: u9, - /// Mask the most-significant bits starting at this bit - MASKSS: u4, - padding: u4, - }), - /// Option register - OR: mmio.Mmio(packed struct(u32) { - /// RTC_ALARM output type on PC13 - RTC_ALARM_TYPE: u1, - /// RTC_OUT remap - RTC_OUT_RMP: u1, - padding: u30, + padding: u12, }), - /// Backup register - BKPR: [32]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, + /// Clock control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// HSI14 clock enable + HSI14ON: u1, + /// HR14 clock ready flag + HSI14RDY: u1, + /// HSI14 clock request from ADC disable + HSI14DIS: u1, + /// HSI14 clock trimming + HSI14TRIM: u5, + /// HSI14 clock calibration + HSI14CAL: u8, + /// HSI48 clock enable + HSI48ON: u1, + /// HSI48 clock ready flag + HSI48RDY: u1, + reserved24: u6, + /// HSI48 factory clock calibration + HSI48CAL: u8, }), }; }; - pub const flash_f3 = struct { - pub const LATENCY = enum(u3) { - /// 0 wait states, if 0 < HCLK <= 24 MHz - WS0 = 0x0, - /// 1 wait state, if 24 < HCLK <= 48 MHz - WS1 = 0x1, - /// 2 wait states, if 48 < HCLK <= 72 MHz - WS2 = 0x2, - _, + pub const rcc_f1 = struct { + pub const ADCPRE = enum(u2) { + /// PCLK2 divided by 2 + Div2 = 0x0, + /// PCLK2 divided by 4 + Div4 = 0x1, + /// PCLK2 divided by 6 + Div6 = 0x2, + /// PCLK2 divided by 8 + Div8 = 0x3, }; - pub const RDPRT = enum(u2) { - /// Level 0 - Level0 = 0x0, - /// Level 1 - Level1 = 0x1, - /// Level 2 - Level2 = 0x3, + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, _, }; - pub const WDG_SW = enum(u1) { - /// Hardware watchdog - Hardware = 0x0, - /// Software watchdog - Software = 0x1, - }; - - pub const nRST_STDBY = enum(u1) { - /// Reset generated when entering Standby mode - Reset = 0x0, - /// No reset generated - NoReset = 0x1, - }; - - pub const nRST_STOP = enum(u1) { - /// Reset generated when entering Stop mode - Reset = 0x0, - /// No reset generated - NoReset = 0x1, - }; - - /// Flash - pub const FLASH = extern struct { - /// Flash access control register - ACR: mmio.Mmio(packed struct(u32) { - /// LATENCY - LATENCY: packed union { - raw: u3, - value: LATENCY, - }, - /// Flash half cycle access enable - HLFCYA: u1, - /// PRFTBE - PRFTBE: u1, - /// PRFTBS - PRFTBS: u1, - padding: u26, - }), - /// Flash key register - KEYR: u32, - /// Flash option key register - OPTKEYR: u32, - /// Flash status register - SR: mmio.Mmio(packed struct(u32) { - /// Busy - BSY: u1, - reserved2: u1, - /// Programming error - PGERR: u1, - reserved4: u1, - /// Write protection error - WRPRTERR: u1, - /// End of operation - EOP: u1, - padding: u26, - }), - /// Flash control register - CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Page erase - PER: u1, - /// Mass erase - MER: u1, - reserved4: u1, - /// Option byte programming - OPTPG: u1, - /// Option byte erase - OPTER: u1, - /// Start - STRT: u1, - /// Lock - LOCK: u1, - reserved9: u1, - /// Option bytes write enable - OPTWRE: u1, - /// Error interrupt enable - ERRIE: u1, - reserved12: u1, - /// End of operation interrupt enable - EOPIE: u1, - /// Force option byte loading - OBL_LAUNCH: u1, - padding: u18, - }), - /// Flash address register - AR: mmio.Mmio(packed struct(u32) { - /// Flash address - FAR: u32, - }), - reserved28: [4]u8, - /// Option byte register - OBR: mmio.Mmio(packed struct(u32) { - /// Option byte error - OPTERR: u1, - /// Read protection Level status - RDPRT: packed union { - raw: u2, - value: RDPRT, - }, - reserved8: u5, - /// WDG_SW - WDG_SW: packed union { - raw: u1, - value: WDG_SW, - }, - /// nRST_STOP - nRST_STOP: packed union { - raw: u1, - value: nRST_STOP, - }, - /// nRST_STDBY - nRST_STDBY: packed union { - raw: u1, - value: nRST_STDBY, - }, - reserved12: u1, - /// BOOT1 - nBOOT1: u1, - /// VDDA_MONITOR - VDDA_MONITOR: u1, - /// SRAM_PARITY_CHECK - SRAM_PARITY_CHECK: u1, - /// SDADC12_VDD_MONITOR - SDADC12_VDD_MONITOR: u1, - /// Data0 - Data0: u8, - /// Data1 - Data1: u8, - }), - /// Write protection register - WRPR: mmio.Mmio(packed struct(u32) { - /// Write protect - WRP: u32, - }), - }; - }; - - pub const dac_v7 = struct { - pub const MODE = enum(u3) { - /// Normal mode, external pin only, buffer enabled - NORMAL_EXT_BUFEN = 0x0, - /// Normal mode, external pin and internal peripherals, buffer enabled - NORMAL_EXT_INT_BUFEN = 0x1, - /// Normal mode, external pin only, buffer disabled - NORMAL_EXT_BUFDIS = 0x2, - /// Normal mode, internal peripherals only, buffer disabled - NORMAL_INT_BUFDIS = 0x3, - /// Sample and hold mode, external pin only, buffer enabled - SAMPHOLD_EXT_BUFEN = 0x4, - /// Sample and hold mode, external pin and internal peripherals, buffer enabled - SAMPHOLD_EXT_INT_BUFEN = 0x5, - /// Sample and hold mode, external pin and internal peripherals, buffer disabled - SAMPHOLD_EXT_INT_BUFDIS = 0x6, - /// Sample and hold mode, internal peripherals only, buffer disabled - SAMPHOLD_INT_BUFDIS = 0x7, - }; - - pub const WAVE = enum(u2) { - /// Wave generation disabled - Disabled = 0x0, - /// Noise wave generation enabled - Noise = 0x1, - /// Triangle wave generation enabled - Triangle = 0x2, - /// Sawtooth wave generation enabled - Sawtooth = 0x3, - }; - - /// Digital-to-analog converter - pub const DAC = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u4, - /// channel noise/triangle wave generation enable - WAVE: packed union { - raw: u2, - value: WAVE, - }, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - /// channel DMA Underrun Interrupt enable - DMAUDRIE: u1, - /// DAC channel calibration enable - CEN: u1, - padding: u17, - }), - /// software trigger register - SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - reserved16: u15, - /// channel software trigger B - SWTRIGB: u1, - padding: u15, - }), - /// channel 12-bit right-aligned data holding register - DHR12R: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - reserved16: u4, - /// channel 12-bit right-aligned data B - DHRB: u12, - padding: u4, - }), - /// channel 12-bit left-aligned data holding register - DHR12L: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - reserved20: u4, - /// channel 12-bit left-aligned data B - DHRB: u12, - }), - /// channel 8-bit right-aligned data holding register - DHR8R: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - /// channel 8-bit right-aligned data B - DHRB: u8, - padding: u16, - }), - reserved32: [12]u8, - /// dual 12-bit right-aligned data holding register - DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, - }), - /// dual 12-bit left aligned data holding register - DHR12LD: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, - }), - /// dual 8-bit right aligned data holding register - DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, - }), - /// channel data output register - DOR: [2]mmio.Mmio(packed struct(u32) { - /// channel data output - DOR: u12, - reserved16: u4, - /// channel data output B - DORB: u12, - padding: u4, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// channel ready status bit - DACRDY: u1, - /// channel output register status bit - DORSTAT: u1, - /// channel DMA underrun flag - DMAUDR: u1, - /// channel calibration offset status - CAL_FLAG: u1, - /// channel busy writing sample time flag - BWST: u1, - padding: u16, - }), - /// calibration control register - CCR: mmio.Mmio(packed struct(u32) { - /// channel offset trimming value - OTRIM: u5, - padding: u27, - }), - /// mode control register - MCR: mmio.Mmio(packed struct(u32) { - /// DAC channel mode - MODE: packed union { - raw: u3, - value: MODE, - }, - reserved8: u5, - /// channel DMA double data mode. - DMADOUBLE: u1, - /// enable signed format for DAC channel - SINFORMAT: u1, - reserved14: u4, - /// high frequency interface mode selection - HFSEL: u2, - padding: u16, - }), - /// sample and hold sample time register - SHSR: [2]mmio.Mmio(packed struct(u32) { - /// channel sample time - TSAMPLE: u10, - padding: u22, - }), - /// sample and hold hold time register - SHHR: mmio.Mmio(packed struct(u32) { - /// channel hold time - THOLD: u10, - padding: u22, - }), - /// sample and hold refresh time register - SHRR: mmio.Mmio(packed struct(u32) { - /// channel refresh time - TREFRESH: u8, - padding: u24, - }), - reserved88: [8]u8, - /// Sawtooth register - STR: [2]mmio.Mmio(packed struct(u32) { - /// channel sawtooth reset value. - RSTDATA: u12, - /// channel sawtooth direction setting - DIR: u1, - reserved16: u3, - /// channel sawtooth increment value (12.4 bit format) - INCDATA: u16, - }), - /// Sawtooth Mode register - STMODR: mmio.Mmio(packed struct(u32) { - /// channel sawtooth reset trigger selection - STRSTTRIGSEL: u4, - reserved8: u4, - /// channel sawtooth increment trigger selection - STINCTRIGSEL: u4, - padding: u20, - }), - }; - }; - - pub const tsc_v2 = struct { - /// Touch sensing controller. - pub const TSC = extern struct { - /// control register. - CR: mmio.Mmio(packed struct(u32) { - /// Touch sensing controller enable. - TSCE: u1, - /// Start a new acquisition. - START: u1, - /// Acquisition mode. - AM: u1, - /// Synchronization pin polarity. - SYNCPOL: u1, - /// I/O Default mode. - IODEF: u1, - /// Max count value. - MCV: u3, - reserved12: u4, - /// pulse generator prescaler. - PGPSC: u3, - /// Spread spectrum prescaler. - SSPSC: u1, - /// Spread spectrum enable. - SSE: u1, - /// Spread spectrum deviation. - SSD: u7, - /// Charge transfer pulse low. - CTPL: u4, - /// Charge transfer pulse high. - CTPH: u4, - }), - /// interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// End of acquisition interrupt enable. - EOAIE: u1, - /// Max count error interrupt enable. - MCEIE: u1, - padding: u30, - }), - /// interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// End of acquisition interrupt clear. - EOAIC: u1, - /// Max count error interrupt clear. - MCEIC: u1, - padding: u30, - }), - /// interrupt status register. - ISR: mmio.Mmio(packed struct(u32) { - /// End of acquisition flag. - EOAF: u1, - /// Max count error flag. - MCEF: u1, - padding: u30, - }), - /// I/O hysteresis control register. - IOHCR: mmio.Mmio(packed struct(u32) { - /// G1_IO1 Schmitt trigger hysteresis mode. - G1_IO1: u1, - /// G1_IO2 Schmitt trigger hysteresis mode. - G1_IO2: u1, - /// G1_IO3 Schmitt trigger hysteresis mode. - G1_IO3: u1, - /// G1_IO4 Schmitt trigger hysteresis mode. - G1_IO4: u1, - /// G2_IO1 Schmitt trigger hysteresis mode. - G2_IO1: u1, - /// G2_IO2 Schmitt trigger hysteresis mode. - G2_IO2: u1, - /// G2_IO3 Schmitt trigger hysteresis mode. - G2_IO3: u1, - /// G2_IO4 Schmitt trigger hysteresis mode. - G2_IO4: u1, - /// G3_IO1 Schmitt trigger hysteresis mode. - G3_IO1: u1, - /// G3_IO2 Schmitt trigger hysteresis mode. - G3_IO2: u1, - /// G3_IO3 Schmitt trigger hysteresis mode. - G3_IO3: u1, - /// G3_IO4 Schmitt trigger hysteresis mode. - G3_IO4: u1, - /// G4_IO1 Schmitt trigger hysteresis mode. - G4_IO1: u1, - /// G4_IO2 Schmitt trigger hysteresis mode. - G4_IO2: u1, - /// G4_IO3 Schmitt trigger hysteresis mode. - G4_IO3: u1, - /// G4_IO4 Schmitt trigger hysteresis mode. - G4_IO4: u1, - /// G5_IO1 Schmitt trigger hysteresis mode. - G5_IO1: u1, - /// G5_IO2 Schmitt trigger hysteresis mode. - G5_IO2: u1, - /// G5_IO3 Schmitt trigger hysteresis mode. - G5_IO3: u1, - /// G5_IO4 Schmitt trigger hysteresis mode. - G5_IO4: u1, - /// G6_IO1 Schmitt trigger hysteresis mode. - G6_IO1: u1, - /// G6_IO2 Schmitt trigger hysteresis mode. - G6_IO2: u1, - /// G6_IO3 Schmitt trigger hysteresis mode. - G6_IO3: u1, - /// G6_IO4 Schmitt trigger hysteresis mode. - G6_IO4: u1, - /// G7_IO1 Schmitt trigger hysteresis mode. - G7_IO1: u1, - /// G7_IO2 Schmitt trigger hysteresis mode. - G7_IO2: u1, - /// G7_IO3 Schmitt trigger hysteresis mode. - G7_IO3: u1, - /// G7_IO4 Schmitt trigger hysteresis mode. - G7_IO4: u1, - padding: u4, - }), - reserved24: [4]u8, - /// I/O analog switch control register. - IOASCR: mmio.Mmio(packed struct(u32) { - /// G1_IO1 analog switch enable. - G1_IO1: u1, - /// G1_IO2 analog switch enable. - G1_IO2: u1, - /// G1_IO3 analog switch enable. - G1_IO3: u1, - /// G1_IO4 analog switch enable. - G1_IO4: u1, - /// G2_IO1 analog switch enable. - G2_IO1: u1, - /// G2_IO2 analog switch enable. - G2_IO2: u1, - /// G2_IO3 analog switch enable. - G2_IO3: u1, - /// G2_IO4 analog switch enable. - G2_IO4: u1, - /// G3_IO1 analog switch enable. - G3_IO1: u1, - /// G3_IO2 analog switch enable. - G3_IO2: u1, - /// G3_IO3 analog switch enable. - G3_IO3: u1, - /// G3_IO4 analog switch enable. - G3_IO4: u1, - /// G4_IO1 analog switch enable. - G4_IO1: u1, - /// G4_IO2 analog switch enable. - G4_IO2: u1, - /// G4_IO3 analog switch enable. - G4_IO3: u1, - /// G4_IO4 analog switch enable. - G4_IO4: u1, - /// G5_IO1 analog switch enable. - G5_IO1: u1, - /// G5_IO2 analog switch enable. - G5_IO2: u1, - /// G5_IO3 analog switch enable. - G5_IO3: u1, - /// G5_IO4 analog switch enable. - G5_IO4: u1, - /// G6_IO1 analog switch enable. - G6_IO1: u1, - /// G6_IO2 analog switch enable. - G6_IO2: u1, - /// G6_IO3 analog switch enable. - G6_IO3: u1, - /// G6_IO4 analog switch enable. - G6_IO4: u1, - /// G7_IO1 analog switch enable. - G7_IO1: u1, - /// G7_IO2 analog switch enable. - G7_IO2: u1, - /// G7_IO3 analog switch enable. - G7_IO3: u1, - /// G7_IO4 analog switch enable. - G7_IO4: u1, - padding: u4, - }), - reserved32: [4]u8, - /// I/O sampling control register. - IOSCR: mmio.Mmio(packed struct(u32) { - /// G1_IO1 sampling mode. - G1_IO1: u1, - /// G1_IO2 sampling mode. - G1_IO2: u1, - /// G1_IO3 sampling mode. - G1_IO3: u1, - /// G1_IO4 sampling mode. - G1_IO4: u1, - /// G2_IO1 sampling mode. - G2_IO1: u1, - /// G2_IO2 sampling mode. - G2_IO2: u1, - /// G2_IO3 sampling mode. - G2_IO3: u1, - /// G2_IO4 sampling mode. - G2_IO4: u1, - /// G3_IO1 sampling mode. - G3_IO1: u1, - /// G3_IO2 sampling mode. - G3_IO2: u1, - /// G3_IO3 sampling mode. - G3_IO3: u1, - /// G3_IO4 sampling mode. - G3_IO4: u1, - /// G4_IO1 sampling mode. - G4_IO1: u1, - /// G4_IO2 sampling mode. - G4_IO2: u1, - /// G4_IO3 sampling mode. - G4_IO3: u1, - /// G4_IO4 sampling mode. - G4_IO4: u1, - /// G5_IO1 sampling mode. - G5_IO1: u1, - /// G5_IO2 sampling mode. - G5_IO2: u1, - /// G5_IO3 sampling mode. - G5_IO3: u1, - /// G5_IO4 sampling mode. - G5_IO4: u1, - /// G6_IO1 sampling mode. - G6_IO1: u1, - /// G6_IO2 sampling mode. - G6_IO2: u1, - /// G6_IO3 sampling mode. - G6_IO3: u1, - /// G6_IO4 sampling mode. - G6_IO4: u1, - /// G7_IO1 sampling mode. - G7_IO1: u1, - /// G7_IO2 sampling mode. - G7_IO2: u1, - /// G7_IO3 sampling mode. - G7_IO3: u1, - /// G7_IO4 sampling mode. - G7_IO4: u1, - padding: u4, - }), - reserved40: [4]u8, - /// I/O channel control register. - IOCCR: mmio.Mmio(packed struct(u32) { - /// G1_IO1 channel mode. - G1_IO1: u1, - /// G1_IO2 channel mode. - G1_IO2: u1, - /// G1_IO3 channel mode. - G1_IO3: u1, - /// G1_IO4 channel mode. - G1_IO4: u1, - /// G2_IO1 channel mode. - G2_IO1: u1, - /// G2_IO2 channel mode. - G2_IO2: u1, - /// G2_IO3 channel mode. - G2_IO3: u1, - /// G2_IO4 channel mode. - G2_IO4: u1, - /// G3_IO1 channel mode. - G3_IO1: u1, - /// G3_IO2 channel mode. - G3_IO2: u1, - /// G3_IO3 channel mode. - G3_IO3: u1, - /// G3_IO4 channel mode. - G3_IO4: u1, - /// G4_IO1 channel mode. - G4_IO1: u1, - /// G4_IO2 channel mode. - G4_IO2: u1, - /// G4_IO3 channel mode. - G4_IO3: u1, - /// G4_IO4 channel mode. - G4_IO4: u1, - /// G5_IO1 channel mode. - G5_IO1: u1, - /// G5_IO2 channel mode. - G5_IO2: u1, - /// G5_IO3 channel mode. - G5_IO3: u1, - /// G5_IO4 channel mode. - G5_IO4: u1, - /// G6_IO1 channel mode. - G6_IO1: u1, - /// G6_IO2 channel mode. - G6_IO2: u1, - /// G6_IO3 channel mode. - G6_IO3: u1, - /// G6_IO4 channel mode. - G6_IO4: u1, - /// G7_IO1 channel mode. - G7_IO1: u1, - /// G7_IO2 channel mode. - G7_IO2: u1, - /// G7_IO3 channel mode. - G7_IO3: u1, - /// G7_IO4 channel mode. - G7_IO4: u1, - padding: u4, - }), - reserved48: [4]u8, - /// I/O group control status register. - IOGCSR: mmio.Mmio(packed struct(u32) { - /// Analog I/O group x enable. - G1E: u1, - /// Analog I/O group x enable. - G2E: u1, - /// Analog I/O group x enable. - G3E: u1, - /// Analog I/O group x enable. - G4E: u1, - /// Analog I/O group x enable. - G5E: u1, - /// Analog I/O group x enable. - G6E: u1, - /// Analog I/O group x enable. - G7E: u1, - reserved16: u9, - /// Analog I/O group x status. - G1S: u1, - /// Analog I/O group x status. - G2S: u1, - /// Analog I/O group x status. - G3S: u1, - /// Analog I/O group x status. - G4S: u1, - /// Analog I/O group x status. - G5S: u1, - /// Analog I/O group x status. - G6S: u1, - /// Analog I/O group x status. - G7S: u1, - padding: u9, - }), - /// I/O group x counter register. - IOGCR: [7]mmio.Mmio(packed struct(u32) { - /// Counter value. - CNT: u14, - padding: u18, - }), - }; - }; - - pub const rcc_f3v3 = struct { - pub const ADCPRE = enum(u2) { - /// PCLK divided by 2 - Div2 = 0x0, - /// PCLK divided by 4 - Div4 = 0x1, - /// PCLK divided by 6 - Div6 = 0x2, - /// PCLK divided by 8 - Div8 = 0x3, - }; - - pub const ADCPRES = enum(u5) { - /// PLL clock not divided - Div1 = 0x10, - /// PLL clock divided by 2 - Div2 = 0x11, - /// PLL clock divided by 4 - Div4 = 0x12, - /// PLL clock divided by 6 - Div6 = 0x13, - /// PLL clock divided by 8 - Div8 = 0x14, - /// PLL clock divided by 10 - Div10 = 0x15, - /// PLL clock divided by 12 - Div12 = 0x16, - /// PLL clock divided by 16 - Div16 = 0x17, - /// PLL clock divided by 32 - Div32 = 0x18, - /// PLL clock divided by 64 - Div64 = 0x19, - /// PLL clock divided by 128 - Div128 = 0x1a, - /// PLL clock divided by 256 - Div256 = 0x1b, - _, - }; - - pub const CECSW = enum(u1) { - /// HSI clock divided by 244 selected as CEC clock source - HSI_DIV_244 = 0x0, - /// LSE clock selected as CEC clock source - LSE = 0x1, - }; - - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, - _, - }; - - pub const ICSW = enum(u1) { - /// HSI clock selected as I2C clock source - HSI = 0x0, - /// SYSCLK clock selected as I2C clock source - SYS = 0x1, - }; - - pub const ISSRC = enum(u1) { - /// System clock used as I2S clock source - SYS = 0x0, - /// External clock mapped on the I2S_CKIN pin used as I2S clock source - CKIN = 0x1, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium high driving capability - MediumHigh = 0x1, - /// Medium low driving capability - MediumLow = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCOPRE = enum(u3) { - /// MCO is divided by 1 - Div1 = 0x0, - /// MCO is divided by 2 - Div2 = 0x1, - /// MCO is divided by 4 - Div4 = 0x2, - /// MCO is divided by 8 - Div8 = 0x3, - /// MCO is divided by 16 - Div16 = 0x4, - /// MCO is divided by 32 - Div32 = 0x5, - /// MCO is divided by 64 - Div64 = 0x6, - /// MCO is divided by 128 - Div128 = 0x7, - }; - - pub const MCOSEL = enum(u3) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// Internal low speed (LSI) oscillator clock selected - LSI = 0x2, - /// External low speed (LSE) oscillator clock selected - LSE = 0x3, - /// System clock selected - SYS = 0x4, - /// Internal RC 8 MHz (HSI) oscillator clock selected - HSI = 0x5, - /// External 4-32 MHz (HSE) oscillator clock selected - HSE = 0x6, - /// PLL clock selected (divided by 1 or 2, depending en PLLMCODIV) - PLL = 0x7, - _, - }; - - pub const PLLMCODIV = enum(u1) { - /// PLL is divided by 2 for MCO - Div2 = 0x0, - /// PLL is not divided for MCO - Div1 = 0x1, + pub const MCOSEL = enum(u3) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// System clock selected + SYS = 0x4, + /// HSI oscillator clock selected + HSI = 0x5, + /// HSE oscillator clock selected + HSE = 0x6, + /// PLL clock divided by 2 selected + PLL = 0x7, + _, }; pub const PLLMUL = enum(u4) { @@ -383445,14 +367735,11 @@ pub const types = struct { _, }; - pub const PLLSRC = enum(u2) { + pub const PLLSRC = enum(u1) { /// HSI divided by 2 selected as PLL input clock HSI_Div2 = 0x0, - /// HSI divided by PREDIV selected as PLL input clock - HSI_Div_PREDIV = 0x1, /// HSE divided by PREDIV selected as PLL input clock - HSE_Div_PREDIV = 0x2, - _, + HSE_Div_PREDIV = 0x1, }; pub const PLLXTPRE = enum(u1) { @@ -383476,41 +367763,6 @@ pub const types = struct { _, }; - pub const PREDIV = enum(u4) { - /// PREDIV input clock not divided - Div1 = 0x0, - /// PREDIV input clock divided by 2 - Div2 = 0x1, - /// PREDIV input clock divided by 3 - Div3 = 0x2, - /// PREDIV input clock divided by 4 - Div4 = 0x3, - /// PREDIV input clock divided by 5 - Div5 = 0x4, - /// PREDIV input clock divided by 6 - Div6 = 0x5, - /// PREDIV input clock divided by 7 - Div7 = 0x6, - /// PREDIV input clock divided by 8 - Div8 = 0x7, - /// PREDIV input clock divided by 9 - Div9 = 0x8, - /// PREDIV input clock divided by 10 - Div10 = 0x9, - /// PREDIV input clock divided by 11 - Div11 = 0xa, - /// PREDIV input clock divided by 12 - Div12 = 0xb, - /// PREDIV input clock divided by 13 - Div13 = 0xc, - /// PREDIV input clock divided by 14 - Div14 = 0xd, - /// PREDIV input clock divided by 15 - Div15 = 0xe, - /// PREDIV input clock divided by 16 - Div16 = 0xf, - }; - pub const RTCSEL = enum(u2) { /// No clock DISABLE = 0x0, @@ -383523,51 +367775,15 @@ pub const types = struct { }; pub const SW = enum(u2) { - /// HSI oscillator used as system clock + /// HSI selected as system clock HSI = 0x0, - /// HSE oscillator used as system clock + /// HSE selected as system clock HSE = 0x1, - /// PLL used as system clock + /// PLL selected as system clock PLL1_P = 0x2, _, }; - pub const TIM2SW = enum(u1) { - /// PCLK2 clock (doubled frequency when prescaled) - PCLK1_TIM = 0x0, - /// PLL vco output (running up to 144 MHz) - PLL1_P_MUL_2 = 0x1, - }; - - pub const TIMSW = enum(u1) { - /// PCLK2 clock (doubled frequency when prescaled) - PCLK2_TIM = 0x0, - /// PLL vco output (running up to 144 MHz) - PLL1_P_MUL_2 = 0x1, - }; - - pub const USART1SW = enum(u2) { - /// PCLK selected as USART clock source - PCLK2 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, - }; - - pub const USARTSW = enum(u2) { - /// PCLK selected as USART clock source - PCLK1 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, - }; - pub const USBPRE = enum(u1) { /// PLL clock is divided by 1.5 Div1_5 = 0x0, @@ -383625,7 +367841,7 @@ pub const types = struct { raw: u3, value: PPRE, }, - /// APB high speed prescaler (APB2) + /// APB High speed prescaler (APB2) PPRE2: packed union { raw: u3, value: PPRE, @@ -383635,8 +367851,12 @@ pub const types = struct { raw: u2, value: ADCPRE, }, - reserved17: u1, - /// HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products. + /// PLL entry clock source + PLLSRC: packed union { + raw: u1, + value: PLLSRC, + }, + /// HSE divider for PLL entry PLLXTPRE: packed union { raw: u1, value: PLLXTPRE, @@ -383651,27 +367871,13 @@ pub const types = struct { raw: u1, value: USBPRE, }, - /// I2S external clock source selection - I2SSRC: packed union { - raw: u1, - value: ISSRC, - }, + reserved24: u1, /// Microcontroller clock output MCOSEL: packed union { raw: u3, value: MCOSEL, }, - reserved28: u1, - /// Microcontroller Clock Output Prescaler - MCOPRE: packed union { - raw: u3, - value: MCOPRE, - }, - /// Do not divide PLL to MCO - PLLMCODIV: packed union { - raw: u1, - value: PLLMCODIV, - }, + padding: u5, }), /// Clock interrupt register (RCC_CIR) CIR: mmio.Mmio(packed struct(u32) { @@ -383716,9 +367922,27 @@ pub const types = struct { }), /// APB2 peripheral reset register (RCC_APB2RSTR) APB2RSTR: mmio.Mmio(packed struct(u32) { - /// SYSCFG and COMP reset - SYSCFGRST: u1, - reserved11: u10, + /// Alternate function I/O reset + AFIORST: u1, + reserved2: u1, + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// ADC 1 interface reset + ADC1RST: u1, + /// ADC 2 interface reset + ADC2RST: u1, /// TIM1 timer reset TIM1RST: u1, /// SPI 1 reset @@ -383727,25 +367951,16 @@ pub const types = struct { TIM8RST: u1, /// USART1 reset USART1RST: u1, - /// SPI4 reset - SPI4RST: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - /// TIM19 timer reset - TIM19RST: u1, - /// TIM20 timer reset - TIM20RST: u1, - reserved22: u1, - /// Debug MCU reset - DBGMCURST: u1, - reserved29: u6, - /// High Resolution Timer1 reset - HRTIM1RST: u1, - padding: u2, + /// ADC 3 interface reset + ADC3RST: u1, + reserved19: u3, + /// TIM9 timer reset + TIM9RST: u1, + /// TIM10 timer reset + TIM10RST: u1, + /// TIM11 timer reset + TIM11RST: u1, + padding: u10, }), /// APB1 peripheral reset register (RCC_APB1RSTR) APB1RSTR: mmio.Mmio(packed struct(u32) { @@ -383753,14 +367968,21 @@ pub const types = struct { TIM2RST: u1, /// Timer 3 reset TIM3RST: u1, - /// Timer 14 reset + /// Timer 4 reset TIM4RST: u1, - reserved4: u1, + /// Timer 5 reset + TIM5RST: u1, /// Timer 6 reset TIM6RST: u1, /// Timer 7 reset TIM7RST: u1, - reserved11: u5, + /// Timer 12 reset + TIM12RST: u1, + /// Timer 13 reset + TIM13RST: u1, + /// Timer 14 reset + TIM14RST: u1, + reserved11: u2, /// Window watchdog reset WWDGRST: u1, reserved14: u2, @@ -383771,11 +367993,11 @@ pub const types = struct { reserved17: u1, /// USART 2 reset USART2RST: u1, - /// USART3 reset + /// USART 3 reset USART3RST: u1, - /// UART 4 reset + /// USART 4 reset UART4RST: u1, - /// UART 5 reset + /// USART 5 reset UART5RST: u1, /// I2C1 reset I2C1RST: u1, @@ -383786,16 +368008,14 @@ pub const types = struct { reserved25: u1, /// CAN reset CANRST: u1, - /// DAC2 interface reset - DAC2RST: u1, - reserved28: u1, + reserved27: u1, + /// Backup interface reset + BKPRST: u1, /// Power interface reset PWRRST: u1, /// DAC interface reset DACRST: u1, - /// I2C3 reset - I2C3RST: u1, - padding: u1, + padding: u2, }), /// AHB Peripheral Clock enable register (RCC_AHBENR) AHBENR: mmio.Mmio(packed struct(u32) { @@ -383808,13 +368028,22 @@ pub const types = struct { reserved4: u1, /// FLASH clock enable FLASHEN: u1, - /// FMC clock enable - FMCEN: u1, + reserved6: u1, /// CRC clock enable CRCEN: u1, - reserved16: u9, - /// IO port H clock enable - GPIOHEN: u1, + reserved8: u1, + /// FSMC clock enable + FSMCEN: u1, + reserved10: u1, + /// SDIO clock enable + SDIOEN: u1, + padding: u21, + }), + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// Alternate function I/O clock enable + AFIOEN: u1, + reserved2: u1, /// I/O port A clock enable GPIOAEN: u1, /// I/O port B clock enable @@ -383827,22 +368056,12 @@ pub const types = struct { GPIOEEN: u1, /// I/O port F clock enable GPIOFEN: u1, - /// IO port G clock enable + /// I/O port G clock enable GPIOGEN: u1, - /// Touch sensing controller clock enable - TSCEN: u1, - reserved28: u3, - /// ADC1 and ADC2 clock enable - ADC12EN: u1, - /// ADC3 and ADC4 clock enable - ADC34EN: u1, - padding: u2, - }), - /// APB2 peripheral clock enable register (RCC_APB2ENR) - APB2ENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved11: u10, + /// ADC 1 interface clock enable + ADC1EN: u1, + /// ADC 2 interface clock enable + ADC2EN: u1, /// TIM1 Timer clock enable TIM1EN: u1, /// SPI 1 clock enable @@ -383851,25 +368070,16 @@ pub const types = struct { TIM8EN: u1, /// USART1 clock enable USART1EN: u1, - /// SPI4 clock enable - SPI4EN: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - /// TIM19 timer clock enable - TIM19EN: u1, - /// TIM20 timer clock enable - TIM20EN: u1, - reserved22: u1, - /// MCU debug module clock enable - DBGMCUEN: u1, - reserved29: u6, - /// High Resolution Timer 1 clock enable - HRTIM1EN: u1, - padding: u2, + /// ADC3 interface clock enable + ADC3EN: u1, + reserved19: u3, + /// TIM9 Timer clock enable + TIM9EN: u1, + /// TIM10 Timer clock enable + TIM10EN: u1, + /// TIM11 Timer clock enable + TIM11EN: u1, + padding: u10, }), /// APB1 peripheral clock enable register (RCC_APB1ENR) APB1ENR: mmio.Mmio(packed struct(u32) { @@ -383879,12 +368089,19 @@ pub const types = struct { TIM3EN: u1, /// Timer 4 clock enable TIM4EN: u1, - reserved4: u1, + /// Timer 5 clock enable + TIM5EN: u1, /// Timer 6 clock enable TIM6EN: u1, /// Timer 7 clock enable TIM7EN: u1, - reserved11: u5, + /// Timer 12 clock enable + TIM12EN: u1, + /// Timer 13 clock enable + TIM13EN: u1, + /// Timer 14 clock enable + TIM14EN: u1, + reserved11: u2, /// Window watchdog clock enable WWDGEN: u1, reserved14: u2, @@ -383897,9 +368114,9 @@ pub const types = struct { USART2EN: u1, /// USART 3 clock enable USART3EN: u1, - /// UART4 clock enable + /// UART 4 clock enable UART4EN: u1, - /// UART5 clock enable + /// UART 5 clock enable UART5EN: u1, /// I2C 1 clock enable I2C1EN: u1, @@ -383910,16 +368127,14 @@ pub const types = struct { reserved25: u1, /// CAN clock enable CANEN: u1, - /// DAC2 interface clock enable - DAC2EN: u1, - reserved28: u1, + reserved27: u1, + /// Backup interface clock enable + BKPEN: u1, /// Power interface clock enable PWREN: u1, /// DAC interface clock enable DACEN: u1, - /// I2C3 clock enable - I2C3EN: u1, - padding: u1, + padding: u2, }), /// Backup domain control register (RCC_BDCR) BDCR: mmio.Mmio(packed struct(u32) { @@ -383929,12 +368144,7 @@ pub const types = struct { LSERDY: u1, /// External Low Speed oscillator bypass LSEBYP: u1, - /// LSE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - reserved8: u3, + reserved8: u5, /// RTC clock source selection RTCSEL: packed union { raw: u2, @@ -383953,13 +368163,10 @@ pub const types = struct { LSION: u1, /// Internal low speed oscillator ready LSIRDY: u1, - reserved23: u21, - /// Reset flag of the 1.8 V domain - V18PWRRSTF: u1, + reserved24: u22, /// Remove reset flag RMVF: u1, - /// Option byte loader reset flag - OBLRSTF: u1, + reserved26: u1, /// PIN reset flag PINRSTF: u1, /// POR/PDR reset flag @@ -383973,1983 +368180,2403 @@ pub const types = struct { /// Low-power reset flag LPWRRSTF: u1, }), - /// AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// FMC reset - FMCRST: u1, - reserved16: u10, - /// IO port H reset - GPIOHRST: u1, - /// I/O port A reset - GPIOARST: u1, - /// I/O port B reset - GPIOBRST: u1, - /// I/O port C reset - GPIOCRST: u1, - /// I/O port D reset - GPIODRST: u1, - /// I/O port E reset - GPIOERST: u1, - /// I/O port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// Touch sensing controller reset - TSCRST: u1, - reserved28: u3, - /// ADC1 and ADC2 reset - ADC12RST: u1, - /// ADC3 and ADC4 reset - ADC34RST: u1, - padding: u2, - }), - /// Clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// PREDIV division factor - PREDIV: packed union { - raw: u4, - value: PREDIV, - }, - /// ADC1 and ADC2 prescaler - ADC12PRES: packed union { - raw: u5, - value: ADCPRES, - }, - /// ADC3 and ADC4 prescaler - ADC34PRES: packed union { - raw: u5, - value: ADCPRES, - }, - padding: u18, + }; + }; + + pub const rcc_f100 = struct { + pub const ADCPRE = enum(u2) { + /// PCLK2 divided by 2 + Div2 = 0x0, + /// PCLK2 divided by 4 + Div4 = 0x1, + /// PCLK2 divided by 6 + Div6 = 0x2, + /// PCLK2 divided by 8 + Div8 = 0x3, + }; + + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, + _, + }; + + pub const MCOSEL = enum(u3) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// System clock selected + SYS = 0x4, + /// HSI oscillator clock selected + HSI = 0x5, + /// HSE oscillator clock selected + HSE = 0x6, + /// PLL clock divided by 2 selected + PLL = 0x7, + _, + }; + + pub const PLLMUL = enum(u4) { + /// PLL input clock x2 + Mul2 = 0x0, + /// PLL input clock x3 + Mul3 = 0x1, + /// PLL input clock x4 + Mul4 = 0x2, + /// PLL input clock x5 + Mul5 = 0x3, + /// PLL input clock x6 + Mul6 = 0x4, + /// PLL input clock x7 + Mul7 = 0x5, + /// PLL input clock x8 + Mul8 = 0x6, + /// PLL input clock x9 + Mul9 = 0x7, + /// PLL input clock x10 + Mul10 = 0x8, + /// PLL input clock x11 + Mul11 = 0x9, + /// PLL input clock x12 + Mul12 = 0xa, + /// PLL input clock x13 + Mul13 = 0xb, + /// PLL input clock x14 + Mul14 = 0xc, + /// PLL input clock x15 + Mul15 = 0xd, + /// PLL input clock x16 + Mul16 = 0xe, + _, + }; + + pub const PLLSRC = enum(u1) { + /// HSI divided by 2 selected as PLL input clock + HSI_Div2 = 0x0, + /// HSE divided by PREDIV selected as PLL input clock + HSE_Div_PREDIV = 0x1, + }; + + pub const PLLXTPRE = enum(u1) { + /// HSE clock not divided + Div1 = 0x0, + /// HSE clock divided by 2 + Div2 = 0x1, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const PREDIV1 = enum(u4) { + /// PREDIV input clock not divided + Div1 = 0x0, + /// PREDIV input clock divided by 2 + Div2 = 0x1, + /// PREDIV input clock divided by 3 + Div3 = 0x2, + /// PREDIV input clock divided by 4 + Div4 = 0x3, + /// PREDIV input clock divided by 5 + Div5 = 0x4, + /// PREDIV input clock divided by 6 + Div6 = 0x5, + /// PREDIV input clock divided by 7 + Div7 = 0x6, + /// PREDIV input clock divided by 8 + Div8 = 0x7, + /// PREDIV input clock divided by 9 + Div9 = 0x8, + /// PREDIV input clock divided by 10 + Div10 = 0x9, + /// PREDIV input clock divided by 11 + Div11 = 0xa, + /// PREDIV input clock divided by 12 + Div12 = 0xb, + /// PREDIV input clock divided by 13 + Div13 = 0xc, + /// PREDIV input clock divided by 14 + Div14 = 0xd, + /// PREDIV input clock divided by 15 + Div15 = 0xe, + /// PREDIV input clock divided by 16 + Div16 = 0xf, + }; + + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, + }; + + pub const SW = enum(u2) { + /// HSI selected as system clock + HSI = 0x0, + /// HSE selected as system clock + HSE = 0x1, + /// PLL selected as system clock + PLL1_P = 0x2, + _, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal High Speed clock enable + HSION: u1, + /// Internal High Speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal High Speed clock trimming + HSITRIM: u5, + /// Internal High Speed clock Calibration + HSICAL: u8, + /// External High Speed clock enable + HSEON: u1, + /// External High Speed clock ready flag + HSERDY: u1, + /// External High Speed clock Bypass + HSEBYP: u1, + /// Clock Security System enable + CSSON: u1, + reserved24: u4, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding: u6, }), - /// Clock configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SW: packed union { + /// Clock configuration register (RCC_CFGR) + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock Switch + SW: packed union { raw: u2, - value: USART1SW, - }, - reserved4: u2, - /// I2C1 clock source selection - I2C1SW: packed union { - raw: u1, - value: ICSW, - }, - /// I2C2 clock source selection - I2C2SW: packed union { - raw: u1, - value: ICSW, - }, - /// HDMI CEC clock source selection - CECSW: packed union { - raw: u1, - value: CECSW, + value: SW, }, - reserved8: u1, - /// Timer1 clock source selection - TIM1SW: packed union { - raw: u1, - value: TIMSW, + /// System Clock Switch Status + SWS: packed union { + raw: u2, + value: SW, }, - /// Timer8 clock source selection - TIM8SW: packed union { - raw: u1, - value: TIMSW, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, }, - /// Timer15 clock source selection - TIM15SW: packed union { - raw: u1, - value: TIMSW, + /// APB Low speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, }, - /// Timer16 clock source selection - TIM16SW: packed union { - raw: u1, - value: TIMSW, + /// APB High speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, }, - /// Hrtim1 clock source selection - HRTIM1SW: packed union { - raw: u1, - value: TIMSW, + /// ADC prescaler + ADCPRE: packed union { + raw: u2, + value: ADCPRE, }, - /// Timer17 clock source selection - TIM17SW: packed union { + /// PLL entry clock source + PLLSRC: packed union { raw: u1, - value: TIMSW, + value: PLLSRC, }, - reserved15: u1, - /// Timer20 clock source selection - TIM20SW: packed union { + /// HSE divider for PLL entry + PLLXTPRE: packed union { raw: u1, - value: TIMSW, - }, - /// USART2 clock source selection - USART2SW: packed union { - raw: u2, - value: USARTSW, + value: PLLXTPRE, }, - /// USART3 clock source selection - USART3SW: packed union { - raw: u2, - value: USARTSW, + /// PLL Multiplication Factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, }, - /// UART4 clock source selection - UART4SW: packed union { - raw: u2, - value: USARTSW, + reserved24: u2, + /// Microcontroller clock output + MCOSEL: packed union { + raw: u3, + value: MCOSEL, }, - /// UART5 clock source selection - UART5SW: packed union { + padding: u5, + }), + /// Clock interrupt register (RCC_CIR) + CIR: mmio.Mmio(packed struct(u32) { + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + reserved7: u2, + /// Clock Security System Interrupt flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + reserved16: u3, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + reserved23: u2, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, + }), + /// APB2 peripheral reset register (RCC_APB2RSTR) + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// Alternate function I/O reset + AFIORST: u1, + reserved2: u1, + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// ADC 1 interface reset + ADC1RST: u1, + reserved11: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// USART1 reset + USART1RST: u1, + reserved16: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + padding: u13, + }), + /// APB1 peripheral reset register (RCC_APB1RSTR) + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + /// Timer 4 reset + TIM4RST: u1, + /// Timer 5 reset + TIM5RST: u1, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + /// Timer 12 reset + TIM12RST: u1, + /// Timer 13 reset + TIM13RST: u1, + /// Timer 14 reset + TIM14RST: u1, + reserved11: u2, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved17: u1, + /// USART 2 reset + USART2RST: u1, + /// USART 3 reset + USART3RST: u1, + /// USART 4 reset + UART4RST: u1, + /// USART 5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + reserved27: u4, + /// Backup interface reset + BKPRST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// CEC reset + CECRST: u1, + padding: u1, + }), + /// AHB Peripheral Clock enable register (RCC_AHBENR) + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock enable + SRAMEN: u1, + reserved4: u1, + /// FLASH clock enable + FLASHEN: u1, + reserved6: u1, + /// CRC clock enable + CRCEN: u1, + reserved8: u1, + /// FSMC clock enable + FSMCEN: u1, + padding: u23, + }), + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// Alternate function I/O clock enable + AFIOEN: u1, + reserved2: u1, + /// I/O port A clock enable + GPIOAEN: u1, + /// I/O port B clock enable + GPIOBEN: u1, + /// I/O port C clock enable + GPIOCEN: u1, + /// I/O port D clock enable + GPIODEN: u1, + /// I/O port E clock enable + GPIOEEN: u1, + /// I/O port F clock enable + GPIOFEN: u1, + /// I/O port G clock enable + GPIOGEN: u1, + /// ADC 1 interface clock enable + ADC1EN: u1, + reserved11: u1, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + reserved14: u1, + /// USART1 clock enable + USART1EN: u1, + reserved16: u1, + /// TIM15 Timer clock enable + TIM15EN: u1, + /// TIM16 Timer clock enable + TIM16EN: u1, + /// TIM17 Timer clock enable + TIM17EN: u1, + padding: u13, + }), + /// APB1 peripheral clock enable register (RCC_APB1ENR) + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + /// Timer 4 clock enable + TIM4EN: u1, + /// Timer 5 clock enable + TIM5EN: u1, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + /// Timer 12 clock enable + TIM12EN: u1, + /// Timer 13 clock enable + TIM13EN: u1, + /// Timer 14 clock enable + TIM14EN: u1, + reserved11: u2, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI 2 clock enable + SPI2EN: u1, + /// SPI 3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART 3 clock enable + USART3EN: u1, + /// UART 4 clock enable + UART4EN: u1, + /// UART 5 clock enable + UART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + reserved27: u4, + /// Backup interface clock enable + BKPEN: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// CEC clock enable + CECEN: u1, + padding: u1, + }), + /// Backup domain control register (RCC_BDCR) + BDCR: mmio.Mmio(packed struct(u32) { + /// External Low Speed oscillator enable + LSEON: u1, + /// External Low Speed oscillator ready + LSERDY: u1, + /// External Low Speed oscillator bypass + LSEBYP: u1, + reserved8: u5, + /// RTC clock source selection + RTCSEL: packed union { raw: u2, - value: USARTSW, - }, - /// Timer2 clock source selection - TIM2SW: packed union { - raw: u1, - value: TIM2SW, + value: RTCSEL, }, - /// Timer34 clock source selection - TIM34SW: packed union { - raw: u1, - value: TIMSW, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, + }), + /// Control/status register (RCC_CSR) + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low speed oscillator enable + LSION: u1, + /// Internal low speed oscillator ready + LSIRDY: u1, + reserved24: u22, + /// Remove reset flag + RMVF: u1, + reserved26: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + reserved44: [4]u8, + /// Clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// PREDIV1 division factor + PREDIV1: packed union { + raw: u4, + value: PREDIV1, }, - padding: u6, + padding: u28, }), }; }; - pub const vrefbuf_v2b = struct { - pub const HIZ = enum(u1) { - /// VREF+ pin is internally connected to the voltage reference buffer output. - Connected = 0x0, - /// VREF+ pin is high impedance. - HighZ = 0x1, + pub const rcc_f1cl = struct { + pub const ADCPRE = enum(u2) { + /// PCLK2 divided by 2 + Div2 = 0x0, + /// PCLK2 divided by 4 + Div4 = 0x1, + /// PCLK2 divided by 6 + Div6 = 0x2, + /// PCLK2 divided by 8 + Div8 = 0x3, }; - pub const VRS = enum(u2) { - /// Voltage reference set to VREF_OUT1 (around 2.048 V). - Vref0 = 0x0, - /// Voltage reference set to VREF_OUT2 (around 2.5 V). - Vref1 = 0x1, - /// Voltage reference set to VREF_OUT2 (around 2.5 V). - Vref2 = 0x2, + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, _, }; - /// Voltage reference buffer. - pub const VREFBUF = extern struct { - /// VREF_BUF Control and Status Register. - CSR: mmio.Mmio(packed struct(u32) { - /// Enable Voltage Reference. - ENVR: u1, - /// High impedence mode for the VREF_BUF. - HIZ: packed union { - raw: u1, - value: HIZ, - }, - reserved3: u1, - /// Voltage reference buffer ready. - VRR: u1, - /// Voltage reference scale. - VRS: packed union { - raw: u2, - value: VRS, - }, - padding: u26, - }), - /// VREF_BUF Calibration Control Register. - CCR: mmio.Mmio(packed struct(u32) { - /// Trimming code. - TRIM: u6, - padding: u26, - }), + pub const I2S2SRC = enum(u1) { + /// System clock (SYSCLK) selected as I2S clock entry + SYS = 0x0, + /// PLL3 VCO clock selected as I2S clock entry + PLL3 = 0x1, }; - }; - pub const can_fdcan_h7 = struct { - pub const TFQM = enum(u1) { - /// Tx FIFO operation - FIFO = 0x0, - /// Tx queue operation - QUEUE = 0x1, + pub const MCOSEL = enum(u4) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// System clock selected + SYS = 0x4, + /// HSI oscillator clock selected + HSI = 0x5, + /// HSE oscillator clock selected + HSE = 0x6, + /// PLL clock divided by 2 selected + PLL = 0x7, + /// PLL2 clock selected + PLL2 = 0x8, + /// PLL3 clock divided by 2 selected + PLL3DIV2 = 0x9, + /// XT1 external oscillator selected + XT1 = 0xa, + /// PLL3 clock selected + PLL3 = 0xb, + _, }; - /// Controller area network with flexible data rate (FD) - pub const FDCAN = extern struct { - /// FDCAN Core Release Register - CREL: mmio.Mmio(packed struct(u32) { - /// Timestamp Day - DAY: u8, - /// Timestamp Month - MON: u8, - /// Timestamp Year - YEAR: u4, - /// Sub-step of Core release - SUBSTEP: u4, - /// Step of Core release - STEP: u4, - /// Core release - REL: u4, - }), - /// FDCAN Core Release Register - ENDN: mmio.Mmio(packed struct(u32) { - /// Endiannes Test Value - ETV: u32, - }), - reserved12: [4]u8, - /// FDCAN Data Bit Timing and Prescaler Register - DBTP: mmio.Mmio(packed struct(u32) { - /// Synchronization Jump Width - DSJW: u4, - /// Data time segment after sample point - DTSEG2: u4, - /// Data time segment after sample point - DTSEG1: u5, - reserved16: u3, - /// Data BIt Rate Prescaler - DBRP: u5, - reserved23: u2, - /// Transceiver Delay Compensation - TDC: u1, - padding: u8, + pub const PLL2MUL = enum(u4) { + /// PLL clock entry x8 + Mul8 = 0x6, + /// PLL clock entry x9 + Mul9 = 0x7, + /// PLL clock entry x10 + Mul10 = 0x8, + /// PLL clock entry x11 + Mul11 = 0x9, + /// PLL clock entry x12 + Mul12 = 0xa, + /// PLL clock entry x13 + Mul13 = 0xb, + /// PLL clock entry x14 + Mul14 = 0xc, + /// PLL clock entry x16 + Mul16 = 0xe, + /// PLL clock entry x20 + Mul20 = 0xf, + _, + }; + + pub const PLLMUL = enum(u4) { + /// PLL input clock x4 + Mul4 = 0x2, + /// PLL input clock x5 + Mul5 = 0x3, + /// PLL input clock x6 + Mul6 = 0x4, + /// PLL input clock x7 + Mul7 = 0x5, + /// PLL input clock x8 + Mul8 = 0x6, + /// PLL input clock x9 + Mul9 = 0x7, + /// PLL input clock x6.5 + Mul6_5 = 0xd, + _, + }; + + pub const PLLSRC = enum(u1) { + /// HSI divided by 2 selected as PLL input clock + HSI_Div2 = 0x0, + /// HSE divided by PREDIV selected as PLL input clock + HSE_Div_PREDIV = 0x1, + }; + + pub const PLLXTPRE = enum(u1) { + /// HSE clock not divided + Div1 = 0x0, + /// HSE clock divided by 2 + Div2 = 0x1, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const PREDIV1 = enum(u4) { + /// PREDIV input clock not divided + Div1 = 0x0, + /// PREDIV input clock divided by 2 + Div2 = 0x1, + /// PREDIV input clock divided by 3 + Div3 = 0x2, + /// PREDIV input clock divided by 4 + Div4 = 0x3, + /// PREDIV input clock divided by 5 + Div5 = 0x4, + /// PREDIV input clock divided by 6 + Div6 = 0x5, + /// PREDIV input clock divided by 7 + Div7 = 0x6, + /// PREDIV input clock divided by 8 + Div8 = 0x7, + /// PREDIV input clock divided by 9 + Div9 = 0x8, + /// PREDIV input clock divided by 10 + Div10 = 0x9, + /// PREDIV input clock divided by 11 + Div11 = 0xa, + /// PREDIV input clock divided by 12 + Div12 = 0xb, + /// PREDIV input clock divided by 13 + Div13 = 0xc, + /// PREDIV input clock divided by 14 + Div14 = 0xd, + /// PREDIV input clock divided by 15 + Div15 = 0xe, + /// PREDIV input clock divided by 16 + Div16 = 0xf, + }; + + pub const PREDIV1SRC = enum(u1) { + /// HSE oscillator clock selected as PREDIV1 clock entry + HSE = 0x0, + /// PLL2 selected as PREDIV1 clock entry + PLL2 = 0x1, + }; + + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, + }; + + pub const SW = enum(u2) { + /// HSI oscillator used as system clock + HSI = 0x0, + /// HSE oscillator used as system clock + HSE = 0x1, + /// PLL used as system clock + PLL1_P = 0x2, + _, + }; + + pub const USBPRE = enum(u1) { + /// PLL clock is divided by 1.5 + Div1_5 = 0x0, + /// PLL clock is not divided + Div1 = 0x1, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal High Speed clock enable + HSION: u1, + /// Internal High Speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal High Speed clock trimming + HSITRIM: u5, + /// Internal High Speed clock Calibration + HSICAL: u8, + /// External High Speed clock enable + HSEON: u1, + /// External High Speed clock ready flag + HSERDY: u1, + /// External High Speed clock Bypass + HSEBYP: u1, + /// Clock Security System enable + CSSON: u1, + reserved24: u4, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + /// PLL2 enable + PLL2ON: u1, + /// PLL2 clock ready flag + PLL2RDY: u1, + /// PLL3 enable + PLL3ON: u1, + /// PLL3 clock ready flag + PLL3RDY: u1, + padding: u2, }), - /// FDCAN Test Register - TEST: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Loop Back mode - LBCK: u1, - /// Loop Back mode - TX: u2, - /// Control of Transmit Pin - RX: u1, - padding: u24, - }), - /// FDCAN RAM Watchdog Register - RWD: mmio.Mmio(packed struct(u32) { - /// Watchdog configuration - WDC: u8, - /// Watchdog value - WDV: u8, - padding: u16, - }), - /// FDCAN CC Control Register - CCCR: mmio.Mmio(packed struct(u32) { - /// Initialization - INIT: u1, - /// Configuration Change Enable - CCE: u1, - /// ASM Restricted Operation Mode - ASM: u1, - /// Clock Stop Acknowledge - CSA: u1, - /// Clock Stop Request - CSR: u1, - /// Bus Monitoring Mode - MON: u1, - /// Disable Automatic Retransmission - DAR: u1, - /// Test Mode Enable - TEST: u1, - /// FD Operation Enable - FDOE: u1, - /// FDCAN Bit Rate Switching - BSE: u1, - reserved12: u2, - /// Protocol Exception Handling Disable - PXHD: u1, - /// Edge Filtering during Bus Integration - EFBI: u1, - /// TXP - TXP: u1, - /// Non ISO Operation - NISO: u1, - padding: u16, - }), - /// FDCAN Nominal Bit Timing and Prescaler Register - NBTP: mmio.Mmio(packed struct(u32) { - /// Nominal Time segment after sample point - NTSEG2: u7, - reserved8: u1, - /// Nominal Time segment before sample point - NTSEG1: u8, - /// Bit Rate Prescaler - NBRP: u9, - /// NSJW: Nominal (Re)Synchronization Jump Width. - NSJW: u7, - }), - /// FDCAN Timestamp Counter Configuration Register - TSCC: mmio.Mmio(packed struct(u32) { - /// Timestamp Select - TSS: u2, - reserved16: u14, - /// Timestamp Counter Prescaler - TCP: u4, - padding: u12, - }), - /// FDCAN Timestamp Counter Value Register - TSCV: mmio.Mmio(packed struct(u32) { - /// Timestamp Counter - TSC: u16, - padding: u16, - }), - /// FDCAN Timeout Counter Configuration Register - TOCC: mmio.Mmio(packed struct(u32) { - /// Enable Timeout Counter - ETOC: u1, - /// Timeout Select - TOS: u2, - reserved16: u13, - /// Timeout Period - TOP: u16, - }), - /// FDCAN Timeout Counter Value Register - TOCV: mmio.Mmio(packed struct(u32) { - /// Timeout Counter - TOC: u16, - padding: u16, - }), - reserved64: [16]u8, - /// FDCAN Error Counter Register - ECR: mmio.Mmio(packed struct(u32) { - /// Transmit Error Counter - TEC: u8, - /// Receive Error Counter - REC: u7, - /// Receive Error Passive - RP: u1, - /// AN Error Logging - CEL: u8, - padding: u8, + /// Clock configuration register (RCC_CFGR) + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock Switch + SW: packed union { + raw: u2, + value: SW, + }, + /// System Clock Switch Status + SWS: packed union { + raw: u2, + value: SW, + }, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// APB Low speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + /// APB High speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + /// ADC prescaler + ADCPRE: packed union { + raw: u2, + value: ADCPRE, + }, + /// PLL entry clock source + PLLSRC: packed union { + raw: u1, + value: PLLSRC, + }, + /// HSE divider for PLL entry + PLLXTPRE: packed union { + raw: u1, + value: PLLXTPRE, + }, + /// PLL Multiplication Factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, + }, + /// USB prescaler + USBPRE: packed union { + raw: u1, + value: USBPRE, + }, + reserved24: u1, + /// Microcontroller clock output + MCOSEL: packed union { + raw: u4, + value: MCOSEL, + }, + padding: u4, }), - /// FDCAN Protocol Status Register - PSR: mmio.Mmio(packed struct(u32) { - /// Last Error Code - LEC: u3, - /// Activity - ACT: u2, - /// Error Passive - EP: u1, - /// Warning Status - EW: u1, - /// Bus_Off Status - BO: u1, - /// Data Last Error Code - DLEC: u3, - /// ESI flag of last received FDCAN Message - RESI: u1, - /// BRS flag of last received FDCAN Message - RBRS: u1, - /// Received FDCAN Message - REDL: u1, - /// Protocol Exception Event - PXE: u1, + /// Clock interrupt register (RCC_CIR) + CIR: mmio.Mmio(packed struct(u32) { + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + /// PLL2 Ready Interrupt flag + PLL2RDYF: u1, + /// PLL3 Ready Interrupt flag + PLL3RDYF: u1, + /// Clock Security System Interrupt flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + /// PLL2 Ready Interrupt Enable + PLL2RDYIE: u1, + /// PLL3 Ready Interrupt Enable + PLL3RDYIE: u1, reserved16: u1, - /// Transmitter Delay Compensation Value - TDCV: u7, - padding: u9, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + /// PLL2 Ready Interrupt Clear + PLL2RDYC: u1, + /// PLL3 Ready Interrupt Clear + PLL3RDYC: u1, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, }), - /// FDCAN Transmitter Delay Compensation Register - TDCR: mmio.Mmio(packed struct(u32) { - /// Transmitter Delay Compensation Filter Window Length - TDCF: u7, - reserved8: u1, - /// Transmitter Delay Compensation Offset - TDCO: u7, + /// APB2 peripheral reset register (RCC_APB2RSTR) + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// Alternate function I/O reset + AFIORST: u1, + reserved2: u1, + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + reserved9: u2, + /// ADC 1 interface reset + ADC1RST: u1, + /// ADC 2 interface reset + ADC2RST: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// USART1 reset + USART1RST: u1, padding: u17, }), - reserved80: [4]u8, - /// FDCAN Interrupt Register - IR: mmio.Mmio(packed struct(u32) { - /// Rx FIFO X New Message - RFN: u1, - /// Rx FIFO X Watermark Reached - RFW: u1, - /// Rx FIFO X Full - RFF: u1, - /// Rx FIFO X Message Lost - RFL: u1, - reserved8: u4, - /// High Priority Message - HPM: u1, - /// Transmission Completed - TC: u1, - /// Transmission Cancellation Finished - TCF: u1, - /// Tx FIFO Empty - TEF: u1, - /// Tx Event FIFO New Entry - TEFN: u1, - /// Tx Event FIFO Watermark Reached - TEFW: u1, - /// Tx Event FIFO Full - TEFF: u1, - /// Tx Event FIFO Element Lost - TEFL: u1, - /// Timestamp Wraparound - TSW: u1, - /// Message RAM Access Failure - MRAF: u1, - /// Timeout Occurred - TOO: u1, - /// Message stored to Dedicated Rx Buffer - DRX: u1, - reserved22: u2, - /// Error Logging Overflow - ELO: u1, - /// Error Passive - EP: u1, - /// Warning Status - EW: u1, - /// Bus_Off Status - BO: u1, - /// Watchdog Interrupt - WDI: u1, - /// Protocol Error in Arbitration Phase (Nominal Bit Time is used) - PEA: u1, - /// Protocol Error in Data Phase (Data Bit Time is used) - PED: u1, - /// Access to Reserved Address - ARA: u1, - padding: u2, - }), - /// FDCAN Interrupt Enable Register - IE: mmio.Mmio(packed struct(u32) { - /// Rx FIFO X New Message Enable - RFNE: u1, - /// Rx FIFO X Watermark Reached Enable - RFWE: u1, - /// Rx FIFO X Full Enable - RFFE: u1, - /// Rx FIFO X Message Lost Enable - RFLE: u1, - reserved8: u4, - /// High Priority Message Enable - HPME: u1, - /// Transmission Completed Enable - TCE: u1, - /// Transmission Cancellation Finished Enable - TCFE: u1, - /// Tx FIFO Empty Enable - TEFE: u1, - /// Tx Event FIFO New Entry Enable - TEFNE: u1, - /// Tx Event FIFO Watermark Reached Enable - TEFWE: u1, - /// Tx Event FIFO Full Enable - TEFFE: u1, - /// Tx Event FIFO Element Lost Enable - TEFLE: u1, - /// Timestamp Wraparound Enable - TSWE: u1, - /// Message RAM Access Failure Enable - MRAFE: u1, - /// Timeout Occurred Enable - TOOE: u1, - /// Message stored to Dedicated Rx Buffer Enable - DRXE: u1, - /// Bit Error Corrected Interrupt Enable - BECE: u1, - /// Bit Error Uncorrected Interrupt Enable - BEUE: u1, - /// Error Logging Overflow Enable - ELOE: u1, - /// Error Passive Enable - EPE: u1, - /// Warning Status Enable - EWE: u1, - /// Bus_Off Status Enable - BOE: u1, - /// Watchdog Interrupt Enable - WDIE: u1, - /// Protocol Error in Arbitration Phase Enable - PEAE: u1, - /// Protocol Error in Data Phase Enable - PEDE: u1, - /// Access to Reserved Address Enable - ARAE: u1, - padding: u2, - }), - /// FDCAN Interrupt Line Select Register - ILS: mmio.Mmio(packed struct(u32) { - /// Rx FIFO X New Message Interrupt Line - RFNL: u1, - /// Rx FIFO X Watermark Reached Interrupt Line - RFWL: u1, - /// Rx FIFO X Full Interrupt Line - RFFL: u1, - /// Rx FIFO X Message Lost Interrupt Line - RFLL: u1, - reserved8: u4, - /// High Priority Message Interrupt Line - HPML: u1, - /// Transmission Completed Interrupt Line - TCL: u1, - /// Transmission Cancellation Finished Interrupt Line - TCFL: u1, - /// Tx FIFO Empty Interrupt Line - TEFL: u1, - /// Tx Event FIFO New Entry Interrupt Line - TEFNL: u1, - /// Tx Event FIFO Watermark Reached Interrupt Line - TEFWL: u1, - /// Tx Event FIFO Full Interrupt Line - TEFFL: u1, - /// Tx Event FIFO Element Lost Interrupt Line - TEFLL: u1, - /// Timestamp Wraparound Interrupt Line - TSWL: u1, - /// Message RAM Access Failure Interrupt Line - MRAFL: u1, - /// Timeout Occurred Interrupt Line - TOOL: u1, - /// Message stored to Dedicated Rx Buffer Interrupt Line - DRXL: u1, - /// Bit Error Corrected Interrupt Line - BECL: u1, - /// Bit Error Uncorrected Interrupt Line - BEUL: u1, - /// Error Logging Overflow Interrupt Line - ELOL: u1, - /// Error Passive Interrupt Line - EPL: u1, - /// Warning Status Interrupt Line - EWL: u1, - /// Bus_Off Status - BOL: u1, - /// Watchdog Interrupt Line - WDIL: u1, - /// Protocol Error in Arbitration Phase Line - PEAL: u1, - /// Protocol Error in Data Phase Line - PEDL: u1, - /// Access to Reserved Address Line - ARAL: u1, + /// APB1 peripheral reset register (RCC_APB1RSTR) + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + /// Timer 4 reset + TIM4RST: u1, + /// Timer 5 reset + TIM5RST: u1, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + reserved11: u5, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved17: u1, + /// USART 2 reset + USART2RST: u1, + /// USART 3 reset + USART3RST: u1, + /// USART 4 reset + UART4RST: u1, + /// USART 5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + reserved25: u2, + /// CAN1 reset + CAN1RST: u1, + /// CAN2 reset + CAN2RST: u1, + /// Backup interface reset + BKPRST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, padding: u2, }), - /// FDCAN Interrupt Line Enable Register - ILE: mmio.Mmio(packed struct(u32) { - /// Enable Interrupt Line 0 - EINT0: u1, - /// Enable Interrupt Line 1 - EINT1: u1, - padding: u30, - }), - reserved128: [32]u8, - /// FDCAN Global Filter Configuration Register - GFC: mmio.Mmio(packed struct(u32) { - /// Reject Remote Frames Extended - RRFE: u1, - /// Reject Remote Frames Standard - RRFS: u1, - /// Accept Non-matching Frames Extended - ANFE: u2, - /// Accept Non-matching Frames Standard - ANFS: u2, - padding: u26, - }), - /// FDCAN Standard ID Filter Configuration Register - SIDFC: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Filter List Standard Start Address - FLSSA: u14, - /// List Size Standard - LSS: u8, - padding: u8, - }), - /// FDCAN Extended ID Filter Configuration Register - XIDFC: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Filter List Standard Start Address - FLESA: u14, - /// List Size Extended - LSE: u8, - padding: u8, - }), - reserved144: [4]u8, - /// FDCAN Extended ID and Mask Register - XIDAM: mmio.Mmio(packed struct(u32) { - /// Extended ID Mask - EIDM: u29, - padding: u3, - }), - /// FDCAN High Priority Message Status Register - HPMS: mmio.Mmio(packed struct(u32) { - /// Buffer Index - BIDX: u6, - /// Message Storage Indicator - MSI: u2, - /// Filter Index - FIDX: u7, - /// Filter List - FLST: u1, - padding: u16, - }), - /// FDCAN New Data 1 Register - NDAT1: mmio.Mmio(packed struct(u32) { - /// New data (buffers 0 - 31) - ND: u32, - }), - /// FDCAN New Data 2 Register - NDAT2: mmio.Mmio(packed struct(u32) { - /// New data (buffers 32 - 63) - ND: u32, - }), - /// FDCAN Rx FIFO X Configuration Register - RXFC: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Rx FIFO X Start Address - FSA: u14, - /// Rx FIFO X Size - FS: u7, - reserved24: u1, - /// FIFO X Watermark - FWM: u7, - /// FIFO X operation mode - FOM: u1, - }), - /// FDCAN Rx FIFO X Status Register - RXFS: mmio.Mmio(packed struct(u32) { - /// Rx FIFO X Fill Level - FFL: u7, - reserved8: u1, - /// Rx FIFO X Get Index - FGI: u6, - reserved16: u2, - /// Rx FIFO X Put Index - FPI: u6, - reserved24: u2, - /// Rx FIFO X Full - FF: u1, - /// Rx FIFO X Message Lost - RFL: u1, - padding: u6, + /// AHB Peripheral Clock enable register (RCC_AHBENR) + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock enable + SRAMEN: u1, + reserved4: u1, + /// FLASH clock enable + FLASHEN: u1, + reserved6: u1, + /// CRC clock enable + CRCEN: u1, + reserved12: u5, + /// USB OTG FS clock enable + USB_OTG_FSEN: u1, + reserved14: u1, + /// Ethernet MAC clock enable + ETHEN: u1, + /// Ethernet MAC TX clock enable + ETHTXEN: u1, + /// Ethernet MAC RX clock enable + ETHRXEN: u1, + padding: u15, }), - /// CAN Rx FIFO X Acknowledge Register - RXFA: mmio.Mmio(packed struct(u32) { - /// Rx FIFO X Acknowledge Index - FAI: u6, - padding: u26, + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// Alternate function I/O clock enable + AFIOEN: u1, + reserved2: u1, + /// I/O port A clock enable + GPIOAEN: u1, + /// I/O port B clock enable + GPIOBEN: u1, + /// I/O port C clock enable + GPIOCEN: u1, + /// I/O port D clock enable + GPIODEN: u1, + /// I/O port E clock enable + GPIOEEN: u1, + reserved9: u2, + /// ADC 1 interface clock enable + ADC1EN: u1, + /// ADC 2 interface clock enable + ADC2EN: u1, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + reserved14: u1, + /// USART1 clock enable + USART1EN: u1, + padding: u17, }), - /// FDCAN Rx Buffer Configuration Register - RXBC: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Rx Buffer Start Address - RBSA: u14, - padding: u16, + /// APB1 peripheral clock enable register (RCC_APB1ENR) + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + /// Timer 4 clock enable + TIM4EN: u1, + /// Timer 5 clock enable + TIM5EN: u1, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + reserved11: u5, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI 2 clock enable + SPI2EN: u1, + /// SPI 3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART 3 clock enable + USART3EN: u1, + /// UART 4 clock enable + UART4EN: u1, + /// UART 5 clock enable + UART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + reserved25: u2, + /// CAN1 clock enable + CAN1EN: u1, + /// CAN2 clock enable + CAN2EN: u1, + /// Backup interface clock enable + BKPEN: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + padding: u2, }), - reserved188: [12]u8, - /// FDCAN Rx Buffer Element Size Configuration Register - RXESC: mmio.Mmio(packed struct(u32) { - /// Rx FIFO X Data Field Size - FDS: u3, + /// Backup domain control register (RCC_BDCR) + BDCR: mmio.Mmio(packed struct(u32) { + /// External Low Speed oscillator enable + LSEON: u1, + /// External Low Speed oscillator ready + LSERDY: u1, + /// External Low Speed oscillator bypass + LSEBYP: u1, reserved8: u5, - /// Rx Buffer Data Field Size - RBDS: u3, - padding: u21, - }), - /// FDCAN Tx Buffer Configuration Register - TXBC: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Tx Buffers Start Address - TBSA: u14, - /// Number of Dedicated Transmit Buffers - NDTB: u6, - reserved24: u2, - /// Transmit FIFO/Queue Size - TFQS: u6, - /// Tx FIFO/Queue Mode - TFQM: packed union { - raw: u1, - value: TFQM, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, }, - padding: u1, - }), - /// FDCAN Tx FIFO/Queue Status Register - TXFQS: mmio.Mmio(packed struct(u32) { - /// Tx FIFO Free Level - TFFL: u6, - reserved8: u2, - /// TFGI - TFGI: u5, - reserved16: u3, - /// Tx FIFO/Queue Put Index - TFQPI: u5, - /// Tx FIFO/Queue Full - TFQF: u1, - padding: u10, - }), - /// FDCAN Tx Buffer Element Size Configuration Register - TXESC: mmio.Mmio(packed struct(u32) { - /// Tx Buffer Data Field Size - TBDS: u3, - padding: u29, - }), - /// FDCAN Tx Buffer Request Pending Register - TXBRP: mmio.Mmio(packed struct(u32) { - /// Transmission Request Pending - TRP: u1, - padding: u31, - }), - /// FDCAN Tx Buffer Add Request Register - TXBAR: mmio.Mmio(packed struct(u32) { - /// Add Request - AR: u1, - padding: u31, - }), - /// FDCAN Tx Buffer Cancellation Request Register - TXBCR: mmio.Mmio(packed struct(u32) { - /// Cancellation Request - CR: u1, - padding: u31, - }), - /// FDCAN Tx Buffer Transmission Occurred Register - TXBTO: mmio.Mmio(packed struct(u32) { - /// Transmission Occurred - TO: u1, - padding: u31, - }), - /// FDCAN Tx Buffer Cancellation Finished Register - TXBCF: mmio.Mmio(packed struct(u32) { - /// Cancellation Finished - CF: u1, - padding: u31, - }), - /// FDCAN Tx Buffer Transmission Interrupt Enable Register - TXBTIE: mmio.Mmio(packed struct(u32) { - /// Transmission Interrupt Enable - TIE: u1, - padding: u31, - }), - /// FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register - TXBCIE: mmio.Mmio(packed struct(u32) { - /// Cancellation Finished Interrupt Enable - CF: u1, - padding: u31, - }), - reserved240: [8]u8, - /// FDCAN Tx Event FIFO Configuration Register - TXEFC: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Event FIFO Start Address - EFSA: u14, - /// Event FIFO Size - EFS: u6, - reserved24: u2, - /// Event FIFO Watermark - EFWM: u6, - padding: u2, - }), - /// FDCAN Tx Event FIFO Status Register - TXEFS: mmio.Mmio(packed struct(u32) { - /// Event FIFO Fill Level - EFFL: u6, - reserved8: u2, - /// Event FIFO Get Index - EFGI: u5, - reserved16: u3, - /// Event FIFO put index - EFPI: u5, - reserved24: u3, - /// Event FIFO Full - EFF: u1, - /// Tx Event FIFO Element Lost - TEFL: u1, - padding: u6, - }), - /// FDCAN Tx Event FIFO Acknowledge Register - TXEFA: mmio.Mmio(packed struct(u32) { - /// Event FIFO Acknowledge Index - EFAI: u5, - padding: u27, - }), - reserved256: [4]u8, - /// FDCAN TT Trigger Memory Configuration Register - TTTMC: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Trigger Memory Start Address - TMSA: u14, - /// Trigger Memory Elements - TME: u7, - padding: u9, - }), - /// FDCAN TT Reference Message Configuration Register - TTRMC: mmio.Mmio(packed struct(u32) { - /// Reference Identifier - RID: u29, - reserved30: u1, - /// Extended Identifier - XTD: u1, - /// Reference Message Payload Select - RMPS: u1, - }), - /// FDCAN TT Operation Configuration Register - TTOCF: mmio.Mmio(packed struct(u32) { - /// Operation Mode - OM: u2, - reserved3: u1, - /// Gap Enable - GEN: u1, - /// Time Master - TM: u1, - /// LD of Synchronization Deviation Limit - LDSDL: u3, - /// Initial Reference Trigger Offset - IRTO: u7, - /// Enable External Clock Synchronization - EECS: u1, - /// Application Watchdog Limit - AWL: u8, - /// Enable Global Time Filtering - EGTF: u1, - /// Enable Clock Calibration - ECC: u1, - /// Event Trigger Polarity - EVTP: u1, - padding: u5, - }), - /// FDCAN TT Matrix Limits Register - TTMLM: mmio.Mmio(packed struct(u32) { - /// Cycle Count Max - CCM: u6, - /// Cycle Start Synchronization - CSS: u2, - /// Tx Enable Window - TXEW: u4, - reserved16: u4, - /// Expected Number of Tx Triggers - ENTT: u12, - padding: u4, - }), - /// FDCAN TUR Configuration Register - TURCF: mmio.Mmio(packed struct(u32) { - /// Numerator Configuration Low - NCL: u16, - /// Denominator Configuration - DC: u14, - reserved31: u1, - /// Enable Local Time - ELT: u1, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, }), - /// FDCAN TT Operation Control Register - TTOCN: mmio.Mmio(packed struct(u32) { - /// Set Global time - SGT: u1, - /// External Clock Synchronization - ECS: u1, - /// Stop Watch Polarity - SWP: u1, - /// Stop Watch Source - SWS: u2, - /// Register Time Mark Interrupt Pulse Enable - RTIE: u1, - /// Register Time Mark Compare - TMC: u2, - /// Trigger Time Mark Interrupt Pulse Enable - TTIE: u1, - /// Gap Control Select - GCS: u1, - /// Finish Gap - FGP: u1, - /// Time Mark Gap - TMG: u1, - /// Next is Gap - NIG: u1, - /// External Synchronization Control - ESCN: u1, - reserved15: u1, - /// TT Operation Control Register Locked - LCKC: u1, - padding: u16, + /// Control/status register (RCC_CSR) + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low speed oscillator enable + LSION: u1, + /// Internal low speed oscillator ready + LSIRDY: u1, + reserved24: u22, + /// Remove reset flag + RMVF: u1, + reserved26: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, }), - /// FDCAN TT Global Time Preset Register - TTGTP: mmio.Mmio(packed struct(u32) { - /// Time Preset - NCL: u16, - /// Cycle Time Target Phase - CTP: u16, + /// AHB peripheral clock reset register (RCC_AHBRSTR) + AHBRSTR: mmio.Mmio(packed struct(u32) { + reserved12: u12, + /// USB OTG FS reset + USB_OTG_FSRST: u1, + reserved14: u1, + /// Ethernet MAC reset + ETHRST: u1, + padding: u17, }), - /// FDCAN TT Time Mark Register - TTTMK: mmio.Mmio(packed struct(u32) { - /// Time Mark - TM: u16, - /// Time Mark Cycle Code - TICC: u7, - reserved31: u8, - /// TT Time Mark Register Locked - LCKM: u1, - }), - /// FDCAN TT Interrupt Register - TTIR: mmio.Mmio(packed struct(u32) { - /// Start of Basic Cycle - SBC: u1, - /// Start of Matrix Cycle - SMC: u1, - /// Change of Synchronization Mode - CSM: u1, - /// Start of Gap - SOG: u1, - /// Register Time Mark Interrupt - RTMI: u1, - /// Trigger Time Mark Event Internal - TTMI: u1, - /// Stop Watch Event - SWE: u1, - /// Global Time Wrap - GTW: u1, - /// Global Time Discontinuity - GTD: u1, - /// Global Time Error - GTE: u1, - /// Tx Count Underflow - TXU: u1, - /// Tx Count Overflow - TXO: u1, - /// Scheduling Error 1 - SE1: u1, - /// Scheduling Error 2 - SE2: u1, - /// Error Level Changed - ELC: u1, - /// Initialization Watch Trigger - IWTG: u1, - /// Watch Trigger - WT: u1, - /// Application Watchdog - AW: u1, - /// Configuration Error - CER: u1, - padding: u13, - }), - /// FDCAN TT Interrupt Enable Register - TTIE: mmio.Mmio(packed struct(u32) { - /// Start of Basic Cycle Interrupt Enable - SBCE: u1, - /// Start of Matrix Cycle Interrupt Enable - SMCE: u1, - /// Change of Synchronization Mode Interrupt Enable - CSME: u1, - /// Start of Gap Interrupt Enable - SOGE: u1, - /// Register Time Mark Interrupt Enable - RTMIE: u1, - /// Trigger Time Mark Event Internal Interrupt Enable - TTMIE: u1, - /// Stop Watch Event Interrupt Enable - SWEE: u1, - /// Global Time Wrap Interrupt Enable - GTWE: u1, - /// Global Time Discontinuity Interrupt Enable - GTDE: u1, - /// Global Time Error Interrupt Enable - GTEE: u1, - /// Tx Count Underflow Interrupt Enable - TXUE: u1, - /// Tx Count Overflow Interrupt Enable - TXOE: u1, - /// Scheduling Error 1 Interrupt Enable - SE1E: u1, - /// Scheduling Error 2 Interrupt Enable - SE2E: u1, - /// Change Error Level Interrupt Enable - ELCE: u1, - /// Initialization Watch Trigger Interrupt Enable - IWTGE: u1, - /// Watch Trigger Interrupt Enable - WTE: u1, - /// Application Watchdog Interrupt Enable - AWE: u1, - /// Configuration Error Interrupt Enable - CERE: u1, - padding: u13, - }), - /// FDCAN TT Interrupt Line Select Register - TTILS: mmio.Mmio(packed struct(u32) { - /// Start of Basic Cycle Interrupt Line - SBCL: u1, - /// Start of Matrix Cycle Interrupt Line - SMCL: u1, - /// Change of Synchronization Mode Interrupt Line - CSML: u1, - /// Start of Gap Interrupt Line - SOGL: u1, - /// Register Time Mark Interrupt Line - RTMIL: u1, - /// Trigger Time Mark Event Internal Interrupt Line - TTMIL: u1, - /// Stop Watch Event Interrupt Line - SWEL: u1, - /// Global Time Wrap Interrupt Line - GTWL: u1, - /// Global Time Discontinuity Interrupt Line - GTDL: u1, - /// Global Time Error Interrupt Line - GTEL: u1, - /// Tx Count Underflow Interrupt Line - TXUL: u1, - /// Tx Count Overflow Interrupt Line - TXOL: u1, - /// Scheduling Error 1 Interrupt Line - SE1L: u1, - /// Scheduling Error 2 Interrupt Line - SE2L: u1, - /// Change Error Level Interrupt Line - ELCL: u1, - /// Initialization Watch Trigger Interrupt Line - IWTGL: u1, - /// Watch Trigger Interrupt Line - WTL: u1, - /// Application Watchdog Interrupt Line - AWL: u1, - /// Configuration Error Interrupt Line - CERL: u1, - padding: u13, - }), - /// FDCAN TT Operation Status Register - TTOST: mmio.Mmio(packed struct(u32) { - /// Error Level - EL: u2, - /// Master State - MS: u2, - /// Synchronization State - SYS: u2, - /// Quality of Global Time Phase - QGTP: u1, - /// Quality of Clock Speed - QCS: u1, - /// Reference Trigger Offset - RTO: u8, - reserved22: u6, - /// Wait for Global Time Discontinuity - WGTD: u1, - /// Gap Finished Indicator - GFI: u1, - /// Time Master Priority - TMP: u3, - /// Gap Started Indicator - GSI: u1, - /// Wait for Event - WFE: u1, - /// Application Watchdog Event - AWE: u1, - /// Wait for External Clock Synchronization - WECS: u1, - /// Schedule Phase Lock - SPL: u1, - }), - /// FDCAN TUR Numerator Actual Register - TURNA: mmio.Mmio(packed struct(u32) { - /// Numerator Actual Value - NAV: u18, - padding: u14, - }), - /// FDCAN TT Local and Global Time Register - TTLGT: mmio.Mmio(packed struct(u32) { - /// Local Time - LT: u16, - /// Global Time - GT: u16, - }), - /// FDCAN TT Cycle Time and Count Register - TTCTC: mmio.Mmio(packed struct(u32) { - /// Cycle Time - CT: u16, - /// Cycle Count - CC: u6, - padding: u10, - }), - /// FDCAN TT Capture Time Register - TTCPT: mmio.Mmio(packed struct(u32) { - /// Cycle Count Value - CCV: u6, - reserved16: u10, - /// Stop Watch Value - SWV: u16, - }), - /// FDCAN TT Cycle Sync Mark Register - TTCSM: mmio.Mmio(packed struct(u32) { - /// Cycle Sync Mark - CSM: u16, - padding: u16, - }), - reserved768: [444]u8, - /// FDCAN TT Trigger Select Register - TTTS: mmio.Mmio(packed struct(u32) { - /// Stop watch trigger input selection - SWTDEL: u2, - reserved4: u2, - /// Event trigger input selection - EVTSEL: u2, - padding: u26, - }), - }; - }; - - pub const spdifrx_h7 = struct { - /// Receiver Interface - pub const SPDIFRX = extern struct { - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Peripheral Block Enable - SPDIFEN: u2, - /// Receiver DMA ENable for data flow - RXDMAEN: u1, - /// STerEO Mode - RXSTEO: u1, - /// RX Data format - DRFMT: u2, - /// Mask Parity error bit - PMSK: u1, - /// Mask of Validity bit - VMSK: u1, - /// Mask of channel status and user bits - CUMSK: u1, - /// Mask of Preamble Type bits - PTMSK: u1, - /// Control Buffer DMA ENable for control flow - CBDMAEN: u1, - /// Channel Selection - CHSEL: u1, - /// Maximum allowed re-tries during synchronization phase - NBTR: u2, - /// Wait For Activity - WFA: u1, - reserved16: u1, - /// input selection - INSEL: u3, - reserved20: u1, - /// Symbol Clock Enable - CKSEN: u1, - /// Backup Symbol Clock Enable - CKSBKPEN: u1, - padding: u10, - }), - /// Interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// RXNE interrupt enable - RXNEIE: u1, - /// Control Buffer Ready Interrupt Enable - CSRNEIE: u1, - /// Parity error interrupt enable - PERRIE: u1, - /// Overrun error Interrupt Enable - OVRIE: u1, - /// Synchronization Block Detected Interrupt Enable - SBLKIE: u1, - /// Synchronization Done - SYNCDIE: u1, - /// Serial Interface Error Interrupt Enable - IFEIE: u1, - padding: u25, - }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Read data register not empty - RXNE: u1, - /// Control Buffer register is not empty - CSRNE: u1, - /// Parity error - PERR: u1, - /// Overrun error - OVR: u1, - /// Synchronization Block Detected - SBD: u1, - /// Synchronization Done - SYNCD: u1, - /// Framing error - FERR: u1, - /// Synchronization error - SERR: u1, - /// Time-out error - TERR: u1, - reserved16: u7, - /// Duration of 5 symbols counted with SPDIF_CLK - WIDTH: u15, - padding: u1, - }), - /// Interrupt Flag Clear register - IFCR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Clears the Parity error flag - PERRCF: u1, - /// Clears the Overrun error flag - OVRCF: u1, - /// Clears the Synchronization Block Detected flag - SBDCF: u1, - /// Clears the Synchronization Done flag - SYNCDCF: u1, - padding: u26, - }), - /// Data input register - FMT0_DR: mmio.Mmio(packed struct(u32) { - /// Parity Error bit - DR: u24, - /// Parity Error bit - PE: u1, - /// Validity bit - V: u1, - /// User bit - U: u1, - /// Channel Status bit - C: u1, - /// Preamble Type - PT: u2, - padding: u2, - }), - /// Channel Status register - CSR: mmio.Mmio(packed struct(u32) { - /// User data information - USR: u16, - /// Channel A status information - CS: u8, - /// Start Of Block - SOB: u1, - padding: u7, - }), - /// Debug Information register - DIR: mmio.Mmio(packed struct(u32) { - /// Threshold HIGH - THI: u13, - reserved16: u3, - /// Threshold LOW - TLO: u13, - padding: u3, + /// Clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// PREDIV1 division factor + PREDIV1: packed union { + raw: u4, + value: PREDIV1, + }, + /// PREDIV2 division factor + PREDIV2: packed union { + raw: u4, + value: PREDIV1, + }, + /// PLL2 Multiplication Factor + PLL2MUL: packed union { + raw: u4, + value: PLL2MUL, + }, + /// PLL3 Multiplication Factor + PLL3MUL: packed union { + raw: u4, + value: PLL2MUL, + }, + /// PREDIV1 entry clock source + PREDIV1SRC: packed union { + raw: u1, + value: PREDIV1SRC, + }, + /// I2S2 clock source + I2S2SRC: packed union { + raw: u1, + value: I2S2SRC, + }, + /// I2S3 clock source + I2S3SRC: packed union { + raw: u1, + value: I2S2SRC, + }, + padding: u13, }), }; }; - pub const syscfg_l0 = struct { - /// System configuration controller - pub const SYSCFG = extern struct { - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection bits - MEM_MODE: u2, - reserved3: u1, - /// User bank swapping - UFB: u1, - reserved8: u4, - /// Boot mode selected by the boot pins status bits - BOOT_MODE: u2, - padding: u22, - }), - /// CFGR2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// Firewall disable bit - FWDIS: u1, - reserved8: u7, - /// Fm+ drive capability on PB6 enable bit - I2C_PB6_FMP: u1, - /// Fm+ drive capability on PB7 enable bit - I2C_PB7_FMP: u1, - /// Fm+ drive capability on PB8 enable bit - I2C_PB8_FMP: u1, - /// Fm+ drive capability on PB9 enable bit - I2C_PB9_FMP: u1, - /// I2C1 Fm+ drive capability enable bit - I2C1_FMP: u1, - /// I2C2 Fm+ drive capability enable bit - I2C2_FMP: u1, - /// I2C3 Fm+ drive capability enable bit - I2C3_FMP: u1, - padding: u17, - }), - /// external interrupt configuration register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u4, - padding: u28, - }), - reserved32: [8]u8, - /// CFGR3 - CFGR3: mmio.Mmio(packed struct(u32) { - /// VREFINT enable and scaler control for COMP2 enable bit - EN_VREFINT: u1, - reserved4: u3, - /// VREFINT_ADC connection bit - SEL_VREF_OUT: u2, - reserved8: u2, - /// VREFINT reference for ADC enable bit - ENBUF_VREFINT_ADC: u1, - /// Temperature sensor reference for ADC enable bit - ENBUF_SENSOR_ADC: u1, - reserved12: u2, - /// VREFINT reference for COMP2 scaler enable bit - ENBUF_VREFINT_COMP2: u1, - /// VREFINT reference for HSI48 oscillator enable bit - ENREF_HSI48: u1, - reserved30: u16, - /// VREFINT ready flag - VREFINT_RDYF: u1, - /// SYSCFG_CFGR3 lock bit - REF_LOCK: u1, - }), + pub const rcc_f2 = struct { + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, + _, }; - }; - pub const pwr_h7rs = struct { - pub const ALS = enum(u2) { - /// AVD level 1. - Level1 = 0x0, - /// AVD level 2. - Level2 = 0x1, - /// AVD level 3. - Level3 = 0x2, - /// AVD level 4. - Level4 = 0x3, + pub const ISSRC = enum(u1) { + /// PLLI2S clock used as I2S clock source + PLLI2S = 0x0, + /// External clock mapped on the I2S_CKIN pin used as I2S clock source + CKIN = 0x1, }; - pub const AVDO = enum(u1) { - /// VDDA is equal or higher than the AVD threshold selected with the ALS[1:0] bits. - AboveOrEqual = 0x0, - /// VDDA is lower than the AVD threshold selected with the ALS[1:0] bits. - Below = 0x1, + pub const MCO1SEL = enum(u2) { + /// HSI clock selected + HSI = 0x0, + /// LSE oscillator selected + LSE = 0x1, + /// HSE oscillator clock selected + HSE = 0x2, + /// PLL clock selected + PLL = 0x3, }; - pub const PDDS = enum(u1) { - /// Stop mode when device enters Deepsleep. - Stop = 0x0, - /// Standby mode when device enters Deepsleep. - Standby = 0x1, + pub const MCO2SEL = enum(u2) { + /// System clock (SYSCLK) selected + SYS = 0x0, + /// PLLI2S clock selected + PLLI2S = 0x1, + /// HSE oscillator clock selected + HSE = 0x2, + /// PLL clock selected + PLL = 0x3, }; - pub const PLS = enum(u3) { - /// PVD level 1. - Level1 = 0x0, - /// PVD level 2. - Level2 = 0x1, - /// PVD level 3. - Level3 = 0x2, - /// PVD level 4. - Level4 = 0x3, - /// PVD level 5. - Level5 = 0x4, - /// PVD level 6. - Level6 = 0x5, - /// PVD level 7. - Level7 = 0x6, - /// External voltage level on PVD_IN pin, compared to internal VREFINT level. - External = 0x7, + pub const MCOPRE = enum(u3) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x4, + /// Division by 3 + Div3 = 0x5, + /// Division by 4 + Div4 = 0x6, + /// Division by 5 + Div5 = 0x7, + _, }; - pub const PVDO = enum(u1) { - /// VDD or PVD_IN voltage is equal or higher than the PVD threshold selected through the. - AboveOrEqual = 0x0, - /// VDD or PVD_IN voltage is lower than the PVD threshold selected through the PLS[2:0]. - Below = 0x1, + pub const PLLM = enum(u6) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + Div16 = 0x10, + Div17 = 0x11, + Div18 = 0x12, + Div19 = 0x13, + Div20 = 0x14, + Div21 = 0x15, + Div22 = 0x16, + Div23 = 0x17, + Div24 = 0x18, + Div25 = 0x19, + Div26 = 0x1a, + Div27 = 0x1b, + Div28 = 0x1c, + Div29 = 0x1d, + Div30 = 0x1e, + Div31 = 0x1f, + Div32 = 0x20, + Div33 = 0x21, + Div34 = 0x22, + Div35 = 0x23, + Div36 = 0x24, + Div37 = 0x25, + Div38 = 0x26, + Div39 = 0x27, + Div40 = 0x28, + Div41 = 0x29, + Div42 = 0x2a, + Div43 = 0x2b, + Div44 = 0x2c, + Div45 = 0x2d, + Div46 = 0x2e, + Div47 = 0x2f, + Div48 = 0x30, + Div49 = 0x31, + Div50 = 0x32, + Div51 = 0x33, + Div52 = 0x34, + Div53 = 0x35, + Div54 = 0x36, + Div55 = 0x37, + Div56 = 0x38, + Div57 = 0x39, + Div58 = 0x3a, + Div59 = 0x3b, + Div60 = 0x3c, + Div61 = 0x3d, + Div62 = 0x3e, + Div63 = 0x3f, + _, }; - pub const RLPSN = enum(u1) { - /// RAM enters to low power mode when system enters to STOP. - LowPower = 0x0, - /// RAM remains in normal mode when system enters to STOP. - Normal = 0x1, + pub const PLLN = enum(u9) { + Mul192 = 0xc0, + Mul193 = 0xc1, + Mul194 = 0xc2, + Mul195 = 0xc3, + Mul196 = 0xc4, + Mul197 = 0xc5, + Mul198 = 0xc6, + Mul199 = 0xc7, + Mul200 = 0xc8, + Mul201 = 0xc9, + Mul202 = 0xca, + Mul203 = 0xcb, + Mul204 = 0xcc, + Mul205 = 0xcd, + Mul206 = 0xce, + Mul207 = 0xcf, + Mul208 = 0xd0, + Mul209 = 0xd1, + Mul210 = 0xd2, + Mul211 = 0xd3, + Mul212 = 0xd4, + Mul213 = 0xd5, + Mul214 = 0xd6, + Mul215 = 0xd7, + Mul216 = 0xd8, + Mul217 = 0xd9, + Mul218 = 0xda, + Mul219 = 0xdb, + Mul220 = 0xdc, + Mul221 = 0xdd, + Mul222 = 0xde, + Mul223 = 0xdf, + Mul224 = 0xe0, + Mul225 = 0xe1, + Mul226 = 0xe2, + Mul227 = 0xe3, + Mul228 = 0xe4, + Mul229 = 0xe5, + Mul230 = 0xe6, + Mul231 = 0xe7, + Mul232 = 0xe8, + Mul233 = 0xe9, + Mul234 = 0xea, + Mul235 = 0xeb, + Mul236 = 0xec, + Mul237 = 0xed, + Mul238 = 0xee, + Mul239 = 0xef, + Mul240 = 0xf0, + Mul241 = 0xf1, + Mul242 = 0xf2, + Mul243 = 0xf3, + Mul244 = 0xf4, + Mul245 = 0xf5, + Mul246 = 0xf6, + Mul247 = 0xf7, + Mul248 = 0xf8, + Mul249 = 0xf9, + Mul250 = 0xfa, + Mul251 = 0xfb, + Mul252 = 0xfc, + Mul253 = 0xfd, + Mul254 = 0xfe, + Mul255 = 0xff, + Mul256 = 0x100, + Mul257 = 0x101, + Mul258 = 0x102, + Mul259 = 0x103, + Mul260 = 0x104, + Mul261 = 0x105, + Mul262 = 0x106, + Mul263 = 0x107, + Mul264 = 0x108, + Mul265 = 0x109, + Mul266 = 0x10a, + Mul267 = 0x10b, + Mul268 = 0x10c, + Mul269 = 0x10d, + Mul270 = 0x10e, + Mul271 = 0x10f, + Mul272 = 0x110, + Mul273 = 0x111, + Mul274 = 0x112, + Mul275 = 0x113, + Mul276 = 0x114, + Mul277 = 0x115, + Mul278 = 0x116, + Mul279 = 0x117, + Mul280 = 0x118, + Mul281 = 0x119, + Mul282 = 0x11a, + Mul283 = 0x11b, + Mul284 = 0x11c, + Mul285 = 0x11d, + Mul286 = 0x11e, + Mul287 = 0x11f, + Mul288 = 0x120, + Mul289 = 0x121, + Mul290 = 0x122, + Mul291 = 0x123, + Mul292 = 0x124, + Mul293 = 0x125, + Mul294 = 0x126, + Mul295 = 0x127, + Mul296 = 0x128, + Mul297 = 0x129, + Mul298 = 0x12a, + Mul299 = 0x12b, + Mul300 = 0x12c, + Mul301 = 0x12d, + Mul302 = 0x12e, + Mul303 = 0x12f, + Mul304 = 0x130, + Mul305 = 0x131, + Mul306 = 0x132, + Mul307 = 0x133, + Mul308 = 0x134, + Mul309 = 0x135, + Mul310 = 0x136, + Mul311 = 0x137, + Mul312 = 0x138, + Mul313 = 0x139, + Mul314 = 0x13a, + Mul315 = 0x13b, + Mul316 = 0x13c, + Mul317 = 0x13d, + Mul318 = 0x13e, + Mul319 = 0x13f, + Mul320 = 0x140, + Mul321 = 0x141, + Mul322 = 0x142, + Mul323 = 0x143, + Mul324 = 0x144, + Mul325 = 0x145, + Mul326 = 0x146, + Mul327 = 0x147, + Mul328 = 0x148, + Mul329 = 0x149, + Mul330 = 0x14a, + Mul331 = 0x14b, + Mul332 = 0x14c, + Mul333 = 0x14d, + Mul334 = 0x14e, + Mul335 = 0x14f, + Mul336 = 0x150, + Mul337 = 0x151, + Mul338 = 0x152, + Mul339 = 0x153, + Mul340 = 0x154, + Mul341 = 0x155, + Mul342 = 0x156, + Mul343 = 0x157, + Mul344 = 0x158, + Mul345 = 0x159, + Mul346 = 0x15a, + Mul347 = 0x15b, + Mul348 = 0x15c, + Mul349 = 0x15d, + Mul350 = 0x15e, + Mul351 = 0x15f, + Mul352 = 0x160, + Mul353 = 0x161, + Mul354 = 0x162, + Mul355 = 0x163, + Mul356 = 0x164, + Mul357 = 0x165, + Mul358 = 0x166, + Mul359 = 0x167, + Mul360 = 0x168, + Mul361 = 0x169, + Mul362 = 0x16a, + Mul363 = 0x16b, + Mul364 = 0x16c, + Mul365 = 0x16d, + Mul366 = 0x16e, + Mul367 = 0x16f, + Mul368 = 0x170, + Mul369 = 0x171, + Mul370 = 0x172, + Mul371 = 0x173, + Mul372 = 0x174, + Mul373 = 0x175, + Mul374 = 0x176, + Mul375 = 0x177, + Mul376 = 0x178, + Mul377 = 0x179, + Mul378 = 0x17a, + Mul379 = 0x17b, + Mul380 = 0x17c, + Mul381 = 0x17d, + Mul382 = 0x17e, + Mul383 = 0x17f, + Mul384 = 0x180, + Mul385 = 0x181, + Mul386 = 0x182, + Mul387 = 0x183, + Mul388 = 0x184, + Mul389 = 0x185, + Mul390 = 0x186, + Mul391 = 0x187, + Mul392 = 0x188, + Mul393 = 0x189, + Mul394 = 0x18a, + Mul395 = 0x18b, + Mul396 = 0x18c, + Mul397 = 0x18d, + Mul398 = 0x18e, + Mul399 = 0x18f, + Mul400 = 0x190, + Mul401 = 0x191, + Mul402 = 0x192, + Mul403 = 0x193, + Mul404 = 0x194, + Mul405 = 0x195, + Mul406 = 0x196, + Mul407 = 0x197, + Mul408 = 0x198, + Mul409 = 0x199, + Mul410 = 0x19a, + Mul411 = 0x19b, + Mul412 = 0x19c, + Mul413 = 0x19d, + Mul414 = 0x19e, + Mul415 = 0x19f, + Mul416 = 0x1a0, + Mul417 = 0x1a1, + Mul418 = 0x1a2, + Mul419 = 0x1a3, + Mul420 = 0x1a4, + Mul421 = 0x1a5, + Mul422 = 0x1a6, + Mul423 = 0x1a7, + Mul424 = 0x1a8, + Mul425 = 0x1a9, + Mul426 = 0x1aa, + Mul427 = 0x1ab, + Mul428 = 0x1ac, + Mul429 = 0x1ad, + Mul430 = 0x1ae, + Mul431 = 0x1af, + Mul432 = 0x1b0, + _, }; - pub const SDLEVEL = enum(u1) { - Reset = 0x0, - V1_8 = 0x1, + pub const PLLP = enum(u2) { + /// PLLP=2 + Div2 = 0x0, + /// PLLP=4 + Div4 = 0x1, + /// PLLP=6 + Div6 = 0x2, + /// PLLP=8 + Div8 = 0x3, }; - pub const SVOS = enum(u1) { - /// SVOS Low. - Low = 0x0, - /// SVOS High (default). - High = 0x1, + pub const PLLQ = enum(u4) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + _, }; - pub const SYNC_ADC = enum(u1) { - /// SD_Converter clock free running. - FreeRunning = 0x0, - /// SD_Converter clock synchronised to ADC. - Synchronized = 0x1, + pub const PLLR = enum(u3) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + _, }; - pub const UNLOCKED = enum(u1) { - /// accessed locked: key was not written and after each register write access. - Locked = 0x0, - /// after key 0xCAFECAFE was written in this register. - Unlocked = 0x1, + pub const PLLSRC = enum(u1) { + /// HSI clock selected as PLL and PLLI2S clock entry + HSI = 0x0, + /// HSE oscillator clock selected as PLL and PLLI2S clock entry + HSE = 0x1, }; - pub const VBRS = enum(u1) { - /// Charge VBAT through a 5 k resistor. - Ohm5k = 0x0, - /// Charge VBAT through a 1.5 k resistor. - Ohm1_5k = 0x1, + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, }; - pub const VOS = enum(u1) { - /// VOS Low level (default). - Low = 0x0, - /// VOS High level. - High = 0x1, + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, }; - pub const WKUPP = enum(u1) { - /// Detection on high level (rising edge). - High = 0x0, - /// Detection on low level (falling edge). - Low = 0x1, + pub const SPREADSEL = enum(u1) { + /// Center spread + Center = 0x0, + /// Down spread + Down = 0x1, }; - pub const WKUPPUPD = enum(u2) { - /// No pull-up. - NoPull = 0x0, - /// Pull-up. - PullUp = 0x1, - /// Pull-down. - PullDown = 0x2, + pub const SW = enum(u2) { + /// HSI selected as system clock + HSI = 0x0, + /// HSE selected as system clock + HSE = 0x1, + /// PLL selected as system clock + PLL1_P = 0x2, _, }; - pub const XSPICAP = enum(u2) { - /// XSPI Capacitor OFF (default) note: to confirm with analog design. - Disabled = 0x0, - /// XSPI Capacitor set to 1/3. - OneThird = 0x1, - /// XSPI Capacitor set to 2/3. - TwoThirds = 0x2, - /// XSPI Capacitor set to full capacitance. - Full = 0x3, - }; - - /// Power control. - pub const PWR = extern struct { - /// PWR control register 1. - CR1: mmio.Mmio(packed struct(u32) { - /// System Stop mode voltage scaling selection. - SVOS: packed union { - raw: u1, - value: SVOS, - }, - reserved4: u3, - /// Programmable voltage detector enable. - PVDE: u1, - /// Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. - PLS: packed union { - raw: u3, - value: PLS, + /// Reset and clock control + pub const RCC = extern struct { + /// clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal high-speed clock enable + HSION: u1, + /// Internal high-speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal high-speed clock trimming + HSITRIM: u5, + /// Internal high-speed clock calibration + HSICAL: u8, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + /// Clock security system enable + CSSON: u1, + reserved24: u4, + /// Main PLL (PLL) enable + PLLON: u1, + /// Main PLL (PLL) clock ready flag + PLLRDY: u1, + /// PLLI2S enable + PLLI2SON: u1, + /// PLLI2S clock ready flag + PLLI2SRDY: u1, + padding: u4, + }), + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM: packed union { + raw: u6, + value: PLLM, }, - /// Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in the PWR_CSR1 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. - DBP: u1, - /// Flash low-power mode in Stop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when device is in Stop mode. consumption). - FLPS: u1, - /// RAM low power mode disable in STOP. When set the RAMs will not enter to low power mode when the system enters to STOP. - RLPSN: packed union { - raw: u1, - value: RLPSN, + /// Main PLL (PLL) multiplication factor for VCO + PLLN: packed union { + raw: u9, + value: PLLN, }, - /// analog switch VBoost control This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits. - BOOSTE: u1, - /// analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected VDDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_CSR1 register) after setting the AVDEN bit and selecting the supply level to be monitored (ALS bits). - AVDREADY: u1, - /// Peripheral voltage monitor on VDDA enable. - AVDEN: u1, - /// Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. - ALS: packed union { + reserved16: u1, + /// Main PLL (PLL) division factor for main system clock + PLLP: packed union { raw: u2, - value: ALS, + value: PLLP, }, - padding: u16, - }), - /// PWR control status register 1. - SR1: mmio.Mmio(packed struct(u32) { - /// VOS currently applied for VCORE voltage scaling selection. These bit reflect the last VOS value applied to the PMU. - ACTVOS: u1, - /// Voltage levels ready bit for currently used ACTVOS and SDHILEVEL This bit is set to 1 by hardware when the voltage regulator and the SMPS step-down converter are both disabled and Bypass mode is selected in PWR control register 2 (PWR_CSR2). - ACTVOSRDY: u1, - reserved4: u2, - /// Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. PLS[2:0] bits. bits. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. - PVDO: packed union { + reserved22: u4, + /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + PLLSRC: packed union { raw: u1, - value: PVDO, + value: PLLSRC, }, - reserved13: u8, - /// Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set. - AVDO: packed union { - raw: u1, - value: AVDO, + reserved24: u1, + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ: packed union { + raw: u4, + value: PLLQ, }, - padding: u18, - }), - /// PWR control status register 1. - CSR1: mmio.Mmio(packed struct(u32) { - /// Backup regulator enable When set, the backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. - BREN: u1, - reserved4: u3, - /// VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. Note: VBAT and temperature monitoring are only available when the backup regulator is enabled (BREN bit set to 1). - MONEN: u1, - reserved16: u11, - /// Backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready. - BRRDY: u1, - reserved20: u3, - /// VBAT level monitoring versus low threshold. - VBATL: u1, - /// VBAT level monitoring versus high threshold. - VBATH: u1, - /// Temperature level monitoring versus low threshold. - TEMPL: u1, - /// Temperature level monitoring versus high threshold. - TEMPH: u1, - padding: u8, + padding: u4, }), - /// PWR control register 2. - CSR2: mmio.Mmio(packed struct(u32) { - /// Power management unit bypass Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41. - BYPASS: u1, - /// Low drop-out regulator enable Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41. - LDOEN: u1, - /// SMPS step-down converter enable Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41. - SDEN: u1, - /// SMPS external power delivery selection Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41. - SDEXTHP: u1, - /// SMPS step-down converter voltage output for LDO or external supply This bit is used when both the LDO and SMPS step-down converter are enabled with SDEN and LDOEN enabled or when SMPSEXTHP is enabled. In this case SDHILEVEL has to be set to 1 to confirm the regulator settings. - SDLEVEL: packed union { - raw: u1, - value: SDLEVEL, - }, - reserved8: u3, - /// VBAT charging enable. - VBE: u1, - /// VBAT charging resistor selection. - VBRS: packed union { - raw: u1, - value: VBRS, + /// clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u2, + value: SW, }, - /// XSPI port 1 capacitor control bits see the product datasheet for more details. - XSPICAP1: packed union { + /// System clock switch status + SWS: packed union { raw: u2, - value: XSPICAP, + value: SW, }, - /// XSPI port 2 capacitor control bits see the product datasheet for more details. - XSPICAP2: packed union { + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + reserved10: u2, + /// APB Low speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + /// APB high-speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + /// HSE division factor for RTC clock + RTCPRE: u5, + /// Microcontroller clock output 1 + MCO1SEL: packed union { raw: u2, - value: XSPICAP, + value: MCO1SEL, }, - /// EN_XSPIM1: this bit allow the SW to enable the XSPI interface. The XSPIM_P1 supply must be stable prior to setting this bit. - EN_XSPIM1: u1, - /// EN_XSPIM2: this bit allows the SW to enable the XSPI interface, when available. The XSPIM_P2 supply must be stable prior to setting this bit. It should also be set when FMC is used. - EN_XSPIM2: u1, - /// SMPS step-down converter external supply ready This bit is set by hardware to indicate that the external supply from the SMPS step-down converter is ready. - SDEXTRDY: u1, - reserved24: u7, - /// VDD33_USB voltage level detector enable. - USB33DEN: u1, - /// USB regulator enable. - USBREGEN: u1, - /// USB supply ready. - USB33RDY: u1, - /// USB HS regulator enable. - USBHSREGEN: u1, - padding: u4, - }), - /// PWR CPU control register 3. - CSR3: mmio.Mmio(packed struct(u32) { - /// Power Down Deepsleep. This bit allows CPU to define the Deepsleep mode. - PDDS: packed union { + /// I2S clock selection + I2SSRC: packed union { raw: u1, - value: PDDS, + value: ISSRC, }, - /// Clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware. - CSSF: u1, - reserved8: u6, - /// STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU CSSF bit. - STOPF: u1, - /// System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU CSSF bit. - SBF: u1, - padding: u22, - }), - /// PWR control status register 4. - CSR4: mmio.Mmio(packed struct(u32) { - /// Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling must be changed before increasing the system frequency. When decreasing performance, the system frequency must first be decreased before changing the voltage scaling. Note: Refer to Section Electrical characteristics of the product datasheet for more details. - VOS: packed union { - raw: u1, - value: VOS, + /// MCO1 prescaler + MCO1PRE: packed union { + raw: u3, + value: MCOPRE, }, - /// VOS Ready bit. - VOSRDY: u1, - padding: u30, - }), - reserved32: [8]u8, - /// PWR wakeup clear register. - WKUPCR: mmio.Mmio(packed struct(u32) { - /// Clear Wakeup pin flag for WKUP1 These bits are always read as 0. - WKUPC: u1, - padding: u31, - }), - /// PWR wakeup flag register. - WKUPFR: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC1 bit in the PWR wakeup clear register (PWR_WKUPCR). - WKUPF: u1, - padding: u31, - }), - /// PWR wakeup enable and polarity register. - WKUPEPR: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge. - WKUPEN: u1, - reserved8: u7, - /// Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin. - WKUPP: packed union { - raw: u1, - value: WKUPP, + /// MCO2 prescaler + MCO2PRE: packed union { + raw: u3, + value: MCOPRE, }, - reserved16: u7, - /// Wakeup pin pull configuration - WKUPPUPD: packed union { + /// Microcontroller clock output 2 + MCO2SEL: packed union { raw: u2, - value: WKUPPUPD, + value: MCO2SEL, }, - padding: u14, }), - /// PWR USB Type-C and Power Delivery register. - UCPDR: mmio.Mmio(packed struct(u32) { - /// UCPD dead battery disable. - UCPD_DBDIS: u1, - /// UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers. - UCPD_STBY: u1, - padding: u30, + /// clock interrupt register + CIR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// Main PLL (PLL) ready interrupt flag + PLLRDYF: u1, + /// PLLI2S ready interrupt flag + PLLI2SRDYF: u1, + reserved7: u1, + /// Clock security system interrupt flag + CSSF: u1, + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// Main PLL (PLL) ready interrupt enable + PLLRDYIE: u1, + /// PLLI2S ready interrupt enable + PLLI2SRDYIE: u1, + reserved16: u2, + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// Main PLL(PLL) ready interrupt clear + PLLRDYC: u1, + /// PLLI2S ready interrupt clear + PLLI2SRDYC: u1, + reserved23: u1, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, }), - /// PWR apply pull configuration register. - APCR: mmio.Mmio(packed struct(u32) { - /// Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx, PDCRx registers are applied in Standby mode even after wakeup until APC bit is reset to 0. When this bit is cleared, the I/O pull-up or pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx and PDCRx registers are not applied in Standby mode and IO becomes Hi-Z. - APC: u1, - reserved16: u15, - /// Port N bit 7 pull-up/down configuration When this bit is set, a weak pull-up or pull-down resistor is applied on PN7 following inverse logic applied on PN6. If the PUN6 bit in PWR_PUCRN register is set and APC bit is set the week pull-down is applied on PN7. If the PDN6 bit in PWR_PDCRN register is set and APC bit is set the week pull-up is applied on PN7. - PN7_PUPD: u1, - /// Port O bit 5 pull-up/down configuration When this bit is set, a weak pull-up or pull down resistor is applied on PO5 following inverse logic applied on PO4. If the PUO4 bit in PWR_PUCRO register is set and APC bit is set the week pull-down is applied on PO5. If the PDO4 bit in PWR_PDCRO register is set and APC bit is set the week pull-up is applied on PO5.. - PO5_PUPD: u1, - reserved28: u10, - /// Port PB6 I3C pull-up bit When I3C is used on PB6, when set, this bit activates the pull-up on I3C1_SCL (PB6) in standby mode. - I3CPB6_PU: u1, - /// Port PB7 I3C pull-up bit When I3C is used on PB7, when set, this bit activates the pull-up on I3C1_SDA (PB7) in standby mode. - I3CPB7_PU: u1, - /// Port PB8 I3C pull-up bit When I3C is used on PB8, when set, this bit activates the pull-up on I3C1_SCL (PB8) in standby mode. - I3CPB8_PU: u1, - /// Port PB9 I3C pull-up bit When I3C is used on PB9, when set, this bit activates the pull-up on I3C1_SDA (PB9) in standby mode. - I3CPB9_PU: u1, + /// AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// IO port H reset + GPIOHRST: u1, + /// IO port I reset + GPIOIRST: u1, + reserved12: u3, + /// CRC reset + CRCRST: u1, + reserved21: u8, + /// DMA2 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + reserved25: u2, + /// Ethernet MAC reset + ETHRST: u1, + reserved29: u3, + /// USB OTG HS module reset + USB_OTG_HSRST: u1, + padding: u2, }), - /// PWR port N pull-up control register. - PUCRN: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Port N pull-up bit 1 When set, each bit activates the pull-up on PN1 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD1 bit is also set. - PUN1: u1, - reserved6: u4, - /// Port N pull-up bit 6 When set activates the pull-up on PN6 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PDN6 bit is also set. - PUN6: u1, - reserved12: u5, - /// Port N pull-up bit 12 When set, each bit activates the pull-up on PN12 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD12 bit is also set. - PUN12: u1, - padding: u19, + /// AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// Camera interface reset + DCMIRST: u1, + reserved4: u3, + /// Cryptographic module reset + CRYPRST: u1, + /// Hash module reset + HSAHRST: u1, + /// Random number generator module reset + RNGRST: u1, + /// USB OTG FS module reset + USB_OTG_FSRST: u1, + padding: u24, }), - /// PWR port N pull-down control register. - PDCRN: mmio.Mmio(packed struct(u32) { - /// Port N pull-down bit 0 When set activates the pull-down on PN0 when the APC bit is set in PWR_APCR. - PDN0: u1, - /// Port N pull-down bit 1 When set activates the pull-down on PN1 when the APC bit is set in PWR_APCR. - PDN1: u1, - /// Port N PN2 to PN5 pull-down activation When set, four pull-down resistors are activated on PN2 to PN5 when the APC bit is set in PWR_APCR. - PDN2N5: u1, - reserved6: u3, - /// Port N pull-down bit 6 When set activates the pull-down on PN6 when the APC bit is set in PWR_APCR. - PDN6: u1, - reserved8: u1, - /// Port N - PN8 to PN11 pull-down activation When set, four pull-down resistors are activated on PN8 to PN11 when the APC bit is set in PWR_APCR. - PDN8N11: u1, - reserved12: u3, - /// Port N pull-down bit 12 When set activates the pull-down on PN12 when the APC bit is set in PWR_APCR. - PDN12: u1, - padding: u19, + /// AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// Flexible static memory controller module reset + FSMCRST: u1, + padding: u31, }), - /// PWR port O pull-up control register. - PUCRO: mmio.Mmio(packed struct(u32) { - /// (n = 1 to 0) Port O pull-up bits When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set. - PUO0: u1, - /// (n = 1 to 0) Port O pull-up bits When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set. - PUO1: u1, + reserved32: [4]u8, + /// APB1 peripheral reset register + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// TIM2 reset + TIM2RST: u1, + /// TIM3 reset + TIM3RST: u1, + /// TIM4 reset + TIM4RST: u1, + /// TIM5 reset + TIM5RST: u1, + /// TIM6 reset + TIM6RST: u1, + /// TIM7 reset + TIM7RST: u1, + /// TIM12 reset + TIM12RST: u1, + /// TIM13 reset + TIM13RST: u1, + /// TIM14 reset + TIM14RST: u1, + reserved11: u2, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI 2 reset + SPI2RST: u1, + /// SPI 3 reset + SPI3RST: u1, + reserved17: u1, + /// USART 2 reset + UART2RST: u1, + /// USART 3 reset + UART3RST: u1, + /// USART 4 reset + UART4RST: u1, + /// USART 5 reset + UART5RST: u1, + /// I2C 1 reset + I2C1RST: u1, + /// I2C 2 reset + I2C2RST: u1, + /// I2C3 reset + I2C3RST: u1, + reserved25: u1, + /// CAN1 reset + CAN1RST: u1, + /// CAN2 reset + CAN2RST: u1, + reserved28: u1, + /// Power interface reset + PWRRST: u1, + /// DAC reset + DACRST: u1, + padding: u2, + }), + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// TIM1 reset + TIM1RST: u1, + /// TIM8 reset + TIM8RST: u1, reserved4: u2, - /// Port O pull-up bit 4 When set activates the pull-up on PO4 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits PDO4 in PWR_PDCRO is also set. - PUO4: u1, - padding: u27, + /// USART1 reset + USART1RST: u1, + /// USART6 reset + USART6RST: u1, + reserved8: u2, + /// ADC interface reset (common to all ADCs) + ADCRST: u1, + reserved11: u2, + /// SDIO reset + SDIORST: u1, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// System configuration controller reset + SYSCFGRST: u1, + reserved16: u1, + /// TIM9 reset + TIM9RST: u1, + /// TIM10 reset + TIM10RST: u1, + /// TIM11 reset + TIM11RST: u1, + padding: u13, }), - /// PWR port O pull-down control register. - PDCRO: mmio.Mmio(packed struct(u32) { - /// Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. - PDO0: u1, - /// Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. - PDO1: u1, - /// Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. - PDO2: u1, - /// Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. - PDO3: u1, - /// Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. - PDO4: u1, - padding: u27, + reserved48: [8]u8, + /// AHB1 peripheral clock register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// IO port H clock enable + GPIOHEN: u1, + /// IO port I clock enable + GPIOIEN: u1, + reserved12: u3, + /// CRC clock enable + CRCEN: u1, + reserved18: u5, + /// Backup SRAM interface clock enable + BKPSRAMEN: u1, + reserved21: u2, + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + reserved25: u2, + /// Ethernet MAC clock enable + ETHEN: u1, + /// Ethernet Transmission clock enable + ETHTXEN: u1, + /// Ethernet Reception clock enable + ETHRXEN: u1, + /// Ethernet PTP clock enable + ETHPTPEN: u1, + /// USB OTG HS clock enable + USB_OTG_HSEN: u1, + /// USB OTG HSULPI clock enable + USB_OTG_HSULPIEN: u1, + padding: u1, }), - /// PWR port P pull-down control register. - PDCRP: mmio.Mmio(packed struct(u32) { - /// Port P0-P3 pull-down activation When set, four pull-down resistors are activated on P0 to P3 when the APC bit is set in PWR_APCR. - PDP0P3: u1, + /// AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// Camera interface enable + DCMIEN: u1, reserved4: u3, - /// Port P4-P7 pull-down activation When set, four pull-down resitors are activated on P4 to P7 when the APC bit is set in PWR_APCR. - PDP4P7: u1, - reserved8: u3, - /// Port P8-P11 pull-down activation When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR. - PDP8P11: u1, - reserved12: u3, - /// Port P12-P15 pull-down activation When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR. - PDP12P15: u1, - padding: u19, + /// Cryptographic modules clock enable + CRYPEN: u1, + /// Hash modules clock enable + HASHEN: u1, + /// Random number generator clock enable + RNGEN: u1, + /// USB OTG FS clock enable + USB_OTG_FSEN: u1, + padding: u24, }), - reserved80: [8]u8, - /// PWR debug register 1. - PDR1: mmio.Mmio(packed struct(u32) { - /// Debug Register Unlocked. - UNLOCKED: packed union { - raw: u1, - value: UNLOCKED, - }, - reserved3: u2, - /// Step down converter force PWM mode. - SDFPWMEN: u1, - reserved16: u12, - /// (Non-User bit). - SYNC_ADC: packed union { - raw: u1, - value: SYNC_ADC, - }, - padding: u15, + /// AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// Flexible static memory controller module clock enable + FSMCEN: u1, + padding: u31, }), - }; - }; - - pub const pwr_h7rm0455 = struct { - pub const SDLEVEL = enum(u2) { - Reset = 0x0, - V1_8 = 0x1, - V2_5 = 0x2, - V2_5_ALT = 0x3, - }; - - pub const VOS = enum(u2) { - Scale3 = 0x0, - Scale2 = 0x1, - Scale1 = 0x2, - Scale0 = 0x3, - }; - - pub const WKUPPUPD = enum(u2) { - /// No pull-up. - NoPull = 0x0, - /// Pull-up. - PullUp = 0x1, - /// Pull-down. - PullDown = 0x2, - _, - }; - - /// PWR - pub const PWR = extern struct { - /// PWR control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) - LPDS: u1, - reserved4: u3, - /// Programmable voltage detector enable - PVDE: u1, - /// Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. - PLS: u3, - /// Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. - DBP: u1, - /// Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. - FLPS: u1, - reserved14: u4, - /// System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. - SVOS: u2, - /// Peripheral voltage monitor on VDDA enable - AVDEN: u1, - /// Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. - ALS: u2, + reserved64: [4]u8, + /// APB1 peripheral clock enable register + APB1ENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable + TIM2EN: u1, + /// TIM3 clock enable + TIM3EN: u1, + /// TIM4 clock enable + TIM4EN: u1, + /// TIM5 clock enable + TIM5EN: u1, + /// TIM6 clock enable + TIM6EN: u1, + /// TIM7 clock enable + TIM7EN: u1, + /// TIM12 clock enable + TIM12EN: u1, + /// TIM13 clock enable + TIM13EN: u1, + /// TIM14 clock enable + TIM14EN: u1, + reserved11: u2, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI2 clock enable + SPI2EN: u1, + /// SPI3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// I2C3 clock enable + I2C3EN: u1, + reserved25: u1, + /// CAN 1 clock enable + CAN1EN: u1, + /// CAN 2 clock enable + CAN2EN: u1, + reserved28: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + padding: u2, + }), + /// APB2 peripheral clock enable register + APB2ENR: mmio.Mmio(packed struct(u32) { + /// TIM1 clock enable + TIM1EN: u1, + /// TIM8 clock enable + TIM8EN: u1, + reserved4: u2, + /// USART1 clock enable + USART1EN: u1, + /// USART6 clock enable + USART6EN: u1, + reserved8: u2, + /// ADC1 clock enable + ADC1EN: u1, + /// ADC2 clock enable + ADC2EN: u1, + /// ADC3 clock enable + ADC3EN: u1, + /// SDIO clock enable + SDIOEN: u1, + /// SPI1 clock enable + SPI1EN: u1, + reserved14: u1, + /// System configuration controller clock enable + SYSCFGEN: u1, + reserved16: u1, + /// TIM9 clock enable + TIM9EN: u1, + /// TIM10 clock enable + TIM10EN: u1, + /// TIM11 clock enable + TIM11EN: u1, padding: u13, }), - /// PWR control status register 1 - CSR1: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. - PVDO: u1, - reserved13: u8, - /// Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). - ACTVOSRDY: u1, - /// VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. - ACTVOS: u2, - /// Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set. - AVDO: u1, - padding: u15, + reserved80: [8]u8, + /// AHB1 peripheral clock enable in low power mode register + AHB1LPENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable during sleep mode + GPIOALPEN: u1, + /// IO port B clock enable during Sleep mode + GPIOBLPEN: u1, + /// IO port C clock enable during Sleep mode + GPIOCLPEN: u1, + /// IO port D clock enable during Sleep mode + GPIODLPEN: u1, + /// IO port E clock enable during Sleep mode + GPIOELPEN: u1, + /// IO port F clock enable during Sleep mode + GPIOFLPEN: u1, + /// IO port G clock enable during Sleep mode + GPIOGLPEN: u1, + /// IO port H clock enable during Sleep mode + GPIOHLPEN: u1, + /// IO port I clock enable during Sleep mode + GPIOILPEN: u1, + reserved12: u3, + /// CRC clock enable during Sleep mode + CRCLPEN: u1, + reserved15: u2, + /// Flash interface clock enable during Sleep mode + FLASHLPEN: u1, + /// SRAM 1interface clock enable during Sleep mode + SRAM1LPEN: u1, + /// SRAM 2 interface clock enable during Sleep mode + SRAM2LPEN: u1, + /// Backup SRAM interface clock enable during Sleep mode + BKPSRAMLPEN: u1, + reserved21: u2, + /// DMA1 clock enable during Sleep mode + DMA1LPEN: u1, + /// DMA2 clock enable during Sleep mode + DMA2LPEN: u1, + reserved25: u2, + /// Ethernet MAC clock enable during Sleep mode + ETHLPEN: u1, + /// Ethernet transmission clock enable during Sleep mode + ETHTXLPEN: u1, + /// Ethernet reception clock enable during Sleep mode + ETHRXLPEN: u1, + /// Ethernet PTP clock enable during Sleep mode + ETHPTPLPEN: u1, + /// USB OTG HS clock enable during Sleep mode + USB_OTG_HSLPEN: u1, + /// USB OTG HS ULPI clock enable during Sleep mode + USB_OTG_HSULPILPEN: u1, + padding: u1, }), - /// This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. - CR2: mmio.Mmio(packed struct(u32) { - /// Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. - BREN: u1, + /// AHB2 peripheral clock enable in low power mode register + AHB2LPENR: mmio.Mmio(packed struct(u32) { + /// Camera interface enable during Sleep mode + DCMILPEN: u1, reserved4: u3, - /// VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. - MONEN: u1, - reserved16: u11, - /// Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. - BRRDY: u1, - reserved20: u3, - /// VBAT level monitoring versus low threshold - VBATL: u1, - /// VBAT level monitoring versus high threshold - VBATH: u1, - /// Temperature level monitoring versus low threshold - TEMPL: u1, - /// Temperature level monitoring versus high threshold - TEMPH: u1, - padding: u8, + /// Cryptography modules clock enable during Sleep mode + CRYPLPEN: u1, + /// Hash modules clock enable during Sleep mode + HASHLPEN: u1, + /// Random number generator clock enable during Sleep mode + RNGLPEN: u1, + /// USB OTG FS clock enable during Sleep mode + USB_OTG_FSLPEN: u1, + padding: u24, }), - /// Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value. - CR3: mmio.Mmio(packed struct(u32) { - /// Power management unit bypass - BYPASS: u1, - /// Low drop-out regulator enable - LDOEN: u1, - /// SD converter Enable - SDEN: u1, - /// Step-down converter forced ON and in High Power MR mode - SDEXTHP: u1, - /// Step-down converter voltage output level selection - SDLEVEL: packed union { - raw: u2, - value: SDLEVEL, - }, - reserved8: u2, - /// VBAT charging enable - VBE: u1, - /// VBAT charging resistor selection - VBRS: u1, - reserved16: u6, - /// SMPS step-down converter external supply ready - SDEXTRDY: u1, - reserved24: u7, - /// VDD33USB voltage level detector enable. - USB33DEN: u1, - /// USB regulator enable. - USBREGEN: u1, - /// USB supply ready. - USB33RDY: u1, - padding: u5, + /// AHB3 peripheral clock enable in low power mode register + AHB3LPENR: mmio.Mmio(packed struct(u32) { + /// Flexible static memory controller module clock enable during Sleep mode + FSMCLPEN: u1, + padding: u31, }), - /// This register allows controlling CPU1 power. - CPUCR: mmio.Mmio(packed struct(u32) { - /// D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. - PDDS_D1: u1, - /// D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. - PDDS_D2: u1, - /// System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. - PDDS_D3: u1, - reserved5: u2, - /// STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. - STOPF: u1, - /// System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit - SBF: u1, - /// D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. - SBF_D1: u1, - /// D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. - SBF_D2: u1, - /// Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. - CSSF: u1, - reserved11: u1, - /// Keep system D3 domain in Run mode regardless of the CPU sub-systems modes - RUN_D3: u1, - padding: u20, + reserved96: [4]u8, + /// APB1 peripheral clock enable in low power mode register + APB1LPENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable during Sleep mode + TIM2LPEN: u1, + /// TIM3 clock enable during Sleep mode + TIM3LPEN: u1, + /// TIM4 clock enable during Sleep mode + TIM4LPEN: u1, + /// TIM5 clock enable during Sleep mode + TIM5LPEN: u1, + /// TIM6 clock enable during Sleep mode + TIM6LPEN: u1, + /// TIM7 clock enable during Sleep mode + TIM7LPEN: u1, + /// TIM12 clock enable during Sleep mode + TIM12LPEN: u1, + /// TIM13 clock enable during Sleep mode + TIM13LPEN: u1, + /// TIM14 clock enable during Sleep mode + TIM14LPEN: u1, + reserved11: u2, + /// Window watchdog clock enable during Sleep mode + WWDGLPEN: u1, + reserved14: u2, + /// SPI2 clock enable during Sleep mode + SPI2LPEN: u1, + /// SPI3 clock enable during Sleep mode + SPI3LPEN: u1, + reserved17: u1, + /// USART2 clock enable during Sleep mode + USART2LPEN: u1, + /// USART3 clock enable during Sleep mode + USART3LPEN: u1, + /// UART4 clock enable during Sleep mode + UART4LPEN: u1, + /// UART5 clock enable during Sleep mode + UART5LPEN: u1, + /// I2C1 clock enable during Sleep mode + I2C1LPEN: u1, + /// I2C2 clock enable during Sleep mode + I2C2LPEN: u1, + /// I2C3 clock enable during Sleep mode + I2C3LPEN: u1, + reserved25: u1, + /// CAN 1 clock enable during Sleep mode + CAN1LPEN: u1, + /// CAN 2 clock enable during Sleep mode + CAN2LPEN: u1, + reserved28: u1, + /// Power interface clock enable during Sleep mode + PWRLPEN: u1, + /// DAC interface clock enable during Sleep mode + DACLPEN: u1, + padding: u2, }), - reserved24: [4]u8, - /// This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software - D3CR: mmio.Mmio(packed struct(u32) { - reserved13: u13, - /// VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). - VOSRDY: u1, - /// Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling. - VOS: packed union { + /// APB2 peripheral clock enabled in low power mode register + APB2LPENR: mmio.Mmio(packed struct(u32) { + /// TIM1 clock enable during Sleep mode + TIM1LPEN: u1, + /// TIM8 clock enable during Sleep mode + TIM8LPEN: u1, + reserved4: u2, + /// USART1 clock enable during Sleep mode + USART1LPEN: u1, + /// USART6 clock enable during Sleep mode + USART6LPEN: u1, + reserved8: u2, + /// ADC1 clock enable during Sleep mode + ADC1LPEN: u1, + /// ADC2 clock enable during Sleep mode + ADC2LPEN: u1, + /// ADC 3 clock enable during Sleep mode + ADC3LPEN: u1, + /// SDIO clock enable during Sleep mode + SDIOLPEN: u1, + /// SPI 1 clock enable during Sleep mode + SPI1LPEN: u1, + reserved14: u1, + /// System configuration controller clock enable during Sleep mode + SYSCFGLPEN: u1, + reserved16: u1, + /// TIM9 clock enable during sleep mode + TIM9LPEN: u1, + /// TIM10 clock enable during Sleep mode + TIM10LPEN: u1, + /// TIM11 clock enable during Sleep mode + TIM11LPEN: u1, + padding: u13, + }), + reserved112: [8]u8, + /// Backup domain control register + BDCR: mmio.Mmio(packed struct(u32) { + /// External low-speed oscillator enable + LSEON: u1, + /// External low-speed oscillator ready + LSERDY: u1, + /// External low-speed oscillator bypass + LSEBYP: u1, + reserved8: u5, + /// RTC clock source selection + RTCSEL: packed union { raw: u2, - value: VOS, + value: RTCSEL, }, - padding: u16, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, }), - reserved32: [4]u8, - /// reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). - WKUPCR: mmio.Mmio(packed struct(u32) { - /// Clear Wakeup pin flag for WKUP. These bits are always read as 0. - WKUPC: u6, - padding: u26, + /// clock control & status register + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low-speed oscillator enable + LSION: u1, + /// Internal low-speed oscillator ready + LSIRDY: u1, + reserved24: u22, + /// Remove reset flag + RMVF: u1, + /// BOR reset flag + BORRSTF: u1, + /// PIN reset flag + PADRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + WDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, }), - /// reset only by system reset, not reset by wakeup from Standby mode - WKUPFR: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). - WKUPF: u1, - padding: u31, + reserved128: [8]u8, + /// spread spectrum clock generation register + SSCGR: mmio.Mmio(packed struct(u32) { + /// Modulation period + MODPER: u13, + /// Incrementation step + INCSTEP: u15, + reserved30: u2, + /// Spread Select + SPREADSEL: packed union { + raw: u1, + value: SPREADSEL, + }, + /// Spread spectrum modulation enable + SSCGEN: u1, }), - /// Reset only by system reset, not reset by wakeup from Standby mode - WKUPEPR: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. - WKUPEN: u1, - reserved8: u7, - /// Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. - WKUPP: u1, - reserved16: u7, - /// Wakeup pin pull configuration - WKUPPUPD: packed union { - raw: u2, - value: WKUPPUPD, + /// PLLI2S configuration register + PLLI2SCFGR: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// PLLI2S multiplication factor for VCO + PLLN: packed union { + raw: u9, + value: PLLN, }, - padding: u14, + reserved28: u13, + /// PLLI2S division factor for I2S clocks + PLLR: packed union { + raw: u3, + value: PLLR, + }, + padding: u1, }), }; }; - pub const rcc_f4 = struct { - pub const CECSEL = enum(u1) { - /// LSE clock is selected as HDMI-CEC clock - LSE = 0x0, - /// HSI divided by 488 clock is selected as HDMI-CEC clock - HSI_Div488 = 0x1, - }; - - pub const CKDFSDMASEL = enum(u1) { - /// CK_I2S_APB1 selected as audio clock - I2S1 = 0x0, - /// CK_I2S_APB2 selected as audio clock - I2S2 = 0x1, - }; - - pub const CKDFSDMSEL = enum(u1) { - /// APB2 clock used as Kernel clock - PCLK2 = 0x0, - /// System clock used as Kernel clock - SYS = 0x1, - }; - - pub const CLK48SEL = enum(u1) { - /// 48MHz clock from PLL is selected - PLL1_Q = 0x0, - /// 48MHz clock from PLLSAI is selected - PLLSAI1_Q = 0x1, + pub const rcc_f37 = struct { + pub const ADCPRE = enum(u2) { + /// PCLK divided by 2 + Div2 = 0x0, + /// PCLK divided by 4 + Div4 = 0x1, + /// PCLK divided by 6 + Div6 = 0x2, + /// PCLK divided by 8 + Div8 = 0x3, }; - pub const DSISEL = enum(u1) { - /// DSI-PHY used as DSI byte lane clock source (usual case) - DSI_PHY = 0x0, - /// PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode) - PLL1_R = 0x1, + pub const ADCPRES = enum(u5) { + /// PLL clock not divided + Div1 = 0x10, + /// PLL clock divided by 2 + Div2 = 0x11, + /// PLL clock divided by 4 + Div4 = 0x12, + /// PLL clock divided by 6 + Div6 = 0x13, + /// PLL clock divided by 8 + Div8 = 0x14, + /// PLL clock divided by 10 + Div10 = 0x15, + /// PLL clock divided by 12 + Div12 = 0x16, + /// PLL clock divided by 16 + Div16 = 0x17, + /// PLL clock divided by 32 + Div32 = 0x18, + /// PLL clock divided by 64 + Div64 = 0x19, + /// PLL clock divided by 128 + Div128 = 0x1a, + /// PLL clock divided by 256 + Div256 = 0x1b, + _, }; - pub const FMPI2CSEL = enum(u2) { - /// APB clock selected as I2C clock - PCLK1 = 0x0, - /// System clock selected as I2C clock - SYS = 0x1, - /// HSI clock selected as I2C clock - HSI = 0x2, - _, + pub const CECSW = enum(u1) { + /// HSI clock divided by 244 selected as CEC clock source + HSI_DIV_244 = 0x0, + /// LSE clock selected as CEC clock source + LSE = 0x1, }; pub const HPRE = enum(u4) { @@ -385974,1060 +370601,282 @@ pub const types = struct { _, }; - pub const I2S1SRC = enum(u2) { - /// I2Sx clock frequency = f(PLLI2S_R) - PLLI2SR = 0x0, - /// I2Sx clock frequency = I2S_CKIN Alternate function input frequency - I2S_CKIN = 0x1, - /// I2Sx clock frequency = f(PLL_R) - PLLR = 0x2, - /// I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) - HSI_HSE = 0x3, + pub const ICSW = enum(u1) { + /// HSI clock selected as I2C clock source + HSI = 0x0, + /// SYSCLK clock selected as I2C clock source + SYS = 0x1, }; - pub const I2SSRC_CFGR = enum(u1) { - /// PLLI2S clock used as I2S clock source - PLLI2S = 0x0, + pub const ISSRC = enum(u1) { + /// System clock used as I2S clock source + SYS = 0x0, /// External clock mapped on the I2S_CKIN pin used as I2S clock source CKIN = 0x1, }; - pub const I2SSRC_DCKCFGR = enum(u2) { - /// clock frequency = f(PLLI2S_R) - PLLI2S_R = 0x0, - /// clock frequency = I2S_CKIN Alternate function input frequency - I2S_CKIN = 0x1, - /// clock frequency = f(PLL_R) - PLL_R = 0x2, - /// clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) - HSI_HSE = 0x3, + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium high driving capability + MediumHigh = 0x1, + /// Medium low driving capability + MediumLow = 0x2, + /// High driving capability + High = 0x3, }; - pub const LPTIMSEL = enum(u2) { - /// APB1 clock (PCLK1) selected as LPTILM1 clock - PCLK1 = 0x0, - /// LSI clock is selected as LPTILM1 clock - LSI = 0x1, - /// HSI clock is selected as LPTILM1 clock - HSI = 0x2, - /// LSE clock is selected as LPTILM1 clock + pub const MCOSEL = enum(u3) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// Internal low speed (LSI) oscillator clock selected + LSI = 0x2, + /// External low speed (LSE) oscillator clock selected LSE = 0x3, + /// System clock selected + SYS = 0x4, + /// Internal RC 8 MHz (HSI) oscillator clock selected + HSI = 0x5, + /// External 4-32 MHz (HSE) oscillator clock selected + HSE = 0x6, + /// PLL clock divided by 2 + PLL_DIV_2 = 0x7, + _, }; - pub const LSEMOD = enum(u1) { - /// LSE oscillator low power mode selection - Low = 0x0, - /// LSE oscillator high drive mode selection - High = 0x1, + pub const PLLMUL = enum(u4) { + /// PLL input clock x2 + Mul2 = 0x0, + /// PLL input clock x3 + Mul3 = 0x1, + /// PLL input clock x4 + Mul4 = 0x2, + /// PLL input clock x5 + Mul5 = 0x3, + /// PLL input clock x6 + Mul6 = 0x4, + /// PLL input clock x7 + Mul7 = 0x5, + /// PLL input clock x8 + Mul8 = 0x6, + /// PLL input clock x9 + Mul9 = 0x7, + /// PLL input clock x10 + Mul10 = 0x8, + /// PLL input clock x11 + Mul11 = 0x9, + /// PLL input clock x12 + Mul12 = 0xa, + /// PLL input clock x13 + Mul13 = 0xb, + /// PLL input clock x14 + Mul14 = 0xc, + /// PLL input clock x15 + Mul15 = 0xd, + /// PLL input clock x16 + Mul16 = 0xe, + _, }; - pub const MCO1SEL = enum(u2) { - /// HSI clock selected - HSI = 0x0, - /// LSE oscillator selected - LSE = 0x1, - /// HSE oscillator clock selected - HSE = 0x2, - /// PLL clock selected - PLL = 0x3, + pub const PLLSRC = enum(u1) { + /// HSI divided by 2 selected as PLL input clock + HSI_Div2 = 0x0, + /// HSE divided by PREDIV selected as PLL input clock + HSE_Div_PREDIV = 0x1, }; - pub const MCO2SEL = enum(u2) { - /// System clock (SYSCLK) selected - SYS = 0x0, - /// PLLI2S clock selected - PLLI2S = 0x1, - /// HSE oscillator clock selected - HSE = 0x2, - /// PLL clock selected - PLL = 0x3, + pub const PLLXTPRE = enum(u1) { + /// HSE clock not divided + Div1 = 0x0, + /// HSE clock divided by 2 + Div2 = 0x1, }; - pub const MCOPRE = enum(u3) { - /// No division + pub const PPRE = enum(u3) { + /// HCLK not divided Div1 = 0x0, - /// Division by 2 + /// HCLK divided by 2 Div2 = 0x4, - /// Division by 3 - Div3 = 0x5, - /// Division by 4 - Div4 = 0x6, - /// Division by 5 - Div5 = 0x7, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, _, }; - pub const PLLDIVR = enum(u5) { - /// PLLSAIDIVQ = /1 + pub const PREDIV = enum(u4) { + /// PREDIV input clock not divided Div1 = 0x0, - /// PLLSAIDIVQ = /2 + /// PREDIV input clock divided by 2 Div2 = 0x1, - /// PLLSAIDIVQ = /3 + /// PREDIV input clock divided by 3 Div3 = 0x2, - /// PLLSAIDIVQ = /4 + /// PREDIV input clock divided by 4 Div4 = 0x3, - /// PLLSAIDIVQ = /5 + /// PREDIV input clock divided by 5 Div5 = 0x4, - /// PLLSAIDIVQ = /6 + /// PREDIV input clock divided by 6 Div6 = 0x5, - /// PLLSAIDIVQ = /7 + /// PREDIV input clock divided by 7 Div7 = 0x6, - /// PLLSAIDIVQ = /8 + /// PREDIV input clock divided by 8 Div8 = 0x7, - /// PLLSAIDIVQ = /9 + /// PREDIV input clock divided by 9 Div9 = 0x8, - /// PLLSAIDIVQ = /10 + /// PREDIV input clock divided by 10 Div10 = 0x9, - /// PLLSAIDIVQ = /11 + /// PREDIV input clock divided by 11 Div11 = 0xa, - /// PLLSAIDIVQ = /12 + /// PREDIV input clock divided by 12 Div12 = 0xb, - /// PLLSAIDIVQ = /13 + /// PREDIV input clock divided by 13 Div13 = 0xc, - /// PLLSAIDIVQ = /14 + /// PREDIV input clock divided by 14 Div14 = 0xd, - /// PLLSAIDIVQ = /15 + /// PREDIV input clock divided by 15 Div15 = 0xe, - /// PLLSAIDIVQ = /16 + /// PREDIV input clock divided by 16 Div16 = 0xf, - /// PLLSAIDIVQ = /17 - Div17 = 0x10, - /// PLLSAIDIVQ = /18 - Div18 = 0x11, - /// PLLSAIDIVQ = /19 - Div19 = 0x12, - /// PLLSAIDIVQ = /20 - Div20 = 0x13, - /// PLLSAIDIVQ = /21 - Div21 = 0x14, - /// PLLSAIDIVQ = /22 - Div22 = 0x15, - /// PLLSAIDIVQ = /23 - Div23 = 0x16, - /// PLLSAIDIVQ = /24 - Div24 = 0x17, - /// PLLSAIDIVQ = /25 - Div25 = 0x18, - /// PLLSAIDIVQ = /26 - Div26 = 0x19, - /// PLLSAIDIVQ = /27 - Div27 = 0x1a, - /// PLLSAIDIVQ = /28 - Div28 = 0x1b, - /// PLLSAIDIVQ = /29 - Div29 = 0x1c, - /// PLLSAIDIVQ = /30 - Div30 = 0x1d, - /// PLLSAIDIVQ = /31 - Div31 = 0x1e, - /// PLLSAIDIVQ = /32 - Div32 = 0x1f, }; - pub const PLLI2SDIVQ = enum(u5) { - /// PLLI2SDIVQ = /1 - Div1 = 0x0, - /// PLLI2SDIVQ = /2 - Div2 = 0x1, - /// PLLI2SDIVQ = /3 - Div3 = 0x2, - /// PLLI2SDIVQ = /4 - Div4 = 0x3, - /// PLLI2SDIVQ = /5 - Div5 = 0x4, - /// PLLI2SDIVQ = /6 - Div6 = 0x5, - /// PLLI2SDIVQ = /7 - Div7 = 0x6, - /// PLLI2SDIVQ = /8 - Div8 = 0x7, - /// PLLI2SDIVQ = /9 - Div9 = 0x8, - /// PLLI2SDIVQ = /10 - Div10 = 0x9, - /// PLLI2SDIVQ = /11 - Div11 = 0xa, - /// PLLI2SDIVQ = /12 - Div12 = 0xb, - /// PLLI2SDIVQ = /13 - Div13 = 0xc, - /// PLLI2SDIVQ = /14 - Div14 = 0xd, - /// PLLI2SDIVQ = /15 - Div15 = 0xe, - /// PLLI2SDIVQ = /16 - Div16 = 0xf, - /// PLLI2SDIVQ = /17 - Div17 = 0x10, - /// PLLI2SDIVQ = /18 - Div18 = 0x11, - /// PLLI2SDIVQ = /19 - Div19 = 0x12, - /// PLLI2SDIVQ = /20 - Div20 = 0x13, - /// PLLI2SDIVQ = /21 - Div21 = 0x14, - /// PLLI2SDIVQ = /22 - Div22 = 0x15, - /// PLLI2SDIVQ = /23 - Div23 = 0x16, - /// PLLI2SDIVQ = /24 - Div24 = 0x17, - /// PLLI2SDIVQ = /25 - Div25 = 0x18, - /// PLLI2SDIVQ = /26 - Div26 = 0x19, - /// PLLI2SDIVQ = /27 - Div27 = 0x1a, - /// PLLI2SDIVQ = /28 - Div28 = 0x1b, - /// PLLI2SDIVQ = /29 - Div29 = 0x1c, - /// PLLI2SDIVQ = /30 - Div30 = 0x1d, - /// PLLI2SDIVQ = /31 - Div31 = 0x1e, - /// PLLI2SDIVQ = /32 - Div32 = 0x1f, + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, }; - pub const PLLI2SDIVR = enum(u5) { - /// PLLI2SDIVQ = /1 - Div1 = 0x0, - /// PLLI2SDIVQ = /2 - Div2 = 0x1, - /// PLLI2SDIVQ = /3 - Div3 = 0x2, - /// PLLI2SDIVQ = /4 - Div4 = 0x3, - /// PLLI2SDIVQ = /5 - Div5 = 0x4, - /// PLLI2SDIVQ = /6 - Div6 = 0x5, - /// PLLI2SDIVQ = /7 - Div7 = 0x6, - /// PLLI2SDIVQ = /8 - Div8 = 0x7, - /// PLLI2SDIVQ = /9 - Div9 = 0x8, - /// PLLI2SDIVQ = /10 - Div10 = 0x9, - /// PLLI2SDIVQ = /11 - Div11 = 0xa, - /// PLLI2SDIVQ = /12 - Div12 = 0xb, - /// PLLI2SDIVQ = /13 - Div13 = 0xc, - /// PLLI2SDIVQ = /14 - Div14 = 0xd, - /// PLLI2SDIVQ = /15 - Div15 = 0xe, - /// PLLI2SDIVQ = /16 - Div16 = 0xf, - /// PLLI2SDIVQ = /17 - Div17 = 0x10, - /// PLLI2SDIVQ = /18 - Div18 = 0x11, - /// PLLI2SDIVQ = /19 - Div19 = 0x12, - /// PLLI2SDIVQ = /20 - Div20 = 0x13, - /// PLLI2SDIVQ = /21 - Div21 = 0x14, - /// PLLI2SDIVQ = /22 - Div22 = 0x15, - /// PLLI2SDIVQ = /23 - Div23 = 0x16, - /// PLLI2SDIVQ = /24 - Div24 = 0x17, - /// PLLI2SDIVQ = /25 - Div25 = 0x18, - /// PLLI2SDIVQ = /26 - Div26 = 0x19, - /// PLLI2SDIVQ = /27 - Div27 = 0x1a, - /// PLLI2SDIVQ = /28 - Div28 = 0x1b, - /// PLLI2SDIVQ = /29 - Div29 = 0x1c, - /// PLLI2SDIVQ = /30 - Div30 = 0x1d, - /// PLLI2SDIVQ = /31 - Div31 = 0x1e, - /// PLLI2SDIVQ = /32 - Div32 = 0x1f, + pub const SDPRE = enum(u5) { + /// SYSCLK divided by 2 + Div2 = 0x0, + /// SYSCLK divided by 4 + Div4 = 0x11, + /// SYSCLK divided by 6 + Div6 = 0x12, + /// SYSCLK divided by 8 + Div8 = 0x13, + /// SYSCLK divided by 10 + Div10 = 0x14, + /// SYSCLK divided by 12 + Div12 = 0x15, + /// SYSCLK divided by 14 + Div14 = 0x16, + /// SYSCLK divided by 16 + Div16 = 0x17, + /// SYSCLK divided by 20 + Div20 = 0x18, + /// SYSCLK divided by 24 + Div24 = 0x19, + /// SYSCLK divided by 28 + Div28 = 0x1a, + /// SYSCLK divided by 32 + Div32 = 0x1b, + /// SYSCLK divided by 36 + Div36 = 0x1c, + /// SYSCLK divided by 40 + Div40 = 0x1d, + /// SYSCLK divided by 44 + Div44 = 0x1e, + /// SYSCLK divided by 48 + Div48 = 0x1f, + _, }; - pub const PLLI2SSRC = enum(u1) { - /// HSE or HSI depending on PLLSRC of PLLCFGR - HSE_HSI = 0x0, - /// External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry - External = 0x1, + pub const SW = enum(u2) { + /// HSI oscillator used as system clock + HSI = 0x0, + /// HSE oscillator used as system clock + HSE = 0x1, + /// PLL used as system clock + PLL1_P = 0x2, + _, }; - pub const PLLM = enum(u6) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - Div16 = 0x10, - Div17 = 0x11, - Div18 = 0x12, - Div19 = 0x13, - Div20 = 0x14, - Div21 = 0x15, - Div22 = 0x16, - Div23 = 0x17, - Div24 = 0x18, - Div25 = 0x19, - Div26 = 0x1a, - Div27 = 0x1b, - Div28 = 0x1c, - Div29 = 0x1d, - Div30 = 0x1e, - Div31 = 0x1f, - Div32 = 0x20, - Div33 = 0x21, - Div34 = 0x22, - Div35 = 0x23, - Div36 = 0x24, - Div37 = 0x25, - Div38 = 0x26, - Div39 = 0x27, - Div40 = 0x28, - Div41 = 0x29, - Div42 = 0x2a, - Div43 = 0x2b, - Div44 = 0x2c, - Div45 = 0x2d, - Div46 = 0x2e, - Div47 = 0x2f, - Div48 = 0x30, - Div49 = 0x31, - Div50 = 0x32, - Div51 = 0x33, - Div52 = 0x34, - Div53 = 0x35, - Div54 = 0x36, - Div55 = 0x37, - Div56 = 0x38, - Div57 = 0x39, - Div58 = 0x3a, - Div59 = 0x3b, - Div60 = 0x3c, - Div61 = 0x3d, - Div62 = 0x3e, - Div63 = 0x3f, - _, + pub const TIM2SW = enum(u1) { + /// PCLK2 clock (doubled frequency when prescaled) + PCLK1_TIM = 0x0, + /// PLL vco output (running up to 144 MHz) + PLL1_P = 0x1, }; - pub const PLLN = enum(u9) { - Mul50 = 0x32, - Mul51 = 0x33, - Mul52 = 0x34, - Mul53 = 0x35, - Mul54 = 0x36, - Mul55 = 0x37, - Mul56 = 0x38, - Mul57 = 0x39, - Mul58 = 0x3a, - Mul59 = 0x3b, - Mul60 = 0x3c, - Mul61 = 0x3d, - Mul62 = 0x3e, - Mul63 = 0x3f, - Mul64 = 0x40, - Mul65 = 0x41, - Mul66 = 0x42, - Mul67 = 0x43, - Mul68 = 0x44, - Mul69 = 0x45, - Mul70 = 0x46, - Mul71 = 0x47, - Mul72 = 0x48, - Mul73 = 0x49, - Mul74 = 0x4a, - Mul75 = 0x4b, - Mul76 = 0x4c, - Mul77 = 0x4d, - Mul78 = 0x4e, - Mul79 = 0x4f, - Mul80 = 0x50, - Mul81 = 0x51, - Mul82 = 0x52, - Mul83 = 0x53, - Mul84 = 0x54, - Mul85 = 0x55, - Mul86 = 0x56, - Mul87 = 0x57, - Mul88 = 0x58, - Mul89 = 0x59, - Mul90 = 0x5a, - Mul91 = 0x5b, - Mul92 = 0x5c, - Mul93 = 0x5d, - Mul94 = 0x5e, - Mul95 = 0x5f, - Mul96 = 0x60, - Mul97 = 0x61, - Mul98 = 0x62, - Mul99 = 0x63, - Mul100 = 0x64, - Mul101 = 0x65, - Mul102 = 0x66, - Mul103 = 0x67, - Mul104 = 0x68, - Mul105 = 0x69, - Mul106 = 0x6a, - Mul107 = 0x6b, - Mul108 = 0x6c, - Mul109 = 0x6d, - Mul110 = 0x6e, - Mul111 = 0x6f, - Mul112 = 0x70, - Mul113 = 0x71, - Mul114 = 0x72, - Mul115 = 0x73, - Mul116 = 0x74, - Mul117 = 0x75, - Mul118 = 0x76, - Mul119 = 0x77, - Mul120 = 0x78, - Mul121 = 0x79, - Mul122 = 0x7a, - Mul123 = 0x7b, - Mul124 = 0x7c, - Mul125 = 0x7d, - Mul126 = 0x7e, - Mul127 = 0x7f, - Mul128 = 0x80, - Mul129 = 0x81, - Mul130 = 0x82, - Mul131 = 0x83, - Mul132 = 0x84, - Mul133 = 0x85, - Mul134 = 0x86, - Mul135 = 0x87, - Mul136 = 0x88, - Mul137 = 0x89, - Mul138 = 0x8a, - Mul139 = 0x8b, - Mul140 = 0x8c, - Mul141 = 0x8d, - Mul142 = 0x8e, - Mul143 = 0x8f, - Mul144 = 0x90, - Mul145 = 0x91, - Mul146 = 0x92, - Mul147 = 0x93, - Mul148 = 0x94, - Mul149 = 0x95, - Mul150 = 0x96, - Mul151 = 0x97, - Mul152 = 0x98, - Mul153 = 0x99, - Mul154 = 0x9a, - Mul155 = 0x9b, - Mul156 = 0x9c, - Mul157 = 0x9d, - Mul158 = 0x9e, - Mul159 = 0x9f, - Mul160 = 0xa0, - Mul161 = 0xa1, - Mul162 = 0xa2, - Mul163 = 0xa3, - Mul164 = 0xa4, - Mul165 = 0xa5, - Mul166 = 0xa6, - Mul167 = 0xa7, - Mul168 = 0xa8, - Mul169 = 0xa9, - Mul170 = 0xaa, - Mul171 = 0xab, - Mul172 = 0xac, - Mul173 = 0xad, - Mul174 = 0xae, - Mul175 = 0xaf, - Mul176 = 0xb0, - Mul177 = 0xb1, - Mul178 = 0xb2, - Mul179 = 0xb3, - Mul180 = 0xb4, - Mul181 = 0xb5, - Mul182 = 0xb6, - Mul183 = 0xb7, - Mul184 = 0xb8, - Mul185 = 0xb9, - Mul186 = 0xba, - Mul187 = 0xbb, - Mul188 = 0xbc, - Mul189 = 0xbd, - Mul190 = 0xbe, - Mul191 = 0xbf, - Mul192 = 0xc0, - Mul193 = 0xc1, - Mul194 = 0xc2, - Mul195 = 0xc3, - Mul196 = 0xc4, - Mul197 = 0xc5, - Mul198 = 0xc6, - Mul199 = 0xc7, - Mul200 = 0xc8, - Mul201 = 0xc9, - Mul202 = 0xca, - Mul203 = 0xcb, - Mul204 = 0xcc, - Mul205 = 0xcd, - Mul206 = 0xce, - Mul207 = 0xcf, - Mul208 = 0xd0, - Mul209 = 0xd1, - Mul210 = 0xd2, - Mul211 = 0xd3, - Mul212 = 0xd4, - Mul213 = 0xd5, - Mul214 = 0xd6, - Mul215 = 0xd7, - Mul216 = 0xd8, - Mul217 = 0xd9, - Mul218 = 0xda, - Mul219 = 0xdb, - Mul220 = 0xdc, - Mul221 = 0xdd, - Mul222 = 0xde, - Mul223 = 0xdf, - Mul224 = 0xe0, - Mul225 = 0xe1, - Mul226 = 0xe2, - Mul227 = 0xe3, - Mul228 = 0xe4, - Mul229 = 0xe5, - Mul230 = 0xe6, - Mul231 = 0xe7, - Mul232 = 0xe8, - Mul233 = 0xe9, - Mul234 = 0xea, - Mul235 = 0xeb, - Mul236 = 0xec, - Mul237 = 0xed, - Mul238 = 0xee, - Mul239 = 0xef, - Mul240 = 0xf0, - Mul241 = 0xf1, - Mul242 = 0xf2, - Mul243 = 0xf3, - Mul244 = 0xf4, - Mul245 = 0xf5, - Mul246 = 0xf6, - Mul247 = 0xf7, - Mul248 = 0xf8, - Mul249 = 0xf9, - Mul250 = 0xfa, - Mul251 = 0xfb, - Mul252 = 0xfc, - Mul253 = 0xfd, - Mul254 = 0xfe, - Mul255 = 0xff, - Mul256 = 0x100, - Mul257 = 0x101, - Mul258 = 0x102, - Mul259 = 0x103, - Mul260 = 0x104, - Mul261 = 0x105, - Mul262 = 0x106, - Mul263 = 0x107, - Mul264 = 0x108, - Mul265 = 0x109, - Mul266 = 0x10a, - Mul267 = 0x10b, - Mul268 = 0x10c, - Mul269 = 0x10d, - Mul270 = 0x10e, - Mul271 = 0x10f, - Mul272 = 0x110, - Mul273 = 0x111, - Mul274 = 0x112, - Mul275 = 0x113, - Mul276 = 0x114, - Mul277 = 0x115, - Mul278 = 0x116, - Mul279 = 0x117, - Mul280 = 0x118, - Mul281 = 0x119, - Mul282 = 0x11a, - Mul283 = 0x11b, - Mul284 = 0x11c, - Mul285 = 0x11d, - Mul286 = 0x11e, - Mul287 = 0x11f, - Mul288 = 0x120, - Mul289 = 0x121, - Mul290 = 0x122, - Mul291 = 0x123, - Mul292 = 0x124, - Mul293 = 0x125, - Mul294 = 0x126, - Mul295 = 0x127, - Mul296 = 0x128, - Mul297 = 0x129, - Mul298 = 0x12a, - Mul299 = 0x12b, - Mul300 = 0x12c, - Mul301 = 0x12d, - Mul302 = 0x12e, - Mul303 = 0x12f, - Mul304 = 0x130, - Mul305 = 0x131, - Mul306 = 0x132, - Mul307 = 0x133, - Mul308 = 0x134, - Mul309 = 0x135, - Mul310 = 0x136, - Mul311 = 0x137, - Mul312 = 0x138, - Mul313 = 0x139, - Mul314 = 0x13a, - Mul315 = 0x13b, - Mul316 = 0x13c, - Mul317 = 0x13d, - Mul318 = 0x13e, - Mul319 = 0x13f, - Mul320 = 0x140, - Mul321 = 0x141, - Mul322 = 0x142, - Mul323 = 0x143, - Mul324 = 0x144, - Mul325 = 0x145, - Mul326 = 0x146, - Mul327 = 0x147, - Mul328 = 0x148, - Mul329 = 0x149, - Mul330 = 0x14a, - Mul331 = 0x14b, - Mul332 = 0x14c, - Mul333 = 0x14d, - Mul334 = 0x14e, - Mul335 = 0x14f, - Mul336 = 0x150, - Mul337 = 0x151, - Mul338 = 0x152, - Mul339 = 0x153, - Mul340 = 0x154, - Mul341 = 0x155, - Mul342 = 0x156, - Mul343 = 0x157, - Mul344 = 0x158, - Mul345 = 0x159, - Mul346 = 0x15a, - Mul347 = 0x15b, - Mul348 = 0x15c, - Mul349 = 0x15d, - Mul350 = 0x15e, - Mul351 = 0x15f, - Mul352 = 0x160, - Mul353 = 0x161, - Mul354 = 0x162, - Mul355 = 0x163, - Mul356 = 0x164, - Mul357 = 0x165, - Mul358 = 0x166, - Mul359 = 0x167, - Mul360 = 0x168, - Mul361 = 0x169, - Mul362 = 0x16a, - Mul363 = 0x16b, - Mul364 = 0x16c, - Mul365 = 0x16d, - Mul366 = 0x16e, - Mul367 = 0x16f, - Mul368 = 0x170, - Mul369 = 0x171, - Mul370 = 0x172, - Mul371 = 0x173, - Mul372 = 0x174, - Mul373 = 0x175, - Mul374 = 0x176, - Mul375 = 0x177, - Mul376 = 0x178, - Mul377 = 0x179, - Mul378 = 0x17a, - Mul379 = 0x17b, - Mul380 = 0x17c, - Mul381 = 0x17d, - Mul382 = 0x17e, - Mul383 = 0x17f, - Mul384 = 0x180, - Mul385 = 0x181, - Mul386 = 0x182, - Mul387 = 0x183, - Mul388 = 0x184, - Mul389 = 0x185, - Mul390 = 0x186, - Mul391 = 0x187, - Mul392 = 0x188, - Mul393 = 0x189, - Mul394 = 0x18a, - Mul395 = 0x18b, - Mul396 = 0x18c, - Mul397 = 0x18d, - Mul398 = 0x18e, - Mul399 = 0x18f, - Mul400 = 0x190, - Mul401 = 0x191, - Mul402 = 0x192, - Mul403 = 0x193, - Mul404 = 0x194, - Mul405 = 0x195, - Mul406 = 0x196, - Mul407 = 0x197, - Mul408 = 0x198, - Mul409 = 0x199, - Mul410 = 0x19a, - Mul411 = 0x19b, - Mul412 = 0x19c, - Mul413 = 0x19d, - Mul414 = 0x19e, - Mul415 = 0x19f, - Mul416 = 0x1a0, - Mul417 = 0x1a1, - Mul418 = 0x1a2, - Mul419 = 0x1a3, - Mul420 = 0x1a4, - Mul421 = 0x1a5, - Mul422 = 0x1a6, - Mul423 = 0x1a7, - Mul424 = 0x1a8, - Mul425 = 0x1a9, - Mul426 = 0x1aa, - Mul427 = 0x1ab, - Mul428 = 0x1ac, - Mul429 = 0x1ad, - Mul430 = 0x1ae, - Mul431 = 0x1af, - Mul432 = 0x1b0, - _, + pub const TIMSW = enum(u1) { + /// PCLK2 clock (doubled frequency when prescaled) + PCLK2_TIM = 0x0, + /// PLL vco output (running up to 144 MHz) + PLL1_P = 0x1, }; - pub const PLLP = enum(u2) { - /// PLLP=2 - Div2 = 0x0, - /// PLLP=4 - Div4 = 0x1, - /// PLLP=6 - Div6 = 0x2, - /// PLLP=8 - Div8 = 0x3, + pub const USART1SW = enum(u2) { + /// PCLK selected as USART clock source + PCLK2 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const PLLQ = enum(u4) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - _, + pub const USARTSW = enum(u2) { + /// PCLK selected as USART clock source + PCLK1 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const PLLR = enum(u3) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - _, - }; - - pub const PLLSAIDIVQ = enum(u5) { - /// PLLSAIDIVQ = /1 - Div1 = 0x0, - /// PLLSAIDIVQ = /2 - Div2 = 0x1, - /// PLLSAIDIVQ = /3 - Div3 = 0x2, - /// PLLSAIDIVQ = /4 - Div4 = 0x3, - /// PLLSAIDIVQ = /5 - Div5 = 0x4, - /// PLLSAIDIVQ = /6 - Div6 = 0x5, - /// PLLSAIDIVQ = /7 - Div7 = 0x6, - /// PLLSAIDIVQ = /8 - Div8 = 0x7, - /// PLLSAIDIVQ = /9 - Div9 = 0x8, - /// PLLSAIDIVQ = /10 - Div10 = 0x9, - /// PLLSAIDIVQ = /11 - Div11 = 0xa, - /// PLLSAIDIVQ = /12 - Div12 = 0xb, - /// PLLSAIDIVQ = /13 - Div13 = 0xc, - /// PLLSAIDIVQ = /14 - Div14 = 0xd, - /// PLLSAIDIVQ = /15 - Div15 = 0xe, - /// PLLSAIDIVQ = /16 - Div16 = 0xf, - /// PLLSAIDIVQ = /17 - Div17 = 0x10, - /// PLLSAIDIVQ = /18 - Div18 = 0x11, - /// PLLSAIDIVQ = /19 - Div19 = 0x12, - /// PLLSAIDIVQ = /20 - Div20 = 0x13, - /// PLLSAIDIVQ = /21 - Div21 = 0x14, - /// PLLSAIDIVQ = /22 - Div22 = 0x15, - /// PLLSAIDIVQ = /23 - Div23 = 0x16, - /// PLLSAIDIVQ = /24 - Div24 = 0x17, - /// PLLSAIDIVQ = /25 - Div25 = 0x18, - /// PLLSAIDIVQ = /26 - Div26 = 0x19, - /// PLLSAIDIVQ = /27 - Div27 = 0x1a, - /// PLLSAIDIVQ = /28 - Div28 = 0x1b, - /// PLLSAIDIVQ = /29 - Div29 = 0x1c, - /// PLLSAIDIVQ = /30 - Div30 = 0x1d, - /// PLLSAIDIVQ = /31 - Div31 = 0x1e, - /// PLLSAIDIVQ = /32 - Div32 = 0x1f, - }; - - pub const PLLSAIDIVR = enum(u2) { - /// PLLSAIDIVR = /2 - Div2 = 0x0, - /// PLLSAIDIVR = /4 - Div4 = 0x1, - /// PLLSAIDIVR = /8 - Div8 = 0x2, - /// PLLSAIDIVR = /16 - Div16 = 0x3, - }; - - pub const PLLSRC = enum(u1) { - /// HSI clock selected as PLL and PLLI2S clock entry - HSI = 0x0, - /// HSE oscillator clock selected as PLL and PLLI2S clock entry - HSE = 0x1, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, - }; - - pub const SAI1SRC = enum(u2) { - /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - PLLSAI = 0x0, - /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - PLLI2S = 0x1, - /// SAI1 clock frequency = f(PLL_R) - PLLR = 0x2, - /// I2S_CKIN Alternate function input frequency - I2S_CKIN = 0x3, - }; - - pub const SAI2SRC = enum(u2) { - /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - PLLSAI = 0x0, - /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - PLLI2S = 0x1, - /// SAI2 clock frequency = f(PLL_R) - PLLR = 0x2, - /// SAI2 clock frequency = Alternate function input frequency - HSI_HSE = 0x3, - }; - - pub const SAIASRC = enum(u2) { - /// SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - PLLSAI = 0x0, - /// SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - PLLI2S = 0x1, - /// SAI1-A clock frequency = Alternate function input frequency - I2S_CKIN = 0x2, - _, - }; - - pub const SAIBSRC = enum(u2) { - /// SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - PLLSAI = 0x0, - /// SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - PLLI2S = 0x1, - /// SAI1-B clock frequency = Alternate function input frequency - I2S_CKIN = 0x2, - _, - }; - - pub const SDIOSEL = enum(u1) { - /// 48 MHz clock is selected as SD clock - CLK48 = 0x0, - /// System clock is selected as SD clock - SYS = 0x1, - }; - - pub const SPDIFRXSEL = enum(u1) { - /// SPDIF-Rx clock from PLL is selected - PLL1_R = 0x0, - /// SPDIF-Rx clock from PLLI2S is selected - PLLI2S1_P = 0x1, - }; - - pub const SPREADSEL = enum(u1) { - /// Center spread - Center = 0x0, - /// Down spread - Down = 0x1, - }; - - pub const SW = enum(u2) { - /// HSI oscillator used as system clock - HSI = 0x0, - /// HSE oscillator used as system clock - HSE = 0x1, - /// PLL used as system clock - PLL1_P = 0x2, - _, - }; - - pub const TIMPRE = enum(u1) { - /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx - Mul2 = 0x0, - /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx - Mul4 = 0x1, + pub const USBPRE = enum(u1) { + /// PLL clock is divided by 1.5 + Div1_5 = 0x0, + /// PLL clock is not divided + Div1 = 0x1, }; /// Reset and clock control pub const RCC = extern struct { - /// clock control register + /// Clock control register CR: mmio.Mmio(packed struct(u32) { - /// Internal high-speed clock enable + /// Internal High Speed clock enable HSION: u1, - /// Internal high-speed clock ready flag + /// Internal High Speed clock ready flag HSIRDY: u1, reserved3: u1, - /// Internal high-speed clock trimming + /// Internal High Speed clock trimming HSITRIM: u5, - /// Internal high-speed clock calibration + /// Internal High Speed clock Calibration HSICAL: u8, - /// HSE clock enable + /// External High Speed clock enable HSEON: u1, - /// HSE clock ready flag + /// External High Speed clock ready flag HSERDY: u1, - /// HSE clock bypass + /// External High Speed clock Bypass HSEBYP: u1, - /// Clock security system enable + /// Clock Security System enable CSSON: u1, reserved24: u4, - /// Main PLL (PLL) enable + /// PLL enable PLLON: u1, - /// Main PLL (PLL) clock ready flag + /// PLL clock ready flag PLLRDY: u1, - /// PLLI2S enable - PLLI2SON: u1, - /// PLLI2S clock ready flag - PLLI2SRDY: u1, - /// PLLSAI enable - PLLSAION: u1, - /// PLLSAI clock ready flag - PLLSAIRDY: u1, - padding: u2, - }), - /// PLL configuration register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - PLLM: packed union { - raw: u6, - value: PLLM, - }, - /// Main PLL (PLL) multiplication factor for VCO - PLLN: packed union { - raw: u9, - value: PLLN, - }, - reserved16: u1, - /// Main PLL (PLL) division factor for main system clock - PLLP: packed union { - raw: u2, - value: PLLP, - }, - reserved22: u4, - /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - PLLSRC: packed union { - raw: u1, - value: PLLSRC, - }, - reserved24: u1, - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - PLLQ: packed union { - raw: u4, - value: PLLQ, - }, - /// PLL division factor for I2S and System clocks - PLLR: packed union { - raw: u3, - value: PLLR, - }, - padding: u1, + padding: u6, }), - /// clock configuration register + /// Clock configuration register (RCC_CFGR) CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch + /// System clock Switch SW: packed union { raw: u2, value: SW, }, - /// System clock switch status + /// System Clock Switch Status SWS: packed union { raw: u2, value: SW, @@ -387037,702 +370886,324 @@ pub const types = struct { raw: u4, value: HPRE, }, - /// MCO output enable - MCO1EN: u1, - /// MCO output enable - MCO2EN: u1, /// APB Low speed prescaler (APB1) PPRE1: packed union { raw: u3, value: PPRE, }, - /// APB high-speed prescaler (APB2) + /// APB high speed prescaler (APB2) PPRE2: packed union { raw: u3, value: PPRE, }, - /// HSE division factor for RTC clock - RTCPRE: u5, - /// Microcontroller clock output 1 - MCO1SEL: packed union { + /// ADC prescaler + ADCPRE: packed union { raw: u2, - value: MCO1SEL, + value: ADCPRE, }, - /// I2S clock selection - I2SSRC: packed union { + /// PLL entry clock source + PLLSRC: packed union { raw: u1, - value: I2SSRC_CFGR, + value: PLLSRC, }, - /// MCO1 prescaler - MCO1PRE: packed union { - raw: u3, - value: MCOPRE, + /// HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products. + PLLXTPRE: packed union { + raw: u1, + value: PLLXTPRE, }, - /// MCO2 prescaler - MCO2PRE: packed union { + /// PLL Multiplication Factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, + }, + /// USB prescaler + USBPRE: packed union { + raw: u1, + value: USBPRE, + }, + /// I2S external clock source selection + I2SSRC: packed union { + raw: u1, + value: ISSRC, + }, + /// Microcontroller clock output + MCOSEL: packed union { raw: u3, - value: MCOPRE, + value: MCOSEL, }, - /// Microcontroller clock output 2 - MCO2SEL: packed union { - raw: u2, - value: MCO2SEL, + /// SDADC prescaler + SDPRE: packed union { + raw: u5, + value: SDPRE, }, }), - /// clock interrupt register + /// Clock interrupt register (RCC_CIR) CIR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag + /// LSI Ready Interrupt flag LSIRDYF: u1, - /// LSE ready interrupt flag + /// LSE Ready Interrupt flag LSERDYF: u1, - /// HSI ready interrupt flag + /// HSI Ready Interrupt flag HSIRDYF: u1, - /// HSE ready interrupt flag + /// HSE Ready Interrupt flag HSERDYF: u1, - /// Main PLL (PLL) ready interrupt flag + /// PLL Ready Interrupt flag PLLRDYF: u1, - /// PLLI2S ready interrupt flag - PLLI2SRDYF: u1, - /// PLLSAI ready interrupt flag - PLLSAIRDYF: u1, - /// Clock security system interrupt flag + reserved7: u2, + /// Clock Security System Interrupt flag CSSF: u1, - /// LSI ready interrupt enable + /// LSI Ready Interrupt Enable LSIRDYIE: u1, - /// LSE ready interrupt enable + /// LSE Ready Interrupt Enable LSERDYIE: u1, - /// HSI ready interrupt enable + /// HSI Ready Interrupt Enable HSIRDYIE: u1, - /// HSE ready interrupt enable + /// HSE Ready Interrupt Enable HSERDYIE: u1, - /// Main PLL (PLL) ready interrupt enable + /// PLL Ready Interrupt Enable PLLRDYIE: u1, - /// PLLI2S ready interrupt enable - PLLI2SRDYIE: u1, - /// PLLSAI Ready Interrupt Enable - PLLSAIRDYIE: u1, - reserved16: u1, - /// LSI ready interrupt clear + reserved16: u3, + /// LSI Ready Interrupt Clear LSIRDYC: u1, - /// LSE ready interrupt clear + /// LSE Ready Interrupt Clear LSERDYC: u1, - /// HSI ready interrupt clear + /// HSI Ready Interrupt Clear HSIRDYC: u1, - /// HSE ready interrupt clear + /// HSE Ready Interrupt Clear HSERDYC: u1, - /// Main PLL(PLL) ready interrupt clear + /// PLL Ready Interrupt Clear PLLRDYC: u1, - /// PLLI2S ready interrupt clear - PLLI2SRDYC: u1, - /// PLLSAI Ready Interrupt Clear - PLLSAIRDYC: u1, + reserved23: u2, /// Clock security system interrupt clear CSSC: u1, padding: u8, }), - /// AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - /// IO port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// IO port H reset - GPIOHRST: u1, - /// IO port I reset - GPIOIRST: u1, - /// IO port J reset - GPIOJRST: u1, - /// IO port K reset - GPIOKRST: u1, - reserved12: u1, - /// CRC reset - CRCRST: u1, - reserved21: u8, - /// DMA2 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - /// DMA2D reset - DMA2DRST: u1, - reserved25: u1, - /// Ethernet MAC reset - ETHRST: u1, - reserved29: u3, - /// USB OTG HS module reset - USB_OTG_HSRST: u1, - padding: u2, - }), - /// AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// Camera interface reset - DCMIRST: u1, - reserved4: u3, - /// CRYP module reset - CRYPRST: u1, - /// Hash module reset - HSAHRST: u1, - /// Random number generator module reset - RNGRST: u1, - /// USB OTG FS module reset - USB_OTG_FSRST: u1, - padding: u24, - }), - /// AHB3 peripheral reset register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - /// Flexible static memory controller module reset - FMCRST: u1, - /// QUADSPI module reset - QUADSPIRST: u1, - padding: u30, + /// APB2 peripheral reset register (RCC_APB2RSTR) + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// SYSCFG and COMP reset + SYSCFGRST: u1, + reserved9: u8, + /// ADC interface reset + ADCRST: u1, + reserved12: u2, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// USART1 reset + USART1RST: u1, + reserved16: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + /// TIM19 timer reset + TIM19RST: u1, + reserved22: u2, + /// MCU debug module clock enable + DBGMCURST: u1, + reserved24: u1, + /// SDADC1 (Sigma delta ADC 1) reset + SDADC1RST: u1, + /// SDADC2 (Sigma delta ADC 2) reset + SDADC2RST: u1, + /// SDADC3 (Sigma delta ADC 3) reset + SDADC3RST: u1, + padding: u5, }), - reserved32: [4]u8, - /// APB1 peripheral reset register + /// APB1 peripheral reset register (RCC_APB1RSTR) APB1RSTR: mmio.Mmio(packed struct(u32) { - /// TIM2 reset + /// Timer 2 reset TIM2RST: u1, - /// TIM3 reset + /// Timer 3 reset TIM3RST: u1, - /// TIM4 reset + /// Timer 14 reset TIM4RST: u1, - /// TIM5 reset + /// Timer 5 reset TIM5RST: u1, - /// TIM6 reset + /// Timer 6 reset TIM6RST: u1, - /// TIM7 reset + /// Timer 7 reset TIM7RST: u1, - /// TIM12 reset + /// Timer 12 reset TIM12RST: u1, - /// TIM13 reset + /// Timer 13 reset TIM13RST: u1, - /// TIM14 reset + /// Timer 14 reset TIM14RST: u1, - /// LPTIM1 reset - LPTIM1RST: u1, + /// Timer 18 reset + TIM18RST: u1, reserved11: u1, /// Window watchdog reset WWDGRST: u1, reserved14: u2, - /// SPI 2 reset + /// SPI2 reset SPI2RST: u1, - /// SPI 3 reset + /// SPI3 reset SPI3RST: u1, - /// SPDIF-IN reset - SPDIFRST: u1, + reserved17: u1, /// USART 2 reset USART2RST: u1, - /// USART 3 reset + /// USART3 reset USART3RST: u1, - /// UART 4 reset - UART4RST: u1, - /// UART 5 reset - UART5RST: u1, - /// I2C 1 reset + reserved21: u2, + /// I2C1 reset I2C1RST: u1, - /// I2C 2 reset + /// I2C2 reset I2C2RST: u1, - /// I2C3 reset - I2C3RST: u1, - /// FMPI2C1 reset - FMPI2C1RST: u1, - /// CAN1 reset - CAN1RST: u1, - /// CAN2 reset - CAN2RST: u1, - /// CAN 3 reset - CAN3RST: u1, + /// USB reset + USBRST: u1, + reserved25: u1, + /// CAN reset + CANRST: u1, + /// DAC2 interface reset + DAC2RST: u1, + reserved28: u1, /// Power interface reset PWRRST: u1, - /// DAC reset + /// DAC interface reset DACRST: u1, - /// UART 7 reset - UART7RST: u1, - /// UART 8 reset - UART8RST: u1, - }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// TIM1 reset - TIM1RST: u1, - /// TIM8 reset - TIM8RST: u1, - reserved4: u2, - /// USART1 reset - USART1RST: u1, - /// USART6 reset - USART6RST: u1, - /// UART9 reset - UART9RST: u1, - /// UART10 reset - UART10RST: u1, - /// ADC interface reset (common to all ADCs) - ADCRST: u1, - reserved11: u2, - /// SDIO reset - SDIORST: u1, - /// SPI 1 reset - SPI1RST: u1, - /// SPI4 reset - SPI4RST: u1, - /// System configuration controller reset - SYSCFGRST: u1, - reserved16: u1, - /// TIM9 reset - TIM9RST: u1, - /// TIM10 reset - TIM10RST: u1, - /// TIM11 reset - TIM11RST: u1, - reserved20: u1, - /// SPI5 reset - SPI5RST: u1, - /// SPI6 reset - SPI6RST: u1, - /// SAI1 reset - SAI1RST: u1, - /// SAI2 reset - SAI2RST: u1, - /// DFSDMRST - DFSDMRST: u1, - /// DFSDM2 reset - DFSDM2RST: u1, - /// LTDC reset - LTDCRST: u1, - /// DSI host reset - DSIRST: u1, - padding: u4, + /// HDMI CEC reset + CECRST: u1, + padding: u1, }), - reserved48: [8]u8, - /// AHB1 peripheral clock register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable + /// AHB Peripheral Clock enable register (RCC_AHBENR) + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock enable + SRAMEN: u1, + reserved4: u1, + /// FLASH clock enable + FLASHEN: u1, + reserved6: u1, + /// CRC clock enable + CRCEN: u1, + reserved17: u10, + /// I/O port A clock enable GPIOAEN: u1, - /// IO port B clock enable + /// I/O port B clock enable GPIOBEN: u1, - /// IO port C clock enable + /// I/O port C clock enable GPIOCEN: u1, - /// IO port D clock enable + /// I/O port D clock enable GPIODEN: u1, - /// IO port E clock enable + /// I/O port E clock enable GPIOEEN: u1, - /// IO port F clock enable + /// I/O port F clock enable GPIOFEN: u1, - /// IO port G clock enable - GPIOGEN: u1, - /// IO port H clock enable - GPIOHEN: u1, - /// IO port I clock enable - GPIOIEN: u1, - /// IO port J clock enable - GPIOJEN: u1, - /// IO port K clock enable - GPIOKEN: u1, - reserved12: u1, - /// CRC clock enable - CRCEN: u1, - reserved18: u5, - /// Backup SRAM interface clock enable - BKPSRAMEN: u1, - reserved20: u1, - /// CCM data RAM clock enable - CCMDATARAMEN: u1, - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// DMA2D clock enable - DMA2DEN: u1, - reserved25: u1, - /// Ethernet MAC clock enable - ETHEN: u1, - /// Ethernet Transmission clock enable - ETHTXEN: u1, - /// Ethernet Reception clock enable - ETHRXEN: u1, - /// Ethernet PTP clock enable - ETHPTPEN: u1, - /// USB OTG HS clock enable - USB_OTG_HSEN: u1, - /// USB OTG HSULPI clock enable - USB_OTG_HSULPIEN: u1, - padding: u1, - }), - /// AHB2 peripheral clock enable register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// Camera interface enable - DCMIEN: u1, - reserved4: u3, - /// CRYP clock enable - CRYPEN: u1, - /// Hash modules clock enable - HASHEN: u1, - /// Random number generator clock enable - RNGEN: u1, - /// USB OTG FS clock enable - USB_OTG_FSEN: u1, - padding: u24, + reserved24: u1, + /// Touch sensing controller clock enable + TSCEN: u1, + padding: u7, }), - /// AHB3 peripheral clock enable register - AHB3ENR: mmio.Mmio(packed struct(u32) { - /// Flexible static memory controller module clock enable - FMCEN: u1, - /// QUADSPI memory controller module clock enable - QUADSPIEN: u1, - padding: u30, + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved9: u8, + /// ADC 1 interface clock enable + ADCEN: u1, + reserved12: u2, + /// SPI 1 clock enable + SPI1EN: u1, + reserved14: u1, + /// USART1 clock enable + USART1EN: u1, + reserved16: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + /// TIM19 timer clock enable + TIM19EN: u1, + reserved22: u2, + /// MCU debug module clock enable + DBGMCUEN: u1, + reserved24: u1, + /// SDADC1 (Sigma Delta ADC 1) clock enable + SDADC1EN: u1, + /// SDADC2 (Sigma Delta ADC 2) clock enable + SDADC2EN: u1, + /// SDADC3 (Sigma Delta ADC 3) clock enable + SDADC3EN: u1, + padding: u5, }), - reserved64: [4]u8, - /// APB1 peripheral clock enable register + /// APB1 peripheral clock enable register (RCC_APB1ENR) APB1ENR: mmio.Mmio(packed struct(u32) { - /// TIM2 clock enable + /// Timer 2 clock enable TIM2EN: u1, - /// TIM3 clock enable + /// Timer 3 clock enable TIM3EN: u1, - /// TIM4 clock enable + /// Timer 4 clock enable TIM4EN: u1, - /// TIM5 clock enable + /// Timer 5 clock enable TIM5EN: u1, - /// TIM6 clock enable + /// Timer 6 clock enable TIM6EN: u1, - /// TIM7 clock enable + /// Timer 7 clock enable TIM7EN: u1, - /// TIM12 clock enable + /// Timer 12 clock enable TIM12EN: u1, - /// TIM13 clock enable + /// Timer 13 clock enable TIM13EN: u1, - /// TIM14 clock enable + /// Timer 14 clock enable TIM14EN: u1, - /// LPTIM1 clock enable - LPTIM1EN: u1, - /// RTC APB clock enable - RTCAPBEN: u1, + /// Timer 18 clock enable + TIM18EN: u1, + reserved11: u1, /// Window watchdog clock enable WWDGEN: u1, reserved14: u2, - /// SPI2 clock enable + /// SPI 2 clock enable SPI2EN: u1, - /// SPI3 clock enable + /// SPI 3 clock enable SPI3EN: u1, - /// SPDIF-IN clock enable - SPDIFEN: u1, + reserved17: u1, /// USART 2 clock enable USART2EN: u1, - /// USART3 clock enable + /// USART 3 clock enable USART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// UART5 clock enable - UART5EN: u1, - /// I2C1 clock enable + reserved21: u2, + /// I2C 1 clock enable I2C1EN: u1, - /// I2C2 clock enable + /// I2C 2 clock enable I2C2EN: u1, - /// I2C3 clock enable - I2C3EN: u1, - /// FMPI2C1 clock enable - FMPI2C1EN: u1, - /// CAN 1 clock enable - CAN1EN: u1, - /// CAN 2 clock enable - CAN2EN: u1, - /// CAN 3 clock enable - CAN3EN: u1, + /// USB clock enable + USBEN: u1, + reserved25: u1, + /// CAN clock enable + CANEN: u1, + /// DAC2 interface clock enable + DAC2EN: u1, + reserved28: u1, /// Power interface clock enable PWREN: u1, /// DAC interface clock enable DACEN: u1, - /// UART7 clock enable - UART7EN: u1, - /// UART8 clock enable - UART8EN: u1, - }), - /// APB2 peripheral clock enable register - APB2ENR: mmio.Mmio(packed struct(u32) { - /// TIM1 clock enable - TIM1EN: u1, - /// TIM8 clock enable - TIM8EN: u1, - reserved4: u2, - /// USART1 clock enable - USART1EN: u1, - /// USART6 clock enable - USART6EN: u1, - /// UART9 clock enable - UART9EN: u1, - /// UART10 clock enable - UART10EN: u1, - /// ADC1 clock enable - ADC1EN: u1, - /// ADC2 clock enable - ADC2EN: u1, - /// ADC3 clock enable - ADC3EN: u1, - /// SDIO clock enable - SDIOEN: u1, - /// SPI1 clock enable - SPI1EN: u1, - /// SPI4 clock enable - SPI4EN: u1, - /// System configuration controller clock enable - SYSCFGEN: u1, - /// EXTI ans external IT clock enable - EXTITEN: u1, - /// TIM9 clock enable - TIM9EN: u1, - /// TIM10 clock enable - TIM10EN: u1, - /// TIM11 clock enable - TIM11EN: u1, - reserved20: u1, - /// SPI5 clock enable - SPI5EN: u1, - /// SPI6 clock enable - SPI6EN: u1, - /// SAI 1 clock enable - SAI1EN: u1, - /// SAI2 clock enable - SAI2EN: u1, - /// DFSDMEN - DFSDMEN: u1, - /// DFSDM2 clock enable - DFSDM2EN: u1, - /// LTDC clock enable - LTDCEN: u1, - /// DSI clocks enable - DSIEN: u1, - padding: u4, - }), - reserved80: [8]u8, - /// AHB1 peripheral clock enable in low power mode register - AHB1LPENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable during sleep mode - GPIOALPEN: u1, - /// IO port B clock enable during Sleep mode - GPIOBLPEN: u1, - /// IO port C clock enable during Sleep mode - GPIOCLPEN: u1, - /// IO port D clock enable during Sleep mode - GPIODLPEN: u1, - /// IO port E clock enable during Sleep mode - GPIOELPEN: u1, - /// IO port F clock enable during Sleep mode - GPIOFLPEN: u1, - /// IO port G clock enable during Sleep mode - GPIOGLPEN: u1, - /// IO port H clock enable during Sleep mode - GPIOHLPEN: u1, - /// IO port I clock enable during Sleep mode - GPIOILPEN: u1, - /// IO port J clock enable during Sleep mode - GPIOJLPEN: u1, - /// IO port K clock enable during Sleep mode - GPIOKLPEN: u1, - reserved12: u1, - /// CRC clock enable during Sleep mode - CRCLPEN: u1, - reserved15: u2, - /// Flash interface clock enable during Sleep mode - FLASHLPEN: u1, - /// SRAM 1interface clock enable during Sleep mode - SRAM1LPEN: u1, - /// SRAM 2 interface clock enable during Sleep mode - SRAM2LPEN: u1, - /// Backup SRAM interface clock enable during Sleep mode - BKPSRAMLPEN: u1, - /// SRAM 3 interface clock enable during Sleep mode - SRAM3LPEN: u1, - reserved21: u1, - /// DMA1 clock enable during Sleep mode - DMA1LPEN: u1, - /// DMA2 clock enable during Sleep mode - DMA2LPEN: u1, - /// DMA2D clock enable during Sleep mode - DMA2DLPEN: u1, - reserved25: u1, - /// Ethernet MAC clock enable during Sleep mode - ETHLPEN: u1, - /// Ethernet transmission clock enable during Sleep mode - ETHTXLPEN: u1, - /// Ethernet reception clock enable during Sleep mode - ETHRXLPEN: u1, - /// Ethernet PTP clock enable during Sleep mode - ETHPTPLPEN: u1, - /// USB OTG HS clock enable during Sleep mode - USB_OTG_HSLPEN: u1, - /// USB OTG HS ULPI clock enable during Sleep mode - USB_OTG_HSULPILPEN: u1, - /// RNG clock enable during sleep mode - RNGLPEN: u1, - }), - /// AHB2 peripheral clock enable in low power mode register - AHB2LPENR: mmio.Mmio(packed struct(u32) { - /// Camera interface enable during Sleep mode - DCMILPEN: u1, - /// QUADSPI memory controller module clock enable during Sleep mode - QUADSPILPEN: u1, - reserved4: u2, - /// Cryptography modules clock enable during Sleep mode - CRYPLPEN: u1, - /// Hash modules clock enable during Sleep mode - HASHLPEN: u1, - /// Random number generator clock enable during Sleep mode - RNGLPEN: u1, - /// USB OTG FS clock enable during Sleep mode - USB_OTG_FSLPEN: u1, - padding: u24, - }), - /// AHB3 peripheral clock enable in low power mode register - AHB3LPENR: mmio.Mmio(packed struct(u32) { - /// Flexible static memory controller module clock enable during Sleep mode - FMCLPEN: u1, - /// QUADSPI memory controller module clock enable during Sleep mode - QUADSPILPEN: u1, - padding: u30, - }), - reserved96: [4]u8, - /// APB1 peripheral clock enable in low power mode register - APB1LPENR: mmio.Mmio(packed struct(u32) { - /// TIM2 clock enable during Sleep mode - TIM2LPEN: u1, - /// TIM3 clock enable during Sleep mode - TIM3LPEN: u1, - /// TIM4 clock enable during Sleep mode - TIM4LPEN: u1, - /// TIM5 clock enable during Sleep mode - TIM5LPEN: u1, - /// TIM6 clock enable during Sleep mode - TIM6LPEN: u1, - /// TIM7 clock enable during Sleep mode - TIM7LPEN: u1, - /// TIM12 clock enable during Sleep mode - TIM12LPEN: u1, - /// TIM13 clock enable during Sleep mode - TIM13LPEN: u1, - /// TIM14 clock enable during Sleep mode - TIM14LPEN: u1, - /// LPTIM1 clock enable during sleep mode - LPTIM1LPEN: u1, - /// RTC APB clock enable during sleep mode - RTCAPBLPEN: u1, - /// Window watchdog clock enable during Sleep mode - WWDGLPEN: u1, - reserved14: u2, - /// SPI2 clock enable during Sleep mode - SPI2LPEN: u1, - /// SPI3 clock enable during Sleep mode - SPI3LPEN: u1, - /// SPDIF clock enable during Sleep mode - SPDIFLPEN: u1, - /// USART2 clock enable during Sleep mode - USART2LPEN: u1, - /// USART3 clock enable during Sleep mode - USART3LPEN: u1, - /// UART4 clock enable during Sleep mode - UART4LPEN: u1, - /// UART5 clock enable during Sleep mode - UART5LPEN: u1, - /// I2C1 clock enable during Sleep mode - I2C1LPEN: u1, - /// I2C2 clock enable during Sleep mode - I2C2LPEN: u1, - /// I2C3 clock enable during Sleep mode - I2C3LPEN: u1, - /// FMPI2C1 clock enable during Sleep - FMPI2C1LPEN: u1, - /// CAN 1 clock enable during Sleep mode - CAN1LPEN: u1, - /// CAN 2 clock enable during Sleep mode - CAN2LPEN: u1, - /// CAN3 clock enable during Sleep mode - CAN3LPEN: u1, - /// Power interface clock enable during Sleep mode - PWRLPEN: u1, - /// DAC interface clock enable during Sleep mode - DACLPEN: u1, - /// UART7 clock enable during Sleep mode - UART7LPEN: u1, - /// UART8 clock enable during Sleep mode - UART8LPEN: u1, - }), - /// APB2 peripheral clock enabled in low power mode register - APB2LPENR: mmio.Mmio(packed struct(u32) { - /// TIM1 clock enable during Sleep mode - TIM1LPEN: u1, - /// TIM8 clock enable during Sleep mode - TIM8LPEN: u1, - reserved4: u2, - /// USART1 clock enable during Sleep mode - USART1LPEN: u1, - /// USART6 clock enable during Sleep mode - USART6LPEN: u1, - /// UART9 clock enable during Sleep mode - UART9LPEN: u1, - /// UART10 clock enable during Sleep mode - UART10LPEN: u1, - /// ADC1 clock enable during Sleep mode - ADC1LPEN: u1, - /// ADC2 clock enable during Sleep mode - ADC2LPEN: u1, - /// ADC 3 clock enable during Sleep mode - ADC3LPEN: u1, - /// SDIO clock enable during Sleep mode - SDIOLPEN: u1, - /// SPI 1 clock enable during Sleep mode - SPI1LPEN: u1, - /// SPI4 clock enable during Sleep mode - SPI4LPEN: u1, - /// System configuration controller clock enable during Sleep mode - SYSCFGLPEN: u1, - /// EXTI and External IT clock enable during sleep mode - EXTITLPEN: u1, - /// TIM9 clock enable during sleep mode - TIM9LPEN: u1, - /// TIM10 clock enable during Sleep mode - TIM10LPEN: u1, - /// TIM11 clock enable during Sleep mode - TIM11LPEN: u1, - reserved20: u1, - /// SPI5 clock enable during Sleep mode - SPI5LPEN: u1, - /// SPI 6 clock enable during Sleep mode - SPI6LPEN: u1, - /// SAI1 clock enable during Sleep mode - SAI1LPEN: u1, - /// SAI2 clock enable - SAI2LPEN: u1, - /// DFSDMLPEN - DFSDMLPEN: u1, - /// DFSDM2 clock enable during Sleep mode - DFSDM2LPEN: u1, - /// LTDC clock enable during Sleep mode - LTDCLPEN: u1, - /// DSI clocks enable during Sleep mode - DSILPEN: u1, - padding: u4, + /// HDMI CEC interface clock enable + CECEN: u1, + padding: u1, }), - reserved112: [8]u8, - /// Backup domain control register + /// Backup domain control register (RCC_BDCR) BDCR: mmio.Mmio(packed struct(u32) { - /// External low-speed oscillator enable + /// External Low Speed oscillator enable LSEON: u1, - /// External low-speed oscillator ready + /// External Low Speed oscillator ready LSERDY: u1, - /// External low-speed oscillator bypass + /// External Low Speed oscillator bypass LSEBYP: u1, - /// External low-speed oscillator bypass - LSEMOD: packed union { - raw: u1, - value: LSEMOD, + /// LSE oscillator drive capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, }, - reserved8: u4, + reserved8: u3, /// RTC clock source selection RTCSEL: packed union { raw: u2, @@ -387745,3617 +371216,3030 @@ pub const types = struct { BDRST: u1, padding: u15, }), - /// clock control & status register + /// Control/status register (RCC_CSR) CSR: mmio.Mmio(packed struct(u32) { - /// Internal low-speed oscillator enable + /// Internal low speed oscillator enable LSION: u1, - /// Internal low-speed oscillator ready + /// Internal low speed oscillator ready LSIRDY: u1, - reserved24: u22, + reserved23: u21, + /// Reset flag of the 1.8 V domain + V18PWRRSTF: u1, /// Remove reset flag RMVF: u1, - /// BOR reset flag - BORRSTF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, /// PIN reset flag - PADRSTF: u1, + PINRSTF: u1, /// POR/PDR reset flag PORRSTF: u1, /// Software reset flag SFTRSTF: u1, /// Independent watchdog reset flag - WDGRSTF: u1, + IWDGRSTF: u1, /// Window watchdog reset flag WWDGRSTF: u1, /// Low-power reset flag LPWRRSTF: u1, }), - reserved128: [8]u8, - /// spread spectrum clock generation register - SSCGR: mmio.Mmio(packed struct(u32) { - /// Modulation period - MODPER: u13, - /// Incrementation step - INCSTEP: u15, - reserved30: u2, - /// Spread Select - SPREADSEL: packed union { - raw: u1, - value: SPREADSEL, - }, - /// Spread spectrum modulation enable - SSCGEN: u1, - }), - /// PLLI2S configuration register - PLLI2SCFGR: mmio.Mmio(packed struct(u32) { - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - PLLM: packed union { - raw: u6, - value: PLLM, - }, - /// Main PLL (PLL) multiplication factor for VCO - PLLN: packed union { - raw: u9, - value: PLLN, - }, - reserved16: u1, - /// Main PLL (PLL) division factor for main system clock - PLLP: packed union { - raw: u2, - value: PLLP, - }, - reserved22: u4, - /// PLLI2S entry clock source - PLLI2SSRC: packed union { - raw: u1, - value: PLLI2SSRC, - }, + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + reserved17: u17, + /// I/O port A reset + GPIOARST: u1, + /// I/O port B reset + GPIOBRST: u1, + /// I/O port C reset + GPIOCRST: u1, + /// I/O port D reset + GPIODRST: u1, + /// I/O port E reset + GPIOERST: u1, + /// I/O port F reset + GPIOFRST: u1, reserved24: u1, - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - PLLQ: packed union { - raw: u4, - value: PLLQ, - }, - /// PLL division factor for I2S and System clocks - PLLR: packed union { - raw: u3, - value: PLLR, - }, - padding: u1, + /// Touch sensing controller reset + TSCRST: u1, + padding: u7, }), - /// RCC PLL configuration register - PLLSAICFGR: mmio.Mmio(packed struct(u32) { - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - PLLM: packed union { - raw: u6, - value: PLLM, - }, - /// Main PLL (PLL) multiplication factor for VCO - PLLN: packed union { - raw: u9, - value: PLLN, - }, - reserved16: u1, - /// Main PLL (PLL) division factor for main system clock - PLLP: packed union { - raw: u2, - value: PLLP, - }, - reserved22: u4, - /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - PLLSRC: packed union { - raw: u1, - value: PLLSRC, - }, - reserved24: u1, - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - PLLQ: packed union { + /// Clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// PREDIV division factor + PREDIV: packed union { raw: u4, - value: PLLQ, - }, - /// PLL division factor for I2S and System clocks - PLLR: packed union { - raw: u3, - value: PLLR, + value: PREDIV, }, - padding: u1, - }), - /// RCC Dedicated Clock Configuration Register - DCKCFGR: mmio.Mmio(packed struct(u32) { - /// PLLI2S division factor for SAI1 clock - PLLI2SDIVQ: packed union { + /// ADC1 and ADC2 prescaler + ADC12PRES: packed union { raw: u5, - value: PLLI2SDIVQ, + value: ADCPRES, }, - reserved8: u3, - /// PLL division factor for SAI1 A/B clock - PLLDIVR: packed union { + /// ADC3 and ADC4 prescaler + ADC34PRES: packed union { raw: u5, - value: PLLDIVR, + value: ADCPRES, }, - reserved14: u1, - /// DFSDM2 audio clock selection - CKDFSDM2ASEL: packed union { - raw: u1, - value: CKDFSDMASEL, + padding: u18, + }), + /// Clock configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SW: packed union { + raw: u2, + value: USART1SW, }, - /// DFSDM1 audio clock selection - CKDFSDM1ASEL: packed union { + reserved4: u2, + /// I2C1 clock source selection + I2C1SW: packed union { raw: u1, - value: CKDFSDMASEL, + value: ICSW, }, - /// division factor for LCD_CLK - PLLSAIDIVR: packed union { - raw: u2, - value: PLLSAIDIVR, + /// I2C2 clock source selection + I2C2SW: packed union { + raw: u1, + value: ICSW, }, - reserved20: u2, - /// SAI1-A clock source selection - SAI1ASRC: packed union { - raw: u2, - value: SAIASRC, + /// HDMI CEC clock source selection + CECSW: packed union { + raw: u1, + value: CECSW, }, - /// SAI1-B clock source selection - SAI1BSRC: packed union { - raw: u2, - value: SAIBSRC, + reserved8: u1, + /// Timer1 clock source selection + TIM1SW: packed union { + raw: u1, + value: TIMSW, }, - /// Timers clocks prescalers selection - TIMPRE: packed union { + /// Timer8 clock source selection + TIM8SW: packed union { raw: u1, - value: TIMPRE, + value: TIMSW, }, - /// I2S APB1 clocks source selection (I2S2/3) - I2S1SRC: packed union { - raw: u2, - value: I2S1SRC, + /// Timer15 clock source selection + TIM15SW: packed union { + raw: u1, + value: TIMSW, }, - /// 48 MHz clock source selection - CLK48SEL: packed union { + /// Timer16 clock source selection + TIM16SW: packed union { raw: u1, - value: CLK48SEL, + value: TIMSW, }, - /// SDIO clock source selection - SDIOSEL: packed union { + /// Hrtim1 clock source selection + HRTIM1SW: packed union { raw: u1, - value: SDIOSEL, + value: TIMSW, }, - /// DSI clock source selection - DSISEL: packed union { + /// Timer17 clock source selection + TIM17SW: packed union { raw: u1, - value: DSISEL, + value: TIMSW, }, - reserved31: u1, - /// DFSDM1 Kernel clock selection - CKDFSDM1SEL: packed union { + reserved15: u1, + /// Timer20 clock source selection + TIM20SW: packed union { raw: u1, - value: CKDFSDMSEL, + value: TIMSW, }, - }), - /// Clocks gated enable register - CKGATENR: mmio.Mmio(packed struct(u32) { - /// AHB to APB1 Bridge clock enable - AHB2APB1_CKEN: u1, - /// AHB to APB2 Bridge clock enable - AHB2APB2_CKEN: u1, - /// Cortex M4 ETM clock enable - CM4DBG_CKEN: u1, - /// Spare clock enable - SPARE_CKEN: u1, - /// SRAM controller clock enable - SRAM_CKEN: u1, - /// Flash interface clock enable - FLASH_CKEN: u1, - /// RCC clock enable - RCC_CKEN: u1, - /// EVTCL clock enable - EVTCL_CKEN: u1, - padding: u24, - }), - /// DCKCFGR2 register - DCKCFGR2: mmio.Mmio(packed struct(u32) { - reserved22: u22, - /// FMPI2C1 kernel clock source selection - FMPI2C1SEL: packed union { + /// USART2 clock source selection + USART2SW: packed union { raw: u2, - value: FMPI2CSEL, + value: USARTSW, }, - reserved26: u2, - /// HDMI CEC clock source selection - CECSEL: packed union { - raw: u1, - value: CECSEL, + /// USART3 clock source selection + USART3SW: packed union { + raw: u2, + value: USARTSW, }, - /// SDIO/USB clock selection - CLK48SEL: packed union { - raw: u1, - value: CLK48SEL, + /// UART4 clock source selection + UART4SW: packed union { + raw: u2, + value: USARTSW, }, - /// SDIO clock selection - SDIOSEL: packed union { - raw: u1, - value: SDIOSEL, + /// UART5 clock source selection + UART5SW: packed union { + raw: u2, + value: USARTSW, }, - /// SPDIF clock selection - SPDIFRXSEL: packed union { + /// Timer2 clock source selection + TIM2SW: packed union { raw: u1, - value: SPDIFRXSEL, + value: TIM2SW, }, - /// LPTIM1SEL - LPTIM1SEL: packed union { - raw: u2, - value: LPTIMSEL, + /// Timer34 clock source selection + TIM34SW: packed union { + raw: u1, + value: TIMSW, }, + padding: u6, }), }; }; - pub const sai_v3_2pdm = struct { - pub const CKSTR = enum(u1) { - /// Data strobing edge is falling edge of SCK - FallingEdge = 0x0, - /// Data strobing edge is rising edge of SCK - RisingEdge = 0x1, - }; - - pub const CNRDY = enum(u1) { - /// External AC’97 Codec is ready - Ready = 0x0, - /// External AC’97 Codec is not ready - NotReady = 0x1, + pub const rcc_f3v1 = struct { + pub const ADCPRE = enum(u2) { + /// PCLK divided by 2 + Div2 = 0x0, + /// PCLK divided by 4 + Div4 = 0x1, + /// PCLK divided by 6 + Div6 = 0x2, + /// PCLK divided by 8 + Div8 = 0x3, }; - pub const COMP = enum(u2) { - /// No companding algorithm - NoCompanding = 0x0, - /// μ-Law algorithm - MuLaw = 0x2, - /// A-Law algorithm - ALaw = 0x3, + pub const ADCPRES = enum(u5) { + /// PLL clock not divided + Div1 = 0x10, + /// PLL clock divided by 2 + Div2 = 0x11, + /// PLL clock divided by 4 + Div4 = 0x12, + /// PLL clock divided by 6 + Div6 = 0x13, + /// PLL clock divided by 8 + Div8 = 0x14, + /// PLL clock divided by 10 + Div10 = 0x15, + /// PLL clock divided by 12 + Div12 = 0x16, + /// PLL clock divided by 16 + Div16 = 0x17, + /// PLL clock divided by 32 + Div32 = 0x18, + /// PLL clock divided by 64 + Div64 = 0x19, + /// PLL clock divided by 128 + Div128 = 0x1a, + /// PLL clock divided by 256 + Div256 = 0x1b, _, }; - pub const CPL = enum(u1) { - /// 1’s complement representation - OnesComplement = 0x0, - /// 2’s complement representation - TwosComplement = 0x1, + pub const CECSW = enum(u1) { + /// HSI clock divided by 244 selected as CEC clock source + HSI_DIV_244 = 0x0, + /// LSE clock selected as CEC clock source + LSE = 0x1, }; - pub const DS = enum(u3) { - /// 8 bits - Bit8 = 0x2, - /// 10 bits - Bit10 = 0x3, - /// 16 bits - Bit16 = 0x4, - /// 20 bits - Bit20 = 0x5, - /// 24 bits - Bit24 = 0x6, - /// 32 bits - Bit32 = 0x7, + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, _, }; - pub const FLVL = enum(u3) { - /// FIFO empty - Empty = 0x0, - /// FIFO <= 1⁄4 but not empty - Quarter1 = 0x1, - /// 1⁄4 < FIFO <= 1⁄2 - Quarter2 = 0x2, - /// 1⁄2 < FIFO <= 3⁄4 - Quarter3 = 0x3, - /// 3⁄4 < FIFO but not full - Quarter4 = 0x4, - /// FIFO full - Full = 0x5, - _, + pub const ICSW = enum(u1) { + /// HSI clock selected as I2C clock source + HSI = 0x0, + /// SYSCLK clock selected as I2C clock source + SYS = 0x1, }; - pub const FSOFF = enum(u1) { - /// FS is asserted on the first bit of the slot 0 - OnFirst = 0x0, - /// FS is asserted one bit before the first bit of the slot 0 - BeforeFirst = 0x1, + pub const ISSRC = enum(u1) { + /// System clock used as I2S clock source + SYS = 0x0, + /// External clock mapped on the I2S_CKIN pin used as I2S clock source + CKIN = 0x1, }; - pub const FSPOL = enum(u1) { - /// FS is active low (falling edge) - FallingEdge = 0x0, - /// FS is active high (rising edge) - RisingEdge = 0x1, + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium high driving capability + MediumHigh = 0x1, + /// Medium low driving capability + MediumLow = 0x2, + /// High driving capability + High = 0x3, }; - pub const FTH = enum(u3) { - /// FIFO empty - Empty = 0x0, - /// 1⁄4 FIFO - Quarter1 = 0x1, - /// 1⁄2 FIFO - Quarter2 = 0x2, - /// 3⁄4 FIFO - Quarter3 = 0x3, - /// FIFO full - Full = 0x4, + pub const MCOSEL = enum(u3) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// Internal low speed (LSI) oscillator clock selected + LSI = 0x2, + /// External low speed (LSE) oscillator clock selected + LSE = 0x3, + /// System clock selected + SYS = 0x4, + /// Internal RC 8 MHz (HSI) oscillator clock selected + HSI = 0x5, + /// External 4-32 MHz (HSE) oscillator clock selected + HSE = 0x6, + /// PLL clock divided by 2 + PLL_DIV_2 = 0x7, _, }; - pub const LSBFIRST = enum(u1) { - /// Data are transferred with MSB first - MsbFirst = 0x0, - /// Data are transferred with LSB first - LsbFirst = 0x1, + pub const PLLMUL = enum(u4) { + /// PLL input clock x2 + Mul2 = 0x0, + /// PLL input clock x3 + Mul3 = 0x1, + /// PLL input clock x4 + Mul4 = 0x2, + /// PLL input clock x5 + Mul5 = 0x3, + /// PLL input clock x6 + Mul6 = 0x4, + /// PLL input clock x7 + Mul7 = 0x5, + /// PLL input clock x8 + Mul8 = 0x6, + /// PLL input clock x9 + Mul9 = 0x7, + /// PLL input clock x10 + Mul10 = 0x8, + /// PLL input clock x11 + Mul11 = 0x9, + /// PLL input clock x12 + Mul12 = 0xa, + /// PLL input clock x13 + Mul13 = 0xb, + /// PLL input clock x14 + Mul14 = 0xc, + /// PLL input clock x15 + Mul15 = 0xd, + /// PLL input clock x16 + Mul16 = 0xe, + _, }; - pub const MODE = enum(u2) { - /// Master transmitter - MasterTx = 0x0, - /// Master receiver - MasterRx = 0x1, - /// Slave transmitter - SlaveTx = 0x2, - /// Slave receiver - SlaveRx = 0x3, + pub const PLLSRC = enum(u1) { + /// HSI divided by 2 selected as PLL input clock + HSI_Div2 = 0x0, + /// HSE divided by PREDIV selected as PLL input clock + HSE_Div_PREDIV = 0x1, }; - pub const MONO = enum(u1) { - /// Stereo mode - Stereo = 0x0, - /// Mono mode - Mono = 0x1, + pub const PLLXTPRE = enum(u1) { + /// HSE clock not divided + Div1 = 0x0, + /// HSE clock divided by 2 + Div2 = 0x1, }; - pub const MUTEVAL = enum(u1) { - /// Bit value 0 is sent during the mute mode - SendZero = 0x0, - /// Last values are sent during the mute mode - SendLast = 0x1, + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, }; - pub const NODIV = enum(u1) { - /// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value - MasterClock = 0x0, - /// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. - NoDiv = 0x1, + pub const PREDIV = enum(u4) { + /// PREDIV input clock not divided + Div1 = 0x0, + /// PREDIV input clock divided by 2 + Div2 = 0x1, + /// PREDIV input clock divided by 3 + Div3 = 0x2, + /// PREDIV input clock divided by 4 + Div4 = 0x3, + /// PREDIV input clock divided by 5 + Div5 = 0x4, + /// PREDIV input clock divided by 6 + Div6 = 0x5, + /// PREDIV input clock divided by 7 + Div7 = 0x6, + /// PREDIV input clock divided by 8 + Div8 = 0x7, + /// PREDIV input clock divided by 9 + Div9 = 0x8, + /// PREDIV input clock divided by 10 + Div10 = 0x9, + /// PREDIV input clock divided by 11 + Div11 = 0xa, + /// PREDIV input clock divided by 12 + Div12 = 0xb, + /// PREDIV input clock divided by 13 + Div13 = 0xc, + /// PREDIV input clock divided by 14 + Div14 = 0xd, + /// PREDIV input clock divided by 15 + Div15 = 0xe, + /// PREDIV input clock divided by 16 + Div16 = 0xf, }; - pub const OUTDRIV = enum(u1) { - /// Audio block output driven when SAIEN is set - OnStart = 0x0, - /// Audio block output driven immediately after the setting of this bit - Immediately = 0x1, + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, }; - pub const PRTCFG = enum(u2) { - /// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol - Free = 0x0, - /// SPDIF protocol - Spdif = 0x1, - /// AC’97 protocol - Ac97 = 0x2, + pub const SW = enum(u2) { + /// HSI oscillator used as system clock + HSI = 0x0, + /// HSE oscillator used as system clock + HSE = 0x1, + /// PLL used as system clock + PLL1_P = 0x2, _, }; - pub const SLOTEN = enum(u16) { - /// Inactive slot - Inactive = 0x0, - /// Active slot - Active = 0x1, - _, + pub const TIM2SW = enum(u1) { + /// PCLK2 clock (doubled frequency when prescaled) + PCLK1_TIM = 0x0, + /// PLL vco output (running up to 144 MHz) + PLL1_P = 0x1, }; - pub const SLOTSZ = enum(u2) { - /// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) - DataSize = 0x0, - /// 16-bit - Bit16 = 0x1, - /// 32-bit - Bit32 = 0x2, - _, + pub const TIMSW = enum(u1) { + /// PCLK2 clock (doubled frequency when prescaled) + PCLK2_TIM = 0x0, + /// PLL vco output (running up to 144 MHz) + PLL1_P = 0x1, }; - pub const SYNCEN = enum(u2) { - /// audio sub-block in asynchronous mode - Asynchronous = 0x0, - /// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode - Internal = 0x1, - /// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode - External = 0x2, - _, + pub const USART1SW = enum(u2) { + /// PCLK selected as USART clock source + PCLK2 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const WCKCFG = enum(u1) { - /// Clock configuration is correct - Correct = 0x0, - /// Clock configuration does not respect the rule concerning the frame length specification - Wrong = 0x1, + pub const USARTSW = enum(u2) { + /// PCLK selected as USART clock source + PCLK1 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - pub const CH = extern struct { - /// Configuration register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// SAIx audio block mode immediately - MODE: packed union { - raw: u2, - value: MODE, - }, - /// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. - PRTCFG: packed union { + pub const USBPRE = enum(u1) { + /// PLL clock is divided by 1.5 + Div1_5 = 0x0, + /// PLL clock is not divided + Div1 = 0x1, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal High Speed clock enable + HSION: u1, + /// Internal High Speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal High Speed clock trimming + HSITRIM: u5, + /// Internal High Speed clock Calibration + HSICAL: u8, + /// External High Speed clock enable + HSEON: u1, + /// External High Speed clock ready flag + HSERDY: u1, + /// External High Speed clock Bypass + HSEBYP: u1, + /// Clock Security System enable + CSSON: u1, + reserved24: u4, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding: u6, + }), + /// Clock configuration register (RCC_CFGR) + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock Switch + SW: packed union { raw: u2, - value: PRTCFG, - }, - reserved5: u1, - /// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. - DS: packed union { - raw: u3, - value: DS, - }, - /// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. - LSBFIRST: packed union { - raw: u1, - value: LSBFIRST, - }, - /// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. - CKSTR: packed union { - raw: u1, - value: CKSTR, + value: SW, }, - /// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. - SYNCEN: packed union { + /// System Clock Switch Status + SWS: packed union { raw: u2, - value: SYNCEN, - }, - /// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. - MONO: packed union { - raw: u1, - value: MONO, - }, - /// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. - OUTDRIV: packed union { - raw: u1, - value: OUTDRIV, + value: SW, }, - reserved16: u2, - /// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. - SAIEN: u1, - /// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. - DMAEN: u1, - reserved19: u1, - /// No fixed divider between MCLK and FS - NODIV: packed union { - raw: u1, - value: NODIV, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, }, - /// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: - MCKDIV: u6, - /// Oversampling ratio for master clock - OSR: u1, - padding: u5, - }), - /// Configuration register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// FIFO threshold. This bit is set and cleared by software. - FTH: packed union { + /// APB Low speed prescaler (APB1) + PPRE1: packed union { raw: u3, - value: FTH, - }, - /// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. - FFLUSH: u1, - /// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. - TRIS: u1, - /// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. - MUTE: u1, - /// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. - MUTEVAL: packed union { - raw: u1, - value: MUTEVAL, + value: PPRE, }, - /// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. - MUTECNT: u6, - /// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. - CPL: packed union { - raw: u1, - value: CPL, + /// APB high speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, }, - /// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. - COMP: packed union { + /// ADC prescaler + ADCPRE: packed union { raw: u2, - value: COMP, + value: ADCPRE, }, - padding: u16, - }), - /// This register has no meaning in AC97 and SPDIF audio protocol - FRCR: mmio.Mmio(packed struct(u32) { - /// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. - FRL: u8, - /// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. - FSALL: u7, - reserved16: u1, - /// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. - FSDEF: u1, - /// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - FSPOL: packed union { + /// PLL entry clock source + PLLSRC: packed union { raw: u1, - value: FSPOL, + value: PLLSRC, }, - /// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - FSOFF: packed union { + /// HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products. + PLLXTPRE: packed union { raw: u1, - value: FSOFF, - }, - padding: u13, - }), - /// This register has no meaning in AC97 and SPDIF audio protocol - SLOTR: mmio.Mmio(packed struct(u32) { - /// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - FBOFF: u5, - reserved6: u1, - /// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - SLOTSZ: packed union { - raw: u2, - value: SLOTSZ, + value: PLLXTPRE, }, - /// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - NBSLOT: u4, - reserved16: u4, - /// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - SLOTEN: packed union { - raw: u16, - value: SLOTEN, + /// PLL Multiplication Factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, }, - }), - /// Interrupt mask register 2 - IM: mmio.Mmio(packed struct(u32) { - /// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. - OVRUDRIE: u1, - /// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. - MUTEDETIE: u1, - /// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. - WCKCFGIE: u1, - /// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, - FREQIE: u1, - /// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. - CNRDYIE: u1, - /// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. - AFSDETIE: u1, - /// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. - LFSDETIE: u1, - padding: u25, - }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. - OVRUDR: u1, - /// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. - MUTEDET: u1, - /// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. - WCKCFG: packed union { + /// USB prescaler + USBPRE: packed union { raw: u1, - value: WCKCFG, + value: USBPRE, }, - /// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. - FREQ: u1, - /// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. - CNRDY: packed union { + /// I2S external clock source selection + I2SSRC: packed union { raw: u1, - value: CNRDY, + value: ISSRC, }, - /// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. - AFSDET: u1, - /// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register - LFSDET: u1, - reserved16: u9, - /// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: - FLVL: packed union { + /// Microcontroller clock output + MCOSEL: packed union { raw: u3, - value: FLVL, + value: MCOSEL, }, - padding: u13, - }), - /// Clear flag register - CLRFR: mmio.Mmio(packed struct(u32) { - /// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. - COVRUDR: u1, - /// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. - CMUTEDET: u1, - /// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. - CWCKCFG: u1, - reserved4: u1, - /// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. - CCNRDY: u1, - /// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. - CAFSDET: u1, - /// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. - CLFSDET: u1, - padding: u25, + reserved28: u1, + /// Microcontroller Clock Output Flag. Set and reset by hardware. It is reset by hardware when MCO field is written with a new value. It is set by hardware when the switch to the new MCO source is effective. + MCOF: u1, + padding: u3, }), - /// Data register - DR: mmio.Mmio(packed struct(u32) { - /// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. - DATA: u32, + /// Clock interrupt register (RCC_CIR) + CIR: mmio.Mmio(packed struct(u32) { + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + reserved7: u2, + /// Clock Security System Interrupt flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + reserved16: u3, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + reserved23: u2, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, }), - }; - - /// Serial audio interface - pub const SAI = extern struct { - /// Global configuration register - GCR: mmio.Mmio(packed struct(u32) { - /// Synchronization inputs - SYNCIN: u2, - reserved4: u2, - /// Synchronization outputs These bits are set and cleared by software. - SYNCOUT: u2, - padding: u26, + /// APB2 peripheral reset register (RCC_APB2RSTR) + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// SYSCFG and COMP reset + SYSCFGRST: u1, + reserved11: u10, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + /// SPI4 reset + SPI4RST: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + /// TIM19 timer reset + TIM19RST: u1, + /// TIM20 timer reset + TIM20RST: u1, + reserved22: u1, + /// Debug MCU reset + DBGMCURST: u1, + reserved29: u6, + /// High Resolution Timer1 reset + HRTIM1RST: u1, + padding: u2, }), - /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - CH: u32, - reserved68: [60]u8, - /// PDM control register - PDMCR: mmio.Mmio(packed struct(u32) { - /// PDM enable - PDMEN: u1, - reserved4: u3, - /// Number of microphones - MICNBR: u2, - reserved8: u2, - /// Clock enable of bitstream clock number 1 - CKEN: u1, - padding: u23, - }), - /// PDM delay register - PDMDLY: mmio.Mmio(packed struct(u32) { - /// Delay line adjust for first microphone of pair 1 - DLYML: u3, + /// APB1 peripheral reset register (RCC_APB1RSTR) + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + /// Timer 14 reset + TIM4RST: u1, reserved4: u1, - /// Delay line adjust for second microphone of pair 1 - DLYMR: u3, - padding: u25, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + reserved11: u5, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved17: u1, + /// USART 2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// UART 4 reset + UART4RST: u1, + /// UART 5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB reset + USBRST: u1, + reserved25: u1, + /// CAN reset + CANRST: u1, + /// DAC2 interface reset + DAC2RST: u1, + reserved28: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// I2C3 reset + I2C3RST: u1, + padding: u1, }), - }; - }; - - pub const usbram_16x2_512 = struct { - /// USB Endpoint memory - pub const USBRAM = extern struct { - /// USB Endpoint memory - MEM: u32, - }; - }; - - pub const flash_wba = struct { - pub const BOR_LEV = enum(u3) { - /// BOR level 0 (reset level threshold around 1.7�V) - Level0 = 0x0, - /// BOR level 1 (reset level threshold around 2.0�V) - Level1 = 0x1, - /// BOR level 2 (reset level threshold around 2.2�V) - Level2 = 0x2, - /// BOR level 3 (reset level threshold around 2.5�V) - Level3 = 0x3, - /// BOR level 4 (reset level threshold around 2.8�V) - Level4 = 0x4, - _, - }; - - pub const CODE_OP = enum(u3) { - /// No operation interrupted by previous reset - B_0x0 = 0x0, - /// Single write operation interrupted - B_0x1 = 0x1, - /// Burst write operation interrupted - B_0x2 = 0x2, - /// Page erase operation interrupted - B_0x3 = 0x3, - /// Reserved - B_0x4 = 0x4, - /// Mass erase operation interrupted - B_0x5 = 0x5, - /// Option change operation interrupted - B_0x6 = 0x6, - /// Reserved - B_0x7 = 0x7, - }; - - pub const RDP = enum(u8) { - /// Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1) - B_0x55 = 0x55, - /// Level 0 (readout protection not active) - B_0xAA = 0xaa, - /// Level 2 (chip readout protection active) - B_0xCC = 0xcc, - _, - }; - - /// Embedded memory - pub const FLASH = extern struct { - /// access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency These bits represent the ratio between the AHB hclk1 clock period and the memory access time. Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. ... Note: Before entering Stop 1 mode software must set wait state latency to at least 1. - LATENCY: u4, - reserved8: u4, - /// Prefetch enable This bit enables the prefetch buffer in the embedded memory. This bit can be protected against unprivileged access by NSPRIV. - PRFTEN: u1, - reserved11: u2, - /// Low-power read mode This bit puts the memory in low-power read mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. This bit can’t be written when a program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a program or erase operation is busy (BSY = 1) is rejected. - LPM: u1, - /// power-down mode request This bit requests to enter power-down mode. When enters power-down mode, this bit is cleared by hardware and the PDKEYR is locked. This bit is write-protected with PDKEYR. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - PDREQ: u1, - reserved14: u1, - /// memory power-down mode during Sleep mode This bit determines whether the memory is in power-down mode or Idle mode when the device is in Sleep mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. The must not be put in power-down while a program or an erase operation is ongoing. - SLEEP_PD: u1, - padding: u17, + /// AHB Peripheral Clock enable register (RCC_AHBENR) + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock enable + SRAMEN: u1, + reserved4: u1, + /// FLASH clock enable + FLASHEN: u1, + /// FMC clock enable + FMCEN: u1, + /// CRC clock enable + CRCEN: u1, + reserved16: u9, + /// IO port H clock enable + GPIOHEN: u1, + /// I/O port A clock enable + GPIOAEN: u1, + /// I/O port B clock enable + GPIOBEN: u1, + /// I/O port C clock enable + GPIOCEN: u1, + /// I/O port D clock enable + GPIODEN: u1, + /// I/O port E clock enable + GPIOEEN: u1, + /// I/O port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// Touch sensing controller clock enable + TSCEN: u1, + reserved28: u3, + /// ADC1 and ADC2 clock enable + ADC12EN: u1, + /// ADC3 and ADC4 clock enable + ADC34EN: u1, + padding: u2, }), - reserved8: [4]u8, - /// key register - NSKEYR: u32, - /// secure key register - SECKEYR: u32, - /// option key register - OPTKEYR: u32, - reserved24: [4]u8, - /// power-down key register - PDKEYR: u32, - reserved32: [4]u8, - /// status register - NSSR: mmio.Mmio(packed struct(u32) { - /// Non-secure end of operation This bit is set by hardware when one or more memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in NSCR1). This bit is cleared by writing�1. - EOP: u1, - /// Non-secure operation error This bit is set by hardware when a memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1. - OPERR: u1, - reserved3: u1, - /// Non-secure programming error This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1. - PROGERR: u1, - /// Non-secure write protection error This bit is set by hardware when a non-secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting. - WRPERR: u1, - /// Non-secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1. - PGAERR: u1, - /// Non-secure size error This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1. - SIZERR: u1, - /// Non-secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting. - PGSERR: u1, - reserved13: u5, - /// Option write error This bit is set by hardware when the options bytes are written with an invalid configuration or when modifying options in RDP level 2.. It is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting. - OPTWERR: u1, - reserved16: u2, - /// Non-secure busy This indicates that a memory secure or non-secure operation is in progress. This bit is set at the beginning of a operation and reset when the operation finishes or when an error occurs. - BSY: u1, - /// Non-secure wait data to write This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory. - WDW: u1, - /// OEM1 key RDP lock This bit indicates that the OEM1 key read during the OBL is not virgin. When set, the OEM1 key RDP lock mechanism is active. - OEM1LOCK: u1, - /// OEM2 key RDP lock This bit indicates that the OEM2 key read during the OBL is not virgin. When set, the OEM2 key RDP lock mechanism is active. - OEM2LOCK: u1, - /// in power-down mode This bit indicates that the memory is in power-down state. It is reset when is in normal mode or being awaken. - PD: u1, - padding: u11, + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved11: u10, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + /// TIM8 Timer clock enable + TIM8EN: u1, + /// USART1 clock enable + USART1EN: u1, + /// SPI4 clock enable + SPI4EN: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + /// TIM19 timer clock enable + TIM19EN: u1, + /// TIM20 timer clock enable + TIM20EN: u1, + reserved22: u1, + /// MCU debug module clock enable + DBGMCUEN: u1, + reserved29: u6, + /// High Resolution Timer 1 clock enable + HRTIM1EN: u1, + padding: u2, }), - /// secure status register - SECSR: mmio.Mmio(packed struct(u32) { - /// Secure end of operation This bit is set by hardware when one or more memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in SECCR1). This bit is cleared by writing�1. - EOP: u1, - /// Secure operation error This bit is set by hardware when a memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1. - OPERR: u1, - reserved3: u1, - /// Secure programming error This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1. - PROGERR: u1, - /// Secure write protection error This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting. - WRPERR: u1, - /// Secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1. - PGAERR: u1, - /// Secure size error This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1. - SIZERR: u1, - /// Secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting. - PGSERR: u1, - reserved16: u8, - /// Secure busy This bit indicates that a memory secure or non-secure operation is in progress. This is set on the beginning of a operation and reset when the operation finishes or when an error occurs. - BSY: u1, - /// Secure wait data to write This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory. - WDW: u1, - padding: u14, + /// APB1 peripheral clock enable register (RCC_APB1ENR) + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + /// Timer 4 clock enable + TIM4EN: u1, + reserved4: u1, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + reserved11: u5, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI 2 clock enable + SPI2EN: u1, + /// SPI 3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART 3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB clock enable + USBEN: u1, + reserved25: u1, + /// CAN clock enable + CANEN: u1, + /// DAC2 interface clock enable + DAC2EN: u1, + reserved28: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// I2C3 clock enable + I2C3EN: u1, + padding: u1, }), - /// control register - NSCR1: mmio.Mmio(packed struct(u32) { - /// Non-secure programming - PG: u1, - /// Non-secure page erase - PER: u1, - /// Non-secure mass erase This bit triggers the non-secure mass erase (all user pages) when set. - MER: u1, - /// Non-secure page number selection These bits select the page to erase. ... Note that bit 9 is reserved on STM32WBA5xEx devices. - PNB: u7, - reserved14: u4, - /// Non-secure burst write programming mode When set, this bit selects the burst write programming mode. - BWR: u1, - reserved16: u1, - /// Non-secure operation start This bit triggers a non-secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR bit in NSSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in NSSR. - STRT: u1, - /// Options modification start This bit triggers an option bytes erase and program operation when set. This bit is write-protected with OPTLOCK.. This bit is set only by software, and is cleared when the BSY bit is cleared in NSSR. - OPTSTRT: u1, - reserved24: u6, - /// Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the NSSR is set to 1. - EOPIE: u1, - /// Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the NSSR is set to 1. - ERRIE: u1, - reserved27: u1, - /// Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. This bit is write-protected with OPTLOCK. Note: The LSE oscillator must be disabled, LSEON = 0 and LSERDY = 0, before starting OBL_LAUNCH. - OBL_LAUNCH: u1, - reserved30: u2, - /// Option lock This bit is set only. When set, the NSCR1.OPTSRT and OBL_LAUNCH bits concerning user options write access is locked. This bit is cleared by hardware after detecting the unlock sequence in OPTKEYR. The NSCR1.LOCK bit must be cleared before doing the OPTKEYR unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next reset. - OPTLOCK: u1, - /// Non-secure lock This bit is set only. When set, the NSCR1 register write access is locked. This bit is cleared by hardware after detecting the unlock sequence in NSKEYR. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. - LOCK: u1, + /// Backup domain control register (RCC_BDCR) + BDCR: mmio.Mmio(packed struct(u32) { + /// External Low Speed oscillator enable + LSEON: u1, + /// External Low Speed oscillator ready + LSERDY: u1, + /// External Low Speed oscillator bypass + LSEBYP: u1, + /// LSE oscillator drive capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + reserved8: u3, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, }), - /// secure control register - SECCR1: mmio.Mmio(packed struct(u32) { - /// Secure programming - PG: u1, - /// Secure page erase - PER: u1, - /// Secure mass erase This bit triggers the secure mass erase (all user pages) when set. - MER: u1, - /// Secure page number selection These bits select the page to erase: ... Note that bit 9 is reserved on STM32WBA5xEx devices. - PNB: u7, - reserved14: u4, - /// Secure burst write programming mode When set, this bit selects the burst write programming mode. - BWR: u1, - reserved16: u1, - /// Secure start This bit triggers a secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR in the SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in SECSR. - STRT: u1, - reserved24: u7, - /// Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in SECSR is set to 1. - EOPIE: u1, - /// Secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in SECSR is set to 1. - ERRIE: u1, - reserved29: u3, - /// memory security state invert This bit inverts the memory security state. - INV: u1, - reserved31: u1, - /// Secure lock This bit is set only. When set, the SECCR1 register is locked. It is cleared by hardware after detecting the unlock sequence in SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. - LOCK: u1, + /// Control/status register (RCC_CSR) + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low speed oscillator enable + LSION: u1, + /// Internal low speed oscillator ready + LSIRDY: u1, + reserved23: u21, + /// Reset flag of the 1.8 V domain + V18PWRRSTF: u1, + /// Remove reset flag + RMVF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, }), - /// ECC register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC fail address This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given relative to base address, from offset 0x0�0000 to 0xF�FFF0. Note that bit 19 is reserved on STM32WBAxEx devices. - ADDR_ECC: u20, - reserved22: u2, - /// System memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system memory. - SYSF_ECC: u1, - reserved24: u1, - /// ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the ECCR register is set. - ECCIE: u1, - reserved30: u5, - /// ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1. - ECCC: u1, - /// ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1. - ECCD: u1, + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// FMC reset + FMCRST: u1, + reserved16: u10, + /// IO port H reset + GPIOHRST: u1, + /// I/O port A reset + GPIOARST: u1, + /// I/O port B reset + GPIOBRST: u1, + /// I/O port C reset + GPIOCRST: u1, + /// I/O port D reset + GPIODRST: u1, + /// I/O port E reset + GPIOERST: u1, + /// I/O port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// Touch sensing controller reset + TSCRST: u1, + reserved28: u3, + /// ADC1 and ADC2 reset + ADC12RST: u1, + /// ADC3 and ADC4 reset + ADC34RST: u1, + padding: u2, }), - /// operation status register - OPSR: mmio.Mmio(packed struct(u32) { - /// Interrupted operation address This field indicates which address in the memory was accessed when reset occurred. The address is given relative to the base address, from offset 0x0�0000 to 0xF�FFF0. Note that bit 19 is reserved on STM32WBAxEx devices. - ADDR_OP: u20, - reserved22: u2, - /// Operation in system memory interrupted This bit indicates that the reset occurred during an operation in the system memory. - SYSF_OP: u1, - reserved29: u6, - /// memory operation code This field indicates which memory operation has been interrupted by a system reset: - CODE_OP: packed union { - raw: u3, - value: CODE_OP, + /// Clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// PREDIV division factor + PREDIV: packed union { + raw: u4, + value: PREDIV, }, + /// ADC1 and ADC2 prescaler + ADC12PRES: packed union { + raw: u5, + value: ADCPRES, + }, + /// ADC3 and ADC4 prescaler + ADC34PRES: packed union { + raw: u5, + value: ADCPRES, + }, + padding: u18, }), - /// control 2 register - NSCR2: mmio.Mmio(packed struct(u32) { - /// Program suspend request - PS: u1, - /// Erase suspend request - ES: u1, - padding: u30, - }), - /// secure control 2 register - SECCR2: mmio.Mmio(packed struct(u32) { - /// Program suspend request - PS: u1, - /// Erase suspend request - ES: u1, - padding: u30, - }), - /// option register - OPTR: mmio.Mmio(packed struct(u32) { - /// Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to Section�7.6.2: Readout protection (RDP) for more details. - RDP: packed union { - raw: u8, - value: RDP, + /// Clock configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SW: packed union { + raw: u2, + value: USART1SW, }, - /// BOR reset level These bits contain the VDD supply level threshold that activates/releases the reset. - BOR_LEV: packed union { - raw: u3, - value: BOR_LEV, + reserved4: u2, + /// I2C1 clock source selection + I2C1SW: packed union { + raw: u1, + value: ICSW, + }, + /// I2C2 clock source selection + I2C2SW: packed union { + raw: u1, + value: ICSW, + }, + /// HDMI CEC clock source selection + CECSW: packed union { + raw: u1, + value: CECSW, + }, + reserved8: u1, + /// Timer1 clock source selection + TIM1SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Timer8 clock source selection + TIM8SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Timer15 clock source selection + TIM15SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Timer16 clock source selection + TIM16SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Hrtim1 clock source selection + HRTIM1SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Timer17 clock source selection + TIM17SW: packed union { + raw: u1, + value: TIMSW, }, - reserved12: u1, - /// Reset generation in Stop mode - NRST_STOP: u1, - /// Reset generation in Standby mode - NRST_STDBY: u1, reserved15: u1, - /// SRAM1 erase upon system reset - SRAM1_RST: u1, - /// Independent watchdog enable selection - IWDG_SW: u1, - /// Independent watchdog counter freeze in Stop mode - IWDG_STOP: u1, - /// Independent watchdog counter freeze in Standby mode - IWDG_STDBY: u1, - /// Window watchdog selection - WWDG_SW: u1, - reserved24: u4, - /// SRAM2 parity check enable - SRAM2_PE: u1, - /// SRAM2 erase when system reset - SRAM2_RST: u1, - /// Software BOOT0 - NSWBOOT0: u1, - /// NBOOT0 option bit - NBOOT0: u1, - reserved31: u3, - /// Global TrustZone security enable - TZEN: u1, - }), - /// boot address 0 register - NSBOOTADD0R: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// Non-secure boot base address 0 This address is only used when TZEN = 0. The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: NSBOOTADD0[24:0] = 0x0100000: Boot from memory (0x0800 0000) NSBOOTADD0[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000) NSBOOTADD0[24:0] = 0x0400200: Boot from SRAM2 on S-Bus (0x2001 0000) - NSBOOTADD0: u25, - }), - /// boot address 1 register - NSBOOTADD1R: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// Non-secure boot address 1 This address is only used when TZEN = 0. The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: NSBOOTADD1[24:0] = 0x0100000: Boot from memory (0x0800 0000) NSBOOTADD1[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000) NSBOOTADD1[24:0] = 0x0400200: Boot from SRAM2 (0x2001 0000) - NSBOOTADD1: u25, - }), - /// secure boot address 0 register - SECBOOTADD0R: mmio.Mmio(packed struct(u32) { - /// Boot lock This lock is only used when TZEN = 0. When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP regression level 1 to level 0. - BOOT_LOCK: u1, - reserved7: u6, - /// Secure boot base address 0 This address is only used when TZEN = 1. The secure boot memory address can be programmed to any address in the valid address range (see Table�28: Boot space versus RDP protection) with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: SECBOOTADD0[24:0] = 0x018 0000: Boot from secure user memory (0x0C00 0000) SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS system memory (0x0FF8 0000) SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000) - SECBOOTADD0: u25, - }), - /// secure watermark register 1 - SECWMR1: mmio.Mmio(packed struct(u32) { - /// Start page of secure area This field contains the first page of the secure area. - SECWM_PSTRT: u7, - reserved16: u9, - /// End page of secure area This field contains the last page of the secure area. - SECWM_PEND: u7, - padding: u9, - }), - /// secure watermark register 2 - SECWMR2: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// End page of secure hide protection area This field contains the last page of the secure HDP area. - HDP_PEND: u7, - reserved31: u8, - /// Secure Hide protection area enable - HDPEN: u1, - }), - /// WRP area A address register - WRPAR: mmio.Mmio(packed struct(u32) { - /// WPR area A start page This field contains the first page of the WPR area A. Note that bit 6 is reserved on STM32WBAxEx devices. - WRPA_PSTRT: u7, - reserved16: u9, - /// WPR area A end page This field contains the last page of the WPR area A. Note that bit 22 is reserved on STM32WBAxEx devices. - WRPA_PEND: u7, - reserved31: u8, - /// WPR area A unlock - UNLOCK: u1, - }), - /// WRP area B address register - WRPBR: mmio.Mmio(packed struct(u32) { - /// WRP area B start page This field contains the first page of the WRP area B. Note that bit 6 is reserved on STM32WBAxEx devices. - WRPB_PSTRT: u7, - reserved16: u9, - /// WRP area B end page This field contains the last page of the WRP area B. Note that bit 22 is reserved on STM32WBAxEx devices. - WRPB_PEND: u7, - reserved31: u8, - /// WPR area B unlock - UNLOCK: u1, - }), - reserved112: [16]u8, - /// OEM1 key register 1 - OEM1KEYR1: u32, - /// OEM1 key register 2 - OEM1KEYR2: u32, - /// OEM2 key register 1 - OEM2KEYR1: u32, - /// OEM2 key register 2 - OEM2KEYR2: u32, - /// secure block based register 1 - SECBBR: [4]mmio.Mmio(packed struct(u32) { - BLOCK: u1, - padding: u31, - }), - reserved192: [48]u8, - /// secure HDP control register - SECHDPCR: mmio.Mmio(packed struct(u32) { - /// Secure HDP area access disable When set, this bit is only cleared by a system reset. - HDP_ACCDIS: u1, - padding: u31, - }), - /// privilege configuration register - PRIFCFGR: mmio.Mmio(packed struct(u32) { - /// Privileged protection for secure registers This bit is secure write protected. It can only be written by a secure privileged access when TrustZone is enabled (TZEN�=�1). - SPRIV: u1, - /// Privileged protection for non-secure registers - NSPRIV: u1, - padding: u30, - }), - reserved208: [8]u8, - /// privilege block based register 1 - PRIVBBR: [4]mmio.Mmio(packed struct(u32) { - BLOCK: u1, - padding: u31, + /// Timer20 clock source selection + TIM20SW: packed union { + raw: u1, + value: TIMSW, + }, + /// USART2 clock source selection + USART2SW: packed union { + raw: u2, + value: USARTSW, + }, + /// USART3 clock source selection + USART3SW: packed union { + raw: u2, + value: USARTSW, + }, + /// UART4 clock source selection + UART4SW: packed union { + raw: u2, + value: USARTSW, + }, + /// UART5 clock source selection + UART5SW: packed union { + raw: u2, + value: USARTSW, + }, + /// Timer2 clock source selection + TIM2SW: packed union { + raw: u1, + value: TIM2SW, + }, + /// Timer34 clock source selection + TIM34SW: packed union { + raw: u1, + value: TIMSW, + }, + padding: u6, }), }; }; - pub const fmc_v4 = struct { - pub const ACCMOD = enum(u2) { - /// Access mode A - A = 0x0, - /// Access mode B - B = 0x1, - /// Access mode C - C = 0x2, - /// Access mode D - D = 0x3, + pub const rcc_f3v2 = struct { + pub const ADCPRE = enum(u2) { + /// PCLK divided by 2 + Div2 = 0x0, + /// PCLK divided by 4 + Div4 = 0x1, + /// PCLK divided by 6 + Div6 = 0x2, + /// PCLK divided by 8 + Div8 = 0x3, }; - pub const CAS = enum(u2) { - /// 1 cycle - Clocks1 = 0x1, - /// 2 cycles - Clocks2 = 0x2, - /// 3 cycles - Clocks3 = 0x3, + pub const ADCPRES = enum(u5) { + /// PLL clock not divided + Div1 = 0x10, + /// PLL clock divided by 2 + Div2 = 0x11, + /// PLL clock divided by 4 + Div4 = 0x12, + /// PLL clock divided by 6 + Div6 = 0x13, + /// PLL clock divided by 8 + Div8 = 0x14, + /// PLL clock divided by 10 + Div10 = 0x15, + /// PLL clock divided by 12 + Div12 = 0x16, + /// PLL clock divided by 16 + Div16 = 0x17, + /// PLL clock divided by 32 + Div32 = 0x18, + /// PLL clock divided by 64 + Div64 = 0x19, + /// PLL clock divided by 128 + Div128 = 0x1a, + /// PLL clock divided by 256 + Div256 = 0x1b, _, }; - pub const CBURSTRW = enum(u1) { - /// Write operations are always performed in Asynchronous mode. - Asynchronous = 0x0, - /// Write operations are performed in Synchronous mode. - Synchronous = 0x1, + pub const CECSW = enum(u1) { + /// HSI clock divided by 244 selected as CEC clock source + HSI_DIV_244 = 0x0, + /// LSE clock selected as CEC clock source + LSE = 0x1, }; - pub const CPSIZE = enum(u3) { - /// No burst split when crossing page boundary - NoBurstSplit = 0x0, - /// 128 bytes CRAM page size - Bytes128 = 0x1, - /// 256 bytes CRAM page size - Bytes256 = 0x2, - /// 512 bytes CRAM page size - Bytes512 = 0x3, - /// 1024 bytes CRAM page size - Bytes1024 = 0x4, + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, _, }; - pub const ECCPS = enum(u3) { - /// ECC page size 256 bytes - Bytes256 = 0x0, - /// ECC page size 512 bytes - Bytes512 = 0x1, - /// ECC page size 1024 bytes - Bytes1024 = 0x2, - /// ECC page size 2048 bytes - Bytes2048 = 0x3, - /// ECC page size 4096 bytes - Bytes4096 = 0x4, - /// ECC page size 8192 bytes - Bytes8192 = 0x5, - _, + pub const ICSW = enum(u1) { + /// HSI clock selected as I2C clock source + HSI = 0x0, + /// SYSCLK clock selected as I2C clock source + SYS = 0x1, }; - pub const MODE = enum(u3) { - /// Normal Mode - Normal = 0x0, - /// Clock Configuration Enable - ClockConfigurationEnable = 0x1, - /// PALL (All Bank Precharge) command - PALL = 0x2, - /// Auto-refresh command - AutoRefreshCommand = 0x3, - /// Load Mode Resgier - LoadModeRegister = 0x4, - /// Self-refresh command - SelfRefreshCommand = 0x5, - /// Power-down command - PowerDownCommand = 0x6, - _, + pub const ISSRC = enum(u1) { + /// System clock used as I2S clock source + SYS = 0x0, + /// External clock mapped on the I2S_CKIN pin used as I2S clock source + CKIN = 0x1, }; - pub const MODES = enum(u2) { - /// Normal Mode - Normal = 0x0, - /// Self-refresh mode - SelfRefresh = 0x1, - /// Power-down mode - PowerDown = 0x2, - _, + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium high driving capability + MediumHigh = 0x1, + /// Medium low driving capability + MediumLow = 0x2, + /// High driving capability + High = 0x3, }; - pub const MTYP = enum(u2) { - /// SRAM memory type - SRAM = 0x0, - /// PSRAM (CRAM) memory type - PSRAM = 0x1, - /// NOR Flash/OneNAND Flash - Flash = 0x2, - _, + pub const MCOPRE = enum(u3) { + /// MCO is divided by 1 + Div1 = 0x0, + /// MCO is divided by 2 + Div2 = 0x1, + /// MCO is divided by 4 + Div4 = 0x2, + /// MCO is divided by 8 + Div8 = 0x3, + /// MCO is divided by 16 + Div16 = 0x4, + /// MCO is divided by 32 + Div32 = 0x5, + /// MCO is divided by 64 + Div64 = 0x6, + /// MCO is divided by 128 + Div128 = 0x7, }; - pub const MWID = enum(u2) { - /// Memory data bus width 8 bits - Bits8 = 0x0, - /// Memory data bus width 16 bits - Bits16 = 0x1, - /// Memory data bus width 32 bits - Bits32 = 0x2, + pub const MCOSEL = enum(u3) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// Internal low speed (LSI) oscillator clock selected + LSI = 0x2, + /// External low speed (LSE) oscillator clock selected + LSE = 0x3, + /// System clock selected + SYS = 0x4, + /// Internal RC 8 MHz (HSI) oscillator clock selected + HSI = 0x5, + /// External 4-32 MHz (HSE) oscillator clock selected + HSE = 0x6, + /// PLL clock selected (divided by 1 or 2, depending en PLLMCODIV) + PLL = 0x7, _, }; - pub const NB = enum(u1) { - /// Two internal Banks - NB2 = 0x0, - /// Four internal Banks - NB4 = 0x1, - }; - - pub const NC = enum(u2) { - /// 8 bits - Bits8 = 0x0, - /// 9 bits - Bits9 = 0x1, - /// 10 bits - Bits10 = 0x2, - /// 11 bits - Bits11 = 0x3, + pub const PLLMCODIV = enum(u1) { + /// PLL is divided by 2 for MCO + Div2 = 0x0, + /// PLL is not divided for MCO + Div1 = 0x1, }; - pub const NR = enum(u2) { - /// 11 bits - Bits11 = 0x0, - /// 12 bits - Bits12 = 0x1, - /// 13 bits - Bits13 = 0x2, + pub const PLLMUL = enum(u4) { + /// PLL input clock x2 + Mul2 = 0x0, + /// PLL input clock x3 + Mul3 = 0x1, + /// PLL input clock x4 + Mul4 = 0x2, + /// PLL input clock x5 + Mul5 = 0x3, + /// PLL input clock x6 + Mul6 = 0x4, + /// PLL input clock x7 + Mul7 = 0x5, + /// PLL input clock x8 + Mul8 = 0x6, + /// PLL input clock x9 + Mul9 = 0x7, + /// PLL input clock x10 + Mul10 = 0x8, + /// PLL input clock x11 + Mul11 = 0x9, + /// PLL input clock x12 + Mul12 = 0xa, + /// PLL input clock x13 + Mul13 = 0xb, + /// PLL input clock x14 + Mul14 = 0xc, + /// PLL input clock x15 + Mul15 = 0xd, + /// PLL input clock x16 + Mul16 = 0xe, _, }; - pub const PTYP = enum(u1) { - /// NAND flash - NAND = 0x1, - _, + pub const PLLSRC = enum(u1) { + /// HSI divided by 2 selected as PLL input clock + HSI_Div2 = 0x0, + /// HSE divided by PREDIV selected as PLL input clock + HSE_Div_PREDIV = 0x1, }; - pub const PWID = enum(u2) { - /// External memory device width 8 bits - Bits8 = 0x0, - /// External memory device width 16 bits - Bits16 = 0x1, - _, + pub const PLLXTPRE = enum(u1) { + /// HSE clock not divided + Div1 = 0x0, + /// HSE clock divided by 2 + Div2 = 0x1, }; - pub const RPIPE = enum(u2) { - /// No clock cycle delay - NoDelay = 0x0, - /// One clock cycle delay - Clocks1 = 0x1, - /// Two clock cycles delay - Clocks2 = 0x2, - _, + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, }; - pub const SDCLK = enum(u2) { - /// SDCLK clock disabled - Disabled = 0x0, - /// SDCLK period = 2 x HCLK period - Div2 = 0x2, - /// SDCLK period = 3 x HCLK period - Div3 = 0x3, + pub const PREDIV = enum(u4) { + /// PREDIV input clock not divided + Div1 = 0x0, + /// PREDIV input clock divided by 2 + Div2 = 0x1, + /// PREDIV input clock divided by 3 + Div3 = 0x2, + /// PREDIV input clock divided by 4 + Div4 = 0x3, + /// PREDIV input clock divided by 5 + Div5 = 0x4, + /// PREDIV input clock divided by 6 + Div6 = 0x5, + /// PREDIV input clock divided by 7 + Div7 = 0x6, + /// PREDIV input clock divided by 8 + Div8 = 0x7, + /// PREDIV input clock divided by 9 + Div9 = 0x8, + /// PREDIV input clock divided by 10 + Div10 = 0x9, + /// PREDIV input clock divided by 11 + Div11 = 0xa, + /// PREDIV input clock divided by 12 + Div12 = 0xb, + /// PREDIV input clock divided by 13 + Div13 = 0xc, + /// PREDIV input clock divided by 14 + Div14 = 0xd, + /// PREDIV input clock divided by 15 + Div15 = 0xe, + /// PREDIV input clock divided by 16 + Div16 = 0xf, + }; + + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, + }; + + pub const SW = enum(u2) { + /// HSI oscillator used as system clock + HSI = 0x0, + /// HSE oscillator used as system clock + HSE = 0x1, + /// PLL used as system clock + PLL1_P = 0x2, _, }; - pub const WAITCFG = enum(u1) { - /// NWAIT signal is active one data cycle before wait state - BeforeWaitState = 0x0, - /// NWAIT signal is active during wait state - DuringWaitState = 0x1, + pub const TIM2SW = enum(u1) { + /// PCLK2 clock (doubled frequency when prescaled) + PCLK1_TIM = 0x0, + /// PLL vco output (running up to 144 MHz) + PLL1_P = 0x1, }; - pub const WAITPOL = enum(u1) { - /// NWAIT active low - ActiveLow = 0x0, - /// NWAIT active high - ActiveHigh = 0x1, + pub const TIMSW = enum(u1) { + /// PCLK2 clock (doubled frequency when prescaled) + PCLK2_TIM = 0x0, + /// PLL vco output (running up to 144 MHz) + PLL1_P = 0x1, }; - /// Flexible memory controller. - pub const FMC = extern struct { - NOR_PSRAM: u32, - reserved128: [124]u8, - NAND: u32, - reserved320: [188]u8, - SDRAM: u32, + pub const USART1SW = enum(u2) { + /// PCLK selected as USART clock source + PCLK2 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const NAND = extern struct { - /// NAND Flash control registers. - PCR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Wait feature enable bit Enables the Wait feature for the NAND Flash memory bank:. - PWAITEN: u1, - /// NAND Flash memory bank enable bit Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. - PBKEN: u1, - /// Memory type Defines the type of device attached to the corresponding memory bank:. - PTYP: packed union { - raw: u1, - value: PTYP, + pub const USARTSW = enum(u2) { + /// PCLK selected as USART clock source + PCLK1 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, + }; + + pub const USBPRE = enum(u1) { + /// PLL clock is divided by 1.5 + Div1_5 = 0x0, + /// PLL clock is not divided + Div1 = 0x1, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal High Speed clock enable + HSION: u1, + /// Internal High Speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal High Speed clock trimming + HSITRIM: u5, + /// Internal High Speed clock Calibration + HSICAL: u8, + /// External High Speed clock enable + HSEON: u1, + /// External High Speed clock ready flag + HSERDY: u1, + /// External High Speed clock Bypass + HSEBYP: u1, + /// Clock Security System enable + CSSON: u1, + reserved24: u4, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding: u6, + }), + /// Clock configuration register (RCC_CFGR) + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock Switch + SW: packed union { + raw: u2, + value: SW, }, - /// Data bus width Defines the external memory device width. - PWID: packed union { + /// System Clock Switch Status + SWS: packed union { raw: u2, - value: PWID, + value: SW, }, - /// ECC computation logic enable bit. - ECCEN: u1, - reserved9: u2, - /// CLE to RE delay Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). Time is t_clr = (TCLR + SET + 2) � THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space. - TCLR: u4, - /// ALE to RE delay Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). Time is: t_ar = (TAR + SET + 2) � THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space. - TAR: u4, - /// ECC page size Defines the page size for the extended ECC:. - ECCPS: packed union { + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// APB Low speed prescaler (APB1) + PPRE1: packed union { raw: u3, - value: ECCPS, + value: PPRE, }, - padding: u12, - }), - /// FIFO status and interrupt register. - SR: mmio.Mmio(packed struct(u32) { - /// Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it is set. - IRS: u1, - /// Interrupt high-level status The flag is set by hardware and reset by software. - ILS: u1, - /// Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it is set. - IFS: u1, - /// Interrupt rising edge detection enable bit. - IREN: u1, - /// Interrupt high-level detection enable bit. - ILEN: u1, - /// Interrupt falling edge detection enable bit. - IFEN: u1, - /// FIFO empty Read-only bit that provides the status of the FIFO. - FEMPT: u1, - padding: u25, - }), - /// Common memory space timing register. - PMEM: mmio.Mmio(packed struct(u32) { - /// Common memory x setup time Defines the number of HCLK (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space on socket x:. - MEMSET: u8, - /// Common memory wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space on socket. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:. - MEMWAIT: u8, - /// Common memory hold time Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write accesses) after the command is deasserted (NWE, NOE), for NAND Flash read or write access to common memory space on socket x:. - MEMHOLD: u8, - /// Common memory x data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space on socket. This is only valid for write transactions:. - MEMHIZ: u8, - }), - /// Attribute memory space timing register. - PATT: mmio.Mmio(packed struct(u32) { - /// Attribute memory setup time Defines the number of HCLK (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket:. - ATTSET: u8, - /// Attribute memory wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:. - ATTWAIT: u8, - /// Attribute memory hold time Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write access) after the command deassertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket:. - ATTHOLD: u8, - /// Attribute memory data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:. - ATTHIZ: u8, - }), - reserved20: [4]u8, - /// ECC result registers. - ECCR: u32, - }; - - pub const NOR_PSRAM = extern struct { - /// SRAM/NOR-Flash chip-select control register for bank 1. - BCR1: mmio.Mmio(packed struct(u32) { - reserved20: u20, - /// Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.). - CCLKEN: u1, - /// Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. - WFDIS: u1, - padding: u10, - }), - /// SRAM/NOR-Flash chip-select timing register for bank 1. - BTR: mmio.Mmio(packed struct(u32) { - reserved20: u20, - /// Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula). - CLKDIV: u4, - /// (see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don't care. - DATLAT: u4, - padding: u4, - }), - /// SRAM/NOR-Flash chip-select control register for bank 2. - BCR: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. - MBKEN: u1, - /// Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:. - MUXEN: u1, - /// Memory type Defines the type of external memory attached to the corresponding memory bank. - MTYP: packed union { - raw: u2, - value: MTYP, + /// APB high speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, }, - /// Memory data bus width Defines the external memory device width, valid for all type of memories. - MWID: packed union { + /// ADC prescaler + ADCPRE: packed union { raw: u2, - value: MWID, + value: ADCPRE, }, - /// Flash access enable Enables NOR Flash memory access operations. - FACCEN: u1, - reserved8: u1, - /// Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode. - BURSTEN: u1, - /// Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. - WAITPOL: packed union { + /// PLL entry clock source + PLLSRC: packed union { raw: u1, - value: WAITPOL, + value: PLLSRC, }, - reserved11: u1, - /// Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. - WAITCFG: packed union { + /// HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products. + PLLXTPRE: packed union { raw: u1, - value: WAITCFG, + value: PLLXTPRE, }, - /// Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. - WREN: u1, - /// Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. - WAITEN: u1, - /// Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). - EXTMOD: u1, - /// Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. - ASYNCWAIT: u1, - /// CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved. - CPSIZE: packed union { + /// PLL Multiplication Factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, + }, + /// USB prescaler + USBPRE: packed union { + raw: u1, + value: USBPRE, + }, + /// I2S external clock source selection + I2SSRC: packed union { + raw: u1, + value: ISSRC, + }, + /// Microcontroller clock output + MCOSEL: packed union { raw: u3, - value: CPSIZE, + value: MCOSEL, }, - /// Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. - CBURSTRW: packed union { + reserved28: u1, + /// Microcontroller Clock Output Prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, + }, + /// Do not divide PLL to MCO + PLLMCODIV: packed union { raw: u1, - value: CBURSTRW, + value: PLLMCODIV, }, - /// Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.). - CCLKEN: u1, - /// Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. - WFDIS: u1, - /// Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low. - NBLSET: u2, - reserved31: u7, - /// FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. + }), + /// Clock interrupt register (RCC_CIR) + CIR: mmio.Mmio(packed struct(u32) { + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + reserved7: u2, + /// Clock Security System Interrupt flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + reserved16: u3, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + reserved23: u2, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, + }), + /// APB2 peripheral reset register (RCC_APB2RSTR) + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// SYSCFG and COMP reset + SYSCFGRST: u1, + reserved11: u10, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + /// SPI4 reset + SPI4RST: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + /// TIM19 timer reset + TIM19RST: u1, + /// TIM20 timer reset + TIM20RST: u1, + reserved22: u1, + /// Debug MCU reset + DBGMCURST: u1, + reserved29: u6, + /// High Resolution Timer1 reset + HRTIM1RST: u1, + padding: u2, + }), + /// APB1 peripheral reset register (RCC_APB1RSTR) + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + /// Timer 14 reset + TIM4RST: u1, + reserved4: u1, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + reserved11: u5, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved17: u1, + /// USART 2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// UART 4 reset + UART4RST: u1, + /// UART 5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB reset + USBRST: u1, + reserved25: u1, + /// CAN reset + CANRST: u1, + /// DAC2 interface reset + DAC2RST: u1, + reserved28: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// I2C3 reset + I2C3RST: u1, + padding: u1, + }), + /// AHB Peripheral Clock enable register (RCC_AHBENR) + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock enable + SRAMEN: u1, + reserved4: u1, + /// FLASH clock enable + FLASHEN: u1, + /// FMC clock enable FMCEN: u1, + /// CRC clock enable + CRCEN: u1, + reserved16: u9, + /// IO port H clock enable + GPIOHEN: u1, + /// I/O port A clock enable + GPIOAEN: u1, + /// I/O port B clock enable + GPIOBEN: u1, + /// I/O port C clock enable + GPIOCEN: u1, + /// I/O port D clock enable + GPIODEN: u1, + /// I/O port E clock enable + GPIOEEN: u1, + /// I/O port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// Touch sensing controller clock enable + TSCEN: u1, + reserved28: u3, + /// ADC1 and ADC2 clock enable + ADC12EN: u1, + /// ADC3 and ADC4 clock enable + ADC34EN: u1, + padding: u2, }), - reserved32: [20]u8, - /// PSRAM chip select counter register. - PCSCNTR: mmio.Mmio(packed struct(u32) { - /// Chip select counter. These bits are written by software to define the maximum chip select low pulse duration. It is expressed in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous accesses. The counter is disabled if the programmed value is 0. - CSCOUNT: u16, - /// Counter Bank 1 enable This bit enables the chip select counter for PSRAM/NOR Bank 1. - CNTBEN: u1, - padding: u15, + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved11: u10, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + /// TIM8 Timer clock enable + TIM8EN: u1, + /// USART1 clock enable + USART1EN: u1, + /// SPI4 clock enable + SPI4EN: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + /// TIM19 timer clock enable + TIM19EN: u1, + /// TIM20 timer clock enable + TIM20EN: u1, + reserved22: u1, + /// MCU debug module clock enable + DBGMCUEN: u1, + reserved29: u6, + /// High Resolution Timer 1 clock enable + HRTIM1EN: u1, + padding: u2, }), - reserved260: [224]u8, - /// SRAM/NOR-Flash write timing registers 1. - BWTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. - ADDSET: u4, - /// Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. - ADDHLD: u4, - /// Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ... - DATAST: u8, - /// Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... - BUSTURN: u4, - reserved28: u8, - /// Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. - ACCMOD: packed union { - raw: u2, - value: ACCMOD, - }, - /// Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:. - DATAHLD: u2, + /// APB1 peripheral clock enable register (RCC_APB1ENR) + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + /// Timer 4 clock enable + TIM4EN: u1, + reserved4: u1, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + reserved11: u5, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI 2 clock enable + SPI2EN: u1, + /// SPI 3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART 3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB clock enable + USBEN: u1, + reserved25: u1, + /// CAN clock enable + CANEN: u1, + /// DAC2 interface clock enable + DAC2EN: u1, + reserved28: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// I2C3 clock enable + I2C3EN: u1, + padding: u1, }), - }; - - pub const SDRAM = extern struct { - /// SDRAM control registers 1. - SDCR: [2]mmio.Mmio(packed struct(u32) { - /// Number of column address bits These bits define the number of bits of a column address. - NC: packed union { + /// Backup domain control register (RCC_BDCR) + BDCR: mmio.Mmio(packed struct(u32) { + /// External Low Speed oscillator enable + LSEON: u1, + /// External Low Speed oscillator ready + LSERDY: u1, + /// External Low Speed oscillator bypass + LSEBYP: u1, + /// LSE oscillator drive capability + LSEDRV: packed union { raw: u2, - value: NC, + value: LSEDRV, }, - /// Number of row address bits These bits define the number of bits of a row address. - NR: packed union { + reserved8: u3, + /// RTC clock source selection + RTCSEL: packed union { raw: u2, - value: NR, + value: RTCSEL, }, - /// Memory data bus width. These bits define the memory device width. - MWID: packed union { + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, + }), + /// Control/status register (RCC_CSR) + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low speed oscillator enable + LSION: u1, + /// Internal low speed oscillator ready + LSIRDY: u1, + reserved23: u21, + /// Reset flag of the 1.8 V domain + V18PWRRSTF: u1, + /// Remove reset flag + RMVF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// FMC reset + FMCRST: u1, + reserved16: u10, + /// IO port H reset + GPIOHRST: u1, + /// I/O port A reset + GPIOARST: u1, + /// I/O port B reset + GPIOBRST: u1, + /// I/O port C reset + GPIOCRST: u1, + /// I/O port D reset + GPIODRST: u1, + /// I/O port E reset + GPIOERST: u1, + /// I/O port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// Touch sensing controller reset + TSCRST: u1, + reserved28: u3, + /// ADC1 and ADC2 reset + ADC12RST: u1, + /// ADC3 and ADC4 reset + ADC34RST: u1, + padding: u2, + }), + /// Clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// PREDIV division factor + PREDIV: packed union { + raw: u4, + value: PREDIV, + }, + /// ADC1 and ADC2 prescaler + ADC12PRES: packed union { + raw: u5, + value: ADCPRES, + }, + /// ADC3 and ADC4 prescaler + ADC34PRES: packed union { + raw: u5, + value: ADCPRES, + }, + padding: u18, + }), + /// Clock configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SW: packed union { raw: u2, - value: MWID, + value: USART1SW, }, - /// Number of internal banks This bit sets the number of internal banks. - NB: packed union { + reserved4: u2, + /// I2C1 clock source selection + I2C1SW: packed union { raw: u1, - value: NB, + value: ICSW, }, - /// CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles. - CAS: packed union { - raw: u2, - value: CAS, + /// I2C2 clock source selection + I2C2SW: packed union { + raw: u1, + value: ICSW, }, - /// Write protection This bit enables write mode access to the SDRAM bank. - WP: u1, - /// SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register are don’t care. - SDCLK: packed union { + /// HDMI CEC clock source selection + CECSW: packed union { + raw: u1, + value: CECSW, + }, + reserved8: u1, + /// Timer1 clock source selection + TIM1SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Timer8 clock source selection + TIM8SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Timer15 clock source selection + TIM15SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Timer16 clock source selection + TIM16SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Hrtim1 clock source selection + HRTIM1SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Timer17 clock source selection + TIM17SW: packed union { + raw: u1, + value: TIMSW, + }, + reserved15: u1, + /// Timer20 clock source selection + TIM20SW: packed union { + raw: u1, + value: TIMSW, + }, + /// USART2 clock source selection + USART2SW: packed union { raw: u2, - value: SDCLK, + value: USARTSW, }, - /// Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is don’t care. - RBURST: u1, - /// Read pipe These bits define the delay, in clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only. - RPIPE: packed union { + /// USART3 clock source selection + USART3SW: packed union { raw: u2, - value: RPIPE, + value: USARTSW, }, - padding: u17, - }), - /// SDRAM timing registers 1. - SDTR: [2]mmio.Mmio(packed struct(u32) { - /// Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. .... - TMRD: u4, - /// Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device. - TXSR: u4, - /// Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. .... - TRAS: u4, - /// Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are don’t care. - TRC: u4, - /// Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: Note: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Note: Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device. Note: If only one SDRAM device is used, the TWR timing must be kept at reset value (0xF) for the not used bank. - TWR: u4, - /// Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are don’t care. - TRP: u4, - /// Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. .... - TRCD: u4, - padding: u4, - }), - /// SDRAM Command Mode register. - SDCMR: mmio.Mmio(packed struct(u32) { - /// Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with it’s associated CTB bit set, the other CTB bit of the the unused bank must be kept to 0. - MODE: packed union { - raw: u3, - value: MODE, + /// UART4 clock source selection + UART4SW: packed union { + raw: u2, + value: USARTSW, }, - /// Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. - CTB: u1, - reserved5: u1, - /// Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = ‘011’. .... - NRFS: u4, - /// Mode Register definition This 13-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. - MRD: u13, - padding: u10, - }), - /// SDRAM refresh timer register. - SDRTR: mmio.Mmio(packed struct(u32) { - /// Clear Refresh error flag This bit is used to clear the Refresh Error Flag (RE) in the Status Register. - CRE: u1, - /// Refresh Timer Count This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29). Refresh rate = (COUNT + 1) x SDRAM frequency clock COUNT = (SDRAM refresh period / Number of rows) - 20. - COUNT: u13, - /// RES Interrupt Enable. - REIE: u1, - padding: u17, - }), - /// SDRAM status register. - SDSR: mmio.Mmio(packed struct(u32) { - /// Refresh error flag An interrupt is generated if REIE = 1 and RE = 1. - RE: u1, - /// Status Mode for Bank 1 This bit defines the Status Mode of SDRAM Bank 1. - MODES: packed union { + /// UART5 clock source selection + UART5SW: packed union { raw: u2, - value: MODES, + value: USARTSW, }, - reserved5: u2, - /// Busy status This bit defines the status of the SDRAM controller after a Command Mode request 1; SDRAM Controller is not ready to accept a new request. - BUSY: u1, - padding: u26, + /// Timer2 clock source selection + TIM2SW: packed union { + raw: u1, + value: TIM2SW, + }, + /// Timer34 clock source selection + TIM34SW: packed union { + raw: u1, + value: TIMSW, + }, + padding: u6, }), }; }; - pub const tamp_l5 = struct { - /// Tamper and backup registers - pub const TAMP = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// TAMPE - TAMPE: u1, - reserved16: u15, - /// ITAMPE - ITAMPE: u1, - padding: u15, - }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Tamper X no erase - TAMPNOER: u1, - reserved16: u15, - /// Tamper X mask - TAMPMSK: u1, - reserved23: u6, - /// BKERASE - BKERASE: u1, - /// Active level for tamper X input - TAMPTRG: u1, - padding: u7, - }), - /// control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Internal Tamper X no erase - ITAMPNOER: u1, - padding: u31, - }), - /// TAMP filter control register - FLTCR: mmio.Mmio(packed struct(u32) { - /// TAMPFREQ - TAMPFREQ: u3, - /// TAMPFLT - TAMPFLT: u2, - /// TAMPPRCH - TAMPPRCH: u2, - /// TAMPPUDIS - TAMPPUDIS: u1, - padding: u24, - }), - /// TAMP active tamper control register 1 - ATCR1: mmio.Mmio(packed struct(u32) { - /// TAMPAM - TAMPAM: u1, - reserved8: u7, - /// ATOSEL - ATOSEL: u2, - reserved16: u6, - /// ATCKSEL - ATCKSEL: u2, - reserved24: u6, - /// ATPER - ATPER: u2, - reserved30: u4, - /// ATOSHARE - ATOSHARE: u1, - /// FLTEN - FLTEN: u1, - }), - /// TAMP active tamper seed register - ATSEEDR: mmio.Mmio(packed struct(u32) { - /// Pseudo-random generator seed value - SEED: u32, - }), - /// TAMP active tamper output register - ATOR: mmio.Mmio(packed struct(u32) { - /// Pseudo-random generator value - PRNG: u8, - reserved14: u6, - /// Seed running flag - SEEDF: u1, - /// Active tamper initialization status - INITS: u1, - padding: u16, - }), - /// TAMP active tamper control register 2 - ATCR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// ATOSEL - ATOSEL: u3, - padding: u21, - }), - /// TAMP secure mode register - SMCR: mmio.Mmio(packed struct(u32) { - /// Backup registers read/write protection offset - BKPRWDPROT: u8, - reserved16: u8, - /// Backup registers write protection offset - BKPWDPROT: u8, - reserved31: u7, - /// Tamper protection - TAMPDPROT: u1, - }), - /// TAMP privilege mode control register - PRIVCR: mmio.Mmio(packed struct(u32) { - reserved29: u29, - /// Backup registers zone 1 privilege protection - BKPRWPRIV: u1, - /// Backup registers zone 2 privilege protection - BKPWPRIV: u1, - /// Tamper privilege protection - TAMPPRIV: u1, - }), - reserved44: [4]u8, - /// TAMP interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt enable - TAMPIE: u1, - reserved16: u15, - /// Internal tamper X interrupt enable - ITAMPIE: u1, - padding: u15, - }), - /// TAMP status register - SR: mmio.Mmio(packed struct(u32) { - /// Tamper X detection flag - TAMPF: u1, - reserved16: u15, - /// Internal tamper X detection flag - ITAMPF: u1, - padding: u15, - }), - /// TAMP masked interrupt status register - MISR: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt masked flag - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X interrupt masked flag - ITAMPMF: u1, - padding: u15, - }), - /// TAMP secure masked interrupt status register - SMISR: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt masked flag - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X interrupt masked flag - ITAMPMF: u1, - padding: u15, - }), - /// TAMP status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear tamper X detection flag - CTAMPF: u1, - reserved16: u15, - /// Clear internal tamper X detection flag - CITAMPF: u1, - padding: u15, - }), - /// TAMP monotonic counter register - COUNTR: mmio.Mmio(packed struct(u32) { - /// COUNT - COUNT: u32, - }), - reserved80: [12]u8, - /// TAMP configuration register - CFGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// TMONEN - TMONEN: u1, - /// VMONEN - VMONEN: u1, - /// WUTMONEN - WUTMONEN: u1, - padding: u28, - }), - reserved256: [172]u8, - /// TAMP backup register - BKPR: [32]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, - }), - }; - }; - - pub const exti_u0 = struct { - /// External interrupt/event controller - pub const EXTI = extern struct { - /// Rising Trigger selection register - RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Falling Trigger selection register - FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Software interrupt event register - SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Rising pending register - RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Falling pending register - FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - reserved96: [76]u8, - /// Configuration register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u8, - padding: u24, - }), - reserved128: [16]u8, - /// Interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Event mask register - EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), + pub const rcc_f3v3 = struct { + pub const ADCPRE = enum(u2) { + /// PCLK divided by 2 + Div2 = 0x0, + /// PCLK divided by 4 + Div4 = 0x1, + /// PCLK divided by 6 + Div6 = 0x2, + /// PCLK divided by 8 + Div8 = 0x3, }; - }; - pub const adc_l0 = struct { - pub const ALIGN = enum(u1) { - /// Right alignment - Right = 0x0, - /// Left alignment - Left = 0x1, + pub const ADCPRES = enum(u5) { + /// PLL clock not divided + Div1 = 0x10, + /// PLL clock divided by 2 + Div2 = 0x11, + /// PLL clock divided by 4 + Div4 = 0x12, + /// PLL clock divided by 6 + Div6 = 0x13, + /// PLL clock divided by 8 + Div8 = 0x14, + /// PLL clock divided by 10 + Div10 = 0x15, + /// PLL clock divided by 12 + Div12 = 0x16, + /// PLL clock divided by 16 + Div16 = 0x17, + /// PLL clock divided by 32 + Div32 = 0x18, + /// PLL clock divided by 64 + Div64 = 0x19, + /// PLL clock divided by 128 + Div128 = 0x1a, + /// PLL clock divided by 256 + Div256 = 0x1b, + _, }; - pub const AWDSGL = enum(u1) { - /// Analog watchdog enabled on all channels - AllChannels = 0x0, - /// Analog watchdog enabled on a single channel - SingleChannel = 0x1, + pub const CECSW = enum(u1) { + /// HSI clock divided by 244 selected as CEC clock source + HSI_DIV_244 = 0x0, + /// LSE clock selected as CEC clock source + LSE = 0x1, }; - pub const CKMODE = enum(u2) { - /// Asynchronous clock mode - ADCCLK = 0x0, - /// Synchronous clock mode (PCLK/2) - PCLK_Div2 = 0x1, - /// Sychronous clock mode (PCLK/4) - PCLK_Div4 = 0x2, - /// Synchronous clock mode (PCLK) - PCLK = 0x3, + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, + _, }; - pub const DMACFG = enum(u1) { - /// DMA One Shot mode selected - OneShot = 0x0, - /// DMA Circular mode selected - Circular = 0x1, + pub const ICSW = enum(u1) { + /// HSI clock selected as I2C clock source + HSI = 0x0, + /// SYSCLK clock selected as I2C clock source + SYS = 0x1, }; - pub const EXTEN = enum(u2) { - /// Trigger detection disabled - Disabled = 0x0, - /// Trigger detection on the rising edge - RisingEdge = 0x1, - /// Trigger detection on the falling edge - FallingEdge = 0x2, - /// Trigger detection on both the rising and falling edges - BothEdges = 0x3, + pub const ISSRC = enum(u1) { + /// System clock used as I2S clock source + SYS = 0x0, + /// External clock mapped on the I2S_CKIN pin used as I2S clock source + CKIN = 0x1, }; - pub const OVRMOD = enum(u1) { - /// ADC_DR register is preserved with the old data when an overrun is detected - Preserved = 0x0, - /// ADC_DR register is overwritten with the last conversion result when an overrun is detected - Overwritten = 0x1, + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium high driving capability + MediumHigh = 0x1, + /// Medium low driving capability + MediumLow = 0x2, + /// High driving capability + High = 0x3, }; - pub const PRESC = enum(u4) { - /// Input ADC clock not divided. + pub const MCOPRE = enum(u3) { + /// MCO is divided by 1 Div1 = 0x0, - /// Input ADC clock divided by 2. + /// MCO is divided by 2 Div2 = 0x1, - /// Input ADC clock divided by 4. + /// MCO is divided by 4 Div4 = 0x2, - /// Input ADC clock divided by 6. - Div6 = 0x3, - /// Input ADC clock divided by 8. - Div8 = 0x4, - /// Input ADC clock divided by 10. - Div10 = 0x5, - /// Input ADC clock divided by 12. - Div12 = 0x6, - /// Input ADC clock divided by 16. - Div16 = 0x7, - /// Input ADC clock divided by 32. - Div32 = 0x8, - /// Input ADC clock divided by 64. - Div64 = 0x9, - /// Input ADC clock divided by 128. - Div128 = 0xa, - /// Input ADC clock divided by 256. - Div256 = 0xb, - _, - }; - - pub const RES = enum(u2) { - /// 12-bit (14 ADCCLK cycles) - Bits12 = 0x0, - /// 10-bit (13 ADCCLK cycles) - Bits10 = 0x1, - /// 8-bit (11 ADCCLK cycles) - Bits8 = 0x2, - /// 6-bit (9 ADCCLK cycles) - Bits6 = 0x3, - }; - - pub const SAMPLE_TIME = enum(u3) { - /// 1.5 cycles - Cycles1_5 = 0x0, - /// 3.5 cycles - Cycles3_5 = 0x1, - /// 7.5 cycles - Cycles7_5 = 0x2, - /// 12.5 cycles - Cycles12_5 = 0x3, - /// 19.5 cycles - Cycles19_5 = 0x4, - /// 39.5 cycles - Cycles39_5 = 0x5, - /// 79.5 cycles - Cycles79_5 = 0x6, - /// 160.5 cycles - Cycles160_5 = 0x7, - }; - - pub const SCANDIR = enum(u1) { - /// Upward scan (from CHSEL0 to CHSEL18) - Upward = 0x0, - /// Backward scan (from CHSEL18 to CHSEL0) - Backward = 0x1, - }; - - /// Analog-to-digital converter - pub const ADC = extern struct { - /// interrupt and status register - ISR: mmio.Mmio(packed struct(u32) { - /// ADC ready - ADRDY: u1, - /// End of sampling flag - EOSMP: u1, - /// End of conversion flag - EOC: u1, - /// End of sequence flag - EOS: u1, - /// ADC overrun - OVR: u1, - reserved7: u2, - /// Analog watchdog flag - AWD: u1, - reserved11: u3, - /// End Of Calibration flag - EOCAL: u1, - padding: u20, - }), - /// interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// ADC ready interrupt enable - ADRDYIE: u1, - /// End of sampling flag interrupt enable - EOSMPIE: u1, - /// End of conversion interrupt enable - EOCIE: u1, - /// End of conversion sequence interrupt enable - EOSIE: u1, - /// Overrun interrupt enable - OVRIE: u1, - reserved7: u2, - /// Analog watchdog interrupt enable - AWDIE: u1, - reserved11: u3, - /// End of calibration interrupt enable. - EOCALIE: u1, - padding: u20, - }), - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// ADC enable command - ADEN: u1, - /// ADC disable command - ADDIS: u1, - /// ADC start conversion command - ADSTART: u1, - reserved4: u1, - /// ADC stop conversion command - ADSTP: u1, - reserved28: u23, - /// ADC Voltage Regulator Enable. - ADVREGEN: u1, - reserved31: u2, - /// ADC calibration - ADCAL: u1, - }), - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// Direct memory access enable - DMAEN: u1, - /// Direct memory access configuration - DMACFG: packed union { - raw: u1, - value: DMACFG, - }, - /// Scan sequence direction - SCANDIR: packed union { - raw: u1, - value: SCANDIR, - }, - /// Data resolution - RES: packed union { - raw: u2, - value: RES, - }, - /// Data alignment - ALIGN: packed union { - raw: u1, - value: ALIGN, - }, - /// External trigger selection - EXTSEL: u3, - reserved10: u1, - /// External trigger enable and polarity selection - EXTEN: packed union { - raw: u2, - value: EXTEN, - }, - /// Overrun management mode - OVRMOD: packed union { - raw: u1, - value: OVRMOD, - }, - /// Continuous conversion - CONT: u1, - /// Wait conversion mode - WAIT: u1, - /// Auto-off mode - AUTOFF: u1, - /// Discontinuous mode - DISCEN: u1, - reserved22: u5, - /// Enable the watchdog on a single channel or on all channels - AWDSGL: packed union { - raw: u1, - value: AWDSGL, - }, - /// Analog watchdog enable - AWDEN: u1, - reserved26: u2, - /// Analog watchdog channel selection - AWDCH: u5, - padding: u1, - }), - /// configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// Oversampler Enable. - OVSE: u1, - reserved2: u1, - /// Oversampling ratio. - OVSR: u3, - /// Oversampling shift. - OVSS: u4, - /// Triggered Oversampling. - TOVS: u1, - reserved30: u20, - /// ADC clock mode - CKMODE: packed union { - raw: u2, - value: CKMODE, - }, - }), - /// sampling time register - SMPR: mmio.Mmio(packed struct(u32) { - /// Sampling time selection - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - padding: u29, - }), - reserved32: [8]u8, - /// watchdog threshold register - TR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog lower threshold - LT: u12, - reserved16: u4, - /// Analog watchdog higher threshold - HT: u12, - padding: u4, - }), - reserved40: [4]u8, - /// channel selection register - CHSELR: mmio.Mmio(packed struct(u32) { - /// Channel-x selection - @"CHSEL x": u1, - padding: u31, - }), - reserved64: [20]u8, - /// data register - DR: mmio.Mmio(packed struct(u32) { - /// Converted data - DATA: u16, - padding: u16, - }), - reserved180: [112]u8, - /// ADC Calibration factor. - CALFACT: mmio.Mmio(packed struct(u32) { - /// Calibration factor. - CALFACT: u7, - padding: u25, - }), - reserved776: [592]u8, - /// common configuration register - CCR: mmio.Mmio(packed struct(u32) { - reserved18: u18, - /// ADC prescaler. - PRESC: packed union { - raw: u4, - value: PRESC, - }, - /// VREFINT enable - VREFEN: u1, - /// Temperature sensor enable - TSEN: u1, - reserved25: u1, - /// Low Frequency Mode enable - LFMEN: u1, - padding: u6, - }), - }; - }; - - pub const rtc_v2f4 = struct { - pub const ALRMR_MSK = enum(u1) { - /// Alarm set if the date/day match - ToMatch = 0x0, - /// Date/day don’t care in Alarm comparison - NotMatch = 0x1, - }; - - pub const ALRMR_PM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, - }; - - pub const ALRMR_WDSEL = enum(u1) { - /// DU[3:0] represents the date units - DateUnits = 0x0, - /// DU[3:0] represents the week day. DT[1:0] is don’t care - WeekDay = 0x1, + /// MCO is divided by 8 + Div8 = 0x3, + /// MCO is divided by 16 + Div16 = 0x4, + /// MCO is divided by 32 + Div32 = 0x5, + /// MCO is divided by 64 + Div64 = 0x6, + /// MCO is divided by 128 + Div128 = 0x7, }; - pub const AMPM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const MCOSEL = enum(u3) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// Internal low speed (LSI) oscillator clock selected + LSI = 0x2, + /// External low speed (LSE) oscillator clock selected + LSE = 0x3, + /// System clock selected + SYS = 0x4, + /// Internal RC 8 MHz (HSI) oscillator clock selected + HSI = 0x5, + /// External 4-32 MHz (HSE) oscillator clock selected + HSE = 0x6, + /// PLL clock selected (divided by 1 or 2, depending en PLLMCODIV) + PLL = 0x7, + _, }; - pub const CALP = enum(u1) { - /// No RTCCLK pulses are added - NoChange = 0x0, - /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - IncreaseFreq = 0x1, + pub const PLLMCODIV = enum(u1) { + /// PLL is divided by 2 for MCO + Div2 = 0x0, + /// PLL is not divided for MCO + Div1 = 0x1, }; - pub const CALW16 = enum(u1) { - /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 - Sixteen_Second = 0x1, + pub const PLLMUL = enum(u4) { + /// PLL input clock x2 + Mul2 = 0x0, + /// PLL input clock x3 + Mul3 = 0x1, + /// PLL input clock x4 + Mul4 = 0x2, + /// PLL input clock x5 + Mul5 = 0x3, + /// PLL input clock x6 + Mul6 = 0x4, + /// PLL input clock x7 + Mul7 = 0x5, + /// PLL input clock x8 + Mul8 = 0x6, + /// PLL input clock x9 + Mul9 = 0x7, + /// PLL input clock x10 + Mul10 = 0x8, + /// PLL input clock x11 + Mul11 = 0x9, + /// PLL input clock x12 + Mul12 = 0xa, + /// PLL input clock x13 + Mul13 = 0xb, + /// PLL input clock x14 + Mul14 = 0xc, + /// PLL input clock x15 + Mul15 = 0xd, + /// PLL input clock x16 + Mul16 = 0xe, _, }; - pub const CALW8 = enum(u1) { - /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected - Eight_Second = 0x1, + pub const PLLSRC = enum(u2) { + /// HSI divided by 2 selected as PLL input clock + HSI_Div2 = 0x0, + /// HSI divided by PREDIV selected as PLL input clock + HSI_Div_PREDIV = 0x1, + /// HSE divided by PREDIV selected as PLL input clock + HSE_Div_PREDIV = 0x2, _, }; - pub const COSEL = enum(u1) { - /// Calibration output is 512 Hz (with default prescaler setting) - CalFreq_512Hz = 0x0, - /// Calibration output is 1 Hz (with default prescaler setting) - CalFreq_1Hz = 0x1, + pub const PLLXTPRE = enum(u1) { + /// HSE clock not divided + Div1 = 0x0, + /// HSE clock divided by 2 + Div2 = 0x1, }; - pub const FMT = enum(u1) { - /// 24 hour/day format - Twenty_Four_Hour = 0x0, - /// AM/PM hour format - AM_PM = 0x1, + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, }; - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Alarm B output enabled - AlarmB = 0x2, - /// Wakeup output enabled - Wakeup = 0x3, + pub const PREDIV = enum(u4) { + /// PREDIV input clock not divided + Div1 = 0x0, + /// PREDIV input clock divided by 2 + Div2 = 0x1, + /// PREDIV input clock divided by 3 + Div3 = 0x2, + /// PREDIV input clock divided by 4 + Div4 = 0x3, + /// PREDIV input clock divided by 5 + Div5 = 0x4, + /// PREDIV input clock divided by 6 + Div6 = 0x5, + /// PREDIV input clock divided by 7 + Div7 = 0x6, + /// PREDIV input clock divided by 8 + Div8 = 0x7, + /// PREDIV input clock divided by 9 + Div9 = 0x8, + /// PREDIV input clock divided by 10 + Div10 = 0x9, + /// PREDIV input clock divided by 11 + Div11 = 0xa, + /// PREDIV input clock divided by 12 + Div12 = 0xb, + /// PREDIV input clock divided by 13 + Div13 = 0xc, + /// PREDIV input clock divided by 14 + Div14 = 0xd, + /// PREDIV input clock divided by 15 + Div15 = 0xe, + /// PREDIV input clock divided by 16 + Div16 = 0xf, }; - pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - Low = 0x1, + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, }; - pub const RECALPF = enum(u1) { - /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 - Pending = 0x1, + pub const SW = enum(u2) { + /// HSI oscillator used as system clock + HSI = 0x0, + /// HSE oscillator used as system clock + HSE = 0x1, + /// PLL used as system clock + PLL1_P = 0x2, _, }; - pub const TAMPFLT = enum(u2) { - /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - Immediate = 0x0, - /// Tamper event is activated after 2 consecutive samples at the active level - Samples2 = 0x1, - /// Tamper event is activated after 4 consecutive samples at the active level - Samples4 = 0x2, - /// Tamper event is activated after 8 consecutive samples at the active level - Samples8 = 0x3, - }; - - pub const TAMPFREQ = enum(u3) { - /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - Div32768 = 0x0, - /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - Div16384 = 0x1, - /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - Div8192 = 0x2, - /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - Div4096 = 0x3, - /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - Div2048 = 0x4, - /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - Div1024 = 0x5, - /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - Div512 = 0x6, - /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - Div256 = 0x7, - }; - - pub const TAMPPRCH = enum(u2) { - /// 1 RTCCLK cycle - Cycles1 = 0x0, - /// 2 RTCCLK cycles - Cycles2 = 0x1, - /// 4 RTCCLK cycles - Cycles4 = 0x2, - /// 8 RTCCLK cycles - Cycles8 = 0x3, + pub const TIM2SW = enum(u1) { + /// PCLK2 clock (doubled frequency when prescaled) + PCLK1_TIM = 0x0, + /// PLL vco output (running up to 144 MHz) + PLL1_P_MUL_2 = 0x1, }; - pub const TAMPPUDIS = enum(u1) { - /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - Enabled = 0x0, - /// Disable precharge of RTC_TAMPx pins - Disabled = 0x1, + pub const TIMSW = enum(u1) { + /// PCLK2 clock (doubled frequency when prescaled) + PCLK2_TIM = 0x0, + /// PLL vco output (running up to 144 MHz) + PLL1_P_MUL_2 = 0x1, }; - pub const TAMPTRG = enum(u1) { - /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. - RisingEdge = 0x0, - /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event - FallingEdge = 0x1, + pub const USART1SW = enum(u2) { + /// PCLK selected as USART clock source + PCLK2 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const TSEDGE = enum(u1) { - /// RTC_TS input rising edge generates a time-stamp event - RisingEdge = 0x0, - /// RTC_TS input falling edge generates a time-stamp event - FallingEdge = 0x1, + pub const USARTSW = enum(u2) { + /// PCLK selected as USART clock source + PCLK1 = 0x0, + /// SYSCLK selected as USART clock source + SYS = 0x1, + /// LSE selected as USART clock source + LSE = 0x2, + /// HSI selected as USART clock source + HSI = 0x3, }; - pub const WUCKSEL = enum(u3) { - /// RTC/16 clock is selected - Div16 = 0x0, - /// RTC/8 clock is selected - Div8 = 0x1, - /// RTC/4 clock is selected - Div4 = 0x2, - /// RTC/2 clock is selected - Div2 = 0x3, - /// ck_spre (usually 1 Hz) clock is selected - ClockSpare = 0x4, - /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - ClockSpareWithOffset = 0x6, - _, + pub const USBPRE = enum(u1) { + /// PLL clock is divided by 1.5 + Div1_5 = 0x0, + /// PLL clock is not divided + Div1 = 0x1, }; - /// Real-time clock - pub const RTC = extern struct { - /// Time register - TR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, - }), - /// Date register - DR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding: u8, - }), - /// Control register + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register CR: mmio.Mmio(packed struct(u32) { - /// Wakeup clock selection - WUCKSEL: packed union { - raw: u3, - value: WUCKSEL, + /// Internal High Speed clock enable + HSION: u1, + /// Internal High Speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal High Speed clock trimming + HSITRIM: u5, + /// Internal High Speed clock Calibration + HSICAL: u8, + /// External High Speed clock enable + HSEON: u1, + /// External High Speed clock ready flag + HSERDY: u1, + /// External High Speed clock Bypass + HSEBYP: u1, + /// Clock Security System enable + CSSON: u1, + reserved24: u4, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding: u6, + }), + /// Clock configuration register (RCC_CFGR) + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock Switch + SW: packed union { + raw: u2, + value: SW, }, - /// Timestamp event active edge - TSEDGE: packed union { - raw: u1, - value: TSEDGE, + /// System Clock Switch Status + SWS: packed union { + raw: u2, + value: SW, }, - /// Reference clock detection enable (50 or 60 Hz) - REFCKON: u1, - /// Bypass the shadow registers - BYPSHAD: u1, - /// Hour format - FMT: packed union { - raw: u1, - value: FMT, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, }, - /// Coarse digital calibration enable - DCE: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, - /// Wakeup timer enable - WUTE: u1, - /// Timestamp enable - TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, - /// Wakeup timer interrupt enable - WUTIE: u1, - /// Timestamp interrupt enable - TSIE: u1, - /// Add 1 hour (summer time change) - ADD1H: u1, - /// Subtract 1 hour (winter time change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output selection - COSEL: packed union { - raw: u1, - value: COSEL, + /// APB Low speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, }, - /// Output polarity - POL: packed union { - raw: u1, - value: POL, + /// APB high speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, }, - /// Output selection - OSEL: packed union { + /// ADC prescaler + ADCPRE: packed union { raw: u2, - value: OSEL, + value: ADCPRE, }, - /// Calibration output enable - COE: u1, - padding: u8, - }), - /// Initialization and status register - ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write allowed - ALRWF: u1, - reserved2: u1, - /// Wakeup timer write allowed - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Enter Initialization mode - INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, - /// Wakeup timer flag - WUTF: u1, - /// Timestamp flag - TSF: u1, - /// Timestamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, - /// Recalibration pending flag - RECALPF: packed union { + reserved17: u1, + /// HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products. + PLLXTPRE: packed union { raw: u1, - value: RECALPF, + value: PLLXTPRE, }, - padding: u15, - }), - /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, - padding: u9, - }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, - padding: u16, - }), - /// Calibration register - CALIBR: mmio.Mmio(packed struct(u32) { - /// Digital calibration - DC: u5, - reserved7: u2, - /// Digital calibration sign - DCS: u1, - padding: u24, - }), - /// Alarm register - ALRMR: [2]mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm seconds mask - MSK1: packed union { - raw: u1, - value: ALRMR_MSK, + /// PLL Multiplication Factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm minutes mask - MSK2: packed union { + /// USB prescaler + USBPRE: packed union { raw: u1, - value: ALRMR_MSK, + value: USBPRE, }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { + /// I2S external clock source selection + I2SSRC: packed union { raw: u1, - value: ALRMR_PM, + value: ISSRC, }, - /// Alarm hours mask - MSK3: packed union { - raw: u1, - value: ALRMR_MSK, + /// Microcontroller clock output + MCOSEL: packed union { + raw: u3, + value: MCOSEL, }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { - raw: u1, - value: ALRMR_WDSEL, + reserved28: u1, + /// Microcontroller Clock Output Prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, }, - /// Alarm date mask - MSK4: packed union { + /// Do not divide PLL to MCO + PLLMCODIV: packed union { raw: u1, - value: ALRMR_MSK, + value: PLLMCODIV, }, }), - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: u8, - padding: u24, + /// Clock interrupt register (RCC_CIR) + CIR: mmio.Mmio(packed struct(u32) { + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + reserved7: u2, + /// Clock Security System Interrupt flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + reserved16: u3, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + reserved23: u2, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, }), - /// Sub second register - SSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, + /// APB2 peripheral reset register (RCC_APB2RSTR) + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// SYSCFG and COMP reset + SYSCFGRST: u1, + reserved11: u10, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + /// SPI4 reset + SPI4RST: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + /// TIM19 timer reset + TIM19RST: u1, + /// TIM20 timer reset + TIM20RST: u1, + reserved22: u1, + /// Debug MCU reset + DBGMCURST: u1, + reserved29: u6, + /// High Resolution Timer1 reset + HRTIM1RST: u1, + padding: u2, }), - /// Shift control register - SHIFTR: mmio.Mmio(packed struct(u32) { - /// Subtract a fraction of a second - SUBFS: u15, - reserved31: u16, - /// Add one second - ADD1S: u1, + /// APB1 peripheral reset register (RCC_APB1RSTR) + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + /// Timer 14 reset + TIM4RST: u1, + reserved4: u1, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + reserved11: u5, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved17: u1, + /// USART 2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// UART 4 reset + UART4RST: u1, + /// UART 5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB reset + USBRST: u1, + reserved25: u1, + /// CAN reset + CANRST: u1, + /// DAC2 interface reset + DAC2RST: u1, + reserved28: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// I2C3 reset + I2C3RST: u1, + padding: u1, }), - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, + /// AHB Peripheral Clock enable register (RCC_AHBENR) + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock enable + SRAMEN: u1, + reserved4: u1, + /// FLASH clock enable + FLASHEN: u1, + /// FMC clock enable + FMCEN: u1, + /// CRC clock enable + CRCEN: u1, + reserved16: u9, + /// IO port H clock enable + GPIOHEN: u1, + /// I/O port A clock enable + GPIOAEN: u1, + /// I/O port B clock enable + GPIOBEN: u1, + /// I/O port C clock enable + GPIOCEN: u1, + /// I/O port D clock enable + GPIODEN: u1, + /// I/O port E clock enable + GPIOEEN: u1, + /// I/O port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// Touch sensing controller clock enable + TSCEN: u1, + reserved28: u3, + /// ADC1 and ADC2 clock enable + ADC12EN: u1, + /// ADC3 and ADC4 clock enable + ADC34EN: u1, + padding: u2, + }), + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved11: u10, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + /// TIM8 Timer clock enable + TIM8EN: u1, + /// USART1 clock enable + USART1EN: u1, + /// SPI4 clock enable + SPI4EN: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + /// TIM19 timer clock enable + TIM19EN: u1, + /// TIM20 timer clock enable + TIM20EN: u1, + reserved22: u1, + /// MCU debug module clock enable + DBGMCUEN: u1, + reserved29: u6, + /// High Resolution Timer 1 clock enable + HRTIM1EN: u1, + padding: u2, + }), + /// APB1 peripheral clock enable register (RCC_APB1ENR) + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + /// Timer 4 clock enable + TIM4EN: u1, + reserved4: u1, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + reserved11: u5, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI 2 clock enable + SPI2EN: u1, + /// SPI 3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART 3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB clock enable + USBEN: u1, + reserved25: u1, + /// CAN clock enable + CANEN: u1, + /// DAC2 interface clock enable + DAC2EN: u1, + reserved28: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// I2C3 clock enable + I2C3EN: u1, + padding: u1, + }), + /// Backup domain control register (RCC_BDCR) + BDCR: mmio.Mmio(packed struct(u32) { + /// External Low Speed oscillator enable + LSEON: u1, + /// External Low Speed oscillator ready + LSERDY: u1, + /// External Low Speed oscillator bypass + LSEBYP: u1, + /// LSE oscillator drive capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, }, - padding: u9, + reserved8: u3, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding: u16, + /// Control/status register (RCC_CSR) + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low speed oscillator enable + LSION: u1, + /// Internal low speed oscillator ready + LSIRDY: u1, + reserved23: u21, + /// Reset flag of the 1.8 V domain + V18PWRRSTF: u1, + /// Remove reset flag + RMVF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, }), - /// Timestamp sub second register - TSSSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// FMC reset + FMCRST: u1, + reserved16: u10, + /// IO port H reset + GPIOHRST: u1, + /// I/O port A reset + GPIOARST: u1, + /// I/O port B reset + GPIOBRST: u1, + /// I/O port C reset + GPIOCRST: u1, + /// I/O port D reset + GPIODRST: u1, + /// I/O port E reset + GPIOERST: u1, + /// I/O port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// Touch sensing controller reset + TSCRST: u1, + reserved28: u3, + /// ADC1 and ADC2 reset + ADC12RST: u1, + /// ADC3 and ADC4 reset + ADC34RST: u1, + padding: u2, }), - /// Calibration register - CALR: mmio.Mmio(packed struct(u32) { - /// Calibration minus - CALM: u9, - reserved13: u4, - /// Use a 16-second calibration cycle period - CALW16: packed union { + /// Clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// PREDIV division factor + PREDIV: packed union { + raw: u4, + value: PREDIV, + }, + /// ADC1 and ADC2 prescaler + ADC12PRES: packed union { + raw: u5, + value: ADCPRES, + }, + /// ADC3 and ADC4 prescaler + ADC34PRES: packed union { + raw: u5, + value: ADCPRES, + }, + padding: u18, + }), + /// Clock configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SW: packed union { + raw: u2, + value: USART1SW, + }, + reserved4: u2, + /// I2C1 clock source selection + I2C1SW: packed union { raw: u1, - value: CALW16, + value: ICSW, }, - /// Use an 8-second calibration cycle period - CALW8: packed union { + /// I2C2 clock source selection + I2C2SW: packed union { raw: u1, - value: CALW8, + value: ICSW, }, - /// Increase frequency of RTC by 488.5 ppm - CALP: packed union { + /// HDMI CEC clock source selection + CECSW: packed union { raw: u1, - value: CALP, + value: CECSW, }, - padding: u16, - }), - /// Tamper and alternate function configuration register - TAFCR: mmio.Mmio(packed struct(u32) { - /// Tamper detection enable - TAMPE: u1, - /// Active level for tamper - TAMPTRG: packed union { + reserved8: u1, + /// Timer1 clock source selection + TIM1SW: packed union { raw: u1, - value: TAMPTRG, + value: TIMSW, }, - /// Tamper interrupt enable - TAMPIE: u1, - reserved7: u4, - /// Activate timestamp on tamper detection event - TAMPTS: u1, - /// Tamper sampling frequency - TAMPFREQ: packed union { - raw: u3, - value: TAMPFREQ, + /// Timer8 clock source selection + TIM8SW: packed union { + raw: u1, + value: TIMSW, }, - /// Tamper filter count - TAMPFLT: packed union { + /// Timer15 clock source selection + TIM15SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Timer16 clock source selection + TIM16SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Hrtim1 clock source selection + HRTIM1SW: packed union { + raw: u1, + value: TIMSW, + }, + /// Timer17 clock source selection + TIM17SW: packed union { + raw: u1, + value: TIMSW, + }, + reserved15: u1, + /// Timer20 clock source selection + TIM20SW: packed union { + raw: u1, + value: TIMSW, + }, + /// USART2 clock source selection + USART2SW: packed union { raw: u2, - value: TAMPFLT, + value: USARTSW, }, - /// Tamper precharge duration - TAMPPRCH: packed union { + /// USART3 clock source selection + USART3SW: packed union { raw: u2, - value: TAMPPRCH, + value: USARTSW, }, - /// Tamper pull-up disable - TAMPPUDIS: packed union { + /// UART4 clock source selection + UART4SW: packed union { + raw: u2, + value: USARTSW, + }, + /// UART5 clock source selection + UART5SW: packed union { + raw: u2, + value: USARTSW, + }, + /// Timer2 clock source selection + TIM2SW: packed union { raw: u1, - value: TAMPPUDIS, + value: TIM2SW, }, - /// Tamper 1 mapping - TAMP1INSEL: u1, - /// Timestamp mapping - TSINSEL: u1, - /// AFO_ALARM output type - ALARMOUTTYPE: u1, - padding: u13, - }), - /// Alarm sub second register - ALRMSSR: [2]mmio.Mmio(packed struct(u32) { - /// Sub seconds value - SS: u15, - reserved24: u9, - /// Mask the most-significant bits starting at this bit - MASKSS: u4, - padding: u4, - }), - reserved80: [4]u8, - /// Backup register - BKPR: [20]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, - }), - }; - }; - - pub const pwr_f3 = struct { - pub const PDDS = enum(u1) { - /// Enter Stop mode when the CPU enters deepsleep - STOP_MODE = 0x0, - /// Enter Standby mode when the CPU enters deepsleep - STANDBY_MODE = 0x1, - }; - - /// Power control - pub const PWR = extern struct { - /// power control register - CR: mmio.Mmio(packed struct(u32) { - /// Low-power deep sleep - LPDS: u1, - /// Power down deepsleep - PDDS: packed union { + /// Timer34 clock source selection + TIM34SW: packed union { raw: u1, - value: PDDS, + value: TIMSW, }, - /// Clear wakeup flag - CWUF: u1, - /// Clear standby flag - CSBF: u1, - /// Power voltage detector enable - PVDE: u1, - /// PVD level selection - PLS: u3, - /// Disable backup domain write protection - DBP: u1, - /// ENable SD1 ADC - ENSD: u1, - padding: u22, - }), - /// power control/status register - CSR: mmio.Mmio(packed struct(u32) { - /// Wakeup flag - WUF: u1, - /// Standby flag - SBF: u1, - /// PVD output - PVDO: u1, - /// Internal voltage reference ready flag - VREFINTRDYF: u1, - reserved8: u4, - /// Enable WKUP1 pin - EWUP: u1, - padding: u23, + padding: u6, }), }; }; - pub const fmc_v1x3 = struct { - pub const ACCMOD = enum(u2) { - /// Access mode A - A = 0x0, - /// Access mode B - B = 0x1, - /// Access mode C - C = 0x2, - /// Access mode D - D = 0x3, + pub const rcc_f4 = struct { + pub const CECSEL = enum(u1) { + /// LSE clock is selected as HDMI-CEC clock + LSE = 0x0, + /// HSI divided by 488 clock is selected as HDMI-CEC clock + HSI_Div488 = 0x1, }; - pub const CAS = enum(u2) { - /// 1 cycle - Clocks1 = 0x1, - /// 2 cycles - Clocks2 = 0x2, - /// 3 cycles - Clocks3 = 0x3, - _, + pub const CKDFSDMASEL = enum(u1) { + /// CK_I2S_APB1 selected as audio clock + I2S1 = 0x0, + /// CK_I2S_APB2 selected as audio clock + I2S2 = 0x1, }; - pub const CPSIZE = enum(u3) { - /// No burst split when crossing page boundary - NoBurstSplit = 0x0, - /// 128 bytes CRAM page size - Bytes128 = 0x1, - /// 256 bytes CRAM page size - Bytes256 = 0x2, - /// 512 bytes CRAM page size - Bytes512 = 0x3, - /// 1024 bytes CRAM page size - Bytes1024 = 0x4, - _, + pub const CKDFSDMSEL = enum(u1) { + /// APB2 clock used as Kernel clock + PCLK2 = 0x0, + /// System clock used as Kernel clock + SYS = 0x1, }; - pub const ECCPS = enum(u3) { - /// ECC page size 256 bytes - Bytes256 = 0x0, - /// ECC page size 512 bytes - Bytes512 = 0x1, - /// ECC page size 1024 bytes - Bytes1024 = 0x2, - /// ECC page size 2048 bytes - Bytes2048 = 0x3, - /// ECC page size 4096 bytes - Bytes4096 = 0x4, - /// ECC page size 8192 bytes - Bytes8192 = 0x5, - _, + pub const CLK48SEL = enum(u1) { + /// 48MHz clock from PLL is selected + PLL1_Q = 0x0, + /// 48MHz clock from PLLSAI is selected + PLLSAI1_Q = 0x1, }; - pub const MODE = enum(u3) { - /// Normal Mode - Normal = 0x0, - /// Clock Configuration Enable - ClockConfigurationEnable = 0x1, - /// PALL (All Bank Precharge) command - PALL = 0x2, - /// Auto-refresh command - AutoRefreshCommand = 0x3, - /// Load Mode Resgier - LoadModeRegister = 0x4, - /// Self-refresh command - SelfRefreshCommand = 0x5, - /// Power-down command - PowerDownCommand = 0x6, - _, + pub const DSISEL = enum(u1) { + /// DSI-PHY used as DSI byte lane clock source (usual case) + DSI_PHY = 0x0, + /// PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode) + PLL1_R = 0x1, }; - pub const MODES = enum(u2) { - /// Normal Mode - Normal = 0x0, - /// Self-refresh mode - SelfRefresh = 0x1, - /// Power-down mode - PowerDown = 0x2, + pub const FMPI2CSEL = enum(u2) { + /// APB clock selected as I2C clock + PCLK1 = 0x0, + /// System clock selected as I2C clock + SYS = 0x1, + /// HSI clock selected as I2C clock + HSI = 0x2, _, }; - pub const MTYP = enum(u2) { - /// SRAM memory type - SRAM = 0x0, - /// PSRAM (CRAM) memory type - PSRAM = 0x1, - /// NOR Flash/OneNAND Flash - Flash = 0x2, + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, _, }; - pub const MWID = enum(u2) { - /// Memory data bus width 8 bits - Bits8 = 0x0, - /// Memory data bus width 16 bits - Bits16 = 0x1, - /// Memory data bus width 32 bits - Bits32 = 0x2, - _, + pub const I2S1SRC = enum(u2) { + /// I2Sx clock frequency = f(PLLI2S_R) + PLLI2SR = 0x0, + /// I2Sx clock frequency = I2S_CKIN Alternate function input frequency + I2S_CKIN = 0x1, + /// I2Sx clock frequency = f(PLL_R) + PLLR = 0x2, + /// I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) + HSI_HSE = 0x3, }; - pub const NB = enum(u1) { - /// Two internal Banks - NB2 = 0x0, - /// Four internal Banks - NB4 = 0x1, + pub const I2SSRC_CFGR = enum(u1) { + /// PLLI2S clock used as I2S clock source + PLLI2S = 0x0, + /// External clock mapped on the I2S_CKIN pin used as I2S clock source + CKIN = 0x1, }; - pub const NC = enum(u2) { - /// 8 bits - Bits8 = 0x0, - /// 9 bits - Bits9 = 0x1, - /// 10 bits - Bits10 = 0x2, - /// 11 bits - Bits11 = 0x3, + pub const I2SSRC_DCKCFGR = enum(u2) { + /// clock frequency = f(PLLI2S_R) + PLLI2S_R = 0x0, + /// clock frequency = I2S_CKIN Alternate function input frequency + I2S_CKIN = 0x1, + /// clock frequency = f(PLL_R) + PLL_R = 0x2, + /// clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) + HSI_HSE = 0x3, }; - pub const NR = enum(u2) { - /// 11 bits - Bits11 = 0x0, - /// 12 bits - Bits12 = 0x1, - /// 13 bits - Bits13 = 0x2, - _, + pub const LPTIMSEL = enum(u2) { + /// APB1 clock (PCLK1) selected as LPTILM1 clock + PCLK1 = 0x0, + /// LSI clock is selected as LPTILM1 clock + LSI = 0x1, + /// HSI clock is selected as LPTILM1 clock + HSI = 0x2, + /// LSE clock is selected as LPTILM1 clock + LSE = 0x3, }; - pub const PTYP = enum(u1) { - /// NAND Flash - NANDFlash = 0x1, - _, + pub const LSEMOD = enum(u1) { + /// LSE oscillator low power mode selection + Low = 0x0, + /// LSE oscillator high drive mode selection + High = 0x1, }; - pub const PWID = enum(u2) { - /// External memory device width 8 bits - Bits8 = 0x0, - /// External memory device width 16 bits - Bits16 = 0x1, - _, + pub const MCO1SEL = enum(u2) { + /// HSI clock selected + HSI = 0x0, + /// LSE oscillator selected + LSE = 0x1, + /// HSE oscillator clock selected + HSE = 0x2, + /// PLL clock selected + PLL = 0x3, }; - pub const RPIPE = enum(u2) { - /// No clock cycle delay - NoDelay = 0x0, - /// One clock cycle delay - Clocks1 = 0x1, - /// Two clock cycles delay - Clocks2 = 0x2, - _, + pub const MCO2SEL = enum(u2) { + /// System clock (SYSCLK) selected + SYS = 0x0, + /// PLLI2S clock selected + PLLI2S = 0x1, + /// HSE oscillator clock selected + HSE = 0x2, + /// PLL clock selected + PLL = 0x3, }; - pub const SDCLK = enum(u2) { - /// SDCLK clock disabled - Disabled = 0x0, - /// SDCLK period = 2 x HCLK period - Div2 = 0x2, - /// SDCLK period = 3 x HCLK period - Div3 = 0x3, + pub const MCOPRE = enum(u3) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x4, + /// Division by 3 + Div3 = 0x5, + /// Division by 4 + Div4 = 0x6, + /// Division by 5 + Div5 = 0x7, _, }; - pub const WAITCFG = enum(u1) { - /// NWAIT signal is active one data cycle before wait state - BeforeWaitState = 0x0, - /// NWAIT signal is active during wait state - DuringWaitState = 0x1, + pub const PLLDIVR = enum(u5) { + /// PLLSAIDIVQ = /1 + Div1 = 0x0, + /// PLLSAIDIVQ = /2 + Div2 = 0x1, + /// PLLSAIDIVQ = /3 + Div3 = 0x2, + /// PLLSAIDIVQ = /4 + Div4 = 0x3, + /// PLLSAIDIVQ = /5 + Div5 = 0x4, + /// PLLSAIDIVQ = /6 + Div6 = 0x5, + /// PLLSAIDIVQ = /7 + Div7 = 0x6, + /// PLLSAIDIVQ = /8 + Div8 = 0x7, + /// PLLSAIDIVQ = /9 + Div9 = 0x8, + /// PLLSAIDIVQ = /10 + Div10 = 0x9, + /// PLLSAIDIVQ = /11 + Div11 = 0xa, + /// PLLSAIDIVQ = /12 + Div12 = 0xb, + /// PLLSAIDIVQ = /13 + Div13 = 0xc, + /// PLLSAIDIVQ = /14 + Div14 = 0xd, + /// PLLSAIDIVQ = /15 + Div15 = 0xe, + /// PLLSAIDIVQ = /16 + Div16 = 0xf, + /// PLLSAIDIVQ = /17 + Div17 = 0x10, + /// PLLSAIDIVQ = /18 + Div18 = 0x11, + /// PLLSAIDIVQ = /19 + Div19 = 0x12, + /// PLLSAIDIVQ = /20 + Div20 = 0x13, + /// PLLSAIDIVQ = /21 + Div21 = 0x14, + /// PLLSAIDIVQ = /22 + Div22 = 0x15, + /// PLLSAIDIVQ = /23 + Div23 = 0x16, + /// PLLSAIDIVQ = /24 + Div24 = 0x17, + /// PLLSAIDIVQ = /25 + Div25 = 0x18, + /// PLLSAIDIVQ = /26 + Div26 = 0x19, + /// PLLSAIDIVQ = /27 + Div27 = 0x1a, + /// PLLSAIDIVQ = /28 + Div28 = 0x1b, + /// PLLSAIDIVQ = /29 + Div29 = 0x1c, + /// PLLSAIDIVQ = /30 + Div30 = 0x1d, + /// PLLSAIDIVQ = /31 + Div31 = 0x1e, + /// PLLSAIDIVQ = /32 + Div32 = 0x1f, }; - pub const WAITPOL = enum(u1) { - /// NWAIT active low - ActiveLow = 0x0, - /// NWAIT active high - ActiveHigh = 0x1, + pub const PLLI2SDIVQ = enum(u5) { + /// PLLI2SDIVQ = /1 + Div1 = 0x0, + /// PLLI2SDIVQ = /2 + Div2 = 0x1, + /// PLLI2SDIVQ = /3 + Div3 = 0x2, + /// PLLI2SDIVQ = /4 + Div4 = 0x3, + /// PLLI2SDIVQ = /5 + Div5 = 0x4, + /// PLLI2SDIVQ = /6 + Div6 = 0x5, + /// PLLI2SDIVQ = /7 + Div7 = 0x6, + /// PLLI2SDIVQ = /8 + Div8 = 0x7, + /// PLLI2SDIVQ = /9 + Div9 = 0x8, + /// PLLI2SDIVQ = /10 + Div10 = 0x9, + /// PLLI2SDIVQ = /11 + Div11 = 0xa, + /// PLLI2SDIVQ = /12 + Div12 = 0xb, + /// PLLI2SDIVQ = /13 + Div13 = 0xc, + /// PLLI2SDIVQ = /14 + Div14 = 0xd, + /// PLLI2SDIVQ = /15 + Div15 = 0xe, + /// PLLI2SDIVQ = /16 + Div16 = 0xf, + /// PLLI2SDIVQ = /17 + Div17 = 0x10, + /// PLLI2SDIVQ = /18 + Div18 = 0x11, + /// PLLI2SDIVQ = /19 + Div19 = 0x12, + /// PLLI2SDIVQ = /20 + Div20 = 0x13, + /// PLLI2SDIVQ = /21 + Div21 = 0x14, + /// PLLI2SDIVQ = /22 + Div22 = 0x15, + /// PLLI2SDIVQ = /23 + Div23 = 0x16, + /// PLLI2SDIVQ = /24 + Div24 = 0x17, + /// PLLI2SDIVQ = /25 + Div25 = 0x18, + /// PLLI2SDIVQ = /26 + Div26 = 0x19, + /// PLLI2SDIVQ = /27 + Div27 = 0x1a, + /// PLLI2SDIVQ = /28 + Div28 = 0x1b, + /// PLLI2SDIVQ = /29 + Div29 = 0x1c, + /// PLLI2SDIVQ = /30 + Div30 = 0x1d, + /// PLLI2SDIVQ = /31 + Div31 = 0x1e, + /// PLLI2SDIVQ = /32 + Div32 = 0x1f, }; - /// Flexible memory controller - pub const FMC = extern struct { - /// SRAM/NOR-Flash chip-select control register 1 - BCR1: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { - raw: u2, - value: MTYP, - }, - /// Memory data bus width - MWID: packed union { - raw: u2, - value: MWID, - }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { - raw: u1, - value: WAITPOL, - }, - /// WRAPMOD - WRAPMOD: u1, - /// Wait timing configuration - WAITCFG: packed union { - raw: u1, - value: WAITCFG, - }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - /// CRAM page size - CPSIZE: packed union { - raw: u3, - value: CPSIZE, - }, - /// Write burst enable - CBURSTRW: u1, - /// Continuous clock enable - CCLKEN: u1, - padding: u11, - }), - /// SRAM/NOR-Flash chip-select timing register 1-4 - BTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - /// Clock divide ratio (for FMC_CLK signal) - CLKDIV: u4, - /// Data latency for synchronous memory - DATLAT: u4, - /// Access mode - ACCMOD: packed union { - raw: u2, - value: ACCMOD, - }, - padding: u2, - }), - /// SRAM/NOR-Flash chip-select control register 2-4 - BCR: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { - raw: u2, - value: MTYP, - }, - /// Memory data bus width - MWID: packed union { - raw: u2, - value: MWID, - }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { - raw: u1, - value: WAITPOL, - }, - /// WRAPMOD - WRAPMOD: u1, - /// Wait timing configuration - WAITCFG: packed union { - raw: u1, - value: WAITCFG, - }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - /// CRAM page size - CPSIZE: packed union { - raw: u3, - value: CPSIZE, - }, - /// Write burst enable - CBURSTRW: u1, - padding: u12, - }), - reserved96: [84]u8, - /// PC Card/NAND Flash control register 2-4 - PCR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Wait feature enable bit - PWAITEN: u1, - /// NAND Flash memory bank enable bit - PBKEN: u1, - /// Memory type - PTYP: packed union { - raw: u1, - value: PTYP, - }, - /// Data bus width - PWID: packed union { - raw: u2, - value: PWID, - }, - /// ECC computation logic enable bit - ECCEN: u1, - reserved9: u2, - /// CLE to RE delay - TCLR: u4, - /// ALE to RE delay - TAR: u4, - /// ECC page size - ECCPS: packed union { - raw: u3, - value: ECCPS, - }, - padding: u12, - }), - /// FIFO status and interrupt register 2-4 - SR: mmio.Mmio(packed struct(u32) { - /// Interrupt rising edge status - IRS: u1, - /// Interrupt high-level status - ILS: u1, - /// Interrupt falling edge status - IFS: u1, - /// Interrupt rising edge detection enable bit - IREN: u1, - /// Interrupt high-level detection enable bit - ILEN: u1, - /// Interrupt falling edge detection enable bit - IFEN: u1, - /// FIFO empty status - FEMPT: u1, - padding: u25, - }), - /// Common memory space timing register 2-4 - PMEM: mmio.Mmio(packed struct(u32) { - /// Common memory x setup time - MEMSET: u8, - /// Common memory wait time - MEMWAIT: u8, - /// Common memory hold time - MEMHOLD: u8, - /// Common memory x data bus Hi-Z time - MEMHIZ: u8, - }), - /// Attribute memory space timing register 2-4 - PATT: mmio.Mmio(packed struct(u32) { - /// Attribute memory setup time - ATTSET: u8, - /// Attribute memory wait time - ATTWAIT: u8, - /// Attribute memory hold time - ATTHOLD: u8, - /// Attribute memory data bus Hi-Z time - ATTHIZ: u8, - }), - reserved116: [4]u8, - /// ECC result register 2-3 - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC computation result value - ECC: u32, - }), - reserved176: [56]u8, - /// I/O space timing register 4 - PIO4: mmio.Mmio(packed struct(u32) { - /// IOSETx - IOSETx: u8, - /// IOWAITx - IOWAITx: u8, - /// IOHOLDx - IOHOLDx: u8, - /// IOHIZx - IOHIZx: u8, - }), - reserved260: [80]u8, - /// SRAM/NOR-Flash write timing registers 1-4 - BWTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - reserved28: u8, - /// Access mode - ACCMOD: packed union { - raw: u2, - value: ACCMOD, - }, - padding: u2, - }), - reserved320: [56]u8, - /// SDRAM Control Register 1-2 - SDCR: [2]mmio.Mmio(packed struct(u32) { - /// Number of column address bits - NC: packed union { - raw: u2, - value: NC, - }, - /// Number of row address bits - NR: packed union { - raw: u2, - value: NR, - }, - /// Memory data bus width - MWID: packed union { - raw: u2, - value: MWID, - }, - /// Number of internal banks - NB: packed union { - raw: u1, - value: NB, - }, - /// CAS latency - CAS: packed union { - raw: u2, - value: CAS, - }, - /// Write protection - WP: u1, - /// SDRAM clock configuration - SDCLK: packed union { - raw: u2, - value: SDCLK, - }, - /// Burst read - RBURST: u1, - /// Read pipe - RPIPE: packed union { - raw: u2, - value: RPIPE, - }, - padding: u17, - }), - /// SDRAM Timing register 1-2 - SDTR: [2]mmio.Mmio(packed struct(u32) { - /// Load Mode Register to Active - TMRD: u4, - /// Exit self-refresh delay - TXSR: u4, - /// Self refresh time - TRAS: u4, - /// Row cycle delay - TRC: u4, - /// Recovery delay - TWR: u4, - /// Row precharge delay - TRP: u4, - /// Row to column delay - TRCD: u4, - padding: u4, - }), - /// SDRAM Command Mode register - SDCMR: mmio.Mmio(packed struct(u32) { - /// Command mode - MODE: packed union { - raw: u3, - value: MODE, - }, - /// Command target bank 2 - CTB2: u1, - /// Command target bank 1 - CTB1: u1, - /// Number of Auto-refresh - NRFS: u4, - /// Mode Register definition - MRD: u13, - padding: u10, - }), - /// SDRAM Refresh Timer register - SDRTR: mmio.Mmio(packed struct(u32) { - /// Clear Refresh error flag - CRE: u1, - /// Refresh Timer Count - COUNT: u13, - /// RES Interrupt Enable - REIE: u1, - padding: u17, - }), - /// SDRAM Status register - SDSR: mmio.Mmio(packed struct(u32) { - /// Refresh error flag - RE: u1, - /// Status Mode for Bank 1 - MODES1: packed union { - raw: u2, - value: MODES, - }, - /// Status Mode for Bank 2 - MODES2: packed union { - raw: u2, - value: MODES, - }, - /// Busy status - BUSY: u1, - padding: u26, - }), - }; - }; - - pub const rcc_h7rs = struct { - pub const ADCSEL = enum(u2) { - /// pll2_p selected as peripheral clock - PLL2_P = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// PER selected as peripheral clock - PER = 0x2, - _, - }; - - pub const ADFSEL = enum(u3) { - /// hclk1 selected as ADF kernel clock (default after reset). - HCLK1 = 0x0, - /// pll2_p_ck selected as ADF kernel clock. - PLL2_P = 0x1, - _, - }; - - pub const CECSEL = enum(u2) { - /// LSE selected as peripheral clock - LSE = 0x0, - /// LSI selected as peripheral clock - LSI = 0x1, - /// csi_ker selected as peripheral clock - CSI = 0x2, - _, - }; - - pub const DWNSPREAD = enum(u1) { - /// Center-spread modulation selected (default after reset). - CenterSpread = 0x0, - /// Down-spread modulation selected. - DownSpread = 0x1, - }; - - pub const ETHPHY_CLK_SEL = enum(u1) { - /// hse_ker_ck selected as clock source (default after reset). - HSE = 0x0, - /// pll3_s_ck selected clock source. - PLL3_S = 0x1, - }; - - pub const ETH_REF_CLK_SEL = enum(u2) { - /// PAD ETH_RMII_REF_CLK selected as kernel peripheral clock (default after reset). - ETH_RMII_REF = 0x0, - /// hse_ker_ck selected as kernel peripheral clock. - HSE = 0x1, - /// eth_clk_fb selected as kernel peripheral clock. - ETH = 0x2, - _, - }; - - pub const FDCANSEL = enum(u2) { - /// HSE selected as peripheral clock - HSE = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// pll2_p selected as peripheral clock - PLL2_P = 0x2, - _, - }; - - pub const FMCSEL = enum(u2) { - /// hclk5 selected as kernel peripheral clock (default after reset). - HCLK5 = 0x0, - /// pll1_q_ck selected as kernel peripheral clock. - PLL1_Q = 0x1, - /// pll2_r_ck selected as kernel peripheral clock. - PLL2_R = 0x2, - /// hsi_ker_ck selected as kernel peripheral clock. - HSI = 0x3, - }; - - pub const FMCSWP = enum(u3) { - /// The switch is in neutral mode and output clock is gated (default after reset). - B_0x0 = 0x0, - /// The switch is selecting hclk5. - B_0x1 = 0x1, - /// The switch is selecting pll1_q_ck. - B_0x2 = 0x2, - /// The switch is selecting pll2_r_ck. - B_0x3 = 0x3, - /// The switch is selecting hsi_ker_ck. - B_0x4 = 0x4, - /// The switch is in recovery position (hclk5/4). - B_0x5 = 0x5, - _, - }; - - pub const HPRE = enum(u4) { - Div1 = 0x0, - Div2 = 0x8, - Div4 = 0x9, - Div8 = 0xa, - Div16 = 0xb, - Div64 = 0xc, - Div128 = 0xd, - Div256 = 0xe, - Div512 = 0xf, - _, - }; - - pub const HSEEXT = enum(u1) { - /// HSE in analog mode (default after reset) - Analog = 0x0, - /// HSE in digital mode - Digital = 0x1, - }; - - pub const HSIDIV = enum(u2) { - /// division by 1, hsi(_ker)_ck = 64 MHz (default after reset). - Div1 = 0x0, - /// division by 2, hsi(_ker)_ck = 32 MHz. - Div2 = 0x1, - /// division by 4, hsi(_ker)_ck = 16 MHz. - Div4 = 0x2, - /// division by 8, hsi(_ker)_ck = 8 MHz. - Div8 = 0x3, - }; - - pub const I2C1_I3C1SEL = enum(u2) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// hsi_ker selected as peripheral clock - HSI = 0x2, - /// csi_ker selected as peripheral clock - CSI = 0x3, - }; - - pub const I2CSEL = enum(u2) { - /// pclk1 selected as kernel clock (default after reset). - PCLK1 = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// hsi_ker selected as peripheral clock - HSI = 0x2, - /// csi_ker selected as peripheral clock - CSI = 0x3, - }; - - pub const LPTIM1SEL = enum(u3) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_r selected as peripheral clock - PLL3_R = 0x2, - /// LSE selected as peripheral clock - LSE = 0x3, - /// LSI selected as peripheral clock - LSI = 0x4, - /// PER selected as peripheral clock - PER = 0x5, - _, - }; - - pub const LPTIMSEL = enum(u3) { - /// rcc_pclk4 selected as peripheral clock - PCLK4 = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_r selected as peripheral clock - PLL3_R = 0x2, - /// LSE selected as peripheral clock - LSE = 0x3, - /// LSI selected as peripheral clock - LSI = 0x4, - /// PER selected as peripheral clock - PER = 0x5, - _, - }; - - pub const LPUARTSEL = enum(u3) { - /// rcc_pclk_d4 selected as peripheral clock - PCLK4 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, - _, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCO1SEL = enum(u3) { - /// HSI selected for micro-controller clock output - HSI = 0x0, - /// LSE selected for micro-controller clock output - LSE = 0x1, - /// HSE selected for micro-controller clock output - HSE = 0x2, - /// pll1_q selected for micro-controller clock output - PLL1_Q = 0x3, - /// HSI48 selected for micro-controller clock output - HSI48 = 0x4, - _, - }; - - pub const MCO2SEL = enum(u3) { - /// System clock selected for micro-controller clock output - SYS = 0x0, - /// pll2_p selected for micro-controller clock output - PLL2_P = 0x1, - /// HSE selected for micro-controller clock output - HSE = 0x2, - /// pll1_p selected for micro-controller clock output - PLL1_P = 0x3, - /// CSI selected for micro-controller clock output - CSI = 0x4, - /// LSI selected for micro-controller clock output - LSI = 0x5, - _, - }; - - pub const MCOPRE = enum(u4) { - /// Divide by 1 - Div1 = 0x1, - /// Divide by 2 - Div2 = 0x2, - /// Divide by 3 - Div3 = 0x3, - /// Divide by 4 - Div4 = 0x4, - /// Divide by 5 - Div5 = 0x5, - /// Divide by 6 - Div6 = 0x6, - /// Divide by 7 - Div7 = 0x7, - /// Divide by 8 - Div8 = 0x8, - /// Divide by 9 - Div9 = 0x9, - /// Divide by 10 - Div10 = 0xa, - /// Divide by 11 - Div11 = 0xb, - /// Divide by 12 - Div12 = 0xc, - /// Divide by 13 - Div13 = 0xd, - /// Divide by 14 - Div14 = 0xe, - /// Divide by 15 - Div15 = 0xf, - _, - }; - - pub const OCTOSPISEL = enum(u2) { - /// hclk5 selected as kernel peripheral clock (default after reset). - HCLK5 = 0x0, - /// pll2_s_ck selected as kernel peripheral clock. - PLL2_S = 0x1, - _, - }; - - pub const PERSEL = enum(u2) { - /// HSI selected as peripheral clock - HSI = 0x0, - /// CSI selected as peripheral clock - CSI = 0x1, - /// HSE selected as peripheral clock - HSE = 0x2, - _, - }; - - pub const PLLDIV = enum(u7) { + pub const PLLI2SDIVR = enum(u5) { + /// PLLI2SDIVQ = /1 Div1 = 0x0, + /// PLLI2SDIVQ = /2 Div2 = 0x1, + /// PLLI2SDIVQ = /3 Div3 = 0x2, + /// PLLI2SDIVQ = /4 Div4 = 0x3, + /// PLLI2SDIVQ = /5 Div5 = 0x4, + /// PLLI2SDIVQ = /6 Div6 = 0x5, + /// PLLI2SDIVQ = /7 Div7 = 0x6, + /// PLLI2SDIVQ = /8 Div8 = 0x7, + /// PLLI2SDIVQ = /9 Div9 = 0x8, + /// PLLI2SDIVQ = /10 Div10 = 0x9, + /// PLLI2SDIVQ = /11 Div11 = 0xa, + /// PLLI2SDIVQ = /12 Div12 = 0xb, + /// PLLI2SDIVQ = /13 Div13 = 0xc, + /// PLLI2SDIVQ = /14 Div14 = 0xd, + /// PLLI2SDIVQ = /15 Div15 = 0xe, + /// PLLI2SDIVQ = /16 Div16 = 0xf, + /// PLLI2SDIVQ = /17 Div17 = 0x10, + /// PLLI2SDIVQ = /18 Div18 = 0x11, + /// PLLI2SDIVQ = /19 Div19 = 0x12, + /// PLLI2SDIVQ = /20 Div20 = 0x13, + /// PLLI2SDIVQ = /21 Div21 = 0x14, + /// PLLI2SDIVQ = /22 Div22 = 0x15, + /// PLLI2SDIVQ = /23 Div23 = 0x16, + /// PLLI2SDIVQ = /24 Div24 = 0x17, + /// PLLI2SDIVQ = /25 Div25 = 0x18, + /// PLLI2SDIVQ = /26 Div26 = 0x19, + /// PLLI2SDIVQ = /27 Div27 = 0x1a, + /// PLLI2SDIVQ = /28 Div28 = 0x1b, + /// PLLI2SDIVQ = /29 Div29 = 0x1c, + /// PLLI2SDIVQ = /30 Div30 = 0x1d, + /// PLLI2SDIVQ = /31 Div31 = 0x1e, + /// PLLI2SDIVQ = /32 Div32 = 0x1f, - Div33 = 0x20, - Div34 = 0x21, - Div35 = 0x22, - Div36 = 0x23, - Div37 = 0x24, - Div38 = 0x25, - Div39 = 0x26, - Div40 = 0x27, - Div41 = 0x28, - Div42 = 0x29, - Div43 = 0x2a, - Div44 = 0x2b, - Div45 = 0x2c, - Div46 = 0x2d, - Div47 = 0x2e, - Div48 = 0x2f, - Div49 = 0x30, - Div50 = 0x31, - Div51 = 0x32, - Div52 = 0x33, - Div53 = 0x34, - Div54 = 0x35, - Div55 = 0x36, - Div56 = 0x37, - Div57 = 0x38, - Div58 = 0x39, - Div59 = 0x3a, - Div60 = 0x3b, - Div61 = 0x3c, - Div62 = 0x3d, - Div63 = 0x3e, - Div64 = 0x3f, - Div65 = 0x40, - Div66 = 0x41, - Div67 = 0x42, - Div68 = 0x43, - Div69 = 0x44, - Div70 = 0x45, - Div71 = 0x46, - Div72 = 0x47, - Div73 = 0x48, - Div74 = 0x49, - Div75 = 0x4a, - Div76 = 0x4b, - Div77 = 0x4c, - Div78 = 0x4d, - Div79 = 0x4e, - Div80 = 0x4f, - Div81 = 0x50, - Div82 = 0x51, - Div83 = 0x52, - Div84 = 0x53, - Div85 = 0x54, - Div86 = 0x55, - Div87 = 0x56, - Div88 = 0x57, - Div89 = 0x58, - Div90 = 0x59, - Div91 = 0x5a, - Div92 = 0x5b, - Div93 = 0x5c, - Div94 = 0x5d, - Div95 = 0x5e, - Div96 = 0x5f, - Div97 = 0x60, - Div98 = 0x61, - Div99 = 0x62, - Div100 = 0x63, - Div101 = 0x64, - Div102 = 0x65, - Div103 = 0x66, - Div104 = 0x67, - Div105 = 0x68, - Div106 = 0x69, - Div107 = 0x6a, - Div108 = 0x6b, - Div109 = 0x6c, - Div110 = 0x6d, - Div111 = 0x6e, - Div112 = 0x6f, - Div113 = 0x70, - Div114 = 0x71, - Div115 = 0x72, - Div116 = 0x73, - Div117 = 0x74, - Div118 = 0x75, - Div119 = 0x76, - Div120 = 0x77, - Div121 = 0x78, - Div122 = 0x79, - Div123 = 0x7a, - Div124 = 0x7b, - Div125 = 0x7c, - Div126 = 0x7d, - Div127 = 0x7e, - Div128 = 0x7f, }; - pub const PLLDIVST = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, + pub const PLLI2SSRC = enum(u1) { + /// HSE or HSI depending on PLLSRC of PLLCFGR + HSE_HSI = 0x0, + /// External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry + External = 0x1, }; pub const PLLM = enum(u6) { - Div1 = 0x1, Div2 = 0x2, Div3 = 0x3, Div4 = 0x4, @@ -391422,472 +374306,530 @@ pub const types = struct { }; pub const PLLN = enum(u9) { - Mul8 = 0x7, - Mul9 = 0x8, - Mul10 = 0x9, - Mul11 = 0xa, - Mul12 = 0xb, - Mul13 = 0xc, - Mul14 = 0xd, - Mul15 = 0xe, - Mul16 = 0xf, - Mul17 = 0x10, - Mul18 = 0x11, - Mul19 = 0x12, - Mul20 = 0x13, - Mul21 = 0x14, - Mul22 = 0x15, - Mul23 = 0x16, - Mul24 = 0x17, - Mul25 = 0x18, - Mul26 = 0x19, - Mul27 = 0x1a, - Mul28 = 0x1b, - Mul29 = 0x1c, - Mul30 = 0x1d, - Mul31 = 0x1e, - Mul32 = 0x1f, - Mul33 = 0x20, - Mul34 = 0x21, - Mul35 = 0x22, - Mul36 = 0x23, - Mul37 = 0x24, - Mul38 = 0x25, - Mul39 = 0x26, - Mul40 = 0x27, - Mul41 = 0x28, - Mul42 = 0x29, - Mul43 = 0x2a, - Mul44 = 0x2b, - Mul45 = 0x2c, - Mul46 = 0x2d, - Mul47 = 0x2e, - Mul48 = 0x2f, - Mul49 = 0x30, - Mul50 = 0x31, - Mul51 = 0x32, - Mul52 = 0x33, - Mul53 = 0x34, - Mul54 = 0x35, - Mul55 = 0x36, - Mul56 = 0x37, - Mul57 = 0x38, - Mul58 = 0x39, - Mul59 = 0x3a, - Mul60 = 0x3b, - Mul61 = 0x3c, - Mul62 = 0x3d, - Mul63 = 0x3e, - Mul64 = 0x3f, - Mul65 = 0x40, - Mul66 = 0x41, - Mul67 = 0x42, - Mul68 = 0x43, - Mul69 = 0x44, - Mul70 = 0x45, - Mul71 = 0x46, - Mul72 = 0x47, - Mul73 = 0x48, - Mul74 = 0x49, - Mul75 = 0x4a, - Mul76 = 0x4b, - Mul77 = 0x4c, - Mul78 = 0x4d, - Mul79 = 0x4e, - Mul80 = 0x4f, - Mul81 = 0x50, - Mul82 = 0x51, - Mul83 = 0x52, - Mul84 = 0x53, - Mul85 = 0x54, - Mul86 = 0x55, - Mul87 = 0x56, - Mul88 = 0x57, - Mul89 = 0x58, - Mul90 = 0x59, - Mul91 = 0x5a, - Mul92 = 0x5b, - Mul93 = 0x5c, - Mul94 = 0x5d, - Mul95 = 0x5e, - Mul96 = 0x5f, - Mul97 = 0x60, - Mul98 = 0x61, - Mul99 = 0x62, - Mul100 = 0x63, - Mul101 = 0x64, - Mul102 = 0x65, - Mul103 = 0x66, - Mul104 = 0x67, - Mul105 = 0x68, - Mul106 = 0x69, - Mul107 = 0x6a, - Mul108 = 0x6b, - Mul109 = 0x6c, - Mul110 = 0x6d, - Mul111 = 0x6e, - Mul112 = 0x6f, - Mul113 = 0x70, - Mul114 = 0x71, - Mul115 = 0x72, - Mul116 = 0x73, - Mul117 = 0x74, - Mul118 = 0x75, - Mul119 = 0x76, - Mul120 = 0x77, - Mul121 = 0x78, - Mul122 = 0x79, - Mul123 = 0x7a, - Mul124 = 0x7b, - Mul125 = 0x7c, - Mul126 = 0x7d, - Mul127 = 0x7e, - Mul128 = 0x7f, - Mul129 = 0x80, - Mul130 = 0x81, - Mul131 = 0x82, - Mul132 = 0x83, - Mul133 = 0x84, - Mul134 = 0x85, - Mul135 = 0x86, - Mul136 = 0x87, - Mul137 = 0x88, - Mul138 = 0x89, - Mul139 = 0x8a, - Mul140 = 0x8b, - Mul141 = 0x8c, - Mul142 = 0x8d, - Mul143 = 0x8e, - Mul144 = 0x8f, - Mul145 = 0x90, - Mul146 = 0x91, - Mul147 = 0x92, - Mul148 = 0x93, - Mul149 = 0x94, - Mul150 = 0x95, - Mul151 = 0x96, - Mul152 = 0x97, - Mul153 = 0x98, - Mul154 = 0x99, - Mul155 = 0x9a, - Mul156 = 0x9b, - Mul157 = 0x9c, - Mul158 = 0x9d, - Mul159 = 0x9e, - Mul160 = 0x9f, - Mul161 = 0xa0, - Mul162 = 0xa1, - Mul163 = 0xa2, - Mul164 = 0xa3, - Mul165 = 0xa4, - Mul166 = 0xa5, - Mul167 = 0xa6, - Mul168 = 0xa7, - Mul169 = 0xa8, - Mul170 = 0xa9, - Mul171 = 0xaa, - Mul172 = 0xab, - Mul173 = 0xac, - Mul174 = 0xad, - Mul175 = 0xae, - Mul176 = 0xaf, - Mul177 = 0xb0, - Mul178 = 0xb1, - Mul179 = 0xb2, - Mul180 = 0xb3, - Mul181 = 0xb4, - Mul182 = 0xb5, - Mul183 = 0xb6, - Mul184 = 0xb7, - Mul185 = 0xb8, - Mul186 = 0xb9, - Mul187 = 0xba, - Mul188 = 0xbb, - Mul189 = 0xbc, - Mul190 = 0xbd, - Mul191 = 0xbe, - Mul192 = 0xbf, - Mul193 = 0xc0, - Mul194 = 0xc1, - Mul195 = 0xc2, - Mul196 = 0xc3, - Mul197 = 0xc4, - Mul198 = 0xc5, - Mul199 = 0xc6, - Mul200 = 0xc7, - Mul201 = 0xc8, - Mul202 = 0xc9, - Mul203 = 0xca, - Mul204 = 0xcb, - Mul205 = 0xcc, - Mul206 = 0xcd, - Mul207 = 0xce, - Mul208 = 0xcf, - Mul209 = 0xd0, - Mul210 = 0xd1, - Mul211 = 0xd2, - Mul212 = 0xd3, - Mul213 = 0xd4, - Mul214 = 0xd5, - Mul215 = 0xd6, - Mul216 = 0xd7, - Mul217 = 0xd8, - Mul218 = 0xd9, - Mul219 = 0xda, - Mul220 = 0xdb, - Mul221 = 0xdc, - Mul222 = 0xdd, - Mul223 = 0xde, - Mul224 = 0xdf, - Mul225 = 0xe0, - Mul226 = 0xe1, - Mul227 = 0xe2, - Mul228 = 0xe3, - Mul229 = 0xe4, - Mul230 = 0xe5, - Mul231 = 0xe6, - Mul232 = 0xe7, - Mul233 = 0xe8, - Mul234 = 0xe9, - Mul235 = 0xea, - Mul236 = 0xeb, - Mul237 = 0xec, - Mul238 = 0xed, - Mul239 = 0xee, - Mul240 = 0xef, - Mul241 = 0xf0, - Mul242 = 0xf1, - Mul243 = 0xf2, - Mul244 = 0xf3, - Mul245 = 0xf4, - Mul246 = 0xf5, - Mul247 = 0xf6, - Mul248 = 0xf7, - Mul249 = 0xf8, - Mul250 = 0xf9, - Mul251 = 0xfa, - Mul252 = 0xfb, - Mul253 = 0xfc, - Mul254 = 0xfd, - Mul255 = 0xfe, - Mul256 = 0xff, - Mul257 = 0x100, - Mul258 = 0x101, - Mul259 = 0x102, - Mul260 = 0x103, - Mul261 = 0x104, - Mul262 = 0x105, - Mul263 = 0x106, - Mul264 = 0x107, - Mul265 = 0x108, - Mul266 = 0x109, - Mul267 = 0x10a, - Mul268 = 0x10b, - Mul269 = 0x10c, - Mul270 = 0x10d, - Mul271 = 0x10e, - Mul272 = 0x10f, - Mul273 = 0x110, - Mul274 = 0x111, - Mul275 = 0x112, - Mul276 = 0x113, - Mul277 = 0x114, - Mul278 = 0x115, - Mul279 = 0x116, - Mul280 = 0x117, - Mul281 = 0x118, - Mul282 = 0x119, - Mul283 = 0x11a, - Mul284 = 0x11b, - Mul285 = 0x11c, - Mul286 = 0x11d, - Mul287 = 0x11e, - Mul288 = 0x11f, - Mul289 = 0x120, - Mul290 = 0x121, - Mul291 = 0x122, - Mul292 = 0x123, - Mul293 = 0x124, - Mul294 = 0x125, - Mul295 = 0x126, - Mul296 = 0x127, - Mul297 = 0x128, - Mul298 = 0x129, - Mul299 = 0x12a, - Mul300 = 0x12b, - Mul301 = 0x12c, - Mul302 = 0x12d, - Mul303 = 0x12e, - Mul304 = 0x12f, - Mul305 = 0x130, - Mul306 = 0x131, - Mul307 = 0x132, - Mul308 = 0x133, - Mul309 = 0x134, - Mul310 = 0x135, - Mul311 = 0x136, - Mul312 = 0x137, - Mul313 = 0x138, - Mul314 = 0x139, - Mul315 = 0x13a, - Mul316 = 0x13b, - Mul317 = 0x13c, - Mul318 = 0x13d, - Mul319 = 0x13e, - Mul320 = 0x13f, - Mul321 = 0x140, - Mul322 = 0x141, - Mul323 = 0x142, - Mul324 = 0x143, - Mul325 = 0x144, - Mul326 = 0x145, - Mul327 = 0x146, - Mul328 = 0x147, - Mul329 = 0x148, - Mul330 = 0x149, - Mul331 = 0x14a, - Mul332 = 0x14b, - Mul333 = 0x14c, - Mul334 = 0x14d, - Mul335 = 0x14e, - Mul336 = 0x14f, - Mul337 = 0x150, - Mul338 = 0x151, - Mul339 = 0x152, - Mul340 = 0x153, - Mul341 = 0x154, - Mul342 = 0x155, - Mul343 = 0x156, - Mul344 = 0x157, - Mul345 = 0x158, - Mul346 = 0x159, - Mul347 = 0x15a, - Mul348 = 0x15b, - Mul349 = 0x15c, - Mul350 = 0x15d, - Mul351 = 0x15e, - Mul352 = 0x15f, - Mul353 = 0x160, - Mul354 = 0x161, - Mul355 = 0x162, - Mul356 = 0x163, - Mul357 = 0x164, - Mul358 = 0x165, - Mul359 = 0x166, - Mul360 = 0x167, - Mul361 = 0x168, - Mul362 = 0x169, - Mul363 = 0x16a, - Mul364 = 0x16b, - Mul365 = 0x16c, - Mul366 = 0x16d, - Mul367 = 0x16e, - Mul368 = 0x16f, - Mul369 = 0x170, - Mul370 = 0x171, - Mul371 = 0x172, - Mul372 = 0x173, - Mul373 = 0x174, - Mul374 = 0x175, - Mul375 = 0x176, - Mul376 = 0x177, - Mul377 = 0x178, - Mul378 = 0x179, - Mul379 = 0x17a, - Mul380 = 0x17b, - Mul381 = 0x17c, - Mul382 = 0x17d, - Mul383 = 0x17e, - Mul384 = 0x17f, - Mul385 = 0x180, - Mul386 = 0x181, - Mul387 = 0x182, - Mul388 = 0x183, - Mul389 = 0x184, - Mul390 = 0x185, - Mul391 = 0x186, - Mul392 = 0x187, - Mul393 = 0x188, - Mul394 = 0x189, - Mul395 = 0x18a, - Mul396 = 0x18b, - Mul397 = 0x18c, - Mul398 = 0x18d, - Mul399 = 0x18e, - Mul400 = 0x18f, - Mul401 = 0x190, - Mul402 = 0x191, - Mul403 = 0x192, - Mul404 = 0x193, - Mul405 = 0x194, - Mul406 = 0x195, - Mul407 = 0x196, - Mul408 = 0x197, - Mul409 = 0x198, - Mul410 = 0x199, - Mul411 = 0x19a, - Mul412 = 0x19b, - Mul413 = 0x19c, - Mul414 = 0x19d, - Mul415 = 0x19e, - Mul416 = 0x19f, - Mul417 = 0x1a0, - Mul418 = 0x1a1, - Mul419 = 0x1a2, - Mul420 = 0x1a3, + Mul50 = 0x32, + Mul51 = 0x33, + Mul52 = 0x34, + Mul53 = 0x35, + Mul54 = 0x36, + Mul55 = 0x37, + Mul56 = 0x38, + Mul57 = 0x39, + Mul58 = 0x3a, + Mul59 = 0x3b, + Mul60 = 0x3c, + Mul61 = 0x3d, + Mul62 = 0x3e, + Mul63 = 0x3f, + Mul64 = 0x40, + Mul65 = 0x41, + Mul66 = 0x42, + Mul67 = 0x43, + Mul68 = 0x44, + Mul69 = 0x45, + Mul70 = 0x46, + Mul71 = 0x47, + Mul72 = 0x48, + Mul73 = 0x49, + Mul74 = 0x4a, + Mul75 = 0x4b, + Mul76 = 0x4c, + Mul77 = 0x4d, + Mul78 = 0x4e, + Mul79 = 0x4f, + Mul80 = 0x50, + Mul81 = 0x51, + Mul82 = 0x52, + Mul83 = 0x53, + Mul84 = 0x54, + Mul85 = 0x55, + Mul86 = 0x56, + Mul87 = 0x57, + Mul88 = 0x58, + Mul89 = 0x59, + Mul90 = 0x5a, + Mul91 = 0x5b, + Mul92 = 0x5c, + Mul93 = 0x5d, + Mul94 = 0x5e, + Mul95 = 0x5f, + Mul96 = 0x60, + Mul97 = 0x61, + Mul98 = 0x62, + Mul99 = 0x63, + Mul100 = 0x64, + Mul101 = 0x65, + Mul102 = 0x66, + Mul103 = 0x67, + Mul104 = 0x68, + Mul105 = 0x69, + Mul106 = 0x6a, + Mul107 = 0x6b, + Mul108 = 0x6c, + Mul109 = 0x6d, + Mul110 = 0x6e, + Mul111 = 0x6f, + Mul112 = 0x70, + Mul113 = 0x71, + Mul114 = 0x72, + Mul115 = 0x73, + Mul116 = 0x74, + Mul117 = 0x75, + Mul118 = 0x76, + Mul119 = 0x77, + Mul120 = 0x78, + Mul121 = 0x79, + Mul122 = 0x7a, + Mul123 = 0x7b, + Mul124 = 0x7c, + Mul125 = 0x7d, + Mul126 = 0x7e, + Mul127 = 0x7f, + Mul128 = 0x80, + Mul129 = 0x81, + Mul130 = 0x82, + Mul131 = 0x83, + Mul132 = 0x84, + Mul133 = 0x85, + Mul134 = 0x86, + Mul135 = 0x87, + Mul136 = 0x88, + Mul137 = 0x89, + Mul138 = 0x8a, + Mul139 = 0x8b, + Mul140 = 0x8c, + Mul141 = 0x8d, + Mul142 = 0x8e, + Mul143 = 0x8f, + Mul144 = 0x90, + Mul145 = 0x91, + Mul146 = 0x92, + Mul147 = 0x93, + Mul148 = 0x94, + Mul149 = 0x95, + Mul150 = 0x96, + Mul151 = 0x97, + Mul152 = 0x98, + Mul153 = 0x99, + Mul154 = 0x9a, + Mul155 = 0x9b, + Mul156 = 0x9c, + Mul157 = 0x9d, + Mul158 = 0x9e, + Mul159 = 0x9f, + Mul160 = 0xa0, + Mul161 = 0xa1, + Mul162 = 0xa2, + Mul163 = 0xa3, + Mul164 = 0xa4, + Mul165 = 0xa5, + Mul166 = 0xa6, + Mul167 = 0xa7, + Mul168 = 0xa8, + Mul169 = 0xa9, + Mul170 = 0xaa, + Mul171 = 0xab, + Mul172 = 0xac, + Mul173 = 0xad, + Mul174 = 0xae, + Mul175 = 0xaf, + Mul176 = 0xb0, + Mul177 = 0xb1, + Mul178 = 0xb2, + Mul179 = 0xb3, + Mul180 = 0xb4, + Mul181 = 0xb5, + Mul182 = 0xb6, + Mul183 = 0xb7, + Mul184 = 0xb8, + Mul185 = 0xb9, + Mul186 = 0xba, + Mul187 = 0xbb, + Mul188 = 0xbc, + Mul189 = 0xbd, + Mul190 = 0xbe, + Mul191 = 0xbf, + Mul192 = 0xc0, + Mul193 = 0xc1, + Mul194 = 0xc2, + Mul195 = 0xc3, + Mul196 = 0xc4, + Mul197 = 0xc5, + Mul198 = 0xc6, + Mul199 = 0xc7, + Mul200 = 0xc8, + Mul201 = 0xc9, + Mul202 = 0xca, + Mul203 = 0xcb, + Mul204 = 0xcc, + Mul205 = 0xcd, + Mul206 = 0xce, + Mul207 = 0xcf, + Mul208 = 0xd0, + Mul209 = 0xd1, + Mul210 = 0xd2, + Mul211 = 0xd3, + Mul212 = 0xd4, + Mul213 = 0xd5, + Mul214 = 0xd6, + Mul215 = 0xd7, + Mul216 = 0xd8, + Mul217 = 0xd9, + Mul218 = 0xda, + Mul219 = 0xdb, + Mul220 = 0xdc, + Mul221 = 0xdd, + Mul222 = 0xde, + Mul223 = 0xdf, + Mul224 = 0xe0, + Mul225 = 0xe1, + Mul226 = 0xe2, + Mul227 = 0xe3, + Mul228 = 0xe4, + Mul229 = 0xe5, + Mul230 = 0xe6, + Mul231 = 0xe7, + Mul232 = 0xe8, + Mul233 = 0xe9, + Mul234 = 0xea, + Mul235 = 0xeb, + Mul236 = 0xec, + Mul237 = 0xed, + Mul238 = 0xee, + Mul239 = 0xef, + Mul240 = 0xf0, + Mul241 = 0xf1, + Mul242 = 0xf2, + Mul243 = 0xf3, + Mul244 = 0xf4, + Mul245 = 0xf5, + Mul246 = 0xf6, + Mul247 = 0xf7, + Mul248 = 0xf8, + Mul249 = 0xf9, + Mul250 = 0xfa, + Mul251 = 0xfb, + Mul252 = 0xfc, + Mul253 = 0xfd, + Mul254 = 0xfe, + Mul255 = 0xff, + Mul256 = 0x100, + Mul257 = 0x101, + Mul258 = 0x102, + Mul259 = 0x103, + Mul260 = 0x104, + Mul261 = 0x105, + Mul262 = 0x106, + Mul263 = 0x107, + Mul264 = 0x108, + Mul265 = 0x109, + Mul266 = 0x10a, + Mul267 = 0x10b, + Mul268 = 0x10c, + Mul269 = 0x10d, + Mul270 = 0x10e, + Mul271 = 0x10f, + Mul272 = 0x110, + Mul273 = 0x111, + Mul274 = 0x112, + Mul275 = 0x113, + Mul276 = 0x114, + Mul277 = 0x115, + Mul278 = 0x116, + Mul279 = 0x117, + Mul280 = 0x118, + Mul281 = 0x119, + Mul282 = 0x11a, + Mul283 = 0x11b, + Mul284 = 0x11c, + Mul285 = 0x11d, + Mul286 = 0x11e, + Mul287 = 0x11f, + Mul288 = 0x120, + Mul289 = 0x121, + Mul290 = 0x122, + Mul291 = 0x123, + Mul292 = 0x124, + Mul293 = 0x125, + Mul294 = 0x126, + Mul295 = 0x127, + Mul296 = 0x128, + Mul297 = 0x129, + Mul298 = 0x12a, + Mul299 = 0x12b, + Mul300 = 0x12c, + Mul301 = 0x12d, + Mul302 = 0x12e, + Mul303 = 0x12f, + Mul304 = 0x130, + Mul305 = 0x131, + Mul306 = 0x132, + Mul307 = 0x133, + Mul308 = 0x134, + Mul309 = 0x135, + Mul310 = 0x136, + Mul311 = 0x137, + Mul312 = 0x138, + Mul313 = 0x139, + Mul314 = 0x13a, + Mul315 = 0x13b, + Mul316 = 0x13c, + Mul317 = 0x13d, + Mul318 = 0x13e, + Mul319 = 0x13f, + Mul320 = 0x140, + Mul321 = 0x141, + Mul322 = 0x142, + Mul323 = 0x143, + Mul324 = 0x144, + Mul325 = 0x145, + Mul326 = 0x146, + Mul327 = 0x147, + Mul328 = 0x148, + Mul329 = 0x149, + Mul330 = 0x14a, + Mul331 = 0x14b, + Mul332 = 0x14c, + Mul333 = 0x14d, + Mul334 = 0x14e, + Mul335 = 0x14f, + Mul336 = 0x150, + Mul337 = 0x151, + Mul338 = 0x152, + Mul339 = 0x153, + Mul340 = 0x154, + Mul341 = 0x155, + Mul342 = 0x156, + Mul343 = 0x157, + Mul344 = 0x158, + Mul345 = 0x159, + Mul346 = 0x15a, + Mul347 = 0x15b, + Mul348 = 0x15c, + Mul349 = 0x15d, + Mul350 = 0x15e, + Mul351 = 0x15f, + Mul352 = 0x160, + Mul353 = 0x161, + Mul354 = 0x162, + Mul355 = 0x163, + Mul356 = 0x164, + Mul357 = 0x165, + Mul358 = 0x166, + Mul359 = 0x167, + Mul360 = 0x168, + Mul361 = 0x169, + Mul362 = 0x16a, + Mul363 = 0x16b, + Mul364 = 0x16c, + Mul365 = 0x16d, + Mul366 = 0x16e, + Mul367 = 0x16f, + Mul368 = 0x170, + Mul369 = 0x171, + Mul370 = 0x172, + Mul371 = 0x173, + Mul372 = 0x174, + Mul373 = 0x175, + Mul374 = 0x176, + Mul375 = 0x177, + Mul376 = 0x178, + Mul377 = 0x179, + Mul378 = 0x17a, + Mul379 = 0x17b, + Mul380 = 0x17c, + Mul381 = 0x17d, + Mul382 = 0x17e, + Mul383 = 0x17f, + Mul384 = 0x180, + Mul385 = 0x181, + Mul386 = 0x182, + Mul387 = 0x183, + Mul388 = 0x184, + Mul389 = 0x185, + Mul390 = 0x186, + Mul391 = 0x187, + Mul392 = 0x188, + Mul393 = 0x189, + Mul394 = 0x18a, + Mul395 = 0x18b, + Mul396 = 0x18c, + Mul397 = 0x18d, + Mul398 = 0x18e, + Mul399 = 0x18f, + Mul400 = 0x190, + Mul401 = 0x191, + Mul402 = 0x192, + Mul403 = 0x193, + Mul404 = 0x194, + Mul405 = 0x195, + Mul406 = 0x196, + Mul407 = 0x197, + Mul408 = 0x198, + Mul409 = 0x199, + Mul410 = 0x19a, + Mul411 = 0x19b, + Mul412 = 0x19c, + Mul413 = 0x19d, + Mul414 = 0x19e, + Mul415 = 0x19f, + Mul416 = 0x1a0, + Mul417 = 0x1a1, + Mul418 = 0x1a2, + Mul419 = 0x1a3, + Mul420 = 0x1a4, + Mul421 = 0x1a5, + Mul422 = 0x1a6, + Mul423 = 0x1a7, + Mul424 = 0x1a8, + Mul425 = 0x1a9, + Mul426 = 0x1aa, + Mul427 = 0x1ab, + Mul428 = 0x1ac, + Mul429 = 0x1ad, + Mul430 = 0x1ae, + Mul431 = 0x1af, + Mul432 = 0x1b0, _, }; - pub const PLLRGE = enum(u2) { - /// Frequency is between 1 and 2 MHz - Range1 = 0x0, - /// Frequency is between 2 and 4 MHz - Range2 = 0x1, - /// Frequency is between 4 and 8 MHz - Range4 = 0x2, - /// Frequency is between 8 and 16 MHz - Range8 = 0x3, + pub const PLLP = enum(u2) { + /// PLLP=2 + Div2 = 0x0, + /// PLLP=4 + Div4 = 0x1, + /// PLLP=6 + Div6 = 0x2, + /// PLLP=8 + Div8 = 0x3, }; - pub const PLLSRC = enum(u2) { - /// HSI selected as PLL clock - HSI = 0x0, - /// CSI selected as PLL clock - CSI = 0x1, - /// HSE selected as PLL clock - HSE = 0x2, - /// No clock sent to DIVMx dividers and PLLs - DISABLE = 0x3, + pub const PLLQ = enum(u4) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + _, }; - pub const PLLVCOSEL = enum(u1) { - /// VCOH selected (default after reset). - WideVCO = 0x0, - /// VCOL selected. - MediumVCO = 0x1, + pub const PLLR = enum(u3) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + _, + }; + + pub const PLLSAIDIVQ = enum(u5) { + /// PLLSAIDIVQ = /1 + Div1 = 0x0, + /// PLLSAIDIVQ = /2 + Div2 = 0x1, + /// PLLSAIDIVQ = /3 + Div3 = 0x2, + /// PLLSAIDIVQ = /4 + Div4 = 0x3, + /// PLLSAIDIVQ = /5 + Div5 = 0x4, + /// PLLSAIDIVQ = /6 + Div6 = 0x5, + /// PLLSAIDIVQ = /7 + Div7 = 0x6, + /// PLLSAIDIVQ = /8 + Div8 = 0x7, + /// PLLSAIDIVQ = /9 + Div9 = 0x8, + /// PLLSAIDIVQ = /10 + Div10 = 0x9, + /// PLLSAIDIVQ = /11 + Div11 = 0xa, + /// PLLSAIDIVQ = /12 + Div12 = 0xb, + /// PLLSAIDIVQ = /13 + Div13 = 0xc, + /// PLLSAIDIVQ = /14 + Div14 = 0xd, + /// PLLSAIDIVQ = /15 + Div15 = 0xe, + /// PLLSAIDIVQ = /16 + Div16 = 0xf, + /// PLLSAIDIVQ = /17 + Div17 = 0x10, + /// PLLSAIDIVQ = /18 + Div18 = 0x11, + /// PLLSAIDIVQ = /19 + Div19 = 0x12, + /// PLLSAIDIVQ = /20 + Div20 = 0x13, + /// PLLSAIDIVQ = /21 + Div21 = 0x14, + /// PLLSAIDIVQ = /22 + Div22 = 0x15, + /// PLLSAIDIVQ = /23 + Div23 = 0x16, + /// PLLSAIDIVQ = /24 + Div24 = 0x17, + /// PLLSAIDIVQ = /25 + Div25 = 0x18, + /// PLLSAIDIVQ = /26 + Div26 = 0x19, + /// PLLSAIDIVQ = /27 + Div27 = 0x1a, + /// PLLSAIDIVQ = /28 + Div28 = 0x1b, + /// PLLSAIDIVQ = /29 + Div29 = 0x1c, + /// PLLSAIDIVQ = /30 + Div30 = 0x1d, + /// PLLSAIDIVQ = /31 + Div31 = 0x1e, + /// PLLSAIDIVQ = /32 + Div32 = 0x1f, + }; + + pub const PLLSAIDIVR = enum(u2) { + /// PLLSAIDIVR = /2 + Div2 = 0x0, + /// PLLSAIDIVR = /4 + Div4 = 0x1, + /// PLLSAIDIVR = /8 + Div8 = 0x2, + /// PLLSAIDIVR = /16 + Div16 = 0x3, + }; + + pub const PLLSRC = enum(u1) { + /// HSI clock selected as PLL and PLLI2S clock entry + HSI = 0x0, + /// HSE oscillator clock selected as PLL and PLLI2S clock entry + HSE = 0x1, }; pub const PPRE = enum(u3) { - /// rcc_hclk not divided + /// HCLK not divided Div1 = 0x0, - /// rcc_hclk divided by 2 + /// HCLK divided by 2 Div2 = 0x4, - /// rcc_hclk divided by 4 + /// HCLK divided by 4 Div4 = 0x5, - /// rcc_hclk divided by 8 + /// HCLK divided by 8 Div8 = 0x6, - /// rcc_hclk divided by 16 + /// HCLK divided by 16 Div16 = 0x7, _, }; - pub const PSSISEL = enum(u1) { - /// pll3_r_ck selected as kernel peripheral clock (default after reset). - PLL3_R = 0x0, - /// per_ck selected as kernel peripheral clock. - PER = 0x1, - }; - pub const RTCSEL = enum(u2) { /// No clock DISABLE = 0x0, @@ -391899,6775 +374841,5010 @@ pub const types = struct { HSE = 0x3, }; - pub const SAI1SEL = enum(u3) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_p selected as peripheral clock - PLL3_P = 0x2, - /// I2S_CKIN selected as peripheral clock - I2S_CKIN = 0x3, - /// PER selected as peripheral clock - PER = 0x4, - _, - }; - - pub const SAI2SEL = enum(u3) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_p selected as peripheral clock - PLL3_P = 0x2, - /// I2S_CKIN selected as peripheral clock + pub const SAI1SRC = enum(u2) { + /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + PLLSAI = 0x0, + /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + PLLI2S = 0x1, + /// SAI1 clock frequency = f(PLL_R) + PLLR = 0x2, + /// I2S_CKIN Alternate function input frequency I2S_CKIN = 0x3, - /// PER selected as peripheral clock - PER = 0x4, - /// spdifrx_symb_ck selected as SAI2 kernel clock. - SPDIFRX_SYMB = 0x5, - _, - }; - - pub const SDMMCSEL = enum(u1) { - /// pll2_s_ck selected as kernel peripheral clock (default after reset). - PLL2_S = 0x0, - /// pll2_t_ck selected as kernel peripheral clock. - PLL2_T = 0x1, }; - pub const SPDIFRXSEL = enum(u2) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_r selected as peripheral clock - PLL2_R = 0x1, - /// pll3_r selected as peripheral clock - PLL3_R = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, + pub const SAI2SRC = enum(u2) { + /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + PLLSAI = 0x0, + /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + PLLI2S = 0x1, + /// SAI2 clock frequency = f(PLL_R) + PLLR = 0x2, + /// SAI2 clock frequency = Alternate function input frequency + HSI_HSE = 0x3, }; - pub const SPI123SEL = enum(u3) { - /// pll1_q_ck selected as SPI/I2S1 and 7 kernel clock (default after reset). - PLL1_Q = 0x0, - /// pll2_p_ck selected as SPI/I2S1 and 7 kernel clock. - PLL2_P = 0x1, - /// pll3_p_ck selected as SPI/I2S1 and 7 kernel clock. - PLL3_P = 0x2, - /// I2S_CKIN selected as SPI/I2S1 and 7 kernel clock. - I2S_CKIN = 0x3, - /// per_ck selected as SPI/I2S1,and 7 kernel clock. - PER = 0x4, + pub const SAIASRC = enum(u2) { + /// SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + PLLSAI = 0x0, + /// SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + PLLI2S = 0x1, + /// SAI1-A clock frequency = Alternate function input frequency + I2S_CKIN = 0x2, _, }; - pub const SPI45SEL = enum(u3) { - /// APB2 clock selected as peripheral clock - PCLK2 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// HSE selected as peripheral clock - HSE = 0x5, + pub const SAIBSRC = enum(u2) { + /// SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + PLLSAI = 0x0, + /// SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + PLLI2S = 0x1, + /// SAI1-B clock frequency = Alternate function input frequency + I2S_CKIN = 0x2, _, }; - pub const SPI6SEL = enum(u3) { - /// rcc_pclk4 selected as peripheral clock - PCLK4 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// HSE selected as peripheral clock - HSE = 0x5, - _, + pub const SDIOSEL = enum(u1) { + /// 48 MHz clock is selected as SD clock + CLK48 = 0x0, + /// System clock is selected as SD clock + SYS = 0x1, }; - pub const STOPKERWUCK = enum(u1) { - /// HSI selected as wake up clock from system Stop (default after reset). - HSI = 0x0, - /// CSI selected as wake up clock from system Stop. - CSI = 0x1, + pub const SPDIFRXSEL = enum(u1) { + /// SPDIF-Rx clock from PLL is selected + PLL1_R = 0x0, + /// SPDIF-Rx clock from PLLI2S is selected + PLLI2S1_P = 0x1, }; - pub const STOPWUCK = enum(u1) { - /// HSI selected as wake up clock from system Stop - HSI = 0x0, - /// CSI selected as wake up clock from system Stop - CSI = 0x1, + pub const SPREADSEL = enum(u1) { + /// Center spread + Center = 0x0, + /// Down spread + Down = 0x1, }; - pub const SW = enum(u3) { - /// HSI selected as system clock + pub const SW = enum(u2) { + /// HSI oscillator used as system clock HSI = 0x0, - /// CSI selected as system clock - CSI = 0x1, - /// HSE selected as system clock - HSE = 0x2, - /// PLL1 selected as system clock - PLL1_P = 0x3, + /// HSE oscillator used as system clock + HSE = 0x1, + /// PLL used as system clock + PLL1_P = 0x2, _, }; pub const TIMPRE = enum(u1) { - /// Timer kernel clock equal to 2x pclk by default - DefaultX2 = 0x0, - /// Timer kernel clock equal to 4x pclk by default - DefaultX4 = 0x1, - }; - - pub const USART1SEL = enum(u3) { - /// rcc_pclk2 selected as peripheral clock - PCLK2 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, - _, - }; - - pub const USART234578SEL = enum(u3) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, - _, - }; - - pub const USBPDCTRL = enum(u1) { - /// In SUSPEND, PHY state machine, bias and USBPHYC PLL remain powered (default after reset). - RemainPowered = 0x0, - /// In SUSPEND, PHY state machine, bias and USBPHYC PLL are powered down. - PowerDown = 0x1, - }; - - pub const USBPHYCSEL = enum(u2) { - /// hse_ker_ck (default after reset). - HSE = 0x0, - /// hse_ker_ck / 2. - HSE_DIV_2 = 0x1, - /// pll3_q_ck. - PLL3_Q = 0x2, - _, - }; - - pub const USBREFCKSEL = enum(u4) { - /// The kernel clock frequency provided to the USBPHYC is 16 MHz. - Mhz16 = 0x3, - /// The kernel clock frequency provided to the USBPHYC is 19.2 MHz. - Mhz19_2 = 0x8, - /// The kernel clock frequency provided to the USBPHYC is 20MHz. - Mhz20 = 0x9, - /// The kernel clock frequency provided to the USBPHYC is 24 MHz (default after reset). - Mhz24 = 0xa, - /// The kernel clock frequency provided to the USBPHYC is 32 MHz. - Mhz32 = 0xb, - /// The kernel clock frequency provided to the USBPHYC is 26 MHz. - Mhz26 = 0xe, - _, - }; - - pub const USB_OTG_FSSEL = enum(u2) { - /// hsi48_ker_ck (default after reset). - HSI48 = 0x0, - /// pll3_q_ck. - PLL3_Q = 0x1, - /// hse_ker_ck. - HSE = 0x2, - /// clk48mohci. - CLK48MOHCI = 0x3, - }; - - pub const XSPISWP = enum(u3) { - /// The switch is in neutral mode and output clock is gated (default after reset). - B_0x0 = 0x0, - /// The switch is selecting hclk5. - B_0x1 = 0x1, - /// The switch is selecting pll2_s_ck. - B_0x2 = 0x2, - /// The switch is selecting pll2_t_ck. - B_0x3 = 0x3, - /// The switch is in recovery position (hclk5/4). - B_0x4 = 0x4, - _, + /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx + Mul2 = 0x0, + /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx + Mul4 = 0x1, }; - /// Reset and clock control. + /// Reset and clock control pub const RCC = extern struct { - /// RCC source control register. + /// clock control register CR: mmio.Mmio(packed struct(u32) { - /// HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 0 or STOPKERWUCK = 0. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW switch) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1. + /// Internal high-speed clock enable HSION: u1, - /// HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION. - HSIKERON: u1, - /// HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable. + /// Internal high-speed clock ready flag HSIRDY: u1, - /// HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored. - HSIDIV: packed union { - raw: u2, - value: HSIDIV, - }, - /// HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. clock setting is completed). - HSIDIVF: u1, - reserved7: u1, - /// CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1. - CSION: u1, - /// CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request). - CSIRDY: u1, - /// CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION. - CSIKERON: u1, - reserved12: u2, - /// HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode. - HSI48ON: u1, - /// HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable. - HSI48RDY: u1, - reserved16: u2, - /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1. + reserved3: u1, + /// Internal high-speed clock trimming + HSITRIM: u5, + /// Internal high-speed clock calibration + HSICAL: u8, + /// HSE clock enable HSEON: u1, - /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. + /// HSE clock ready flag HSERDY: u1, - /// HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + /// HSE clock bypass HSEBYP: u1, - /// external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled. - HSEEXT: packed union { - raw: u1, - value: HSEEXT, - }, - /// HSE clock security system enable Set by software to enable clock security system on HSE. This bit is set only (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected. - HSECSSON: u1, - reserved24: u3, - /// PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3) or if FMCCKP = 1, or if XSPICKP = 1. + /// Clock security system enable + CSSON: u1, + reserved24: u4, + /// Main PLL (PLL) enable PLLON: u1, - /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + /// Main PLL (PLL) clock ready flag PLLRDY: u1, - padding: u6, - }), - /// RCC HSI calibration register. - HSICFGR: mmio.Mmio(packed struct(u32) { - /// HSI clock calibration Set by hardware by option byte loading. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value. - HSICAL: u12, - reserved24: u12, - /// HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_opt. Note: The reset value of the field is 0x40. - HSITRIM: u7, - padding: u1, - }), - /// RCC clock recovery RC register. - CRRCR: mmio.Mmio(packed struct(u32) { - /// Internal RC 48 MHz clock calibration Set by hardware by option byte loading. Read-only. - HSI48CAL: u10, - padding: u22, - }), - /// RCC CSI calibration register. - CSICFGR: mmio.Mmio(packed struct(u32) { - /// CSI clock calibration Set by hardware by option byte loading. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value. - CSICAL: u8, - reserved24: u16, - /// CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_opt) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_opt. Note: The reset value of the field is 0x20. - CSITRIM: u6, + /// PLLI2S enable + PLLI2SON: u1, + /// PLLI2S clock ready flag + PLLI2SRDY: u1, + /// PLLSAI enable + PLLSAION: u1, + /// PLLSAI clock ready flag + PLLSAIRDY: u1, padding: u2, }), - /// RCC clock configuration register. - CFGR: mmio.Mmio(packed struct(u32) { - /// system clock switch Set and reset by software to select system clock source (sys_ck). Set by hardware in order to force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode or in case of failure of the HSE when used directly or indirectly as system clock. others: reserved. - SW: packed union { - raw: u3, - value: SW, - }, - /// system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. others: reserved. - SWS: packed union { - raw: u3, - value: SW, - }, - /// system clock selection after a wake up from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details. STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10). - STOPWUCK: packed union { - raw: u1, - value: STOPWUCK, - }, - /// kernel clock selection after a wake up from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details. - STOPKERWUCK: packed union { - raw: u1, - value: STOPKERWUCK, - }, - /// HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ... - RTCPRE: u6, - reserved15: u1, - /// timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. or 4, else it is equal to 4 x Frcc_pclkx_d2 Refer to Table 64: Ratio between clock timer and pclk for more details. - TIMPRE: packed union { - raw: u1, - value: TIMPRE, - }, - reserved18: u2, - /// MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... - MCO1PRE: packed union { - raw: u4, - value: MCOPRE, - }, - /// Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved. - MCO1SEL: packed union { - raw: u3, - value: MCO1SEL, - }, - /// MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... - MCO2PRE: packed union { - raw: u4, - value: MCOPRE, - }, - /// microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved. - MCO2SEL: packed union { - raw: u3, - value: MCO2SEL, - }, - }), - reserved24: [4]u8, - /// RCC CPU domain clock configuration register. - CDCFGR: mmio.Mmio(packed struct(u32) { - /// CPU domain core prescaler Set and reset by software to control the CPU clock division factor. Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks. After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register. 0xxx: sys_ck not divided (default after reset). - CPRE: packed union { - raw: u4, - value: HPRE, - }, - padding: u28, - }), - /// RCC AHB clock configuration register. - BMCFGR: mmio.Mmio(packed struct(u32) { - /// Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk[5:1] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk[5:1] = rcc_aclk = sys_bus_ck. - BMPRE: packed union { - raw: u4, - value: HPRE, - }, - padding: u28, - }), - /// RCC APB clocks configuration register. - APBCFGR: mmio.Mmio(packed struct(u32) { - /// CPU domain APB1 prescaler Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE1 write. 0xx: rcc_pclk1 = sys_bus_ck (default after reset). - PPRE1: packed union { - raw: u3, - value: PPRE, - }, - reserved4: u1, - /// CPU domain APB2 prescaler Set and reset by software to control the division factor of rcc_pclk2. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE2 write. 0xx: rcc_pclk2 = sys_bus_ck (default after reset). - PPRE2: packed union { - raw: u3, - value: PPRE, - }, - reserved8: u1, - /// CPU domain APB4 prescaler Set and reset by software to control the division factor of rcc_pclk4. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE4 write. 0xx: rcc_pclk4 = sys_bus_ck (default after reset). - PPRE4: packed union { - raw: u3, - value: PPRE, - }, - reserved12: u1, - /// CPU domain APB5 prescaler Set and reset by software to control the division factor of rcc_pclk5. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE5 write. 0xx: rcc_pclk5 = sys_bus_ck (default after reset). - PPRE5: packed union { - raw: u3, - value: PPRE, - }, - padding: u17, - }), - reserved40: [4]u8, - /// RCC PLLs clock source selection register. - PLLCKSELR: mmio.Mmio(packed struct(u32) { - /// DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, PLLSRC must be set to 11. - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - reserved4: u2, - /// prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... - DIVM: packed union { + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM: packed union { raw: u6, value: PLLM, }, - padding: u22, - }), - /// RCC PLLs configuration register. - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. - PLLFRACEN: u1, - /// PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref1_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref1_ck must be between 1 and 2 MHz). - PLLVCOSEL: packed union { - raw: u1, - value: PLLVCOSEL, - }, - /// PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks. - PLLSSCGEN: u1, - /// PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. - PLLRGE: packed union { - raw: u2, - value: PLLRGE, - }, - /// PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. - DIVPEN: u1, - /// PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. - DIVQEN: u1, - /// PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. - DIVREN: u1, - /// PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used. - DIVSEN: u1, - /// PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used. - DIVTEN: u1, - padding: u22, - }), - /// RCC PLL dividers configuration register 1. - PLLDIVR: mmio.Mmio(packed struct(u32) { - /// multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = PLL1RDY = 0). ..........: not used ... ... Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x DIVN1, when fractional value 0 has been loaded into FRACN, with: DIVN1 between 8 and 420 The input frequency Fref1_ck must be between 1 and 16 MHz. + /// Main PLL (PLL) multiplication factor for VCO PLLN: packed union { raw: u9, value: PLLN, }, - /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1DIVPEN = 0. ... + reserved16: u1, + /// Main PLL (PLL) division factor for main system clock PLLP: packed union { - raw: u7, - value: PLLDIV, + raw: u2, + value: PLLP, }, - /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1DIVQEN = 0. ... - PLLQ: packed union { - raw: u7, - value: PLLDIV, + reserved22: u4, + /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + PLLSRC: packed union { + raw: u1, + value: PLLSRC, }, reserved24: u1, - /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1DIVREN = 0. ... + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ: packed union { + raw: u4, + value: PLLQ, + }, + /// PLL division factor for I2S and System clocks PLLR: packed union { - raw: u7, - value: PLLDIV, + raw: u3, + value: PLLR, }, padding: u1, }), - /// RCC PLL fractional divider register. - PLLFRACR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544 MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (DIVN1 + (FRACN / 213)), with DIVN1 between 8 and 420 FRACN can be between 0 and 213- 1 The input frequency Fref1_ck must be between 1 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACLE to 0. Write the new fractional value into FRACN. Set the bit PLL1FRACLE to 1. - FRACN: u13, - padding: u16, - }), - reserved76: [20]u8, - /// RCC AHB peripheral kernel clock selection register. - AHBPERCKSELR: mmio.Mmio(packed struct(u32) { - /// FMC kernel clock source selection Set and reset by software. - FMCSEL: packed union { - raw: u2, - value: FMCSEL, - }, - /// SDMMC1 and SDMMC2 kernel clock source selection Set and reset by software. - SDMMCSEL: packed union { - raw: u1, - value: SDMMCSEL, - }, - reserved4: u1, - /// XSPI1 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock. - OCTOSPI1SEL: packed union { + /// clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { raw: u2, - value: OCTOSPISEL, + value: SW, }, - /// XSPI2 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock. - OCTOSPI2SEL: packed union { + /// System clock switch status + SWS: packed union { raw: u2, - value: OCTOSPISEL, + value: SW, }, - /// USBPHYC kernel clock frequency selection Set and reset by software. This field is used to indicate to the USBPHYC, the frequency of the reference kernel clock provided to the USBPHYC. others: reserved. - USBREFCKSEL: packed union { + /// AHB prescaler + HPRE: packed union { raw: u4, - value: USBREFCKSEL, - }, - /// USBPHYC kernel clock source selection Set and reset by software. - USBPHYCSEL: packed union { - raw: u2, - value: USBPHYCSEL, - }, - /// OTGFS kernel clock source selection Set and reset by software. - USB_OTG_FSSEL: packed union { - raw: u2, - value: USB_OTG_FSSEL, - }, - /// Ethernet reference clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. - ETH_REF_CLK_SEL: packed union { - raw: u2, - value: ETH_REF_CLK_SEL, + value: HPRE, }, - /// Clock source selection for external Ethernet PHY Set and reset by software. - ETHPHY_CLK_SEL: packed union { - raw: u1, - value: ETHPHY_CLK_SEL, + /// MCO output enable + MCO1EN: u1, + /// MCO output enable + MCO2EN: u1, + /// APB Low speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, }, - reserved20: u1, - /// ADF kernel clock source selection Set and reset by software. Note: I2S_CKIN is an external clock taken from a pin. - ADFSEL: packed union { + /// APB high-speed prescaler (APB2) + PPRE2: packed union { raw: u3, - value: ADFSEL, + value: PPRE, }, - reserved24: u1, - /// SAR ADC kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. - ADCSEL: packed union { + /// HSE division factor for RTC clock + RTCPRE: u5, + /// Microcontroller clock output 1 + MCO1SEL: packed union { raw: u2, - value: ADCSEL, + value: MCO1SEL, }, - reserved27: u1, - /// PSSI kernel clock source selection Set and reset by software. - PSSISEL: packed union { + /// I2S clock selection + I2SSRC: packed union { raw: u1, - value: PSSISEL, - }, - /// per_ck clock source selection. - PERSEL: packed union { - raw: u2, - value: PERSEL, - }, - padding: u2, - }), - /// RCC APB1 peripherals kernel clock selection register. - APB1PERCKSELR: mmio.Mmio(packed struct(u32) { - /// USART2,3, UART4,5,7,8 (APB1) kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. - USART234578SEL: packed union { - raw: u3, - value: USART234578SEL, + value: I2SSRC_CFGR, }, - reserved4: u1, - /// SPI/I2S2 and SPI/I2S3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. - SPI23SEL: packed union { + /// MCO1 prescaler + MCO1PRE: packed union { raw: u3, - value: SPI123SEL, - }, - reserved8: u1, - /// I2C2, I2C3 kernel clock source selection Set and reset by software. - I2C23SEL: packed union { - raw: u2, - value: I2CSEL, - }, - reserved12: u2, - /// I2C1 or I3C1 kernel clock source selection Set and reset by software. - I2C1_I3C1SEL: packed union { - raw: u2, - value: I2C1_I3C1SEL, + value: MCOPRE, }, - reserved16: u2, - /// LPTIM1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. - LPTIM1SEL: packed union { + /// MCO2 prescaler + MCO2PRE: packed union { raw: u3, - value: LPTIM1SEL, - }, - reserved22: u3, - /// FDCAN kernel clock source selection. - FDCANSEL: packed union { - raw: u2, - value: FDCANSEL, - }, - /// SPDIFRX kernel clock source selection. - SPDIFRXSEL: packed union { - raw: u2, - value: SPDIFRXSEL, + value: MCOPRE, }, - reserved28: u2, - /// HDMI-CEC kernel clock source selection Set and reset by software. - CECSEL: packed union { + /// Microcontroller clock output 2 + MCO2SEL: packed union { raw: u2, - value: CECSEL, - }, - padding: u2, - }), - /// RCC APB2 peripherals kernel clock selection register. - APB2PERCKSELR: mmio.Mmio(packed struct(u32) { - /// USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. - USART1SEL: packed union { - raw: u3, - value: USART1SEL, - }, - reserved4: u1, - /// SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. - SPI45SEL: packed union { - raw: u3, - value: SPI45SEL, - }, - reserved8: u1, - /// SPI/I2S1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. - SPI1SEL: packed union { - raw: u3, - value: SPI123SEL, - }, - reserved16: u5, - /// SAI1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. - SAI1SEL: packed union { - raw: u3, - value: SAI1SEL, - }, - reserved20: u1, - /// SAI2 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see Figure 51). - SAI2SEL: packed union { - raw: u3, - value: SAI2SEL, - }, - padding: u9, - }), - /// RCC APB4,5 peripherals kernel clock selection register. - APB45PERCKSELR: mmio.Mmio(packed struct(u32) { - /// LPUART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. - LPUART1SEL: packed union { - raw: u3, - value: LPUARTSEL, - }, - reserved4: u1, - /// SPI/I2S6 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. - SPI6SEL: packed union { - raw: u3, - value: SPI6SEL, - }, - reserved8: u1, - /// LPTIM2 and LPTIM3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. - LPTIM23SEL: packed union { - raw: u3, - value: LPTIMSEL, - }, - reserved12: u1, - /// LPTIM4, and LPTIM5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. - LPTIM45SEL: packed union { - raw: u3, - value: LPTIMSEL, + value: MCO2SEL, }, - padding: u17, - }), - reserved96: [4]u8, - /// RCC clock source interrupt enable register. - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization. - LSIRDYIE: u1, - /// LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization. - LSERDYIE: u1, - /// HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization. - HSIRDYIE: u1, - /// HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization. - HSERDYIE: u1, - /// CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization. - CSIRDYIE: u1, - /// HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. - HSI48RDYIE: u1, - /// PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. - PLLRDYIE: u1, - reserved9: u2, - /// LSE clock security system interrupt enable Set and reset by software to enable/disable interrupt caused by the clock security system (CSS) on external 32 kHz oscillator. - LSECSSIE: u1, - padding: u22, }), - /// RCC clock source interrupt flag register. - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. + /// clock interrupt register + CIR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag LSIRDYF: u1, - /// LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set. + /// LSE ready interrupt flag LSERDYF: u1, - /// HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set. + /// HSI ready interrupt flag HSIRDYF: u1, - /// HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. + /// HSE ready interrupt flag HSERDYF: u1, - /// CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set. - CSIRDYF: u1, - /// HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. - HSI48RDYF: u1, - /// PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + /// Main PLL (PLL) ready interrupt flag PLLRDYF: u1, - reserved9: u2, - /// LSE clock security system interrupt flag Reset by software by writing LSECSSC bit. Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set. - LSECSSF: u1, - /// HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. - HSECSSF: u1, - padding: u21, - }), - /// RCC clock source interrupt clear register. - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done. + /// PLLI2S ready interrupt flag + PLLI2SRDYF: u1, + /// PLLSAI ready interrupt flag + PLLSAIRDYF: u1, + /// Clock security system interrupt flag + CSSF: u1, + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// Main PLL (PLL) ready interrupt enable + PLLRDYIE: u1, + /// PLLI2S ready interrupt enable + PLLI2SRDYIE: u1, + /// PLLSAI Ready Interrupt Enable + PLLSAIRDYIE: u1, + reserved16: u1, + /// LSI ready interrupt clear LSIRDYC: u1, - /// LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done. + /// LSE ready interrupt clear LSERDYC: u1, - /// HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done. + /// HSI ready interrupt clear HSIRDYC: u1, - /// HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done. + /// HSE ready interrupt clear HSERDYC: u1, - /// CSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done. - CSIRDYC: u1, - /// HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. - HSI48RDYC: u1, - /// PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + /// Main PLL(PLL) ready interrupt clear PLLRDYC: u1, - reserved9: u2, - /// LSE clock security system interrupt clear Set by software to clear LSECSSF. Reset by hardware when clear done. - LSECSSC: u1, - /// HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done. - HSECSSC: u1, - padding: u21, - }), - reserved112: [4]u8, - /// RCC Backup domain control register. - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enabled Set and reset by software. - LSEON: u1, - /// LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0. - LSERDY: u1, - /// LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1). - LSEBYP: u1, - /// LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit can only be disabled, After a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON. After a back-up domain reset. - LSECSSON: u1, - /// LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator. - LSECSSD: u1, - /// low-speed external clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled. - LSEEXT: u1, - /// RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST). - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved12: u2, - /// Re-Arm the LSECSS function Set by software. After a LSE failure detection, the software application can re-enable the LSECSS by writing this bit to 1. Reading this bit returns the written value. Prior to set this bit to 1, LSECSSON must be set to 0. Please refer to Section : CSS on LSE for details. - LSECSSRA: u1, - reserved15: u2, - /// RTC clock enable Set and reset by software. - RTCEN: u1, - /// VSwitch domain software reset Set and reset by software. To generate a VSW reset, it is recommended to write this bit to 1, then back to 0. - VSWRST: u1, - padding: u15, - }), - /// RCC clock control and status register. - CSR: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable Set and reset by software. - LSION: u1, - /// LSI oscillator ready Set and reset by hardware to indicate when the low-speed internal RC oscillator is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to 0. This bit can be set even when LSION is not enabled if there is a request for LSI clock by the clock security system on LSE or by the low-speed watchdog or by the RTC. - LSIRDY: u1, - padding: u30, - }), - reserved124: [4]u8, - /// RCC AHB5 peripheral reset register. - AHB5RSTR: mmio.Mmio(packed struct(u32) { - /// HPDMA1 block reset Set and reset by software. - HPDMA1RST: u1, - /// DMA2D block reset Set and reset by software. - DMA2DRST: u1, - reserved3: u1, - /// JPEG block reset Set and reset by software. - JPEGRST: u1, - /// FMC and MCE3 blocks reset Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. - FMCRST: u1, - /// XSPI1 and MCE1 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. - XSPI1RST: u1, - reserved8: u2, - /// SDMMC1 and DB_SDMMC1 blocks reset Set and reset by software. - SDMMC1RST: u1, - reserved12: u3, - /// XSPI2 and MCE2 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. - XSPI2RST: u1, - reserved14: u1, - /// XSPIM reset Set and reset by software. - IOMNGRRST: u1, - reserved19: u4, - /// GFXMMU block reset Set and reset by software. - GFXMMURST: u1, - /// GPU block reset Set and reset by software. - GPURST: u1, - padding: u11, + /// PLLI2S ready interrupt clear + PLLI2SRDYC: u1, + /// PLLSAI Ready Interrupt Clear + PLLSAIRDYC: u1, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, }), - /// RCC AHB1 peripheral reset register. + /// AHB1 peripheral reset register AHB1RSTR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// GPDMA1 blocks reset Set and reset by software. - GPDMA1RST: u1, - /// ADC1 and 2 blocks reset Set and reset by software. - ADC12RST: u1, - reserved15: u9, - /// ETH1 block reset Set and reset by software. - ETHRST: u1, - reserved25: u9, - /// OTGHS block reset Set and reset by software. - USB_OTG_HSRST: u1, - /// USBPHYC block reset Set and reset by software. - USBPHYCRST: u1, - /// OTGFS block reset Set and reset by software. - USB_OTG_FSRST: u1, - reserved31: u3, - /// ADF block reset Set and reset by software. - ADFRST: u1, - }), - /// RCC AHB2 peripheral reset register. - AHB2RSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// PSSI block reset Set and reset by software. - PSSIRST: u1, - reserved9: u7, - /// SDMMC2 and SDMMC2 delay blocks reset Set and reset by software. - SDMMC2RST: u1, - reserved14: u4, - /// CORDIC reset Set and reset by software. - CORDICRST: u1, - padding: u17, - }), - /// RCC AHB4 peripheral reset register. - AHB4RSTR: mmio.Mmio(packed struct(u32) { - /// GPIOA block reset Set and reset by software. + /// IO port A reset GPIOARST: u1, - /// GPIOB block reset Set and reset by software. + /// IO port B reset GPIOBRST: u1, - /// GPIOC block reset Set and reset by software. + /// IO port C reset GPIOCRST: u1, - /// GPIOD block reset Set and reset by software. + /// IO port D reset GPIODRST: u1, - /// GPIOE block reset Set and reset by software. + /// IO port E reset GPIOERST: u1, - /// GPIOF block reset Set and reset by software. + /// IO port F reset GPIOFRST: u1, - /// GPIOG block reset Set and reset by software. + /// IO port G reset GPIOGRST: u1, - /// GPIOH block reset Set and reset by software. + /// IO port H reset GPIOHRST: u1, - reserved12: u4, - /// GPIOM block reset Set and reset by software. - GPIOMRST: u1, - /// GPION block reset Set and reset by software. - GPIONRST: u1, - /// GPIOO block reset Set and reset by software. - GPIOORST: u1, - /// GPIOP block reset Set and reset by software. - GPIOPRST: u1, - reserved19: u3, - /// CRC block reset Set and reset by software. + /// IO port I reset + GPIOIRST: u1, + /// IO port J reset + GPIOJRST: u1, + /// IO port K reset + GPIOKRST: u1, + reserved12: u1, + /// CRC reset CRCRST: u1, - padding: u12, + reserved21: u8, + /// DMA2 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + /// DMA2D reset + DMA2DRST: u1, + reserved25: u1, + /// Ethernet MAC reset + ETHRST: u1, + reserved29: u3, + /// USB OTG HS module reset + USB_OTG_HSRST: u1, + padding: u2, }), - /// RCC APB5 peripheral reset register. - APB5RSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// LTDC block reset Set and reset by software. - LTDCRST: u1, - /// DCMIPP block reset Set and reset by software. - DCMIPPRST: u1, - reserved4: u1, - /// GFXTIM block reset Set and reset by software. - GFXTIMRST: u1, - padding: u27, + /// AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// Camera interface reset + DCMIRST: u1, + reserved4: u3, + /// CRYP module reset + CRYPRST: u1, + /// Hash module reset + HSAHRST: u1, + /// Random number generator module reset + RNGRST: u1, + /// USB OTG FS module reset + USB_OTG_FSRST: u1, + padding: u24, }), - /// RCC APB1 peripheral reset register 1. - APB1RSTR1: mmio.Mmio(packed struct(u32) { - /// TIM2 block reset Set and reset by software. + /// AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// Flexible static memory controller module reset + FMCRST: u1, + /// QUADSPI module reset + QUADSPIRST: u1, + padding: u30, + }), + reserved32: [4]u8, + /// APB1 peripheral reset register + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// TIM2 reset TIM2RST: u1, - /// TIM3 block reset Set and reset by software. + /// TIM3 reset TIM3RST: u1, - /// TIM4 block reset Set and reset by software. + /// TIM4 reset TIM4RST: u1, - /// TIM5 block reset Set and reset by software. + /// TIM5 reset TIM5RST: u1, - /// TIM6 block reset Set and reset by software. + /// TIM6 reset TIM6RST: u1, - /// TIM7 block reset Set and reset by software. + /// TIM7 reset TIM7RST: u1, - /// TIM12 block reset Set and reset by software. + /// TIM12 reset TIM12RST: u1, - /// TIM13 block reset Set and reset by software. + /// TIM13 reset TIM13RST: u1, - /// TIM14 block reset Set and reset by software. + /// TIM14 reset TIM14RST: u1, - /// LPTIM1 block reset Set and reset by software. + /// LPTIM1 reset LPTIM1RST: u1, - reserved14: u4, - /// SPI2S2 block reset Set and reset by software. + reserved11: u1, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI 2 reset SPI2RST: u1, - /// SPI2S3 block reset Set and reset by software. + /// SPI 3 reset SPI3RST: u1, - /// SPDIFRX block reset Set and reset by software. - SPDIFRXRST: u1, - /// USART2 block reset Set and reset by software. + /// SPDIF-IN reset + SPDIFRST: u1, + /// USART 2 reset USART2RST: u1, - /// USART3 block reset Set and reset by software. + /// USART 3 reset USART3RST: u1, - /// UART4 block reset Set and reset by software. + /// UART 4 reset UART4RST: u1, - /// UART5 block reset Set and reset by software. + /// UART 5 reset UART5RST: u1, - /// I2C1/I3C1 block reset Set and reset by software. - I2C1_I3C1RST: u1, - /// I2C2 block reset Set and reset by software. + /// I2C 1 reset + I2C1RST: u1, + /// I2C 2 reset I2C2RST: u1, - /// I2C3 block reset Set and reset by software. + /// I2C3 reset I2C3RST: u1, - reserved27: u3, - /// HDMI-CEC block reset Set and reset by software. - CECRST: u1, - reserved30: u2, - /// UART7 block reset Set and reset by software. + /// FMPI2C1 reset + FMPI2C1RST: u1, + /// CAN1 reset + CAN1RST: u1, + /// CAN2 reset + CAN2RST: u1, + /// CAN 3 reset + CAN3RST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC reset + DACRST: u1, + /// UART 7 reset UART7RST: u1, - /// UART8 block reset Set and reset by software. + /// UART 8 reset UART8RST: u1, }), - /// RCC APB1 peripheral reset register 2. - APB1RSTR2: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// clock recovery system reset Set and reset by software. - CRSRST: u1, - reserved5: u3, - /// MDIOS block reset Set and reset by software. - MDIOSRST: u1, - reserved8: u2, - /// FDCAN block reset Set and reset by software. - FDCANRST: u1, - reserved27: u18, - /// UCPD block reset Set and reset by software. - UCPDRST: u1, - padding: u4, - }), - /// RCC APB2 peripheral reset register. + /// APB2 peripheral reset register APB2RSTR: mmio.Mmio(packed struct(u32) { - /// TIM1 block reset Set and reset by software. + /// TIM1 reset TIM1RST: u1, - reserved4: u3, - /// USART1 block reset Set and reset by software. + /// TIM8 reset + TIM8RST: u1, + reserved4: u2, + /// USART1 reset USART1RST: u1, - reserved12: u7, - /// SPI2S1 block reset Set and reset by software. + /// USART6 reset + USART6RST: u1, + /// UART9 reset + UART9RST: u1, + /// UART10 reset + UART10RST: u1, + /// ADC interface reset (common to all ADCs) + ADCRST: u1, + reserved11: u2, + /// SDIO reset + SDIORST: u1, + /// SPI 1 reset SPI1RST: u1, - /// SPI4 block reset Set and reset by software. + /// SPI4 reset SPI4RST: u1, - reserved16: u2, - /// TIM15 block reset Set and reset by software. - TIM15RST: u1, - /// TIM16 block reset Set and reset by software. - TIM16RST: u1, - /// TIM17 block reset Set and reset by software. - TIM17RST: u1, - /// TIM9 block reset Set and reset by software. + /// System configuration controller reset + SYSCFGRST: u1, + reserved16: u1, + /// TIM9 reset TIM9RST: u1, - /// SPI5 block reset Set and reset by software. + /// TIM10 reset + TIM10RST: u1, + /// TIM11 reset + TIM11RST: u1, + reserved20: u1, + /// SPI5 reset SPI5RST: u1, - reserved22: u1, - /// SAI1 block reset Set and reset by software. + /// SPI6 reset + SPI6RST: u1, + /// SAI1 reset SAI1RST: u1, - /// SAI2 block reset Set and reset by software. + /// SAI2 reset SAI2RST: u1, - padding: u8, - }), - /// RCC APB4 peripheral reset register. - APB4RSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SBS block reset Set and reset by software. - SYSCFGRST: u1, - reserved3: u1, - /// LPUART1 block reset Set and reset by software. - LPUART1RST: u1, - reserved5: u1, - /// SPI/I2S6 block reset Set and reset by software. - SPI6RST: u1, - reserved9: u3, - /// LPTIM2 block reset Set and reset by software. - LPTIM2RST: u1, - /// LPTIM3 block reset Set and reset by software. - LPTIM3RST: u1, - /// LPTIM4 block reset Set and reset by software. - LPTIM4RST: u1, - /// LPTIM5 block reset Set and reset by software. - LPTIM5RST: u1, - reserved15: u2, - /// VREF block reset Set and reset by software. - VREFRST: u1, - reserved26: u10, - /// TMPSENS block reset Set and reset by software. - TMPSENSRST: u1, - padding: u5, - }), - reserved164: [4]u8, - /// RCC AHB3 peripheral reset register. - AHB3RSTR: mmio.Mmio(packed struct(u32) { - /// random number generator block reset Set and reset by software. - RNGRST: u1, - /// HASH block reset Set and reset by software. - HASHRST: u1, - /// CRYP block reset Set and reset by software. - CRYPRST: u1, - reserved4: u1, - /// SAES block reset Set and reset by software. - SAESRST: u1, - reserved6: u1, - /// PKA block reset Set and reset by software. - PKARST: u1, - padding: u25, + /// DFSDMRST + DFSDMRST: u1, + /// DFSDM2 reset + DFSDM2RST: u1, + /// LTDC reset + LTDCRST: u1, + /// DSI host reset + DSIRST: u1, + padding: u4, }), - reserved176: [8]u8, - /// RCC AXI clocks gating disable register. - CKGDISR: mmio.Mmio(packed struct(u32) { - /// AXI interconnect matrix clock gating disable This bit is set and reset by software. - AXICKG: u1, - /// AXI master AHB clock gating disable This bit is set and reset by software. - AHBMCKG: u1, - /// AXI master SDMMC1 clock gating disable This bit is set and reset by software. - SDMMC1CKG: u1, - /// AXI master HPDMA1 clock gating disable This bit is set and reset by software. - HPDMA1CKG: u1, - /// AXI master CPU clock gating disable This bit is set and reset by software. - CPUCKG: u1, - /// AXI master 0 GPU clock gating disable This bit is set and reset by software. - GPUS0CKG: u1, - /// AXI master 1 GPU clock gating disable This bit is set and reset by software. - GPUS1CKG: u1, - /// AXI master cache GPU clock gating disable This bit is set and reset by software. - GPUCLCKG: u1, - /// AXI master DCMIPP clock gating disable This bit is set and reset by software. - DCMIPPCKG: u1, - /// AXI master DMA2D clock gating disable This bit is set and reset by software. - DMA2DCKG: u1, - /// AXI matrix slave GFXMMU clock gating disable This bit is set and reset by software. - GFXMMUSCKG: u1, - /// AXI master LTDC clock gating disable This bit is set and reset by software. - LTDCCKG: u1, - /// AXI master GFXMMU clock gating disable This bit is set and reset by software. - GFXMMUMCKG: u1, - /// AXI slave AHB clock gating disable This bit is set and reset by software. - AHBSCKG: u1, - /// AXI slave FMC and MCE3 clock gating disable This bit is set and reset by software. - FMCCKG: u1, - /// AXI slave XSPI1 and MCE1 clock gating disable This bit is set and reset by software. - XSPI1CKG: u1, - /// AXI slave XSPI2 and MCE2 clock gating disable This bit is set and reset by software. - XSPI2CKG: u1, - /// AXI matrix slave SRAM4 clock gating disable This bit is set and reset by software. - AXIRAM4CKG: u1, - /// AXI matrix slave SRAM3 clock gating disable This bit is set and reset by software. - AXIRAM3CKG: u1, - /// AXI slave SRAM2 clock gating disable This bit is set and reset by software. - AXIRAM2CKG: u1, - /// AXI slave SRAM1 / error code correction (ECC) clock gating disable This bit is set and reset by software. - AXIRAM1CKG: u1, - /// AXI slave Flash interface (FLIFT) clock gating disable This bit is set and reset by software. - FLITFCKG: u1, - reserved30: u8, - /// EXTI clock gating disable This bit is set and reset by software. - EXTICKG: u1, - /// JTAG automatic clock gating disabling This bit is set and reset by software. - JTAGCKG: u1, + reserved48: [8]u8, + /// AHB1 peripheral clock register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// IO port H clock enable + GPIOHEN: u1, + /// IO port I clock enable + GPIOIEN: u1, + /// IO port J clock enable + GPIOJEN: u1, + /// IO port K clock enable + GPIOKEN: u1, + reserved12: u1, + /// CRC clock enable + CRCEN: u1, + reserved18: u5, + /// Backup SRAM interface clock enable + BKPSRAMEN: u1, + reserved20: u1, + /// CCM data RAM clock enable + CCMDATARAMEN: u1, + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// DMA2D clock enable + DMA2DEN: u1, + reserved25: u1, + /// Ethernet MAC clock enable + ETHEN: u1, + /// Ethernet Transmission clock enable + ETHTXEN: u1, + /// Ethernet Reception clock enable + ETHRXEN: u1, + /// Ethernet PTP clock enable + ETHPTPEN: u1, + /// USB OTG HS clock enable + USB_OTG_HSEN: u1, + /// USB OTG HSULPI clock enable + USB_OTG_HSULPIEN: u1, + padding: u1, }), - reserved192: [12]u8, - /// RCC PLL dividers configuration register 2. - PLLDIVR2: [3]mmio.Mmio(packed struct(u32) { - /// PLL1 DIVS division factor Set and reset by software to control the frequency of the pll1_s_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVS+1) is even, With VCOH, for all DIVS values These bits can be written only when the PLL1DIVSEN = 0. - PLLS: packed union { - raw: u3, - value: PLLDIVST, - }, - reserved8: u5, - /// PLL1 DIVT division factor Set and reset by software to control the frequency of the pll1_t_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVT+1) is even, With VCOH, for all DIVT values These bits can be written only when the PLL1DIVTEN = 0. - PLLT: packed union { - raw: u3, - value: PLLDIVST, - }, - padding: u21, + /// AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// Camera interface enable + DCMIEN: u1, + reserved4: u3, + /// CRYP clock enable + CRYPEN: u1, + /// Hash modules clock enable + HASHEN: u1, + /// Random number generator clock enable + RNGEN: u1, + /// USB OTG FS clock enable + USB_OTG_FSEN: u1, + padding: u24, }), - /// RCC PLL Spread Spectrum Clock Generator register. - PLLSSCGR: [3]mmio.Mmio(packed struct(u32) { - /// Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator. - MOD_PER: u13, - /// Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function. - TPDFN_DIS1: u1, - /// Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function. - RPDFN_DIS1: u1, - /// Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode. - DWNSPREAD1: packed union { - raw: u1, - value: DWNSPREAD, - }, - /// Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator. - INC_STEP: u15, - padding: u1, + /// AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// Flexible static memory controller module clock enable + FMCEN: u1, + /// QUADSPI memory controller module clock enable + QUADSPIEN: u1, + padding: u30, }), - reserved256: [40]u8, - /// RCC clock protection register. - CKPROTR: mmio.Mmio(packed struct(u32) { - /// XSPI clock protection Set and cleared by software. When set to 1, this bit prevents disabling accidentally the XSPIs. The following fields cannot be modified when this bit is set to 1: PLL2ON, PLL2DIVSEN, PLL2DIVTEN, HSEON, HSION, CSION, XSPIxEN, OCTOSPIxLPEN, OCTOSPIxRST. - XSPICKP: u1, - /// FMC clock protection Set and cleared by software. When set to 1, this bit prevents disabling accidentally the FMC. The following fields cannot be modified when this bit is set to 1: PLL1ON, PLL2ON, PLL1DIVQEN, PLL2DIVREN, HSEON, HSION, CSION, FMCEN, FMCLPEN, FMCRST. - FMCCKP: u1, - reserved4: u2, - /// XSPI1 kernel clock switch position Set by hardware. This field can be used to verify the real position of XSPI2 kernel switch selector. - XSPI1SWP: packed union { - raw: u3, - value: XSPISWP, - }, - reserved8: u1, - /// XSPI2 kernel clock switch position Set by hardware. This field can be used to verify the real position of XSPI2 kernel switch selector. - XSPI2SWP: packed union { - raw: u3, - value: XSPISWP, - }, - reserved12: u1, - /// FMC kernel clock switch position Set by hardware. This field can be used to verify the real position of FMC kernel switch selector. - FMCSWP: packed union { - raw: u3, - value: FMCSWP, - }, - padding: u17, - }), - reserved304: [44]u8, - /// RCC Reset status register. - RSR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// remove reset flag Set and reset by software to reset the value of the reset flags. - RMVF: u1, - /// Option byte loading reset flag (1) Reset by software by the RMVF bit. Set by hardware when a reset from the option byte loading occurs. - OBLRSTF: u1, - reserved21: u3, - /// BOR reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). - BORRSTF: u1, - /// pin reset flag (NRST) (1) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. - PINRSTF: u1, - /// POR/PDR reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs. - PORRSTF: u1, - /// system reset from CPU reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7. - SFTRSTF: u1, - reserved26: u1, - /// independent watchdog reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. - IWDGRSTF: u1, - reserved28: u1, - /// window watchdog reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. - WWDGRSTF: u1, - reserved30: u1, - /// reset due to illegal Stop or Standby flag Reset by software by writing the RMVF bit. Set by hardware when the CPU goes erroneously in Stop or Standby mode,. - LPWRRSTF: u1, - padding: u1, - }), - /// RCC AHB5 clock enable register. - AHB5ENR: mmio.Mmio(packed struct(u32) { - /// HPDMA1 peripheral clock enable Set and reset by software. - HPDMA1EN: u1, - /// DMA2D peripheral clock enable Set and reset by software. - DMA2DEN: u1, - reserved3: u1, - /// JPEG peripheral clock enable Set and reset by software. - JPEGEN: u1, - /// FMC and MCE3 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock. - FMCEN: u1, - /// XSPI1 and MCE1 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. - XSPI1EN: u1, - reserved8: u2, - /// SDMMC1 and DB_SDMMC1 peripheral clocks enable Set and reset by software. - SDMMC1EN: u1, - reserved12: u3, - /// XSPI2 and MCE2 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. - XSPI2EN: u1, - reserved14: u1, - /// XSPIM peripheral clock enable Set and reset by software. - IOMNGREN: u1, - reserved19: u4, - /// GFXMMU peripheral clock enable Set and reset by software. - GFXMMUEN: u1, - /// GPU peripheral clock enable Set and reset by software. - GPUEN: u1, - padding: u11, - }), - /// RCC AHB1 clock enable register. - AHB1ENR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// GPDMA1 clock enable Set and reset by software. - GPDMA1EN: u1, - /// ADC1 and 2 peripheral clocks enable Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the hclk1 bus interface clock. - ADC12EN: u1, - reserved15: u9, - /// ETH1 MAC peripheral clock enable Set and reset by software. - ETHEN: u1, - /// ETH1 transmission clock enable Set and reset by software. - ETHTXEN: u1, - /// ETH1 reception clock enable Set and reset by software. - ETHRXEN: u1, - reserved25: u7, - /// OTGHS clocks enable Set and reset by software. - USB_OTG_HSEN: u1, - /// USBPHYC clocks enable Set and reset by software. - USBPHYCEN: u1, - /// OTGFS peripheral clocks enable Set and reset by software. - USB_OTG_FSEN: u1, - reserved31: u3, - /// ADF clocks enable Set and reset by software. - ADFEN: u1, - }), - /// RCC AHB2 clock enable register. - AHB2ENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// PSSI peripheral clocks enable Set and reset by software. - PSSIEN: u1, - reserved9: u7, - /// SDMMC2 and SDMMC2 delay clock enable Set and reset by software. - SDMMC2EN: u1, - reserved14: u4, - /// CORDIC clock enable Set and reset by software. - CORDICEN: u1, - reserved29: u14, - /// SRAM1 clock enable Set and reset by software. - SRAM1EN: u1, - /// SRAM2 clock enable Set and reset by software. - SRAM2EN: u1, - padding: u1, - }), - /// RCC AHB4 clock enable register. - AHB4ENR: mmio.Mmio(packed struct(u32) { - /// GPIOA peripheral clock enable Set and reset by software. - GPIOAEN: u1, - /// GPIOB peripheral clock enable Set and reset by software. - GPIOBEN: u1, - /// GPIOC peripheral clock enable Set and reset by software. - GPIOCEN: u1, - /// GPIOD peripheral clock enable Set and reset by software. - GPIODEN: u1, - /// GPIOE peripheral clock enable Set and reset by software. - GPIOEEN: u1, - /// GPIOF peripheral clock enable Set and reset by software. - GPIOFEN: u1, - /// GPIOG peripheral clock enable Set and reset by software. - GPIOGEN: u1, - /// GPIOH peripheral clock enable Set and reset by software. - GPIOHEN: u1, - reserved12: u4, - /// GPIOM peripheral clock enable Set and reset by software. - GPIOMEN: u1, - /// GPION peripheral clock enable Set and reset by software. - GPIONEN: u1, - /// GPIOO peripheral clock enable Set and reset by software. - GPIOOEN: u1, - /// GPIOP peripheral clock enable Set and reset by software. - GPIOPEN: u1, - reserved19: u3, - /// CRC clock enable Set and reset by software. - CRCEN: u1, - reserved28: u8, - /// Backup RAM clock enable Set and reset by software. - BKPRAMEN: u1, - padding: u3, - }), - /// RCC APB5 clock enable register. - APB5ENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// LTDC peripheral clock enable Provides the pixel clock (ltdc_clk) to the LTDC block. Set and reset by software. - LTDCEN: u1, - /// DCMIPP peripheral clock enable Set and reset by software. - DCMIPPEN: u1, - reserved4: u1, - /// GFXTIM peripheral clock enable Set and reset by software. - GFXTIMEN: u1, - padding: u27, - }), - /// RCC APB1 clock enable register 1. - APB1ENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 peripheral clock enable Set and reset by software. + reserved64: [4]u8, + /// APB1 peripheral clock enable register + APB1ENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable TIM2EN: u1, - /// TIM3 peripheral clock enable Set and reset by software. + /// TIM3 clock enable TIM3EN: u1, - /// TIM4 peripheral clock enable Set and reset by software. + /// TIM4 clock enable TIM4EN: u1, - /// TIM5 peripheral clock enable Set and reset by software. + /// TIM5 clock enable TIM5EN: u1, - /// TIM6 peripheral clock enable Set and reset by software. + /// TIM6 clock enable TIM6EN: u1, - /// TIM7 peripheral clock enable Set and reset by software. + /// TIM7 clock enable TIM7EN: u1, - /// TIM12 peripheral clock enable Set and reset by software. + /// TIM12 clock enable TIM12EN: u1, - /// TIM13 peripheral clock enable Set and reset by software. + /// TIM13 clock enable TIM13EN: u1, - /// TIM14 peripheral clock enable Set and reset by software. + /// TIM14 clock enable TIM14EN: u1, - /// LPTIM1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to clk_lpt input, and the rcc_pclk1 bus interface clock. + /// LPTIM1 clock enable LPTIM1EN: u1, - reserved11: u1, - /// WWDG clock enable Set by software, and reset by hardware when a system reset occurs. + /// RTC APB clock enable + RTCAPBEN: u1, + /// Window watchdog clock enable WWDGEN: u1, reserved14: u2, - /// SPI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock. + /// SPI2 clock enable SPI2EN: u1, - /// SPI3 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock. + /// SPI3 clock enable SPI3EN: u1, - /// SPDIFRX peripheral clocks enable Set and reset by software. The peripheral clocks of the SPDIFRX are the kernel clock selected by SPDIFRXSEL and provided to SPDIFRX_CLK input, and the rcc_pclk1 bus interface clock. - SPDIFRXEN: u1, - /// USART2peripheral clocks enable Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. + /// SPDIF-IN clock enable + SPDIFEN: u1, + /// USART 2 clock enable USART2EN: u1, - /// USART3 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. + /// USART3 clock enable USART3EN: u1, - /// UART4 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. + /// UART4 clock enable UART4EN: u1, - /// UART5 peripheral clocks enable Set and reset by software. + /// UART5 clock enable UART5EN: u1, - /// I2C1/I3C1 peripheral clocks enable Set and reset by software. - I2C1_I3C1EN: u1, - /// I2C2 peripheral clocks enable Set and reset by software. + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable I2C2EN: u1, - /// I2C3 peripheral clocks enable Set and reset by software. + /// I2C3 clock enable I2C3EN: u1, - reserved27: u3, - /// HDMI-CEC peripheral clock enable Set and reset by software. - CECEN: u1, - reserved30: u2, - /// UART7 peripheral clocks enable Set and reset by software. + /// FMPI2C1 clock enable + FMPI2C1EN: u1, + /// CAN 1 clock enable + CAN1EN: u1, + /// CAN 2 clock enable + CAN2EN: u1, + /// CAN 3 clock enable + CAN3EN: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// UART7 clock enable UART7EN: u1, - /// UART8 peripheral clocks enable Set and reset by software. + /// UART8 clock enable UART8EN: u1, }), - /// RCC APB1 clock enable register 2. - APB1ENR2: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// clock recovery system peripheral clock enable Set and reset by software. - CRSEN: u1, - reserved5: u3, - /// MDIOS peripheral clock enable Set and reset by software. - MDIOSEN: u1, - reserved8: u2, - /// FDCAN peripheral clock enable Set and reset by software. - FDCANEN: u1, - reserved27: u18, - /// UCPD peripheral clock enable Set and reset by software. - UCPDEN: u1, - padding: u4, - }), - /// RCC APB2 clock enable register. + /// APB2 peripheral clock enable register APB2ENR: mmio.Mmio(packed struct(u32) { - /// TIM1 peripheral clock enable Set and reset by software. + /// TIM1 clock enable TIM1EN: u1, - reserved4: u3, - /// USART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART1SEL, and the pclk2 bus interface clock. + /// TIM8 clock enable + TIM8EN: u1, + reserved4: u2, + /// USART1 clock enable USART1EN: u1, - reserved12: u7, - /// SPI2S1 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI2S1 are: the kernel clock selected by SPI1SEL, and the pclk2 bus interface clock. + /// USART6 clock enable + USART6EN: u1, + /// UART9 clock enable + UART9EN: u1, + /// UART10 clock enable + UART10EN: u1, + /// ADC1 clock enable + ADC1EN: u1, + /// ADC2 clock enable + ADC2EN: u1, + /// ADC3 clock enable + ADC3EN: u1, + /// SDIO clock enable + SDIOEN: u1, + /// SPI1 clock enable SPI1EN: u1, - /// SPI4 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL, and the pclk2 bus interface clock. + /// SPI4 clock enable SPI4EN: u1, - reserved16: u2, - /// TIM15 peripheral clock enable Set and reset by software. - TIM15EN: u1, - /// TIM16 peripheral clock enable Set and reset by software. - TIM16EN: u1, - /// TIM17 peripheral clock enable Set and reset by software. - TIM17EN: u1, - /// TIM9 peripheral clock enable Set and reset by software. + /// System configuration controller clock enable + SYSCFGEN: u1, + /// EXTI ans external IT clock enable + EXTITEN: u1, + /// TIM9 clock enable TIM9EN: u1, - /// SPI5 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL, and the pclk2 bus interface clock. + /// TIM10 clock enable + TIM10EN: u1, + /// TIM11 clock enable + TIM11EN: u1, + reserved20: u1, + /// SPI5 clock enable SPI5EN: u1, - reserved22: u1, - /// SAI1 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI1 are the kernel clock selected by SAI1SEL, and the pclk2 bus interface clock. + /// SPI6 clock enable + SPI6EN: u1, + /// SAI 1 clock enable SAI1EN: u1, - /// SAI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI2 are the kernel clock selected by SAI2SEL, and the pclk2 bus interface clock. + /// SAI2 clock enable SAI2EN: u1, - padding: u8, - }), - /// RCC APB4 clock enable register. - APB4ENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SBS peripheral clock enable Set and reset by software. - SYSCFGEN: u1, - reserved3: u1, - /// LPUART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the pclk4 bus interface clock. - LPUART1EN: u1, - reserved5: u1, - /// SPI/I2S6 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_clk input, and the pclk4 bus interface clock. - SPI6EN: u1, - reserved9: u3, - /// LPTIM2 peripheral clocks enable Set and reset by software. The LPTIM2 kernel clock can be selected by LPTIM23SEL. - LPTIM2EN: u1, - /// LPTIM3 peripheral clocks enable Set and reset by software. The LPTIM3 kernel clock can be selected by LPTIM23SEL. - LPTIM3EN: u1, - /// LPTIM4 peripheral clocks enable Set and reset by software. The LPTIM4 kernel clock can be selected by LPTIM45SEL. - LPTIM4EN: u1, - /// LPTIM5 peripheral clocks enable Set and reset by software. The LPTIM5 kernel clock can be selected by LPTIM45SEL. - LPTIM5EN: u1, - reserved15: u2, - /// VREF peripheral clock enable Set and reset by software. - VREFEN: u1, - /// RTC APB clock enable Set and reset by software. - RTCAPBEN: u1, - reserved26: u9, - /// Temperature Sensor peripheral clock enable Set and reset by software. - TMPSENSEN: u1, - padding: u5, - }), - /// RCC AHB3 clock enable register. - AHB3ENR: mmio.Mmio(packed struct(u32) { - /// RNG peripheral clocks enable Set and reset by software. - RNGEN: u1, - /// HASH peripheral clock enable Set and reset by software. - HASHEN: u1, - /// CRYP peripheral clock enable Set and reset by software. - CRYPEN: u1, - reserved4: u1, - /// SAES peripheral clock enable Set and reset by software. This bit controls the enable of the clock delivered to the SAES. - SAESEN: u1, - reserved6: u1, - /// PKA peripheral clock enable Set and reset by software. - PKAEN: u1, - padding: u25, - }), - /// RCC AHB5 low-power clock enable register. - AHB5LPENR: mmio.Mmio(packed struct(u32) { - /// HPDMA1 low-power peripheral clock enable Set and reset by software. - HPDMA1LPEN: u1, - /// DMA2D low-power peripheral clock enable Set and reset by software. - DMA2DLPEN: u1, - /// FLITF low-power peripheral clock enable Set and reset by software. - FLITFLPEN: u1, - /// JPEG clock enable during Sleep mode Set and reset by software. - JPEGLPEN: u1, - /// FMC and MCE3 peripheral clocks enable during Sleep mode Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock. - FMCLPEN: u1, - /// XSPI1 and MCE1 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. - XSPI1LPEN: u1, - reserved8: u2, - /// SDMMC1 and SDMMC1 delay low-power peripheral clock enable Set and reset by software. - SDMMC1LPEN: u1, - reserved12: u3, - /// XSPI2 and MCE2 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. - XSPI2LPEN: u1, - reserved14: u1, - /// XSPIM low-power peripheral clock enable Set and reset by software. - XSPIMLPEN: u1, - reserved19: u4, - /// GFXMMU low-power peripheral clock enable Set and reset by software. - GFXMMULPEN: u1, - /// GPU low-power peripheral clock enable Set and reset by software. - GPULPEN: u1, - reserved28: u7, - /// DTCM1 low-power peripheral clock enable Set and reset by software. - DTCM1LPEN: u1, - /// DTCM2 low-power peripheral clock enable Set and reset by software. - DTCM2LPEN: u1, - /// ITCM low-power peripheral clock enable Set and reset by software. - ITCMLPEN: u1, - /// AXISRAM[4:1] low-power peripheral clock enable Set and reset by software. - AXISRAMLPEN: u1, + /// DFSDMEN + DFSDMEN: u1, + /// DFSDM2 clock enable + DFSDM2EN: u1, + /// LTDC clock enable + LTDCEN: u1, + /// DSI clocks enable + DSIEN: u1, + padding: u4, }), - /// RCC AHB1 low-power clock enable register. + reserved80: [8]u8, + /// AHB1 peripheral clock enable in low power mode register AHB1LPENR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// GPDMA1 clock enable in low-power mode Set and reset by software. - GPDMA1LPEN: u1, - /// ADC1 and 2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the rcc_hclk1 bus interface clock. - ADC12LPEN: u1, - reserved15: u9, - /// ETH1 MAC peripheral clock enable in low-power mode Set and reset by software. - ETHLPEN: u1, - /// ETH1 transmission peripheral clock enable in low-power mode Set and reset by software. - ETHTXLPEN: u1, - /// ETH1 reception peripheral clock enable in low-power mode Set and reset by software. - ETHRXLPEN: u1, - reserved24: u6, - /// USBPHYC common block power-down control Set and reset by software. - USBPDCTRL: packed union { - raw: u1, - value: USBPDCTRL, - }, - /// OTGHS peripheral clock enable in low-power mode Set and reset by software. - USB_OTG_HSLPEN: u1, - /// USBPHYC peripheral clock enable in low-power mode Set and reset by software. - USBPHYCLPEN: u1, - /// OTGFS clock enable in low-power mode Set and reset by software. - USB_OTG_FSLPEN: u1, - reserved31: u3, - /// ADF clock enable in low-power mode Set and reset by software. - ADFLPEN: u1, - }), - /// RCC AHB2 low-power clock enable register. - AHB2LPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// PSSI peripheral clock enable in low-power mode Set and reset by software. - PSSILPEN: u1, - reserved9: u7, - /// SDMMC2 and SDMMC2 delay clock enable in low-power mode Set and reset by software. - SDMMC2LPEN: u1, - reserved14: u4, - /// CORDIC clock enable in low-power mode Set and reset by software. - CORDICLPEN: u1, - reserved29: u14, - /// SRAM1 clock enable in low-power mode Set and reset by software. - SRAM1LPEN: u1, - /// SRAM2 clock enable in low-power mode Set and reset by software. - SRAM2LPEN: u1, - padding: u1, - }), - /// RCC AHB4 low-power clock enable register. - AHB4LPENR: mmio.Mmio(packed struct(u32) { - /// GPIOA peripheral clock enable in low-power mode Set and reset by software. + /// IO port A clock enable during sleep mode GPIOALPEN: u1, - /// GPIOB peripheral clock enable in low-power mode Set and reset by software. + /// IO port B clock enable during Sleep mode GPIOBLPEN: u1, - /// GPIOC peripheral clock enable in low-power mode Set and reset by software. + /// IO port C clock enable during Sleep mode GPIOCLPEN: u1, - /// GPIOD peripheral clock enable in low-power mode Set and reset by software. + /// IO port D clock enable during Sleep mode GPIODLPEN: u1, - /// GPIOE peripheral clock enable in low-power mode Set and reset by software. + /// IO port E clock enable during Sleep mode GPIOELPEN: u1, - /// GPIOF peripheral clock enable in low-power mode Set and reset by software. + /// IO port F clock enable during Sleep mode GPIOFLPEN: u1, - /// GPIOG peripheral clock enable in low-power mode Set and reset by software. + /// IO port G clock enable during Sleep mode GPIOGLPEN: u1, - /// GPIOH peripheral clock enable in low-power mode Set and reset by software. + /// IO port H clock enable during Sleep mode GPIOHLPEN: u1, - reserved12: u4, - /// GPIOM peripheral clock enable in low-power mode Set and reset by software. - GPIOMLPEN: u1, - /// GPION peripheral clock enable in low-power mode Set and reset by software. - GPIONLPEN: u1, - /// GPIOO peripheral clock enable in low-power mode Set and reset by software. - GPIOOLPEN: u1, - /// GPIOP peripheral clock enable in low-power mode Set and reset by software. - GPIOPLPEN: u1, - reserved19: u3, - /// CRC clock enable in low-power mode Set and reset by software. + /// IO port I clock enable during Sleep mode + GPIOILPEN: u1, + /// IO port J clock enable during Sleep mode + GPIOJLPEN: u1, + /// IO port K clock enable during Sleep mode + GPIOKLPEN: u1, + reserved12: u1, + /// CRC clock enable during Sleep mode CRCLPEN: u1, - reserved28: u8, - /// Backup RAM clock enable in low-power mode Set and reset by software. - BKPRAMLPEN: u1, - padding: u3, - }), - /// RCC AHB3 low-power clock enable register. - AHB3LPENR: mmio.Mmio(packed struct(u32) { - /// RNG peripheral clock enable in low-power mode Set and reset by software. + reserved15: u2, + /// Flash interface clock enable during Sleep mode + FLASHLPEN: u1, + /// SRAM 1interface clock enable during Sleep mode + SRAM1LPEN: u1, + /// SRAM 2 interface clock enable during Sleep mode + SRAM2LPEN: u1, + /// Backup SRAM interface clock enable during Sleep mode + BKPSRAMLPEN: u1, + /// SRAM 3 interface clock enable during Sleep mode + SRAM3LPEN: u1, + reserved21: u1, + /// DMA1 clock enable during Sleep mode + DMA1LPEN: u1, + /// DMA2 clock enable during Sleep mode + DMA2LPEN: u1, + /// DMA2D clock enable during Sleep mode + DMA2DLPEN: u1, + reserved25: u1, + /// Ethernet MAC clock enable during Sleep mode + ETHLPEN: u1, + /// Ethernet transmission clock enable during Sleep mode + ETHTXLPEN: u1, + /// Ethernet reception clock enable during Sleep mode + ETHRXLPEN: u1, + /// Ethernet PTP clock enable during Sleep mode + ETHPTPLPEN: u1, + /// USB OTG HS clock enable during Sleep mode + USB_OTG_HSLPEN: u1, + /// USB OTG HS ULPI clock enable during Sleep mode + USB_OTG_HSULPILPEN: u1, + /// RNG clock enable during sleep mode RNGLPEN: u1, - /// HASH peripheral clock enable in low-power mode Set and reset by software. - HASHLPEN: u1, - /// CRYP peripheral clock enable in low-power mode Set and reset by software. + }), + /// AHB2 peripheral clock enable in low power mode register + AHB2LPENR: mmio.Mmio(packed struct(u32) { + /// Camera interface enable during Sleep mode + DCMILPEN: u1, + /// QUADSPI memory controller module clock enable during Sleep mode + QUADSPILPEN: u1, + reserved4: u2, + /// Cryptography modules clock enable during Sleep mode CRYPLPEN: u1, - reserved4: u1, - /// SAES peripheral clock enable in low-power mode Set and reset by software. - SAESLPEN: u1, - reserved6: u1, - /// PKA peripheral clock enable in low-power mode Set and reset by software. - PKALPEN: u1, - padding: u25, + /// Hash modules clock enable during Sleep mode + HASHLPEN: u1, + /// Random number generator clock enable during Sleep mode + RNGLPEN: u1, + /// USB OTG FS clock enable during Sleep mode + USB_OTG_FSLPEN: u1, + padding: u24, }), - /// RCC APB1 low-power clock enable register 1. - APB1LPENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 peripheral clock enable in low-power mode Set and reset by software. + /// AHB3 peripheral clock enable in low power mode register + AHB3LPENR: mmio.Mmio(packed struct(u32) { + /// Flexible static memory controller module clock enable during Sleep mode + FMCLPEN: u1, + /// QUADSPI memory controller module clock enable during Sleep mode + QUADSPILPEN: u1, + padding: u30, + }), + reserved96: [4]u8, + /// APB1 peripheral clock enable in low power mode register + APB1LPENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable during Sleep mode TIM2LPEN: u1, - /// TIM3 peripheral clock enable in low-power mode Set and reset by software. + /// TIM3 clock enable during Sleep mode TIM3LPEN: u1, - /// TIM4 peripheral clock enable in low-power mode Set and reset by software. + /// TIM4 clock enable during Sleep mode TIM4LPEN: u1, - /// TIM5 peripheral clock enable in low-power mode Set and reset by software. + /// TIM5 clock enable during Sleep mode TIM5LPEN: u1, - /// TIM6 peripheral clock enable in low-power mode Set and reset by software. + /// TIM6 clock enable during Sleep mode TIM6LPEN: u1, - /// TIM7 peripheral clock enable in low-power mode Set and reset by software. + /// TIM7 clock enable during Sleep mode TIM7LPEN: u1, - /// TIM12 peripheral clock enable in low-power mode Set and reset by software. + /// TIM12 clock enable during Sleep mode TIM12LPEN: u1, - /// TIM13 peripheral clock enable in low-power mode Set and reset by software. + /// TIM13 clock enable during Sleep mode TIM13LPEN: u1, - /// TIM14 peripheral clock enable in low-power mode Set and reset by software. + /// TIM14 clock enable during Sleep mode TIM14LPEN: u1, - /// LPTIM1 peripheral clocks enable in low-power mode Set and reset by software. + /// LPTIM1 clock enable during sleep mode LPTIM1LPEN: u1, - reserved11: u1, - /// WWDG clock enable in low-power mode Set and reset by software. + /// RTC APB clock enable during sleep mode + RTCAPBLPEN: u1, + /// Window watchdog clock enable during Sleep mode WWDGLPEN: u1, reserved14: u2, - /// SPI2 peripheral clocks enable in low-power mode Set and reset by software. + /// SPI2 clock enable during Sleep mode SPI2LPEN: u1, - /// SPI3 peripheral clocks enable in low-power mode Set and reset by software. + /// SPI3 clock enable during Sleep mode SPI3LPEN: u1, - /// SPDIFRX peripheral clocks enable in low-power mode Set and reset by software. - SPDIFRXLPEN: u1, - /// USART2 peripheral clocks enable in low-power mode Set and reset by software. + /// SPDIF clock enable during Sleep mode + SPDIFLPEN: u1, + /// USART2 clock enable during Sleep mode USART2LPEN: u1, - /// USART3 peripheral clocks enable in low-power mode Set and reset by software. + /// USART3 clock enable during Sleep mode USART3LPEN: u1, - /// UART4 peripheral clocks enable in low-power mode Set and reset by software. + /// UART4 clock enable during Sleep mode UART4LPEN: u1, - /// UART5 peripheral clocks enable in low-power mode Set and reset by software. + /// UART5 clock enable during Sleep mode UART5LPEN: u1, - /// I2C1/I3C1 peripheral clocks enable in low-power mode Set and reset by software. - I2C1_I3C1LPEN: u1, - /// I2C2 peripheral clocks enable in low-power mode Set and reset by software. + /// I2C1 clock enable during Sleep mode + I2C1LPEN: u1, + /// I2C2 clock enable during Sleep mode I2C2LPEN: u1, - /// I2C3 peripheral clocks enable in low-power mode Set and reset by software. + /// I2C3 clock enable during Sleep mode I2C3LPEN: u1, - reserved27: u3, - /// HDMI-CEC peripheral clocks enable in low-power mode Set and reset by software. - CECLPEN: u1, - reserved30: u2, - /// UART7 peripheral clocks enable in low-power mode Set and reset by software. + /// FMPI2C1 clock enable during Sleep + FMPI2C1LPEN: u1, + /// CAN 1 clock enable during Sleep mode + CAN1LPEN: u1, + /// CAN 2 clock enable during Sleep mode + CAN2LPEN: u1, + /// CAN3 clock enable during Sleep mode + CAN3LPEN: u1, + /// Power interface clock enable during Sleep mode + PWRLPEN: u1, + /// DAC interface clock enable during Sleep mode + DACLPEN: u1, + /// UART7 clock enable during Sleep mode UART7LPEN: u1, - /// UART8 peripheral clocks enable in low-power mode Set and reset by software. + /// UART8 clock enable during Sleep mode UART8LPEN: u1, }), - /// RCC APB1 low-power clock enable register 2. - APB1LPENR2: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// clock recovery system peripheral clock enable in low-power mode Set and reset by software. - CRSLPEN: u1, - reserved5: u3, - /// MDIOS peripheral clock enable in low-power mode Set and reset by software. - MDIOSLPEN: u1, - reserved8: u2, - /// FDCAN peripheral clock enable in low-power mode Set and reset by software. - FDCANLPEN: u1, - reserved27: u18, - /// UCPD peripheral clock enable in low-power mode Set and reset by software. - UCPDLPEN: u1, - padding: u4, - }), - /// RCC APB2 low-power clock enable register. + /// APB2 peripheral clock enabled in low power mode register APB2LPENR: mmio.Mmio(packed struct(u32) { - /// TIM1 peripheral clock enable in low-power mode Set and reset by software. + /// TIM1 clock enable during Sleep mode TIM1LPEN: u1, - reserved4: u3, - /// USART1 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART169SEL and provided to UCLK inputs, and the pclk2 bus interface clock. + /// TIM8 clock enable during Sleep mode + TIM8LPEN: u1, + reserved4: u2, + /// USART1 clock enable during Sleep mode USART1LPEN: u1, - reserved12: u7, - /// SPI2S1 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the SPI2S1 are: the kernel clock selected by I2S1SEL and provided to spi_ker_ck input, and the pclk2 bus interface clock. + /// USART6 clock enable during Sleep mode + USART6LPEN: u1, + /// UART9 clock enable during Sleep mode + UART9LPEN: u1, + /// UART10 clock enable during Sleep mode + UART10LPEN: u1, + /// ADC1 clock enable during Sleep mode + ADC1LPEN: u1, + /// ADC2 clock enable during Sleep mode + ADC2LPEN: u1, + /// ADC 3 clock enable during Sleep mode + ADC3LPEN: u1, + /// SDIO clock enable during Sleep mode + SDIOLPEN: u1, + /// SPI 1 clock enable during Sleep mode SPI1LPEN: u1, - /// SPI4 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to com_clk input, and the pclk2 bus interface clock. + /// SPI4 clock enable during Sleep mode SPI4LPEN: u1, - reserved16: u2, - /// TIM15 peripheral clock enable in low-power mode Set and reset by software. - TIM15LPEN: u1, - /// TIM16 peripheral clock enable in low-power mode Set and reset by software. - TIM16LPEN: u1, - /// TIM17 peripheral clock enable in low-power mode Set and reset by software. - TIM17LPEN: u1, - /// TIM9 peripheral clock enable in low-power mode Set and reset by software. + /// System configuration controller clock enable during Sleep mode + SYSCFGLPEN: u1, + /// EXTI and External IT clock enable during sleep mode + EXTITLPEN: u1, + /// TIM9 clock enable during sleep mode TIM9LPEN: u1, - /// SPI5 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to com_clk input, and the pclk2 bus interface clock. + /// TIM10 clock enable during Sleep mode + TIM10LPEN: u1, + /// TIM11 clock enable during Sleep mode + TIM11LPEN: u1, + reserved20: u1, + /// SPI5 clock enable during Sleep mode SPI5LPEN: u1, - reserved22: u1, - /// SAI1 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to SAI_CK_A and SAI_CK_B inputs, and the pclk2 bus interface clock. + /// SPI 6 clock enable during Sleep mode + SPI6LPEN: u1, + /// SAI1 clock enable during Sleep mode SAI1LPEN: u1, - /// SAI2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SAI2 are: the kernel clock selected by SAI2SEL and provided to SAI_CK_A and SAI_CK_B inputs, and the pclk2 bus interface clock. + /// SAI2 clock enable SAI2LPEN: u1, - padding: u8, - }), - /// RCC APB4 low-power clock enable register. - APB4LPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SBS peripheral clock enable in low-power mode Set and reset by software. - SYSCFGLPEN: u1, - reserved3: u1, - /// LPUART1 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the rcc_pclk4 bus interface clock. - LPUART1LPEN: u1, - reserved5: u1, - /// SPI/I2S6 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_ck input, and the rcc_pclk4 bus interface clock. - SPI6LPEN: u1, - reserved9: u3, - /// LPTIM2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM23SEL and provided to clk_lpt input, and the pclk4 bus interface clock. - LPTIM2LPEN: u1, - /// LPTIM3 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM23SEL and provided to clk_lpt input, and the pclk4 bus interface clock. - LPTIM3LPEN: u1, - /// LPTIM4 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM4 are the kernel clock selected by LPTIM45SEL and provided to clk_lpt input, and the pclk4 bus interface clock. - LPTIM4LPEN: u1, - /// LPTIM5 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM5 are the kernel clock selected by LPTIM45SEL and provided to clk_lpt input, and the pclk4 bus interface clock. - LPTIM5LPEN: u1, - reserved15: u2, - /// VREF peripheral clock enable in low-power mode Set and reset by software. - VREFLPEN: u1, - /// RTC APB clock enable in low-power mode Set and reset by software. - RTCAPBLPEN: u1, - reserved26: u9, - /// temperature sensor peripheral clock enable in low-power mode Set and reset by software. - TMPSENSLPEN: u1, - padding: u5, - }), - /// RCC APB5 sleep clock register. - APB5LPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// LTDC peripheral clock enable in low-power mode Set and reset by software. + /// DFSDMLPEN + DFSDMLPEN: u1, + /// DFSDM2 clock enable during Sleep mode + DFSDM2LPEN: u1, + /// LTDC clock enable during Sleep mode LTDCLPEN: u1, - /// DCMIPP peripheral clock enable in low-power mode Set and reset by software. - DCMIPPLPEN: u1, - reserved4: u1, - /// GFXTIM peripheral clock enable in low-power mode Set and reset by software. - GFXTIMLPEN: u1, - padding: u27, + /// DSI clocks enable during Sleep mode + DSILPEN: u1, + padding: u4, }), - }; - }; - - pub const pwr_f2 = struct { - pub const PDDS = enum(u1) { - /// Enter Stop mode when the CPU enters deepsleep - STOP_MODE = 0x0, - /// Enter Standby mode when the CPU enters deepsleep - STANDBY_MODE = 0x1, - }; - - /// Power control - pub const PWR = extern struct { - /// power control register - CR: mmio.Mmio(packed struct(u32) { - /// Low-power deep sleep - LPDS: u1, - /// Power down deepsleep - PDDS: packed union { + reserved112: [8]u8, + /// Backup domain control register + BDCR: mmio.Mmio(packed struct(u32) { + /// External low-speed oscillator enable + LSEON: u1, + /// External low-speed oscillator ready + LSERDY: u1, + /// External low-speed oscillator bypass + LSEBYP: u1, + /// External low-speed oscillator bypass + LSEMOD: packed union { raw: u1, - value: PDDS, + value: LSEMOD, }, - /// Clear wakeup flag - CWUF: u1, - /// Clear standby flag - CSBF: u1, - /// Power voltage detector enable - PVDE: u1, - /// PVD level selection - PLS: u3, - /// Disable backup domain write protection - DBP: u1, - /// Flash power down in Stop mode - FPDS: u1, - padding: u22, + reserved8: u4, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, }), - /// power control/status register + /// clock control & status register CSR: mmio.Mmio(packed struct(u32) { - /// Wakeup flag - WUF: u1, - /// Standby flag - SBF: u1, - /// PVD output - PVDO: u1, - /// Backup regulator ready - BRR: u1, - reserved8: u4, - /// Enable WKUP pin - EWUP: u1, - /// Backup regulator enable - BRE: u1, - padding: u22, + /// Internal low-speed oscillator enable + LSION: u1, + /// Internal low-speed oscillator ready + LSIRDY: u1, + reserved24: u22, + /// Remove reset flag + RMVF: u1, + /// BOR reset flag + BORRSTF: u1, + /// PIN reset flag + PADRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + WDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, }), - }; - }; - - pub const bdma_v2 = struct { - pub const DIR = enum(u1) { - /// Read from peripheral - FromPeripheral = 0x0, - /// Read from memory - FromMemory = 0x1, - }; - - pub const PL = enum(u2) { - /// Low priority - Low = 0x0, - /// Medium priority - Medium = 0x1, - /// High priority - High = 0x2, - /// Very high priority - VeryHigh = 0x3, - }; - - pub const SIZE = enum(u2) { - /// 8-bit size - Bits8 = 0x0, - /// 16-bit size - Bits16 = 0x1, - /// 32-bit size - Bits32 = 0x2, - _, - }; - - /// Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers - pub const CH = extern struct { - /// DMA channel configuration register (DMA_CCR) - CR: mmio.Mmio(packed struct(u32) { - /// Channel enable - EN: u1, - /// Transfer complete interrupt enable - TCIE: u1, - /// Half Transfer interrupt enable - HTIE: u1, - /// Transfer error interrupt enable - TEIE: u1, - /// Data transfer direction - DIR: packed union { + reserved128: [8]u8, + /// spread spectrum clock generation register + SSCGR: mmio.Mmio(packed struct(u32) { + /// Modulation period + MODPER: u13, + /// Incrementation step + INCSTEP: u15, + reserved30: u2, + /// Spread Select + SPREADSEL: packed union { raw: u1, - value: DIR, + value: SPREADSEL, }, - /// Circular mode enabled - CIRC: u1, - /// Peripheral increment mode enabled - PINC: u1, - /// Memory increment mode enabled - MINC: u1, - /// Peripheral size - PSIZE: packed union { - raw: u2, - value: SIZE, + /// Spread spectrum modulation enable + SSCGEN: u1, + }), + /// PLLI2S configuration register + PLLI2SCFGR: mmio.Mmio(packed struct(u32) { + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM: packed union { + raw: u6, + value: PLLM, }, - /// Memory size - MSIZE: packed union { - raw: u2, - value: SIZE, + /// Main PLL (PLL) multiplication factor for VCO + PLLN: packed union { + raw: u9, + value: PLLN, }, - /// Channel Priority level - PL: packed union { + reserved16: u1, + /// Main PLL (PLL) division factor for main system clock + PLLP: packed union { raw: u2, - value: PL, + value: PLLP, }, - /// Memory to memory mode enabled - MEM2MEM: u1, - padding: u17, + reserved22: u4, + /// PLLI2S entry clock source + PLLI2SSRC: packed union { + raw: u1, + value: PLLI2SSRC, + }, + reserved24: u1, + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ: packed union { + raw: u4, + value: PLLQ, + }, + /// PLL division factor for I2S and System clocks + PLLR: packed union { + raw: u3, + value: PLLR, + }, + padding: u1, }), - /// DMA channel 1 number of data register - NDTR: mmio.Mmio(packed struct(u32) { - /// Number of data to transfer - NDT: u16, - padding: u16, + /// RCC PLL configuration register + PLLSAICFGR: mmio.Mmio(packed struct(u32) { + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM: packed union { + raw: u6, + value: PLLM, + }, + /// Main PLL (PLL) multiplication factor for VCO + PLLN: packed union { + raw: u9, + value: PLLN, + }, + reserved16: u1, + /// Main PLL (PLL) division factor for main system clock + PLLP: packed union { + raw: u2, + value: PLLP, + }, + reserved22: u4, + /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + PLLSRC: packed union { + raw: u1, + value: PLLSRC, + }, + reserved24: u1, + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ: packed union { + raw: u4, + value: PLLQ, + }, + /// PLL division factor for I2S and System clocks + PLLR: packed union { + raw: u3, + value: PLLR, + }, + padding: u1, }), - /// DMA channel 1 peripheral address register - PAR: u32, - /// DMA channel 1 memory address register - MAR: u32, - }; - - /// DMA controller - pub const DMA = extern struct { - /// DMA interrupt status register (DMA_ISR) - ISR: mmio.Mmio(packed struct(u32) { - /// Channel 1 Global interrupt flag - GIF: u1, - /// Channel 1 Transfer Complete flag - TCIF: u1, - /// Channel 1 Half Transfer Complete flag - HTIF: u1, - /// Channel 1 Transfer Error flag - TEIF: u1, - padding: u28, - }), - /// DMA interrupt flag clear register (DMA_IFCR) - IFCR: mmio.Mmio(packed struct(u32) { - /// Channel 1 Global interrupt flag - GIF: u1, - /// Channel 1 Transfer Complete flag - TCIF: u1, - /// Channel 1 Half Transfer Complete flag - HTIF: u1, - /// Channel 1 Transfer Error flag - TEIF: u1, - padding: u28, - }), - /// Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers - CH: u32, - reserved168: [156]u8, - /// channel selection register - CSELR: mmio.Mmio(packed struct(u32) { - /// DMA channel selection - CS: u4, - padding: u28, - }), - }; - }; - - pub const flash_u0 = struct { - pub const BORR_LEV = enum(u3) { - /// BOR rising level 1 with threshold around 2.1 V - Level1 = 0x0, - /// BOR rising level 2 with threshold around 2.3 V - Level2 = 0x1, - /// BOR rising level 3 with threshold around 2.6 V - Level3 = 0x2, - /// BOR rising level 4 with threshold around 2.9 V - Level4 = 0x3, - _, - }; - - pub const NRST_MODE = enum(u2) { - /// Reset input only: a low level on the NRST pin generates system reset; internal RESET is not propagated to the NRST pin. - OnlyInput = 0x1, - /// Standard GPIO: only internal RESET is possible - OnlyInternal = 0x2, - /// Bidirectional reset: the NRST pin is configured in reset input/output (legacy) mode - Bidirectional = 0x3, - _, - }; - - pub const RDP = enum(u8) { - /// Level 0, read protection not active - Level0 = 0xaa, - /// Level 2, chip read protection active - Level2 = 0xcc, - _, - }; - - /// Mamba FLASH register block - pub const FLASH = extern struct { - /// FLASH access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Flash memory access latency The value in this bitfield represents the number of CPU wait states when accessing the flash memory. Other: Reserved A new write into the bitfield becomes effective when it returns the same value upon read. - LATENCY: u3, - reserved8: u5, - /// CPU Prefetch enable - PRFTEN: u1, - /// CPU Instruction cache enable - ICEN: u1, - reserved11: u1, - /// CPU Instruction cache reset This bit can be written only when the instruction cache is disabled. - ICRST: u1, - reserved16: u4, - /// Main flash memory area empty This bit indicates whether the first location of the main flash memory area is erased or has a programmed value. The bit can be set and reset by software. - EMPTY: u1, - reserved18: u1, - /// Debug access software enable Software may use this bit to enable/disable the debugger read access. - DBG_SWEN: u1, - padding: u13, - }), - reserved8: [4]u8, - /// FLASH key register - KEYR: mmio.Mmio(packed struct(u32) { - /// FLASH key The following values must be written consecutively to unlock the FLASH control register (FLASH_CR), thus enabling programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB - KEY: u32, - }), - /// FLASH option key register - OPTKEYR: mmio.Mmio(packed struct(u32) { - /// Option byte key The following values must be written consecutively to unlock the flash memory option registers, enabling option byte programming/erasing operations: KEY1: 0x0819 2A3B KEY2: 0x4C5D 6E7F - OPTKEY: u32, - }), - /// FLASH status register - SR: mmio.Mmio(packed struct(u32) { - /// End of operation Set by hardware when one or more flash memory operation (programming / erase) has been completed successfully. This bit is set only if the end of operation interrupts are enabled (EOPIE=1). Cleared by writing 1. - EOP: u1, - /// Operation error Set by hardware when a flash memory operation (program / erase) completes unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE=1). Cleared by writing 1. - OPERR: u1, - reserved3: u1, - /// Programming error Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. Cleared by writing 1. - PROGERR: u1, - /// Write protection error Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the flash memory. Cleared by writing 1. - WRPERR: u1, - /// Programming alignment error Set by hardware when the data to program cannot be contained in the same double word (64-bit) flash memory in case of standard programming, or if there is a change of page during fast programming. Cleared by writing 1. - PGAERR: u1, - /// Size error Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). Cleared by writing 1. - SIZERR: u1, - /// Programming sequence error Set by hardware when a write access to the flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. Cleared by writing 1. - PGSERR: u1, - /// Fast programming data miss error In Fast programming mode, 16 double words (128 bytes) must be sent to flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. Cleared by writing 1. - MISSERR: u1, - /// Fast programming error Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. Cleared by writing 1. - FASTERR: u1, - reserved14: u4, - /// PCROP read error Set by hardware when an address to be read belongs to a read protected area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. Cleared by writing 1. - RDERR: u1, - /// Option and Engineering bits loading validity error - OPTVERR: u1, - /// Busy This flag indicates that a flash memory operation requested by FLASH control register (FLASH_CR) is in progress. This bit is set at the beginning of the flash memory operation, and cleared when the operation finishes or when an error occurs. - BSY1: u1, - reserved18: u1, - /// Programming or erase configuration busy. This flag is set and cleared by hardware. It is set when the first word is sent for program or when setting the STRT bit of FLASH control register (FLASH_CR) for erase. It is cleared when the flash memory program or erase operation completes or ends with an error. When set, launching any other operation through the FLASH control register (FLASH_CR) is impossible, and must be postponed (a programming or erase operation is ongoing). When cleared, the program and erase settings in the FLASH control register (FLASH_CR) can be modified. - CFGBSY: u1, - padding: u13, - }), - /// FLASH control register - CR: mmio.Mmio(packed struct(u32) { - /// Flash memory programming enable - PG: u1, - /// Page erase enable - PER: u1, - /// Mass erase When set, this bit triggers the mass erase, that is, all user pages. - MER1: u1, - /// Page number selection These bits select the page to erase: ... Note: Values corresponding to addresses outside the main memory are not allowed. - PNB: u7, - reserved16: u6, - /// Start erase operation This bit triggers an erase operation when set. This bit is possible to set only by software and to clear only by hardware. The hardware clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero. - STRT: u1, - /// Start of modification of option bytes This bit triggers an options operation when set. This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR. - OPTSTRT: u1, - /// Fast programming enable - FSTPG: u1, - reserved24: u5, - /// End-of-operation interrupt enable This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register. - EOPIE: u1, - /// Error interrupt enable This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR register. - ERRIE: u1, - /// PCROP read error interrupt enable This bit enables the interrupt generation upon setting the RDERR flag in the FLASH_SR register. - RDERRIE: u1, - /// Option byte load launch When set, this bit triggers the load of option bytes into option registers. It is automatically cleared upon the completion of the load. The high state of the bit indicates pending option byte load. The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set. - OBL_LAUNCH: u1, - /// Securable memory area protection enable This bit enables the protection on securable area, provided that a non-null securable memory area size (SEC_SIZE[4:0]) is defined in option bytes. This bit is possible to set only by software and to clear only through a system reset. - SEC_PROT: u1, - reserved30: u1, - /// Options Lock This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset. - OPTLOCK: u1, - /// FLASH_CR Lock This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. - LOCK: u1, - }), - /// FLASH ECC register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC fail double-word address offset In case of ECC error or ECC correction detected, this bitfield contains double-word offset (multiple of 64 bits) to main Flash memory. - ADDR_ECC: u14, - reserved20: u6, - /// System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory. - SYSF_ECC: u1, - reserved24: u3, - /// ECC correction interrupt enable - ECCCIE: u1, - reserved30: u5, - /// ECC correction Set by hardware when one ECC error has been detected and corrected. An interrupt is generated if ECCIE is set. Cleared by writing 1. - ECCC: u1, - /// ECC detection Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is generated. Cleared by writing 1. - ECCD: u1, - }), - reserved32: [4]u8, - /// FLASH option register - OPTR: mmio.Mmio(packed struct(u32) { - /// Read protection level Other: Level 1, memories read protection active - RDP: packed union { - raw: u8, - value: RDP, - }, - /// BOR reset level - BORR_LEV: packed union { - raw: u3, - value: BORR_LEV, - }, - reserved13: u2, - /// Reset generated when entering Stop mode - NRST_STOP: u1, - /// Reset generated when entering Standby mode - NRST_STDBY: u1, - /// Reset generated when entering Shutdown mode - NRST_SHDW: u1, - /// Independent watchdog selection - IWDG_SW: u1, - /// Independent watchdog counter freeze in Stop mode - IWDG_STOP: u1, - /// Independent watchdog counter freeze in Standby mode - IWDG_STDBY: u1, - /// Window watchdog selection - WWDG_SW: u1, - reserved21: u1, - /// Backup domain reset - BDRST: u1, - /// SRAM parity check control enable/disable - RAM_PARITY_CHECK: u1, - /// Backup SRAM erase prevention - BKPSRAM_HW_ERASE_DISABLE: u1, - /// BOOT0 signal source selection This option bit defines the source of the BOOT0 signal. - NBOOT_SEL: u1, - /// Boot configuration Together with the BOOT0 pin or option bit NBOOT0 (depending on NBOOT_SEL option bit configuration), this bit selects boot mode from the main flash memory, SRAM or the system memory. Refer to Section12.5: Boot configuration. - NBOOT1: u1, - /// NBOOT0 option bit - NBOOT0: u1, - /// NRST pin configuration - NRST_MODE: packed union { - raw: u2, - value: NRST_MODE, - }, - /// Internal reset holder enable bit - IRHEN: u1, - padding: u2, - }), - reserved44: [8]u8, - /// FLASH WRP area A address register - WRP1AR: mmio.Mmio(packed struct(u32) { - /// WRP area A start offset This bitfield contains the offset of the first page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device. - WRP1A_STRT: u7, - reserved16: u9, - /// WRP area A end offset This bitfield contains the offset of the last page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device. - WRP1A_END: u7, - padding: u9, - }), - /// FLASH WRP area B address register - WRP1BR: mmio.Mmio(packed struct(u32) { - /// WRP area B start offset This bitfield contains the offset of the first page of the WRP area B. Note: The number of effective bits depends on the size of the flash memory in the device. - WRP1B_STRT: u7, - reserved16: u9, - /// WRP area B end offset This bitfield contains the offset of the last page of the WRP area B. Note: The number of effective bits depends on the size of the flash memory in the device. - WRP1B_END: u7, - padding: u9, - }), - reserved128: [76]u8, - /// FLASH security register - SECR: mmio.Mmio(packed struct(u32) { - /// Last page of the first hide protection area - HDP1_PEND: u7, - reserved16: u9, - /// used to force boot from user area If the bit is set in association with RDP level 1, the debug capabilities are disabled, except in the case of a bad OBL (mismatch). - BOOT_LOCK: u1, - reserved24: u7, - /// Hide protection area enable - HDP1EN: u8, - }), - }; - }; - - pub const fsmc_v5x1 = struct { - pub const ACCMOD = enum(u2) { - /// Access mode A - A = 0x0, - /// Access mode B - B = 0x1, - /// Access mode C - C = 0x2, - /// Access mode D - D = 0x3, - }; - - pub const CPSIZE = enum(u3) { - /// No burst split when crossing page boundary - NoBurstSplit = 0x0, - /// 128 bytes CRAM page size - Bytes128 = 0x1, - /// 256 bytes CRAM page size - Bytes256 = 0x2, - /// 512 bytes CRAM page size - Bytes512 = 0x3, - /// 1024 bytes CRAM page size - Bytes1024 = 0x4, - _, - }; - - pub const ECCPS = enum(u3) { - /// ECC page size 256 bytes - Bytes256 = 0x0, - /// ECC page size 512 bytes - Bytes512 = 0x1, - /// ECC page size 1024 bytes - Bytes1024 = 0x2, - /// ECC page size 2048 bytes - Bytes2048 = 0x3, - /// ECC page size 4096 bytes - Bytes4096 = 0x4, - /// ECC page size 8192 bytes - Bytes8192 = 0x5, - _, - }; - - pub const MTYP = enum(u2) { - /// SRAM memory type - SRAM = 0x0, - /// PSRAM (CRAM) memory type - PSRAM = 0x1, - /// NOR Flash/OneNAND Flash - Flash = 0x2, - _, - }; - - pub const MWID = enum(u2) { - /// Memory data bus width 8 bits - Bits8 = 0x0, - /// Memory data bus width 16 bits - Bits16 = 0x1, - /// Memory data bus width 32 bits - Bits32 = 0x2, - _, - }; - - pub const PTYP = enum(u1) { - /// NAND Flash - NANDFlash = 0x1, - _, - }; - - pub const PWID = enum(u2) { - /// External memory device width 8 bits - Bits8 = 0x0, - /// External memory device width 16 bits - Bits16 = 0x1, - _, - }; - - pub const WAITCFG = enum(u1) { - /// NWAIT signal is active one data cycle before wait state - BeforeWaitState = 0x0, - /// NWAIT signal is active during wait state - DuringWaitState = 0x1, - }; - - pub const WAITPOL = enum(u1) { - /// NWAIT active low - ActiveLow = 0x0, - /// NWAIT active high - ActiveHigh = 0x1, - }; - - /// Flexible static memory controller - pub const FSMC = extern struct { - /// SRAM/NOR-Flash chip-select control register 1 - BCR1: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { - raw: u2, - value: MTYP, + /// RCC Dedicated Clock Configuration Register + DCKCFGR: mmio.Mmio(packed struct(u32) { + /// PLLI2S division factor for SAI1 clock + PLLI2SDIVQ: packed union { + raw: u5, + value: PLLI2SDIVQ, }, - /// Memory data bus width - MWID: packed union { - raw: u2, - value: MWID, + reserved8: u3, + /// PLL division factor for SAI1 A/B clock + PLLDIVR: packed union { + raw: u5, + value: PLLDIVR, }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { + reserved14: u1, + /// DFSDM2 audio clock selection + CKDFSDM2ASEL: packed union { raw: u1, - value: WAITPOL, + value: CKDFSDMASEL, }, - reserved11: u1, - /// Wait timing configuration - WAITCFG: packed union { + /// DFSDM1 audio clock selection + CKDFSDM1ASEL: packed union { raw: u1, - value: WAITCFG, + value: CKDFSDMASEL, }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - /// CRAM page size - CPSIZE: packed union { - raw: u3, - value: CPSIZE, + /// division factor for LCD_CLK + PLLSAIDIVR: packed union { + raw: u2, + value: PLLSAIDIVR, }, - /// Write burst enable - CBURSTRW: u1, - /// Continuous clock enable - CCLKEN: u1, - /// Write FIFO disable - WFDIS: u1, - /// Byte lane (NBL) setup - NBLSET: u2, - reserved31: u7, - /// FMC controller enable - FMCEN: u1, - }), - /// SRAM/NOR-Flash chip-select timing register 1-4 - BTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - /// Clock divide ratio (for FMC_CLK signal) - CLKDIV: u4, - /// Data latency for synchronous memory - DATLAT: u4, - /// Access mode - ACCMOD: packed union { + reserved20: u2, + /// SAI1-A clock source selection + SAI1ASRC: packed union { raw: u2, - value: ACCMOD, + value: SAIASRC, }, - /// Data hold phase duration - DATAHLD: u2, - }), - /// SRAM/NOR-Flash chip-select control register 2-4 - BCR: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { + /// SAI1-B clock source selection + SAI1BSRC: packed union { raw: u2, - value: MTYP, + value: SAIBSRC, }, - /// Memory data bus width - MWID: packed union { + /// Timers clocks prescalers selection + TIMPRE: packed union { + raw: u1, + value: TIMPRE, + }, + /// I2S APB1 clocks source selection (I2S2/3) + I2S1SRC: packed union { raw: u2, - value: MWID, + value: I2S1SRC, }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { + /// 48 MHz clock source selection + CLK48SEL: packed union { raw: u1, - value: WAITPOL, + value: CLK48SEL, }, - reserved11: u1, - /// Wait timing configuration - WAITCFG: packed union { + /// SDIO clock source selection + SDIOSEL: packed union { raw: u1, - value: WAITCFG, + value: SDIOSEL, }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - /// CRAM page size - CPSIZE: packed union { - raw: u3, - value: CPSIZE, + /// DSI clock source selection + DSISEL: packed union { + raw: u1, + value: DSISEL, + }, + reserved31: u1, + /// DFSDM1 Kernel clock selection + CKDFSDM1SEL: packed union { + raw: u1, + value: CKDFSDMSEL, }, - /// Write burst enable - CBURSTRW: u1, - reserved22: u2, - /// Byte lane (NBL) setup - NBLSET: u2, - padding: u8, }), - reserved32: [20]u8, - /// PSRAM chip select counter register - PCSCNTR: mmio.Mmio(packed struct(u32) { - /// Chip select counter - CSCOUNT: u16, - /// Counter Bank 1 enable - CNTB1EN: u1, - /// Counter Bank 2 enable - CNTB2EN: u1, - /// Counter Bank 3 enable - CNTB3EN: u1, - /// Counter Bank 4 enable - CNTB4EN: u1, - padding: u12, + /// Clocks gated enable register + CKGATENR: mmio.Mmio(packed struct(u32) { + /// AHB to APB1 Bridge clock enable + AHB2APB1_CKEN: u1, + /// AHB to APB2 Bridge clock enable + AHB2APB2_CKEN: u1, + /// Cortex M4 ETM clock enable + CM4DBG_CKEN: u1, + /// Spare clock enable + SPARE_CKEN: u1, + /// SRAM controller clock enable + SRAM_CKEN: u1, + /// Flash interface clock enable + FLASH_CKEN: u1, + /// RCC clock enable + RCC_CKEN: u1, + /// EVTCL clock enable + EVTCL_CKEN: u1, + padding: u24, }), - reserved128: [92]u8, - /// PC Card/NAND Flash control register - PCR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Wait feature enable bit - PWAITEN: u1, - /// NAND Flash memory bank enable bit - PBKEN: u1, - /// Memory type - PTYP: packed union { + /// DCKCFGR2 register + DCKCFGR2: mmio.Mmio(packed struct(u32) { + reserved22: u22, + /// FMPI2C1 kernel clock source selection + FMPI2C1SEL: packed union { + raw: u2, + value: FMPI2CSEL, + }, + reserved26: u2, + /// HDMI CEC clock source selection + CECSEL: packed union { raw: u1, - value: PTYP, + value: CECSEL, }, - /// Data bus width - PWID: packed union { - raw: u2, - value: PWID, + /// SDIO/USB clock selection + CLK48SEL: packed union { + raw: u1, + value: CLK48SEL, }, - /// ECC computation logic enable bit - ECCEN: u1, - reserved9: u2, - /// CLE to RE delay - TCLR: u4, - /// ALE to RE delay - TAR: u4, - /// ECC page size - ECCPS: packed union { - raw: u3, - value: ECCPS, + /// SDIO clock selection + SDIOSEL: packed union { + raw: u1, + value: SDIOSEL, }, - padding: u12, - }), - /// FIFO status and interrupt register - SR: mmio.Mmio(packed struct(u32) { - /// Interrupt rising edge status - IRS: u1, - /// Interrupt high-level status - ILS: u1, - /// Interrupt falling edge status - IFS: u1, - /// Interrupt rising edge detection enable bit - IREN: u1, - /// Interrupt high-level detection enable bit - ILEN: u1, - /// Interrupt falling edge detection enable bit - IFEN: u1, - /// FIFO empty status - FEMPT: u1, - padding: u25, - }), - /// Common memory space timing register - PMEM: mmio.Mmio(packed struct(u32) { - /// Common memory x setup time - MEMSET: u8, - /// Common memory wait time - MEMWAIT: u8, - /// Common memory hold time - MEMHOLD: u8, - /// Common memory x data bus Hi-Z time - MEMHIZ: u8, - }), - /// Attribute memory space timing register - PATT: mmio.Mmio(packed struct(u32) { - /// Attribute memory setup time - ATTSET: u8, - /// Attribute memory wait time - ATTWAIT: u8, - /// Attribute memory hold time - ATTHOLD: u8, - /// Attribute memory data bus Hi-Z time - ATTHIZ: u8, - }), - reserved148: [4]u8, - /// ECC result register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC computation result value - ECC: u32, - }), - reserved260: [108]u8, - /// SRAM/NOR-Flash write timing registers 1-4 - BWTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - reserved28: u8, - /// Access mode - ACCMOD: packed union { - raw: u2, - value: ACCMOD, + /// SPDIF clock selection + SPDIFRXSEL: packed union { + raw: u1, + value: SPDIFRXSEL, }, - /// Data hold phase duration - DATAHLD: u2, - }), - }; - }; - - pub const pwr_g4 = struct { - pub const VOS = enum(u2) { - Range1 = 0x1, - Range2 = 0x2, - _, - }; - - /// Power control - pub const PWR = extern struct { - /// Power control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection - LPMS: u3, - reserved8: u5, - /// Disable backup domain write protection - DBP: u1, - /// Voltage scaling range selection - VOS: packed union { + /// LPTIM1SEL + LPTIM1SEL: packed union { raw: u2, - value: VOS, + value: LPTIMSEL, }, - reserved14: u3, - /// Low-power run - LPR: u1, - padding: u17, - }), - /// Power control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Power voltage detector enable - PVDE: u1, - /// Power voltage detector level selection - PLS: u3, - /// Peripheral voltage monitoring 1 enable: VDDA vs. COMP min voltage - PVMEN1: u1, - /// Peripheral voltage monitoring 2 enable: VDDA vs. Fast DAC min voltage - PVMEN2: u1, - /// Peripheral voltage monitoring 3 enable: VDDA vs. ADC min voltage 1.62V - PVMEN3: u1, - /// Peripheral voltage monitoring 4 enable: VDDA vs. OPAMP/DAC min voltage - PVMEN4: u1, - padding: u24, - }), - /// Power control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin WKUP1 - EWUP1: u1, - /// Enable Wakeup pin WKUP2 - EWUP2: u1, - /// Enable Wakeup pin WKUP3 - EWUP3: u1, - /// Enable Wakeup pin WKUP4 - EWUP4: u1, - /// Enable Wakeup pin WKUP5 - EWUP5: u1, - reserved8: u3, - /// SRAM2 retention in Standby mode - RRS: u1, - reserved10: u1, - /// Apply pull-up and pull-down configuration - APC: u1, - reserved13: u2, - /// STDBY - UCPD1_STDBY: u1, - /// DBDIS - UCPD1_DBDIS: u1, - /// Enable external WakeUp line - EIWUL: u1, - padding: u16, - }), - /// Power control register 4 - CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity - WP1: u1, - /// Wakeup pin WKUP2 polarity - WP2: u1, - /// Wakeup pin WKUP3 polarity - WP3: u1, - /// Wakeup pin WKUP4 polarity - WP4: u1, - /// Wakeup pin WKUP5 polarity - WP5: u1, - reserved8: u3, - /// VBAT battery charging enable - VBE: u1, - /// VBAT battery charging resistor selection - VBRS: u1, - padding: u22, - }), - /// Power status register 1 - SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag 1 - WUF1: u1, - /// Wakeup flag 2 - WUF2: u1, - /// Wakeup flag 3 - WUF3: u1, - /// Wakeup flag 4 - WUF4: u1, - /// Wakeup flag 5 - WUF5: u1, - reserved8: u3, - /// Standby flag - SBF: u1, - reserved15: u6, - /// Wakeup flag internal - WUFI: u1, - padding: u16, - }), - /// Power status register 2 - SR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Low-power regulator started - REGLPS: u1, - /// Low-power regulator flag - REGLPF: u1, - /// Voltage scaling flag - VOSF: u1, - /// Power voltage detector output - PVDO: u1, - /// Peripheral voltage monitoring output: VDDUSB vs. 1.2 V - PVMO1: u1, - /// Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V - PVMO2: u1, - /// Peripheral voltage monitoring output: VDDA vs. 1.62 V - PVMO3: u1, - /// Peripheral voltage monitoring output: VDDA vs. 2.2 V - PVMO4: u1, - padding: u16, - }), - /// Power status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag 1 - CWUF1: u1, - /// Clear wakeup flag 2 - CWUF2: u1, - /// Clear wakeup flag 3 - CWUF3: u1, - /// Clear wakeup flag 4 - CWUF4: u1, - /// Clear wakeup flag 5 - CWUF5: u1, - reserved8: u3, - /// Clear standby flag - CSBF: u1, - padding: u23, - }), - reserved32: [4]u8, - /// Power Port pull-up control register - PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, - }), - /// Power Port pull-down control register - PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, - }), - reserved128: [88]u8, - /// Power control register 5 - CR5: mmio.Mmio(packed struct(u32) { - /// Main regular range 1 mode - R1MODE: u1, - padding: u31, }), }; }; - pub const pwr_wl5 = struct { - pub const CDS = enum(u1) { - /// CPU is running or in sleep - RunningOrSleep = 0x0, - /// CPU is in Deep-Sleep - DeepSleep = 0x1, - }; - - pub const FPDR = enum(u1) { - /// Flash memory in Idle mode when system is in LPRun mode - Idle = 0x0, - /// Flash memory in Power-down mode when system is in LPRun mode - PowerDown = 0x1, - }; - - pub const FPDS = enum(u1) { - /// Flash memory in Idle mode when system is in LPSleep mode - Idle = 0x0, - /// Flash memory in Power-down mode when system is in LPSleep mode - PowerDown = 0x1, + pub const rcc_f410 = struct { + pub const FMPI2CSEL = enum(u2) { + /// APB clock selected as I2C clock + PCLK1 = 0x0, + /// System clock selected as I2C clock + SYS = 0x1, + /// HSI clock selected as I2C clock + HSI = 0x2, + _, }; - pub const LPMS = enum(u3) { - /// Stop 0 mode - Stop0 = 0x0, - /// Stop 1 mode - Stop1 = 0x1, - /// Stop 2 mode - Stop2 = 0x2, - /// Standby mode - Standby = 0x3, - /// Shutdown mode - Shutdown = 0x4, + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, _, }; - pub const LPR = enum(u1) { - /// Voltage regulator in Main mode in Low-power run mode - MainMode = 0x0, - /// Voltage regulator in low-power mode in Low-power run mode - LowPowerMode = 0x1, + pub const ISSRC = enum(u2) { + /// I2Sx clock frequency = f(PLLCLK_R) + PLLCLKR = 0x0, + /// I2Sx clock frequency = I2S_CKIN Alternate function input frequency + I2S_CKIN = 0x1, + /// I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) + HSI_HSE = 0x3, + _, }; - pub const PLS = enum(u3) { - /// 2.0V - V2_0 = 0x0, - /// 2.2V - V2_2 = 0x1, - /// 2.4V - V2_4 = 0x2, - /// 2.5V - V2_5 = 0x3, - /// 2.6V - V2_6 = 0x4, - /// 2.8V - V2_8 = 0x5, - /// 2.9V - V2_9 = 0x6, - /// External input analog voltage PVD_IN (compared internally to VREFINT) - External = 0x7, + pub const LPTIMSEL = enum(u2) { + /// APB1 clock (PCLK1) selected as LPTILM1 clock + PCLK1 = 0x0, + /// LSI clock is selected as LPTILM1 clock + LSI = 0x1, + /// HSI clock is selected as LPTILM1 clock + HSI = 0x2, + /// LSE clock is selected as LPTILM1 clock + LSE = 0x3, }; - pub const SUBGHZSPINSSSEL = enum(u1) { - /// sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS functionality enabled) - SUBGHZSPICR = 0x0, - /// sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled) - LPTIM3 = 0x1, + pub const MCO1SEL = enum(u2) { + /// HSI clock selected + HSI = 0x0, + /// LSE oscillator selected + LSE = 0x1, + /// HSE oscillator clock selected + HSE = 0x2, + /// PLL clock selected + PLL = 0x3, }; - pub const VBRS = enum(u1) { - /// VBAT charging through a 5 kΩ resistor - R5k = 0x0, - /// VBAT charging through a 1.5 kΩ resistor - R1_5k = 0x1, + pub const MCO2SEL = enum(u2) { + /// System clock (SYSCLK) selected + SYS = 0x0, + /// PLLI2S clock selected + PLLI2S = 0x1, + /// HSE oscillator clock selected + HSE = 0x2, + /// PLL clock selected + PLL = 0x3, }; - pub const VOS = enum(u2) { - /// 1.2 V (range 1) - Range1 = 0x1, - /// 1.0 V (range 2) - Range2 = 0x2, + pub const MCOPRE = enum(u3) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x4, + /// Division by 3 + Div3 = 0x5, + /// Division by 4 + Div4 = 0x6, + /// Division by 5 + Div5 = 0x7, _, }; - pub const WP = enum(u1) { - /// Detection on high level (rising edge) - RisingEdge = 0x0, - /// Detection on low level (falling edge) - FallingEdge = 0x1, - }; - - /// Power control - pub const PWR = extern struct { - /// Power control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection for CPU1 - LPMS: packed union { - raw: u3, - value: LPMS, - }, - /// sub-GHz SPI NSS source select - SUBGHZSPINSSSEL: packed union { - raw: u1, - value: SUBGHZSPINSSSEL, - }, - /// Flash memory power down mode during LPRun for CPU1 - FPDR: packed union { - raw: u1, - value: FPDR, - }, - /// Flash memory power down mode during LPSleep for CPU1 - FPDS: packed union { - raw: u1, - value: FPDS, - }, - reserved8: u2, - /// Disable backup domain write protection - DBP: u1, - /// Voltage scaling range selection - VOS: packed union { - raw: u2, - value: VOS, - }, - reserved14: u3, - /// Low-power run - LPR: packed union { - raw: u1, - value: LPR, - }, - padding: u17, - }), - /// Power control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Power voltage detector enable - PVDE: u1, - /// Power voltage detector level selection. - PLS: packed union { - raw: u3, - value: PLS, - }, - reserved6: u2, - /// Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V - PVME: u1, - padding: u25, - }), - /// Power control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin WKUP1 for CPU1 - EWUP: u1, - reserved7: u6, - /// Ultra-low-power enable - EULPEN: u1, - /// Enable wakeup PVD for CPU1 - EWPVD: u1, - /// SRAM2 retention in Standby mode - RRS: u1, - /// Apply pull-up and pull-down configuration from CPU1 - APC: u1, - /// Enable Radio BUSY Wakeup from Standby for CPU1 - EWRFBUSY: u1, - reserved13: u1, - /// Wakeup for CPU1 - EWRFIRQ: u1, - /// nable CPU2 Hold interrupt for CPU1 - EC2H: u1, - /// Enable internal wakeup line for CPU1 - EIWUL: u1, - padding: u16, - }), - /// Power control register 4 - CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity - WP: packed union { - raw: u1, - value: WP, - }, - reserved8: u7, - /// VBAT battery charging enable - VBE: u1, - /// VBAT battery charging resistor selection - VBRS: packed union { - raw: u1, - value: VBRS, - }, - reserved11: u1, - /// Wakeup Radio BUSY polarity - WRFBUSYP: u1, - reserved15: u3, - /// oot CPU2 after reset or wakeup from Stop or Standby modes. - C2BOOT: u1, - padding: u16, - }), - /// Power status register 1 - SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag 1 - WUF: u1, - reserved8: u7, - /// Wakeup PVD flag - WPVDF: u1, - reserved11: u2, - /// Radio BUSY wakeup flag - WRFBUSYF: u1, - reserved14: u2, - /// PU2 Hold interrupt flag - C2HF: u1, - /// Internal wakeup interrupt flag - WUFI: u1, - padding: u16, - }), - /// Power status register 2 - SR2: mmio.Mmio(packed struct(u32) { - /// PU2 boot/wakeup request source information - C2BOOTS: u1, - /// Radio BUSY signal status - RFBUSYS: u1, - /// Radio BUSY masked signal status - RFBUSYMS: u1, - /// SMPS ready flag - SMPSRDY: u1, - /// LDO ready flag - LDORDY: u1, - /// Radio end of life flag - RFEOLF: u1, - /// regulator2 low power flag - REGMRS: u1, - /// Flash ready - FLASHRDY: u1, - /// regulator1 started - REGLPS: u1, - /// regulator1 low power flag - REGLPF: u1, - /// Voltage scaling flag - VOSF: u1, - /// Power voltage detector output - PVDO: u1, - reserved14: u2, - /// Peripheral voltage monitoring output: VDDA vs. 1.62 V - PVMO: u1, - padding: u17, - }), - /// Power status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag 1 - CWUF: u1, - reserved8: u7, - /// Clear wakeup PVD interrupt flag - CWPVDF: u1, - reserved11: u2, - /// Clear wakeup Radio BUSY flag - CWRFBUSYF: u1, - reserved14: u2, - /// lear CPU2 Hold interrupt flag - CC2HF: u1, - padding: u17, - }), - /// Power control register 5 - CR5: mmio.Mmio(packed struct(u32) { - reserved14: u14, - /// Enable Radio End Of Life detector enabled - RFEOLEN: u1, - /// Enable SMPS Step Down converter SMPS mode enabled. - SMPSEN: u1, - padding: u16, - }), - /// Power Port pull-up control register - PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, - }), - /// Power Port pull-down control register - PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, - }), - reserved128: [88]u8, - /// Power CPU2 control register 1 [dual core device only] - C2CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection for CPU2 - LPMS: u3, - reserved4: u1, - /// Flash memory power down mode during LPRun for CPU2 - FPDR: u1, - /// Flash memory power down mode during LPSleep for CPU2 - FPDS: u1, - padding: u26, - }), - /// Power CPU2 control register 3 [dual core device only] - C2CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin WKUP1 for CPU2 - EWUP: u1, - reserved8: u7, - /// Enable wakeup PVD for CPU2 - EWPVD: u1, - reserved10: u1, - /// Apply pull-up and pull-down configuration for CPU2 - APC: u1, - /// EWRFBUSY - EWRFBUSY: u1, - reserved13: u1, - /// akeup for CPU2 - EWRFIRQ: u1, - reserved15: u1, - /// Enable internal wakeup line for CPU2 - EIWUL: u1, - padding: u16, - }), - /// Power extended status and status clear register - EXTSCR: mmio.Mmio(packed struct(u32) { - /// Clear CPU1 Stop Standby flags - C1CSSF: u1, - /// lear CPU2 Stop Standby flags - C2CSSF: u1, - reserved8: u6, - /// System Standby flag for CPU1. (no core states retained) - C1SBF: u1, - /// System Stop2 flag for CPU1. (partial core states retained) - C1STOP2F: u1, - /// System Stop0, 1 flag for CPU1. (All core states retained) - C1STOPF: u1, - /// ystem Standby flag for CPU2. (no core states retained) - C2SBF: u1, - /// ystem Stop2 flag for CPU2. (partial core states retained) - C2STOP2F: u1, - /// ystem Stop0, 1 flag for CPU2. (All core states retained) - C2STOPF: u1, - /// CPU1 deepsleep mode - C1DS: packed union { - raw: u1, - value: CDS, - }, - /// PU2 deepsleep mode - C2DS: u1, - padding: u16, - }), - /// Power security configuration register [dual core device only] - SECCFGR: mmio.Mmio(packed struct(u32) { - reserved15: u15, - /// wakeup on CPU2 illegal access interrupt enable - C2EWILA: u1, - padding: u16, - }), - /// Power SPI3 control register - SUBGHZSPICR: mmio.Mmio(packed struct(u32) { - reserved15: u15, - /// sub-GHz SPI NSS control - NSS: u1, - padding: u16, - }), - reserved152: [4]u8, - /// RSS Command register [dual core device only] - RSSCMDR: mmio.Mmio(packed struct(u32) { - /// RSS command - RSSCMD: u8, - padding: u24, - }), + pub const PLLM = enum(u6) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + Div16 = 0x10, + Div17 = 0x11, + Div18 = 0x12, + Div19 = 0x13, + Div20 = 0x14, + Div21 = 0x15, + Div22 = 0x16, + Div23 = 0x17, + Div24 = 0x18, + Div25 = 0x19, + Div26 = 0x1a, + Div27 = 0x1b, + Div28 = 0x1c, + Div29 = 0x1d, + Div30 = 0x1e, + Div31 = 0x1f, + Div32 = 0x20, + Div33 = 0x21, + Div34 = 0x22, + Div35 = 0x23, + Div36 = 0x24, + Div37 = 0x25, + Div38 = 0x26, + Div39 = 0x27, + Div40 = 0x28, + Div41 = 0x29, + Div42 = 0x2a, + Div43 = 0x2b, + Div44 = 0x2c, + Div45 = 0x2d, + Div46 = 0x2e, + Div47 = 0x2f, + Div48 = 0x30, + Div49 = 0x31, + Div50 = 0x32, + Div51 = 0x33, + Div52 = 0x34, + Div53 = 0x35, + Div54 = 0x36, + Div55 = 0x37, + Div56 = 0x38, + Div57 = 0x39, + Div58 = 0x3a, + Div59 = 0x3b, + Div60 = 0x3c, + Div61 = 0x3d, + Div62 = 0x3e, + Div63 = 0x3f, + _, }; - }; - pub const flash_h7rs = struct { - pub const BOR_LEV = enum(u2) { - /// BOR OFF, POR/PDR reset threshold level is applied. - Disabled = 0x0, - /// BOR Level 1, the threshold level is low (around 2.1 V). - Level1 = 0x1, - /// BOR Level 2, the threshold level is medium (around 2.4 V). - Level2 = 0x2, - /// BOR Level 3, the threshold level is high (around 2.7 V). - Level3 = 0x3, + pub const PLLN = enum(u9) { + Mul50 = 0x32, + Mul51 = 0x33, + Mul52 = 0x34, + Mul53 = 0x35, + Mul54 = 0x36, + Mul55 = 0x37, + Mul56 = 0x38, + Mul57 = 0x39, + Mul58 = 0x3a, + Mul59 = 0x3b, + Mul60 = 0x3c, + Mul61 = 0x3d, + Mul62 = 0x3e, + Mul63 = 0x3f, + Mul64 = 0x40, + Mul65 = 0x41, + Mul66 = 0x42, + Mul67 = 0x43, + Mul68 = 0x44, + Mul69 = 0x45, + Mul70 = 0x46, + Mul71 = 0x47, + Mul72 = 0x48, + Mul73 = 0x49, + Mul74 = 0x4a, + Mul75 = 0x4b, + Mul76 = 0x4c, + Mul77 = 0x4d, + Mul78 = 0x4e, + Mul79 = 0x4f, + Mul80 = 0x50, + Mul81 = 0x51, + Mul82 = 0x52, + Mul83 = 0x53, + Mul84 = 0x54, + Mul85 = 0x55, + Mul86 = 0x56, + Mul87 = 0x57, + Mul88 = 0x58, + Mul89 = 0x59, + Mul90 = 0x5a, + Mul91 = 0x5b, + Mul92 = 0x5c, + Mul93 = 0x5d, + Mul94 = 0x5e, + Mul95 = 0x5f, + Mul96 = 0x60, + Mul97 = 0x61, + Mul98 = 0x62, + Mul99 = 0x63, + Mul100 = 0x64, + Mul101 = 0x65, + Mul102 = 0x66, + Mul103 = 0x67, + Mul104 = 0x68, + Mul105 = 0x69, + Mul106 = 0x6a, + Mul107 = 0x6b, + Mul108 = 0x6c, + Mul109 = 0x6d, + Mul110 = 0x6e, + Mul111 = 0x6f, + Mul112 = 0x70, + Mul113 = 0x71, + Mul114 = 0x72, + Mul115 = 0x73, + Mul116 = 0x74, + Mul117 = 0x75, + Mul118 = 0x76, + Mul119 = 0x77, + Mul120 = 0x78, + Mul121 = 0x79, + Mul122 = 0x7a, + Mul123 = 0x7b, + Mul124 = 0x7c, + Mul125 = 0x7d, + Mul126 = 0x7e, + Mul127 = 0x7f, + Mul128 = 0x80, + Mul129 = 0x81, + Mul130 = 0x82, + Mul131 = 0x83, + Mul132 = 0x84, + Mul133 = 0x85, + Mul134 = 0x86, + Mul135 = 0x87, + Mul136 = 0x88, + Mul137 = 0x89, + Mul138 = 0x8a, + Mul139 = 0x8b, + Mul140 = 0x8c, + Mul141 = 0x8d, + Mul142 = 0x8e, + Mul143 = 0x8f, + Mul144 = 0x90, + Mul145 = 0x91, + Mul146 = 0x92, + Mul147 = 0x93, + Mul148 = 0x94, + Mul149 = 0x95, + Mul150 = 0x96, + Mul151 = 0x97, + Mul152 = 0x98, + Mul153 = 0x99, + Mul154 = 0x9a, + Mul155 = 0x9b, + Mul156 = 0x9c, + Mul157 = 0x9d, + Mul158 = 0x9e, + Mul159 = 0x9f, + Mul160 = 0xa0, + Mul161 = 0xa1, + Mul162 = 0xa2, + Mul163 = 0xa3, + Mul164 = 0xa4, + Mul165 = 0xa5, + Mul166 = 0xa6, + Mul167 = 0xa7, + Mul168 = 0xa8, + Mul169 = 0xa9, + Mul170 = 0xaa, + Mul171 = 0xab, + Mul172 = 0xac, + Mul173 = 0xad, + Mul174 = 0xae, + Mul175 = 0xaf, + Mul176 = 0xb0, + Mul177 = 0xb1, + Mul178 = 0xb2, + Mul179 = 0xb3, + Mul180 = 0xb4, + Mul181 = 0xb5, + Mul182 = 0xb6, + Mul183 = 0xb7, + Mul184 = 0xb8, + Mul185 = 0xb9, + Mul186 = 0xba, + Mul187 = 0xbb, + Mul188 = 0xbc, + Mul189 = 0xbd, + Mul190 = 0xbe, + Mul191 = 0xbf, + Mul192 = 0xc0, + Mul193 = 0xc1, + Mul194 = 0xc2, + Mul195 = 0xc3, + Mul196 = 0xc4, + Mul197 = 0xc5, + Mul198 = 0xc6, + Mul199 = 0xc7, + Mul200 = 0xc8, + Mul201 = 0xc9, + Mul202 = 0xca, + Mul203 = 0xcb, + Mul204 = 0xcc, + Mul205 = 0xcd, + Mul206 = 0xce, + Mul207 = 0xcf, + Mul208 = 0xd0, + Mul209 = 0xd1, + Mul210 = 0xd2, + Mul211 = 0xd3, + Mul212 = 0xd4, + Mul213 = 0xd5, + Mul214 = 0xd6, + Mul215 = 0xd7, + Mul216 = 0xd8, + Mul217 = 0xd9, + Mul218 = 0xda, + Mul219 = 0xdb, + Mul220 = 0xdc, + Mul221 = 0xdd, + Mul222 = 0xde, + Mul223 = 0xdf, + Mul224 = 0xe0, + Mul225 = 0xe1, + Mul226 = 0xe2, + Mul227 = 0xe3, + Mul228 = 0xe4, + Mul229 = 0xe5, + Mul230 = 0xe6, + Mul231 = 0xe7, + Mul232 = 0xe8, + Mul233 = 0xe9, + Mul234 = 0xea, + Mul235 = 0xeb, + Mul236 = 0xec, + Mul237 = 0xed, + Mul238 = 0xee, + Mul239 = 0xef, + Mul240 = 0xf0, + Mul241 = 0xf1, + Mul242 = 0xf2, + Mul243 = 0xf3, + Mul244 = 0xf4, + Mul245 = 0xf5, + Mul246 = 0xf6, + Mul247 = 0xf7, + Mul248 = 0xf8, + Mul249 = 0xf9, + Mul250 = 0xfa, + Mul251 = 0xfb, + Mul252 = 0xfc, + Mul253 = 0xfd, + Mul254 = 0xfe, + Mul255 = 0xff, + Mul256 = 0x100, + Mul257 = 0x101, + Mul258 = 0x102, + Mul259 = 0x103, + Mul260 = 0x104, + Mul261 = 0x105, + Mul262 = 0x106, + Mul263 = 0x107, + Mul264 = 0x108, + Mul265 = 0x109, + Mul266 = 0x10a, + Mul267 = 0x10b, + Mul268 = 0x10c, + Mul269 = 0x10d, + Mul270 = 0x10e, + Mul271 = 0x10f, + Mul272 = 0x110, + Mul273 = 0x111, + Mul274 = 0x112, + Mul275 = 0x113, + Mul276 = 0x114, + Mul277 = 0x115, + Mul278 = 0x116, + Mul279 = 0x117, + Mul280 = 0x118, + Mul281 = 0x119, + Mul282 = 0x11a, + Mul283 = 0x11b, + Mul284 = 0x11c, + Mul285 = 0x11d, + Mul286 = 0x11e, + Mul287 = 0x11f, + Mul288 = 0x120, + Mul289 = 0x121, + Mul290 = 0x122, + Mul291 = 0x123, + Mul292 = 0x124, + Mul293 = 0x125, + Mul294 = 0x126, + Mul295 = 0x127, + Mul296 = 0x128, + Mul297 = 0x129, + Mul298 = 0x12a, + Mul299 = 0x12b, + Mul300 = 0x12c, + Mul301 = 0x12d, + Mul302 = 0x12e, + Mul303 = 0x12f, + Mul304 = 0x130, + Mul305 = 0x131, + Mul306 = 0x132, + Mul307 = 0x133, + Mul308 = 0x134, + Mul309 = 0x135, + Mul310 = 0x136, + Mul311 = 0x137, + Mul312 = 0x138, + Mul313 = 0x139, + Mul314 = 0x13a, + Mul315 = 0x13b, + Mul316 = 0x13c, + Mul317 = 0x13d, + Mul318 = 0x13e, + Mul319 = 0x13f, + Mul320 = 0x140, + Mul321 = 0x141, + Mul322 = 0x142, + Mul323 = 0x143, + Mul324 = 0x144, + Mul325 = 0x145, + Mul326 = 0x146, + Mul327 = 0x147, + Mul328 = 0x148, + Mul329 = 0x149, + Mul330 = 0x14a, + Mul331 = 0x14b, + Mul332 = 0x14c, + Mul333 = 0x14d, + Mul334 = 0x14e, + Mul335 = 0x14f, + Mul336 = 0x150, + Mul337 = 0x151, + Mul338 = 0x152, + Mul339 = 0x153, + Mul340 = 0x154, + Mul341 = 0x155, + Mul342 = 0x156, + Mul343 = 0x157, + Mul344 = 0x158, + Mul345 = 0x159, + Mul346 = 0x15a, + Mul347 = 0x15b, + Mul348 = 0x15c, + Mul349 = 0x15d, + Mul350 = 0x15e, + Mul351 = 0x15f, + Mul352 = 0x160, + Mul353 = 0x161, + Mul354 = 0x162, + Mul355 = 0x163, + Mul356 = 0x164, + Mul357 = 0x165, + Mul358 = 0x166, + Mul359 = 0x167, + Mul360 = 0x168, + Mul361 = 0x169, + Mul362 = 0x16a, + Mul363 = 0x16b, + Mul364 = 0x16c, + Mul365 = 0x16d, + Mul366 = 0x16e, + Mul367 = 0x16f, + Mul368 = 0x170, + Mul369 = 0x171, + Mul370 = 0x172, + Mul371 = 0x173, + Mul372 = 0x174, + Mul373 = 0x175, + Mul374 = 0x176, + Mul375 = 0x177, + Mul376 = 0x178, + Mul377 = 0x179, + Mul378 = 0x17a, + Mul379 = 0x17b, + Mul380 = 0x17c, + Mul381 = 0x17d, + Mul382 = 0x17e, + Mul383 = 0x17f, + Mul384 = 0x180, + Mul385 = 0x181, + Mul386 = 0x182, + Mul387 = 0x183, + Mul388 = 0x184, + Mul389 = 0x185, + Mul390 = 0x186, + Mul391 = 0x187, + Mul392 = 0x188, + Mul393 = 0x189, + Mul394 = 0x18a, + Mul395 = 0x18b, + Mul396 = 0x18c, + Mul397 = 0x18d, + Mul398 = 0x18e, + Mul399 = 0x18f, + Mul400 = 0x190, + Mul401 = 0x191, + Mul402 = 0x192, + Mul403 = 0x193, + Mul404 = 0x194, + Mul405 = 0x195, + Mul406 = 0x196, + Mul407 = 0x197, + Mul408 = 0x198, + Mul409 = 0x199, + Mul410 = 0x19a, + Mul411 = 0x19b, + Mul412 = 0x19c, + Mul413 = 0x19d, + Mul414 = 0x19e, + Mul415 = 0x19f, + Mul416 = 0x1a0, + Mul417 = 0x1a1, + Mul418 = 0x1a2, + Mul419 = 0x1a3, + Mul420 = 0x1a4, + Mul421 = 0x1a5, + Mul422 = 0x1a6, + Mul423 = 0x1a7, + Mul424 = 0x1a8, + Mul425 = 0x1a9, + Mul426 = 0x1aa, + Mul427 = 0x1ab, + Mul428 = 0x1ac, + Mul429 = 0x1ad, + Mul430 = 0x1ae, + Mul431 = 0x1af, + Mul432 = 0x1b0, + _, }; - pub const CRC_BURST = enum(u2) { - /// every burst has a size of 4 Flash words (64 Bytes). - Word4 = 0x0, - /// every burst has a size of 16 Flash words (256 Bytes). - Word16 = 0x1, - /// every burst has a size of 64 Flash words (1 Kbytes). - Word64 = 0x2, - /// every burst has a size of 256 Flash words (4 Kbytes). - Word256 = 0x3, + pub const PLLP = enum(u2) { + /// PLLP=2 + Div2 = 0x0, + /// PLLP=4 + Div4 = 0x1, + /// PLLP=6 + Div6 = 0x2, + /// PLLP=8 + Div8 = 0x3, }; - pub const DBG_AUTH = enum(u8) { - /// Authentication method using ECDSA signature (NIST P256). - ECDSA = 0x51, - /// Delegated debug (to OEM iRoT code in user Flash). - Delegated = 0x6f, - /// Authentication method using password. - Password = 0x8a, - /// Locked device (no debug allowed). - Locked = 0xb4, + pub const PLLQ = enum(u4) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, _, }; - pub const IROT_SELECT = enum(u8) { - /// ST iRoT is selected at boot. - Selected = 0xb4, + pub const PLLR = enum(u3) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, _, }; - pub const NEXTKL = enum(u2) { - /// OBKINDEX represents the index of the option byte key stored for the hide protection level indicated in SBS_HDPLSR. - Plus0 = 0x0, - /// OBKINDEX represents the index of the option byte key stored for the hide protection level indicated in SBS_HDPLSR plus one (e.g. if HDPL=1 in SBS_HDPLR the key of level 2 is selected). - Plus1 = 0x1, - _, + pub const PLLSRC = enum(u1) { + /// HSI clock selected as PLL and PLLI2S clock entry + HSI = 0x0, + /// HSE oscillator clock selected as PLL and PLLI2S clock entry + HSE = 0x1, }; - pub const NVSRP_NVSTATE = enum(u8) { - /// CLOSE. - Close = 0x51, - /// OPEN. - Open = 0xb4, + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, _, }; - pub const NVSR_NVSTATE = enum(u8) { - /// CLOSED device. - Closed = 0x51, - /// OPEN device. - Open = 0xb4, - _, + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, }; - pub const OBKSIZE = enum(u2) { - /// Key size is 32 bits. - Bits32 = 0x0, - /// Key size is 64 bits. - Bits64 = 0x1, - /// Key size is 128 bits. - Bits128 = 0x2, - /// Key size is 256 bits. - Bits256 = 0x3, + pub const SPREADSEL = enum(u1) { + /// Center spread + Center = 0x0, + /// Down spread + Down = 0x1, }; - pub const OEM_PROVD = enum(u8) { - /// Device has been provisioned by the OEM. - Provisioned = 0xb4, + pub const SW = enum(u2) { + /// HSI oscillator used as system clock + HSI = 0x0, + /// HSE oscillator used as system clock + HSE = 0x1, + /// PLL used as system clock + PLL1_P = 0x2, _, }; - /// Embedded Flash memory. - pub const FLASH = extern struct { - /// Access control register. - ACR: mmio.Mmio(packed struct(u32) { - /// Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. Please refer to Table 27 for details. ... Note: Embedded Flash does not verify that the configuration is correct. - LATENCY: u4, - /// Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to Table 27 for details. Note: Embedded Flash does not verify that the configuration is correct. - WRHIGHFREQ: u2, - padding: u26, - }), - /// FLASH control key register. - KEYR: mmio.Mmio(packed struct(u32) { - /// Control unlock key Following values must be written to FLASH_KEYR consecutively to unlock FLASH_CR register: 1st key = 0x4567 0123 2nd key = 0xCDEF 89AB Reads to this register returns zero. If above sequence is wrong or performed twice, the FLASH_CR register is locked until the next system reset, and access to it generates a bus error. - CUKEY: u32, - }), - reserved16: [8]u8, - /// FLASH control register. + pub const TIMPRE = enum(u1) { + /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx + Mul2 = 0x0, + /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx + Mul4 = 0x1, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// clock control register CR: mmio.Mmio(packed struct(u32) { - /// Configuration lock bit When this bit is set write to all other bits in this register, and to FLASH_IER register, are ignored. Clearing this bit requires the correct write sequence to FLASH_KEYR register (see this register for details). If a wrong sequence is executed, or if the unlock sequence is performed twice, this bit remains locked until the next system reset. During the write access to set LOCK bit from 0 to 1, it is possible to change the other bits of this register. - LOCK: u1, - /// Internal buffer control bit Setting this bit enables internal buffer for write operations. This allows preparing program operations even if a sector or bank erase is ongoing. When PG is cleared, the internal buffer is disabled for write operations, and all the data stored in the buffer but not sent to the operation queue are lost. - PG: u1, - /// Sector erase request Setting this bit requests a sector erase. Write protection error is triggered when a sector erase is required on at least one protected sector. BER has a higher priority than SER: if both bits are set, the embedded Flash memory executes a bank erase. - SER: u1, - /// Bank erase request Setting this bit requests a bank erase operation (user Flash memory only). Write protection error is triggered when a bank erase is required and some sectors are protected. BER has a higher priority than SER: if both are set, the embedded Flash memory executes a bank erase. - BER: u1, - /// Force write This bit forces a write operation even if the write buffer is not full. In this case all bits not written are set by hardware. The embedded Flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it will lead to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively). - FW: u1, - /// Erase start control bit This bit is used to start a sector erase or a bank erase operation. The embedded Flash memory resets START when the corresponding operation has been acknowledged. The user application cannot access any embedded Flash memory register until the operation is acknowledged. - START: u1, - /// Sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). ... - SSN: u2, - reserved16: u8, - /// Program Enable for OTP Area Set this bit to enable write operations to OTP area. - PG_OTP: u1, - /// CRC enable Setting this bit enables the CRC calculation. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR register. When CRC calculation is performed it can be disabled by clearing CRC_EN bit. Doing so sets CRCDATA to 0x0, clears CRC configuration and resets the content of FLASH_CRCDATAR register. - CRC_EN: u1, - reserved24: u6, - /// All banks select bit When this bit is set the erase is done on all Flash Memory sectors. ALL_BANKS is used only if a bank erase is required (BER=1). In all others operations, this control bit is ignored. - ALL_BANKS: u1, - padding: u7, - }), - /// FLASH status register. - SR: mmio.Mmio(packed struct(u32) { - /// Busy flag This bit is set when an effective write, erase or option byte change operation is ongoing. It is possible to know what type of operation is being executed reading the flags IS_PROGRAM, IS_ERASE and IS_OPTCHANGE. BUSY cannot be cleared by application. It is automatically reset by hardware every time a step in a write, erase or option byte change operation completes. It is not recommended to do software polling on BUSY to know when one operation completed because, depending of operation, more pulses are possible for one only operation. For software polling it is therefore better to use QW flag or to check the EOPF flag. - BUSY: u1, - /// Write buffer not empty flag This bit is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_CR the embedded Flash memory detects an error that involves data loss the application software has disabled write operations This bit cannot be forced to 0. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. - WBNE: u1, - /// Wait queue flag This bit is set when a write, erase or option byte change operation is pending in the command queue buffer. It is not possible to know what type of programming operation is present in the queue. This flag is reset by hardware when all write, erase or option byte change operations have been executed and thus removed from the waiting queue(s). This bit cannot be forced to 0. It is reset after a deterministic time if no other operations are requested. - QW: u1, - /// CRC busy flag This bit is set when a CRC calculation is ongoing. This bit cannot be forced to 0. The user must wait until the CRC calculation has completed or disable CRC computation using CRC_EN bit in FLASH_CR register. - CRC_BUSY: u1, - /// Is a program This bit is set together with BUSY when a program operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_OPTCHANGE, because an program operation can happen during an option change. - IS_PROGRAM: u1, - /// Is an erase This bit is set together with BUSY when an erase operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_OPTCHANGE, because an erase operation can happen during an option change. - IS_ERASE: u1, - /// Is an option change This bit is set together with BUSY when an option change operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_PROGRAM or IS_ERASE, because a program or erase step is ongoing during option change. - IS_OPTCHANGE: u1, - reserved25: u18, - /// Root code check flag This bit returns the status of the root code check performed following the first access to the Flash. This bit is cleared with RCHECKF bit in FLASH_FCR (optional). - RCHECKF: u1, + /// Internal high-speed clock enable + HSION: u1, + /// Internal high-speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal high-speed clock trimming + HSITRIM: u5, + /// Internal high-speed clock calibration + HSICAL: u8, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + /// Clock security system enable + CSSON: u1, + reserved24: u4, + /// Main PLL (PLL) enable + PLLON: u1, + /// Main PLL (PLL) clock ready flag + PLLRDY: u1, padding: u6, }), - /// FLASH status register. - FCR: mmio.Mmio(packed struct(u32) { - reserved25: u25, - /// Root code check flag clear Set this bit to clear RCHECKF bit in FLASH_SR. - RCHECKF: u1, - padding: u6, + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM: packed union { + raw: u6, + value: PLLM, + }, + /// Main PLL (PLL) multiplication factor for VCO + PLLN: packed union { + raw: u9, + value: PLLN, + }, + reserved16: u1, + /// Main PLL (PLL) division factor for main system clock + PLLP: packed union { + raw: u2, + value: PLLP, + }, + reserved22: u4, + /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + PLLSRC: packed union { + raw: u1, + value: PLLSRC, + }, + reserved24: u1, + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ: packed union { + raw: u4, + value: PLLQ, + }, + /// PLL division factor for I2S and System clocks + PLLR: packed union { + raw: u3, + value: PLLR, + }, + padding: u1, }), - reserved32: [4]u8, - /// FLASH interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// End-of-program interrupt control bit. - EOPIE: u1, - /// Write protection error interrupt enable bit. - WRPERRIE: u1, - /// Programming sequence error interrupt enable bit. - PGSERRIE: u1, - /// Strobe error interrupt enable bit. - STRBERRIE: u1, - /// Option byte loading error interrupt enable bit. - OBLERRIE: u1, - /// Inconsistency error interrupt enable bit. - INCERRIE: u1, - reserved24: u2, - /// Read security error interrupt enable bit. - RDSERRIE: u1, - /// ECC single correction error interrupt enable bit. - SNECCERRIE: u1, - /// ECC double detection error interrupt enable bit. - DBECCERRIE: u1, - /// CRC end of calculation interrupt enable bit. - CRCENDIE: u1, - /// CRC read error interrupt enable bit. - CRCRDERRIE: u1, - padding: u3, + /// clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u2, + value: SW, + }, + /// System clock switch status + SWS: packed union { + raw: u2, + value: SW, + }, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// MCO output enable + MCO1EN: u1, + /// MCO output enable + MCO2EN: u1, + /// APB Low speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + /// APB high-speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + /// HSE division factor for RTC clock + RTCPRE: u5, + /// Microcontroller clock output 1 + MCO1SEL: packed union { + raw: u2, + value: MCO1SEL, + }, + reserved24: u1, + /// MCO1 prescaler + MCO1PRE: packed union { + raw: u3, + value: MCOPRE, + }, + /// MCO2 prescaler + MCO2PRE: packed union { + raw: u3, + value: MCOPRE, + }, + /// Microcontroller clock output 2 + MCO2SEL: packed union { + raw: u2, + value: MCO2SEL, + }, }), - /// FLASH interrupt status register. - ISR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// End-of-program flag This bit is set when a programming operation completes. An interrupt is generated if the EOPIE is set. It is not necessary to reset EOPF before starting a new operation. Setting EOPF bit in FLASH_ICR register clears this bit. - EOPF: u1, - /// Write protection error flag This bit is set when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set. Setting WRPERRF bit in FLASH_ICR register clears this bit. - WRPERRF: u1, - /// Programming sequence error flag This bit is set when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set. Setting PGSERRF bit in FLASH_ICR register clears this bit. - PGSERRF: u1, - /// Strobe error flag This bit is set when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set. Setting STRBERRF bit in FLASH_ICR register clears this bit. - STRBERRF: u1, - /// Option byte loading error flag This bit is set when an error is found during the option byte loading sequence. An interrupt is generated if OBLERRIE is set. Setting OBLERRF bit in the FLASH_ICR register clears this bit. - OBLERRF: u1, - /// Inconsistency error flag This bit is set when a inconsistency error occurs. An interrupt is generated if INCERRIE is set. Setting INCERRF bit in the FLASH_ICR register clears this bit. - INCERRF: u1, - reserved24: u2, - /// Read security error flag This bit is set when a read security error occurs (read access to hide protected area with incorrect hide protection level). An interrupt is generated if RDSERRIE is set. Setting RDSERRF bit in FLASH_ICR register clears this bit. - RDSERRF: u1, - /// ECC single error flag This bit is set when an ECC single correction error occurs during a read operation. An interrupt is generated if SNECCERRIE is set. Setting SNECCERRF bit in FLASH_ICR register clears this bit. - SNECCERRF: u1, - /// ECC double error flag This bit is set when an ECC double detection error occurs during a read operation. An interrupt is generated if DBECCERRIE is set. Setting DBECCERRF bit in FLASH_ICR register clears this bit. - DBECCERRF: u1, - /// CRC end flag This bit is set when the CRC computation has completed. An interrupt is generated if CRCENDIE is set. It is not necessary to reset CRCEND before restarting CRC computation. Setting CRCENDF bit in FLASH_ICR register clears this bit. - CRCENDF: u1, - /// CRC read error flag This bit is set when a word is found read protected during a CRC operation. An interrupt is generated if CRCRDIE is set. Setting CRCRDERRF bit in FLASH_ICR register clears this bit. This flag is valid only when CRCEND bit is set. - CRCRDERRF: u1, - padding: u3, - }), - /// FLASH interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// End-of-program flag clear Setting this bit clears EOPF flag in FLASH_ISR register. - EOPF: u1, - /// Write protection error flag clear Setting this bit clears WRPERRF flag in FLASH_ISR register. - WRPERRF: u1, - /// Programming sequence error flag clear Setting this bit clears PGSERRF flag in FLASH_ISR register. - PGSERRF: u1, - /// Strobe error flag clear Setting this bit clears STRBERRF flag in FLASH_ISR register. - STRBERRF: u1, - /// Option byte loading error flag clear Setting this bit clears OBLERRF flag in FLASH_ISR register. - OBLERRF: u1, - /// Inconsistency error flag clear Setting this bit clears INCERRF flag in FLASH_ISR register. - INCERRF: u1, - reserved24: u2, - /// Read security error flag clear Setting this bit clears RDSERRF flag in FLASH_ISR register. - RDSERRF: u1, - /// ECC single error flag clear Setting this bit clears SNECCERRF flag in FLASH_ISR register. If the DBECCERRF flag of FLASH_ISR register is also cleared, FLASH_ECCFAR register is reset to zero as well. - SNECCERRF: u1, - /// ECC double error flag clear Setting this bit clears DBECCERRF flag in FLASH_ISR register. If the SNECCERRF flag of FLASH_ISR register is also cleared, FLASH_ECCFAR register is reset to zero as well. - DBECCERRF: u1, - /// CRC end flag clear Setting this bit clears CRCENDF flag in FLASH_ISR register. - CRCENDF: u1, - /// CRC error flag clear Setting this bit clears CRCRDERRF flag in FLASH_ISR register. - CRCRDERRF: u1, - padding: u3, - }), - reserved48: [4]u8, - /// FLASH CRC control register. - CRCCR: mmio.Mmio(packed struct(u32) { - /// CRC sector number CRC_SECT is used to select one user Flash sectors to be added to the list of sectors on which the CRC is calculated. The CRC can be computed either between two addresses (using registers FLASH_CRCSADDR and FLASH_CRCEADDR) or on a list of sectors using this register. If this latter option is selected, it is possible to add a sector to the list of sectors by programming the sector number in CRC_SECT and then setting ADD_SECT bit. The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC computation. ... - CRC_SECT: u2, - reserved9: u7, - /// CRC sector mode select bit When this bit is set the CRC calculation is performed at sector level, on the sectors present in the list of sectors. To add a sector to this list, use ADD_SECT and CRC_SECT bits. To clean the list, use CLEAN_SECT bit. When CRC_BY_SECT is cleared the CRC calculation is performed on all addresses defined between start and end addresses defined in FLASH_CRCSADDR and FLASH_CRCEADDR registers. - CRC_BY_SECT: u1, - /// CRC sector select bit When this bit is set the sector whose number is written in CRC_SECT is added to the list of sectors on which the CRC is calculated. - ADD_SECT: u1, - /// CRC sector list clear bit When this bit is set the list of sectors on which the CRC is calculated is cleared. - CLEAN_SECT: u1, - reserved16: u4, - /// CRC start bit START_CRC bit triggers a CRC calculation using the current configuration. No CRC calculation can launched when an option byte change operation is ongoing because all read accesses to embedded Flash memory registers are put on hold until the option byte change operation has completed. This bit is cleared when CRC computation starts. - START_CRC: u1, - /// CRC clear bit Setting CLEAN_CRC to 1 clears the current CRC result stored in the FLASH_CRCDATAR register. - CLEAN_CRC: u1, - reserved20: u2, - /// CRC burst size CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit. A Flash word is 128-bit. - CRC_BURST: packed union { - raw: u2, - value: CRC_BURST, - }, - reserved24: u2, - /// All sectors selection When this bit is set all the sectors in user Flash are added to list of sectors on which the CRC shall be calculated. This bit is cleared when CRC computation starts. - ALL_SECT: u1, - padding: u7, + /// clock interrupt register + CIR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// Main PLL (PLL) ready interrupt flag + PLLRDYF: u1, + reserved7: u2, + /// Clock security system interrupt flag + CSSF: u1, + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// Main PLL (PLL) ready interrupt enable + PLLRDYIE: u1, + reserved16: u3, + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// Main PLL(PLL) ready interrupt clear + PLLRDYC: u1, + /// PLLI2S ready interrupt clear + PLLI2SRDYC: u1, + reserved23: u1, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, }), - /// FLASH CRC start address register. - CRCSADDR: mmio.Mmio(packed struct(u32) { - reserved6: u6, - /// CRC start address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the first Flash word to use for the CRC calculation, done burst by burst. CRC computation starts at an address aligned to the burst size defined in CRC_BURST of FLASH_CRCCR register. Hence least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank. - CRC_START_ADDR: u11, - padding: u15, + /// AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + reserved7: u4, + /// IO port H reset + GPIOHRST: u1, + reserved12: u4, + /// CRC reset + CRCRST: u1, + reserved21: u8, + /// DMA2 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + reserved31: u8, + /// RNGRST + RNGRST: u1, }), - /// FLASH CRC end address register. - CRCEADDR: mmio.Mmio(packed struct(u32) { - reserved6: u6, - /// CRC end address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the Flash word starting the last burst of the CRC calculation. The burst size is defined in CRC_BURST of FLASH_CRCCR register. The least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank. - CRC_END_ADDR: u11, - padding: u15, + reserved32: [12]u8, + /// APB1 peripheral reset register + APB1RSTR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// TIM5 reset + TIM5RST: u1, + /// TIM6 reset + TIM6RST: u1, + reserved9: u4, + /// LPTIM1 reset + LPTIM1RST: u1, + reserved11: u1, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI 2 reset + SPI2RST: u1, + reserved17: u2, + /// USART 2 reset + USART2RST: u1, + reserved21: u3, + /// I2C 1 reset + I2C1RST: u1, + /// I2C 2 reset + I2C2RST: u1, + reserved24: u1, + /// FMPI2C1 reset + FMPI2C1RST: u1, + reserved28: u3, + /// Power interface reset + PWRRST: u1, + /// DAC reset + DACRST: u1, + padding: u2, }), - /// FLASH CRC data register. - CRCDATAR: mmio.Mmio(packed struct(u32) { - /// CRC result This bitfield contains the result of the last CRC calculation. The value is valid only when CRC calculation completed (CRCENDF is set in FLASH_ISR register). CRC_DATA is cleared when CRC_EN is cleared in FLASH_CR register (CRC disabled), or when CLEAN_CRC bit is set in FLASH_CRCCR register. - CRC_DATA: u32, + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// TIM1 reset + TIM1RST: u1, + reserved4: u3, + /// USART1 reset + USART1RST: u1, + /// USART6 reset + USART6RST: u1, + reserved8: u2, + /// ADC interface reset (common to all ADCs) + ADCRST: u1, + reserved12: u3, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// System configuration controller reset + SYSCFGRST: u1, + reserved16: u1, + /// TIM9 reset + TIM9RST: u1, + reserved18: u1, + /// TIM11 reset + TIM11RST: u1, + reserved20: u1, + /// SPI5 reset + SPI5RST: u1, + padding: u11, }), - /// FLASH ECC single error fail address. - ECCSFADDR: mmio.Mmio(packed struct(u32) { - /// ECC single error correction fail address When a single ECC error correction occurs during a read operation, the SEC_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when SNECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC single error correction error is saved in this register. - SEC_FADD: u32, + reserved48: [8]u8, + /// AHB1 peripheral clock register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + reserved7: u4, + /// IO port H clock enable + GPIOHEN: u1, + reserved12: u4, + /// CRC clock enable + CRCEN: u1, + reserved21: u8, + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + reserved31: u8, + /// RNG clock enable + RNGEN: u1, }), - /// FLASH ECC double error fail address. - ECCDFADDR: mmio.Mmio(packed struct(u32) { - /// ECC double error detection fail address When a double ECC detection occurs during a read operation, the DED_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when the DBECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC double error detection error is saved in this register. - DED_FADD: u32, + reserved64: [12]u8, + /// APB1 peripheral clock enable register + APB1ENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// TIM5 clock enable + TIM5EN: u1, + /// TIM6 clock enable + TIM6EN: u1, + reserved9: u4, + /// LPTIM1 clock enable + LPTIM1EN: u1, + /// RTC APB clock enable + RTCAPBEN: u1, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI2 clock enable + SPI2EN: u1, + reserved17: u2, + /// USART 2 clock enable + USART2EN: u1, + reserved21: u3, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + reserved24: u1, + /// FMPI2C1 clock enable + FMPI2C1EN: u1, + reserved28: u3, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + padding: u2, }), - reserved256: [184]u8, - /// FLASH options key register. - OPTKEYR: mmio.Mmio(packed struct(u32) { - /// Options configuration unlock key Following values must be written to FLASH_OPTKEYR consecutively to unlock FLASH_OPTCR register: 1st key = 0x0819 2A3B 2nd key = 0x4C5D 6E7F Reads to this register returns zero. If above sequence is performed twice locks up the corresponding register/bit until the next system reset, and generates a bus error. - OCUKEY: u32, + /// APB2 peripheral clock enable register + APB2ENR: mmio.Mmio(packed struct(u32) { + /// TIM1 clock enable + TIM1EN: u1, + reserved4: u3, + /// USART1 clock enable + USART1EN: u1, + /// USART6 clock enable + USART6EN: u1, + reserved8: u2, + /// ADC1 clock enable + ADC1EN: u1, + reserved12: u3, + /// SPI1 clock enable + SPI1EN: u1, + reserved14: u1, + /// System configuration controller clock enable + SYSCFGEN: u1, + /// EXTI ans external IT clock enable + EXTITEN: u1, + /// TIM9 clock enable + TIM9EN: u1, + reserved18: u1, + /// TIM11 clock enable + TIM11EN: u1, + reserved20: u1, + /// SPI5 clock enable + SPI5EN: u1, + padding: u11, }), - /// FLASH options control register. - OPTCR: mmio.Mmio(packed struct(u32) { - /// Options lock When this bit is set write to all other bits in this register, and write to OTP words, option bytes and option bytes keys control registers, are ignored. Clearing this bit requires the correct write sequence to FLASH_OPTKEYR register (see this register for details). If a wrong sequence is executed, or the unlock sequence is performed twice, this bit remains locked until next system reset. During the write access to set LOCK bit from 0 to 1, it is possible to change the other bits of this register. - OPTLOCK: u1, - /// Program options. - PG_OPT: u1, - reserved27: u25, - /// Key valid error interrupt enable bit This bit controls if an interrupt has to be generated when KVEF is set in FLASH_OPTISR. - KVEIE: u1, - /// Key transfer error interrupt enable bit This bit controls if an interrupt has to be generated when KTEF is set in FLASH_OPTISR. - KTEIE: u1, - reserved30: u1, - /// Option byte change error interrupt enable bit This bit controls if an interrupt has to be generated when an error occurs during an option byte change. - OPTERRIE: u1, - padding: u1, + reserved80: [8]u8, + /// AHB1 peripheral clock enable in low power mode register + AHB1LPENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable during sleep mode + GPIOALPEN: u1, + /// IO port B clock enable during Sleep mode + GPIOBLPEN: u1, + /// IO port C clock enable during Sleep mode + GPIOCLPEN: u1, + reserved7: u4, + /// IO port H clock enable during Sleep mode + GPIOHLPEN: u1, + reserved12: u4, + /// CRC clock enable during Sleep mode + CRCLPEN: u1, + reserved15: u2, + /// Flash interface clock enable during Sleep mode + FLASHLPEN: u1, + /// SRAM 1interface clock enable during Sleep mode + SRAM1LPEN: u1, + reserved21: u4, + /// DMA1 clock enable during Sleep mode + DMA1LPEN: u1, + /// DMA2 clock enable during Sleep mode + DMA2LPEN: u1, + reserved31: u8, + /// RNG clock enable during sleep mode + RNGLPEN: u1, }), - /// FLASH options interrupt status register. - OPTISR: mmio.Mmio(packed struct(u32) { - reserved27: u27, - /// Key valid error flag This bit is set when loading an unknown or corrupted option byte key. More specifically: Embedded Flash did not find an option byte key that corresponds to the given OBKINDEX[4:0] and the requested HDPL (optionally modified by NEXTKL[1:0]). It can happen for example when requested key has not being provisioned. A double error detection was found when loading the requested option byte key. In this case, if this key is provisioned again the error should disappear. When KVEF is set write to START bit in FLASH_OBKCR is ignored. An interrupt is generated when this flag is raised if the KVEIE bit of FLASH_OPTCR register is set. Setting KVEF bit of register FLASH_OPTICR clears this bit. - KVEF: u1, - /// Key transfer error flag This bit is set when embedded Flash signals an error to the SAES peripheral. It happens when the key size (128-bit or 256-bit) is not matching between embedded Flash OBKSIZE[1:0] and KEYSIZE bit in SAES_CR register. It also happen when an ECC dual error detection occurred while embedded Flash loaded an option byte key for the SAES peripheral. When KTEF is set write to START bit in FLASH_OBKCR is ignored. An interrupt is generated when this flag is raised if the KTEIE bit of FLASH_OPTCR register is set. Setting KTEF bit of register FLASH_OPTICR clears this bit. - KTEF: u1, - reserved30: u1, - /// Option byte change error flag When OPTERRF is set, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTERRIE bit of FLASH_OPTCR register is set. Setting OPTERRF of register FLASH_OPTICR clears this bit. - OPTERRF: u1, - padding: u1, + reserved96: [12]u8, + /// APB1 peripheral clock enable in low power mode register + APB1LPENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// TIM5 clock enable during Sleep mode + TIM5LPEN: u1, + /// TIM6 clock enable during Sleep mode + TIM6LPEN: u1, + reserved9: u4, + /// LPTIM1 clock enable during sleep mode + LPTIM1LPEN: u1, + /// RTC APB clock enable during sleep mode + RTCAPBLPEN: u1, + /// Window watchdog clock enable during Sleep mode + WWDGLPEN: u1, + reserved14: u2, + /// SPI2 clock enable during Sleep mode + SPI2LPEN: u1, + reserved17: u2, + /// USART2 clock enable during Sleep mode + USART2LPEN: u1, + reserved21: u3, + /// I2C1 clock enable during Sleep mode + I2C1LPEN: u1, + /// I2C2 clock enable during Sleep mode + I2C2LPEN: u1, + reserved24: u1, + /// FMPI2C1 clock enable during Sleep + FMPI2C1LPEN: u1, + reserved28: u3, + /// Power interface clock enable during Sleep mode + PWRLPEN: u1, + /// DAC interface clock enable during sleep mode + DACLPEN: u1, + padding: u2, }), - /// FLASH options interrupt clear register. - OPTICR: mmio.Mmio(packed struct(u32) { - reserved27: u27, - /// key valid error flag Set this bit to clear KVEF flag in FLASH_OPTISR register. - KVEF: u1, - /// key transfer error flag Set this bit to clear KTEF flag in FLASH_OPTISR register. - KTEF: u1, - reserved30: u1, - /// Option byte change error flag Set this bit to clear OPTERRF flag in FLASH_OPTISR register. - OPTERRF: u1, - padding: u1, + /// APB2 peripheral clock enabled in low power mode register + APB2LPENR: mmio.Mmio(packed struct(u32) { + /// TIM1 clock enable during Sleep mode + TIM1LPEN: u1, + reserved4: u3, + /// USART1 clock enable during Sleep mode + USART1LPEN: u1, + /// USART6 clock enable during Sleep mode + USART6LPEN: u1, + reserved8: u2, + /// ADC1 clock enable during Sleep mode + ADC1LPEN: u1, + reserved11: u2, + /// SDIO clock enable during Sleep mode + SDIOLPEN: u1, + /// SPI 1 clock enable during Sleep mode + SPI1LPEN: u1, + reserved14: u1, + /// System configuration controller clock enable during Sleep mode + SYSCFGLPEN: u1, + /// EXTI and External IT clock enable during sleep mode + EXTITLPEN: u1, + /// TIM9 clock enable during sleep mode + TIM9LPEN: u1, + reserved18: u1, + /// TIM11 clock enable during Sleep mode + TIM11LPEN: u1, + reserved20: u1, + /// SPI5 clock enable during Sleep mode + SPI5LPEN: u1, + padding: u11, }), - /// FLASH option byte key control register. - OBKCR: mmio.Mmio(packed struct(u32) { - /// Option byte key index This bitfield represents the index of the option byte key in a given hide protection level. Reading keys with index lower that 8, the value is not be available in OBKDRx registers. It is instead sent directly to SAES peripheral. All others keys can be read using OBKDRx registers. Up to 32 keys can be provisioned per hide protection level (0, 1 or 2), provided there is enough space left in the Flash to store them. - OBKINDEX: u5, - reserved8: u3, - /// Next key level 10 or 11: reserved. - NEXTKL: packed union { - raw: u2, - value: NEXTKL, - }, - /// Option byte key size Application must use this bitfield to specify how many bits must be used for the new key. Embedded Flash ignores OBKSIZE during read of option keys because size is stored with the key. - OBKSIZE: packed union { + reserved112: [8]u8, + /// Backup domain control register + BDCR: mmio.Mmio(packed struct(u32) { + /// External low-speed oscillator enable + LSEON: u1, + /// External low-speed oscillator ready + LSERDY: u1, + /// External low-speed oscillator bypass + LSEBYP: u1, + reserved8: u5, + /// RTC clock source selection + RTCSEL: packed union { raw: u2, - value: OBKSIZE, + value: RTCSEL, }, - reserved14: u2, - /// Key program This bit must be set to write option byte keys (keys are read otherwise). - KEYPROG: u1, - /// Key option start This bit is used to start the option byte key operation defined by the PROG bit. The embedded Flash memory resets START when the corresponding operation has been acknowledged. - KEYSTART: u1, - padding: u16, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, }), - reserved280: [4]u8, - /// FLASH option bytes key data register 0. - OBKDR: [8]u32, - reserved512: [200]u8, - /// FLASH non-volatile status register. - NVSR: mmio.Mmio(packed struct(u32) { - /// Non-volatile state others: invalid configuration. - NVSTATE: packed union { - raw: u8, - value: NVSR_NVSTATE, - }, - padding: u24, + /// clock control & status register + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low-speed oscillator enable + LSION: u1, + /// Internal low-speed oscillator ready + LSIRDY: u1, + reserved24: u22, + /// Remove reset flag + RMVF: u1, + /// BOR reset flag + BORRSTF: u1, + /// PIN reset flag + PADRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + WDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, }), - /// FLASH security status register programming. - NVSRP: mmio.Mmio(packed struct(u32) { - /// Non-volatile state programming Write to change corresponding bits in FLASH_NVSR register: Actual option byte change from close to open is triggered only after memory clear hardware process is confirmed. When NVSTATE=0xB4 (resp. 0x51) writing any other value than 0x51 (resp. 0xB4) triggers an option byte change error (OPTERRF). - NVSTATE: packed union { - raw: u8, - value: NVSRP_NVSTATE, + reserved128: [8]u8, + /// spread spectrum clock generation register + SSCGR: mmio.Mmio(packed struct(u32) { + /// Modulation period + MODPER: u13, + /// Incrementation step + INCSTEP: u15, + reserved30: u2, + /// Spread Select + SPREADSEL: packed union { + raw: u1, + value: SPREADSEL, }, - padding: u24, + /// Spread spectrum modulation enable + SSCGEN: u1, }), - /// FLASH RoT status register. - ROTSR: mmio.Mmio(packed struct(u32) { - /// OEM provisioned device Any other value: device is not provisioned by the OEM. - OEM_PROVD: packed union { - raw: u8, - value: OEM_PROVD, - }, - /// Debug authentication method Any other value: no authentication method selected (NotSet). - DBG_AUTH: packed union { - raw: u8, - value: DBG_AUTH, + reserved140: [8]u8, + /// DCKCFGR register + DCKCFGR: mmio.Mmio(packed struct(u32) { + reserved24: u24, + /// TIMPRE + TIMPRE: packed union { + raw: u1, + value: TIMPRE, }, - reserved24: u8, - /// iRoT selection This option is ignored for STM32H7R devices (OEM iRoT is always selected). Any other value: OEM iRoT is selected at boot. - IROT_SELECT: packed union { - raw: u8, - value: IROT_SELECT, + /// I2SSRC + I2SSRC: packed union { + raw: u2, + value: ISSRC, }, + padding: u5, }), - /// FLASH RoT status register programming. - ROTSRP: mmio.Mmio(packed struct(u32) { - /// OEM provisioned device Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 1. - OEM_PROVD: u8, - /// Debug authentication method programming Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 0. - DBG_AUTH: u8, - reserved24: u8, - /// iRoT selection This option is ignored for STM32H7R devices. Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 1 and if NVSTATE is not 0xB4 (OPEN). - IROT_SELECT: u8, - }), - /// FLASH OTP lock status register. - OTPLSR: mmio.Mmio(packed struct(u32) { - /// OTP lock n Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. OTPL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and can no longer be programmed. OTPL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked and can still be modified. - OTPL: u16, - padding: u16, - }), - /// FLASH OTP lock status register programming. - OTPLSRP: mmio.Mmio(packed struct(u32) { - /// OTP lock n programming Write to change corresponding option byte bit in FLASH_OTPLSR. OTPL bits can be only be set, not cleared. - OTPL: u16, - padding: u16, - }), - /// FLASH write protection status register. - WRPSR: mmio.Mmio(packed struct(u32) { - /// Write protection for sector n This bit reflects the write protection status of user Flash sector n. - WRPS: u8, - padding: u24, - }), - /// FLASH write protection status register programming. - WRPSRP: mmio.Mmio(packed struct(u32) { - /// Write protection for sector n programming Write to change corresponding bit in FLASH_WRPSR. - WRPS: u8, - padding: u24, - }), - reserved560: [16]u8, - /// FLASH hide protection status register. - HDPSR: mmio.Mmio(packed struct(u32) { - /// Hide protection user Flash area start This option sets the start address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_ENDCORE voltage scaling output selection Set and cleared by hardware. When decreasing the voltage scaling range, VOSRDY must be one before increasing the SYSCLK frequency. - VOSRDY: u1, - /// Voltage scaling range selection Set a and cleared by software. Cleared by hardware when entering Stop 1 mode. Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - VOS: packed union { - raw: u1, - value: VOS, - }, - padding: u15, - }), - /// supply voltage monitoring control register - SVMCR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Programmable voltage detector enable - PVDE: u1, - /// Programmable voltage detector level selection These bits select the voltage threshold detected by the programmable voltage detector: - PVDLS: packed union { - raw: u3, - value: PVDLS, - }, - padding: u24, - }), - /// wakeup control register 1 - WUCR1: mmio.Mmio(packed struct(u32) { - /// Wakeup and interrupt pin WKUP1 enable Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - WUPEN: u1, - padding: u31, - }), - /// wakeup control register 2 - WUCR2: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - WUPP: packed union { - raw: u1, - value: WUPP, - }, - padding: u31, - }), - /// wakeup control register 3 - WUCR3: mmio.Mmio(packed struct(u32) { - /// Wakeup and interrupt pin WKUP1 selection This field must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - WUSEL1: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup and interrupt pin WKUP2 selection This field must be configured when WUPEN2 = 0. Access can be secured by WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - WUSEL2: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup and interrupt pin WKUP3 selection This field must be configured when WUPEN3 = 0. Access can be secured by WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - WUSEL3: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup and interrupt pin WKUP4 selection This field must be configured when WUPEN4 = 0. Access can be secured by WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - WUSEL4: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup and interrupt pin WKUP5 selection This field must be configured when WUPEN5 = 0. Access can be secured by WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - WUSEL5: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup and interrupt pin WKUP6 selection This field must be configured when WUPEN6 = 0. Access can be secured by WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - WUSEL6: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup and interrupt pin WKUP7 selection This field must be configured when WUPEN7 = 0. Access can be secured by WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - WUSEL7: packed union { - raw: u2, - value: WUSEL, - }, - /// Wakeup and interrupt pin WKUP8 selection This field must be configured when WUPEN8 = 0. Access can be secured by WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - WUSEL8: packed union { - raw: u2, - value: WUSEL, - }, - padding: u16, - }), - reserved40: [8]u8, - /// disable Backup domain register - DBPCR: mmio.Mmio(packed struct(u32) { - /// Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers. - DBP: u1, - padding: u31, - }), - reserved48: [4]u8, - /// security configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// WUP1 secure protection - WUP1SEC: u1, - reserved12: u11, - /// Low-power modes secure protection - LPMSEC: u1, - /// Voltage detection secure protection - VDMSEC: u1, - /// Backup domain secure protection - VBSEC: u1, - padding: u17, - }), - /// privilege control register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// secure functions privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access. - SPRIV: u1, - /// non-secure functions privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. - NSPRIV: u1, - padding: u30, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Clear Stop and Standby flags Access can be secured by LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the STOPF and SBF flags. - CSSF: u1, - /// Stop flag This bit is set by hardware when the device enters a Stop or Standby mode at the same time as the sysclk has been set by hardware to select HSI. It’s cleared by software by writing 1 to the CSSF bit and by hardware when SBF is set. - STOPF: u1, - /// Standby flag This bit is set by hardware when the device enters the Standby mode and the CPU restart from its reset vector. It’s cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset. - SBF: u1, - padding: u29, - }), - /// supply voltage monitoring status register - SVMSR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Programmable voltage detector output - PVDO: packed union { - raw: u1, - value: PVDO, - }, - reserved15: u10, - /// Voltage level ready for currently used VOS - ACTVOSRDY: u1, - /// VOS currently applied to VCORE This field provides the last VOS value. - ACTVOS: packed union { - raw: u1, - value: ACTVOS, - }, - padding: u15, - }), - reserved68: [4]u8, - /// wakeup status register - WUSR: mmio.Mmio(packed struct(u32) { - /// Wakeup and interrupt pending flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0. - WUF: u1, - padding: u31, - }), - /// wakeup status clear register - WUSCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag 1 Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the WUF1 flag in WUSR. - CWUF: u1, - padding: u31, - }), - reserved80: [4]u8, - /// port Standby IO retention enable register - IORETENR: mmio.Mmio(packed struct(u32) { - /// Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy - EN: u1, - padding: u31, - }), - /// port Standby IO retention status register - IORETRA: mmio.Mmio(packed struct(u32) { - /// Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. - RET: u1, - padding: u31, - }), - reserved256: [168]u8, - /// 2.4 GHz RADIO status and control register - RADIOSCR: mmio.Mmio(packed struct(u32) { - /// 2.4 GHz RADIO operating mode. 1x: 2.4 GHz RADIO active mode - MODE: packed union { - raw: u2, - value: MODE, - }, - /// 2.4 GHz RADIO PHY operating mode - PHYMODE: u1, - /// 2.4 GHz RADIO encryption function operating mode - ENCMODE: u1, - reserved8: u4, - /// 2.4 GHz RADIO VDDHPA control word. Bits [3:0] see Table 81: PA output power table format for definition. Bit [4] rf_event. - RFVDDHPA: u5, - reserved15: u2, - /// Ready bit for VDDHPA voltage level when selecting VDDRFPA input. Note: REGPARDYVDDRFPA does not allow to detect correct VDDHPA voltage level when request to lower the level. - REGPARDYVDDRFPA: u1, - padding: u16, - }), + pub const DSISEL = enum(u1) { + /// DSI-PHY used as DSI byte lane clock source (usual case) + DSI_PHY = 0x0, + /// PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode) + PLL1_R = 0x1, }; - }; - pub const cordic_v1 = struct { - pub const FUNC = enum(u4) { - /// Cosine function. - Cosine = 0x0, - /// Sine function. - Sine = 0x1, - /// Phase function. - Phase = 0x2, - /// Modulus function. - Modulus = 0x3, - /// Arctangent function. - Arctangent = 0x4, - /// Hyperbolic Cosine function. - HyperbolicCosine = 0x5, - /// Hyperbolic Sine function. - HyperbolicSine = 0x6, - /// Arctanh function. - Arctanh = 0x7, - /// Natural Logarithm function. - NaturalLogarithm = 0x8, - /// Square Root function. - SquareRoot = 0x9, + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, _, }; - pub const Num = enum(u1) { - /// 1 input/output - Num1 = 0x0, - /// 2 input/output - Num2 = 0x1, - }; - - pub const PRECISION = enum(u4) { - /// 4 iterations. - Iters4 = 0x1, - /// 8 iterations. - Iters8 = 0x2, - /// 12 iterations. - Iters12 = 0x3, - /// 16 iterations. - Iters16 = 0x4, - /// 20 iterations. - Iters20 = 0x5, - /// 24 iterations. - Iters24 = 0x6, - /// 28 iterations. - Iters28 = 0x7, - /// 32 iterations. - Iters32 = 0x8, - /// 36 iterations. - Iters36 = 0x9, - /// 40 iterations. - Iters40 = 0xa, - /// 44 iterations. - Iters44 = 0xb, - /// 48 iterations. - Iters48 = 0xc, - /// 52 iterations. - Iters52 = 0xd, - /// 56 iterations. - Iters56 = 0xe, - /// 60 iterations. - Iters60 = 0xf, + pub const I2CSEL = enum(u2) { + /// APB clock selected as I2C clock + PCLK1 = 0x0, + /// System clock selected as I2C clock + SYS = 0x1, + /// HSI clock selected as I2C clock + HSI = 0x2, _, }; - pub const Scale = enum(u3) { - /// Argument multiplied by 1, result multiplied by 1 - A1_R1 = 0x0, - /// Argument multiplied by 1/2, result multiplied by 2 - A1o2_R2 = 0x1, - /// Argument multiplied by 1/4, result multiplied by 4 - A1o4_R4 = 0x2, - /// Argument multiplied by 1/8, result multiplied by 8 - A1o8_R8 = 0x3, - /// Argument multiplied by 1/16, result multiplied by 16 - A1o16_R16 = 0x4, - /// Argument multiplied by 1/32, result multiplied by 32 - A1o32_R32 = 0x5, - /// Argument multiplied by 1/64, result multiplied by 64 - A1o64_R64 = 0x6, - /// Argument multiplied by 1/128, result multiplied by 128 - A1o128_R128 = 0x7, - }; - - pub const Size = enum(u1) { - /// Use 32 bit input/output values. - Bits32 = 0x0, - /// Use 16 bit input/output values. - Bits16 = 0x1, - }; - - /// CORDIC co-processor. - pub const CORDIC = extern struct { - /// Control and status register. - CSR: mmio.Mmio(packed struct(u32) { - /// Function. - FUNC: packed union { - raw: u4, - value: FUNC, - }, - /// Precision required (number of iterations/cycles), where PRECISION = (number of iterations/4). - PRECISION: packed union { - raw: u4, - value: PRECISION, - }, - /// Scaling factor. Input value has been multiplied by 2^(-n) before for argument. Output value will need to be multiplied by 2^n later for results. - SCALE: packed union { - raw: u3, - value: Scale, - }, - reserved16: u5, - /// Enable interrupt. - IEN: u1, - /// Enable DMA wread channel. - DMAREN: u1, - /// Enable DMA write channel. - DMAWEN: u1, - /// Number of results in the RDATA register. - NRES: packed union { - raw: u1, - value: Num, - }, - /// Number of arguments expected by the WDATA register. - NARGS: packed union { - raw: u1, - value: Num, - }, - /// Width of output data. - RESSIZE: packed union { - raw: u1, - value: Size, - }, - /// Width of input data. - ARGSIZE: packed union { - raw: u1, - value: Size, - }, - reserved31: u8, - /// Result ready flag. - RRDY: u1, - }), - /// Argument register. - WDATA: u32, - /// Result register. - RDATA: u32, - }; - }; - - pub const opamp_h_v2 = struct { - pub const CALON = enum(u1) { - /// Normal mode - Normal = 0x0, - /// Calibration mode (all switches opened by HW) - Calibration = 0x1, - }; - - pub const CALOUT = enum(u1) { - /// Non-inverting < inverting - Less = 0x0, - /// Non-inverting > inverting - Greater = 0x1, - }; - - pub const CALSEL = enum(u2) { - /// VREFOPAMP=3.3% VDDA. - Percent3_3 = 0x0, - /// VREFOPAMP=10% VDDA. - Percent10 = 0x1, - /// VREFOPAMP=50% VDDA. - Percent50 = 0x2, - /// VREFOPAMP=90% VDDA. - Percent90 = 0x3, - }; - - pub const FORCE_VP = enum(u1) { - /// Normal operating mode. Non-inverting input connected to inputs. - NormalOperating = 0x0, - /// Calibration verification mode. Non-inverting input connected to calibration reference voltage. - CalibrationVerification = 0x1, + pub const ISSRC = enum(u1) { + /// PLLI2S clock used as I2S clock source + PLLI2S = 0x0, + /// External clock mapped on the I2S_CKIN pin used as I2S clock source + CKIN = 0x1, }; - pub const OPAHSM = enum(u1) { - /// operational amplifier in normal mode - Normal = 0x0, - /// operational amplifier in high-speed mode - HighSpeed = 0x1, + pub const LPTIMSEL = enum(u2) { + /// APB1 clock (PCLK1) selected as LPTILM1 clock + PCLK1 = 0x0, + /// LSI clock is selected as LPTILM1 clock + LSI = 0x1, + /// HSI clock is selected as LPTILM1 clock + HSI = 0x2, + /// LSE clock is selected as LPTILM1 clock + LSE = 0x3, }; - pub const PGA_GAIN = enum(u4) { - /// Non-inverting internal Gain 2, VREF- referenced - Gain2 = 0x0, - /// Non-inverting internal Gain 4, VREF- referenced - Gain4 = 0x1, - /// Non-inverting internal Gain 8, VREF- referenced - Gain8 = 0x2, - /// Non-inverting internal Gain 16, VREF- referenced - Gain16 = 0x3, - /// Non-inverting internal Gain 2 with filtering on INM0, VREF- referenced - Gain2_FilteringVINM0 = 0x4, - /// Non-inverting internal Gain 4 with filtering on INM0, VREF- referenced - Gain4_FilteringVINM0 = 0x5, - /// Non-inverting internal Gain 8 with filtering on INM0, VREF- referenced - Gain8_FilteringVINM0 = 0x6, - /// Non-inverting internal Gain 8 with filtering on INM0, VREF- referenced - Gain16_FilteringVINM0 = 0x7, - /// Inverting gain=-1/ Non-inverting gain =2 with INM0 node for input or bias - Gain2InvGainNeg1_InputVINM0 = 0x8, - /// Inverting gain=-3/ Non-inverting gain =4 with INM0 node for input or bias - Gain4InvGainNeg3_InputVINM0 = 0x9, - /// Inverting gain=-7/ Non-inverting gain =8 with INM0 node for input or bias - Gain8InvGainNeg7_InputVINM0 = 0xa, - /// Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias - Gain16InvGainNeg15_InputVINM0 = 0xb, - /// Inverting gain=-1/ Non-inverting gain =2 with INM0 node for input or bias, INM1 node for filtering - Gain2InvGainNeg1_InputVINM0FilteringVINM1 = 0xc, - /// Inverting gain=-3/ Non-inverting gain =4 with INM0 node for input or bias, INM1 node for filtering - Gain4InvGainNeg3_InputVINM0FilteringVINM1 = 0xd, - /// Inverting gain=-7/ Non-inverting gain =8 with INM0 node for input or bias, INM1 node for filtering - Gain8InvGainNeg7_InputVINM0FilteringVINM1 = 0xe, - /// Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias, INM1 node for filtering - Gain16InvGainNeg15_InputVINM0FilteringVINM1 = 0xf, + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium high driving capability + MediumHigh = 0x1, + /// Medium low driving capability + MediumLow = 0x2, + /// High driving capability + High = 0x3, }; - pub const USERTRIM = enum(u1) { - /// \'factory\' trim code used - Factory = 0x0, - /// \'user\' trim code used - User = 0x1, + pub const MCO1SEL = enum(u2) { + /// HSI clock selected + HSI = 0x0, + /// LSE oscillator selected + LSE = 0x1, + /// HSE oscillator clock selected + HSE = 0x2, + /// PLL clock selected + PLL = 0x3, }; - pub const VM_SEL = enum(u2) { - /// INM0 connected to OPAMP_VINM input - Inm0 = 0x0, - /// INM1 connected to OPAMP_VINM input - Inm1 = 0x1, - /// Feedback resistor is connected to the OPAMP_VINM input (PGA mode), Inverting input selection depends on the PGA_GAIN setting - Pga = 0x2, - /// opamp_out connected to OPAMP_VINM input (Follower mode) - Follower = 0x3, + pub const MCO2SEL = enum(u2) { + /// System clock (SYSCLK) selected + SYS = 0x0, + /// PLLI2S clock selected + PLLI2S = 0x1, + /// HSE oscillator clock selected + HSE = 0x2, + /// PLL clock selected + PLL = 0x3, }; - pub const VP_SEL = enum(u2) { - /// GPIO INP0 connected to OPAMP_VINP - GpioInp0 = 0x0, - /// dac_outx connected to OPAMPx_VINP - DacOut = 0x1, - /// GPIO INP2 is connected to OPAMP_VINP - GpioInp2 = 0x2, + pub const MCOPRE = enum(u3) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x4, + /// Division by 3 + Div3 = 0x5, + /// Division by 4 + Div4 = 0x6, + /// Division by 5 + Div5 = 0x7, _, }; - /// Operational amplifiers. - pub const OPAMP = extern struct { - /// OPAMP1 control/status register. - CSR: mmio.Mmio(packed struct(u32) { - /// Operational amplifier Enable. - OPAMPEN: u1, - /// Force internal reference on VP (reserved for test. - FORCE_VP: packed union { - raw: u1, - value: FORCE_VP, - }, - /// Operational amplifier PGA mode. - VP_SEL: packed union { - raw: u2, - value: VP_SEL, - }, - reserved5: u1, - /// Inverting input selection. - VM_SEL: packed union { - raw: u2, - value: VM_SEL, - }, - reserved8: u1, - /// Operational amplifier high-speed mode. - OPAHSM: packed union { - raw: u1, - value: OPAHSM, - }, - reserved11: u2, - /// Calibration mode enabled. - CALON: packed union { - raw: u1, - value: CALON, - }, - /// Calibration selection. - CALSEL: packed union { - raw: u2, - value: CALSEL, - }, - /// allows to switch from AOP offset trimmed values to AOP offset. - PGA_GAIN: packed union { - raw: u4, - value: PGA_GAIN, - }, - /// User trimming enable. - USERTRIM: packed union { - raw: u1, - value: USERTRIM, - }, - reserved29: u10, - /// OPAMP calibration reference voltage output control (reserved for test). - TSTREF: u1, - /// Operational amplifier calibration output. - CALOUT: packed union { - raw: u1, - value: CALOUT, - }, - padding: u1, - }), - /// OPAMP1 offset trimming register in normal mode. - OTR: mmio.Mmio(packed struct(u32) { - /// Trim for NMOS differential pairs. - TRIMOFFSETN: u5, - reserved8: u3, - /// Trim for PMOS differential pairs. - TRIMOFFSETP: u5, - padding: u19, - }), - /// OPAMP1 offset trimming register in low-power mode. - HSOTR: mmio.Mmio(packed struct(u32) { - /// Trim for NMOS differential pairs. - TRIMLPOFFSETN: u5, - reserved8: u3, - /// Trim for PMOS differential pairs. - TRIMLPOFFSETP: u5, - padding: u19, - }), + pub const PLLI2SDIVQ = enum(u5) { + /// PLLI2SDIVQ = /1 + Div1 = 0x0, + /// PLLI2SDIVQ = /2 + Div2 = 0x1, + /// PLLI2SDIVQ = /3 + Div3 = 0x2, + /// PLLI2SDIVQ = /4 + Div4 = 0x3, + /// PLLI2SDIVQ = /5 + Div5 = 0x4, + /// PLLI2SDIVQ = /6 + Div6 = 0x5, + /// PLLI2SDIVQ = /7 + Div7 = 0x6, + /// PLLI2SDIVQ = /8 + Div8 = 0x7, + /// PLLI2SDIVQ = /9 + Div9 = 0x8, + /// PLLI2SDIVQ = /10 + Div10 = 0x9, + /// PLLI2SDIVQ = /11 + Div11 = 0xa, + /// PLLI2SDIVQ = /12 + Div12 = 0xb, + /// PLLI2SDIVQ = /13 + Div13 = 0xc, + /// PLLI2SDIVQ = /14 + Div14 = 0xd, + /// PLLI2SDIVQ = /15 + Div15 = 0xe, + /// PLLI2SDIVQ = /16 + Div16 = 0xf, + /// PLLI2SDIVQ = /17 + Div17 = 0x10, + /// PLLI2SDIVQ = /18 + Div18 = 0x11, + /// PLLI2SDIVQ = /19 + Div19 = 0x12, + /// PLLI2SDIVQ = /20 + Div20 = 0x13, + /// PLLI2SDIVQ = /21 + Div21 = 0x14, + /// PLLI2SDIVQ = /22 + Div22 = 0x15, + /// PLLI2SDIVQ = /23 + Div23 = 0x16, + /// PLLI2SDIVQ = /24 + Div24 = 0x17, + /// PLLI2SDIVQ = /25 + Div25 = 0x18, + /// PLLI2SDIVQ = /26 + Div26 = 0x19, + /// PLLI2SDIVQ = /27 + Div27 = 0x1a, + /// PLLI2SDIVQ = /28 + Div28 = 0x1b, + /// PLLI2SDIVQ = /29 + Div29 = 0x1c, + /// PLLI2SDIVQ = /30 + Div30 = 0x1d, + /// PLLI2SDIVQ = /31 + Div31 = 0x1e, + /// PLLI2SDIVQ = /32 + Div32 = 0x1f, }; - }; - pub const syscfg_l1 = struct { - /// System configuration controller - pub const SYSCFG = extern struct { - /// memory remap register - MEMRMP: mmio.Mmio(packed struct(u32) { - /// MEM_MODE - MEM_MODE: u2, - reserved8: u6, - /// BOOT_MODE - BOOT_MODE: u2, - padding: u22, - }), - /// peripheral mode configuration register - PMC: mmio.Mmio(packed struct(u32) { - /// USB pull-up - USB_PU: u1, - /// USB pull-up enable on DP line - LCD_CAPA: u5, - padding: u26, - }), - /// external interrupt configuration register 1 - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration (x = 8 to 11) - EXTI: u4, - padding: u28, - }), + pub const PLLM = enum(u6) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + Div16 = 0x10, + Div17 = 0x11, + Div18 = 0x12, + Div19 = 0x13, + Div20 = 0x14, + Div21 = 0x15, + Div22 = 0x16, + Div23 = 0x17, + Div24 = 0x18, + Div25 = 0x19, + Div26 = 0x1a, + Div27 = 0x1b, + Div28 = 0x1c, + Div29 = 0x1d, + Div30 = 0x1e, + Div31 = 0x1f, + Div32 = 0x20, + Div33 = 0x21, + Div34 = 0x22, + Div35 = 0x23, + Div36 = 0x24, + Div37 = 0x25, + Div38 = 0x26, + Div39 = 0x27, + Div40 = 0x28, + Div41 = 0x29, + Div42 = 0x2a, + Div43 = 0x2b, + Div44 = 0x2c, + Div45 = 0x2d, + Div46 = 0x2e, + Div47 = 0x2f, + Div48 = 0x30, + Div49 = 0x31, + Div50 = 0x32, + Div51 = 0x33, + Div52 = 0x34, + Div53 = 0x35, + Div54 = 0x36, + Div55 = 0x37, + Div56 = 0x38, + Div57 = 0x39, + Div58 = 0x3a, + Div59 = 0x3b, + Div60 = 0x3c, + Div61 = 0x3d, + Div62 = 0x3e, + Div63 = 0x3f, + _, }; - }; - pub const spdifrx_v1 = struct { - /// Receiver Interface - pub const SPDIFRX = extern struct { - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Peripheral Block Enable - SPDIFEN: u2, - /// Receiver DMA ENable for data flow - RXDMAEN: u1, - /// STerEO Mode - RXSTEO: u1, - /// RX Data format - DRFMT: u2, - /// Mask Parity error bit - PMSK: u1, - /// Mask of Validity bit - VMSK: u1, - /// Mask of channel status and user bits - CUMSK: u1, - /// Mask of Preamble Type bits - PTMSK: u1, - /// Control Buffer DMA ENable for control flow - CBDMAEN: u1, - /// Channel Selection - CHSEL: u1, - /// Maximum allowed re-tries during synchronization phase - NBTR: u2, - /// Wait For Activity - WFA: u1, - reserved16: u1, - /// input selection - INSEL: u3, - padding: u13, - }), - /// Interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// RXNE interrupt enable - RXNEIE: u1, - /// Control Buffer Ready Interrupt Enable - CSRNEIE: u1, - /// Parity error interrupt enable - PERRIE: u1, - /// Overrun error Interrupt Enable - OVRIE: u1, - /// Synchronization Block Detected Interrupt Enable - SBLKIE: u1, - /// Synchronization Done - SYNCDIE: u1, - /// Serial Interface Error Interrupt Enable - IFEIE: u1, - padding: u25, - }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Read data register not empty - RXNE: u1, - /// Control Buffer register is not empty - CSRNE: u1, - /// Parity error - PERR: u1, - /// Overrun error - OVR: u1, - /// Synchronization Block Detected - SBD: u1, - /// Synchronization Done - SYNCD: u1, - /// Framing error - FERR: u1, - /// Synchronization error - SERR: u1, - /// Time-out error - TERR: u1, - reserved16: u7, - /// Duration of 5 symbols counted with SPDIF_CLK - WIDTH: u15, - padding: u1, - }), - /// Interrupt Flag Clear register - IFCR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Clears the Parity error flag - PERRCF: u1, - /// Clears the Overrun error flag - OVRCF: u1, - /// Clears the Synchronization Block Detected flag - SBDCF: u1, - /// Clears the Synchronization Done flag - SYNCDCF: u1, - padding: u26, - }), - /// Data input register - DR: mmio.Mmio(packed struct(u32) { - /// Parity Error bit - DR: u24, - /// Parity Error bit - PE: u1, - /// Validity bit - V: u1, - /// User bit - U: u1, - /// Channel Status bit - C: u1, - /// Preamble Type - PT: u2, - padding: u2, - }), - /// Channel Status register - CSR: mmio.Mmio(packed struct(u32) { - /// User data information - USR: u16, - /// Channel A status information - CS: u8, - /// Start Of Block - SOB: u1, - padding: u7, - }), - /// Debug Information register - DIR: mmio.Mmio(packed struct(u32) { - /// Threshold HIGH - THI: u13, - reserved16: u3, - /// Threshold LOW - TLO: u13, - padding: u3, - }), + pub const PLLN = enum(u9) { + Mul50 = 0x32, + Mul51 = 0x33, + Mul52 = 0x34, + Mul53 = 0x35, + Mul54 = 0x36, + Mul55 = 0x37, + Mul56 = 0x38, + Mul57 = 0x39, + Mul58 = 0x3a, + Mul59 = 0x3b, + Mul60 = 0x3c, + Mul61 = 0x3d, + Mul62 = 0x3e, + Mul63 = 0x3f, + Mul64 = 0x40, + Mul65 = 0x41, + Mul66 = 0x42, + Mul67 = 0x43, + Mul68 = 0x44, + Mul69 = 0x45, + Mul70 = 0x46, + Mul71 = 0x47, + Mul72 = 0x48, + Mul73 = 0x49, + Mul74 = 0x4a, + Mul75 = 0x4b, + Mul76 = 0x4c, + Mul77 = 0x4d, + Mul78 = 0x4e, + Mul79 = 0x4f, + Mul80 = 0x50, + Mul81 = 0x51, + Mul82 = 0x52, + Mul83 = 0x53, + Mul84 = 0x54, + Mul85 = 0x55, + Mul86 = 0x56, + Mul87 = 0x57, + Mul88 = 0x58, + Mul89 = 0x59, + Mul90 = 0x5a, + Mul91 = 0x5b, + Mul92 = 0x5c, + Mul93 = 0x5d, + Mul94 = 0x5e, + Mul95 = 0x5f, + Mul96 = 0x60, + Mul97 = 0x61, + Mul98 = 0x62, + Mul99 = 0x63, + Mul100 = 0x64, + Mul101 = 0x65, + Mul102 = 0x66, + Mul103 = 0x67, + Mul104 = 0x68, + Mul105 = 0x69, + Mul106 = 0x6a, + Mul107 = 0x6b, + Mul108 = 0x6c, + Mul109 = 0x6d, + Mul110 = 0x6e, + Mul111 = 0x6f, + Mul112 = 0x70, + Mul113 = 0x71, + Mul114 = 0x72, + Mul115 = 0x73, + Mul116 = 0x74, + Mul117 = 0x75, + Mul118 = 0x76, + Mul119 = 0x77, + Mul120 = 0x78, + Mul121 = 0x79, + Mul122 = 0x7a, + Mul123 = 0x7b, + Mul124 = 0x7c, + Mul125 = 0x7d, + Mul126 = 0x7e, + Mul127 = 0x7f, + Mul128 = 0x80, + Mul129 = 0x81, + Mul130 = 0x82, + Mul131 = 0x83, + Mul132 = 0x84, + Mul133 = 0x85, + Mul134 = 0x86, + Mul135 = 0x87, + Mul136 = 0x88, + Mul137 = 0x89, + Mul138 = 0x8a, + Mul139 = 0x8b, + Mul140 = 0x8c, + Mul141 = 0x8d, + Mul142 = 0x8e, + Mul143 = 0x8f, + Mul144 = 0x90, + Mul145 = 0x91, + Mul146 = 0x92, + Mul147 = 0x93, + Mul148 = 0x94, + Mul149 = 0x95, + Mul150 = 0x96, + Mul151 = 0x97, + Mul152 = 0x98, + Mul153 = 0x99, + Mul154 = 0x9a, + Mul155 = 0x9b, + Mul156 = 0x9c, + Mul157 = 0x9d, + Mul158 = 0x9e, + Mul159 = 0x9f, + Mul160 = 0xa0, + Mul161 = 0xa1, + Mul162 = 0xa2, + Mul163 = 0xa3, + Mul164 = 0xa4, + Mul165 = 0xa5, + Mul166 = 0xa6, + Mul167 = 0xa7, + Mul168 = 0xa8, + Mul169 = 0xa9, + Mul170 = 0xaa, + Mul171 = 0xab, + Mul172 = 0xac, + Mul173 = 0xad, + Mul174 = 0xae, + Mul175 = 0xaf, + Mul176 = 0xb0, + Mul177 = 0xb1, + Mul178 = 0xb2, + Mul179 = 0xb3, + Mul180 = 0xb4, + Mul181 = 0xb5, + Mul182 = 0xb6, + Mul183 = 0xb7, + Mul184 = 0xb8, + Mul185 = 0xb9, + Mul186 = 0xba, + Mul187 = 0xbb, + Mul188 = 0xbc, + Mul189 = 0xbd, + Mul190 = 0xbe, + Mul191 = 0xbf, + Mul192 = 0xc0, + Mul193 = 0xc1, + Mul194 = 0xc2, + Mul195 = 0xc3, + Mul196 = 0xc4, + Mul197 = 0xc5, + Mul198 = 0xc6, + Mul199 = 0xc7, + Mul200 = 0xc8, + Mul201 = 0xc9, + Mul202 = 0xca, + Mul203 = 0xcb, + Mul204 = 0xcc, + Mul205 = 0xcd, + Mul206 = 0xce, + Mul207 = 0xcf, + Mul208 = 0xd0, + Mul209 = 0xd1, + Mul210 = 0xd2, + Mul211 = 0xd3, + Mul212 = 0xd4, + Mul213 = 0xd5, + Mul214 = 0xd6, + Mul215 = 0xd7, + Mul216 = 0xd8, + Mul217 = 0xd9, + Mul218 = 0xda, + Mul219 = 0xdb, + Mul220 = 0xdc, + Mul221 = 0xdd, + Mul222 = 0xde, + Mul223 = 0xdf, + Mul224 = 0xe0, + Mul225 = 0xe1, + Mul226 = 0xe2, + Mul227 = 0xe3, + Mul228 = 0xe4, + Mul229 = 0xe5, + Mul230 = 0xe6, + Mul231 = 0xe7, + Mul232 = 0xe8, + Mul233 = 0xe9, + Mul234 = 0xea, + Mul235 = 0xeb, + Mul236 = 0xec, + Mul237 = 0xed, + Mul238 = 0xee, + Mul239 = 0xef, + Mul240 = 0xf0, + Mul241 = 0xf1, + Mul242 = 0xf2, + Mul243 = 0xf3, + Mul244 = 0xf4, + Mul245 = 0xf5, + Mul246 = 0xf6, + Mul247 = 0xf7, + Mul248 = 0xf8, + Mul249 = 0xf9, + Mul250 = 0xfa, + Mul251 = 0xfb, + Mul252 = 0xfc, + Mul253 = 0xfd, + Mul254 = 0xfe, + Mul255 = 0xff, + Mul256 = 0x100, + Mul257 = 0x101, + Mul258 = 0x102, + Mul259 = 0x103, + Mul260 = 0x104, + Mul261 = 0x105, + Mul262 = 0x106, + Mul263 = 0x107, + Mul264 = 0x108, + Mul265 = 0x109, + Mul266 = 0x10a, + Mul267 = 0x10b, + Mul268 = 0x10c, + Mul269 = 0x10d, + Mul270 = 0x10e, + Mul271 = 0x10f, + Mul272 = 0x110, + Mul273 = 0x111, + Mul274 = 0x112, + Mul275 = 0x113, + Mul276 = 0x114, + Mul277 = 0x115, + Mul278 = 0x116, + Mul279 = 0x117, + Mul280 = 0x118, + Mul281 = 0x119, + Mul282 = 0x11a, + Mul283 = 0x11b, + Mul284 = 0x11c, + Mul285 = 0x11d, + Mul286 = 0x11e, + Mul287 = 0x11f, + Mul288 = 0x120, + Mul289 = 0x121, + Mul290 = 0x122, + Mul291 = 0x123, + Mul292 = 0x124, + Mul293 = 0x125, + Mul294 = 0x126, + Mul295 = 0x127, + Mul296 = 0x128, + Mul297 = 0x129, + Mul298 = 0x12a, + Mul299 = 0x12b, + Mul300 = 0x12c, + Mul301 = 0x12d, + Mul302 = 0x12e, + Mul303 = 0x12f, + Mul304 = 0x130, + Mul305 = 0x131, + Mul306 = 0x132, + Mul307 = 0x133, + Mul308 = 0x134, + Mul309 = 0x135, + Mul310 = 0x136, + Mul311 = 0x137, + Mul312 = 0x138, + Mul313 = 0x139, + Mul314 = 0x13a, + Mul315 = 0x13b, + Mul316 = 0x13c, + Mul317 = 0x13d, + Mul318 = 0x13e, + Mul319 = 0x13f, + Mul320 = 0x140, + Mul321 = 0x141, + Mul322 = 0x142, + Mul323 = 0x143, + Mul324 = 0x144, + Mul325 = 0x145, + Mul326 = 0x146, + Mul327 = 0x147, + Mul328 = 0x148, + Mul329 = 0x149, + Mul330 = 0x14a, + Mul331 = 0x14b, + Mul332 = 0x14c, + Mul333 = 0x14d, + Mul334 = 0x14e, + Mul335 = 0x14f, + Mul336 = 0x150, + Mul337 = 0x151, + Mul338 = 0x152, + Mul339 = 0x153, + Mul340 = 0x154, + Mul341 = 0x155, + Mul342 = 0x156, + Mul343 = 0x157, + Mul344 = 0x158, + Mul345 = 0x159, + Mul346 = 0x15a, + Mul347 = 0x15b, + Mul348 = 0x15c, + Mul349 = 0x15d, + Mul350 = 0x15e, + Mul351 = 0x15f, + Mul352 = 0x160, + Mul353 = 0x161, + Mul354 = 0x162, + Mul355 = 0x163, + Mul356 = 0x164, + Mul357 = 0x165, + Mul358 = 0x166, + Mul359 = 0x167, + Mul360 = 0x168, + Mul361 = 0x169, + Mul362 = 0x16a, + Mul363 = 0x16b, + Mul364 = 0x16c, + Mul365 = 0x16d, + Mul366 = 0x16e, + Mul367 = 0x16f, + Mul368 = 0x170, + Mul369 = 0x171, + Mul370 = 0x172, + Mul371 = 0x173, + Mul372 = 0x174, + Mul373 = 0x175, + Mul374 = 0x176, + Mul375 = 0x177, + Mul376 = 0x178, + Mul377 = 0x179, + Mul378 = 0x17a, + Mul379 = 0x17b, + Mul380 = 0x17c, + Mul381 = 0x17d, + Mul382 = 0x17e, + Mul383 = 0x17f, + Mul384 = 0x180, + Mul385 = 0x181, + Mul386 = 0x182, + Mul387 = 0x183, + Mul388 = 0x184, + Mul389 = 0x185, + Mul390 = 0x186, + Mul391 = 0x187, + Mul392 = 0x188, + Mul393 = 0x189, + Mul394 = 0x18a, + Mul395 = 0x18b, + Mul396 = 0x18c, + Mul397 = 0x18d, + Mul398 = 0x18e, + Mul399 = 0x18f, + Mul400 = 0x190, + Mul401 = 0x191, + Mul402 = 0x192, + Mul403 = 0x193, + Mul404 = 0x194, + Mul405 = 0x195, + Mul406 = 0x196, + Mul407 = 0x197, + Mul408 = 0x198, + Mul409 = 0x199, + Mul410 = 0x19a, + Mul411 = 0x19b, + Mul412 = 0x19c, + Mul413 = 0x19d, + Mul414 = 0x19e, + Mul415 = 0x19f, + Mul416 = 0x1a0, + Mul417 = 0x1a1, + Mul418 = 0x1a2, + Mul419 = 0x1a3, + Mul420 = 0x1a4, + Mul421 = 0x1a5, + Mul422 = 0x1a6, + Mul423 = 0x1a7, + Mul424 = 0x1a8, + Mul425 = 0x1a9, + Mul426 = 0x1aa, + Mul427 = 0x1ab, + Mul428 = 0x1ac, + Mul429 = 0x1ad, + Mul430 = 0x1ae, + Mul431 = 0x1af, + Mul432 = 0x1b0, + _, }; - }; - pub const pwr_u0 = struct { - pub const LPMS = enum(u3) { - /// Stop 0 mode - Stop0 = 0x0, - /// Stop 1 mode - Stop1 = 0x1, - /// Stop 2 mode - Stop2 = 0x2, - /// Standby mode - Standby = 0x3, + pub const PLLP = enum(u2) { + /// PLLP=2 + Div2 = 0x0, + /// PLLP=4 + Div4 = 0x1, + /// PLLP=6 + Div6 = 0x2, + /// PLLP=8 + Div8 = 0x3, + }; + + pub const PLLQ = enum(u4) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, _, }; - pub const PLS = enum(u3) { - /// VPVD0 around 2.01V - B_0x0 = 0x0, - /// VPVD1 around 2.21V - B_0x1 = 0x1, - /// VPVD2 around 2.41V - B_0x2 = 0x2, - /// VPVD3 around 2.51V - B_0x3 = 0x3, - /// VPVD4 around 2.61V - B_0x4 = 0x4, - /// VPVD5 around 2.81V - B_0x5 = 0x5, - /// VPVD6 around 2.91V - B_0x6 = 0x6, - /// External input analog voltage PVD_IN (compared internally to VREFINT) - B_0x7 = 0x7, + pub const PLLR = enum(u3) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + _, }; - pub const STOPF = enum(u3) { - /// The device did not enter any Stop mode. - None = 0x0, - /// The device entered in Stop 0 mode. - Stop0 = 0x4, - /// The device entered in Stop 1 mode. - Stop1 = 0x5, - /// The device entered in Stop 2 mode. - Stop2 = 0x6, + pub const PLLSAIDIVQ = enum(u5) { + /// PLLSAIDIVQ = /1 + Div1 = 0x0, + /// PLLSAIDIVQ = /2 + Div2 = 0x1, + /// PLLSAIDIVQ = /3 + Div3 = 0x2, + /// PLLSAIDIVQ = /4 + Div4 = 0x3, + /// PLLSAIDIVQ = /5 + Div5 = 0x4, + /// PLLSAIDIVQ = /6 + Div6 = 0x5, + /// PLLSAIDIVQ = /7 + Div7 = 0x6, + /// PLLSAIDIVQ = /8 + Div8 = 0x7, + /// PLLSAIDIVQ = /9 + Div9 = 0x8, + /// PLLSAIDIVQ = /10 + Div10 = 0x9, + /// PLLSAIDIVQ = /11 + Div11 = 0xa, + /// PLLSAIDIVQ = /12 + Div12 = 0xb, + /// PLLSAIDIVQ = /13 + Div13 = 0xc, + /// PLLSAIDIVQ = /14 + Div14 = 0xd, + /// PLLSAIDIVQ = /15 + Div15 = 0xe, + /// PLLSAIDIVQ = /16 + Div16 = 0xf, + /// PLLSAIDIVQ = /17 + Div17 = 0x10, + /// PLLSAIDIVQ = /18 + Div18 = 0x11, + /// PLLSAIDIVQ = /19 + Div19 = 0x12, + /// PLLSAIDIVQ = /20 + Div20 = 0x13, + /// PLLSAIDIVQ = /21 + Div21 = 0x14, + /// PLLSAIDIVQ = /22 + Div22 = 0x15, + /// PLLSAIDIVQ = /23 + Div23 = 0x16, + /// PLLSAIDIVQ = /24 + Div24 = 0x17, + /// PLLSAIDIVQ = /25 + Div25 = 0x18, + /// PLLSAIDIVQ = /26 + Div26 = 0x19, + /// PLLSAIDIVQ = /27 + Div27 = 0x1a, + /// PLLSAIDIVQ = /28 + Div28 = 0x1b, + /// PLLSAIDIVQ = /29 + Div29 = 0x1c, + /// PLLSAIDIVQ = /30 + Div30 = 0x1d, + /// PLLSAIDIVQ = /31 + Div31 = 0x1e, + /// PLLSAIDIVQ = /32 + Div32 = 0x1f, + }; + + pub const PLLSAIDIVR = enum(u2) { + /// PLLSAIDIVR = /2 + Div2 = 0x0, + /// PLLSAIDIVR = /4 + Div4 = 0x1, + /// PLLSAIDIVR = /8 + Div8 = 0x2, + /// PLLSAIDIVR = /16 + Div16 = 0x3, + }; + + pub const PLLSRC = enum(u1) { + /// HSI clock selected as PLL and PLLI2S clock entry + HSI = 0x0, + /// HSE oscillator clock selected as PLL and PLLI2S clock entry + HSE = 0x1, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, _, }; - pub const VOS = enum(u2) { - /// Range 1 - Range1 = 0x1, - /// Range 2 - Range2 = 0x2, + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, + }; + + pub const SAISEL = enum(u2) { + /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + PLLSAI1_Q = 0x0, + /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + PLLI2S1_Q = 0x1, + /// SAI2 clock frequency = Alternate function input frequency + AFIF = 0x2, + /// SAI2 clock frequency = HSI or HSE + HSI_HSE = 0x3, + }; + + pub const SDMMCSEL = enum(u1) { + /// 48 MHz clock is selected as SD clock + CLK48 = 0x0, + /// System clock is selected as SD clock + SYS = 0x1, + }; + + pub const SPREADSEL = enum(u1) { + /// Center spread + Center = 0x0, + /// Down spread + Down = 0x1, + }; + + pub const SW = enum(u2) { + /// HSI oscillator used as system clock + HSI = 0x0, + /// HSE oscillator used as system clock + HSE = 0x1, + /// PLL used as system clock + PLL1_P = 0x2, _, }; - /// PWR register block - pub const PWR = extern struct { - /// Power control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection These bits select the low-power mode entered when CPU enters the deepsleep mode. 1xx: Shutdown mode Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2. Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. - LPMS: packed union { - raw: u3, - value: LPMS, + pub const TIMPRE = enum(u1) { + /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx + Mul2 = 0x0, + /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx + Mul4 = 0x1, + }; + + pub const USART1SEL = enum(u2) { + /// APB2 clock (PCLK2) is selected as USART clock + PCLK2 = 0x0, + /// System clock is selected as USART clock + SYS = 0x1, + /// HSI clock is selected as USART clock + HSI = 0x2, + /// LSE clock is selected as USART clock + LSE = 0x3, + }; + + pub const USART2SEL = enum(u2) { + /// APB1 clock (PCLK1) is selected as USART clock + PCLK1 = 0x0, + /// System clock is selected as USART clock + SYS = 0x1, + /// HSI clock is selected as USART clock + HSI = 0x2, + /// LSE clock is selected as USART clock + LSE = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal high-speed clock enable + HSION: u1, + /// Internal high-speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal high-speed clock trimming + HSITRIM: u5, + /// Internal high-speed clock calibration + HSICAL: u8, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + /// Clock security system enable + CSSON: u1, + reserved24: u4, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + /// PLLI2S enable + PLLI2SON: u1, + /// PLLI2S clock ready flag + PLLI2SRDY: u1, + /// PLLSAI enable + PLLSAION: u1, + /// PLLSAI clock ready flag + PLLSAIRDY: u1, + padding: u2, + }), + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// Division factor for the PLL and audio PLL (PLLI2S) input clock + PLLM: packed union { + raw: u6, + value: PLLM, }, - /// Flash memory powered down during Stop mode. This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode. - FPD_STOP: u1, - /// Flash memory powered down during Low-power run mode. This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode. - FPD_LPRUN: u1, - /// Flash memory powered down during Low-power sleep mode. This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode. - FPD_LPSLP: u1, - reserved8: u2, - /// Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. - DBP: u1, - /// Voltage scaling range selection - VOS: packed union { + /// PLL multiplication factor for VCO + PLLN: packed union { + raw: u9, + value: PLLN, + }, + reserved16: u1, + /// PLL division factor for main system clock + PLLP: packed union { raw: u2, - value: VOS, + value: PLLP, }, - reserved14: u3, - /// Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead. - LPR: u1, - padding: u17, - }), - /// Power control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Programmable voltage detector enable Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: This bit is reset only by a system reset. - PVDE: u1, - /// Programmable voltage detector level selection. These bits select the voltage threshold detected by the programmable voltage detector: Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: These bits are reset only by a system reset. - PLS: packed union { + reserved22: u4, + /// PLL and audio PLL (PLLI2S, PLLSAI) entry clock source + PLLSRC: packed union { + raw: u1, + value: PLLSRC, + }, + reserved24: u1, + /// PLL division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ: packed union { + raw: u4, + value: PLLQ, + }, + /// PLL division factor for DSI clock + PLLR: packed union { raw: u3, - value: PLS, + value: PLLR, }, - /// Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.21V - PVME1: u1, - /// Peripheral voltage monitoring 3 enable: VDDA vs. 1.621V - PVME3: u1, - /// Peripheral voltage monitoring 4 enable: VDDA vs. 1.861V - PVME4: u1, - reserved10: u3, - /// VDDUSB USB supply valid This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB FS peripheral. If VDDUSB is not always present in the application, the PVM can be used to determine whether this supply is ready or not. - USV: u1, - padding: u21, - }), - /// Power control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wake-up pin WKUP1 When this bit is set, the external wake-up pin WKUP1 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register. - EWUP1: u1, - /// Enable Wake-up pin WKUP2 When this bit is set, the external wake-up pin WKUP2 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register. - EWUP2: u1, - /// Enable Wake-up pin WKUP3 When this bit is set, the external wake-up pin WKUP3 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register. - EWUP3: u1, - /// Enable Wake-up pin WKUP4 When this bit is set, the external wake-up pin WKUP4 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. - EWUP4: u1, - /// Enable Wake-up pin WKUP5 When this bit is set, the external wake-up pin WKUP5 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register. - EWUP5: u1, - reserved6: u1, - /// Enable Wake-up pin WKUP7. When this bit is set, the external wake-up pin WKUP7 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP7 bit in the PWR_CR4 register. - EWUP7: u1, - reserved8: u1, - /// SRAM2 retention in Standby mode - RRS: u1, - /// Enable ULP sampling When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases is not detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes. - ENULP: u1, - /// Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os are in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during RUN mode. - APC: u1, - reserved15: u4, - /// Enable internal wake-up line - EIWUL: u1, - padding: u16, - }), - /// Power control register 4 - CR4: mmio.Mmio(packed struct(u32) { - /// Wake-up pin WKUP1 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP1 - WP1: u1, - /// Wake-up pin WKUP2 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 - WP2: u1, - /// Wake-up pin WKUP3 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 - WP3: u1, - /// Wake-up pin WKUP4 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 - WP4: u1, - /// Wake-up pin WKUP5 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 - WP5: u1, - reserved6: u1, - /// Wake-up pin WKUP7 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP7 - WP7: u1, - reserved8: u1, - /// VBAT battery charging enable - VBE: u1, - /// VBAT battery charging resistor selection - VBRS: u1, - padding: u22, + padding: u1, }), - /// Power status register 1 - SR1: mmio.Mmio(packed struct(u32) { - /// Wake-up flag 1 This bit is set when a wake-up event is detected on wake-up pin, WKUP1. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register. - WUF1: u1, - /// Wake-up flag 2 This bit is set when a wake-up event is detected on wake-up pin, WKUP2. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register. - WUF2: u1, - /// Wake-up flag 3 This bit is set when a wake-up event is detected on wake-up pin, WKUP3. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register. - WUF3: u1, - /// Wake-up flag 4 This bit is set when a wake-up event is detected on wake-up pin,WKUP4. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register. - WUF4: u1, - /// Wake-up flag 5 This bit is set when a wake-up event is detected on wake-up pin, WKUP5. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register. - WUF5: u1, - reserved6: u1, - /// Wake-up flag 7 This bit is set when a wake-up event is detected on wake-up pin, WKUP7. It is cleared by writing 1 in the CWUF7 bit of the PWR_SCR register. - WUF7: u1, - reserved8: u1, - /// Standby flag This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. - SBF: u1, - /// Stop Flags These bits are set by hardware when the device enters any stop mode and are cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. - STOPF: packed union { + /// clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u2, + value: SW, + }, + /// System clock switch status + SWS: packed union { + raw: u2, + value: SW, + }, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + reserved10: u2, + /// APB Low speed prescaler (APB1) + PPRE1: packed union { raw: u3, - value: STOPF, + value: PPRE, + }, + /// APB high-speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + /// HSE division factor for RTC clock + RTCPRE: u5, + /// Microcontroller clock output 1 + MCO1SEL: packed union { + raw: u2, + value: MCO1SEL, + }, + /// I2S clock selection + I2SSRC: packed union { + raw: u1, + value: ISSRC, + }, + /// MCO1 prescaler + MCO1PRE: packed union { + raw: u3, + value: MCOPRE, + }, + /// MCO2 prescaler + MCO2PRE: packed union { + raw: u3, + value: MCOPRE, + }, + /// Microcontroller clock output 2 + MCO2SEL: packed union { + raw: u2, + value: MCO2SEL, }, - reserved15: u3, - /// Wake-up flag internal This bit is set when a wake-up is detected on the internal wake-up line. It is cleared when all internal wake-up sources are cleared. - WUFI: u1, - padding: u16, - }), - /// Power status register 2 - SR2: mmio.Mmio(packed struct(u32) { - reserved7: u7, - /// Flash ready flag This bit is set by hardware to indicate when the flash memory is readey to be accessed after wake-up from power-down. To place the flash memory in power-down, set either FPD_LPRUN, FPD_LPSLP or FPD_STP bits. Note : If the system boots from SRAM, the user application must wait until the FLASH_RDY bit is set, prior to jumping to flash memory. - FLASH_RDY: u1, - /// Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wake-up from Standby mode time may be increased. - REGLPS: u1, - /// Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready. - REGLPF: u1, - /// Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. - VOSF: u1, - /// Programmable voltage detector output - PVDO: u1, - /// Peripheral voltage monitoring output: VDDUSB vs. 1.2 V Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wake-up time. - PVMO1: u1, - reserved14: u1, - /// Peripheral voltage monitoring output: VDDA vs. 1.621V Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wake-up time. - PVMO3: u1, - /// Peripheral voltage monitoring output: VDDA vs. 2.21V Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wake-up time. - PVMO4: u1, - padding: u16, - }), - /// Power status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear wake-up flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register. - CWUF1: u1, - /// Clear wake-up flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register. - CWUF2: u1, - /// Clear wake-up flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register. - CWUF3: u1, - /// Clear wake-up flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register. - CWUF4: u1, - /// Clear wake-up flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register. - CWUF5: u1, - reserved6: u1, - /// Clear wake-up flag 7 Setting this bit clears the WUF7 flag in the PWR_SR1 register. - CWUF7: u1, - reserved8: u1, - /// Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register. - CSBF: u1, - padding: u23, }), - reserved32: [4]u8, - /// Power Port A pull-up control register - PUCRA: mmio.Mmio(packed struct(u32) { - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU0: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU1: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU2: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU3: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU4: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU5: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU6: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU7: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU8: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU9: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU10: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU11: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU12: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU13: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU14: u1, - /// Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU15: u1, - padding: u16, - }), - /// Power Port A pull-down control register - PDCRA: mmio.Mmio(packed struct(u32) { - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD0: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD1: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD2: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD3: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD4: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD5: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD6: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD7: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD8: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD9: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD10: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD11: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD12: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD13: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD14: u1, - /// Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. - PD15: u1, - padding: u16, - }), - /// Power Port B pull-up control register - PUCRB: mmio.Mmio(packed struct(u32) { - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU0: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU1: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU2: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU3: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU4: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU5: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU6: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU7: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU8: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU9: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU10: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU11: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU12: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU13: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU14: u1, - /// Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. - PU15: u1, - padding: u16, - }), - /// Power Port B pull-down control register - PDCRB: mmio.Mmio(packed struct(u32) { - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD0: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD1: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD2: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD3: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD4: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD5: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD6: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD7: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD8: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD9: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD10: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD11: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD12: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD13: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD14: u1, - /// Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. - PD15: u1, - padding: u16, + /// clock interrupt register + CIR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// PLL ready interrupt flag + PLLRDYF: u1, + /// PLLI2S ready interrupt flag + PLLI2SRDYF: u1, + /// PLLSAI ready interrupt flag + PLLSAIRDYF: u1, + /// Clock security system interrupt flag + CSSF: u1, + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// PLL ready interrupt enable + PLLRDYIE: u1, + /// PLLI2S ready interrupt enable + PLLI2SRDYIE: u1, + /// PLLSAI Ready Interrupt Enable + PLLSAIRDYIE: u1, + reserved16: u1, + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// Main PLL(PLL) ready interrupt clear + PLLRDYC: u1, + /// PLLI2S ready interrupt clear + PLLI2SRDYC: u1, + /// PLLSAI Ready Interrupt Clear + PLLSAIRDYC: u1, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, }), - /// Power Port C pull-up control register - PUCRC: mmio.Mmio(packed struct(u32) { - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU0: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU1: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU2: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU3: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU4: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU5: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU6: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU7: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU8: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU9: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU10: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU11: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU12: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU13: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU14: u1, - /// Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU15: u1, - padding: u16, + /// AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// IO port H reset + GPIOHRST: u1, + /// IO port I reset + GPIOIRST: u1, + /// IO port J reset + GPIOJRST: u1, + /// IO port K reset + GPIOKRST: u1, + reserved12: u1, + /// CRC reset + CRCRST: u1, + reserved21: u8, + /// DMA2 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + /// DMA2D reset + DMA2DRST: u1, + reserved25: u1, + /// Ethernet MAC reset + ETHRST: u1, + reserved29: u3, + /// USB OTG HS module reset + USB_OTG_HSRST: u1, + padding: u2, }), - /// Power Port C pull-down control register - PDCRC: mmio.Mmio(packed struct(u32) { - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD0: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD1: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD2: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD3: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD4: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD5: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD6: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD7: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD8: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD9: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD10: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD11: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD12: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD13: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD14: u1, - /// Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. - PD15: u1, - padding: u16, + /// AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// Camera interface reset + DCMIRST: u1, + reserved4: u3, + /// AES module reset + AESRST: u1, + /// Hash module reset + HSAHRST: u1, + /// Random number generator module reset + RNGRST: u1, + /// USB OTG FS module reset + USB_OTG_FSRST: u1, + padding: u24, }), - /// Power Port D pull-up control register - PUCRD: mmio.Mmio(packed struct(u32) { - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU0: u1, - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU1: u1, - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU2: u1, - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU3: u1, - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU4: u1, - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU5: u1, - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU6: u1, - reserved8: u1, - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU8: u1, - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU9: u1, - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU10: u1, - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU11: u1, - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU12: u1, - /// Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU13: u1, - padding: u18, + /// AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller module reset + FMCRST: u1, + /// Quad SPI memory controller reset + QUADSPIRST: u1, + padding: u30, }), - /// Power Port D pull-down control register - PDCRD: mmio.Mmio(packed struct(u32) { - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD0: u1, - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD1: u1, - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD2: u1, - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD3: u1, - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD4: u1, - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD5: u1, - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD6: u1, - reserved8: u1, - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD8: u1, - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD9: u1, - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD10: u1, - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD11: u1, - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD12: u1, - /// Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. - PD13: u1, - padding: u18, + reserved32: [4]u8, + /// APB1 peripheral reset register + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// TIM2 reset + TIM2RST: u1, + /// TIM3 reset + TIM3RST: u1, + /// TIM4 reset + TIM4RST: u1, + /// TIM5 reset + TIM5RST: u1, + /// TIM6 reset + TIM6RST: u1, + /// TIM7 reset + TIM7RST: u1, + /// TIM12 reset + TIM12RST: u1, + /// TIM13 reset + TIM13RST: u1, + /// TIM14 reset + TIM14RST: u1, + /// Low power timer 1 reset + LPTIM1RST: u1, + reserved11: u1, + /// Window watchdog reset + WWDGRST: u1, + reserved13: u1, + /// CAN 3 reset + CAN3RST: u1, + /// SPI 2 reset + SPI2RST: u1, + /// SPI 3 reset + SPI3RST: u1, + /// SPDIF-RX reset + SPDIFRXRST: u1, + /// USART 2 reset + USART2RST: u1, + /// USART 3 reset + USART3RST: u1, + /// USART 4 reset + UART4RST: u1, + /// USART 5 reset + UART5RST: u1, + /// I2C 1 reset + I2C1RST: u1, + /// I2C 2 reset + I2C2RST: u1, + /// I2C3 reset + I2C3RST: u1, + /// I2C 4 reset + I2C4RST: u1, + /// CAN1 reset + CAN1RST: u1, + /// CAN2 reset + CAN2RST: u1, + /// HDMI-CEC reset + CECRST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC reset + DACRST: u1, + /// UART7 reset + UART7RST: u1, + /// UART8 reset + UART8RST: u1, }), - /// Power Port E pull-up control register - PUCRE: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Port E pull-up bit 3 When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU3: u1, - reserved7: u3, - /// Port E pull-up bit y When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU7: u1, - /// Port E pull-up bit y When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU8: u1, - /// Port E pull-up bit y When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU9: u1, - padding: u22, + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// TIM1 reset + TIM1RST: u1, + /// TIM8 reset + TIM8RST: u1, + reserved4: u2, + /// USART1 reset + USART1RST: u1, + /// USART6 reset + USART6RST: u1, + reserved7: u1, + /// SDMMC2 reset + SDMMC2RST: u1, + /// ADC interface reset (common to all ADCs) + ADCRST: u1, + reserved11: u2, + /// SDMMC1 reset + SDMMC1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + /// SPI4 reset + SPI4RST: u1, + /// System configuration controller reset + SYSCFGRST: u1, + reserved16: u1, + /// TIM9 reset + TIM9RST: u1, + /// TIM10 reset + TIM10RST: u1, + /// TIM11 reset + TIM11RST: u1, + reserved20: u1, + /// SPI5 reset + SPI5RST: u1, + /// SPI6 reset + SPI6RST: u1, + /// SAI1 reset + SAI1RST: u1, + /// SAI2 reset + SAI2RST: u1, + reserved26: u2, + /// LTDC reset + LTDCRST: u1, + /// DSI reset + DSIRST: u1, + reserved29: u1, + /// DFSDM 1 reset + DFSDM1RST: u1, + /// MDIOS reset + MDIOSRST: u1, + /// USB OTG HS PHY controller reset + USBPHYCRST: u1, }), - /// Power Port E pull-down control register - PDCRE: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Port E pull-down bit 3 When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. - PD3: u1, - reserved7: u3, - /// Port E pull-down bit y When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. - PD7: u1, - /// Port E pull-down bit y When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. - PD8: u1, - /// Port E pull-down bit y When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. - PD9: u1, - padding: u22, + reserved48: [8]u8, + /// AHB1 peripheral clock register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// IO port H clock enable + GPIOHEN: u1, + /// IO port I clock enable + GPIOIEN: u1, + /// IO port J clock enable + GPIOJEN: u1, + /// IO port K clock enable + GPIOKEN: u1, + reserved12: u1, + /// CRC clock enable + CRCEN: u1, + reserved18: u5, + /// Backup SRAM interface clock enable + BKPSRAMEN: u1, + reserved20: u1, + /// CCM data RAM clock enable + DTCMRAMEN: u1, + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// DMA2D clock enable + DMA2DEN: u1, + reserved25: u1, + /// Ethernet MAC clock enable + ETHEN: u1, + /// Ethernet Transmission clock enable + ETHTXEN: u1, + /// Ethernet Reception clock enable + ETHRXEN: u1, + /// Ethernet PTP clock enable + ETHPTPEN: u1, + /// USB OTG HS clock enable + USB_OTG_HSEN: u1, + /// USB OTG HSULPI clock enable + USB_OTG_HSULPIEN: u1, + padding: u1, }), - /// Power Port F pull-up control register - PUCRF: mmio.Mmio(packed struct(u32) { - /// Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU0: u1, - /// Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU1: u1, - /// Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU2: u1, - /// Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. - PU3: u1, - padding: u28, + /// AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// Camera interface enable + DCMIEN: u1, + /// JPEG enable + JPEGEN: u1, + reserved4: u2, + /// AES module clock enable + AESEN: u1, + /// Hash modules clock enable + HASHEN: u1, + /// Random number generator clock enable + RNGEN: u1, + /// USB OTG FS clock enable + USB_OTG_FSEN: u1, + padding: u24, }), - /// Power Port F pull-down control register - PDCRF: mmio.Mmio(packed struct(u32) { - /// Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. - PD0: u1, - /// Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. - PD1: u1, - /// Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. - PD2: u1, - /// Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. - PD3: u1, - padding: u28, + /// AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller module clock enable + FMCEN: u1, + /// Quad SPI memory controller clock enable + QUADSPIEN: u1, + padding: u30, }), - }; - }; - - pub const can_fdcan_v1 = struct { - pub const ACT = enum(u2) { - /// Synchronizing: node is synchronizing on CAN communication. - SYNC = 0x0, - /// Idle: node is neither receiver nor transmitter. - IDLE = 0x1, - /// Receiver: node is operating as receiver. - RX = 0x2, - /// Transmitter: node is operating as transmitter. - TX = 0x3, - }; - - pub const ANFE = enum(u2) { - /// Accept in Rx FIFO 0 - ACCEPT_FIFO_0 = 0x0, - /// Accept in Rx FIFO 1 - ACCEPT_FIFO_1 = 0x1, - /// Reject - REJECT = 0x2, - _, - }; - - pub const ANFS = enum(u2) { - /// Accept in Rx FIFO 0 - ACCEPT_FIFO_0 = 0x0, - /// Accept in Rx FIFO 1 - ACCEPT_FIFO_1 = 0x1, - /// Reject - REJECT = 0x2, - _, - }; - - pub const LEC = enum(u3) { - /// No Error: No error occurred since LEC has been reset by successful reception or transmission. - NO_ERROR = 0x0, - /// Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. - STUFF = 0x1, - /// Form Error: A fixed format part of a received frame has the wrong format. - FORM = 0x2, - /// AckError: The message transmitted by the FDCAN was not acknowledged by another node. - ACK = 0x3, - /// Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant. - BIT_1 = 0x4, - /// Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). - BIT_0 = 0x5, - /// CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. - CRC = 0x6, - /// NoChange: Any read access to the Protocol status register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol status register. - NO_CHANGE = 0x7, - }; - - pub const MSI = enum(u2) { - /// No FIFO selected - NO_FIFO = 0x0, - /// FIFO overrun - OVERRUN = 0x1, - /// Message stored in FIFO 0 - FIFO_0 = 0x2, - /// Message stored in FIFO 1 - FIFO_1 = 0x3, - }; - - pub const PDIV = enum(u4) { - /// Divide by 1 - DIV_1 = 0x0, - /// Divide by 2 - DIV_2 = 0x1, - /// Divide by 4 - DIV_4 = 0x2, - /// Divide by 6 - DIV_6 = 0x3, - /// Divide by 8 - DIV_8 = 0x4, - /// Divide by 10 - DIV_10 = 0x5, - /// Divide by 12 - DIV_12 = 0x6, - /// Divide by 14 - DIV_14 = 0x7, - /// Divide by 16 - DIV_16 = 0x8, - /// Divide by 18 - DIV_18 = 0x9, - /// Divide by 20 - DIV_20 = 0xa, - /// Divide by 22 - DIV_22 = 0xb, - /// Divide by 24 - DIV_24 = 0xc, - /// Divide by 26 - DIV_26 = 0xd, - /// Divide by 28 - DIV_28 = 0xe, - /// Divide by 30 - DIV_30 = 0xf, - }; - - pub const TFQM = enum(u1) { - /// Tx FIFO operation - FIFO = 0x0, - /// Tx queue operation - QUEUE = 0x1, - }; - - pub const TOS = enum(u2) { - /// Continuous operation - CONTINUOUS = 0x0, - /// Timeout controlled by Tx event FIFO - TX_EVENT_FIFO = 0x1, - /// Timeout controlled by Rx FIFO 0 - RX_FIFO_0 = 0x2, - /// Timeout controlled by Rx FIFO 1 - RX_FIFO_1 = 0x3, - }; - - pub const TSS = enum(u2) { - /// Timestamp counter value always 0x0000 - ZERO = 0x0, - /// Timestamp counter value incremented according to TCP - INCREMENT = 0x1, - /// External timestamp counter from TIM3 value (tim3_cnt[0:15]) - EXTERNAL = 0x2, - _, - }; - - pub const TX = enum(u2) { - /// Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time - RESET = 0x0, - /// Sample point can be monitored at pin FDCANx_TX - SAMPLE_POINT = 0x1, - /// Dominant (0) level at pin FDCANx_TX - DOMINANT = 0x2, - /// Recessive (1) at pin FDCANx_TX - RECESSIVE = 0x3, - }; - - /// Controller area network with flexible data rate (FD) - pub const FDCAN = extern struct { - /// FDCAN core release register - CREL: mmio.Mmio(packed struct(u32) { - /// DAY - DAY: u8, - /// MON - MON: u8, - /// YEAR - YEAR: u4, - /// SUBSTEP - SUBSTEP: u4, - /// STEP - STEP: u4, - /// REL - REL: u4, + reserved64: [4]u8, + /// APB1 peripheral clock enable register + APB1ENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable + TIM2EN: u1, + /// TIM3 clock enable + TIM3EN: u1, + /// TIM4 clock enable + TIM4EN: u1, + /// TIM5 clock enable + TIM5EN: u1, + /// TIM6 clock enable + TIM6EN: u1, + /// TIM7 clock enable + TIM7EN: u1, + /// TIM12 clock enable + TIM12EN: u1, + /// TIM13 clock enable + TIM13EN: u1, + /// TIM14 clock enable + TIM14EN: u1, + /// Low power timer 1 clock enable + LPTIM1EN: u1, + /// RTCAPB clock enable + RTCEN: u1, + /// Window watchdog clock enable + WWDGEN: u1, + reserved13: u1, + /// CAN 3 enable + CAN3EN: u1, + /// SPI2 clock enable + SPI2EN: u1, + /// SPI3 clock enable + SPI3EN: u1, + /// SPDIF-RX clock enable + SPDIFRXEN: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// I2C3 clock enable + I2C3EN: u1, + /// I2C4 clock enable + I2C4EN: u1, + /// CAN 1 clock enable + CAN1EN: u1, + /// CAN 2 clock enable + CAN2EN: u1, + /// HDMI-CEN clock enable + CECEN: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// UART7 clock enable + UART7EN: u1, + /// UART8 clock enable + UART8EN: u1, }), - /// FDCAN endian register - ENDN: mmio.Mmio(packed struct(u32) { - /// Endianness test value. The endianness test value is 0x8765 4321 - ETV: u32, + /// APB2 peripheral clock enable register + APB2ENR: mmio.Mmio(packed struct(u32) { + /// TIM1 clock enable + TIM1EN: u1, + /// TIM8 clock enable + TIM8EN: u1, + reserved4: u2, + /// USART1 clock enable + USART1EN: u1, + /// USART6 clock enable + USART6EN: u1, + reserved7: u1, + /// SDMMC2 clock enable + SDMMC2EN: u1, + /// ADC1 clock enable + ADC1EN: u1, + /// ADC2 clock enable + ADC2EN: u1, + /// ADC3 clock enable + ADC3EN: u1, + /// SDMMC1 clock enable + SDMMC1EN: u1, + /// SPI1 clock enable + SPI1EN: u1, + /// SPI4 clock enable + SPI4EN: u1, + /// System configuration controller clock enable + SYSCFGEN: u1, + reserved16: u1, + /// TIM9 clock enable + TIM9EN: u1, + /// TIM10 clock enable + TIM10EN: u1, + /// TIM11 clock enable + TIM11EN: u1, + reserved20: u1, + /// SPI5 clock enable + SPI5EN: u1, + /// SPI6 clock enable + SPI6EN: u1, + /// SAI1 clock enable + SAI1EN: u1, + /// SAI2 clock enable + SAI2EN: u1, + reserved26: u2, + /// LTDC clock enable + LTDCEN: u1, + /// DSI clock enable + DSIEN: u1, + reserved29: u1, + /// DFSDM1 clock enable + DFSDM1EN: u1, + /// MDIO clock enable + MDIOSEN: u1, + /// USB OTG HS PHY controller clock enable + USBPHYCEN: u1, }), - reserved12: [4]u8, - /// FDCAN data bit timing and prescaler register - DBTP: mmio.Mmio(packed struct(u32) { - /// Synchronization jump width. Must always be smaller than DTSEG2, valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1: tSJW = (DSJW + 1) x tq. - DSJW: u4, - /// Data time segment after sample point. Valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS2 = (DTSEG2 + 1) x tq - DTSEG2: u4, - /// Data time segment before sample point. Valid values are 0 to 31. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS1 = (DTSEG1 + 1) x tq - DTSEG1: u5, - reserved16: u3, - /// Data bit rate prescaler. The value by which the oscillator frequency is divided to generate the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31. The hardware interpreters this value as the value programmed plus 1 - DBRP: u5, - reserved23: u2, - /// Transceiver delay compensation - TDC: u1, - padding: u8, + reserved80: [8]u8, + /// AHB1 peripheral clock enable in low power mode register + AHB1LPENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable during sleep mode + GPIOALPEN: u1, + /// IO port B clock enable during Sleep mode + GPIOBLPEN: u1, + /// IO port C clock enable during Sleep mode + GPIOCLPEN: u1, + /// IO port D clock enable during Sleep mode + GPIODLPEN: u1, + /// IO port E clock enable during Sleep mode + GPIOELPEN: u1, + /// IO port F clock enable during Sleep mode + GPIOFLPEN: u1, + /// IO port G clock enable during Sleep mode + GPIOGLPEN: u1, + /// IO port H clock enable during Sleep mode + GPIOHLPEN: u1, + /// IO port I clock enable during Sleep mode + GPIOILPEN: u1, + /// IO port J clock enable during Sleep mode + GPIOJLPEN: u1, + /// IO port K clock enable during Sleep mode + GPIOKLPEN: u1, + reserved12: u1, + /// CRC clock enable during Sleep mode + CRCLPEN: u1, + /// AXI to AHB bridge clock enable during Sleep mode + AXILPEN: u1, + reserved15: u1, + /// Flash interface clock enable during Sleep mode + FLASHLPEN: u1, + /// SRAM 1interface clock enable during Sleep mode + SRAM1LPEN: u1, + /// SRAM 2 interface clock enable during Sleep mode + SRAM2LPEN: u1, + /// Backup SRAM interface clock enable during Sleep mode + BKPSRAMLPEN: u1, + /// SRAM 3 interface clock enable during Sleep mode + SRAM3LPEN: u1, + /// DTCM RAM interface clock enable during Sleep mode + DTCMLPEN: u1, + /// DMA1 clock enable during Sleep mode + DMA1LPEN: u1, + /// DMA2 clock enable during Sleep mode + DMA2LPEN: u1, + /// DMA2D clock enable during Sleep mode + DMA2DLPEN: u1, + reserved25: u1, + /// Ethernet MAC clock enable during Sleep mode + ETHLPEN: u1, + /// Ethernet transmission clock enable during Sleep mode + ETHTXLPEN: u1, + /// Ethernet reception clock enable during Sleep mode + ETHRXLPEN: u1, + /// Ethernet PTP clock enable during Sleep mode + ETHPTPLPEN: u1, + /// USB OTG HS clock enable during Sleep mode + USB_OTG_HSLPEN: u1, + /// USB OTG HS ULPI clock enable during Sleep mode + USB_OTG_HSULPILPEN: u1, + padding: u1, }), - /// FDCAN test register - TEST: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Loop back mode - LBCK: u1, - /// Control of transmit pin - TX: packed union { - raw: u2, - value: TX, - }, - /// Receive pin. Monitors the actual value of pin FDCANx_RX - RX: u1, + /// AHB2 peripheral clock enable in low power mode register + AHB2LPENR: mmio.Mmio(packed struct(u32) { + /// Camera interface enable during Sleep mode + DCMILPEN: u1, + /// JPEG module enabled during Sleep mode + JPEGLPEN: u1, + reserved4: u2, + /// AES module clock enable during Sleep mode + AESLPEN: u1, + /// Hash modules clock enable during Sleep mode + HASHLPEN: u1, + /// Random number generator clock enable during Sleep mode + RNGLPEN: u1, + /// USB OTG FS clock enable during Sleep mode + USB_OTG_FSLPEN: u1, padding: u24, }), - /// FDCAN RAM watchdog register - RWD: mmio.Mmio(packed struct(u32) { - /// Watchdog configuration. Start value of the message RAM watchdog counter. With the reset value of 00, the counter is disabled. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of FDCAN_CCCR register are set to 1 - WDC: u8, - /// Watchdog value. Actual message RAM watchdog counter value - WDV: u8, - padding: u16, + /// AHB3 peripheral clock enable in low power mode register + AHB3LPENR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller module clock enable during Sleep mode + FMCLPEN: u1, + /// Quand SPI memory controller clock enable during Sleep mode + QUADSPILPEN: u1, + padding: u30, }), - /// FDCAN CC control register - CCCR: mmio.Mmio(packed struct(u32) { - /// Initialization - INIT: u1, - /// Configuration change enable - CCE: u1, - /// ASM restricted operation mode. The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted operation Mode after it has received a valid frame. In the optional Restricted operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time - ASM: u1, - /// Clock stop acknowledge - CSA: u1, - /// Clock stop request - CSR: u1, - /// Bus monitoring mode. Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time - MON: u1, - /// Disable automatic retransmission - DAR: u1, - /// Test mode enable - TEST: u1, - /// FD operation enable - FDOE: u1, - /// FDCAN bit rate switching - BRSE: u1, - reserved12: u2, - /// Protocol exception handling disable - PXHD: u1, - /// Edge filtering during bus integration - EFBI: u1, - /// If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame - TXP: u1, - /// Non ISO operation. If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0 - NISO: u1, - padding: u16, + reserved96: [4]u8, + /// APB1 peripheral clock enable in low power mode register + APB1LPENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable during Sleep mode + TIM2LPEN: u1, + /// TIM3 clock enable during Sleep mode + TIM3LPEN: u1, + /// TIM4 clock enable during Sleep mode + TIM4LPEN: u1, + /// TIM5 clock enable during Sleep mode + TIM5LPEN: u1, + /// TIM6 clock enable during Sleep mode + TIM6LPEN: u1, + /// TIM7 clock enable during Sleep mode + TIM7LPEN: u1, + /// TIM12 clock enable during Sleep mode + TIM12LPEN: u1, + /// TIM13 clock enable during Sleep mode + TIM13LPEN: u1, + /// TIM14 clock enable during Sleep mode + TIM14LPEN: u1, + /// low power timer 1 clock enable during Sleep mode + LPTIM1LPEN: u1, + /// RTCAPB clock enable during Sleep mode + RTCLPEN: u1, + /// Window watchdog clock enable during Sleep mode + WWDGLPEN: u1, + reserved13: u1, + /// CAN 3 clock enable during Sleep mode + CAN3LPEN: u1, + /// SPI2 clock enable during Sleep mode + SPI2LPEN: u1, + /// SPI3 clock enable during Sleep mode + SPI3LPEN: u1, + /// SPDIF-RX clock enable during sleep mode + SPDIFRXLPEN: u1, + /// USART2 clock enable during Sleep mode + USART2LPEN: u1, + /// USART3 clock enable during Sleep mode + USART3LPEN: u1, + /// UART4 clock enable during Sleep mode + UART4LPEN: u1, + /// UART5 clock enable during Sleep mode + UART5LPEN: u1, + /// I2C1 clock enable during Sleep mode + I2C1LPEN: u1, + /// I2C2 clock enable during Sleep mode + I2C2LPEN: u1, + /// I2C3 clock enable during Sleep mode + I2C3LPEN: u1, + /// I2C4 clock enable during Sleep mode + I2C4LPEN: u1, + /// CAN 1 clock enable during Sleep mode + CAN1LPEN: u1, + /// CAN 2 clock enable during Sleep mode + CAN2LPEN: u1, + /// HDMI-CEN clock enable during Sleep mode + CECLPEN: u1, + /// Power interface clock enable during Sleep mode + PWRLPEN: u1, + /// DAC interface clock enable during Sleep mode + DACLPEN: u1, + /// UART7 clock enable during Sleep mode + UART7LPEN: u1, + /// UART8 clock enable during Sleep mode + UART8LPEN: u1, }), - /// FDCAN nominal bit timing and prescaler register - NBTP: mmio.Mmio(packed struct(u32) { - /// Nominal time segment after sample point. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used - NTSEG2: u7, - reserved8: u1, - /// Nominal time segment before sample point. Valid values are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - NTSEG1: u8, - /// Bit rate prescaler. Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - NBRP: u9, - /// Nominal (re)synchronization jump width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - NSJW: u7, + /// APB2 peripheral clock enabled in low power mode register + APB2LPENR: mmio.Mmio(packed struct(u32) { + /// TIM1 clock enable during Sleep mode + TIM1LPEN: u1, + /// TIM8 clock enable during Sleep mode + TIM8LPEN: u1, + reserved4: u2, + /// USART1 clock enable during Sleep mode + USART1LPEN: u1, + /// USART6 clock enable during Sleep mode + USART6LPEN: u1, + reserved7: u1, + /// SDMMC2 clock enable during Sleep mode + SDMMC2LPEN: u1, + /// ADC1 clock enable during Sleep mode + ADC1LPEN: u1, + /// ADC2 clock enable during Sleep mode + ADC2LPEN: u1, + /// ADC 3 clock enable during Sleep mode + ADC3LPEN: u1, + /// SDMMC1 clock enable during Sleep mode + SDMMC1LPEN: u1, + /// SPI 1 clock enable during Sleep mode + SPI1LPEN: u1, + /// SPI 4 clock enable during Sleep mode + SPI4LPEN: u1, + /// System configuration controller clock enable during Sleep mode + SYSCFGLPEN: u1, + reserved16: u1, + /// TIM9 clock enable during sleep mode + TIM9LPEN: u1, + /// TIM10 clock enable during Sleep mode + TIM10LPEN: u1, + /// TIM11 clock enable during Sleep mode + TIM11LPEN: u1, + reserved20: u1, + /// SPI 5 clock enable during Sleep mode + SPI5LPEN: u1, + /// SPI 6 clock enable during Sleep mode + SPI6LPEN: u1, + /// SAI1 clock enable during sleep mode + SAI1LPEN: u1, + /// SAI2 clock enable during sleep mode + SAI2LPEN: u1, + reserved26: u2, + /// LTDC clock enable during sleep mode + LTDCLPEN: u1, + /// DSI clock enable during Sleep mode + DSILPEN: u1, + reserved29: u1, + /// DFSDM1 clock enable during Sleep mode + DFSDM1LPEN: u1, + /// MDIO clock enable during Sleep mode + MDIOSLPEN: u1, + padding: u1, }), - /// FDCAN timestamp counter configuration register - TSCC: mmio.Mmio(packed struct(u32) { - /// Timestamp select. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - TSS: packed union { + reserved112: [8]u8, + /// Backup domain control register + BDCR: mmio.Mmio(packed struct(u32) { + /// External low-speed oscillator enable + LSEON: u1, + /// External low-speed oscillator ready + LSERDY: u1, + /// External low-speed oscillator bypass + LSEBYP: u1, + /// LSE oscillator drive capability + LSEDRV: packed union { raw: u2, - value: TSS, + value: LSEDRV, }, - reserved16: u14, - /// Timestamp counter prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1 … 16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. In CAN FD mode the internal timestamp counter TCP does not provide a constant time base due to the different CAN bit times between arbitration phase and data phase. Thus CAN FD requires an external counter for timestamp generation (TSS = 10). These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - TCP: u4, - padding: u12, - }), - /// FDCAN timestamp counter value register - TSCV: mmio.Mmio(packed struct(u32) { - /// Timestamp counter. The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). When TSCC[TSS] = 01, the timestamp counter is incremented in multiples of CAN bit times [1 … 16] depending on the configuration of TSCC[TCP]. A wrap around sets interrupt flag IR[TSW]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access has no impact - TSC: u16, - padding: u16, - }), - /// FDCAN timeout counter configuration register - TOCC: mmio.Mmio(packed struct(u32) { - /// Timeout counter enable. This is a protected write (P) bit, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - ETOC: u1, - /// Timeout select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - TOS: packed union { + reserved8: u3, + /// RTC clock source selection + RTCSEL: packed union { raw: u2, - value: TOS, + value: RTCSEL, }, - reserved16: u13, - /// Timeout period. Start value of the timeout counter (down-counter). Configures the timeout period - TOP: u16, - }), - /// FDCAN timeout counter value register - TOCV: mmio.Mmio(packed struct(u32) { - /// Timeout counter. The timeout counter is decremented in multiples of CAN bit times [1 … 16] depending on the configuration of TSCC.TCP. When decremented to 0, interrupt flag IR.TOO is set and the timeout counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS - TOC: u16, - padding: u16, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, }), - reserved64: [16]u8, - /// FDCAN error counter register - ECR: mmio.Mmio(packed struct(u32) { - /// Transmit error counter. Actual state of the transmit error counter, values between 0 and 255. When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented - TEC: u8, - /// Receive error counter. Actual state of the receive error counter, values between 0 and 127 - REC: u7, - /// Receive error passive - RP: u1, - /// CAN error logging. The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. Access type is RX: reset on read. - CEL: u8, - padding: u8, + /// clock control & status register + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low-speed oscillator enable + LSION: u1, + /// Internal low-speed oscillator ready + LSIRDY: u1, + reserved24: u22, + /// Remove reset flag + RMVF: u1, + /// BOR reset flag + BORRSTF: u1, + /// PIN reset flag + PADRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + WDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, }), - /// FDCAN protocol status register - PSR: mmio.Mmio(packed struct(u32) { - /// Last error code. The LEC indicates the type of the last error to occur on the CAN bus. This field is cleared to 0 when a message has been transferred (reception or transmission) without error. Access type is RS: set on read. - LEC: packed union { - raw: u3, - value: LEC, + reserved128: [8]u8, + /// spread spectrum clock generation register + SSCGR: mmio.Mmio(packed struct(u32) { + /// Modulation period + MODPER: u13, + /// Incrementation step + INCSTEP: u15, + reserved30: u2, + /// Spread Select + SPREADSEL: packed union { + raw: u1, + value: SPREADSEL, }, - /// Activity. Monitors the module’s CAN communication state - ACT: packed union { - raw: u2, - value: ACT, + /// Spread spectrum modulation enable + SSCGEN: u1, + }), + /// PLLI2S configuration register + PLLI2SCFGR: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// PLL multiplication factor for VCO + PLLN: packed union { + raw: u9, + value: PLLN, }, - /// Error passive - EP: u1, - /// Warning Sstatus - EW: u1, - /// Bus_Off status - BO: u1, - /// Data last error code. Type of last error that occurred in the data phase of a FDCAN format frame with its BRS flag set. Coding is the same as for LEC. This field is cleared to 0 when a FDCAN format frame with its BRS flag set has been transferred (reception or transmission) without error. Access type is RS: set on read. - DLEC: u3, - /// ESI flag of last received FDCAN message. This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read. - RESI: u1, - /// BRS flag of last received FDCAN message. This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read. - RBRS: u1, - /// Received FDCAN message. This bit is set independent of acceptance filtering. Access type is RX: reset on read. - REDL: u1, - /// Protocol exception event - PXE: u1, reserved16: u1, - /// Transmitter delay compensation value. Position of the secondary sample point, defined by the sum of the measured delay from FDCAN_TX to FDCAN_RX and TDCR.TDCO. The SSP position is, in the data phase, the number of minimum time quanta (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq - TDCV: u7, - padding: u9, - }), - /// FDCAN transmitter delay compensation register - TDCR: mmio.Mmio(packed struct(u32) { - /// Transmitter delay compensation filter window length. Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would result in an earlier SSP position are ignored for transmitter delay measurements. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - TDCF: u7, - reserved8: u1, - /// Transmitter delay compensation offset. Offset value defining the distance between the measured delay from FDCAN_TX to FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - TDCO: u7, - padding: u17, - }), - reserved80: [4]u8, - /// FDCAN interrupt register - IR: mmio.Mmio(packed struct(u32) { - /// Rx FIFO X new message - RFN: u1, - /// Rx FIFO X full - RFF: u1, - /// Rx FIFO X message lost - RFL: u1, - reserved6: u3, - /// High-priority message - HPM: u1, - /// Transmission completed - TC: u1, - /// Transmission cancellation finished - TCF: u1, - /// Tx FIFO empty - TFE: u1, - /// Tx event FIFO New Entry - TEFN: u1, - /// Tx event FIFO full - TEFF: u1, - /// Tx event FIFO element lost - TEFL: u1, - /// Timestamp wraparound - TSW: u1, - /// Message RAM access failure. The flag is set when the Rx handler: has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx handler starts processing of the following message. was unable to write a message to the message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated. The partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the FDCAN is switched into Restricted operation Mode (see mode). To leave Restricted operation Mode, the Host CPU has to reset CCCR.ASM. - MRAF: u1, - /// Timeout occurred - TOO: u1, - /// Error logging overflow - ELO: u1, - /// Error passive - EP: u1, - /// Warning status - EW: u1, - /// Bus_Off status - BO: u1, - /// Watchdog interrupt - WDI: u1, - /// Protocol error in arbitration phase (nominal bit time is used) - PEA: u1, - /// Protocol error in data phase (data bit time is used) - PED: u1, - /// Access to reserved address - ARA: u1, - padding: u8, - }), - /// FDCAN interrupt enable register - IE: mmio.Mmio(packed struct(u32) { - /// Rx FIFO X new message interrupt enable - RFNE: u1, - /// Rx FIFO X full interrupt enable - RFFE: u1, - /// Rx FIFO X message lost interrupt enable - RFLE: u1, - reserved6: u3, - /// High-priority message interrupt enable - HPME: u1, - /// Transmission completed interrupt enable - TCE: u1, - /// Transmission cancellation finished interrupt enable - TCFE: u1, - /// Tx FIFO empty interrupt enable - TFEE: u1, - /// Tx event FIFO new entry interrupt enable - TEFNE: u1, - /// Tx event FIFO full interrupt enable - TEFFE: u1, - /// Tx event FIFO element lost interrupt enable - TEFLE: u1, - /// Timestamp wraparound interrupt enable - TSWE: u1, - /// Message RAM access failure interrupt enable - MRAFE: u1, - /// Timeout occurred interrupt enable - TOOE: u1, - /// Error logging overflow interrupt enable - ELOE: u1, - /// Error passive interrupt enable - EPE: u1, - /// Warning status interrupt enable - EWE: u1, - /// Bus_Off status enable - BOE: u1, - /// Watchdog interrupt enable - WDIE: u1, - /// Protocol error in arbitration phase enable - PEAE: u1, - /// Protocol error in data phase enable - PEDE: u1, - /// Access to reserved address enable - ARAE: u1, - padding: u8, - }), - /// FDCAN interrupt line select register - ILS: mmio.Mmio(packed struct(u32) { - /// RX FIFO bit grouping the following interruption. RFLL: Rx FIFO X message lost interrupt line RFFL: Rx FIFO X full interrupt line RFNL: Rx FIFO X new message interrupt line. - RXFIFO: u1, - reserved2: u1, - /// Status message bit grouping the following interruption. TCFL: Transmission cancellation finished interrupt line TCL: Transmission completed interrupt line HPML: High-priority message interrupt line. - SMSG: u1, - /// Tx FIFO ERROR grouping the following interruption. TEFLL: Tx event FIFO element lost interrupt line TEFFL: Tx event FIFO full interrupt line TEFNL: Tx event FIFO new entry interrupt line TFEL: Tx FIFO empty interrupt line. - TFERR: u1, - /// Interrupt regrouping the following interruption. TOOL: Timeout occurred interrupt line MRAFL: Message RAM access failure interrupt line TSWL: Timestamp wraparound interrupt line. - MISC: u1, - /// Bit and line error grouping the following interruption. EPL Error passive interrupt line ELOL: Error logging overflow interrupt line. - BERR: u1, - /// Protocol error grouping the following interruption. ARAL: Access to reserved address line PEDL: Protocol error in data phase line PEAL: Protocol error in arbitration phase line WDIL: Watchdog interrupt line BOL: Bus_Off status EWL: Warning status interrupt line. - PERR: u1, - padding: u25, - }), - /// FDCAN interrupt line enable register - ILE: mmio.Mmio(packed struct(u32) { - /// Enable interrupt line 0 - EINT0: u1, - /// Enable interrupt line 1 - EINT1: u1, - padding: u30, - }), - reserved128: [32]u8, - /// FDCAN global filter configuration register - RXGFC: mmio.Mmio(packed struct(u32) { - /// Reject remote frames extended. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - RRFE: u1, - /// Reject remote frames standard. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - RRFS: u1, - /// Accept non-matching frames extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - ANFE: packed union { + /// PLL division factor for main system clock + PLLP: packed union { raw: u2, - value: ANFE, + value: PLLP, }, - /// Accept Non-matching frames standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - ANFS: packed union { - raw: u2, - value: ANFS, + reserved24: u6, + /// PLL division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ: packed union { + raw: u4, + value: PLLQ, }, - reserved8: u2, - /// FIFO 1 operation mode (overwrite or blocking). This is a protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - F1OM: u1, - /// FIFO 0 operation mode (overwrite or blocking). This is protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - F0OM: u1, - reserved16: u6, - /// List size standard. >28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. - LSS: u5, - reserved24: u3, - /// List size extended. >8: Values greater than 8 are interpreted as 8. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. - LSE: u4, - padding: u4, - }), - /// FDCAN extended ID and mask register - XIDAM: mmio.Mmio(packed struct(u32) { - /// Extended ID mask. For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - EIDM: u29, - padding: u3, - }), - /// FDCAN high-priority message status register - HPMS: mmio.Mmio(packed struct(u32) { - /// Buffer index. Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = 1 - BIDX: u3, - reserved6: u3, - /// Message storage indicator - MSI: packed union { - raw: u2, - value: MSI, + /// PLL division factor for DSI clock + PLLR: packed union { + raw: u3, + value: PLLR, }, - /// Filter index. Index of matching filter element. Range is 0 to RXGFC[LSS] - 1 or RXGFC[LSE] - 1 - FIDX: u5, - reserved15: u2, - /// Filter list. Indicates the filter list of the matching filter element - FLST: u1, - padding: u16, - }), - reserved144: [4]u8, - /// FDCAN Rx FIFO X status register - RXFS: mmio.Mmio(packed struct(u32) { - /// Rx FIFO X fill level. Number of elements stored in Rx FIFO X, range 0 to 3 - FFL: u4, - reserved8: u4, - /// Rx FIFO X get index. Rx FIFO X read index pointer, range 0 to 2 - FGI: u2, - reserved16: u6, - /// Rx FIFO X put index. Rx FIFO X write index pointer, range 0 to 2 - FPI: u2, - reserved24: u6, - /// Rx FIFO X full - FF: u1, - /// Rx FIFO X message lost. This bit is a copy of interrupt flag IR[RFL]. When IR[RFL] is reset, this bit is also reset - RFL: u1, - padding: u6, - }), - /// CAN Rx FIFO X acknowledge register - RXFA: mmio.Mmio(packed struct(u32) { - /// Rx FIFO X acknowledge index. After the Host has read a message or a sequence of messages from Rx FIFO X it has to write the buffer index of the last element read from Rx FIFO X to FAI. This sets the Rx FIFO X get index RXFS[FGI] to FAI + 1 and update the FIFO X fill level RXFS[FFL] - FAI: u3, - padding: u29, + padding: u1, }), - reserved192: [40]u8, - /// FDCAN Tx buffer configuration register - TXBC: mmio.Mmio(packed struct(u32) { - reserved24: u24, - /// Tx FIFO/queue mode. This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - TFQM: packed union { - raw: u1, - value: TFQM, + /// PLL configuration register + PLLSAICFGR: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// PLL multiplication factor for VCO + PLLN: packed union { + raw: u9, + value: PLLN, + }, + reserved16: u1, + /// PLL division factor for main system clock + PLLP: packed union { + raw: u2, + value: PLLP, }, - padding: u7, - }), - /// FDCAN Tx FIFO/queue status register - TXFQS: mmio.Mmio(packed struct(u32) { - /// Tx FIFO free level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC[TFQM] = 1) - TFFL: u3, - reserved8: u5, - /// Tx FIFO get index. Tx FIFO read index pointer, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC.TFQM = 1) - TFGI: u2, - reserved16: u6, - /// Tx FIFO/queue put index. Tx FIFO/queue write index pointer, range 0 to 3 - TFQPI: u2, - reserved21: u3, - /// Tx FIFO/queue full - TFQF: u1, - padding: u10, - }), - /// FDCAN Tx buffer request pending register - TXBRP: mmio.Mmio(packed struct(u32) { - /// Transmission request pending. Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions - TRP: u1, - padding: u31, - }), - /// FDCAN Tx buffer add request register - TXBAR: mmio.Mmio(packed struct(u32) { - /// Add request. Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed - AR: u1, - padding: u31, - }), - /// FDCAN Tx buffer cancellation request register - TXBCR: mmio.Mmio(packed struct(u32) { - /// Cancellation request. Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset - CR: u1, - padding: u31, - }), - /// FDCAN Tx buffer transmission occurred register - TXBTO: mmio.Mmio(packed struct(u32) { - /// Transmission occurred.. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR - TO: u1, - padding: u31, - }), - /// FDCAN Tx buffer cancellation finished register - TXBCF: mmio.Mmio(packed struct(u32) { - /// Cancellation finished. Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR - CF: u1, - padding: u31, - }), - /// FDCAN Tx buffer transmission interrupt enable register - TXBTIE: mmio.Mmio(packed struct(u32) { - /// Transmission interrupt enable. Each Tx buffer has its own TIE bit - TIE: u1, - padding: u31, - }), - /// FDCAN Tx buffer cancellation finished interrupt enable register - TXBCIE: mmio.Mmio(packed struct(u32) { - /// Cancellation finished interrupt enable.. Each Tx buffer has its own CFIE bit - CFIE: u1, - padding: u31, - }), - /// FDCAN Tx event FIFO status register - TXEFS: mmio.Mmio(packed struct(u32) { - /// Event FIFO fill level. Number of elements stored in Tx event FIFO, range 0 to 3 - EFFL: u3, - reserved8: u5, - /// Event FIFO get index. Tx event FIFO read index pointer, range 0 to 3 - EFGI: u2, - reserved16: u6, - /// Event FIFO put index. Tx event FIFO write index pointer, range 0 to 3 - EFPI: u2, reserved24: u6, - /// Event FIFO full - EFF: u1, - /// Tx event FIFO element lost. This bit is a copy of interrupt flag IR[TEFL]. When IR[TEFL] is reset, this bit is also reset. 0 No Tx event FIFO element lost 1 Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0 - TEFL: u1, - padding: u6, - }), - /// FDCAN Tx event FIFO acknowledge register - TXEFA: mmio.Mmio(packed struct(u32) { - /// Event FIFO acknowledge index. After the Host has read an element or a sequence of elements from the Tx event FIFO, it has to write the index of the last element read from Tx event FIFO to EFAI. This sets the Tx event FIFO get index TXEFS[EFGI] to EFAI + 1 and updates the FIFO 0 fill level TXEFS[EFFL] - EFAI: u2, - padding: u30, - }), - reserved256: [20]u8, - /// FDCAN CFG clock divider register - CKDIV: mmio.Mmio(packed struct(u32) { - /// input clock divider. The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 - PDIV: packed union { + /// PLL division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ: packed union { raw: u4, - value: PDIV, + value: PLLQ, }, - padding: u28, + /// PLL division factor for DSI clock + PLLR: packed union { + raw: u3, + value: PLLR, + }, + padding: u1, }), - }; - }; - - pub const fsmc_v2x3 = struct { - pub const ACCMOD = enum(u2) { - /// Access mode A - A = 0x0, - /// Access mode B - B = 0x1, - /// Access mode C - C = 0x2, - /// Access mode D - D = 0x3, - }; - - pub const ECCPS = enum(u3) { - /// ECC page size 256 bytes - Bytes256 = 0x0, - /// ECC page size 512 bytes - Bytes512 = 0x1, - /// ECC page size 1024 bytes - Bytes1024 = 0x2, - /// ECC page size 2048 bytes - Bytes2048 = 0x3, - /// ECC page size 4096 bytes - Bytes4096 = 0x4, - /// ECC page size 8192 bytes - Bytes8192 = 0x5, - _, - }; - - pub const MTYP = enum(u2) { - /// SRAM memory type - SRAM = 0x0, - /// PSRAM (CRAM) memory type - PSRAM = 0x1, - /// NOR Flash/OneNAND Flash - Flash = 0x2, - _, - }; - - pub const MWID = enum(u2) { - /// Memory data bus width 8 bits - Bits8 = 0x0, - /// Memory data bus width 16 bits - Bits16 = 0x1, - /// Memory data bus width 32 bits - Bits32 = 0x2, - _, - }; - - pub const PTYP = enum(u1) { - /// NAND Flash - NANDFlash = 0x1, - _, - }; - - pub const PWID = enum(u2) { - /// External memory device width 8 bits - Bits8 = 0x0, - /// External memory device width 16 bits - Bits16 = 0x1, - _, - }; - - pub const WAITCFG = enum(u1) { - /// NWAIT signal is active one data cycle before wait state - BeforeWaitState = 0x0, - /// NWAIT signal is active during wait state - DuringWaitState = 0x1, - }; - - pub const WAITPOL = enum(u1) { - /// NWAIT active low - ActiveLow = 0x0, - /// NWAIT active high - ActiveHigh = 0x1, - }; - - /// Flexible static memory controller - pub const FSMC = extern struct { - /// SRAM/NOR-Flash chip-select control register 1 - BCR1: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { + /// dedicated clocks configuration register + DCKCFGR1: mmio.Mmio(packed struct(u32) { + /// PLLI2S division factor for SAI1 clock + PLLI2SDIVQ: packed union { + raw: u5, + value: PLLI2SDIVQ, + }, + reserved8: u3, + /// PLLSAI division factor for SAI1 clock + PLLSAIDIVQ: packed union { + raw: u5, + value: PLLSAIDIVQ, + }, + reserved16: u3, + /// division factor for LCD_CLK + PLLSAIDIVR: packed union { raw: u2, - value: MTYP, + value: PLLSAIDIVR, }, - /// Memory data bus width - MWID: packed union { + reserved20: u2, + /// SAI1 clock source selection + SAI1SEL: packed union { raw: u2, - value: MWID, + value: SAISEL, }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { + /// SAI2 clock source selection + SAI2SEL: packed union { + raw: u2, + value: SAISEL, + }, + /// Timers clocks prescalers selection + TIMPRE: packed union { raw: u1, - value: WAITPOL, + value: TIMPRE, }, - /// WRAPMOD - WRAPMOD: u1, - /// Wait timing configuration - WAITCFG: packed union { + /// DFSDM1 clock source selection + DFSDM1SEL: packed union { raw: u1, - value: WAITCFG, + value: DFSDMSEL, }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - reserved19: u3, - /// Write burst enable - CBURSTRW: u1, - /// Continuous clock enable - CCLKEN: u1, - padding: u11, + /// DFSDM1 AUDIO clock source selection + ADFSDM1SEL: packed union { + raw: u1, + value: ADFSDMSEL, + }, + padding: u5, }), - /// SRAM/NOR-Flash chip-select timing register 1-4 - BTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - /// Clock divide ratio (for FMC_CLK signal) - CLKDIV: u4, - /// Data latency for synchronous memory - DATLAT: u4, - /// Access mode - ACCMOD: packed union { + /// dedicated clocks configuration register + DCKCFGR2: mmio.Mmio(packed struct(u32) { + /// USART 1 clock source selection + USART1SEL: packed union { raw: u2, - value: ACCMOD, + value: USART1SEL, }, - padding: u2, - }), - /// SRAM/NOR-Flash chip-select control register 2-4 - BCR: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { + /// USART 2 clock source selection + USART2SEL: packed union { raw: u2, - value: MTYP, + value: USART2SEL, }, - /// Memory data bus width - MWID: packed union { + /// USART 3 clock source selection + USART3SEL: packed union { raw: u2, - value: MWID, + value: USART2SEL, }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { - raw: u1, - value: WAITPOL, + /// UART 4 clock source selection + UART4SEL: packed union { + raw: u2, + value: USART2SEL, }, - /// WRAPMOD - WRAPMOD: u1, - /// Wait timing configuration - WAITCFG: packed union { - raw: u1, - value: WAITCFG, + /// UART 5 clock source selection + UART5SEL: packed union { + raw: u2, + value: USART2SEL, }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - reserved19: u3, - /// Write burst enable - CBURSTRW: u1, - padding: u12, - }), - reserved96: [84]u8, - /// PC Card/NAND Flash control register 2-4 - PCR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Wait feature enable bit - PWAITEN: u1, - /// NAND Flash memory bank enable bit - PBKEN: u1, - /// Memory type - PTYP: packed union { - raw: u1, - value: PTYP, + /// USART 6 clock source selection + USART6SEL: packed union { + raw: u2, + value: USART1SEL, }, - /// Data bus width - PWID: packed union { + /// UART 7 clock source selection + UART7SEL: packed union { raw: u2, - value: PWID, + value: USART2SEL, }, - /// ECC computation logic enable bit - ECCEN: u1, - reserved9: u2, - /// CLE to RE delay - TCLR: u4, - /// ALE to RE delay - TAR: u4, - /// ECC page size - ECCPS: packed union { - raw: u3, - value: ECCPS, + /// UART 8 clock source selection + UART8SEL: packed union { + raw: u2, + value: USART2SEL, }, - padding: u12, - }), - /// FIFO status and interrupt register 2-4 - SR: mmio.Mmio(packed struct(u32) { - /// Interrupt rising edge status - IRS: u1, - /// Interrupt high-level status - ILS: u1, - /// Interrupt falling edge status - IFS: u1, - /// Interrupt rising edge detection enable bit - IREN: u1, - /// Interrupt high-level detection enable bit - ILEN: u1, - /// Interrupt falling edge detection enable bit - IFEN: u1, - /// FIFO empty status - FEMPT: u1, - padding: u25, - }), - /// Common memory space timing register 2-4 - PMEM: mmio.Mmio(packed struct(u32) { - /// Common memory x setup time - MEMSET: u8, - /// Common memory wait time - MEMWAIT: u8, - /// Common memory hold time - MEMHOLD: u8, - /// Common memory x data bus Hi-Z time - MEMHIZ: u8, - }), - /// Attribute memory space timing register 2-4 - PATT: mmio.Mmio(packed struct(u32) { - /// Attribute memory setup time - ATTSET: u8, - /// Attribute memory wait time - ATTWAIT: u8, - /// Attribute memory hold time - ATTHOLD: u8, - /// Attribute memory data bus Hi-Z time - ATTHIZ: u8, - }), - reserved116: [4]u8, - /// ECC result register 2-3 - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC computation result value - ECC: u32, - }), - reserved176: [56]u8, - /// I/O space timing register 4 - PIO4: mmio.Mmio(packed struct(u32) { - /// IOSETx - IOSETx: u8, - /// IOWAITx - IOWAITx: u8, - /// IOHOLDx - IOHOLDx: u8, - /// IOHIZx - IOHIZx: u8, - }), - reserved260: [80]u8, - /// SRAM/NOR-Flash write timing registers 1-4 - BWTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - reserved28: u12, - /// Access mode - ACCMOD: packed union { + /// I2C1 clock source selection + I2C1SEL: packed union { raw: u2, - value: ACCMOD, + value: I2CSEL, }, - padding: u2, + /// I2C2 clock source selection + I2C2SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// I2C3 clock source selection + I2C3SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// I2C4 clock source selection + I2C4SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// Low power timer 1 clock source selection + LPTIM1SEL: packed union { + raw: u2, + value: LPTIMSEL, + }, + /// HDMI-CEC clock source selection + CECSEL: packed union { + raw: u1, + value: CECSEL, + }, + /// 48MHz clock source selection + CLK48SEL: packed union { + raw: u1, + value: CLK48SEL, + }, + /// SDMMC1 clock source selection + SDMMC1SEL: packed union { + raw: u1, + value: SDMMCSEL, + }, + /// SDMMC2 clock source selection + SDMMC2SEL: packed union { + raw: u1, + value: SDMMCSEL, + }, + /// DSI clock source selection + DSISEL: packed union { + raw: u1, + value: DSISEL, + }, + padding: u1, }), }; }; - pub const rcc_f3v2 = struct { - pub const ADCPRE = enum(u2) { - /// PCLK divided by 2 - Div2 = 0x0, - /// PCLK divided by 4 - Div4 = 0x1, - /// PCLK divided by 6 - Div6 = 0x2, - /// PCLK divided by 8 - Div8 = 0x3, - }; - - pub const ADCPRES = enum(u5) { - /// PLL clock not divided - Div1 = 0x10, - /// PLL clock divided by 2 - Div2 = 0x11, - /// PLL clock divided by 4 - Div4 = 0x12, - /// PLL clock divided by 6 - Div6 = 0x13, - /// PLL clock divided by 8 - Div8 = 0x14, - /// PLL clock divided by 10 - Div10 = 0x15, - /// PLL clock divided by 12 - Div12 = 0x16, - /// PLL clock divided by 16 - Div16 = 0x17, - /// PLL clock divided by 32 - Div32 = 0x18, - /// PLL clock divided by 64 - Div64 = 0x19, - /// PLL clock divided by 128 - Div128 = 0x1a, - /// PLL clock divided by 256 - Div256 = 0x1b, + pub const rcc_g0 = struct { + pub const ADCSEL = enum(u2) { + /// SYSCLK used as ADC clock source + SYS = 0x0, + /// PLLPCLK used as ADC clock source + PLL1_P = 0x1, + /// HSI used as ADC clock source + HSI = 0x2, _, }; - pub const CECSW = enum(u1) { - /// HSI clock divided by 244 selected as CEC clock source - HSI_DIV_244 = 0x0, - /// LSE clock selected as CEC clock source + pub const CECSEL = enum(u1) { + /// HSI divided by 488 used as CEC clock + HSI_DIV_488 = 0x0, + /// LSE used as CEC clock LSE = 0x1, }; + pub const FDCANSEL = enum(u2) { + /// PCLK used as FDCAN clock source + PCLK1 = 0x0, + /// PLLQCLK used as FDCAN clock source + PLL1_Q = 0x1, + /// HSE used as FDCAN clock source + HSE = 0x2, + _, + }; + pub const HPRE = enum(u4) { /// SYSCLK not divided Div1 = 0x0, - /// SYSCLK divided by 2 + /// SYSCLK is divided by 2 Div2 = 0x8, - /// SYSCLK divided by 4 + /// SYSCLK is divided by 4 Div4 = 0x9, - /// SYSCLK divided by 8 + /// SYSCLK is divided by 8 Div8 = 0xa, - /// SYSCLK divided by 16 + /// SYSCLK is divided by 16 Div16 = 0xb, - /// SYSCLK divided by 64 + /// SYSCLK is divided by 64 Div64 = 0xc, - /// SYSCLK divided by 128 + /// SYSCLK is divided by 128 Div128 = 0xd, - /// SYSCLK divided by 256 + /// SYSCLK is divided by 256 Div256 = 0xe, - /// SYSCLK divided by 512 + /// SYSCLK is divided by 512 Div512 = 0xf, _, }; - pub const ICSW = enum(u1) { - /// HSI clock selected as I2C clock source - HSI = 0x0, - /// SYSCLK clock selected as I2C clock source + pub const HSIDIV = enum(u3) { + /// HSI clock is not divided + Div1 = 0x0, + /// HSI clock is divided by 2 + Div2 = 0x1, + /// HSI clock is divided by 4 + Div4 = 0x2, + /// HSI clock is divided by 8 + Div8 = 0x3, + /// HSI clock is divided by 16 + Div16 = 0x4, + /// HSI clock is divided by 32 + Div32 = 0x5, + /// HSI clock is divided by 64 + Div64 = 0x6, + /// HSI clock is divided by 128 + Div128 = 0x7, + }; + + pub const I2C1SEL = enum(u2) { + /// PCLK used as I2C1 clock source + PCLK1 = 0x0, + /// SYSCLK used as I2C1 clock source SYS = 0x1, + /// HSI used as I2C1 clock source + HSI = 0x2, + _, }; - pub const ISSRC = enum(u1) { - /// System clock used as I2S clock source + pub const I2C2I2S1SEL = enum(u2) { + /// PCLK used as I2C2/I2S2 clock source + PCLK1 = 0x0, + /// SYSCLK used as I2C2/I2S2 clock source + SYS = 0x1, + /// HSI used as I2C2/I2S2 clock source + HSI = 0x2, + /// External clock used as I2C2/I2S2 clock source + I2S_CKIN = 0x3, + }; + + pub const I2S1SEL = enum(u2) { + /// SYSCLK used as I2S1 clock source SYS = 0x0, - /// External clock mapped on the I2S_CKIN pin used as I2S clock source - CKIN = 0x1, + /// PLLPCLK used as I2S1 clock source + PLL1_P = 0x1, + /// HSI used as I2S1 clock source + HSI = 0x2, + /// External clock used as I2S1 clock source + I2S_CKIN = 0x3, + }; + + pub const I2S2SEL = enum(u2) { + /// SYSCLK used as I2S2 clock source + SYS = 0x0, + /// PLLPCLK used as I2S2 clock source + PLL1_P = 0x1, + /// HSI used as I2S2 clock source + HSI = 0x2, + /// External clock used as I2S2 clock source + I2S_CKIN = 0x3, + }; + + pub const LPTIM1SEL = enum(u2) { + /// PCLK used as LPTIM1 clock source + PCLK1 = 0x0, + /// LSI used as LPTIM1 clock source + LSI = 0x1, + /// HSI used as LPTIM1 clock source + HSI = 0x2, + /// LSE used as LPTIM1 clock source + LSE = 0x3, + }; + + pub const LPTIM2SEL = enum(u2) { + /// PCLK used as LPTIM2 clock source + PCLK1 = 0x0, + /// LSI used as LPTIM2 clock source + LSI = 0x1, + /// HSI used as LPTIM2 clock source + HSI = 0x2, + /// LSE used as LPTIM2 clock source + LSE = 0x3, + }; + + pub const LPUART1SEL = enum(u2) { + /// PCLK used as LPUART1 clock source + PCLK1 = 0x0, + /// SYSCLK used as LPUART1 clock source + SYS = 0x1, + /// HSI used as LPUART1 clock source + HSI = 0x2, + /// LSE used as LPUART1 clock source + LSE = 0x3, + }; + + pub const LPUART2SEL = enum(u2) { + /// PCLK used as LPUART2 clock source + PCLK1 = 0x0, + /// SYSCLK used as LPUART2 clock source + SYS = 0x1, + /// HSI used as LPUART2 clock source + HSI = 0x2, + /// LSE used as LPUART2 clock source + LSE = 0x3, }; pub const LSEDRV = enum(u2) { /// Low driving capability Low = 0x0, - /// Medium high driving capability - MediumHigh = 0x1, /// Medium low driving capability - MediumLow = 0x2, + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, /// High driving capability High = 0x3, }; - pub const MCOPRE = enum(u3) { - /// MCO is divided by 1 + pub const MCOPRE = enum(u4) { + /// MCO1 not divided Div1 = 0x0, - /// MCO is divided by 2 + /// MCO clock is divided by 2 Div2 = 0x1, - /// MCO is divided by 4 + /// MCO clock is divided by 4 Div4 = 0x2, - /// MCO is divided by 8 + /// MCO clock is divided by 8 Div8 = 0x3, - /// MCO is divided by 16 + /// MCO clock is divided divided by 16 Div16 = 0x4, - /// MCO is divided by 32 + /// MCO clock is divided divided by 32 Div32 = 0x5, - /// MCO is divided by 64 + /// MCO clock is divided divided by 64 Div64 = 0x6, - /// MCO is divided by 128 + /// MCO clock is divided divided by 128 Div128 = 0x7, - }; - - pub const MCOSEL = enum(u3) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// Internal low speed (LSI) oscillator clock selected - LSI = 0x2, - /// External low speed (LSE) oscillator clock selected - LSE = 0x3, - /// System clock selected - SYS = 0x4, - /// Internal RC 8 MHz (HSI) oscillator clock selected - HSI = 0x5, - /// External 4-32 MHz (HSE) oscillator clock selected - HSE = 0x6, - /// PLL clock selected (divided by 1 or 2, depending en PLLMCODIV) - PLL = 0x7, + /// MCO clock is divided divided by 256 + Div256 = 0x8, + /// MCO clock is divided divided by 512 + Div512 = 0x9, + /// MCO clock is divided divided by 1024 + Div1024 = 0xa, _, }; - pub const PLLMCODIV = enum(u1) { - /// PLL is divided by 2 for MCO - Div2 = 0x0, - /// PLL is not divided for MCO - Div1 = 0x1, - }; - - pub const PLLMUL = enum(u4) { - /// PLL input clock x2 - Mul2 = 0x0, - /// PLL input clock x3 - Mul3 = 0x1, - /// PLL input clock x4 - Mul4 = 0x2, - /// PLL input clock x5 - Mul5 = 0x3, - /// PLL input clock x6 - Mul6 = 0x4, - /// PLL input clock x7 - Mul7 = 0x5, - /// PLL input clock x8 - Mul8 = 0x6, - /// PLL input clock x9 - Mul9 = 0x7, - /// PLL input clock x10 - Mul10 = 0x8, - /// PLL input clock x11 - Mul11 = 0x9, - /// PLL input clock x12 - Mul12 = 0xa, - /// PLL input clock x13 - Mul13 = 0xb, - /// PLL input clock x14 - Mul14 = 0xc, - /// PLL input clock x15 - Mul15 = 0xd, - /// PLL input clock x16 - Mul16 = 0xe, + pub const MCOSEL = enum(u4) { + /// No clock, MCO output disabled + DISABLE = 0x0, + /// SYSCLK selected as MCO source + SYS = 0x1, + /// HSI48 selected as MCO source + HSI48 = 0x2, + /// HSI selected as MCO source + HSI = 0x3, + /// HSE selected as MCO source + HSE = 0x4, + /// PLLRCLK selected as MCO source + PLLRCLK = 0x5, + /// LSI selected as MCO source + LSI = 0x6, + /// LSE selected as MCO source + LSE = 0x7, + /// PLLPCLK selected as MCO source + PLL1_P = 0x8, + /// PLLQCLK selected as MCO source + PLL1_Q = 0x9, + /// RTCCLK selected as MCO source + RTCCLK = 0xa, + /// RTC_Wakeup selected as MCO source + RTC_WKUP = 0xb, _, }; - pub const PLLSRC = enum(u1) { - /// HSI divided by 2 selected as PLL input clock - HSI_Div2 = 0x0, - /// HSE divided by PREDIV selected as PLL input clock - HSE_Div_PREDIV = 0x1, - }; - - pub const PLLXTPRE = enum(u1) { - /// HSE clock not divided + pub const PLLM = enum(u3) { Div1 = 0x0, - /// HSE clock divided by 2 Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, + pub const PLLN = enum(u7) { + Mul8 = 0x8, + Mul9 = 0x9, + Mul10 = 0xa, + Mul11 = 0xb, + Mul12 = 0xc, + Mul13 = 0xd, + Mul14 = 0xe, + Mul15 = 0xf, + Mul16 = 0x10, + Mul17 = 0x11, + Mul18 = 0x12, + Mul19 = 0x13, + Mul20 = 0x14, + Mul21 = 0x15, + Mul22 = 0x16, + Mul23 = 0x17, + Mul24 = 0x18, + Mul25 = 0x19, + Mul26 = 0x1a, + Mul27 = 0x1b, + Mul28 = 0x1c, + Mul29 = 0x1d, + Mul30 = 0x1e, + Mul31 = 0x1f, + Mul32 = 0x20, + Mul33 = 0x21, + Mul34 = 0x22, + Mul35 = 0x23, + Mul36 = 0x24, + Mul37 = 0x25, + Mul38 = 0x26, + Mul39 = 0x27, + Mul40 = 0x28, + Mul41 = 0x29, + Mul42 = 0x2a, + Mul43 = 0x2b, + Mul44 = 0x2c, + Mul45 = 0x2d, + Mul46 = 0x2e, + Mul47 = 0x2f, + Mul48 = 0x30, + Mul49 = 0x31, + Mul50 = 0x32, + Mul51 = 0x33, + Mul52 = 0x34, + Mul53 = 0x35, + Mul54 = 0x36, + Mul55 = 0x37, + Mul56 = 0x38, + Mul57 = 0x39, + Mul58 = 0x3a, + Mul59 = 0x3b, + Mul60 = 0x3c, + Mul61 = 0x3d, + Mul62 = 0x3e, + Mul63 = 0x3f, + Mul64 = 0x40, + Mul65 = 0x41, + Mul66 = 0x42, + Mul67 = 0x43, + Mul68 = 0x44, + Mul69 = 0x45, + Mul70 = 0x46, + Mul71 = 0x47, + Mul72 = 0x48, + Mul73 = 0x49, + Mul74 = 0x4a, + Mul75 = 0x4b, + Mul76 = 0x4c, + Mul77 = 0x4d, + Mul78 = 0x4e, + Mul79 = 0x4f, + Mul80 = 0x50, + Mul81 = 0x51, + Mul82 = 0x52, + Mul83 = 0x53, + Mul84 = 0x54, + Mul85 = 0x55, + Mul86 = 0x56, _, }; - pub const PREDIV = enum(u4) { - /// PREDIV input clock not divided - Div1 = 0x0, - /// PREDIV input clock divided by 2 + pub const PLLP = enum(u5) { Div2 = 0x1, - /// PREDIV input clock divided by 3 Div3 = 0x2, - /// PREDIV input clock divided by 4 Div4 = 0x3, - /// PREDIV input clock divided by 5 Div5 = 0x4, - /// PREDIV input clock divided by 6 Div6 = 0x5, - /// PREDIV input clock divided by 7 Div7 = 0x6, - /// PREDIV input clock divided by 8 Div8 = 0x7, - /// PREDIV input clock divided by 9 Div9 = 0x8, - /// PREDIV input clock divided by 10 Div10 = 0x9, - /// PREDIV input clock divided by 11 Div11 = 0xa, - /// PREDIV input clock divided by 12 Div12 = 0xb, - /// PREDIV input clock divided by 13 Div13 = 0xc, - /// PREDIV input clock divided by 14 Div14 = 0xd, - /// PREDIV input clock divided by 15 Div15 = 0xe, - /// PREDIV input clock divided by 16 Div16 = 0xf, + Div17 = 0x10, + Div18 = 0x11, + Div19 = 0x12, + Div20 = 0x13, + Div21 = 0x14, + Div22 = 0x15, + Div23 = 0x16, + Div24 = 0x17, + Div25 = 0x18, + Div26 = 0x19, + Div27 = 0x1a, + Div28 = 0x1b, + Div29 = 0x1c, + Div30 = 0x1d, + Div31 = 0x1e, + Div32 = 0x1f, + _, + }; + + pub const PLLQ = enum(u3) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + _, + }; + + pub const PLLR = enum(u3) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + _, + }; + + pub const PLLSRC = enum(u2) { + /// No clock selected as PLL entry clock source + DISABLE = 0x0, + /// HSI selected as PLL entry clock source + HSI = 0x2, + /// HSE selected as PLL entry clock source + HSE = 0x3, + _, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK is divided by 2 + Div2 = 0x4, + /// HCLK is divided by 4 + Div4 = 0x5, + /// HCLK is divided by 8 + Div8 = 0x6, + /// HCLK is divided by 16 + Div16 = 0x7, + _, + }; + + pub const RNGDIV = enum(u2) { + /// RNG clock is not divided + Div1 = 0x0, + /// RNG clock is divided by 2 + Div2 = 0x1, + /// RNG clock is divided by 4 + Div4 = 0x2, + /// RNG clock is divided by 8 + Div8 = 0x3, + }; + + pub const RNGSEL = enum(u2) { + /// No clock used as RNG clock source + DISABLE = 0x0, + /// HSI divided by 8 used as RNG clock source + HSI_DIV_8 = 0x1, + /// SYSCLK used as RNG clock source + SYS = 0x2, + /// PLLQCLK used as RNG clock source + PLL1_Q = 0x3, }; pub const RTCSEL = enum(u2) { - /// No clock + /// No clock used as RTC clock DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock + /// LSE used as RTC clock LSE = 0x1, - /// LSI oscillator clock used as RTC clock + /// LSI used as RTC clock LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, + /// HSE divided by 32 used as RTC clock + HSE_Div32 = 0x3, }; - pub const SW = enum(u2) { - /// HSI oscillator used as system clock + pub const SW = enum(u3) { + /// HSI selected as system clock HSI = 0x0, - /// HSE oscillator used as system clock + /// HSE selected as system clock HSE = 0x1, - /// PLL used as system clock - PLL1_P = 0x2, + /// PLLRCLK selected as system clock + PLL1_R = 0x2, + /// LSI selected as system clock + LSI = 0x3, + /// LSE selected as system clock + LSE = 0x4, _, }; - pub const TIM2SW = enum(u1) { - /// PCLK2 clock (doubled frequency when prescaled) + pub const TIM15SEL = enum(u1) { + /// TIMPCLK used as TIM15 clock source PCLK1_TIM = 0x0, - /// PLL vco output (running up to 144 MHz) - PLL1_P = 0x1, - }; - - pub const TIMSW = enum(u1) { - /// PCLK2 clock (doubled frequency when prescaled) - PCLK2_TIM = 0x0, - /// PLL vco output (running up to 144 MHz) - PLL1_P = 0x1, + /// PLLQCLK used as TIM15 clock source + PLL1_Q = 0x1, }; - pub const USART1SW = enum(u2) { - /// PCLK selected as USART clock source - PCLK2 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, + pub const TIM1SEL = enum(u1) { + /// TIMPCLK used as TIM1 clock source + PCLK1_TIM = 0x0, + /// PLLQCLK used as TIM1 clock source + PLL1_Q = 0x1, }; - pub const USARTSW = enum(u2) { - /// PCLK selected as USART clock source + pub const USARTSEL = enum(u2) { + /// PCLK used as USART clock source PCLK1 = 0x0, - /// SYSCLK selected as USART clock source + /// SYSCLK used as USART clock source SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, + /// HSI used as USART clock source + HSI = 0x2, + /// LSE used as USART clock source + LSE = 0x3, }; - pub const USBPRE = enum(u1) { - /// PLL clock is divided by 1.5 - Div1_5 = 0x0, - /// PLL clock is not divided - Div1 = 0x1, + pub const USBSEL = enum(u2) { + /// HSI48 used as USB clock source + HSI48 = 0x0, + /// HSE used as USB clock source + HSE = 0x1, + /// PLLQCLK used as USB clock source + PLL1_Q = 0x2, + _, }; /// Reset and clock control pub const RCC = extern struct { /// Clock control register CR: mmio.Mmio(packed struct(u32) { - /// Internal High Speed clock enable + reserved8: u8, + /// HSI clock enable HSION: u1, - /// Internal High Speed clock ready flag + /// HSI always enable for peripheral kernels + HSIKERON: u1, + /// HSI clock ready flag HSIRDY: u1, - reserved3: u1, - /// Internal High Speed clock trimming - HSITRIM: u5, - /// Internal High Speed clock Calibration - HSICAL: u8, - /// External High Speed clock enable + /// HSI clock division factor + HSIDIV: packed union { + raw: u3, + value: HSIDIV, + }, + reserved16: u2, + /// HSE clock enable HSEON: u1, - /// External High Speed clock ready flag + /// HSE clock ready flag HSERDY: u1, - /// External High Speed clock Bypass + /// HSE crystal oscillator bypass HSEBYP: u1, - /// Clock Security System enable + /// Clock security system enable CSSON: u1, - reserved24: u4, + reserved22: u2, + /// HSI48ON + HSI48ON: u1, + /// HSI48RDY + HSI48RDY: u1, /// PLL enable PLLON: u1, /// PLL clock ready flag PLLRDY: u1, padding: u6, }), - /// Clock configuration register (RCC_CFGR) + /// Internal clock sources calibration register + ICSCR: mmio.Mmio(packed struct(u32) { + /// HSI clock calibration + HSICAL: u8, + /// HSI clock trimming + HSITRIM: u7, + padding: u17, + }), + /// Clock configuration register CFGR: mmio.Mmio(packed struct(u32) { - /// System clock Switch + /// System clock switch SW: packed union { - raw: u2, + raw: u3, value: SW, }, - /// System Clock Switch Status + /// System clock switch status SWS: packed union { - raw: u2, + raw: u3, value: SW, }, + reserved8: u2, /// AHB prescaler HPRE: packed union { raw: u4, value: HPRE, }, - /// APB Low speed prescaler (APB1) - PPRE1: packed union { + /// APB prescaler + PPRE: packed union { raw: u3, value: PPRE, }, - /// APB high speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, + reserved16: u1, + /// MCO2SEL + MCO2SEL: packed union { + raw: u4, + value: MCOSEL, }, - /// ADC prescaler - ADCPRE: packed union { - raw: u2, - value: ADCPRE, + /// MCO2PRE + MCO2PRE: packed union { + raw: u4, + value: MCOPRE, }, - /// PLL entry clock source + /// Microcontroller clock output + MCO1SEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// Microcontroller clock output prescaler + MCO1PRE: packed union { + raw: u4, + value: MCOPRE, + }, + }), + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// PLL input clock source PLLSRC: packed union { - raw: u1, + raw: u2, value: PLLSRC, }, - /// HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products. - PLLXTPRE: packed union { - raw: u1, - value: PLLXTPRE, - }, - /// PLL Multiplication Factor - PLLMUL: packed union { - raw: u4, - value: PLLMUL, + reserved4: u2, + /// Division factor M of the PLL input clock divider + PLLM: packed union { + raw: u3, + value: PLLM, }, - /// USB prescaler - USBPRE: packed union { - raw: u1, - value: USBPRE, + reserved8: u1, + /// PLL frequency multiplication factor N + PLLN: packed union { + raw: u7, + value: PLLN, }, - /// I2S external clock source selection - I2SSRC: packed union { - raw: u1, - value: ISSRC, + reserved16: u1, + /// PLLPCLK clock output enable + PLLPEN: u1, + /// PLL VCO division factor P for PLLPCLK clock output + PLLP: packed union { + raw: u5, + value: PLLP, }, - /// Microcontroller clock output - MCOSEL: packed union { + reserved24: u2, + /// PLLQCLK clock output enable + PLLQEN: u1, + /// PLL VCO division factor Q for PLLQCLK clock output + PLLQ: packed union { raw: u3, - value: MCOSEL, + value: PLLQ, }, - reserved28: u1, - /// Microcontroller Clock Output Prescaler - MCOPRE: packed union { + /// PLLRCLK clock output enable + PLLREN: u1, + /// PLL VCO division factor R for PLLRCLK clock output + PLLR: packed union { raw: u3, - value: MCOPRE, - }, - /// Do not divide PLL to MCO - PLLMCODIV: packed union { - raw: u1, - value: PLLMCODIV, + value: PLLR, }, }), - /// Clock interrupt register (RCC_CIR) - CIR: mmio.Mmio(packed struct(u32) { - /// LSI Ready Interrupt flag + reserved20: [4]u8, + /// RCC clock recovery RC register + CRRCR: mmio.Mmio(packed struct(u32) { + /// HSI48 clock calibration + HSI48CAL: u9, + padding: u23, + }), + /// Clock interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + reserved3: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// PLL ready interrupt enable + PLLSYSRDYIE: u1, + padding: u26, + }), + /// Clock interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag LSIRDYF: u1, - /// LSE Ready Interrupt flag + /// LSE ready interrupt flag LSERDYF: u1, - /// HSI Ready Interrupt flag + /// HSI48RDYF + HSI48RDYF: u1, + /// HSI ready interrupt flag HSIRDYF: u1, - /// HSE Ready Interrupt flag + /// HSE ready interrupt flag HSERDYF: u1, - /// PLL Ready Interrupt flag - PLLRDYF: u1, - reserved7: u2, - /// Clock Security System Interrupt flag + /// PLL ready interrupt flag + PLLSYSRDYF: u1, + reserved8: u2, + /// Clock security system interrupt flag CSSF: u1, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1, - /// LSE Ready Interrupt Enable - LSERDYIE: u1, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1, - /// HSE Ready Interrupt Enable - HSERDYIE: u1, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1, - reserved16: u3, - /// LSI Ready Interrupt Clear + /// LSE Clock security system interrupt flag + LSECSSF: u1, + padding: u22, + }), + /// Clock interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt clear LSIRDYC: u1, - /// LSE Ready Interrupt Clear + /// LSE ready interrupt clear LSERDYC: u1, - /// HSI Ready Interrupt Clear + /// HSI48RDYC + HSI48RDYC: u1, + /// HSI ready interrupt clear HSIRDYC: u1, - /// HSE Ready Interrupt Clear + /// HSE ready interrupt clear HSERDYC: u1, - /// PLL Ready Interrupt Clear - PLLRDYC: u1, - reserved23: u2, + /// PLL ready interrupt clear + PLLSYSRDYC: u1, + reserved8: u2, /// Clock security system interrupt clear CSSC: u1, - padding: u8, + /// LSE Clock security system interrupt clear + LSECSSC: u1, + padding: u22, }), - /// APB2 peripheral reset register (RCC_APB2RSTR) - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// SYSCFG and COMP reset - SYSCFGRST: u1, - reserved11: u10, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI 1 reset - SPI1RST: u1, - /// TIM8 timer reset - TIM8RST: u1, - /// USART1 reset - USART1RST: u1, - /// SPI4 reset - SPI4RST: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - /// TIM19 timer reset - TIM19RST: u1, - /// TIM20 timer reset - TIM20RST: u1, - reserved22: u1, - /// Debug MCU reset - DBGMCURST: u1, - reserved29: u6, - /// High Resolution Timer1 reset - HRTIM1RST: u1, - padding: u2, + /// GPIO reset register + GPIORSTR: mmio.Mmio(packed struct(u32) { + /// I/O port A reset + GPIOARST: u1, + /// I/O port B reset + GPIOBRST: u1, + /// I/O port C reset + GPIOCRST: u1, + /// I/O port D reset + GPIODRST: u1, + reserved5: u1, + /// I/O port F reset + GPIOFRST: u1, + padding: u26, }), - /// APB1 peripheral reset register (RCC_APB1RSTR) - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + /// DMA1 reset + DMA1RST: u1, + /// DMA1 reset + DMA2RST: u1, + reserved8: u6, + /// FLASH reset + FLASHRST: u1, + reserved12: u3, + /// CRC reset + CRCRST: u1, + reserved16: u3, + /// AES hardware accelerator reset + AESRST: u1, + reserved18: u1, + /// Random number generator reset + RNGRST: u1, + padding: u13, + }), + /// APB peripheral reset register 1 + APBRSTR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer reset TIM2RST: u1, - /// Timer 3 reset + /// TIM3 timer reset TIM3RST: u1, - /// Timer 14 reset + /// TIM4 timer reset TIM4RST: u1, reserved4: u1, - /// Timer 6 reset + /// TIM6 timer reset TIM6RST: u1, - /// Timer 7 reset + /// TIM7 timer reset TIM7RST: u1, - reserved11: u5, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, + reserved7: u1, + /// LPUART2RST + LPUART2RST: u1, + /// USART5RST + USART5RST: u1, + /// USART6RST + USART6RST: u1, + reserved12: u2, + /// FDCANRST + FDCANRST: u1, + /// USBRST + USBRST: u1, /// SPI2 reset SPI2RST: u1, /// SPI3 reset SPI3RST: u1, - reserved17: u1, - /// USART 2 reset + /// CRSRST + CRSRST: u1, + /// USART2 reset USART2RST: u1, /// USART3 reset USART3RST: u1, - /// UART 4 reset - UART4RST: u1, - /// UART 5 reset - UART5RST: u1, + /// USART4 reset + USART4RST: u1, + /// LPUART1 reset + LPUART1RST: u1, /// I2C1 reset I2C1RST: u1, /// I2C2 reset I2C2RST: u1, - /// USB reset - USBRST: u1, - reserved25: u1, - /// CAN reset - CANRST: u1, - /// DAC2 interface reset - DAC2RST: u1, - reserved28: u1, + /// I2C3RST reset + I2C3RST: u1, + /// HDMI CEC reset + CECRST: u1, + /// UCPD1 reset + UCPD1RST: u1, + /// UCPD2 reset + UCPD2RST: u1, + /// Debug support reset + DBGRST: u1, /// Power interface reset PWRRST: u1, - /// DAC interface reset - DACRST: u1, - /// I2C3 reset - I2C3RST: u1, - padding: u1, + /// DAC1 interface reset + DAC1RST: u1, + /// Low Power Timer 2 reset + LPTIM2RST: u1, + /// Low Power Timer 1 reset + LPTIM1RST: u1, }), - /// AHB Peripheral Clock enable register (RCC_AHBENR) - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// SRAM interface clock enable - SRAMEN: u1, - reserved4: u1, - /// FLASH clock enable - FLASHEN: u1, - /// FMC clock enable - FMCEN: u1, - /// CRC clock enable - CRCEN: u1, - reserved16: u9, - /// IO port H clock enable - GPIOHEN: u1, + /// APB peripheral reset register 2 + APBRSTR2: mmio.Mmio(packed struct(u32) { + /// SYSCFG, COMP and VREFBUF reset + SYSCFGRST: u1, + reserved11: u10, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI1 reset + SPI1RST: u1, + reserved14: u1, + /// USART1 reset + USART1RST: u1, + /// TIM14 timer reset + TIM14RST: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + reserved20: u1, + /// ADC reset + ADCRST: u1, + padding: u11, + }), + /// GPIO clock enable register + GPIOENR: mmio.Mmio(packed struct(u32) { /// I/O port A clock enable GPIOAEN: u1, /// I/O port B clock enable @@ -398676,118 +379853,374 @@ pub const types = struct { GPIOCEN: u1, /// I/O port D clock enable GPIODEN: u1, - /// I/O port E clock enable - GPIOEEN: u1, + reserved5: u1, /// I/O port F clock enable GPIOFEN: u1, - /// IO port G clock enable - GPIOGEN: u1, - /// Touch sensing controller clock enable - TSCEN: u1, - reserved28: u3, - /// ADC1 and ADC2 clock enable - ADC12EN: u1, - /// ADC3 and ADC4 clock enable - ADC34EN: u1, - padding: u2, + padding: u26, }), - /// APB2 peripheral clock enable register (RCC_APB2ENR) - APB2ENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved11: u10, - /// TIM1 Timer clock enable - TIM1EN: u1, - /// SPI 1 clock enable - SPI1EN: u1, - /// TIM8 Timer clock enable - TIM8EN: u1, - /// USART1 clock enable - USART1EN: u1, - /// SPI4 clock enable - SPI4EN: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - /// TIM19 timer clock enable - TIM19EN: u1, - /// TIM20 timer clock enable - TIM20EN: u1, - reserved22: u1, - /// MCU debug module clock enable - DBGMCUEN: u1, - reserved29: u6, - /// High Resolution Timer 1 clock enable - HRTIM1EN: u1, - padding: u2, + /// AHB peripheral clock enable register + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + reserved8: u6, + /// Flash memory interface clock enable + FLASHEN: u1, + reserved12: u3, + /// CRC clock enable + CRCEN: u1, + reserved16: u3, + /// AES hardware accelerator + AESEN: u1, + reserved18: u1, + /// Random number generator clock enable + RNGEN: u1, + padding: u13, }), - /// APB1 peripheral clock enable register (RCC_APB1ENR) - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer 2 clock enable + /// APB peripheral clock enable register 1 + APBENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clock enable TIM2EN: u1, - /// Timer 3 clock enable + /// TIM3 timer clock enable TIM3EN: u1, - /// Timer 4 clock enable + /// TIM4 timer clock enable TIM4EN: u1, reserved4: u1, - /// Timer 6 clock enable + /// TIM6 timer clock enable TIM6EN: u1, - /// Timer 7 clock enable + /// TIM7 timer clock enable TIM7EN: u1, - reserved11: u5, - /// Window watchdog clock enable + reserved7: u1, + /// LPUART2 clock enable + LPUART2EN: u1, + /// USART5EN + USART5EN: u1, + /// USART6EN + USART6EN: u1, + /// RTC APB clock enable + RTCAPBEN: u1, + /// WWDG clock enable WWDGEN: u1, - reserved14: u2, - /// SPI 2 clock enable + /// USBEN + FDCANEN: u1, + /// USBEN + USBEN: u1, + /// SPI2 clock enable SPI2EN: u1, - /// SPI 3 clock enable + /// SPI3 clock enable SPI3EN: u1, - reserved17: u1, - /// USART 2 clock enable + /// CRSEN + CRSEN: u1, + /// USART2 clock enable USART2EN: u1, - /// USART 3 clock enable + /// USART3 clock enable USART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// UART5 clock enable - UART5EN: u1, - /// I2C 1 clock enable + /// USART4 clock enable + USART4EN: u1, + /// LPUART1 clock enable + LPUART1EN: u1, + /// I2C1 clock enable I2C1EN: u1, - /// I2C 2 clock enable + /// I2C2 clock enable I2C2EN: u1, - /// USB clock enable - USBEN: u1, - reserved25: u1, - /// CAN clock enable - CANEN: u1, - /// DAC2 interface clock enable - DAC2EN: u1, - reserved28: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, /// I2C3 clock enable I2C3EN: u1, - padding: u1, + /// HDMI CEC clock enable + CECEN: u1, + /// UCPD1 clock enable + UCPD1EN: u1, + /// UCPD2 clock enable + UCPD2EN: u1, + /// Debug support clock enable + DBGEN: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC1 interface clock enable + DAC1EN: u1, + /// LPTIM2 clock enable + LPTIM2EN: u1, + /// LPTIM1 clock enable + LPTIM1EN: u1, }), - /// Backup domain control register (RCC_BDCR) + /// APB peripheral clock enable register 2 + APBENR2: mmio.Mmio(packed struct(u32) { + /// SYSCFG, COMP and VREFBUF clock enable + SYSCFGEN: u1, + reserved11: u10, + /// TIM1 timer clock enable + TIM1EN: u1, + /// SPI1 clock enable + SPI1EN: u1, + reserved14: u1, + /// USART1 clock enable + USART1EN: u1, + /// TIM14 timer clock enable + TIM14EN: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM16 timer clock enable + TIM17EN: u1, + reserved20: u1, + /// ADC clock enable + ADCEN: u1, + padding: u11, + }), + /// GPIO in Sleep mode clock enable register + GPIOSMENR: mmio.Mmio(packed struct(u32) { + /// I/O port A clock enable during Sleep mode + GPIOASMEN: u1, + /// I/O port B clock enable during Sleep mode + GPIOBSMEN: u1, + /// I/O port C clock enable during Sleep mode + GPIOCSMEN: u1, + /// I/O port D clock enable during Sleep mode + GPIODSMEN: u1, + reserved5: u1, + /// I/O port F clock enable during Sleep mode + GPIOFSMEN: u1, + padding: u26, + }), + /// AHB peripheral clock enable in Sleep mode register + AHBSMENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable during Sleep mode + DMA1SMEN: u1, + /// DMA2 clock enable during Sleep mode + DMA2SMEN: u1, + reserved8: u6, + /// Flash memory interface clock enable during Sleep mode + FLASHSMEN: u1, + /// SRAM clock enable during Sleep mode + SRAMSMEN: u1, + reserved12: u2, + /// CRC clock enable during Sleep mode + CRCSMEN: u1, + reserved16: u3, + /// AES hardware accelerator clock enable during Sleep mode + AESSMEN: u1, + reserved18: u1, + /// Random number generator clock enable during Sleep mode + RNGSMEN: u1, + padding: u13, + }), + /// APB peripheral clock enable in Sleep mode register 1 + APBSMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clock enable during Sleep mode + TIM2SMEN: u1, + /// TIM3 timer clock enable during Sleep mode + TIM3SMEN: u1, + /// TIM4 timer clock enable during Sleep mode + TIM4SMEN: u1, + reserved4: u1, + /// TIM6 timer clock enable during Sleep mode + TIM6SMEN: u1, + /// TIM7 timer clock enable during Sleep mode + TIM7SMEN: u1, + reserved7: u1, + /// LPUART2 clock enable + LPUART2SMEN: u1, + /// USART5 clock enable + USART5SMEN: u1, + /// USART6 clock enable + USART6SMEN: u1, + /// RTC APB clock enable during Sleep mode + RTCAPBSMEN: u1, + /// WWDG clock enable during Sleep mode + WWDGSMEN: u1, + /// FDCAN clock enable during Sleep mode + FDCANSMEN: u1, + /// USB clock enable during Sleep mode + USBSMEN: u1, + /// SPI2 clock enable during Sleep mode + SPI2SMEN: u1, + /// SPI3 clock enable during Sleep mode + SPI3SMEN: u1, + /// CRSS clock enable during Sleep mode + CRSSSMEN: u1, + /// USART2 clock enable during Sleep mode + USART2SMEN: u1, + /// USART3 clock enable during Sleep mode + USART3SMEN: u1, + /// USART4 clock enable during Sleep mode + USART4SMEN: u1, + /// LPUART1 clock enable during Sleep mode + LPUART1SMEN: u1, + /// I2C1 clock enable during Sleep mode + I2C1SMEN: u1, + /// I2C2 clock enable during Sleep mode + I2C2SMEN: u1, + /// I2C3 clock enable during Sleep mode + I2C3SMEN: u1, + /// HDMI CEC clock enable during Sleep mode + CECSMEN: u1, + /// UCPD1 clock enable during Sleep mode + UCPD1SMEN: u1, + /// UCPD2 clock enable during Sleep mode + UCPD2SMEN: u1, + /// Debug support clock enable during Sleep mode + DBGSMEN: u1, + /// Power interface clock enable during Sleep mode + PWRSMEN: u1, + /// DAC1 interface clock enable during Sleep mode + DAC1SMEN: u1, + /// Low Power Timer 2 clock enable during Sleep mode + LPTIM2SMEN: u1, + /// Low Power Timer 1 clock enable during Sleep mode + LPTIM1SMEN: u1, + }), + /// APB peripheral clock enable in Sleep mode register 2 + APBSMENR2: mmio.Mmio(packed struct(u32) { + /// SYSCFG, COMP and VREFBUF clock enable during Sleep mode + SYSCFGSMEN: u1, + reserved11: u10, + /// TIM1 timer clock enable during Sleep mode + TIM1SMEN: u1, + /// SPI1 clock enable during Sleep mode + SPI1SMEN: u1, + reserved14: u1, + /// USART1 clock enable during Sleep mode + USART1SMEN: u1, + /// TIM14 timer clock enable during Sleep mode + TIM14SMEN: u1, + /// TIM15 timer clock enable during Sleep mode + TIM15SMEN: u1, + /// TIM16 timer clock enable during Sleep mode + TIM16SMEN: u1, + /// TIM16 timer clock enable during Sleep mode + TIM17SMEN: u1, + reserved20: u1, + /// ADC clock enable during Sleep mode + ADCSMEN: u1, + padding: u11, + }), + /// Peripherals independent clock configuration register + CCIPR: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// USART2 clock source selection + USART2SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// USART3 clock source selection + USART3SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// HDMI CEC clock source selection + CECSEL: packed union { + raw: u1, + value: CECSEL, + }, + reserved8: u1, + /// LPUART2 clock source selection + LPUART2SEL: packed union { + raw: u2, + value: LPUART2SEL, + }, + /// LPUART1 clock source selection + LPUART1SEL: packed union { + raw: u2, + value: LPUART1SEL, + }, + /// I2C1 clock source selection + I2C1SEL: packed union { + raw: u2, + value: I2C1SEL, + }, + /// I2C2 or I2S1 clock source selection + I2C2I2S1SEL: packed union { + raw: u2, + value: I2C2I2S1SEL, + }, + reserved18: u2, + /// LPTIM1 clock source selection + LPTIM1SEL: packed union { + raw: u2, + value: LPTIM1SEL, + }, + /// LPTIM2 clock source selection + LPTIM2SEL: packed union { + raw: u2, + value: LPTIM2SEL, + }, + /// TIM1 clock source selection + TIM1SEL: packed union { + raw: u1, + value: TIM1SEL, + }, + reserved24: u1, + /// TIM15 clock source selection + TIM15SEL: packed union { + raw: u1, + value: TIM15SEL, + }, + reserved26: u1, + /// RNG clock source selection + RNGSEL: packed union { + raw: u2, + value: RNGSEL, + }, + /// Division factor of RNG clock divider + RNGDIV: packed union { + raw: u2, + value: RNGDIV, + }, + /// ADCs clock source selection + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, + }), + /// Peripherals independent clock configuration register 2 + CCIPR2: mmio.Mmio(packed struct(u32) { + /// I2S1SEL + I2S1SEL: packed union { + raw: u2, + value: I2S1SEL, + }, + /// I2S2SEL + I2S2SEL: packed union { + raw: u2, + value: I2S2SEL, + }, + reserved8: u4, + /// FDCANSEL + FDCANSEL: packed union { + raw: u2, + value: FDCANSEL, + }, + reserved12: u2, + /// USBSEL + USBSEL: packed union { + raw: u2, + value: USBSEL, + }, + padding: u18, + }), + /// RTC domain control register BDCR: mmio.Mmio(packed struct(u32) { - /// External Low Speed oscillator enable + /// LSE oscillator enable LSEON: u1, - /// External Low Speed oscillator ready + /// LSE oscillator ready LSERDY: u1, - /// External Low Speed oscillator bypass + /// LSE oscillator bypass LSEBYP: u1, /// LSE oscillator drive capability LSEDRV: packed union { raw: u2, value: LSEDRV, }, - reserved8: u3, + /// CSS on LSE enable + LSECSSON: u1, + /// CSS on LSE failure Detection + LSECSSD: u1, + reserved8: u1, /// RTC clock source selection RTCSEL: packed union { raw: u2, @@ -398796,6224 +380229,6001 @@ pub const types = struct { reserved15: u5, /// RTC clock enable RTCEN: u1, - /// Backup domain software reset + /// RTC domain software reset BDRST: u1, - padding: u15, + reserved24: u7, + /// Low-speed clock output (LSCO) enable + LSCOEN: u1, + /// Low-speed clock output selection + LSCOSEL: u1, + padding: u6, }), - /// Control/status register (RCC_CSR) + /// Control/status register CSR: mmio.Mmio(packed struct(u32) { - /// Internal low speed oscillator enable + /// LSI oscillator enable LSION: u1, - /// Internal low speed oscillator ready + /// LSI oscillator ready LSIRDY: u1, reserved23: u21, - /// Reset flag of the 1.8 V domain - V18PWRRSTF: u1, - /// Remove reset flag + /// Remove reset flags RMVF: u1, + reserved25: u1, /// Option byte loader reset flag OBLRSTF: u1, - /// PIN reset flag + /// Pin reset flag PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, + /// BOR or POR/PDR flag + PWRRSTF: u1, /// Software reset flag SFTRSTF: u1, - /// Independent watchdog reset flag + /// Independent window watchdog reset flag IWDGRSTF: u1, /// Window watchdog reset flag WWDGRSTF: u1, /// Low-power reset flag LPWRRSTF: u1, }), - /// AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// FMC reset - FMCRST: u1, - reserved16: u10, - /// IO port H reset - GPIOHRST: u1, - /// I/O port A reset - GPIOARST: u1, - /// I/O port B reset - GPIOBRST: u1, - /// I/O port C reset - GPIOCRST: u1, - /// I/O port D reset - GPIODRST: u1, - /// I/O port E reset - GPIOERST: u1, - /// I/O port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// Touch sensing controller reset - TSCRST: u1, - reserved28: u3, - /// ADC1 and ADC2 reset - ADC12RST: u1, - /// ADC3 and ADC4 reset - ADC34RST: u1, - padding: u2, + }; + }; + + pub const rcc_g4 = struct { + pub const ADCSEL = enum(u2) { + /// No clock selected + DISABLE = 0x0, + /// PLL 'P' clock selected as ADC clock + PLL1_P = 0x1, + /// System clock selected as ADC clock + SYS = 0x2, + _, + }; + + pub const CLK48SEL = enum(u2) { + /// HSI48 oscillator clock selected as 48 MHz clock + HSI48 = 0x0, + /// PLLQCLK selected as 48 MHz clock + PLL1_Q = 0x2, + _, + }; + + pub const FDCANSEL = enum(u2) { + /// HSE used as FDCAN clock source + HSE = 0x0, + /// PLLQCLK used as FDCAN clock source + PLL1_Q = 0x1, + /// PCLK used as FDCAN clock source + PCLK1 = 0x2, + _, + }; + + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK is divided by 2 + Div2 = 0x8, + /// SYSCLK is divided by 4 + Div4 = 0x9, + /// SYSCLK is divided by 8 + Div8 = 0xa, + /// SYSCLK is divided by 16 + Div16 = 0xb, + /// SYSCLK is divided by 64 + Div64 = 0xc, + /// SYSCLK is divided by 128 + Div128 = 0xd, + /// SYSCLK is divided by 256 + Div256 = 0xe, + /// SYSCLK is divided by 512 + Div512 = 0xf, + _, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const MCOPRE = enum(u3) { + /// MCO1 not divided + Div1 = 0x0, + /// MCO clock is divided by 2 + Div2 = 0x1, + /// MCO clock is divided by 4 + Div4 = 0x2, + /// MCO clock is divided by 8 + Div8 = 0x3, + /// MCO clock is divided divided by 16 + Div16 = 0x4, + _, + }; + + pub const MCOSEL = enum(u4) { + /// No clock, MCO output disabled + DISABLE = 0x0, + /// SYSCLK selected as MCO source + SYS = 0x1, + /// HSI selected as MCO source + HSI = 0x3, + /// HSE selected as MCO source + HSE = 0x4, + /// Main PLLCLK selected as MCO source + PLLCLK = 0x5, + /// LSI selected as MCO source + LSI = 0x6, + /// LSE selected as MCO source + LSE = 0x7, + /// HSI48 selected as MCO source + HSI48 = 0x8, + _, + }; + + pub const PLLM = enum(u4) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + }; + + pub const PLLN = enum(u7) { + Mul8 = 0x8, + Mul9 = 0x9, + Mul10 = 0xa, + Mul11 = 0xb, + Mul12 = 0xc, + Mul13 = 0xd, + Mul14 = 0xe, + Mul15 = 0xf, + Mul16 = 0x10, + Mul17 = 0x11, + Mul18 = 0x12, + Mul19 = 0x13, + Mul20 = 0x14, + Mul21 = 0x15, + Mul22 = 0x16, + Mul23 = 0x17, + Mul24 = 0x18, + Mul25 = 0x19, + Mul26 = 0x1a, + Mul27 = 0x1b, + Mul28 = 0x1c, + Mul29 = 0x1d, + Mul30 = 0x1e, + Mul31 = 0x1f, + Mul32 = 0x20, + Mul33 = 0x21, + Mul34 = 0x22, + Mul35 = 0x23, + Mul36 = 0x24, + Mul37 = 0x25, + Mul38 = 0x26, + Mul39 = 0x27, + Mul40 = 0x28, + Mul41 = 0x29, + Mul42 = 0x2a, + Mul43 = 0x2b, + Mul44 = 0x2c, + Mul45 = 0x2d, + Mul46 = 0x2e, + Mul47 = 0x2f, + Mul48 = 0x30, + Mul49 = 0x31, + Mul50 = 0x32, + Mul51 = 0x33, + Mul52 = 0x34, + Mul53 = 0x35, + Mul54 = 0x36, + Mul55 = 0x37, + Mul56 = 0x38, + Mul57 = 0x39, + Mul58 = 0x3a, + Mul59 = 0x3b, + Mul60 = 0x3c, + Mul61 = 0x3d, + Mul62 = 0x3e, + Mul63 = 0x3f, + Mul64 = 0x40, + Mul65 = 0x41, + Mul66 = 0x42, + Mul67 = 0x43, + Mul68 = 0x44, + Mul69 = 0x45, + Mul70 = 0x46, + Mul71 = 0x47, + Mul72 = 0x48, + Mul73 = 0x49, + Mul74 = 0x4a, + Mul75 = 0x4b, + Mul76 = 0x4c, + Mul77 = 0x4d, + Mul78 = 0x4e, + Mul79 = 0x4f, + Mul80 = 0x50, + Mul81 = 0x51, + Mul82 = 0x52, + Mul83 = 0x53, + Mul84 = 0x54, + Mul85 = 0x55, + Mul86 = 0x56, + Mul87 = 0x57, + Mul88 = 0x58, + Mul89 = 0x59, + Mul90 = 0x5a, + Mul91 = 0x5b, + Mul92 = 0x5c, + Mul93 = 0x5d, + Mul94 = 0x5e, + Mul95 = 0x5f, + Mul96 = 0x60, + Mul97 = 0x61, + Mul98 = 0x62, + Mul99 = 0x63, + Mul100 = 0x64, + Mul101 = 0x65, + Mul102 = 0x66, + Mul103 = 0x67, + Mul104 = 0x68, + Mul105 = 0x69, + Mul106 = 0x6a, + Mul107 = 0x6b, + Mul108 = 0x6c, + Mul109 = 0x6d, + Mul110 = 0x6e, + Mul111 = 0x6f, + Mul112 = 0x70, + Mul113 = 0x71, + Mul114 = 0x72, + Mul115 = 0x73, + Mul116 = 0x74, + Mul117 = 0x75, + Mul118 = 0x76, + Mul119 = 0x77, + Mul120 = 0x78, + Mul121 = 0x79, + Mul122 = 0x7a, + Mul123 = 0x7b, + Mul124 = 0x7c, + Mul125 = 0x7d, + Mul126 = 0x7e, + Mul127 = 0x7f, + _, + }; + + pub const PLLP = enum(u5) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + Div16 = 0x10, + Div17 = 0x11, + Div18 = 0x12, + Div19 = 0x13, + Div20 = 0x14, + Div21 = 0x15, + Div22 = 0x16, + Div23 = 0x17, + Div24 = 0x18, + Div25 = 0x19, + Div26 = 0x1a, + Div27 = 0x1b, + Div28 = 0x1c, + Div29 = 0x1d, + Div30 = 0x1e, + Div31 = 0x1f, + _, + }; + + pub const PLLPBIT = enum(u1) { + Div7 = 0x0, + Div17 = 0x1, + }; + + pub const PLLQ = enum(u2) { + Div2 = 0x0, + Div4 = 0x1, + Div6 = 0x2, + Div8 = 0x3, + }; + + pub const PLLR = enum(u2) { + Div2 = 0x0, + Div4 = 0x1, + Div6 = 0x2, + Div8 = 0x3, + }; + + pub const PLLSRC = enum(u2) { + /// No clock selected as PLL entry clock source + DISABLE = 0x0, + /// HSI selected as PLL entry clock source + HSI = 0x2, + /// HSE selected as PLL entry clock source + HSE = 0x3, + _, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK is divided by 2 + Div2 = 0x4, + /// HCLK is divided by 4 + Div4 = 0x5, + /// HCLK is divided by 8 + Div8 = 0x6, + /// HCLK is divided by 16 + Div16 = 0x7, + _, + }; + + pub const RTCSEL = enum(u2) { + /// No clock used as RTC clock + DISABLE = 0x0, + /// LSE used as RTC clock + LSE = 0x1, + /// LSI used as RTC clock + LSI = 0x2, + /// HSE divided by 32 used as RTC clock + HSE_Div32 = 0x3, + }; + + pub const SW = enum(u2) { + /// HSI selected as system clock + HSI = 0x1, + /// HSE selected as system clock + HSE = 0x2, + /// PLLRCLK selected as system clock + PLL1_R = 0x3, + _, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// HSI clock enable + HSION: u1, + /// HSI always enable for peripheral kernels + HSIKERON: u1, + /// HSI clock ready flag + HSIRDY: u1, + reserved16: u5, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE crystal oscillator bypass + HSEBYP: u1, + /// Clock security system enable + CSSON: u1, + reserved24: u4, + /// Main PLL enable + PLLON: u1, + /// Main PLL clock ready flag + PLLRDY: u1, + padding: u6, }), - /// Clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// PREDIV division factor - PREDIV: packed union { - raw: u4, - value: PREDIV, - }, - /// ADC1 and ADC2 prescaler - ADC12PRES: packed union { - raw: u5, - value: ADCPRES, - }, - /// ADC3 and ADC4 prescaler - ADC34PRES: packed union { - raw: u5, - value: ADCPRES, - }, - padding: u18, + /// Internal clock sources calibration register + ICSCR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Internal High Speed clock Calibration + HSICAL0: u8, + /// Internal High Speed clock trimming + HSITRIM: u7, + padding: u1, }), - /// Clock configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SW: packed union { + /// Clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { raw: u2, - value: USART1SW, + value: SW, }, - reserved4: u2, - /// I2C1 clock source selection - I2C1SW: packed union { - raw: u1, - value: ICSW, + /// System clock switch status + SWS: packed union { + raw: u2, + value: SW, }, - /// I2C2 clock source selection - I2C2SW: packed union { - raw: u1, - value: ICSW, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, }, - /// HDMI CEC clock source selection - CECSW: packed union { - raw: u1, - value: CECSW, + /// PB low-speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, }, - reserved8: u1, - /// Timer1 clock source selection - TIM1SW: packed union { - raw: u1, - value: TIMSW, + /// APB high-speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, }, - /// Timer8 clock source selection - TIM8SW: packed union { - raw: u1, - value: TIMSW, + reserved24: u10, + /// Microcontroller clock output + MCOSEL: packed union { + raw: u4, + value: MCOSEL, }, - /// Timer15 clock source selection - TIM15SW: packed union { - raw: u1, - value: TIMSW, + /// Microcontroller clock output prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, }, - /// Timer16 clock source selection - TIM16SW: packed union { - raw: u1, - value: TIMSW, + padding: u1, + }), + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// Main PLL, PLLSAI1 and PLLSAI2 entry clock source + PLLSRC: packed union { + raw: u2, + value: PLLSRC, }, - /// Hrtim1 clock source selection - HRTIM1SW: packed union { - raw: u1, - value: TIMSW, + reserved4: u2, + /// Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + PLLM: packed union { + raw: u4, + value: PLLM, }, - /// Timer17 clock source selection - TIM17SW: packed union { - raw: u1, - value: TIMSW, + /// Main PLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, }, - reserved15: u1, - /// Timer20 clock source selection - TIM20SW: packed union { + reserved16: u1, + /// Main PLL PLLSAI3CLK output enable + PLLPEN: u1, + /// Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + PLLPBIT: packed union { raw: u1, - value: TIMSW, - }, - /// USART2 clock source selection - USART2SW: packed union { - raw: u2, - value: USARTSW, - }, - /// USART3 clock source selection - USART3SW: packed union { - raw: u2, - value: USARTSW, + value: PLLPBIT, }, - /// UART4 clock source selection - UART4SW: packed union { + reserved20: u2, + /// Main PLL PLLUSB1CLK output enable + PLLQEN: u1, + /// Main PLL division factor for PLLUSB1CLK(48 MHz clock) + PLLQ: packed union { raw: u2, - value: USARTSW, + value: PLLQ, }, - /// UART5 clock source selection - UART5SW: packed union { + reserved24: u1, + /// Main PLL PLLCLK output enable + PLLREN: u1, + /// Main PLL division factor for PLLCLK (system clock) + PLLR: packed union { raw: u2, - value: USARTSW, - }, - /// Timer2 clock source selection - TIM2SW: packed union { - raw: u1, - value: TIM2SW, + value: PLLR, }, - /// Timer34 clock source selection - TIM34SW: packed union { - raw: u1, - value: TIMSW, + /// Main PLL division factor for PLLSAI2CLK + PLLP: packed union { + raw: u5, + value: PLLP, }, - padding: u6, - }), - }; - }; - - pub const tsc_v3 = struct { - /// Touch sensing controller. - pub const TSC = extern struct { - /// control register. - CR: mmio.Mmio(packed struct(u32) { - /// Touch sensing controller enable. - TSCE: u1, - /// Start a new acquisition. - START: u1, - /// Acquisition mode. - AM: u1, - /// Synchronization pin polarity. - SYNCPOL: u1, - /// I/O Default mode. - IODEF: u1, - /// Max count value. - MCV: u3, - reserved12: u4, - /// pulse generator prescaler. - PGPSC: u3, - /// Spread spectrum prescaler. - SSPSC: u1, - /// Spread spectrum enable. - SSE: u1, - /// Spread spectrum deviation. - SSD: u7, - /// Charge transfer pulse low. - CTPL: u4, - /// Charge transfer pulse high. - CTPH: u4, - }), - /// interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// End of acquisition interrupt enable. - EOAIE: u1, - /// Max count error interrupt enable. - MCEIE: u1, - padding: u30, }), - /// interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// End of acquisition interrupt clear. - EOAIC: u1, - /// Max count error interrupt clear. - MCEIC: u1, - padding: u30, - }), - /// interrupt status register. - ISR: mmio.Mmio(packed struct(u32) { - /// End of acquisition flag. - EOAF: u1, - /// Max count error flag. - MCEF: u1, - padding: u30, - }), - /// I/O hysteresis control register. - IOHCR: mmio.Mmio(packed struct(u32) { - /// G1_IO1 Schmitt trigger hysteresis mode. - G1_IO1: u1, - /// G1_IO2 Schmitt trigger hysteresis mode. - G1_IO2: u1, - /// G1_IO3 Schmitt trigger hysteresis mode. - G1_IO3: u1, - /// G1_IO4 Schmitt trigger hysteresis mode. - G1_IO4: u1, - /// G2_IO1 Schmitt trigger hysteresis mode. - G2_IO1: u1, - /// G2_IO2 Schmitt trigger hysteresis mode. - G2_IO2: u1, - /// G2_IO3 Schmitt trigger hysteresis mode. - G2_IO3: u1, - /// G2_IO4 Schmitt trigger hysteresis mode. - G2_IO4: u1, - /// G3_IO1 Schmitt trigger hysteresis mode. - G3_IO1: u1, - /// G3_IO2 Schmitt trigger hysteresis mode. - G3_IO2: u1, - /// G3_IO3 Schmitt trigger hysteresis mode. - G3_IO3: u1, - /// G3_IO4 Schmitt trigger hysteresis mode. - G3_IO4: u1, - /// G4_IO1 Schmitt trigger hysteresis mode. - G4_IO1: u1, - /// G4_IO2 Schmitt trigger hysteresis mode. - G4_IO2: u1, - /// G4_IO3 Schmitt trigger hysteresis mode. - G4_IO3: u1, - /// G4_IO4 Schmitt trigger hysteresis mode. - G4_IO4: u1, - /// G5_IO1 Schmitt trigger hysteresis mode. - G5_IO1: u1, - /// G5_IO2 Schmitt trigger hysteresis mode. - G5_IO2: u1, - /// G5_IO3 Schmitt trigger hysteresis mode. - G5_IO3: u1, - /// G5_IO4 Schmitt trigger hysteresis mode. - G5_IO4: u1, - /// G6_IO1 Schmitt trigger hysteresis mode. - G6_IO1: u1, - /// G6_IO2 Schmitt trigger hysteresis mode. - G6_IO2: u1, - /// G6_IO3 Schmitt trigger hysteresis mode. - G6_IO3: u1, - /// G6_IO4 Schmitt trigger hysteresis mode. - G6_IO4: u1, - /// G7_IO1 Schmitt trigger hysteresis mode. - G7_IO1: u1, - /// G7_IO2 Schmitt trigger hysteresis mode. - G7_IO2: u1, - /// G7_IO3 Schmitt trigger hysteresis mode. - G7_IO3: u1, - /// G7_IO4 Schmitt trigger hysteresis mode. - G7_IO4: u1, - /// G8_IO1 Schmitt trigger hysteresis mode. - G8_IO1: u1, - /// G8_IO2 Schmitt trigger hysteresis mode. - G8_IO2: u1, - /// G8_IO3 Schmitt trigger hysteresis mode. - G8_IO3: u1, - /// G8_IO4 Schmitt trigger hysteresis mode. - G8_IO4: u1, + reserved24: [8]u8, + /// Clock interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + reserved3: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// PLL ready interrupt enable + PLLRDYIE: u1, + reserved9: u3, + /// LSE clock security system interrupt enable + LSECSSIE: u1, + /// HSI48 ready interrupt enable + HSI48RDYIE: u1, + padding: u21, }), - reserved24: [4]u8, - /// I/O analog switch control register. - IOASCR: mmio.Mmio(packed struct(u32) { - /// G1_IO1 analog switch enable. - G1_IO1: u1, - /// G1_IO2 analog switch enable. - G1_IO2: u1, - /// G1_IO3 analog switch enable. - G1_IO3: u1, - /// G1_IO4 analog switch enable. - G1_IO4: u1, - /// G2_IO1 analog switch enable. - G2_IO1: u1, - /// G2_IO2 analog switch enable. - G2_IO2: u1, - /// G2_IO3 analog switch enable. - G2_IO3: u1, - /// G2_IO4 analog switch enable. - G2_IO4: u1, - /// G3_IO1 analog switch enable. - G3_IO1: u1, - /// G3_IO2 analog switch enable. - G3_IO2: u1, - /// G3_IO3 analog switch enable. - G3_IO3: u1, - /// G3_IO4 analog switch enable. - G3_IO4: u1, - /// G4_IO1 analog switch enable. - G4_IO1: u1, - /// G4_IO2 analog switch enable. - G4_IO2: u1, - /// G4_IO3 analog switch enable. - G4_IO3: u1, - /// G4_IO4 analog switch enable. - G4_IO4: u1, - /// G5_IO1 analog switch enable. - G5_IO1: u1, - /// G5_IO2 analog switch enable. - G5_IO2: u1, - /// G5_IO3 analog switch enable. - G5_IO3: u1, - /// G5_IO4 analog switch enable. - G5_IO4: u1, - /// G6_IO1 analog switch enable. - G6_IO1: u1, - /// G6_IO2 analog switch enable. - G6_IO2: u1, - /// G6_IO3 analog switch enable. - G6_IO3: u1, - /// G6_IO4 analog switch enable. - G6_IO4: u1, - /// G7_IO1 analog switch enable. - G7_IO1: u1, - /// G7_IO2 analog switch enable. - G7_IO2: u1, - /// G7_IO3 analog switch enable. - G7_IO3: u1, - /// G7_IO4 analog switch enable. - G7_IO4: u1, - /// G8_IO1 analog switch enable. - G8_IO1: u1, - /// G8_IO2 analog switch enable. - G8_IO2: u1, - /// G8_IO3 analog switch enable. - G8_IO3: u1, - /// G8_IO4 analog switch enable. - G8_IO4: u1, + /// Clock interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + reserved3: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// PLL ready interrupt flag + PLLRDYF: u1, + reserved8: u2, + /// Clock security system interrupt flag + CSSF: u1, + /// LSE Clock security system interrupt flag + LSECSSF: u1, + /// HSI48 ready interrupt flag + HSI48RDYF: u1, + padding: u21, }), - reserved32: [4]u8, - /// I/O sampling control register. - IOSCR: mmio.Mmio(packed struct(u32) { - /// G1_IO1 sampling mode. - G1_IO1: u1, - /// G1_IO2 sampling mode. - G1_IO2: u1, - /// G1_IO3 sampling mode. - G1_IO3: u1, - /// G1_IO4 sampling mode. - G1_IO4: u1, - /// G2_IO1 sampling mode. - G2_IO1: u1, - /// G2_IO2 sampling mode. - G2_IO2: u1, - /// G2_IO3 sampling mode. - G2_IO3: u1, - /// G2_IO4 sampling mode. - G2_IO4: u1, - /// G3_IO1 sampling mode. - G3_IO1: u1, - /// G3_IO2 sampling mode. - G3_IO2: u1, - /// G3_IO3 sampling mode. - G3_IO3: u1, - /// G3_IO4 sampling mode. - G3_IO4: u1, - /// G4_IO1 sampling mode. - G4_IO1: u1, - /// G4_IO2 sampling mode. - G4_IO2: u1, - /// G4_IO3 sampling mode. - G4_IO3: u1, - /// G4_IO4 sampling mode. - G4_IO4: u1, - /// G5_IO1 sampling mode. - G5_IO1: u1, - /// G5_IO2 sampling mode. - G5_IO2: u1, - /// G5_IO3 sampling mode. - G5_IO3: u1, - /// G5_IO4 sampling mode. - G5_IO4: u1, - /// G6_IO1 sampling mode. - G6_IO1: u1, - /// G6_IO2 sampling mode. - G6_IO2: u1, - /// G6_IO3 sampling mode. - G6_IO3: u1, - /// G6_IO4 sampling mode. - G6_IO4: u1, - /// G7_IO1 sampling mode. - G7_IO1: u1, - /// G7_IO2 sampling mode. - G7_IO2: u1, - /// G7_IO3 sampling mode. - G7_IO3: u1, - /// G7_IO4 sampling mode. - G7_IO4: u1, - /// G8_IO1 sampling mode. - G8_IO1: u1, - /// G8_IO2 sampling mode. - G8_IO2: u1, - /// G8_IO3 sampling mode. - G8_IO3: u1, - /// G8_IO4 sampling mode. - G8_IO4: u1, + /// Clock interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + reserved3: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// PLL ready interrupt clear + PLLRDYC: u1, + reserved8: u2, + /// Clock security system interrupt clear + CSSC: u1, + /// LSE Clock security system interrupt clear + LSECSSC: u1, + /// HSI48 oscillator ready interrupt clear + HSI48RDYC: u1, + padding: u21, }), reserved40: [4]u8, - /// I/O channel control register. - IOCCR: mmio.Mmio(packed struct(u32) { - /// G1_IO1 channel mode. - G1_IO1: u1, - /// G1_IO2 channel mode. - G1_IO2: u1, - /// G1_IO3 channel mode. - G1_IO3: u1, - /// G1_IO4 channel mode. - G1_IO4: u1, - /// G2_IO1 channel mode. - G2_IO1: u1, - /// G2_IO2 channel mode. - G2_IO2: u1, - /// G2_IO3 channel mode. - G2_IO3: u1, - /// G2_IO4 channel mode. - G2_IO4: u1, - /// G3_IO1 channel mode. - G3_IO1: u1, - /// G3_IO2 channel mode. - G3_IO2: u1, - /// G3_IO3 channel mode. - G3_IO3: u1, - /// G3_IO4 channel mode. - G3_IO4: u1, - /// G4_IO1 channel mode. - G4_IO1: u1, - /// G4_IO2 channel mode. - G4_IO2: u1, - /// G4_IO3 channel mode. - G4_IO3: u1, - /// G4_IO4 channel mode. - G4_IO4: u1, - /// G5_IO1 channel mode. - G5_IO1: u1, - /// G5_IO2 channel mode. - G5_IO2: u1, - /// G5_IO3 channel mode. - G5_IO3: u1, - /// G5_IO4 channel mode. - G5_IO4: u1, - /// G6_IO1 channel mode. - G6_IO1: u1, - /// G6_IO2 channel mode. - G6_IO2: u1, - /// G6_IO3 channel mode. - G6_IO3: u1, - /// G6_IO4 channel mode. - G6_IO4: u1, - /// G7_IO1 channel mode. - G7_IO1: u1, - /// G7_IO2 channel mode. - G7_IO2: u1, - /// G7_IO3 channel mode. - G7_IO3: u1, - /// G7_IO4 channel mode. - G7_IO4: u1, - /// G8_IO1 channel mode. - G8_IO1: u1, - /// G8_IO2 channel mode. - G8_IO2: u1, - /// G8_IO3 channel mode. - G8_IO3: u1, - /// G8_IO4 channel mode. - G8_IO4: u1, - }), - reserved48: [4]u8, - /// I/O group control status register. - IOGCSR: mmio.Mmio(packed struct(u32) { - /// Analog I/O group x enable. - G1E: u1, - /// Analog I/O group x enable. - G2E: u1, - /// Analog I/O group x enable. - G3E: u1, - /// Analog I/O group x enable. - G4E: u1, - /// Analog I/O group x enable. - G5E: u1, - /// Analog I/O group x enable. - G6E: u1, - /// Analog I/O group x enable. - G7E: u1, - /// Analog I/O group x enable. - G8E: u1, - reserved16: u8, - /// Analog I/O group x status. - G1S: u1, - /// Analog I/O group x status. - G2S: u1, - /// Analog I/O group x status. - G3S: u1, - /// Analog I/O group x status. - G4S: u1, - /// Analog I/O group x status. - G5S: u1, - /// Analog I/O group x status. - G6S: u1, - /// Analog I/O group x status. - G7S: u1, - /// Analog I/O group x status. - G8S: u1, - padding: u8, - }), - /// I/O group x counter register. - IOGCR: [8]mmio.Mmio(packed struct(u32) { - /// Counter value. - CNT: u14, - padding: u18, - }), - }; - }; - - pub const flash_f2 = struct { - pub const LATENCY = enum(u3) { - /// 0 wait states - WS0 = 0x0, - /// 1 wait states - WS1 = 0x1, - /// 2 wait states - WS2 = 0x2, - /// 3 wait states - WS3 = 0x3, - /// 4 wait states - WS4 = 0x4, - /// 5 wait states - WS5 = 0x5, - /// 6 wait states - WS6 = 0x6, - /// 7 wait states - WS7 = 0x7, - }; - - pub const PSIZE = enum(u2) { - /// Program x8 - PSIZE8 = 0x0, - /// Program x16 - PSIZE16 = 0x1, - /// Program x32 - PSIZE32 = 0x2, - /// Program x64 - PSIZE64 = 0x3, - }; - - /// FLASH - pub const FLASH = extern struct { - /// Flash access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: packed union { - raw: u3, - value: LATENCY, - }, - reserved8: u5, - /// Prefetch enable - PRFTEN: u1, - /// Instruction cache enable - ICEN: u1, - /// Data cache enable - DCEN: u1, - /// Instruction cache reset - ICRST: u1, - /// Data cache reset - DCRST: u1, + /// AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// DMA1 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + /// DMAMUX1RST + DMAMUX1RST: u1, + /// CORDIC reset + CORDICRST: u1, + /// FMAC reset + FMACRST: u1, + reserved8: u3, + /// Flash memory interface reset + FLASHRST: u1, + reserved12: u3, + /// CRC reset + CRCRST: u1, padding: u19, }), - /// Flash key register - KEYR: u32, - /// Flash option key register - OPTKEYR: u32, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved4: u2, - /// Write protection error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Programming parallelism error - PGPERR: u1, - /// Programming sequence error - PGSERR: u1, - reserved16: u8, - /// Busy - BSY: u1, - padding: u15, - }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Sector Erase - SER: u1, - /// Mass Erase - MER: u1, - /// Sector number - SNB: u4, - reserved8: u1, - /// Program size - PSIZE: packed union { - raw: u2, - value: PSIZE, - }, - reserved16: u6, - /// Start - STRT: u1, - reserved24: u7, - /// End of operation interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - reserved31: u5, - /// Lock - LOCK: u1, + /// AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + reserved13: u6, + /// ADC reset + ADC12RST: u1, + /// SAR ADC345 interface reset + ADC345RST: u1, + reserved16: u1, + /// DAC1 interface reset + DAC1RST: u1, + /// DAC2 interface reset + DAC2RST: u1, + /// DAC3 interface reset + DAC3RST: u1, + /// DAC4 interface reset + DAC4RST: u1, + reserved24: u4, + /// Cryptography module reset + AESRST: u1, + reserved26: u1, + /// Random Number Generator module reset + RNGRST: u1, + padding: u5, }), - /// Flash option control register - OPTCR: mmio.Mmio(packed struct(u32) { - /// Option lock - OPTLOCK: u1, - /// Option start - OPTSTRT: u1, - /// BOR reset Level - BOR_LEV: u2, - reserved5: u1, - /// WDG_SW User option bytes - WDG_SW: u1, - /// nRST_STOP User option bytes - nRST_STOP: u1, - /// nRST_STDBY User option bytes - nRST_STDBY: u1, - /// Read protect - RDP: u8, - /// Not write protect - nWRP: u12, - padding: u4, + /// AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller reset + FMCRST: u1, + reserved8: u7, + /// Quad SPI 1 module reset + QUADSPIRST: u1, + padding: u23, }), - }; - }; - - pub const dac_v6 = struct { - pub const MODE = enum(u3) { - /// Normal mode, external pin only, buffer enabled - NORMAL_EXT_BUFEN = 0x0, - /// Normal mode, external pin and internal peripherals, buffer enabled - NORMAL_EXT_INT_BUFEN = 0x1, - /// Normal mode, external pin only, buffer disabled - NORMAL_EXT_BUFDIS = 0x2, - /// Normal mode, internal peripherals only, buffer disabled - NORMAL_INT_BUFDIS = 0x3, - /// Sample and hold mode, external pin only, buffer enabled - SAMPHOLD_EXT_BUFEN = 0x4, - /// Sample and hold mode, external pin and internal peripherals, buffer enabled - SAMPHOLD_EXT_INT_BUFEN = 0x5, - /// Sample and hold mode, external pin and internal peripherals, buffer disabled - SAMPHOLD_EXT_INT_BUFDIS = 0x6, - /// Sample and hold mode, internal peripherals only, buffer disabled - SAMPHOLD_INT_BUFDIS = 0x7, - }; - - pub const WAVE = enum(u2) { - /// Wave generation disabled - Disabled = 0x0, - /// Noise wave generation enabled - Noise = 0x1, - /// Triangle wave generation enabled - Triangle = 0x2, - _, - }; - - /// Digital-to-analog converter - pub const DAC = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u4, - /// channel noise/triangle wave generation enable - WAVE: packed union { - raw: u2, - value: WAVE, - }, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - /// channel DMA Underrun Interrupt enable - DMAUDRIE: u1, - /// DAC channel calibration enable - CEN: u1, - padding: u17, + reserved56: [4]u8, + /// APB1 peripheral reset register 1 + APB1RSTR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer reset + TIM2RST: u1, + /// TIM3 timer reset + TIM3RST: u1, + /// TIM3 timer reset + TIM4RST: u1, + /// TIM5 timer reset + TIM5RST: u1, + /// TIM6 timer reset + TIM6RST: u1, + /// TIM7 timer reset + TIM7RST: u1, + reserved8: u2, + /// Clock recovery system reset + CRSRST: u1, + reserved14: u5, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved17: u1, + /// USART2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// UART4 reset + UART4RST: u1, + /// UART5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USBD reset + USBRST: u1, + reserved25: u1, + /// FDCAN reset + FDCANRST: u1, + reserved28: u2, + /// Power interface reset + PWRRST: u1, + reserved30: u1, + /// I2C3 interface reset + I2C3RST: u1, + /// Low Power Timer 1 reset + LPTIM1RST: u1, }), - /// software trigger register - SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - reserved16: u15, - /// channel software trigger B - SWTRIGB: u1, - padding: u15, + /// APB1 peripheral reset register 2 + APB1RSTR2: mmio.Mmio(packed struct(u32) { + /// Low-power UART 1 reset + LPUART1RST: u1, + /// I2C4 reset + I2C4RST: u1, + reserved8: u6, + /// UCPD1 reset + UCPD1RST: u1, + padding: u23, }), - /// channel 12-bit right-aligned data holding register - DHR12R: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - reserved16: u4, - /// channel 12-bit right-aligned data B - DHRB: u12, - padding: u4, + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// System configuration (SYSCFG) reset + SYSCFGRST: u1, + reserved11: u10, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + /// SPI 4 reset + SPI4RST: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + reserved20: u1, + /// Timer 20 reset + TIM20RST: u1, + /// Serial audio interface 1 (SAI1) reset + SAI1RST: u1, + reserved26: u4, + /// HRTIMER reset + HRTIM1RST: u1, + padding: u5, }), - /// channel 12-bit left-aligned data holding register - DHR12L: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - reserved20: u4, - /// channel 12-bit left-aligned data B - DHRB: u12, + reserved72: [4]u8, + /// AHB1 peripheral clock enable register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// DMAMUX clock enable + DMAMUX1EN: u1, + /// CORDIC clock enable + CORDICEN: u1, + /// FMAC clock enable + FMACEN: u1, + reserved8: u3, + /// Flash memory interface clock enable + FLASHEN: u1, + reserved12: u3, + /// CRC clock enable + CRCEN: u1, + padding: u19, }), - /// channel 8-bit right-aligned data holding register - DHR8R: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - /// channel 8-bit right-aligned data B - DHRB: u8, - padding: u16, + /// AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + reserved13: u6, + /// ADC clock enable + ADC12EN: u1, + /// DCMI clock enable + ADC345EN: u1, + reserved16: u1, + /// AES accelerator clock enable + DAC1EN: u1, + /// HASH clock enable + DAC2EN: u1, + /// Random Number Generator clock enable + DAC3EN: u1, + /// DAC4 clock enable + DAC4EN: u1, + reserved24: u4, + /// AES clock enable + AESEN: u1, + reserved26: u1, + /// Random Number Generator clock enable + RNGEN: u1, + padding: u5, }), - reserved32: [12]u8, - /// dual 12-bit right-aligned data holding register - DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller clock enable + FMCEN: u1, + reserved8: u7, + /// QUADSPI memory interface clock enable + QUADSPIEN: u1, + padding: u23, }), - /// dual 12-bit left aligned data holding register - DHR12LD: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + reserved88: [4]u8, + /// APB1ENR1 + APB1ENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clock enable + TIM2EN: u1, + /// TIM3 timer clock enable + TIM3EN: u1, + /// TIM4 timer clock enable + TIM4EN: u1, + /// TIM5 timer clock enable + TIM5EN: u1, + /// TIM6 timer clock enable + TIM6EN: u1, + /// TIM7 timer clock enable + TIM7EN: u1, + reserved8: u2, + /// CRSclock enable + CRSEN: u1, + reserved10: u1, + /// RTC APB clock enable + RTCAPBEN: u1, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI2 clock enable + SPI2EN: u1, + /// SPI3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// USB device clock enable + USBEN: u1, + reserved25: u1, + /// FDCAN clock enable + FDCANEN: u1, + reserved28: u2, + /// Power interface clock enable + PWREN: u1, + reserved30: u1, + /// I2C3 clock enable + I2C3EN: u1, + /// Low power timer 1 clock enable + LPTIM1EN: u1, }), - /// dual 8-bit right aligned data holding register - DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// APB1 peripheral clock enable register 2 + APB1ENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clock enable + LPUART1EN: u1, + /// I2C4 clock enable + I2C4EN: u1, + reserved8: u6, + /// UCPD1 clock enable + UCPD1EN: u1, + padding: u23, }), - /// channel data output register - DOR: [2]mmio.Mmio(packed struct(u32) { - /// channel data output - DOR: u12, - reserved16: u4, - /// channel data output B - DORB: u12, - padding: u4, + /// APB2ENR + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved11: u10, + /// TIM1 timer clock enable + TIM1EN: u1, + /// SPI1 clock enable + SPI1EN: u1, + /// TIM8 timer clock enable + TIM8EN: u1, + /// USART1clock enable + USART1EN: u1, + /// SPI 4 clock enable + SPI4EN: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + reserved20: u1, + /// Timer 20 clock enable + TIM20EN: u1, + /// SAI1 clock enable + SAI1EN: u1, + reserved26: u4, + /// HRTIMER clock enable + HRTIM1EN: u1, + padding: u5, }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// channel ready status bit - DACRDY: u1, - /// channel output register status bit - DORSTAT: u1, - /// channel DMA underrun flag - DMAUDR: u1, - /// channel calibration offset status - CAL_FLAG: u1, - /// channel busy writing sample time flag - BWST: u1, - padding: u16, + reserved104: [4]u8, + /// AHB1 peripheral clocks enable in Sleep and Stop modes register + AHB1SMENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clocks enable during Sleep and Stop modes + DMA1SMEN: u1, + /// DMA2 clocks enable during Sleep and Stop modes + DMA2SMEN: u1, + /// DMAMUX clock enable during Sleep and Stop modes + DMAMUX1SMEN: u1, + /// CORDIC clock enable during sleep mode + CORDICSMEN: u1, + /// FMACSM clock enable + FMACSMEN: u1, + reserved8: u3, + /// Flash memory interface clocks enable during Sleep and Stop modes + FLASHSMEN: u1, + /// SRAM1 interface clocks enable during Sleep and Stop modes + SRAM1SMEN: u1, + reserved12: u2, + /// CRCSMEN + CRCSMEN: u1, + padding: u19, }), - /// calibration control register - CCR: mmio.Mmio(packed struct(u32) { - /// channel offset trimming value - OTRIM: u5, - padding: u27, + /// AHB2 peripheral clocks enable in Sleep and Stop modes register + AHB2SMENR: mmio.Mmio(packed struct(u32) { + /// IO port A clocks enable during Sleep and Stop modes + GPIOASMEN: u1, + /// IO port B clocks enable during Sleep and Stop modes + GPIOBSMEN: u1, + /// IO port C clocks enable during Sleep and Stop modes + GPIOCSMEN: u1, + /// IO port D clocks enable during Sleep and Stop modes + GPIODSMEN: u1, + /// IO port E clocks enable during Sleep and Stop modes + GPIOESMEN: u1, + /// IO port F clocks enable during Sleep and Stop modes + GPIOFSMEN: u1, + /// IO port G clocks enable during Sleep and Stop modes + GPIOGSMEN: u1, + reserved9: u2, + /// CCM SRAM interface clocks enable during Sleep and Stop modes + CCMSRAMSMEN: u1, + /// SRAM2 interface clocks enable during Sleep and Stop modes + SRAM2SMEN: u1, + reserved13: u2, + /// ADC clocks enable during Sleep and Stop modes + ADC12SMEN: u1, + /// DCMI clock enable during Sleep and Stop modes + ADC345SMEN: u1, + reserved16: u1, + /// AES accelerator clocks enable during Sleep and Stop modes + DAC1SMEN: u1, + /// HASH clock enable during Sleep and Stop modes + DAC2SMEN: u1, + /// DAC3 clock enable during sleep mode + DAC3SMEN: u1, + /// DAC4 clock enable during sleep mode + DAC4SMEN: u1, + reserved24: u4, + /// Cryptography clock enable during sleep mode + AESMEN: u1, + reserved26: u1, + /// Random Number Generator clock enable during sleep mode + RNGEN: u1, + padding: u5, }), - /// mode control register - MCR: mmio.Mmio(packed struct(u32) { - /// DAC channel mode - MODE: packed union { - raw: u3, - value: MODE, - }, - reserved8: u5, - /// channel DMA double data mode. - DMADOUBLE: u1, - /// enable signed format for DAC channel - SINFORMAT: u1, - reserved14: u4, - /// high frequency interface mode selection - HFSEL: u2, - padding: u16, + /// AHB3 peripheral clocks enable in Sleep and Stop modes register + AHB3SMENR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller clocks enable during Sleep and Stop modes + FMCSMEN: u1, + reserved8: u7, + /// QUADSPI memory interface clock enable during Sleep and Stop modes + QUADSPISMEN: u1, + padding: u23, }), - /// sample and hold sample time register - SHSR: [2]mmio.Mmio(packed struct(u32) { - /// channel sample time - TSAMPLE: u10, - padding: u22, + reserved120: [4]u8, + /// APB1SMENR1 + APB1SMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clocks enable during Sleep and Stop modes + TIM2SMEN: u1, + /// TIM3 timer clocks enable during Sleep and Stop modes + TIM3SMEN: u1, + /// TIM4 timer clocks enable during Sleep and Stop modes + TIM4SMEN: u1, + /// TIM5 timer clocks enable during Sleep and Stop modes + TIM5SMEN: u1, + /// TIM6 timer clocks enable during Sleep and Stop modes + TIM6SMEN: u1, + /// TIM7 timer clocks enable during Sleep and Stop modes + TIM7SMEN: u1, + reserved8: u2, + /// CRS clock enable during sleep mode + CRSSMEN: u1, + reserved10: u1, + /// RTC APB clock enable during Sleep and Stop modes + RTCAPBSMEN: u1, + /// Window watchdog clocks enable during Sleep and Stop modes + WWDGSMEN: u1, + reserved14: u2, + /// SPI2 clocks enable during Sleep and Stop modes + SPI2SMEN: u1, + /// SPI3 clocks enable during Sleep and Stop modes + SP3SMEN: u1, + reserved17: u1, + /// USART2 clocks enable during Sleep and Stop modes + USART2SMEN: u1, + /// USART3 clocks enable during Sleep and Stop modes + USART3SMEN: u1, + /// UART4 clocks enable during Sleep and Stop modes + UART4SMEN: u1, + /// UART5 clocks enable during Sleep and Stop modes + UART5SMEN: u1, + /// I2C1 clocks enable during Sleep and Stop modes + I2C1SMEN: u1, + /// I2C2 clocks enable during Sleep and Stop modes + I2C2SMEN: u1, + /// USB device clocks enable during Sleep and Stop modes + USBSMEN: u1, + reserved25: u1, + /// FDCAN clock enable during sleep mode + FDCANSMEN: u1, + reserved28: u2, + /// Power interface clocks enable during Sleep and Stop modes + PWRSMEN: u1, + reserved30: u1, + /// I2C3 clocks enable during Sleep and Stop modes + I2C3SMEN: u1, + /// Low Power Timer1 clock enable during sleep mode + LPTIM1SMEN: u1, }), - /// sample and hold hold time register - SHHR: mmio.Mmio(packed struct(u32) { - /// channel hold time - THOLD: u10, - padding: u22, + /// APB1 peripheral clocks enable in Sleep and Stop modes register 2 + APB1SMENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clocks enable during Sleep and Stop modes + LPUART1SMEN: u1, + /// I2C4 clocks enable during Sleep and Stop modes + I2C4SMEN: u1, + reserved8: u6, + /// UCPD1 clocks enable during Sleep and Stop modes + UCPD1SMEN: u1, + padding: u23, }), - /// sample and hold refresh time register - SHRR: mmio.Mmio(packed struct(u32) { - /// channel refresh time - TREFRESH: u8, - padding: u24, + /// APB2SMENR + APB2SMENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clocks enable during Sleep and Stop modes + SYSCFGSMEN: u1, + reserved11: u10, + /// TIM1 timer clocks enable during Sleep and Stop modes + TIM1SMEN: u1, + /// SPI1 clocks enable during Sleep and Stop modes + SPI1SMEN: u1, + /// TIM8 timer clocks enable during Sleep and Stop modes + TIM8SMEN: u1, + /// USART1clocks enable during Sleep and Stop modes + USART1SMEN: u1, + /// SPI4 timer clocks enable during Sleep and Stop modes + SPI4SMEN: u1, + /// TIM15 timer clocks enable during Sleep and Stop modes + TIM15SMEN: u1, + /// TIM16 timer clocks enable during Sleep and Stop modes + TIM16SMEN: u1, + /// TIM17 timer clocks enable during Sleep and Stop modes + TIM17SMEN: u1, + reserved20: u1, + /// Timer 20clock enable during sleep mode + TIM20SMEN: u1, + /// SAI1 clock enable during sleep mode + SAI1SMEN: u1, + reserved26: u4, + /// HRTIMER clock enable during sleep mode + HRTIM1SMEN: u1, + padding: u5, }), - }; - }; - - pub const tamp_g0 = struct { - /// Tamper and backup registers - pub const TAMP = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Tamper detection on IN X enable - TAMPE: u1, - reserved16: u15, - /// Internal tamper X enable - ITAMPE: u1, - padding: u15, + reserved136: [4]u8, + /// CCIPR + CCIPR: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SEL: u2, + /// USART2 clock source selection + USART2SEL: u2, + /// USART3 clock source selection + USART3SEL: u2, + /// UART4 clock source selection + UART4SEL: u2, + /// UART5 clock source selection + UART5SEL: u2, + /// LPUART1 clock source selection + LPUART1SEL: u2, + /// I2C1 clock source selection + I2C1SEL: u2, + /// I2C2 clock source selection + I2C2SEL: u2, + /// I2C3 clock source selection + I2C3SEL: u2, + /// Low power timer 1 clock source selection + LPTIM1SEL: u2, + /// SAI1 clock source selection + SAI1SEL: u2, + /// I2S23 clock source selection + I2S23SEL: u2, + /// FDCAN clock source selection + FDCANSEL: packed union { + raw: u2, + value: FDCANSEL, + }, + /// 48 MHz clock source selection + CLK48SEL: packed union { + raw: u2, + value: CLK48SEL, + }, + /// ADCs clock source selection + ADC12SEL: packed union { + raw: u2, + value: ADCSEL, + }, + /// ADC3/4/5 clock source selection + ADC345SEL: packed union { + raw: u2, + value: ADCSEL, + }, }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Tamper X no erase - TAMPNOER: u1, - reserved16: u15, - /// Tamper X mask - TAMPMSK: u1, + reserved144: [4]u8, + /// BDCR + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enable + LSEON: u1, + /// LSE oscillator ready + LSERDY: u1, + /// LSE oscillator bypass + LSEBYP: u1, + /// SE oscillator drive capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// LSECSSON + LSECSSON: u1, + /// LSECSSD + LSECSSD: u1, + reserved8: u1, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// RTC domain software reset + BDRST: u1, reserved24: u7, - /// Active level for tamper X input - TAMPTRG: u1, - padding: u7, - }), - reserved12: [4]u8, - /// TAMP filter control register - FLTCR: mmio.Mmio(packed struct(u32) { - /// Tamper sampling frequency. Determines the frequency at which each of the INx inputs are sampled. - TAMPFREQ: u3, - /// INx filter count. These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the INx inputs. - TAMPFLT: u2, - /// INx precharge duration. These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the INx inputs. - TAMPPRCH: u2, - /// INx pull-up disable. This bit determines if each of the TAMPx pins are precharged before each sample. - TAMPPUDIS: u1, - padding: u24, - }), - reserved44: [28]u8, - /// TAMP interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt enable - TAMPIE: u1, - reserved16: u15, - /// Internal tamper X interrupt enable - ITAMPIE: u1, - padding: u15, - }), - /// TAMP status register - SR: mmio.Mmio(packed struct(u32) { - /// Tamper X detection flag - TAMPF: u1, - reserved16: u15, - /// Internal tamper X detection flag - ITAMPF: u1, - padding: u15, - }), - /// TAMP masked interrupt status register - MISR: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt masked flag - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X interrupt masked flag - ITAMPMF: u1, - padding: u15, - }), - reserved60: [4]u8, - /// TAMP status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear tamper X detection flag - CTAMPF: u1, - reserved16: u15, - /// Clear internal tamper X detection flag - CITAMPF: u1, - padding: u15, - }), - reserved256: [192]u8, - /// TAMP backup register - BKPR: [5]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, - }), - reserved1004: [728]u8, - /// TAMP hardware configuration register 2 - HWCFGR2: mmio.Mmio(packed struct(u32) { - /// PTIONREG_OUT - PTIONREG_OUT: u8, - /// TRUST_ZONE - TRUST_ZONE: u4, - padding: u20, - }), - /// TAMP hardware configuration register 1 - HWCFGR1: mmio.Mmio(packed struct(u32) { - /// BACKUP_REGS - BACKUP_REGS: u8, - /// TAMPER - TAMPER: u4, - /// ACTIVE_TAMPER - ACTIVE_TAMPER: u4, - /// INT_TAMPER - INT_TAMPER: u16, + /// Low speed clock output enable + LSCOEN: u1, + /// Low speed clock output selection + LSCOSEL: u1, + padding: u6, }), - /// EXTI IP Version register - VERR: mmio.Mmio(packed struct(u32) { - /// Minor Revision number - MINREV: u4, - /// Major Revision number - MAJREV: u4, - padding: u24, + /// CSR + CSR: mmio.Mmio(packed struct(u32) { + /// LSI oscillator enable + LSION: u1, + /// LSI oscillator ready + LSIRDY: u1, + reserved23: u21, + /// Remove reset flag + RMVF: u1, + reserved25: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// Pad reset flag + PINRSTF: u1, + /// BOR flag + BORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent window watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, }), - /// EXTI Identification register - IPIDR: mmio.Mmio(packed struct(u32) { - /// IP Identification - IPID: u32, + /// Clock recovery RC register + CRRCR: mmio.Mmio(packed struct(u32) { + /// HSI48 clock enable + HSI48ON: u1, + /// HSI48 clock ready flag + HSI48RDY: u1, + reserved7: u5, + /// HSI48 clock calibration + HSI48CAL: u9, + padding: u16, }), - /// EXTI Size ID register - SIDR: mmio.Mmio(packed struct(u32) { - /// Size Identification - SID: u32, + /// Peripherals independent clock configuration register + CCIPR2: mmio.Mmio(packed struct(u32) { + /// I2C4 clock source selection + I2C4SEL: u2, + reserved20: u18, + /// Octospi clock source selection + QUADSPISEL: u2, + padding: u10, }), }; }; - pub const adc_f3_v1_1 = struct { - pub const ADC_CFG = enum(u1) { - /// Bank A selected for channels ADC_IN0..31 - BANK_A = 0x0, - /// Bank B selected for channels ADC_IN0..31b - BANK_B = 0x1, + pub const rcc_h5 = struct { + pub const ADCDACSEL = enum(u3) { + /// rcc_hclk selected as kernel clock (default after reset) + HCLK2 = 0x0, + /// sys_ck selected as kernel clock + SYS = 0x1, + /// pll2_r_ck selected as kernel clock + PLL2_R = 0x2, + /// hse_ck selected as kernel clock + HSE = 0x3, + /// hsi_ker_ck selected as kernel clock + HSI = 0x4, + /// csi_ker_ck selected as kernel clock + CSI = 0x5, + _, }; - pub const DELS = enum(u3) { - /// No Delay - NO_DELAY = 0x0, - /// Until the converted data have been read - AFTER_READ = 0x1, - /// Delay 7 APB clock cycles after the conversion - DELAY_7_CLK = 0x2, - /// Delay 16 APB clock cycles after the conversion - DELAY_15_CLK = 0x3, - /// Delay 31 APB clock cycles after the conversion - DELAY_31_CLK = 0x4, - /// Delay 63 APB clock cycles after the conversion - DELAY_63_CLK = 0x5, - /// Delay 127 APB clock cycles after the conversion - DELAY_127_CLK = 0x6, - /// Delay 255 APB clock cycles after the conversion - DELAY_255_CLK = 0x7, + pub const CECSEL = enum(u2) { + /// lse_ck selected as kernel clock (default after reset) + LSE = 0x0, + /// lsi_ker_ck selected as kernel clock + LSI = 0x1, + /// csi_ker_ck/122 selected as kernel clock + CSI_DIV_122 = 0x2, + _, }; - pub const DISCNUM = enum(u3) { - /// 1 conversions are discontinued and the conversion is carried out on one channel - DISCNUM_1 = 0x0, - /// 2 conversion is discontinued and the conversions are carried out on 2 channels - DISCNUM_2 = 0x1, - /// 3 conversions are discontinued and the conversions are carried out on 3 channels - DISCNUM_3 = 0x2, - /// 4 conversions are discontinued and the conversions are carried out on 4 channels - DISCNUM_4 = 0x3, - /// 5 conversions are discontinued and the conversions are carried out on 5 channels - DISCNUM_5 = 0x4, - /// 6 conversions are discontinued and the conversions are carried out on 6 channels - DISCNUM_6 = 0x5, - /// 7 conversions are discontinued and the conversions are carried out on 7 channels - DISCNUM_7 = 0x6, - /// 8 conversions are discontinued and the conversions are carried out on 8 channels - DISCNUM_8 = 0x7, + pub const DACHOLDSEL = enum(u1) { + /// dac_hold_ck selected as kernel clock (default after reset) + DAC_HOLD = 0x0, + /// dac_hold_ck selected as kernel clock + DAC_HOLD_2 = 0x1, }; - pub const EXTEN = enum(u2) { - /// Trigger detection disabled - DISABLED = 0x0, - /// Trigger detection on the rising edge - RISING = 0x1, - /// Trigger detection on the falling edge - FALLING = 0x2, - /// Trigger detection on both edges - BOTH = 0x3, + pub const FDCANSEL = enum(u2) { + /// hse_ck selected as kernel clock (default after reset) + HSE = 0x0, + /// pll1_q_ck selected as kernel clock + PLL1_Q = 0x1, + /// pll2_q_ck selected as kernel clock + PLL2_Q = 0x2, + _, }; - pub const EXTSEL = enum(u4) { - /// Timer 9 CC2 event - TIM9_CC2 = 0x0, - /// Timer 9 TRGO event - TIM9_TRGO = 0x1, - /// Timer 2 CC3 event - TIM2_CC3 = 0x2, - /// Timer 2 CC2 event - TIM2_CC2 = 0x3, - /// Timer 3 TRGO event - TIM3_TRGO = 0x4, - /// Timer 4 CC4 event - TIM4_CC4 = 0x5, - /// Timer 2 TRGO event - TIM2_TRGO = 0x6, - /// Timer 3 CC1 event - TIM3_CC1 = 0x7, - /// Timer 3 CC3 event - TIM3_CC3 = 0x8, - /// Timer 4 TRGO event - TIM4_TRGO = 0x9, - /// Timer 6 TRGO event - TIM6_TRGO = 0xa, - /// External interrupt line 11 - EXTI_LINE11 = 0xf, + pub const HPRE = enum(u4) { + /// sys_ck not divided + Div1 = 0x0, + /// sys_ck divided by 2 + Div2 = 0x8, + /// sys_ck divided by 4 + Div4 = 0x9, + /// sys_ck divided by 8 + Div8 = 0xa, + /// sys_ck divided by 16 + Div16 = 0xb, + /// sys_ck divided by 64 + Div64 = 0xc, + /// sys_ck divided by 128 + Div128 = 0xd, + /// sys_ck divided by 256 + Div256 = 0xe, + /// sys_ck divided by 512 + Div512 = 0xf, _, }; - pub const JEXTSEL = enum(u4) { - /// Timer 9 CC1 event - TIM9_CC1 = 0x0, - /// Timer 9 TRGO event - TIM9_TRGO = 0x1, - /// Timer 2 TRGO event - TIM2_TRGO = 0x2, - /// Timer 2 CC1 event - TIM2_CC1 = 0x3, - /// Timer 3 CC4 event - TIM3_CC4 = 0x4, - /// Timer 4 TRGO event - TIM4_TRGO = 0x5, - /// Timer 4 CC1 event - TIM4_CC1 = 0x6, - /// Timer 4 CC2 event - TIM4_CC2 = 0x7, - /// Timer 4 CC3 event - TIM4_CC3 = 0x8, - /// Timer 4 CC3 event - TIM10_CC1 = 0x9, - /// Timer 7 TRGO event - TIM7_TRGO = 0xa, - /// External interrupt line 15 - EXTI_LINE15 = 0xf, - _, + pub const HSEEXT = enum(u1) { + /// HSE in analog mode (default after reset) + Analog = 0x0, + /// HSE in digital mode + Digital = 0x1, }; - pub const RES = enum(u2) { - /// 12-bit resolution - Bits12 = 0x0, - /// 10-bit resolution - Bits10 = 0x1, - /// 8-bit resolution - Bits8 = 0x2, - /// 6-bit resolution - Bits6 = 0x3, + pub const HSIDIV = enum(u2) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x1, + /// Division by 4 + Div4 = 0x2, + /// Division by 8 + Div8 = 0x3, }; - pub const SAMPLE_TIME = enum(u3) { - /// 4 ADC clock cycles - Cycles4 = 0x0, - /// 9 ADC clock cycles - Cycles9 = 0x1, - /// 16 ADC clock cycles - Cycles16 = 0x2, - /// 24 ADC clock cycles - Cycles24 = 0x3, - /// 48 ADC clock cycles - Cycles48 = 0x4, - /// 96 ADC clock cycles - Cycles96 = 0x5, - /// 192 ADC clock cycles - Cycles192 = 0x6, - /// 384 ADC clock cycles - Cycles384 = 0x7, + pub const I2C34SEL = enum(u2) { + /// rcc_pclk3 selected as peripheral clock + PCLK3 = 0x0, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// hsi_ker selected as peripheral clock + HSI = 0x2, + /// csi_ker selected as peripheral clock + CSI = 0x3, }; - /// Analog-to-digital converter - pub const ADC = extern struct { - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog flag - AWD: u1, - /// Regular channel end of conversion - EOC: u1, - /// Injected channel end of conversion - JEOC: u1, - /// Injected channel start flag - JSTRT: u1, - /// Regular channel start flag - STRT: u1, - /// Overrun - OVR: u1, - /// ADC ON status - ADONS: u1, - reserved8: u1, - /// Regular channel not ready - RCNR: u1, - /// Injected channel not ready - JCNR: u1, - padding: u22, - }), - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Analog watchdog channel select bits - AWDCH: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Analog watchdog interrupt enable - AWDIE: u1, - /// Interrupt enable for injected channels - JEOCIE: u1, - /// Scan mode - SCAN: u1, - /// Enable the watchdog on a single channel in scan mode - AWDSGL: u1, - /// Automatic injected group conversion - JAUTO: u1, - /// Discontinuous mode on regular channels - DISCEN: u1, - /// Discontinuous mode on injected channels - JDISCEN: u1, - /// Discontinuous mode channel count - DISCNUM: packed union { - raw: u3, - value: DISCNUM, - }, - /// Power down during the delay phase - PDD: u1, - /// Power down during the idle phase - PDI: u1, - reserved22: u4, - /// Analog watchdog enable on injected channels - JAWDEN: u1, - /// Analog watchdog enable on regular channels - AWDEN: u1, - /// Resolution - RES: packed union { - raw: u2, - value: RES, - }, - /// Overrun interrupt enable - OVRIE: u1, - padding: u5, - }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// A/D Converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - /// ADC configuration - ADC_CFG: packed union { - raw: u1, - value: ADC_CFG, - }, - reserved4: u1, - /// Delay selection - DELS: packed union { - raw: u3, - value: DELS, - }, - reserved8: u1, - /// Direct memory access mode - DMA: u1, - /// DMA disable selection - DDS: u1, - /// End of conversion selection - EOCS: u1, - /// Data alignment - ALIGN: u1, - reserved16: u4, - /// External event select for injected group - JEXTSEL: packed union { - raw: u4, - value: JEXTSEL, - }, - /// External trigger enable for injected channels - JEXTEN: packed union { - raw: u2, - value: EXTEN, - }, - /// Start conversion of injected channels - JSWSTART: u1, - reserved24: u1, - /// External event select for regular group - EXTSEL: packed union { - raw: u4, - value: EXTSEL, - }, - /// External trigger enable for regular channels - EXTEN: packed union { - raw: u2, - value: EXTEN, - }, - /// Start conversion of regular channels - SWSTART: u1, - padding: u1, - }), - /// sample time register 1 - SMPR1: mmio.Mmio(packed struct(u32) { - /// channel 20-29 sampling time selection - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - padding: u29, - }), - /// sample time register 2 - SMPR2: mmio.Mmio(packed struct(u32) { - /// channel 10-19 sampling time selection - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - padding: u29, - }), - /// sample time register 3 - SMPR3: mmio.Mmio(packed struct(u32) { - /// channel 0-9 sampling time selection - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - padding: u29, - }), - /// injected channel data offset register 1 - JOFR1: mmio.Mmio(packed struct(u32) { - /// Data offset for injected channel x - JOFFSET1: u12, - padding: u20, - }), - /// injected channel data offset register 2 - JOFR2: mmio.Mmio(packed struct(u32) { - /// Data offset for injected channel x - JOFFSET2: u12, - padding: u20, - }), - /// injected channel data offset register 3 - JOFR3: mmio.Mmio(packed struct(u32) { - /// Data offset for injected channel x - JOFFSET3: u12, - padding: u20, - }), - /// injected channel data offset register 4 - JOFR4: mmio.Mmio(packed struct(u32) { - /// Data offset for injected channel x - JOFFSET4: u12, - padding: u20, - }), - /// watchdog higher threshold register - HTR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog higher threshold - HT: u12, - padding: u20, - }), - /// watchdog lower threshold register - LTR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog lower threshold - LT: u12, - padding: u20, - }), - /// regular sequence register 1 - SQR1: mmio.Mmio(packed struct(u32) { - /// 25th-29th conversion in regular sequence - SQ: u5, - reserved20: u15, - /// Regular channel sequence length - L: u4, - padding: u8, - }), - /// regular sequence register 2 - SQR2: mmio.Mmio(packed struct(u32) { - /// 19th-24th conversion in regular sequence - SQ: u5, - padding: u27, - }), - /// regular sequence register 3 - SQR3: mmio.Mmio(packed struct(u32) { - /// 13th-18th conversion in regular sequence - SQ: u5, - padding: u27, - }), - /// regular sequence register 4 - SQR4: mmio.Mmio(packed struct(u32) { - /// 7th-12th conversion in regular sequence - SQ: u5, - padding: u27, - }), - /// regular sequence register 5 - SQR5: mmio.Mmio(packed struct(u32) { - /// 1st-6th conversion in regular sequence - SQ: u5, - padding: u27, - }), - /// injected sequence register - JSQR: mmio.Mmio(packed struct(u32) { - /// 1st conversion in injected sequence - JSQ1: u5, - /// 2nd conversion in injected sequence - JSQ2: u5, - /// 3rd conversion in injected sequence - JSQ3: u5, - /// 4th conversion in injected sequence - JSQ4: u5, - /// Injected sequence length - JL: u2, - padding: u10, - }), - /// injected data register x1 - JDR1: mmio.Mmio(packed struct(u32) { - /// Injected data - JDATA: u16, - padding: u16, - }), - /// injected data register 2 - JDR2: mmio.Mmio(packed struct(u32) { - /// Injected data - JDATA: u16, - padding: u16, - }), - /// injected data register 3 - JDR3: mmio.Mmio(packed struct(u32) { - /// Injected data - JDATA: u16, - padding: u16, - }), - /// injected data register 4 - JDR4: mmio.Mmio(packed struct(u32) { - /// Injected data - JDATA: u16, - padding: u16, - }), - /// regular data register - DR: mmio.Mmio(packed struct(u32) { - /// Regular data - rdata: u16, - padding: u16, - }), - /// sample time register 0 - SMPR0: mmio.Mmio(packed struct(u32) { - /// channel 30-31 sampling time selection - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - padding: u29, - }), - reserved768: [672]u8, - /// ADC common status register - CSR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog flag of the ADC - AWD1: u1, - /// End of conversion of the ADC - EOC1: u1, - /// Injected channel end of conversion of the ADC - JEOC1: u1, - /// Injected channel Start flag of the ADC - JSTRT1: u1, - /// Regular channel Start flag of the ADC - STRT1: u1, - /// Overrun flag of the ADC - OVR1: u1, - /// ADON Status of ADC1 - ADONS1: u1, - padding: u25, - }), - /// ADC common control register - CCR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// ADC prescaler - ADCPRE: u2, - reserved23: u5, - /// Temperature sensor and VREFINT enable - TSVREFE: u1, - padding: u8, - }), + pub const I2CSEL = enum(u2) { + /// rcc_pclk1 selected as peripheral clock + PCLK1 = 0x0, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// hsi_ker selected as peripheral clock + HSI = 0x2, + /// csi_ker selected as peripheral clock + CSI = 0x3, }; - }; - pub const dbgmcu_f0 = struct { - /// Debug support - pub const DBGMCU = extern struct { - /// MCU Device ID Code Register - IDCODE: mmio.Mmio(packed struct(u32) { - /// Device Identifier - DEV_ID: u12, - /// Division Identifier - DIV_ID: u4, - /// Revision Identifier - REV_ID: u16, - }), - /// Debug MCU Configuration Register - CR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Debug Stop Mode - DBG_STOP: u1, - /// Debug Standby Mode - DBG_STANDBY: u1, - padding: u29, - }), - /// Debug MCU APB1 freeze register - APB1_FZ: mmio.Mmio(packed struct(u32) { - /// TIM2 counter stopped when core is halted - TIM2: u1, - /// TIM3 counter stopped when core is halted - TIM3: u1, - reserved4: u2, - /// TIM6 counter stopped when core is halted - TIM6: u1, - /// TIM7 counter stopped when core is halted - TIM7: u1, - reserved8: u2, - /// TIM14 counter stopped when core is halted - TIM14: u1, - reserved10: u1, - /// Debug RTC stopped when core is halted - RTC: u1, - /// Debug window watchdog stopped when core is halted - WWDG: u1, - /// Debug independent watchdog stopped when core is halted - IWDG: u1, - reserved21: u8, - /// SMBUS timeout mode stopped when core is halted - DBG_I2C1_SMBUS_TIMEOUT: u1, - reserved25: u3, - /// CAN stopped when core is halted - CAN: u1, - padding: u6, - }), - /// Debug MCU APB2 freeze register - APB2_FZ: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 counter stopped when core is halted - TIM1: u1, - reserved16: u4, - /// TIM15 counter stopped when core is halted - TIM15: u1, - /// TIM16 counter stopped when core is halted - TIM16: u1, - /// TIM17 counter stopped when core is halted - TIM17: u1, - padding: u13, - }), + pub const LPTIM2SEL = enum(u3) { + /// rcc_pclk1 selected as peripheral clock + PCLK1 = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// LSE selected as peripheral clock + LSE = 0x3, + /// LSI selected as peripheral clock + LSI = 0x4, + /// PER selected as peripheral clock + PER = 0x5, + _, }; - }; - pub const octospi_v2 = struct { - pub const FlashSelect = enum(u1) { - /// FLASH 1 selected (data exchanged over IO[3:0]) - FlashOne = 0x0, - /// FLASH 2 selected (data exchanged over IO[7:4]) - FlashTwo = 0x1, + pub const LPTIMSEL = enum(u3) { + /// rcc_pclk3 selected as peripheral clock + PCLK3 = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_r selected as peripheral clock + PLL3_R = 0x2, + /// LSE selected as peripheral clock + LSE = 0x3, + /// LSI selected as peripheral clock + LSI = 0x4, + /// PER selected as peripheral clock + PER = 0x5, + _, }; - pub const FunctionalMode = enum(u2) { - /// Indirect-write mode - IndirectWrite = 0x0, - /// Indirect-read mode - IndirectRead = 0x1, - /// Automatic status-polling mode - AutoStatusPolling = 0x2, - /// Memory-mapped mode - MemoryMapped = 0x3, + pub const LPUSARTSEL = enum(u3) { + /// rcc_pclk3 selected as kernel clock (default after reset) + PCLK3 = 0x0, + /// pll2_q_ck selected as kernel clock + PLL2_Q = 0x1, + /// pll3_q_ck selected as kernel clock + PLL3_Q = 0x2, + /// hsi_ker_ck selected as kernel clock + HSI = 0x3, + /// csi_ker_ck selected as kernel clock + CSI = 0x4, + /// lse_ck selected as kernel clock + LSE = 0x5, + _, }; - pub const LatencyMode = enum(u1) { - /// Variable initial latency - Variable = 0x0, - /// Fixed latency - Fixed = 0x1, + pub const LSCOSEL = enum(u1) { + /// LSI clock selected + LSI = 0x0, + /// LSE clock selected + LSE = 0x1, }; - pub const MatchMode = enum(u1) { - /// AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register. - MatchAnd = 0x0, - /// OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register. - MatchOr = 0x1, + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, }; - pub const MemType = enum(u3) { - /// Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes. - Micron = 0x0, - /// Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes. - Macronix = 0x1, - /// Standard mode - B_Standard = 0x2, - /// Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping. - MacronixRam = 0x3, - /// HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected. - HyperBusMemory = 0x4, - /// HyperBus register mode, addressing register space. The memory-mapped accesses in. this mode must be non-cacheable, or Indirect read/write modes must be used. - HyperBusRegister = 0x5, - _, + pub const LSEEXT = enum(u1) { + /// LSE in analog mode (default after Backup domain reset) + Analog = 0x0, + /// LSE in digital mode (do not use if RTC is active). + Digital = 0x1, }; - pub const PhaseMode = enum(u3) { - /// No alternate bytes - None = 0x0, - /// Alternate bytes on a single line - OneLine = 0x1, - /// Alternate bytes on two lines - TwoLines = 0x2, - /// Alternate bytes on four lines - FourLines = 0x3, - /// Alternate bytes on eight lines - EightLines = 0x4, + pub const MCO1SEL = enum(u3) { + /// HSI selected for micro-controller clock output + HSI = 0x0, + /// LSE selected for micro-controller clock output + LSE = 0x1, + /// HSE selected for micro-controller clock output + HSE = 0x2, + /// pll1_q selected for micro-controller clock output + PLL1_Q = 0x3, + /// HSI48 selected for micro-controller clock output + HSI48 = 0x4, _, }; - pub const SampleShift = enum(u1) { - /// No shift - None = 0x0, - /// 1/2 cycle shift - HalfCycle = 0x1, - }; - - pub const SizeInBits = enum(u2) { - /// 8-bit alternate bytes - @"8Bit" = 0x0, - /// 16-bit alternate bytes - @"16Bit" = 0x1, - /// 24-bit alternate bytes - @"24Bit" = 0x2, - /// 32-bit alternate bytes - @"32Bit" = 0x3, - }; - - pub const Threshold = enum(u5) { - /// FTF is set if there are one or more free bytes available to be written to in the FIFO in Indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in Indirect-read mode. - NeedOneByte = 0x0, - /// FTF is set if there are two or more free bytes available to be written to in the FIFO in Indirect‑write mode, or if there are two or more valid bytes can be read from the FIFO in Indirect-read mode. - NeedTwoBytes = 0x1, - /// FTF is set if there are 32 free bytes available to be written to in the FIFO in Indirect-write mode, or if there are 32 valid bytes can be read from the FIFO in Indirect-read mode. - NeedThirtyTwoBytes = 0x1f, + pub const MCO2SEL = enum(u3) { + /// System clock selected for micro-controller clock output + SYS = 0x0, + /// pll2_p selected for micro-controller clock output + PLL2_P = 0x1, + /// HSE selected for micro-controller clock output + HSE = 0x2, + /// pll1_p selected for micro-controller clock output + PLL1_P = 0x3, + /// CSI selected for micro-controller clock output + CSI = 0x4, + /// LSI selected for micro-controller clock output + LSI = 0x5, _, }; - /// OctoSPI - pub const OCTOSPI = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// Enable This bit enables the OCTOSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case. this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active. - EN: u1, - /// Abort request. This bit aborts the ongoing command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0. - ABORT: u1, - /// DMA enable In Indirect mode, the DMA can be used to input or output data via DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write. this bit during DMA operation. - DMAEN: u1, - /// Timeout counter enable. This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter. - TCEN: u1, - reserved6: u2, - /// Dual-memory configuration. This bit activates the dual-memory configuration, where two external devices are used simultaneously to double the throughput and the capacity - DMM: u1, - /// Flash select. This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in single-memory configuration (when DMM = 0). This bit is ignored when DMM = 1 or when Octal-SPI mode is selected. - FSEL: packed union { - raw: u1, - value: FlashSelect, - }, - /// FIFO threshold level. This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[4:0] value. - FTHRES: packed union { - raw: u5, - value: Threshold, - }, - reserved16: u3, - /// Transfer error interrupt enable. This bit enables the transfer error interrupt. - TEIE: u1, - /// Transfer complete interrupt enable. This bit enables the transfer complete interrupt. - TCIE: u1, - /// FIFO threshold interrupt enable. This bit enables the FIFO threshold interrupt. - FTIE: u1, - /// Status match interrupt enable. This bit enables the status match interrupt. - SMIE: u1, - /// Timeout interrupt enable. This bit enables the timeout interrupt. - TOIE: u1, - reserved22: u1, - /// Automatic status-polling mode stop. This bit determines if the Automatic status-polling mode is stopped after a match. - APMS: u1, - /// Polling match mode. This bit indicates which method must be used to determine a match during the Automatic status-polling mode. - PMM: packed union { - raw: u1, - value: MatchMode, - }, - reserved28: u4, - /// Functional mode. This field defines the OCTOSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state. - FMODE: packed union { - raw: u2, - value: FunctionalMode, - }, - padding: u2, - }), - reserved8: [4]u8, - /// device configuration register 1 - DCR1: mmio.Mmio(packed struct(u32) { - /// Mode 0/Mode 3 This bit indicates the level taken by the CLK between commands (when NCS = 1). - CKMODE: u1, - /// Free running clock. This bit configures the free running clock. - FRCK: u1, - reserved3: u1, - /// Delay block bypass - DLYBYP: u1, - reserved8: u4, - /// Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (NCS) must remain high between commands issued to the external device. ... - CSHT: u6, - reserved16: u2, - /// Device size. This field defines the size of the external device using the following formula: Number of bytes in device = 2[DEVSIZE+1]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes. In Regular-command protocol, if DMM = 1, DEVSIZE[4:0] indicates the total capacity of the two devices together. - DEVSIZE: u5, - reserved24: u3, - /// Memory type. This bit indicates the type of memory to be supported. Note: In. this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP[2:0] for memories different from Micron. Others: Reserved - MTYP: packed union { - raw: u3, - value: MemType, - }, - padding: u5, - }), - /// device configuration register 2 - DCR2: mmio.Mmio(packed struct(u32) { - /// Clock prescaler. This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). 2: FCLK = FKERNEL/3 ... 255: FCLK = FKERNEL/256 For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low one cycle longer than it stays high. - PRESCALER: u8, - reserved16: u8, - /// Wrap size. This field indicates the wrap size to which the memory is configured. For memories which have a separate command for wrapped instructions, this field indicates the wrap-size associated with the command held in the OCTOSPI1_WPIR register. 110-111: Reserved - WRAPSIZE: u3, - padding: u13, - }), - /// device configuration register 3 - DCR3: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// NCS boundary. This field enables the transaction boundary feature. When active, a minimum value of 3 is recommended. The NCS is released on each boundary of 2CSBOUND bytes. others: NCS boundary set to 2CSBOUND bytes - CSBOUND: u5, - padding: u11, - }), - /// device configuration register 4 - DCR4: mmio.Mmio(packed struct(u32) { - /// Refresh rate. This field enables the refresh rate feature. The NCS is released every REFRESH + 1 clock cycles for writes, and REFRESH + 4 clock cycles for reads. Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in Single-, Dual- or Quad-SPI mode, because the byte transmission must be completed. others: Maximum communication length is set to REFRESH + 1 clock cycles. - REFRESH: u32, - }), - reserved32: [8]u8, - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Transfer error flag. This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode. It is cleared by writing 1 to CTEF. - TEF: u1, - /// Transfer complete flag. This bit is set in Indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF. - TCF: u1, - /// FIFO threshold flag In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete. It is cleared automatically as soon as the threshold condition is no longer true. In Automatic status-polling mode, this bit is set every time the status register is read, and the bit is cleared when the data register is read. - FTF: u1, - /// Status match flag. This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (PSMAR). It is cleared by writing 1 to CSMF. - SMF: u1, - /// Timeout flag. This bit is set when timeout occurs. It is cleared by writing 1 to CTOF. - TOF: u1, - /// Busy. This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty. - BUSY: u1, - reserved8: u2, - /// FIFO level. This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 32 when it is full. In Automatic status-polling mode, FLEVEL is zero. - FLEVEL: u6, - padding: u18, - }), - /// flag clear register - FCR: mmio.Mmio(packed struct(u32) { - /// Clear transfer error flag Writing 1 clears the TEF flag in the SR register. - CTEF: u1, - /// Clear transfer complete flag Writing 1 clears the TCF flag in the SR register. - CTCF: u1, - reserved3: u1, - /// Clear status match flag Writing 1 clears the SMF flag in the SR register. - CSMF: u1, - /// Clear timeout flag Writing 1 clears the TOF flag in the SR register. - CTOF: u1, - padding: u27, - }), - reserved64: [24]u8, - /// data length register - DLR: mmio.Mmio(packed struct(u32) { - /// [31: 0]: Data length Number of data to be retrieved (value+1) in Indirect and Automatic status-polling modes. A value not greater than three (indicating 4 bytes) must be used for Automatic status-polling mode. All 1’s in Indirect mode means undefined length, where OCTOSPI continues until the end of the memory, as defined by DEVSIZE. 0x0000_0000: 1 byte is to be transferred. 0x0000_0001: 2 bytes are to be transferred. 0x0000_0002: 3 bytes are to be transferred. 0x0000_0003: 4 bytes are to be transferred. ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred. 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred. 0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F. DL[0] is stuck at 1 in dual-memory configuration (DMM = 1) even when 0 is written to. this bit, thus assuring that each access transfers an even number of bytes. This field has no effect in Memory-mapped mode. - DL: u32, - }), - reserved72: [4]u8, - /// address register - AR: mmio.Mmio(packed struct(u32) { - /// Address to be sent to the external device. In HyperBus protocol, this field must be even as this protocol is 16-bit word oriented. In dual-memory configuration, AR[0] is forced to 1. Writes to. this field are ignored when BUSY = 1 or when FMODE = 11 (Memory-mapped mode). - ADDRESS: u32, - }), - reserved80: [4]u8, - /// data register - DR: mmio.Mmio(packed struct(u32) { - /// [31: 0]: Data Data to be sent/received to/from the external SPI device In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In Indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In Automatic status-polling mode, this register contains the last data read from the external device (without masking). Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes. Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read 2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom of. this register: A byte read must read DATA[7:0] and a half-word read must read DATA[15:0]. - DATA: u32, - }), - reserved128: [44]u8, - /// polling status mask register - PSMKR: mmio.Mmio(packed struct(u32) { - /// Status mask Mask to be applied to the status bytes received in Automatic status-polling mode For bit n: - MASK: u32, - }), - reserved136: [4]u8, - /// polling status match register - PSMAR: mmio.Mmio(packed struct(u32) { - /// [31: 0]: Status match Value to be compared with the masked status register to get a match - MATCH: u32, - }), - reserved144: [4]u8, - /// polling interval register - PIR: mmio.Mmio(packed struct(u32) { - /// [15: 0]: Polling interval Number of CLK cycle between a read during the Automatic status-polling phases - INTERVAL: u16, - padding: u16, - }), - reserved256: [108]u8, - /// communication configuration register - CCR: mmio.Mmio(packed struct(u32) { - /// Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved - IMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// Instruction double transfer rate. This bit sets the DTR mode for the instruction phase. - IDTR: u1, - /// Instruction size. This bit defines instruction size. - ISIZE: packed union { - raw: u2, - value: SizeInBits, - }, - reserved8: u2, - /// Address mode. This field defines the address phase mode of operation. 101-111: Reserved - ADMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// Address double transfer rate. This bit sets the DTR mode for the address phase. - ADDTR: u1, - /// Address size. This field defines address size. - ADSIZE: packed union { - raw: u2, - value: SizeInBits, - }, - reserved16: u2, - /// Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved - ABMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase. This field can be written only when BUSY = 0. - ABDTR: u1, - /// Alternate bytes size. This bit defines alternate bytes size. - ABSIZE: packed union { - raw: u2, - value: SizeInBits, - }, - reserved24: u2, - /// Data mode. This field defines the data phase mode of operation. 101-111: Reserved - DMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// Data double transfer rate. This bit sets the DTR mode for the data phase. - DDTR: u1, - reserved29: u1, - /// DQS enable. This bit enables the data strobe management. - DQSE: u1, - reserved31: u1, - /// Send instruction only once mode. This bit has no effect when IMODE = 00 (see ). - SIOO: u1, - }), - reserved264: [4]u8, - /// timing configuration register - TCR: mmio.Mmio(packed struct(u32) { - /// Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least six dummy cycles when using memories with DQS activated. - DCYC: u5, - reserved28: u23, - /// Delay hold quarter cycle - DHQC: u1, - reserved30: u1, - /// Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.) - SSHIFT: packed union { - raw: u1, - value: SampleShift, - }, - padding: u1, - }), - reserved272: [4]u8, - /// instruction register - IR: mmio.Mmio(packed struct(u32) { - /// Instruction to be sent to the external SPI device - INSTRUCTION: u32, - }), - reserved288: [12]u8, - /// alternate bytes register - ABR: mmio.Mmio(packed struct(u32) { - /// Alternate bytes - ALTERNATE: u32, - }), - reserved304: [12]u8, - /// low-power timeout register - LPTR: mmio.Mmio(packed struct(u32) { - /// [15: 0]: Timeout period After each access in Memory-mapped mode, the OCTOSPI prefetches the subsequent bytes and hold them in the FIFO. This field indicates how many CLK cycles the OCTOSPI waits after the clock becomes inactive and until it raises the NCS, putting the external device in a lower-consumption state. - TIMEOUT: u16, - padding: u16, - }), - reserved320: [12]u8, - /// wrap communication configuration register - WPCCR: mmio.Mmio(packed struct(u32) { - /// Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved - IMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// Instruction double transfer rate. This bit sets the DTR mode for the instruction phase. - IDTR: u1, - /// Instruction size. This field defines instruction size. - ISIZE: packed union { - raw: u2, - value: SizeInBits, - }, - reserved8: u2, - /// Address mode. This field defines the address phase mode of operation. 101-111: Reserved - ADMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// Address double transfer rate. This bit sets the DTR mode for the address phase. - ADDTR: u1, - /// Address size. This field defines address size. - ADSIZE: packed union { - raw: u2, - value: SizeInBits, - }, - reserved16: u2, - /// Alternate-byte mode. This field defines the alternate byte phase mode of operation. 101-111: Reserved - ABMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase. - ABDTR: u1, - /// Alternate bytes size. This bit defines alternate bytes size. - ABSIZE: packed union { - raw: u2, - value: SizeInBits, - }, - reserved24: u2, - /// Data mode. This field defines the data phase mode of operation. 101-111: Reserved - DMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// Data double transfer rate. This bit sets the DTR mode for the data phase. - DDTR: u1, - reserved29: u1, - /// DQS enable. This bit enables the data strobe management. - DQSE: u1, - padding: u2, - }), - reserved328: [4]u8, - /// wrap timing configuration register - WPTCR: mmio.Mmio(packed struct(u32) { - /// Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. - DCYC: u5, - reserved28: u23, - /// Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement. - DHQC: u1, - reserved30: u1, - /// Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1). - SSHIFT: packed union { - raw: u1, - value: SampleShift, - }, - padding: u1, - }), - reserved336: [4]u8, - /// wrap instruction register - WPIR: mmio.Mmio(packed struct(u32) { - /// [31: 0]: Instruction Instruction to be sent to the external SPI device - INSTRUCTION: u32, - }), - reserved352: [12]u8, - /// wrap alternate bytes register - WPABR: mmio.Mmio(packed struct(u32) { - /// [31: 0]: Alternate bytes Optional data to be sent to the external SPI device right after the address - ALTERNATE: u32, - }), - reserved384: [28]u8, - /// write communication configuration register - WCCR: mmio.Mmio(packed struct(u32) { - /// Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved - IMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// Instruction double transfer rate. This bit sets the DTR mode for the instruction phase. - IDTR: u1, - /// Instruction size. This bit defines instruction size: - ISIZE: packed union { - raw: u2, - value: SizeInBits, - }, - reserved8: u2, - /// Address mode. This field defines the address phase mode of operation. 101-111: Reserved - ADMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// Address double transfer rate. This bit sets the DTR mode for the address phase. - ADDTR: u1, - /// Address size. This field defines address size. - ADSIZE: packed union { - raw: u2, - value: SizeInBits, - }, - reserved16: u2, - /// Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved - ABMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate-bytes phase. - ABDTR: u1, - /// Alternate bytes size. This field defines alternate bytes size: - ABSIZE: packed union { - raw: u2, - value: SizeInBits, - }, - reserved24: u2, - /// Data mode. This field defines the data phase mode of operation. 101-111: Reserved - DMODE: packed union { - raw: u3, - value: PhaseMode, - }, - /// data double transfer rate. This bit sets the DTR mode for the data phase. - DDTR: u1, - reserved29: u1, - /// DQS enable. This bit enables the data strobe management. - DQSE: u1, - padding: u2, - }), - reserved392: [4]u8, - /// write timing configuration register - WTCR: mmio.Mmio(packed struct(u32) { - /// Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. - DCYC: u5, - padding: u27, - }), - reserved400: [4]u8, - /// write instruction register - WIR: mmio.Mmio(packed struct(u32) { - /// Instruction Instruction to be sent to the external SPI device - INSTRUCTION: u32, - }), - reserved416: [12]u8, - /// write alternate bytes register - WABR: mmio.Mmio(packed struct(u32) { - /// [31: 0]: Alternate bytes. Optional data to be sent to the external SPI device right after the address - ALTERNATE: u32, - }), - reserved512: [92]u8, - /// OCTOSPI HyperBus latency configuration register - HLCR: mmio.Mmio(packed struct(u32) { - /// Latency mode. This bit selects the Latency mode. - LM: packed union { - raw: u1, - value: LatencyMode, - }, - /// Write zero latency. This bit enables zero latency on write operations. - WZL: u1, - reserved8: u6, - /// [7: 0]: Access time. Device access time expressed in number of communication clock cycles - TACC: u8, - /// Read write recovery time Device read write recovery time expressed in number of communication clock cycles - TRWR: u8, - padding: u8, - }), - }; - }; - - pub const usart_v2 = struct { - pub const CPHA = enum(u1) { - /// The first clock transition is the first data capture edge - First = 0x0, - /// The second clock transition is the first data capture edge - Second = 0x1, - }; - - pub const CPOL = enum(u1) { - /// Steady low value on CK pin outside transmission window - Low = 0x0, - /// Steady high value on CK pin outside transmission window - High = 0x1, - }; - - pub const IRLP = enum(u1) { - /// Normal mode - Normal = 0x0, - /// Low-power mode - LowPower = 0x1, - }; - - pub const LBDL = enum(u1) { - /// 10-bit break detection - Bit10 = 0x0, - /// 11-bit break detection - Bit11 = 0x1, - }; - - pub const M0 = enum(u1) { - /// 1 start bit, 8 data bits, n stop bits - Bit8 = 0x0, - /// 1 start bit, 9 data bits, n stop bits - Bit9 = 0x1, - }; - - pub const OVER8 = enum(u1) { - /// Oversampling by 16 - Oversampling16 = 0x0, - /// Oversampling by 8 - Oversampling8 = 0x1, - }; - - pub const PS = enum(u1) { - /// Even parity - Even = 0x0, - /// Odd parity - Odd = 0x1, - }; - - pub const RWU = enum(u1) { - /// Receiver in active mode - Active = 0x0, - /// Receiver in mute mode - Mute = 0x1, - }; - - pub const STOP = enum(u2) { - /// 1 stop bit - Stop1 = 0x0, - /// 0.5 stop bits - Stop0p5 = 0x1, - /// 2 stop bits - Stop2 = 0x2, - /// 1.5 stop bits - Stop1p5 = 0x3, + pub const MCOPRE = enum(u4) { + /// Divide by 1 + Div1 = 0x1, + /// Divide by 2 + Div2 = 0x2, + /// Divide by 3 + Div3 = 0x3, + /// Divide by 4 + Div4 = 0x4, + /// Divide by 5 + Div5 = 0x5, + /// Divide by 6 + Div6 = 0x6, + /// Divide by 7 + Div7 = 0x7, + /// Divide by 8 + Div8 = 0x8, + /// Divide by 9 + Div9 = 0x9, + /// Divide by 10 + Div10 = 0xa, + /// Divide by 11 + Div11 = 0xb, + /// Divide by 12 + Div12 = 0xc, + /// Divide by 13 + Div13 = 0xd, + /// Divide by 14 + Div14 = 0xe, + /// Divide by 15 + Div15 = 0xf, + _, }; - pub const WAKE = enum(u1) { - /// USART wakeup on idle line - IdleLine = 0x0, - /// USART wakeup on address mark - AddressMark = 0x1, + pub const NSPRIV = enum(u1) { + /// Read and write to RCC non-secure functions can be done by privileged or unprivileged access. + B_0x0 = 0x0, + /// Read and write to RCC non-secure functions can be done by privileged access only + B_0x1 = 0x1, }; - /// Universal asynchronous receiver transmitter - pub const UART = extern struct { - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise error flag - NE: u1, - /// Overrun error - ORE: u1, - /// Idle line detected - IDLE: u1, - /// Read data register not empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding: u22, - }), - /// Data register - DR: mmio.Mmio(packed struct(u32) { - /// Data value - DR: u9, - padding: u23, - }), - /// Baud rate register - BRR: mmio.Mmio(packed struct(u32) { - /// USARTDIV - BRR: u16, - padding: u16, - }), - /// Control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: packed union { - raw: u1, - value: RWU, - }, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: packed union { - raw: u1, - value: PS, - }, - /// Parity control enable - PCE: u1, - /// Receiver wakeup method - WAKE: packed union { - raw: u1, - value: WAKE, - }, - /// Word length - M0: packed union { - raw: u1, - value: M0, - }, - /// USART enable - UE: u1, - reserved15: u1, - /// Oversampling mode - OVER8: packed union { - raw: u1, - value: OVER8, - }, - padding: u16, - }), - /// Control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Address of the USART node - ADD: u4, - reserved5: u1, - /// Line break detection length - LBDL: packed union { - raw: u1, - value: LBDL, - }, - /// LIN break detection interrupt enable - LBDIE: u1, - reserved12: u5, - /// STOP bits - STOP: packed union { - raw: u2, - value: STOP, - }, - /// LIN mode enable - LINEN: u1, - padding: u17, - }), - /// Control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: packed union { - raw: u1, - value: IRLP, - }, - /// Half-duplex selection - HDSEL: u1, - reserved6: u2, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - padding: u24, - }), + pub const OCTOSPISEL = enum(u2) { + /// rcc_hclk selected as kernel clock (default after reset) + HCLK4 = 0x0, + /// pll1_q_ck selected as kernel clock + PLL1_Q = 0x1, + /// pll2_r_ck selected as kernel clock + PLL2_R = 0x2, + /// per_ck selected as kernel clock + PER = 0x3, }; - /// Universal synchronous asynchronous receiver transmitter - pub const USART = extern struct { - reserved16: [16]u8, - /// Control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: packed union { - raw: u1, - value: CPHA, - }, - /// Clock polarity - CPOL: packed union { - raw: u1, - value: CPOL, - }, - /// Clock enable - CLKEN: u1, - padding: u20, - }), - /// Control register 3 - CR3: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - reserved8: u2, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method enable - ONEBIT: u1, - padding: u20, - }), - /// Guard time and prescaler register - GTPR: mmio.Mmio(packed struct(u32) { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding: u16, - }), + pub const PERSEL = enum(u2) { + /// hsi_ker_ck selected as kernel clock (default after reset) + HSI = 0x0, + /// csi_ker_ck selected as kernel clock + CSI = 0x1, + /// hse_ck selected as kernel clock + HSE = 0x2, + _, }; - }; - pub const pwr_h7rm0399 = struct { - pub const SDLEVEL = enum(u2) { - Reset = 0x0, - V1_8 = 0x1, - V2_5 = 0x2, - V2_5_ALT = 0x3, + pub const PLLDIV = enum(u7) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + Div17 = 0x10, + Div18 = 0x11, + Div19 = 0x12, + Div20 = 0x13, + Div21 = 0x14, + Div22 = 0x15, + Div23 = 0x16, + Div24 = 0x17, + Div25 = 0x18, + Div26 = 0x19, + Div27 = 0x1a, + Div28 = 0x1b, + Div29 = 0x1c, + Div30 = 0x1d, + Div31 = 0x1e, + Div32 = 0x1f, + Div33 = 0x20, + Div34 = 0x21, + Div35 = 0x22, + Div36 = 0x23, + Div37 = 0x24, + Div38 = 0x25, + Div39 = 0x26, + Div40 = 0x27, + Div41 = 0x28, + Div42 = 0x29, + Div43 = 0x2a, + Div44 = 0x2b, + Div45 = 0x2c, + Div46 = 0x2d, + Div47 = 0x2e, + Div48 = 0x2f, + Div49 = 0x30, + Div50 = 0x31, + Div51 = 0x32, + Div52 = 0x33, + Div53 = 0x34, + Div54 = 0x35, + Div55 = 0x36, + Div56 = 0x37, + Div57 = 0x38, + Div58 = 0x39, + Div59 = 0x3a, + Div60 = 0x3b, + Div61 = 0x3c, + Div62 = 0x3d, + Div63 = 0x3e, + Div64 = 0x3f, + Div65 = 0x40, + Div66 = 0x41, + Div67 = 0x42, + Div68 = 0x43, + Div69 = 0x44, + Div70 = 0x45, + Div71 = 0x46, + Div72 = 0x47, + Div73 = 0x48, + Div74 = 0x49, + Div75 = 0x4a, + Div76 = 0x4b, + Div77 = 0x4c, + Div78 = 0x4d, + Div79 = 0x4e, + Div80 = 0x4f, + Div81 = 0x50, + Div82 = 0x51, + Div83 = 0x52, + Div84 = 0x53, + Div85 = 0x54, + Div86 = 0x55, + Div87 = 0x56, + Div88 = 0x57, + Div89 = 0x58, + Div90 = 0x59, + Div91 = 0x5a, + Div92 = 0x5b, + Div93 = 0x5c, + Div94 = 0x5d, + Div95 = 0x5e, + Div96 = 0x5f, + Div97 = 0x60, + Div98 = 0x61, + Div99 = 0x62, + Div100 = 0x63, + Div101 = 0x64, + Div102 = 0x65, + Div103 = 0x66, + Div104 = 0x67, + Div105 = 0x68, + Div106 = 0x69, + Div107 = 0x6a, + Div108 = 0x6b, + Div109 = 0x6c, + Div110 = 0x6d, + Div111 = 0x6e, + Div112 = 0x6f, + Div113 = 0x70, + Div114 = 0x71, + Div115 = 0x72, + Div116 = 0x73, + Div117 = 0x74, + Div118 = 0x75, + Div119 = 0x76, + Div120 = 0x77, + Div121 = 0x78, + Div122 = 0x79, + Div123 = 0x7a, + Div124 = 0x7b, + Div125 = 0x7c, + Div126 = 0x7d, + Div127 = 0x7e, + Div128 = 0x7f, }; - pub const VOS = enum(u2) { - Scale3 = 0x1, - Scale2 = 0x2, - Scale1 = 0x3, + pub const PLLM = enum(u6) { + Div1 = 0x1, + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + Div16 = 0x10, + Div17 = 0x11, + Div18 = 0x12, + Div19 = 0x13, + Div20 = 0x14, + Div21 = 0x15, + Div22 = 0x16, + Div23 = 0x17, + Div24 = 0x18, + Div25 = 0x19, + Div26 = 0x1a, + Div27 = 0x1b, + Div28 = 0x1c, + Div29 = 0x1d, + Div30 = 0x1e, + Div31 = 0x1f, + Div32 = 0x20, + Div33 = 0x21, + Div34 = 0x22, + Div35 = 0x23, + Div36 = 0x24, + Div37 = 0x25, + Div38 = 0x26, + Div39 = 0x27, + Div40 = 0x28, + Div41 = 0x29, + Div42 = 0x2a, + Div43 = 0x2b, + Div44 = 0x2c, + Div45 = 0x2d, + Div46 = 0x2e, + Div47 = 0x2f, + Div48 = 0x30, + Div49 = 0x31, + Div50 = 0x32, + Div51 = 0x33, + Div52 = 0x34, + Div53 = 0x35, + Div54 = 0x36, + Div55 = 0x37, + Div56 = 0x38, + Div57 = 0x39, + Div58 = 0x3a, + Div59 = 0x3b, + Div60 = 0x3c, + Div61 = 0x3d, + Div62 = 0x3e, _, }; - pub const WKUPPUPD = enum(u2) { - /// No pull-up. - NoPull = 0x0, - /// Pull-up. - PullUp = 0x1, - /// Pull-down. - PullDown = 0x2, + pub const PLLN = enum(u9) { + Mul4 = 0x3, + Mul5 = 0x4, + Mul6 = 0x5, + Mul7 = 0x6, + Mul8 = 0x7, + Mul9 = 0x8, + Mul10 = 0x9, + Mul11 = 0xa, + Mul12 = 0xb, + Mul13 = 0xc, + Mul14 = 0xd, + Mul15 = 0xe, + Mul16 = 0xf, + Mul17 = 0x10, + Mul18 = 0x11, + Mul19 = 0x12, + Mul20 = 0x13, + Mul21 = 0x14, + Mul22 = 0x15, + Mul23 = 0x16, + Mul24 = 0x17, + Mul25 = 0x18, + Mul26 = 0x19, + Mul27 = 0x1a, + Mul28 = 0x1b, + Mul29 = 0x1c, + Mul30 = 0x1d, + Mul31 = 0x1e, + Mul32 = 0x1f, + Mul33 = 0x20, + Mul34 = 0x21, + Mul35 = 0x22, + Mul36 = 0x23, + Mul37 = 0x24, + Mul38 = 0x25, + Mul39 = 0x26, + Mul40 = 0x27, + Mul41 = 0x28, + Mul42 = 0x29, + Mul43 = 0x2a, + Mul44 = 0x2b, + Mul45 = 0x2c, + Mul46 = 0x2d, + Mul47 = 0x2e, + Mul48 = 0x2f, + Mul49 = 0x30, + Mul50 = 0x31, + Mul51 = 0x32, + Mul52 = 0x33, + Mul53 = 0x34, + Mul54 = 0x35, + Mul55 = 0x36, + Mul56 = 0x37, + Mul57 = 0x38, + Mul58 = 0x39, + Mul59 = 0x3a, + Mul60 = 0x3b, + Mul61 = 0x3c, + Mul62 = 0x3d, + Mul63 = 0x3e, + Mul64 = 0x3f, + Mul65 = 0x40, + Mul66 = 0x41, + Mul67 = 0x42, + Mul68 = 0x43, + Mul69 = 0x44, + Mul70 = 0x45, + Mul71 = 0x46, + Mul72 = 0x47, + Mul73 = 0x48, + Mul74 = 0x49, + Mul75 = 0x4a, + Mul76 = 0x4b, + Mul77 = 0x4c, + Mul78 = 0x4d, + Mul79 = 0x4e, + Mul80 = 0x4f, + Mul81 = 0x50, + Mul82 = 0x51, + Mul83 = 0x52, + Mul84 = 0x53, + Mul85 = 0x54, + Mul86 = 0x55, + Mul87 = 0x56, + Mul88 = 0x57, + Mul89 = 0x58, + Mul90 = 0x59, + Mul91 = 0x5a, + Mul92 = 0x5b, + Mul93 = 0x5c, + Mul94 = 0x5d, + Mul95 = 0x5e, + Mul96 = 0x5f, + Mul97 = 0x60, + Mul98 = 0x61, + Mul99 = 0x62, + Mul100 = 0x63, + Mul101 = 0x64, + Mul102 = 0x65, + Mul103 = 0x66, + Mul104 = 0x67, + Mul105 = 0x68, + Mul106 = 0x69, + Mul107 = 0x6a, + Mul108 = 0x6b, + Mul109 = 0x6c, + Mul110 = 0x6d, + Mul111 = 0x6e, + Mul112 = 0x6f, + Mul113 = 0x70, + Mul114 = 0x71, + Mul115 = 0x72, + Mul116 = 0x73, + Mul117 = 0x74, + Mul118 = 0x75, + Mul119 = 0x76, + Mul120 = 0x77, + Mul121 = 0x78, + Mul122 = 0x79, + Mul123 = 0x7a, + Mul124 = 0x7b, + Mul125 = 0x7c, + Mul126 = 0x7d, + Mul127 = 0x7e, + Mul128 = 0x7f, + Mul129 = 0x80, + Mul130 = 0x81, + Mul131 = 0x82, + Mul132 = 0x83, + Mul133 = 0x84, + Mul134 = 0x85, + Mul135 = 0x86, + Mul136 = 0x87, + Mul137 = 0x88, + Mul138 = 0x89, + Mul139 = 0x8a, + Mul140 = 0x8b, + Mul141 = 0x8c, + Mul142 = 0x8d, + Mul143 = 0x8e, + Mul144 = 0x8f, + Mul145 = 0x90, + Mul146 = 0x91, + Mul147 = 0x92, + Mul148 = 0x93, + Mul149 = 0x94, + Mul150 = 0x95, + Mul151 = 0x96, + Mul152 = 0x97, + Mul153 = 0x98, + Mul154 = 0x99, + Mul155 = 0x9a, + Mul156 = 0x9b, + Mul157 = 0x9c, + Mul158 = 0x9d, + Mul159 = 0x9e, + Mul160 = 0x9f, + Mul161 = 0xa0, + Mul162 = 0xa1, + Mul163 = 0xa2, + Mul164 = 0xa3, + Mul165 = 0xa4, + Mul166 = 0xa5, + Mul167 = 0xa6, + Mul168 = 0xa7, + Mul169 = 0xa8, + Mul170 = 0xa9, + Mul171 = 0xaa, + Mul172 = 0xab, + Mul173 = 0xac, + Mul174 = 0xad, + Mul175 = 0xae, + Mul176 = 0xaf, + Mul177 = 0xb0, + Mul178 = 0xb1, + Mul179 = 0xb2, + Mul180 = 0xb3, + Mul181 = 0xb4, + Mul182 = 0xb5, + Mul183 = 0xb6, + Mul184 = 0xb7, + Mul185 = 0xb8, + Mul186 = 0xb9, + Mul187 = 0xba, + Mul188 = 0xbb, + Mul189 = 0xbc, + Mul190 = 0xbd, + Mul191 = 0xbe, + Mul192 = 0xbf, + Mul193 = 0xc0, + Mul194 = 0xc1, + Mul195 = 0xc2, + Mul196 = 0xc3, + Mul197 = 0xc4, + Mul198 = 0xc5, + Mul199 = 0xc6, + Mul200 = 0xc7, + Mul201 = 0xc8, + Mul202 = 0xc9, + Mul203 = 0xca, + Mul204 = 0xcb, + Mul205 = 0xcc, + Mul206 = 0xcd, + Mul207 = 0xce, + Mul208 = 0xcf, + Mul209 = 0xd0, + Mul210 = 0xd1, + Mul211 = 0xd2, + Mul212 = 0xd3, + Mul213 = 0xd4, + Mul214 = 0xd5, + Mul215 = 0xd6, + Mul216 = 0xd7, + Mul217 = 0xd8, + Mul218 = 0xd9, + Mul219 = 0xda, + Mul220 = 0xdb, + Mul221 = 0xdc, + Mul222 = 0xdd, + Mul223 = 0xde, + Mul224 = 0xdf, + Mul225 = 0xe0, + Mul226 = 0xe1, + Mul227 = 0xe2, + Mul228 = 0xe3, + Mul229 = 0xe4, + Mul230 = 0xe5, + Mul231 = 0xe6, + Mul232 = 0xe7, + Mul233 = 0xe8, + Mul234 = 0xe9, + Mul235 = 0xea, + Mul236 = 0xeb, + Mul237 = 0xec, + Mul238 = 0xed, + Mul239 = 0xee, + Mul240 = 0xef, + Mul241 = 0xf0, + Mul242 = 0xf1, + Mul243 = 0xf2, + Mul244 = 0xf3, + Mul245 = 0xf4, + Mul246 = 0xf5, + Mul247 = 0xf6, + Mul248 = 0xf7, + Mul249 = 0xf8, + Mul250 = 0xf9, + Mul251 = 0xfa, + Mul252 = 0xfb, + Mul253 = 0xfc, + Mul254 = 0xfd, + Mul255 = 0xfe, + Mul256 = 0xff, + Mul257 = 0x100, + Mul258 = 0x101, + Mul259 = 0x102, + Mul260 = 0x103, + Mul261 = 0x104, + Mul262 = 0x105, + Mul263 = 0x106, + Mul264 = 0x107, + Mul265 = 0x108, + Mul266 = 0x109, + Mul267 = 0x10a, + Mul268 = 0x10b, + Mul269 = 0x10c, + Mul270 = 0x10d, + Mul271 = 0x10e, + Mul272 = 0x10f, + Mul273 = 0x110, + Mul274 = 0x111, + Mul275 = 0x112, + Mul276 = 0x113, + Mul277 = 0x114, + Mul278 = 0x115, + Mul279 = 0x116, + Mul280 = 0x117, + Mul281 = 0x118, + Mul282 = 0x119, + Mul283 = 0x11a, + Mul284 = 0x11b, + Mul285 = 0x11c, + Mul286 = 0x11d, + Mul287 = 0x11e, + Mul288 = 0x11f, + Mul289 = 0x120, + Mul290 = 0x121, + Mul291 = 0x122, + Mul292 = 0x123, + Mul293 = 0x124, + Mul294 = 0x125, + Mul295 = 0x126, + Mul296 = 0x127, + Mul297 = 0x128, + Mul298 = 0x129, + Mul299 = 0x12a, + Mul300 = 0x12b, + Mul301 = 0x12c, + Mul302 = 0x12d, + Mul303 = 0x12e, + Mul304 = 0x12f, + Mul305 = 0x130, + Mul306 = 0x131, + Mul307 = 0x132, + Mul308 = 0x133, + Mul309 = 0x134, + Mul310 = 0x135, + Mul311 = 0x136, + Mul312 = 0x137, + Mul313 = 0x138, + Mul314 = 0x139, + Mul315 = 0x13a, + Mul316 = 0x13b, + Mul317 = 0x13c, + Mul318 = 0x13d, + Mul319 = 0x13e, + Mul320 = 0x13f, + Mul321 = 0x140, + Mul322 = 0x141, + Mul323 = 0x142, + Mul324 = 0x143, + Mul325 = 0x144, + Mul326 = 0x145, + Mul327 = 0x146, + Mul328 = 0x147, + Mul329 = 0x148, + Mul330 = 0x149, + Mul331 = 0x14a, + Mul332 = 0x14b, + Mul333 = 0x14c, + Mul334 = 0x14d, + Mul335 = 0x14e, + Mul336 = 0x14f, + Mul337 = 0x150, + Mul338 = 0x151, + Mul339 = 0x152, + Mul340 = 0x153, + Mul341 = 0x154, + Mul342 = 0x155, + Mul343 = 0x156, + Mul344 = 0x157, + Mul345 = 0x158, + Mul346 = 0x159, + Mul347 = 0x15a, + Mul348 = 0x15b, + Mul349 = 0x15c, + Mul350 = 0x15d, + Mul351 = 0x15e, + Mul352 = 0x15f, + Mul353 = 0x160, + Mul354 = 0x161, + Mul355 = 0x162, + Mul356 = 0x163, + Mul357 = 0x164, + Mul358 = 0x165, + Mul359 = 0x166, + Mul360 = 0x167, + Mul361 = 0x168, + Mul362 = 0x169, + Mul363 = 0x16a, + Mul364 = 0x16b, + Mul365 = 0x16c, + Mul366 = 0x16d, + Mul367 = 0x16e, + Mul368 = 0x16f, + Mul369 = 0x170, + Mul370 = 0x171, + Mul371 = 0x172, + Mul372 = 0x173, + Mul373 = 0x174, + Mul374 = 0x175, + Mul375 = 0x176, + Mul376 = 0x177, + Mul377 = 0x178, + Mul378 = 0x179, + Mul379 = 0x17a, + Mul380 = 0x17b, + Mul381 = 0x17c, + Mul382 = 0x17d, + Mul383 = 0x17e, + Mul384 = 0x17f, + Mul385 = 0x180, + Mul386 = 0x181, + Mul387 = 0x182, + Mul388 = 0x183, + Mul389 = 0x184, + Mul390 = 0x185, + Mul391 = 0x186, + Mul392 = 0x187, + Mul393 = 0x188, + Mul394 = 0x189, + Mul395 = 0x18a, + Mul396 = 0x18b, + Mul397 = 0x18c, + Mul398 = 0x18d, + Mul399 = 0x18e, + Mul400 = 0x18f, + Mul401 = 0x190, + Mul402 = 0x191, + Mul403 = 0x192, + Mul404 = 0x193, + Mul405 = 0x194, + Mul406 = 0x195, + Mul407 = 0x196, + Mul408 = 0x197, + Mul409 = 0x198, + Mul410 = 0x199, + Mul411 = 0x19a, + Mul412 = 0x19b, + Mul413 = 0x19c, + Mul414 = 0x19d, + Mul415 = 0x19e, + Mul416 = 0x19f, + Mul417 = 0x1a0, + Mul418 = 0x1a1, + Mul419 = 0x1a2, + Mul420 = 0x1a3, + Mul421 = 0x1a4, + Mul422 = 0x1a5, + Mul423 = 0x1a6, + Mul424 = 0x1a7, + Mul425 = 0x1a8, + Mul426 = 0x1a9, + Mul427 = 0x1aa, + Mul428 = 0x1ab, + Mul429 = 0x1ac, + Mul430 = 0x1ad, + Mul431 = 0x1ae, + Mul432 = 0x1af, + Mul433 = 0x1b0, + Mul434 = 0x1b1, + Mul435 = 0x1b2, + Mul436 = 0x1b3, + Mul437 = 0x1b4, + Mul438 = 0x1b5, + Mul439 = 0x1b6, + Mul440 = 0x1b7, + Mul441 = 0x1b8, + Mul442 = 0x1b9, + Mul443 = 0x1ba, + Mul444 = 0x1bb, + Mul445 = 0x1bc, + Mul446 = 0x1bd, + Mul447 = 0x1be, + Mul448 = 0x1bf, + Mul449 = 0x1c0, + Mul450 = 0x1c1, + Mul451 = 0x1c2, + Mul452 = 0x1c3, + Mul453 = 0x1c4, + Mul454 = 0x1c5, + Mul455 = 0x1c6, + Mul456 = 0x1c7, + Mul457 = 0x1c8, + Mul458 = 0x1c9, + Mul459 = 0x1ca, + Mul460 = 0x1cb, + Mul461 = 0x1cc, + Mul462 = 0x1cd, + Mul463 = 0x1ce, + Mul464 = 0x1cf, + Mul465 = 0x1d0, + Mul466 = 0x1d1, + Mul467 = 0x1d2, + Mul468 = 0x1d3, + Mul469 = 0x1d4, + Mul470 = 0x1d5, + Mul471 = 0x1d6, + Mul472 = 0x1d7, + Mul473 = 0x1d8, + Mul474 = 0x1d9, + Mul475 = 0x1da, + Mul476 = 0x1db, + Mul477 = 0x1dc, + Mul478 = 0x1dd, + Mul479 = 0x1de, + Mul480 = 0x1df, + Mul481 = 0x1e0, + Mul482 = 0x1e1, + Mul483 = 0x1e2, + Mul484 = 0x1e3, + Mul485 = 0x1e4, + Mul486 = 0x1e5, + Mul487 = 0x1e6, + Mul488 = 0x1e7, + Mul489 = 0x1e8, + Mul490 = 0x1e9, + Mul491 = 0x1ea, + Mul492 = 0x1eb, + Mul493 = 0x1ec, + Mul494 = 0x1ed, + Mul495 = 0x1ee, + Mul496 = 0x1ef, + Mul497 = 0x1f0, + Mul498 = 0x1f1, + Mul499 = 0x1f2, + Mul500 = 0x1f3, + Mul501 = 0x1f4, + Mul502 = 0x1f5, + Mul503 = 0x1f6, + Mul504 = 0x1f7, + Mul505 = 0x1f8, + Mul506 = 0x1f9, + Mul507 = 0x1fa, + Mul508 = 0x1fb, + Mul509 = 0x1fc, + Mul510 = 0x1fd, + Mul511 = 0x1fe, + Mul512 = 0x1ff, _, }; - /// PWR - pub const PWR = extern struct { - /// PWR control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) - LPDS: u1, - reserved4: u3, - /// Programmable voltage detector enable - PVDE: u1, - /// Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. - PLS: u3, - /// Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. - DBP: u1, - /// Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. - FLPS: u1, - reserved14: u4, - /// System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. - SVOS: u2, - /// Peripheral voltage monitor on VDDA enable - AVDEN: u1, - /// Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. - ALS: u2, - padding: u13, - }), - /// PWR control status register 1 - CSR1: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. - PVDO: u1, - reserved13: u8, - /// Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). - ACTVOSRDY: u1, - /// VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. - ACTVOS: u2, - /// Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set. - AVDO: u1, - padding: u15, - }), - /// This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. - CR2: mmio.Mmio(packed struct(u32) { - /// Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. - BREN: u1, - reserved4: u3, - /// VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. - MONEN: u1, - reserved16: u11, - /// Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. - BRRDY: u1, - reserved20: u3, - /// VBAT level monitoring versus low threshold - VBATL: u1, - /// VBAT level monitoring versus high threshold - VBATH: u1, - /// Temperature level monitoring versus low threshold - TEMPL: u1, - /// Temperature level monitoring versus high threshold - TEMPH: u1, - padding: u8, - }), - /// Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value. - CR3: mmio.Mmio(packed struct(u32) { - /// Power management unit bypass - BYPASS: u1, - /// Low drop-out regulator enable - LDOEN: u1, - /// SD converter Enable - SDEN: u1, - /// Step-down converter forced ON and in High Power MR mode - SDEXTHP: u1, - /// Step-down converter voltage output level selection - SDLEVEL: packed union { - raw: u2, - value: SDLEVEL, - }, - reserved8: u2, - /// VBAT charging enable - VBE: u1, - /// VBAT charging resistor selection - VBRS: u1, - reserved16: u6, - /// SMPS step-down converter external supply ready - SDEXTRDY: u1, - reserved24: u7, - /// VDD33USB voltage level detector enable. - USB33DEN: u1, - /// USB regulator enable. - USBREGEN: u1, - /// USB supply ready. - USB33RDY: u1, - padding: u5, - }), - /// This register allows controlling CPU1 power. - CPUCR: mmio.Mmio(packed struct(u32) { - /// D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. - PDDS_D1: u1, - /// D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. - PDDS_D2: u1, - /// System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. - PDDS_D3: u1, - reserved5: u2, - /// STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. - STOPF: u1, - /// System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit - SBF: u1, - /// D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. - SBF_D1: u1, - /// D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. - SBF_D2: u1, - /// Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. - CSSF: u1, - reserved11: u1, - /// Keep system D3 domain in Run mode regardless of the CPU sub-systems modes - RUN_D3: u1, - padding: u20, - }), - reserved24: [4]u8, - /// This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software - D3CR: mmio.Mmio(packed struct(u32) { - reserved13: u13, - /// VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). - VOSRDY: u1, - /// Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling. - VOS: packed union { - raw: u2, - value: VOS, - }, - padding: u16, - }), - reserved32: [4]u8, - /// reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). - WKUPCR: mmio.Mmio(packed struct(u32) { - /// Clear Wakeup pin flag for WKUP. These bits are always read as 0. - WKUPC: u6, - padding: u26, - }), - /// reset only by system reset, not reset by wakeup from Standby mode - WKUPFR: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). - WKUPF: u1, - padding: u31, - }), - /// Reset only by system reset, not reset by wakeup from Standby mode - WKUPEPR: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. - WKUPEN: u1, - reserved8: u7, - /// Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. - WKUPP: u1, - reserved16: u7, - /// Wakeup pin pull configuration - WKUPPUPD: packed union { - raw: u2, - value: WKUPPUPD, - }, - padding: u14, - }), + pub const PLLRGE = enum(u2) { + /// Frequency is between 1 and 2 MHz + Range1 = 0x0, + /// Frequency is between 2 and 4 MHz + Range2 = 0x1, + /// Frequency is between 4 and 8 MHz + Range4 = 0x2, + /// Frequency is between 8 and 16 MHz + Range8 = 0x3, }; - }; - pub const adc_f3 = struct { - pub const ADVREGEN = enum(u2) { - /// Intermediate state required when moving the ADC voltage regulator between states - Intermediate = 0x0, - /// ADC voltage regulator enabled - Enabled = 0x1, - /// ADC voltage regulator disabled - Disabled = 0x2, + pub const PLLSRC = enum(u2) { + /// no clock send to DIVMx divider and PLLs (default after reset) + DISABLE = 0x0, + /// HSI selected as PLL clock (hsi_ck) + HSI = 0x1, + /// CSI selected as PLL clock (csi_ck) + CSI = 0x2, + /// HSE selected as PLL clock (hse_ck) + HSE = 0x3, + }; + + pub const PLLVCOSEL = enum(u1) { + /// VCO frequency range 192 to 836 MHz + WideVCO = 0x0, + /// VCO frequency range 150 to 420 MHz + MediumVCO = 0x1, + }; + + pub const PPRE = enum(u3) { + /// rcc_pclk3 = rcc_hclk1 / 1 + Div1 = 0x0, + /// rcc_pclk3 = rcc_hclk1 / 2 + Div2 = 0x4, + /// rcc_pclk3 = rcc_hclk1 / 4 + Div4 = 0x5, + /// rcc_pclk3 = rcc_hclk1 / 8 + Div8 = 0x6, + /// rcc_pclk3 = rcc_hclk1 / 16 + Div16 = 0x7, _, }; - pub const ALIGN = enum(u1) { - /// Right alignment - Right = 0x0, - /// Left alignment - Left = 0x1, + pub const RNGSEL = enum(u2) { + /// hsi48_ker_ck selected as kernel clock (default after reset) + HSI48 = 0x0, + /// pll1_q_ck selected as kernel clock + PLL1_Q = 0x1, + /// lse_ck selected as kernel clock + LSE = 0x2, + /// lsi_ker_ck selected as kernel clock + LSI = 0x3, }; - pub const AWD1SGL = enum(u1) { - /// Analog watchdog 1 enabled on all channels - All = 0x0, - /// Analog watchdog 1 enabled on single channel selected in AWD1CH - Single = 0x1, + pub const RTCSEL = enum(u2) { + /// no clock (default after Backup domain reset) + DISABLE = 0x0, + /// LSE selected as RTC clock + LSE = 0x1, + /// LSI selected as RTC clock + LSI = 0x2, + /// HSE divided by RTCPRE value selected as RTC clock + HSE_DIV_RTCPRE = 0x3, }; - pub const DIFSEL_10 = enum(u1) { - /// Input channel is configured in single-ended mode - SingleEnded = 0x0, - /// Input channel is configured in differential mode - Differential = 0x1, + pub const SAISEL = enum(u3) { + /// pll1_q_ck selected as kernel clock (default after reset) + PLL1_Q = 0x0, + /// pll2_p_ck selected as kernel clock + PLL2_P = 0x1, + /// pll3_p_ck selected as kernel clock + PLL3_P = 0x2, + /// AUDIOCLK selected as kernel clock + AUDIOCLK = 0x3, + /// per_ck selected as kernel clock + PER = 0x4, + _, }; - pub const DMACFG = enum(u1) { - /// DMA One Shot mode selected - OneShot = 0x0, - /// DMA Circular mode selected - Circular = 0x1, + pub const SDMMCSEL = enum(u1) { + /// pll1_q_ck selected as kernel clock (default after reset) + PLL1_Q = 0x0, + /// pll2_r_ck selected as kernel clock + PLL2_R = 0x1, }; - pub const EXTEN = enum(u2) { - /// Trigger detection disabled - Disabled = 0x0, - /// Trigger detection on the rising edge - RisingEdge = 0x1, - /// Trigger detection on the falling edge - FallingEdge = 0x2, - /// Trigger detection on both the rising and falling edges - BothEdges = 0x3, + pub const SPI1SEL = enum(u3) { + /// pll1_q_ck selected as kernel clock (default after reset) + PLL1_Q = 0x0, + /// pll2_p_ck selected as kernel clock + PLL2_P = 0x1, + /// pll3_p_ck selected as kernel clock + PLL3_P = 0x2, + /// AUDIOCLK selected as kernel clock + AUDIOCLK = 0x3, + /// per_ck selected as kernel clock + PER = 0x4, + _, }; - pub const JEXTEN = enum(u2) { - /// Trigger detection disabled - Disabled = 0x0, - /// Trigger detection on the rising edge - RisingEdge = 0x1, - /// Trigger detection on the falling edge - FallingEdge = 0x2, - /// Trigger detection on both the rising and falling edges - BothEdges = 0x3, + pub const SPI2SEL = enum(u3) { + /// pll1_q_ck selected as kernel clock (default after reset) + PLL1_Q = 0x0, + /// pll2_p_ck selected as kernel clock + PLL2_P = 0x1, + /// pll3_p_ck selected as kernel clock + PLL3_P = 0x2, + /// AUDIOCLK selected as kernel clock + AUDIOCLK = 0x3, + /// per_ck selected as kernel clock + PER = 0x4, + _, }; - pub const JQM = enum(u1) { - /// JSQR Mode 0: Queue maintains the last written configuration into JSQR - Mode0 = 0x0, - /// JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence - Mode1 = 0x1, + pub const SPI3SEL = enum(u3) { + /// pll1_q_ck selected as kernel clock (default after reset) + PLL1_Q = 0x0, + /// pll2_p_ck selected as kernel clock + PLL2_P = 0x1, + /// pll3_p_ck selected as kernel clock + PLL3_P = 0x2, + /// AUDIOCLK selected as kernel clock + AUDIOCLK = 0x3, + /// per_ck selected as kernel clock + PER = 0x4, + _, }; - pub const RES = enum(u2) { - /// 12-bit resolution - Bits12 = 0x0, - /// 10-bit resolution - Bits10 = 0x1, - /// 8-bit resolution - Bits8 = 0x2, - /// 6-bit resolution - Bits6 = 0x3, + pub const SPI4SEL = enum(u3) { + /// rcc_pclk2 selected as kernel clock (default after reset) + PCLK2 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// HSE selected as peripheral clock + HSE = 0x5, + _, }; - pub const SAMPLE_TIME = enum(u3) { - /// 1.5 ADC clock cycles - Cycles1_5 = 0x0, - /// 2.5 ADC clock cycles - Cycles2_5 = 0x1, - /// 4.5 ADC clock cycles - Cycles4_5 = 0x2, - /// 7.5 ADC clock cycles - Cycles7_5 = 0x3, - /// 19.5 ADC clock cycles - Cycles19_5 = 0x4, - /// 61.5 ADC clock cycles - Cycles61_5 = 0x5, - /// 181.5 ADC clock cycles - Cycles181_5 = 0x6, - /// 601.5 ADC clock cycles - Cycles601_5 = 0x7, + pub const SPI5SEL = enum(u3) { + /// rcc_pclk3 selected as kernel clock (default after reset) + PCLK3 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// HSE selected as peripheral clock + HSE = 0x5, + _, }; - /// Analog-to-Digital Converter - pub const ADC = extern struct { - /// interrupt and status register - ISR: mmio.Mmio(packed struct(u32) { - /// ADC Ready - ADRDY: u1, - /// End of sampling flag - EOSMP: u1, - /// End of conversion flag - EOC: u1, - /// End of regular sequence flag - EOS: u1, - /// ADC overrun - OVR: u1, - /// Injected channel end of conversion flag - JEOC: u1, - /// Injected channel end of sequence flag - JEOS: u1, - /// Analog watchdog flag - AWD: u1, - reserved10: u2, - /// Injected context queue overflow - JQOVF: u1, - padding: u21, - }), - /// interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// ADC ready interrupt enable - ADRDYIE: u1, - /// End of sampling flag interrupt enable for regular conversions - EOSMPIE: u1, - /// End of regular conversion interrupt enable - EOCIE: u1, - /// End of regular sequence of conversions interrupt enable - EOSIE: u1, - /// Overrun interrupt enable - OVRIE: u1, - /// End of injected conversion interrupt enable - JEOCIE: u1, - /// End of injected sequence of conversions interrupt enable - JEOSIE: u1, - /// Analog watchdog X interrupt enable - AWDIE: u1, - reserved10: u2, - /// Injected context queue overflow interrupt enable - JQOVFIE: u1, - padding: u21, - }), - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// ADC enable control - ADEN: u1, - /// ADC disable command - ADDIS: u1, - /// ADC start of regular conversion - ADSTART: u1, - /// ADC start of injected conversion - JADSTART: u1, - /// ADC stop of regular conversion command - ADSTP: u1, - /// ADC stop of injected conversion command - JADSTP: u1, - reserved28: u22, - /// ADC voltage regulator enable - ADVREGEN: packed union { - raw: u2, - value: ADVREGEN, - }, - /// Differential mode for calibration - ADCALDIF: u1, - /// ADC calibration - ADCAL: u1, - }), - /// configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// Direct memory access enable - DMAEN: u1, - /// Direct memory access configuration - DMACFG: packed union { - raw: u1, - value: DMACFG, - }, - reserved3: u1, - /// Data resolution - RES: packed union { - raw: u2, - value: RES, - }, - /// Data alignment - ALIGN: packed union { - raw: u1, - value: ALIGN, - }, - /// External trigger selection for regular group - EXTSEL: u4, - /// External trigger enable and polarity selection for regular channels - EXTEN: packed union { - raw: u2, - value: EXTEN, - }, - /// Overrun Mode - OVRMOD: u1, - /// Continuous conversion - CONT: u1, - /// Delayed conversion mode - AUTDLY: u1, - reserved16: u1, - /// Discontinuous mode for regular channels - DISCEN: u1, - /// Discontinuous mode channel count - DISCNUM: u3, - /// Discontinuous mode on injected channels - JDISCEN: u1, - /// JSQR queue mode - JQM: packed union { - raw: u1, - value: JQM, - }, - /// Enable the watchdog 1 on a single channel or on all channels - AWD1SGL: packed union { - raw: u1, - value: AWD1SGL, - }, - /// Analog watchdog 1 enable on regular channels - AWD1EN: u1, - /// Analog watchdog 1 enable on injected channels - JAWD1EN: u1, - /// Automatic injected group conversion - JAUTO: u1, - /// Analog watchdog 1 channel selection - AWD1CH: u5, - padding: u1, - }), - reserved20: [4]u8, - /// sample time register 1 - SMPR1: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Channel x sampling time selection - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - padding: u26, - }), - /// sample time register 2 - SMPR2: mmio.Mmio(packed struct(u32) { - /// Channel x sampling time selection - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - padding: u29, - }), - reserved32: [4]u8, - /// watchdog threshold register 1 - TR1: mmio.Mmio(packed struct(u32) { - /// LT1 - LT1: u12, - reserved16: u4, - /// HT1 - HT1: u12, - padding: u4, - }), - /// watchdog threshold register - TR2: mmio.Mmio(packed struct(u32) { - /// LT2 - LT2: u8, - reserved16: u8, - /// HT2 - HT2: u8, - padding: u8, - }), - /// watchdog threshold register 3 - TR3: mmio.Mmio(packed struct(u32) { - /// LT3 - LT3: u8, - reserved16: u8, - /// HT3 - HT3: u8, - padding: u8, - }), - reserved48: [4]u8, - /// regular sequence register 1 - SQR1: mmio.Mmio(packed struct(u32) { - /// Regular channel sequence length - L: u4, - reserved6: u2, - /// X conversion in regular sequence - SQ: u5, - padding: u21, - }), - /// regular sequence register 2 - SQR2: mmio.Mmio(packed struct(u32) { - /// X conversion in regular sequence - SQ: u5, - padding: u27, - }), - /// regular sequence register 3 - SQR3: mmio.Mmio(packed struct(u32) { - /// X conversion in regular sequence - SQ: u5, - padding: u27, - }), - /// regular sequence register 4 - SQR4: mmio.Mmio(packed struct(u32) { - /// X conversion in regular sequence - SQ: u5, - padding: u27, - }), - /// regular Data Register - DR: mmio.Mmio(packed struct(u32) { - /// Regular data - RDATA: u16, - padding: u16, - }), - reserved76: [8]u8, - /// injected sequence register - JSQR: mmio.Mmio(packed struct(u32) { - /// Injected channel sequence length - JL: u2, - /// External Trigger Selection for injected group - JEXTSEL: u4, - /// External Trigger Enable and Polarity Selection for injected channels - JEXTEN: packed union { - raw: u2, - value: JEXTEN, - }, - /// X conversion in the injected sequence - JSQ: u5, - padding: u19, - }), - reserved96: [16]u8, - /// offset register X - OFR: [4]mmio.Mmio(packed struct(u32) { - /// Data offset y for the channel programmed into bits OFFSETy_CH - OFFSET: u12, - reserved26: u14, - /// Data offset y for the channel programmed into bits OFFSETy_CH - CH: u5, - /// Offset y Enable - EN: u1, - }), - reserved128: [16]u8, - /// injected data register X - JDR: [4]mmio.Mmio(packed struct(u32) { - /// Injected data - JDATA: u16, - padding: u16, - }), - reserved160: [16]u8, - /// Analog Watchdog X Configuration Register - AWDCR: [2]mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// AWD2CH - AWD2CH0: u1, - padding: u30, - }), - reserved176: [8]u8, - /// Differential Mode Selection Register 2 - DIFSEL: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Differential mode for channels 15 to 1 - DIFSEL_10: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_11: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_12: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_13: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_14: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_15: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_16: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_17: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_18: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_19: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_110: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_111: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_112: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_113: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_114: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_115: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_116: packed union { - raw: u1, - value: DIFSEL_10, - }, - /// Differential mode for channels 15 to 1 - DIFSEL_117: packed union { - raw: u1, - value: DIFSEL_10, - }, - padding: u13, - }), - /// Calibration Factors - CALFACT: mmio.Mmio(packed struct(u32) { - /// CALFACT_S - CALFACT_S: u7, - reserved16: u9, - /// CALFACT_D - CALFACT_D: u7, - padding: u9, - }), - }; - }; - - pub const pwr_l0 = struct { - pub const DS_EE_KOFF = enum(u1) { - /// NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set - NVMWakeUp = 0x0, - /// NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set) - NVMSleep = 0x1, + pub const SPI6SEL = enum(u3) { + /// rcc_pclk2 selected as peripheral clock + PCLK2 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// HSE selected as peripheral clock + HSE = 0x5, + _, }; - pub const MODE = enum(u1) { - /// Voltage regulator in Main mode - MAIN_MODE = 0x0, - /// Voltage regulator switches to low-power mode - LOW_POWER_MODE = 0x1, + pub const SPRIV = enum(u1) { + /// Read and write to RCC secure functions can be done by privileged or unprivileged access. + Any = 0x0, + /// Read and write to RCC secure functions can be done by privileged access only + Privileged = 0x1, }; - pub const PDDS = enum(u1) { - /// Enter Stop mode when the CPU enters deepsleep - STOP_MODE = 0x0, - /// Enter Standby mode when the CPU enters deepsleep - STANDBY_MODE = 0x1, + pub const STOPKERWUCK = enum(u1) { + /// HSI selected as wakeup clock from system Stop (default after reset) + HSI = 0x0, + /// CSI selected as wakeup clock from system Stop + CSI = 0x1, }; - pub const PLS = enum(u3) { - /// 1.9 V - V1_9 = 0x0, - /// 2.1 V - V2_1 = 0x1, - /// 2.3 V - V2_3 = 0x2, - /// 2.5 V - V2_5 = 0x3, - /// 2.7 V - V2_7 = 0x4, - /// 2.9 V - V2_9 = 0x5, - /// 3.1 V - V3_1 = 0x6, - /// External input analog voltage (Compare internally to VREFINT) - External = 0x7, + pub const STOPWUCK = enum(u1) { + /// CSI selected as wakeup clock from system Stop + CSI = 0x1, + _, }; - pub const VOS = enum(u2) { - /// 1.8 V (range 1) - Range1 = 0x1, - /// 1.5 V (range 2) - Range2 = 0x2, - /// 1.2 V (range 3) - Range3 = 0x3, + pub const SW = enum(u3) { + /// HSI selected as system clock + HSI = 0x0, + /// CSI selected as system clock + CSI = 0x1, + /// HSE selected as system clock + HSE = 0x2, + /// PLL1 selected as system clock + PLL1_P = 0x3, _, }; - /// Power control - pub const PWR = extern struct { - /// power control register - CR: mmio.Mmio(packed struct(u32) { - /// Low-power deepsleep/Sleep/Low-power run - LPSDSR: packed union { - raw: u1, - value: MODE, - }, - /// Power down deepsleep - PDDS: packed union { - raw: u1, - value: PDDS, - }, - /// Clear wakeup flag - CWUF: u1, - /// Clear standby flag - CSBF: u1, - /// Power voltage detector enable - PVDE: u1, - /// PVD level selection - PLS: packed union { - raw: u3, - value: PLS, - }, - /// Disable backup domain write protection - DBP: u1, - /// Ultra-low-power mode - ULP: u1, - /// Fast wakeup - FWU: u1, - /// Voltage scaling range selection - VOS: packed union { - raw: u2, - value: VOS, - }, - /// Deep sleep mode with Flash memory kept off - DS_EE_KOFF: packed union { - raw: u1, - value: DS_EE_KOFF, - }, - /// Low power run mode - LPRUN: packed union { - raw: u1, - value: MODE, - }, - reserved16: u1, - /// Regulator in Low-power deepsleep mode - LPDS: packed union { - raw: u1, - value: MODE, - }, - padding: u15, - }), - /// power control/status register - CSR: mmio.Mmio(packed struct(u32) { - /// Wakeup flag - WUF: u1, - /// Standby flag - SBF: u1, - /// PVD output - PVDO: u1, - /// Internal voltage reference ready flag - VREFINTRDYF: u1, - /// Voltage Scaling select flag - VOSF: u1, - /// Regulator LP flag - REGLPF: u1, - reserved8: u2, - /// Enable WKUP pin 1 - EWUP1: u1, - /// Enable WKUP pin 2 - EWUP2: u1, - /// Enable WKUP pin 3 - EWUP3: u1, - padding: u21, - }), + pub const SYSTICKSEL = enum(u2) { + /// rcc_hclk/8 selected as clock source (default after reset) + HCLK1_DIV_8 = 0x0, + /// lsi_ker_ck[1] selected as clock source + LSI = 0x1, + /// lse_ck[1] selected as clock source + LSE = 0x2, + _, }; - }; - pub const comp_h7_b = struct { - pub const BLANKING = enum(u4) { - NoBlanking = 0x0, - Tim1Oc5 = 0x1, - Tim2Oc3 = 0x2, - Tim3Oc3 = 0x3, - Tim3Oc4 = 0x4, - Tim8Oc5 = 0x5, - Tim15Oc1 = 0x6, - _, + pub const TIMICSEL = enum(u1) { + /// No internal clock available for timers input capture (default after reset) + B_0x0 = 0x0, + /// hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture + B_0x1 = 0x1, }; - pub const HYST = enum(u2) { - None = 0x0, - Low = 0x1, - Medium = 0x2, - High = 0x3, + pub const TIMPRE = enum(u1) { + /// The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset) + DefaultX2 = 0x0, + /// The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2 + DefaultX4 = 0x1, }; - pub const INMSEL = enum(u3) { - VRef_1over4 = 0x0, - VRef_1over2 = 0x1, - VRef_3over4 = 0x2, - VRef = 0x3, - Inm1 = 0x4, - Inm2 = 0x5, - COMPx_Inm1 = 0x6, - COMPx_Inm2 = 0x7, + pub const USART1SEL = enum(u3) { + /// rcc_pclk2 selected as peripheral clock + PCLK2 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, }; - pub const INPSEL = enum(u1) { - INP1 = 0x0, - INP2 = 0x1, + pub const USARTSEL = enum(u3) { + /// rcc_pclk1 selected as peripheral clock + PCLK1 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, }; - pub const PWRMODE = enum(u2) { - /// High speed / full power - High = 0x0, - /// Medium speed / medium power - Medium = 0x1, - /// Medium speed / medium power - MediumEither = 0x2, - /// Ultra low power / ultra-low-power - Low = 0x3, + pub const USBSEL = enum(u2) { + /// Disable the kernel clock + DISABLE = 0x0, + /// pll1_q selected as peripheral clock + PLL1_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// HSI48 selected as peripheral clock + HSI48 = 0x3, }; - /// COMP1. - pub const COMP = extern struct { - /// Comparator status register. - SR: mmio.Mmio(packed struct(u32) { - /// COMP channel 1 output status bit. - CVAL: u1, - reserved16: u15, - /// COMP channel 1 Interrupt Flag. - CIF: u1, - padding: u15, + /// Reset and clock controller + pub const RCC = extern struct { + /// RCC clock control register + CR: mmio.Mmio(packed struct(u32) { + /// HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). + HSION: u1, + /// HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable. + HSIRDY: u1, + /// HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION. + HSIKERON: u1, + /// HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored. + HSIDIV: packed union { + raw: u2, + value: HSIDIV, + }, + /// HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. + HSIDIVF: u1, + reserved8: u2, + /// CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). + CSION: u1, + /// CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request). + CSIRDY: u1, + /// CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION. + CSIKERON: u1, + reserved12: u1, + /// HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode. + HSI48ON: u1, + /// HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable. + HSI48RDY: u1, + reserved16: u2, + /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). + HSEON: u1, + /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. + HSERDY: u1, + /// HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + HSEBYP: u1, + /// HSE clock security system enable Set by software to enable clock security system on HSE. This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected. + HSECSSON: u1, + /// external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled. + HSEEXT: packed union { + raw: u1, + value: HSEEXT, + }, + reserved24: u3, + /// PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock. + PLLON: u1, + /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + PLLRDY: u1, + padding: u6, }), - /// Comparator interrupt clear flag register. - ICFR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Clear COMP channel 1 Interrupt Flag. - CCIF: u1, - padding: u15, + reserved16: [12]u8, + /// RCC HSI calibration register + HSICFGR: mmio.Mmio(packed struct(u32) { + /// HSI clock calibration Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value. + HSICAL: u12, + reserved16: u4, + /// HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_OPT. After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated Note: The reset value of the field is 0x40. + HSITRIM: u7, + padding: u9, }), - /// Comparator option register. - OR: mmio.Mmio(packed struct(u32) { - /// Selection of source for alternate function of output ports. - AFOP: u11, - padding: u21, + /// RCC clock recovery RC register + CRRCR: mmio.Mmio(packed struct(u32) { + /// Internal RC 48 MHz clock calibration Set by hardware by option-byte loading during system reset NRESET. Read-only. + HSI48CAL: u10, + padding: u22, }), - /// Comparator configuration register 1. - CFGR1: mmio.Mmio(packed struct(u32) { - /// COMP channel 1 enable bit. - EN: u1, - /// Scaler bridge enable. - BRGEN: u1, - /// Voltage scaler enable bit. - SCALEN: u1, - /// COMP channel 1 polarity selection bit. - POLARITY: u1, - reserved6: u2, - /// COMP channel 1 interrupt enable. - ITEN: u1, - reserved8: u1, - /// COMP channel 1 hysteresis selection bits. - HYST: packed union { - raw: u2, - value: HYST, - }, - reserved12: u2, - /// Power Mode of the COMP channel 1. - PWRMODE: packed union { - raw: u2, - value: PWRMODE, + /// RCC CSI calibration register + CSICFGR: mmio.Mmio(packed struct(u32) { + /// CSI clock calibration Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value. + CSICAL: u8, + reserved16: u8, + /// CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_OPT. Note: The reset value of the field is 0x20. + CSITRIM: u6, + padding: u10, + }), + /// RCC clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// system clock and trace clock switch Set and reset by software to select system clock and trace clock sources (sys_ck). Set by hardware in order to: - force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode - force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock others: reserved + SW: packed union { + raw: u3, + value: SW, }, - reserved16: u2, - /// COMP channel 1 inverting input selection field. - INMSEL: packed union { + /// system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset). others: reserved + SWS: packed union { raw: u3, - value: INMSEL, + value: SW, }, - reserved20: u1, - /// COMP channel 1 non-inverting input selection bit. - INPSEL: packed union { + /// system clock selection after a wakeup from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset) STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10). + STOPWUCK: packed union { raw: u1, - value: INPSEL, + value: STOPWUCK, }, - reserved24: u3, - /// COMP channel 1 blanking source selection bits. - BLANKING: packed union { + /// kernel clock selection after a wakeup from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. + STOPKERWUCK: packed union { + raw: u1, + value: STOPKERWUCK, + }, + /// HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ... + RTCPRE: u6, + reserved15: u1, + /// timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. + TIMPRE: packed union { + raw: u1, + value: TIMPRE, + }, + reserved18: u2, + /// MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... + MCO1PRE: packed union { raw: u4, - value: BLANKING, + value: MCOPRE, + }, + /// Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved + MCO1SEL: packed union { + raw: u3, + value: MCO1SEL, + }, + /// MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... + MCO2PRE: packed union { + raw: u4, + value: MCOPRE, + }, + /// microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved + MCO2SEL: packed union { + raw: u3, + value: MCO2SEL, }, - reserved31: u3, - /// Lock bit. - LOCK: u1, }), - /// Comparator configuration register 2. + /// RCC CPU domain clock configuration register 2 CFGR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Window comparator mode selection bit. - WINMODE: u1, - padding: u27, - }), - }; - }; - - pub const iwdg_v1 = struct { - pub const KEY = enum(u16) { - /// Enable access to PR, RLR and WINR registers (0x5555) - Enable = 0x5555, - /// Reset the watchdog value (0xAAAA) - Reset = 0xaaaa, - /// Start the watchdog (0xCCCC) - Start = 0xcccc, - _, - }; - - pub const PR = enum(u3) { - /// Divider /4 - DivideBy4 = 0x0, - /// Divider /8 - DivideBy8 = 0x1, - /// Divider /16 - DivideBy16 = 0x2, - /// Divider /32 - DivideBy32 = 0x3, - /// Divider /64 - DivideBy64 = 0x4, - /// Divider /128 - DivideBy128 = 0x5, - /// Divider /256 - DivideBy256 = 0x6, - /// Divider /256 - DivideBy256bis = 0x7, - }; - - /// Independent watchdog - pub const IWDG = extern struct { - /// Key register - KR: mmio.Mmio(packed struct(u32) { - /// Key value (write only, read 0000h) - KEY: packed union { - raw: u16, - value: KEY, + /// AHB prescaler Set and reset by software to control the division factor of rcc_hclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks 0xxx: rcc_hclk = sys_ck (default after reset) + HPRE: packed union { + raw: u4, + value: HPRE, }, - padding: u16, - }), - /// Prescaler register - PR: mmio.Mmio(packed struct(u32) { - /// Prescaler divider - PR: packed union { + /// APB low-speed prescaler (APB1) Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write. 0xx: rcc_pclk1 = rcc_hclk1 (default after reset) + PPRE1: packed union { raw: u3, - value: PR, + value: PPRE, }, - padding: u29, - }), - /// Reload register - RLR: mmio.Mmio(packed struct(u32) { - /// Watchdog counter reload value - RL: u12, - padding: u20, - }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Watchdog prescaler value update - PVU: u1, - /// Watchdog counter reload value update - RVU: u1, - padding: u30, + reserved8: u1, + /// APB high-speed prescaler (APB2) Set and reset by software to control APB high-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write. 0xx: rcc_pclk2 = rcc_hclk1 + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + reserved12: u1, + /// APB low-speed prescaler (APB3) Set and reset by software to control APB low-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write. 0xx: rcc_pclk3 = rcc_hclk1 + PPRE3: packed union { + raw: u3, + value: PPRE, + }, + reserved16: u1, + /// AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals from RCC_AHB1ENR are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from RCC_AHB1ENR are off. enable control bits + AHB1DIS: u1, + /// AHB2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR are used and when their clocks are disabled in RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR are off. enable control bits + AHB2DIS: u1, + reserved19: u1, + /// AHB4 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB4 peripherals from RCC_AHB4ENR are used and when their clocks are disabled in RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from RCC_AHB4ENR are off. enable control bits + AHB4DIS: u1, + /// APB1 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. control bits + APB1DIS: u1, + /// APB2 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off. control bits + APB2DIS: u1, + /// APB3 clock disable value.Set and cleared by software This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. control bits + APB3DIS: u1, + padding: u9, }), - }; - }; - - pub const usb_v4 = struct { - pub const DIR = enum(u1) { - /// data transmitted by the USB peripheral to the host PC - To = 0x0, - /// data received by the USB peripheral from the host PC - From = 0x1, - }; - - pub const EP_TYPE = enum(u2) { - /// Bulk endpoint - Bulk = 0x0, - /// Control endpoint - Control = 0x1, - /// Iso endpoint - Iso = 0x2, - /// Interrupt endpoint - Interrupt = 0x3, - }; - - pub const LPMACK = enum(u1) { - /// The valid LPM Token will be NYET / NYET answer - Nyet = 0x0, - /// The valid LPM Token will be ACK / ACK answer - Ack = 0x1, - }; - - pub const SDET = enum(u1) { - /// CDP detected - CDP = 0x0, - /// DCP detected - DCP = 0x1, - }; - - pub const STAT = enum(u2) { - /// all requests addressed to this endpoint are ignored - Disabled = 0x0, - /// the endpoint is stalled and all requests result in a STALL handshake - Stall = 0x1, - /// the endpoint is naked and all requests result in a NAK handshake - Nak = 0x2, - /// this endpoint is enabled, requests are ACKed - Valid = 0x3, - }; - - /// Universal serial bus full-speed host/device interface - pub const USB = extern struct { - /// endpoint/channel - EPR: [8]mmio.Mmio(packed struct(u32) { - /// endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. - EA: u4, - /// Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be VALID or DISABLED. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to STALL or NAK for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC) - STAT_TX: packed union { + reserved40: [4]u8, + /// RCC PLL clock source selection register + PLLCFGR: [3]mmio.Mmio(packed struct(u32) { + /// DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset). + PLLSRC: packed union { raw: u2, - value: STAT, + value: PLLSRC, }, - /// Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1. - DTOG_TX: u1, - /// Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions. - CTR_TX: u1, - /// endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. - EP_KIND: u1, - /// USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers - EP_TYPE: packed union { + /// PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. + PLLRGE: packed union { raw: u2, - value: EP_TYPE, + value: PLLRGE, }, - /// Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. - SETUP: u1, - /// Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALL or 'NAK for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate. - STAT_RX: packed union { - raw: u2, - value: STAT, + /// PLL1 fractional latch enable Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator. In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator. + PLLFRACEN: u1, + /// PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. + PLLVCOSEL: packed union { + raw: u1, + value: PLLVCOSEL, }, - /// Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. - DTOG_RX: u1, - /// USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect. - CTR_RX: u1, - /// Host mode Device address assigned to the endpoint during the enumeration process. - DEVADDR: u7, - /// Host mode This bit is set by the hardware when a device responds with a NAK. Software can be use this bit to monitoring the number of NAKs received from a device. - NAK: u1, - /// Low speed endpoint Host with HUB only Host mode This bit is set by the software to send an LS transaction to the corresponding endpoint. - LS_EP: u1, - /// Transmit error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - ERR_TX: u1, - /// Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - ERR_RX: u1, - padding: u5, - }), - reserved64: [32]u8, - /// control register - CNTR: mmio.Mmio(packed struct(u32) { - /// Force a reset of the USB peripheral, exactly like a RESET signaling on the USB - FRES: u1, - /// Power down This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used. - PDWN: u1, - /// Suspend state effective This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wakeup logic and single ended receiver is kept alive to detect remote wakeup or resume events. Software must poll this bit to confirm it to be set before any STOP mode entry. This bit is cleared by hardware simultaneously to the WAKEUP flag being set. - LPMODE: u1, - /// Suspend state enable Device mode Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3 ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to purse more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY=1 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Host mode Software can set this bit when Host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to purse more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. - FSUSP: u1, - /// L2 Remote Wakeup / Resume driver Device mode The microcontroller can set this bit to send remote wake-up signaling to the Host. It must be activated, according to USB specifications, for no less than 1ms and no more than 15ms after which the Host PC is ready to drive the resume sequence up to its end. Host mode Software sets this bit to send resume signaling to the device. Software clears this bit to send end of resume to device and restart SOF generation. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. - RESUME: u1, - /// L1 Remote Wakeup / Resume driver Device mode Software sets this bit to send a LPM L1 50us remote wakeup signaling to the host. After the signaling ends, this bit is cleared by hardware. Host mode Software sets this bit to send L1 resume signaling to device. Resume duration and next SOF generation is automatically driven to set the restart of USB activity timely aligned with the programmed BESL value. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. This bit is cleared by hardware at the end of resume. - L1RESUME: u1, - reserved7: u1, - /// LPM L1 state request interrupt mask - L1REQM: u1, - /// Expected start of frame interrupt mask - ESOFM: u1, - /// Start of frame interrupt mask - SOFM: u1, - /// reset interrupt mask - RESETM: u1, - /// Suspend mode interrupt mask - SUSPM: u1, - /// Wakeup interrupt mask - WKUPM: u1, - /// Error interrupt mask - ERRM: u1, - /// Packet memory area over / underrun interrupt mask - PMAOVRM: u1, - /// CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - CTRM: u1, - /// 512 byte threshold interrupt mask - THR512M: u1, - reserved31: u14, - /// HOST mode HOST bit selects betweens Host or Device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit. - HOST: u1, + reserved8: u2, + /// prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... + DIVM: packed union { + raw: u6, + value: PLLM, + }, + reserved16: u2, + /// PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. + PLLPEN: u1, + /// PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). + PLLQEN: u1, + /// PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). + PLLREN: u1, + padding: u13, }), - /// interrupt status register - ISTR: mmio.Mmio(packed struct(u32) { - /// Device Endpoint / Host channel identification number These bits are written by the hardware according to the host channel or device endpoint number, which generated the interrupt request. If several endpoint/channel transactions are pending, the hardware writes the identification number related to the endpoint/channel having the highest priority defined in the following way: Two levels are defined, in order of priority: Isochronous and double-buffered bulk channels/endpoints are considered first and then the others are examined. If more than one endpoint/channel from the same set is requesting an interrupt, the IDN bits in USB_ISTR register are assigned according to the lowest requesting register, CHEP0R having the highest priority followed by CHEP1R and so on. The application software can assign a register to each endpoint/channel according to this priority scheme, so as to order the concurring endpoint/channel requests in a suitable way. These bits are read only. - EP_ID: u4, - /// Direction of transaction This bit is written by the hardware according to the direction of the successful transaction, which generated the interrupt request. If DIR bit=0, VTTX bit is set in the USB_EPnR register related to the interrupting endpoint. The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host PC). If DIR bit=1, VTRX bit or both VTTX/VTRX are set in the USB_EPnR register related to the interrupting endpoint. The interrupting transaction is of OUT type (data received by the USB peripheral from the host PC) or two pending transactions are waiting to be processed. This information can be used by the application software to access the USB_EPnR bits related to the triggering transaction since it represents the direction having the interrupt pending. This bit is read-only. - DIR: packed union { - raw: u1, - value: DIR, + /// RCC PLL1 dividers register + PLLDIVR: mmio.Mmio(packed struct(u32) { + /// Multiplication factor for PLL1VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved + PLLN: packed union { + raw: u9, + value: PLLN, + }, + /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... + PLLP: packed union { + raw: u7, + value: PLLDIV, + }, + /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLQ: packed union { + raw: u7, + value: PLLDIV, + }, + reserved24: u1, + /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLR: packed union { + raw: u7, + value: PLLDIV, }, - reserved7: u2, - /// LPM L1 state request This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. This bit is read/write but only '0 can be written and writing '1 has no effect. - L1REQ: u1, - /// Expected start of frame This bit is set by the hardware when an SOF packet is expected but not received. The host sends an SOF packet each 1 ms, but if the device does not receive it properly, the Suspend Timer issues this interrupt. If three consecutive ESOF interrupts are generated (i.e. three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the missing SOF packets occur while the Suspend Timer is not yet locked. This bit is read/write but only '0 can be written and writing '1 has no effect. - ESOF: u1, - /// Start of frame This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 1 ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this could be useful for isochronous applications). This bit is read/write but only '0 can be written and writing '1 has no effect. - SOF: u1, - /// reset request Device mode This bit is set by hardware when an USB reset is released by the host and the bus returns to idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles. Host mode This bit is set by hardware when device connection or device disconnection is detected. Device connection is signaled after J state is sampled for 22cycles consecutively from unconnected state. Device disconnection is signaled after SE0 state is sampled for 22cycles consecutively from connected state. - RESET: u1, - /// Suspend mode request This bit is set by the hardware when no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only '0 can be written and writing '1 has no effect. - SUSP: u1, - /// Wakeup This bit is set to 1 by the hardware when, during suspend mode, activity is detected that wakes up the USB peripheral. This event asynchronously clears the LP_MODE bit in the CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of the device (e.g. wakeup unit) about the start of the resume process. This bit is read/write but only '0 can be written and writing '1 has no effect. - WKUP: u1, - /// Error This flag is set whenever one of the errors listed below has occurred: NANS: No ANSwer. The timeout for a host response has expired. CRC: Cyclic Redundancy Check error. One of the received CRCs, either in the token or in the data, was wrong. BST: Bit Stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or CRC. FVIO: Framing format Violation. A non-standard frame was received (EOP not in the right place, wrong token sequence, etc.). The USB software can usually ignore errors, since the USB peripheral and the PC host manage retransmission in case of errors in a fully transparent way. This interrupt can be useful during the software development phase, or to monitor the quality of transmission over the USB bus, to flag possible problems to the user (e.g. loose connector, too noisy environment, broken conductor in the USB cable and so on). This bit is read/write but only '0 can be written and writing '1 has no effect. - ERR: u1, - /// Packet memory area over / underrun This bit is set if the microcontroller has not been able to respond in time to an USB memory request. The USB peripheral handles this event in the following way: During reception an ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the transmitted stream; in both cases the host will retry the transaction. The PMAOVR interrupt should never occur during normal operations. Since the failed transaction is retried by the host, the application software has the chance to speed-up device operations during this interrupt handling, to be ready for the next transaction retry; however this does not happen during Isochronous transfers (no isochronous transaction is anyway retried) leading to a loss of data in this case. This bit is read/write but only '0 can be written and writing '1 has no effect. - PMAOVR: u1, - /// Correct transfer This bit is set by the hardware to indicate that an endpoint/channel has successfully completed a transaction; using DIR and EP_ID bits software can determine which endpoint/channel requested the interrupt. This bit is read-only. - CTR: u1, - /// 512 byte threshold interrupt This bit is set to 1 by the hardware when 512 bytes have been transmitted or received during isochronous transfers. This bit is read/write but only 0 can be written and writing 1 has no effect. Note that no information is available to indicate the associated channel/endpoint, however in practice only one ISO endpoint/channel with such large packets can be supported, so that channel. - THR512: u1, - reserved29: u12, - /// Device connection status Host mode: This bit contains information about device connection status. It is set by hardware when a LS/FS device is attached to the host while it is reset when the device is disconnected. - DCON_STAT: u1, - /// Low Speed device connected Host mode: This bit is set by hardware when an LS device connection is detected. Device connection is signaled after LS J-state is sampled for 22 consecutive cycles of the USB clock (48 MHz) from the unconnected state. - LS_DCON: u1, padding: u1, }), - /// frame number register - FNR: mmio.Mmio(packed struct(u32) { - /// Frame number This bit field contains the 11-bits frame number contained in the last received SOF packet. The frame number is incremented for every frame sent by the host and it is useful for Isochronous transfers. This bit field is updated on the generation of an SOF interrupt. - FN: u11, - /// Lost SOF Device mode These bits are written by the hardware when an ESOF interrupt is generated, counting the number of consecutive SOF packets lost. At the reception of an SOF packet, these bits are cleared. - LSOF: u2, - /// Locked Device mode This bit is set by the hardware when at least two consecutive SOF packets have been received after the end of an USB reset condition or after the end of an USB resume sequence. Once locked, the frame timer remains in this state until an USB reset or USB suspend event occurs. - LCK: u1, - /// Receive data - line status This bit can be used to observe the status of received data minus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event. - RXDM: u1, - /// Receive data + line status This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event. - RXDP: u1, + /// RCC PLL1 fractional divider register + PLLFRACR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: * 128 to 560 MHz if PLL1VCOSEL = 0 * 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with * PLL1N between 8 and 420 * PLL1FRACN can be between 0 and 213- 1 * The input frequency Fref1_ck must be between 1 and 16 MHz. To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: * Set the bit PLL1FRACEN to 0 * Write the new fractional value into PLL1FRACN * Set the bit PLL1FRACEN to 1 + PLLFRACN: u13, padding: u16, }), - /// device address - DADDR: mmio.Mmio(packed struct(u32) { - /// Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel Address (EA) field in the associated USB_EPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction - ADD: u7, - /// Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD[6:0] bits. If this bit is at '0 no transactions are handled, irrespective of the settings of USB_EPnR registers. - EF: u1, - padding: u24, - }), - reserved84: [4]u8, - /// LPM control and status register - LPMCSR: mmio.Mmio(packed struct(u32) { - /// LPM support enable Device mode This bit is set by the software to enable the LPM support within the USB device. If this bit is at '0 no LPM transactions are handled. Host mode Software sets this bit to transmit an LPM transaction to device. This bit is cleared by hardware, simultaneous with L1REQ flag set, when device answer is received - LPMEN: u1, - /// LPM Token acknowledge enable The NYET/ACK will be returned only on a successful LPM transaction: No errors in both the EXT token and the LPM token (else ERROR) A valid bLinkState = 0001B (L1) is received (else STALL) This bit contains the device answer to the LPM transaction. It mast be evaluated following the L1REQ interrupt. - LPMACK: packed union { - raw: u1, - value: LPMACK, - }, - reserved3: u1, - /// bRemoteWake value Device mode This bit contains the bRemoteWake value received with last ACKed LPM Token Host mode This bit contains the bRemoteWake value transmitted with the LPM transaction - REMWAKE: u1, - /// BESL value Device mode These bits contain the BESL value received with last ACKed LPM Token Host mode These bits contain the BESL value transmitted with the LPM transaction - BESL: u4, - padding: u24, + reserved80: [20]u8, + /// RCC clock source interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization. + LSIRDYIE: u1, + /// LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization. + LSERDYIE: u1, + /// CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization. + CSIRDYIE: u1, + /// HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization. + HSIRDYIE: u1, + /// HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization. + HSERDYIE: u1, + /// HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. + HSI48RDYIE: u1, + /// PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. + PLLRDYIE: u1, + padding: u25, }), - /// Battery charging detector - BCDR: mmio.Mmio(packed struct(u32) { - /// Battery charging detector (BCD) enable Device mode This bit is set by the software to enable the BCD support within the USB device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD should be placed in OFF mode by clearing this bit to '0 in order to allow the normal USB operation. - BCDEN: u1, - /// Data contact detection (DCD) mode enable Device mode This bit is set by the software to put the BCD into DCD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. - DCDEN: u1, - /// Primary detection (PD) mode enable Device mode This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. - PDEN: u1, - /// Secondary detection (SD) mode enable Device mode This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. - SDEN: u1, - /// Data contact detection (DCD) status Device mode This bit gives the result of DCD. - DCDET: u1, - /// Primary detection (PD) status Device mode This bit gives the result of PD. - PDET: u1, - /// Secondary detection (SD) status Device mode This bit gives the result of SD. - SDET: packed union { - raw: u1, - value: SDET, - }, - /// DM pull-up detection status Device mode This bit is active only during PD and gives the result of comparison between DM voltage level and VLGC threshold. In normal situation, the DM level should be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification. - PS2DET: u1, - reserved15: u7, - /// DP pull-up / DPDM pull-down Device mode This bit is set by software to enable the embedded pull-up on DP line. Clearing it to '0 can be used to signal disconnect to the host when needed by the user software. Host mode This bit is set by software to enable the embedded pull-down on DP and DM lines. - DPPU: u1, - padding: u16, + /// RCC clock source interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. + LSIRDYF: u1, + /// LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set. + LSERDYF: u1, + /// CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set. + CSIRDYF: u1, + /// HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set. + HSIRDYF: u1, + /// HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. + HSERDYF: u1, + /// HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. + HSI48RDYF: u1, + /// PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + PLLRDYF: u1, + reserved10: u3, + /// HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. + HSECSSF: u1, + padding: u21, }), - }; - }; - - pub const flash_l0 = struct { - /// Flash - pub const FLASH = extern struct { - /// Access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: u1, - /// Prefetch enable - PRFTEN: u1, - reserved3: u1, - /// Flash mode during Sleep - SLEEP_PD: u1, - /// Flash mode during Run - RUN_PD: u1, - /// Disable Buffer - DISAB_BUF: u1, - /// Pre-read data address - PRE_READ: u1, - padding: u25, + /// RCC clock source interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done. + LSIRDYC: u1, + /// LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done. + LSERDYC: u1, + /// HSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done. + CSIRDYC: u1, + /// HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done. + HSIRDYC: u1, + /// HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done. + HSERDYC: u1, + /// HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. + HSI48RDYC: u1, + /// PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + PLLRDYC: u1, + reserved10: u3, + /// HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done. + HSECSSC: u1, + padding: u21, }), - /// Program/erase control register - PECR: mmio.Mmio(packed struct(u32) { - /// FLASH_PECR and data EEPROM lock - PELOCK: u1, - /// Program memory lock - PRGLOCK: u1, - /// Option bytes block lock - OPTLOCK: u1, - /// Program memory selection - PROG: u1, - /// Data EEPROM selection - DATA: u1, - reserved8: u3, - /// Fixed time data write for Byte, Half Word and Word programming - FIX: u1, - /// Page or Double Word erase mode - ERASE: u1, - /// Half Page/Double Word programming mode - FPRG: u1, - reserved15: u4, - /// Parallel bank mode - PARALLELBANK: u1, - /// End of programming interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// Launch the option byte loading - OBL_LAUNCH: u1, - padding: u13, + reserved96: [4]u8, + /// RCC AHB1 reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 block reset Set and reset by software. + GPDMA1RST: u1, + /// GPDMA2 block reset Set and reset by software. + GPDMA2RST: u1, + reserved12: u10, + /// CRC block reset Set and reset by software. + CRCRST: u1, + reserved14: u1, + /// CORDIC block reset Set and reset by software. + CORDICRST: u1, + /// FMAC block reset Set and reset by software. + FMACRST: u1, + reserved17: u1, + /// RAMCFG block reset Set and reset by software. + RAMCFGRST: u1, + reserved19: u1, + /// ETH1 block reset Set and reset by software + ETHRST: u1, + reserved24: u4, + /// TZSC1 reset Set and reset by software + TZSC1RST: u1, + padding: u7, }), - /// Power down key register - PDKEYR: u32, - /// Program/erase key register - PEKEYR: u32, - /// Program memory key register - PRGKEYR: u32, - /// Option byte key register - OPTKEYR: u32, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Write/erase operations in progress - BSY: u1, - /// End of operation - EOP: u1, - /// End of high voltage - ENDHV: u1, - /// Flash memory module ready after low power mode - READY: u1, - reserved8: u4, - /// Write protected error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Size error - SIZERR: u1, - /// Option validity error - OPTVERR: u1, - reserved14: u2, - /// RDERR - RDERR: u1, - reserved16: u1, - /// NOTZEROERR - NOTZEROERR: u1, - /// FWWERR - FWWERR: u1, - padding: u14, + /// RCC AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// GPIOA block reset Set and reset by software. + GPIOARST: u1, + /// GPIOB block reset Set and reset by software. + GPIOBRST: u1, + /// GPIOC block reset Set and reset by software. + GPIOCRST: u1, + /// GPIOD block reset Set and reset by software. + GPIODRST: u1, + /// GPIOE block reset Set and reset by software. + GPIOERST: u1, + /// GPIOF block reset Set and reset by software. + GPIOFRST: u1, + /// GPIOG block reset Set and reset by software. + GPIOGRST: u1, + /// GPIOH block reset Set and reset by software. + GPIOHRST: u1, + /// GPIOI block reset Set and reset by software. + GPIOIRST: u1, + reserved10: u1, + /// ADC1 and 2 blocks reset Set and reset by software. + ADC12RST: u1, + /// DAC block reset Set and reset by software. + DAC1RST: u1, + /// digital camera interface block reset (DCMI or PSSI depending which interface is active) Set and reset by software. + DCMI_PSSIRST: u1, + reserved16: u3, + /// AES block reset Set and reset by software. + AESRST: u1, + /// HASH block reset Set and reset by software. + HASHRST: u1, + /// RNG block reset Set and reset by software. + RNGRST: u1, + /// PKA block reset Set and reset by software. + PKARST: u1, + /// SAES block reset Set and reset by software. + SAESRST: u1, + padding: u11, }), - /// Option byte register - OPTR: mmio.Mmio(packed struct(u32) { - /// Read protection - RDPROT: u8, - /// Selection of protection mode of WPR bits - WPRMOD: u1, - reserved16: u7, - /// BOR_LEV - BOR_LEV: u4, - padding: u12, + reserved108: [4]u8, + /// RCC AHB4 peripheral reset register + AHB4RSTR: mmio.Mmio(packed struct(u32) { + reserved7: u7, + /// OTFDEC1 block reset Set and reset by software. + OTFDEC1RST: u1, + reserved11: u3, + /// SDMMC1 and SDMMC1 delay blocks reset Set and reset by software. + SDMMC1RST: u1, + /// SDMMC2 and SDMMC2 delay blocks reset Set and reset by software. + SDMMC2RST: u1, + reserved16: u3, + /// FMC block reset Set and reset by software. + FMCRST: u1, + reserved20: u3, + /// OCTOSPI1 block reset Set and reset by software. + OCTOSPI1RST: u1, + padding: u11, }), - /// Write Protection Register 1 - WRPROT: mmio.Mmio(packed struct(u32) { - /// Write Protection - WRPROT: u1, - padding: u31, + reserved116: [4]u8, + /// RCC APB1 peripheral low reset register + APB1LRSTR: mmio.Mmio(packed struct(u32) { + /// TIM2 block reset Set and reset by software. + TIM2RST: u1, + /// TIM3 block reset Set and reset by software. + TIM3RST: u1, + /// TIM4 block reset Set and reset by software. + TIM4RST: u1, + /// TIM5 block reset Set and reset by software. + TIM5RST: u1, + /// TIM6 block reset Set and reset by software. + TIM6RST: u1, + /// TIM7 block reset Set and reset by software. + TIM7RST: u1, + /// TIM12 block reset Set and reset by software. + TIM12RST: u1, + /// TIM13 block reset t Set and reset by software. + TIM13RST: u1, + /// TIM14 block reset Set and reset by software. + TIM14RST: u1, + reserved14: u5, + /// SPI2 block reset Set and reset by software. + SPI2RST: u1, + /// SPI3 block reset Set and reset by software. + SPI3RST: u1, + reserved17: u1, + /// USART2 block reset Set and reset by software. + USART2RST: u1, + /// USART3 block reset Set and reset by software. + USART3RST: u1, + /// UART4 block reset Set and reset by software. + UART4RST: u1, + /// UART5 block reset Set and reset by software. + UART5RST: u1, + /// I2C1 block reset Set and reset by software. + I2C1RST: u1, + /// I2C2 block reset Set and reset by software. + I2C2RST: u1, + /// I3C1 block reset Set and reset by software. + I3C1RST: u1, + /// CRS block reset Set and reset by software. + CRSRST: u1, + /// USART6 block reset Set and reset by software. + USART6RST: u1, + /// USART10 block reset Set and reset by software. + USART10RST: u1, + /// USART11 block reset Set and reset by software. + USART11RST: u1, + /// HDMI-CEC block reset Set and reset by software. + CECRST: u1, + reserved30: u1, + /// UART7 block reset Set and reset by software. + UART7RST: u1, + /// UART8 block reset Set and reset by software. + UART8RST: u1, }), - reserved128: [92]u8, - /// Write Protection Register 2 - WRPROT2: mmio.Mmio(packed struct(u32) { - /// Write Protection - WRPROT: u1, - padding: u31, + /// RCC APB1 peripheral high reset register + APB1HRSTR: mmio.Mmio(packed struct(u32) { + /// UART9 block reset Set and reset by software. + UART9RST: u1, + /// UART12 block reset Set and reset by software. + UART12RST: u1, + reserved3: u1, + /// DTS block reset Set and reset by software. + DTSRST: u1, + reserved5: u1, + /// LPTIM2 block reset Set and reset by software. + LPTIM2RST: u1, + reserved9: u3, + /// FDCAN1 and FDCAN2 blocks reset Set and reset by software. + FDCAN12RST: u1, + reserved23: u13, + /// UCPD block reset Set and reset by software. + UCPDRST: u1, + padding: u8, }), - }; - }; - - pub const wwdg_v1 = struct { - pub const WDGTB = enum(u2) { - /// Counter clock (PCLK1 div 4096) div 1 - Div1 = 0x0, - /// Counter clock (PCLK1 div 4096) div 2 - Div2 = 0x1, - /// Counter clock (PCLK1 div 4096) div 4 - Div4 = 0x2, - /// Counter clock (PCLK1 div 4096) div 8 - Div8 = 0x3, - }; - - /// Window watchdog - pub const WWDG = extern struct { - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// 7-bit counter (MSB to LSB) - T: u7, - /// Watchdog activated - WDGA: u1, - padding: u24, + /// RCC APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 block reset Set and reset by software. + TIM1RST: u1, + /// SPI1 block reset Set and reset by software. + SPI1RST: u1, + /// TIM8 block reset Set and reset by software. + TIM8RST: u1, + /// USART1 block reset Set and reset by software. + USART1RST: u1, + reserved16: u1, + /// TIM15 block reset Set and reset by software. + TIM15RST: u1, + /// TIM16 block reset Set and reset by software. + TIM16RST: u1, + /// TIM17 block reset Set and reset by software. + TIM17RST: u1, + /// SPI4 block reset Set and reset by software. + SPI4RST: u1, + /// SPI6 block reset Set and reset by software. + SPI6RST: u1, + /// SAI1 block reset Set and reset by software. + SAI1RST: u1, + /// SAI2 block reset Set and reset by software. + SAI2RST: u1, + reserved24: u1, + /// USB block reset Set and reset by software. + USBRST: u1, + padding: u7, }), - /// Configuration register - CFR: mmio.Mmio(packed struct(u32) { - /// 7-bit window value - W: u7, - /// Timer base - WDGTB: packed union { - raw: u2, - value: WDGTB, - }, - /// Early wakeup interrupt - EWI: u1, - padding: u22, + /// RCC APB3 peripheral reset register + APB3RSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SBS block reset Set and reset by software. + SYSCFGRST: u1, + reserved5: u3, + /// SPI5 block reset Set and reset by software. + SPI5RST: u1, + /// LPUART1 block reset Set and reset by software. + LPUART1RST: u1, + /// I2C3 block reset Set and reset by software. + I2C3RST: u1, + /// I2C4 block reset Set and reset by software. + I2C4RST: u1, + reserved11: u2, + /// LPTIM1 block reset Set and reset by software. + LPTIM1RST: u1, + /// LPTIM3 block reset Set and reset by software. + LPTIM3RST: u1, + /// LPTIM4 block reset Set and reset by software. + LPTIM4RST: u1, + /// LPTIM5 block reset Set and reset by software. + LPTIM5RST: u1, + /// LPTIM6 block reset Set and reset by software. + LPTIM6RST: u1, + reserved20: u4, + /// VREF block reset Set and reset by software. + VREFRST: u1, + padding: u11, }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Early wakeup interrupt flag - EWIF: u1, - padding: u31, + reserved136: [4]u8, + /// RCC AHB1 peripherals clock register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 clock enable Set and reset by software. + GPDMA1EN: u1, + /// GPDMA2 clock enable Set and reset by software. + GPDMA2EN: u1, + reserved8: u6, + /// Flash interface clock enable Set and reset by software. + FLITFEN: u1, + reserved12: u3, + /// CRC clock enable Set and reset by software. + CRCEN: u1, + reserved14: u1, + /// CORDIC clock enable Set and reset by software. + CORDICEN: u1, + /// FMAC clock enable Set and reset by software. + FMACEN: u1, + reserved17: u1, + /// RAMCFG clock enable Set and reset by software. + RAMCFGEN: u1, + reserved19: u1, + /// ETH clock enable Set and reset by software + ETHEN: u1, + /// ETHTX clock enable Set and reset by software + ETHTXEN: u1, + /// ETHRX clock enable Set and reset by software + ETHRXEN: u1, + reserved24: u2, + /// TZSC1 clock enable Set and reset by software + TZSC1EN: u1, + reserved28: u3, + /// BKPRAM clock enable Set and reset by software + BKPRAMEN: u1, + reserved30: u1, + /// DCACHE clock enable Set and reset by software + DCACHEEN: u1, + /// SRAM1 clock enable Set and reset by software. + SRAM1EN: u1, }), - }; - }; - - pub const flash_g4c3 = struct { - pub const LATENCY = enum(u4) { - /// Zero wait states - WS0 = 0x0, - /// One wait state - WS1 = 0x1, - /// Two wait states - WS2 = 0x2, - /// Three wait states - WS3 = 0x3, - /// Four wait states - WS4 = 0x4, - _, - }; - - pub const NRST_MODE = enum(u2) { - /// Reset pin is in reset input mode only - INPUT_ONLY = 0x1, - /// Reset pin is in GPIO mode only - GPIO = 0x2, - /// Reset pin is in reset input and output mode - INPUT_OUTPUT = 0x3, - _, - }; - - pub const RDP = enum(u8) { - /// Read protection not active - LEVEL_0 = 0xaa, - /// Memories read protection active - LEVEL_1 = 0xbb, - /// Chip read protection active - LEVEL_2 = 0xcc, - _, - }; - - /// Flash - pub const FLASH = extern struct { - /// Access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: packed union { - raw: u4, - value: LATENCY, - }, - reserved8: u4, - /// Prefetch enable - PRFTEN: u1, - /// Instruction cache enable - ICEN: u1, - /// Data cache enable - DCEN: u1, - /// Instruction cache reset - ICRST: u1, - /// Data cache reset - DCRST: u1, - /// Flash Power-down mode during Low-power run mode - RUN_PD: u1, - /// Flash Power-down mode during Low-power sleep mode - SLEEP_PD: u1, - reserved18: u3, - /// Debug software enable - DBG_SWEN: u1, - padding: u13, + /// RCC AHB2 peripheral clock register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// GPIOA clock enable Set and reset by software. + GPIOAEN: u1, + /// GPIOB clock enable Set and reset by software. + GPIOBEN: u1, + /// GPIOC clock enable Set and reset by software. + GPIOCEN: u1, + /// GPIOD clock enable Set and reset by software. + GPIODEN: u1, + /// GPIOE clock enable Set and reset by software. + GPIOEEN: u1, + /// GPIOF clock enable Set and reset by software. + GPIOFEN: u1, + /// GPIOG clock enable Set and reset by software. + GPIOGEN: u1, + /// GPIOH clock enable Set and reset by software. + GPIOHEN: u1, + /// GPIOI clock enable Set and reset by software. + GPIOIEN: u1, + reserved10: u1, + /// ADC1 and 2 peripherals clock enabled Set and reset by software. + ADC12EN: u1, + /// DAC clock enable Set and reset by software. + DAC1EN: u1, + /// digital camera interface clock enable (DCMI or PSSI depending which interface is active) Set and reset by software. + DCMI_PSSIEN: u1, + reserved16: u3, + /// AES clock enable Set and reset by software. + AESEN: u1, + /// HASH clock enable Set and reset by software. + HASHEN: u1, + /// RNG clock enable Set and reset by software. + RNGEN: u1, + /// PKA clock enable Set and reset by software. + PKAEN: u1, + /// SAES clock enable Set and reset by software. + SAESEN: u1, + reserved30: u9, + /// SRAM3 clock enable Set and reset by software. + SRAM3EN: u1, + /// SRAM2 clock enable Set and reset by software. + SRAM2EN: u1, }), - /// Power down key register - PDKEYR: u32, - /// Flash key register - KEYR: u32, - /// Option byte key register - OPTKEYR: u32, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved3: u1, - /// Programming error - PROGERR: u1, - /// Write protected error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Size error - SIZERR: u1, - /// Programming sequence error - PGSERR: u1, - /// Fast programming data miss error - MISERR: u1, - /// Fast programming error - FASTERR: u1, - reserved14: u4, - /// PCROP read error - RDERR: u1, - /// Option validity error - OPTVERR: u1, - /// Busy - BSY: u1, - padding: u15, + reserved148: [4]u8, + /// RCC AHB4 peripheral clock register + AHB4ENR: mmio.Mmio(packed struct(u32) { + reserved7: u7, + /// OTFDEC1 clock enable Set and reset by software. + OTFDEC1EN: u1, + reserved11: u3, + /// SDMMC1 and SDMMC1 delay peripheral clock enable reset + SDMMC1EN: u1, + /// SDMMC2 and SDMMC2 delay peripheral clock enabled Set and reset by software. + SDMMC2EN: u1, + reserved16: u3, + /// FMC clock enable Set and reset by software. + FMCEN: u1, + reserved20: u3, + /// OCTOSPI1 clock enable Set and reset by software. + OCTOSPI1EN: u1, + padding: u11, }), - /// Flash control register - CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Page erase - PER: u1, - /// Bank 1 Mass erase - MER1: u1, - /// Page number - PNB: u7, - reserved15: u5, - /// Bank 2 Mass erase - MER2: u1, - /// Start - STRT: u1, - /// Options modification start - OPTSTRT: u1, - /// Fast programming - FSTPG: u1, - reserved24: u5, - /// End of operation interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// PCROP read error interrupt enable - RDERRIE: u1, - /// Force the option byte loading - OBL_LAUNCH: u1, - /// Securable memory area protection enable - SEC_PROT1: u1, + reserved156: [4]u8, + /// RCC APB1 peripheral clock register + APB1LENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable Set and reset by software. + TIM2EN: u1, + /// TIM3 clock enable Set and reset by software. + TIM3EN: u1, + /// TIM4 clock enable Set and reset by software. + TIM4EN: u1, + /// TIM5 clock enable Set and reset by software. + TIM5EN: u1, + /// TIM6 clock enable Set and reset by software. + TIM6EN: u1, + /// TIM7 clock enable Set and reset by software. + TIM7EN: u1, + /// TIM12 clock enable Set and reset by software. + TIM12EN: u1, + /// TIM13 clock enable Set and reset by software. + TIM13EN: u1, + /// TIM14 clock enable Set and reset by software. + TIM14EN: u1, + reserved11: u2, + /// WWDG clock enable Set and reset by software. + WWDGEN: u1, + reserved14: u2, + /// SPI2 clock enable Set and reset by software. + SPI2EN: u1, + /// SPI3 clock enable Set and reset by software. + SPI3EN: u1, + reserved17: u1, + /// USART2 clock enable Set and reset by software. + USART2EN: u1, + /// USART3 clock enable Set and reset by software. + USART3EN: u1, + /// UART4 clock enable Set and reset by software. + UART4EN: u1, + /// UART5 clock enable Set and reset by software. + UART5EN: u1, + /// I2C1 clock enable Set and reset by software. + I2C1EN: u1, + /// I2C2 clock enable Set and reset by software. + I2C2EN: u1, + /// I3C1 clock enable Set and reset by software. + I3C1EN: u1, + /// CRS clock enable Set and reset by software. + CRSEN: u1, + /// USART6 clock enable Set and reset by software. + USART6EN: u1, + /// USART10 clock enable Set and reset by software. + USART10EN: u1, + /// USART11 clock enable + USART11EN: u1, + /// HDMI-CEC clock enable Set and reset by software. + CECEN: u1, reserved30: u1, - /// Options Lock - OPTLOCK: u1, - /// FLASH_CR Lock - LOCK: u1, + /// UART7 clock enable Set and reset by software. + UART7EN: u1, + /// UART8 clock enable Set and reset by software. + UART8EN: u1, }), - /// Flash ECC register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC fail address - ADDR_ECC: u19, - reserved21: u2, - /// ECC fail for Corrected ECC Error or Double ECC Error in info block - BK_ECC: u1, - /// ECC fail for Corrected ECC Error or Double ECC Error in info block - SYSF_ECC: u1, - reserved24: u1, - /// ECC correction interrupt enable - ECCIE: u1, - reserved28: u3, - /// ECC correction - ECCC2: u1, - /// ECC2 detection - ECCD2: u1, - /// ECC correction - ECCC: u1, - /// ECC detection - ECCD: u1, + /// RCC APB1 peripheral clock register + APB1HENR: mmio.Mmio(packed struct(u32) { + /// UART9 clock enable Set and reset by software. + UART9EN: u1, + /// UART12 clock enable Set and reset by software. + UART12EN: u1, + reserved3: u1, + /// DTS clock enable Set and reset by software. + DTSEN: u1, + reserved5: u1, + /// LPTIM2 clock enable Set and reset by software. + LPTIM2EN: u1, + reserved9: u3, + /// FDCAN1 and FDCAN2 peripheral clock enable Set and reset by software. + FDCAN12EN: u1, + reserved23: u13, + /// UCPD clock enable Set and reset by software. + UCPDEN: u1, + padding: u8, }), - reserved32: [4]u8, - /// Flash option register - OPTR: mmio.Mmio(packed struct(u32) { - /// Read protection level - RDP: packed union { - raw: u8, - value: RDP, - }, - /// BOR reset Level - BOR_LEV: u3, - reserved12: u1, - /// nRST_STOP - nRST_STOP: u1, - /// nRST_STDBY - nRST_STDBY: u1, - /// nRST_SHDW - nRST_SHDW: u1, + /// RCC APB2 peripheral clock register + APB2ENR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 clock enable Set and reset by software. + TIM1EN: u1, + /// SPI1 clock enable Set and reset by software. + SPI1EN: u1, + /// TIM8 clock enable Set and reset by software. + TIM8EN: u1, + /// USART1 clock enable Set and reset by software. + USART1EN: u1, reserved16: u1, - /// Independent watchdog selection - IDWG_SW: u1, - /// Independent watchdog counter freeze in Stop mode - IWDG_STOP: u1, - /// Independent watchdog counter freeze in Standby mode - IWDG_STDBY: u1, - /// Window watchdog selection - WWDG_SW: u1, - /// Dual bank boot - BFB2: u1, - reserved22: u1, - /// Dual bank memory mode - DBANK: u1, - /// Boot configuration - nBOOT1: u1, - /// SRAM2 parity check enable - SRAM2_PE: u1, - /// SRAM2 Erase when system reset - SRAM2_RST: u1, - /// nSWBOOT0 - nSWBOOT0: u1, - /// nBOOT0 option bit - nBOOT0: u1, - /// NRST_MODE - NRST_MODE: packed union { - raw: u2, - value: NRST_MODE, - }, - /// Internal reset holder enable bit - IRHEN: u1, - padding: u1, - }), - /// Flash Bank 1 PCROP Start address register - PCROP1SR: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area start offset - PCROP1_STRT: u15, - padding: u17, + /// TIM15 clock enable Set and reset by software. + TIM15EN: u1, + /// TIM16 clock enable Set and reset by software. + TIM16EN: u1, + /// TIM17 clock enable Set and reset by software. + TIM17EN: u1, + /// SPI4 clock enable Set and reset by software. + SPI4EN: u1, + /// SPI6 clock enable Set and reset by software. + SPI6EN: u1, + /// SAI1 clock enable Set and reset by software. + SAI1EN: u1, + /// SAI2 clock enable Set and cleared by software. + SAI2EN: u1, + reserved24: u1, + /// USB clock enable Set and reset by software. + USBEN: u1, + padding: u7, }), - /// Flash Bank 1 PCROP End address register - PCROP1ER: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area end offset - PCROP1_END: u15, - reserved31: u16, - /// PCROP area preserved when RDP level decreased - PCROP_RDP: u1, + /// RCC APB3 peripheral clock register + APB3ENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SBS clock enable Set and reset by software. + SYSCFGEN: u1, + reserved5: u3, + /// SPI5 clock enable Set and reset by software. + SPI5EN: u1, + /// LPUART1 clock enable Set and reset by software. + LPUART1EN: u1, + /// I2C3 clock enable Set and reset by software. + I2C3EN: u1, + /// I2C4 clock enable Set and reset by software. + I2C4EN: u1, + reserved11: u2, + /// LPTIM1 clock enable Set and reset by software. + LPTIM1EN: u1, + /// LPTIM3 clock enable Set and reset by software. + LPTIM3EN: u1, + /// LPTIM4 clock enable Set and reset by software. + LPTIM4EN: u1, + /// LPTIM5 clock enable Set and reset by software. + LPTIM5EN: u1, + /// LPTIM6 clock enable Set and reset by software. + LPTIM6EN: u1, + reserved20: u4, + /// VREF clock enable Set and reset by software. + VREFEN: u1, + /// RTC APB interface clock enable Set and reset by software. + RTCAPBEN: u1, + padding: u10, }), - /// Flash Bank 1 WRP area A address register - WRP1AR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP first area start offset - WRP1A_STRT: u7, - reserved16: u9, - /// Bank 1 WRP first area A end offset - WRP1A_END: u7, - padding: u9, + reserved176: [4]u8, + /// RCC AHB1 sleep clock register + AHB1LPENR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 clock enable during sleep mode Set and reset by software. + GPDMA1LPEN: u1, + /// GPDMA2 clock enable during sleep mode Set and reset by software. + GPDMA2LPEN: u1, + reserved8: u6, + /// Flash interface (FLITF) clock enable during sleep mode Set and reset by software. + FLITFLPEN: u1, + reserved12: u3, + /// CRC clock enable during sleep mode Set and reset by software. + CRCLPEN: u1, + reserved14: u1, + /// CORDIC clock enable during sleep mode Set and reset by software. + CORDICLPEN: u1, + /// FMAC clock enable during sleep mode Set and reset by software. + FMACLPEN: u1, + reserved17: u1, + /// RAMCFG clock enable during sleep mode Set and reset by software. + RAMCFGLPEN: u1, + reserved19: u1, + /// ETH clock enable during Sleep mode Set and reset by software + ETHLPEN: u1, + /// ETHTX clock enable during sleep mode Set and reset by software + ETHTXLPEN: u1, + /// ETHRX clock enable during sleep mode Set and reset by software + ETHRXLPEN: u1, + reserved24: u2, + /// TZSC1 clock enable during sleep mode Set and reset by software + TZSC1LPEN: u1, + reserved28: u3, + /// BKPRAM clock enable during sleep mode Set and reset by software + BKPRAMLPEN: u1, + /// ICACHE clock enable during sleep mode Set and reset by software + ICACHELPEN: u1, + /// DCACHE clock enable during sleep mode Set and reset by software + DCACHELPEN: u1, + /// SRAM1 clock enable during sleep mode Set and reset by software + SRAM1LPEN: u1, }), - /// Flash Bank 1 WRP area B address register - WRP1BR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP second area B end offset - WRP1B_STRT: u7, - reserved16: u9, - /// Bank 1 WRP second area B start offset - WRP1B_END: u7, - padding: u9, + /// RCC AHB2 sleep clock register + AHB2LPENR: mmio.Mmio(packed struct(u32) { + /// GPIOA clock enable during sleep mode Set and reset by software. + GPIOALPEN: u1, + /// GPIOB clock enable during sleep mode Set and reset by software. + GPIOBLPEN: u1, + /// GPIOC clock enable during sleep mode Set and reset by software. + GPIOCLPEN: u1, + /// GPIOD clock enable during sleep mode Set and reset by software. + GPIODLPEN: u1, + /// GPIOE clock enable during sleep mode Set and reset by software. + GPIOELPEN: u1, + /// GPIOF clock enable during sleep mode Set and reset by software. + GPIOFLPEN: u1, + /// GPIOG clock enable during sleep mode Set and reset by software. + GPIOGLPEN: u1, + /// GPIOH clock enable during sleep mode Set and reset by software. + GPIOHLPEN: u1, + /// GPIOI clock enable during sleep mode Set and reset by software. + GPIOILPEN: u1, + reserved10: u1, + /// ADC1 and 2 peripherals clock enable during sleep mode Set and reset by software. + ADC12LPEN: u1, + /// DAC clock enable during sleep mode Set and reset by software. + DAC1LPEN: u1, + /// digital camera interface clock enable during sleep mode (DCMI or PSSI depending which interface is active) Set and reset by software. + DCMI_PSSILPEN: u1, + reserved16: u3, + /// AES clock enable during sleep mode Set and reset by software. + AESLPEN: u1, + /// HASH clock enable during sleep mode Set and reset by software. + HASHLPEN: u1, + /// RNG clock enable during sleep mode Set and reset by software. + RNGLPEN: u1, + /// PKA clock enable during sleep mode Set and reset by software. + PKALPEN: u1, + /// SAES clock enable during sleep mode Set and reset by software. + SAESLPEN: u1, + reserved30: u9, + /// SRAM2 clock enable during sleep mode Set and reset by software. + SRAM2LPEN: u1, + /// SRAM3 clock enable during sleep mode Set and reset by software. + SRAM3LPEN: u1, }), - reserved112: [60]u8, - /// securable area bank1 register - SEC1R: mmio.Mmio(packed struct(u32) { - /// SEC_SIZE1 - SEC_SIZE1: u8, - reserved16: u8, - /// used to force boot from user area - BOOT_LOCK: u1, - padding: u15, + reserved188: [4]u8, + /// RCC AHB4 sleep clock register + AHB4LPENR: mmio.Mmio(packed struct(u32) { + reserved7: u7, + /// OTFDEC1 clock enable during sleep mode Set and reset by software. + OTFDEC1LPEN: u1, + reserved11: u3, + /// SDMMC1 and SDMMC1 delay peripheral clock enable during sleep mode Set and reset by software + SDMMC1LPEN: u1, + /// SDMMC2 and SDMMC2 delay peripheral clock enable during sleep mode Set and reset by software. + SDMMC2LPEN: u1, + reserved16: u3, + /// FMC clock enable during sleep mode Set and reset by software. + FMCLPEN: u1, + reserved20: u3, + /// OCTOSPI1 clock enable during sleep mode Set and reset by software. + OCTOSPI1LPEN: u1, + padding: u11, }), - }; - }; - - pub const i2c_v1 = struct { - pub const ADDMODE = enum(u1) { - /// 7-bit addressing mode - Bit7 = 0x0, - /// 10-bit addressing mode - Bit10 = 0x1, - }; - - pub const DNF = enum(u4) { - /// Digital filter disabled - NoFilter = 0x0, - /// Digital filter enabled and filtering capability up to 1 tI2CCLK - Filter1 = 0x1, - /// Digital filter enabled and filtering capability up to 2 tI2CCLK - Filter2 = 0x2, - /// Digital filter enabled and filtering capability up to 3 tI2CCLK - Filter3 = 0x3, - /// Digital filter enabled and filtering capability up to 4 tI2CCLK - Filter4 = 0x4, - /// Digital filter enabled and filtering capability up to 5 tI2CCLK - Filter5 = 0x5, - /// Digital filter enabled and filtering capability up to 6 tI2CCLK - Filter6 = 0x6, - /// Digital filter enabled and filtering capability up to 7 tI2CCLK - Filter7 = 0x7, - /// Digital filter enabled and filtering capability up to 8 tI2CCLK - Filter8 = 0x8, - /// Digital filter enabled and filtering capability up to 9 tI2CCLK - Filter9 = 0x9, - /// Digital filter enabled and filtering capability up to 10 tI2CCLK - Filter10 = 0xa, - /// Digital filter enabled and filtering capability up to 11 tI2CCLK - Filter11 = 0xb, - /// Digital filter enabled and filtering capability up to 12 tI2CCLK - Filter12 = 0xc, - /// Digital filter enabled and filtering capability up to 13 tI2CCLK - Filter13 = 0xd, - /// Digital filter enabled and filtering capability up to 14 tI2CCLK - Filter14 = 0xe, - /// Digital filter enabled and filtering capability up to 15 tI2CCLK - Filter15 = 0xf, - }; - - pub const DUTY = enum(u1) { - /// Duty cycle t_low/t_high = 2/1 - Duty2_1 = 0x0, - /// Duty cycle t_low/t_high = 16/9 - Duty16_9 = 0x1, - }; - - pub const ENDUAL = enum(u1) { - /// Single addressing mode - Single = 0x0, - /// Dual addressing mode - Dual = 0x1, - }; - - pub const F_S = enum(u1) { - /// Standard mode I2C - Standard = 0x0, - /// Fast mode I2C - Fast = 0x1, - }; - - pub const POS = enum(u1) { - /// ACK bit controls the (N)ACK of the current byte being received - Current = 0x0, - /// ACK bit controls the (N)ACK of the next byte to be received - Next = 0x1, - }; - - pub const SMBTYPE = enum(u1) { - /// SMBus Device - Device = 0x0, - /// SMBus Host - Host = 0x1, - }; - - pub const SMBUS = enum(u1) { - /// I2C Mode - I2C = 0x0, - /// SMBus - SMBus = 0x1, - }; - - /// Inter-integrated circuit - pub const I2C = extern struct { - /// Control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Peripheral enable - PE: u1, - /// SMBus mode - SMBUS: packed union { - raw: u1, - value: SMBUS, - }, + reserved196: [4]u8, + /// RCC APB1 sleep clock register + APB1LLPENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable during sleep mode Set and reset by software. + TIM2LPEN: u1, + /// TIM3 clock enable during sleep mode Set and reset by software. + TIM3LPEN: u1, + /// TIM4 clock enable during sleep mode Set and reset by software. + TIM4LPEN: u1, + /// TIM5 clock enable during sleep mode Set and reset by software. + TIM5LPEN: u1, + /// TIM6 clock enable during sleep mode Set and reset by software. + TIM6LPEN: u1, + /// TIM7 clock enable during sleep mode Set and reset by software. + TIM7LPEN: u1, + /// TIM12 clock enable during sleep mode Set and reset by software. + TIM12LPEN: u1, + /// TIM13 clock enable during sleep mode Set and reset by software. + TIM13LPEN: u1, + /// TIM14 clock enable during sleep mode Set and reset by software. + TIM14LPEN: u1, + reserved11: u2, + /// WWDG clock enable during sleep mode Set and reset by software. + WWDGLPEN: u1, + reserved14: u2, + /// SPI2 clock enable during sleep mode Set and reset by software. + SPI2LPEN: u1, + /// SPI3 clock enable during sleep mode Set and reset by software. + SPI3LPEN: u1, + reserved17: u1, + /// USART2 clock enable during sleep mode Set and reset by software. + USART2LPEN: u1, + /// USART3 clock enable during sleep mode Set and reset by software. + USART3LPEN: u1, + /// UART4 clock enable during sleep mode Set and reset by software. + UART4LPEN: u1, + /// UART5 clock enable during sleep mode Set and reset by software. + UART5LPEN: u1, + /// I2C1 clock enable during sleep mode Set and reset by software. + I2C1LPEN: u1, + /// I2C2 clock enable during sleep mode Set and reset by software. + I2C2LPEN: u1, + /// I3C1 clock enable during sleep mode Set and reset by software. + I3C1LPEN: u1, + /// CRS clock enable during sleep mode Set and reset by software. + CRSLPEN: u1, + /// USART6 clock enable during sleep mode Set and reset by software. + USART6LPEN: u1, + /// USART10 clock enable during sleep mode Set and reset by software. + USART10LPEN: u1, + /// USART11 clock enable during sleep mode Set and reset by software. + USART11LPEN: u1, + /// HDMI-CEC clock enable during sleep mode Set and reset by software. + CECLPEN: u1, + reserved30: u1, + /// UART7 clock enable during sleep mode Set and reset by software. + UART7LPEN: u1, + /// UART8 clock enable during sleep mode Set and reset by software. + UART8LPEN: u1, + }), + /// RCC APB1 sleep clock register + APB1HLPENR: mmio.Mmio(packed struct(u32) { + /// UART9 clock enable during sleep mode Set and reset by software. + UART9LPEN: u1, + /// UART12 clock enable during sleep mode Set and reset by software. + UART12LPEN: u1, reserved3: u1, - /// SMBus type - SMBTYPE: packed union { - raw: u1, - value: SMBTYPE, + /// DTS clock enable during sleep mode Set and reset by software. + DTSLPEN: u1, + reserved5: u1, + /// LPTIM2 clock enable during sleep mode Set and reset by software. + LPTIM2LPEN: u1, + reserved9: u3, + /// FDCAN1 and FDCAN2 peripheral clock enable during sleep mode Set and reset by software. + FDCAN12LPEN: u1, + reserved23: u13, + /// UCPD clock enable during sleep mode Set and reset by software. + UCPDLPEN: u1, + padding: u8, + }), + /// RCC APB2 sleep clock register + APB2LPENR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 clock enable during sleep mode Set and reset by software. + TIM1LPEN: u1, + /// SPI1 clock enable during sleep mode Set and reset by software. + SPI1LPEN: u1, + /// TIM8 clock enable during sleep mode Set and reset by software. + TIM8LPEN: u1, + /// USART1 clock enable during sleep mode Set and reset by software. + USART1LPEN: u1, + reserved16: u1, + /// TIM15 clock enable during sleep mode Set and reset by software. + TIM15LPEN: u1, + /// TIM16 clock enable during sleep mode Set and reset by software. + TIM16LPEN: u1, + /// TIM17 clock enable during sleep mode Set and reset by software. + TIM17LPEN: u1, + /// SPI4 clock enable during sleep mode Set and reset by software. + SPI4LPEN: u1, + /// SPI6 clock enable during sleep mode Set and reset by software. + SPI6LPEN: u1, + /// SAI1 clock enable during sleep mode Set and reset by software. + SAI1LPEN: u1, + /// SAI2 clock enable during sleep mode Set and reset by software. + SAI2LPEN: u1, + reserved24: u1, + /// USB clock enable during sleep mode Set and reset by software. + USBLPEN: u1, + padding: u7, + }), + /// RCC APB3 sleep clock register + APB3LPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SBS clock enable during sleep mode Set and reset by software. + SYSCFGLPEN: u1, + reserved5: u3, + /// SPI5 clock enable during Slsleepeep mode Set and reset by software. + SPI5LPEN: u1, + /// LPUART1 clock enable during sleep mode Set and reset by software. + LPUART1LPEN: u1, + /// I2C3 clock enable during sleep mode Set and reset by software. + I2C3LPEN: u1, + /// I2C4 clock enable during sleep mode Set and reset by software. + I2C4LPEN: u1, + reserved11: u2, + /// LPTIM1 clock enable during sleep mode Set and reset by software. + LPTIM1LPEN: u1, + /// LPTIM3 clock enable during sleep mode Set and reset by software. + LPTIM3LPEN: u1, + /// LPTIM4 clock enable during sleep mode Set and reset by software. + LPTIM4LPEN: u1, + /// LPTIM5 clock enable during sleep mode Set and reset by software. + LPTIM5LPEN: u1, + /// LPTIM6 clock enable during sleep mode Set and reset by software. + LPTIM6LPEN: u1, + reserved20: u4, + /// VREF clock enable during sleep mode Set and reset by software. + VREFLPEN: u1, + /// RTC APB interface clock enable during sleep mode Set and reset by software. + RTCAPBLPEN: u1, + padding: u10, + }), + reserved216: [4]u8, + /// RCC kernel clock configuration register + CCIPR1: mmio.Mmio(packed struct(u32) { + /// USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + USART1SEL: packed union { + raw: u3, + value: USART1SEL, }, - /// ARP enable - ENARP: u1, - /// PEC enable - ENPEC: u1, - /// General call enable - ENGC: u1, - /// Clock stretching disable (Slave mode) - NOSTRETCH: u1, - /// Start generation - START: u1, - /// Stop generation - STOP: u1, - /// Acknowledge enable - ACK: u1, - /// Acknowledge/PEC Position (for data reception) - POS: packed union { + /// USART2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + USART2SEL: packed union { + raw: u3, + value: USARTSEL, + }, + /// USART3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + USART3SEL: packed union { + raw: u3, + value: USARTSEL, + }, + /// UART4 kernel clock source selection others: reserved, the kernel clock is disabled + UART4SEL: packed union { + raw: u3, + value: USARTSEL, + }, + /// UART5 kernel clock source selection others: reserved, the kernel clock is disabled + UART5SEL: packed union { + raw: u3, + value: USARTSEL, + }, + /// USART6 kernel clock source selection others: reserved, the kernel clock is disabled + USART6SEL: packed union { + raw: u3, + value: USARTSEL, + }, + /// UART7 kernel clock source selection others: reserved, the kernel clock is disabled + UART7SEL: packed union { + raw: u3, + value: USARTSEL, + }, + /// UART8 kernel clock source selection others: reserved, the kernel clock is disabled + UART8SEL: packed union { + raw: u3, + value: USARTSEL, + }, + /// UART9 kernel clock source selection others: reserved, the kernel clock is disabled + UART9SEL: packed union { + raw: u3, + value: USARTSEL, + }, + /// USART10 kernel clock source selection others: reserved, the kernel clock is disabled + USART10SEL: packed union { + raw: u3, + value: USARTSEL, + }, + reserved31: u1, + /// TIM12, TIM15 and LPTIM2 input capture source selection Set and reset by software. + TIMICSEL: packed union { raw: u1, - value: POS, + value: TIMICSEL, }, - /// Packet error checking - PEC: u1, - /// SMBus alert - ALERT: u1, - reserved15: u1, - /// Software reset - SWRST: u1, - padding: u16, }), - /// Control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Peripheral clock frequency - FREQ: u6, - reserved8: u2, - /// Error interrupt enable - ITERREN: u1, - /// Event interrupt enable - ITEVTEN: u1, - /// Buffer interrupt enable - ITBUFEN: u1, - /// DMA requests enable - DMAEN: u1, - /// DMA last transfer - LAST: u1, - padding: u19, + /// RCC kernel clock configuration register + CCIPR2: mmio.Mmio(packed struct(u32) { + /// USART11 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + USART11SEL: packed union { + raw: u3, + value: USARTSEL, + }, + reserved4: u1, + /// USART12 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + USART12SEL: packed union { + raw: u3, + value: USARTSEL, + }, + reserved8: u1, + /// LPTIM1 kernel clock source selection others: reserved, the kernel clock is disabled + LPTIM1SEL: packed union { + raw: u3, + value: LPTIMSEL, + }, + reserved12: u1, + /// LPTIM2 kernel clock source selection others: reserved, the kernel clock is disabled + LPTIM2SEL: packed union { + raw: u3, + value: LPTIM2SEL, + }, + reserved16: u1, + /// LPTIM3 kernel clock source selection others: reserved, the kernel clock is disabled + LPTIM3SEL: packed union { + raw: u3, + value: LPTIMSEL, + }, + reserved20: u1, + /// LPTIM4 kernel clock source selection others: reserved, the kernel clock is disabled + LPTIM4SEL: packed union { + raw: u3, + value: LPTIMSEL, + }, + reserved24: u1, + /// LPTIM5 kernel clock source selection others: reserved, the kernel clock is disabled + LPTIM5SEL: packed union { + raw: u3, + value: LPTIMSEL, + }, + reserved28: u1, + /// LPTIM6 kernel clock source selection others: reserved, the kernel clock is disabled + LPTIM6SEL: packed union { + raw: u3, + value: LPTIMSEL, + }, + padding: u1, }), - /// Own address register 1 - OAR1: mmio.Mmio(packed struct(u32) { - /// Interface address - ADD: u10, - reserved15: u5, - /// Addressing mode (slave mode) - ADDMODE: packed union { - raw: u1, - value: ADDMODE, + /// RCC kernel clock configuration register + CCIPR3: mmio.Mmio(packed struct(u32) { + /// SPI1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + SPI1SEL: packed union { + raw: u3, + value: SPI1SEL, }, - padding: u16, + /// SPI2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + SPI2SEL: packed union { + raw: u3, + value: SPI2SEL, + }, + /// SPI3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + SPI3SEL: packed union { + raw: u3, + value: SPI3SEL, + }, + /// SPI4 kernel clock source selection others: reserved, the kernel clock is disabled + SPI4SEL: packed union { + raw: u3, + value: SPI4SEL, + }, + /// SPI5 kernel clock source selection others: reserved, the kernel clock is disabled + SPI5SEL: packed union { + raw: u3, + value: SPI5SEL, + }, + /// SPI6 kernel clock source selection others: reserved, the kernel clock is disabled + SPI6SEL: packed union { + raw: u3, + value: SPI6SEL, + }, + reserved24: u6, + /// LPUART1 kernel clock source selection others: reserved, the kernel clock is disabled + LPUART1SEL: packed union { + raw: u3, + value: LPUSARTSEL, + }, + padding: u5, }), - /// Own address register 2 - OAR2: mmio.Mmio(packed struct(u32) { - /// Dual addressing mode enable - ENDUAL: packed union { + /// RCC kernel clock configuration register + CCIPR4: mmio.Mmio(packed struct(u32) { + /// OCTOSPI1 kernel clock source selection Set and reset by software. + OCTOSPI1SEL: packed union { + raw: u2, + value: OCTOSPISEL, + }, + /// SYSTICK clock source selection Note: rcc_hclk frequency must be four times higher than lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK). + SYSTICKSEL: packed union { + raw: u2, + value: SYSTICKSEL, + }, + /// USB kernel clock source selection + USBSEL: packed union { + raw: u2, + value: USBSEL, + }, + /// SDMMC1 kernel clock source selection + SDMMC1SEL: packed union { raw: u1, - value: ENDUAL, + value: SDMMCSEL, }, - /// Interface address - ADD2: u7, - padding: u24, - }), - /// Data register - DR: mmio.Mmio(packed struct(u32) { - /// 8-bit data register - DR: u8, - padding: u24, - }), - /// Status register 1 - SR1: mmio.Mmio(packed struct(u32) { - /// Start bit (Master mode) - START: u1, - /// Address sent (master mode)/matched (slave mode) - ADDR: u1, - /// Byte transfer finished - BTF: u1, - /// 10-bit header sent (Master mode) - ADD10: u1, - /// Stop detection (slave mode) - STOPF: u1, - reserved6: u1, - /// Data register not empty (receivers) - RXNE: u1, - /// Data register empty (transmitters) - TXE: u1, - /// Bus error - BERR: u1, - /// Arbitration lost (master mode) - ARLO: u1, - /// Acknowledge failure - AF: u1, - /// Overrun/Underrun - OVR: u1, - /// PEC Error in reception - PECERR: u1, - reserved14: u1, - /// Timeout or t_low detection flag - TIMEOUT: u1, - /// SMBus alert - ALERT: u1, - padding: u16, + /// SDMMC2 kernel clock source selection + SDMMC2SEL: packed union { + raw: u1, + value: SDMMCSEL, + }, + reserved16: u8, + /// I2C1 kernel clock source selection + I2C1SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// I2C2 kernel clock source selection + I2C2SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// I2C3 kernel clock source selection + I2C3SEL: packed union { + raw: u2, + value: I2C34SEL, + }, + /// I2C4 kernel clock source selection + I2C4SEL: packed union { + raw: u2, + value: I2C34SEL, + }, + /// I3C1 kernel clock source selection + I3C1SEL: packed union { + raw: u2, + value: I2CSEL, + }, + padding: u6, }), - /// Status register 2 - SR2: mmio.Mmio(packed struct(u32) { - /// Master/slave - MSL: u1, - /// Bus busy - BUSY: u1, - /// Transmitter/receiver - TRA: u1, - reserved4: u1, - /// General call address (Slave mode) - GENCALL: u1, - /// SMBus device default address (Slave mode) - SMBDEFAULT: u1, - /// SMBus host header (Slave mode) - SMBHOST: u1, - /// Dual flag (Slave mode) - DUALF: u1, - /// Packet error checking register - PEC: u8, - padding: u16, + /// RCC kernel clock configuration register + CCIPR5: mmio.Mmio(packed struct(u32) { + /// ADC and DAC kernel clock source selection others: reserved, the kernel clock is disabled + ADCDACSEL: packed union { + raw: u3, + value: ADCDACSEL, + }, + /// DAC hold clock + DACHOLDSEL: packed union { + raw: u1, + value: DACHOLDSEL, + }, + /// RNG kernel clock source selection + RNGSEL: packed union { + raw: u2, + value: RNGSEL, + }, + /// HSMI-CEC kernel clock source selection + CECSEL: packed union { + raw: u2, + value: CECSEL, + }, + /// FDCAN1 and FDCAN2 kernel clock source selection + FDCAN12SEL: packed union { + raw: u2, + value: FDCANSEL, + }, + reserved16: u6, + /// SAI1 kernel clock source selection others: reserved, the kernel clock is disabled + SAI1SEL: packed union { + raw: u3, + value: SAISEL, + }, + /// SAI2 kernel clock source selection others: reserved, the kernel clock is disabled + SAI2SEL: packed union { + raw: u3, + value: SAISEL, + }, + reserved30: u8, + /// per_ck clock source selection + PERSEL: packed union { + raw: u2, + value: PERSEL, + }, }), - /// Clock control register - CCR: mmio.Mmio(packed struct(u32) { - /// Clock control register in Fast/Standard mode (Master mode) - CCR: u12, - reserved14: u2, - /// Fast mode duty cycle - DUTY: packed union { + reserved240: [4]u8, + /// RCC Backup domain control register + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enabled Set and reset by software. + LSEON: u1, + /// LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0. + LSERDY: u1, + /// LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1) + LSEBYP: u1, + /// LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0). + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON. + LSECSSON: u1, + /// LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator. + LSECSSD: u1, + /// low-speed external clock type in bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled. + LSEEXT: packed union { raw: u1, - value: DUTY, + value: LSEEXT, }, - /// I2C master mode selection - F_S: packed union { + /// RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST). + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable Set and reset by software. + RTCEN: u1, + /// VSwitch domain software reset Set and reset by software. + VSWRST: u1, + reserved24: u7, + /// Low-speed clock output (LSCO) enable Set and cleared by software. + LSCOEN: u1, + /// Low-speed clock output selection Set and cleared by software. + LSCOSEL: packed union { raw: u1, - value: F_S, + value: LSCOSEL, }, - padding: u16, + /// LSI oscillator enable Set and cleared by software. + LSION: u1, + /// LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0. + LSIRDY: u1, + padding: u4, }), - /// TRISE register - TRISE: mmio.Mmio(packed struct(u32) { - /// Maximum rise time in Fast/Standard mode (Master mode) - TRISE: u6, - padding: u26, + /// RCC reset status register + RSR: mmio.Mmio(packed struct(u32) { + reserved23: u23, + /// remove reset flag Set and reset by software to reset the value of the reset flags. + RMVF: u1, + reserved26: u2, + /// pin reset flag (NRST) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. + PINRSTF: u1, + /// BOR reset flag Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). + BORRSTF: u1, + /// system reset from CPU reset flag Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33. + SFTRSTF: u1, + /// independent watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. + IWDGRSTF: u1, + /// window watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. + WWDGRSTF: u1, + /// Low-power reset flag Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared. Cleared by writing to the RMVF bit. + LPWRRSTF: u1, }), - /// FLTR register - FLTR: mmio.Mmio(packed struct(u32) { - /// Digital noise filter - DNF: packed union { - raw: u4, - value: DNF, + reserved272: [24]u8, + /// RCC secure configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// HSI clock configuration and status bits security Set and reset by software. + HSISEC: u1, + /// HSE clock configuration bits, status bits and HSE_CSS security Set and reset by software. + HSESEC: u1, + /// CSI clock configuration and status bits security Set and reset by software. + CSISEC: u1, + /// LSI clock configuration and status bits security Set and reset by software. + LSISEC: u1, + /// LSE clock configuration and status bits security Set and reset by software. + LSESEC: u1, + /// SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security Set and reset by software. + SYSCLKSEC: u1, + /// AHBx/APBx prescaler configuration bits security Set and reset by software. + PRESCSEC: u1, + /// PLL1 clock configuration and status bits security Set and reset by software. + PLLSEC: u1, + reserved11: u3, + /// HSI48 clock configuration and status bits security Set and reset by software. + HSI48SEC: u1, + /// Remove reset flag security Set and reset by software. + RMVFSEC: u1, + /// per_ck selection security Set and reset by software. + PERSELSEC: u1, + padding: u18, + }), + /// RCC privilege configuration register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access. + SPRIV: packed union { + raw: u1, + value: SPRIV, }, - /// Analog noise filter - ANOFF: u1, - padding: u27, + /// RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure. + NSPRIV: packed union { + raw: u1, + value: NSPRIV, + }, + padding: u30, }), }; }; - pub const i3c_v1 = struct { - pub const ACK = enum(u1) { - Must_NACKed = 0x0, - Must_ACKed = 0x1, + pub const rcc_h50 = struct { + pub const ADCDACSEL = enum(u3) { + /// rcc_hclk selected as kernel clock (default after reset) + HCLK2 = 0x0, + /// sys_ck selected as kernel clock + SYS = 0x1, + /// pll2_r_ck selected as kernel clock + PLL2_R = 0x2, + /// hse_ck selected as kernel clock + HSE = 0x3, + /// hsi_ker_ck selected as kernel clock + HSI = 0x4, + /// csi_ker_ck selected as kernel clock + CSI = 0x5, + _, }; - pub const CODERR = enum(u4) { - /// Transaction after sending CCC. Controller detected an illegally formatted CCC - CE0 = 0x0, - /// Monitoring error. Controller detected that transmitted data on the bus is different from expected - CE1 = 0x1, - /// No response to broadcast address. Controller detected a not acknowledged broadcast address (0b111_1110) - CE2 = 0x2, - /// Failed controller-role hand-off. Controller detected the new controller did not drive bus after controller-role hand-off - CE3 = 0x3, - /// Invalid broadcast address 0b111_1110 + W. Target detected an invalid broadcast address 0b111_1110 + W - TE0 = 0x8, - /// CCC code. Target detected a parity error on a CCC code via a parity check (vs. T bit) - TE1 = 0x9, - /// Write data. Target detected a parity error on a write data via a parity check (vs. T bit) - TE2 = 0xa, - /// Assigned address during dynamic address arbitration. Target detected a parity error on the assigned address during dynamic address arbitration via a parity check (vs. PAR bit) - TE3 = 0xb, - /// 0b111_1110 + R missing after Sr during dynamic address arbitration. Target detected a 0b111_1110 + R missing after Sr during dynamic address arbitration - TE4 = 0xc, - /// Transaction after detecting CCC. Target detected an illegally formatted CCC - TE5 = 0xd, - /// Monitoring error. Target detected that transmitted data on the bus is different from expected - TE6 = 0xe, + pub const DACHOLDSEL = enum(u1) { + /// dac_hold_ck selected as kernel clock (default after reset) + DAC_HOLD = 0x0, + /// dac_hold_ck selected as kernel clock + DAC_HOLD_2 = 0x1, + }; + + pub const FDCANSEL = enum(u2) { + /// hse_ck selected as kernel clock (default after reset) + HSE = 0x0, + /// pll1_q_ck selected as kernel clock + PLL1_Q = 0x1, + /// pll2_q_ck selected as kernel clock + PLL2_Q = 0x2, _, }; - pub const CRINIT = enum(u1) { - /// Once enabled by setting EN = 1, the peripheral initially acts as a target. I3C does not drive SCL line and does not enable SDA pull-up, until it eventually acquires the controller role. - Target = 0x0, - /// Once enabled by setting EN = 1, the peripheral initially acts as a controller. It has the I3C controller role, so drives SCL line and enables SDA pull-up, until it eventually offers the controller role to an I3C secondary controller. - Controller = 0x1, + pub const HPRE = enum(u4) { + /// sys_ck not divided + Div1 = 0x0, + /// sys_ck divided by 2 + Div2 = 0x8, + /// sys_ck divided by 4 + Div4 = 0x9, + /// sys_ck divided by 8 + Div8 = 0xa, + /// sys_ck divided by 16 + Div16 = 0xb, + /// sys_ck divided by 64 + Div64 = 0xc, + /// sys_ck divided by 128 + Div128 = 0xd, + /// sys_ck divided by 256 + Div256 = 0xe, + /// sys_ck divided by 512 + Div512 = 0xf, + _, }; - pub const DIR = enum(u1) { - Write = 0x0, - Read = 0x1, + pub const HSEEXT = enum(u1) { + /// HSE in analog mode (default after reset) + Analog = 0x0, + /// HSE in digital mode + Digital = 0x1, }; - pub const DIS = enum(u1) { - /// write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed - Allowed = 0x0, - /// write to DA[7:0] and to IBIDEN is disabled/locked - Locked = 0x1, + pub const HSIDIV = enum(u2) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x1, + /// Division by 4 + Div4 = 0x2, + /// Division by 8 + Div8 = 0x3, }; - pub const MEND = enum(u1) { - /// this message from controller is followed by a repeated start (Sr), before another message must be emitted - RepeatedStart = 0x0, - /// this message from controller ends with a stop (P), being the last message of a frame - Stop = 0x1, + pub const I2CSEL = enum(u2) { + /// rcc_pclk1 selected as peripheral clock + PCLK1 = 0x0, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// hsi_ker selected as peripheral clock + HSI = 0x2, + /// csi_ker selected as peripheral clock + CSI = 0x3, }; - pub const RNW = enum(u1) { - /// write message - Write = 0x0, - /// read message - Read = 0x1, + pub const I3C2SEL = enum(u2) { + /// rcc_pclk3 selected as peripheral clock + PCLK3 = 0x0, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// hsi_ker selected as peripheral clock + HSI = 0x2, + /// csi_ker selected as peripheral clock + CSI = 0x3, }; - pub const RSTACT = enum(u2) { - NoReset = 0x0, - /// first level of reset: the application software must either: a) partially reset the peripheral, by a write and clear of the enable bit of the I3C configuration register (write EN = 0). This resets the I3C bus interface and the I3C kernel sub-parts, without modifying the content of the I3C APB registers (except the EN bit). b) fully reset the peripheral, including all its registers, via a write and set of the I3C reset control bit of the RCC (reset and clock controller) register. - FirstLevel = 0x1, - /// second level of reset: the application software must issue a warm reset, also known as a system reset. This (see Section 11: Reset and clock control (RCC)) has the same impact as a pin reset (NRST = 0): – the software writes and sets the SYSRESETREQ control bit of the AITR register, when the device is controlled by a Cortex®-M. – the software writes and sets SYSRST = 1 in the RCC_GRSTCSETR register, when the device is controlled by a Cortex®-A. - SecondLevel = 0x2, - NoResetEither = 0x3, + pub const LPTIM1SEL = enum(u3) { + /// rcc_pclk3 selected as peripheral clock + PCLK3 = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// LSE selected as peripheral clock + LSE = 0x3, + /// LSI selected as peripheral clock + LSI = 0x4, + /// PER selected as peripheral clock + PER = 0x5, + _, }; - pub const THRES = enum(u1) { - /// TXFNFF is set when 1 byte must be written in TX-FIFO (in I3C_TDR). - Byte = 0x0, - /// TXFNFF is set when 1 word / 4 bytes must be written in TX-FIFO (in the I3C_TDWR register). If the a number of the last transmitted data is not a multiple of 4 bytes (XDCNT[1:0] = 00 in the I3C_SR register), only the relevant 1, 2, or 3 valid LSB bytes of the last word are taken into account by the hardware, and sent on the I3C bus. - Word = 0x1, + pub const LPTIM2SEL = enum(u3) { + /// rcc_pclk1 selected as peripheral clock + PCLK1 = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// LSE selected as peripheral clock + LSE = 0x3, + /// LSI selected as peripheral clock + LSI = 0x4, + /// PER selected as peripheral clock + PER = 0x5, + _, }; - pub const DataRegs = extern struct { - /// I3C receive data byte register. - DR: mmio.Mmio(packed struct(u32) { - /// 8-bit received data on I3C bus. - DB: u8, - padding: u24, - }), - /// I3C receive data word register. - DWR: mmio.Mmio(packed struct(u32) { - /// 8-bit received data (earliest byte on I3C bus). - DB: u8, - padding: u24, - }), + pub const LPUARTSEL = enum(u3) { + /// rcc_pclk3 selected as kernel clock (default after reset) + PCLK3 = 0x0, + /// pll2_q_ck selected as kernel clock + PLL2_Q = 0x1, + /// hsi_ker_ck selected as kernel clock + HSI = 0x3, + /// csi_ker_ck selected as kernel clock + CSI = 0x4, + /// lse_ck selected as kernel clock + LSE = 0x5, + _, }; - /// Improved inter-integrated circuit. - pub const I3C = extern struct { - /// I3C message control register. - CR: mmio.Mmio(packed struct(u32) { - /// count of data to transfer during a read or write message, in bytes (whatever I3C is acting as controller/target) Linear encoding up to 64 Kbytes -1 ... - DCNT: u16, - /// read / non-write message (when I3C is acting as controller) When I3C is acting as controller, this field is used if MTYPE[3:0]=0010 (private message) or MTYPE[3:0]=0011 (direct message) or MTYPE[3:0]=0100 (legacy I2C message), in order to emit the RnW bit on the I3C bus. - RNW: packed union { - raw: u1, - value: RNW, - }, - /// 7-bit I3C dynamic / I2C static target address (when I3C is acting as controller) When I3C is acting as controller, this field is used if MTYPE[3:0]=0010 (private message) or MTYPE[3:0]=0011 (direct message) or MTYPE[3:0]=0100 (legacy I2C message). - ADD: u7, - reserved27: u3, - /// message type (whatever I3C is acting as controller/target) Bits[26:0] are ignored. After M2 error detection on an I3C SDR message, this is needed for SCL “stuck at” recovery. Bits[26:0] are ignored. If I3C_CFGR.EXITPTRN=1, an HDR exit pattern is emitted on the bus to generate an escalation fault. Bits[23:17] (ADD[6:0]) is the emitted 7-bit dynamic address. Bit[16] (RNW) is the emitted RnW bit. The transferred private message is: {S / S+7’h7E+RnW=0+Sr / Sr+*} + 7-bit DynAddr + RnW + (8-bit Data + T)* + Sr/P. After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7’h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7’h7E+RnW=0) if needed, i.e. if it follows an I3C direct message without ending by a P (Stop). Bits[23:17] (ADD[6:0]) is the emitted 7-bit dynamic address. Bit[16] (RNW) is the emitted RnW bit. The transferred direct message is: Sr + 7-bit DynAddr + RnW + (8-bit Data + T)* + Sr/P Bits[23:17] (ADD[6:0]) is the emitted 7-bit static address. Bit[16] (RNW) is the emitted RnW bit. The transferred legacy I2C message is: {S / S+ 7’h7E+RnW=0 + Sr / Sr+*} + 7-bit StaAddr + RnW + (8-bit Data + T)* + Sr/P. After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7’h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7’h7E+RnW=0) if needed, i.e. if it follows an I3C direct message without ending by a P (Stop). 1xxx: reserved (when I3C is acting as I3C controller, used when target) 0xxx: reserved {S +} 7’h02 addr + RnW=0 {S +} 7-bit I3C_DEVR0.DA[6:0] + RnW=0 after a bus available condition (the target first emits a START request), or once the controller drives a START. {S +} 7-bit I3C_DEVR0.DA[6:0] + RnW=1 (+Ack/Nack from controller) When acknowledged from controller, the next (optional, depending on I3C_BCR.BCR2) transmitted IBI payload data is defined by I3C_CR.DCNT[15:0] and must be consistently programmed vs the maximum IBI payload data size which is defined by I3C_IBIDR.IBIP[2:0]. Others: reserved. - MTYPE: u4, - /// message end type (when the I3C is acting as controller). - MEND: packed union { - raw: u1, - value: MEND, - }, - }), - /// I3C configuration register. - CFGR: mmio.Mmio(packed struct(u32) { - /// I3C enable (whatever I3C is acting as controller/target) - Except registers, the peripheral is under reset (a.k.a. partial reset). - Before clearing EN, when I3C is acting as a controller, all the possible target requests must be disabled using DISEC CCC. - When I3C is acting as a target, software should not disable the I3C, unless a partial reset is needed. In this state, some register fields can not be modified (like CRINIT, HKSDAEN for the I3C_CFGR). - EN: u1, - /// initial controller/target role This bit can be modified only when I3C_CFGR.EN = 0. Once enabled by setting I3C_CFGR.EN = 1, I3C peripheral initially acts as an I3C target. I3C does not drive SCL line and does not enable SDA pull-up, until it eventually acquires the controller role. Once enabled by setting I3C_CFGR.EN = 1, I3C peripheral initially acts as a controller. It has the I3C controller role, so drives SCL line and enables SDA pull-up, until it eventually offers the controller role to an I3C secondary controller. - CRINIT: packed union { - raw: u1, - value: CRINIT, - }, - /// no arbitrable header after a START (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame. - The target address is emitted directly after a START in case of a legacy I2C message or an I3C SDR private read/write message. - This is a more performing option (when is useless the emission of the 0x7E arbitrable header), but this is to be used only when the controller is sure that the addressed target device can not emit concurrently an IBI or a controller-role request (to insure no misinterpretation and no potential conflict between the address emitted by the controller in open-drain mode and the same address a target device can emit after a START, for IBI or MR). - NOARBH: u1, - /// HDR reset pattern enable (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame. - RSTPTRN: u1, - /// HDR Exit Pattern enable (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame. This is used to send only the header to test ownership of the bus when there is a suspicion of problem after controller-role hand-off (new controller didn’t assert its controller-role by accessing the previous one in less than Activity State time). The HDR Exit Pattern is sent even if the message header {S/Sr + 0x7E addr + W } is ACKed. - EXITPTRN: u1, - /// High-keeper enable on SDA line (when I3C is acting as a controller) This bit can be modified only when I3C_CFGR.EN=0. - HKSDAEN: u1, - reserved7: u1, - /// Hot Join request acknowledge (when I3C is acting as a controller) After the NACK, the message continues as initially programmed (the hot-joining target is aware of the NACK and surely emits another hot-join request later on). After the ACK, the message continues as initially programmed. The software is aware by the HJ interrupt (flag I3C_EVR.HJF is set) and initiates the ENTDAA sequence later on, potentially preventing others Hot Join requests with a Disable target events command (DISEC, with DISHJ=1). Independently of the HJACK configuration, further Hot Join request(s) are NACKed until the Hot Join flag, HJF, is cleared. However, a NACKed target can be assigned a dynamic address by the ENTDAA sequence initiated later on by the first HJ request, preventing this target to emit an HJ request again. - HJACK: u1, - /// RX-FIFO DMA request enable (whatever I3C is acting as controller/target) - Software reads and pops a data byte/word from RX-FIFO i.e. reads I3C_RDR or I3C_RDWR register. - A next data byte/word is to be read by the software either via polling on the flag I3C_EVR.RXFNEF=1 or via interrupt notification (enabled by I3C_IER.RXFNEIE=1). - DMA reads and pops data byte(s)/word(s) from RX-FIFO i.e. reads I3C_RDR or I3C_RDWR register. - A next data byte/word is automatically read by the programmed hardware (i.e. via the asserted RX-FIFO DMA request from the I3C and the programmed DMA channel). - RXDMAEN: u1, - /// RX-FIFO flush (whatever I3C is acting as controller/target) This bit can only be written. - RXFLUSH: u1, - /// RX-FIFO threshold (whatever I3C is acting as controller/target) This threshold defines, compared to the RX-FIFO level, when the I3C_EVR.RXFNEF flag is set (and consequently if RXDMAEN=1 when is asserted a DMA RX request). RXFNEF is set when 1 byte is to be read in RX-FIFO (i.e. in I3C_RDR). RXFNEF is set when 4 bytes are to be read in RX-FIFO (i.e. in I3C_RDWR). - RXTHRES: packed union { - raw: u1, - value: THRES, - }, - reserved12: u1, - /// TX-FIFO DMA request enable (whatever I3C is acting as controller/target) - Software writes and pushes a data byte/word into TX-FIFO i.e. writes I3C_TDR or I3C_TDWR register, to be transmitted over the I3C bus. - A next data byte/word is to be written by the software either via polling on the flag I3C_EVR.TXFNFF=1 or via interrupt notification (enabled by I3C_IER.TXFNFIE=1). - DMA writes and pushes data byte(s)/word(s) into TX-FIFO i.e. writes I3C_TDR or I3C_TDWR register. - A next data byte/word transfer is automatically pushed by the programmed hardware (i.e. via the asserted TX-FIFO DMA request from the I3C and the programmed DMA channel). - TXDMAEN: u1, - /// TX-FIFO flush (whatever I3C is acting as controller/target) This bit can only be written. When the I3C is acting as target, this bit can be used to flush the TX-FIFO on a private read if the controller has early ended the read data (i.e. driven low the T bit) and there is/are remaining data in the TX-FIFO (i.e. I3C_SR.ABT=1 and I3C_SR.XDCNT[15:0] < I3C_TGTTDR.TGTTDCNT[15:0]). - TXFLUSH: u1, - /// TX-FIFO threshold (whatever I3C is acting as controller/target) This threshold defines, compared to the TX-FIFO level, when the I3C_EVR.TXFNFF flag is set (and consequently if TXDMAEN=1 when is asserted a DMA TX request). TXFNFF is set when 1 byte is to be written in TX-FIFO (i.e. in I3C_TDR). TXFNFF is set when 4 bytes are to be written in TX-FIFO (i.e. in I3C_TDWR). - TXTHRES: packed union { - raw: u1, - value: THRES, - }, - reserved16: u1, - /// S-FIFO DMA request enable (when I3C is acting as controller) Condition: When RMODE=1 (FIFO is enabled for the status): - Software reads and pops a status word from S-FIFO i.e. reads I3C_SR register after a completed frame (I3C_EVR.FCF=1) or an error (I3C_EVR.ERRF=1). - A status word can be read by the software either via polling on these register flags or via interrupt notification (enabled by I3C_IER.FCIE=1 and I3C_IER.ERRIE=1). - DMA reads and pops status word(s) from S-FIFO i.e. reads I3C_SR register. - Status word(s) are automatically read by the programmed hardware (i.e. via the asserted S-FIFO DMA request from the I3C and the programmed DMA channel). - SDMAEN: u1, - /// S-FIFO flush (when I3C is acting as controller) When I3C is acting as I3C controller, this bit can only be written (and is only used when I3C is acting as controller). - SFLUSH: u1, - /// S-FIFO enable / status receive mode (when I3C is acting as controller) When I3C is acting as I3C controller, this bit is used for the enabling the FIFO for the status (S-FIFO) vs the received status from the target on the I3C bus. When I3C is acting as target, this bit must be cleared. - Status register (i.e. I3C_SR) is used without FIFO mechanism. - There is no SCL stretch if a new status register content is not read. - Status register must be read before being lost/overwritten. All message status must be read. There is SCL stretch when there is no more space in the S-FIFO. - RMODE: u1, - /// transmit mode (when I3C is acting as controller) When I3C is acting as I3C controller, this bit is used for the C-FIFO and TX-FIFO management vs the emitted frame on the I3C bus. A frame transfer starts as soon as first control word is present in C-FIFO. - TMODE: u1, - /// C-FIFO DMA request enable (when I3C is acting as controller) When I3C is acting as controller: - Software writes and pushes control word(s) into C-FIFO i.e. writes I3C_CR register, as needed for a given frame. - A next control word transfer can be written by software either via polling on the flag I3C_EVR.CFNFF=1 or via interrupt notification (enabled by I3C_IER.CFNFIE=1). - DMA writes and pushes control word(s) into C-FIFO i.e. writes I3C_CR register, as needed for a given frame. - A next control word transfer is automatically written by the programmed hardware (i.e. via the asserted C-FIFO DMA request from the I3C and the programmed DMA channel). - CDMAEN: u1, - /// C-FIFO flush (when I3C is acting as controller) This bit can only be written. - CFLUSH: u1, - reserved30: u8, - /// frame transfer set (a.k.a. software trigger) (when I3C is acting as controller) This bit can only be written. When I3C is acting as I3C controller: Note: If this bit is not set, the other alternative for the software to initiate a frame transfer is to directly write the first control word register (i.e. I3C_CR) while C-FIFO is empty (i.e. I3C_EVR.CFEF=1). Then, if the first written control word is not tagged as a message end (i.e I3C_CR.MEND=0), it causes the hardware to assert the flag I3C_EVR.CFNFF (C-FIFO not full and a next control word is needed). - TSFSET: u1, - padding: u1, - }), - reserved16: [8]u8, - RxDataRegs: u32, - reserved24: [4]u8, - TxDataRegs: u32, - reserved32: [4]u8, - /// I3C IBI payload data register. - IBIDR: mmio.Mmio(packed struct(u32) { - /// 8-bit IBI payload data (earliest byte on I3C bus, i.e. MDB[7:0] mandatory data byte). - IBIDB: u8, - padding: u24, - }), - /// I3C target transmit configuration register. - TGTTDR: mmio.Mmio(packed struct(u32) { - /// transmit data counter, in bytes (when I3C is configured as target) This field must be written by software in the same access when is asserted PRELOAD, in order to define the number of bytes to preload and to transmit. This field is updated by hardware and reports, when read, the remaining number of bytes to be loaded into the TX-FIFO. - TGTTDCNT: u16, - /// preload of the TX-FIFO (when I3C is configured as target) This bit must be written and asserted by software in the same access when is written and defined the number of bytes to preload into the TX-FIFO and to transmit. This bit is cleared by hardware when all the data bytes to transmit are loaded into the TX-FIFO. - PRELOAD: u1, - padding: u15, - }), - reserved48: [8]u8, - /// I3C status register. - SR: mmio.Mmio(packed struct(u32) { - /// data counter - When the I3C is acting as controller: number of targets detected on the bus - When the I3C is acting as target: number of transmitted bytes - Whatever the I3C is acting as controller or target: number of data bytes read from or transmitted on the I3C bus during the MID[7:0] message. - XDCNT: u16, - reserved17: u1, - /// a private read message is completed/aborted prematurely by the target (when the I3C is acting as controller) When the I3C is acting as controller, this bit indicates if the private read data which is transmitted by the target early terminates (i.e. the target drives T bit low earlier vs what does expect the controller in terms of programmed number of read data bytes i.e. I3C_CR.DCNT[15:0]). - ABT: u1, - /// message direction Whatever the I3C is acting as controller or target, this bit indicates the direction of the related message on the I3C bus Note: ENTDAA CCC is considered as a write command. - DIR: packed union { - raw: u1, - value: DIR, - }, - reserved24: u5, - /// message identifier/counter of a given frame (when the I3C is acting as controller) When the I3C is acting as controller, this field identifies the control word message (i.e. I3C_CR) to which the I3C_SR status register refers. First message of a frame is identified with MID[7:0]=0. This field is incremented (by hardware) on the completion of a new message control word (i.e. I3C_CR) over I3C bus. This field is reset for every new frame start. - MID: u8, - }), - /// I3C status error register. - SER: mmio.Mmio(packed struct(u32) { - /// protocol error code/type controller detected an illegally formatted CCC controller detected that transmitted data on the bus is different from expected controller detected a not acknowledged broadcast address (7’hE) controller detected the new controller did not drive bus after controller-role hand-off target detected an invalid broadcast address 7’hE+W target detected a parity error on a CCC code via a parity check (vs T bit) target detected a parity error on a write data via a parity check (vs T bit) target detected a parity error on the assigned address during dynamic address arbitration via a parity check (vs PAR bit) target detected a 7’hE+R missing after Sr during dynamic address arbitration target detected an illegally formatted CCC target detected that transmitted data on the bus is different from expected others: reserved. - CODERR: packed union { - raw: u4, - value: CODERR, - }, - /// protocol error. - PERR: u1, - /// SCL stall error (when the I3C is acting as target). - STALL: u1, - /// RX-FIFO overrun or TX-FIFO underrun i) a TX-FIFO underrun: TX-FIFO is empty and a write data byte has to be transmitted ii) a RX-FIFO overrun: RX-FIFO is full and a new data byte is received. - DOVR: u1, - /// C-FIFO underrun or S-FIFO overrun (when the I3C is acting as controller) i) a C-FIFO underrun: control FIFO is empty and a restart has to be emitted ii) a S-FIFO overrun: S-FIFO is full and a new message ends. - COVR: u1, - /// address not acknowledged (when the I3C is configured as controller) i) a legacy I2C read/write transfer ii) a direct CCC write transfer iii) the second trial of a direct CCC read transfer iv) a private read/write transfer. - ANACK: u1, - /// data not acknowledged (when the I3C is acting as controller) i) a legacy I2C write transfer ii) the second trial when sending dynamic address during ENTDAA procedure. - DNACK: u1, - /// data error (when the I3C is acting as controller). - DERR: u1, - padding: u21, - }), - reserved64: [8]u8, - /// I3C received message register. - RMR: mmio.Mmio(packed struct(u32) { - /// IBI received payload data count (when the I3C is configured as controller) When the I3C is configured as controller, this field logs the number of data bytes effectively received in the I3C_IBIDR register. - IBIRDCNT: u3, - reserved8: u5, - /// received CCC code (when the I3C is configured as target) When the I3C is configured as target, this field logs the received CCC code. - RCODE: u8, - reserved17: u1, - /// received target address (when the I3C is configured as controller) When the I3C is configured as controller, this field logs the received dynamic address from the target during acknowledged IBI or controller-role request. - RADD: u7, - padding: u8, - }), - reserved80: [12]u8, - /// I3C event register. - EVR: mmio.Mmio(packed struct(u32) { - /// C-FIFO empty flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the C-FIFO is empty when controller, and that the I3C_CR register contains no control word (i.e. none IBI/CR/HJ request) when target. This flag is de-asserted by hardware to indicate that the C-FIFO is not empty when controller, and that the I3C_CR register contains one control word (i.e. a pending IBI/CR/HJ request) when target. Note: When the I3C is acting as controller, if the C-FIFO and TX-FIFO preload is configured (i.e. I3C_CFGR.TMODE=1), the software must wait for TXFEF=1 and CFEF=1 before starting a new frame transfer. - CFEF: u1, - /// TX-FIFO empty flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the TX-FIFO is empty. This flag is de-asserted by hardware to indicate that the TX-FIFO is not empty. Note: When the I3C is acting as controller, if the C-FIFO and TX-FIFO preload is configured (i.e. I3C_CFGR.TMODE=1), the software must wait for TXFEF=1 and CFEF=1 before starting a new frame transfer. - TXFEF: u1, - /// C-FIFO not full flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that a control word is to be written to the C-FIFO. This flag is de-asserted by hardware to indicate that a control word is not to be written to the C-FIFO. Note: The software must wait for CFNFF=1 (by polling or via the enabled interrupt) before writing to C-FIFO (i.e. writing to I3C_CR). - CFNFF: u1, - /// S-FIFO not empty flag (when the I3C is acting as controller) When the I3C is acting as controller, if the S-FIFO is enabled (i.e. I3C_CFGR.RMODE=1), this flag is asserted by hardware to indicate that a status word is to be read from the S-FIFO. This flag is de-asserted by hardware to indicate that a status word is not to be read from the S-FIFO. - SFNEF: u1, - /// TX-FIFO not full flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that a data byte/word is to be written to the TX-FIFO. This flag is de-asserted by hardware to indicate that a data byte/word is not to be written to the TX-FIFO. Note: The software must wait for TXFNFF=1 (by polling or via the enabled interrupt) before writing to TX-FIFO (i.e. writing to I3C_TDR or I3C_TDWR depending on I3C_CFGR.TXTHRES). Note: When the I3C is acting as target, if the software intends to use the TXFNFF flag for writing into I3C_TDR/I3C_TDWR, it must have configured and set the TX-FIFO preload (i.e. write I3C_TGTTDR.PRELOAD). - TXFNFF: u1, - /// RX-FIFO not empty flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that a data byte is to be read from the RX-FIFO. This flag is de-asserted by hardware to indicate that a data byte is not to be read from the RX-FIFO. Note: The software must wait for RXFNEF=1 (by polling or via the enabled interrupt) before reading from RX-FIFO (i.e. writing to I3C_RDR or I3C_RDWR depending on I3C_CFGR.RXTHRES). - RXFNEF: u1, - /// last written data byte/word flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the last data byte/word (depending on I3C_CFGR.TXTHRES) of a message is to be written to the TX-FIFO. This flag is de-asserted by hardware when the last data byte/word of a message is written. - TXLASTF: u1, - /// last read data byte/word flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the last data byte/word (depending on I3C_CFGR.RXTHRES) of a message is to be read from the RX-FIFO. This flag is de-asserted by hardware when the last data byte/word of a message is read. - RXLASTF: u1, - reserved9: u1, - /// frame complete flag (whatever the I3C is acting as controller/target) When the I3C is acting as controller, this flag is asserted by hardware to indicate that a frame has been (normally) completed on the I3C bus, i.e when a stop is issued. When the I3C is acting as target, this flag is asserted by hardware to indicate that a message addressed to/by this target has been (normally) completed on the I3C bus, i.e when a next stop or repeated start is then issued by the controller. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CFCF bit. - FCF: u1, - /// target-initiated read end flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that the target has prematurely ended a read transfer. Then, software should read I3C_SR to get more information on the prematurely read transfer. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CRXTGTENDF bit. - RXTGTENDF: u1, - /// flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that an error occurred.Then, software should read I3C_SER to get the error type. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CERRF bit. - ERRF: u1, - reserved15: u3, - /// IBI flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that an IBI request has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CIBIF bit. - IBIF: u1, - /// IBI end flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a IBI transfer has been received and completed (IBI acknowledged and IBI data bytes read by controller if any). This flag is cleared when software writes 1 into corresponding I3C_CEVR.CIBIENDF bit. - IBIENDF: u1, - /// controller-role request flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that a controller-role request has been acknowledged and completed (by hardware). The software should then issue a GETACCCR CCC (get accept controller role) for the controller-role hand-off procedure. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CCRF bit. - CRF: u1, - /// controller-role update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that it has now gained the controller role after the completed controller-role hand-off procedure. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CCRUPDF bit. - CRUPDF: u1, - /// hot-join flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that an hot join request has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CHJF bit. - HJF: u1, - reserved21: u1, - /// wakeup/missed start flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a start has been detected (i.e. a SDA falling edge followed by a SCL falling edge) but on the next SCL falling edge, the I3C kernel clock is (still) gated. Thus an I3C bus transaction may have been lost by the target. The corresponding interrupt may be used to wakeup the device from a low power mode (Sleep or Stop mode). This flag is cleared when software writes 1 into corresponding I3C_CEVR.CWKPF bit. - WKPF: u1, - /// get flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that any direct CCC of get type (GET*** CCC) has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CGETF bit. - GETF: u1, - /// get status flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a direct GETSTATUS CCC (get status) has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CSTAF bit. - STAF: u1, - /// dynamic address update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a dynamic address update has been received via any of the broadcast ENTDAA, RSTDAA and direct SETNEWDA CCC. Then, software should read I3C_DEVR0.DA[6:0] to get the maximum write length value. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CDAUPDF bit. - DAUPDF: u1, - /// maximum write length update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a direct SETMWL CCC (set max write length) has been received. Then, software should read I3C_MAXWLR.MWL[15:0] to get the maximum write length value. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CMWLUPDF bit. - MWLUPDF: u1, - /// maximum read length update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a direct SETMRL CCC (set max read length) has been received. Then, software should read I3C_MAXRLR.MRL[15:0] to get the maximum read length value. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CMRLUPDF bit. - MRLUPDF: u1, - /// reset pattern flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a reset pattern has been detected (i.e. 14 SDA transitions while SCL is low, followed by repeated start, then stop). Then, software should read I3C_DEVR0.RSTACT[1:0] and I3C_DEVR0.RSTVAL, to know what reset level is required. If RSTVAL=1: when the RSTF is asserted (and/or the corresponding interrupt if enabled), I3C_DEVR0.RSTACT[1:0] dictates the reset action to be performed by the software if any. If RSTVAL=0: when the RSTF is asserted (and/or the corresponding interrupt if enabled), the software should issue an I3C reset after a first detected reset pattern, and a system reset on the second one. The corresponding interrupt may be used to wakeup the device from a low power mode (Sleep or Stop mode). This flag is cleared when software writes 1 into corresponding I3C_CEVR.CRSTF bit. - RSTF: u1, - /// activity state update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that the direct or broadcast ENTASx CCC (with x=0...3) has been received. Then, software should read I3C_DEVR0.AS[1:0]. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CASUPDF bit. - ASUPDF: u1, - /// interrupt/controller-role/hot-join update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that the direct or broadcast ENEC/DISEC CCC (enable/disable target events) has been received, where a target event is either an interrupt/IBI request, a controller-role request, or an hot-join request. Then, software should read respectively I3C_DEVR0.IBIEN, I3C_DEVR0.CREN or I3C_DEVR0.HJEN. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CINTUPDF bit. - INTUPDF: u1, - /// DEFTGTS flag (when the I3C is acting as target) When the I3C is acting as target (and is typically controller capable), this flag is asserted by hardware to indicate that the broadcast DEFTGTS CCC (define list of targets) has been received. Then, software may store the received data for when getting the controller role. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CDEFF bit. - DEFF: u1, - /// group addressing flag (when the I3C is acting as target) When the I3C is acting as target (and is typically controller capable), this flag is asserted by hardware to indicate that the broadcast DEFGRPA CCC (define list of group addresses) has been received. Then, software may store the received data for when getting the controller role. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CGRPF bit. - GRPF: u1, - }), - /// I3C interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// C-FIFO not full interrupt enable (whatever the I3C is acting as controller/target). - CFNFIE: u1, - /// S-FIFO not empty interrupt enable (whatever the I3C is acting as controller/target). - SFNEIE: u1, - /// TX-FIFO not full interrupt enable (whatever the I3C is acting as controller/target). - TXFNFIE: u1, - /// RX-FIFO not empty interrupt enable (whatever the I3C is acting as controller/target). - RXFNEIE: u1, - reserved9: u3, - /// frame complete interrupt enable (whatever the I3C is acting as controller/target). - FCIE: u1, - /// target-initiated read end interrupt enable (when the I3C is acting as controller). - RXTGTENDIE: u1, - /// error interrupt enable (whatever the I3C is acting as controller/target). - ERRIE: u1, - reserved15: u3, - /// IBI request interrupt enable (when the I3C is acting as controller). - IBIIE: u1, - /// IBI end interrupt enable (when the I3C is acting as target). - IBIENDIE: u1, - /// controller-role request interrupt enable (when the I3C is acting as controller). - CRIE: u1, - /// controller-role update interrupt enable (when the I3C is acting as target). - CRUPDIE: u1, - /// hot-join interrupt enable (when the I3C is acting as controller). - HJIE: u1, - reserved21: u1, - /// wakeup interrupt enable (when the I3C is acting as target). - WKPIE: u1, - /// GETxxx CCC interrupt enable (when the I3C is acting as target). - GETIE: u1, - /// GETSTATUS CCC interrupt enable (when the I3C is acting as target). - STAIE: u1, - /// ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C is acting as target). - DAUPDIE: u1, - /// SETMWL CCC interrupt enable (when the I3C is acting as target). - MWLUPDIE: u1, - /// SETMRL CCC interrupt enable (when the I3C is acting as target). - MRLUPDIE: u1, - /// reset pattern interrupt enable (when the I3C is acting as target). - RSTIE: u1, - /// ENTASx CCC interrupt enable (when the I3C is acting as target). - ASUPDIE: u1, - /// ENEC/DISEC CCC interrupt enable (when the I3C is acting as target). - INTUPDIE: u1, - /// DEFTGTS CCC interrupt enable (when the I3C is acting as target). - DEFIE: u1, - /// DEFGRPA CCC interrupt enable (when the I3C is acting as target). - GRPIE: u1, - }), - /// I3C clear event register. - CEVR: mmio.Mmio(packed struct(u32) { - reserved9: u9, - /// clear frame complete flag (whatever the I3C is acting as controller/target). - CFCF: u1, - /// clear target-initiated read end flag (when the I3C is acting as controller). - CRXTGTENDF: u1, - /// clear error flag (whatever the I3C is acting as controller/target). - CERRF: u1, - reserved15: u3, - /// clear IBI request flag (when the I3C is acting as controller). - CIBIF: u1, - /// clear IBI end flag (when the I3C is acting as target). - CIBIENDF: u1, - /// clear controller-role request flag (when the I3C is acting as controller). - CCRF: u1, - /// clear controller-role update flag (when the I3C is acting as target). - CCRUPDF: u1, - /// clear hot-join flag (when the I3C is acting as controller). - CHJF: u1, - reserved21: u1, - /// clear wakeup flag (when the I3C is acting as target). - CWKPF: u1, - /// clear GETxxx CCC flag (when the I3C is acting as target). - CGETF: u1, - /// clear GETSTATUS CCC flag (when the I3C is acting as target). - CSTAF: u1, - /// clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C is acting as target). - CDAUPDF: u1, - /// clear SETMWL CCC flag (when the I3C is acting as target). - CMWLUPDF: u1, - /// clear SETMRL CCC flag (when the I3C is acting as target). - CMRLUPDF: u1, - /// clear reset pattern flag (when the I3C is acting as target). - CRSTF: u1, - /// clear ENTASx CCC flag (when the I3C is acting as target). - CASUPDF: u1, - /// clear ENEC/DISEC CCC flag (when the I3C is acting as target). - CINTUPDF: u1, - /// clear DEFTGTS CCC flag (when the I3C is acting as target). - CDEFF: u1, - /// clear DEFGRPA CCC flag (when the I3C is acting as target). - CGRPF: u1, - }), - reserved96: [4]u8, - /// I3C own device characteristics register. - DEVR0: mmio.Mmio(packed struct(u32) { - /// dynamic address is valid (when the I3C is acting as target) When the I3C is acting as controller, this field can be written by software, for validating its own dynamic address, for example before a controller-role hand-off. When the I3C is acting as target, this field is asserted by hardware on the acknowledge of the broadcast ENTDAA CCC or the direct SETNEWDA CCC, and this field is cleared by hardware on the acknowledge of the broadcast RSTDAA CCC. - DAVAL: u1, - /// 7-bit dynamic address When the I3C is acting as controller, this field can be written by software, for defining its own dynamic address. When the I3C is acting as target, this field is updated by hardware on the reception of either the broadcast ENTDAA CCC or the direct SETNEWDA CCC. - DA: u7, - reserved16: u8, - /// IBI request enable (when the I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0, and is updated by hardware on the reception of DISEC CCC with DISINT=1 (i.e. cleared) and the reception of ENEC CCC with ENINT=1 (i.e. set). - IBIEN: u1, - /// controller-role request enable (when the I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0, and is updated by hardware on the reception of DISEC CCC with DISCR=1 (i.e. cleared) and the reception of ENEC CCC with ENCR=1 (i.e. set). - CREN: u1, - reserved19: u1, - /// hot-join request enable (when the I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0, and is updated by hardware on the reception of DISEC CCC with DISHJ=1 (i.e. cleared) and the reception of ENEC CCC with ENHJ=1 (i.e. set). - HJEN: u1, - /// activity state (when the I3C is acting as target) This read field is updated by hardware on the reception of a ENTASx CCC (enter activity state, with x=0-3):. - AS: u2, - /// reset action/level on received reset pattern (when the I3C is acting as target) This read field is used by hardware on the reception of a direct read RSTACT CCC in order to return the corresponding data byte on the I3C bus. This read field is updated by hardware on the reception of a broadcast or direct write RSTACT CCC (target reset action). Only the defining bytes 0x00, 0x01 and 0x02 are mapped, and RSTACT[1:0] = Defining Byte[1:0]. a) partially reset the I3C peripheral, by a write and clear of the enable bit of the i3C configuration register (i.e. write I3C_CFGR.EN=0). This reset the I3C bus interface and the I3C kernel sub-parts, without modifying the content of the I3C APB registers (excepted the I3C_CFGR.EN bit). b) reset fully the I3C peripheral including all its registers via a write and set to the I3C reset control bit of the RCC (Reset and Clock Controller) register. a system reset. This has the same impact as a pin reset (i.e. NRST=0) (refer to RCC functional description - Reset part): – the software writes and set the AICR.SYSRESETREQ register control bit, when the device is controlled by a CortexTM-M. – the software writes and set the RCC_GRSTCSETR.SYSRST=1, when the device is controlled by a CortexTM-A. - RSTACT: packed union { - raw: u2, - value: RSTACT, - }, - /// reset action is valid (when the I3C is acting as target) This read bit is asserted by hardware to indicate that the RTSACT[1:0] field has been updated on the reception of a broadcast or direct write RSTACT CCC (target reset action) and is valid. This field is cleared by hardware when the target receives a frame start. If RSTVAL=1: when the RSTF is asserted (and/or the corresponding interrupt if enabled), I3C_DEVR0.RSTACT[1:0] dictates the reset action to be performed by the software if any. If RSTVAL=0: when the RSTF is asserted (and/or the corresponding interrupt if enabled), the software should issue an I3C reset after a first detected reset pattern, and a system reset on the second one. - RSTVAL: u1, - padding: u7, - }), - /// I3C device 1 characteristics register. - DEVR: [4]mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// assigned I3C dynamic address to target x (when the I3C is acting as controller) When the I3C is acting as controller, this field should be written by software to store the 7-bit dynamic address that the controller sends via a broadcast ENTDAA or a direct SETNEWDA CCC which has been acknowledged by the target x. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1. - DA: u7, - reserved16: u8, - /// IBI request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a IBI request from target x: - After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another IBI request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the controller logs the IBI payload data, if any, depending on I3C_DEVRx.IBIDEN. - The software is notified by the IBI flag (i.e. I3C_EVR.IBIF=1) and/or the corresponding interrupt if enabled; - Independently from IBIACK configuration for this or other devices, further IBI request(s) are NACKed until IBI request flag (i.e. I3C_EVR.IBIF) and controller-role request flag (i.e. I3C_EVR.CRF) are both cleared. - IBIACK: packed union { - raw: u1, - value: ACK, - }, - /// controller-role request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a controller-role request from target x: After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another controller-role request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the message continues as initially programmed. The software is notified by the controller-role request flag (i.e. I3C_EVR.CRF=1) and/or the corresponding interrupt if enabled; For effectively granting the controller-role to the requesting secondary controller, software should issue a GETACCCR (formerly known as GETACCMST), followed by a STOP. - Independently of CRACK configuration for this or other devices, further controller-role request(s) are NACKed until controller-role request flag (i.e. I3C_EVR.CRF) and IBI flag (i.e. I3C_EVR.IBIF) are both cleared. - CRACK: packed union { - raw: u1, - value: ACK, - }, - /// IBI data enable (when the I3C is acting as controller) When the I3C is acting as controller, this bit should be written by software to store the BCR[2] bit as received from the target x during broadcast ENTDAA or direct GETBCR CCC via the received I3C_RDR. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1. - IBIDEN: u1, - /// suspend/stop I3C transfer on received IBI (when the I3C is acting as controller) When the I3C is acting as controller, this bit is used to receive an IBI from target x with pending read notification feature (i.e. with received MDB[7:5]=3’b101). If this bit is set, when an IBI is received (i.e. I3C_EVR.IBIF=1), a Stop is emitted on the I3C bus and the C-FIFO is automatically flushed by hardware; to avoid a next private read communication issue if a previous private read message to the target x was stored in the C-FIFO. - SUSP: u1, - reserved31: u11, - /// DA[6:0] write disabled (when the I3C is acting as controller) When the I3C is acting as controller, once that software set IBIACK=1 or CRACK=1, this read bit is set by hardware (i.e. DIS=1) to lock the configured DA[6:0] and IBIDEN values. Then, to be able to next modify DA[6:0] or IBIDEN, the software must wait for this field DIS to be de-asserted by hardware (i.e. polling on DIS=0) before modifying these two assigned values to the target x. Indeed, the target may be requesting an IBI or a controller-role meanwhile the controller intends to modify DA[6:0] or IBIDEN. - DIS: packed union { - raw: u1, - value: DIS, - }, - }), - reserved144: [28]u8, - /// I3C maximum read length register. - MAXRLR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// IBI payload data size, in bytes (when I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0 to set the number of data bytes to be sent to the controller after an IBI request has been acknowledged.This field may be updated by hardware on the reception of SETMRL command (which potentially also updated IBIP[2:0]). Software is notified of a MRL update by the I3C_EVR.MRLUPF and the corresponding interrupt if enabled. others: same as 100. - IBIP: u3, - padding: u13, - }), - /// I3C maximum write length register. - MAXWLR: mmio.Mmio(packed struct(u32) { - /// maximum data write length (when I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0 and updated by hardware on the reception of SETMWL command. Software is notified of a MWL update by the I3C_EVR.MWLUPF and the corresponding interrupt if enabled. This field is used by hardware to return the value on the I3C bus when the target receives a GETMWL CCC. - ML: u16, - padding: u16, - }), - reserved160: [8]u8, - /// I3C timing register 0. - TIMINGR0: mmio.Mmio(packed struct(u32) { - /// SCL low duration in I3C push-pull phases, in number of kernel clocks cycles: tSCLL_PP = (SCLL_PP + 1) x tI3CCLK SCLL_PP is used to generate tLOW (I3C) timing. - SCLL_PP: u8, - /// SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles: tSCLH_I3C = (SCLH_I3C + 1) x tI3CCLK SCLH_I3C is used to generate both tHIGH (I3C) and tHIGH_MIXED timings. - SCLH_I3C: u8, - /// SCL low duration in open-drain phases, used for legacy I2C commands and for I3C open-drain phases (address header phase following a START, not a Repeated START), in number of kernel clocks cycles: tSCLL_OD = (SCLL_OD + 1) x tI3CCLK SCLL_OD is used to generate both tLOW (I2C) and tLOW_OD timings (max. of the two). - SCLL_OD: u8, - /// SCL high duration, used for legacy I2C commands, in number of kernel clocks cycles: tSCLH_I2C = (SCLH_I2C + 1) x tI3CCLK SCLH_I2C is used to generate tHIGH (I2C) timing. - SCLH_I2C: u8, - }), - /// I3C timing register 1. - TIMINGR1: mmio.Mmio(packed struct(u32) { - /// number of kernel clock cycles, that is used whatever I3C is acting as controller or target, to set the following MIPI I3C timings, like bus available condition time: When the I3C is acting as target: for bus available condition time: it must wait for (bus available condition) time to be elapsed after a stop and before issuing a start request for an IBI or a controller-role request (i.e. bus free condition is sustained for at least tAVAL). refer to MIPI timing tAVAL = 1 �s. This timing is defined by: tAVAL = (AVAL[7:0] + 2) x tI3CCLK for bus idle condition time: it must wait for (bus idle condition) time to be elapsed after that both SDA and SCL are continuously high and stable before issuing a hot-join event. Refer to MIPI v1.1 timing tIDLE = 200 �s . This timing is defined by: tIDLE = (AVAL[7:0] + 2) x 200 x tI3CCLK When the I3C is acting as controller, it can not stall the clock beyond a maximum stall time (i.e. stall the SCL clock low), as follows: on first bit of assigned address during dynamic address assignment: it can not stall the clock beyond the MIPI timing tSTALLDAA = 15 ms. This timing is defined by: tSTALLDAA = (AVAL[7:0] + 1) x 15000 x tI3CCLK on ACK/NACK phase of I3C/I2C transfer, on parity bit of write data transfer, on transition bit of I3C read transfer: it can not stall the clock beyond the MIPI timing tSTALL = 100 �s. This timing is defined by: tSTALL = (AVAL[7:0] + 1) x 100 x tI3CCLK Whatever the I3C is acting as controller or as (controller-capable) target, during a controller-role hand-off procedure: The new controller must wait for a time (refer to MIPI timing tNEWCRLock) before pulling SDA low (i.e. issuing a start). And the active controller must wait for the same time while monitoring new controller and before testing the new controller by pulling SDA low. This time to wait is dependent on the defined I3C_TIMINGR1.ANSCR[1:0], as follows: If ASNCR[1:0]=00: tNEWCRLock = (AVAL[7:0] + 1) x tI3CCLK If ASNCR[1:0]=01: tNEWCRLock = (AVAL[7:0] + 1) x 100 x tI3CCLK If ASNCR[1:0]=10: tNEWCRLock = (AVAL[7:0] + 1) x 2000 x tI3CCLK If ASNCR[1:0]=11: tNEWCRLock = (AVAL[7:0] + 1) x 50000 x tI3CCLK. - AVAL: u8, - /// activity state of the new controller (when I3C is acting as - active- controller) This field indicates the time to wait before being accessed as new target, refer to the other field AVAL[7:0]. This field can be modified only when the I3C is acting as controller. - ASNCR: u2, - reserved16: u6, - /// number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C is acting as controller) When the I3C is acting as controller: for I3C start timing: it must wait for (bus free condition) time to be elapsed after a stop and before a start, refer to MIPI timings (I3C) tCAS and (I2C) tBUF. These timings are defined by: tBUF= tCAS = [ (FREE[6:0] + 1) x 2 - (0,5 + SDA_HD)] x tI3CCLK Note: for pure I3C bus: tCASmin= 38,4 ns. Note: for pure I3C bus: tCASmax=1�s, 100�s, 2ms, 50ms for respectively ENTAS0,1,2, and 3. Note: for mixed bus with I2C fm+ device: tBUFmin = 0,5 �s. Note: for mixed bus with I2C fm device: tBUFmin = 1,3 �s. for I3C repeated start timing: it must wait for time to be elapsed after a repeated start (i.e. SDA is de-asserted) and before driving SCL low, refer to. MIPI timing tCASr. This timing is defined by: tCASr = [ (FREE[6:0] + 1) x 2 - (0,5 + SDA_HD)] x tI3CCLK for I3C stop timing: it must wait for time to be elapsed after that the SCL clock is driven high and before the stop condition (i.e. SDA is asserted). This timing is defined by: tCBP = (FREE[6:0] + 1) x tI3CCLK for I3C repeated start timing (T-bit when controller ends read with repeated start followed by stop): it must wait for time to be elapsed after that the SCL clock is driven high and before the repeated start condition (i.e. SDA is de-asserted). This timing is defined by: tCBSr = (FREE[6:0] + 1) x tI3CCLK. - FREE: u7, - reserved28: u5, - /// SDA hold time (when the I3C is acting as controller), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull tHD_PP):. - SDA_HD: u1, - padding: u3, - }), - /// I3C timing register 2. - TIMINGR2: mmio.Mmio(packed struct(u32) { - /// Controller clock stall on T-bit phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to prepare data to be sent. - STALLT: u1, - /// controller clock stall on PAR phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to read received data. - STALLD: u1, - /// controller clock stall on PAR phase of CCC enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase of common command code (before 9th bit). This allows the target to decode the command. - STALLC: u1, - /// controller clock stall enable on ACK phase The SCL is stalled (during tSCLL_STALLas defined by STALL) in the address ACK/NACK phase (before 9th bit). This allows the target to prepare data or the controller to respond to target interrupt. - STALLA: u1, - reserved8: u4, - /// controller clock stall time, in number of kernel clock cycles tSCLL_STALL = STALL x tI3CCLK. - STALL: u8, - padding: u16, - }), - reserved192: [20]u8, - /// I3C bus characteristics register. - BCR: mmio.Mmio(packed struct(u32) { - /// max data speed limitation. - BCR0: u1, - reserved2: u1, - /// in-band interrupt (IBI) payload. - BCR2: u1, - reserved6: u3, - /// controller capable. - BCR6: u1, - padding: u25, - }), - /// I3C device characteristics register. - DCR: mmio.Mmio(packed struct(u32) { - /// device characteristics ID others: ID to describe the type of the I3C sensor/device Note: The latest MIPI DCR ID assignments are available at: https://www.mipi.org/MIPI_I3C_device_characteristics_register. - DCR: u8, - padding: u24, - }), - /// I3C get capability register. - GETCAPR: mmio.Mmio(packed struct(u32) { - reserved14: u14, - /// IBI MDB support for pending read notification This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates the support (or not) of the pending read notification via the IBI MDB[7:0] value. This bit is used to return the GETCAP3 byte in response to the GETCAPS CCC format 1. - CAPPEND: u1, - padding: u17, - }), - /// I3C controller-role capability register. - CRCAPR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// delayed controller-role hand-off This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates if this target I3C may need additional time to process a controller-role hand-off requested by the current controller. This bit is used to return the CRCAP2 byte in response to the GETCAPS CCC format 2. - CAPDHOFF: u1, - reserved9: u5, - /// group management support (when acting as controller) This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates if the I3C is able to support group management when it acts as a controller (after controller-role hand-off) via emitted DEFGRPA, RSTGRPA, and SETGRPA CCC. This bit is used to return the CRCAP1 byte in response to the GETCAPS CCC format 2. - CAPGRP: u1, - padding: u22, - }), - /// I3C get capability register. - GETMXDSR: mmio.Mmio(packed struct(u32) { - /// controller hand-off activity state This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates in which initial activity state the (other) current controller should expect the I3C bus after a controller-role hand-off to this controller-capable I3C, when returning the defining byte CRHDLY (0x91) to a GETMXDS CCC. This 2-bit field is used to return the CRHDLY1 byte in response to the GETCAPS CCC format 3, in order to state which is the activity state of this I3C when becoming controller after a controller-role hand-off, and consequently the time the former controller should wait before testing this I3C to be confirmed its ownership. - HOFFAS: u2, - reserved8: u6, - /// GETMXDS CCC format. - FMT: u2, - reserved16: u6, - /// programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte) This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and writes the value of the selected byte (via the FMT[1:0] field) of the 3-byte MaxRdTurn which is returned in response to the GETMXDS CCC format 2 to encode the maximum read turnaround time. - RDTURN: u8, - /// clock-to-data turnaround time (tSCO) This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and is used to specify the clock-to-data turnaround time tSCO (vs the value of 12 ns). This bit is used by the hardware in response to the GETMXDS CCC to return the encoded clock-to-data turnaround time via the returned MaxRd[5:3] bits. - TSCO: u1, - padding: u7, - }), - /// I3C extended provisioned ID register. - EPIDR: mmio.Mmio(packed struct(u32) { - reserved12: u12, - /// 4-bit MIPI Instance ID This field is written by software to set and identify individually each instance of this I3C IP with a specific number on a single I3C bus. This field represents the bits[15:12] of the 48-bit provisioned ID. Note: The bits[11:0] of the provisioned ID may be 0. - MIPIID: u4, - /// provisioned ID type selector This field is set as 0 i.e. vendor fixed value. This field represents the bit[32] of the 48-bit provisioned ID. Note: The bits[31:16] of the provisioned ID may be 0. - IDTSEL: u1, - /// 15-bit MIPI manufacturer ID This read field is the 15-bit STMicroelectronics MIPI ID i.e. 0x0104. This field represents the bits[47:33] of the 48-bit provisioned ID. - MIPIMID: u15, - }), - }; - }; - - pub const icache_v1_3crr = struct { - pub const HBURST = enum(u1) { - Wrap = 0x0, - Increment = 0x1, - }; - - pub const MSTSEL = enum(u1) { - Master1Selected = 0x0, - Master2Selected = 0x1, - }; - - pub const RSIZE = enum(u3) { - MegaBytes2 = 0x1, - MegaBytes4 = 0x2, - MegaBytes8 = 0x3, - MegaBytes16 = 0x4, - MegaBytes32 = 0x5, - MegaBytes64 = 0x6, - MegaBytes128 = 0x7, - _, - }; - - pub const WAYSEL = enum(u1) { - /// direct mapped cache (1-way cache) - DirectMapped = 0x0, - /// n-way set associative cache (reset value) - NWaySetAssociative = 0x1, - }; - - /// Instruction Cache Control Registers. - pub const ICACHE = extern struct { - /// ICACHE control register. - CR: mmio.Mmio(packed struct(u32) { - /// EN. - EN: u1, - /// Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. - CACHEINV: u1, - /// This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). - WAYSEL: packed union { - raw: u1, - value: WAYSEL, - }, - reserved16: u13, - /// Hit monitor enable. - HITMEN: u1, - /// Miss monitor enable. - MISSMEN: u1, - /// Hit monitor reset. - HITMRST: u1, - /// Miss monitor reset. - MISSMRST: u1, - padding: u12, - }), - /// ICACHE status register. - SR: mmio.Mmio(packed struct(u32) { - /// cache busy executing a full invalidate CACHEINV operation. - BUSYF: u1, - /// full invalidate CACHEINV operation finished. - BSYENDF: u1, - /// an error occurred during the operation. - ERRF: u1, - padding: u29, - }), - /// ICACHE interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Interrupt enable on busy end. - BSYENDIE: u1, - /// Error interrupt on cache error. - ERRIE: u1, - padding: u29, - }), - /// ICACHE flag clear register. - FCR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clear busy end flag. - CBSYENDF: u1, - /// Clear ERRF flag in SR. - CERRF: u1, - padding: u29, - }), - /// ICACHE hit monitor register. - HMONR: u32, - /// ICACHE miss monitor register. - MMONR: mmio.Mmio(packed struct(u32) { - /// Miss monitor register. - MISSMON: u16, - padding: u16, - }), - reserved32: [8]u8, - /// Cluster CRR%s, container region configuration registers. - CRR: [3]mmio.Mmio(packed struct(u32) { - /// base address for region. - BASEADDR: u8, - reserved9: u1, - /// size for region. - RSIZE: packed union { - raw: u3, - value: RSIZE, - }, - reserved15: u3, - /// enable for region. - REN: u1, - /// remapped address for region. - REMAPADDR: u11, - reserved28: u1, - /// AHB cache master selection for region. - MSTSEL: packed union { - raw: u1, - value: MSTSEL, - }, - reserved31: u2, - /// output burst type for region. - HBURST: packed union { - raw: u1, - value: HBURST, - }, - }), - }; - }; - - pub const octospim_v1 = struct { - /// OctoSPI IO Manager - pub const OCTOSPIM = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// Multiplexed mode enable - MUXEN: u1, - reserved16: u15, - /// REQ to ACK time - REQ2ACK_TIME: u8, - padding: u8, - }), - /// OctoSPI IO Manager Port 1 Configuration Register - P1CR: mmio.Mmio(packed struct(u32) { - /// CLK/CLK Enable for Port - CLKEN: u1, - /// CLK/CLK Source for Port - CLKSRC: u1, - reserved4: u2, - /// DQS Enable for Port - DQSEN: u1, - /// DQS Source for Port - DQSSRC: u1, - reserved8: u2, - /// CS Enable for Port - NCSEN: u1, - /// CS Source for Port - NCSSRC: u1, - reserved16: u6, - /// Enable for Port - IOLEN: u1, - /// Source for Port - IOLSRC: u2, - reserved24: u5, - /// Enable for Port n - IOHEN: u1, - /// Source for Port - IOHSRC: u2, - padding: u5, - }), - /// OctoSPI IO Manager Port 2 Configuration Register - P2CR: mmio.Mmio(packed struct(u32) { - /// CLK/CLK Enable for Port - CLKEN: u1, - /// CLK/CLK Source for Port - CLKSRC: u1, - reserved4: u2, - /// DQS Enable for Port - DQSEN: u1, - /// DQS Source for Port - DQSSRC: u1, - reserved8: u2, - /// CS Enable for Port - NCSEN: u1, - /// CS Source for Port - NCSSRC: u1, - reserved16: u6, - /// Enable for Port - IOLEN: u1, - /// Source for Port - IOLSRC: u2, - reserved24: u5, - /// Enable for Port n - IOHEN: u1, - /// Source for Port - IOHSRC: u2, - padding: u5, - }), - }; - }; - - pub const syscfg_f3 = struct { - pub const ADC12_EXT13_RMP = enum(u1) { - /// Trigger source is TIM6_TRGO - Tim6 = 0x0, - /// Trigger source is TIM20_CC2 - Tim20 = 0x1, - }; - - pub const ADC12_EXT15_RMP = enum(u1) { - /// Trigger source is TIM3_CC4 - Tim3 = 0x0, - /// Trigger source is TIM20_CC3 - Tim20 = 0x1, - }; - - pub const ADC12_EXT2_RMP = enum(u1) { - /// Trigger source is TIM3_CC3 - Tim1 = 0x0, - /// rigger source is TIM20_TRGO - Tim20 = 0x1, - }; - - pub const ADC12_EXT3_RMP = enum(u1) { - /// Trigger source is TIM2_CC2 - Tim2 = 0x0, - /// rigger source is TIM20_TRGO2 - Tim20 = 0x1, - }; - - pub const ADC12_EXT5_RMP = enum(u1) { - /// Trigger source is TIM4_CC4 - Tim4 = 0x0, - /// Trigger source is TIM20_CC1 - Tim20 = 0x1, - }; - - pub const ADC12_JEXT13_RMP = enum(u1) { - /// Trigger source is TIM3_CC1 - Tim3 = 0x0, - /// Trigger source is TIM20_CC4 - Tim20 = 0x1, + pub const LSCOSEL = enum(u1) { + /// LSI clock selected + LSI = 0x0, + /// LSE clock selected + LSE = 0x1, }; - pub const ADC12_JEXT3_RMP = enum(u1) { - /// Trigger source is TIM2_CC1 - Tim2 = 0x0, - /// Trigger source is TIM20_TRGO - Tim20 = 0x1, + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, }; - pub const ADC12_JEXT6_RMP = enum(u1) { - /// Trigger source is EXTI line 15 - Exti15 = 0x0, - /// Trigger source is TIM20_TRGO2 - Tim20 = 0x1, + pub const LSEEXT = enum(u1) { + /// LSE in analog mode (default after Backup domain reset) + Analog = 0x0, + /// LSE in digital mode (do not use if RTC is active). + Digital = 0x1, }; - pub const ADC2_DMA_RMP_CFGR3 = enum(u2) { - /// ADC2 mapped on DMA1 channel 2 - MapDma1Ch2 = 0x2, - /// ADC2 mapped on DMA1 channel 4 - MapDma1Ch4 = 0x3, + pub const MCO1SEL = enum(u3) { + /// HSI selected for micro-controller clock output + HSI = 0x0, + /// LSE selected for micro-controller clock output + LSE = 0x1, + /// HSE selected for micro-controller clock output + HSE = 0x2, + /// pll1_q selected for micro-controller clock output + PLL1_Q = 0x3, + /// HSI48 selected for micro-controller clock output + HSI48 = 0x4, _, }; - pub const ADC34_EXT15_RMP = enum(u1) { - /// Trigger source is TIM2_CC1 - Tim2 = 0x0, - /// Trigger source is TIM20_CC1 - Tim20 = 0x1, - }; - - pub const ADC34_EXT5_RMP = enum(u1) { - /// Trigger source is EXTI line 2 when reset at 0 - Exti2 = 0x0, - /// Trigger source is TIM20_TRGO - Tim20 = 0x1, - }; - - pub const ADC34_EXT6_RMP = enum(u1) { - /// Trigger source is TIM4_CC1 - Tim4 = 0x0, - /// Trigger source is TIM20_TRGO2 - Tim20 = 0x1, - }; - - pub const ADC34_JEXT11_RMP = enum(u1) { - /// Trigger source is TIM1_CC3 - Tim1 = 0x0, - /// Trigger source is TIM20_TRGO2 - Tim20 = 0x1, - }; - - pub const ADC34_JEXT14_RMP = enum(u1) { - /// Trigger source is TIM7_TRGO - Tim7 = 0x0, - /// Trigger source is TIM20_CC2 - Tim20 = 0x1, - }; - - pub const ADC34_JEXT5_RMP = enum(u1) { - /// Trigger source is TIM4_CC3 - Tim4 = 0x0, - /// Trigger source is TIM20_TRGO - Tim20 = 0x1, - }; - - pub const DAC1_TRIG3_RMP = enum(u1) { - /// DAC trigger is TIM15_TRGO - Tim15 = 0x0, - /// DAC trigger is HRTIM1_DAC1_TRIG1 - HrTim1 = 0x1, - }; - - pub const ENCODER_MODE = enum(u2) { - /// No redirection - NoRedirection = 0x0, - /// TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively - MapTim2Tim15 = 0x1, - /// TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively - MapTim3Tim15 = 0x2, + pub const MCO2SEL = enum(u3) { + /// System clock selected for micro-controller clock output + SYS = 0x0, + /// pll2_p selected for micro-controller clock output + PLL2_P = 0x1, + /// HSE selected for micro-controller clock output + HSE = 0x2, + /// pll1_p selected for micro-controller clock output + PLL1_P = 0x3, + /// CSI selected for micro-controller clock output + CSI = 0x4, + /// LSI selected for micro-controller clock output + LSI = 0x5, _, }; - pub const FMP = enum(u1) { - /// Standard - Standard = 0x0, - /// FM+ - FMP = 0x1, - }; - - pub const I2C1_RX_DMA_RMP = enum(u2) { - /// I2C1_RX mapped on DMA1 CH7 - MapDma1Ch7 = 0x0, - /// I2C1_RX mapped on DMA1 CH3 - MapDma1Ch3 = 0x1, - /// I2C1_RX mapped on DMA1 CH5 - MapDma1Ch5 = 0x2, + pub const MCOPRE = enum(u4) { + /// Divide by 1 + Div1 = 0x1, + /// Divide by 2 + Div2 = 0x2, + /// Divide by 3 + Div3 = 0x3, + /// Divide by 4 + Div4 = 0x4, + /// Divide by 5 + Div5 = 0x5, + /// Divide by 6 + Div6 = 0x6, + /// Divide by 7 + Div7 = 0x7, + /// Divide by 8 + Div8 = 0x8, + /// Divide by 9 + Div9 = 0x9, + /// Divide by 10 + Div10 = 0xa, + /// Divide by 11 + Div11 = 0xb, + /// Divide by 12 + Div12 = 0xc, + /// Divide by 13 + Div13 = 0xd, + /// Divide by 14 + Div14 = 0xe, + /// Divide by 15 + Div15 = 0xf, _, }; - pub const I2C1_TX_DMA_RMP = enum(u2) { - /// I2C1_TX mapped on DMA1 CH6 - MapDma1Ch6 = 0x0, - /// I2C1_TX mapped on DMA1 CH2 - MapDma1Ch2 = 0x1, - /// I2C1_TX mapped on DMA1 CH4 - MapDma1Ch4 = 0x2, + pub const PERSEL = enum(u2) { + /// hsi_ker_ck selected as kernel clock (default after reset) + HSI = 0x0, + /// csi_ker_ck selected as kernel clock + CSI = 0x1, + /// hse_ck selected as kernel clock + HSE = 0x2, _, }; - pub const MEM_MODE = enum(u2) { - /// Main Flash memory mapped at 0x0000_0000 - MainFlash = 0x0, - /// System Flash memory mapped at 0x0000_0000 - SystemFlash = 0x1, - /// Main Flash memory mapped at 0x0000_0000 - MainFlash2 = 0x2, - /// Embedded SRAM mapped at 0x0000_0000 - SRAM = 0x3, - }; - - pub const SPI1_RX_DMA_RMP = enum(u2) { - /// SPI1_RX mapped on DMA1 CH2 - MapDma1Ch3 = 0x0, - /// SPI1_RX mapped on DMA1 CH4 - MapDma1Ch5 = 0x1, - /// SPI1_RX mapped on DMA1 CH6 - MapDma1Ch7 = 0x2, - _, + pub const PLLDIV = enum(u7) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + Div17 = 0x10, + Div18 = 0x11, + Div19 = 0x12, + Div20 = 0x13, + Div21 = 0x14, + Div22 = 0x15, + Div23 = 0x16, + Div24 = 0x17, + Div25 = 0x18, + Div26 = 0x19, + Div27 = 0x1a, + Div28 = 0x1b, + Div29 = 0x1c, + Div30 = 0x1d, + Div31 = 0x1e, + Div32 = 0x1f, + Div33 = 0x20, + Div34 = 0x21, + Div35 = 0x22, + Div36 = 0x23, + Div37 = 0x24, + Div38 = 0x25, + Div39 = 0x26, + Div40 = 0x27, + Div41 = 0x28, + Div42 = 0x29, + Div43 = 0x2a, + Div44 = 0x2b, + Div45 = 0x2c, + Div46 = 0x2d, + Div47 = 0x2e, + Div48 = 0x2f, + Div49 = 0x30, + Div50 = 0x31, + Div51 = 0x32, + Div52 = 0x33, + Div53 = 0x34, + Div54 = 0x35, + Div55 = 0x36, + Div56 = 0x37, + Div57 = 0x38, + Div58 = 0x39, + Div59 = 0x3a, + Div60 = 0x3b, + Div61 = 0x3c, + Div62 = 0x3d, + Div63 = 0x3e, + Div64 = 0x3f, + Div65 = 0x40, + Div66 = 0x41, + Div67 = 0x42, + Div68 = 0x43, + Div69 = 0x44, + Div70 = 0x45, + Div71 = 0x46, + Div72 = 0x47, + Div73 = 0x48, + Div74 = 0x49, + Div75 = 0x4a, + Div76 = 0x4b, + Div77 = 0x4c, + Div78 = 0x4d, + Div79 = 0x4e, + Div80 = 0x4f, + Div81 = 0x50, + Div82 = 0x51, + Div83 = 0x52, + Div84 = 0x53, + Div85 = 0x54, + Div86 = 0x55, + Div87 = 0x56, + Div88 = 0x57, + Div89 = 0x58, + Div90 = 0x59, + Div91 = 0x5a, + Div92 = 0x5b, + Div93 = 0x5c, + Div94 = 0x5d, + Div95 = 0x5e, + Div96 = 0x5f, + Div97 = 0x60, + Div98 = 0x61, + Div99 = 0x62, + Div100 = 0x63, + Div101 = 0x64, + Div102 = 0x65, + Div103 = 0x66, + Div104 = 0x67, + Div105 = 0x68, + Div106 = 0x69, + Div107 = 0x6a, + Div108 = 0x6b, + Div109 = 0x6c, + Div110 = 0x6d, + Div111 = 0x6e, + Div112 = 0x6f, + Div113 = 0x70, + Div114 = 0x71, + Div115 = 0x72, + Div116 = 0x73, + Div117 = 0x74, + Div118 = 0x75, + Div119 = 0x76, + Div120 = 0x77, + Div121 = 0x78, + Div122 = 0x79, + Div123 = 0x7a, + Div124 = 0x7b, + Div125 = 0x7c, + Div126 = 0x7d, + Div127 = 0x7e, + Div128 = 0x7f, }; - pub const SPI1_TX_DMA_RMP = enum(u2) { - /// SPI1_TX mapped on DMA1 CH3 - MapDma1Ch3 = 0x0, - /// SPI1_TX mapped on DMA1 CH5 - MapDma1Ch5 = 0x1, - /// SPI1_TX mapped on DMA1 CH7 - MapDma1Ch7 = 0x2, + pub const PLLM = enum(u6) { + Div1 = 0x1, + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + Div16 = 0x10, + Div17 = 0x11, + Div18 = 0x12, + Div19 = 0x13, + Div20 = 0x14, + Div21 = 0x15, + Div22 = 0x16, + Div23 = 0x17, + Div24 = 0x18, + Div25 = 0x19, + Div26 = 0x1a, + Div27 = 0x1b, + Div28 = 0x1c, + Div29 = 0x1d, + Div30 = 0x1e, + Div31 = 0x1f, + Div32 = 0x20, + Div33 = 0x21, + Div34 = 0x22, + Div35 = 0x23, + Div36 = 0x24, + Div37 = 0x25, + Div38 = 0x26, + Div39 = 0x27, + Div40 = 0x28, + Div41 = 0x29, + Div42 = 0x2a, + Div43 = 0x2b, + Div44 = 0x2c, + Div45 = 0x2d, + Div46 = 0x2e, + Div47 = 0x2f, + Div48 = 0x30, + Div49 = 0x31, + Div50 = 0x32, + Div51 = 0x33, + Div52 = 0x34, + Div53 = 0x35, + Div54 = 0x36, + Div55 = 0x37, + Div56 = 0x38, + Div57 = 0x39, + Div58 = 0x3a, + Div59 = 0x3b, + Div60 = 0x3c, + Div61 = 0x3d, + Div62 = 0x3e, _, }; - /// System configuration controller - pub const SYSCFG = extern struct { - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection bits - MEM_MODE: packed union { - raw: u2, - value: MEM_MODE, - }, - reserved5: u3, - /// USB interrupt remap 0: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively 1: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively - USB_IT_RMP: u1, - /// Timer 1 ITR3 selection 0: Not remapped 1: TIM1_ITR3 = TIM17_OC - TIM1_ITR3_RMP: u1, - /// DAC trigger remap (when TSEL = 001) 0: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices 1: DAC trigger is TIM3_TRGO - DAC1_TRIG_RMP: u1, - /// ADC24 DMA remapping bit 0: ADC24 DMA requests mapped on DMA2 channels 1 and 2 1: ADC24 DMA requests mapped on DMA2 channels 3 and 4 - ADC2_DMA_RMP: u1, - reserved11: u2, - /// TIM16 DMA request remapping bit 0: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 1: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 - TIM16_DMA_RMP: u1, - /// TIM17 DMA request remapping bit 0: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 1: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 - TIM17_DMA_RMP: u1, - /// TIM6 and DAC1 DMA request remapping bit 0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 - TIM6_DAC1_CH1_DMA_RMP: u1, - /// TIM7 and DAC2 DMA request remapping bit 0: Not remapped 1: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4 - TIM7_DAC1_CH2_DMA_RMP: u1, - /// DAC2 channel1 DMA remap 0: Not remapped 1: DAC2_CH1 DMA requests mapped on DMA1 channel 5 - DAC2_CH1_DMA_RMP: u1, - /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB6 pin operate in standard mode 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed - I2C_PB6_FMP: packed union { - raw: u1, - value: FMP, - }, - /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB7 pin operate in standard mode 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed - I2C_PB7_FMP: packed union { - raw: u1, - value: FMP, - }, - /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB8 pin operate in standard mode 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed - I2C_PB8_FMP: packed union { - raw: u1, - value: FMP, - }, - /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB9 pin operate in standard mode 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed - I2C_PB9_FMP: packed union { - raw: u1, - value: FMP, - }, - /// I2C1 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits - I2C1_FMP: packed union { - raw: u1, - value: FMP, - }, - /// I2C2 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits - I2C2_FMP: packed union { - raw: u1, - value: FMP, - }, - /// Encoder mode - ENCODER_MODE: packed union { + pub const PLLN = enum(u9) { + Mul4 = 0x3, + Mul5 = 0x4, + Mul6 = 0x5, + Mul7 = 0x6, + Mul8 = 0x7, + Mul9 = 0x8, + Mul10 = 0x9, + Mul11 = 0xa, + Mul12 = 0xb, + Mul13 = 0xc, + Mul14 = 0xd, + Mul15 = 0xe, + Mul16 = 0xf, + Mul17 = 0x10, + Mul18 = 0x11, + Mul19 = 0x12, + Mul20 = 0x13, + Mul21 = 0x14, + Mul22 = 0x15, + Mul23 = 0x16, + Mul24 = 0x17, + Mul25 = 0x18, + Mul26 = 0x19, + Mul27 = 0x1a, + Mul28 = 0x1b, + Mul29 = 0x1c, + Mul30 = 0x1d, + Mul31 = 0x1e, + Mul32 = 0x1f, + Mul33 = 0x20, + Mul34 = 0x21, + Mul35 = 0x22, + Mul36 = 0x23, + Mul37 = 0x24, + Mul38 = 0x25, + Mul39 = 0x26, + Mul40 = 0x27, + Mul41 = 0x28, + Mul42 = 0x29, + Mul43 = 0x2a, + Mul44 = 0x2b, + Mul45 = 0x2c, + Mul46 = 0x2d, + Mul47 = 0x2e, + Mul48 = 0x2f, + Mul49 = 0x30, + Mul50 = 0x31, + Mul51 = 0x32, + Mul52 = 0x33, + Mul53 = 0x34, + Mul54 = 0x35, + Mul55 = 0x36, + Mul56 = 0x37, + Mul57 = 0x38, + Mul58 = 0x39, + Mul59 = 0x3a, + Mul60 = 0x3b, + Mul61 = 0x3c, + Mul62 = 0x3d, + Mul63 = 0x3e, + Mul64 = 0x3f, + Mul65 = 0x40, + Mul66 = 0x41, + Mul67 = 0x42, + Mul68 = 0x43, + Mul69 = 0x44, + Mul70 = 0x45, + Mul71 = 0x46, + Mul72 = 0x47, + Mul73 = 0x48, + Mul74 = 0x49, + Mul75 = 0x4a, + Mul76 = 0x4b, + Mul77 = 0x4c, + Mul78 = 0x4d, + Mul79 = 0x4e, + Mul80 = 0x4f, + Mul81 = 0x50, + Mul82 = 0x51, + Mul83 = 0x52, + Mul84 = 0x53, + Mul85 = 0x54, + Mul86 = 0x55, + Mul87 = 0x56, + Mul88 = 0x57, + Mul89 = 0x58, + Mul90 = 0x59, + Mul91 = 0x5a, + Mul92 = 0x5b, + Mul93 = 0x5c, + Mul94 = 0x5d, + Mul95 = 0x5e, + Mul96 = 0x5f, + Mul97 = 0x60, + Mul98 = 0x61, + Mul99 = 0x62, + Mul100 = 0x63, + Mul101 = 0x64, + Mul102 = 0x65, + Mul103 = 0x66, + Mul104 = 0x67, + Mul105 = 0x68, + Mul106 = 0x69, + Mul107 = 0x6a, + Mul108 = 0x6b, + Mul109 = 0x6c, + Mul110 = 0x6d, + Mul111 = 0x6e, + Mul112 = 0x6f, + Mul113 = 0x70, + Mul114 = 0x71, + Mul115 = 0x72, + Mul116 = 0x73, + Mul117 = 0x74, + Mul118 = 0x75, + Mul119 = 0x76, + Mul120 = 0x77, + Mul121 = 0x78, + Mul122 = 0x79, + Mul123 = 0x7a, + Mul124 = 0x7b, + Mul125 = 0x7c, + Mul126 = 0x7d, + Mul127 = 0x7e, + Mul128 = 0x7f, + Mul129 = 0x80, + Mul130 = 0x81, + Mul131 = 0x82, + Mul132 = 0x83, + Mul133 = 0x84, + Mul134 = 0x85, + Mul135 = 0x86, + Mul136 = 0x87, + Mul137 = 0x88, + Mul138 = 0x89, + Mul139 = 0x8a, + Mul140 = 0x8b, + Mul141 = 0x8c, + Mul142 = 0x8d, + Mul143 = 0x8e, + Mul144 = 0x8f, + Mul145 = 0x90, + Mul146 = 0x91, + Mul147 = 0x92, + Mul148 = 0x93, + Mul149 = 0x94, + Mul150 = 0x95, + Mul151 = 0x96, + Mul152 = 0x97, + Mul153 = 0x98, + Mul154 = 0x99, + Mul155 = 0x9a, + Mul156 = 0x9b, + Mul157 = 0x9c, + Mul158 = 0x9d, + Mul159 = 0x9e, + Mul160 = 0x9f, + Mul161 = 0xa0, + Mul162 = 0xa1, + Mul163 = 0xa2, + Mul164 = 0xa3, + Mul165 = 0xa4, + Mul166 = 0xa5, + Mul167 = 0xa6, + Mul168 = 0xa7, + Mul169 = 0xa8, + Mul170 = 0xa9, + Mul171 = 0xaa, + Mul172 = 0xab, + Mul173 = 0xac, + Mul174 = 0xad, + Mul175 = 0xae, + Mul176 = 0xaf, + Mul177 = 0xb0, + Mul178 = 0xb1, + Mul179 = 0xb2, + Mul180 = 0xb3, + Mul181 = 0xb4, + Mul182 = 0xb5, + Mul183 = 0xb6, + Mul184 = 0xb7, + Mul185 = 0xb8, + Mul186 = 0xb9, + Mul187 = 0xba, + Mul188 = 0xbb, + Mul189 = 0xbc, + Mul190 = 0xbd, + Mul191 = 0xbe, + Mul192 = 0xbf, + Mul193 = 0xc0, + Mul194 = 0xc1, + Mul195 = 0xc2, + Mul196 = 0xc3, + Mul197 = 0xc4, + Mul198 = 0xc5, + Mul199 = 0xc6, + Mul200 = 0xc7, + Mul201 = 0xc8, + Mul202 = 0xc9, + Mul203 = 0xca, + Mul204 = 0xcb, + Mul205 = 0xcc, + Mul206 = 0xcd, + Mul207 = 0xce, + Mul208 = 0xcf, + Mul209 = 0xd0, + Mul210 = 0xd1, + Mul211 = 0xd2, + Mul212 = 0xd3, + Mul213 = 0xd4, + Mul214 = 0xd5, + Mul215 = 0xd6, + Mul216 = 0xd7, + Mul217 = 0xd8, + Mul218 = 0xd9, + Mul219 = 0xda, + Mul220 = 0xdb, + Mul221 = 0xdc, + Mul222 = 0xdd, + Mul223 = 0xde, + Mul224 = 0xdf, + Mul225 = 0xe0, + Mul226 = 0xe1, + Mul227 = 0xe2, + Mul228 = 0xe3, + Mul229 = 0xe4, + Mul230 = 0xe5, + Mul231 = 0xe6, + Mul232 = 0xe7, + Mul233 = 0xe8, + Mul234 = 0xe9, + Mul235 = 0xea, + Mul236 = 0xeb, + Mul237 = 0xec, + Mul238 = 0xed, + Mul239 = 0xee, + Mul240 = 0xef, + Mul241 = 0xf0, + Mul242 = 0xf1, + Mul243 = 0xf2, + Mul244 = 0xf3, + Mul245 = 0xf4, + Mul246 = 0xf5, + Mul247 = 0xf6, + Mul248 = 0xf7, + Mul249 = 0xf8, + Mul250 = 0xf9, + Mul251 = 0xfa, + Mul252 = 0xfb, + Mul253 = 0xfc, + Mul254 = 0xfd, + Mul255 = 0xfe, + Mul256 = 0xff, + Mul257 = 0x100, + Mul258 = 0x101, + Mul259 = 0x102, + Mul260 = 0x103, + Mul261 = 0x104, + Mul262 = 0x105, + Mul263 = 0x106, + Mul264 = 0x107, + Mul265 = 0x108, + Mul266 = 0x109, + Mul267 = 0x10a, + Mul268 = 0x10b, + Mul269 = 0x10c, + Mul270 = 0x10d, + Mul271 = 0x10e, + Mul272 = 0x10f, + Mul273 = 0x110, + Mul274 = 0x111, + Mul275 = 0x112, + Mul276 = 0x113, + Mul277 = 0x114, + Mul278 = 0x115, + Mul279 = 0x116, + Mul280 = 0x117, + Mul281 = 0x118, + Mul282 = 0x119, + Mul283 = 0x11a, + Mul284 = 0x11b, + Mul285 = 0x11c, + Mul286 = 0x11d, + Mul287 = 0x11e, + Mul288 = 0x11f, + Mul289 = 0x120, + Mul290 = 0x121, + Mul291 = 0x122, + Mul292 = 0x123, + Mul293 = 0x124, + Mul294 = 0x125, + Mul295 = 0x126, + Mul296 = 0x127, + Mul297 = 0x128, + Mul298 = 0x129, + Mul299 = 0x12a, + Mul300 = 0x12b, + Mul301 = 0x12c, + Mul302 = 0x12d, + Mul303 = 0x12e, + Mul304 = 0x12f, + Mul305 = 0x130, + Mul306 = 0x131, + Mul307 = 0x132, + Mul308 = 0x133, + Mul309 = 0x134, + Mul310 = 0x135, + Mul311 = 0x136, + Mul312 = 0x137, + Mul313 = 0x138, + Mul314 = 0x139, + Mul315 = 0x13a, + Mul316 = 0x13b, + Mul317 = 0x13c, + Mul318 = 0x13d, + Mul319 = 0x13e, + Mul320 = 0x13f, + Mul321 = 0x140, + Mul322 = 0x141, + Mul323 = 0x142, + Mul324 = 0x143, + Mul325 = 0x144, + Mul326 = 0x145, + Mul327 = 0x146, + Mul328 = 0x147, + Mul329 = 0x148, + Mul330 = 0x149, + Mul331 = 0x14a, + Mul332 = 0x14b, + Mul333 = 0x14c, + Mul334 = 0x14d, + Mul335 = 0x14e, + Mul336 = 0x14f, + Mul337 = 0x150, + Mul338 = 0x151, + Mul339 = 0x152, + Mul340 = 0x153, + Mul341 = 0x154, + Mul342 = 0x155, + Mul343 = 0x156, + Mul344 = 0x157, + Mul345 = 0x158, + Mul346 = 0x159, + Mul347 = 0x15a, + Mul348 = 0x15b, + Mul349 = 0x15c, + Mul350 = 0x15d, + Mul351 = 0x15e, + Mul352 = 0x15f, + Mul353 = 0x160, + Mul354 = 0x161, + Mul355 = 0x162, + Mul356 = 0x163, + Mul357 = 0x164, + Mul358 = 0x165, + Mul359 = 0x166, + Mul360 = 0x167, + Mul361 = 0x168, + Mul362 = 0x169, + Mul363 = 0x16a, + Mul364 = 0x16b, + Mul365 = 0x16c, + Mul366 = 0x16d, + Mul367 = 0x16e, + Mul368 = 0x16f, + Mul369 = 0x170, + Mul370 = 0x171, + Mul371 = 0x172, + Mul372 = 0x173, + Mul373 = 0x174, + Mul374 = 0x175, + Mul375 = 0x176, + Mul376 = 0x177, + Mul377 = 0x178, + Mul378 = 0x179, + Mul379 = 0x17a, + Mul380 = 0x17b, + Mul381 = 0x17c, + Mul382 = 0x17d, + Mul383 = 0x17e, + Mul384 = 0x17f, + Mul385 = 0x180, + Mul386 = 0x181, + Mul387 = 0x182, + Mul388 = 0x183, + Mul389 = 0x184, + Mul390 = 0x185, + Mul391 = 0x186, + Mul392 = 0x187, + Mul393 = 0x188, + Mul394 = 0x189, + Mul395 = 0x18a, + Mul396 = 0x18b, + Mul397 = 0x18c, + Mul398 = 0x18d, + Mul399 = 0x18e, + Mul400 = 0x18f, + Mul401 = 0x190, + Mul402 = 0x191, + Mul403 = 0x192, + Mul404 = 0x193, + Mul405 = 0x194, + Mul406 = 0x195, + Mul407 = 0x196, + Mul408 = 0x197, + Mul409 = 0x198, + Mul410 = 0x199, + Mul411 = 0x19a, + Mul412 = 0x19b, + Mul413 = 0x19c, + Mul414 = 0x19d, + Mul415 = 0x19e, + Mul416 = 0x19f, + Mul417 = 0x1a0, + Mul418 = 0x1a1, + Mul419 = 0x1a2, + Mul420 = 0x1a3, + Mul421 = 0x1a4, + Mul422 = 0x1a5, + Mul423 = 0x1a6, + Mul424 = 0x1a7, + Mul425 = 0x1a8, + Mul426 = 0x1a9, + Mul427 = 0x1aa, + Mul428 = 0x1ab, + Mul429 = 0x1ac, + Mul430 = 0x1ad, + Mul431 = 0x1ae, + Mul432 = 0x1af, + Mul433 = 0x1b0, + Mul434 = 0x1b1, + Mul435 = 0x1b2, + Mul436 = 0x1b3, + Mul437 = 0x1b4, + Mul438 = 0x1b5, + Mul439 = 0x1b6, + Mul440 = 0x1b7, + Mul441 = 0x1b8, + Mul442 = 0x1b9, + Mul443 = 0x1ba, + Mul444 = 0x1bb, + Mul445 = 0x1bc, + Mul446 = 0x1bd, + Mul447 = 0x1be, + Mul448 = 0x1bf, + Mul449 = 0x1c0, + Mul450 = 0x1c1, + Mul451 = 0x1c2, + Mul452 = 0x1c3, + Mul453 = 0x1c4, + Mul454 = 0x1c5, + Mul455 = 0x1c6, + Mul456 = 0x1c7, + Mul457 = 0x1c8, + Mul458 = 0x1c9, + Mul459 = 0x1ca, + Mul460 = 0x1cb, + Mul461 = 0x1cc, + Mul462 = 0x1cd, + Mul463 = 0x1ce, + Mul464 = 0x1cf, + Mul465 = 0x1d0, + Mul466 = 0x1d1, + Mul467 = 0x1d2, + Mul468 = 0x1d3, + Mul469 = 0x1d4, + Mul470 = 0x1d5, + Mul471 = 0x1d6, + Mul472 = 0x1d7, + Mul473 = 0x1d8, + Mul474 = 0x1d9, + Mul475 = 0x1da, + Mul476 = 0x1db, + Mul477 = 0x1dc, + Mul478 = 0x1dd, + Mul479 = 0x1de, + Mul480 = 0x1df, + Mul481 = 0x1e0, + Mul482 = 0x1e1, + Mul483 = 0x1e2, + Mul484 = 0x1e3, + Mul485 = 0x1e4, + Mul486 = 0x1e5, + Mul487 = 0x1e6, + Mul488 = 0x1e7, + Mul489 = 0x1e8, + Mul490 = 0x1e9, + Mul491 = 0x1ea, + Mul492 = 0x1eb, + Mul493 = 0x1ec, + Mul494 = 0x1ed, + Mul495 = 0x1ee, + Mul496 = 0x1ef, + Mul497 = 0x1f0, + Mul498 = 0x1f1, + Mul499 = 0x1f2, + Mul500 = 0x1f3, + Mul501 = 0x1f4, + Mul502 = 0x1f5, + Mul503 = 0x1f6, + Mul504 = 0x1f7, + Mul505 = 0x1f8, + Mul506 = 0x1f9, + Mul507 = 0x1fa, + Mul508 = 0x1fb, + Mul509 = 0x1fc, + Mul510 = 0x1fd, + Mul511 = 0x1fe, + Mul512 = 0x1ff, + _, + }; + + pub const PLLRGE = enum(u2) { + /// Frequency is between 1 and 2 MHz + Range1 = 0x0, + /// Frequency is between 2 and 4 MHz + Range2 = 0x1, + /// Frequency is between 4 and 8 MHz + Range4 = 0x2, + /// Frequency is between 8 and 16 MHz + Range8 = 0x3, + }; + + pub const PLLSRC = enum(u2) { + /// no clock send to DIVMx divider and PLLs (default after reset) + DISABLE = 0x0, + /// HSI selected as PLL clock (hsi_ck) + HSI = 0x1, + /// CSI selected as PLL clock (csi_ck) + CSI = 0x2, + /// HSE selected as PLL clock (hse_ck) + HSE = 0x3, + }; + + pub const PLLVCOSEL = enum(u1) { + /// VCO frequency range 192 to 836 MHz + WideVCO = 0x0, + /// VCO frequency range 150 to 420 MHz + MediumVCO = 0x1, + }; + + pub const PPRE = enum(u3) { + /// rcc_pclk3 = rcc_hclk1 / 1 + Div1 = 0x0, + /// rcc_pclk3 = rcc_hclk1 / 2 + Div2 = 0x4, + /// rcc_pclk3 = rcc_hclk1 / 4 + Div4 = 0x5, + /// rcc_pclk3 = rcc_hclk1 / 8 + Div8 = 0x6, + /// rcc_pclk3 = rcc_hclk1 / 16 + Div16 = 0x7, + _, + }; + + pub const RNGSEL = enum(u2) { + /// hsi48_ker_ck selected as kernel clock (default after reset) + HSI48 = 0x0, + /// pll1_q_ck selected as kernel clock + PLL1_Q = 0x1, + /// lse_ck selected as kernel clock + LSE = 0x2, + /// lsi_ker_ck selected as kernel clock + LSI = 0x3, + }; + + pub const RTCSEL = enum(u2) { + /// no clock (default after Backup domain reset) + DISABLE = 0x0, + /// LSE selected as RTC clock + LSE = 0x1, + /// LSI selected as RTC clock + LSI = 0x2, + /// HSE divided by RTCPRE value selected as RTC clock + HSE_DIV_RTCPRE = 0x3, + }; + + pub const SPISEL = enum(u3) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// hsi_ker selected as peripheral clock + AUDIOCLK = 0x3, + /// csi_ker selected as peripheral clock + PER = 0x4, + _, + }; + + pub const STOPKERWUCK = enum(u1) { + /// HSI selected as wakeup clock from system Stop (default after reset) + HSI = 0x0, + /// CSI selected as wakeup clock from system Stop + CSI = 0x1, + }; + + pub const STOPWUCK = enum(u1) { + /// CSI selected as wakeup clock from system Stop + CSI = 0x1, + _, + }; + + pub const SW = enum(u3) { + /// HSI selected as system clock + HSI = 0x0, + /// CSI selected as system clock + CSI = 0x1, + /// HSE selected as system clock + HSE = 0x2, + /// PLL1 selected as system clock + PLL1_P = 0x3, + _, + }; + + pub const SYSTICKSEL = enum(u2) { + /// rcc_hclk/8 selected as clock source (default after reset) + HCLK1_DIV_8 = 0x0, + /// lsi_ker_ck[1] selected as clock source + LSI = 0x1, + /// lse_ck[1] selected as clock source + LSE = 0x2, + _, + }; + + pub const TIMICSEL = enum(u1) { + /// No internal clock available for timers input capture (default after reset) + B_0x0 = 0x0, + /// hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture + B_0x1 = 0x1, + }; + + pub const TIMPRE = enum(u1) { + /// The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset) + DefaultX2 = 0x0, + /// The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2 + DefaultX4 = 0x1, + }; + + pub const USART1SEL = enum(u3) { + /// rcc_pclk2 selected as peripheral clock + PCLK2 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, + }; + + pub const USARTSEL = enum(u3) { + /// rcc_pclk2 selected as peripheral clock + PCLK1 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, + }; + + pub const USBSEL = enum(u2) { + /// Disable the kernel clock + DISABLE = 0x0, + /// pll1_q selected as peripheral clock + PLL1_Q = 0x1, + /// HSI48 selected as peripheral clock + HSI48 = 0x3, + _, + }; + + /// Reset and clock controller + pub const RCC = extern struct { + /// RCC clock control register + CR: mmio.Mmio(packed struct(u32) { + /// HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). + HSION: u1, + /// HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable. + HSIRDY: u1, + /// HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION. + HSIKERON: u1, + /// HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored. + HSIDIV: packed union { raw: u2, - value: ENCODER_MODE, + value: HSIDIV, }, - /// I2C3 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits - I2C3_FMP: packed union { + /// HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. + HSIDIVF: u1, + reserved8: u2, + /// CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). + CSION: u1, + /// CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request). + CSIRDY: u1, + /// CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION. + CSIKERON: u1, + reserved12: u1, + /// HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode. + HSI48ON: u1, + /// HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable. + HSI48RDY: u1, + reserved16: u2, + /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1). + HSEON: u1, + /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. + HSERDY: u1, + /// HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + HSEBYP: u1, + /// HSE clock security system enable Set by software to enable clock security system on HSE. This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected. + HSECSSON: u1, + /// external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled. + HSEEXT: packed union { raw: u1, - value: FMP, + value: HSEEXT, }, - reserved26: u1, - /// Idx 0: Invalid operation interrupt enable; Idx 1: Devide-by-zero interrupt enable; Idx 2: Underflow interrupt enable; Idx 3: Overflow interrupt enable; Idx 4: Input denormal interrupt enable; Idx 5: Inexact interrupt enable - FPU_IE: u1, - padding: u5, + reserved24: u3, + /// PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock. + PLLON: u1, + /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + PLLRDY: u1, + padding: u6, }), - /// CCM SRAM protection register - RCR: mmio.Mmio(packed struct(u32) { - /// CCM SRAM page x write protection enabled - PAGE_WP: u1, - padding: u31, + reserved16: [12]u8, + /// RCC HSI calibration register + HSICFGR: mmio.Mmio(packed struct(u32) { + /// HSI clock calibration Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value. + HSICAL: u12, + reserved16: u4, + /// HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_OPT. After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated Note: The reset value of the field is 0x40. + HSITRIM: u7, + padding: u9, }), - /// external interrupt configuration register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration - EXTI: u4, - padding: u28, + /// RCC clock recovery RC register + CRRCR: mmio.Mmio(packed struct(u32) { + /// Internal RC 48 MHz clock calibration Set by hardware by option-byte loading during system reset NRESET. Read-only. + HSI48CAL: u10, + padding: u22, }), - /// configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// Cortex-M0 LOCKUP bit enable bit - LOCKUP_LOCK: u1, - /// SRAM parity lock bit - SRAM_PARITY_LOCK: u1, - /// PVD lock enable bit - PVD_LOCK: u1, - reserved4: u1, - /// Bypass address bit 29 in parity calculation - BYP_ADDR_PAR: u1, - reserved8: u3, - /// SRAM parity flag - SRAM_PEF: u1, - padding: u23, + /// RCC CSI calibration register + CSICFGR: mmio.Mmio(packed struct(u32) { + /// CSI clock calibration Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value. + CSICAL: u8, + reserved16: u8, + /// CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_OPT. Note: The reset value of the field is 0x20. + CSITRIM: u6, + padding: u10, }), - reserved72: [44]u8, - /// configuration register 4 - CFGR4: mmio.Mmio(packed struct(u32) { - /// Controls the Input trigger of ADC12 regular channel EXT2 - ADC12_EXT2_RMP: packed union { - raw: u1, - value: ADC12_EXT2_RMP, - }, - /// Controls the Input trigger of ADC12 regular channel EXT3 - ADC12_EXT3_RMP: packed union { - raw: u1, - value: ADC12_EXT3_RMP, + /// RCC clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// system clock and trace clock switch Set and reset by software to select system clock and trace clock sources (sys_ck). Set by hardware in order to: - force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode - force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock others: reserved + SW: packed union { + raw: u3, + value: SW, }, - /// Controls the Input trigger of ADC12 regular channel EXT5 - ADC12_EXT5_RMP: packed union { - raw: u1, - value: ADC12_EXT5_RMP, + /// system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset). others: reserved + SWS: packed union { + raw: u3, + value: SW, }, - /// Controls the Input trigger of ADC12 regular channel EXT13 - ADC12_EXT13_RMP: packed union { + /// system clock selection after a wakeup from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset) STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10). + STOPWUCK: packed union { raw: u1, - value: ADC12_EXT13_RMP, + value: STOPWUCK, }, - /// Controls the Input trigger of ADC12 regular channel EXT15 - ADC12_EXT15_RMP: packed union { + /// kernel clock selection after a wakeup from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. + STOPKERWUCK: packed union { raw: u1, - value: ADC12_EXT15_RMP, + value: STOPKERWUCK, }, - /// Controls the Input trigger of ADC12 injected channel JEXT3 - ADC12_JEXT3_RMP: packed union { + /// HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ... + RTCPRE: u6, + reserved15: u1, + /// timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. + TIMPRE: packed union { raw: u1, - value: ADC12_JEXT3_RMP, + value: TIMPRE, }, - /// Controls the Input trigger of ADC12 injected channel JEXT6 - ADC12_JEXT6_RMP: packed union { - raw: u1, - value: ADC12_JEXT6_RMP, + reserved18: u2, + /// MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... + MCO1PRE: packed union { + raw: u4, + value: MCOPRE, }, - /// Controls the Input trigger of ADC12 injected channel JEXT13 - ADC12_JEXT13_RMP: packed union { - raw: u1, - value: ADC12_JEXT13_RMP, + /// Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved + MCO1SEL: packed union { + raw: u3, + value: MCO1SEL, }, - /// Controls the Input trigger of ADC34 regular channel EXT5 - ADC34_EXT5_RMP: packed union { - raw: u1, - value: ADC34_EXT5_RMP, + /// MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... + MCO2PRE: packed union { + raw: u4, + value: MCOPRE, }, - /// Controls the Input trigger of ADC34 regular channel EXT6 - ADC34_EXT6_RMP: packed union { - raw: u1, - value: ADC34_EXT6_RMP, + /// microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved + MCO2SEL: packed union { + raw: u3, + value: MCO2SEL, }, - /// Controls the Input trigger of ADC34 regular channel EXT15 - ADC34_EXT15_RMP: packed union { - raw: u1, - value: ADC34_EXT15_RMP, + }), + /// RCC CPU domain clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// AHB prescaler Set and reset by software to control the division factor of rcc_hclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks 0xxx: rcc_hclk = sys_ck (default after reset) + HPRE: packed union { + raw: u4, + value: HPRE, }, - /// Controls the Input trigger of ADC34 injected channel JEXT5 - ADC34_JEXT5_RMP: packed union { - raw: u1, - value: ADC34_JEXT5_RMP, + /// APB low-speed prescaler (APB1) Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write. 0xx: rcc_pclk1 = rcc_hclk1 (default after reset) + PPRE1: packed union { + raw: u3, + value: PPRE, }, - /// Controls the Input trigger of ADC34 injected channel JEXT11 - ADC34_JEXT11_RMP: packed union { - raw: u1, - value: ADC34_JEXT11_RMP, + reserved8: u1, + /// APB high-speed prescaler (APB2) Set and reset by software to control APB high-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write. 0xx: rcc_pclk2 = rcc_hclk1 + PPRE2: packed union { + raw: u3, + value: PPRE, }, - /// Controls the Input trigger of ADC34 injected channel JEXT14 - ADC34_JEXT14_RMP: packed union { - raw: u1, - value: ADC34_JEXT14_RMP, + reserved12: u1, + /// APB low-speed prescaler (APB3) Set and reset by software to control APB low-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write. 0xx: rcc_pclk3 = rcc_hclk1 + PPRE3: packed union { + raw: u3, + value: PPRE, }, - padding: u18, + reserved16: u1, + /// AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals from RCC_AHB1ENR are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from RCC_AHB1ENR are off. enable control bits + AHB1DIS: u1, + /// AHB2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR are used and when their clocks are disabled in RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR are off. enable control bits + AHB2DIS: u1, + reserved19: u1, + /// AHB4 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB4 peripherals from RCC_AHB4ENR are used and when their clocks are disabled in RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from RCC_AHB4ENR are off. enable control bits + AHB4DIS: u1, + /// APB1 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. control bits + APB1DIS: u1, + /// APB2 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off. control bits + APB2DIS: u1, + /// APB3 clock disable value.Set and cleared by software This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. control bits + APB3DIS: u1, + padding: u9, }), - reserved80: [4]u8, - /// configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - /// SPI1_RX DMA remapping bit - SPI1_RX_DMA_RMP: packed union { + reserved40: [4]u8, + /// RCC PLL clock source selection register + PLLCFGR: [2]mmio.Mmio(packed struct(u32) { + /// DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset). + PLLSRC: packed union { raw: u2, - value: SPI1_RX_DMA_RMP, + value: PLLSRC, }, - /// SPI1_TX DMA remapping bit - SPI1_TX_DMA_RMP: packed union { + /// PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. + PLLRGE: packed union { raw: u2, - value: SPI1_TX_DMA_RMP, + value: PLLRGE, }, - /// I2C1_RX DMA remapping bit - I2C1_RX_DMA_RMP: packed union { - raw: u2, - value: I2C1_RX_DMA_RMP, + /// PLL1 fractional latch enable Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator. In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator. + PLLFRACEN: u1, + /// PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. + PLLVCOSEL: packed union { + raw: u1, + value: PLLVCOSEL, }, - /// I2C1_TX DMA remapping bit - I2C1_TX_DMA_RMP: packed union { - raw: u2, - value: I2C1_TX_DMA_RMP, + reserved8: u2, + /// prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... + DIVM: packed union { + raw: u6, + value: PLLM, }, - /// ADC2 DMA remapping bit - ADC2_DMA_RMP: packed union { - raw: u2, - value: ADC2_DMA_RMP_CFGR3, + reserved16: u2, + /// PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. + PLLPEN: u1, + /// PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). + PLLQEN: u1, + /// PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). + PLLREN: u1, + padding: u13, + }), + reserved52: [4]u8, + /// RCC PLL1 dividers register + PLLDIVR: mmio.Mmio(packed struct(u32) { + /// Multiplication factor for PLL1VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved + PLLN: packed union { + raw: u9, + value: PLLN, }, - reserved16: u6, - /// DAC1_CH1 / DAC1_CH2 Trigger remap - DAC1_TRIG3_RMP: packed union { - raw: u1, - value: DAC1_TRIG3_RMP, + /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... + PLLP: packed union { + raw: u7, + value: PLLDIV, }, - /// DAC1_CH1 / DAC1_CH2 Trigger remap 0: Not remapped 1: DAC trigger is HRTIM1_DAC1_TRIG2 - DAC1_TRIG5_RMP: u1, - padding: u14, + /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLQ: packed union { + raw: u7, + value: PLLDIV, + }, + reserved24: u1, + /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLR: packed union { + raw: u7, + value: PLLDIV, + }, + padding: u1, }), - }; - }; - - pub const lptim_v1c = struct { - pub const CKPOL = enum(u2) { - /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. - Rising = 0x0, - /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. - Falling = 0x1, - /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. - Both = 0x2, - _, - }; - - pub const ClockSource = enum(u1) { - /// clocked by internal clock source (APB clock or any of the embedded oscillators) - Internal = 0x0, - /// clocked by an external clock source through the LPTIM external Input1 - External = 0x1, - }; - - pub const Filter = enum(u2) { - Count1 = 0x0, - Count2 = 0x1, - Count4 = 0x2, - Count8 = 0x3, - }; - - pub const PRESC = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div4 = 0x2, - Div8 = 0x3, - Div16 = 0x4, - Div32 = 0x5, - Div64 = 0x6, - Div128 = 0x7, - }; - - pub const TRIGEN = enum(u2) { - /// software trigger (counting start is initiated by software) - Software = 0x0, - /// rising edge is the active edge - RisingEdge = 0x1, - /// falling edge is the active edge - FallingEdge = 0x2, - /// both edges are active edges - BothEdge = 0x3, - }; - - pub const WAVPOL = enum(u1) { - /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. - Positive = 0x0, - /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. - Negative = 0x1, - }; - - /// Low power timer with Output Compare - pub const LPTIM = extern struct { - /// LPTIM interrupt and status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, - /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. - ARRM: u1, - /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. - EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, - /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. - ARROK: u1, - /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UP: u1, - /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWN: u1, - /// LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. - UE: u1, - /// Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. - REPOK: u1, - padding: u23, + /// RCC PLL1 fractional divider register + PLLFRACR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: * 128 to 560 MHz if PLL1VCOSEL = 0 * 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with * PLL1N between 8 and 420 * PLL1FRACN can be between 0 and 213- 1 * The input frequency Fref1_ck must be between 1 and 16 MHz. To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: * Set the bit PLL1FRACEN to 0 * Write the new fractional value into PLL1FRACN * Set the bit PLL1FRACEN to 1 + PLLFRACN: u13, + padding: u16, }), - /// LPTIM interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, - /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. - ARRMCF: u1, - /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. - EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, - /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. - ARROKCF: u1, - /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPCF: u1, - /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNCF: u1, - /// Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. - UECF: u1, - /// Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. - REPOKCF: u1, - padding: u23, + reserved80: [20]u8, + /// RCC clock source interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization. + LSIRDYIE: u1, + /// LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization. + LSERDYIE: u1, + /// CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization. + CSIRDYIE: u1, + /// HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization. + HSIRDYIE: u1, + /// HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization. + HSERDYIE: u1, + /// HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. + HSI48RDYIE: u1, + /// PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. + PLLRDYIE: u1, + padding: u25, }), - /// LPTIM interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, - /// Autoreload match Interrupt Enable. - ARRMIE: u1, - /// External trigger valid edge Interrupt Enable. - EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, - /// Autoreload register update OK Interrupt Enable. - ARROKIE: u1, - /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPIE: u1, - /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNIE: u1, - /// Update event interrupt enable. - UEIE: u1, - /// Repetition register update OK interrupt Enable. - REPOKIE: u1, - padding: u23, + /// RCC clock source interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. + LSIRDYF: u1, + /// LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set. + LSERDYF: u1, + /// CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set. + CSIRDYF: u1, + /// HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set. + HSIRDYF: u1, + /// HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. + HSERDYF: u1, + /// HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. + HSI48RDYF: u1, + /// PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + PLLRDYF: u1, + reserved10: u3, + /// HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. + HSECSSF: u1, + padding: u21, }), - /// LPTIM configuration register. - CFGR: mmio.Mmio(packed struct(u32) { - /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. - CKSEL: packed union { - raw: u1, - value: ClockSource, - }, - /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. - CKPOL: packed union { - raw: u2, - value: CKPOL, - }, - /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - CKFLT: packed union { - raw: u2, - value: Filter, - }, - reserved6: u1, - /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. - TRGFLT: packed union { - raw: u2, - value: Filter, - }, - reserved9: u1, - /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. - PRESC: packed union { - raw: u3, - value: PRESC, - }, - reserved13: u1, - /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. - TRIGSEL: u3, - reserved17: u1, - /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. - TRIGEN: packed union { - raw: u2, - value: TRIGEN, - }, - /// Timeout enable The TIMOUT bit controls the Timeout feature. - TIMOUT: u1, - /// Waveform shape The WAVE bit controls the output shape. - WAVE: u1, - /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. - WAVPOL: packed union { - raw: u1, - value: WAVPOL, - }, - /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. - PRELOAD: u1, - /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. - COUNTMODE: packed union { - raw: u1, - value: ClockSource, - }, - /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - ENC: u1, + /// RCC clock source interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done. + LSIRDYC: u1, + /// LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done. + LSERDYC: u1, + /// HSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done. + CSIRDYC: u1, + /// HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done. + HSIRDYC: u1, + /// HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done. + HSERDYC: u1, + /// HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. + HSI48RDYC: u1, + /// PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + PLLRDYC: u1, + reserved10: u3, + /// HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done. + HSECSSC: u1, + padding: u21, + }), + reserved96: [4]u8, + /// RCC AHB1 reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 block reset Set and reset by software. + GPDMA1RST: u1, + /// GPDMA2 block reset Set and reset by software. + GPDMA2RST: u1, + reserved12: u10, + /// CRC block reset Set and reset by software. + CRCRST: u1, + reserved17: u4, + /// RAMCFG block reset Set and reset by software. + RAMCFGRST: u1, + padding: u14, + }), + /// RCC AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// GPIOA block reset Set and reset by software. + GPIOARST: u1, + /// GPIOB block reset Set and reset by software. + GPIOBRST: u1, + /// GPIOC block reset Set and reset by software. + GPIOCRST: u1, + /// GPIOD block reset Set and reset by software. + GPIODRST: u1, + reserved7: u3, + /// GPIOH block reset Set and reset by software. + GPIOHRST: u1, + reserved10: u2, + /// ADC1 block reset Set and reset by software. + ADC1RST: u1, + /// DAC block reset Set and reset by software. + DAC1RST: u1, + reserved17: u5, + /// HASH block reset Set and reset by software. + HASHRST: u1, + /// RNG block reset Set and reset by software. + RNGRST: u1, + padding: u13, + }), + reserved116: [12]u8, + /// RCC APB1 peripheral low reset register + APB1LRSTR: mmio.Mmio(packed struct(u32) { + /// TIM2 block reset Set and reset by software. + TIM2RST: u1, + /// TIM3 block reset Set and reset by software. + TIM3RST: u1, + reserved4: u2, + /// TIM6 block reset Set and reset by software. + TIM6RST: u1, + /// TIM7 block reset Set and reset by software. + TIM7RST: u1, + reserved13: u7, + /// OPAMP block reset Set and reset by software. + OPAMPRST: u1, + /// SPI2 block reset Set and reset by software. + SPI2RST: u1, + /// SPI3 block reset Set and reset by software. + SPI3RST: u1, + /// COMP block reset Set and reset by software. + COMPRST: u1, + /// USART2 block reset Set and reset by software. + USART2RST: u1, + /// USART3 block reset Set and reset by software. + USART3RST: u1, + reserved21: u2, + /// I2C1 block reset Set and reset by software. + I2C1RST: u1, + /// I2C2 block reset Set and reset by software. + I2C2RST: u1, + /// I3C1 block reset Set and reset by software. + I3C1RST: u1, + /// CRS block reset Set and reset by software. + CRSRST: u1, padding: u7, }), - /// LPTIM control register. - CR: mmio.Mmio(packed struct(u32) { - /// LPTIM enable The ENABLE bit is set and cleared by software. - ENABLE: u1, - /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. - SNGSTRT: u1, - /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. - CNTSTRT: u1, - /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. - COUNTRST: u1, - /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. - RSTARE: u1, - padding: u27, + /// RCC APB1 peripheral high reset register + APB1HRSTR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// DTS block reset Set and reset by software. + DTSRST: u1, + reserved5: u1, + /// LPTIM2 block reset Set and reset by software. + LPTIM2RST: u1, + reserved9: u3, + /// FDCAN1 block reset Set and reset by software. + FDCAN12RST: u1, + padding: u22, }), - /// LPTIM compare register 1. - CMP: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. - CMP: u16, - padding: u16, + /// RCC APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 block reset Set and reset by software. + TIM1RST: u1, + /// SPI1 block reset Set and reset by software. + SPI1RST: u1, + reserved14: u1, + /// USART1 block reset Set and reset by software. + USART1RST: u1, + reserved24: u9, + /// USB block reset Set and reset by software. + USBRST: u1, + padding: u7, }), - /// LPTIM autoreload register. - ARR: mmio.Mmio(packed struct(u32) { - /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. - ARR: u16, - padding: u16, + /// RCC APB3 peripheral reset register + APB3RSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SBS block reset Set and reset by software. + SYSCFGRST: u1, + reserved6: u4, + /// LPUART1 block reset Set and reset by software. + LPUART1RST: u1, + reserved9: u2, + /// I3C2RST block reset Set and reset by software. + I3C2RST: u1, + reserved11: u1, + /// LPTIM1 block reset Set and reset by software. + LPTIM1RST: u1, + reserved20: u8, + /// VREF block reset Set and reset by software. + VREFRST: u1, + padding: u11, }), - /// LPTIM counter register. - CNT: mmio.Mmio(packed struct(u32) { - /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. - CNT: u16, - padding: u16, + reserved136: [4]u8, + /// RCC AHB1 peripherals clock register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 clock enable Set and reset by software. + GPDMA1EN: u1, + /// GPDMA2 clock enable Set and reset by software. + GPDMA2EN: u1, + reserved8: u6, + /// Flash interface clock enable Set and reset by software. + FLITFEN: u1, + reserved12: u3, + /// CRC clock enable Set and reset by software. + CRCEN: u1, + reserved17: u4, + /// RAMCFG clock enable Set and reset by software. + RAMCFGEN: u1, + reserved28: u10, + /// BKPRAM clock enable Set and reset by software + BKPRAMEN: u1, + reserved31: u2, + /// SRAM1 clock enable Set and reset by software. + SRAM1EN: u1, }), - /// LPTIM option register. - OR: u32, - reserved40: [4]u8, - /// LPTIM repetition register. - RCR: mmio.Mmio(packed struct(u32) { - /// Repetition register value REP is the repetition value for the LPTIM. - REP: u8, - padding: u24, + /// RCC AHB2 peripheral clock register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// GPIOA clock enable Set and reset by software. + GPIOAEN: u1, + /// GPIOB clock enable Set and reset by software. + GPIOBEN: u1, + /// GPIOC clock enable Set and reset by software. + GPIOCEN: u1, + /// GPIOD clock enable Set and reset by software. + GPIODEN: u1, + reserved7: u3, + /// GPIOH clock enable Set and reset by software. + GPIOHEN: u1, + reserved10: u2, + /// ADC1 peripherals clock enabled Set and reset by software. + ADC1EN: u1, + /// DAC clock enable Set and reset by software. + DAC1EN: u1, + reserved17: u5, + /// HASH clock enable Set and reset by software. + HASHEN: u1, + /// RNG clock enable Set and reset by software. + RNGEN: u1, + reserved30: u11, + /// SRAM2 clock enable Set and reset by software. + SRAM2EN: u1, + padding: u1, }), - }; - }; - - pub const dac_v1 = struct { - pub const WAVE = enum(u2) { - /// Wave generation disabled - Disabled = 0x0, - /// Noise wave generation enabled - Noise = 0x1, - /// Triangle wave generation enabled - Triangle = 0x2, - _, - }; - - /// Digital-to-analog converter - pub const DAC = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, - /// channel output buffer disable - BOFF: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u3, - /// channel noise/triangle wave generation enable - WAVE: packed union { - raw: u2, - value: WAVE, - }, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - padding: u19, + reserved156: [12]u8, + /// RCC APB1 peripheral clock register + APB1LENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable Set and reset by software. + TIM2EN: u1, + /// TIM3 clock enable Set and reset by software. + TIM3EN: u1, + reserved4: u2, + /// TIM6 clock enable Set and reset by software. + TIM6EN: u1, + /// TIM7 clock enable Set and reset by software. + TIM7EN: u1, + reserved11: u5, + /// WWDG clock enable Set and reset by software. + WWDGEN: u1, + reserved13: u1, + /// OPAMP clock enable Set and reset by software. + OPAMPEN: u1, + /// SPI2 clock enable Set and reset by software. + SPI2EN: u1, + /// SPI3 clock enable Set and reset by software. + SPI3EN: u1, + /// COMP clock enable Set and reset by software. + COMPEN: u1, + /// USART2 clock enable Set and reset by software. + USART2EN: u1, + /// USART3 clock enable Set and reset by software. + USART3EN: u1, + reserved21: u2, + /// I2C1 clock enable Set and reset by software. + I2C1EN: u1, + /// I2C2 clock enable Set and reset by software. + I2C2EN: u1, + /// I3C1 clock enable Set and reset by software. + I3C1EN: u1, + /// CRS clock enable Set and reset by software. + CRSEN: u1, + padding: u7, }), - /// software trigger register - SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - padding: u31, + /// RCC APB1 peripheral clock register + APB1HENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// DTS clock enable Set and reset by software. + DTSEN: u1, + reserved5: u1, + /// LPTIM2 clock enable Set and reset by software. + LPTIM2EN: u1, + reserved9: u3, + /// FDCAN1 peripheral clock enable Set and reset by software. + FDCAN12EN: u1, + padding: u22, }), - /// channel 12-bit right-aligned data holding register - DHR12R: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// RCC APB2 peripheral clock register + APB2ENR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 clock enable Set and reset by software. + TIM1EN: u1, + /// SPI1 clock enable Set and reset by software. + SPI1EN: u1, + reserved14: u1, + /// USART1 clock enable Set and reset by software. + USART1EN: u1, + reserved24: u9, + /// USB clock enable Set and reset by software. + USBEN: u1, + padding: u7, }), - /// channel 12-bit left-aligned data holding register - DHR12L: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + /// RCC APB3 peripheral clock register + APB3ENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SBS clock enable Set and reset by software. + SYSCFGEN: u1, + reserved6: u4, + /// LPUART1 clock enable Set and reset by software. + LPUART1EN: u1, + reserved9: u2, + /// I3C2EN clock enable Set and reset by software. + I3C2EN: u1, + reserved11: u1, + /// LPTIM1 clock enable Set and reset by software. + LPTIM1EN: u1, + reserved20: u8, + /// VREF clock enable Set and reset by software. + VREFEN: u1, + /// RTC APB interface clock enable Set and reset by software. + RTCAPBEN: u1, + padding: u10, }), - /// channel 8-bit right-aligned data holding register - DHR8R: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + reserved176: [4]u8, + /// RCC AHB1 sleep clock register + AHB1LPENR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 clock enable during sleep mode Set and reset by software. + GPDMA1LPEN: u1, + /// GPDMA2 clock enable during sleep mode Set and reset by software. + GPDMA2LPEN: u1, + reserved8: u6, + /// Flash interface (FLITF) clock enable during sleep mode Set and reset by software. + FLITFLPEN: u1, + reserved12: u3, + /// CRC clock enable during sleep mode Set and reset by software. + CRCLPEN: u1, + reserved17: u4, + /// RAMCFG clock enable during sleep mode Set and reset by software. + RAMCFGLPEN: u1, + reserved28: u10, + /// BKPRAM clock enable during sleep mode Set and reset by software + BKPRAMLPEN: u1, + /// ICACHE clock enable during sleep mode Set and reset by software + ICACHELPEN: u1, + reserved31: u1, + /// SRAM1 clock enable during sleep mode Set and reset by software + SRAM1LPEN: u1, }), - reserved32: [12]u8, - /// dual 12-bit right-aligned data holding register - DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// RCC AHB2 sleep clock register + AHB2LPENR: mmio.Mmio(packed struct(u32) { + /// GPIOA clock enable during sleep mode Set and reset by software. + GPIOALPEN: u1, + /// GPIOB clock enable during sleep mode Set and reset by software. + GPIOBLPEN: u1, + /// GPIOC clock enable during sleep mode Set and reset by software. + GPIOCLPEN: u1, + /// GPIOD clock enable during sleep mode Set and reset by software. + GPIODLPEN: u1, + reserved7: u3, + /// GPIOH clock enable during sleep mode Set and reset by software. + GPIOHLPEN: u1, + reserved10: u2, + /// ADC1 peripherals clock enable during sleep mode Set and reset by software. + ADC1LPEN: u1, + /// DAC clock enable during sleep mode Set and reset by software. + DAC1LPEN: u1, + reserved17: u5, + /// HASH clock enable during sleep mode Set and reset by software. + HASHLPEN: u1, + /// RNG clock enable during sleep mode Set and reset by software. + RNGLPEN: u1, + reserved30: u11, + /// SRAM2 clock enable during sleep mode Set and reset by software. + SRAM2LPEN: u1, + padding: u1, }), - /// dual 12-bit left aligned data holding register - DHR12LD: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + reserved196: [12]u8, + /// RCC APB1 sleep clock register + APB1LLPENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable during sleep mode Set and reset by software. + TIM2LPEN: u1, + /// TIM3 clock enable during sleep mode Set and reset by software. + TIM3LPEN: u1, + reserved4: u2, + /// TIM6 clock enable during sleep mode Set and reset by software. + TIM6LPEN: u1, + /// TIM7 clock enable during sleep mode Set and reset by software. + TIM7LPEN: u1, + reserved11: u5, + /// WWDG clock enable during sleep mode Set and reset by software. + WWDGLPEN: u1, + reserved13: u1, + /// OPAMP clock enable during sleep mode Set and reset by software. + OPAMPLPEN: u1, + /// SPI2 clock enable during sleep mode Set and reset by software. + SPI2LPEN: u1, + /// SPI3 clock enable during sleep mode Set and reset by software. + SPI3LPEN: u1, + /// COMP clock enable during sleep mode Set and reset by software. + COMPLPEN: u1, + /// USART2 clock enable during sleep mode Set and reset by software. + USART2LPEN: u1, + /// USART3 clock enable during sleep mode Set and reset by software. + USART3LPEN: u1, + reserved21: u2, + /// I2C1 clock enable during sleep mode Set and reset by software. + I2C1LPEN: u1, + /// I2C2 clock enable during sleep mode Set and reset by software. + I2C2LPEN: u1, + /// I3C1 clock enable during sleep mode Set and reset by software. + I3C1LPEN: u1, + /// CRS clock enable during sleep mode Set and reset by software. + CRSLPEN: u1, + padding: u7, }), - /// dual 8-bit right aligned data holding register - DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// RCC APB1 sleep clock register + APB1HLPENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// DTS clock enable during sleep mode Set and reset by software. + DTSLPEN: u1, + reserved5: u1, + /// LPTIM2 clock enable during sleep mode Set and reset by software. + LPTIM2LPEN: u1, + reserved9: u3, + /// FDCAN1 peripheral clock enable during sleep mode Set and reset by software. + FDCAN12LPEN: u1, + padding: u22, }), - /// channel data output register - DOR: [2]mmio.Mmio(packed struct(u32) { - /// channel data output - DOR: u12, - padding: u20, + /// RCC APB2 sleep clock register + APB2LPENR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 clock enable during sleep mode Set and reset by software. + TIM1LPEN: u1, + /// SPI1 clock enable during sleep mode Set and reset by software. + SPI1LPEN: u1, + reserved14: u1, + /// USART1 clock enable during sleep mode Set and reset by software. + USART1LPEN: u1, + reserved24: u9, + /// USB clock enable during sleep mode Set and reset by software. + USBLPEN: u1, + padding: u7, }), - }; - }; - - pub const dmamux_v1 = struct { - pub const POL = enum(u2) { - /// No event, i.e. no synchronization nor detection - NoEdge = 0x0, - /// Rising edge - RisingEdge = 0x1, - /// Falling edge - FallingEdge = 0x2, - /// Rising and falling edges - BothEdges = 0x3, - }; - - /// DMAMUX - pub const DMAMUX = extern struct { - /// DMAMux - DMA request line multiplexer channel x control register - CCR: [16]mmio.Mmio(packed struct(u32) { - /// Input DMA request line selected - DMAREQ_ID: u8, - /// Interrupt enable at synchronization event overrun - SOIE: u1, - /// Event generation enable/disable - EGE: u1, - reserved16: u6, - /// Synchronous operating mode enable/disable - SE: u1, - /// Synchronization event type selector Defines the synchronization event on the selected synchronization input: - SPOL: packed union { - raw: u2, - value: POL, + /// RCC APB3 sleep clock register + APB3LPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SBS clock enable during sleep mode Set and reset by software. + SYSCFGLPEN: u1, + reserved6: u4, + /// LPUART1 clock enable during sleep mode Set and reset by software. + LPUART1LPEN: u1, + reserved9: u2, + /// I3C2 clock enable during sleep mode Set and reset by software. + I3C2LPEN: u1, + reserved11: u1, + /// LPTIM1 clock enable during sleep mode Set and reset by software. + LPTIM1LPEN: u1, + reserved20: u8, + /// VREF clock enable during sleep mode Set and reset by software. + VREFLPEN: u1, + /// RTC APB interface clock enable during sleep mode Set and reset by software. + RTCAPBLPEN: u1, + padding: u10, + }), + reserved216: [4]u8, + /// RCC kernel clock configuration register + CCIPR1: mmio.Mmio(packed struct(u32) { + /// USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + USART1SEL: packed union { + raw: u3, + value: USART1SEL, + }, + /// USART2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + USART2SEL: packed union { + raw: u3, + value: USARTSEL, + }, + /// USART3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + USART3SEL: packed union { + raw: u3, + value: USARTSEL, + }, + reserved31: u22, + /// TIM2, TIM3 and LPTIM2 input capture source selection Set and reset by software. + TIMICSEL: packed union { + raw: u1, + value: TIMICSEL, }, - /// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. - NBREQ: u5, - /// Synchronization input selected - SYNC_ID: u5, - padding: u3, }), - reserved128: [64]u8, - /// DMAMUX request line multiplexer interrupt channel status register - CSR: mmio.Mmio(packed struct(u32) { - /// Synchronization overrun event flag - SOF: u1, - padding: u31, + /// RCC kernel clock configuration register + CCIPR2: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// LPTIM1 kernel clock source selection others: reserved, the kernel clock is disabled + LPTIM1SEL: packed union { + raw: u3, + value: LPTIM1SEL, + }, + reserved12: u1, + /// LPTIM2 kernel clock source selection others: reserved, the kernel clock is disabled + LPTIM2SEL: packed union { + raw: u3, + value: LPTIM2SEL, + }, + padding: u17, }), - /// DMAMUX request line multiplexer interrupt clear flag register - CFR: mmio.Mmio(packed struct(u32) { - /// Synchronization overrun event flag - SOF: u1, - padding: u31, + /// RCC kernel clock configuration register + CCIPR3: mmio.Mmio(packed struct(u32) { + /// SPI1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + SPI1SEL: packed union { + raw: u3, + value: SPISEL, + }, + /// SPI2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + SPI2SEL: packed union { + raw: u3, + value: SPISEL, + }, + /// SPI3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled + SPI3SEL: packed union { + raw: u3, + value: SPISEL, + }, + reserved24: u15, + /// LPUART1 kernel clock source selection others: reserved, the kernel clock is disabled + LPUART1SEL: packed union { + raw: u3, + value: LPUARTSEL, + }, + padding: u5, }), - reserved256: [120]u8, - /// DMAMux - DMA request generator channel x control register - RGCR: [8]mmio.Mmio(packed struct(u32) { - /// DMA request trigger input selected - SIG_ID: u5, - reserved8: u3, - /// Interrupt enable at trigger event overrun - OIE: u1, - reserved16: u7, - /// DMA request generator channel enable/disable - GE: u1, - /// DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input - GPOL: packed union { + /// RCC kernel clock configuration register + CCIPR4: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// SYSTICK clock source selection Note: rcc_hclk frequency must be four times higher than lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK). + SYSTICKSEL: packed union { raw: u2, - value: POL, + value: SYSTICKSEL, }, - /// Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. - GNBREQ: u5, - padding: u8, + /// USB kernel clock source selection + USBSEL: packed union { + raw: u2, + value: USBSEL, + }, + reserved16: u10, + /// I2C1 kernel clock source selection + I2C1SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// I2C2 kernel clock source selection + I2C2SEL: packed union { + raw: u2, + value: I2CSEL, + }, + reserved24: u4, + /// I3C1 kernel clock source selection + I3C1SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// I3C2 kernel clock source selection + I3C2SEL: packed union { + raw: u2, + value: I3C2SEL, + }, + padding: u4, }), - reserved320: [32]u8, - /// DMAMux - DMA request generator status register - RGSR: mmio.Mmio(packed struct(u32) { - /// Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. - OF: u1, - padding: u31, + /// RCC kernel clock configuration register + CCIPR5: mmio.Mmio(packed struct(u32) { + /// ADC and DAC kernel clock source selection others: reserved, the kernel clock is disabled + ADCDACSEL: packed union { + raw: u3, + value: ADCDACSEL, + }, + /// DAC hold clock + DACHOLDSEL: packed union { + raw: u1, + value: DACHOLDSEL, + }, + /// RNG kernel clock source selection + RNGSEL: packed union { + raw: u2, + value: RNGSEL, + }, + reserved8: u2, + /// FDCAN1 kernel clock source selection + FDCAN12SEL: packed union { + raw: u2, + value: FDCANSEL, + }, + reserved30: u20, + /// per_ck clock source selection + PERSEL: packed union { + raw: u2, + value: PERSEL, + }, }), - /// DMAMux - DMA request generator clear flag register - RGCFR: mmio.Mmio(packed struct(u32) { - /// Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. - OF: u1, - padding: u31, + reserved240: [4]u8, + /// RCC Backup domain control register + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enabled Set and reset by software. + LSEON: u1, + /// LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0. + LSERDY: u1, + /// LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1) + LSEBYP: u1, + /// LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0). + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON. + LSECSSON: u1, + /// LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator. + LSECSSD: u1, + /// low-speed external clock type in bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled. + LSEEXT: packed union { + raw: u1, + value: LSEEXT, + }, + /// RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST). + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable Set and reset by software. + RTCEN: u1, + /// VSwitch domain software reset Set and reset by software. + VSWRST: u1, + reserved24: u7, + /// Low-speed clock output (LSCO) enable Set and cleared by software. + LSCOEN: u1, + /// Low-speed clock output selection Set and cleared by software. + LSCOSEL: packed union { + raw: u1, + value: LSCOSEL, + }, + /// LSI oscillator enable Set and cleared by software. + LSION: u1, + /// LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0. + LSIRDY: u1, + padding: u4, + }), + /// RCC reset status register + RSR: mmio.Mmio(packed struct(u32) { + reserved23: u23, + /// remove reset flag Set and reset by software to reset the value of the reset flags. + RMVF: u1, + reserved26: u2, + /// pin reset flag (NRST) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. + PINRSTF: u1, + /// BOR reset flag Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). + BORRSTF: u1, + /// system reset from CPU reset flag Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33. + SFTRSTF: u1, + /// independent watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. + IWDGRSTF: u1, + /// window watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. + WWDGRSTF: u1, + /// Low-power reset flag Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared. Cleared by writing to the RMVF bit. + LPWRRSTF: u1, }), }; }; - pub const dcmi_v1 = struct { - /// Digital camera interface - pub const DCMI = extern struct { - /// control register 1 - CR: mmio.Mmio(packed struct(u32) { - /// Capture enable - CAPTURE: u1, - /// Capture mode - CM: u1, - /// Crop feature - CROP: u1, - /// JPEG format - JPEG: u1, - /// Embedded synchronization select - ESS: u1, - /// Pixel clock polarity - PCKPOL: u1, - /// Horizontal synchronization polarity - HSPOL: u1, - /// Vertical synchronization polarity - VSPOL: u1, - /// Frame capture rate control - FCRC: u2, - /// Extended data mode - EDM: u2, - reserved14: u2, - /// DCMI enable - ENABLE: u1, - padding: u17, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// HSYNC - HSYNC: u1, - /// VSYNC - VSYNC: u1, - /// FIFO not empty - FNE: u1, - padding: u29, - }), - /// raw interrupt status register - RIS: mmio.Mmio(packed struct(u32) { - /// Capture complete raw interrupt status - FRAME_RIS: u1, - /// Overrun raw interrupt status - OVR_RIS: u1, - /// Synchronization error raw interrupt status - ERR_RIS: u1, - /// VSYNC raw interrupt status - VSYNC_RIS: u1, - /// Line raw interrupt status - LINE_RIS: u1, - padding: u27, - }), - /// interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// Capture complete interrupt enable - FRAME_IE: u1, - /// Overrun interrupt enable - OVR_IE: u1, - /// Synchronization error interrupt enable - ERR_IE: u1, - /// VSYNC interrupt enable - VSYNC_IE: u1, - /// Line interrupt enable - LINE_IE: u1, - padding: u27, - }), - /// masked interrupt status register - MIS: mmio.Mmio(packed struct(u32) { - /// Capture complete masked interrupt status - FRAME_MIS: u1, - /// Overrun masked interrupt status - OVR_MIS: u1, - /// Synchronization error masked interrupt status - ERR_MIS: u1, - /// VSYNC masked interrupt status - VSYNC_MIS: u1, - /// Line masked interrupt status - LINE_MIS: u1, - padding: u27, - }), - /// interrupt clear register - ICR: mmio.Mmio(packed struct(u32) { - /// Capture complete interrupt status clear - FRAME_ISC: u1, - /// Overrun interrupt status clear - OVR_ISC: u1, - /// Synchronization error interrupt status clear - ERR_ISC: u1, - /// Vertical synch interrupt status clear - VSYNC_ISC: u1, - /// line interrupt status clear - LINE_ISC: u1, - padding: u27, - }), - /// embedded synchronization code register - ESCR: mmio.Mmio(packed struct(u32) { - /// Frame start delimiter code - FSC: u8, - /// Line start delimiter code - LSC: u8, - /// Line end delimiter code - LEC: u8, - /// Frame end delimiter code - FEC: u8, - }), - /// embedded synchronization unmask register - ESUR: mmio.Mmio(packed struct(u32) { - /// Frame start delimiter unmask - FSU: u8, - /// Line start delimiter unmask - LSU: u8, - /// Line end delimiter unmask - LEU: u8, - /// Frame end delimiter unmask - FEU: u8, - }), - /// crop window start - CWSTRT: mmio.Mmio(packed struct(u32) { - /// Horizontal offset count - HOFFCNT: u14, - reserved16: u2, - /// Vertical start line count - VST: u13, - padding: u3, - }), - /// crop window size - CWSIZE: mmio.Mmio(packed struct(u32) { - /// Capture count - CAPCNT: u14, - reserved16: u2, - /// Vertical line count - VLINE: u14, - padding: u2, - }), - /// data register - DR: mmio.Mmio(packed struct(u32) { - /// Data byte 0 - Byte0: u8, - /// Data byte 1 - Byte1: u8, - /// Data byte 2 - Byte2: u8, - /// Data byte 3 - Byte3: u8, - }), + pub const rcc_h7 = struct { + pub const ADCSEL = enum(u2) { + /// pll2_p selected as peripheral clock + PLL2_P = 0x0, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// PER selected as peripheral clock + PER = 0x2, + _, }; - }; - pub const syscfg_h7 = struct { - pub const ETH_SEL_PHY = enum(u3) { - /// GMII or MII - MII_GMII = 0x0, - /// RMII - RMII = 0x4, + pub const CECSEL = enum(u2) { + /// LSE selected as peripheral clock + LSE = 0x0, + /// LSI selected as peripheral clock + LSI = 0x1, + /// csi_ker selected as peripheral clock + CSI = 0x2, _, }; - pub const ITCM_AXI_RAM_SIZE = enum(u2) { - /// 64 Kbyte ITCM-RAM / 320 Kbyte AXI-SRAM - Itcm64Axi320 = 0x0, - /// 128 Kbyte ITCM-RAM / 256 Kbyte AXI-SRAM - Itcm128Axi256 = 0x1, - /// 192 Kbyte ITCM-RAM / 192 Kbyte AXI-SRAM - Itcm192Axi192 = 0x2, - /// 256 Kbyte ITCM-RAM / 128 Kbyte AXI-SRAM - Itcm256Axi128 = 0x3, + pub const DFSDMSEL = enum(u1) { + /// rcc_pclk2 selected as peripheral clock + PCLK2 = 0x0, + /// System clock selected as peripheral clock + SYS = 0x1, }; - /// System configuration controller - pub const SYSCFG = extern struct { - reserved4: [4]u8, - /// peripheral mode configuration register - PMCR: mmio.Mmio(packed struct(u32) { - /// I2C1 Fm+ - I2C1FMP: u1, - /// I2C2 Fm+ - I2C2FMP: u1, - /// I2C3 Fm+ - I2C3FMP: u1, - /// I2C4 Fm+ - I2C4FMP: u1, - /// PB(6) Fm+ - PB6FMP: u1, - /// PB(7) Fast Mode Plus - PB7FMP: u1, - /// PB(8) Fast Mode Plus - PB8FMP: u1, - /// PB(9) Fm+ - PB9FMP: u1, - /// Booster Enable - BOOSTE: u1, - /// Analog switch supply voltage selection - BOOSTVDDSEL: u1, - reserved21: u11, - /// Ethernet PHY interface selection. - ETH_SEL_PHY: packed union { - raw: u3, - value: ETH_SEL_PHY, - }, - /// PA0 Switch Open - PA0SO: u1, - /// PA1 Switch Open - PA1SO: u1, - /// PC2 Switch Open - PC2SO: u1, - /// PC3 Switch Open - PC3SO: u1, - padding: u4, - }), - /// external interrupt configuration register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration (x = 4 to 7) - EXTI: u4, - padding: u28, - }), - reserved32: [8]u8, - /// compensation cell control/status register - CCCSR: mmio.Mmio(packed struct(u32) { - /// enable - EN: u1, - /// Code selection - CS: u1, - reserved8: u6, - /// Compensation cell ready flag - RDY: u1, - reserved16: u7, - /// High-speed at low-voltage - HSLV: u1, - padding: u15, - }), - /// SYSCFG compensation cell value register - CCVR: mmio.Mmio(packed struct(u32) { - /// NMOS compensation value - NCV: u4, - /// PMOS compensation value - PCV: u4, - padding: u24, - }), - /// SYSCFG compensation cell code register - CCCR: mmio.Mmio(packed struct(u32) { - /// NMOS compensation code - NCC: u4, - /// PMOS compensation code - PCC: u4, - padding: u24, - }), - reserved292: [248]u8, - /// SYSCFG package register - PKGR: mmio.Mmio(packed struct(u32) { - /// Package - PKG: u4, - padding: u28, - }), - reserved768: [472]u8, - /// SYSCFG user register 0 - UR0: mmio.Mmio(packed struct(u32) { - /// Bank Swap - BKS: u1, - reserved16: u15, - /// Readout protection - RDP: u8, - padding: u8, - }), - reserved776: [4]u8, - /// SYSCFG user register 2 - UR2: mmio.Mmio(packed struct(u32) { - /// BOR_LVL Brownout Reset Threshold Level - BORH: u2, - reserved16: u14, - /// Boot Address 0 - BOOT_ADD0: u16, - }), - /// SYSCFG user register 3 - UR3: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Boot Address 1 - BOOT_ADD1: u16, - }), - /// SYSCFG user register 4 - UR4: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Mass Erase Protected Area Disabled for bank 1 - MEPAD_1: u1, - padding: u15, - }), - /// SYSCFG user register 5 - UR5: mmio.Mmio(packed struct(u32) { - /// Mass erase secured area disabled for bank 1 - MESAD_1: u1, - reserved16: u15, - /// Write protection for flash bank 1 - WRPN_1: u8, - padding: u8, - }), - /// SYSCFG user register 6 - UR6: mmio.Mmio(packed struct(u32) { - /// Protected area start address for bank 1 - PA_BEG_1: u12, - reserved16: u4, - /// Protected area end address for bank 1 - PA_END_1: u12, - padding: u4, - }), - /// SYSCFG user register 7 - UR7: mmio.Mmio(packed struct(u32) { - /// Secured area start address for bank 1 - SA_BEG_1: u12, - reserved16: u4, - /// Secured area end address for bank 1 - SA_END_1: u12, - padding: u4, - }), - /// SYSCFG user register 8 - UR8: mmio.Mmio(packed struct(u32) { - /// Mass erase protected area disabled for bank 2 - MEPAD_2: u1, - reserved16: u15, - /// Mass erase secured area disabled for bank 2 - MESAD_2: u1, - padding: u15, - }), - /// SYSCFG user register 9 - UR9: mmio.Mmio(packed struct(u32) { - /// Write protection for flash bank 2 - WRPN_2: u8, - reserved16: u8, - /// Protected area start address for bank 2 - PA_BEG_2: u12, - padding: u4, - }), - /// SYSCFG user register 10 - UR10: mmio.Mmio(packed struct(u32) { - /// Protected area end address for bank 2 - PA_END_2: u12, - reserved16: u4, - /// Secured area start address for bank 2 - SA_BEG_2: u12, - padding: u4, - }), - /// SYSCFG user register 11 - UR11: mmio.Mmio(packed struct(u32) { - /// Secured area end address for bank 2 - SA_END_2: u12, - reserved16: u4, - /// Independent Watchdog 1 mode - IWDG1M: u1, - padding: u15, - }), - /// SYSCFG user register 12 - UR12: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Secure mode - SECURE: u1, - padding: u15, - }), - /// SYSCFG user register 13 - UR13: mmio.Mmio(packed struct(u32) { - /// Secured DTCM RAM Size - SDRS: u2, - reserved16: u14, - /// D1 Standby reset - D1SBRST: u1, - padding: u15, - }), - /// SYSCFG user register 14 - UR14: mmio.Mmio(packed struct(u32) { - /// D1 Stop Reset - D1STPRST: u1, - padding: u31, - }), - /// SYSCFG user register 15 - UR15: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Freeze independent watchdog in Standby mode - FZIWDGSTB: u1, - padding: u15, - }), - /// SYSCFG user register 16 - UR16: mmio.Mmio(packed struct(u32) { - /// Freeze independent watchdog in Stop mode - FZIWDGSTP: u1, - reserved16: u15, - /// Private key programmed - PKP: u1, - padding: u15, - }), - /// SYSCFG user register 17 - UR17: mmio.Mmio(packed struct(u32) { - /// I/O high speed / low voltage - IO_HSLV: u1, - reserved16: u15, - /// ITCM-RAM / AXI-SRAM size - TCM_AXI_SHARED_CFG: packed union { - raw: u2, - value: ITCM_AXI_RAM_SIZE, - }, - padding: u14, - }), - /// SYSCFG user register 18 - UR18: mmio.Mmio(packed struct(u32) { - /// CPU maximum frequency boost enable - CPU_FREQ_BOOST: u1, - padding: u31, - }), + pub const DSISEL = enum(u1) { + /// DSI-PHY used as DSI byte lane clock source (usual case) + DSI_PHY = 0x0, + /// PLL2_Q used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode) + PLL2_Q = 0x1, }; - }; - pub const rcc_u0 = struct { - pub const ADCSEL = enum(u2) { - SYS = 0x0, - PLL1_P = 0x1, - HSI = 0x2, + pub const FDCANSEL = enum(u2) { + /// HSE selected as peripheral clock + HSE = 0x0, + /// pll1_q selected as peripheral clock + PLL1_Q = 0x1, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x2, _, }; - pub const CLK48SEL = enum(u2) { - DISABLE = 0x0, - MSI = 0x1, - PLL1_Q = 0x2, - HSI48 = 0x3, + pub const FMCSEL = enum(u2) { + /// AHB3 selected as peripheral clock + HCLK3 = 0x0, + /// pll1_q selected as peripheral clock + PLL1_Q = 0x1, + /// pll2_r selected as peripheral clock + PLL2_R = 0x2, + /// PER selected as peripheral clock + PER = 0x3, }; pub const HPRE = enum(u4) { + /// sys_ck not divided Div1 = 0x0, + /// sys_ck divided by 2 Div2 = 0x8, + /// sys_ck divided by 4 Div4 = 0x9, + /// sys_ck divided by 8 Div8 = 0xa, + /// sys_ck divided by 16 Div16 = 0xb, + /// sys_ck divided by 64 Div64 = 0xc, + /// sys_ck divided by 128 Div128 = 0xd, + /// sys_ck divided by 256 Div256 = 0xe, + /// sys_ck divided by 512 Div512 = 0xf, _, }; - pub const I2C1SEL = enum(u2) { - PCLK1 = 0x0, - SYS = 0x1, - HSI = 0x2, - _, - }; - - pub const I2C3SEL = enum(u2) { - PCLK1 = 0x0, - SYS = 0x1, - HSI = 0x2, - _, - }; - - pub const LPTIM1SEL = enum(u2) { - PCLK1 = 0x0, - LSI = 0x1, - HSI = 0x2, - LSE = 0x3, + pub const HRTIMSEL = enum(u1) { + /// The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) + TIMY_KER = 0x0, + /// The HRTIM prescaler clock source is the CPU clock (c_ck) + C_CK = 0x1, }; - pub const LPTIM2SEL = enum(u2) { - PCLK1 = 0x0, - LSI = 0x1, - HSI = 0x2, - LSE = 0x3, + pub const HSIDIV = enum(u2) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x1, + /// Division by 4 + Div4 = 0x2, + /// Division by 8 + Div8 = 0x3, }; - pub const LPTIM3SEL = enum(u2) { + pub const I2C1235SEL = enum(u2) { + /// rcc_pclk1 selected as peripheral clock PCLK1 = 0x0, - LSI = 0x1, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// hsi_ker selected as peripheral clock HSI = 0x2, - LSE = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x3, }; - pub const LPUART1SEL = enum(u2) { - PCLK1 = 0x0, - SYS = 0x1, + pub const I2C4SEL = enum(u2) { + /// rcc_pclk4 selected as peripheral clock + PCLK4 = 0x0, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// hsi_ker selected as peripheral clock HSI = 0x2, - LSE = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x3, }; - pub const LPUART2SEL = enum(u2) { + pub const LPTIM1SEL = enum(u3) { + /// rcc_pclk1 selected as peripheral clock PCLK1 = 0x0, - SYS = 0x1, - HSI = 0x2, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_r selected as peripheral clock + PLL3_R = 0x2, + /// LSE selected as peripheral clock LSE = 0x3, + /// LSI selected as peripheral clock + LSI = 0x4, + /// PER selected as peripheral clock + PER = 0x5, + _, }; - pub const LPUART3SEL = enum(u2) { - PCLK1 = 0x0, - SYS = 0x1, - HSI = 0x2, + pub const LPTIM2SEL = enum(u3) { + /// rcc_pclk4 selected as peripheral clock + PCLK4 = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_r selected as peripheral clock + PLL3_R = 0x2, + /// LSE selected as peripheral clock LSE = 0x3, + /// LSI selected as peripheral clock + LSI = 0x4, + /// PER selected as peripheral clock + PER = 0x5, + _, }; - pub const LSCOSEL = enum(u1) { - LSI = 0x0, - LSE = 0x1, + pub const LPUARTSEL = enum(u3) { + /// rcc_pclk_d4 selected as peripheral clock + PCLK4 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, }; pub const LSEDRV = enum(u2) { @@ -405027,82 +386237,81 @@ pub const types = struct { High = 0x3, }; - pub const LSIPREDIV = enum(u1) { - Div1 = 0x0, - Div128 = 0x1, - }; - - pub const MCOPRE = enum(u4) { - Div1 = 0x0, - Div2 = 0x1, - Div4 = 0x2, - Div8 = 0x3, - Div16 = 0x4, - Div32 = 0x5, - Div64 = 0x6, - Div128 = 0x7, - Div256 = 0x8, - Div512 = 0x9, - Div1024 = 0xa, + pub const MCO1SEL = enum(u3) { + /// HSI selected for micro-controller clock output + HSI = 0x0, + /// LSE selected for micro-controller clock output + LSE = 0x1, + /// HSE selected for micro-controller clock output + HSE = 0x2, + /// pll1_q selected for micro-controller clock output + PLL1_Q = 0x3, + /// HSI48 selected for micro-controller clock output + HSI48 = 0x4, _, }; - pub const MCOSEL = enum(u4) { - DISABLE = 0x0, - SYS = 0x1, - MSI = 0x2, - HSI = 0x3, - HSE = 0x4, - PLL1_R = 0x5, - LSI = 0x6, - LSE = 0x7, - HSI48 = 0x8, - RTC = 0x9, - RTC_WKUP = 0xa, + pub const MCO2SEL = enum(u3) { + /// System clock selected for micro-controller clock output + SYS = 0x0, + /// pll2_p selected for micro-controller clock output + PLL2_P = 0x1, + /// HSE selected for micro-controller clock output + HSE = 0x2, + /// pll1_p selected for micro-controller clock output + PLL1_P = 0x3, + /// CSI selected for micro-controller clock output + CSI = 0x4, + /// LSI selected for micro-controller clock output + LSI = 0x5, _, }; - pub const MSIRANGE = enum(u4) { - /// range 0 around 100 kHz - Range100K = 0x0, - /// range 1 around 200 kHz - Range200K = 0x1, - /// range 2 around 400 kHz - Range400K = 0x2, - /// range 3 around 800 kHz - Range800K = 0x3, - /// range 4 around 1 MHz - Range1M = 0x4, - /// range 5 around 2 MHz - Range2M = 0x5, - /// range 6 around 4 MHz - Range4M = 0x6, - /// range 7 around 8 MHz - Range8M = 0x7, - /// range 8 around 16 MHz - Range16M = 0x8, - /// range 9 around 24 MHz - Range24M = 0x9, - /// range 10 around 32 MHz - Range32M = 0xa, - /// range 11 around 48 MHz - Range48M = 0xb, + pub const MCOPRE = enum(u4) { + /// Divide by 1 + Div1 = 0x1, + /// Divide by 2 + Div2 = 0x2, + /// Divide by 3 + Div3 = 0x3, + /// Divide by 4 + Div4 = 0x4, + /// Divide by 5 + Div5 = 0x5, + /// Divide by 6 + Div6 = 0x6, + /// Divide by 7 + Div7 = 0x7, + /// Divide by 8 + Div8 = 0x8, + /// Divide by 9 + Div9 = 0x9, + /// Divide by 10 + Div10 = 0xa, + /// Divide by 11 + Div11 = 0xb, + /// Divide by 12 + Div12 = 0xc, + /// Divide by 13 + Div13 = 0xd, + /// Divide by 14 + Div14 = 0xe, + /// Divide by 15 + Div15 = 0xf, _, }; - pub const MSIRGSEL = enum(u1) { - /// MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register - CSR = 0x0, - /// MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register - CR = 0x1, - }; - - pub const MSISRANGE = enum(u4) { - RANGE_81MHz = 0x4, + pub const PERSEL = enum(u2) { + /// HSI selected as peripheral clock + HSI = 0x0, + /// CSI selected as peripheral clock + CSI = 0x1, + /// HSE selected as peripheral clock + HSE = 0x2, _, }; - pub const PLLM = enum(u3) { + pub const PLLDIV = enum(u7) { Div1 = 0x0, Div2 = 0x1, Div3 = 0x2, @@ -405111,144 +386320,6 @@ pub const types = struct { Div6 = 0x5, Div7 = 0x6, Div8 = 0x7, - }; - - pub const PLLN = enum(u7) { - Mul4 = 0x4, - Mul5 = 0x5, - Mul6 = 0x6, - Mul7 = 0x7, - Mul8 = 0x8, - Mul9 = 0x9, - Mul10 = 0xa, - Mul11 = 0xb, - Mul12 = 0xc, - Mul13 = 0xd, - Mul14 = 0xe, - Mul15 = 0xf, - Mul16 = 0x10, - Mul17 = 0x11, - Mul18 = 0x12, - Mul19 = 0x13, - Mul20 = 0x14, - Mul21 = 0x15, - Mul22 = 0x16, - Mul23 = 0x17, - Mul24 = 0x18, - Mul25 = 0x19, - Mul26 = 0x1a, - Mul27 = 0x1b, - Mul28 = 0x1c, - Mul29 = 0x1d, - Mul30 = 0x1e, - Mul31 = 0x1f, - Mul32 = 0x20, - Mul33 = 0x21, - Mul34 = 0x22, - Mul35 = 0x23, - Mul36 = 0x24, - Mul37 = 0x25, - Mul38 = 0x26, - Mul39 = 0x27, - Mul40 = 0x28, - Mul41 = 0x29, - Mul42 = 0x2a, - Mul43 = 0x2b, - Mul44 = 0x2c, - Mul45 = 0x2d, - Mul46 = 0x2e, - Mul47 = 0x2f, - Mul48 = 0x30, - Mul49 = 0x31, - Mul50 = 0x32, - Mul51 = 0x33, - Mul52 = 0x34, - Mul53 = 0x35, - Mul54 = 0x36, - Mul55 = 0x37, - Mul56 = 0x38, - Mul57 = 0x39, - Mul58 = 0x3a, - Mul59 = 0x3b, - Mul60 = 0x3c, - Mul61 = 0x3d, - Mul62 = 0x3e, - Mul63 = 0x3f, - Mul64 = 0x40, - Mul65 = 0x41, - Mul66 = 0x42, - Mul67 = 0x43, - Mul68 = 0x44, - Mul69 = 0x45, - Mul70 = 0x46, - Mul71 = 0x47, - Mul72 = 0x48, - Mul73 = 0x49, - Mul74 = 0x4a, - Mul75 = 0x4b, - Mul76 = 0x4c, - Mul77 = 0x4d, - Mul78 = 0x4e, - Mul79 = 0x4f, - Mul80 = 0x50, - Mul81 = 0x51, - Mul82 = 0x52, - Mul83 = 0x53, - Mul84 = 0x54, - Mul85 = 0x55, - Mul86 = 0x56, - Mul87 = 0x57, - Mul88 = 0x58, - Mul89 = 0x59, - Mul90 = 0x5a, - Mul91 = 0x5b, - Mul92 = 0x5c, - Mul93 = 0x5d, - Mul94 = 0x5e, - Mul95 = 0x5f, - Mul96 = 0x60, - Mul97 = 0x61, - Mul98 = 0x62, - Mul99 = 0x63, - Mul100 = 0x64, - Mul101 = 0x65, - Mul102 = 0x66, - Mul103 = 0x67, - Mul104 = 0x68, - Mul105 = 0x69, - Mul106 = 0x6a, - Mul107 = 0x6b, - Mul108 = 0x6c, - Mul109 = 0x6d, - Mul110 = 0x6e, - Mul111 = 0x6f, - Mul112 = 0x70, - Mul113 = 0x71, - Mul114 = 0x72, - Mul115 = 0x73, - Mul116 = 0x74, - Mul117 = 0x75, - Mul118 = 0x76, - Mul119 = 0x77, - Mul120 = 0x78, - Mul121 = 0x79, - Mul122 = 0x7a, - Mul123 = 0x7b, - Mul124 = 0x7c, - Mul125 = 0x7d, - Mul126 = 0x7e, - Mul127 = 0x7f, - _, - }; - - pub const PLLP = enum(u5) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, Div9 = 0x8, Div10 = 0x9, Div11 = 0xa, @@ -405273,1311 +386344,3053 @@ pub const types = struct { Div30 = 0x1d, Div31 = 0x1e, Div32 = 0x1f, - _, - }; - - pub const PLLQ = enum(u3) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - _, - }; - - pub const PLLR = enum(u3) { - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - _, - }; - - pub const PLLSRC = enum(u2) { - DISABLE = 0x0, - MSI = 0x1, - HSI = 0x2, - HSE = 0x3, + Div33 = 0x20, + Div34 = 0x21, + Div35 = 0x22, + Div36 = 0x23, + Div37 = 0x24, + Div38 = 0x25, + Div39 = 0x26, + Div40 = 0x27, + Div41 = 0x28, + Div42 = 0x29, + Div43 = 0x2a, + Div44 = 0x2b, + Div45 = 0x2c, + Div46 = 0x2d, + Div47 = 0x2e, + Div48 = 0x2f, + Div49 = 0x30, + Div50 = 0x31, + Div51 = 0x32, + Div52 = 0x33, + Div53 = 0x34, + Div54 = 0x35, + Div55 = 0x36, + Div56 = 0x37, + Div57 = 0x38, + Div58 = 0x39, + Div59 = 0x3a, + Div60 = 0x3b, + Div61 = 0x3c, + Div62 = 0x3d, + Div63 = 0x3e, + Div64 = 0x3f, + Div65 = 0x40, + Div66 = 0x41, + Div67 = 0x42, + Div68 = 0x43, + Div69 = 0x44, + Div70 = 0x45, + Div71 = 0x46, + Div72 = 0x47, + Div73 = 0x48, + Div74 = 0x49, + Div75 = 0x4a, + Div76 = 0x4b, + Div77 = 0x4c, + Div78 = 0x4d, + Div79 = 0x4e, + Div80 = 0x4f, + Div81 = 0x50, + Div82 = 0x51, + Div83 = 0x52, + Div84 = 0x53, + Div85 = 0x54, + Div86 = 0x55, + Div87 = 0x56, + Div88 = 0x57, + Div89 = 0x58, + Div90 = 0x59, + Div91 = 0x5a, + Div92 = 0x5b, + Div93 = 0x5c, + Div94 = 0x5d, + Div95 = 0x5e, + Div96 = 0x5f, + Div97 = 0x60, + Div98 = 0x61, + Div99 = 0x62, + Div100 = 0x63, + Div101 = 0x64, + Div102 = 0x65, + Div103 = 0x66, + Div104 = 0x67, + Div105 = 0x68, + Div106 = 0x69, + Div107 = 0x6a, + Div108 = 0x6b, + Div109 = 0x6c, + Div110 = 0x6d, + Div111 = 0x6e, + Div112 = 0x6f, + Div113 = 0x70, + Div114 = 0x71, + Div115 = 0x72, + Div116 = 0x73, + Div117 = 0x74, + Div118 = 0x75, + Div119 = 0x76, + Div120 = 0x77, + Div121 = 0x78, + Div122 = 0x79, + Div123 = 0x7a, + Div124 = 0x7b, + Div125 = 0x7c, + Div126 = 0x7d, + Div127 = 0x7e, + Div128 = 0x7f, }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, + pub const PLLM = enum(u6) { + Div1 = 0x1, + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + Div16 = 0x10, + Div17 = 0x11, + Div18 = 0x12, + Div19 = 0x13, + Div20 = 0x14, + Div21 = 0x15, + Div22 = 0x16, + Div23 = 0x17, + Div24 = 0x18, + Div25 = 0x19, + Div26 = 0x1a, + Div27 = 0x1b, + Div28 = 0x1c, + Div29 = 0x1d, + Div30 = 0x1e, + Div31 = 0x1f, + Div32 = 0x20, + Div33 = 0x21, + Div34 = 0x22, + Div35 = 0x23, + Div36 = 0x24, + Div37 = 0x25, + Div38 = 0x26, + Div39 = 0x27, + Div40 = 0x28, + Div41 = 0x29, + Div42 = 0x2a, + Div43 = 0x2b, + Div44 = 0x2c, + Div45 = 0x2d, + Div46 = 0x2e, + Div47 = 0x2f, + Div48 = 0x30, + Div49 = 0x31, + Div50 = 0x32, + Div51 = 0x33, + Div52 = 0x34, + Div53 = 0x35, + Div54 = 0x36, + Div55 = 0x37, + Div56 = 0x38, + Div57 = 0x39, + Div58 = 0x3a, + Div59 = 0x3b, + Div60 = 0x3c, + Div61 = 0x3d, + Div62 = 0x3e, _, }; - pub const RTCSEL = enum(u2) { - DISABLE = 0x0, - LSE = 0x1, - LSI = 0x2, - HSE = 0x3, - }; - - pub const SW = enum(u3) { - MSI = 0x0, - HSI = 0x1, - HSE = 0x2, - PLL1_R = 0x3, - LSI = 0x4, - LSE = 0x5, - _, + pub const PLLN = enum(u9) { + Mul4 = 0x3, + Mul5 = 0x4, + Mul6 = 0x5, + Mul7 = 0x6, + Mul8 = 0x7, + Mul9 = 0x8, + Mul10 = 0x9, + Mul11 = 0xa, + Mul12 = 0xb, + Mul13 = 0xc, + Mul14 = 0xd, + Mul15 = 0xe, + Mul16 = 0xf, + Mul17 = 0x10, + Mul18 = 0x11, + Mul19 = 0x12, + Mul20 = 0x13, + Mul21 = 0x14, + Mul22 = 0x15, + Mul23 = 0x16, + Mul24 = 0x17, + Mul25 = 0x18, + Mul26 = 0x19, + Mul27 = 0x1a, + Mul28 = 0x1b, + Mul29 = 0x1c, + Mul30 = 0x1d, + Mul31 = 0x1e, + Mul32 = 0x1f, + Mul33 = 0x20, + Mul34 = 0x21, + Mul35 = 0x22, + Mul36 = 0x23, + Mul37 = 0x24, + Mul38 = 0x25, + Mul39 = 0x26, + Mul40 = 0x27, + Mul41 = 0x28, + Mul42 = 0x29, + Mul43 = 0x2a, + Mul44 = 0x2b, + Mul45 = 0x2c, + Mul46 = 0x2d, + Mul47 = 0x2e, + Mul48 = 0x2f, + Mul49 = 0x30, + Mul50 = 0x31, + Mul51 = 0x32, + Mul52 = 0x33, + Mul53 = 0x34, + Mul54 = 0x35, + Mul55 = 0x36, + Mul56 = 0x37, + Mul57 = 0x38, + Mul58 = 0x39, + Mul59 = 0x3a, + Mul60 = 0x3b, + Mul61 = 0x3c, + Mul62 = 0x3d, + Mul63 = 0x3e, + Mul64 = 0x3f, + Mul65 = 0x40, + Mul66 = 0x41, + Mul67 = 0x42, + Mul68 = 0x43, + Mul69 = 0x44, + Mul70 = 0x45, + Mul71 = 0x46, + Mul72 = 0x47, + Mul73 = 0x48, + Mul74 = 0x49, + Mul75 = 0x4a, + Mul76 = 0x4b, + Mul77 = 0x4c, + Mul78 = 0x4d, + Mul79 = 0x4e, + Mul80 = 0x4f, + Mul81 = 0x50, + Mul82 = 0x51, + Mul83 = 0x52, + Mul84 = 0x53, + Mul85 = 0x54, + Mul86 = 0x55, + Mul87 = 0x56, + Mul88 = 0x57, + Mul89 = 0x58, + Mul90 = 0x59, + Mul91 = 0x5a, + Mul92 = 0x5b, + Mul93 = 0x5c, + Mul94 = 0x5d, + Mul95 = 0x5e, + Mul96 = 0x5f, + Mul97 = 0x60, + Mul98 = 0x61, + Mul99 = 0x62, + Mul100 = 0x63, + Mul101 = 0x64, + Mul102 = 0x65, + Mul103 = 0x66, + Mul104 = 0x67, + Mul105 = 0x68, + Mul106 = 0x69, + Mul107 = 0x6a, + Mul108 = 0x6b, + Mul109 = 0x6c, + Mul110 = 0x6d, + Mul111 = 0x6e, + Mul112 = 0x6f, + Mul113 = 0x70, + Mul114 = 0x71, + Mul115 = 0x72, + Mul116 = 0x73, + Mul117 = 0x74, + Mul118 = 0x75, + Mul119 = 0x76, + Mul120 = 0x77, + Mul121 = 0x78, + Mul122 = 0x79, + Mul123 = 0x7a, + Mul124 = 0x7b, + Mul125 = 0x7c, + Mul126 = 0x7d, + Mul127 = 0x7e, + Mul128 = 0x7f, + Mul129 = 0x80, + Mul130 = 0x81, + Mul131 = 0x82, + Mul132 = 0x83, + Mul133 = 0x84, + Mul134 = 0x85, + Mul135 = 0x86, + Mul136 = 0x87, + Mul137 = 0x88, + Mul138 = 0x89, + Mul139 = 0x8a, + Mul140 = 0x8b, + Mul141 = 0x8c, + Mul142 = 0x8d, + Mul143 = 0x8e, + Mul144 = 0x8f, + Mul145 = 0x90, + Mul146 = 0x91, + Mul147 = 0x92, + Mul148 = 0x93, + Mul149 = 0x94, + Mul150 = 0x95, + Mul151 = 0x96, + Mul152 = 0x97, + Mul153 = 0x98, + Mul154 = 0x99, + Mul155 = 0x9a, + Mul156 = 0x9b, + Mul157 = 0x9c, + Mul158 = 0x9d, + Mul159 = 0x9e, + Mul160 = 0x9f, + Mul161 = 0xa0, + Mul162 = 0xa1, + Mul163 = 0xa2, + Mul164 = 0xa3, + Mul165 = 0xa4, + Mul166 = 0xa5, + Mul167 = 0xa6, + Mul168 = 0xa7, + Mul169 = 0xa8, + Mul170 = 0xa9, + Mul171 = 0xaa, + Mul172 = 0xab, + Mul173 = 0xac, + Mul174 = 0xad, + Mul175 = 0xae, + Mul176 = 0xaf, + Mul177 = 0xb0, + Mul178 = 0xb1, + Mul179 = 0xb2, + Mul180 = 0xb3, + Mul181 = 0xb4, + Mul182 = 0xb5, + Mul183 = 0xb6, + Mul184 = 0xb7, + Mul185 = 0xb8, + Mul186 = 0xb9, + Mul187 = 0xba, + Mul188 = 0xbb, + Mul189 = 0xbc, + Mul190 = 0xbd, + Mul191 = 0xbe, + Mul192 = 0xbf, + Mul193 = 0xc0, + Mul194 = 0xc1, + Mul195 = 0xc2, + Mul196 = 0xc3, + Mul197 = 0xc4, + Mul198 = 0xc5, + Mul199 = 0xc6, + Mul200 = 0xc7, + Mul201 = 0xc8, + Mul202 = 0xc9, + Mul203 = 0xca, + Mul204 = 0xcb, + Mul205 = 0xcc, + Mul206 = 0xcd, + Mul207 = 0xce, + Mul208 = 0xcf, + Mul209 = 0xd0, + Mul210 = 0xd1, + Mul211 = 0xd2, + Mul212 = 0xd3, + Mul213 = 0xd4, + Mul214 = 0xd5, + Mul215 = 0xd6, + Mul216 = 0xd7, + Mul217 = 0xd8, + Mul218 = 0xd9, + Mul219 = 0xda, + Mul220 = 0xdb, + Mul221 = 0xdc, + Mul222 = 0xdd, + Mul223 = 0xde, + Mul224 = 0xdf, + Mul225 = 0xe0, + Mul226 = 0xe1, + Mul227 = 0xe2, + Mul228 = 0xe3, + Mul229 = 0xe4, + Mul230 = 0xe5, + Mul231 = 0xe6, + Mul232 = 0xe7, + Mul233 = 0xe8, + Mul234 = 0xe9, + Mul235 = 0xea, + Mul236 = 0xeb, + Mul237 = 0xec, + Mul238 = 0xed, + Mul239 = 0xee, + Mul240 = 0xef, + Mul241 = 0xf0, + Mul242 = 0xf1, + Mul243 = 0xf2, + Mul244 = 0xf3, + Mul245 = 0xf4, + Mul246 = 0xf5, + Mul247 = 0xf6, + Mul248 = 0xf7, + Mul249 = 0xf8, + Mul250 = 0xf9, + Mul251 = 0xfa, + Mul252 = 0xfb, + Mul253 = 0xfc, + Mul254 = 0xfd, + Mul255 = 0xfe, + Mul256 = 0xff, + Mul257 = 0x100, + Mul258 = 0x101, + Mul259 = 0x102, + Mul260 = 0x103, + Mul261 = 0x104, + Mul262 = 0x105, + Mul263 = 0x106, + Mul264 = 0x107, + Mul265 = 0x108, + Mul266 = 0x109, + Mul267 = 0x10a, + Mul268 = 0x10b, + Mul269 = 0x10c, + Mul270 = 0x10d, + Mul271 = 0x10e, + Mul272 = 0x10f, + Mul273 = 0x110, + Mul274 = 0x111, + Mul275 = 0x112, + Mul276 = 0x113, + Mul277 = 0x114, + Mul278 = 0x115, + Mul279 = 0x116, + Mul280 = 0x117, + Mul281 = 0x118, + Mul282 = 0x119, + Mul283 = 0x11a, + Mul284 = 0x11b, + Mul285 = 0x11c, + Mul286 = 0x11d, + Mul287 = 0x11e, + Mul288 = 0x11f, + Mul289 = 0x120, + Mul290 = 0x121, + Mul291 = 0x122, + Mul292 = 0x123, + Mul293 = 0x124, + Mul294 = 0x125, + Mul295 = 0x126, + Mul296 = 0x127, + Mul297 = 0x128, + Mul298 = 0x129, + Mul299 = 0x12a, + Mul300 = 0x12b, + Mul301 = 0x12c, + Mul302 = 0x12d, + Mul303 = 0x12e, + Mul304 = 0x12f, + Mul305 = 0x130, + Mul306 = 0x131, + Mul307 = 0x132, + Mul308 = 0x133, + Mul309 = 0x134, + Mul310 = 0x135, + Mul311 = 0x136, + Mul312 = 0x137, + Mul313 = 0x138, + Mul314 = 0x139, + Mul315 = 0x13a, + Mul316 = 0x13b, + Mul317 = 0x13c, + Mul318 = 0x13d, + Mul319 = 0x13e, + Mul320 = 0x13f, + Mul321 = 0x140, + Mul322 = 0x141, + Mul323 = 0x142, + Mul324 = 0x143, + Mul325 = 0x144, + Mul326 = 0x145, + Mul327 = 0x146, + Mul328 = 0x147, + Mul329 = 0x148, + Mul330 = 0x149, + Mul331 = 0x14a, + Mul332 = 0x14b, + Mul333 = 0x14c, + Mul334 = 0x14d, + Mul335 = 0x14e, + Mul336 = 0x14f, + Mul337 = 0x150, + Mul338 = 0x151, + Mul339 = 0x152, + Mul340 = 0x153, + Mul341 = 0x154, + Mul342 = 0x155, + Mul343 = 0x156, + Mul344 = 0x157, + Mul345 = 0x158, + Mul346 = 0x159, + Mul347 = 0x15a, + Mul348 = 0x15b, + Mul349 = 0x15c, + Mul350 = 0x15d, + Mul351 = 0x15e, + Mul352 = 0x15f, + Mul353 = 0x160, + Mul354 = 0x161, + Mul355 = 0x162, + Mul356 = 0x163, + Mul357 = 0x164, + Mul358 = 0x165, + Mul359 = 0x166, + Mul360 = 0x167, + Mul361 = 0x168, + Mul362 = 0x169, + Mul363 = 0x16a, + Mul364 = 0x16b, + Mul365 = 0x16c, + Mul366 = 0x16d, + Mul367 = 0x16e, + Mul368 = 0x16f, + Mul369 = 0x170, + Mul370 = 0x171, + Mul371 = 0x172, + Mul372 = 0x173, + Mul373 = 0x174, + Mul374 = 0x175, + Mul375 = 0x176, + Mul376 = 0x177, + Mul377 = 0x178, + Mul378 = 0x179, + Mul379 = 0x17a, + Mul380 = 0x17b, + Mul381 = 0x17c, + Mul382 = 0x17d, + Mul383 = 0x17e, + Mul384 = 0x17f, + Mul385 = 0x180, + Mul386 = 0x181, + Mul387 = 0x182, + Mul388 = 0x183, + Mul389 = 0x184, + Mul390 = 0x185, + Mul391 = 0x186, + Mul392 = 0x187, + Mul393 = 0x188, + Mul394 = 0x189, + Mul395 = 0x18a, + Mul396 = 0x18b, + Mul397 = 0x18c, + Mul398 = 0x18d, + Mul399 = 0x18e, + Mul400 = 0x18f, + Mul401 = 0x190, + Mul402 = 0x191, + Mul403 = 0x192, + Mul404 = 0x193, + Mul405 = 0x194, + Mul406 = 0x195, + Mul407 = 0x196, + Mul408 = 0x197, + Mul409 = 0x198, + Mul410 = 0x199, + Mul411 = 0x19a, + Mul412 = 0x19b, + Mul413 = 0x19c, + Mul414 = 0x19d, + Mul415 = 0x19e, + Mul416 = 0x19f, + Mul417 = 0x1a0, + Mul418 = 0x1a1, + Mul419 = 0x1a2, + Mul420 = 0x1a3, + Mul421 = 0x1a4, + Mul422 = 0x1a5, + Mul423 = 0x1a6, + Mul424 = 0x1a7, + Mul425 = 0x1a8, + Mul426 = 0x1a9, + Mul427 = 0x1aa, + Mul428 = 0x1ab, + Mul429 = 0x1ac, + Mul430 = 0x1ad, + Mul431 = 0x1ae, + Mul432 = 0x1af, + Mul433 = 0x1b0, + Mul434 = 0x1b1, + Mul435 = 0x1b2, + Mul436 = 0x1b3, + Mul437 = 0x1b4, + Mul438 = 0x1b5, + Mul439 = 0x1b6, + Mul440 = 0x1b7, + Mul441 = 0x1b8, + Mul442 = 0x1b9, + Mul443 = 0x1ba, + Mul444 = 0x1bb, + Mul445 = 0x1bc, + Mul446 = 0x1bd, + Mul447 = 0x1be, + Mul448 = 0x1bf, + Mul449 = 0x1c0, + Mul450 = 0x1c1, + Mul451 = 0x1c2, + Mul452 = 0x1c3, + Mul453 = 0x1c4, + Mul454 = 0x1c5, + Mul455 = 0x1c6, + Mul456 = 0x1c7, + Mul457 = 0x1c8, + Mul458 = 0x1c9, + Mul459 = 0x1ca, + Mul460 = 0x1cb, + Mul461 = 0x1cc, + Mul462 = 0x1cd, + Mul463 = 0x1ce, + Mul464 = 0x1cf, + Mul465 = 0x1d0, + Mul466 = 0x1d1, + Mul467 = 0x1d2, + Mul468 = 0x1d3, + Mul469 = 0x1d4, + Mul470 = 0x1d5, + Mul471 = 0x1d6, + Mul472 = 0x1d7, + Mul473 = 0x1d8, + Mul474 = 0x1d9, + Mul475 = 0x1da, + Mul476 = 0x1db, + Mul477 = 0x1dc, + Mul478 = 0x1dd, + Mul479 = 0x1de, + Mul480 = 0x1df, + Mul481 = 0x1e0, + Mul482 = 0x1e1, + Mul483 = 0x1e2, + Mul484 = 0x1e3, + Mul485 = 0x1e4, + Mul486 = 0x1e5, + Mul487 = 0x1e6, + Mul488 = 0x1e7, + Mul489 = 0x1e8, + Mul490 = 0x1e9, + Mul491 = 0x1ea, + Mul492 = 0x1eb, + Mul493 = 0x1ec, + Mul494 = 0x1ed, + Mul495 = 0x1ee, + Mul496 = 0x1ef, + Mul497 = 0x1f0, + Mul498 = 0x1f1, + Mul499 = 0x1f2, + Mul500 = 0x1f3, + Mul501 = 0x1f4, + Mul502 = 0x1f5, + Mul503 = 0x1f6, + Mul504 = 0x1f7, + Mul505 = 0x1f8, + Mul506 = 0x1f9, + Mul507 = 0x1fa, + Mul508 = 0x1fb, + Mul509 = 0x1fc, + Mul510 = 0x1fd, + Mul511 = 0x1fe, + Mul512 = 0x1ff, + _, }; - pub const TIM15SEL = enum(u1) { - PCLK1_TIM = 0x0, - PLL1_Q = 0x1, + pub const PLLRGE = enum(u2) { + /// Frequency is between 1 and 2 MHz + Range1 = 0x0, + /// Frequency is between 2 and 4 MHz + Range2 = 0x1, + /// Frequency is between 4 and 8 MHz + Range4 = 0x2, + /// Frequency is between 8 and 16 MHz + Range8 = 0x3, }; - pub const TIM1SEL = enum(u1) { - PCLK1_TIM = 0x0, + pub const PLLSRC = enum(u2) { + /// HSI selected as PLL clock + HSI = 0x0, + /// CSI selected as PLL clock + CSI = 0x1, + /// HSE selected as PLL clock + HSE = 0x2, + /// No clock sent to DIVMx dividers and PLLs + DISABLE = 0x3, + }; + + pub const PLLVCOSEL = enum(u1) { + /// VCO frequency range 192 to 836 MHz + WideVCO = 0x0, + /// VCO frequency range 150 to 420 MHz + MediumVCO = 0x1, + }; + + pub const PPRE = enum(u3) { + /// rcc_hclk not divided + Div1 = 0x0, + /// rcc_hclk divided by 2 + Div2 = 0x4, + /// rcc_hclk divided by 4 + Div4 = 0x5, + /// rcc_hclk divided by 8 + Div8 = 0x6, + /// rcc_hclk divided by 16 + Div16 = 0x7, + _, + }; + + pub const RNGSEL = enum(u2) { + /// HSI48 selected as peripheral clock + HSI48 = 0x0, + /// pll1_q selected as peripheral clock PLL1_Q = 0x1, + /// LSE selected as peripheral clock + LSE = 0x2, + /// LSI selected as peripheral clock + LSI = 0x3, }; - pub const USART1SEL = enum(u2) { + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, + }; + + pub const SAIASEL = enum(u3) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_p selected as peripheral clock + PLL3_P = 0x2, + /// i2s_ckin selected as peripheral clock + I2S_CKIN = 0x3, + /// PER selected as peripheral clock + PER = 0x4, + _, + }; + + pub const SAISEL = enum(u3) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_p selected as peripheral clock + PLL3_P = 0x2, + /// I2S_CKIN selected as peripheral clock + I2S_CKIN = 0x3, + /// PER selected as peripheral clock + PER = 0x4, + _, + }; + + pub const SDMMCSEL = enum(u1) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_r selected as peripheral clock + PLL2_R = 0x1, + }; + + pub const SPDIFRXSEL = enum(u2) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_r selected as peripheral clock + PLL2_R = 0x1, + /// pll3_r selected as peripheral clock + PLL3_R = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + }; + + pub const SPI45SEL = enum(u3) { + /// APB2 clock selected as peripheral clock + PCLK2 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// HSE selected as peripheral clock + HSE = 0x5, + _, + }; + + pub const SPI6SEL = enum(u3) { + /// rcc_pclk4 selected as peripheral clock + PCLK4 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// HSE selected as peripheral clock + HSE = 0x5, + _, + }; + + pub const STOPWUCK = enum(u1) { + /// HSI selected as wake up clock from system Stop + HSI = 0x0, + /// CSI selected as wake up clock from system Stop + CSI = 0x1, + }; + + pub const SW = enum(u3) { + /// HSI selected as system clock + HSI = 0x0, + /// CSI selected as system clock + CSI = 0x1, + /// HSE selected as system clock + HSE = 0x2, + /// PLL1 selected as system clock + PLL1_P = 0x3, + _, + }; + + pub const SWPMISEL = enum(u1) { + /// pclk selected as peripheral clock PCLK1 = 0x0, - SYS = 0x1, - HSI = 0x2, - LSE = 0x3, + /// hsi_ker selected as peripheral clock + HSI = 0x1, }; - pub const USART2SEL = enum(u2) { + pub const TIMPRE = enum(u1) { + /// Timer kernel clock equal to 2x pclk by default + DefaultX2 = 0x0, + /// Timer kernel clock equal to 4x pclk by default + DefaultX4 = 0x1, + }; + + pub const USART16910SEL = enum(u3) { + /// rcc_pclk2 selected as peripheral clock + PCLK2 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, + }; + + pub const USART234578SEL = enum(u3) { + /// rcc_pclk1 selected as peripheral clock PCLK1 = 0x0, - SYS = 0x1, - HSI = 0x2, - LSE = 0x3, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, }; - /// RCC address block description. + pub const USBSEL = enum(u2) { + /// Disable the kernel clock + DISABLE = 0x0, + /// pll1_q selected as peripheral clock + PLL1_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// HSI48 selected as peripheral clock + HSI48 = 0x3, + }; + + /// Reset and clock control pub const RCC = extern struct { - /// Clock control register. + /// clock control register CR: mmio.Mmio(packed struct(u32) { - /// MSI clock enable This bit is set and cleared by software. Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator Set by hardware when used directly or indirectly as system clock. - MSION: u1, - /// MSI clock ready flag This bit is set by hardware to indicate that the MSI oscillator is stable. Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles. - MSIRDY: u1, - /// MSI clock PLL enable Set and cleared by software to enable/ disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure (refer to RCC_CSR register). - MSIPLLEN: u1, - /// MSI clock range selection Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect. After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by MSISRANGE in CSR register. - MSIRGSEL: packed union { - raw: u1, - value: MSIRGSEL, - }, - /// MSI clock ranges These bits are configured by software to choose the frequency range of MSI when MSIRGSEL is set.12 frequency ranges are available: others: not allowed (hardware write protection) Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT ready (MSION=1 and MSIRDY=0). - MSIRANGE: packed union { - raw: u4, - value: MSIRANGE, - }, - /// HSI clock enable Set and cleared by software. Cleared by hardware to stop the HSI oscillator when entering Stop, Standby, or Shutdown mode. Forced by hardware to keep the HSI oscillator ON when it is used directly or indirectly as system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of the HSE oscillator used for system clock). + /// Internal high-speed clock enable HSION: u1, - /// HSI always enable for peripheral kernels. Set and cleared by software to force HSI ON even in Stop modes. The HSI can only feed USART1, USART2, CEC and I2C1 peripherals configured with HSI as kernel clock. Keeping the HSI ON in Stop mode allows avoiding to slow down the communication speed because of the HSI startup time. This bit has no effect on HSION value. + /// High Speed Internal clock enable in Stop mode HSIKERON: u1, - /// HSI clock ready flag Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI clock cycles. + /// HSI clock ready flag HSIRDY: u1, - /// HSI automatic start from Stop Set and cleared by software. When the system wake-up clock is MSI, this bit is used to wake up the HSI is parallel of the system wake-up. - HSIASFS: u1, - reserved16: u4, - /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. + /// HSI clock divider + HSIDIV: packed union { + raw: u2, + value: HSIDIV, + }, + /// HSI divider flag + HSIDIVF: u1, + reserved7: u1, + /// CSI clock enable + CSION: u1, + /// CSI clock ready flag + CSIRDY: u1, + /// CSI clock enable in Stop mode + CSIKERON: u1, + reserved12: u2, + /// RC48 clock enable + HSI48ON: u1, + /// RC48 clock ready flag + HSI48RDY: u1, + /// D1 domain clocks ready flag + D1CKRDY: u1, + /// D2 domain clocks ready flag + D2CKRDY: u1, + /// HSE clock enable HSEON: u1, - /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. + /// HSE clock ready flag HSERDY: u1, - /// HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + /// HSE clock bypass HSEBYP: u1, - /// Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. - CSSON: u1, + /// HSE Clock Security System enable + HSECSSON: u1, reserved24: u4, - /// PLL enable Set and cleared by software to enable the PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. + /// PLL1 enable PLLON: u1, - /// PLL clock ready flag Set by hardware to indicate that the PLL is locked. + /// PLL1 clock ready flag PLLRDY: u1, padding: u6, }), - /// Internal clock sources calibration register. - ICSCR: mmio.Mmio(packed struct(u32) { - /// MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value. - MSICAL: u8, - /// MSI clock trimming These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI. - MSITRIM: u8, - /// HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. - HSICAL: u8, - /// HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI. The default value is 64 when added to the HSICAL value, trim the HSI to 161MHz 1 11%. + /// RCC HSI configuration register + HSICFGR: mmio.Mmio(packed struct(u32) { + /// HSI clock calibration + HSICAL: u12, + reserved24: u12, + /// HSI clock trimming HSITRIM: u7, padding: u1, }), - /// Clock configuration register. + /// RCC Clock Recovery RC Register + CRRCR: mmio.Mmio(packed struct(u32) { + /// Internal RC 48 MHz clock calibration + HSI48CAL: u10, + padding: u22, + }), + /// RCC CSI configuration register + CSICFGR: mmio.Mmio(packed struct(u32) { + /// CSI clock calibration + CSICAL: u9, + reserved24: u15, + /// CSI clock trimming + CSITRIM: u6, + padding: u2, + }), + /// RCC Clock Configuration Register CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected. + /// System clock switch SW: packed union { raw: u3, value: SW, }, - /// System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved. + /// System clock switch status SWS: packed union { raw: u3, value: SW, }, - reserved8: u2, - /// AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1 Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Section14.1.4: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. - HPRE: packed union { - raw: u4, - value: HPRE, + /// System clock selection after a wake up from system Stop + STOPWUCK: packed union { + raw: u1, + value: STOPWUCK, }, - /// APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1. - PPRE: packed union { - raw: u3, - value: PPRE, + /// Kernel clock selection after a wake up from system Stop + STOPKERWUCK: packed union { + raw: u1, + value: STOPWUCK, }, - /// Wake-up from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=10) or a switch on HSE is requested (SW=10). - STOPWUCK: u1, - /// Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching. - MCO2SEL: packed union { + /// HSE division factor for RTC clock + RTCPRE: u6, + /// High Resolution Timer clock prescaler selection + HRTIMSEL: packed union { + raw: u1, + value: HRTIMSEL, + }, + /// Timers clocks prescaler selection + TIMPRE: packed union { + raw: u1, + value: TIMPRE, + }, + reserved18: u2, + /// MCO1 prescaler + MCO1PRE: packed union { raw: u4, - value: MCOSEL, + value: MCOPRE, }, - /// Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: ... Others: reserved It is highly recommended to set this field before the MCO2 output is enabled. + /// Micro-controller clock output 1 + MCO1SEL: packed union { + raw: u3, + value: MCO1SEL, + }, + /// MCO2 prescaler MCO2PRE: packed union { raw: u4, value: MCOPRE, }, - /// Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. - MCOSEL: packed union { + /// Micro-controller clock output 2 + MCO2SEL: packed union { + raw: u3, + value: MCO2SEL, + }, + }), + reserved24: [4]u8, + /// RCC Domain 1 Clock Configuration Register + D1CFGR: mmio.Mmio(packed struct(u32) { + /// D1 domain AHB prescaler + HPRE: packed union { raw: u4, - value: MCOSEL, + value: HPRE, }, - /// Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: ... Others: reserved It is highly recommended to set this field before the MCO output is enabled. - MCOPRE: packed union { + /// D1 domain APB3 prescaler + D1PPRE: packed union { + raw: u3, + value: PPRE, + }, + reserved8: u1, + /// D1 domain Core prescaler + D1CPRE: packed union { raw: u4, - value: MCOPRE, + value: HPRE, }, + padding: u20, }), - /// PLL configuration register. - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// PLL input clock source This bit is controlled by software to select PLL clock source, as follows: The bitfield can be written only when the PLL is disabled. When the PLL is not used, selecting 00 allows saving power. + /// RCC Domain 2 Clock Configuration Register + D2CFGR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// D2 domain APB1 prescaler + D2PPRE1: packed union { + raw: u3, + value: PPRE, + }, + reserved8: u1, + /// D2 domain APB2 prescaler + D2PPRE2: packed union { + raw: u3, + value: PPRE, + }, + padding: u21, + }), + /// RCC Domain 3 Clock Configuration Register + D3CFGR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// D3 domain APB4 prescaler + D3PPRE: packed union { + raw: u3, + value: PPRE, + }, + padding: u25, + }), + reserved40: [4]u8, + /// RCC PLLs Clock Source Selection Register + PLLCKSELR: mmio.Mmio(packed struct(u32) { + /// DIVMx and PLLs clock source selection PLLSRC: packed union { raw: u2, value: PLLSRC, }, reserved4: u2, - /// Division factor M of the PLL input clock divider This bit is controlled by software to divide the PLL input clock before the actual phase-locked loop, as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the PLL input frequency after the /M divider is between 2.66 and 161MHz. - PLLM: packed union { - raw: u3, + /// Prescaler for PLL1 + DIVM: packed union { + raw: u6, value: PLLM, }, - reserved8: u1, - /// PLL frequency multiplication factor N This bit is controlled by software to set the division factor of the fVCO feedback divider (that determines the PLL multiplication ratio) as follows: ... ... The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the VCO output frequency is between 96 and 3441MHz. + padding: u22, + }), + /// RCC PLLs Configuration Register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// PLL1 fractional latch enable + PLLFRACEN: u1, + /// PLL1 VCO selection + PLLVCOSEL: packed union { + raw: u1, + value: PLLVCOSEL, + }, + /// PLL1 input frequency range + PLLRGE: packed union { + raw: u2, + value: PLLRGE, + }, + reserved16: u12, + /// PLL1 DIVP divider output enable + DIVPEN: u1, + /// PLL1 DIVQ divider output enable + DIVQEN: u1, + /// PLL1 DIVR divider output enable + DIVREN: u1, + padding: u13, + }), + /// RCC PLL1 Dividers Configuration Register + PLLDIVR: mmio.Mmio(packed struct(u32) { + /// Multiplication factor for PLL1 VCO PLLN: packed union { - raw: u7, + raw: u9, value: PLLN, }, - reserved16: u1, - /// PLLPCLK clock output enable This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL: Disabling the PLLPCLK clock output, when not used, allows saving power. - PLLPEN: u1, - /// PLL VCO division factor P for PLLPCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor P as follows: ... The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock. + /// PLL DIVP division factor PLLP: packed union { - raw: u5, - value: PLLP, + raw: u7, + value: PLLDIV, }, - reserved24: u2, - /// PLLQCLK clock output enable This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL: Disabling the PLLQCLK clock output, when not used, allows saving power. - PLLQEN: u1, - /// PLL VCO division factor Q for PLLQCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock. + /// PLL DIVQ division factor PLLQ: packed union { - raw: u3, - value: PLLQ, + raw: u7, + value: PLLDIV, }, - /// PLLRCLK clock output enable This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL: This bit cannot be written when PLLRCLK output of the PLL is selected for system clock. Disabling the PLLRCLK clock output, when not used, allows saving power. - PLLREN: u1, - /// PLL VCO division factor R for PLLRCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor R as follows: The bitfield can be written only when the PLL is disabled. The PLLRCLK clock can be selected as system clock. Caution: The software must set this bitfield so as not to exceed 122MHz on this clock. + reserved24: u1, + /// PLL DIVR division factor PLLR: packed union { - raw: u3, - value: PLLR, + raw: u7, + value: PLLDIV, }, + padding: u1, }), - reserved24: [8]u8, - /// Clock interrupt enable register. - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:. - LSIRDYIE: u1, - /// LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:. - LSERDYIE: u1, - /// MSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. - MSIRDYIE: u1, - /// HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization:. - HSIRDYIE: u1, - /// HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:. - HSERDYIE: u1, - /// PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock:. - PLLRDYIE: u1, - reserved9: u3, - /// LSE clock security system interrupt enable Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. - LSECSSIE: u1, - /// HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. + /// RCC PLL1 Fractional Divider Register + PLLFRACR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Fractional part of the multiplication factor for PLL VCO + FRACN: u13, + padding: u16, + }), + reserved76: [20]u8, + /// RCC Domain 1 Kernel Clock Configuration Register + D1CCIPR: mmio.Mmio(packed struct(u32) { + /// FMC kernel clock source selection + FMCSEL: packed union { + raw: u2, + value: FMCSEL, + }, + reserved4: u2, + /// OCTOSPI kernel clock source selection + OCTOSPISEL: packed union { + raw: u2, + value: FMCSEL, + }, + reserved8: u2, + /// DSI clock source selection (not available on all chips) + DSISEL: packed union { + raw: u1, + value: DSISEL, + }, + reserved16: u7, + /// SDMMC kernel clock source selection + SDMMCSEL: packed union { + raw: u1, + value: SDMMCSEL, + }, + reserved28: u11, + /// per_ck clock source selection + PERSEL: packed union { + raw: u2, + value: PERSEL, + }, + padding: u2, + }), + /// RCC Domain 2 Kernel Clock Configuration Register + D2CCIP1R: mmio.Mmio(packed struct(u32) { + /// SAI1 and DFSDM1 kernel Aclk clock source selection + SAI1SEL: packed union { + raw: u3, + value: SAISEL, + }, + reserved6: u3, + /// SAI2 and SAI3 kernel clock source selection + SAI23SEL: packed union { + raw: u3, + value: SAISEL, + }, + reserved12: u3, + /// SPI/I2S1,2 and 3 kernel clock source selection + SPI123SEL: packed union { + raw: u3, + value: SAISEL, + }, + reserved16: u1, + /// SPI4 and 5 kernel clock source selection + SPI45SEL: packed union { + raw: u3, + value: SPI45SEL, + }, + reserved20: u1, + /// SPDIFRX kernel clock source selection + SPDIFRXSEL: packed union { + raw: u2, + value: SPDIFRXSEL, + }, + reserved24: u2, + /// DFSDM1 kernel Clk clock source selection + DFSDM1SEL: packed union { + raw: u1, + value: DFSDMSEL, + }, + reserved28: u3, + /// FDCAN kernel clock source selection + FDCANSEL: packed union { + raw: u2, + value: FDCANSEL, + }, + reserved31: u1, + /// SWPMI kernel clock source selection + SWPMISEL: packed union { + raw: u1, + value: SWPMISEL, + }, + }), + /// RCC Domain 2 Kernel Clock Configuration Register + D2CCIP2R: mmio.Mmio(packed struct(u32) { + /// USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection + USART234578SEL: packed union { + raw: u3, + value: USART234578SEL, + }, + /// USART1, 6, 9 and 10 kernel clock source selection + USART16910SEL: packed union { + raw: u3, + value: USART16910SEL, + }, + reserved8: u2, + /// RNG kernel clock source selection + RNGSEL: packed union { + raw: u2, + value: RNGSEL, + }, + reserved12: u2, + /// I2C1,2,3 kernel clock source selection + I2C1235SEL: packed union { + raw: u2, + value: I2C1235SEL, + }, + reserved20: u6, + /// USBOTG 1 and 2 kernel clock source selection + USBSEL: packed union { + raw: u2, + value: USBSEL, + }, + /// HDMI-CEC kernel clock source selection + CECSEL: packed union { + raw: u2, + value: CECSEL, + }, + reserved28: u4, + /// LPTIM1 kernel clock source selection + LPTIM1SEL: packed union { + raw: u3, + value: LPTIM1SEL, + }, + padding: u1, + }), + /// RCC Domain 3 Kernel Clock Configuration Register + D3CCIPR: mmio.Mmio(packed struct(u32) { + /// LPUART1 kernel clock source selection + LPUART1SEL: packed union { + raw: u3, + value: LPUARTSEL, + }, + reserved8: u5, + /// I2C4 kernel clock source selection + I2C4SEL: packed union { + raw: u2, + value: I2C4SEL, + }, + /// LPTIM2 kernel clock source selection + LPTIM2SEL: packed union { + raw: u3, + value: LPTIM2SEL, + }, + /// LPTIM3,4,5 kernel clock source selection + LPTIM345SEL: packed union { + raw: u3, + value: LPTIM2SEL, + }, + /// SAR ADC kernel clock source selection + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, + reserved21: u3, + /// Sub-Block A of SAI4 kernel clock source selection + SAI4ASEL: packed union { + raw: u3, + value: SAIASEL, + }, + /// Sub-Block B of SAI4 kernel clock source selection + SAI4BSEL: packed union { + raw: u3, + value: SAIASEL, + }, + /// DFSDM2 kernel clock source selection + DFSDM2SEL: u1, + /// SPI6 kernel clock source selection + SPI6SEL: packed union { + raw: u3, + value: SPI6SEL, + }, + padding: u1, + }), + reserved96: [4]u8, + /// RCC Clock Source Interrupt Enable Register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready Interrupt Enable + LSIRDYIE: u1, + /// LSE ready Interrupt Enable + LSERDYIE: u1, + /// HSI ready Interrupt Enable + HSIRDYIE: u1, + /// HSE ready Interrupt Enable + HSERDYIE: u1, + /// CSI ready Interrupt Enable + CSIRDYIE: u1, + /// RC48 ready Interrupt Enable HSI48RDYIE: u1, - padding: u21, + /// PLL1 ready Interrupt Enable + PLLRDYIE: u1, + reserved9: u2, + /// LSE clock security system Interrupt Enable + LSECSSIE: u1, + padding: u22, }), - /// Clock interrupt flag register. + /// RCC Clock Source Interrupt Flag Register CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. + /// LSI ready Interrupt Flag LSIRDYF: u1, - /// LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. + /// LSE ready Interrupt Flag LSERDYF: u1, - /// MSI ready interrupt flag Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set. Cleared by software setting the MSIRDYC bit. - MSIRDYF: u1, - /// HSI ready interrupt flag Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. + /// HSI ready Interrupt Flag HSIRDYF: u1, - /// HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit. + /// HSE ready Interrupt Flag HSERDYF: u1, - /// PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYIE is set. Cleared by software setting the PLLRDYC bit. + /// CSI ready Interrupt Flag + CSIRDY: u1, + /// RC48 ready Interrupt Flag + HSI48RDYF: u1, + /// PLL1 ready Interrupt Flag PLLRDYF: u1, - reserved8: u2, - /// HSE clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. - CSSF: u1, - /// LSE clock security system interrupt flag Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit. + reserved9: u2, + /// LSE clock security system Interrupt Flag LSECSSF: u1, - /// HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to RCC clock recovery RC register (RCC_CRRCR)). Cleared by software setting the HSI48RDYC bit. - HSI48RDYF: u1, + /// HSE clock security system Interrupt Flag + HSECSSF: u1, padding: u21, }), - /// Clock interrupt clear register. + /// RCC Clock Source Interrupt Clear Register CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. + /// LSI ready Interrupt Clear LSIRDYC: u1, - /// LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. + /// LSE ready Interrupt Clear LSERDYC: u1, - /// MSI ready interrupt clear This bit is set by software to clear the MSIRDYF flag. - MSIRDYC: u1, - /// HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag. + /// HSI ready Interrupt Clear HSIRDYC: u1, - /// HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. + /// HSE ready Interrupt Clear HSERDYC: u1, - /// PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. + /// CSI ready Interrupt Clear + HSE_ready_Interrupt_Clear: u1, + /// RC48 ready Interrupt Clear + HSI48RDYC: u1, + /// PLL1 ready Interrupt Clear PLLRDYC: u1, - reserved8: u2, - /// Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag. - CSSC: u1, - /// LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag. + reserved9: u2, + /// LSE clock security system Interrupt Clear LSECSSC: u1, - /// HSI48 oscillator ready interrupt clear This bit is set by software to clear the HSI48RDYF flag. - HSI48RDYC: u1, + /// HSE clock security system Interrupt Clear + HSECSSC: u1, padding: u21, }), - reserved40: [4]u8, - /// AHB peripheral reset register. - AHBRSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 and DMAMUX reset Set and cleared by software. + reserved112: [4]u8, + /// RCC Backup Domain Control Register + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enabled + LSEON: u1, + /// LSE oscillator ready + LSERDY: u1, + /// LSE oscillator bypass + LSEBYP: u1, + /// LSE oscillator driving capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// LSE clock security system enable + LSECSSON: u1, + /// LSE clock security system failure detection + LSECSSD: u1, + reserved8: u1, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// VSwitch domain software reset + BDRST: u1, + padding: u15, + }), + /// RCC Clock Control and Status Register + CSR: mmio.Mmio(packed struct(u32) { + /// LSI oscillator enable + LSION: u1, + /// LSI oscillator ready + LSIRDY: u1, + padding: u30, + }), + reserved124: [4]u8, + /// RCC AHB3 Reset Register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// MDMA block reset + MDMARST: u1, + reserved4: u3, + /// DMA2D block reset + DMA2DRST: u1, + /// JPGDEC block reset + JPGDECRST: u1, + reserved12: u6, + /// FMC block reset + FMCRST: u1, + reserved14: u1, + /// OCTOSPI1 and OCTOSPI1 delay block reset + OCTOSPI1RST: u1, + reserved16: u1, + /// SDMMC1 and SDMMC1 delay block reset + SDMMC1RST: u1, + reserved19: u2, + /// OCTOSPI2 and OCTOSPI2 delay block reset + OCTOSPI2RST: u1, + reserved21: u1, + /// OCTOSPI IO manager reset + IOMNGRRST: u1, + /// OTFDEC1 reset + OTFD1RST: u1, + /// OTFDEC2 reset + OTFD2RST: u1, + reserved31: u7, + /// CPU reset + CPURST: u1, + }), + /// RCC AHB1 Peripheral Reset Register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// DMA1 block reset DMA1RST: u1, - /// DMA2 and DMAMUX reset Set and cleared by software. + /// DMA2 block reset DMA2RST: u1, - reserved8: u6, - /// Flash memory interface reset Set and cleared by software. This bit can only be set when the flash memory is in power down mode. - FLASHRST: u1, - reserved12: u3, - /// CRC reset Set and cleared by software. - CRCRST: u1, - reserved16: u3, - /// AES hardware accelerator reset Set and cleared by software. - AESRST: u1, - reserved18: u1, - /// Random number generator reset Set and cleared by software. + reserved5: u3, + /// ADC1&2 block reset + ADC12RST: u1, + reserved14: u8, + /// ART block reset + ARTRST: u1, + /// ETH block reset + ETHRST: u1, + reserved25: u9, + /// USB_OTG_HS block reset + USB_OTG_HSRST: u1, + reserved27: u1, + /// USB_OTG_FS block reset + USB_OTG_FSRST: u1, + padding: u4, + }), + /// RCC AHB2 Peripheral Reset Register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// DCMI block reset + DCMIRST: u1, + reserved4: u3, + /// CRYPography block reset + CRYPRST: u1, + /// Hash block reset + HASHRST: u1, + /// Random Number Generator block reset RNGRST: u1, - reserved24: u5, - /// Touch sensing controller reset Set and cleared by software. - TSCRST: u1, - padding: u7, + reserved9: u2, + /// SDMMC2 and SDMMC2 Delay block reset + SDMMC2RST: u1, + reserved16: u6, + /// FMAC reset + FMACRST: u1, + /// CORDIC reset + CORDICRST: u1, + padding: u14, }), - /// I/O port reset register. - GPIORSTR: mmio.Mmio(packed struct(u32) { - /// I/O port A reset This bit is set and cleared by software. + /// RCC AHB4 Peripheral Reset Register + AHB4RSTR: mmio.Mmio(packed struct(u32) { + /// GPIO block reset GPIOARST: u1, - /// I/O port B reset This bit is set and cleared by software. + /// GPIO block reset GPIOBRST: u1, - /// I/O port C reset This bit is set and cleared by software. + /// GPIO block reset GPIOCRST: u1, - /// I/O port D reset This bit is set and cleared by software. + /// GPIO block reset GPIODRST: u1, - /// I/O port E reset This bit is set and cleared by software. + /// GPIO block reset GPIOERST: u1, - /// I/O port F reset This bit is set and cleared by software. + /// GPIO block reset GPIOFRST: u1, - padding: u26, + /// GPIO block reset + GPIOGRST: u1, + /// GPIO block reset + GPIOHRST: u1, + /// GPIO block reset + GPIOIRST: u1, + /// GPIO block reset + GPIOJRST: u1, + /// GPIO block reset + GPIOKRST: u1, + reserved19: u8, + /// CRC block reset + CRCRST: u1, + reserved21: u1, + /// BDMA block reset + BDMARST: u1, + reserved24: u2, + /// ADC3 block reset + ADC3RST: u1, + /// HSEM block reset + HSEMRST: u1, + padding: u6, }), - reserved56: [8]u8, - /// APB peripheral reset register 1. - APBRSTR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer reset Set and cleared by software. + /// RCC APB3 Peripheral Reset Register + APB3RSTR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC block reset + LTDCRST: u1, + /// DSI block reset + DSIRST: u1, + padding: u27, + }), + /// RCC APB1 Peripheral Reset Register + APB1LRSTR: mmio.Mmio(packed struct(u32) { + /// TIM block reset TIM2RST: u1, - /// TIM3 timer reset Set and cleared by software. + /// TIM block reset TIM3RST: u1, - reserved4: u2, - /// TIM6 timer reset Set and cleared by software. + /// TIM block reset + TIM4RST: u1, + /// TIM block reset + TIM5RST: u1, + /// TIM block reset TIM6RST: u1, - /// TIM7 timer reset Set and cleared by software. + /// TIM block reset TIM7RST: u1, - reserved7: u1, - /// LPUART2 reset Set and cleared by software. - LPUART2RST: u1, - reserved9: u1, - /// LCD reset(1) Set and cleared by software. - LCDRST: u1, - reserved12: u2, - /// LPUART3 reset(1) Set and cleared by software. - LPUART3RST: u1, - /// USB reset(1) Set and cleared by software. - USBRST: u1, - /// SPI2 reset Set and cleared by software. + /// TIM block reset + TIM12RST: u1, + /// TIM block reset + TIM13RST: u1, + /// TIM block reset + TIM14RST: u1, + /// TIM block reset + LPTIM1RST: u1, + reserved14: u4, + /// SPI2 block reset SPI2RST: u1, - /// SPI3 reset(1) Set and cleared by software. + /// SPI3 block reset SPI3RST: u1, - /// CRS reset(1) Set and cleared by software. - CRSRST: u1, - /// USART2 reset Set and cleared by software. + /// SPDIFRX block reset + SPDIFRXRST: u1, + /// USART2 block reset USART2RST: u1, - /// USART3 reset Set and cleared by software. + /// USART3 block reset USART3RST: u1, - /// USART4 reset Set and cleared by software. - USART4RST: u1, - /// LPUART1 reset Set and cleared by software. - LPUART1RST: u1, - /// I2C1 reset Set and cleared by software. + /// UART4 block reset + UART4RST: u1, + /// UART5 block reset + UART5RST: u1, + /// I2C1 block reset I2C1RST: u1, - /// I2C2 reset Set and cleared by software. + /// I2C2 block reset I2C2RST: u1, - /// I2C3 reset Set and cleared by software. + /// I2C3 block reset I2C3RST: u1, - /// OPAMP reset Set and cleared by software. + reserved25: u1, + /// I2C5 block reset + I2C5RST: u1, + reserved27: u1, + /// HDMI-CEC block reset + CECRST: u1, + reserved29: u1, + /// DAC1 and 2 Blocks Reset + DAC12RST: u1, + /// UART7 block reset + UART7RST: u1, + /// UART8 block reset + UART8RST: u1, + }), + /// RCC APB1 Peripheral Reset Register + APB1HRSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clock Recovery System reset + CRSRST: u1, + /// SWPMI block reset + SWPMIRST: u1, + reserved4: u1, + /// OPAMP block reset OPAMPRST: u1, - /// I2C4 reset(1) Set and cleared by software. + /// MDIOS block reset + MDIOSRST: u1, + reserved8: u2, + /// FDCAN block reset + FDCANRST: u1, + reserved24: u15, + /// TIM23 block reset + TIM23RST: u1, + /// TIM24 block reset + TIM24RST: u1, + padding: u6, + }), + /// RCC APB2 Peripheral Reset Register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// TIM1 block reset + TIM1RST: u1, + /// TIM8 block reset + TIM8RST: u1, + reserved4: u2, + /// USART1 block reset + USART1RST: u1, + /// USART6 block reset + USART6RST: u1, + /// UART9 block reset + UART9RST: u1, + /// USART10 block reset + USART10RST: u1, + reserved12: u4, + /// SPI1 block reset + SPI1RST: u1, + /// SPI4 block reset + SPI4RST: u1, + reserved16: u2, + /// TIM15 block reset + TIM15RST: u1, + /// TIM16 block reset + TIM16RST: u1, + /// TIM17 block reset + TIM17RST: u1, + reserved20: u1, + /// SPI5 block reset + SPI5RST: u1, + reserved22: u1, + /// SAI1 block reset + SAI1RST: u1, + /// SAI2 block reset + SAI2RST: u1, + /// SAI3 block reset + SAI3RST: u1, + reserved28: u3, + /// DFSDM1 block reset + DFSDM1RST: u1, + /// HRTIM block reset + HRTIMRST: u1, + padding: u2, + }), + /// RCC APB4 Peripheral Reset Register + APB4RSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG block reset + SYSCFGRST: u1, + reserved3: u1, + /// LPUART1 block reset + LPUART1RST: u1, + reserved5: u1, + /// SPI6 block reset + SPI6RST: u1, + reserved7: u1, + /// I2C4 block reset I2C4RST: u1, - /// LPTIM3 reset Set and cleared by software. + reserved9: u1, + /// LPTIM2 block reset + LPTIM2RST: u1, + /// LPTIM3 block reset LPTIM3RST: u1, + /// LPTIM4 block reset + LPTIM4RST: u1, + /// LPTIM5 block reset + LPTIM5RST: u1, + /// DAC2 (containing one converter) reset + DAC2RST: u1, + /// COMP12 Blocks Reset + COMP12RST: u1, + /// VREF block reset + VREFRST: u1, + reserved21: u5, + /// SAI4 block reset + SAI4RST: u1, + reserved26: u4, + /// Digital temperature sensor block reset + DTSRST: u1, + padding: u5, + }), + /// Global Control Register + GCR: mmio.Mmio(packed struct(u32) { + /// WWDG1 reset scope control + WW1RSC: u1, + /// WWDG2 reset scope control + WW2RSC: u1, + /// Force allow CPU1 to boot + BOOT_C1: u1, + /// Force allow CPU2 to boot + BOOT_C2: u1, + padding: u28, + }), + reserved168: [4]u8, + /// RCC D3 Autonomous mode Register + D3AMR: mmio.Mmio(packed struct(u32) { + /// BDMA and DMAMUX Autonomous mode enable + BDMAAMEN: u1, + reserved3: u2, + /// LPUART1 Autonomous mode enable + LPUART1AMEN: u1, + reserved5: u1, + /// SPI6 Autonomous mode enable + SPI6AMEN: u1, + reserved7: u1, + /// I2C4 Autonomous mode enable + I2C4AMEN: u1, + reserved9: u1, + /// LPTIM2 Autonomous mode enable + LPTIM2AMEN: u1, + /// LPTIM3 Autonomous mode enable + LPTIM3AMEN: u1, + /// LPTIM4 Autonomous mode enable + LPTIM4AMEN: u1, + /// LPTIM5 Autonomous mode enable + LPTIM5AMEN: u1, + /// DAC2 (containing one converter) Autonomous mode enable + DAC2AMEN: u1, + /// COMP12 Autonomous mode enable + COMP12AMEN: u1, + /// VREF Autonomous mode enable + VREFAMEN: u1, + /// RTC Autonomous mode enable + RTCAMEN: u1, + reserved19: u2, + /// CRC Autonomous mode enable + CRCAMEN: u1, + reserved21: u1, + /// SAI4 Autonomous mode enable + SAI4AMEN: u1, + reserved24: u2, + /// ADC3 Autonomous mode enable + ADC3AMEN: u1, + reserved26: u1, + /// Digital temperature sensor Autonomous mode enable + DTSAMEN: u1, reserved28: u1, - /// Power interface reset Set and cleared by software. - PWRRST: u1, - /// DAC1 interface reset Set and cleared by software. - DAC1RST: u1, - /// Low Power Timer 2 reset Set and cleared by software. - LPTIM2RST: u1, - /// Low Power Timer 1 reset Set and cleared by software. - LPTIM1RST: u1, + /// Backup RAM Autonomous mode enable + BKPSRAMAMEN: u1, + /// SRAM4 Autonomous mode enable + SRAM4AMEN: u1, + padding: u2, }), - reserved64: [4]u8, - /// APB peripheral reset register 2. - APBRSTR2: mmio.Mmio(packed struct(u32) { - /// SYSCFG, COMP and VREFBUF reset Set and cleared by software. - SYSCFGRST: u1, - reserved11: u10, - /// TIM1 timer reset Set and cleared by software. - TIM1RST: u1, - /// SPI1 reset Set and cleared by software. - SPI1RST: u1, + reserved208: [36]u8, + /// RCC Reset Status Register + RSR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Remove reset flag + RMVF: u1, + /// CPU reset flag + CPURSTF: u1, + reserved19: u1, + /// D1 domain power switch reset flag + D1RSTF: u1, + /// D2 domain power switch reset flag + D2RSTF: u1, + /// BOR reset flag + BORRSTF: u1, + /// Pin reset flag (NRST) + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// System reset from CPU reset flag + SFTRSTF: u1, + reserved26: u1, + /// Independent Watchdog reset flag + IWDG1RSTF: u1, + reserved28: u1, + /// Window Watchdog reset flag + WWDG1RSTF: u1, + reserved30: u1, + /// Reset due to illegal D1 DStandby or CPU CStop flag + LPWRRSTF: u1, + padding: u1, + }), + /// RCC AHB3 Clock Register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// MDMA Peripheral Clock Enable + MDMAEN: u1, + reserved4: u3, + /// DMA2D Peripheral Clock Enable + DMA2DEN: u1, + /// JPGDEC Peripheral Clock Enable + JPGDECEN: u1, + reserved12: u6, + /// FMC Peripheral Clocks Enable + FMCEN: u1, reserved14: u1, - /// USART1 reset Set and cleared by software. - USART1RST: u1, + /// OCTOSPI2 and OCTOSPI2 delay block enable + OCTOSPI1EN: u1, reserved16: u1, - /// TIM15 timer reset Set and cleared by software. - TIM15RST: u1, - /// TIM16 timer reset Set and cleared by software. - TIM16RST: u1, - reserved20: u2, - /// ADC reset Set and cleared by software. - ADCRST: u1, - padding: u11, + /// SDMMC1 and SDMMC1 Delay Clock Enable + SDMMC1EN: u1, + reserved19: u2, + /// OCTOSPI2 and OCTOSPI2 delay block enable + OCTOSPI2EN: u1, + reserved21: u1, + /// OCTOSPI IO manager enable + IOMNGREN: u1, + /// OTFDEC1 enable + OTFD1EN: u1, + /// OTFDEC2 enable + OTFD2EN: u1, + reserved28: u4, + /// D1 DTCM1 block enable + DTCM1EN: u1, + /// D1 DTCM2 block enable + DTCM2EN: u1, + /// D1 ITCM block enable + ITCM1EN: u1, + /// AXISRAM block enable + AXISRAMEN: u1, }), - reserved72: [4]u8, - /// AHB peripheral clock enable register. - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled. + /// RCC AHB1 Clock Register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// DMA1 Clock Enable DMA1EN: u1, - /// DMA2 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled. + /// DMA2 Clock Enable DMA2EN: u1, - reserved8: u6, - /// Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the flash memory is in power down mode. - FLASHEN: u1, - reserved12: u3, - /// CRC clock enable Set and cleared by software. - CRCEN: u1, - reserved16: u3, - /// AES hardware accelerator Set and cleared by software. - AESEN: u1, - reserved18: u1, - /// Random number generator clock enable Set and cleared by software. + reserved5: u3, + /// ADC1/2 Peripheral Clocks Enable + ADC12EN: u1, + reserved14: u8, + /// ART Clock Enable + ARTEN: u1, + /// Ethernet MAC bus interface Clock Enable + ETHEN: u1, + /// Ethernet Transmission Clock Enable + ETHTXEN: u1, + /// Ethernet Reception Clock Enable + ETHRXEN: u1, + reserved25: u7, + /// USB_OTG_HS Peripheral Clocks Enable + USB_OTG_HSEN: u1, + /// USB_OTG_HS ULPI clock enable + USB_OTG_HS_ULPIEN: u1, + /// USB_OTG_FS Peripheral Clocks Enable + USB_OTG_FSEN: u1, + /// USB_OTG_FS ULPI clock enable + USB_OTG_FS_ULPIEN: u1, + padding: u3, + }), + /// RCC AHB2 Clock Register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// DCMI peripheral clock + DCMIEN: u1, + reserved4: u3, + /// CRYP peripheral clock enable + CRYPEN: u1, + /// HASH peripheral clock enable + HASHEN: u1, + /// RNG peripheral clocks enable RNGEN: u1, - reserved24: u5, - /// Touch sensing controller clock enable Set and cleared by software. - TSCEN: u1, - padding: u7, + reserved9: u2, + /// SDMMC2 and SDMMC2 delay clock enable + SDMMC2EN: u1, + reserved16: u6, + /// FMAC enable + FMACEN: u1, + /// CORDIC enable + CORDICEN: u1, + reserved29: u11, + /// SRAM1 block enable + SRAM1EN: u1, + /// SRAM2 block enable + SRAM2EN: u1, + /// SRAM3 block enable + SRAM3EN: u1, }), - /// I/O port clock enable register. - GPIOENR: mmio.Mmio(packed struct(u32) { - /// I/O port A clock enable This bit is set and cleared by software. + /// RCC AHB4 Clock Register + AHB4ENR: mmio.Mmio(packed struct(u32) { + /// 0GPIO peripheral clock enable GPIOAEN: u1, - /// I/O port B clock enable This bit is set and cleared by software. + /// 0GPIO peripheral clock enable GPIOBEN: u1, - /// I/O port C clock enable This bit is set and cleared by software. + /// 0GPIO peripheral clock enable GPIOCEN: u1, - /// I/O port D clock enable This bit is set and cleared by software. + /// 0GPIO peripheral clock enable GPIODEN: u1, - /// I/O port E clock enable(1) This bit is set and cleared by software. + /// 0GPIO peripheral clock enable GPIOEEN: u1, - /// I/O port F clock enable This bit is set and cleared by software. + /// 0GPIO peripheral clock enable GPIOFEN: u1, - padding: u26, + /// 0GPIO peripheral clock enable + GPIOGEN: u1, + /// 0GPIO peripheral clock enable + GPIOHEN: u1, + /// 0GPIO peripheral clock enable + GPIOIEN: u1, + /// 0GPIO peripheral clock enable + GPIOJEN: u1, + /// 0GPIO peripheral clock enable + GPIOKEN: u1, + reserved19: u8, + /// CRC peripheral clock enable + CRCEN: u1, + reserved21: u1, + /// BDMA and DMAMUX2 Clock Enable + BDMAEN: u1, + reserved24: u2, + /// ADC3 Peripheral Clocks Enable + ADC3EN: u1, + /// HSEM peripheral clock enable + HSEMEN: u1, + reserved28: u2, + /// Backup RAM Clock Enable + BKPSRAMEN: u1, + padding: u3, }), - /// Debug configuration register. - DBGCFGR: mmio.Mmio(packed struct(u32) { - /// Debug support clock enable Set and cleared by software. - DBGEN: u1, - /// Debug support reset Set and cleared by software. - DBGRST: u1, - padding: u30, + /// RCC APB3 Clock Register + APB3ENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC peripheral clock enable + LTDCEN: u1, + /// DSI Peripheral clocks enable + DSIEN: u1, + reserved6: u1, + /// WWDG1 Clock Enable + WWDG1EN: u1, + padding: u25, }), - reserved88: [4]u8, - /// APB peripheral clock enable register 1. - APBENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clock enable Set and cleared by software. + /// RCC APB1 Clock Register + APB1LENR: mmio.Mmio(packed struct(u32) { + /// TIM peripheral clock enable TIM2EN: u1, - /// TIM3 timer clock enable Set and cleared by software. + /// TIM peripheral clock enable TIM3EN: u1, - reserved4: u2, - /// TIM6 timer clock enable Set and cleared by software. + /// TIM peripheral clock enable + TIM4EN: u1, + /// TIM peripheral clock enable + TIM5EN: u1, + /// TIM peripheral clock enable TIM6EN: u1, - /// TIM7 timer clock enable Set and cleared by software. + /// TIM peripheral clock enable TIM7EN: u1, - reserved7: u1, - /// LPUART2 clock enable Set and cleared by software. - LPUART2EN: u1, - reserved9: u1, - /// LCD clock enable(1) Set and cleared by software. - LCDEN: u1, - /// RTC APB clock enable Set and cleared by software. - RTCAPBEN: u1, - /// WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0. - WWDGEN: u1, - /// LPUART3 clock enable Set and cleared by software. - LPUART3EN: u1, - /// USB clock enable(1) Set and cleared by software. - USBEN: u1, - /// SPI2 clock enable Set and cleared by software. + /// TIM peripheral clock enable + TIM12EN: u1, + /// TIM peripheral clock enable + TIM13EN: u1, + /// TIM peripheral clock enable + TIM14EN: u1, + /// LPTIM1 Peripheral Clocks Enable + LPTIM1EN: u1, + reserved11: u1, + /// WWDG2 peripheral clock enable + WWDG2EN: u1, + reserved14: u2, + /// SPI2 Peripheral Clocks Enable SPI2EN: u1, - /// SPI3 clock enable(1) Set and cleared by software. + /// SPI3 Peripheral Clocks Enable SPI3EN: u1, - /// CRS clock enable(1) Set and cleared by software. - CRSEN: u1, - /// USART2 clock enable Set and cleared by software. + /// SPDIFRX Peripheral Clocks Enable + SPDIFRXEN: u1, + /// USART2 Peripheral Clocks Enable USART2EN: u1, - /// USART3 clock enable Set and cleared by software. + /// USART3 Peripheral Clocks Enable USART3EN: u1, - /// USART4 clock enable Set and cleared by software. - USART4EN: u1, - /// LPUART1 clock enable Set and cleared by software. - LPUART1EN: u1, - /// I2C1 clock enable Set and cleared by software. + /// UART4 Peripheral Clocks Enable + UART4EN: u1, + /// UART5 Peripheral Clocks Enable + UART5EN: u1, + /// I2C1 Peripheral Clocks Enable I2C1EN: u1, - /// I2C2 clock enable Set and cleared by software. + /// I2C2 Peripheral Clocks Enable I2C2EN: u1, - /// I2C3 clock enable Set and cleared by software. + /// I2C3 Peripheral Clocks Enable I2C3EN: u1, - /// OPAMP clock enable Set and cleared by software. - OPAMPEN: u1, - /// I2C4EN clock enable(1) Set and cleared by software. - I2C4EN: u1, - /// LPTIM3 clock enable Set and cleared by software. - LPTIM3EN: u1, - reserved28: u1, - /// Power interface clock enable Set and cleared by software. - PWREN: u1, - /// DAC1 interface clock enable Set and cleared by software. - DAC1EN: u1, - /// LPTIM2 clock enable Set and cleared by software. - LPTIM2EN: u1, - /// LPTIM1 clock enable Set and cleared by software. - LPTIM1EN: u1, + reserved25: u1, + /// I2C5 Peripheral Clocks Enable + I2C5EN: u1, + reserved27: u1, + /// HDMI-CEC peripheral clock enable + CECEN: u1, + reserved29: u1, + /// DAC1&2 peripheral clock enable + DAC12EN: u1, + /// UART7 Peripheral Clocks Enable + UART7EN: u1, + /// UART8 Peripheral Clocks Enable + UART8EN: u1, }), - reserved96: [4]u8, - /// APB peripheral clock enable register 2. - APBENR2: mmio.Mmio(packed struct(u32) { - /// SYSCFG, COMP and VREFBUF clock enable Set and cleared by software. - SYSCFGEN: u1, - reserved11: u10, - /// TIM1 timer clock enable Set and cleared by software. - TIM1EN: u1, - /// SPI1 clock enable Set and cleared by software. - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable Set and cleared by software. - USART1EN: u1, - reserved16: u1, - /// TIM15 timer clock enable Set and cleared by software. - TIM15EN: u1, - /// TIM16 timer clock enable Set and cleared by software. - TIM16EN: u1, - reserved20: u2, - /// ADC clock enable Set and cleared by software. - ADCEN: u1, - padding: u11, - }), - reserved104: [4]u8, - /// AHB peripheral clock enable in Sleep/Stop mode register. - AHBSMENR: mmio.Mmio(packed struct(u32) { - /// DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. - DMA1SMEN: u1, - /// DMA2 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. - DMA2SMEN: u1, - reserved8: u6, - /// Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the flash memory is in power down mode. - FLASHSMEN: u1, - /// SRAM clock enable during Sleep mode Set and cleared by software. - SRAMSMEN: u1, - reserved12: u2, - /// CRC clock enable during Sleep mode Set and cleared by software. - CRCSMEN: u1, - reserved16: u3, - /// AES hardware accelerator clock enable during Sleep mode Set and cleared by software. - AESSMEN: u1, - reserved18: u1, - /// RNG clock enable during Sleep and Stop mode Set and cleared by software. - RNGSMEN: u1, - reserved24: u5, - /// TSC clock enable during Sleep and Stop mode Set and cleared by software. - TSCSMEN: u1, - padding: u7, - }), - /// I/O port in Sleep mode clock enable register. - GPIOSMENR: mmio.Mmio(packed struct(u32) { - /// I/O port A clock enable during Sleep mode Set and cleared by software. - GPIOASMEN: u1, - /// I/O port B clock enable during Sleep mode Set and cleared by software. - GPIOBSMEN: u1, - /// I/O port C clock enable during Sleep mode Set and cleared by software. - GPIOCSMEN: u1, - /// I/O port D clock enable during Sleep mode(1) Set and cleared by software. - GPIODSMEN: u1, - /// I/O port E clock enable during Sleep mode Set and cleared by software. - GPIOESMEN: u1, - /// I/O port F clock enable during Sleep mode Set and cleared by software. - GPIOFSMEN: u1, - padding: u26, + /// RCC APB1 Clock Register + APB1HENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clock Recovery System peripheral clock enable + CRSEN: u1, + /// SWPMI Peripheral Clocks Enable + SWPMIEN: u1, + reserved4: u1, + /// OPAMP peripheral clock enable + OPAMPEN: u1, + /// MDIOS peripheral clock enable + MDIOSEN: u1, + reserved8: u2, + /// FDCAN Peripheral Clocks Enable + FDCANEN: u1, + reserved24: u15, + /// TIM23 block enable + TIM23EN: u1, + /// TIM24 block enable + TIM24EN: u1, + padding: u6, }), - reserved120: [8]u8, - /// APB peripheral clock enable in Sleep/Stop mode register 1. - APBSMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clock enable during Sleep mode Set and cleared by software. - TIM2SMEN: u1, - /// TIM3 timer clock enable during Sleep mode Set and cleared by software. - TIM3SMEN: u1, + /// RCC APB2 Clock Register + APB2ENR: mmio.Mmio(packed struct(u32) { + /// TIM1 peripheral clock enable + TIM1EN: u1, + /// TIM8 peripheral clock enable + TIM8EN: u1, reserved4: u2, - /// TIM6 timer clock enable during Sleep mode Set and cleared by software. - TIM6SMEN: u1, - /// TIM7 timer clock enable during Sleep mode Set and cleared by software. - TIM7SMEN: u1, + /// USART1 Peripheral Clocks Enable + USART1EN: u1, + /// USART6 Peripheral Clocks Enable + USART6EN: u1, + /// UART9 Peripheral Clocks Enable + UART9EN: u1, + /// USART10 Peripheral Clocks Enable + USART10EN: u1, + reserved12: u4, + /// SPI1 Peripheral Clocks Enable + SPI1EN: u1, + /// SPI4 Peripheral Clocks Enable + SPI4EN: u1, + reserved16: u2, + /// TIM15 peripheral clock enable + TIM15EN: u1, + /// TIM16 peripheral clock enable + TIM16EN: u1, + /// TIM17 peripheral clock enable + TIM17EN: u1, + reserved20: u1, + /// SPI5 Peripheral Clocks Enable + SPI5EN: u1, + reserved22: u1, + /// SAI1 Peripheral Clocks Enable + SAI1EN: u1, + /// SAI2 Peripheral Clocks Enable + SAI2EN: u1, + /// SAI3 Peripheral Clocks Enable + SAI3EN: u1, + reserved28: u3, + /// DFSDM1 Peripheral Clocks Enable + DFSDM1EN: u1, + /// HRTIM peripheral clock enable + HRTIMEN: u1, + padding: u2, + }), + /// RCC APB4 Clock Register + APB4ENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG peripheral clock enable + SYSCFGEN: u1, + reserved3: u1, + /// LPUART1 Peripheral Clocks Enable + LPUART1EN: u1, + reserved5: u1, + /// SPI6 Peripheral Clocks Enable + SPI6EN: u1, reserved7: u1, - /// LPUART2 clock enable during Sleep and Stop modes Set and cleared by software. - LPUART2SMEN: u1, + /// I2C4 Peripheral Clocks Enable + I2C4EN: u1, reserved9: u1, - /// LCD clock enable during Sleep mode(1) Set and cleared by software. - LCDSMEN: u1, - /// RTC APB clock enable during Sleep mode Set and cleared by software. - RTCAPBSMEN: u1, - /// WWDG clock enable during Sleep and Stop modes Set and cleared by software. - WWDGSMEN: u1, - /// LPUART3 clock enable during Sleep and Stop modes Set and cleared by software. - LPUART3SMEN: u1, - /// USB clock enable during Sleep mode(1) Set and cleared by software. - USBSMEN: u1, - /// SPI2 clock enable during Sleep mode Set and cleared by software. - SPI2SMEN: u1, - /// SPI3 clock enable during Sleep mode(1) Set and cleared by software. - SPI3SMEN: u1, - /// CRS clock enable during Sleep and Stop modes(1) Set and cleared by software. - CRSSMEN: u1, - /// USART2 clock enable during Sleep and Stop modes Set and cleared by software. - USART2SMEN: u1, - /// USART3 clock enable during Sleep mode Set and cleared by software. - USART3SMEN: u1, - /// USART4 clock enable during Sleep mode Set and cleared by software. - USART4SMEN: u1, - /// LPUART1 clock enable during Sleep and Stop modes Set and cleared by software. - LPUART1SMEN: u1, - /// I2C1 clock enable during Sleep and Stop modes Set and cleared by software. - I2C1SMEN: u1, - /// I2C2 clock enable during Sleep mode Set and cleared by software. - I2C2SMEN: u1, - /// I2C3 clock enable during Sleep mode Set and cleared by software. - I2C3SMEN: u1, - /// OPAMP clock enable during Sleep and Stop modes Set and cleared by software. - OPAMPSMEN: u1, - /// I2C4 clock enable during Sleep mode(1) Set and cleared by software. - I2C4SMEN: u1, - /// Low power timer 3 clock enable during Sleep mode Set and cleared by software. - LPTIM3SMEN: u1, - reserved28: u1, - /// Power interface clock enable during Sleep mode Set and cleared by software. - PWRSMEN: u1, - /// DAC1 interface clock enable during Sleep and Stop modes Set and cleared by software. - DAC1SMEN: u1, - /// Low Power Timer 2 clock enable during Sleep and Stop modes Set and cleared by software. - LPTIM2SMEN: u1, - /// Low Power Timer 1 clock enable during Sleep and Stop modes Set and cleared by software. - LPTIM1SMEN: u1, + /// LPTIM2 Peripheral Clocks Enable + LPTIM2EN: u1, + /// LPTIM3 Peripheral Clocks Enable + LPTIM3EN: u1, + /// LPTIM4 Peripheral Clocks Enable + LPTIM4EN: u1, + /// LPTIM5 Peripheral Clocks Enable + LPTIM5EN: u1, + /// DAC2 (containing one converter) peripheral clock enable + DAC2EN: u1, + /// COMP1/2 peripheral clock enable + COMP12EN: u1, + /// VREF peripheral clock enable + VREFEN: u1, + /// RTC APB Clock Enable + RTCAPBEN: u1, + reserved21: u4, + /// SAI4 Peripheral Clocks Enable + SAI4EN: u1, + reserved26: u4, + /// Digital temperature sensor block enable + DTSEN: u1, + padding: u5, }), - reserved128: [4]u8, - /// APB peripheral clock enable in Sleep/Stop mode register 2. - APBSMENR2: mmio.Mmio(packed struct(u32) { - /// SYSCFG, COMP and VREFBUF clock enable during Sleep and Stop modes Set and cleared by software. - SYSCFGSMEN: u1, - reserved11: u10, - /// TIM1 timer clock enable during Sleep mode Set and cleared by software. - TIM1SMEN: u1, - /// SPI1 clock enable during Sleep mode Set and cleared by software. - SPI1SMEN: u1, + reserved252: [4]u8, + /// RCC AHB3 Sleep Clock Register + AHB3LPENR: mmio.Mmio(packed struct(u32) { + /// MDMA Clock Enable During CSleep Mode + MDMALPEN: u1, + reserved4: u3, + /// DMA2D Clock Enable During CSleep Mode + DMA2DLPEN: u1, + /// JPGDEC Clock Enable During CSleep Mode + JPGDECLPEN: u1, + reserved8: u2, + /// FLASH Clock Enable During CSleep Mode + FLASHLPEN: u1, + reserved12: u3, + /// FMC Peripheral Clocks Enable During CSleep Mode + FMCLPEN: u1, reserved14: u1, - /// USART1 clock enable during Sleep and Stop modes Set and cleared by software. - USART1SMEN: u1, + /// OCTOSPI1 and OCTOSPI1 delay block enable during CSleep Mode + OCTOSPI1LPEN: u1, reserved16: u1, - /// TIM15 timer clock enable during Sleep mode Set and cleared by software. - TIM15SMEN: u1, - /// TIM16 timer clock enable during Sleep mode Set and cleared by software. - TIM16SMEN: u1, - reserved20: u2, - /// ADC clock enable during Sleep mode Set and cleared by software. - ADCSMEN: u1, - padding: u11, + /// SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + SDMMC1LPEN: u1, + reserved19: u2, + /// OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode + OCTOSPI2LPEN: u1, + reserved21: u1, + /// OCTOSPI IO manager enable during CSleep Mode + IOMNGRLPEN: u1, + /// OTFDEC1 enable during CSleep Mode + OTFD1LPEN: u1, + /// OTFDEC2 enable during CSleep Mode + OTFD2LPEN: u1, + reserved28: u4, + /// D1DTCM1 Block Clock Enable During CSleep mode + D1DTCM1LPEN: u1, + /// D1 DTCM2 Block Clock Enable During CSleep mode + DTCM2LPEN: u1, + /// D1ITCM Block Clock Enable During CSleep mode + ITCMLPEN: u1, + /// AXISRAM Block Clock Enable During CSleep mode + AXISRAMLPEN: u1, }), - reserved136: [4]u8, - /// Peripherals independent clock configuration register. - CCIPR: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows:. - USART1SEL: packed union { - raw: u2, - value: USART1SEL, - }, - /// USART2 clock source selection This bitfield is controlled by software to select USART2 clock source as follows:. - USART2SEL: packed union { - raw: u2, - value: USART2SEL, - }, - reserved6: u2, - /// LPUART3 clock source selection(1) This bitfield is controlled by software to select LPUART3 clock source as follows:. - LPUART3SEL: packed union { - raw: u2, - value: LPUART3SEL, - }, - /// LPUART2 clock source selection This bitfield is controlled by software to select LPUART2 clock source as follows:. - LPUART2SEL: packed union { - raw: u2, - value: LPUART2SEL, - }, - /// LPUART1 clock source selection This bitfield is controlled by software to select LPUART1 clock source as follows:. - LPUART1SEL: packed union { - raw: u2, - value: LPUART1SEL, - }, - /// I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows:. - I2C1SEL: packed union { - raw: u2, - value: I2C1SEL, - }, - reserved16: u2, - /// I2C3 clock source selection This bitfield is controlled by software to select I2C3 clock source as follows:. - I2C3SEL: packed union { - raw: u2, - value: I2C3SEL, - }, - /// LPTIM1 clock source selection This bitfield is controlled by software to select LPTIM1 clock source as follows:. - LPTIM1SEL: packed union { - raw: u2, - value: LPTIM1SEL, - }, - /// LPTIM2 clock source selection This bitfield is controlled by software to select LPTIM2 clock source as follows:. - LPTIM2SEL: packed union { - raw: u2, - value: LPTIM2SEL, - }, - /// LPTIM3 clock source selection This bitfield is controlled by software to select LPTIM3 clock source as follows:. - LPTIM3SEL: packed union { - raw: u2, - value: LPTIM3SEL, - }, - /// TIM1 clock source selection This bit is set and cleared by software. It selects TIM1 clock source as follows:. - TIM1SEL: packed union { - raw: u1, - value: TIM1SEL, - }, - /// TIM15 clock source selection This bit is set and cleared by software. It selects TIM15 clock source as follows:. - TIM15SEL: packed union { - raw: u1, - value: TIM15SEL, - }, - /// 481MHz clock source selection This bitfield is controlled by software to select the 481MHz clock source used by the USB FS and the RNG:. - CLK48SEL: packed union { - raw: u2, - value: CLK48SEL, - }, - /// ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC:. - ADCSEL: packed union { - raw: u2, - value: ADCSEL, - }, + /// RCC AHB1 Sleep Clock Register + AHB1LPENR: mmio.Mmio(packed struct(u32) { + /// DMA1 Clock Enable During CSleep Mode + DMA1LPEN: u1, + /// DMA2 Clock Enable During CSleep Mode + DMA2LPEN: u1, + reserved5: u3, + /// ADC1/2 Peripheral Clocks Enable During CSleep Mode + ADC12LPEN: u1, + reserved14: u8, + /// ART Clock Enable During CSleep Mode + ARTLPEN: u1, + /// Ethernet MAC bus interface Clock Enable During CSleep Mode + ETHLPEN: u1, + /// Ethernet Transmission Clock Enable During CSleep Mode + ETHTXLPEN: u1, + /// Ethernet Reception Clock Enable During CSleep Mode + ETHRXLPEN: u1, + reserved25: u7, + /// USB_OTG_HS peripheral clock enable during CSleep mode + USB_OTG_HSLPEN: u1, + /// USB_PHY1 clock enable during CSleep mode + USB_OTG_HS_ULPILPEN: u1, + /// USB_OTG_FS peripheral clock enable during CSleep mode + USB_OTG_FSLPEN: u1, + /// USB_PHY2 clocks enable during CSleep mode + USB_OTG_FS_ULPILPEN: u1, + padding: u3, + }), + /// RCC AHB2 Sleep Clock Register + AHB2LPENR: mmio.Mmio(packed struct(u32) { + /// DCMI peripheral clock enable during csleep mode + DCMILPEN: u1, + reserved4: u3, + /// CRYP peripheral clock enable during CSleep mode + CRYPLPEN: u1, + /// HASH peripheral clock enable during CSleep mode + HASHLPEN: u1, + /// RNG peripheral clock enable during CSleep mode + RNGLPEN: u1, + reserved9: u2, + /// SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + SDMMC2LPEN: u1, + reserved16: u6, + /// FMAC enable during CSleep Mode + FMACLPEN: u1, + /// CORDIC enable during CSleep Mode + CORDICLPEN: u1, + reserved29: u11, + /// SRAM1 Clock Enable During CSleep Mode + SRAM1LPEN: u1, + /// SRAM2 Clock Enable During CSleep Mode + SRAM2LPEN: u1, + /// SRAM3 Clock Enable During CSleep Mode + SRAM3LPEN: u1, + }), + /// RCC AHB4 Sleep Clock Register + AHB4LPENR: mmio.Mmio(packed struct(u32) { + /// GPIO peripheral clock enable during CSleep mode + GPIOALPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOBLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOCLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIODLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOELPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOFLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOGLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOHLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOILPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOJLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOKLPEN: u1, + reserved19: u8, + /// CRC peripheral clock enable during CSleep mode + CRCLPEN: u1, + reserved21: u1, + /// BDMA Clock Enable During CSleep Mode + BDMALPEN: u1, + reserved24: u2, + /// ADC3 Peripheral Clocks Enable During CSleep Mode + ADC3LPEN: u1, + reserved28: u3, + /// Backup RAM Clock Enable During CSleep Mode + BKPSRAMLPEN: u1, + /// SRAM4 Clock Enable During CSleep Mode + SRAM4LPEN: u1, padding: u2, }), - reserved144: [4]u8, - /// RTC domain control register. - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enable Set and cleared by software to enable LSE oscillator:. - LSEON: u1, - /// LSE oscillator ready Set and cleared by hardware to indicate when the external 321kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. - LSERDY: u1, - /// LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 321kHz oscillator is disabled (LSEON=0 and LSERDY=0). - LSEBYP: u1, - /// LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode. - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// CSS on LSE enable Set by software to enable the clock security system on LSE (321kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit. - LSECSSON: u1, - /// CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 321kHz oscillator (LSE):. - LSECSSD: u1, - /// LSE clock enable for system usage This bit must be set by software to enable the LSE clock for a system usage. - LSESYSEN: u1, - /// RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset this bitfield to 00. - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, + /// RCC APB3 Sleep Clock Register + APB3LPENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC peripheral clock enable during CSleep mode + LTDCLPEN: u1, + /// DSI Peripheral Clock Enable During CSleep Mode + DSILPEN: u1, + reserved6: u1, + /// WWDG1 Clock Enable During CSleep Mode + WWDG1LPEN: u1, + padding: u25, + }), + /// RCC APB1 Low Sleep Clock Register + APB1LLPENR: mmio.Mmio(packed struct(u32) { + /// TIM2 peripheral clock enable during CSleep mode + TIM2LPEN: u1, + /// TIM3 peripheral clock enable during CSleep mode + TIM3LPEN: u1, + /// TIM4 peripheral clock enable during CSleep mode + TIM4LPEN: u1, + /// TIM5 peripheral clock enable during CSleep mode + TIM5LPEN: u1, + /// TIM6 peripheral clock enable during CSleep mode + TIM6LPEN: u1, + /// TIM7 peripheral clock enable during CSleep mode + TIM7LPEN: u1, + /// TIM12 peripheral clock enable during CSleep mode + TIM12LPEN: u1, + /// TIM13 peripheral clock enable during CSleep mode + TIM13LPEN: u1, + /// TIM14 peripheral clock enable during CSleep mode + TIM14LPEN: u1, + /// LPTIM1 Peripheral Clocks Enable During CSleep Mode + LPTIM1LPEN: u1, reserved11: u1, - /// LSE clock ready for system usage This flag is set by hardware to indicate that the LSE clock is ready for being used by the system (see LSESYSEN bit). This flag is set when LSE clock is ready (LSEON1=11 and LSERDY1=11) and two LSE clock cycles after that LSESYSEN is set. Cleared by hardware to indicate that the LSE clock is not ready to be used by the system. - LSESYSRDY: u1, - reserved15: u3, - /// RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP. - RTCEN: u1, - /// RTC domain software reset Set and cleared by software to reset the RTC domain:. - BDRST: u1, - reserved24: u7, - /// Low-speed clock output (LSCO) enable Set and cleared by software. - LSCOEN: u1, - /// Low-speed clock output selection Set and cleared by software to select the low-speed output clock:. - LSCOSEL: packed union { - raw: u1, - value: LSCOSEL, - }, + /// WWDG2 peripheral Clocks Enable During CSleep Mode + WWDG2LPEN: u1, + reserved14: u2, + /// SPI2 Peripheral Clocks Enable During CSleep Mode + SPI2LPEN: u1, + /// SPI3 Peripheral Clocks Enable During CSleep Mode + SPI3LPEN: u1, + /// SPDIFRX Peripheral Clocks Enable During CSleep Mode + SPDIFRXLPEN: u1, + /// USART2 Peripheral Clocks Enable During CSleep Mode + USART2LPEN: u1, + /// USART3 Peripheral Clocks Enable During CSleep Mode + USART3LPEN: u1, + /// UART4 Peripheral Clocks Enable During CSleep Mode + UART4LPEN: u1, + /// UART5 Peripheral Clocks Enable During CSleep Mode + UART5LPEN: u1, + /// I2C1 Peripheral Clocks Enable During CSleep Mode + I2C1LPEN: u1, + /// I2C2 Peripheral Clocks Enable During CSleep Mode + I2C2LPEN: u1, + /// I2C3 Peripheral Clocks Enable During CSleep Mode + I2C3LPEN: u1, + reserved25: u1, + /// I2C5 block enable during CSleep Mode + I2C5LPEN: u1, + reserved27: u1, + /// HDMI-CEC Peripheral Clocks Enable During CSleep Mode + CECLPEN: u1, + reserved29: u1, + /// DAC1/2 peripheral clock enable during CSleep mode + DAC12LPEN: u1, + /// UART7 Peripheral Clocks Enable During CSleep Mode + UART7LPEN: u1, + /// UART8 Peripheral Clocks Enable During CSleep Mode + UART8LPEN: u1, + }), + /// RCC APB1 High Sleep Clock Register + APB1HLPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clock Recovery System peripheral clock enable during CSleep mode + CRSLPEN: u1, + /// SWPMI Peripheral Clocks Enable During CSleep Mode + SWPMILPEN: u1, + reserved4: u1, + /// OPAMP peripheral clock enable during CSleep mode + OPAMPLPEN: u1, + /// MDIOS peripheral clock enable during CSleep mode + MDIOSLPEN: u1, + reserved8: u2, + /// FDCAN Peripheral Clocks Enable During CSleep Mode + FDCANLPEN: u1, + reserved24: u15, + /// TIM23 block enable during CSleep Mode + TIM23LPEN: u1, + /// TIM24 block enable during CSleep Mode + TIM24LPEN: u1, padding: u6, }), - /// Control/status register. - CSR: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable Set and cleared by software to enable/disable the LSI oscillator:. - LSION: u1, - /// LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. - LSIRDY: u1, - /// Internal low-speed oscillator pre-divided by 128 Set and reset by hardware to indicate when the low-speed internal RC oscillator has to be divided by 128. The software has to switch off the LSI before changing this bit. - LSIPREDIV: packed union { - raw: u1, - value: LSIPREDIV, - }, - reserved8: u5, - /// MSI range after Standby mode Set by software to chose the MSI frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always 41MHz. MSISRANGE[3:0] can be written only when MSIRGSEL1=11. Others: Reserved Note: Changing the MSISRANGE[3:0] does not change the current MSI frequency. - MSISRANGE: packed union { - raw: u4, - value: MSISRANGE, - }, - reserved23: u11, - /// Remove reset flags Set by software to clear the reset flags. + /// RCC APB2 Sleep Clock Register + APB2LPENR: mmio.Mmio(packed struct(u32) { + /// TIM1 peripheral clock enable during CSleep mode + TIM1LPEN: u1, + /// TIM8 peripheral clock enable during CSleep mode + TIM8LPEN: u1, + reserved4: u2, + /// USART1 Peripheral Clocks Enable During CSleep Mode + USART1LPEN: u1, + /// USART6 Peripheral Clocks Enable During CSleep Mode + USART6LPEN: u1, + reserved12: u6, + /// SPI1 Peripheral Clocks Enable During CSleep Mode + SPI1LPEN: u1, + /// SPI4 Peripheral Clocks Enable During CSleep Mode + SPI4LPEN: u1, + reserved16: u2, + /// TIM15 peripheral clock enable during CSleep mode + TIM15LPEN: u1, + /// TIM16 peripheral clock enable during CSleep mode + TIM16LPEN: u1, + /// TIM17 peripheral clock enable during CSleep mode + TIM17LPEN: u1, + reserved20: u1, + /// SPI5 Peripheral Clocks Enable During CSleep Mode + SPI5LPEN: u1, + reserved22: u1, + /// SAI1 Peripheral Clocks Enable During CSleep Mode + SAI1LPEN: u1, + /// SAI2 Peripheral Clocks Enable During CSleep Mode + SAI2LPEN: u1, + /// SAI3 Peripheral Clocks Enable During CSleep Mode + SAI3LPEN: u1, + reserved28: u3, + /// DFSDM1 Peripheral Clocks Enable During CSleep Mode + DFSDM1LPEN: u1, + /// HRTIM peripheral clock enable during CSleep mode + HRTIMLPEN: u1, + padding: u2, + }), + /// RCC APB4 Sleep Clock Register + APB4LPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG peripheral clock enable during CSleep mode + SYSCFGLPEN: u1, + reserved3: u1, + /// LPUART1 Peripheral Clocks Enable During CSleep Mode + LPUART1LPEN: u1, + reserved5: u1, + /// SPI6 Peripheral Clocks Enable During CSleep Mode + SPI6LPEN: u1, + reserved7: u1, + /// I2C4 Peripheral Clocks Enable During CSleep Mode + I2C4LPEN: u1, + reserved9: u1, + /// LPTIM2 Peripheral Clocks Enable During CSleep Mode + LPTIM2LPEN: u1, + /// LPTIM3 Peripheral Clocks Enable During CSleep Mode + LPTIM3LPEN: u1, + /// LPTIM4 Peripheral Clocks Enable During CSleep Mode + LPTIM4LPEN: u1, + /// LPTIM5 Peripheral Clocks Enable During CSleep Mode + LPTIM5LPEN: u1, + /// DAC2 (containing one converter) peripheral clock enable during CSleep mode + DAC2LPEN: u1, + /// COMP1/2 peripheral clock enable during CSleep mode + COMP12LPEN: u1, + /// VREF peripheral clock enable during CSleep mode + VREFLPEN: u1, + /// RTC APB Clock Enable During CSleep Mode + RTCAPBLPEN: u1, + reserved21: u4, + /// SAI4 Peripheral Clocks Enable During CSleep Mode + SAI4LPEN: u1, + reserved26: u4, + /// Digital temperature sensor block enable during CSleep Mode + DTSLPEN: u1, + padding: u5, + }), + reserved304: [16]u8, + /// RCC Reset Status Register + C1_RSR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Remove reset flag RMVF: u1, - reserved25: u1, - /// Option byte loader reset flag Set by hardware when a reset from the Option byte loading occurs. Cleared by setting the RMVF bit. - OBLRSTF: u1, - /// Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by setting the RMVF bit. + /// CPU reset flag + CPURSTF: u1, + reserved19: u1, + /// D1 domain power switch reset flag + D1RSTF: u1, + /// D2 domain power switch reset flag + D2RSTF: u1, + /// BOR reset flag + BORRSTF: u1, + /// Pin reset flag (NRST) PINRSTF: u1, - /// BOR or POR/PDR flag Set by hardware when a BOR or POR/PDR occurs. Cleared by setting the RMVF bit. - PWRRSTF: u1, - /// Software reset flag Set by hardware when a software reset occurs. Cleared by setting the RMVF bit. + /// POR/PDR reset flag + PORRSTF: u1, + /// System reset from CPU reset flag SFTRSTF: u1, - /// Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by setting the RMVF bit. - IWDGRSTF: u1, - /// Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by setting the RMVF bit. - WWDGRSTF: u1, - /// Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. This operates only if nRST_STOP, nRST_STDBY or nRST_SHDW option bits are cleared. + reserved26: u1, + /// Independent Watchdog reset flag + IWDG1RSTF: u1, + reserved28: u1, + /// Window Watchdog reset flag + WWDG1RSTF: u1, + reserved30: u1, + /// Reset due to illegal D1 DStandby or CPU CStop flag LPWRRSTF: u1, + padding: u1, }), - /// RCC clock recovery RC register. - CRRCR: mmio.Mmio(packed struct(u32) { - /// HSI48 RC oscillator enable(1). - HSI48ON: u1, - /// HSI48 clock ready flag(1) The flag is set when the HSI48 clock is ready for use. - HSI48RDY: u1, - reserved7: u5, - /// HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. - HSI48CAL: u9, - padding: u16, - }), - }; - }; - - pub const pka_v1b = struct { - /// Public key accelerator. - pub const PKA = extern struct { - /// PKA control register. - CR: mmio.Mmio(packed struct(u32) { - /// PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application. - EN: u1, - /// start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy. - START: u1, - reserved8: u6, - /// PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. - MODE: u6, - reserved17: u3, - /// End of operation interrupt enable. - PROCENDIE: u1, - reserved19: u1, - /// RAM error interrupt enable. - RAMERRIE: u1, - /// Address error interrupt enable. - ADDRERRIE: u1, - /// Operation error interrupt enable. - OPERRIE: u1, - padding: u10, - }), - /// PKA status register. - SR: mmio.Mmio(packed struct(u32) { - /// PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. - INITOK: u1, - reserved16: u15, - /// PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). - BUSY: u1, - /// PKA End of Operation flag. - PROCENDF: u1, - reserved19: u1, - /// PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. - RAMERRF: u1, - /// Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. - ADDRERRF: u1, - /// Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. - OPERRF: u1, - padding: u10, - }), - /// PKA clear flag register. - CLRFR: mmio.Mmio(packed struct(u32) { - reserved17: u17, - /// Clear PKA End of Operation flag. - PROCENDFC: u1, - reserved19: u1, - /// Clear PKA RAM error flag. - RAMERRFC: u1, - /// Clear address error flag. - ADDRERRFC: u1, - /// Clear operation error flag. - OPERRFC: u1, - padding: u10, + /// RCC AHB3 Clock Register + C1_AHB3ENR: mmio.Mmio(packed struct(u32) { + /// MDMA Peripheral Clock Enable + MDMAEN: u1, + reserved4: u3, + /// DMA2D Peripheral Clock Enable + DMA2DEN: u1, + /// JPGDEC Peripheral Clock Enable + JPGDECEN: u1, + reserved12: u6, + /// FMC Peripheral Clocks Enable + FMCEN: u1, + reserved14: u1, + /// QUADSPI and QUADSPI Delay Clock Enable + QUADSPIEN: u1, + reserved16: u1, + /// SDMMC1 and SDMMC1 Delay Clock Enable + SDMMC1EN: u1, + padding: u15, }), - reserved1024: [1012]u8, - /// PKA internal memeory. - RAM: [1334]u32, - }; - }; - - pub const ucpd_v1 = struct { - pub const ANAMODE = enum(u1) { - /// Source - Source = 0x0, - /// Sink - Sink = 0x1, - }; - - pub const CCENABLE = enum(u2) { - /// Disable both PHYs - Disabled = 0x0, - /// Enable CC1 PHY - Cc1 = 0x1, - /// Enable CC2 PHY - Cc2 = 0x2, - /// Enable CC1 and CC2 PHY - Both = 0x3, - }; - - pub const PHYCCSEL = enum(u1) { - /// Use CC1 IO for Power Delivery communication - Cc1 = 0x0, - /// Use CC2 IO for Power Delivery communication - Cc2 = 0x1, - }; - - pub const PSC_USBPDCLK = enum(u3) { - /// 1 (bypass) - Div1 = 0x0, - /// 2 - Div2 = 0x1, - /// 4 - Div4 = 0x2, - /// 8 - Div8 = 0x3, - /// 16 - Div16 = 0x4, - _, - }; - - pub const RXORDSET = enum(u3) { - /// SOP code detected in receiver - Sop = 0x0, - /// SOP' code detected in receiver - SopPrime = 0x1, - /// SOP'' code detected in receiver - SopDoublePrime = 0x2, - /// SOP'_Debug detected in receiver - SopPrimeDebug = 0x3, - /// SOP''_Debug detected in receiver - SopDoublePrimeDebug = 0x4, - /// Cable Reset detected in receiver - CableReset = 0x5, - /// SOP extension#1 detected in receiver - Ext1 = 0x6, - /// SOP extension#2 detected in receiver - Ext2 = 0x7, - }; - - pub const RXSOPKINVALID = enum(u3) { - /// No K‑code corrupted - None = 0x0, - /// First K‑code corrupted - First = 0x1, - /// Second K‑code corrupted - Second = 0x2, - /// Third K‑code corrupted - Third = 0x3, - /// Fourth K‑code corrupted - Fourth = 0x4, - _, - }; - - pub const TXMODE = enum(u2) { - /// Transmission of Tx packet previously defined in other registers - Packet = 0x0, - /// Cable Reset sequence - CableReset = 0x1, - /// BIST test sequence (BIST Carrier Mode 2) - Bist = 0x2, - _, - }; - - pub const TYPEC_VSTATE_CC = enum(u2) { - /// Lowest - Lowest = 0x0, - /// Low - Low = 0x1, - /// High - High = 0x2, - /// Highest - Highest = 0x3, - }; - - /// USB Power Delivery interface - pub const UCPD = extern struct { - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfield value plus one) of a clk divider producing half-bit clock (hbit_clk). - HBITCLKDIV: u6, - /// Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal. - IFRGAP: u5, - /// Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the clk frequency and the HBITCLKDIV[5:0] bitfield setting. - TRANSWIN: u5, - reserved17: u1, - /// Pre-scaler division ratio for generating clk The bitfield determines the division ratio of a kernel clock pre-scaler producing peripheral clock (clk). It is recommended to use the pre-scaler so as to set the clk frequency in the range from 6 to 9 MHz. - PSC_USBPDCLK: packed union { - raw: u3, - value: PSC_USBPDCLK, - }, - /// Receiver ordered set enable The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function: 0bxxxxxxxx1: SOP detect enabled 0bxxxxxxx1x: SOP' detect enabled 0bxxxxxx1xx: SOP'' detect enabled 0bxxxxx1xxx: Hard Reset detect enabled 0bxxxx1xxxx: Cable Detect reset enabled 0bxxx1xxxxx: SOP'_Debug enabled 0bxx1xxxxxx: SOP''_Debug enabled 0bx1xxxxxxx: SOP extension#1 enabled 0b1xxxxxxxx: SOP extension#2 enabled - RXORDSETEN: u9, - /// Transmission DMA mode enable When set, the bit enables DMA mode for transmission. - TXDMAEN: u1, - /// Reception DMA mode enable When set, the bit enables DMA mode for reception. - RXDMAEN: u1, - /// peripheral enable General enable of the peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state. - UCPDEN: u1, + /// RCC AHB1 Clock Register + C1_AHB1ENR: mmio.Mmio(packed struct(u32) { + /// DMA1 Clock Enable + DMA1EN: u1, + /// DMA2 Clock Enable + DMA2EN: u1, + reserved5: u3, + /// ADC1/2 Peripheral Clocks Enable + ADC12EN: u1, + reserved14: u8, + /// ART Clock Enable + ARTEN: u1, + /// Ethernet MAC bus interface Clock Enable + ETHEN: u1, + /// Ethernet Transmission Clock Enable + ETHTXEN: u1, + /// Ethernet Reception Clock Enable + ETHRXEN: u1, + reserved25: u7, + /// USB_OTG_HS Peripheral Clocks Enable + USB_OTG_HSEN: u1, + /// USB_PHY1 Clocks Enable + USB_OTG_HS_ULPIEN: u1, + /// USB_OTG_FS Peripheral Clocks Enable + USB_OTG_FSEN: u1, + /// USB_PHY2 Clocks Enable + USB_OTG_FS_ULPIEN: u1, + padding: u3, }), - /// configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler). - RXFILTDIS: u1, - /// BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value. - RXFILT2N3: u1, - /// Force ClkReq clock request - FORCECLK: u1, - /// Wakeup from Stop mode enable Setting the bit enables the ASYNC_INT signal. - WUPEN: u1, - padding: u28, + /// RCC AHB2 Clock Register + C1_AHB2ENR: mmio.Mmio(packed struct(u32) { + /// DCMI peripheral clock + DCMIEN: u1, + reserved4: u3, + /// CRYP peripheral clock enable + CRYPEN: u1, + /// HASH peripheral clock enable + HASHEN: u1, + /// RNG peripheral clocks enable + RNGEN: u1, + reserved9: u2, + /// SDMMC2 and SDMMC2 delay clock enable + SDMMC2EN: u1, + reserved29: u19, + /// SRAM1 block enable + SRAM1EN: u1, + /// SRAM2 block enable + SRAM2EN: u1, + /// SRAM3 block enable + SRAM3EN: u1, }), - /// configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - /// SW trim value for Rd resistor on the CC1 line - TRIM_CC1_RD: u4, - reserved9: u5, - /// SW trim value for Rp current sources on the CC1 line - TRIM_CC1_RP: u4, - reserved16: u3, - /// SW trim value for Rd resistor on the CC2 line - TRIM_CC2_RD: u4, - reserved25: u5, - /// SW trim value for Rp current sources on the CC2 line - TRIM_CC2_RP: u4, + /// RCC AHB4 Clock Register + C1_AHB4ENR: mmio.Mmio(packed struct(u32) { + /// 0GPIO peripheral clock enable + GPIOAEN: u1, + /// 0GPIO peripheral clock enable + GPIOBEN: u1, + /// 0GPIO peripheral clock enable + GPIOCEN: u1, + /// 0GPIO peripheral clock enable + GPIODEN: u1, + /// 0GPIO peripheral clock enable + GPIOEEN: u1, + /// 0GPIO peripheral clock enable + GPIOFEN: u1, + /// 0GPIO peripheral clock enable + GPIOGEN: u1, + /// 0GPIO peripheral clock enable + GPIOHEN: u1, + /// 0GPIO peripheral clock enable + GPIOIEN: u1, + /// 0GPIO peripheral clock enable + GPIOJEN: u1, + /// 0GPIO peripheral clock enable + GPIOKEN: u1, + reserved19: u8, + /// CRC peripheral clock enable + CRCEN: u1, + reserved21: u1, + /// BDMA and DMAMUX2 Clock Enable + BDMAEN: u1, + reserved24: u2, + /// ADC3 Peripheral Clocks Enable + ADC3EN: u1, + /// HSEM peripheral clock enable + HSEMEN: u1, + reserved28: u2, + /// Backup RAM Clock Enable + BKPSRAMEN: u1, padding: u3, }), - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the "tBISTContMode" delay), disable the peripheral (UCPDEN = 0). - TXMODE: packed union { - raw: u2, - value: TXMODE, - }, - /// Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded. - TXSEND: u1, - /// Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded. - TXHRST: u1, - /// Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message. - RXMODE: u1, - /// USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set. - PHYRXEN: u1, - /// CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach. - PHYCCSEL: packed union { - raw: u1, - value: PHYCCSEL, - }, - /// Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield. - ANASUBMODE: u2, - /// Analog PHY operating mode The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0]. - ANAMODE: packed union { - raw: u1, - value: ANAMODE, - }, - /// CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source. - CCENABLE: packed union { - raw: u2, - value: CCENABLE, - }, - reserved13: u1, - /// VCONN switch enable for CC1 - CC1VCONNEN: u1, - /// VCONN switch enable for CC2 - CC2VCONNEN: u1, - /// Dead battery function enable The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register. Dead battery function only operates if the external circuit is appropriately configured. - DBATTEN: u1, - /// FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink. - FRSRXEN: u1, - /// FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0. - FRSTX: u1, - /// Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to "USB Type-C ECN for Source VCONN Discharge". The CCENABLE[1:0] bitfield must be set accordingly, too. - RDCH: u1, - reserved20: u1, - /// CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE[1:0]. - CC1TCDIS: u1, - /// CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE[1:0]. - CC2TCDIS: u1, - padding: u10, - }), - /// interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// TXIS interrupt enable - TXISIE: u1, - /// TXMSGDISC interrupt enable - TXMSGDISCIE: u1, - /// TXMSGSENT interrupt enable - TXMSGSENTIE: u1, - /// TXMSGABT interrupt enable - TXMSGABTIE: u1, - /// HRSTDISC interrupt enable - HRSTDISCIE: u1, - /// HRSTSENT interrupt enable - HRSTSENTIE: u1, - /// TXUND interrupt enable - TXUNDIE: u1, - reserved8: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// RXORDDET interrupt enable - RXORDDETIE: u1, - /// RXHRSTDET interrupt enable - RXHRSTDETIE: u1, - /// RXOVR interrupt enable - RXOVRIE: u1, - /// RXMSGEND interrupt enable - RXMSGENDIE: u1, - reserved14: u1, - /// TYPECEVT1 interrupt enable - TYPECEVT1IE: u1, - /// TYPECEVT2 interrupt enable - TYPECEVT2IE: u1, - reserved20: u4, - /// FRSEVT interrupt enable - FRSEVTIE: u1, - padding: u11, + /// RCC APB3 Clock Register + C1_APB3ENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC peripheral clock enable + LTDCEN: u1, + /// DSI Peripheral clocks enable + DSIEN: u1, + reserved6: u1, + /// WWDG1 Clock Enable + WWDG1EN: u1, + padding: u25, }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Transmit interrupt status The flag indicates that the TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the TXDR register. - TXIS: u1, - /// Message transmission discarded The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit. Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle. - TXMSGDISC: u1, - /// Message transmission completed The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit. In the event of a message transmission interrupted by a Hard Reset, the flag is not raised. - TXMSGSENT: u1, - /// Transmit message abort The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit. - TXMSGABT: u1, - /// Hard Reset discarded The flag indicates that the Hard Reset message is discarded. The flag is cleared by setting the HRSTDISCCF bit. - HRSTDISC: u1, - /// Hard Reset message sent The flag indicates that the Hard Reset message is sent. The flag is cleared by setting the HRSTSENTCF bit. - HRSTSENT: u1, - /// Tx data underrun detection The flag indicates that the Tx data register (TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit. - TXUND: u1, - reserved8: u1, - /// Receive data register not empty detection The flag indicates that the RXDR register is not empty. It is automatically cleared upon reading RXDR. - RXNE: u1, - /// Rx ordered set (4 K-codes) detection The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET[2:0] bitfield of the RX_ORDSET register. It is cleared by setting the RXORDDETCF bit. - RXORDDET: u1, - /// Rx Hard Reset receipt detection The flag indicates the receipt of valid Hard Reset message. It is cleared by setting the RXHRSTDETCF bit. - RXHRSTDET: u1, - /// Rx data overflow detection The flag indicates Rx data buffer overflow. It is cleared by setting the RXOVRCF bit. The buffer overflow can occur if the received data are not read fast enough. - RXOVR: u1, - /// Rx message received The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit. The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message. - RXMSGEND: u1, - /// Receive message error The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set. - RXERR: u1, - /// Type-C voltage level event on CC1 line The flag indicates a change of the TYPEC_VSTATE_CC1[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit. - TYPECEVT1: u1, - /// Type-C voltage level event on CC2 line The flag indicates a change of the TYPEC_VSTATE_CC2[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit. - TYPECEVT2: u1, - /// The status bitfield indicates the voltage level on the CC1 line in its steady state. The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value. - TYPEC_VSTATE_CC1: packed union { - raw: u2, - value: TYPEC_VSTATE_CC, - }, - /// CC2 line voltage level The status bitfield indicates the voltage level on the CC2 line in its steady state. The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value. - TYPEC_VSTATE_CC2: packed union { - raw: u2, - value: TYPEC_VSTATE_CC, - }, - /// FRS detection event The flag is cleared by setting the FRSEVTCF bit. - FRSEVT: u1, - padding: u11, + /// RCC APB1 Clock Register + C1_APB1LENR: mmio.Mmio(packed struct(u32) { + /// TIM peripheral clock enable + TIM2EN: u1, + /// TIM peripheral clock enable + TIM3EN: u1, + /// TIM peripheral clock enable + TIM4EN: u1, + /// TIM peripheral clock enable + TIM5EN: u1, + /// TIM peripheral clock enable + TIM6EN: u1, + /// TIM peripheral clock enable + TIM7EN: u1, + /// TIM peripheral clock enable + TIM12EN: u1, + /// TIM peripheral clock enable + TIM13EN: u1, + /// TIM peripheral clock enable + TIM14EN: u1, + /// LPTIM1 Peripheral Clocks Enable + LPTIM1EN: u1, + reserved11: u1, + /// WWDG2 peripheral clock enable + WWDG2EN: u1, + reserved14: u2, + /// SPI2 Peripheral Clocks Enable + SPI2EN: u1, + /// SPI3 Peripheral Clocks Enable + SPI3EN: u1, + /// SPDIFRX Peripheral Clocks Enable + SPDIFRXEN: u1, + /// USART2 Peripheral Clocks Enable + USART2EN: u1, + /// USART3 Peripheral Clocks Enable + USART3EN: u1, + /// UART4 Peripheral Clocks Enable + UART4EN: u1, + /// UART5 Peripheral Clocks Enable + UART5EN: u1, + /// I2C1 Peripheral Clocks Enable + I2C1EN: u1, + /// I2C2 Peripheral Clocks Enable + I2C2EN: u1, + /// I2C3 Peripheral Clocks Enable + I2C3EN: u1, + reserved25: u1, + /// I2C5 Peripheral Clocks Enable + I2C5EN: u1, + reserved27: u1, + /// HDMI-CEC peripheral clock enable + CECEN: u1, + reserved29: u1, + /// DAC1&2 peripheral clock enable + DAC12EN: u1, + /// UART7 Peripheral Clocks Enable + UART7EN: u1, + /// UART8 Peripheral Clocks Enable + UART8EN: u1, }), - /// interrupt clear register - ICR: mmio.Mmio(packed struct(u32) { + /// RCC APB1 Clock Register + C1_APB1HENR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Tx message discard flag (TXMSGDISC) clear Setting the bit clears the TXMSGDISC flag in the SR register. - TXMSGDISCCF: u1, - /// Tx message send flag (TXMSGSENT) clear Setting the bit clears the TXMSGSENT flag in the SR register. - TXMSGSENTCF: u1, - /// Tx message abort flag (TXMSGABT) clear Setting the bit clears the TXMSGABT flag in the SR register. - TXMSGABTCF: u1, - /// Hard reset discard flag (HRSTDISC) clear Setting the bit clears the HRSTDISC flag in the SR register. - HRSTDISCCF: u1, - /// Hard reset send flag (HRSTSENT) clear Setting the bit clears the HRSTSENT flag in the SR register. - HRSTSENTCF: u1, - /// Tx underflow flag (TXUND) clear Setting the bit clears the TXUND flag in the SR register. - TXUNDCF: u1, - reserved9: u2, - /// Rx ordered set detect flag (RXORDDET) clear Setting the bit clears the RXORDDET flag in the SR register. - RXORDDETCF: u1, - /// Rx Hard Reset detect flag (RXHRSTDET) clear Setting the bit clears the RXHRSTDET flag in the SR register. - RXHRSTDETCF: u1, - /// Rx overflow flag (RXOVR) clear Setting the bit clears the RXOVR flag in the SR register. - RXOVRCF: u1, - /// Rx message received flag (RXMSGEND) clear Setting the bit clears the RXMSGEND flag in the SR register. - RXMSGENDCF: u1, - reserved14: u1, - /// Type-C CC1 event flag (TYPECEVT1) clear Setting the bit clears the TYPECEVT1 flag in the SR register - TYPECEVT1CF: u1, - /// Type-C CC2 line event flag (TYPECEVT2) clear Setting the bit clears the TYPECEVT2 flag in the SR register - TYPECEVT2CF: u1, - reserved20: u4, - /// FRS event flag (FRSEVT) clear Setting the bit clears the FRSEVT flag in the SR register. - FRSEVTCF: u1, - padding: u11, + /// Clock Recovery System peripheral clock enable + CRSEN: u1, + /// SWPMI Peripheral Clocks Enable + SWPMIEN: u1, + reserved4: u1, + /// OPAMP peripheral clock enable + OPAMPEN: u1, + /// MDIOS peripheral clock enable + MDIOSEN: u1, + reserved8: u2, + /// FDCAN Peripheral Clocks Enable + FDCANEN: u1, + padding: u23, }), - /// Tx ordered set type register - TX_ORDSETR: mmio.Mmio(packed struct(u32) { - /// Ordered set to transmit The bitfield determines a full 20-bit sequence to transmit, consisting of four K-codes, each of five bits, defining the packet to transmit. The bit 0 (bit 0 of K-code1) is the first, the bit 19 (bit 4 of K‑code4) the last. - TXORDSET: u20, - padding: u12, + /// RCC APB2 Clock Register + C1_APB2ENR: mmio.Mmio(packed struct(u32) { + /// TIM1 peripheral clock enable + TIM1EN: u1, + /// TIM8 peripheral clock enable + TIM8EN: u1, + reserved4: u2, + /// USART1 Peripheral Clocks Enable + USART1EN: u1, + /// USART6 Peripheral Clocks Enable + USART6EN: u1, + /// UART9 Peripheral Clocks Enable + UART9EN: u1, + /// USART10 Peripheral Clocks Enable + USART10EN: u1, + reserved12: u4, + /// SPI1 Peripheral Clocks Enable + SPI1EN: u1, + /// SPI4 Peripheral Clocks Enable + SPI4EN: u1, + reserved16: u2, + /// TIM15 peripheral clock enable + TIM15EN: u1, + /// TIM16 peripheral clock enable + TIM16EN: u1, + /// TIM17 peripheral clock enable + TIM17EN: u1, + reserved20: u1, + /// SPI5 Peripheral Clocks Enable + SPI5EN: u1, + reserved22: u1, + /// SAI1 Peripheral Clocks Enable + SAI1EN: u1, + /// SAI2 Peripheral Clocks Enable + SAI2EN: u1, + /// SAI3 Peripheral Clocks Enable + SAI3EN: u1, + reserved28: u3, + /// DFSDM1 Peripheral Clocks Enable + DFSDM1EN: u1, + /// HRTIM peripheral clock enable + HRTIMEN: u1, + padding: u2, }), - /// Tx payload size register - TX_PAYSZR: mmio.Mmio(packed struct(u32) { - /// Payload size yet to transmit The bitfield is modified by software and by hardware. It contains the number of bytes of a payload (including header but excluding CRC) yet to transmit: each time a data byte is written into the TXDR register, the bitfield value decrements and the TXIS bit is set, except when the bitfield value reaches zero. The enumerated values are standard payload sizes before the start of transmission. - TXPAYSZ: u10, - padding: u22, + /// RCC APB4 Clock Register + C1_APB4ENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG peripheral clock enable + SYSCFGEN: u1, + reserved3: u1, + /// LPUART1 Peripheral Clocks Enable + LPUART1EN: u1, + reserved5: u1, + /// SPI6 Peripheral Clocks Enable + SPI6EN: u1, + reserved7: u1, + /// I2C4 Peripheral Clocks Enable + I2C4EN: u1, + reserved9: u1, + /// LPTIM2 Peripheral Clocks Enable + LPTIM2EN: u1, + /// LPTIM3 Peripheral Clocks Enable + LPTIM3EN: u1, + /// LPTIM4 Peripheral Clocks Enable + LPTIM4EN: u1, + /// LPTIM5 Peripheral Clocks Enable + LPTIM5EN: u1, + reserved14: u1, + /// COMP1/2 peripheral clock enable + COMP12EN: u1, + /// VREF peripheral clock enable + VREFEN: u1, + /// RTC APB Clock Enable + RTCAPBEN: u1, + reserved21: u4, + /// SAI4 Peripheral Clocks Enable + SAI4EN: u1, + padding: u10, }), - /// Tx data register - TXDR: mmio.Mmio(packed struct(u32) { - /// Data byte to transmit - TXDATA: u8, - padding: u24, + reserved348: [4]u8, + /// RCC AHB3 Sleep Clock Register + C1_AHB3LPENR: mmio.Mmio(packed struct(u32) { + /// MDMA Clock Enable During CSleep Mode + MDMALPEN: u1, + reserved4: u3, + /// DMA2D Clock Enable During CSleep Mode + DMA2DLPEN: u1, + /// JPGDEC Clock Enable During CSleep Mode + JPGDECLPEN: u1, + reserved8: u2, + /// Flash interface clock enable during csleep mode + FLASHPREN: u1, + reserved12: u3, + /// FMC Peripheral Clocks Enable During CSleep Mode + FMCLPEN: u1, + reserved14: u1, + /// QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + QUADSPILPEN: u1, + reserved16: u1, + /// SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + SDMMC1LPEN: u1, + reserved19: u2, + /// OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode + OCTOSPI2LPEN: u1, + reserved21: u1, + /// OCTOSPI IO manager enable during CSleep Mode + IOMNGRLPEN: u1, + /// OTFDEC1 enable during CSleep Mode + OTFD1LPEN: u1, + /// OTFDEC2 enable during CSleep Mode + OTFD2LPEN: u1, + reserved28: u4, + /// D1DTCM1 Block Clock Enable During CSleep mode + D1DTCM1LPEN: u1, + /// D1 DTCM2 Block Clock Enable During CSleep mode + DTCM2LPEN: u1, + /// D1ITCM Block Clock Enable During CSleep mode + ITCMLPEN: u1, + /// AXISRAM Block Clock Enable During CSleep mode + AXISRAMLPEN: u1, }), - RX_ORDSETR: mmio.Mmio(packed struct(u32) { - /// Rx ordered set code detected - RXORDSET: packed union { - raw: u3, - value: RXORDSET, - }, - /// The bit indicates the number of correct K‑codes. For debug purposes only. - RXSOP3OF4: u1, - /// The bitfield is for debug purposes only. Others: Invalid - RXSOPKINVALID: packed union { - raw: u3, - value: RXSOPKINVALID, - }, - padding: u25, + /// RCC AHB1 Sleep Clock Register + C1_AHB1LPENR: mmio.Mmio(packed struct(u32) { + /// DMA1 Clock Enable During CSleep Mode + DMA1LPEN: u1, + /// DMA2 Clock Enable During CSleep Mode + DMA2LPEN: u1, + reserved5: u3, + /// ADC1/2 Peripheral Clocks Enable During CSleep Mode + ADC12LPEN: u1, + reserved14: u8, + /// ART Clock Enable During CSleep Mode + ARTLPEN: u1, + /// Ethernet MAC bus interface Clock Enable During CSleep Mode + ETHLPEN: u1, + /// Ethernet Transmission Clock Enable During CSleep Mode + ETHTXLPEN: u1, + /// Ethernet Reception Clock Enable During CSleep Mode + ETHRXLPEN: u1, + reserved25: u7, + /// USB_OTG_HS peripheral clock enable during CSleep mode + USB_OTG_HSLPEN: u1, + /// USB_PHY1 clock enable during CSleep mode + USB_OTG_HS_ULPILPEN: u1, + /// USB_OTG_FS peripheral clock enable during CSleep mode + USB_OTG_FSLPEN: u1, + /// USB_PHY2 clocks enable during CSleep mode + USB_OTG_FS_ULPILPEN: u1, + padding: u3, }), - RX_PAYSZR: mmio.Mmio(packed struct(u32) { - /// Rx payload size received This bitfield contains the number of bytes of a payload (including header but excluding CRC) received: each time a new data byte is received in the RXDR register, the bitfield value increments and the RXMSGEND flag is set (and an interrupt generated if enabled). The bitfield may return a spurious value when a byte reception is ongoing (the RXMSGEND flag is low). - RXPAYSZ: u10, - padding: u22, + /// RCC AHB2 Sleep Clock Register + C1_AHB2LPENR: mmio.Mmio(packed struct(u32) { + /// DCMI peripheral clock enable during csleep mode + DCMILPEN: u1, + reserved4: u3, + /// CRYP peripheral clock enable during CSleep mode + CRYPLPEN: u1, + /// HASH peripheral clock enable during CSleep mode + HASHLPEN: u1, + /// RNG peripheral clock enable during CSleep mode + RNGLPEN: u1, + reserved9: u2, + /// SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + SDMMC2LPEN: u1, + reserved16: u6, + /// FMAC enable during CSleep Mode + FMACLPEN: u1, + /// CORDIC enable during CSleep Mode + CORDICLPEN: u1, + reserved29: u11, + /// SRAM1 Clock Enable During CSleep Mode + SRAM1LPEN: u1, + /// SRAM2 Clock Enable During CSleep Mode + SRAM2LPEN: u1, + /// SRAM3 Clock Enable During CSleep Mode + SRAM3LPEN: u1, }), - RXDR: mmio.Mmio(packed struct(u32) { - /// Data byte received - RXDATA: u8, - padding: u24, + /// RCC AHB4 Sleep Clock Register + C1_AHB4LPENR: mmio.Mmio(packed struct(u32) { + /// GPIO peripheral clock enable during CSleep mode + GPIOALPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOBLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOCLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIODLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOELPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOFLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOGLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOHLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOILPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOJLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOKLPEN: u1, + reserved19: u8, + /// CRC peripheral clock enable during CSleep mode + CRCLPEN: u1, + reserved21: u1, + /// BDMA Clock Enable During CSleep Mode + BDMALPEN: u1, + reserved24: u2, + /// ADC3 Peripheral Clocks Enable During CSleep Mode + ADC3LPEN: u1, + reserved28: u3, + /// Backup RAM Clock Enable During CSleep Mode + BKPSRAMLPEN: u1, + /// SRAM4 Clock Enable During CSleep Mode + SRAM4LPEN: u1, + padding: u2, }), - /// Rx ordered set extension register 1 - RX_ORDEXTR1: mmio.Mmio(packed struct(u32) { - /// Ordered set 1 received The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last. - RXSOPX1: u20, - padding: u12, + /// RCC APB3 Sleep Clock Register + C1_APB3LPENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC peripheral clock enable during CSleep mode + LTDCLPEN: u1, + /// DSI Peripheral Clock Enable During CSleep Mode + DSILPEN: u1, + reserved6: u1, + /// WWDG1 Clock Enable During CSleep Mode + WWDG1LPEN: u1, + padding: u25, }), - /// Rx ordered set extension register 2 - RX_ORDEXTR2: mmio.Mmio(packed struct(u32) { - /// Ordered set 2 received The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last. - RXSOPX2: u20, - padding: u12, + /// RCC APB1 Low Sleep Clock Register + C1_APB1LLPENR: mmio.Mmio(packed struct(u32) { + /// TIM2 peripheral clock enable during CSleep mode + TIM2LPEN: u1, + /// TIM3 peripheral clock enable during CSleep mode + TIM3LPEN: u1, + /// TIM4 peripheral clock enable during CSleep mode + TIM4LPEN: u1, + /// TIM5 peripheral clock enable during CSleep mode + TIM5LPEN: u1, + /// TIM6 peripheral clock enable during CSleep mode + TIM6LPEN: u1, + /// TIM7 peripheral clock enable during CSleep mode + TIM7LPEN: u1, + /// TIM12 peripheral clock enable during CSleep mode + TIM12LPEN: u1, + /// TIM13 peripheral clock enable during CSleep mode + TIM13LPEN: u1, + /// TIM14 peripheral clock enable during CSleep mode + TIM14LPEN: u1, + /// LPTIM1 Peripheral Clocks Enable During CSleep Mode + LPTIM1LPEN: u1, + reserved11: u1, + /// WWDG2 peripheral Clocks Enable During CSleep Mode + WWDG2LPEN: u1, + reserved14: u2, + /// SPI2 Peripheral Clocks Enable During CSleep Mode + SPI2LPEN: u1, + /// SPI3 Peripheral Clocks Enable During CSleep Mode + SPI3LPEN: u1, + /// SPDIFRX Peripheral Clocks Enable During CSleep Mode + SPDIFRXLPEN: u1, + /// USART2 Peripheral Clocks Enable During CSleep Mode + USART2LPEN: u1, + /// USART3 Peripheral Clocks Enable During CSleep Mode + USART3LPEN: u1, + /// UART4 Peripheral Clocks Enable During CSleep Mode + UART4LPEN: u1, + /// UART5 Peripheral Clocks Enable During CSleep Mode + UART5LPEN: u1, + /// I2C1 Peripheral Clocks Enable During CSleep Mode + I2C1LPEN: u1, + /// I2C2 Peripheral Clocks Enable During CSleep Mode + I2C2LPEN: u1, + /// I2C3 Peripheral Clocks Enable During CSleep Mode + I2C3LPEN: u1, + reserved25: u1, + /// I2C5 block enable during CSleep Mode + I2C5LPEN: u1, + reserved27: u1, + /// HDMI-CEC Peripheral Clocks Enable During CSleep Mode + CECLPEN: u1, + reserved29: u1, + /// DAC1/2 peripheral clock enable during CSleep mode + DAC12LPEN: u1, + /// UART7 Peripheral Clocks Enable During CSleep Mode + UART7LPEN: u1, + /// UART8 Peripheral Clocks Enable During CSleep Mode + UART8LPEN: u1, }), - reserved1012: [952]u8, - /// UCPD IP ID register - IPVER: mmio.Mmio(packed struct(u32) { - /// IPVER - IPVER: u32, + /// RCC APB1 High Sleep Clock Register + C1_APB1HLPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clock Recovery System peripheral clock enable during CSleep mode + CRSLPEN: u1, + /// SWPMI Peripheral Clocks Enable During CSleep Mode + SWPMILPEN: u1, + reserved4: u1, + /// OPAMP peripheral clock enable during CSleep mode + OPAMPLPEN: u1, + /// MDIOS peripheral clock enable during CSleep mode + MDIOSLPEN: u1, + reserved8: u2, + /// FDCAN Peripheral Clocks Enable During CSleep Mode + FDCANLPEN: u1, + reserved24: u15, + /// TIM23 block enable during CSleep Mode + TIM23LPEN: u1, + /// TIM24 block enable during CSleep Mode + TIM24LPEN: u1, + padding: u6, }), - /// UCPD IP ID register - IPID: mmio.Mmio(packed struct(u32) { - /// IPID - IPID: u32, + /// RCC APB2 Sleep Clock Register + C1_APB2LPENR: mmio.Mmio(packed struct(u32) { + /// TIM1 peripheral clock enable during CSleep mode + TIM1LPEN: u1, + /// TIM8 peripheral clock enable during CSleep mode + TIM8LPEN: u1, + reserved4: u2, + /// USART1 Peripheral Clocks Enable During CSleep Mode + USART1LPEN: u1, + /// USART6 Peripheral Clocks Enable During CSleep Mode + USART6LPEN: u1, + reserved12: u6, + /// SPI1 Peripheral Clocks Enable During CSleep Mode + SPI1LPEN: u1, + /// SPI4 Peripheral Clocks Enable During CSleep Mode + SPI4LPEN: u1, + reserved16: u2, + /// TIM15 peripheral clock enable during CSleep mode + TIM15LPEN: u1, + /// TIM16 peripheral clock enable during CSleep mode + TIM16LPEN: u1, + /// TIM17 peripheral clock enable during CSleep mode + TIM17LPEN: u1, + reserved20: u1, + /// SPI5 Peripheral Clocks Enable During CSleep Mode + SPI5LPEN: u1, + reserved22: u1, + /// SAI1 Peripheral Clocks Enable During CSleep Mode + SAI1LPEN: u1, + /// SAI2 Peripheral Clocks Enable During CSleep Mode + SAI2LPEN: u1, + /// SAI3 Peripheral Clocks Enable During CSleep Mode + SAI3LPEN: u1, + reserved28: u3, + /// DFSDM1 Peripheral Clocks Enable During CSleep Mode + DFSDM1LPEN: u1, + /// HRTIM peripheral clock enable during CSleep mode + HRTIMLPEN: u1, + padding: u2, }), - /// UCPD IP ID register - MID: mmio.Mmio(packed struct(u32) { - /// IPID - IPID: u32, + /// RCC APB4 Sleep Clock Register + C1_APB4LPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG peripheral clock enable during CSleep mode + SYSCFGLPEN: u1, + reserved3: u1, + /// LPUART1 Peripheral Clocks Enable During CSleep Mode + LPUART1LPEN: u1, + reserved5: u1, + /// SPI6 Peripheral Clocks Enable During CSleep Mode + SPI6LPEN: u1, + reserved7: u1, + /// I2C4 Peripheral Clocks Enable During CSleep Mode + I2C4LPEN: u1, + reserved9: u1, + /// LPTIM2 Peripheral Clocks Enable During CSleep Mode + LPTIM2LPEN: u1, + /// LPTIM3 Peripheral Clocks Enable During CSleep Mode + LPTIM3LPEN: u1, + /// LPTIM4 Peripheral Clocks Enable During CSleep Mode + LPTIM4LPEN: u1, + /// LPTIM5 Peripheral Clocks Enable During CSleep Mode + LPTIM5LPEN: u1, + reserved14: u1, + /// COMP1/2 peripheral clock enable during CSleep mode + COMP12LPEN: u1, + /// VREF peripheral clock enable during CSleep mode + VREFLPEN: u1, + /// RTC APB Clock Enable During CSleep Mode + RTCAPBLPEN: u1, + reserved21: u4, + /// SAI4 Peripheral Clocks Enable During CSleep Mode + SAI4LPEN: u1, + reserved26: u4, + /// Digital temperature sensor block enable during CSleep Mode + DTSLPEN: u1, + padding: u5, }), }; }; - pub const rcc_h7rm0433 = struct { + pub const rcc_h7ab = struct { pub const ADCSEL = enum(u2) { /// pll2_p selected as peripheral clock PLL2_P = 0x0, @@ -406739,10 +389552,10 @@ pub const types = struct { pub const LSEDRV = enum(u2) { /// Low driving capability Low = 0x0, - /// Medium high driving capability - MediumHigh = 0x1, /// Medium low driving capability - MediumLow = 0x2, + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, /// High driving capability High = 0x3, }; @@ -407531,3779 +390344,23926 @@ pub const types = struct { _, }; - pub const PLLRGE = enum(u2) { - /// Frequency is between 1 and 2 MHz - Range1 = 0x0, - /// Frequency is between 2 and 4 MHz - Range2 = 0x1, - /// Frequency is between 4 and 8 MHz - Range4 = 0x2, - /// Frequency is between 8 and 16 MHz - Range8 = 0x3, + pub const PLLRGE = enum(u2) { + /// Frequency is between 1 and 2 MHz + Range1 = 0x0, + /// Frequency is between 2 and 4 MHz + Range2 = 0x1, + /// Frequency is between 4 and 8 MHz + Range4 = 0x2, + /// Frequency is between 8 and 16 MHz + Range8 = 0x3, + }; + + pub const PLLSRC = enum(u2) { + /// HSI selected as PLL clock + HSI = 0x0, + /// CSI selected as PLL clock + CSI = 0x1, + /// HSE selected as PLL clock + HSE = 0x2, + /// No clock sent to DIVMx dividers and PLLs + DISABLE = 0x3, + }; + + pub const PLLVCOSEL = enum(u1) { + /// VCO frequency range 192 to 836 MHz + WideVCO = 0x0, + /// VCO frequency range 150 to 420 MHz + MediumVCO = 0x1, + }; + + pub const PPRE = enum(u3) { + /// rcc_hclk not divided + Div1 = 0x0, + /// rcc_hclk divided by 2 + Div2 = 0x4, + /// rcc_hclk divided by 4 + Div4 = 0x5, + /// rcc_hclk divided by 8 + Div8 = 0x6, + /// rcc_hclk divided by 16 + Div16 = 0x7, + _, + }; + + pub const RNGSEL = enum(u2) { + /// HSI48 selected as peripheral clock + HSI48 = 0x0, + /// pll1_q selected as peripheral clock + PLL1_Q = 0x1, + /// LSE selected as peripheral clock + LSE = 0x2, + /// LSI selected as peripheral clock + LSI = 0x3, + }; + + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, + }; + + pub const SAIASEL = enum(u3) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_p selected as peripheral clock + PLL3_P = 0x2, + /// i2s_ckin selected as peripheral clock + I2S_CKIN = 0x3, + /// PER selected as peripheral clock + PER = 0x4, + _, + }; + + pub const SAISEL = enum(u3) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_p selected as peripheral clock + PLL3_P = 0x2, + /// I2S_CKIN selected as peripheral clock + I2S_CKIN = 0x3, + /// PER selected as peripheral clock + PER = 0x4, + _, + }; + + pub const SDMMCSEL = enum(u1) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_r selected as peripheral clock + PLL2_R = 0x1, + }; + + pub const SPDIFRXSEL = enum(u2) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_r selected as peripheral clock + PLL2_R = 0x1, + /// pll3_r selected as peripheral clock + PLL3_R = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + }; + + pub const SPI45SEL = enum(u3) { + /// APB2 clock selected as peripheral clock + PCLK2 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// HSE selected as peripheral clock + HSE = 0x5, + _, + }; + + pub const SPI6SEL = enum(u3) { + /// rcc_pclk4 selected as peripheral clock + PCLK4 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// HSE selected as peripheral clock + HSE = 0x5, + _, + }; + + pub const STOPWUCK = enum(u1) { + /// HSI selected as wake up clock from system Stop + HSI = 0x0, + /// CSI selected as wake up clock from system Stop + CSI = 0x1, + }; + + pub const SW = enum(u3) { + /// HSI selected as system clock + HSI = 0x0, + /// CSI selected as system clock + CSI = 0x1, + /// HSE selected as system clock + HSE = 0x2, + /// PLL1 selected as system clock + PLL1_P = 0x3, + _, + }; + + pub const SWPMISEL = enum(u1) { + /// pclk selected as peripheral clock + PCLK1 = 0x0, + /// hsi_ker selected as peripheral clock + HSI = 0x1, + }; + + pub const TIMPRE = enum(u1) { + /// Timer kernel clock equal to 2x pclk by default + DefaultX2 = 0x0, + /// Timer kernel clock equal to 4x pclk by default + DefaultX4 = 0x1, + }; + + pub const USART16910SEL = enum(u3) { + /// rcc_pclk2 selected as peripheral clock + PCLK2 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, + }; + + pub const USART234578SEL = enum(u3) { + /// rcc_pclk1 selected as peripheral clock + PCLK1 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, + }; + + pub const USBSEL = enum(u2) { + /// Disable the kernel clock + DISABLE = 0x0, + /// pll1_q selected as peripheral clock + PLL1_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// HSI48 selected as peripheral clock + HSI48 = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal high-speed clock enable + HSION: u1, + /// High Speed Internal clock enable in Stop mode + HSIKERON: u1, + /// HSI clock ready flag + HSIRDY: u1, + /// HSI clock divider + HSIDIV: packed union { + raw: u2, + value: HSIDIV, + }, + /// HSI divider flag + HSIDIVF: u1, + reserved7: u1, + /// CSI clock enable + CSION: u1, + /// CSI clock ready flag + CSIRDY: u1, + /// CSI clock enable in Stop mode + CSIKERON: u1, + reserved12: u2, + /// RC48 clock enable + HSI48ON: u1, + /// RC48 clock ready flag + HSI48RDY: u1, + /// D1 domain clocks ready flag + D1CKRDY: u1, + /// D2 domain clocks ready flag + D2CKRDY: u1, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + /// HSE Clock Security System enable + HSECSSON: u1, + reserved24: u4, + /// PLL1 enable + PLLON: u1, + /// PLL1 clock ready flag + PLLRDY: u1, + padding: u6, + }), + /// RCC HSI configuration register + HSICFGR: mmio.Mmio(packed struct(u32) { + /// HSI clock calibration + HSICAL: u12, + reserved24: u12, + /// HSI clock trimming + HSITRIM: u7, + padding: u1, + }), + /// RCC Clock Recovery RC Register + CRRCR: mmio.Mmio(packed struct(u32) { + /// Internal RC 48 MHz clock calibration + HSI48CAL: u10, + padding: u22, + }), + /// RCC CSI configuration register + CSICFGR: mmio.Mmio(packed struct(u32) { + /// CSI clock calibration + CSICAL: u9, + reserved24: u15, + /// CSI clock trimming + CSITRIM: u6, + padding: u2, + }), + /// RCC Clock Configuration Register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u3, + value: SW, + }, + /// System clock switch status + SWS: packed union { + raw: u3, + value: SW, + }, + /// System clock selection after a wake up from system Stop + STOPWUCK: packed union { + raw: u1, + value: STOPWUCK, + }, + /// Kernel clock selection after a wake up from system Stop + STOPKERWUCK: packed union { + raw: u1, + value: STOPWUCK, + }, + /// HSE division factor for RTC clock + RTCPRE: u6, + /// High Resolution Timer clock prescaler selection + HRTIMSEL: packed union { + raw: u1, + value: HRTIMSEL, + }, + /// Timers clocks prescaler selection + TIMPRE: packed union { + raw: u1, + value: TIMPRE, + }, + reserved18: u2, + /// MCO1 prescaler + MCO1PRE: packed union { + raw: u4, + value: MCOPRE, + }, + /// Micro-controller clock output 1 + MCO1SEL: packed union { + raw: u3, + value: MCO1SEL, + }, + /// MCO2 prescaler + MCO2PRE: packed union { + raw: u4, + value: MCOPRE, + }, + /// Micro-controller clock output 2 + MCO2SEL: packed union { + raw: u3, + value: MCO2SEL, + }, + }), + reserved24: [4]u8, + /// RCC Domain 1 Clock Configuration Register + D1CFGR: mmio.Mmio(packed struct(u32) { + /// D1 domain AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// D1 domain APB3 prescaler + D1PPRE: packed union { + raw: u3, + value: PPRE, + }, + reserved8: u1, + /// D1 domain Core prescaler + D1CPRE: packed union { + raw: u4, + value: HPRE, + }, + padding: u20, + }), + /// RCC Domain 2 Clock Configuration Register + D2CFGR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// D2 domain APB1 prescaler + D2PPRE1: packed union { + raw: u3, + value: PPRE, + }, + reserved8: u1, + /// D2 domain APB2 prescaler + D2PPRE2: packed union { + raw: u3, + value: PPRE, + }, + padding: u21, + }), + /// RCC Domain 3 Clock Configuration Register + D3CFGR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// D3 domain APB4 prescaler + D3PPRE: packed union { + raw: u3, + value: PPRE, + }, + padding: u25, + }), + reserved40: [4]u8, + /// RCC PLLs Clock Source Selection Register + PLLCKSELR: mmio.Mmio(packed struct(u32) { + /// DIVMx and PLLs clock source selection + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + reserved4: u2, + /// Prescaler for PLL1 + DIVM: packed union { + raw: u6, + value: PLLM, + }, + padding: u22, + }), + /// RCC PLLs Configuration Register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// PLL1 fractional latch enable + PLLFRACEN: u1, + /// PLL1 VCO selection + PLLVCOSEL: packed union { + raw: u1, + value: PLLVCOSEL, + }, + /// PLL1 input frequency range + PLLRGE: packed union { + raw: u2, + value: PLLRGE, + }, + reserved16: u12, + /// PLL1 DIVP divider output enable + DIVPEN: u1, + /// PLL1 DIVQ divider output enable + DIVQEN: u1, + /// PLL1 DIVR divider output enable + DIVREN: u1, + padding: u13, + }), + /// RCC PLL1 Dividers Configuration Register + PLLDIVR: mmio.Mmio(packed struct(u32) { + /// Multiplication factor for PLL1 VCO + PLLN: packed union { + raw: u9, + value: PLLN, + }, + /// PLL DIVP division factor + PLLP: packed union { + raw: u7, + value: PLLDIV, + }, + /// PLL DIVQ division factor + PLLQ: packed union { + raw: u7, + value: PLLDIV, + }, + reserved24: u1, + /// PLL DIVR division factor + PLLR: packed union { + raw: u7, + value: PLLDIV, + }, + padding: u1, + }), + /// RCC PLL1 Fractional Divider Register + PLLFRACR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Fractional part of the multiplication factor for PLL VCO + FRACN: u13, + padding: u16, + }), + reserved76: [20]u8, + /// RCC Domain 1 Kernel Clock Configuration Register + D1CCIPR: mmio.Mmio(packed struct(u32) { + /// FMC kernel clock source selection + FMCSEL: packed union { + raw: u2, + value: FMCSEL, + }, + reserved4: u2, + /// OCTOSPI kernel clock source selection + OCTOSPISEL: packed union { + raw: u2, + value: FMCSEL, + }, + reserved16: u10, + /// SDMMC kernel clock source selection + SDMMCSEL: packed union { + raw: u1, + value: SDMMCSEL, + }, + reserved28: u11, + /// per_ck clock source selection + PERSEL: packed union { + raw: u2, + value: PERSEL, + }, + padding: u2, + }), + /// RCC Domain 2 Kernel Clock Configuration Register + D2CCIP1R: mmio.Mmio(packed struct(u32) { + /// SAI1 and DFSDM1 kernel Aclk clock source selection + SAI1SEL: packed union { + raw: u3, + value: SAISEL, + }, + reserved6: u3, + /// SAI2 kernel clock source A source selection + SAI2ASEL: packed union { + raw: u3, + value: SAIASEL, + }, + /// SAI2 kernel clock source B source selection + SAI2BSEL: packed union { + raw: u3, + value: SAIASEL, + }, + /// SPI/I2S1,2 and 3 kernel clock source selection + SPI123SEL: packed union { + raw: u3, + value: SAISEL, + }, + reserved16: u1, + /// SPI4 and 5 kernel clock source selection + SPI45SEL: packed union { + raw: u3, + value: SPI45SEL, + }, + reserved20: u1, + /// SPDIFRX kernel clock source selection + SPDIFRXSEL: packed union { + raw: u2, + value: SPDIFRXSEL, + }, + reserved24: u2, + /// DFSDM1 kernel Clk clock source selection + DFSDM1SEL: packed union { + raw: u1, + value: DFSDMSEL, + }, + reserved28: u3, + /// FDCAN kernel clock source selection + FDCANSEL: packed union { + raw: u2, + value: FDCANSEL, + }, + reserved31: u1, + /// SWPMI kernel clock source selection + SWPMISEL: packed union { + raw: u1, + value: SWPMISEL, + }, + }), + /// RCC Domain 2 Kernel Clock Configuration Register + D2CCIP2R: mmio.Mmio(packed struct(u32) { + /// USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection + USART234578SEL: packed union { + raw: u3, + value: USART234578SEL, + }, + /// USART1, 6, 9 and 10 kernel clock source selection + USART16910SEL: packed union { + raw: u3, + value: USART16910SEL, + }, + reserved8: u2, + /// RNG kernel clock source selection + RNGSEL: packed union { + raw: u2, + value: RNGSEL, + }, + reserved12: u2, + /// I2C1,2,3 kernel clock source selection + I2C1235SEL: packed union { + raw: u2, + value: I2C1235SEL, + }, + reserved20: u6, + /// USBOTG 1 and 2 kernel clock source selection + USBSEL: packed union { + raw: u2, + value: USBSEL, + }, + /// HDMI-CEC kernel clock source selection + CECSEL: packed union { + raw: u2, + value: CECSEL, + }, + reserved28: u4, + /// LPTIM1 kernel clock source selection + LPTIM1SEL: packed union { + raw: u3, + value: LPTIM1SEL, + }, + padding: u1, + }), + /// RCC Domain 3 Kernel Clock Configuration Register + D3CCIPR: mmio.Mmio(packed struct(u32) { + /// LPUART1 kernel clock source selection + LPUART1SEL: packed union { + raw: u3, + value: LPUARTSEL, + }, + reserved8: u5, + /// I2C4 kernel clock source selection + I2C4SEL: packed union { + raw: u2, + value: I2C4SEL, + }, + /// LPTIM2 kernel clock source selection + LPTIM2SEL: packed union { + raw: u3, + value: LPTIM2SEL, + }, + /// LPTIM3,4,5 kernel clock source selection + LPTIM345SEL: packed union { + raw: u3, + value: LPTIM2SEL, + }, + /// SAR ADC kernel clock source selection + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, + reserved27: u9, + /// DFSDM2 kernel clock source selection + DFSDM2SEL: u1, + /// SPI6 kernel clock source selection + SPI6SEL: packed union { + raw: u3, + value: SPI6SEL, + }, + padding: u1, + }), + reserved96: [4]u8, + /// RCC Clock Source Interrupt Enable Register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready Interrupt Enable + LSIRDYIE: u1, + /// LSE ready Interrupt Enable + LSERDYIE: u1, + /// HSI ready Interrupt Enable + HSIRDYIE: u1, + /// HSE ready Interrupt Enable + HSERDYIE: u1, + /// CSI ready Interrupt Enable + CSIRDYIE: u1, + /// RC48 ready Interrupt Enable + HSI48RDYIE: u1, + /// PLL1 ready Interrupt Enable + PLLRDYIE: u1, + reserved9: u2, + /// LSE clock security system Interrupt Enable + LSECSSIE: u1, + padding: u22, + }), + /// RCC Clock Source Interrupt Flag Register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready Interrupt Flag + LSIRDYF: u1, + /// LSE ready Interrupt Flag + LSERDYF: u1, + /// HSI ready Interrupt Flag + HSIRDYF: u1, + /// HSE ready Interrupt Flag + HSERDYF: u1, + /// CSI ready Interrupt Flag + CSIRDYF: u1, + /// RC48 ready Interrupt Flag + HSI48RDYF: u1, + /// PLL1 ready Interrupt Flag + PLLRDYF: u1, + reserved9: u2, + /// LSE clock security system Interrupt Flag + LSECSSF: u1, + /// HSE clock security system Interrupt Flag + HSECSSF: u1, + padding: u21, + }), + /// RCC Clock Source Interrupt Clear Register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready Interrupt Clear + LSIRDYC: u1, + /// LSE ready Interrupt Clear + LSERDYC: u1, + /// HSI ready Interrupt Clear + HSIRDYC: u1, + /// HSE ready Interrupt Clear + HSERDYC: u1, + /// CSI ready Interrupt Clear + HSE_ready_Interrupt_Clear: u1, + /// RC48 ready Interrupt Clear + HSI48RDYC: u1, + /// PLL1 ready Interrupt Clear + PLLRDYC: u1, + reserved9: u2, + /// LSE clock security system Interrupt Clear + LSECSSC: u1, + /// HSE clock security system Interrupt Clear + HSECSSC: u1, + padding: u21, + }), + reserved112: [4]u8, + /// RCC Backup Domain Control Register + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enabled + LSEON: u1, + /// LSE oscillator ready + LSERDY: u1, + /// LSE oscillator bypass + LSEBYP: u1, + /// LSE oscillator driving capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// LSE clock security system enable + LSECSSON: u1, + /// LSE clock security system failure detection + LSECSSD: u1, + reserved8: u1, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// VSwitch domain software reset + BDRST: u1, + padding: u15, + }), + /// RCC Clock Control and Status Register + CSR: mmio.Mmio(packed struct(u32) { + /// LSI oscillator enable + LSION: u1, + /// LSI oscillator ready + LSIRDY: u1, + padding: u30, + }), + reserved124: [4]u8, + /// RCC AHB3 Reset Register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// MDMA block reset + MDMARST: u1, + reserved4: u3, + /// DMA2D block reset + DMA2DRST: u1, + /// JPGDEC block reset + JPGDECRST: u1, + reserved12: u6, + /// FMC block reset + FMCRST: u1, + reserved14: u1, + /// OCTOSPI1 and OCTOSPI1 delay block reset + OCTOSPI1RST: u1, + reserved16: u1, + /// SDMMC1 and SDMMC1 delay block reset + SDMMC1RST: u1, + reserved19: u2, + /// OCTOSPI2 and OCTOSPI2 delay block reset + OCTOSPI2RST: u1, + reserved21: u1, + /// OCTOSPI IO manager reset + IOMNGRRST: u1, + /// OTFDEC1 reset + OTFD1RST: u1, + /// OTFDEC2 reset + OTFD2RST: u1, + reserved31: u7, + /// CPU reset + CPURST: u1, + }), + /// RCC AHB1 Peripheral Reset Register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// DMA1 block reset + DMA1RST: u1, + /// DMA2 block reset + DMA2RST: u1, + reserved5: u3, + /// ADC1&2 block reset + ADC12RST: u1, + reserved14: u8, + /// ART block reset + ARTRST: u1, + /// ETH block reset + ETHRST: u1, + reserved25: u9, + /// USB_OTG_HS block reset + USB_OTG_HSRST: u1, + reserved27: u1, + /// USB_OTG_FS block reset + USB_OTG_FSRST: u1, + padding: u4, + }), + /// RCC AHB2 Peripheral Reset Register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// DCMI block reset + DCMIRST: u1, + reserved4: u3, + /// CRYPography block reset + CRYPRST: u1, + /// Hash block reset + HASHRST: u1, + /// Random Number Generator block reset + RNGRST: u1, + reserved9: u2, + /// SDMMC2 and SDMMC2 Delay block reset + SDMMC2RST: u1, + reserved11: u1, + /// BDMA1 block reset + BDMA1RST: u1, + reserved16: u4, + /// FMAC reset + FMACRST: u1, + /// CORDIC reset + CORDICRST: u1, + padding: u14, + }), + /// RCC AHB4 Peripheral Reset Register + AHB4RSTR: mmio.Mmio(packed struct(u32) { + /// GPIO block reset + GPIOARST: u1, + /// GPIO block reset + GPIOBRST: u1, + /// GPIO block reset + GPIOCRST: u1, + /// GPIO block reset + GPIODRST: u1, + /// GPIO block reset + GPIOERST: u1, + /// GPIO block reset + GPIOFRST: u1, + /// GPIO block reset + GPIOGRST: u1, + /// GPIO block reset + GPIOHRST: u1, + /// GPIO block reset + GPIOIRST: u1, + /// GPIO block reset + GPIOJRST: u1, + /// GPIO block reset + GPIOKRST: u1, + reserved19: u8, + /// CRC block reset + CRCRST: u1, + reserved21: u1, + /// BDMA2 block reset + BDMA2RST: u1, + reserved24: u2, + /// ADC3 block reset + ADC3RST: u1, + /// HSEM block reset + HSEMRST: u1, + padding: u6, + }), + /// RCC APB3 Peripheral Reset Register + APB3RSTR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC block reset + LTDCRST: u1, + /// DSI block reset + DSIRST: u1, + padding: u27, + }), + /// RCC APB1 Peripheral Reset Register + APB1LRSTR: mmio.Mmio(packed struct(u32) { + /// TIM block reset + TIM2RST: u1, + /// TIM block reset + TIM3RST: u1, + /// TIM block reset + TIM4RST: u1, + /// TIM block reset + TIM5RST: u1, + /// TIM block reset + TIM6RST: u1, + /// TIM block reset + TIM7RST: u1, + /// TIM block reset + TIM12RST: u1, + /// TIM block reset + TIM13RST: u1, + /// TIM block reset + TIM14RST: u1, + /// TIM block reset + LPTIM1RST: u1, + reserved14: u4, + /// SPI2 block reset + SPI2RST: u1, + /// SPI3 block reset + SPI3RST: u1, + /// SPDIFRX block reset + SPDIFRXRST: u1, + /// USART2 block reset + USART2RST: u1, + /// USART3 block reset + USART3RST: u1, + /// UART4 block reset + UART4RST: u1, + /// UART5 block reset + UART5RST: u1, + /// I2C1 block reset + I2C1RST: u1, + /// I2C2 block reset + I2C2RST: u1, + /// I2C3 block reset + I2C3RST: u1, + reserved25: u1, + /// I2C5 block reset + I2C5RST: u1, + reserved27: u1, + /// HDMI-CEC block reset + CECRST: u1, + reserved29: u1, + /// DAC1 (containing two converters) reset + DAC1RST: u1, + /// UART7 block reset + UART7RST: u1, + /// UART8 block reset + UART8RST: u1, + }), + /// RCC APB1 Peripheral Reset Register + APB1HRSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clock Recovery System reset + CRSRST: u1, + /// SWPMI block reset + SWPMIRST: u1, + reserved4: u1, + /// OPAMP block reset + OPAMPRST: u1, + /// MDIOS block reset + MDIOSRST: u1, + reserved8: u2, + /// FDCAN block reset + FDCANRST: u1, + reserved24: u15, + /// TIM23 block reset + TIM23RST: u1, + /// TIM24 block reset + TIM24RST: u1, + padding: u6, + }), + /// RCC APB2 Peripheral Reset Register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// TIM1 block reset + TIM1RST: u1, + /// TIM8 block reset + TIM8RST: u1, + reserved4: u2, + /// USART1 block reset + USART1RST: u1, + /// USART6 block reset + USART6RST: u1, + /// UART9 block reset + UART9RST: u1, + /// USART10 block reset + USART10RST: u1, + reserved12: u4, + /// SPI1 block reset + SPI1RST: u1, + /// SPI4 block reset + SPI4RST: u1, + reserved16: u2, + /// TIM15 block reset + TIM15RST: u1, + /// TIM16 block reset + TIM16RST: u1, + /// TIM17 block reset + TIM17RST: u1, + reserved20: u1, + /// SPI5 block reset + SPI5RST: u1, + reserved22: u1, + /// SAI1 block reset + SAI1RST: u1, + /// SAI2 block reset + SAI2RST: u1, + /// SAI3 block reset + SAI3RST: u1, + reserved28: u3, + /// DFSDM1 block reset + DFSDM1RST: u1, + /// HRTIM block reset + HRTIMRST: u1, + padding: u2, + }), + /// RCC APB4 Peripheral Reset Register + APB4RSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG block reset + SYSCFGRST: u1, + reserved3: u1, + /// LPUART1 block reset + LPUART1RST: u1, + reserved5: u1, + /// SPI6 block reset + SPI6RST: u1, + reserved7: u1, + /// I2C4 block reset + I2C4RST: u1, + reserved9: u1, + /// LPTIM2 block reset + LPTIM2RST: u1, + /// LPTIM3 block reset + LPTIM3RST: u1, + /// LPTIM4 block reset + LPTIM4RST: u1, + /// LPTIM5 block reset + LPTIM5RST: u1, + /// DAC2 (containing one converter) reset + DAC2RST: u1, + /// COMP12 Blocks Reset + COMP12RST: u1, + /// VREF block reset + VREFRST: u1, + reserved21: u5, + /// SAI4 block reset + SAI4RST: u1, + reserved26: u4, + /// Digital temperature sensor block reset + DTSRST: u1, + padding: u5, + }), + /// Global Control Register + GCR: mmio.Mmio(packed struct(u32) { + /// WWDG1 reset scope control + WW1RSC: u1, + padding: u31, + }), + reserved168: [4]u8, + /// RCC D3 Autonomous mode Register + D3AMR: mmio.Mmio(packed struct(u32) { + /// BDMA2 and DMAMUX Autonomous mode enable + BDMA2AMEN: u1, + reserved3: u2, + /// LPUART1 Autonomous mode enable + LPUART1AMEN: u1, + reserved5: u1, + /// SPI6 Autonomous mode enable + SPI6AMEN: u1, + reserved7: u1, + /// I2C4 Autonomous mode enable + I2C4AMEN: u1, + reserved9: u1, + /// LPTIM2 Autonomous mode enable + LPTIM2AMEN: u1, + /// LPTIM3 Autonomous mode enable + LPTIM3AMEN: u1, + /// LPTIM4 Autonomous mode enable + LPTIM4AMEN: u1, + /// LPTIM5 Autonomous mode enable + LPTIM5AMEN: u1, + /// DAC2 (containing one converter) Autonomous mode enable + DAC2AMEN: u1, + /// COMP12 Autonomous mode enable + COMP12AMEN: u1, + /// VREF Autonomous mode enable + VREFAMEN: u1, + /// RTC Autonomous mode enable + RTCAMEN: u1, + reserved19: u2, + /// CRC Autonomous mode enable + CRCAMEN: u1, + reserved21: u1, + /// SAI4 Autonomous mode enable + SAI4AMEN: u1, + reserved24: u2, + /// ADC3 Autonomous mode enable + ADC3AMEN: u1, + reserved26: u1, + /// Digital temperature sensor Autonomous mode enable + DTSAMEN: u1, + reserved28: u1, + /// Backup RAM Autonomous mode enable + BKPSRAMAMEN: u1, + /// SRAM4 Autonomous mode enable + SRAM4AMEN: u1, + padding: u2, + }), + reserved304: [132]u8, + /// RCC Reset Status Register + RSR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Remove reset flag + RMVF: u1, + /// CPU reset flag + CPURSTF: u1, + reserved19: u1, + /// D1 domain power switch reset flag + D1RSTF: u1, + /// D2 domain power switch reset flag + D2RSTF: u1, + /// BOR reset flag + BORRSTF: u1, + /// Pin reset flag (NRST) + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// System reset from CPU reset flag + SFTRSTF: u1, + reserved26: u1, + /// Independent Watchdog reset flag + IWDG1RSTF: u1, + reserved28: u1, + /// Window Watchdog reset flag + WWDG1RSTF: u1, + reserved30: u1, + /// Reset due to illegal D1 DStandby or CPU CStop flag + LPWRRSTF: u1, + padding: u1, + }), + /// RCC AHB3 Clock Register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// MDMA Peripheral Clock Enable + MDMAEN: u1, + reserved4: u3, + /// DMA2D Peripheral Clock Enable + DMA2DEN: u1, + /// JPGDEC Peripheral Clock Enable + JPGDECEN: u1, + reserved12: u6, + /// FMC Peripheral Clocks Enable + FMCEN: u1, + reserved14: u1, + /// OCTOSPI1 and OCTOSPI1 Delay Clock Enable + OCTOSPI1EN: u1, + reserved16: u1, + /// SDMMC1 and SDMMC1 Delay Clock Enable + SDMMC1EN: u1, + reserved19: u2, + /// OCTOSPI2 and OCTOSPI2 delay block enable + OCTOSPI2EN: u1, + reserved21: u1, + /// OCTOSPI IO manager enable + IOMNGREN: u1, + /// OTFDEC1 enable + OTFD1EN: u1, + /// OTFDEC2 enable + OTFD2EN: u1, + reserved28: u4, + /// D1 DTCM1 block enable + DTCM1EN: u1, + /// D1 DTCM2 block enable + DTCM2EN: u1, + /// D1 ITCM block enable + ITCM1EN: u1, + /// AXISRAM block enable + AXISRAMEN: u1, + }), + /// RCC AHB1 Clock Register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// DMA1 Clock Enable + DMA1EN: u1, + /// DMA2 Clock Enable + DMA2EN: u1, + reserved5: u3, + /// ADC1/2 Peripheral Clocks Enable + ADC12EN: u1, + reserved14: u8, + /// ART Clock Enable + ARTEN: u1, + /// Ethernet MAC bus interface Clock Enable + ETHEN: u1, + /// Ethernet Transmission Clock Enable + ETHTXEN: u1, + /// Ethernet Reception Clock Enable + ETHRXEN: u1, + reserved25: u7, + /// USB_OTG_HS Peripheral Clocks Enable + USB_OTG_HSEN: u1, + /// USB_OTG_HS ULPI clock enable + USB_OTG_HS_ULPIEN: u1, + /// USB_OTG_FS Peripheral Clocks Enable + USB_OTG_FSEN: u1, + /// USB_OTG_FS ULPI clock enable + USB_OTG_FS_ULPIEN: u1, + padding: u3, + }), + /// RCC AHB2 Clock Register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// DCMI peripheral clock + DCMIEN: u1, + reserved4: u3, + /// CRYP peripheral clock enable + CRYPEN: u1, + /// HASH peripheral clock enable + HASHEN: u1, + /// RNG peripheral clocks enable + RNGEN: u1, + reserved9: u2, + /// SDMMC2 and SDMMC2 delay clock enable + SDMMC2EN: u1, + reserved11: u1, + /// BDMA1 clock enable + BDMA1EN: u1, + reserved16: u4, + /// FMAC enable + FMACEN: u1, + /// CORDIC enable + CORDICEN: u1, + reserved29: u11, + /// SRAM1 block enable + SRAM1EN: u1, + /// SRAM2 block enable + SRAM2EN: u1, + /// SRAM3 block enable + SRAM3EN: u1, + }), + /// RCC AHB4 Clock Register + AHB4ENR: mmio.Mmio(packed struct(u32) { + /// 0GPIO peripheral clock enable + GPIOAEN: u1, + /// 0GPIO peripheral clock enable + GPIOBEN: u1, + /// 0GPIO peripheral clock enable + GPIOCEN: u1, + /// 0GPIO peripheral clock enable + GPIODEN: u1, + /// 0GPIO peripheral clock enable + GPIOEEN: u1, + /// 0GPIO peripheral clock enable + GPIOFEN: u1, + /// 0GPIO peripheral clock enable + GPIOGEN: u1, + /// 0GPIO peripheral clock enable + GPIOHEN: u1, + /// 0GPIO peripheral clock enable + GPIOIEN: u1, + /// 0GPIO peripheral clock enable + GPIOJEN: u1, + /// 0GPIO peripheral clock enable + GPIOKEN: u1, + reserved19: u8, + /// CRC peripheral clock enable + CRCEN: u1, + reserved21: u1, + /// BDMA2 and DMAMUX2 Clock Enable + BDMA2EN: u1, + reserved24: u2, + /// ADC3 Peripheral Clocks Enable + ADC3EN: u1, + /// HSEM peripheral clock enable + HSEMEN: u1, + reserved28: u2, + /// Backup RAM Clock Enable + BKPSRAMEN: u1, + padding: u3, + }), + /// RCC APB3 Clock Register + APB3ENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC peripheral clock enable + LTDCEN: u1, + /// DSI Peripheral clocks enable + DSIEN: u1, + reserved6: u1, + /// WWDG1 Clock Enable + WWDG1EN: u1, + padding: u25, + }), + /// RCC APB1 Clock Register + APB1LENR: mmio.Mmio(packed struct(u32) { + /// TIM peripheral clock enable + TIM2EN: u1, + /// TIM peripheral clock enable + TIM3EN: u1, + /// TIM peripheral clock enable + TIM4EN: u1, + /// TIM peripheral clock enable + TIM5EN: u1, + /// TIM peripheral clock enable + TIM6EN: u1, + /// TIM peripheral clock enable + TIM7EN: u1, + /// TIM peripheral clock enable + TIM12EN: u1, + /// TIM peripheral clock enable + TIM13EN: u1, + /// TIM peripheral clock enable + TIM14EN: u1, + /// LPTIM1 Peripheral Clocks Enable + LPTIM1EN: u1, + reserved11: u1, + /// WWDG2 peripheral clock enable + WWDG2EN: u1, + reserved14: u2, + /// SPI2 Peripheral Clocks Enable + SPI2EN: u1, + /// SPI3 Peripheral Clocks Enable + SPI3EN: u1, + /// SPDIFRX Peripheral Clocks Enable + SPDIFRXEN: u1, + /// USART2 Peripheral Clocks Enable + USART2EN: u1, + /// USART3 Peripheral Clocks Enable + USART3EN: u1, + /// UART4 Peripheral Clocks Enable + UART4EN: u1, + /// UART5 Peripheral Clocks Enable + UART5EN: u1, + /// I2C1 Peripheral Clocks Enable + I2C1EN: u1, + /// I2C2 Peripheral Clocks Enable + I2C2EN: u1, + /// I2C3 Peripheral Clocks Enable + I2C3EN: u1, + reserved25: u1, + /// I2C5 Peripheral Clocks Enable + I2C5EN: u1, + reserved27: u1, + /// HDMI-CEC peripheral clock enable + CECEN: u1, + reserved29: u1, + /// DAC1 (containing two converters) peripheral clock enable + DAC1EN: u1, + /// UART7 Peripheral Clocks Enable + UART7EN: u1, + /// UART8 Peripheral Clocks Enable + UART8EN: u1, + }), + /// RCC APB1 Clock Register + APB1HENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clock Recovery System peripheral clock enable + CRSEN: u1, + /// SWPMI Peripheral Clocks Enable + SWPMIEN: u1, + reserved4: u1, + /// OPAMP peripheral clock enable + OPAMPEN: u1, + /// MDIOS peripheral clock enable + MDIOSEN: u1, + reserved8: u2, + /// FDCAN Peripheral Clocks Enable + FDCANEN: u1, + reserved24: u15, + /// TIM23 block enable + TIM23EN: u1, + /// TIM24 block enable + TIM24EN: u1, + padding: u6, + }), + /// RCC APB2 Clock Register + APB2ENR: mmio.Mmio(packed struct(u32) { + /// TIM1 peripheral clock enable + TIM1EN: u1, + /// TIM8 peripheral clock enable + TIM8EN: u1, + reserved4: u2, + /// USART1 Peripheral Clocks Enable + USART1EN: u1, + /// USART6 Peripheral Clocks Enable + USART6EN: u1, + /// UART9 Peripheral Clocks Enable + UART9EN: u1, + /// USART10 Peripheral Clocks Enable + USART10EN: u1, + reserved12: u4, + /// SPI1 Peripheral Clocks Enable + SPI1EN: u1, + /// SPI4 Peripheral Clocks Enable + SPI4EN: u1, + reserved16: u2, + /// TIM15 peripheral clock enable + TIM15EN: u1, + /// TIM16 peripheral clock enable + TIM16EN: u1, + /// TIM17 peripheral clock enable + TIM17EN: u1, + reserved20: u1, + /// SPI5 Peripheral Clocks Enable + SPI5EN: u1, + reserved22: u1, + /// SAI1 Peripheral Clocks Enable + SAI1EN: u1, + /// SAI2 Peripheral Clocks Enable + SAI2EN: u1, + /// SAI3 Peripheral Clocks Enable + SAI3EN: u1, + reserved28: u3, + /// DFSDM1 Peripheral Clocks Enable + DFSDM1EN: u1, + /// HRTIM peripheral clock enable + HRTIMEN: u1, + padding: u2, + }), + /// RCC APB4 Clock Register + APB4ENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG peripheral clock enable + SYSCFGEN: u1, + reserved3: u1, + /// LPUART1 Peripheral Clocks Enable + LPUART1EN: u1, + reserved5: u1, + /// SPI6 Peripheral Clocks Enable + SPI6EN: u1, + reserved7: u1, + /// I2C4 Peripheral Clocks Enable + I2C4EN: u1, + reserved9: u1, + /// LPTIM2 Peripheral Clocks Enable + LPTIM2EN: u1, + /// LPTIM3 Peripheral Clocks Enable + LPTIM3EN: u1, + /// LPTIM4 Peripheral Clocks Enable + LPTIM4EN: u1, + /// LPTIM5 Peripheral Clocks Enable + LPTIM5EN: u1, + /// DAC2 (containing one converter) peripheral clock enable + DAC2EN: u1, + /// COMP1/2 peripheral clock enable + COMP12EN: u1, + /// VREF peripheral clock enable + VREFEN: u1, + /// RTC APB Clock Enable + RTCAPBEN: u1, + reserved21: u4, + /// SAI4 Peripheral Clocks Enable + SAI4EN: u1, + reserved26: u4, + /// Digital temperature sensor block enable + DTSEN: u1, + padding: u5, + }), + reserved348: [4]u8, + /// RCC AHB3 Sleep Clock Register + AHB3LPENR: mmio.Mmio(packed struct(u32) { + /// MDMA Clock Enable During CSleep Mode + MDMALPEN: u1, + reserved4: u3, + /// DMA2D Clock Enable During CSleep Mode + DMA2DLPEN: u1, + /// JPGDEC Clock Enable During CSleep Mode + JPGDECLPEN: u1, + reserved8: u2, + /// FLASH Clock Enable During CSleep Mode + FLASHLPEN: u1, + reserved12: u3, + /// FMC Peripheral Clocks Enable During CSleep Mode + FMCLPEN: u1, + reserved14: u1, + /// OCTOSPI1 and OCTOSPI1 Delay Clock Enable During CSleep Mode + OCTOSPI1LPEN: u1, + reserved16: u1, + /// SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + SDMMC1LPEN: u1, + reserved19: u2, + /// OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode + OCTOSPI2LPEN: u1, + reserved21: u1, + /// OCTOSPI IO manager enable during CSleep Mode + IOMNGRLPEN: u1, + /// OTFDEC1 enable during CSleep Mode + OTFD1LPEN: u1, + /// OTFDEC2 enable during CSleep Mode + OTFD2LPEN: u1, + reserved28: u4, + /// D1DTCM1 Block Clock Enable During CSleep mode + D1DTCM1LPEN: u1, + /// D1 DTCM2 Block Clock Enable During CSleep mode + DTCM2LPEN: u1, + /// D1ITCM Block Clock Enable During CSleep mode + ITCMLPEN: u1, + /// AXISRAM Block Clock Enable During CSleep mode + AXISRAMLPEN: u1, + }), + /// RCC AHB1 Sleep Clock Register + AHB1LPENR: mmio.Mmio(packed struct(u32) { + /// DMA1 Clock Enable During CSleep Mode + DMA1LPEN: u1, + /// DMA2 Clock Enable During CSleep Mode + DMA2LPEN: u1, + reserved5: u3, + /// ADC1/2 Peripheral Clocks Enable During CSleep Mode + ADC12LPEN: u1, + reserved14: u8, + /// ART Clock Enable During CSleep Mode + ARTLPEN: u1, + /// Ethernet MAC bus interface Clock Enable During CSleep Mode + ETHLPEN: u1, + /// Ethernet Transmission Clock Enable During CSleep Mode + ETHTXLPEN: u1, + /// Ethernet Reception Clock Enable During CSleep Mode + ETHRXLPEN: u1, + reserved25: u7, + /// USB_OTG_HS peripheral clock enable during CSleep mode + USB_OTG_HSLPEN: u1, + /// USB_PHY1 clock enable during CSleep mode + USB_OTG_HS_ULPILPEN: u1, + /// USB_OTG_FS peripheral clock enable during CSleep mode + USB_OTG_FSLPEN: u1, + /// USB_PHY2 clocks enable during CSleep mode + USB_OTG_FS_ULPILPEN: u1, + padding: u3, + }), + /// RCC AHB2 Sleep Clock Register + AHB2LPENR: mmio.Mmio(packed struct(u32) { + /// DCMI peripheral clock enable during csleep mode + DCMILPEN: u1, + reserved4: u3, + /// CRYP peripheral clock enable during CSleep mode + CRYPLPEN: u1, + /// HASH peripheral clock enable during CSleep mode + HASHLPEN: u1, + /// RNG peripheral clock enable during CSleep mode + RNGLPEN: u1, + reserved9: u2, + /// SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + SDMMC2LPEN: u1, + reserved11: u1, + /// BDMA1 Clock Enable During CSleep Mode + BDMA1LPEN: u1, + reserved16: u4, + /// FMAC enable during CSleep Mode + FMACLPEN: u1, + /// CORDIC enable during CSleep Mode + CORDICLPEN: u1, + reserved29: u11, + /// SRAM1 Clock Enable During CSleep Mode + SRAM1LPEN: u1, + /// SRAM2 Clock Enable During CSleep Mode + SRAM2LPEN: u1, + /// SRAM3 Clock Enable During CSleep Mode + SRAM3LPEN: u1, + }), + /// RCC AHB4 Sleep Clock Register + AHB4LPENR: mmio.Mmio(packed struct(u32) { + /// GPIO peripheral clock enable during CSleep mode + GPIOALPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOBLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOCLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIODLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOELPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOFLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOGLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOHLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOILPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOJLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOKLPEN: u1, + reserved19: u8, + /// CRC peripheral clock enable during CSleep mode + CRCLPEN: u1, + reserved21: u1, + /// BDMA2 Clock Enable During CSleep Mode + BDMA2LPEN: u1, + reserved24: u2, + /// ADC3 Peripheral Clocks Enable During CSleep Mode + ADC3LPEN: u1, + reserved28: u3, + /// Backup RAM Clock Enable During CSleep Mode + BKPSRAMLPEN: u1, + /// SRAM4 Clock Enable During CSleep Mode + SRAM4LPEN: u1, + padding: u2, + }), + /// RCC APB3 Sleep Clock Register + APB3LPENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC peripheral clock enable during CSleep mode + LTDCLPEN: u1, + /// DSI Peripheral Clock Enable During CSleep Mode + DSILPEN: u1, + reserved6: u1, + /// WWDG1 Clock Enable During CSleep Mode + WWDG1LPEN: u1, + padding: u25, + }), + /// RCC APB1 Low Sleep Clock Register + APB1LLPENR: mmio.Mmio(packed struct(u32) { + /// TIM2 peripheral clock enable during CSleep mode + TIM2LPEN: u1, + /// TIM3 peripheral clock enable during CSleep mode + TIM3LPEN: u1, + /// TIM4 peripheral clock enable during CSleep mode + TIM4LPEN: u1, + /// TIM5 peripheral clock enable during CSleep mode + TIM5LPEN: u1, + /// TIM6 peripheral clock enable during CSleep mode + TIM6LPEN: u1, + /// TIM7 peripheral clock enable during CSleep mode + TIM7LPEN: u1, + /// TIM12 peripheral clock enable during CSleep mode + TIM12LPEN: u1, + /// TIM13 peripheral clock enable during CSleep mode + TIM13LPEN: u1, + /// TIM14 peripheral clock enable during CSleep mode + TIM14LPEN: u1, + /// LPTIM1 Peripheral Clocks Enable During CSleep Mode + LPTIM1LPEN: u1, + reserved11: u1, + /// WWDG2 peripheral Clocks Enable During CSleep Mode + WWDG2LPEN: u1, + reserved14: u2, + /// SPI2 Peripheral Clocks Enable During CSleep Mode + SPI2LPEN: u1, + /// SPI3 Peripheral Clocks Enable During CSleep Mode + SPI3LPEN: u1, + /// SPDIFRX Peripheral Clocks Enable During CSleep Mode + SPDIFRXLPEN: u1, + /// USART2 Peripheral Clocks Enable During CSleep Mode + USART2LPEN: u1, + /// USART3 Peripheral Clocks Enable During CSleep Mode + USART3LPEN: u1, + /// UART4 Peripheral Clocks Enable During CSleep Mode + UART4LPEN: u1, + /// UART5 Peripheral Clocks Enable During CSleep Mode + UART5LPEN: u1, + /// I2C1 Peripheral Clocks Enable During CSleep Mode + I2C1LPEN: u1, + /// I2C2 Peripheral Clocks Enable During CSleep Mode + I2C2LPEN: u1, + /// I2C3 Peripheral Clocks Enable During CSleep Mode + I2C3LPEN: u1, + reserved25: u1, + /// I2C5 block enable during CSleep Mode + I2C5LPEN: u1, + reserved27: u1, + /// HDMI-CEC Peripheral Clocks Enable During CSleep Mode + CECLPEN: u1, + reserved29: u1, + /// DAC1 (containing two converters) peripheral clock enable during CSleep mode + DAC1LPEN: u1, + /// UART7 Peripheral Clocks Enable During CSleep Mode + UART7LPEN: u1, + /// UART8 Peripheral Clocks Enable During CSleep Mode + UART8LPEN: u1, + }), + /// RCC APB1 High Sleep Clock Register + APB1HLPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clock Recovery System peripheral clock enable during CSleep mode + CRSLPEN: u1, + /// SWPMI Peripheral Clocks Enable During CSleep Mode + SWPMILPEN: u1, + reserved4: u1, + /// OPAMP peripheral clock enable during CSleep mode + OPAMPLPEN: u1, + /// MDIOS peripheral clock enable during CSleep mode + MDIOSLPEN: u1, + reserved8: u2, + /// FDCAN Peripheral Clocks Enable During CSleep Mode + FDCANLPEN: u1, + reserved24: u15, + /// TIM23 block enable during CSleep Mode + TIM23LPEN: u1, + /// TIM24 block enable during CSleep Mode + TIM24LPEN: u1, + padding: u6, + }), + /// RCC APB2 Sleep Clock Register + APB2LPENR: mmio.Mmio(packed struct(u32) { + /// TIM1 peripheral clock enable during CSleep mode + TIM1LPEN: u1, + /// TIM8 peripheral clock enable during CSleep mode + TIM8LPEN: u1, + reserved4: u2, + /// USART1 Peripheral Clocks Enable During CSleep Mode + USART1LPEN: u1, + /// USART6 Peripheral Clocks Enable During CSleep Mode + USART6LPEN: u1, + reserved12: u6, + /// SPI1 Peripheral Clocks Enable During CSleep Mode + SPI1LPEN: u1, + /// SPI4 Peripheral Clocks Enable During CSleep Mode + SPI4LPEN: u1, + reserved16: u2, + /// TIM15 peripheral clock enable during CSleep mode + TIM15LPEN: u1, + /// TIM16 peripheral clock enable during CSleep mode + TIM16LPEN: u1, + /// TIM17 peripheral clock enable during CSleep mode + TIM17LPEN: u1, + reserved20: u1, + /// SPI5 Peripheral Clocks Enable During CSleep Mode + SPI5LPEN: u1, + reserved22: u1, + /// SAI1 Peripheral Clocks Enable During CSleep Mode + SAI1LPEN: u1, + /// SAI2 Peripheral Clocks Enable During CSleep Mode + SAI2LPEN: u1, + /// SAI3 Peripheral Clocks Enable During CSleep Mode + SAI3LPEN: u1, + reserved28: u3, + /// DFSDM1 Peripheral Clocks Enable During CSleep Mode + DFSDM1LPEN: u1, + /// HRTIM peripheral clock enable during CSleep mode + HRTIMLPEN: u1, + padding: u2, + }), + /// RCC APB4 Sleep Clock Register + APB4LPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG peripheral clock enable during CSleep mode + SYSCFGLPEN: u1, + reserved3: u1, + /// LPUART1 Peripheral Clocks Enable During CSleep Mode + LPUART1LPEN: u1, + reserved5: u1, + /// SPI6 Peripheral Clocks Enable During CSleep Mode + SPI6LPEN: u1, + reserved7: u1, + /// I2C4 Peripheral Clocks Enable During CSleep Mode + I2C4LPEN: u1, + reserved9: u1, + /// LPTIM2 Peripheral Clocks Enable During CSleep Mode + LPTIM2LPEN: u1, + /// LPTIM3 Peripheral Clocks Enable During CSleep Mode + LPTIM3LPEN: u1, + /// LPTIM4 Peripheral Clocks Enable During CSleep Mode + LPTIM4LPEN: u1, + /// LPTIM5 Peripheral Clocks Enable During CSleep Mode + LPTIM5LPEN: u1, + /// DAC2 (containing one converter) peripheral clock enable during CSleep mode + DAC2LPEN: u1, + /// COMP1/2 peripheral clock enable during CSleep mode + COMP12LPEN: u1, + /// VREF peripheral clock enable during CSleep mode + VREFLPEN: u1, + /// RTC APB Clock Enable During CSleep Mode + RTCAPBLPEN: u1, + reserved21: u4, + /// SAI4 Peripheral Clocks Enable During CSleep Mode + SAI4LPEN: u1, + reserved26: u4, + /// Digital temperature sensor block enable during CSleep Mode + DTSLPEN: u1, + padding: u5, + }), + }; + }; + + pub const rcc_h7rm0433 = struct { + pub const ADCSEL = enum(u2) { + /// pll2_p selected as peripheral clock + PLL2_P = 0x0, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// PER selected as peripheral clock + PER = 0x2, + _, + }; + + pub const CECSEL = enum(u2) { + /// LSE selected as peripheral clock + LSE = 0x0, + /// LSI selected as peripheral clock + LSI = 0x1, + /// csi_ker selected as peripheral clock + CSI = 0x2, + _, + }; + + pub const DFSDMSEL = enum(u1) { + /// rcc_pclk2 selected as peripheral clock + PCLK2 = 0x0, + /// System clock selected as peripheral clock + SYS = 0x1, + }; + + pub const FDCANSEL = enum(u2) { + /// HSE selected as peripheral clock + HSE = 0x0, + /// pll1_q selected as peripheral clock + PLL1_Q = 0x1, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x2, + _, + }; + + pub const FMCSEL = enum(u2) { + /// rcc_hclk3 selected as peripheral clock + HCLK3 = 0x0, + /// pll1_q selected as peripheral clock + PLL1_Q = 0x1, + /// pll2_r selected as peripheral clock + PLL2_R = 0x2, + /// PER selected as peripheral clock + PER = 0x3, + }; + + pub const HPRE = enum(u4) { + /// sys_ck not divided + Div1 = 0x0, + /// sys_ck divided by 2 + Div2 = 0x8, + /// sys_ck divided by 4 + Div4 = 0x9, + /// sys_ck divided by 8 + Div8 = 0xa, + /// sys_ck divided by 16 + Div16 = 0xb, + /// sys_ck divided by 64 + Div64 = 0xc, + /// sys_ck divided by 128 + Div128 = 0xd, + /// sys_ck divided by 256 + Div256 = 0xe, + /// sys_ck divided by 512 + Div512 = 0xf, + _, + }; + + pub const HRTIMSEL = enum(u1) { + /// The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) + TIMY_KER = 0x0, + /// The HRTIM prescaler clock source is the CPU clock (c_ck) + C_CK = 0x1, + }; + + pub const HSIDIV = enum(u2) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x1, + /// Division by 4 + Div4 = 0x2, + /// Division by 8 + Div8 = 0x3, + }; + + pub const I2C1235SEL = enum(u2) { + /// rcc_pclk1 selected as peripheral clock + PCLK1 = 0x0, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// hsi_ker selected as peripheral clock + HSI = 0x2, + /// csi_ker selected as peripheral clock + CSI = 0x3, + }; + + pub const I2C4SEL = enum(u2) { + /// rcc_pclk4 selected as peripheral clock + PCLK4 = 0x0, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// hsi_ker selected as peripheral clock + HSI = 0x2, + /// csi_ker selected as peripheral clock + CSI = 0x3, + }; + + pub const LPTIM1SEL = enum(u3) { + /// rcc_pclk1 selected as peripheral clock + PCLK1 = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_r selected as peripheral clock + PLL3_R = 0x2, + /// LSE selected as peripheral clock + LSE = 0x3, + /// LSI selected as peripheral clock + LSI = 0x4, + /// PER selected as peripheral clock + PER = 0x5, + _, + }; + + pub const LPTIM2SEL = enum(u3) { + /// rcc_pclk4 selected as peripheral clock + PCLK4 = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_r selected as peripheral clock + PLL3_R = 0x2, + /// LSE selected as peripheral clock + LSE = 0x3, + /// LSI selected as peripheral clock + LSI = 0x4, + /// PER selected as peripheral clock + PER = 0x5, + _, + }; + + pub const LPUARTSEL = enum(u3) { + /// rcc_pclk_d4 selected as peripheral clock + PCLK4 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium high driving capability + MediumHigh = 0x1, + /// Medium low driving capability + MediumLow = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const MCO1SEL = enum(u3) { + /// HSI selected for micro-controller clock output + HSI = 0x0, + /// LSE selected for micro-controller clock output + LSE = 0x1, + /// HSE selected for micro-controller clock output + HSE = 0x2, + /// pll1_q selected for micro-controller clock output + PLL1_Q = 0x3, + /// HSI48 selected for micro-controller clock output + HSI48 = 0x4, + _, + }; + + pub const MCO2SEL = enum(u3) { + /// System clock selected for micro-controller clock output + SYS = 0x0, + /// pll2_p selected for micro-controller clock output + PLL2_P = 0x1, + /// HSE selected for micro-controller clock output + HSE = 0x2, + /// pll1_p selected for micro-controller clock output + PLL1_P = 0x3, + /// CSI selected for micro-controller clock output + CSI = 0x4, + /// LSI selected for micro-controller clock output + LSI = 0x5, + _, + }; + + pub const MCOPRE = enum(u4) { + /// Divide by 1 + Div1 = 0x1, + /// Divide by 2 + Div2 = 0x2, + /// Divide by 3 + Div3 = 0x3, + /// Divide by 4 + Div4 = 0x4, + /// Divide by 5 + Div5 = 0x5, + /// Divide by 6 + Div6 = 0x6, + /// Divide by 7 + Div7 = 0x7, + /// Divide by 8 + Div8 = 0x8, + /// Divide by 9 + Div9 = 0x9, + /// Divide by 10 + Div10 = 0xa, + /// Divide by 11 + Div11 = 0xb, + /// Divide by 12 + Div12 = 0xc, + /// Divide by 13 + Div13 = 0xd, + /// Divide by 14 + Div14 = 0xe, + /// Divide by 15 + Div15 = 0xf, + _, + }; + + pub const PERSEL = enum(u2) { + /// HSI selected as peripheral clock + HSI = 0x0, + /// CSI selected as peripheral clock + CSI = 0x1, + /// HSE selected as peripheral clock + HSE = 0x2, + _, + }; + + pub const PLLDIV = enum(u7) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + Div17 = 0x10, + Div18 = 0x11, + Div19 = 0x12, + Div20 = 0x13, + Div21 = 0x14, + Div22 = 0x15, + Div23 = 0x16, + Div24 = 0x17, + Div25 = 0x18, + Div26 = 0x19, + Div27 = 0x1a, + Div28 = 0x1b, + Div29 = 0x1c, + Div30 = 0x1d, + Div31 = 0x1e, + Div32 = 0x1f, + Div33 = 0x20, + Div34 = 0x21, + Div35 = 0x22, + Div36 = 0x23, + Div37 = 0x24, + Div38 = 0x25, + Div39 = 0x26, + Div40 = 0x27, + Div41 = 0x28, + Div42 = 0x29, + Div43 = 0x2a, + Div44 = 0x2b, + Div45 = 0x2c, + Div46 = 0x2d, + Div47 = 0x2e, + Div48 = 0x2f, + Div49 = 0x30, + Div50 = 0x31, + Div51 = 0x32, + Div52 = 0x33, + Div53 = 0x34, + Div54 = 0x35, + Div55 = 0x36, + Div56 = 0x37, + Div57 = 0x38, + Div58 = 0x39, + Div59 = 0x3a, + Div60 = 0x3b, + Div61 = 0x3c, + Div62 = 0x3d, + Div63 = 0x3e, + Div64 = 0x3f, + Div65 = 0x40, + Div66 = 0x41, + Div67 = 0x42, + Div68 = 0x43, + Div69 = 0x44, + Div70 = 0x45, + Div71 = 0x46, + Div72 = 0x47, + Div73 = 0x48, + Div74 = 0x49, + Div75 = 0x4a, + Div76 = 0x4b, + Div77 = 0x4c, + Div78 = 0x4d, + Div79 = 0x4e, + Div80 = 0x4f, + Div81 = 0x50, + Div82 = 0x51, + Div83 = 0x52, + Div84 = 0x53, + Div85 = 0x54, + Div86 = 0x55, + Div87 = 0x56, + Div88 = 0x57, + Div89 = 0x58, + Div90 = 0x59, + Div91 = 0x5a, + Div92 = 0x5b, + Div93 = 0x5c, + Div94 = 0x5d, + Div95 = 0x5e, + Div96 = 0x5f, + Div97 = 0x60, + Div98 = 0x61, + Div99 = 0x62, + Div100 = 0x63, + Div101 = 0x64, + Div102 = 0x65, + Div103 = 0x66, + Div104 = 0x67, + Div105 = 0x68, + Div106 = 0x69, + Div107 = 0x6a, + Div108 = 0x6b, + Div109 = 0x6c, + Div110 = 0x6d, + Div111 = 0x6e, + Div112 = 0x6f, + Div113 = 0x70, + Div114 = 0x71, + Div115 = 0x72, + Div116 = 0x73, + Div117 = 0x74, + Div118 = 0x75, + Div119 = 0x76, + Div120 = 0x77, + Div121 = 0x78, + Div122 = 0x79, + Div123 = 0x7a, + Div124 = 0x7b, + Div125 = 0x7c, + Div126 = 0x7d, + Div127 = 0x7e, + Div128 = 0x7f, + }; + + pub const PLLM = enum(u6) { + Div1 = 0x1, + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + Div16 = 0x10, + Div17 = 0x11, + Div18 = 0x12, + Div19 = 0x13, + Div20 = 0x14, + Div21 = 0x15, + Div22 = 0x16, + Div23 = 0x17, + Div24 = 0x18, + Div25 = 0x19, + Div26 = 0x1a, + Div27 = 0x1b, + Div28 = 0x1c, + Div29 = 0x1d, + Div30 = 0x1e, + Div31 = 0x1f, + Div32 = 0x20, + Div33 = 0x21, + Div34 = 0x22, + Div35 = 0x23, + Div36 = 0x24, + Div37 = 0x25, + Div38 = 0x26, + Div39 = 0x27, + Div40 = 0x28, + Div41 = 0x29, + Div42 = 0x2a, + Div43 = 0x2b, + Div44 = 0x2c, + Div45 = 0x2d, + Div46 = 0x2e, + Div47 = 0x2f, + Div48 = 0x30, + Div49 = 0x31, + Div50 = 0x32, + Div51 = 0x33, + Div52 = 0x34, + Div53 = 0x35, + Div54 = 0x36, + Div55 = 0x37, + Div56 = 0x38, + Div57 = 0x39, + Div58 = 0x3a, + Div59 = 0x3b, + Div60 = 0x3c, + Div61 = 0x3d, + Div62 = 0x3e, + _, + }; + + pub const PLLN = enum(u9) { + Mul4 = 0x3, + Mul5 = 0x4, + Mul6 = 0x5, + Mul7 = 0x6, + Mul8 = 0x7, + Mul9 = 0x8, + Mul10 = 0x9, + Mul11 = 0xa, + Mul12 = 0xb, + Mul13 = 0xc, + Mul14 = 0xd, + Mul15 = 0xe, + Mul16 = 0xf, + Mul17 = 0x10, + Mul18 = 0x11, + Mul19 = 0x12, + Mul20 = 0x13, + Mul21 = 0x14, + Mul22 = 0x15, + Mul23 = 0x16, + Mul24 = 0x17, + Mul25 = 0x18, + Mul26 = 0x19, + Mul27 = 0x1a, + Mul28 = 0x1b, + Mul29 = 0x1c, + Mul30 = 0x1d, + Mul31 = 0x1e, + Mul32 = 0x1f, + Mul33 = 0x20, + Mul34 = 0x21, + Mul35 = 0x22, + Mul36 = 0x23, + Mul37 = 0x24, + Mul38 = 0x25, + Mul39 = 0x26, + Mul40 = 0x27, + Mul41 = 0x28, + Mul42 = 0x29, + Mul43 = 0x2a, + Mul44 = 0x2b, + Mul45 = 0x2c, + Mul46 = 0x2d, + Mul47 = 0x2e, + Mul48 = 0x2f, + Mul49 = 0x30, + Mul50 = 0x31, + Mul51 = 0x32, + Mul52 = 0x33, + Mul53 = 0x34, + Mul54 = 0x35, + Mul55 = 0x36, + Mul56 = 0x37, + Mul57 = 0x38, + Mul58 = 0x39, + Mul59 = 0x3a, + Mul60 = 0x3b, + Mul61 = 0x3c, + Mul62 = 0x3d, + Mul63 = 0x3e, + Mul64 = 0x3f, + Mul65 = 0x40, + Mul66 = 0x41, + Mul67 = 0x42, + Mul68 = 0x43, + Mul69 = 0x44, + Mul70 = 0x45, + Mul71 = 0x46, + Mul72 = 0x47, + Mul73 = 0x48, + Mul74 = 0x49, + Mul75 = 0x4a, + Mul76 = 0x4b, + Mul77 = 0x4c, + Mul78 = 0x4d, + Mul79 = 0x4e, + Mul80 = 0x4f, + Mul81 = 0x50, + Mul82 = 0x51, + Mul83 = 0x52, + Mul84 = 0x53, + Mul85 = 0x54, + Mul86 = 0x55, + Mul87 = 0x56, + Mul88 = 0x57, + Mul89 = 0x58, + Mul90 = 0x59, + Mul91 = 0x5a, + Mul92 = 0x5b, + Mul93 = 0x5c, + Mul94 = 0x5d, + Mul95 = 0x5e, + Mul96 = 0x5f, + Mul97 = 0x60, + Mul98 = 0x61, + Mul99 = 0x62, + Mul100 = 0x63, + Mul101 = 0x64, + Mul102 = 0x65, + Mul103 = 0x66, + Mul104 = 0x67, + Mul105 = 0x68, + Mul106 = 0x69, + Mul107 = 0x6a, + Mul108 = 0x6b, + Mul109 = 0x6c, + Mul110 = 0x6d, + Mul111 = 0x6e, + Mul112 = 0x6f, + Mul113 = 0x70, + Mul114 = 0x71, + Mul115 = 0x72, + Mul116 = 0x73, + Mul117 = 0x74, + Mul118 = 0x75, + Mul119 = 0x76, + Mul120 = 0x77, + Mul121 = 0x78, + Mul122 = 0x79, + Mul123 = 0x7a, + Mul124 = 0x7b, + Mul125 = 0x7c, + Mul126 = 0x7d, + Mul127 = 0x7e, + Mul128 = 0x7f, + Mul129 = 0x80, + Mul130 = 0x81, + Mul131 = 0x82, + Mul132 = 0x83, + Mul133 = 0x84, + Mul134 = 0x85, + Mul135 = 0x86, + Mul136 = 0x87, + Mul137 = 0x88, + Mul138 = 0x89, + Mul139 = 0x8a, + Mul140 = 0x8b, + Mul141 = 0x8c, + Mul142 = 0x8d, + Mul143 = 0x8e, + Mul144 = 0x8f, + Mul145 = 0x90, + Mul146 = 0x91, + Mul147 = 0x92, + Mul148 = 0x93, + Mul149 = 0x94, + Mul150 = 0x95, + Mul151 = 0x96, + Mul152 = 0x97, + Mul153 = 0x98, + Mul154 = 0x99, + Mul155 = 0x9a, + Mul156 = 0x9b, + Mul157 = 0x9c, + Mul158 = 0x9d, + Mul159 = 0x9e, + Mul160 = 0x9f, + Mul161 = 0xa0, + Mul162 = 0xa1, + Mul163 = 0xa2, + Mul164 = 0xa3, + Mul165 = 0xa4, + Mul166 = 0xa5, + Mul167 = 0xa6, + Mul168 = 0xa7, + Mul169 = 0xa8, + Mul170 = 0xa9, + Mul171 = 0xaa, + Mul172 = 0xab, + Mul173 = 0xac, + Mul174 = 0xad, + Mul175 = 0xae, + Mul176 = 0xaf, + Mul177 = 0xb0, + Mul178 = 0xb1, + Mul179 = 0xb2, + Mul180 = 0xb3, + Mul181 = 0xb4, + Mul182 = 0xb5, + Mul183 = 0xb6, + Mul184 = 0xb7, + Mul185 = 0xb8, + Mul186 = 0xb9, + Mul187 = 0xba, + Mul188 = 0xbb, + Mul189 = 0xbc, + Mul190 = 0xbd, + Mul191 = 0xbe, + Mul192 = 0xbf, + Mul193 = 0xc0, + Mul194 = 0xc1, + Mul195 = 0xc2, + Mul196 = 0xc3, + Mul197 = 0xc4, + Mul198 = 0xc5, + Mul199 = 0xc6, + Mul200 = 0xc7, + Mul201 = 0xc8, + Mul202 = 0xc9, + Mul203 = 0xca, + Mul204 = 0xcb, + Mul205 = 0xcc, + Mul206 = 0xcd, + Mul207 = 0xce, + Mul208 = 0xcf, + Mul209 = 0xd0, + Mul210 = 0xd1, + Mul211 = 0xd2, + Mul212 = 0xd3, + Mul213 = 0xd4, + Mul214 = 0xd5, + Mul215 = 0xd6, + Mul216 = 0xd7, + Mul217 = 0xd8, + Mul218 = 0xd9, + Mul219 = 0xda, + Mul220 = 0xdb, + Mul221 = 0xdc, + Mul222 = 0xdd, + Mul223 = 0xde, + Mul224 = 0xdf, + Mul225 = 0xe0, + Mul226 = 0xe1, + Mul227 = 0xe2, + Mul228 = 0xe3, + Mul229 = 0xe4, + Mul230 = 0xe5, + Mul231 = 0xe6, + Mul232 = 0xe7, + Mul233 = 0xe8, + Mul234 = 0xe9, + Mul235 = 0xea, + Mul236 = 0xeb, + Mul237 = 0xec, + Mul238 = 0xed, + Mul239 = 0xee, + Mul240 = 0xef, + Mul241 = 0xf0, + Mul242 = 0xf1, + Mul243 = 0xf2, + Mul244 = 0xf3, + Mul245 = 0xf4, + Mul246 = 0xf5, + Mul247 = 0xf6, + Mul248 = 0xf7, + Mul249 = 0xf8, + Mul250 = 0xf9, + Mul251 = 0xfa, + Mul252 = 0xfb, + Mul253 = 0xfc, + Mul254 = 0xfd, + Mul255 = 0xfe, + Mul256 = 0xff, + Mul257 = 0x100, + Mul258 = 0x101, + Mul259 = 0x102, + Mul260 = 0x103, + Mul261 = 0x104, + Mul262 = 0x105, + Mul263 = 0x106, + Mul264 = 0x107, + Mul265 = 0x108, + Mul266 = 0x109, + Mul267 = 0x10a, + Mul268 = 0x10b, + Mul269 = 0x10c, + Mul270 = 0x10d, + Mul271 = 0x10e, + Mul272 = 0x10f, + Mul273 = 0x110, + Mul274 = 0x111, + Mul275 = 0x112, + Mul276 = 0x113, + Mul277 = 0x114, + Mul278 = 0x115, + Mul279 = 0x116, + Mul280 = 0x117, + Mul281 = 0x118, + Mul282 = 0x119, + Mul283 = 0x11a, + Mul284 = 0x11b, + Mul285 = 0x11c, + Mul286 = 0x11d, + Mul287 = 0x11e, + Mul288 = 0x11f, + Mul289 = 0x120, + Mul290 = 0x121, + Mul291 = 0x122, + Mul292 = 0x123, + Mul293 = 0x124, + Mul294 = 0x125, + Mul295 = 0x126, + Mul296 = 0x127, + Mul297 = 0x128, + Mul298 = 0x129, + Mul299 = 0x12a, + Mul300 = 0x12b, + Mul301 = 0x12c, + Mul302 = 0x12d, + Mul303 = 0x12e, + Mul304 = 0x12f, + Mul305 = 0x130, + Mul306 = 0x131, + Mul307 = 0x132, + Mul308 = 0x133, + Mul309 = 0x134, + Mul310 = 0x135, + Mul311 = 0x136, + Mul312 = 0x137, + Mul313 = 0x138, + Mul314 = 0x139, + Mul315 = 0x13a, + Mul316 = 0x13b, + Mul317 = 0x13c, + Mul318 = 0x13d, + Mul319 = 0x13e, + Mul320 = 0x13f, + Mul321 = 0x140, + Mul322 = 0x141, + Mul323 = 0x142, + Mul324 = 0x143, + Mul325 = 0x144, + Mul326 = 0x145, + Mul327 = 0x146, + Mul328 = 0x147, + Mul329 = 0x148, + Mul330 = 0x149, + Mul331 = 0x14a, + Mul332 = 0x14b, + Mul333 = 0x14c, + Mul334 = 0x14d, + Mul335 = 0x14e, + Mul336 = 0x14f, + Mul337 = 0x150, + Mul338 = 0x151, + Mul339 = 0x152, + Mul340 = 0x153, + Mul341 = 0x154, + Mul342 = 0x155, + Mul343 = 0x156, + Mul344 = 0x157, + Mul345 = 0x158, + Mul346 = 0x159, + Mul347 = 0x15a, + Mul348 = 0x15b, + Mul349 = 0x15c, + Mul350 = 0x15d, + Mul351 = 0x15e, + Mul352 = 0x15f, + Mul353 = 0x160, + Mul354 = 0x161, + Mul355 = 0x162, + Mul356 = 0x163, + Mul357 = 0x164, + Mul358 = 0x165, + Mul359 = 0x166, + Mul360 = 0x167, + Mul361 = 0x168, + Mul362 = 0x169, + Mul363 = 0x16a, + Mul364 = 0x16b, + Mul365 = 0x16c, + Mul366 = 0x16d, + Mul367 = 0x16e, + Mul368 = 0x16f, + Mul369 = 0x170, + Mul370 = 0x171, + Mul371 = 0x172, + Mul372 = 0x173, + Mul373 = 0x174, + Mul374 = 0x175, + Mul375 = 0x176, + Mul376 = 0x177, + Mul377 = 0x178, + Mul378 = 0x179, + Mul379 = 0x17a, + Mul380 = 0x17b, + Mul381 = 0x17c, + Mul382 = 0x17d, + Mul383 = 0x17e, + Mul384 = 0x17f, + Mul385 = 0x180, + Mul386 = 0x181, + Mul387 = 0x182, + Mul388 = 0x183, + Mul389 = 0x184, + Mul390 = 0x185, + Mul391 = 0x186, + Mul392 = 0x187, + Mul393 = 0x188, + Mul394 = 0x189, + Mul395 = 0x18a, + Mul396 = 0x18b, + Mul397 = 0x18c, + Mul398 = 0x18d, + Mul399 = 0x18e, + Mul400 = 0x18f, + Mul401 = 0x190, + Mul402 = 0x191, + Mul403 = 0x192, + Mul404 = 0x193, + Mul405 = 0x194, + Mul406 = 0x195, + Mul407 = 0x196, + Mul408 = 0x197, + Mul409 = 0x198, + Mul410 = 0x199, + Mul411 = 0x19a, + Mul412 = 0x19b, + Mul413 = 0x19c, + Mul414 = 0x19d, + Mul415 = 0x19e, + Mul416 = 0x19f, + Mul417 = 0x1a0, + Mul418 = 0x1a1, + Mul419 = 0x1a2, + Mul420 = 0x1a3, + Mul421 = 0x1a4, + Mul422 = 0x1a5, + Mul423 = 0x1a6, + Mul424 = 0x1a7, + Mul425 = 0x1a8, + Mul426 = 0x1a9, + Mul427 = 0x1aa, + Mul428 = 0x1ab, + Mul429 = 0x1ac, + Mul430 = 0x1ad, + Mul431 = 0x1ae, + Mul432 = 0x1af, + Mul433 = 0x1b0, + Mul434 = 0x1b1, + Mul435 = 0x1b2, + Mul436 = 0x1b3, + Mul437 = 0x1b4, + Mul438 = 0x1b5, + Mul439 = 0x1b6, + Mul440 = 0x1b7, + Mul441 = 0x1b8, + Mul442 = 0x1b9, + Mul443 = 0x1ba, + Mul444 = 0x1bb, + Mul445 = 0x1bc, + Mul446 = 0x1bd, + Mul447 = 0x1be, + Mul448 = 0x1bf, + Mul449 = 0x1c0, + Mul450 = 0x1c1, + Mul451 = 0x1c2, + Mul452 = 0x1c3, + Mul453 = 0x1c4, + Mul454 = 0x1c5, + Mul455 = 0x1c6, + Mul456 = 0x1c7, + Mul457 = 0x1c8, + Mul458 = 0x1c9, + Mul459 = 0x1ca, + Mul460 = 0x1cb, + Mul461 = 0x1cc, + Mul462 = 0x1cd, + Mul463 = 0x1ce, + Mul464 = 0x1cf, + Mul465 = 0x1d0, + Mul466 = 0x1d1, + Mul467 = 0x1d2, + Mul468 = 0x1d3, + Mul469 = 0x1d4, + Mul470 = 0x1d5, + Mul471 = 0x1d6, + Mul472 = 0x1d7, + Mul473 = 0x1d8, + Mul474 = 0x1d9, + Mul475 = 0x1da, + Mul476 = 0x1db, + Mul477 = 0x1dc, + Mul478 = 0x1dd, + Mul479 = 0x1de, + Mul480 = 0x1df, + Mul481 = 0x1e0, + Mul482 = 0x1e1, + Mul483 = 0x1e2, + Mul484 = 0x1e3, + Mul485 = 0x1e4, + Mul486 = 0x1e5, + Mul487 = 0x1e6, + Mul488 = 0x1e7, + Mul489 = 0x1e8, + Mul490 = 0x1e9, + Mul491 = 0x1ea, + Mul492 = 0x1eb, + Mul493 = 0x1ec, + Mul494 = 0x1ed, + Mul495 = 0x1ee, + Mul496 = 0x1ef, + Mul497 = 0x1f0, + Mul498 = 0x1f1, + Mul499 = 0x1f2, + Mul500 = 0x1f3, + Mul501 = 0x1f4, + Mul502 = 0x1f5, + Mul503 = 0x1f6, + Mul504 = 0x1f7, + Mul505 = 0x1f8, + Mul506 = 0x1f9, + Mul507 = 0x1fa, + Mul508 = 0x1fb, + Mul509 = 0x1fc, + Mul510 = 0x1fd, + Mul511 = 0x1fe, + Mul512 = 0x1ff, + _, + }; + + pub const PLLRGE = enum(u2) { + /// Frequency is between 1 and 2 MHz + Range1 = 0x0, + /// Frequency is between 2 and 4 MHz + Range2 = 0x1, + /// Frequency is between 4 and 8 MHz + Range4 = 0x2, + /// Frequency is between 8 and 16 MHz + Range8 = 0x3, + }; + + pub const PLLSRC = enum(u2) { + /// HSI selected as PLL clock + HSI = 0x0, + /// CSI selected as PLL clock + CSI = 0x1, + /// HSE selected as PLL clock + HSE = 0x2, + /// No clock sent to DIVMx dividers and PLLs + DISABLE = 0x3, + }; + + pub const PLLVCOSEL = enum(u1) { + /// VCO frequency range 192 to 836 MHz + WideVCO = 0x0, + /// VCO frequency range 150 to 420 MHz + MediumVCO = 0x1, + }; + + pub const PPRE = enum(u3) { + /// rcc_hclk not divided + Div1 = 0x0, + /// rcc_hclk divided by 2 + Div2 = 0x4, + /// rcc_hclk divided by 4 + Div4 = 0x5, + /// rcc_hclk divided by 8 + Div8 = 0x6, + /// rcc_hclk divided by 16 + Div16 = 0x7, + _, + }; + + pub const RNGSEL = enum(u2) { + /// HSI48 selected as peripheral clock + HSI48 = 0x0, + /// pll1_q selected as peripheral clock + PLL1_Q = 0x1, + /// LSE selected as peripheral clock + LSE = 0x2, + /// LSI selected as peripheral clock + LSI = 0x3, + }; + + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, + }; + + pub const SAIASEL = enum(u3) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_p selected as peripheral clock + PLL3_P = 0x2, + /// i2s_ckin selected as peripheral clock + I2S_CKIN = 0x3, + /// PER selected as peripheral clock + PER = 0x4, + _, + }; + + pub const SAISEL = enum(u3) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_p selected as peripheral clock + PLL3_P = 0x2, + /// I2S_CKIN selected as peripheral clock + I2S_CKIN = 0x3, + /// PER selected as peripheral clock + PER = 0x4, + _, + }; + + pub const SDMMCSEL = enum(u1) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_r selected as peripheral clock + PLL2_R = 0x1, + }; + + pub const SPDIFRXSEL = enum(u2) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_r selected as peripheral clock + PLL2_R = 0x1, + /// pll3_r selected as peripheral clock + PLL3_R = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + }; + + pub const SPI45SEL = enum(u3) { + /// APB2 clock selected as peripheral clock + PCLK2 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// HSE selected as peripheral clock + HSE = 0x5, + _, + }; + + pub const SPI6SEL = enum(u3) { + /// rcc_pclk4 selected as peripheral clock + PCLK4 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// HSE selected as peripheral clock + HSE = 0x5, + _, + }; + + pub const STOPWUCK = enum(u1) { + /// HSI selected as wake up clock from system Stop + HSI = 0x0, + /// CSI selected as wake up clock from system Stop + CSI = 0x1, + }; + + pub const SW = enum(u3) { + /// HSI selected as system clock + HSI = 0x0, + /// CSI selected as system clock + CSI = 0x1, + /// HSE selected as system clock + HSE = 0x2, + /// PLL1 selected as system clock + PLL1_P = 0x3, + _, + }; + + pub const SWPMISEL = enum(u1) { + /// pclk selected as peripheral clock + PCLK1 = 0x0, + /// hsi_ker selected as peripheral clock + HSI = 0x1, + }; + + pub const TIMPRE = enum(u1) { + /// Timer kernel clock equal to 2x pclk by default + DefaultX2 = 0x0, + /// Timer kernel clock equal to 4x pclk by default + DefaultX4 = 0x1, + }; + + pub const USART16910SEL = enum(u3) { + /// rcc_pclk2 selected as peripheral clock + PCLK2 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, + }; + + pub const USART234578SEL = enum(u3) { + /// rcc_pclk1 selected as peripheral clock + PCLK1 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, + }; + + pub const USBSEL = enum(u2) { + /// Disable the kernel clock + DISABLE = 0x0, + /// pll1_q selected as peripheral clock + PLL1_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// HSI48 selected as peripheral clock + HSI48 = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal high-speed clock enable + HSION: u1, + /// High Speed Internal clock enable in Stop mode + HSIKERON: u1, + /// HSI clock ready flag + HSIRDY: u1, + /// HSI clock divider + HSIDIV: packed union { + raw: u2, + value: HSIDIV, + }, + /// HSI divider flag + HSIDIVF: u1, + reserved7: u1, + /// CSI clock enable + CSION: u1, + /// CSI clock ready flag + CSIRDY: u1, + /// CSI clock enable in Stop mode + CSIKERON: u1, + reserved12: u2, + /// RC48 clock enable + HSI48ON: u1, + /// RC48 clock ready flag + HSI48RDY: u1, + /// D1 domain clocks ready flag + D1CKRDY: u1, + /// D2 domain clocks ready flag + D2CKRDY: u1, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + /// HSE Clock Security System enable + HSECSSON: u1, + reserved24: u4, + /// PLL1 enable + PLLON: u1, + /// PLL1 clock ready flag + PLLRDY: u1, + padding: u6, + }), + /// RCC HSI configuration register + HSICFGR: mmio.Mmio(packed struct(u32) { + /// HSI clock calibration + HSICAL: u12, + reserved24: u12, + /// HSI clock trimming + HSITRIM: u7, + padding: u1, + }), + /// RCC Clock Recovery RC Register + CRRCR: mmio.Mmio(packed struct(u32) { + /// Internal RC 48 MHz clock calibration + HSI48CAL: u10, + padding: u22, + }), + /// RCC CSI configuration register + CSICFGR: mmio.Mmio(packed struct(u32) { + /// CSI clock calibration + CSICAL: u9, + reserved24: u15, + /// CSI clock trimming + CSITRIM: u6, + padding: u2, + }), + /// RCC Clock Configuration Register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u3, + value: SW, + }, + /// System clock switch status + SWS: packed union { + raw: u3, + value: SW, + }, + /// System clock selection after a wake up from system Stop + STOPWUCK: packed union { + raw: u1, + value: STOPWUCK, + }, + /// Kernel clock selection after a wake up from system Stop + STOPKERWUCK: packed union { + raw: u1, + value: STOPWUCK, + }, + /// HSE division factor for RTC clock + RTCPRE: u6, + /// High Resolution Timer clock prescaler selection + HRTIMSEL: packed union { + raw: u1, + value: HRTIMSEL, + }, + /// Timers clocks prescaler selection + TIMPRE: packed union { + raw: u1, + value: TIMPRE, + }, + reserved18: u2, + /// MCO1 prescaler + MCO1PRE: packed union { + raw: u4, + value: MCOPRE, + }, + /// Micro-controller clock output 1 + MCO1SEL: packed union { + raw: u3, + value: MCO1SEL, + }, + /// MCO2 prescaler + MCO2PRE: packed union { + raw: u4, + value: MCOPRE, + }, + /// Micro-controller clock output 2 + MCO2SEL: packed union { + raw: u3, + value: MCO2SEL, + }, + }), + reserved24: [4]u8, + /// RCC Domain 1 Clock Configuration Register + D1CFGR: mmio.Mmio(packed struct(u32) { + /// D1 domain AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// D1 domain APB3 prescaler + D1PPRE: packed union { + raw: u3, + value: PPRE, + }, + reserved8: u1, + /// D1 domain Core prescaler + D1CPRE: packed union { + raw: u4, + value: HPRE, + }, + padding: u20, + }), + /// RCC Domain 2 Clock Configuration Register + D2CFGR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// D2 domain APB1 prescaler + D2PPRE1: packed union { + raw: u3, + value: PPRE, + }, + reserved8: u1, + /// D2 domain APB2 prescaler + D2PPRE2: packed union { + raw: u3, + value: PPRE, + }, + padding: u21, + }), + /// RCC Domain 3 Clock Configuration Register + D3CFGR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// D3 domain APB4 prescaler + D3PPRE: packed union { + raw: u3, + value: PPRE, + }, + padding: u25, + }), + reserved40: [4]u8, + /// RCC PLLs Clock Source Selection Register + PLLCKSELR: mmio.Mmio(packed struct(u32) { + /// DIVMx and PLLs clock source selection + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + reserved4: u2, + /// Prescaler for PLLx + DIVM: packed union { + raw: u6, + value: PLLM, + }, + padding: u22, + }), + /// RCC PLLs Configuration Register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// PLL1 fractional latch enable + PLLFRACEN: u1, + /// PLL1 VCO selection + PLLVCOSEL: packed union { + raw: u1, + value: PLLVCOSEL, + }, + /// PLL1 input frequency range + PLLRGE: packed union { + raw: u2, + value: PLLRGE, + }, + reserved16: u12, + /// PLL1 DIVP divider output enable + DIVPEN: u1, + /// PLL1 DIVQ divider output enable + DIVQEN: u1, + /// PLL1 DIVR divider output enable + DIVREN: u1, + padding: u13, + }), + /// RCC PLL1 Dividers Configuration Register + PLLDIVR: mmio.Mmio(packed struct(u32) { + /// Multiplication factor for PLL1 VCO + PLLN: packed union { + raw: u9, + value: PLLN, + }, + /// PLL DIVP division factor + PLLP: packed union { + raw: u7, + value: PLLDIV, + }, + /// PLL DIVQ division factor + PLLQ: packed union { + raw: u7, + value: PLLDIV, + }, + reserved24: u1, + /// PLL DIVR division factor + PLLR: packed union { + raw: u7, + value: PLLDIV, + }, + padding: u1, + }), + /// RCC PLL1 Fractional Divider Register + PLLFRACR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Fractional part of the multiplication factor for PLL VCO + FRACN: u13, + padding: u16, + }), + reserved76: [20]u8, + /// RCC Domain 1 Kernel Clock Configuration Register + D1CCIPR: mmio.Mmio(packed struct(u32) { + /// FMC kernel clock source selection + FMCSEL: packed union { + raw: u2, + value: FMCSEL, + }, + reserved4: u2, + /// QUADSPI kernel clock source selection + QUADSPISEL: packed union { + raw: u2, + value: FMCSEL, + }, + reserved16: u10, + /// SDMMC kernel clock source selection + SDMMCSEL: packed union { + raw: u1, + value: SDMMCSEL, + }, + reserved28: u11, + /// per_ck clock source selection + PERSEL: packed union { + raw: u2, + value: PERSEL, + }, + padding: u2, + }), + /// RCC Domain 2 Kernel Clock Configuration Register + D2CCIP1R: mmio.Mmio(packed struct(u32) { + /// SAI1 and DFSDM1 kernel Aclk clock source selection + SAI1SEL: packed union { + raw: u3, + value: SAISEL, + }, + reserved6: u3, + /// SAI2 and SAI3 kernel clock source selection + SAI23SEL: packed union { + raw: u3, + value: SAISEL, + }, + reserved12: u3, + /// SPI/I2S1,2 and 3 kernel clock source selection + SPI123SEL: packed union { + raw: u3, + value: SAISEL, + }, + reserved16: u1, + /// SPI4 and 5 kernel clock source selection + SPI45SEL: packed union { + raw: u3, + value: SPI45SEL, + }, + reserved20: u1, + /// SPDIFRX kernel clock source selection + SPDIFRXSEL: packed union { + raw: u2, + value: SPDIFRXSEL, + }, + reserved24: u2, + /// DFSDM1 kernel Clk clock source selection + DFSDM1SEL: packed union { + raw: u1, + value: DFSDMSEL, + }, + reserved28: u3, + /// FDCAN kernel clock source selection + FDCANSEL: packed union { + raw: u2, + value: FDCANSEL, + }, + reserved31: u1, + /// SWPMI kernel clock source selection + SWPMISEL: packed union { + raw: u1, + value: SWPMISEL, + }, + }), + /// RCC Domain 2 Kernel Clock Configuration Register + D2CCIP2R: mmio.Mmio(packed struct(u32) { + /// USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection + USART234578SEL: packed union { + raw: u3, + value: USART234578SEL, + }, + /// USART1, 6, 9 and 10 kernel clock source selection + USART16910SEL: packed union { + raw: u3, + value: USART16910SEL, + }, + reserved8: u2, + /// RNG kernel clock source selection + RNGSEL: packed union { + raw: u2, + value: RNGSEL, + }, + reserved12: u2, + /// I2C1,2,3 kernel clock source selection + I2C1235SEL: packed union { + raw: u2, + value: I2C1235SEL, + }, + reserved20: u6, + /// USBOTG 1 and 2 kernel clock source selection + USBSEL: packed union { + raw: u2, + value: USBSEL, + }, + /// HDMI-CEC kernel clock source selection + CECSEL: packed union { + raw: u2, + value: CECSEL, + }, + reserved28: u4, + /// LPTIM1 kernel clock source selection + LPTIM1SEL: packed union { + raw: u3, + value: LPTIM1SEL, + }, + padding: u1, + }), + /// RCC Domain 3 Kernel Clock Configuration Register + D3CCIPR: mmio.Mmio(packed struct(u32) { + /// LPUART1 kernel clock source selection + LPUART1SEL: packed union { + raw: u3, + value: LPUARTSEL, + }, + reserved8: u5, + /// I2C4 kernel clock source selection + I2C4SEL: packed union { + raw: u2, + value: I2C4SEL, + }, + /// LPTIM2 kernel clock source selection + LPTIM2SEL: packed union { + raw: u3, + value: LPTIM2SEL, + }, + /// LPTIM3,4,5 kernel clock source selection + LPTIM345SEL: packed union { + raw: u3, + value: LPTIM2SEL, + }, + /// SAR ADC kernel clock source selection + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, + reserved21: u3, + /// Sub-Block A of SAI4 kernel clock source selection + SAI4ASEL: packed union { + raw: u3, + value: SAIASEL, + }, + /// Sub-Block B of SAI4 kernel clock source selection + SAI4BSEL: packed union { + raw: u3, + value: SAIASEL, + }, + /// DFSDM2 kernel clock source selection + DFSDM2SEL: u1, + /// SPI6 kernel clock source selection + SPI6SEL: packed union { + raw: u3, + value: SPI6SEL, + }, + padding: u1, + }), + reserved96: [4]u8, + /// RCC Clock Source Interrupt Enable Register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready Interrupt Enable + LSIRDYIE: u1, + /// LSE ready Interrupt Enable + LSERDYIE: u1, + /// HSI ready Interrupt Enable + HSIRDYIE: u1, + /// HSE ready Interrupt Enable + HSERDYIE: u1, + /// CSI ready Interrupt Enable + CSIRDYIE: u1, + /// RC48 ready Interrupt Enable + HSI48RDYIE: u1, + /// PLL1 ready Interrupt Enable + PLLRDYIE: u1, + reserved9: u2, + /// LSE clock security system Interrupt Enable + LSECSSIE: u1, + padding: u22, + }), + /// RCC Clock Source Interrupt Flag Register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready Interrupt Flag + LSIRDYF: u1, + /// LSE ready Interrupt Flag + LSERDYF: u1, + /// HSI ready Interrupt Flag + HSIRDYF: u1, + /// HSE ready Interrupt Flag + HSERDYF: u1, + /// CSI ready Interrupt Flag + CSIRDY: u1, + /// RC48 ready Interrupt Flag + HSI48RDYF: u1, + /// PLL1 ready Interrupt Flag + PLLRDYF: u1, + reserved9: u2, + /// LSE clock security system Interrupt Flag + LSECSSF: u1, + /// HSE clock security system Interrupt Flag + HSECSSF: u1, + padding: u21, + }), + /// RCC Clock Source Interrupt Clear Register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready Interrupt Clear + LSIRDYC: u1, + /// LSE ready Interrupt Clear + LSERDYC: u1, + /// HSI ready Interrupt Clear + HSIRDYC: u1, + /// HSE ready Interrupt Clear + HSERDYC: u1, + /// CSI ready Interrupt Clear + HSE_ready_Interrupt_Clear: u1, + /// RC48 ready Interrupt Clear + HSI48RDYC: u1, + /// PLL1 ready Interrupt Clear + PLLRDYC: u1, + reserved9: u2, + /// LSE clock security system Interrupt Clear + LSECSSC: u1, + /// HSE clock security system Interrupt Clear + HSECSSC: u1, + padding: u21, + }), + reserved112: [4]u8, + /// RCC Backup Domain Control Register + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enabled + LSEON: u1, + /// LSE oscillator ready + LSERDY: u1, + /// LSE oscillator bypass + LSEBYP: u1, + /// LSE oscillator driving capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// LSE clock security system enable + LSECSSON: u1, + /// LSE clock security system failure detection + LSECSSD: u1, + reserved8: u1, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// VSwitch domain software reset + BDRST: u1, + padding: u15, + }), + /// RCC Clock Control and Status Register + CSR: mmio.Mmio(packed struct(u32) { + /// LSI oscillator enable + LSION: u1, + /// LSI oscillator ready + LSIRDY: u1, + padding: u30, + }), + reserved124: [4]u8, + /// RCC AHB3 Reset Register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// MDMA block reset + MDMARST: u1, + reserved4: u3, + /// DMA2D block reset + DMA2DRST: u1, + /// JPGDEC block reset + JPGDECRST: u1, + reserved12: u6, + /// FMC block reset + FMCRST: u1, + reserved14: u1, + /// QUADSPI and QUADSPI delay block reset + QUADSPIRST: u1, + reserved16: u1, + /// SDMMC1 and SDMMC1 delay block reset + SDMMC1RST: u1, + reserved19: u2, + /// OCTOSPI2 and OCTOSPI2 delay block reset + OCTOSPI2RST: u1, + reserved21: u1, + /// OCTOSPI IO manager reset + IOMNGRRST: u1, + /// OTFDEC1 reset + OTFD1RST: u1, + /// OTFDEC2 reset + OTFD2RST: u1, + reserved31: u7, + /// CPU reset + CPURST: u1, + }), + /// RCC AHB1 Peripheral Reset Register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// DMA1 block reset + DMA1RST: u1, + /// DMA2 block reset + DMA2RST: u1, + reserved5: u3, + /// ADC1&2 block reset + ADC12RST: u1, + reserved14: u8, + /// ART block reset + ARTRST: u1, + /// ETH block reset + ETHRST: u1, + reserved25: u9, + /// USB_OTG_HS block reset + USB_OTG_HSRST: u1, + reserved27: u1, + /// USB_OTG_FS block reset + USB_OTG_FSRST: u1, + padding: u4, + }), + /// RCC AHB2 Peripheral Reset Register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// DCMI block reset + DCMIRST: u1, + reserved4: u3, + /// CRYPography block reset + CRYPRST: u1, + /// Hash block reset + HASHRST: u1, + /// Random Number Generator block reset + RNGRST: u1, + reserved9: u2, + /// SDMMC2 and SDMMC2 Delay block reset + SDMMC2RST: u1, + reserved16: u6, + /// FMAC reset + FMACRST: u1, + /// CORDIC reset + CORDICRST: u1, + padding: u14, + }), + /// RCC AHB4 Peripheral Reset Register + AHB4RSTR: mmio.Mmio(packed struct(u32) { + /// GPIO block reset + GPIOARST: u1, + /// GPIO block reset + GPIOBRST: u1, + /// GPIO block reset + GPIOCRST: u1, + /// GPIO block reset + GPIODRST: u1, + /// GPIO block reset + GPIOERST: u1, + /// GPIO block reset + GPIOFRST: u1, + /// GPIO block reset + GPIOGRST: u1, + /// GPIO block reset + GPIOHRST: u1, + /// GPIO block reset + GPIOIRST: u1, + /// GPIO block reset + GPIOJRST: u1, + /// GPIO block reset + GPIOKRST: u1, + reserved19: u8, + /// CRC block reset + CRCRST: u1, + reserved21: u1, + /// BDMA block reset + BDMARST: u1, + reserved24: u2, + /// ADC3 block reset + ADC3RST: u1, + /// HSEM block reset + HSEMRST: u1, + padding: u6, + }), + /// RCC APB3 Peripheral Reset Register + APB3RSTR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC block reset + LTDCRST: u1, + /// DSI block reset + DSIRST: u1, + padding: u27, + }), + /// RCC APB1 Peripheral Reset Register + APB1LRSTR: mmio.Mmio(packed struct(u32) { + /// TIM block reset + TIM2RST: u1, + /// TIM block reset + TIM3RST: u1, + /// TIM block reset + TIM4RST: u1, + /// TIM block reset + TIM5RST: u1, + /// TIM block reset + TIM6RST: u1, + /// TIM block reset + TIM7RST: u1, + /// TIM block reset + TIM12RST: u1, + /// TIM block reset + TIM13RST: u1, + /// TIM block reset + TIM14RST: u1, + /// TIM block reset + LPTIM1RST: u1, + reserved14: u4, + /// SPI2 block reset + SPI2RST: u1, + /// SPI3 block reset + SPI3RST: u1, + /// SPDIFRX block reset + SPDIFRXRST: u1, + /// USART2 block reset + USART2RST: u1, + /// USART3 block reset + USART3RST: u1, + /// UART4 block reset + UART4RST: u1, + /// UART5 block reset + UART5RST: u1, + /// I2C1 block reset + I2C1RST: u1, + /// I2C2 block reset + I2C2RST: u1, + /// I2C3 block reset + I2C3RST: u1, + reserved25: u1, + /// I2C5 block reset + I2C5RST: u1, + reserved27: u1, + /// HDMI-CEC block reset + CECRST: u1, + reserved29: u1, + /// DAC1 and 2 Blocks Reset + DAC12RST: u1, + /// UART7 block reset + UART7RST: u1, + /// UART8 block reset + UART8RST: u1, + }), + /// RCC APB1 Peripheral Reset Register + APB1HRSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clock Recovery System reset + CRSRST: u1, + /// SWPMI block reset + SWPMIRST: u1, + reserved4: u1, + /// OPAMP block reset + OPAMPRST: u1, + /// MDIOS block reset + MDIOSRST: u1, + reserved8: u2, + /// FDCAN block reset + FDCANRST: u1, + reserved24: u15, + /// TIM23 block reset + TIM23RST: u1, + /// TIM24 block reset + TIM24RST: u1, + padding: u6, + }), + /// RCC APB2 Peripheral Reset Register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// TIM1 block reset + TIM1RST: u1, + /// TIM8 block reset + TIM8RST: u1, + reserved4: u2, + /// USART1 block reset + USART1RST: u1, + /// USART6 block reset + USART6RST: u1, + /// UART9 block reset + UART9RST: u1, + /// USART10 block reset + USART10RST: u1, + reserved12: u4, + /// SPI1 block reset + SPI1RST: u1, + /// SPI4 block reset + SPI4RST: u1, + reserved16: u2, + /// TIM15 block reset + TIM15RST: u1, + /// TIM16 block reset + TIM16RST: u1, + /// TIM17 block reset + TIM17RST: u1, + reserved20: u1, + /// SPI5 block reset + SPI5RST: u1, + reserved22: u1, + /// SAI1 block reset + SAI1RST: u1, + /// SAI2 block reset + SAI2RST: u1, + /// SAI3 block reset + SAI3RST: u1, + reserved28: u3, + /// DFSDM1 block reset + DFSDM1RST: u1, + /// HRTIM block reset + HRTIMRST: u1, + padding: u2, + }), + /// RCC APB4 Peripheral Reset Register + APB4RSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG block reset + SYSCFGRST: u1, + reserved3: u1, + /// LPUART1 block reset + LPUART1RST: u1, + reserved5: u1, + /// SPI6 block reset + SPI6RST: u1, + reserved7: u1, + /// I2C4 block reset + I2C4RST: u1, + reserved9: u1, + /// LPTIM2 block reset + LPTIM2RST: u1, + /// LPTIM3 block reset + LPTIM3RST: u1, + /// LPTIM4 block reset + LPTIM4RST: u1, + /// LPTIM5 block reset + LPTIM5RST: u1, + /// DAC2 (containing one converter) reset + DAC2RST: u1, + /// COMP12 Blocks Reset + COMP12RST: u1, + /// VREF block reset + VREFRST: u1, + reserved21: u5, + /// SAI4 block reset + SAI4RST: u1, + reserved26: u4, + /// Digital temperature sensor block reset + DTSRST: u1, + padding: u5, + }), + /// Global Control Register + GCR: mmio.Mmio(packed struct(u32) { + /// WWDG1 reset scope control + WW1RSC: u1, + /// WWDG2 reset scope control + WW2RSC: u1, + /// Force allow CPU1 to boot + BOOT_C1: u1, + /// Force allow CPU2 to boot + BOOT_C2: u1, + padding: u28, + }), + reserved168: [4]u8, + /// RCC D3 Autonomous mode Register + D3AMR: mmio.Mmio(packed struct(u32) { + /// BDMA and DMAMUX Autonomous mode enable + BDMAAMEN: u1, + reserved3: u2, + /// LPUART1 Autonomous mode enable + LPUART1AMEN: u1, + reserved5: u1, + /// SPI6 Autonomous mode enable + SPI6AMEN: u1, + reserved7: u1, + /// I2C4 Autonomous mode enable + I2C4AMEN: u1, + reserved9: u1, + /// LPTIM2 Autonomous mode enable + LPTIM2AMEN: u1, + /// LPTIM3 Autonomous mode enable + LPTIM3AMEN: u1, + /// LPTIM4 Autonomous mode enable + LPTIM4AMEN: u1, + /// LPTIM5 Autonomous mode enable + LPTIM5AMEN: u1, + /// DAC2 (containing one converter) Autonomous mode enable + DAC2AMEN: u1, + /// COMP12 Autonomous mode enable + COMP12AMEN: u1, + /// VREF Autonomous mode enable + VREFAMEN: u1, + /// RTC Autonomous mode enable + RTCAMEN: u1, + reserved19: u2, + /// CRC Autonomous mode enable + CRCAMEN: u1, + reserved21: u1, + /// SAI4 Autonomous mode enable + SAI4AMEN: u1, + reserved24: u2, + /// ADC3 Autonomous mode enable + ADC3AMEN: u1, + reserved26: u1, + /// Digital temperature sensor Autonomous mode enable + DTSAMEN: u1, + reserved28: u1, + /// Backup RAM Autonomous mode enable + BKPSRAMAMEN: u1, + /// SRAM4 Autonomous mode enable + SRAM4AMEN: u1, + padding: u2, + }), + reserved208: [36]u8, + /// RCC Reset Status Register + RSR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Remove reset flag + RMVF: u1, + /// CPU reset flag + CPURSTF: u1, + reserved19: u1, + /// D1 domain power switch reset flag + D1RSTF: u1, + /// D2 domain power switch reset flag + D2RSTF: u1, + /// BOR reset flag + BORRSTF: u1, + /// Pin reset flag (NRST) + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// System reset from CPU reset flag + SFTRSTF: u1, + reserved26: u1, + /// Independent Watchdog reset flag + IWDG1RSTF: u1, + reserved28: u1, + /// Window Watchdog reset flag + WWDG1RSTF: u1, + reserved30: u1, + /// Reset due to illegal D1 DStandby or CPU CStop flag + LPWRRSTF: u1, + padding: u1, + }), + /// RCC AHB3 Clock Register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// MDMA Peripheral Clock Enable + MDMAEN: u1, + reserved4: u3, + /// DMA2D Peripheral Clock Enable + DMA2DEN: u1, + /// JPGDEC Peripheral Clock Enable + JPGDECEN: u1, + reserved12: u6, + /// FMC Peripheral Clocks Enable + FMCEN: u1, + reserved14: u1, + /// QUADSPI and QUADSPI Delay Clock Enable + QUADSPIEN: u1, + reserved16: u1, + /// SDMMC1 and SDMMC1 Delay Clock Enable + SDMMC1EN: u1, + reserved19: u2, + /// OCTOSPI2 and OCTOSPI2 delay block enable + OCTOSPI2EN: u1, + reserved21: u1, + /// OCTOSPI IO manager enable + IOMNGREN: u1, + /// OTFDEC1 enable + OTFD1EN: u1, + /// OTFDEC2 enable + OTFD2EN: u1, + reserved28: u4, + /// D1 DTCM1 block enable + DTCM1EN: u1, + /// D1 DTCM2 block enable + DTCM2EN: u1, + /// D1 ITCM block enable + ITCM1EN: u1, + /// AXISRAM block enable + AXISRAMEN: u1, + }), + /// RCC AHB1 Clock Register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// DMA1 Clock Enable + DMA1EN: u1, + /// DMA2 Clock Enable + DMA2EN: u1, + reserved5: u3, + /// ADC1/2 Peripheral Clocks Enable + ADC12EN: u1, + reserved14: u8, + /// ART Clock Enable + ARTEN: u1, + /// Ethernet MAC bus interface Clock Enable + ETHEN: u1, + /// Ethernet Transmission Clock Enable + ETHTXEN: u1, + /// Ethernet Reception Clock Enable + ETHRXEN: u1, + reserved25: u7, + /// USB_OTG_HS Peripheral Clocks Enable + USB_OTG_HSEN: u1, + /// USB_OTG_HS ULPI clock enable + USB_OTG_HS_ULPIEN: u1, + /// USB_OTG_FS Peripheral Clocks Enable + USB_OTG_FSEN: u1, + /// USB_OTG_FS ULPI clock enable + USB_OTG_FS_ULPIEN: u1, + padding: u3, + }), + /// RCC AHB2 Clock Register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// DCMI peripheral clock + DCMIEN: u1, + reserved4: u3, + /// CRYP peripheral clock enable + CRYPEN: u1, + /// HASH peripheral clock enable + HASHEN: u1, + /// RNG peripheral clocks enable + RNGEN: u1, + reserved9: u2, + /// SDMMC2 and SDMMC2 delay clock enable + SDMMC2EN: u1, + reserved16: u6, + /// FMAC enable + FMACEN: u1, + /// CORDIC enable + CORDICEN: u1, + reserved29: u11, + /// SRAM1 block enable + SRAM1EN: u1, + /// SRAM2 block enable + SRAM2EN: u1, + /// SRAM3 block enable + SRAM3EN: u1, + }), + /// RCC AHB4 Clock Register + AHB4ENR: mmio.Mmio(packed struct(u32) { + /// 0GPIO peripheral clock enable + GPIOAEN: u1, + /// 0GPIO peripheral clock enable + GPIOBEN: u1, + /// 0GPIO peripheral clock enable + GPIOCEN: u1, + /// 0GPIO peripheral clock enable + GPIODEN: u1, + /// 0GPIO peripheral clock enable + GPIOEEN: u1, + /// 0GPIO peripheral clock enable + GPIOFEN: u1, + /// 0GPIO peripheral clock enable + GPIOGEN: u1, + /// 0GPIO peripheral clock enable + GPIOHEN: u1, + /// 0GPIO peripheral clock enable + GPIOIEN: u1, + /// 0GPIO peripheral clock enable + GPIOJEN: u1, + /// 0GPIO peripheral clock enable + GPIOKEN: u1, + reserved19: u8, + /// CRC peripheral clock enable + CRCEN: u1, + reserved21: u1, + /// BDMA and DMAMUX2 Clock Enable + BDMAEN: u1, + reserved24: u2, + /// ADC3 Peripheral Clocks Enable + ADC3EN: u1, + /// HSEM peripheral clock enable + HSEMEN: u1, + reserved28: u2, + /// Backup RAM Clock Enable + BKPSRAMEN: u1, + padding: u3, + }), + /// RCC APB3 Clock Register + APB3ENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC peripheral clock enable + LTDCEN: u1, + /// DSI Peripheral clocks enable + DSIEN: u1, + reserved6: u1, + /// WWDG1 Clock Enable + WWDG1EN: u1, + padding: u25, + }), + /// RCC APB1 Clock Register + APB1LENR: mmio.Mmio(packed struct(u32) { + /// TIM peripheral clock enable + TIM2EN: u1, + /// TIM peripheral clock enable + TIM3EN: u1, + /// TIM peripheral clock enable + TIM4EN: u1, + /// TIM peripheral clock enable + TIM5EN: u1, + /// TIM peripheral clock enable + TIM6EN: u1, + /// TIM peripheral clock enable + TIM7EN: u1, + /// TIM peripheral clock enable + TIM12EN: u1, + /// TIM peripheral clock enable + TIM13EN: u1, + /// TIM peripheral clock enable + TIM14EN: u1, + /// LPTIM1 Peripheral Clocks Enable + LPTIM1EN: u1, + reserved11: u1, + /// WWDG2 peripheral clock enable + WWDG2EN: u1, + reserved14: u2, + /// SPI2 Peripheral Clocks Enable + SPI2EN: u1, + /// SPI3 Peripheral Clocks Enable + SPI3EN: u1, + /// SPDIFRX Peripheral Clocks Enable + SPDIFRXEN: u1, + /// USART2 Peripheral Clocks Enable + USART2EN: u1, + /// USART3 Peripheral Clocks Enable + USART3EN: u1, + /// UART4 Peripheral Clocks Enable + UART4EN: u1, + /// UART5 Peripheral Clocks Enable + UART5EN: u1, + /// I2C1 Peripheral Clocks Enable + I2C1EN: u1, + /// I2C2 Peripheral Clocks Enable + I2C2EN: u1, + /// I2C3 Peripheral Clocks Enable + I2C3EN: u1, + reserved25: u1, + /// I2C5 Peripheral Clocks Enable + I2C5EN: u1, + reserved27: u1, + /// HDMI-CEC peripheral clock enable + CECEN: u1, + reserved29: u1, + /// DAC1&2 peripheral clock enable + DAC12EN: u1, + /// UART7 Peripheral Clocks Enable + UART7EN: u1, + /// UART8 Peripheral Clocks Enable + UART8EN: u1, + }), + /// RCC APB1 Clock Register + APB1HENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clock Recovery System peripheral clock enable + CRSEN: u1, + /// SWPMI Peripheral Clocks Enable + SWPMIEN: u1, + reserved4: u1, + /// OPAMP peripheral clock enable + OPAMPEN: u1, + /// MDIOS peripheral clock enable + MDIOSEN: u1, + reserved8: u2, + /// FDCAN Peripheral Clocks Enable + FDCANEN: u1, + reserved24: u15, + /// TIM23 block enable + TIM23EN: u1, + /// TIM24 block enable + TIM24EN: u1, + padding: u6, + }), + /// RCC APB2 Clock Register + APB2ENR: mmio.Mmio(packed struct(u32) { + /// TIM1 peripheral clock enable + TIM1EN: u1, + /// TIM8 peripheral clock enable + TIM8EN: u1, + reserved4: u2, + /// USART1 Peripheral Clocks Enable + USART1EN: u1, + /// USART6 Peripheral Clocks Enable + USART6EN: u1, + /// UART9 Peripheral Clocks Enable + UART9EN: u1, + /// USART10 Peripheral Clocks Enable + USART10EN: u1, + reserved12: u4, + /// SPI1 Peripheral Clocks Enable + SPI1EN: u1, + /// SPI4 Peripheral Clocks Enable + SPI4EN: u1, + reserved16: u2, + /// TIM15 peripheral clock enable + TIM15EN: u1, + /// TIM16 peripheral clock enable + TIM16EN: u1, + /// TIM17 peripheral clock enable + TIM17EN: u1, + reserved20: u1, + /// SPI5 Peripheral Clocks Enable + SPI5EN: u1, + reserved22: u1, + /// SAI1 Peripheral Clocks Enable + SAI1EN: u1, + /// SAI2 Peripheral Clocks Enable + SAI2EN: u1, + /// SAI3 Peripheral Clocks Enable + SAI3EN: u1, + reserved28: u3, + /// DFSDM1 Peripheral Clocks Enable + DFSDM1EN: u1, + /// HRTIM peripheral clock enable + HRTIMEN: u1, + padding: u2, + }), + /// RCC APB4 Clock Register + APB4ENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG peripheral clock enable + SYSCFGEN: u1, + reserved3: u1, + /// LPUART1 Peripheral Clocks Enable + LPUART1EN: u1, + reserved5: u1, + /// SPI6 Peripheral Clocks Enable + SPI6EN: u1, + reserved7: u1, + /// I2C4 Peripheral Clocks Enable + I2C4EN: u1, + reserved9: u1, + /// LPTIM2 Peripheral Clocks Enable + LPTIM2EN: u1, + /// LPTIM3 Peripheral Clocks Enable + LPTIM3EN: u1, + /// LPTIM4 Peripheral Clocks Enable + LPTIM4EN: u1, + /// LPTIM5 Peripheral Clocks Enable + LPTIM5EN: u1, + /// DAC2 (containing one converter) peripheral clock enable + DAC2EN: u1, + /// COMP1/2 peripheral clock enable + COMP12EN: u1, + /// VREF peripheral clock enable + VREFEN: u1, + /// RTC APB Clock Enable + RTCAPBEN: u1, + reserved21: u4, + /// SAI4 Peripheral Clocks Enable + SAI4EN: u1, + reserved26: u4, + /// Digital temperature sensor block enable + DTSEN: u1, + padding: u5, + }), + reserved252: [4]u8, + /// RCC AHB3 Sleep Clock Register + AHB3LPENR: mmio.Mmio(packed struct(u32) { + /// MDMA Clock Enable During CSleep Mode + MDMALPEN: u1, + reserved4: u3, + /// DMA2D Clock Enable During CSleep Mode + DMA2DLPEN: u1, + /// JPGDEC Clock Enable During CSleep Mode + JPGDECLPEN: u1, + reserved8: u2, + /// FLASH Clock Enable During CSleep Mode + FLASHLPEN: u1, + reserved12: u3, + /// FMC Peripheral Clocks Enable During CSleep Mode + FMCLPEN: u1, + reserved14: u1, + /// QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + QUADSPILPEN: u1, + reserved16: u1, + /// SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + SDMMC1LPEN: u1, + reserved19: u2, + /// OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode + OCTOSPI2LPEN: u1, + reserved21: u1, + /// OCTOSPI IO manager enable during CSleep Mode + IOMNGRLPEN: u1, + /// OTFDEC1 enable during CSleep Mode + OTFD1LPEN: u1, + /// OTFDEC2 enable during CSleep Mode + OTFD2LPEN: u1, + reserved28: u4, + /// D1DTCM1 Block Clock Enable During CSleep mode + D1DTCM1LPEN: u1, + /// D1 DTCM2 Block Clock Enable During CSleep mode + DTCM2LPEN: u1, + /// D1ITCM Block Clock Enable During CSleep mode + ITCMLPEN: u1, + /// AXISRAM Block Clock Enable During CSleep mode + AXISRAMLPEN: u1, + }), + /// RCC AHB1 Sleep Clock Register + AHB1LPENR: mmio.Mmio(packed struct(u32) { + /// DMA1 Clock Enable During CSleep Mode + DMA1LPEN: u1, + /// DMA2 Clock Enable During CSleep Mode + DMA2LPEN: u1, + reserved5: u3, + /// ADC1/2 Peripheral Clocks Enable During CSleep Mode + ADC12LPEN: u1, + reserved14: u8, + /// ART Clock Enable During CSleep Mode + ARTLPEN: u1, + /// Ethernet MAC bus interface Clock Enable During CSleep Mode + ETHLPEN: u1, + /// Ethernet Transmission Clock Enable During CSleep Mode + ETHTXLPEN: u1, + /// Ethernet Reception Clock Enable During CSleep Mode + ETHRXLPEN: u1, + reserved25: u7, + /// USB_OTG_HS peripheral clock enable during CSleep mode + USB_OTG_HSLPEN: u1, + /// USB_PHY1 clock enable during CSleep mode + USB_OTG_HS_ULPILPEN: u1, + /// USB_OTG_FS peripheral clock enable during CSleep mode + USB_OTG_FSLPEN: u1, + /// USB_PHY2 clocks enable during CSleep mode + USB_OTG_FS_ULPILPEN: u1, + padding: u3, + }), + /// RCC AHB2 Sleep Clock Register + AHB2LPENR: mmio.Mmio(packed struct(u32) { + /// DCMI peripheral clock enable during csleep mode + DCMILPEN: u1, + reserved4: u3, + /// CRYP peripheral clock enable during CSleep mode + CRYPLPEN: u1, + /// HASH peripheral clock enable during CSleep mode + HASHLPEN: u1, + /// RNG peripheral clock enable during CSleep mode + RNGLPEN: u1, + reserved9: u2, + /// SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + SDMMC2LPEN: u1, + reserved16: u6, + /// FMAC enable during CSleep Mode + FMACLPEN: u1, + /// CORDIC enable during CSleep Mode + CORDICLPEN: u1, + reserved29: u11, + /// SRAM1 Clock Enable During CSleep Mode + SRAM1LPEN: u1, + /// SRAM2 Clock Enable During CSleep Mode + SRAM2LPEN: u1, + /// SRAM3 Clock Enable During CSleep Mode + SRAM3LPEN: u1, + }), + /// RCC AHB4 Sleep Clock Register + AHB4LPENR: mmio.Mmio(packed struct(u32) { + /// GPIO peripheral clock enable during CSleep mode + GPIOALPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOBLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOCLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIODLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOELPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOFLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOGLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOHLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOILPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOJLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOKLPEN: u1, + reserved19: u8, + /// CRC peripheral clock enable during CSleep mode + CRCLPEN: u1, + reserved21: u1, + /// BDMA Clock Enable During CSleep Mode + BDMALPEN: u1, + reserved24: u2, + /// ADC3 Peripheral Clocks Enable During CSleep Mode + ADC3LPEN: u1, + reserved28: u3, + /// Backup RAM Clock Enable During CSleep Mode + BKPSRAMLPEN: u1, + /// SRAM4 Clock Enable During CSleep Mode + SRAM4LPEN: u1, + padding: u2, + }), + /// RCC APB3 Sleep Clock Register + APB3LPENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC peripheral clock enable during CSleep mode + LTDCLPEN: u1, + /// DSI Peripheral Clock Enable During CSleep Mode + DSILPEN: u1, + reserved6: u1, + /// WWDG1 Clock Enable During CSleep Mode + WWDG1LPEN: u1, + padding: u25, + }), + /// RCC APB1 Low Sleep Clock Register + APB1LLPENR: mmio.Mmio(packed struct(u32) { + /// TIM2 peripheral clock enable during CSleep mode + TIM2LPEN: u1, + /// TIM3 peripheral clock enable during CSleep mode + TIM3LPEN: u1, + /// TIM4 peripheral clock enable during CSleep mode + TIM4LPEN: u1, + /// TIM5 peripheral clock enable during CSleep mode + TIM5LPEN: u1, + /// TIM6 peripheral clock enable during CSleep mode + TIM6LPEN: u1, + /// TIM7 peripheral clock enable during CSleep mode + TIM7LPEN: u1, + /// TIM12 peripheral clock enable during CSleep mode + TIM12LPEN: u1, + /// TIM13 peripheral clock enable during CSleep mode + TIM13LPEN: u1, + /// TIM14 peripheral clock enable during CSleep mode + TIM14LPEN: u1, + /// LPTIM1 Peripheral Clocks Enable During CSleep Mode + LPTIM1LPEN: u1, + reserved11: u1, + /// WWDG2 peripheral Clocks Enable During CSleep Mode + WWDG2LPEN: u1, + reserved14: u2, + /// SPI2 Peripheral Clocks Enable During CSleep Mode + SPI2LPEN: u1, + /// SPI3 Peripheral Clocks Enable During CSleep Mode + SPI3LPEN: u1, + /// SPDIFRX Peripheral Clocks Enable During CSleep Mode + SPDIFRXLPEN: u1, + /// USART2 Peripheral Clocks Enable During CSleep Mode + USART2LPEN: u1, + /// USART3 Peripheral Clocks Enable During CSleep Mode + USART3LPEN: u1, + /// UART4 Peripheral Clocks Enable During CSleep Mode + UART4LPEN: u1, + /// UART5 Peripheral Clocks Enable During CSleep Mode + UART5LPEN: u1, + /// I2C1 Peripheral Clocks Enable During CSleep Mode + I2C1LPEN: u1, + /// I2C2 Peripheral Clocks Enable During CSleep Mode + I2C2LPEN: u1, + /// I2C3 Peripheral Clocks Enable During CSleep Mode + I2C3LPEN: u1, + reserved25: u1, + /// I2C5 block enable during CSleep Mode + I2C5LPEN: u1, + reserved27: u1, + /// HDMI-CEC Peripheral Clocks Enable During CSleep Mode + CECLPEN: u1, + reserved29: u1, + /// DAC1/2 peripheral clock enable during CSleep mode + DAC12LPEN: u1, + /// UART7 Peripheral Clocks Enable During CSleep Mode + UART7LPEN: u1, + /// UART8 Peripheral Clocks Enable During CSleep Mode + UART8LPEN: u1, + }), + /// RCC APB1 High Sleep Clock Register + APB1HLPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clock Recovery System peripheral clock enable during CSleep mode + CRSLPEN: u1, + /// SWPMI Peripheral Clocks Enable During CSleep Mode + SWPMILPEN: u1, + reserved4: u1, + /// OPAMP peripheral clock enable during CSleep mode + OPAMPLPEN: u1, + /// MDIOS peripheral clock enable during CSleep mode + MDIOSLPEN: u1, + reserved8: u2, + /// FDCAN Peripheral Clocks Enable During CSleep Mode + FDCANLPEN: u1, + reserved24: u15, + /// TIM23 block enable during CSleep Mode + TIM23LPEN: u1, + /// TIM24 block enable during CSleep Mode + TIM24LPEN: u1, + padding: u6, + }), + /// RCC APB2 Sleep Clock Register + APB2LPENR: mmio.Mmio(packed struct(u32) { + /// TIM1 peripheral clock enable during CSleep mode + TIM1LPEN: u1, + /// TIM8 peripheral clock enable during CSleep mode + TIM8LPEN: u1, + reserved4: u2, + /// USART1 Peripheral Clocks Enable During CSleep Mode + USART1LPEN: u1, + /// USART6 Peripheral Clocks Enable During CSleep Mode + USART6LPEN: u1, + reserved12: u6, + /// SPI1 Peripheral Clocks Enable During CSleep Mode + SPI1LPEN: u1, + /// SPI4 Peripheral Clocks Enable During CSleep Mode + SPI4LPEN: u1, + reserved16: u2, + /// TIM15 peripheral clock enable during CSleep mode + TIM15LPEN: u1, + /// TIM16 peripheral clock enable during CSleep mode + TIM16LPEN: u1, + /// TIM17 peripheral clock enable during CSleep mode + TIM17LPEN: u1, + reserved20: u1, + /// SPI5 Peripheral Clocks Enable During CSleep Mode + SPI5LPEN: u1, + reserved22: u1, + /// SAI1 Peripheral Clocks Enable During CSleep Mode + SAI1LPEN: u1, + /// SAI2 Peripheral Clocks Enable During CSleep Mode + SAI2LPEN: u1, + /// SAI3 Peripheral Clocks Enable During CSleep Mode + SAI3LPEN: u1, + reserved28: u3, + /// DFSDM1 Peripheral Clocks Enable During CSleep Mode + DFSDM1LPEN: u1, + /// HRTIM peripheral clock enable during CSleep mode + HRTIMLPEN: u1, + padding: u2, + }), + /// RCC APB4 Sleep Clock Register + APB4LPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG peripheral clock enable during CSleep mode + SYSCFGLPEN: u1, + reserved3: u1, + /// LPUART1 Peripheral Clocks Enable During CSleep Mode + LPUART1LPEN: u1, + reserved5: u1, + /// SPI6 Peripheral Clocks Enable During CSleep Mode + SPI6LPEN: u1, + reserved7: u1, + /// I2C4 Peripheral Clocks Enable During CSleep Mode + I2C4LPEN: u1, + reserved9: u1, + /// LPTIM2 Peripheral Clocks Enable During CSleep Mode + LPTIM2LPEN: u1, + /// LPTIM3 Peripheral Clocks Enable During CSleep Mode + LPTIM3LPEN: u1, + /// LPTIM4 Peripheral Clocks Enable During CSleep Mode + LPTIM4LPEN: u1, + /// LPTIM5 Peripheral Clocks Enable During CSleep Mode + LPTIM5LPEN: u1, + /// DAC2 (containing one converter) peripheral clock enable during CSleep mode + DAC2LPEN: u1, + /// COMP1/2 peripheral clock enable during CSleep mode + COMP12LPEN: u1, + /// VREF peripheral clock enable during CSleep mode + VREFLPEN: u1, + /// RTC APB Clock Enable During CSleep Mode + RTCAPBLPEN: u1, + reserved21: u4, + /// SAI4 Peripheral Clocks Enable During CSleep Mode + SAI4LPEN: u1, + reserved26: u4, + /// Digital temperature sensor block enable during CSleep Mode + DTSLPEN: u1, + padding: u5, + }), + reserved304: [16]u8, + /// RCC Reset Status Register + C1_RSR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Remove reset flag + RMVF: u1, + /// CPU reset flag + CPURSTF: u1, + reserved19: u1, + /// D1 domain power switch reset flag + D1RSTF: u1, + /// D2 domain power switch reset flag + D2RSTF: u1, + /// BOR reset flag + BORRSTF: u1, + /// Pin reset flag (NRST) + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// System reset from CPU reset flag + SFTRSTF: u1, + reserved26: u1, + /// Independent Watchdog reset flag + IWDG1RSTF: u1, + reserved28: u1, + /// Window Watchdog reset flag + WWDG1RSTF: u1, + reserved30: u1, + /// Reset due to illegal D1 DStandby or CPU CStop flag + LPWRRSTF: u1, + padding: u1, + }), + /// RCC AHB3 Clock Register + C1_AHB3ENR: mmio.Mmio(packed struct(u32) { + /// MDMA Peripheral Clock Enable + MDMAEN: u1, + reserved4: u3, + /// DMA2D Peripheral Clock Enable + DMA2DEN: u1, + /// JPGDEC Peripheral Clock Enable + JPGDECEN: u1, + reserved12: u6, + /// FMC Peripheral Clocks Enable + FMCEN: u1, + reserved14: u1, + /// QUADSPI and QUADSPI Delay Clock Enable + QUADSPIEN: u1, + reserved16: u1, + /// SDMMC1 and SDMMC1 Delay Clock Enable + SDMMC1EN: u1, + padding: u15, + }), + /// RCC AHB1 Clock Register + C1_AHB1ENR: mmio.Mmio(packed struct(u32) { + /// DMA1 Clock Enable + DMA1EN: u1, + /// DMA2 Clock Enable + DMA2EN: u1, + reserved5: u3, + /// ADC1/2 Peripheral Clocks Enable + ADC12EN: u1, + reserved14: u8, + /// ART Clock Enable + ARTEN: u1, + /// Ethernet MAC bus interface Clock Enable + ETHEN: u1, + /// Ethernet Transmission Clock Enable + ETHTXEN: u1, + /// Ethernet Reception Clock Enable + ETHRXEN: u1, + reserved25: u7, + /// USB_OTG_HS Peripheral Clocks Enable + USB_OTG_HSEN: u1, + /// USB_PHY1 Clocks Enable + USB_OTG_HS_ULPIEN: u1, + /// USB_OTG_FS Peripheral Clocks Enable + USB_OTG_FSEN: u1, + /// USB_PHY2 Clocks Enable + USB_OTG_FS_ULPIEN: u1, + padding: u3, + }), + /// RCC AHB2 Clock Register + C1_AHB2ENR: mmio.Mmio(packed struct(u32) { + /// DCMI peripheral clock + DCMIEN: u1, + reserved4: u3, + /// CRYP peripheral clock enable + CRYPEN: u1, + /// HASH peripheral clock enable + HASHEN: u1, + /// RNG peripheral clocks enable + RNGEN: u1, + reserved9: u2, + /// SDMMC2 and SDMMC2 delay clock enable + SDMMC2EN: u1, + reserved29: u19, + /// SRAM1 block enable + SRAM1EN: u1, + /// SRAM2 block enable + SRAM2EN: u1, + /// SRAM3 block enable + SRAM3EN: u1, + }), + /// RCC AHB4 Clock Register + C1_AHB4ENR: mmio.Mmio(packed struct(u32) { + /// 0GPIO peripheral clock enable + GPIOAEN: u1, + /// 0GPIO peripheral clock enable + GPIOBEN: u1, + /// 0GPIO peripheral clock enable + GPIOCEN: u1, + /// 0GPIO peripheral clock enable + GPIODEN: u1, + /// 0GPIO peripheral clock enable + GPIOEEN: u1, + /// 0GPIO peripheral clock enable + GPIOFEN: u1, + /// 0GPIO peripheral clock enable + GPIOGEN: u1, + /// 0GPIO peripheral clock enable + GPIOHEN: u1, + /// 0GPIO peripheral clock enable + GPIOIEN: u1, + /// 0GPIO peripheral clock enable + GPIOJEN: u1, + /// 0GPIO peripheral clock enable + GPIOKEN: u1, + reserved19: u8, + /// CRC peripheral clock enable + CRCEN: u1, + reserved21: u1, + /// BDMA and DMAMUX2 Clock Enable + BDMAEN: u1, + reserved24: u2, + /// ADC3 Peripheral Clocks Enable + ADC3EN: u1, + /// HSEM peripheral clock enable + HSEMEN: u1, + reserved28: u2, + /// Backup RAM Clock Enable + BKPSRAMEN: u1, + padding: u3, + }), + /// RCC APB3 Clock Register + C1_APB3ENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC peripheral clock enable + LTDCEN: u1, + /// DSI Peripheral clocks enable + DSIEN: u1, + reserved6: u1, + /// WWDG1 Clock Enable + WWDG1EN: u1, + padding: u25, + }), + /// RCC APB1 Clock Register + C1_APB1LENR: mmio.Mmio(packed struct(u32) { + /// TIM peripheral clock enable + TIM2EN: u1, + /// TIM peripheral clock enable + TIM3EN: u1, + /// TIM peripheral clock enable + TIM4EN: u1, + /// TIM peripheral clock enable + TIM5EN: u1, + /// TIM peripheral clock enable + TIM6EN: u1, + /// TIM peripheral clock enable + TIM7EN: u1, + /// TIM peripheral clock enable + TIM12EN: u1, + /// TIM peripheral clock enable + TIM13EN: u1, + /// TIM peripheral clock enable + TIM14EN: u1, + /// LPTIM1 Peripheral Clocks Enable + LPTIM1EN: u1, + reserved11: u1, + /// WWDG2 peripheral clock enable + WWDG2EN: u1, + reserved14: u2, + /// SPI2 Peripheral Clocks Enable + SPI2EN: u1, + /// SPI3 Peripheral Clocks Enable + SPI3EN: u1, + /// SPDIFRX Peripheral Clocks Enable + SPDIFRXEN: u1, + /// USART2 Peripheral Clocks Enable + USART2EN: u1, + /// USART3 Peripheral Clocks Enable + USART3EN: u1, + /// UART4 Peripheral Clocks Enable + UART4EN: u1, + /// UART5 Peripheral Clocks Enable + UART5EN: u1, + /// I2C1 Peripheral Clocks Enable + I2C1EN: u1, + /// I2C2 Peripheral Clocks Enable + I2C2EN: u1, + /// I2C3 Peripheral Clocks Enable + I2C3EN: u1, + reserved25: u1, + /// I2C5 Peripheral Clocks Enable + I2C5EN: u1, + reserved27: u1, + /// HDMI-CEC peripheral clock enable + CECEN: u1, + reserved29: u1, + /// DAC1&2 peripheral clock enable + DAC12EN: u1, + /// UART7 Peripheral Clocks Enable + UART7EN: u1, + /// UART8 Peripheral Clocks Enable + UART8EN: u1, + }), + /// RCC APB1 Clock Register + C1_APB1HENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clock Recovery System peripheral clock enable + CRSEN: u1, + /// SWPMI Peripheral Clocks Enable + SWPMIEN: u1, + reserved4: u1, + /// OPAMP peripheral clock enable + OPAMPEN: u1, + /// MDIOS peripheral clock enable + MDIOSEN: u1, + reserved8: u2, + /// FDCAN Peripheral Clocks Enable + FDCANEN: u1, + padding: u23, + }), + /// RCC APB2 Clock Register + C1_APB2ENR: mmio.Mmio(packed struct(u32) { + /// TIM1 peripheral clock enable + TIM1EN: u1, + /// TIM8 peripheral clock enable + TIM8EN: u1, + reserved4: u2, + /// USART1 Peripheral Clocks Enable + USART1EN: u1, + /// USART6 Peripheral Clocks Enable + USART6EN: u1, + /// UART9 Peripheral Clocks Enable + UART9EN: u1, + /// USART10 Peripheral Clocks Enable + USART10EN: u1, + reserved12: u4, + /// SPI1 Peripheral Clocks Enable + SPI1EN: u1, + /// SPI4 Peripheral Clocks Enable + SPI4EN: u1, + reserved16: u2, + /// TIM15 peripheral clock enable + TIM15EN: u1, + /// TIM16 peripheral clock enable + TIM16EN: u1, + /// TIM17 peripheral clock enable + TIM17EN: u1, + reserved20: u1, + /// SPI5 Peripheral Clocks Enable + SPI5EN: u1, + reserved22: u1, + /// SAI1 Peripheral Clocks Enable + SAI1EN: u1, + /// SAI2 Peripheral Clocks Enable + SAI2EN: u1, + /// SAI3 Peripheral Clocks Enable + SAI3EN: u1, + reserved28: u3, + /// DFSDM1 Peripheral Clocks Enable + DFSDM1EN: u1, + /// HRTIM peripheral clock enable + HRTIMEN: u1, + padding: u2, + }), + /// RCC APB4 Clock Register + C1_APB4ENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG peripheral clock enable + SYSCFGEN: u1, + reserved3: u1, + /// LPUART1 Peripheral Clocks Enable + LPUART1EN: u1, + reserved5: u1, + /// SPI6 Peripheral Clocks Enable + SPI6EN: u1, + reserved7: u1, + /// I2C4 Peripheral Clocks Enable + I2C4EN: u1, + reserved9: u1, + /// LPTIM2 Peripheral Clocks Enable + LPTIM2EN: u1, + /// LPTIM3 Peripheral Clocks Enable + LPTIM3EN: u1, + /// LPTIM4 Peripheral Clocks Enable + LPTIM4EN: u1, + /// LPTIM5 Peripheral Clocks Enable + LPTIM5EN: u1, + reserved14: u1, + /// COMP1/2 peripheral clock enable + COMP12EN: u1, + /// VREF peripheral clock enable + VREFEN: u1, + /// RTC APB Clock Enable + RTCAPBEN: u1, + reserved21: u4, + /// SAI4 Peripheral Clocks Enable + SAI4EN: u1, + padding: u10, + }), + reserved348: [4]u8, + /// RCC AHB3 Sleep Clock Register + C1_AHB3LPENR: mmio.Mmio(packed struct(u32) { + /// MDMA Clock Enable During CSleep Mode + MDMALPEN: u1, + reserved4: u3, + /// DMA2D Clock Enable During CSleep Mode + DMA2DLPEN: u1, + /// JPGDEC Clock Enable During CSleep Mode + JPGDECLPEN: u1, + reserved8: u2, + /// Flash interface clock enable during csleep mode + FLASHPREN: u1, + reserved12: u3, + /// FMC Peripheral Clocks Enable During CSleep Mode + FMCLPEN: u1, + reserved14: u1, + /// QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + QUADSPILPEN: u1, + reserved16: u1, + /// SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + SDMMC1LPEN: u1, + reserved19: u2, + /// OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode + OCTOSPI2LPEN: u1, + reserved21: u1, + /// OCTOSPI IO manager enable during CSleep Mode + IOMNGRLPEN: u1, + /// OTFDEC1 enable during CSleep Mode + OTFD1LPEN: u1, + /// OTFDEC2 enable during CSleep Mode + OTFD2LPEN: u1, + reserved28: u4, + /// D1DTCM1 Block Clock Enable During CSleep mode + D1DTCM1LPEN: u1, + /// D1 DTCM2 Block Clock Enable During CSleep mode + DTCM2LPEN: u1, + /// D1ITCM Block Clock Enable During CSleep mode + ITCMLPEN: u1, + /// AXISRAM Block Clock Enable During CSleep mode + AXISRAMLPEN: u1, + }), + /// RCC AHB1 Sleep Clock Register + C1_AHB1LPENR: mmio.Mmio(packed struct(u32) { + /// DMA1 Clock Enable During CSleep Mode + DMA1LPEN: u1, + /// DMA2 Clock Enable During CSleep Mode + DMA2LPEN: u1, + reserved5: u3, + /// ADC1/2 Peripheral Clocks Enable During CSleep Mode + ADC12LPEN: u1, + reserved14: u8, + /// ART Clock Enable During CSleep Mode + ARTLPEN: u1, + /// Ethernet MAC bus interface Clock Enable During CSleep Mode + ETHLPEN: u1, + /// Ethernet Transmission Clock Enable During CSleep Mode + ETHTXLPEN: u1, + /// Ethernet Reception Clock Enable During CSleep Mode + ETHRXLPEN: u1, + reserved25: u7, + /// USB_OTG_HS peripheral clock enable during CSleep mode + USB_OTG_HSLPEN: u1, + /// USB_PHY1 clock enable during CSleep mode + USB_OTG_HS_ULPILPEN: u1, + /// USB_OTG_FS peripheral clock enable during CSleep mode + USB_OTG_FSLPEN: u1, + /// USB_PHY2 clocks enable during CSleep mode + USB_OTG_FS_ULPILPEN: u1, + padding: u3, + }), + /// RCC AHB2 Sleep Clock Register + C1_AHB2LPENR: mmio.Mmio(packed struct(u32) { + /// DCMI peripheral clock enable during csleep mode + DCMILPEN: u1, + reserved4: u3, + /// CRYP peripheral clock enable during CSleep mode + CRYPLPEN: u1, + /// HASH peripheral clock enable during CSleep mode + HASHLPEN: u1, + /// RNG peripheral clock enable during CSleep mode + RNGLPEN: u1, + reserved9: u2, + /// SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + SDMMC2LPEN: u1, + reserved16: u6, + /// FMAC enable during CSleep Mode + FMACLPEN: u1, + /// CORDIC enable during CSleep Mode + CORDICLPEN: u1, + reserved29: u11, + /// SRAM1 Clock Enable During CSleep Mode + SRAM1LPEN: u1, + /// SRAM2 Clock Enable During CSleep Mode + SRAM2LPEN: u1, + /// SRAM3 Clock Enable During CSleep Mode + SRAM3LPEN: u1, + }), + /// RCC AHB4 Sleep Clock Register + C1_AHB4LPENR: mmio.Mmio(packed struct(u32) { + /// GPIO peripheral clock enable during CSleep mode + GPIOALPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOBLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOCLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIODLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOELPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOFLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOGLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOHLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOILPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOJLPEN: u1, + /// GPIO peripheral clock enable during CSleep mode + GPIOKLPEN: u1, + reserved19: u8, + /// CRC peripheral clock enable during CSleep mode + CRCLPEN: u1, + reserved21: u1, + /// BDMA Clock Enable During CSleep Mode + BDMALPEN: u1, + reserved24: u2, + /// ADC3 Peripheral Clocks Enable During CSleep Mode + ADC3LPEN: u1, + reserved28: u3, + /// Backup RAM Clock Enable During CSleep Mode + BKPSRAMLPEN: u1, + /// SRAM4 Clock Enable During CSleep Mode + SRAM4LPEN: u1, + padding: u2, + }), + /// RCC APB3 Sleep Clock Register + C1_APB3LPENR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// LTDC peripheral clock enable during CSleep mode + LTDCLPEN: u1, + /// DSI Peripheral Clock Enable During CSleep Mode + DSILPEN: u1, + reserved6: u1, + /// WWDG1 Clock Enable During CSleep Mode + WWDG1LPEN: u1, + padding: u25, + }), + /// RCC APB1 Low Sleep Clock Register + C1_APB1LLPENR: mmio.Mmio(packed struct(u32) { + /// TIM2 peripheral clock enable during CSleep mode + TIM2LPEN: u1, + /// TIM3 peripheral clock enable during CSleep mode + TIM3LPEN: u1, + /// TIM4 peripheral clock enable during CSleep mode + TIM4LPEN: u1, + /// TIM5 peripheral clock enable during CSleep mode + TIM5LPEN: u1, + /// TIM6 peripheral clock enable during CSleep mode + TIM6LPEN: u1, + /// TIM7 peripheral clock enable during CSleep mode + TIM7LPEN: u1, + /// TIM12 peripheral clock enable during CSleep mode + TIM12LPEN: u1, + /// TIM13 peripheral clock enable during CSleep mode + TIM13LPEN: u1, + /// TIM14 peripheral clock enable during CSleep mode + TIM14LPEN: u1, + /// LPTIM1 Peripheral Clocks Enable During CSleep Mode + LPTIM1LPEN: u1, + reserved11: u1, + /// WWDG2 peripheral Clocks Enable During CSleep Mode + WWDG2LPEN: u1, + reserved14: u2, + /// SPI2 Peripheral Clocks Enable During CSleep Mode + SPI2LPEN: u1, + /// SPI3 Peripheral Clocks Enable During CSleep Mode + SPI3LPEN: u1, + /// SPDIFRX Peripheral Clocks Enable During CSleep Mode + SPDIFRXLPEN: u1, + /// USART2 Peripheral Clocks Enable During CSleep Mode + USART2LPEN: u1, + /// USART3 Peripheral Clocks Enable During CSleep Mode + USART3LPEN: u1, + /// UART4 Peripheral Clocks Enable During CSleep Mode + UART4LPEN: u1, + /// UART5 Peripheral Clocks Enable During CSleep Mode + UART5LPEN: u1, + /// I2C1 Peripheral Clocks Enable During CSleep Mode + I2C1LPEN: u1, + /// I2C2 Peripheral Clocks Enable During CSleep Mode + I2C2LPEN: u1, + /// I2C3 Peripheral Clocks Enable During CSleep Mode + I2C3LPEN: u1, + reserved25: u1, + /// I2C5 block enable during CSleep Mode + I2C5LPEN: u1, + reserved27: u1, + /// HDMI-CEC Peripheral Clocks Enable During CSleep Mode + CECLPEN: u1, + reserved29: u1, + /// DAC1/2 peripheral clock enable during CSleep mode + DAC12LPEN: u1, + /// UART7 Peripheral Clocks Enable During CSleep Mode + UART7LPEN: u1, + /// UART8 Peripheral Clocks Enable During CSleep Mode + UART8LPEN: u1, + }), + /// RCC APB1 High Sleep Clock Register + C1_APB1HLPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Clock Recovery System peripheral clock enable during CSleep mode + CRSLPEN: u1, + /// SWPMI Peripheral Clocks Enable During CSleep Mode + SWPMILPEN: u1, + reserved4: u1, + /// OPAMP peripheral clock enable during CSleep mode + OPAMPLPEN: u1, + /// MDIOS peripheral clock enable during CSleep mode + MDIOSLPEN: u1, + reserved8: u2, + /// FDCAN Peripheral Clocks Enable During CSleep Mode + FDCANLPEN: u1, + reserved24: u15, + /// TIM23 block enable during CSleep Mode + TIM23LPEN: u1, + /// TIM24 block enable during CSleep Mode + TIM24LPEN: u1, + padding: u6, + }), + /// RCC APB2 Sleep Clock Register + C1_APB2LPENR: mmio.Mmio(packed struct(u32) { + /// TIM1 peripheral clock enable during CSleep mode + TIM1LPEN: u1, + /// TIM8 peripheral clock enable during CSleep mode + TIM8LPEN: u1, + reserved4: u2, + /// USART1 Peripheral Clocks Enable During CSleep Mode + USART1LPEN: u1, + /// USART6 Peripheral Clocks Enable During CSleep Mode + USART6LPEN: u1, + reserved12: u6, + /// SPI1 Peripheral Clocks Enable During CSleep Mode + SPI1LPEN: u1, + /// SPI4 Peripheral Clocks Enable During CSleep Mode + SPI4LPEN: u1, + reserved16: u2, + /// TIM15 peripheral clock enable during CSleep mode + TIM15LPEN: u1, + /// TIM16 peripheral clock enable during CSleep mode + TIM16LPEN: u1, + /// TIM17 peripheral clock enable during CSleep mode + TIM17LPEN: u1, + reserved20: u1, + /// SPI5 Peripheral Clocks Enable During CSleep Mode + SPI5LPEN: u1, + reserved22: u1, + /// SAI1 Peripheral Clocks Enable During CSleep Mode + SAI1LPEN: u1, + /// SAI2 Peripheral Clocks Enable During CSleep Mode + SAI2LPEN: u1, + /// SAI3 Peripheral Clocks Enable During CSleep Mode + SAI3LPEN: u1, + reserved28: u3, + /// DFSDM1 Peripheral Clocks Enable During CSleep Mode + DFSDM1LPEN: u1, + /// HRTIM peripheral clock enable during CSleep mode + HRTIMLPEN: u1, + padding: u2, + }), + /// RCC APB4 Sleep Clock Register + C1_APB4LPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG peripheral clock enable during CSleep mode + SYSCFGLPEN: u1, + reserved3: u1, + /// LPUART1 Peripheral Clocks Enable During CSleep Mode + LPUART1LPEN: u1, + reserved5: u1, + /// SPI6 Peripheral Clocks Enable During CSleep Mode + SPI6LPEN: u1, + reserved7: u1, + /// I2C4 Peripheral Clocks Enable During CSleep Mode + I2C4LPEN: u1, + reserved9: u1, + /// LPTIM2 Peripheral Clocks Enable During CSleep Mode + LPTIM2LPEN: u1, + /// LPTIM3 Peripheral Clocks Enable During CSleep Mode + LPTIM3LPEN: u1, + /// LPTIM4 Peripheral Clocks Enable During CSleep Mode + LPTIM4LPEN: u1, + /// LPTIM5 Peripheral Clocks Enable During CSleep Mode + LPTIM5LPEN: u1, + reserved14: u1, + /// COMP1/2 peripheral clock enable during CSleep mode + COMP12LPEN: u1, + /// VREF peripheral clock enable during CSleep mode + VREFLPEN: u1, + /// RTC APB Clock Enable During CSleep Mode + RTCAPBLPEN: u1, + reserved21: u4, + /// SAI4 Peripheral Clocks Enable During CSleep Mode + SAI4LPEN: u1, + reserved26: u4, + /// Digital temperature sensor block enable during CSleep Mode + DTSLPEN: u1, + padding: u5, + }), + }; + }; + + pub const rcc_h7rs = struct { + pub const ADCSEL = enum(u2) { + /// pll2_p selected as peripheral clock + PLL2_P = 0x0, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// PER selected as peripheral clock + PER = 0x2, + _, + }; + + pub const ADFSEL = enum(u3) { + /// hclk1 selected as ADF kernel clock (default after reset). + HCLK1 = 0x0, + /// pll2_p_ck selected as ADF kernel clock. + PLL2_P = 0x1, + _, + }; + + pub const CECSEL = enum(u2) { + /// LSE selected as peripheral clock + LSE = 0x0, + /// LSI selected as peripheral clock + LSI = 0x1, + /// csi_ker selected as peripheral clock + CSI = 0x2, + _, + }; + + pub const DWNSPREAD = enum(u1) { + /// Center-spread modulation selected (default after reset). + CenterSpread = 0x0, + /// Down-spread modulation selected. + DownSpread = 0x1, + }; + + pub const ETHPHY_CLK_SEL = enum(u1) { + /// hse_ker_ck selected as clock source (default after reset). + HSE = 0x0, + /// pll3_s_ck selected clock source. + PLL3_S = 0x1, + }; + + pub const ETH_REF_CLK_SEL = enum(u2) { + /// PAD ETH_RMII_REF_CLK selected as kernel peripheral clock (default after reset). + ETH_RMII_REF = 0x0, + /// hse_ker_ck selected as kernel peripheral clock. + HSE = 0x1, + /// eth_clk_fb selected as kernel peripheral clock. + ETH = 0x2, + _, + }; + + pub const FDCANSEL = enum(u2) { + /// HSE selected as peripheral clock + HSE = 0x0, + /// pll1_q selected as peripheral clock + PLL1_Q = 0x1, + /// pll2_p selected as peripheral clock + PLL2_P = 0x2, + _, + }; + + pub const FMCSEL = enum(u2) { + /// hclk5 selected as kernel peripheral clock (default after reset). + HCLK5 = 0x0, + /// pll1_q_ck selected as kernel peripheral clock. + PLL1_Q = 0x1, + /// pll2_r_ck selected as kernel peripheral clock. + PLL2_R = 0x2, + /// hsi_ker_ck selected as kernel peripheral clock. + HSI = 0x3, + }; + + pub const FMCSWP = enum(u3) { + /// The switch is in neutral mode and output clock is gated (default after reset). + B_0x0 = 0x0, + /// The switch is selecting hclk5. + B_0x1 = 0x1, + /// The switch is selecting pll1_q_ck. + B_0x2 = 0x2, + /// The switch is selecting pll2_r_ck. + B_0x3 = 0x3, + /// The switch is selecting hsi_ker_ck. + B_0x4 = 0x4, + /// The switch is in recovery position (hclk5/4). + B_0x5 = 0x5, + _, + }; + + pub const HPRE = enum(u4) { + Div1 = 0x0, + Div2 = 0x8, + Div4 = 0x9, + Div8 = 0xa, + Div16 = 0xb, + Div64 = 0xc, + Div128 = 0xd, + Div256 = 0xe, + Div512 = 0xf, + _, + }; + + pub const HSEEXT = enum(u1) { + /// HSE in analog mode (default after reset) + Analog = 0x0, + /// HSE in digital mode + Digital = 0x1, + }; + + pub const HSIDIV = enum(u2) { + /// division by 1, hsi(_ker)_ck = 64 MHz (default after reset). + Div1 = 0x0, + /// division by 2, hsi(_ker)_ck = 32 MHz. + Div2 = 0x1, + /// division by 4, hsi(_ker)_ck = 16 MHz. + Div4 = 0x2, + /// division by 8, hsi(_ker)_ck = 8 MHz. + Div8 = 0x3, + }; + + pub const I2C1_I3C1SEL = enum(u2) { + /// rcc_pclk1 selected as peripheral clock + PCLK1 = 0x0, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// hsi_ker selected as peripheral clock + HSI = 0x2, + /// csi_ker selected as peripheral clock + CSI = 0x3, + }; + + pub const I2CSEL = enum(u2) { + /// pclk1 selected as kernel clock (default after reset). + PCLK1 = 0x0, + /// pll3_r selected as peripheral clock + PLL3_R = 0x1, + /// hsi_ker selected as peripheral clock + HSI = 0x2, + /// csi_ker selected as peripheral clock + CSI = 0x3, + }; + + pub const LPTIM1SEL = enum(u3) { + /// rcc_pclk1 selected as peripheral clock + PCLK1 = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_r selected as peripheral clock + PLL3_R = 0x2, + /// LSE selected as peripheral clock + LSE = 0x3, + /// LSI selected as peripheral clock + LSI = 0x4, + /// PER selected as peripheral clock + PER = 0x5, + _, + }; + + pub const LPTIMSEL = enum(u3) { + /// rcc_pclk4 selected as peripheral clock + PCLK4 = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_r selected as peripheral clock + PLL3_R = 0x2, + /// LSE selected as peripheral clock + LSE = 0x3, + /// LSI selected as peripheral clock + LSI = 0x4, + /// PER selected as peripheral clock + PER = 0x5, + _, + }; + + pub const LPUARTSEL = enum(u3) { + /// rcc_pclk_d4 selected as peripheral clock + PCLK4 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const MCO1SEL = enum(u3) { + /// HSI selected for micro-controller clock output + HSI = 0x0, + /// LSE selected for micro-controller clock output + LSE = 0x1, + /// HSE selected for micro-controller clock output + HSE = 0x2, + /// pll1_q selected for micro-controller clock output + PLL1_Q = 0x3, + /// HSI48 selected for micro-controller clock output + HSI48 = 0x4, + _, + }; + + pub const MCO2SEL = enum(u3) { + /// System clock selected for micro-controller clock output + SYS = 0x0, + /// pll2_p selected for micro-controller clock output + PLL2_P = 0x1, + /// HSE selected for micro-controller clock output + HSE = 0x2, + /// pll1_p selected for micro-controller clock output + PLL1_P = 0x3, + /// CSI selected for micro-controller clock output + CSI = 0x4, + /// LSI selected for micro-controller clock output + LSI = 0x5, + _, + }; + + pub const MCOPRE = enum(u4) { + /// Divide by 1 + Div1 = 0x1, + /// Divide by 2 + Div2 = 0x2, + /// Divide by 3 + Div3 = 0x3, + /// Divide by 4 + Div4 = 0x4, + /// Divide by 5 + Div5 = 0x5, + /// Divide by 6 + Div6 = 0x6, + /// Divide by 7 + Div7 = 0x7, + /// Divide by 8 + Div8 = 0x8, + /// Divide by 9 + Div9 = 0x9, + /// Divide by 10 + Div10 = 0xa, + /// Divide by 11 + Div11 = 0xb, + /// Divide by 12 + Div12 = 0xc, + /// Divide by 13 + Div13 = 0xd, + /// Divide by 14 + Div14 = 0xe, + /// Divide by 15 + Div15 = 0xf, + _, + }; + + pub const OCTOSPISEL = enum(u2) { + /// hclk5 selected as kernel peripheral clock (default after reset). + HCLK5 = 0x0, + /// pll2_s_ck selected as kernel peripheral clock. + PLL2_S = 0x1, + _, + }; + + pub const PERSEL = enum(u2) { + /// HSI selected as peripheral clock + HSI = 0x0, + /// CSI selected as peripheral clock + CSI = 0x1, + /// HSE selected as peripheral clock + HSE = 0x2, + _, + }; + + pub const PLLDIV = enum(u7) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + Div17 = 0x10, + Div18 = 0x11, + Div19 = 0x12, + Div20 = 0x13, + Div21 = 0x14, + Div22 = 0x15, + Div23 = 0x16, + Div24 = 0x17, + Div25 = 0x18, + Div26 = 0x19, + Div27 = 0x1a, + Div28 = 0x1b, + Div29 = 0x1c, + Div30 = 0x1d, + Div31 = 0x1e, + Div32 = 0x1f, + Div33 = 0x20, + Div34 = 0x21, + Div35 = 0x22, + Div36 = 0x23, + Div37 = 0x24, + Div38 = 0x25, + Div39 = 0x26, + Div40 = 0x27, + Div41 = 0x28, + Div42 = 0x29, + Div43 = 0x2a, + Div44 = 0x2b, + Div45 = 0x2c, + Div46 = 0x2d, + Div47 = 0x2e, + Div48 = 0x2f, + Div49 = 0x30, + Div50 = 0x31, + Div51 = 0x32, + Div52 = 0x33, + Div53 = 0x34, + Div54 = 0x35, + Div55 = 0x36, + Div56 = 0x37, + Div57 = 0x38, + Div58 = 0x39, + Div59 = 0x3a, + Div60 = 0x3b, + Div61 = 0x3c, + Div62 = 0x3d, + Div63 = 0x3e, + Div64 = 0x3f, + Div65 = 0x40, + Div66 = 0x41, + Div67 = 0x42, + Div68 = 0x43, + Div69 = 0x44, + Div70 = 0x45, + Div71 = 0x46, + Div72 = 0x47, + Div73 = 0x48, + Div74 = 0x49, + Div75 = 0x4a, + Div76 = 0x4b, + Div77 = 0x4c, + Div78 = 0x4d, + Div79 = 0x4e, + Div80 = 0x4f, + Div81 = 0x50, + Div82 = 0x51, + Div83 = 0x52, + Div84 = 0x53, + Div85 = 0x54, + Div86 = 0x55, + Div87 = 0x56, + Div88 = 0x57, + Div89 = 0x58, + Div90 = 0x59, + Div91 = 0x5a, + Div92 = 0x5b, + Div93 = 0x5c, + Div94 = 0x5d, + Div95 = 0x5e, + Div96 = 0x5f, + Div97 = 0x60, + Div98 = 0x61, + Div99 = 0x62, + Div100 = 0x63, + Div101 = 0x64, + Div102 = 0x65, + Div103 = 0x66, + Div104 = 0x67, + Div105 = 0x68, + Div106 = 0x69, + Div107 = 0x6a, + Div108 = 0x6b, + Div109 = 0x6c, + Div110 = 0x6d, + Div111 = 0x6e, + Div112 = 0x6f, + Div113 = 0x70, + Div114 = 0x71, + Div115 = 0x72, + Div116 = 0x73, + Div117 = 0x74, + Div118 = 0x75, + Div119 = 0x76, + Div120 = 0x77, + Div121 = 0x78, + Div122 = 0x79, + Div123 = 0x7a, + Div124 = 0x7b, + Div125 = 0x7c, + Div126 = 0x7d, + Div127 = 0x7e, + Div128 = 0x7f, + }; + + pub const PLLDIVST = enum(u3) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + }; + + pub const PLLM = enum(u6) { + Div1 = 0x1, + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + Div16 = 0x10, + Div17 = 0x11, + Div18 = 0x12, + Div19 = 0x13, + Div20 = 0x14, + Div21 = 0x15, + Div22 = 0x16, + Div23 = 0x17, + Div24 = 0x18, + Div25 = 0x19, + Div26 = 0x1a, + Div27 = 0x1b, + Div28 = 0x1c, + Div29 = 0x1d, + Div30 = 0x1e, + Div31 = 0x1f, + Div32 = 0x20, + Div33 = 0x21, + Div34 = 0x22, + Div35 = 0x23, + Div36 = 0x24, + Div37 = 0x25, + Div38 = 0x26, + Div39 = 0x27, + Div40 = 0x28, + Div41 = 0x29, + Div42 = 0x2a, + Div43 = 0x2b, + Div44 = 0x2c, + Div45 = 0x2d, + Div46 = 0x2e, + Div47 = 0x2f, + Div48 = 0x30, + Div49 = 0x31, + Div50 = 0x32, + Div51 = 0x33, + Div52 = 0x34, + Div53 = 0x35, + Div54 = 0x36, + Div55 = 0x37, + Div56 = 0x38, + Div57 = 0x39, + Div58 = 0x3a, + Div59 = 0x3b, + Div60 = 0x3c, + Div61 = 0x3d, + Div62 = 0x3e, + Div63 = 0x3f, + _, + }; + + pub const PLLN = enum(u9) { + Mul8 = 0x7, + Mul9 = 0x8, + Mul10 = 0x9, + Mul11 = 0xa, + Mul12 = 0xb, + Mul13 = 0xc, + Mul14 = 0xd, + Mul15 = 0xe, + Mul16 = 0xf, + Mul17 = 0x10, + Mul18 = 0x11, + Mul19 = 0x12, + Mul20 = 0x13, + Mul21 = 0x14, + Mul22 = 0x15, + Mul23 = 0x16, + Mul24 = 0x17, + Mul25 = 0x18, + Mul26 = 0x19, + Mul27 = 0x1a, + Mul28 = 0x1b, + Mul29 = 0x1c, + Mul30 = 0x1d, + Mul31 = 0x1e, + Mul32 = 0x1f, + Mul33 = 0x20, + Mul34 = 0x21, + Mul35 = 0x22, + Mul36 = 0x23, + Mul37 = 0x24, + Mul38 = 0x25, + Mul39 = 0x26, + Mul40 = 0x27, + Mul41 = 0x28, + Mul42 = 0x29, + Mul43 = 0x2a, + Mul44 = 0x2b, + Mul45 = 0x2c, + Mul46 = 0x2d, + Mul47 = 0x2e, + Mul48 = 0x2f, + Mul49 = 0x30, + Mul50 = 0x31, + Mul51 = 0x32, + Mul52 = 0x33, + Mul53 = 0x34, + Mul54 = 0x35, + Mul55 = 0x36, + Mul56 = 0x37, + Mul57 = 0x38, + Mul58 = 0x39, + Mul59 = 0x3a, + Mul60 = 0x3b, + Mul61 = 0x3c, + Mul62 = 0x3d, + Mul63 = 0x3e, + Mul64 = 0x3f, + Mul65 = 0x40, + Mul66 = 0x41, + Mul67 = 0x42, + Mul68 = 0x43, + Mul69 = 0x44, + Mul70 = 0x45, + Mul71 = 0x46, + Mul72 = 0x47, + Mul73 = 0x48, + Mul74 = 0x49, + Mul75 = 0x4a, + Mul76 = 0x4b, + Mul77 = 0x4c, + Mul78 = 0x4d, + Mul79 = 0x4e, + Mul80 = 0x4f, + Mul81 = 0x50, + Mul82 = 0x51, + Mul83 = 0x52, + Mul84 = 0x53, + Mul85 = 0x54, + Mul86 = 0x55, + Mul87 = 0x56, + Mul88 = 0x57, + Mul89 = 0x58, + Mul90 = 0x59, + Mul91 = 0x5a, + Mul92 = 0x5b, + Mul93 = 0x5c, + Mul94 = 0x5d, + Mul95 = 0x5e, + Mul96 = 0x5f, + Mul97 = 0x60, + Mul98 = 0x61, + Mul99 = 0x62, + Mul100 = 0x63, + Mul101 = 0x64, + Mul102 = 0x65, + Mul103 = 0x66, + Mul104 = 0x67, + Mul105 = 0x68, + Mul106 = 0x69, + Mul107 = 0x6a, + Mul108 = 0x6b, + Mul109 = 0x6c, + Mul110 = 0x6d, + Mul111 = 0x6e, + Mul112 = 0x6f, + Mul113 = 0x70, + Mul114 = 0x71, + Mul115 = 0x72, + Mul116 = 0x73, + Mul117 = 0x74, + Mul118 = 0x75, + Mul119 = 0x76, + Mul120 = 0x77, + Mul121 = 0x78, + Mul122 = 0x79, + Mul123 = 0x7a, + Mul124 = 0x7b, + Mul125 = 0x7c, + Mul126 = 0x7d, + Mul127 = 0x7e, + Mul128 = 0x7f, + Mul129 = 0x80, + Mul130 = 0x81, + Mul131 = 0x82, + Mul132 = 0x83, + Mul133 = 0x84, + Mul134 = 0x85, + Mul135 = 0x86, + Mul136 = 0x87, + Mul137 = 0x88, + Mul138 = 0x89, + Mul139 = 0x8a, + Mul140 = 0x8b, + Mul141 = 0x8c, + Mul142 = 0x8d, + Mul143 = 0x8e, + Mul144 = 0x8f, + Mul145 = 0x90, + Mul146 = 0x91, + Mul147 = 0x92, + Mul148 = 0x93, + Mul149 = 0x94, + Mul150 = 0x95, + Mul151 = 0x96, + Mul152 = 0x97, + Mul153 = 0x98, + Mul154 = 0x99, + Mul155 = 0x9a, + Mul156 = 0x9b, + Mul157 = 0x9c, + Mul158 = 0x9d, + Mul159 = 0x9e, + Mul160 = 0x9f, + Mul161 = 0xa0, + Mul162 = 0xa1, + Mul163 = 0xa2, + Mul164 = 0xa3, + Mul165 = 0xa4, + Mul166 = 0xa5, + Mul167 = 0xa6, + Mul168 = 0xa7, + Mul169 = 0xa8, + Mul170 = 0xa9, + Mul171 = 0xaa, + Mul172 = 0xab, + Mul173 = 0xac, + Mul174 = 0xad, + Mul175 = 0xae, + Mul176 = 0xaf, + Mul177 = 0xb0, + Mul178 = 0xb1, + Mul179 = 0xb2, + Mul180 = 0xb3, + Mul181 = 0xb4, + Mul182 = 0xb5, + Mul183 = 0xb6, + Mul184 = 0xb7, + Mul185 = 0xb8, + Mul186 = 0xb9, + Mul187 = 0xba, + Mul188 = 0xbb, + Mul189 = 0xbc, + Mul190 = 0xbd, + Mul191 = 0xbe, + Mul192 = 0xbf, + Mul193 = 0xc0, + Mul194 = 0xc1, + Mul195 = 0xc2, + Mul196 = 0xc3, + Mul197 = 0xc4, + Mul198 = 0xc5, + Mul199 = 0xc6, + Mul200 = 0xc7, + Mul201 = 0xc8, + Mul202 = 0xc9, + Mul203 = 0xca, + Mul204 = 0xcb, + Mul205 = 0xcc, + Mul206 = 0xcd, + Mul207 = 0xce, + Mul208 = 0xcf, + Mul209 = 0xd0, + Mul210 = 0xd1, + Mul211 = 0xd2, + Mul212 = 0xd3, + Mul213 = 0xd4, + Mul214 = 0xd5, + Mul215 = 0xd6, + Mul216 = 0xd7, + Mul217 = 0xd8, + Mul218 = 0xd9, + Mul219 = 0xda, + Mul220 = 0xdb, + Mul221 = 0xdc, + Mul222 = 0xdd, + Mul223 = 0xde, + Mul224 = 0xdf, + Mul225 = 0xe0, + Mul226 = 0xe1, + Mul227 = 0xe2, + Mul228 = 0xe3, + Mul229 = 0xe4, + Mul230 = 0xe5, + Mul231 = 0xe6, + Mul232 = 0xe7, + Mul233 = 0xe8, + Mul234 = 0xe9, + Mul235 = 0xea, + Mul236 = 0xeb, + Mul237 = 0xec, + Mul238 = 0xed, + Mul239 = 0xee, + Mul240 = 0xef, + Mul241 = 0xf0, + Mul242 = 0xf1, + Mul243 = 0xf2, + Mul244 = 0xf3, + Mul245 = 0xf4, + Mul246 = 0xf5, + Mul247 = 0xf6, + Mul248 = 0xf7, + Mul249 = 0xf8, + Mul250 = 0xf9, + Mul251 = 0xfa, + Mul252 = 0xfb, + Mul253 = 0xfc, + Mul254 = 0xfd, + Mul255 = 0xfe, + Mul256 = 0xff, + Mul257 = 0x100, + Mul258 = 0x101, + Mul259 = 0x102, + Mul260 = 0x103, + Mul261 = 0x104, + Mul262 = 0x105, + Mul263 = 0x106, + Mul264 = 0x107, + Mul265 = 0x108, + Mul266 = 0x109, + Mul267 = 0x10a, + Mul268 = 0x10b, + Mul269 = 0x10c, + Mul270 = 0x10d, + Mul271 = 0x10e, + Mul272 = 0x10f, + Mul273 = 0x110, + Mul274 = 0x111, + Mul275 = 0x112, + Mul276 = 0x113, + Mul277 = 0x114, + Mul278 = 0x115, + Mul279 = 0x116, + Mul280 = 0x117, + Mul281 = 0x118, + Mul282 = 0x119, + Mul283 = 0x11a, + Mul284 = 0x11b, + Mul285 = 0x11c, + Mul286 = 0x11d, + Mul287 = 0x11e, + Mul288 = 0x11f, + Mul289 = 0x120, + Mul290 = 0x121, + Mul291 = 0x122, + Mul292 = 0x123, + Mul293 = 0x124, + Mul294 = 0x125, + Mul295 = 0x126, + Mul296 = 0x127, + Mul297 = 0x128, + Mul298 = 0x129, + Mul299 = 0x12a, + Mul300 = 0x12b, + Mul301 = 0x12c, + Mul302 = 0x12d, + Mul303 = 0x12e, + Mul304 = 0x12f, + Mul305 = 0x130, + Mul306 = 0x131, + Mul307 = 0x132, + Mul308 = 0x133, + Mul309 = 0x134, + Mul310 = 0x135, + Mul311 = 0x136, + Mul312 = 0x137, + Mul313 = 0x138, + Mul314 = 0x139, + Mul315 = 0x13a, + Mul316 = 0x13b, + Mul317 = 0x13c, + Mul318 = 0x13d, + Mul319 = 0x13e, + Mul320 = 0x13f, + Mul321 = 0x140, + Mul322 = 0x141, + Mul323 = 0x142, + Mul324 = 0x143, + Mul325 = 0x144, + Mul326 = 0x145, + Mul327 = 0x146, + Mul328 = 0x147, + Mul329 = 0x148, + Mul330 = 0x149, + Mul331 = 0x14a, + Mul332 = 0x14b, + Mul333 = 0x14c, + Mul334 = 0x14d, + Mul335 = 0x14e, + Mul336 = 0x14f, + Mul337 = 0x150, + Mul338 = 0x151, + Mul339 = 0x152, + Mul340 = 0x153, + Mul341 = 0x154, + Mul342 = 0x155, + Mul343 = 0x156, + Mul344 = 0x157, + Mul345 = 0x158, + Mul346 = 0x159, + Mul347 = 0x15a, + Mul348 = 0x15b, + Mul349 = 0x15c, + Mul350 = 0x15d, + Mul351 = 0x15e, + Mul352 = 0x15f, + Mul353 = 0x160, + Mul354 = 0x161, + Mul355 = 0x162, + Mul356 = 0x163, + Mul357 = 0x164, + Mul358 = 0x165, + Mul359 = 0x166, + Mul360 = 0x167, + Mul361 = 0x168, + Mul362 = 0x169, + Mul363 = 0x16a, + Mul364 = 0x16b, + Mul365 = 0x16c, + Mul366 = 0x16d, + Mul367 = 0x16e, + Mul368 = 0x16f, + Mul369 = 0x170, + Mul370 = 0x171, + Mul371 = 0x172, + Mul372 = 0x173, + Mul373 = 0x174, + Mul374 = 0x175, + Mul375 = 0x176, + Mul376 = 0x177, + Mul377 = 0x178, + Mul378 = 0x179, + Mul379 = 0x17a, + Mul380 = 0x17b, + Mul381 = 0x17c, + Mul382 = 0x17d, + Mul383 = 0x17e, + Mul384 = 0x17f, + Mul385 = 0x180, + Mul386 = 0x181, + Mul387 = 0x182, + Mul388 = 0x183, + Mul389 = 0x184, + Mul390 = 0x185, + Mul391 = 0x186, + Mul392 = 0x187, + Mul393 = 0x188, + Mul394 = 0x189, + Mul395 = 0x18a, + Mul396 = 0x18b, + Mul397 = 0x18c, + Mul398 = 0x18d, + Mul399 = 0x18e, + Mul400 = 0x18f, + Mul401 = 0x190, + Mul402 = 0x191, + Mul403 = 0x192, + Mul404 = 0x193, + Mul405 = 0x194, + Mul406 = 0x195, + Mul407 = 0x196, + Mul408 = 0x197, + Mul409 = 0x198, + Mul410 = 0x199, + Mul411 = 0x19a, + Mul412 = 0x19b, + Mul413 = 0x19c, + Mul414 = 0x19d, + Mul415 = 0x19e, + Mul416 = 0x19f, + Mul417 = 0x1a0, + Mul418 = 0x1a1, + Mul419 = 0x1a2, + Mul420 = 0x1a3, + _, + }; + + pub const PLLRGE = enum(u2) { + /// Frequency is between 1 and 2 MHz + Range1 = 0x0, + /// Frequency is between 2 and 4 MHz + Range2 = 0x1, + /// Frequency is between 4 and 8 MHz + Range4 = 0x2, + /// Frequency is between 8 and 16 MHz + Range8 = 0x3, + }; + + pub const PLLSRC = enum(u2) { + /// HSI selected as PLL clock + HSI = 0x0, + /// CSI selected as PLL clock + CSI = 0x1, + /// HSE selected as PLL clock + HSE = 0x2, + /// No clock sent to DIVMx dividers and PLLs + DISABLE = 0x3, + }; + + pub const PLLVCOSEL = enum(u1) { + /// VCOH selected (default after reset). + WideVCO = 0x0, + /// VCOL selected. + MediumVCO = 0x1, + }; + + pub const PPRE = enum(u3) { + /// rcc_hclk not divided + Div1 = 0x0, + /// rcc_hclk divided by 2 + Div2 = 0x4, + /// rcc_hclk divided by 4 + Div4 = 0x5, + /// rcc_hclk divided by 8 + Div8 = 0x6, + /// rcc_hclk divided by 16 + Div16 = 0x7, + _, + }; + + pub const PSSISEL = enum(u1) { + /// pll3_r_ck selected as kernel peripheral clock (default after reset). + PLL3_R = 0x0, + /// per_ck selected as kernel peripheral clock. + PER = 0x1, + }; + + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, + }; + + pub const SAI1SEL = enum(u3) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_p selected as peripheral clock + PLL3_P = 0x2, + /// I2S_CKIN selected as peripheral clock + I2S_CKIN = 0x3, + /// PER selected as peripheral clock + PER = 0x4, + _, + }; + + pub const SAI2SEL = enum(u3) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_p selected as peripheral clock + PLL2_P = 0x1, + /// pll3_p selected as peripheral clock + PLL3_P = 0x2, + /// I2S_CKIN selected as peripheral clock + I2S_CKIN = 0x3, + /// PER selected as peripheral clock + PER = 0x4, + /// spdifrx_symb_ck selected as SAI2 kernel clock. + SPDIFRX_SYMB = 0x5, + _, + }; + + pub const SDMMCSEL = enum(u1) { + /// pll2_s_ck selected as kernel peripheral clock (default after reset). + PLL2_S = 0x0, + /// pll2_t_ck selected as kernel peripheral clock. + PLL2_T = 0x1, + }; + + pub const SPDIFRXSEL = enum(u2) { + /// pll1_q selected as peripheral clock + PLL1_Q = 0x0, + /// pll2_r selected as peripheral clock + PLL2_R = 0x1, + /// pll3_r selected as peripheral clock + PLL3_R = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + }; + + pub const SPI123SEL = enum(u3) { + /// pll1_q_ck selected as SPI/I2S1 and 7 kernel clock (default after reset). + PLL1_Q = 0x0, + /// pll2_p_ck selected as SPI/I2S1 and 7 kernel clock. + PLL2_P = 0x1, + /// pll3_p_ck selected as SPI/I2S1 and 7 kernel clock. + PLL3_P = 0x2, + /// I2S_CKIN selected as SPI/I2S1 and 7 kernel clock. + I2S_CKIN = 0x3, + /// per_ck selected as SPI/I2S1,and 7 kernel clock. + PER = 0x4, + _, + }; + + pub const SPI45SEL = enum(u3) { + /// APB2 clock selected as peripheral clock + PCLK2 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// HSE selected as peripheral clock + HSE = 0x5, + _, + }; + + pub const SPI6SEL = enum(u3) { + /// rcc_pclk4 selected as peripheral clock + PCLK4 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// HSE selected as peripheral clock + HSE = 0x5, + _, + }; + + pub const STOPKERWUCK = enum(u1) { + /// HSI selected as wake up clock from system Stop (default after reset). + HSI = 0x0, + /// CSI selected as wake up clock from system Stop. + CSI = 0x1, + }; + + pub const STOPWUCK = enum(u1) { + /// HSI selected as wake up clock from system Stop + HSI = 0x0, + /// CSI selected as wake up clock from system Stop + CSI = 0x1, + }; + + pub const SW = enum(u3) { + /// HSI selected as system clock + HSI = 0x0, + /// CSI selected as system clock + CSI = 0x1, + /// HSE selected as system clock + HSE = 0x2, + /// PLL1 selected as system clock + PLL1_P = 0x3, + _, + }; + + pub const TIMPRE = enum(u1) { + /// Timer kernel clock equal to 2x pclk by default + DefaultX2 = 0x0, + /// Timer kernel clock equal to 4x pclk by default + DefaultX4 = 0x1, + }; + + pub const USART1SEL = enum(u3) { + /// rcc_pclk2 selected as peripheral clock + PCLK2 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, + }; + + pub const USART234578SEL = enum(u3) { + /// rcc_pclk1 selected as peripheral clock + PCLK1 = 0x0, + /// pll2_q selected as peripheral clock + PLL2_Q = 0x1, + /// pll3_q selected as peripheral clock + PLL3_Q = 0x2, + /// hsi_ker selected as peripheral clock + HSI = 0x3, + /// csi_ker selected as peripheral clock + CSI = 0x4, + /// LSE selected as peripheral clock + LSE = 0x5, + _, + }; + + pub const USBPDCTRL = enum(u1) { + /// In SUSPEND, PHY state machine, bias and USBPHYC PLL remain powered (default after reset). + RemainPowered = 0x0, + /// In SUSPEND, PHY state machine, bias and USBPHYC PLL are powered down. + PowerDown = 0x1, + }; + + pub const USBPHYCSEL = enum(u2) { + /// hse_ker_ck (default after reset). + HSE = 0x0, + /// hse_ker_ck / 2. + HSE_DIV_2 = 0x1, + /// pll3_q_ck. + PLL3_Q = 0x2, + _, + }; + + pub const USBREFCKSEL = enum(u4) { + /// The kernel clock frequency provided to the USBPHYC is 16 MHz. + Mhz16 = 0x3, + /// The kernel clock frequency provided to the USBPHYC is 19.2 MHz. + Mhz19_2 = 0x8, + /// The kernel clock frequency provided to the USBPHYC is 20MHz. + Mhz20 = 0x9, + /// The kernel clock frequency provided to the USBPHYC is 24 MHz (default after reset). + Mhz24 = 0xa, + /// The kernel clock frequency provided to the USBPHYC is 32 MHz. + Mhz32 = 0xb, + /// The kernel clock frequency provided to the USBPHYC is 26 MHz. + Mhz26 = 0xe, + _, + }; + + pub const USB_OTG_FSSEL = enum(u2) { + /// hsi48_ker_ck (default after reset). + HSI48 = 0x0, + /// pll3_q_ck. + PLL3_Q = 0x1, + /// hse_ker_ck. + HSE = 0x2, + /// clk48mohci. + CLK48MOHCI = 0x3, + }; + + pub const XSPISWP = enum(u3) { + /// The switch is in neutral mode and output clock is gated (default after reset). + B_0x0 = 0x0, + /// The switch is selecting hclk5. + B_0x1 = 0x1, + /// The switch is selecting pll2_s_ck. + B_0x2 = 0x2, + /// The switch is selecting pll2_t_ck. + B_0x3 = 0x3, + /// The switch is in recovery position (hclk5/4). + B_0x4 = 0x4, + _, + }; + + /// Reset and clock control. + pub const RCC = extern struct { + /// RCC source control register. + CR: mmio.Mmio(packed struct(u32) { + /// HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 0 or STOPKERWUCK = 0. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW switch) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1. + HSION: u1, + /// HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION. + HSIKERON: u1, + /// HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable. + HSIRDY: u1, + /// HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored. + HSIDIV: packed union { + raw: u2, + value: HSIDIV, + }, + /// HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. clock setting is completed). + HSIDIVF: u1, + reserved7: u1, + /// CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1. + CSION: u1, + /// CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request). + CSIRDY: u1, + /// CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION. + CSIKERON: u1, + reserved12: u2, + /// HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode. + HSI48ON: u1, + /// HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable. + HSI48RDY: u1, + reserved16: u2, + /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1. + HSEON: u1, + /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. + HSERDY: u1, + /// HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + HSEBYP: u1, + /// external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled. + HSEEXT: packed union { + raw: u1, + value: HSEEXT, + }, + /// HSE clock security system enable Set by software to enable clock security system on HSE. This bit is set only (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected. + HSECSSON: u1, + reserved24: u3, + /// PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3) or if FMCCKP = 1, or if XSPICKP = 1. + PLLON: u1, + /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + PLLRDY: u1, + padding: u6, + }), + /// RCC HSI calibration register. + HSICFGR: mmio.Mmio(packed struct(u32) { + /// HSI clock calibration Set by hardware by option byte loading. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value. + HSICAL: u12, + reserved24: u12, + /// HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_opt. Note: The reset value of the field is 0x40. + HSITRIM: u7, + padding: u1, + }), + /// RCC clock recovery RC register. + CRRCR: mmio.Mmio(packed struct(u32) { + /// Internal RC 48 MHz clock calibration Set by hardware by option byte loading. Read-only. + HSI48CAL: u10, + padding: u22, + }), + /// RCC CSI calibration register. + CSICFGR: mmio.Mmio(packed struct(u32) { + /// CSI clock calibration Set by hardware by option byte loading. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value. + CSICAL: u8, + reserved24: u16, + /// CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_opt) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_opt. Note: The reset value of the field is 0x20. + CSITRIM: u6, + padding: u2, + }), + /// RCC clock configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// system clock switch Set and reset by software to select system clock source (sys_ck). Set by hardware in order to force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode or in case of failure of the HSE when used directly or indirectly as system clock. others: reserved. + SW: packed union { + raw: u3, + value: SW, + }, + /// system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. others: reserved. + SWS: packed union { + raw: u3, + value: SW, + }, + /// system clock selection after a wake up from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details. STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10). + STOPWUCK: packed union { + raw: u1, + value: STOPWUCK, + }, + /// kernel clock selection after a wake up from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details. + STOPKERWUCK: packed union { + raw: u1, + value: STOPKERWUCK, + }, + /// HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ... + RTCPRE: u6, + reserved15: u1, + /// timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. or 4, else it is equal to 4 x Frcc_pclkx_d2 Refer to Table 64: Ratio between clock timer and pclk for more details. + TIMPRE: packed union { + raw: u1, + value: TIMPRE, + }, + reserved18: u2, + /// MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... + MCO1PRE: packed union { + raw: u4, + value: MCOPRE, + }, + /// Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved. + MCO1SEL: packed union { + raw: u3, + value: MCO1SEL, + }, + /// MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... + MCO2PRE: packed union { + raw: u4, + value: MCOPRE, + }, + /// microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved. + MCO2SEL: packed union { + raw: u3, + value: MCO2SEL, + }, + }), + reserved24: [4]u8, + /// RCC CPU domain clock configuration register. + CDCFGR: mmio.Mmio(packed struct(u32) { + /// CPU domain core prescaler Set and reset by software to control the CPU clock division factor. Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks. After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register. 0xxx: sys_ck not divided (default after reset). + CPRE: packed union { + raw: u4, + value: HPRE, + }, + padding: u28, + }), + /// RCC AHB clock configuration register. + BMCFGR: mmio.Mmio(packed struct(u32) { + /// Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk[5:1] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk[5:1] = rcc_aclk = sys_bus_ck. + BMPRE: packed union { + raw: u4, + value: HPRE, + }, + padding: u28, + }), + /// RCC APB clocks configuration register. + APBCFGR: mmio.Mmio(packed struct(u32) { + /// CPU domain APB1 prescaler Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE1 write. 0xx: rcc_pclk1 = sys_bus_ck (default after reset). + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + reserved4: u1, + /// CPU domain APB2 prescaler Set and reset by software to control the division factor of rcc_pclk2. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE2 write. 0xx: rcc_pclk2 = sys_bus_ck (default after reset). + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + reserved8: u1, + /// CPU domain APB4 prescaler Set and reset by software to control the division factor of rcc_pclk4. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE4 write. 0xx: rcc_pclk4 = sys_bus_ck (default after reset). + PPRE4: packed union { + raw: u3, + value: PPRE, + }, + reserved12: u1, + /// CPU domain APB5 prescaler Set and reset by software to control the division factor of rcc_pclk5. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE5 write. 0xx: rcc_pclk5 = sys_bus_ck (default after reset). + PPRE5: packed union { + raw: u3, + value: PPRE, + }, + padding: u17, + }), + reserved40: [4]u8, + /// RCC PLLs clock source selection register. + PLLCKSELR: mmio.Mmio(packed struct(u32) { + /// DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, PLLSRC must be set to 11. + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + reserved4: u2, + /// prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... + DIVM: packed union { + raw: u6, + value: PLLM, + }, + padding: u22, + }), + /// RCC PLLs configuration register. + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. + PLLFRACEN: u1, + /// PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref1_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref1_ck must be between 1 and 2 MHz). + PLLVCOSEL: packed union { + raw: u1, + value: PLLVCOSEL, + }, + /// PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks. + PLLSSCGEN: u1, + /// PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. + PLLRGE: packed union { + raw: u2, + value: PLLRGE, + }, + /// PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. + DIVPEN: u1, + /// PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. + DIVQEN: u1, + /// PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. + DIVREN: u1, + /// PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used. + DIVSEN: u1, + /// PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used. + DIVTEN: u1, + padding: u22, + }), + /// RCC PLL dividers configuration register 1. + PLLDIVR: mmio.Mmio(packed struct(u32) { + /// multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = PLL1RDY = 0). ..........: not used ... ... Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x DIVN1, when fractional value 0 has been loaded into FRACN, with: DIVN1 between 8 and 420 The input frequency Fref1_ck must be between 1 and 16 MHz. + PLLN: packed union { + raw: u9, + value: PLLN, + }, + /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1DIVPEN = 0. ... + PLLP: packed union { + raw: u7, + value: PLLDIV, + }, + /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1DIVQEN = 0. ... + PLLQ: packed union { + raw: u7, + value: PLLDIV, + }, + reserved24: u1, + /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1DIVREN = 0. ... + PLLR: packed union { + raw: u7, + value: PLLDIV, + }, + padding: u1, + }), + /// RCC PLL fractional divider register. + PLLFRACR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544 MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (DIVN1 + (FRACN / 213)), with DIVN1 between 8 and 420 FRACN can be between 0 and 213- 1 The input frequency Fref1_ck must be between 1 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACLE to 0. Write the new fractional value into FRACN. Set the bit PLL1FRACLE to 1. + FRACN: u13, + padding: u16, + }), + reserved76: [20]u8, + /// RCC AHB peripheral kernel clock selection register. + AHBPERCKSELR: mmio.Mmio(packed struct(u32) { + /// FMC kernel clock source selection Set and reset by software. + FMCSEL: packed union { + raw: u2, + value: FMCSEL, + }, + /// SDMMC1 and SDMMC2 kernel clock source selection Set and reset by software. + SDMMCSEL: packed union { + raw: u1, + value: SDMMCSEL, + }, + reserved4: u1, + /// XSPI1 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock. + OCTOSPI1SEL: packed union { + raw: u2, + value: OCTOSPISEL, + }, + /// XSPI2 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock. + OCTOSPI2SEL: packed union { + raw: u2, + value: OCTOSPISEL, + }, + /// USBPHYC kernel clock frequency selection Set and reset by software. This field is used to indicate to the USBPHYC, the frequency of the reference kernel clock provided to the USBPHYC. others: reserved. + USBREFCKSEL: packed union { + raw: u4, + value: USBREFCKSEL, + }, + /// USBPHYC kernel clock source selection Set and reset by software. + USBPHYCSEL: packed union { + raw: u2, + value: USBPHYCSEL, + }, + /// OTGFS kernel clock source selection Set and reset by software. + USB_OTG_FSSEL: packed union { + raw: u2, + value: USB_OTG_FSSEL, + }, + /// Ethernet reference clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. + ETH_REF_CLK_SEL: packed union { + raw: u2, + value: ETH_REF_CLK_SEL, + }, + /// Clock source selection for external Ethernet PHY Set and reset by software. + ETHPHY_CLK_SEL: packed union { + raw: u1, + value: ETHPHY_CLK_SEL, + }, + reserved20: u1, + /// ADF kernel clock source selection Set and reset by software. Note: I2S_CKIN is an external clock taken from a pin. + ADFSEL: packed union { + raw: u3, + value: ADFSEL, + }, + reserved24: u1, + /// SAR ADC kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, + reserved27: u1, + /// PSSI kernel clock source selection Set and reset by software. + PSSISEL: packed union { + raw: u1, + value: PSSISEL, + }, + /// per_ck clock source selection. + PERSEL: packed union { + raw: u2, + value: PERSEL, + }, + padding: u2, + }), + /// RCC APB1 peripherals kernel clock selection register. + APB1PERCKSELR: mmio.Mmio(packed struct(u32) { + /// USART2,3, UART4,5,7,8 (APB1) kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. + USART234578SEL: packed union { + raw: u3, + value: USART234578SEL, + }, + reserved4: u1, + /// SPI/I2S2 and SPI/I2S3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. + SPI23SEL: packed union { + raw: u3, + value: SPI123SEL, + }, + reserved8: u1, + /// I2C2, I2C3 kernel clock source selection Set and reset by software. + I2C23SEL: packed union { + raw: u2, + value: I2CSEL, + }, + reserved12: u2, + /// I2C1 or I3C1 kernel clock source selection Set and reset by software. + I2C1_I3C1SEL: packed union { + raw: u2, + value: I2C1_I3C1SEL, + }, + reserved16: u2, + /// LPTIM1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. + LPTIM1SEL: packed union { + raw: u3, + value: LPTIM1SEL, + }, + reserved22: u3, + /// FDCAN kernel clock source selection. + FDCANSEL: packed union { + raw: u2, + value: FDCANSEL, + }, + /// SPDIFRX kernel clock source selection. + SPDIFRXSEL: packed union { + raw: u2, + value: SPDIFRXSEL, + }, + reserved28: u2, + /// HDMI-CEC kernel clock source selection Set and reset by software. + CECSEL: packed union { + raw: u2, + value: CECSEL, + }, + padding: u2, + }), + /// RCC APB2 peripherals kernel clock selection register. + APB2PERCKSELR: mmio.Mmio(packed struct(u32) { + /// USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. + USART1SEL: packed union { + raw: u3, + value: USART1SEL, + }, + reserved4: u1, + /// SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. + SPI45SEL: packed union { + raw: u3, + value: SPI45SEL, + }, + reserved8: u1, + /// SPI/I2S1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. + SPI1SEL: packed union { + raw: u3, + value: SPI123SEL, + }, + reserved16: u5, + /// SAI1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. + SAI1SEL: packed union { + raw: u3, + value: SAI1SEL, + }, + reserved20: u1, + /// SAI2 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see Figure 51). + SAI2SEL: packed union { + raw: u3, + value: SAI2SEL, + }, + padding: u9, + }), + /// RCC APB4,5 peripherals kernel clock selection register. + APB45PERCKSELR: mmio.Mmio(packed struct(u32) { + /// LPUART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. + LPUART1SEL: packed union { + raw: u3, + value: LPUARTSEL, + }, + reserved4: u1, + /// SPI/I2S6 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. + SPI6SEL: packed union { + raw: u3, + value: SPI6SEL, + }, + reserved8: u1, + /// LPTIM2 and LPTIM3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. + LPTIM23SEL: packed union { + raw: u3, + value: LPTIMSEL, + }, + reserved12: u1, + /// LPTIM4, and LPTIM5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled. + LPTIM45SEL: packed union { + raw: u3, + value: LPTIMSEL, + }, + padding: u17, + }), + reserved96: [4]u8, + /// RCC clock source interrupt enable register. + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization. + LSIRDYIE: u1, + /// LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization. + LSERDYIE: u1, + /// HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization. + HSIRDYIE: u1, + /// HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization. + HSERDYIE: u1, + /// CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization. + CSIRDYIE: u1, + /// HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. + HSI48RDYIE: u1, + /// PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. + PLLRDYIE: u1, + reserved9: u2, + /// LSE clock security system interrupt enable Set and reset by software to enable/disable interrupt caused by the clock security system (CSS) on external 32 kHz oscillator. + LSECSSIE: u1, + padding: u22, + }), + /// RCC clock source interrupt flag register. + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. + LSIRDYF: u1, + /// LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set. + LSERDYF: u1, + /// HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set. + HSIRDYF: u1, + /// HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. + HSERDYF: u1, + /// CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set. + CSIRDYF: u1, + /// HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. + HSI48RDYF: u1, + /// PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + PLLRDYF: u1, + reserved9: u2, + /// LSE clock security system interrupt flag Reset by software by writing LSECSSC bit. Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set. + LSECSSF: u1, + /// HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. + HSECSSF: u1, + padding: u21, + }), + /// RCC clock source interrupt clear register. + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done. + LSIRDYC: u1, + /// LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done. + LSERDYC: u1, + /// HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done. + HSIRDYC: u1, + /// HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done. + HSERDYC: u1, + /// CSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done. + CSIRDYC: u1, + /// HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. + HSI48RDYC: u1, + /// PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + PLLRDYC: u1, + reserved9: u2, + /// LSE clock security system interrupt clear Set by software to clear LSECSSF. Reset by hardware when clear done. + LSECSSC: u1, + /// HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done. + HSECSSC: u1, + padding: u21, + }), + reserved112: [4]u8, + /// RCC Backup domain control register. + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enabled Set and reset by software. + LSEON: u1, + /// LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0. + LSERDY: u1, + /// LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1). + LSEBYP: u1, + /// LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit can only be disabled, After a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON. After a back-up domain reset. + LSECSSON: u1, + /// LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator. + LSECSSD: u1, + /// low-speed external clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled. + LSEEXT: u1, + /// RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST). + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved12: u2, + /// Re-Arm the LSECSS function Set by software. After a LSE failure detection, the software application can re-enable the LSECSS by writing this bit to 1. Reading this bit returns the written value. Prior to set this bit to 1, LSECSSON must be set to 0. Please refer to Section : CSS on LSE for details. + LSECSSRA: u1, + reserved15: u2, + /// RTC clock enable Set and reset by software. + RTCEN: u1, + /// VSwitch domain software reset Set and reset by software. To generate a VSW reset, it is recommended to write this bit to 1, then back to 0. + VSWRST: u1, + padding: u15, + }), + /// RCC clock control and status register. + CSR: mmio.Mmio(packed struct(u32) { + /// LSI oscillator enable Set and reset by software. + LSION: u1, + /// LSI oscillator ready Set and reset by hardware to indicate when the low-speed internal RC oscillator is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to 0. This bit can be set even when LSION is not enabled if there is a request for LSI clock by the clock security system on LSE or by the low-speed watchdog or by the RTC. + LSIRDY: u1, + padding: u30, + }), + reserved124: [4]u8, + /// RCC AHB5 peripheral reset register. + AHB5RSTR: mmio.Mmio(packed struct(u32) { + /// HPDMA1 block reset Set and reset by software. + HPDMA1RST: u1, + /// DMA2D block reset Set and reset by software. + DMA2DRST: u1, + reserved3: u1, + /// JPEG block reset Set and reset by software. + JPEGRST: u1, + /// FMC and MCE3 blocks reset Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. + FMCRST: u1, + /// XSPI1 and MCE1 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. + XSPI1RST: u1, + reserved8: u2, + /// SDMMC1 and DB_SDMMC1 blocks reset Set and reset by software. + SDMMC1RST: u1, + reserved12: u3, + /// XSPI2 and MCE2 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. + XSPI2RST: u1, + reserved14: u1, + /// XSPIM reset Set and reset by software. + IOMNGRRST: u1, + reserved19: u4, + /// GFXMMU block reset Set and reset by software. + GFXMMURST: u1, + /// GPU block reset Set and reset by software. + GPURST: u1, + padding: u11, + }), + /// RCC AHB1 peripheral reset register. + AHB1RSTR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// GPDMA1 blocks reset Set and reset by software. + GPDMA1RST: u1, + /// ADC1 and 2 blocks reset Set and reset by software. + ADC12RST: u1, + reserved15: u9, + /// ETH1 block reset Set and reset by software. + ETHRST: u1, + reserved25: u9, + /// OTGHS block reset Set and reset by software. + USB_OTG_HSRST: u1, + /// USBPHYC block reset Set and reset by software. + USBPHYCRST: u1, + /// OTGFS block reset Set and reset by software. + USB_OTG_FSRST: u1, + reserved31: u3, + /// ADF block reset Set and reset by software. + ADFRST: u1, + }), + /// RCC AHB2 peripheral reset register. + AHB2RSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PSSI block reset Set and reset by software. + PSSIRST: u1, + reserved9: u7, + /// SDMMC2 and SDMMC2 delay blocks reset Set and reset by software. + SDMMC2RST: u1, + reserved14: u4, + /// CORDIC reset Set and reset by software. + CORDICRST: u1, + padding: u17, + }), + /// RCC AHB4 peripheral reset register. + AHB4RSTR: mmio.Mmio(packed struct(u32) { + /// GPIOA block reset Set and reset by software. + GPIOARST: u1, + /// GPIOB block reset Set and reset by software. + GPIOBRST: u1, + /// GPIOC block reset Set and reset by software. + GPIOCRST: u1, + /// GPIOD block reset Set and reset by software. + GPIODRST: u1, + /// GPIOE block reset Set and reset by software. + GPIOERST: u1, + /// GPIOF block reset Set and reset by software. + GPIOFRST: u1, + /// GPIOG block reset Set and reset by software. + GPIOGRST: u1, + /// GPIOH block reset Set and reset by software. + GPIOHRST: u1, + reserved12: u4, + /// GPIOM block reset Set and reset by software. + GPIOMRST: u1, + /// GPION block reset Set and reset by software. + GPIONRST: u1, + /// GPIOO block reset Set and reset by software. + GPIOORST: u1, + /// GPIOP block reset Set and reset by software. + GPIOPRST: u1, + reserved19: u3, + /// CRC block reset Set and reset by software. + CRCRST: u1, + padding: u12, + }), + /// RCC APB5 peripheral reset register. + APB5RSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// LTDC block reset Set and reset by software. + LTDCRST: u1, + /// DCMIPP block reset Set and reset by software. + DCMIPPRST: u1, + reserved4: u1, + /// GFXTIM block reset Set and reset by software. + GFXTIMRST: u1, + padding: u27, + }), + /// RCC APB1 peripheral reset register 1. + APB1RSTR1: mmio.Mmio(packed struct(u32) { + /// TIM2 block reset Set and reset by software. + TIM2RST: u1, + /// TIM3 block reset Set and reset by software. + TIM3RST: u1, + /// TIM4 block reset Set and reset by software. + TIM4RST: u1, + /// TIM5 block reset Set and reset by software. + TIM5RST: u1, + /// TIM6 block reset Set and reset by software. + TIM6RST: u1, + /// TIM7 block reset Set and reset by software. + TIM7RST: u1, + /// TIM12 block reset Set and reset by software. + TIM12RST: u1, + /// TIM13 block reset Set and reset by software. + TIM13RST: u1, + /// TIM14 block reset Set and reset by software. + TIM14RST: u1, + /// LPTIM1 block reset Set and reset by software. + LPTIM1RST: u1, + reserved14: u4, + /// SPI2S2 block reset Set and reset by software. + SPI2RST: u1, + /// SPI2S3 block reset Set and reset by software. + SPI3RST: u1, + /// SPDIFRX block reset Set and reset by software. + SPDIFRXRST: u1, + /// USART2 block reset Set and reset by software. + USART2RST: u1, + /// USART3 block reset Set and reset by software. + USART3RST: u1, + /// UART4 block reset Set and reset by software. + UART4RST: u1, + /// UART5 block reset Set and reset by software. + UART5RST: u1, + /// I2C1/I3C1 block reset Set and reset by software. + I2C1_I3C1RST: u1, + /// I2C2 block reset Set and reset by software. + I2C2RST: u1, + /// I2C3 block reset Set and reset by software. + I2C3RST: u1, + reserved27: u3, + /// HDMI-CEC block reset Set and reset by software. + CECRST: u1, + reserved30: u2, + /// UART7 block reset Set and reset by software. + UART7RST: u1, + /// UART8 block reset Set and reset by software. + UART8RST: u1, + }), + /// RCC APB1 peripheral reset register 2. + APB1RSTR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// clock recovery system reset Set and reset by software. + CRSRST: u1, + reserved5: u3, + /// MDIOS block reset Set and reset by software. + MDIOSRST: u1, + reserved8: u2, + /// FDCAN block reset Set and reset by software. + FDCANRST: u1, + reserved27: u18, + /// UCPD block reset Set and reset by software. + UCPDRST: u1, + padding: u4, + }), + /// RCC APB2 peripheral reset register. + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// TIM1 block reset Set and reset by software. + TIM1RST: u1, + reserved4: u3, + /// USART1 block reset Set and reset by software. + USART1RST: u1, + reserved12: u7, + /// SPI2S1 block reset Set and reset by software. + SPI1RST: u1, + /// SPI4 block reset Set and reset by software. + SPI4RST: u1, + reserved16: u2, + /// TIM15 block reset Set and reset by software. + TIM15RST: u1, + /// TIM16 block reset Set and reset by software. + TIM16RST: u1, + /// TIM17 block reset Set and reset by software. + TIM17RST: u1, + /// TIM9 block reset Set and reset by software. + TIM9RST: u1, + /// SPI5 block reset Set and reset by software. + SPI5RST: u1, + reserved22: u1, + /// SAI1 block reset Set and reset by software. + SAI1RST: u1, + /// SAI2 block reset Set and reset by software. + SAI2RST: u1, + padding: u8, + }), + /// RCC APB4 peripheral reset register. + APB4RSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SBS block reset Set and reset by software. + SYSCFGRST: u1, + reserved3: u1, + /// LPUART1 block reset Set and reset by software. + LPUART1RST: u1, + reserved5: u1, + /// SPI/I2S6 block reset Set and reset by software. + SPI6RST: u1, + reserved9: u3, + /// LPTIM2 block reset Set and reset by software. + LPTIM2RST: u1, + /// LPTIM3 block reset Set and reset by software. + LPTIM3RST: u1, + /// LPTIM4 block reset Set and reset by software. + LPTIM4RST: u1, + /// LPTIM5 block reset Set and reset by software. + LPTIM5RST: u1, + reserved15: u2, + /// VREF block reset Set and reset by software. + VREFRST: u1, + reserved26: u10, + /// TMPSENS block reset Set and reset by software. + TMPSENSRST: u1, + padding: u5, + }), + reserved164: [4]u8, + /// RCC AHB3 peripheral reset register. + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// random number generator block reset Set and reset by software. + RNGRST: u1, + /// HASH block reset Set and reset by software. + HASHRST: u1, + /// CRYP block reset Set and reset by software. + CRYPRST: u1, + reserved4: u1, + /// SAES block reset Set and reset by software. + SAESRST: u1, + reserved6: u1, + /// PKA block reset Set and reset by software. + PKARST: u1, + padding: u25, + }), + reserved176: [8]u8, + /// RCC AXI clocks gating disable register. + CKGDISR: mmio.Mmio(packed struct(u32) { + /// AXI interconnect matrix clock gating disable This bit is set and reset by software. + AXICKG: u1, + /// AXI master AHB clock gating disable This bit is set and reset by software. + AHBMCKG: u1, + /// AXI master SDMMC1 clock gating disable This bit is set and reset by software. + SDMMC1CKG: u1, + /// AXI master HPDMA1 clock gating disable This bit is set and reset by software. + HPDMA1CKG: u1, + /// AXI master CPU clock gating disable This bit is set and reset by software. + CPUCKG: u1, + /// AXI master 0 GPU clock gating disable This bit is set and reset by software. + GPUS0CKG: u1, + /// AXI master 1 GPU clock gating disable This bit is set and reset by software. + GPUS1CKG: u1, + /// AXI master cache GPU clock gating disable This bit is set and reset by software. + GPUCLCKG: u1, + /// AXI master DCMIPP clock gating disable This bit is set and reset by software. + DCMIPPCKG: u1, + /// AXI master DMA2D clock gating disable This bit is set and reset by software. + DMA2DCKG: u1, + /// AXI matrix slave GFXMMU clock gating disable This bit is set and reset by software. + GFXMMUSCKG: u1, + /// AXI master LTDC clock gating disable This bit is set and reset by software. + LTDCCKG: u1, + /// AXI master GFXMMU clock gating disable This bit is set and reset by software. + GFXMMUMCKG: u1, + /// AXI slave AHB clock gating disable This bit is set and reset by software. + AHBSCKG: u1, + /// AXI slave FMC and MCE3 clock gating disable This bit is set and reset by software. + FMCCKG: u1, + /// AXI slave XSPI1 and MCE1 clock gating disable This bit is set and reset by software. + XSPI1CKG: u1, + /// AXI slave XSPI2 and MCE2 clock gating disable This bit is set and reset by software. + XSPI2CKG: u1, + /// AXI matrix slave SRAM4 clock gating disable This bit is set and reset by software. + AXIRAM4CKG: u1, + /// AXI matrix slave SRAM3 clock gating disable This bit is set and reset by software. + AXIRAM3CKG: u1, + /// AXI slave SRAM2 clock gating disable This bit is set and reset by software. + AXIRAM2CKG: u1, + /// AXI slave SRAM1 / error code correction (ECC) clock gating disable This bit is set and reset by software. + AXIRAM1CKG: u1, + /// AXI slave Flash interface (FLIFT) clock gating disable This bit is set and reset by software. + FLITFCKG: u1, + reserved30: u8, + /// EXTI clock gating disable This bit is set and reset by software. + EXTICKG: u1, + /// JTAG automatic clock gating disabling This bit is set and reset by software. + JTAGCKG: u1, + }), + reserved192: [12]u8, + /// RCC PLL dividers configuration register 2. + PLLDIVR2: [3]mmio.Mmio(packed struct(u32) { + /// PLL1 DIVS division factor Set and reset by software to control the frequency of the pll1_s_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVS+1) is even, With VCOH, for all DIVS values These bits can be written only when the PLL1DIVSEN = 0. + PLLS: packed union { + raw: u3, + value: PLLDIVST, + }, + reserved8: u5, + /// PLL1 DIVT division factor Set and reset by software to control the frequency of the pll1_t_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVT+1) is even, With VCOH, for all DIVT values These bits can be written only when the PLL1DIVTEN = 0. + PLLT: packed union { + raw: u3, + value: PLLDIVST, + }, + padding: u21, + }), + /// RCC PLL Spread Spectrum Clock Generator register. + PLLSSCGR: [3]mmio.Mmio(packed struct(u32) { + /// Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator. + MOD_PER: u13, + /// Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function. + TPDFN_DIS1: u1, + /// Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function. + RPDFN_DIS1: u1, + /// Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode. + DWNSPREAD1: packed union { + raw: u1, + value: DWNSPREAD, + }, + /// Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator. + INC_STEP: u15, + padding: u1, + }), + reserved256: [40]u8, + /// RCC clock protection register. + CKPROTR: mmio.Mmio(packed struct(u32) { + /// XSPI clock protection Set and cleared by software. When set to 1, this bit prevents disabling accidentally the XSPIs. The following fields cannot be modified when this bit is set to 1: PLL2ON, PLL2DIVSEN, PLL2DIVTEN, HSEON, HSION, CSION, XSPIxEN, OCTOSPIxLPEN, OCTOSPIxRST. + XSPICKP: u1, + /// FMC clock protection Set and cleared by software. When set to 1, this bit prevents disabling accidentally the FMC. The following fields cannot be modified when this bit is set to 1: PLL1ON, PLL2ON, PLL1DIVQEN, PLL2DIVREN, HSEON, HSION, CSION, FMCEN, FMCLPEN, FMCRST. + FMCCKP: u1, + reserved4: u2, + /// XSPI1 kernel clock switch position Set by hardware. This field can be used to verify the real position of XSPI2 kernel switch selector. + XSPI1SWP: packed union { + raw: u3, + value: XSPISWP, + }, + reserved8: u1, + /// XSPI2 kernel clock switch position Set by hardware. This field can be used to verify the real position of XSPI2 kernel switch selector. + XSPI2SWP: packed union { + raw: u3, + value: XSPISWP, + }, + reserved12: u1, + /// FMC kernel clock switch position Set by hardware. This field can be used to verify the real position of FMC kernel switch selector. + FMCSWP: packed union { + raw: u3, + value: FMCSWP, + }, + padding: u17, + }), + reserved304: [44]u8, + /// RCC Reset status register. + RSR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// remove reset flag Set and reset by software to reset the value of the reset flags. + RMVF: u1, + /// Option byte loading reset flag (1) Reset by software by the RMVF bit. Set by hardware when a reset from the option byte loading occurs. + OBLRSTF: u1, + reserved21: u3, + /// BOR reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). + BORRSTF: u1, + /// pin reset flag (NRST) (1) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. + PINRSTF: u1, + /// POR/PDR reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs. + PORRSTF: u1, + /// system reset from CPU reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7. + SFTRSTF: u1, + reserved26: u1, + /// independent watchdog reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. + IWDGRSTF: u1, + reserved28: u1, + /// window watchdog reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. + WWDGRSTF: u1, + reserved30: u1, + /// reset due to illegal Stop or Standby flag Reset by software by writing the RMVF bit. Set by hardware when the CPU goes erroneously in Stop or Standby mode,. + LPWRRSTF: u1, + padding: u1, + }), + /// RCC AHB5 clock enable register. + AHB5ENR: mmio.Mmio(packed struct(u32) { + /// HPDMA1 peripheral clock enable Set and reset by software. + HPDMA1EN: u1, + /// DMA2D peripheral clock enable Set and reset by software. + DMA2DEN: u1, + reserved3: u1, + /// JPEG peripheral clock enable Set and reset by software. + JPEGEN: u1, + /// FMC and MCE3 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock. + FMCEN: u1, + /// XSPI1 and MCE1 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. + XSPI1EN: u1, + reserved8: u2, + /// SDMMC1 and DB_SDMMC1 peripheral clocks enable Set and reset by software. + SDMMC1EN: u1, + reserved12: u3, + /// XSPI2 and MCE2 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. + XSPI2EN: u1, + reserved14: u1, + /// XSPIM peripheral clock enable Set and reset by software. + IOMNGREN: u1, + reserved19: u4, + /// GFXMMU peripheral clock enable Set and reset by software. + GFXMMUEN: u1, + /// GPU peripheral clock enable Set and reset by software. + GPUEN: u1, + padding: u11, + }), + /// RCC AHB1 clock enable register. + AHB1ENR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// GPDMA1 clock enable Set and reset by software. + GPDMA1EN: u1, + /// ADC1 and 2 peripheral clocks enable Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the hclk1 bus interface clock. + ADC12EN: u1, + reserved15: u9, + /// ETH1 MAC peripheral clock enable Set and reset by software. + ETHEN: u1, + /// ETH1 transmission clock enable Set and reset by software. + ETHTXEN: u1, + /// ETH1 reception clock enable Set and reset by software. + ETHRXEN: u1, + reserved25: u7, + /// OTGHS clocks enable Set and reset by software. + USB_OTG_HSEN: u1, + /// USBPHYC clocks enable Set and reset by software. + USBPHYCEN: u1, + /// OTGFS peripheral clocks enable Set and reset by software. + USB_OTG_FSEN: u1, + reserved31: u3, + /// ADF clocks enable Set and reset by software. + ADFEN: u1, + }), + /// RCC AHB2 clock enable register. + AHB2ENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PSSI peripheral clocks enable Set and reset by software. + PSSIEN: u1, + reserved9: u7, + /// SDMMC2 and SDMMC2 delay clock enable Set and reset by software. + SDMMC2EN: u1, + reserved14: u4, + /// CORDIC clock enable Set and reset by software. + CORDICEN: u1, + reserved29: u14, + /// SRAM1 clock enable Set and reset by software. + SRAM1EN: u1, + /// SRAM2 clock enable Set and reset by software. + SRAM2EN: u1, + padding: u1, + }), + /// RCC AHB4 clock enable register. + AHB4ENR: mmio.Mmio(packed struct(u32) { + /// GPIOA peripheral clock enable Set and reset by software. + GPIOAEN: u1, + /// GPIOB peripheral clock enable Set and reset by software. + GPIOBEN: u1, + /// GPIOC peripheral clock enable Set and reset by software. + GPIOCEN: u1, + /// GPIOD peripheral clock enable Set and reset by software. + GPIODEN: u1, + /// GPIOE peripheral clock enable Set and reset by software. + GPIOEEN: u1, + /// GPIOF peripheral clock enable Set and reset by software. + GPIOFEN: u1, + /// GPIOG peripheral clock enable Set and reset by software. + GPIOGEN: u1, + /// GPIOH peripheral clock enable Set and reset by software. + GPIOHEN: u1, + reserved12: u4, + /// GPIOM peripheral clock enable Set and reset by software. + GPIOMEN: u1, + /// GPION peripheral clock enable Set and reset by software. + GPIONEN: u1, + /// GPIOO peripheral clock enable Set and reset by software. + GPIOOEN: u1, + /// GPIOP peripheral clock enable Set and reset by software. + GPIOPEN: u1, + reserved19: u3, + /// CRC clock enable Set and reset by software. + CRCEN: u1, + reserved28: u8, + /// Backup RAM clock enable Set and reset by software. + BKPRAMEN: u1, + padding: u3, + }), + /// RCC APB5 clock enable register. + APB5ENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// LTDC peripheral clock enable Provides the pixel clock (ltdc_clk) to the LTDC block. Set and reset by software. + LTDCEN: u1, + /// DCMIPP peripheral clock enable Set and reset by software. + DCMIPPEN: u1, + reserved4: u1, + /// GFXTIM peripheral clock enable Set and reset by software. + GFXTIMEN: u1, + padding: u27, + }), + /// RCC APB1 clock enable register 1. + APB1ENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 peripheral clock enable Set and reset by software. + TIM2EN: u1, + /// TIM3 peripheral clock enable Set and reset by software. + TIM3EN: u1, + /// TIM4 peripheral clock enable Set and reset by software. + TIM4EN: u1, + /// TIM5 peripheral clock enable Set and reset by software. + TIM5EN: u1, + /// TIM6 peripheral clock enable Set and reset by software. + TIM6EN: u1, + /// TIM7 peripheral clock enable Set and reset by software. + TIM7EN: u1, + /// TIM12 peripheral clock enable Set and reset by software. + TIM12EN: u1, + /// TIM13 peripheral clock enable Set and reset by software. + TIM13EN: u1, + /// TIM14 peripheral clock enable Set and reset by software. + TIM14EN: u1, + /// LPTIM1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to clk_lpt input, and the rcc_pclk1 bus interface clock. + LPTIM1EN: u1, + reserved11: u1, + /// WWDG clock enable Set by software, and reset by hardware when a system reset occurs. + WWDGEN: u1, + reserved14: u2, + /// SPI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock. + SPI2EN: u1, + /// SPI3 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock. + SPI3EN: u1, + /// SPDIFRX peripheral clocks enable Set and reset by software. The peripheral clocks of the SPDIFRX are the kernel clock selected by SPDIFRXSEL and provided to SPDIFRX_CLK input, and the rcc_pclk1 bus interface clock. + SPDIFRXEN: u1, + /// USART2peripheral clocks enable Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. + USART2EN: u1, + /// USART3 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. + USART3EN: u1, + /// UART4 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. + UART4EN: u1, + /// UART5 peripheral clocks enable Set and reset by software. + UART5EN: u1, + /// I2C1/I3C1 peripheral clocks enable Set and reset by software. + I2C1_I3C1EN: u1, + /// I2C2 peripheral clocks enable Set and reset by software. + I2C2EN: u1, + /// I2C3 peripheral clocks enable Set and reset by software. + I2C3EN: u1, + reserved27: u3, + /// HDMI-CEC peripheral clock enable Set and reset by software. + CECEN: u1, + reserved30: u2, + /// UART7 peripheral clocks enable Set and reset by software. + UART7EN: u1, + /// UART8 peripheral clocks enable Set and reset by software. + UART8EN: u1, + }), + /// RCC APB1 clock enable register 2. + APB1ENR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// clock recovery system peripheral clock enable Set and reset by software. + CRSEN: u1, + reserved5: u3, + /// MDIOS peripheral clock enable Set and reset by software. + MDIOSEN: u1, + reserved8: u2, + /// FDCAN peripheral clock enable Set and reset by software. + FDCANEN: u1, + reserved27: u18, + /// UCPD peripheral clock enable Set and reset by software. + UCPDEN: u1, + padding: u4, + }), + /// RCC APB2 clock enable register. + APB2ENR: mmio.Mmio(packed struct(u32) { + /// TIM1 peripheral clock enable Set and reset by software. + TIM1EN: u1, + reserved4: u3, + /// USART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART1SEL, and the pclk2 bus interface clock. + USART1EN: u1, + reserved12: u7, + /// SPI2S1 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI2S1 are: the kernel clock selected by SPI1SEL, and the pclk2 bus interface clock. + SPI1EN: u1, + /// SPI4 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL, and the pclk2 bus interface clock. + SPI4EN: u1, + reserved16: u2, + /// TIM15 peripheral clock enable Set and reset by software. + TIM15EN: u1, + /// TIM16 peripheral clock enable Set and reset by software. + TIM16EN: u1, + /// TIM17 peripheral clock enable Set and reset by software. + TIM17EN: u1, + /// TIM9 peripheral clock enable Set and reset by software. + TIM9EN: u1, + /// SPI5 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL, and the pclk2 bus interface clock. + SPI5EN: u1, + reserved22: u1, + /// SAI1 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI1 are the kernel clock selected by SAI1SEL, and the pclk2 bus interface clock. + SAI1EN: u1, + /// SAI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI2 are the kernel clock selected by SAI2SEL, and the pclk2 bus interface clock. + SAI2EN: u1, + padding: u8, + }), + /// RCC APB4 clock enable register. + APB4ENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SBS peripheral clock enable Set and reset by software. + SYSCFGEN: u1, + reserved3: u1, + /// LPUART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the pclk4 bus interface clock. + LPUART1EN: u1, + reserved5: u1, + /// SPI/I2S6 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_clk input, and the pclk4 bus interface clock. + SPI6EN: u1, + reserved9: u3, + /// LPTIM2 peripheral clocks enable Set and reset by software. The LPTIM2 kernel clock can be selected by LPTIM23SEL. + LPTIM2EN: u1, + /// LPTIM3 peripheral clocks enable Set and reset by software. The LPTIM3 kernel clock can be selected by LPTIM23SEL. + LPTIM3EN: u1, + /// LPTIM4 peripheral clocks enable Set and reset by software. The LPTIM4 kernel clock can be selected by LPTIM45SEL. + LPTIM4EN: u1, + /// LPTIM5 peripheral clocks enable Set and reset by software. The LPTIM5 kernel clock can be selected by LPTIM45SEL. + LPTIM5EN: u1, + reserved15: u2, + /// VREF peripheral clock enable Set and reset by software. + VREFEN: u1, + /// RTC APB clock enable Set and reset by software. + RTCAPBEN: u1, + reserved26: u9, + /// Temperature Sensor peripheral clock enable Set and reset by software. + TMPSENSEN: u1, + padding: u5, + }), + /// RCC AHB3 clock enable register. + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// RNG peripheral clocks enable Set and reset by software. + RNGEN: u1, + /// HASH peripheral clock enable Set and reset by software. + HASHEN: u1, + /// CRYP peripheral clock enable Set and reset by software. + CRYPEN: u1, + reserved4: u1, + /// SAES peripheral clock enable Set and reset by software. This bit controls the enable of the clock delivered to the SAES. + SAESEN: u1, + reserved6: u1, + /// PKA peripheral clock enable Set and reset by software. + PKAEN: u1, + padding: u25, + }), + /// RCC AHB5 low-power clock enable register. + AHB5LPENR: mmio.Mmio(packed struct(u32) { + /// HPDMA1 low-power peripheral clock enable Set and reset by software. + HPDMA1LPEN: u1, + /// DMA2D low-power peripheral clock enable Set and reset by software. + DMA2DLPEN: u1, + /// FLITF low-power peripheral clock enable Set and reset by software. + FLITFLPEN: u1, + /// JPEG clock enable during Sleep mode Set and reset by software. + JPEGLPEN: u1, + /// FMC and MCE3 peripheral clocks enable during Sleep mode Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock. + FMCLPEN: u1, + /// XSPI1 and MCE1 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. + XSPI1LPEN: u1, + reserved8: u2, + /// SDMMC1 and SDMMC1 delay low-power peripheral clock enable Set and reset by software. + SDMMC1LPEN: u1, + reserved12: u3, + /// XSPI2 and MCE2 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. + XSPI2LPEN: u1, + reserved14: u1, + /// XSPIM low-power peripheral clock enable Set and reset by software. + XSPIMLPEN: u1, + reserved19: u4, + /// GFXMMU low-power peripheral clock enable Set and reset by software. + GFXMMULPEN: u1, + /// GPU low-power peripheral clock enable Set and reset by software. + GPULPEN: u1, + reserved28: u7, + /// DTCM1 low-power peripheral clock enable Set and reset by software. + DTCM1LPEN: u1, + /// DTCM2 low-power peripheral clock enable Set and reset by software. + DTCM2LPEN: u1, + /// ITCM low-power peripheral clock enable Set and reset by software. + ITCMLPEN: u1, + /// AXISRAM[4:1] low-power peripheral clock enable Set and reset by software. + AXISRAMLPEN: u1, + }), + /// RCC AHB1 low-power clock enable register. + AHB1LPENR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// GPDMA1 clock enable in low-power mode Set and reset by software. + GPDMA1LPEN: u1, + /// ADC1 and 2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the rcc_hclk1 bus interface clock. + ADC12LPEN: u1, + reserved15: u9, + /// ETH1 MAC peripheral clock enable in low-power mode Set and reset by software. + ETHLPEN: u1, + /// ETH1 transmission peripheral clock enable in low-power mode Set and reset by software. + ETHTXLPEN: u1, + /// ETH1 reception peripheral clock enable in low-power mode Set and reset by software. + ETHRXLPEN: u1, + reserved24: u6, + /// USBPHYC common block power-down control Set and reset by software. + USBPDCTRL: packed union { + raw: u1, + value: USBPDCTRL, + }, + /// OTGHS peripheral clock enable in low-power mode Set and reset by software. + USB_OTG_HSLPEN: u1, + /// USBPHYC peripheral clock enable in low-power mode Set and reset by software. + USBPHYCLPEN: u1, + /// OTGFS clock enable in low-power mode Set and reset by software. + USB_OTG_FSLPEN: u1, + reserved31: u3, + /// ADF clock enable in low-power mode Set and reset by software. + ADFLPEN: u1, + }), + /// RCC AHB2 low-power clock enable register. + AHB2LPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PSSI peripheral clock enable in low-power mode Set and reset by software. + PSSILPEN: u1, + reserved9: u7, + /// SDMMC2 and SDMMC2 delay clock enable in low-power mode Set and reset by software. + SDMMC2LPEN: u1, + reserved14: u4, + /// CORDIC clock enable in low-power mode Set and reset by software. + CORDICLPEN: u1, + reserved29: u14, + /// SRAM1 clock enable in low-power mode Set and reset by software. + SRAM1LPEN: u1, + /// SRAM2 clock enable in low-power mode Set and reset by software. + SRAM2LPEN: u1, + padding: u1, + }), + /// RCC AHB4 low-power clock enable register. + AHB4LPENR: mmio.Mmio(packed struct(u32) { + /// GPIOA peripheral clock enable in low-power mode Set and reset by software. + GPIOALPEN: u1, + /// GPIOB peripheral clock enable in low-power mode Set and reset by software. + GPIOBLPEN: u1, + /// GPIOC peripheral clock enable in low-power mode Set and reset by software. + GPIOCLPEN: u1, + /// GPIOD peripheral clock enable in low-power mode Set and reset by software. + GPIODLPEN: u1, + /// GPIOE peripheral clock enable in low-power mode Set and reset by software. + GPIOELPEN: u1, + /// GPIOF peripheral clock enable in low-power mode Set and reset by software. + GPIOFLPEN: u1, + /// GPIOG peripheral clock enable in low-power mode Set and reset by software. + GPIOGLPEN: u1, + /// GPIOH peripheral clock enable in low-power mode Set and reset by software. + GPIOHLPEN: u1, + reserved12: u4, + /// GPIOM peripheral clock enable in low-power mode Set and reset by software. + GPIOMLPEN: u1, + /// GPION peripheral clock enable in low-power mode Set and reset by software. + GPIONLPEN: u1, + /// GPIOO peripheral clock enable in low-power mode Set and reset by software. + GPIOOLPEN: u1, + /// GPIOP peripheral clock enable in low-power mode Set and reset by software. + GPIOPLPEN: u1, + reserved19: u3, + /// CRC clock enable in low-power mode Set and reset by software. + CRCLPEN: u1, + reserved28: u8, + /// Backup RAM clock enable in low-power mode Set and reset by software. + BKPRAMLPEN: u1, + padding: u3, + }), + /// RCC AHB3 low-power clock enable register. + AHB3LPENR: mmio.Mmio(packed struct(u32) { + /// RNG peripheral clock enable in low-power mode Set and reset by software. + RNGLPEN: u1, + /// HASH peripheral clock enable in low-power mode Set and reset by software. + HASHLPEN: u1, + /// CRYP peripheral clock enable in low-power mode Set and reset by software. + CRYPLPEN: u1, + reserved4: u1, + /// SAES peripheral clock enable in low-power mode Set and reset by software. + SAESLPEN: u1, + reserved6: u1, + /// PKA peripheral clock enable in low-power mode Set and reset by software. + PKALPEN: u1, + padding: u25, + }), + /// RCC APB1 low-power clock enable register 1. + APB1LPENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 peripheral clock enable in low-power mode Set and reset by software. + TIM2LPEN: u1, + /// TIM3 peripheral clock enable in low-power mode Set and reset by software. + TIM3LPEN: u1, + /// TIM4 peripheral clock enable in low-power mode Set and reset by software. + TIM4LPEN: u1, + /// TIM5 peripheral clock enable in low-power mode Set and reset by software. + TIM5LPEN: u1, + /// TIM6 peripheral clock enable in low-power mode Set and reset by software. + TIM6LPEN: u1, + /// TIM7 peripheral clock enable in low-power mode Set and reset by software. + TIM7LPEN: u1, + /// TIM12 peripheral clock enable in low-power mode Set and reset by software. + TIM12LPEN: u1, + /// TIM13 peripheral clock enable in low-power mode Set and reset by software. + TIM13LPEN: u1, + /// TIM14 peripheral clock enable in low-power mode Set and reset by software. + TIM14LPEN: u1, + /// LPTIM1 peripheral clocks enable in low-power mode Set and reset by software. + LPTIM1LPEN: u1, + reserved11: u1, + /// WWDG clock enable in low-power mode Set and reset by software. + WWDGLPEN: u1, + reserved14: u2, + /// SPI2 peripheral clocks enable in low-power mode Set and reset by software. + SPI2LPEN: u1, + /// SPI3 peripheral clocks enable in low-power mode Set and reset by software. + SPI3LPEN: u1, + /// SPDIFRX peripheral clocks enable in low-power mode Set and reset by software. + SPDIFRXLPEN: u1, + /// USART2 peripheral clocks enable in low-power mode Set and reset by software. + USART2LPEN: u1, + /// USART3 peripheral clocks enable in low-power mode Set and reset by software. + USART3LPEN: u1, + /// UART4 peripheral clocks enable in low-power mode Set and reset by software. + UART4LPEN: u1, + /// UART5 peripheral clocks enable in low-power mode Set and reset by software. + UART5LPEN: u1, + /// I2C1/I3C1 peripheral clocks enable in low-power mode Set and reset by software. + I2C1_I3C1LPEN: u1, + /// I2C2 peripheral clocks enable in low-power mode Set and reset by software. + I2C2LPEN: u1, + /// I2C3 peripheral clocks enable in low-power mode Set and reset by software. + I2C3LPEN: u1, + reserved27: u3, + /// HDMI-CEC peripheral clocks enable in low-power mode Set and reset by software. + CECLPEN: u1, + reserved30: u2, + /// UART7 peripheral clocks enable in low-power mode Set and reset by software. + UART7LPEN: u1, + /// UART8 peripheral clocks enable in low-power mode Set and reset by software. + UART8LPEN: u1, + }), + /// RCC APB1 low-power clock enable register 2. + APB1LPENR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// clock recovery system peripheral clock enable in low-power mode Set and reset by software. + CRSLPEN: u1, + reserved5: u3, + /// MDIOS peripheral clock enable in low-power mode Set and reset by software. + MDIOSLPEN: u1, + reserved8: u2, + /// FDCAN peripheral clock enable in low-power mode Set and reset by software. + FDCANLPEN: u1, + reserved27: u18, + /// UCPD peripheral clock enable in low-power mode Set and reset by software. + UCPDLPEN: u1, + padding: u4, + }), + /// RCC APB2 low-power clock enable register. + APB2LPENR: mmio.Mmio(packed struct(u32) { + /// TIM1 peripheral clock enable in low-power mode Set and reset by software. + TIM1LPEN: u1, + reserved4: u3, + /// USART1 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART169SEL and provided to UCLK inputs, and the pclk2 bus interface clock. + USART1LPEN: u1, + reserved12: u7, + /// SPI2S1 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the SPI2S1 are: the kernel clock selected by I2S1SEL and provided to spi_ker_ck input, and the pclk2 bus interface clock. + SPI1LPEN: u1, + /// SPI4 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to com_clk input, and the pclk2 bus interface clock. + SPI4LPEN: u1, + reserved16: u2, + /// TIM15 peripheral clock enable in low-power mode Set and reset by software. + TIM15LPEN: u1, + /// TIM16 peripheral clock enable in low-power mode Set and reset by software. + TIM16LPEN: u1, + /// TIM17 peripheral clock enable in low-power mode Set and reset by software. + TIM17LPEN: u1, + /// TIM9 peripheral clock enable in low-power mode Set and reset by software. + TIM9LPEN: u1, + /// SPI5 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to com_clk input, and the pclk2 bus interface clock. + SPI5LPEN: u1, + reserved22: u1, + /// SAI1 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to SAI_CK_A and SAI_CK_B inputs, and the pclk2 bus interface clock. + SAI1LPEN: u1, + /// SAI2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SAI2 are: the kernel clock selected by SAI2SEL and provided to SAI_CK_A and SAI_CK_B inputs, and the pclk2 bus interface clock. + SAI2LPEN: u1, + padding: u8, + }), + /// RCC APB4 low-power clock enable register. + APB4LPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SBS peripheral clock enable in low-power mode Set and reset by software. + SYSCFGLPEN: u1, + reserved3: u1, + /// LPUART1 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the rcc_pclk4 bus interface clock. + LPUART1LPEN: u1, + reserved5: u1, + /// SPI/I2S6 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_ck input, and the rcc_pclk4 bus interface clock. + SPI6LPEN: u1, + reserved9: u3, + /// LPTIM2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM23SEL and provided to clk_lpt input, and the pclk4 bus interface clock. + LPTIM2LPEN: u1, + /// LPTIM3 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM23SEL and provided to clk_lpt input, and the pclk4 bus interface clock. + LPTIM3LPEN: u1, + /// LPTIM4 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM4 are the kernel clock selected by LPTIM45SEL and provided to clk_lpt input, and the pclk4 bus interface clock. + LPTIM4LPEN: u1, + /// LPTIM5 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM5 are the kernel clock selected by LPTIM45SEL and provided to clk_lpt input, and the pclk4 bus interface clock. + LPTIM5LPEN: u1, + reserved15: u2, + /// VREF peripheral clock enable in low-power mode Set and reset by software. + VREFLPEN: u1, + /// RTC APB clock enable in low-power mode Set and reset by software. + RTCAPBLPEN: u1, + reserved26: u9, + /// temperature sensor peripheral clock enable in low-power mode Set and reset by software. + TMPSENSLPEN: u1, + padding: u5, + }), + /// RCC APB5 sleep clock register. + APB5LPENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// LTDC peripheral clock enable in low-power mode Set and reset by software. + LTDCLPEN: u1, + /// DCMIPP peripheral clock enable in low-power mode Set and reset by software. + DCMIPPLPEN: u1, + reserved4: u1, + /// GFXTIM peripheral clock enable in low-power mode Set and reset by software. + GFXTIMLPEN: u1, + padding: u27, + }), + }; + }; + + pub const rcc_l0 = struct { + pub const HPRE = enum(u4) { + /// system clock not divided + Div1 = 0x0, + /// system clock divided by 2 + Div2 = 0x8, + /// system clock divided by 4 + Div4 = 0x9, + /// system clock divided by 8 + Div8 = 0xa, + /// system clock divided by 16 + Div16 = 0xb, + /// system clock divided by 64 + Div64 = 0xc, + /// system clock divided by 128 + Div128 = 0xd, + /// system clock divided by 256 + Div256 = 0xe, + /// system clock divided by 512 + Div512 = 0xf, + _, + }; + + pub const I2CSEL = enum(u2) { + /// APB clock selected as peripheral clock + PCLK1 = 0x0, + /// System clock selected as peripheral clock + SYS = 0x1, + /// HSI clock selected as peripheral clock + HSI = 0x2, + _, + }; + + pub const LPTIMSEL = enum(u2) { + /// APB clock selected as Timer clock + PCLK1 = 0x0, + /// LSI clock selected as Timer clock + LSI = 0x1, + /// HSI clock selected as Timer clock + HSI = 0x2, + /// LSE clock selected as Timer clock + LSE = 0x3, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const MCOPRE = enum(u3) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x1, + /// Division by 4 + Div4 = 0x2, + /// Division by 8 + Div8 = 0x3, + /// Division by 16 + Div16 = 0x4, + _, + }; + + pub const MCOSEL = enum(u4) { + /// No clock + DISABLE = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI oscillator clock selected + HSI = 0x2, + /// MSI oscillator clock selected + MSI = 0x3, + /// HSE oscillator clock selected + HSE = 0x4, + /// PLL clock selected + PLL = 0x5, + /// LSI oscillator clock selected + LSI = 0x6, + /// LSE oscillator clock selected + LSE = 0x7, + _, + }; + + pub const MSIRANGE = enum(u3) { + /// range 0 around 65.536 kHz + Range66K = 0x0, + /// range 1 around 131.072 kHz + Range131K = 0x1, + /// range 2 around 262.144 kHz + Range262K = 0x2, + /// range 3 around 524.288 kHz + Range524K = 0x3, + /// range 4 around 1.048 MHz + Range1M = 0x4, + /// range 5 around 2.097 MHz (reset value) + Range2M = 0x5, + /// range 6 around 4.194 MHz + Range4M = 0x6, + _, + }; + + pub const PLLDIV = enum(u2) { + /// PLLVCO / 2 + Div2 = 0x1, + /// PLLVCO / 3 + Div3 = 0x2, + /// PLLVCO / 4 + Div4 = 0x3, + _, + }; + + pub const PLLMUL = enum(u4) { + /// PLL clock entry x 3 + Mul3 = 0x0, + /// PLL clock entry x 4 + Mul4 = 0x1, + /// PLL clock entry x 6 + Mul6 = 0x2, + /// PLL clock entry x 8 + Mul8 = 0x3, + /// PLL clock entry x 12 + Mul12 = 0x4, + /// PLL clock entry x 16 + Mul16 = 0x5, + /// PLL clock entry x 24 + Mul24 = 0x6, + /// PLL clock entry x 32 + Mul32 = 0x7, + /// PLL clock entry x 48 + Mul48 = 0x8, + _, + }; + + pub const PLLSRC = enum(u1) { + /// HSI selected as PLL input clock + HSI = 0x0, + /// HSE selected as PLL input clock + HSE = 0x1, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const RTCPRE = enum(u2) { + /// HSE divided by 2 + Div2 = 0x0, + /// HSE divided by 4 + Div4 = 0x1, + /// HSE divided by 8 + Div8 = 0x2, + /// HSE divided by 16 + Div16 = 0x3, + }; + + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock + HSE = 0x3, + }; + + pub const STOPWUCK = enum(u1) { + /// Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock + MSI = 0x0, + /// Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI/4 if HSIDIVEN=1) + HSI = 0x1, + }; + + pub const SW = enum(u2) { + /// MSI oscillator used as system clock + MSI = 0x0, + /// HSI oscillator used as system clock + HSI = 0x1, + /// HSE oscillator used as system clock + HSE = 0x2, + /// PLL used as system clock + PLL1_R = 0x3, + }; + + pub const UARTSEL = enum(u2) { + /// APB clock selected as peripheral clock + PCLK1 = 0x0, + /// System clock selected as peripheral clock + SYS = 0x1, + /// HSI clock selected as peripheral clock + HSI = 0x2, + /// LSE clock selected as peripheral clock + LSE = 0x3, + }; + + pub const USART1SEL = enum(u2) { + /// APB clock selected as peripheral clock + PCLK2 = 0x0, + /// System clock selected as peripheral clock + SYS = 0x1, + /// HSI clock selected as peripheral clock + HSI = 0x2, + /// LSE clock selected as peripheral clock + LSE = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// 16 MHz high-speed internal clock enable + HSION: u1, + /// High-speed internal clock enable bit for some IP kernels + HSIKERON: u1, + /// Internal high-speed clock ready flag + HSIRDY: u1, + /// HSIDIVEN + HSIDIVEN: u1, + /// HSIDIVF + HSIDIVF: u1, + /// 16 MHz high-speed internal clock output enable + HSIOUTEN: u1, + reserved8: u2, + /// MSI clock enable + MSION: u1, + /// MSI clock ready flag + MSIRDY: u1, + reserved16: u6, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + /// Clock security system on HSE enable + CSSHSEON: u1, + /// TC/LCD prescaler + RTCPRE: packed union { + raw: u2, + value: RTCPRE, + }, + reserved24: u2, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding: u6, + }), + /// Internal clock sources calibration register + ICSCR: mmio.Mmio(packed struct(u32) { + /// nternal high speed clock calibration + HSICAL: u8, + /// High speed internal clock trimming + HSITRIM: u5, + /// MSI clock ranges + MSIRANGE: packed union { + raw: u3, + value: MSIRANGE, + }, + /// MSI clock calibration + MSICAL: u8, + /// MSI clock trimming + MSITRIM: u8, + }), + reserved12: [4]u8, + /// Clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u2, + value: SW, + }, + /// System clock switch status + SWS: packed union { + raw: u2, + value: SW, + }, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// APB low-speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + /// APB high-speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + reserved15: u1, + /// Wake-up from stop clock selection + STOPWUCK: packed union { + raw: u1, + value: STOPWUCK, + }, + /// PLL entry clock source + PLLSRC: packed union { + raw: u1, + value: PLLSRC, + }, + reserved18: u1, + /// PLL multiplication factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, + }, + /// PLL output division + PLLDIV: packed union { + raw: u2, + value: PLLDIV, + }, + /// Microcontroller clock output selection + MCOSEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// Microcontroller clock output prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, + }, + padding: u1, + }), + /// Clock interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYIE: u1, + /// LSE ready interrupt flag + LSERDYIE: u1, + /// HSI ready interrupt flag + HSIRDYIE: u1, + /// HSE ready interrupt flag + HSERDYIE: u1, + /// PLL ready interrupt flag + PLLRDYIE: u1, + /// MSI ready interrupt flag + MSIRDYIE: u1, + reserved7: u1, + /// LSE CSS interrupt flag + CSSLSE: u1, + padding: u24, + }), + /// Clock interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// PLL ready interrupt flag + PLLRDYF: u1, + /// MSI ready interrupt flag + MSIRDYF: u1, + reserved7: u1, + /// LSE Clock Security System Interrupt flag + CSSLSEF: u1, + /// Clock Security System Interrupt flag + CSSHSEF: u1, + padding: u23, + }), + /// Clock interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready Interrupt clear + LSIRDYC: u1, + /// LSE ready Interrupt clear + LSERDYC: u1, + /// HSI ready Interrupt clear + HSIRDYC: u1, + /// HSE ready Interrupt clear + HSERDYC: u1, + /// PLL ready Interrupt clear + PLLRDYC: u1, + /// MSI ready Interrupt clear + MSIRDYC: u1, + reserved7: u1, + /// LSE Clock Security System Interrupt clear + CSSLSEC: u1, + /// Clock Security System Interrupt clear + CSSHSEC: u1, + padding: u23, + }), + /// GPIO reset register + GPIORSTR: mmio.Mmio(packed struct(u32) { + /// I/O port A reset + GPIOARST: u1, + /// I/O port B reset + GPIOBRST: u1, + /// I/O port A reset + GPIOCRST: u1, + /// I/O port D reset + GPIODRST: u1, + /// I/O port E reset + GPIOERST: u1, + reserved7: u2, + /// I/O port H reset + GPIOHRST: u1, + padding: u24, + }), + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + /// DMA reset + DMA1RST: u1, + reserved8: u7, + /// Memory interface reset + MIFRST: u1, + reserved12: u3, + /// Test integration module reset + CRCRST: u1, + reserved16: u3, + /// Touch Sensing reset + TSCRST: u1, + reserved20: u3, + /// Random Number Generator module reset + RNGRST: u1, + reserved24: u3, + /// Crypto module reset + CRYPRST: u1, + padding: u7, + }), + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// System configuration controller reset + SYSCFGRST: u1, + reserved2: u1, + /// TIM21 timer reset + TIM21RST: u1, + reserved5: u2, + /// TIM22 timer reset + TIM22RST: u1, + reserved9: u3, + /// ADC interface reset + ADCRST: u1, + reserved12: u2, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// USART1 reset + USART1RST: u1, + reserved22: u7, + /// DBG reset + DBGRST: u1, + padding: u9, + }), + /// APB1 peripheral reset register + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + reserved4: u2, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + reserved11: u5, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + reserved17: u2, + /// USART2 reset + USART2RST: u1, + /// LPUART1 reset + LPUART1RST: u1, + /// USART4 reset + USART4RST: u1, + /// USART5 reset + USART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB reset + USBRST: u1, + reserved27: u3, + /// Clock recovery system reset + CRSRST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// I2C3 reset + I2C3RST: u1, + /// Low power timer reset + LPTIM1RST: u1, + }), + /// GPIO clock enable register + GPIOENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port A clock enable + GPIOCEN: u1, + /// I/O port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + reserved7: u2, + /// I/O port H clock enable + GPIOHEN: u1, + padding: u24, + }), + /// AHB peripheral clock enable register + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA clock enable + DMA1EN: u1, + reserved8: u7, + /// NVM interface clock enable + MIFEN: u1, + reserved12: u3, + /// CRC clock enable + CRCEN: u1, + reserved16: u3, + /// Touch Sensing clock enable + TSCEN: u1, + reserved20: u3, + /// Random Number Generator clock enable + RNGEN: u1, + reserved24: u3, + /// Crypto clock enable + CRYPEN: u1, + padding: u7, + }), + /// APB2 peripheral clock enable register + APB2ENR: mmio.Mmio(packed struct(u32) { + /// System configuration controller clock enable + SYSCFGEN: u1, + reserved2: u1, + /// TIM21 timer clock enable + TIM21EN: u1, + reserved5: u2, + /// TIM22 timer clock enable + TIM22EN: u1, + reserved7: u1, + /// Firewall clock enable + FWEN: u1, + reserved9: u1, + /// ADC clock enable + ADCEN: u1, + reserved12: u2, + /// SPI1 clock enable + SPI1EN: u1, + reserved14: u1, + /// USART1 clock enable + USART1EN: u1, + reserved22: u7, + /// DBG clock enable + DBGEN: u1, + padding: u9, + }), + /// APB1 peripheral clock enable register + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer2 clock enable + TIM2EN: u1, + /// Timer 3 clock enbale + TIM3EN: u1, + reserved4: u2, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + reserved11: u5, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI2 clock enable + SPI2EN: u1, + reserved17: u2, + /// UART2 clock enable + USART2EN: u1, + /// LPUART1 clock enable + LPUART1EN: u1, + /// USART4 clock enable + USART4EN: u1, + /// USART5 clock enable + USART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// USB clock enable + USBEN: u1, + reserved27: u3, + /// Clock recovery system clock enable + CRSEN: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// I2C3 clock enable + I2C3EN: u1, + /// Low power timer clock enable + LPTIM1EN: u1, + }), + /// GPIO clock enable in sleep mode register + GPIOSMEN: mmio.Mmio(packed struct(u32) { + /// Port A clock enable during Sleep mode + GPIOASMEN: u1, + /// Port B clock enable during Sleep mode + GPIOBSMEN: u1, + /// Port C clock enable during Sleep mode + GPIOCSMEN: u1, + /// Port D clock enable during Sleep mode + GPIODSMEN: u1, + /// Port E clock enable during Sleep mode + GPIOESMEN: u1, + reserved7: u2, + /// Port H clock enable during Sleep mode + GPIOHSMEN: u1, + padding: u24, + }), + /// AHB peripheral clock enable in sleep mode register + AHBSMENR: mmio.Mmio(packed struct(u32) { + /// DMA clock enable during sleep mode + DMA1SMEN: u1, + reserved8: u7, + /// NVM interface clock enable during sleep mode + MIFSMEN: u1, + /// SRAM interface clock enable during sleep mode + SRAMSMEN: u1, + reserved12: u2, + /// CRC clock enable during sleep mode + CRCSMEN: u1, + reserved16: u3, + /// Touch Sensing clock enable during sleep mode + TSCSMEN: u1, + reserved20: u3, + /// Random Number Generator clock enable during sleep mode + RNGSMEN: u1, + reserved24: u3, + /// Crypto clock enable during sleep mode + CRYPSMEN: u1, + padding: u7, + }), + /// APB2 peripheral clock enable in sleep mode register + APB2SMENR: mmio.Mmio(packed struct(u32) { + /// System configuration controller clock enable during sleep mode + SYSCFGSMEN: u1, + reserved2: u1, + /// TIM21 timer clock enable during sleep mode + TIM21SMEN: u1, + reserved5: u2, + /// TIM22 timer clock enable during sleep mode + TIM22SMEN: u1, + reserved9: u3, + /// ADC clock enable during sleep mode + ADCSMEN: u1, + reserved12: u2, + /// SPI1 clock enable during sleep mode + SPI1SMEN: u1, + reserved14: u1, + /// USART1 clock enable during sleep mode + USART1SMEN: u1, + reserved22: u7, + /// DBG clock enable during sleep mode + DBGSMEN: u1, + padding: u9, + }), + /// APB1 peripheral clock enable in sleep mode register + APB1SMENR: mmio.Mmio(packed struct(u32) { + /// Timer2 clock enable during sleep mode + TIM2SMEN: u1, + /// Timer 3 clock enable during sleep mode + TIM3SMEN: u1, + reserved4: u2, + /// Timer 6 clock enable during sleep mode + TIM6SMEN: u1, + /// Timer 7 clock enable during sleep mode + TIM7SMEN: u1, + reserved11: u5, + /// Window watchdog clock enable during sleep mode + WWDGSMEN: u1, + reserved14: u2, + /// SPI2 clock enable during sleep mode + SPI2SMEN: u1, + reserved17: u2, + /// UART2 clock enable during sleep mode + USART2SMEN: u1, + /// LPUART1 clock enable during sleep mode + LPUART1SMEN: u1, + /// USART4 clock enabe during sleep mode + USART4SMEN: u1, + /// USART5 clock enable during sleep mode + USART5SMEN: u1, + /// I2C1 clock enable during sleep mode + I2C1SMEN: u1, + /// I2C2 clock enable during sleep mode + I2C2SMEN: u1, + /// USB clock enable during sleep mode + USBSMEN: u1, + reserved27: u3, + /// Clock recovery system clock enable during sleep mode + CRSSMEN: u1, + /// Power interface clock enable during sleep mode + PWRSMEN: u1, + /// DAC interface clock enable during sleep mode + DACSMEN: u1, + /// I2C3 clock enable during sleep mode + I2C3SMEN: u1, + /// Low power timer clock enable during sleep mode + LPTIM1SMEN: u1, + }), + /// Clock configuration register + CCIPR: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SEL: packed union { + raw: u2, + value: USART1SEL, + }, + /// USART2 clock source selection + USART2SEL: packed union { + raw: u2, + value: UARTSEL, + }, + reserved10: u6, + /// LPUART1 clock source selection + LPUART1SEL: packed union { + raw: u2, + value: UARTSEL, + }, + /// I2C1 clock source selection + I2C1SEL: packed union { + raw: u2, + value: I2CSEL, + }, + reserved16: u2, + /// I2C3 clock source selection + I2C3SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// Low Power Timer clock source selection + LPTIM1SEL: packed union { + raw: u2, + value: LPTIMSEL, + }, + padding: u12, + }), + /// Control and status register + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low-speed oscillator enable + LSION: u1, + /// Internal low-speed oscillator ready + LSIRDY: u1, + reserved8: u6, + /// External low-speed oscillator enable + LSEON: u1, + /// External low-speed oscillator ready + LSERDY: u1, + /// External low-speed oscillator bypass + LSEBYP: u1, + /// LSEDRV + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// CSSLSEON + CSSLSEON: u1, + /// CSS on LSE failure detection flag + CSSLSED: u1, + reserved16: u1, + /// RTC and LCD clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + /// RTC clock enable + RTCEN: u1, + /// RTC software reset + RTCRST: u1, + reserved23: u3, + /// Remove reset flag + RMVF: u1, + /// Firewall reset flag + FWRSTF: u1, + /// OBLRSTF + OBLRSTF: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + }; + }; + + pub const rcc_l0_v2 = struct { + pub const CLK48SEL = enum(u1) { + /// PLL VCO divided by 2 selected + PLL1_VCO_DIV_2 = 0x0, + /// HSI48 clock selected + HSI48 = 0x1, + }; + + pub const HPRE = enum(u4) { + /// system clock not divided + Div1 = 0x0, + /// system clock divided by 2 + Div2 = 0x8, + /// system clock divided by 4 + Div4 = 0x9, + /// system clock divided by 8 + Div8 = 0xa, + /// system clock divided by 16 + Div16 = 0xb, + /// system clock divided by 64 + Div64 = 0xc, + /// system clock divided by 128 + Div128 = 0xd, + /// system clock divided by 256 + Div256 = 0xe, + /// system clock divided by 512 + Div512 = 0xf, + _, + }; + + pub const I2CSEL = enum(u2) { + /// APB clock selected as peripheral clock + PCLK1 = 0x0, + /// System clock selected as peripheral clock + SYS = 0x1, + /// HSI clock selected as peripheral clock + HSI = 0x2, + _, + }; + + pub const LPTIMSEL = enum(u2) { + /// APB clock selected as Timer clock + PCLK1 = 0x0, + /// LSI clock selected as Timer clock + LSI = 0x1, + /// HSI clock selected as Timer clock + HSI = 0x2, + /// LSE clock selected as Timer clock + LSE = 0x3, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const MCOPRE = enum(u3) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x1, + /// Division by 4 + Div4 = 0x2, + /// Division by 8 + Div8 = 0x3, + /// Division by 16 + Div16 = 0x4, + _, + }; + + pub const MCOSEL = enum(u4) { + /// No clock + DISABLE = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI oscillator clock selected + HSI = 0x2, + /// MSI oscillator clock selected + MSI = 0x3, + /// HSE oscillator clock selected + HSE = 0x4, + /// PLL clock selected + PLL = 0x5, + /// LSI oscillator clock selected + LSI = 0x6, + /// LSE oscillator clock selected + LSE = 0x7, + _, + }; + + pub const MSIRANGE = enum(u3) { + /// range 0 around 65.536 kHz + Range66K = 0x0, + /// range 1 around 131.072 kHz + Range131K = 0x1, + /// range 2 around 262.144 kHz + Range262K = 0x2, + /// range 3 around 524.288 kHz + Range524K = 0x3, + /// range 4 around 1.048 MHz + Range1M = 0x4, + /// range 5 around 2.097 MHz (reset value) + Range2M = 0x5, + /// range 6 around 4.194 MHz + Range4M = 0x6, + _, + }; + + pub const PLLDIV = enum(u2) { + /// PLLVCO / 2 + Div2 = 0x1, + /// PLLVCO / 3 + Div3 = 0x2, + /// PLLVCO / 4 + Div4 = 0x3, + _, + }; + + pub const PLLMUL = enum(u4) { + /// PLL clock entry x 3 + Mul3 = 0x0, + /// PLL clock entry x 4 + Mul4 = 0x1, + /// PLL clock entry x 6 + Mul6 = 0x2, + /// PLL clock entry x 8 + Mul8 = 0x3, + /// PLL clock entry x 12 + Mul12 = 0x4, + /// PLL clock entry x 16 + Mul16 = 0x5, + /// PLL clock entry x 24 + Mul24 = 0x6, + /// PLL clock entry x 32 + Mul32 = 0x7, + /// PLL clock entry x 48 + Mul48 = 0x8, + _, + }; + + pub const PLLSRC = enum(u1) { + /// HSI selected as PLL input clock + HSI = 0x0, + /// HSE selected as PLL input clock + HSE = 0x1, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const RTCPRE = enum(u2) { + /// HSE divided by 2 + Div2 = 0x0, + /// HSE divided by 4 + Div4 = 0x1, + /// HSE divided by 8 + Div8 = 0x2, + /// HSE divided by 16 + Div16 = 0x3, + }; + + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock + HSE = 0x3, + }; + + pub const STOPWUCK = enum(u1) { + /// Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock + MSI = 0x0, + /// Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI/4 if HSIDIVEN=1) + HSI = 0x1, + }; + + pub const SW = enum(u2) { + /// MSI oscillator used as system clock + MSI = 0x0, + /// HSI oscillator used as system clock + HSI = 0x1, + /// HSE oscillator used as system clock + HSE = 0x2, + /// PLL used as system clock + PLL1_R = 0x3, + }; + + pub const UARTSEL = enum(u2) { + /// APB clock selected as peripheral clock + PCLK1 = 0x0, + /// System clock selected as peripheral clock + SYS = 0x1, + /// HSI clock selected as peripheral clock + HSI = 0x2, + /// LSE clock selected as peripheral clock + LSE = 0x3, + }; + + pub const USART1SEL = enum(u2) { + /// APB clock selected as peripheral clock + PCLK2 = 0x0, + /// System clock selected as peripheral clock + SYS = 0x1, + /// HSI clock selected as peripheral clock + HSI = 0x2, + /// LSE clock selected as peripheral clock + LSE = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// 16 MHz high-speed internal clock enable + HSION: u1, + /// High-speed internal clock enable bit for some IP kernels + HSIKERON: u1, + /// Internal high-speed clock ready flag + HSIRDY: u1, + /// HSIDIVEN + HSIDIVEN: u1, + /// HSIDIVF + HSIDIVF: u1, + /// 16 MHz high-speed internal clock output enable + HSIOUTEN: u1, + reserved8: u2, + /// MSI clock enable + MSION: u1, + /// MSI clock ready flag + MSIRDY: u1, + reserved16: u6, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + /// Clock security system on HSE enable + CSSHSEON: u1, + /// TC/LCD prescaler + RTCPRE: packed union { + raw: u2, + value: RTCPRE, + }, + reserved24: u2, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding: u6, + }), + /// Internal clock sources calibration register + ICSCR: mmio.Mmio(packed struct(u32) { + /// nternal high speed clock calibration + HSICAL: u8, + /// High speed internal clock trimming + HSITRIM: u5, + /// MSI clock ranges + MSIRANGE: packed union { + raw: u3, + value: MSIRANGE, + }, + /// MSI clock calibration + MSICAL: u8, + /// MSI clock trimming + MSITRIM: u8, + }), + /// Clock recovery RC register + CRRCR: mmio.Mmio(packed struct(u32) { + /// 48MHz HSI clock enable + HSI48ON: u1, + /// 48MHz HSI clock ready flag + HSI48RDY: u1, + /// 48 MHz HSI clock divided by 6 output enable + HSI48DIV6EN: u1, + reserved8: u5, + /// 48 MHz HSI clock calibration + HSI48CAL: u8, + padding: u16, + }), + /// Clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u2, + value: SW, + }, + /// System clock switch status + SWS: packed union { + raw: u2, + value: SW, + }, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// APB low-speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + /// APB high-speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + reserved15: u1, + /// Wake-up from stop clock selection + STOPWUCK: packed union { + raw: u1, + value: STOPWUCK, + }, + /// PLL entry clock source + PLLSRC: packed union { + raw: u1, + value: PLLSRC, + }, + reserved18: u1, + /// PLL multiplication factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, + }, + /// PLL output division + PLLDIV: packed union { + raw: u2, + value: PLLDIV, + }, + /// Microcontroller clock output selection + MCOSEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// Microcontroller clock output prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, + }, + padding: u1, + }), + /// Clock interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYIE: u1, + /// LSE ready interrupt flag + LSERDYIE: u1, + /// HSI ready interrupt flag + HSIRDYIE: u1, + /// HSE ready interrupt flag + HSERDYIE: u1, + /// PLL ready interrupt flag + PLLRDYIE: u1, + /// MSI ready interrupt flag + MSIRDYIE: u1, + /// HSI48 ready interrupt flag + HSI48RDYIE: u1, + /// LSE CSS interrupt flag + CSSLSE: u1, + padding: u24, + }), + /// Clock interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// PLL ready interrupt flag + PLLRDYF: u1, + /// MSI ready interrupt flag + MSIRDYF: u1, + /// HSI48 ready interrupt flag + HSI48RDYF: u1, + /// LSE Clock Security System Interrupt flag + CSSLSEF: u1, + /// Clock Security System Interrupt flag + CSSHSEF: u1, + padding: u23, + }), + /// Clock interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready Interrupt clear + LSIRDYC: u1, + /// LSE ready Interrupt clear + LSERDYC: u1, + /// HSI ready Interrupt clear + HSIRDYC: u1, + /// HSE ready Interrupt clear + HSERDYC: u1, + /// PLL ready Interrupt clear + PLLRDYC: u1, + /// MSI ready Interrupt clear + MSIRDYC: u1, + /// HSI48 ready Interrupt clear + HSI48RDYC: u1, + /// LSE Clock Security System Interrupt clear + CSSLSEC: u1, + /// Clock Security System Interrupt clear + CSSHSEC: u1, + padding: u23, + }), + /// GPIO reset register + GPIORSTR: mmio.Mmio(packed struct(u32) { + /// I/O port A reset + GPIOARST: u1, + /// I/O port B reset + GPIOBRST: u1, + /// I/O port A reset + GPIOCRST: u1, + /// I/O port D reset + GPIODRST: u1, + /// I/O port E reset + GPIOERST: u1, + reserved7: u2, + /// I/O port H reset + GPIOHRST: u1, + padding: u24, + }), + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + /// DMA reset + DMA1RST: u1, + reserved8: u7, + /// Memory interface reset + MIFRST: u1, + reserved12: u3, + /// Test integration module reset + CRCRST: u1, + reserved16: u3, + /// Touch Sensing reset + TSCRST: u1, + reserved20: u3, + /// Random Number Generator module reset + RNGRST: u1, + reserved24: u3, + /// Crypto module reset + CRYPRST: u1, + padding: u7, + }), + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// System configuration controller reset + SYSCFGRST: u1, + reserved2: u1, + /// TIM21 timer reset + TIM21RST: u1, + reserved5: u2, + /// TIM22 timer reset + TIM22RST: u1, + reserved9: u3, + /// ADC interface reset + ADCRST: u1, + reserved12: u2, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// USART1 reset + USART1RST: u1, + reserved22: u7, + /// DBG reset + DBGRST: u1, + padding: u9, + }), + /// APB1 peripheral reset register + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + reserved4: u2, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + reserved11: u5, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + reserved17: u2, + /// USART2 reset + USART2RST: u1, + /// LPUART1 reset + LPUART1RST: u1, + /// USART4 reset + USART4RST: u1, + /// USART5 reset + USART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB reset + USBRST: u1, + reserved27: u3, + /// Clock recovery system reset + CRSRST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// I2C3 reset + I2C3RST: u1, + /// Low power timer reset + LPTIM1RST: u1, + }), + /// GPIO clock enable register + GPIOENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port A clock enable + GPIOCEN: u1, + /// I/O port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + reserved7: u2, + /// I/O port H clock enable + GPIOHEN: u1, + padding: u24, + }), + /// AHB peripheral clock enable register + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA clock enable + DMA1EN: u1, + reserved8: u7, + /// NVM interface clock enable + MIFEN: u1, + reserved12: u3, + /// CRC clock enable + CRCEN: u1, + reserved16: u3, + /// Touch Sensing clock enable + TSCEN: u1, + reserved20: u3, + /// Random Number Generator clock enable + RNGEN: u1, + reserved24: u3, + /// Crypto clock enable + CRYPEN: u1, + padding: u7, + }), + /// APB2 peripheral clock enable register + APB2ENR: mmio.Mmio(packed struct(u32) { + /// System configuration controller clock enable + SYSCFGEN: u1, + reserved2: u1, + /// TIM21 timer clock enable + TIM21EN: u1, + reserved5: u2, + /// TIM22 timer clock enable + TIM22EN: u1, + reserved7: u1, + /// Firewall clock enable + FWEN: u1, + reserved9: u1, + /// ADC clock enable + ADCEN: u1, + reserved12: u2, + /// SPI1 clock enable + SPI1EN: u1, + reserved14: u1, + /// USART1 clock enable + USART1EN: u1, + reserved22: u7, + /// DBG clock enable + DBGEN: u1, + padding: u9, + }), + /// APB1 peripheral clock enable register + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer2 clock enable + TIM2EN: u1, + /// Timer 3 clock enbale + TIM3EN: u1, + reserved4: u2, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + reserved11: u5, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI2 clock enable + SPI2EN: u1, + reserved17: u2, + /// UART2 clock enable + USART2EN: u1, + /// LPUART1 clock enable + LPUART1EN: u1, + /// USART4 clock enable + USART4EN: u1, + /// USART5 clock enable + USART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// USB clock enable + USBEN: u1, + reserved27: u3, + /// Clock recovery system clock enable + CRSEN: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// I2C3 clock enable + I2C3EN: u1, + /// Low power timer clock enable + LPTIM1EN: u1, + }), + /// GPIO clock enable in sleep mode register + GPIOSMEN: mmio.Mmio(packed struct(u32) { + /// Port A clock enable during Sleep mode + GPIOASMEN: u1, + /// Port B clock enable during Sleep mode + GPIOBSMEN: u1, + /// Port C clock enable during Sleep mode + GPIOCSMEN: u1, + /// Port D clock enable during Sleep mode + GPIODSMEN: u1, + /// Port E clock enable during Sleep mode + GPIOESMEN: u1, + reserved7: u2, + /// Port H clock enable during Sleep mode + GPIOHSMEN: u1, + padding: u24, + }), + /// AHB peripheral clock enable in sleep mode register + AHBSMENR: mmio.Mmio(packed struct(u32) { + /// DMA clock enable during sleep mode + DMA1SMEN: u1, + reserved8: u7, + /// NVM interface clock enable during sleep mode + MIFSMEN: u1, + /// SRAM interface clock enable during sleep mode + SRAMSMEN: u1, + reserved12: u2, + /// CRC clock enable during sleep mode + CRCSMEN: u1, + reserved16: u3, + /// Touch Sensing clock enable during sleep mode + TSCSMEN: u1, + reserved20: u3, + /// Random Number Generator clock enable during sleep mode + RNGSMEN: u1, + reserved24: u3, + /// Crypto clock enable during sleep mode + CRYPSMEN: u1, + padding: u7, + }), + /// APB2 peripheral clock enable in sleep mode register + APB2SMENR: mmio.Mmio(packed struct(u32) { + /// System configuration controller clock enable during sleep mode + SYSCFGSMEN: u1, + reserved2: u1, + /// TIM21 timer clock enable during sleep mode + TIM21SMEN: u1, + reserved5: u2, + /// TIM22 timer clock enable during sleep mode + TIM22SMEN: u1, + reserved9: u3, + /// ADC clock enable during sleep mode + ADCSMEN: u1, + reserved12: u2, + /// SPI1 clock enable during sleep mode + SPI1SMEN: u1, + reserved14: u1, + /// USART1 clock enable during sleep mode + USART1SMEN: u1, + reserved22: u7, + /// DBG clock enable during sleep mode + DBGSMEN: u1, + padding: u9, + }), + /// APB1 peripheral clock enable in sleep mode register + APB1SMENR: mmio.Mmio(packed struct(u32) { + /// Timer2 clock enable during sleep mode + TIM2SMEN: u1, + /// Timer 3 clock enable during sleep mode + TIM3SMEN: u1, + reserved4: u2, + /// Timer 6 clock enable during sleep mode + TIM6SMEN: u1, + /// Timer 7 clock enable during sleep mode + TIM7SMEN: u1, + reserved11: u5, + /// Window watchdog clock enable during sleep mode + WWDGSMEN: u1, + reserved14: u2, + /// SPI2 clock enable during sleep mode + SPI2SMEN: u1, + reserved17: u2, + /// UART2 clock enable during sleep mode + USART2SMEN: u1, + /// LPUART1 clock enable during sleep mode + LPUART1SMEN: u1, + /// USART4 clock enabe during sleep mode + USART4SMEN: u1, + /// USART5 clock enable during sleep mode + USART5SMEN: u1, + /// I2C1 clock enable during sleep mode + I2C1SMEN: u1, + /// I2C2 clock enable during sleep mode + I2C2SMEN: u1, + /// USB clock enable during sleep mode + USBSMEN: u1, + reserved27: u3, + /// Clock recovery system clock enable during sleep mode + CRSSMEN: u1, + /// Power interface clock enable during sleep mode + PWRSMEN: u1, + /// DAC interface clock enable during sleep mode + DACSMEN: u1, + /// I2C3 clock enable during sleep mode + I2C3SMEN: u1, + /// Low power timer clock enable during sleep mode + LPTIM1SMEN: u1, + }), + /// Clock configuration register + CCIPR: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SEL: packed union { + raw: u2, + value: USART1SEL, + }, + /// USART2 clock source selection + USART2SEL: packed union { + raw: u2, + value: UARTSEL, + }, + reserved10: u6, + /// LPUART1 clock source selection + LPUART1SEL: packed union { + raw: u2, + value: UARTSEL, + }, + /// I2C1 clock source selection + I2C1SEL: packed union { + raw: u2, + value: I2CSEL, + }, + reserved16: u2, + /// I2C3 clock source selection + I2C3SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// Low Power Timer clock source selection + LPTIM1SEL: packed union { + raw: u2, + value: LPTIMSEL, + }, + reserved26: u6, + /// 48 MHz clock source selection + CLK48SEL: packed union { + raw: u1, + value: CLK48SEL, + }, + padding: u5, + }), + /// Control and status register + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low-speed oscillator enable + LSION: u1, + /// Internal low-speed oscillator ready + LSIRDY: u1, + reserved8: u6, + /// External low-speed oscillator enable + LSEON: u1, + /// External low-speed oscillator ready + LSERDY: u1, + /// External low-speed oscillator bypass + LSEBYP: u1, + /// LSEDRV + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// CSSLSEON + CSSLSEON: u1, + /// CSS on LSE failure detection flag + CSSLSED: u1, + reserved16: u1, + /// RTC and LCD clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + /// RTC clock enable + RTCEN: u1, + /// RTC software reset + RTCRST: u1, + reserved23: u3, + /// Remove reset flag + RMVF: u1, + /// Firewall reset flag + FWRSTF: u1, + /// OBLRSTF + OBLRSTF: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + }; + }; + + pub const rcc_l1 = struct { + pub const HPRE = enum(u4) { + /// system clock not divided + Div1 = 0x0, + /// system clock divided by 2 + Div2 = 0x8, + /// system clock divided by 4 + Div4 = 0x9, + /// system clock divided by 8 + Div8 = 0xa, + /// system clock divided by 16 + Div16 = 0xb, + /// system clock divided by 64 + Div64 = 0xc, + /// system clock divided by 128 + Div128 = 0xd, + /// system clock divided by 256 + Div256 = 0xe, + /// system clock divided by 512 + Div512 = 0xf, + _, + }; + + pub const MCOPRE = enum(u3) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x1, + /// Division by 4 + Div4 = 0x2, + /// Division by 8 + Div8 = 0x3, + /// Division by 16 + Div16 = 0x4, + _, + }; + + pub const MCOSEL = enum(u3) { + /// No clock + DISABLE = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI oscillator clock selected + HSI = 0x2, + /// MSI oscillator clock selected + MSI = 0x3, + /// HSE oscillator clock selected + HSE = 0x4, + /// PLL clock selected + PLL = 0x5, + /// LSI oscillator clock selected + LSI = 0x6, + /// LSE oscillator clock selected + LSE = 0x7, + }; + + pub const MSIRANGE = enum(u3) { + /// range 0 around 65.536 kHz + Range66K = 0x0, + /// range 1 around 131.072 kHz + Range131K = 0x1, + /// range 2 around 262.144 kHz + Range262K = 0x2, + /// range 3 around 524.288 kHz + Range524K = 0x3, + /// range 4 around 1.048 MHz + Range1M = 0x4, + /// range 5 around 2.097 MHz (reset value) + Range2M = 0x5, + /// range 6 around 4.194 MHz + Range4M = 0x6, + _, + }; + + pub const PLLDIV = enum(u2) { + /// PLLVCO / 2 + Div2 = 0x1, + /// PLLVCO / 3 + Div3 = 0x2, + /// PLLVCO / 4 + Div4 = 0x3, + _, + }; + + pub const PLLMUL = enum(u4) { + /// PLL clock entry x 3 + Mul3 = 0x0, + /// PLL clock entry x 4 + Mul4 = 0x1, + /// PLL clock entry x 6 + Mul6 = 0x2, + /// PLL clock entry x 8 + Mul8 = 0x3, + /// PLL clock entry x 12 + Mul12 = 0x4, + /// PLL clock entry x 16 + Mul16 = 0x5, + /// PLL clock entry x 24 + Mul24 = 0x6, + /// PLL clock entry x 32 + Mul32 = 0x7, + /// PLL clock entry x 48 + Mul48 = 0x8, + _, + }; + + pub const PLLSRC = enum(u1) { + /// HSI selected as PLL input clock + HSI = 0x0, + /// HSE selected as PLL input clock + HSE = 0x1, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const RTCPRE = enum(u2) { + /// HSE divided by 2 + Div2 = 0x0, + /// HSE divided by 4 + Div4 = 0x1, + /// HSE divided by 8 + Div8 = 0x2, + /// HSE divided by 16 + Div16 = 0x3, + }; + + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock + HSE = 0x3, + }; + + pub const SW = enum(u2) { + /// MSI oscillator used as system clock + MSI = 0x0, + /// HSI oscillator used as system clock + HSI = 0x1, + /// HSE oscillator used as system clock + HSE = 0x2, + /// PLL used as system clock + PLL1_R = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal high-speed clock enable + HSION: u1, + /// Internal high-speed clock ready flag + HSIRDY: u1, + reserved8: u6, + /// MSI clock enable + MSION: u1, + /// MSI clock ready flag + MSIRDY: u1, + reserved16: u6, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + reserved24: u5, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + reserved28: u2, + /// Clock security system enable + CSSON: u1, + /// RTC/LCD prescaler + RTCPRE: packed union { + raw: u2, + value: RTCPRE, + }, + padding: u1, + }), + /// Internal clock sources calibration register + ICSCR: mmio.Mmio(packed struct(u32) { + /// nternal high speed clock calibration + HSICAL: u8, + /// High speed internal clock trimming + HSITRIM: u5, + /// MSI clock ranges + MSIRANGE: packed union { + raw: u3, + value: MSIRANGE, + }, + /// MSI clock calibration + MSICAL: u8, + /// MSI clock trimming + MSITRIM: u8, + }), + /// Clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u2, + value: SW, + }, + /// System clock switch status + SWS: packed union { + raw: u2, + value: SW, + }, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// APB low-speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + /// APB high-speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + reserved16: u2, + /// PLL entry clock source + PLLSRC: packed union { + raw: u1, + value: PLLSRC, + }, + reserved18: u1, + /// PLL multiplication factor + PLLMUL: packed union { + raw: u4, + value: PLLMUL, + }, + /// PLL output division + PLLDIV: packed union { + raw: u2, + value: PLLDIV, + }, + /// Microcontroller clock output selection + MCOSEL: packed union { + raw: u3, + value: MCOSEL, + }, + reserved28: u1, + /// Microcontroller clock output prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, + }, + padding: u1, + }), + /// Clock interrupt register + CIR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// PLL ready interrupt flag + PLLRDYF: u1, + /// MSI ready interrupt flag + MSIRDYF: u1, + reserved7: u1, + /// Clock security system interrupt flag + CSSF: u1, + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// PLL ready interrupt enable + PLLRDYIE: u1, + /// MSI ready interrupt enable + MSIRDYIE: u1, + reserved16: u2, + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// PLL ready interrupt clear + PLLRDYC: u1, + /// MSI ready interrupt clear + MSIRDYC: u1, + reserved23: u1, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, + }), + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port H reset + GPIOHRST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + reserved12: u4, + /// CRC reset + CRCRST: u1, + reserved15: u2, + /// FLASH reset + FLASHRST: u1, + reserved24: u8, + /// DMA1 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + reserved30: u4, + /// FSMC reset + FSMCRST: u1, + padding: u1, + }), + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// SYSCFGRST + SYSCFGRST: u1, + reserved2: u1, + /// TIM9RST + TIM9RST: u1, + /// TM10RST + TM10RST: u1, + /// TM11RST + TM11RST: u1, + reserved9: u4, + /// ADC1RST + ADC1RST: u1, + reserved11: u1, + /// SDIORST + SDIORST: u1, + /// SPI1RST + SPI1RST: u1, + reserved14: u1, + /// USART1RST + USART1RST: u1, + padding: u17, + }), + /// APB1 peripheral reset register + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + /// Timer 4 reset + TIM4RST: u1, + /// Timer 5 reset + TIM5RST: u1, + /// Timer 6reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + reserved9: u3, + /// LCD reset + LCDRST: u1, + reserved11: u1, + /// Window watchdog reset + WWDRST: u1, + reserved14: u2, + /// SPI 2 reset + SPI2RST: u1, + /// SPI 3 reset + SPI3RST: u1, + reserved17: u1, + /// USART 2 reset + USART2RST: u1, + /// USART 3 reset + USART3RST: u1, + /// UART 4 reset + UART4RST: u1, + /// UART 5 reset + UART5RST: u1, + /// I2C 1 reset + I2C1RST: u1, + /// I2C 2 reset + I2C2RST: u1, + /// USB reset + USBRST: u1, + reserved28: u4, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + reserved31: u1, + /// COMP interface reset + COMPRST: u1, + }), + /// AHB peripheral clock enable register + AHBENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port H clock enable + GPIOHEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + reserved12: u4, + /// CRC clock enable + CRCEN: u1, + reserved15: u2, + /// FLASH clock enable + FLASHEN: u1, + reserved24: u8, + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + reserved30: u4, + /// FSMCEN + FSMCEN: u1, + padding: u1, + }), + /// APB2 peripheral clock enable register + APB2ENR: mmio.Mmio(packed struct(u32) { + /// System configuration controller clock enable + SYSCFGEN: u1, + reserved2: u1, + /// TIM9 timer clock enable + TIM9EN: u1, + /// TIM10 timer clock enable + TIM10EN: u1, + /// TIM11 timer clock enable + TIM11EN: u1, + reserved9: u4, + /// ADC1 interface clock enable + ADC1EN: u1, + reserved11: u1, + /// SDIO clock enable + SDIOEN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + reserved14: u1, + /// USART1 clock enable + USART1EN: u1, + padding: u17, + }), + /// APB1 peripheral clock enable register + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + /// Timer 4 clock enable + TIM4EN: u1, + /// Timer 5 clock enable + TIM5EN: u1, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + reserved9: u3, + /// LCD clock enable + LCDEN: u1, + reserved11: u1, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI 2 clock enable + SPI2EN: u1, + /// SPI 3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART 3 clock enable + USART3EN: u1, + /// UART 4 clock enable + USART4EN: u1, + /// UART 5 clock enable + USART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB clock enable + USBEN: u1, + reserved28: u4, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + reserved31: u1, + /// COMP interface clock enable + COMPEN: u1, + }), + /// AHB peripheral clock enable in low power mode register + AHBLPENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable during Sleep mode + GPIOALPEN: u1, + /// IO port B clock enable during Sleep mode + GPIOBLPEN: u1, + /// IO port C clock enable during Sleep mode + GPIOCLPEN: u1, + /// IO port D clock enable during Sleep mode + GPIODLPEN: u1, + /// IO port E clock enable during Sleep mode + GPIOELPEN: u1, + /// IO port H clock enable during Sleep mode + GPIOHLPEN: u1, + /// IO port F clock enable during Sleep mode + GPIOFLPEN: u1, + /// IO port G clock enable during Sleep mode + GPIOGLPEN: u1, + reserved12: u4, + /// CRC clock enable during Sleep mode + CRCLPEN: u1, + reserved15: u2, + /// FLASH clock enable during Sleep mode + FLASHLPEN: u1, + /// SRAM clock enable during Sleep mode + SRAMLPEN: u1, + reserved24: u7, + /// DMA1 clock enable during Sleep mode + DMA1LPEN: u1, + /// DMA2 clock enable during Sleep mode + DMA2LPEN: u1, + padding: u6, + }), + /// APB2 peripheral clock enable in low power mode register + APB2LPENR: mmio.Mmio(packed struct(u32) { + /// System configuration controller clock enable during Sleep mode + SYSCFGLPEN: u1, + reserved2: u1, + /// TIM9 timer clock enable during Sleep mode + TIM9LPEN: u1, + /// TIM10 timer clock enable during Sleep mode + TIM10LPEN: u1, + /// TIM11 timer clock enable during Sleep mode + TIM11LPEN: u1, + reserved9: u4, + /// ADC1 interface clock enable during Sleep mode + ADC1LPEN: u1, + reserved11: u1, + /// SDIO clock enable during Sleep mode + SDIOLPEN: u1, + /// SPI 1 clock enable during Sleep mode + SPI1LPEN: u1, + reserved14: u1, + /// USART1 clock enable during Sleep mode + USART1LPEN: u1, + padding: u17, + }), + /// APB1 peripheral clock enable in low power mode register + APB1LPENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable during Sleep mode + TIM2LPEN: u1, + /// Timer 3 clock enable during Sleep mode + TIM3LPEN: u1, + /// Timer 4 clock enable during Sleep mode + TIM4LPEN: u1, + reserved4: u1, + /// Timer 6 clock enable during Sleep mode + TIM6LPEN: u1, + /// Timer 7 clock enable during Sleep mode + TIM7LPEN: u1, + reserved9: u3, + /// LCD clock enable during Sleep mode + LCDLPEN: u1, + reserved11: u1, + /// Window watchdog clock enable during Sleep mode + WWDGLPEN: u1, + reserved14: u2, + /// SPI 2 clock enable during Sleep mode + SPI2LPEN: u1, + reserved17: u2, + /// USART 2 clock enable during Sleep mode + USART2LPEN: u1, + /// USART 3 clock enable during Sleep mode + USART3LPEN: u1, + reserved21: u2, + /// I2C 1 clock enable during Sleep mode + I2C1LPEN: u1, + /// I2C 2 clock enable during Sleep mode + I2C2LPEN: u1, + /// USB clock enable during Sleep mode + USBLPEN: u1, + reserved28: u4, + /// Power interface clock enable during Sleep mode + PWRLPEN: u1, + /// DAC interface clock enable during Sleep mode + DACLPEN: u1, + reserved31: u1, + /// COMP interface clock enable during Sleep mode + COMPLPEN: u1, + }), + /// Control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low-speed oscillator enable + LSION: u1, + /// Internal low-speed oscillator ready + LSIRDY: u1, + reserved8: u6, + /// External low-speed oscillator enable + LSEON: u1, + /// External low-speed oscillator ready + LSERDY: u1, + /// External low-speed oscillator bypass + LSEBYP: u1, + reserved16: u5, + /// RTC and LCD clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved22: u4, + /// RTC clock enable + RTCEN: u1, + /// RTC software reset + RTCRST: u1, + /// Remove reset flag + RMVF: u1, + reserved26: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + }; + }; + + pub const rcc_l4 = struct { + pub const ADCSEL = enum(u2) { + /// No clock selected + DISABLE = 0x0, + /// PLLADC1CLK clock selected + PLL1_Q = 0x1, + /// SYSCLK clock selected + SYS = 0x3, + _, + }; + + pub const CLK48SEL = enum(u2) { + /// HSI48 clock selected (only for STM32L41x/L42x/L43x/L44x/L45x/L46x/L49x/L4Ax devices, otherwise no clock selected) + HSI48 = 0x0, + /// PLLSAI1_Q aka PLL48M1CLK clock selected + PLLSAI1_Q = 0x1, + /// PLL_Q aka PLL48M2CLK clock selected + PLL1_Q = 0x2, + /// MSI clock selected + MSI = 0x3, + }; + + pub const DFSDMSEL = enum(u1) { + /// APB2 clock (PCLK2) selected as DFSDM kernel clock + PCLK2 = 0x0, + /// System clock selected as DFSDM kernel clock + SYS = 0x1, + }; + + pub const HPRE = enum(u4) { + /// system clock not divided + Div1 = 0x0, + /// system clock divided by 2 + Div2 = 0x8, + /// system clock divided by 4 + Div4 = 0x9, + /// system clock divided by 8 + Div8 = 0xa, + /// system clock divided by 16 + Div16 = 0xb, + /// system clock divided by 64 + Div64 = 0xc, + /// system clock divided by 128 + Div128 = 0xd, + /// system clock divided by 256 + Div256 = 0xe, + /// system clock divided by 512 + Div512 = 0xf, + _, + }; + + pub const I2C1SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + _, + }; + + pub const I2C2SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + _, + }; + + pub const I2C3SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + _, + }; + + pub const LPTIM1SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// LSI clock selected + LSI = 0x1, + /// HSI clock selected + HSI = 0x2, + /// LSE clock selected + LSE = 0x3, + }; + + pub const LPTIM2SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// LSI clock selected + LSI = 0x1, + /// HSI clock selected + HSI = 0x2, + /// LSE clock selected + LSE = 0x3, + }; + + pub const LPUART1SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + /// LSE clock selected + LSE = 0x3, + }; + + pub const LSCOSEL = enum(u1) { + /// LSI clock selected + LSI = 0x0, + /// LSE clock selected + LSE = 0x1, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const MCOPRE = enum(u3) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x1, + /// Division by 4 + Div4 = 0x2, + /// Division by 8 + Div8 = 0x3, + /// Division by 16 + Div16 = 0x4, + _, + }; + + pub const MCOSEL = enum(u4) { + /// No clock + DISABLE = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// MSI oscillator clock selected + MSI = 0x2, + /// HSI oscillator clock selected + HSI = 0x3, + /// HSE oscillator clock selected + HSE = 0x4, + /// PLL clock selected + PLL = 0x5, + /// LSI oscillator clock selected + LSI = 0x6, + /// LSE oscillator clock selected + LSE = 0x7, + /// HSI48 oscillator clock selected + HSI48 = 0x8, + _, + }; + + pub const MSIRANGE = enum(u4) { + /// range 0 around 100 kHz + Range100K = 0x0, + /// range 1 around 200 kHz + Range200K = 0x1, + /// range 2 around 400 kHz + Range400K = 0x2, + /// range 3 around 800 kHz + Range800K = 0x3, + /// range 4 around 1 MHz + Range1M = 0x4, + /// range 5 around 2 MHz + Range2M = 0x5, + /// range 6 around 4 MHz + Range4M = 0x6, + /// range 7 around 8 MHz + Range8M = 0x7, + /// range 8 around 16 MHz + Range16M = 0x8, + /// range 9 around 24 MHz + Range24M = 0x9, + /// range 10 around 32 MHz + Range32M = 0xa, + /// range 11 around 48 MHz + Range48M = 0xb, + _, + }; + + pub const MSIRGSEL = enum(u1) { + /// MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register + CSR = 0x0, + /// MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register + CR = 0x1, + }; + + pub const PLLM = enum(u3) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + }; + + pub const PLLN = enum(u7) { + Mul8 = 0x8, + Mul9 = 0x9, + Mul10 = 0xa, + Mul11 = 0xb, + Mul12 = 0xc, + Mul13 = 0xd, + Mul14 = 0xe, + Mul15 = 0xf, + Mul16 = 0x10, + Mul17 = 0x11, + Mul18 = 0x12, + Mul19 = 0x13, + Mul20 = 0x14, + Mul21 = 0x15, + Mul22 = 0x16, + Mul23 = 0x17, + Mul24 = 0x18, + Mul25 = 0x19, + Mul26 = 0x1a, + Mul27 = 0x1b, + Mul28 = 0x1c, + Mul29 = 0x1d, + Mul30 = 0x1e, + Mul31 = 0x1f, + Mul32 = 0x20, + Mul33 = 0x21, + Mul34 = 0x22, + Mul35 = 0x23, + Mul36 = 0x24, + Mul37 = 0x25, + Mul38 = 0x26, + Mul39 = 0x27, + Mul40 = 0x28, + Mul41 = 0x29, + Mul42 = 0x2a, + Mul43 = 0x2b, + Mul44 = 0x2c, + Mul45 = 0x2d, + Mul46 = 0x2e, + Mul47 = 0x2f, + Mul48 = 0x30, + Mul49 = 0x31, + Mul50 = 0x32, + Mul51 = 0x33, + Mul52 = 0x34, + Mul53 = 0x35, + Mul54 = 0x36, + Mul55 = 0x37, + Mul56 = 0x38, + Mul57 = 0x39, + Mul58 = 0x3a, + Mul59 = 0x3b, + Mul60 = 0x3c, + Mul61 = 0x3d, + Mul62 = 0x3e, + Mul63 = 0x3f, + Mul64 = 0x40, + Mul65 = 0x41, + Mul66 = 0x42, + Mul67 = 0x43, + Mul68 = 0x44, + Mul69 = 0x45, + Mul70 = 0x46, + Mul71 = 0x47, + Mul72 = 0x48, + Mul73 = 0x49, + Mul74 = 0x4a, + Mul75 = 0x4b, + Mul76 = 0x4c, + Mul77 = 0x4d, + Mul78 = 0x4e, + Mul79 = 0x4f, + Mul80 = 0x50, + Mul81 = 0x51, + Mul82 = 0x52, + Mul83 = 0x53, + Mul84 = 0x54, + Mul85 = 0x55, + Mul86 = 0x56, + Mul87 = 0x57, + Mul88 = 0x58, + Mul89 = 0x59, + Mul90 = 0x5a, + Mul91 = 0x5b, + Mul92 = 0x5c, + Mul93 = 0x5d, + Mul94 = 0x5e, + Mul95 = 0x5f, + Mul96 = 0x60, + Mul97 = 0x61, + Mul98 = 0x62, + Mul99 = 0x63, + Mul100 = 0x64, + Mul101 = 0x65, + Mul102 = 0x66, + Mul103 = 0x67, + Mul104 = 0x68, + Mul105 = 0x69, + Mul106 = 0x6a, + Mul107 = 0x6b, + Mul108 = 0x6c, + Mul109 = 0x6d, + Mul110 = 0x6e, + Mul111 = 0x6f, + Mul112 = 0x70, + Mul113 = 0x71, + Mul114 = 0x72, + Mul115 = 0x73, + Mul116 = 0x74, + Mul117 = 0x75, + Mul118 = 0x76, + Mul119 = 0x77, + Mul120 = 0x78, + Mul121 = 0x79, + Mul122 = 0x7a, + Mul123 = 0x7b, + Mul124 = 0x7c, + Mul125 = 0x7d, + Mul126 = 0x7e, + Mul127 = 0x7f, + _, + }; + + pub const PLLP = enum(u5) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + Div16 = 0x10, + Div17 = 0x11, + Div18 = 0x12, + Div19 = 0x13, + Div20 = 0x14, + Div21 = 0x15, + Div22 = 0x16, + Div23 = 0x17, + Div24 = 0x18, + Div25 = 0x19, + Div26 = 0x1a, + Div27 = 0x1b, + Div28 = 0x1c, + Div29 = 0x1d, + Div30 = 0x1e, + Div31 = 0x1f, + _, + }; + + pub const PLLPBIT = enum(u1) { + Div7 = 0x0, + Div17 = 0x1, + }; + + pub const PLLQ = enum(u2) { + Div2 = 0x0, + Div4 = 0x1, + Div6 = 0x2, + Div8 = 0x3, + }; + + pub const PLLR = enum(u2) { + Div2 = 0x0, + Div4 = 0x1, + Div6 = 0x2, + Div8 = 0x3, + }; + + pub const PLLSRC = enum(u2) { + /// No clock sent to PLL + DISABLE = 0x0, + /// MSI selected as PLL input clock + MSI = 0x1, + /// HSI selected as PLL input clock + HSI = 0x2, + /// HSE selected as PLL input clock + HSE = 0x3, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by 32 used as the RTC clock + HSE = 0x3, + }; + + pub const SAI1SEL = enum(u2) { + /// PLLSAI1CLK clock is selected as SAIx clock + PLLSAI1_P = 0x0, + /// PLLSAI2CLK clock is selected as SAIx clock + PLLSAI2_P = 0x1, + /// PLLSAI3CLK clock is selected as SAIx clock + PLL1_P = 0x2, + /// External clock SAIx_EXTCLK clock selected as SAIx clock + SAI1_EXTCLK = 0x3, + }; + + pub const SAI2SEL = enum(u2) { + /// PLLSAI1CLK clock is selected as SAIx clock + PLLSAI1_P = 0x0, + /// PLLSAI2CLK clock is selected as SAIx clock + PLLSAI2_P = 0x1, + /// PLLSAI3CLK clock is selected as SAIx clock + PLL1_P = 0x2, + /// External clock SAIx_EXTCLK clock selected as SAIx clock + SAI2_EXTCLK = 0x3, + }; + + pub const STOPWUCK = enum(u1) { + /// MSI oscillator selected as wake-up from Stop clock + MSI = 0x0, + /// HSI oscillator selected as wake-up from Stop clock + HSI = 0x1, + }; + + pub const SW = enum(u2) { + /// MSI selected as system clock + MSI = 0x0, + /// HSI selected as system clock + HSI = 0x1, + /// HSE selected as system clock + HSE = 0x2, + /// PLL selected as system clock + PLL1_R = 0x3, + }; + + pub const SWPMI1SEL = enum(u1) { + PCLK1 = 0x0, + HSI = 0x1, + }; + + pub const USART1SEL = enum(u2) { + /// PCLK clock selected + PCLK2 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + /// LSE clock selected + LSE = 0x3, + }; + + pub const USARTSEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + /// LSE clock selected + LSE = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// MSI clock enable + MSION: u1, + /// MSI clock ready flag + MSIRDY: u1, + /// MSI clock PLL enable + MSIPLLEN: u1, + /// MSI clock range selection + MSIRGSEL: packed union { + raw: u1, + value: MSIRGSEL, + }, + /// MSI clock ranges + MSIRANGE: packed union { + raw: u4, + value: MSIRANGE, + }, + /// HSI clock enable + HSION: u1, + /// HSI always enable for peripheral kernels + HSIKERON: u1, + /// HSI clock ready flag + HSIRDY: u1, + /// HSI automatic start from Stop + HSIASFS: u1, + reserved16: u4, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE crystal oscillator bypass + HSEBYP: u1, + /// Clock security system enable + CSSON: u1, + reserved24: u4, + /// Main PLL enable + PLLON: u1, + /// Main PLL clock ready flag + PLLRDY: u1, + /// SAI1 PLL enable + PLLSAI1ON: u1, + /// SAI1 PLL clock ready flag + PLLSAI1RDY: u1, + /// SAI2 PLL enable + PLLSAI2ON: u1, + /// SAI2 PLL clock ready flag + PLLSAI2RDY: u1, + padding: u2, + }), + /// Internal clock sources calibration register + ICSCR: mmio.Mmio(packed struct(u32) { + /// MSI clock calibration + MSICAL: u8, + /// MSI clock trimming + MSITRIM: u8, + /// HSI clock calibration + HSICAL: u8, + /// HSI clock trimming + HSITRIM: u7, + padding: u1, + }), + /// Clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u2, + value: SW, + }, + /// System clock switch status + SWS: packed union { + raw: u2, + value: SW, + }, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// APB low-speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + /// APB high-speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + reserved15: u1, + /// Wakeup from Stop and CSS backup clock selection + STOPWUCK: packed union { + raw: u1, + value: STOPWUCK, + }, + reserved24: u8, + /// Microcontroller clock output selection + MCOSEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// Microcontroller clock output prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, + }, + padding: u1, + }), + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// Main PLL, PLLSAI1 and PLLSAI2 entry clock source + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + reserved4: u2, + /// Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + PLLM: packed union { + raw: u3, + value: PLLM, + }, + reserved8: u1, + /// Main PLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, + }, + reserved16: u1, + /// Main PLL PLLSAI3CLK output enable + PLLPEN: u1, + /// Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + PLLPBIT: packed union { + raw: u1, + value: PLLPBIT, + }, + reserved20: u2, + /// Main PLL PLLUSB1CLK output enable + PLLQEN: u1, + /// Main PLL division factor for PLLUSB1CLK(48 MHz clock) + PLLQ: packed union { + raw: u2, + value: PLLQ, + }, + reserved24: u1, + /// Main PLL PLLCLK output enable + PLLREN: u1, + /// Main PLL division factor for PLLCLK (system clock) + PLLR: packed union { + raw: u2, + value: PLLR, + }, + /// Main PLL division factor for PLLSAI2CLK + PLLP: packed union { + raw: u5, + value: PLLP, + }, + }), + /// PLLSAI1 configuration register + PLLSAI1CFGR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// SAI1PLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, + }, + reserved16: u1, + /// SAI1PLL PLLSAICLK output enable + PLLPEN: u1, + /// SAI1PLL division factor for PLLSAICLK + PLLPBIT: packed union { + raw: u1, + value: PLLPBIT, + }, + reserved20: u2, + /// SAI1PLL PLLUSB2CLK output enable + PLLQEN: u1, + /// SAI1PLL division factor for PLLUSB2CLK + PLLQ: packed union { + raw: u2, + value: PLLQ, + }, + reserved24: u1, + /// PLLSAI PLLADC1CLK output enable + PLLREN: u1, + /// PLLSAI division factor for PLLADC1CLK + PLLR: packed union { + raw: u2, + value: PLLR, + }, + /// PLLSAI division factor for PLLSAICLK + PLLP: packed union { + raw: u5, + value: PLLP, + }, + }), + /// PLLSAI2 configuration register + PLLSAI2CFGR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// SAI1PLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, + }, + reserved16: u1, + /// SAI1PLL PLLSAICLK output enable + PLLPEN: u1, + /// SAI1PLL division factor for PLLSAICLK + PLLPBIT: packed union { + raw: u1, + value: PLLPBIT, + }, + reserved20: u2, + /// SAI1PLL PLLUSB2CLK output enable + PLLQEN: u1, + /// SAI1PLL division factor for PLLUSB2CLK + PLLQ: packed union { + raw: u2, + value: PLLQ, + }, + reserved24: u1, + /// PLLSAI PLLADC1CLK output enable + PLLREN: u1, + /// PLLSAI division factor for PLLADC1CLK + PLLR: packed union { + raw: u2, + value: PLLR, + }, + /// PLLSAI division factor for PLLSAICLK + PLLP: packed union { + raw: u5, + value: PLLP, + }, + }), + /// Clock interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// MSI ready interrupt enable + MSIRDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// PLL ready interrupt enable + PLLRDYIE: u1, + /// PLLSAI1 ready interrupt enable + PLLSAI1RDYIE: u1, + /// PLLSAI2 ready interrupt enable + PLLSAI2RDYIE: u1, + reserved9: u1, + /// LSE clock security system interrupt enable + LSECSSIE: u1, + /// HSI48 ready interrupt enable + HSI48RDYIE: u1, + padding: u21, + }), + /// Clock interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// MSI ready interrupt flag + MSIRDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// PLL ready interrupt flag + PLLRDYF: u1, + /// PLLSAI1 ready interrupt flag + PLLSAI1RDYF: u1, + /// PLLSAI2 ready interrupt flag + PLLSAI2RDYF: u1, + /// Clock security system interrupt flag + CSSF: u1, + /// LSE Clock security system interrupt flag + LSECSSF: u1, + /// HSI48 ready interrupt flag + HSI48RDYF: u1, + padding: u21, + }), + /// Clock interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// MSI ready interrupt clear + MSIRDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// PLL ready interrupt clear + PLLRDYC: u1, + /// PLLSAI1 ready interrupt clear + PLLSAI1RDYC: u1, + /// PLLSAI2 ready interrupt clear + PLLSAI2RDYC: u1, + /// Clock security system interrupt clear + CSSC: u1, + /// LSE Clock security system interrupt clear + LSECSSC: u1, + /// HSI48 oscillator ready interrupt clear + HSI48RDYC: u1, + padding: u21, + }), + reserved40: [4]u8, + /// AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// DMA1 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + reserved8: u6, + /// Flash memory interface reset + FLASHRST: u1, + reserved12: u3, + /// CRC reset + CRCRST: u1, + reserved16: u3, + /// Touch Sensing Controller reset + TSCRST: u1, + /// DMA2D reset + DMA2DRST: u1, + padding: u14, + }), + /// AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// IO port H reset + GPIOHRST: u1, + /// IO port I reset + GPIOIRST: u1, + reserved12: u3, + /// USB OTG FS reset + USB_OTG_FSRST: u1, + /// ADC reset + ADCRST: u1, + /// Digital Camera Interface reset + DCMIRST: u1, + reserved16: u1, + /// AES hardware accelerator reset + AESRST: u1, + /// Hash reset + HASHRST: u1, + /// Random number generator reset + RNGRST: u1, + padding: u13, + }), + /// AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller reset + FMCRST: u1, + reserved8: u7, + /// Quad SPI memory interface reset + QUADSPIRST: u1, + padding: u23, + }), + reserved56: [4]u8, + /// APB1 peripheral reset register 1 + APB1RSTR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer reset + TIM2RST: u1, + /// TIM3 timer reset + TIM3RST: u1, + /// TIM3 timer reset + TIM4RST: u1, + /// TIM5 timer reset + TIM5RST: u1, + /// TIM6 timer reset + TIM6RST: u1, + /// TIM7 timer reset + TIM7RST: u1, + reserved9: u3, + /// LCD interface reset + LCDRST: u1, + reserved14: u4, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved17: u1, + /// USART2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// UART4 reset + UART4RST: u1, + /// UART5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// I2C3 reset + I2C3RST: u1, + /// CRS reset + CRSRST: u1, + /// CAN1 reset + CAN1RST: u1, + /// CAN2 reset + CAN2RST: u1, + reserved28: u1, + /// Power interface reset + PWRRST: u1, + /// DAC1 interface reset + DAC1RST: u1, + /// OPAMP interface reset + OPAMPRST: u1, + /// Low Power Timer 1 reset + LPTIM1RST: u1, + }), + /// APB1 peripheral reset register 2 + APB1RSTR2: mmio.Mmio(packed struct(u32) { + /// Low-power UART 1 reset + LPUART1RST: u1, + /// I2C4 reset + I2C4RST: u1, + /// Single wire protocol reset + SWPMI1RST: u1, + reserved5: u2, + /// Low-power timer 2 reset + LPTIM2RST: u1, + padding: u26, + }), + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// System configuration (SYSCFG) reset + SYSCFGRST: u1, + reserved10: u9, + /// SDMMC reset + SDMMCRST: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + reserved16: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + reserved21: u2, + /// Serial audio interface 1 (SAI1) reset + SAI1RST: u1, + /// Serial audio interface 2 (SAI2) reset + SAI2RST: u1, + reserved24: u1, + /// DFSDM filter reset + DFSDMRST: u1, + padding: u7, + }), + reserved72: [4]u8, + /// AHB1 peripheral clock enable register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + reserved8: u6, + /// Flash memory interface clock enable + FLASHEN: u1, + reserved12: u3, + /// CRC clock enable + CRCEN: u1, + reserved16: u3, + /// Touch Sensing Controller clock enable + TSCEN: u1, + /// DMA2D clock enable + DMA2DEN: u1, + padding: u14, + }), + /// AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// IO port H clock enable + GPIOHEN: u1, + /// IO port I clock enable + GPIOIEN: u1, + reserved12: u3, + /// OTG full speed clock enable + USB_OTG_FSEN: u1, + /// ADC clock enable + ADCEN: u1, + /// DCMI clock enable + DCMIEN: u1, + reserved16: u1, + /// AES accelerator clock enable + AESEN: u1, + /// HASH clock enable + HASHEN: u1, + /// Random Number Generator clock enable + RNGEN: u1, + padding: u13, + }), + /// AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller clock enable + FMCEN: u1, + reserved8: u7, + /// QUADSPIEN + QUADSPIEN: u1, + padding: u23, + }), + reserved88: [4]u8, + /// APB1ENR1 + APB1ENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clock enable + TIM2EN: u1, + /// TIM3 timer clock enable + TIM3EN: u1, + /// TIM4 timer clock enable + TIM4EN: u1, + /// TIM5 timer clock enable + TIM5EN: u1, + /// TIM6 timer clock enable + TIM6EN: u1, + /// TIM7 timer clock enable + TIM7EN: u1, + reserved9: u3, + /// LCD clock enable + LCDEN: u1, + /// RTC APB clock enable + RTCAPBEN: u1, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI2 clock enable + SPI2EN: u1, + /// SPI3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// I2C3 clock enable + I2C3EN: u1, + /// Clock Recovery System clock enable + CRSEN: u1, + /// CAN1 clock enable + CAN1EN: u1, + /// CAN2 clock enable + CAN2EN: u1, + reserved28: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC1 interface clock enable + DAC1EN: u1, + /// OPAMP interface clock enable + OPAMPEN: u1, + /// Low power timer 1 clock enable + LPTIM1EN: u1, + }), + /// APB1 peripheral clock enable register 2 + APB1ENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clock enable + LPUART1EN: u1, + /// I2C4 clock enable + I2C4EN: u1, + /// Single wire protocol clock enable + SWPMI1EN: u1, + reserved5: u2, + /// LPTIM2EN + LPTIM2EN: u1, + padding: u26, + }), + /// APB2ENR + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved7: u6, + /// Firewall clock enable + FWEN: u1, + reserved10: u2, + /// SDMMC clock enable + SDMMCEN: u1, + /// TIM1 timer clock enable + TIM1EN: u1, + /// SPI1 clock enable + SPI1EN: u1, + /// TIM8 timer clock enable + TIM8EN: u1, + /// USART1clock enable + USART1EN: u1, + reserved16: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + reserved21: u2, + /// SAI1 clock enable + SAI1EN: u1, + /// SAI2 clock enable + SAI2EN: u1, + reserved24: u1, + /// DFSDMEN enable + DFSDMEN: u1, + padding: u7, + }), + reserved104: [4]u8, + /// AHB1 peripheral clocks enable in Sleep and Stop modes register + AHB1SMENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clocks enable during Sleep and Stop modes + DMA1SMEN: u1, + /// DMA2 clocks enable during Sleep and Stop modes + DMA2SMEN: u1, + reserved8: u6, + /// Flash memory interface clocks enable during Sleep and Stop modes + FLASHSMEN: u1, + /// SRAM1 interface clocks enable during Sleep and Stop modes + SRAM1SMEN: u1, + reserved12: u2, + /// CRCSMEN + CRCSMEN: u1, + reserved16: u3, + /// Touch Sensing Controller clocks enable during Sleep and Stop modes + TSCSMEN: u1, + /// DMA2D clock enable during Sleep and Stop modes + DMA2DSMEN: u1, + padding: u14, + }), + /// AHB2 peripheral clocks enable in Sleep and Stop modes register + AHB2SMENR: mmio.Mmio(packed struct(u32) { + /// IO port A clocks enable during Sleep and Stop modes + GPIOASMEN: u1, + /// IO port B clocks enable during Sleep and Stop modes + GPIOBSMEN: u1, + /// IO port C clocks enable during Sleep and Stop modes + GPIOCSMEN: u1, + /// IO port D clocks enable during Sleep and Stop modes + GPIODSMEN: u1, + /// IO port E clocks enable during Sleep and Stop modes + GPIOESMEN: u1, + /// IO port F clocks enable during Sleep and Stop modes + GPIOFSMEN: u1, + /// IO port G clocks enable during Sleep and Stop modes + GPIOGSMEN: u1, + /// IO port H clocks enable during Sleep and Stop modes + GPIOHSMEN: u1, + /// IO port I clocks enable during Sleep and Stop modes + GPIOISMEN: u1, + /// SRAM2 interface clocks enable during Sleep and Stop modes + SRAM2SMEN: u1, + reserved12: u2, + /// OTG full speed clocks enable during Sleep and Stop modes + USB_OTG_FSSMEN: u1, + /// ADC clocks enable during Sleep and Stop modes + ADCFSSMEN: u1, + /// DCMI clock enable during Sleep and Stop modes + DCMISMEN: u1, + reserved16: u1, + /// AES accelerator clocks enable during Sleep and Stop modes + AESSMEN: u1, + /// HASH clock enable during Sleep and Stop modes + HASHSMEN: u1, + /// Random Number Generator clocks enable during Sleep and Stop modes + RNGSMEN: u1, + padding: u13, + }), + /// AHB3 peripheral clocks enable in Sleep and Stop modes register + AHB3SMENR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller clocks enable during Sleep and Stop modes + FMCSMEN: u1, + reserved8: u7, + /// QUADSPISMEN + QUADSPISMEN: u1, + padding: u23, + }), + reserved120: [4]u8, + /// APB1SMENR1 + APB1SMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clocks enable during Sleep and Stop modes + TIM2SMEN: u1, + /// TIM3 timer clocks enable during Sleep and Stop modes + TIM3SMEN: u1, + /// TIM4 timer clocks enable during Sleep and Stop modes + TIM4SMEN: u1, + /// TIM5 timer clocks enable during Sleep and Stop modes + TIM5SMEN: u1, + /// TIM6 timer clocks enable during Sleep and Stop modes + TIM6SMEN: u1, + /// TIM7 timer clocks enable during Sleep and Stop modes + TIM7SMEN: u1, + reserved9: u3, + /// LCD clocks enable during Sleep and Stop modes + LCDSMEN: u1, + /// RTC APB clock enable during Sleep and Stop modes + RTCAPBSMEN: u1, + /// Window watchdog clocks enable during Sleep and Stop modes + WWDGSMEN: u1, + reserved14: u2, + /// SPI2 clocks enable during Sleep and Stop modes + SPI2SMEN: u1, + /// SPI3 clocks enable during Sleep and Stop modes + SP3SMEN: u1, + reserved17: u1, + /// USART2 clocks enable during Sleep and Stop modes + USART2SMEN: u1, + /// USART3 clocks enable during Sleep and Stop modes + USART3SMEN: u1, + /// UART4 clocks enable during Sleep and Stop modes + UART4SMEN: u1, + /// UART5 clocks enable during Sleep and Stop modes + UART5SMEN: u1, + /// I2C1 clocks enable during Sleep and Stop modes + I2C1SMEN: u1, + /// I2C2 clocks enable during Sleep and Stop modes + I2C2SMEN: u1, + /// I2C3 clocks enable during Sleep and Stop modes + I2C3SMEN: u1, + /// CRS clock enable during Sleep and Stop modes + CRSSMEN: u1, + /// CAN1 clocks enable during Sleep and Stop modes + CAN1SMEN: u1, + /// CAN2 clocks enable during Sleep and Stop modes + CAN2SMEN: u1, + reserved28: u1, + /// Power interface clocks enable during Sleep and Stop modes + PWRSMEN: u1, + /// DAC1 interface clocks enable during Sleep and Stop modes + DAC1SMEN: u1, + /// OPAMP interface clocks enable during Sleep and Stop modes + OPAMPSMEN: u1, + /// Low power timer 1 clocks enable during Sleep and Stop modes + LPTIM1SMEN: u1, + }), + /// APB1 peripheral clocks enable in Sleep and Stop modes register 2 + APB1SMENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clocks enable during Sleep and Stop modes + LPUART1SMEN: u1, + /// I2C4 clocks enable during Sleep and Stop modes + I2C4SMEN: u1, + /// Single wire protocol clocks enable during Sleep and Stop modes + SWPMI1SMEN: u1, + reserved5: u2, + /// LPTIM2SMEN + LPTIM2SMEN: u1, + padding: u26, + }), + /// APB2SMENR + APB2SMENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clocks enable during Sleep and Stop modes + SYSCFGSMEN: u1, + reserved10: u9, + /// SDMMC clocks enable during Sleep and Stop modes + SDMMCSMEN: u1, + /// TIM1 timer clocks enable during Sleep and Stop modes + TIM1SMEN: u1, + /// SPI1 clocks enable during Sleep and Stop modes + SPI1SMEN: u1, + /// TIM8 timer clocks enable during Sleep and Stop modes + TIM8SMEN: u1, + /// USART1clocks enable during Sleep and Stop modes + USART1SMEN: u1, + reserved16: u1, + /// TIM15 timer clocks enable during Sleep and Stop modes + TIM15SMEN: u1, + /// TIM16 timer clocks enable during Sleep and Stop modes + TIM16SMEN: u1, + /// TIM17 timer clocks enable during Sleep and Stop modes + TIM17SMEN: u1, + reserved21: u2, + /// SAI1 clocks enable during Sleep and Stop modes + SAI1SMEN: u1, + /// SAI2 clocks enable during Sleep and Stop modes + SAI2SMEN: u1, + reserved24: u1, + /// DFSDM timer clocks enable during Sleep and Stop modes + DFSDMSMEN: u1, + padding: u7, + }), + reserved136: [4]u8, + /// CCIPR + CCIPR: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SEL: packed union { + raw: u2, + value: USART1SEL, + }, + /// USART2 clock source selection + USART2SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// USART3 clock source selection + USART3SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// UART4 clock source selection + UART4SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// UART5 clock source selection + UART5SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// LPUART1 clock source selection + LPUART1SEL: packed union { + raw: u2, + value: LPUART1SEL, + }, + /// I2C1 clock source selection + I2C1SEL: packed union { + raw: u2, + value: I2C1SEL, + }, + /// I2C2 clock source selection + I2C2SEL: packed union { + raw: u2, + value: I2C2SEL, + }, + /// I2C3 clock source selection + I2C3SEL: packed union { + raw: u2, + value: I2C3SEL, + }, + /// Low power timer 1 clock source selection + LPTIM1SEL: packed union { + raw: u2, + value: LPTIM1SEL, + }, + /// Low power timer 2 clock source selection + LPTIM2SEL: packed union { + raw: u2, + value: LPTIM2SEL, + }, + /// SAI1 clock source selection + SAI1SEL: packed union { + raw: u2, + value: SAI1SEL, + }, + /// SAI2 clock source selection + SAI2SEL: packed union { + raw: u2, + value: SAI2SEL, + }, + /// 48 MHz clock source selection + CLK48SEL: packed union { + raw: u2, + value: CLK48SEL, + }, + /// ADCs clock source selection + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, + /// SWPMI1 clock source selection + SWPMI1SEL: packed union { + raw: u1, + value: SWPMI1SEL, + }, + /// DFSDM clock source selection + DFSDMSEL: packed union { + raw: u1, + value: DFSDMSEL, + }, + }), + reserved144: [4]u8, + /// BDCR + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enable + LSEON: u1, + /// LSE oscillator ready + LSERDY: u1, + /// LSE oscillator bypass + LSEBYP: u1, + /// SE oscillator drive capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// LSECSSON + LSECSSON: u1, + /// LSECSSD + LSECSSD: u1, + reserved8: u1, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + reserved24: u7, + /// Low speed clock output enable + LSCOEN: u1, + /// Low speed clock output selection + LSCOSEL: packed union { + raw: u1, + value: LSCOSEL, + }, + padding: u6, + }), + /// CSR + CSR: mmio.Mmio(packed struct(u32) { + /// LSI oscillator enable + LSION: u1, + /// LSI oscillator ready + LSIRDY: u1, + reserved8: u6, + /// SI range after Standby mode + MSISRANGE: u4, + reserved23: u11, + /// Remove reset flag + RMVF: u1, + /// Firewall reset flag + FWRSTF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// Pin reset flag + PINRSTF: u1, + /// BOR flag + BORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent window watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + /// Clock recovery RC register + CRRCR: mmio.Mmio(packed struct(u32) { + /// HSI48 clock enable + HSI48ON: u1, + /// HSI48 clock ready flag + HSI48RDY: u1, + reserved7: u5, + /// HSI48 clock calibration + HSI48CAL: u9, + padding: u16, + }), + }; + }; + + pub const rcc_l4plus = struct { + pub const ADCSEL = enum(u2) { + /// No clock selected + DISABLE = 0x0, + /// PLLADC1CLK clock selected + PLLSAI1_R = 0x1, + /// SYSCLK clock selected + SYS = 0x3, + _, + }; + + pub const ADFSDMSEL = enum(u2) { + /// SAI1clock selected as DFSDM audio clock + PLLSAI1_P = 0x0, + /// HSI clock selected as DFSDM audio clock + HSI = 0x1, + /// MSI clock selected as DFSDM audio clock + MSI = 0x2, + _, + }; + + pub const CLK48SEL = enum(u2) { + /// HSI48 clock selected + HSI48 = 0x0, + /// PLLSAI1_Q aka PLL48M1CLK clock selected + PLLSAI1_Q = 0x1, + /// PLL_Q aka PLL48M2CLK clock selected + PLL1_Q = 0x2, + /// MSI clock selected + MSI = 0x3, + }; + + pub const DFSDMSEL = enum(u1) { + /// APB2 clock (PCLK2) selected as DFSDM kernel clock + PCLK2 = 0x0, + /// System clock selected as DFSDM kernel clock + SYS = 0x1, + }; + + pub const DSISEL = enum(u1) { + /// DSI-PHY is selected as DSI byte lane clock source (usual case) + DSI_PHY = 0x0, + /// PLLDSICLK is selected as DSI byte lane clock source, used in case DSI PLL and DSIPHY are off (low-power mode) + PLLSAI2_Q = 0x1, + }; + + pub const HPRE = enum(u4) { + /// system clock not divided + Div1 = 0x0, + /// system clock divided by 2 + Div2 = 0x8, + /// system clock divided by 4 + Div4 = 0x9, + /// system clock divided by 8 + Div8 = 0xa, + /// system clock divided by 16 + Div16 = 0xb, + /// system clock divided by 64 + Div64 = 0xc, + /// system clock divided by 128 + Div128 = 0xd, + /// system clock divided by 256 + Div256 = 0xe, + /// system clock divided by 512 + Div512 = 0xf, + _, + }; + + pub const I2C1SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + _, + }; + + pub const I2C2SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + _, + }; + + pub const I2C3SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + _, + }; + + pub const I2C4SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + _, + }; + + pub const LPTIM1SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// LSI clock selected + LSI = 0x1, + /// HSI clock selected + HSI = 0x2, + /// LSE clock selected + LSE = 0x3, + }; + + pub const LPTIM2SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// LSI clock selected + LSI = 0x1, + /// HSI clock selected + HSI = 0x2, + /// LSE clock selected + LSE = 0x3, + }; + + pub const LPUART1SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + /// LSE clock selected + LSE = 0x3, + }; + + pub const LSCOSEL = enum(u1) { + /// LSI clock selected + LSI = 0x0, + /// LSE clock selected + LSE = 0x1, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const MCOPRE = enum(u3) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x1, + /// Division by 4 + Div4 = 0x2, + /// Division by 8 + Div8 = 0x3, + /// Division by 16 + Div16 = 0x4, + _, + }; + + pub const MCOSEL = enum(u4) { + /// No clock + DISABLE = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// MSI oscillator clock selected + MSI = 0x2, + /// HSI oscillator clock selected + HSI = 0x3, + /// HSE oscillator clock selected + HSE = 0x4, + /// PLL clock selected + PLL = 0x5, + /// LSI oscillator clock selected + LSI = 0x6, + /// LSE oscillator clock selected + LSE = 0x7, + /// HSI48 oscillator clock selected + HSI48 = 0x8, + _, + }; + + pub const MSIRANGE = enum(u4) { + /// range 0 around 100 kHz + Range100K = 0x0, + /// range 1 around 200 kHz + Range200K = 0x1, + /// range 2 around 400 kHz + Range400K = 0x2, + /// range 3 around 800 kHz + Range800K = 0x3, + /// range 4 around 1 MHz + Range1M = 0x4, + /// range 5 around 2 MHz + Range2M = 0x5, + /// range 6 around 4 MHz + Range4M = 0x6, + /// range 7 around 8 MHz + Range8M = 0x7, + /// range 8 around 16 MHz + Range16M = 0x8, + /// range 9 around 24 MHz + Range24M = 0x9, + /// range 10 around 32 MHz + Range32M = 0xa, + /// range 11 around 48 MHz + Range48M = 0xb, + _, + }; + + pub const MSIRGSEL = enum(u1) { + /// MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register + CSR = 0x0, + /// MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register + CR = 0x1, + }; + + pub const OCTOSPISEL = enum(u2) { + /// System clock selected as OctoSPI kernel clock + SYS = 0x0, + /// MSI clock selected as OctoSPI kernel clock + MSI = 0x1, + /// PLL48M1CLK clock selected as OctoSPI kernel clock + PLL1_Q = 0x2, + _, + }; + + pub const PLLM = enum(u4) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + }; + + pub const PLLN = enum(u7) { + Mul8 = 0x8, + Mul9 = 0x9, + Mul10 = 0xa, + Mul11 = 0xb, + Mul12 = 0xc, + Mul13 = 0xd, + Mul14 = 0xe, + Mul15 = 0xf, + Mul16 = 0x10, + Mul17 = 0x11, + Mul18 = 0x12, + Mul19 = 0x13, + Mul20 = 0x14, + Mul21 = 0x15, + Mul22 = 0x16, + Mul23 = 0x17, + Mul24 = 0x18, + Mul25 = 0x19, + Mul26 = 0x1a, + Mul27 = 0x1b, + Mul28 = 0x1c, + Mul29 = 0x1d, + Mul30 = 0x1e, + Mul31 = 0x1f, + Mul32 = 0x20, + Mul33 = 0x21, + Mul34 = 0x22, + Mul35 = 0x23, + Mul36 = 0x24, + Mul37 = 0x25, + Mul38 = 0x26, + Mul39 = 0x27, + Mul40 = 0x28, + Mul41 = 0x29, + Mul42 = 0x2a, + Mul43 = 0x2b, + Mul44 = 0x2c, + Mul45 = 0x2d, + Mul46 = 0x2e, + Mul47 = 0x2f, + Mul48 = 0x30, + Mul49 = 0x31, + Mul50 = 0x32, + Mul51 = 0x33, + Mul52 = 0x34, + Mul53 = 0x35, + Mul54 = 0x36, + Mul55 = 0x37, + Mul56 = 0x38, + Mul57 = 0x39, + Mul58 = 0x3a, + Mul59 = 0x3b, + Mul60 = 0x3c, + Mul61 = 0x3d, + Mul62 = 0x3e, + Mul63 = 0x3f, + Mul64 = 0x40, + Mul65 = 0x41, + Mul66 = 0x42, + Mul67 = 0x43, + Mul68 = 0x44, + Mul69 = 0x45, + Mul70 = 0x46, + Mul71 = 0x47, + Mul72 = 0x48, + Mul73 = 0x49, + Mul74 = 0x4a, + Mul75 = 0x4b, + Mul76 = 0x4c, + Mul77 = 0x4d, + Mul78 = 0x4e, + Mul79 = 0x4f, + Mul80 = 0x50, + Mul81 = 0x51, + Mul82 = 0x52, + Mul83 = 0x53, + Mul84 = 0x54, + Mul85 = 0x55, + Mul86 = 0x56, + Mul87 = 0x57, + Mul88 = 0x58, + Mul89 = 0x59, + Mul90 = 0x5a, + Mul91 = 0x5b, + Mul92 = 0x5c, + Mul93 = 0x5d, + Mul94 = 0x5e, + Mul95 = 0x5f, + Mul96 = 0x60, + Mul97 = 0x61, + Mul98 = 0x62, + Mul99 = 0x63, + Mul100 = 0x64, + Mul101 = 0x65, + Mul102 = 0x66, + Mul103 = 0x67, + Mul104 = 0x68, + Mul105 = 0x69, + Mul106 = 0x6a, + Mul107 = 0x6b, + Mul108 = 0x6c, + Mul109 = 0x6d, + Mul110 = 0x6e, + Mul111 = 0x6f, + Mul112 = 0x70, + Mul113 = 0x71, + Mul114 = 0x72, + Mul115 = 0x73, + Mul116 = 0x74, + Mul117 = 0x75, + Mul118 = 0x76, + Mul119 = 0x77, + Mul120 = 0x78, + Mul121 = 0x79, + Mul122 = 0x7a, + Mul123 = 0x7b, + Mul124 = 0x7c, + Mul125 = 0x7d, + Mul126 = 0x7e, + Mul127 = 0x7f, + _, + }; + + pub const PLLP = enum(u5) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + Div16 = 0x10, + Div17 = 0x11, + Div18 = 0x12, + Div19 = 0x13, + Div20 = 0x14, + Div21 = 0x15, + Div22 = 0x16, + Div23 = 0x17, + Div24 = 0x18, + Div25 = 0x19, + Div26 = 0x1a, + Div27 = 0x1b, + Div28 = 0x1c, + Div29 = 0x1d, + Div30 = 0x1e, + Div31 = 0x1f, + _, + }; + + pub const PLLPBIT = enum(u1) { + Div7 = 0x0, + Div17 = 0x1, + }; + + pub const PLLQ = enum(u2) { + Div2 = 0x0, + Div4 = 0x1, + Div6 = 0x2, + Div8 = 0x3, + }; + + pub const PLLR = enum(u2) { + Div2 = 0x0, + Div4 = 0x1, + Div6 = 0x2, + Div8 = 0x3, + }; + + pub const PLLSRC = enum(u2) { + /// No clock sent to PLL + DISABLE = 0x0, + /// MSI selected as PLL input clock + MSI = 0x1, + /// HSI selected as PLL input clock + HSI = 0x2, + /// HSE selected as PLL input clock + HSE = 0x3, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const RTCSEL = enum(u2) { + /// No clock + Disable = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by 32 used as the RTC clock + HSE = 0x3, + }; + + pub const SAI1SEL = enum(u3) { + /// PLLSAI1CLK clock is selected as SAIx clock + PLLSAI1_P = 0x0, + /// PLLSAI2CLK clock is selected as SAIx clock + PLLSAI2_P = 0x1, + /// PLLSAI3CLK clock is selected as SAIx clock + PLL1_P = 0x2, + /// External clock SAIx_EXTCLK clock selected as SAIx clock + SAI1_EXTCLK = 0x3, + /// HSI clock selected as SAIx clock + HSI = 0x4, + _, + }; + + pub const SAI2SEL = enum(u3) { + /// PLLSAI1CLK clock is selected as SAIx clock + PLLSAI1_P = 0x0, + /// PLLSAI2CLK clock is selected as SAIx clock + PLLSAI2_P = 0x1, + /// PLLSAI3CLK clock is selected as SAIx clock + PLL1_P = 0x2, + /// External clock SAIx_EXTCLK clock selected as SAIx clock + SAI2_EXTCLK = 0x3, + /// HSI clock selected as SAIx clock + HSI = 0x4, + _, + }; + + pub const SDMMCSEL = enum(u1) { + /// 48 MHz clock is selected as SDMMC kernel clock + HSI48 = 0x0, + /// PLLSAI3CLK is selected as SDMMC kernel clock, used in case higher frequency than 48MHz is needed (for SDR50 mode) + PLL1_P = 0x1, + }; + + pub const STOPWUCK = enum(u1) { + /// MSI oscillator selected as wake-up from Stop clock + MSI = 0x0, + /// HSI oscillator selected as wake-up from Stop clock + HSI = 0x1, + }; + + pub const SW = enum(u2) { + /// MSI selected as system clock + MSI = 0x0, + /// HSI selected as system clock + HSI = 0x1, + /// HSE selected as system clock + HSE = 0x2, + /// PLL selected as system clock + PLL1_R = 0x3, + }; + + pub const USART1SEL = enum(u2) { + /// PCLK clock selected + PCLK2 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + /// LSE clock selected + LSE = 0x3, + }; + + pub const USARTSEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + /// LSE clock selected + LSE = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// MSI clock enable + MSION: u1, + /// MSI clock ready flag + MSIRDY: u1, + /// MSI clock PLL enable + MSIPLLEN: u1, + /// MSI clock range selection + MSIRGSEL: packed union { + raw: u1, + value: MSIRGSEL, + }, + /// MSI clock ranges + MSIRANGE: packed union { + raw: u4, + value: MSIRANGE, + }, + /// HSI clock enable + HSION: u1, + /// HSI always enable for peripheral kernels + HSIKERON: u1, + /// HSI clock ready flag + HSIRDY: u1, + /// HSI automatic start from Stop + HSIASFS: u1, + reserved16: u4, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE crystal oscillator bypass + HSEBYP: u1, + /// Clock security system enable + CSSON: u1, + reserved24: u4, + /// Main PLL enable + PLLON: u1, + /// Main PLL clock ready flag + PLLRDY: u1, + /// SAI1 PLL enable + PLLSAI1ON: u1, + /// SAI1 PLL clock ready flag + PLLSAI1RDY: u1, + /// SAI2 PLL enable + PLLSAI2ON: u1, + /// SAI2 PLL clock ready flag + PLLSAI2RDY: u1, + padding: u2, + }), + /// Internal clock sources calibration register + ICSCR: mmio.Mmio(packed struct(u32) { + /// MSI clock calibration + MSICAL: u8, + /// MSI clock trimming + MSITRIM: u8, + /// HSI clock calibration + HSICAL: u8, + /// HSI clock trimming + HSITRIM: u7, + padding: u1, + }), + /// Clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u2, + value: SW, + }, + /// System clock switch status + SWS: packed union { + raw: u2, + value: SW, + }, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// APB low-speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + /// APB high-speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + reserved15: u1, + /// Wakeup from Stop and CSS backup clock selection + STOPWUCK: packed union { + raw: u1, + value: STOPWUCK, + }, + reserved24: u8, + /// Microcontroller clock output selection + MCOSEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// Microcontroller clock output prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, + }, + padding: u1, + }), + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// Main PLL, PLLSAI1 and PLLSAI2 entry clock source + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + reserved4: u2, + /// Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + PLLM: packed union { + raw: u4, + value: PLLM, + }, + /// Main PLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, + }, + reserved16: u1, + /// Main PLL PLLSAI3CLK output enable + PLLPEN: u1, + /// Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + PLLPBIT: packed union { + raw: u1, + value: PLLPBIT, + }, + reserved20: u2, + /// Main PLL PLLUSB1CLK output enable + PLLQEN: u1, + /// Main PLL division factor for PLLUSB1CLK(48 MHz clock) + PLLQ: packed union { + raw: u2, + value: PLLQ, + }, + reserved24: u1, + /// Main PLL PLLCLK output enable + PLLREN: u1, + /// Main PLL division factor for PLLCLK (system clock) + PLLR: packed union { + raw: u2, + value: PLLR, + }, + /// Main PLL division factor for PLLSAI2CLK + PLLP: packed union { + raw: u5, + value: PLLP, + }, + }), + /// PLLSAI1 configuration register + PLLSAI1CFGR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Division factor for PLLSAI input clock + PLLM: packed union { + raw: u4, + value: PLLM, + }, + /// SAI1PLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, + }, + reserved16: u1, + /// SAI1PLL PLLSAICLK output enable + PLLPEN: u1, + /// SAI1PLL division factor for PLLSAICLK + PLLPBIT: packed union { + raw: u1, + value: PLLPBIT, + }, + reserved20: u2, + /// SAI1PLL PLLUSB2CLK output enable + PLLQEN: u1, + /// SAI1PLL division factor for PLLUSB2CLK + PLLQ: packed union { + raw: u2, + value: PLLQ, + }, + reserved24: u1, + /// PLLSAI PLLADC1CLK output enable + PLLREN: u1, + /// PLLSAI division factor for PLLADC1CLK + PLLR: packed union { + raw: u2, + value: PLLR, + }, + /// PLLSAI division factor for PLLSAICLK + PLLP: packed union { + raw: u5, + value: PLLP, + }, + }), + /// PLLSAI2 configuration register + PLLSAI2CFGR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Division factor for PLLSAI input clock + PLLM: packed union { + raw: u4, + value: PLLM, + }, + /// SAI1PLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, + }, + reserved16: u1, + /// SAI1PLL PLLSAICLK output enable + PLLPEN: u1, + /// SAI1PLL division factor for PLLSAICLK + PLLPBIT: packed union { + raw: u1, + value: PLLPBIT, + }, + reserved20: u2, + /// SAI1PLL PLLUSB2CLK output enable + PLLQEN: u1, + /// SAI1PLL division factor for PLLUSB2CLK + PLLQ: packed union { + raw: u2, + value: PLLQ, + }, + reserved24: u1, + /// PLLSAI PLLADC1CLK output enable + PLLREN: u1, + /// PLLSAI division factor for PLLADC1CLK + PLLR: packed union { + raw: u2, + value: PLLR, + }, + /// PLLSAI division factor for PLLSAICLK + PLLP: packed union { + raw: u5, + value: PLLP, + }, + }), + /// Clock interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// MSI ready interrupt enable + MSIRDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// PLL ready interrupt enable + PLLRDYIE: u1, + /// PLLSAI1 ready interrupt enable + PLLSAI1RDYIE: u1, + /// PLLSAI2 ready interrupt enable + PLLSAI2RDYIE: u1, + reserved9: u1, + /// LSE clock security system interrupt enable + LSECSSIE: u1, + /// HSI48 ready interrupt enable + HSI48RDYIE: u1, + padding: u21, + }), + /// Clock interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// MSI ready interrupt flag + MSIRDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// PLL ready interrupt flag + PLLRDYF: u1, + /// PLLSAI1 ready interrupt flag + PLLSAI1RDYF: u1, + /// PLLSAI2 ready interrupt flag + PLLSAI2RDYF: u1, + /// Clock security system interrupt flag + CSSF: u1, + /// LSE Clock security system interrupt flag + LSECSSF: u1, + /// HSI48 ready interrupt flag + HSI48RDYF: u1, + padding: u21, + }), + /// Clock interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// MSI ready interrupt clear + MSIRDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// PLL ready interrupt clear + PLLRDYC: u1, + /// PLLSAI1 ready interrupt clear + PLLSAI1RDYC: u1, + /// PLLSAI2 ready interrupt clear + PLLSAI2RDYC: u1, + /// Clock security system interrupt clear + CSSC: u1, + /// LSE Clock security system interrupt clear + LSECSSC: u1, + /// HSI48 oscillator ready interrupt clear + HSI48RDYC: u1, + padding: u21, + }), + reserved40: [4]u8, + /// AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// DMA1 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + /// DMAMUX1RST + DMAMUX1RST: u1, + reserved8: u5, + /// Flash memory interface reset + FLASHRST: u1, + reserved12: u3, + /// CRC reset + CRCRST: u1, + reserved16: u3, + /// Touch Sensing Controller reset + TSCRST: u1, + /// DMA2D reset + DMA2DRST: u1, + /// GFXMMU reset + GFXMMURST: u1, + padding: u13, + }), + /// AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// IO port H reset + GPIOHRST: u1, + /// IO port I reset + GPIOIRST: u1, + reserved12: u3, + /// USB OTG FS reset + USB_OTG_FSRST: u1, + /// ADC reset + ADCRST: u1, + /// Digital Camera Interface reset + DCMIRST: u1, + /// PKA reset + PKARST: u1, + /// AES hardware accelerator reset + AESRST: u1, + /// Hash reset + HASHRST: u1, + /// Random number generator reset + RNGRST: u1, + reserved20: u1, + /// OCTOSPI IO manager reset + OCTOSPIMRST: u1, + reserved22: u1, + /// SDMMC1 reset + SDMMC1RST: u1, + /// SDMMC2 reset + SDMMC2RST: u1, + padding: u8, + }), + /// AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller reset + FMCRST: u1, + reserved8: u7, + /// OctoSPI1 memory interface reset + OCTOSPI1RST: u1, + /// OctOSPI2 memory interface reset + OCTOSPI2RST: u1, + padding: u22, + }), + reserved56: [4]u8, + /// APB1 peripheral reset register 1 + APB1RSTR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer reset + TIM2RST: u1, + /// TIM3 timer reset + TIM3RST: u1, + /// TIM3 timer reset + TIM4RST: u1, + /// TIM5 timer reset + TIM5RST: u1, + /// TIM6 timer reset + TIM6RST: u1, + /// TIM7 timer reset + TIM7RST: u1, + reserved14: u8, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved17: u1, + /// USART2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// UART4 reset + UART4RST: u1, + /// UART5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// I2C3 reset + I2C3RST: u1, + /// CRS reset + CRSRST: u1, + /// CAN1 reset + CAN1RST: u1, + reserved28: u2, + /// Power interface reset + PWRRST: u1, + /// DAC1 interface reset + DAC1RST: u1, + /// OPAMP interface reset + OPAMPRST: u1, + /// Low Power Timer 1 reset + LPTIM1RST: u1, + }), + /// APB1 peripheral reset register 2 + APB1RSTR2: mmio.Mmio(packed struct(u32) { + /// Low-power UART 1 reset + LPUART1RST: u1, + /// I2C4 reset + I2C4RST: u1, + reserved5: u3, + /// Low-power timer 2 reset + LPTIM2RST: u1, + padding: u26, + }), + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// System configuration (SYSCFG) reset + SYSCFGRST: u1, + reserved11: u10, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + reserved16: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + reserved21: u2, + /// Serial audio interface 1 (SAI1) reset + SAI1RST: u1, + /// Serial audio interface 2 (SAI2) reset + SAI2RST: u1, + reserved24: u1, + /// Digital filters for sigma-delata modulators (DFSDM) reset + DFSDM1RST: u1, + reserved26: u1, + /// LCD-TFT reset + LTDCRST: u1, + /// DSI reset + DSIRST: u1, + padding: u4, + }), + reserved72: [4]u8, + /// AHB1 peripheral clock enable register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// DMAMUX clock enable + DMAMUX1EN: u1, + reserved8: u5, + /// Flash memory interface clock enable + FLASHEN: u1, + reserved12: u3, + /// CRC clock enable + CRCEN: u1, + reserved16: u3, + /// Touch Sensing Controller clock enable + TSCEN: u1, + /// DMA2D clock enable + DMA2DEN: u1, + /// Graphic MMU clock enable + GFXMMUEN: u1, + padding: u13, + }), + /// AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// IO port H clock enable + GPIOHEN: u1, + /// IO port I clock enable + GPIOIEN: u1, + reserved12: u3, + /// OTG full speed clock enable + USB_OTG_FSEN: u1, + /// ADC clock enable + ADCEN: u1, + /// DCMI clock enable + DCMIEN: u1, + /// PKA clock enable + PKAEN: u1, + /// AES accelerator clock enable + AESEN: u1, + /// HASH clock enable + HASHEN: u1, + /// Random Number Generator clock enable + RNGEN: u1, + reserved20: u1, + /// OctoSPI IO manager clock enable + OCTOSPIMEN: u1, + reserved22: u1, + /// SDMMC1 clock enable + SDMMC1EN: u1, + /// SDMMC2 clock enable + SDMMC2EN: u1, + padding: u8, + }), + /// AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller clock enable + FMCEN: u1, + reserved8: u7, + /// OctoSPI1 memory interface clock enable + OCTOSPI1EN: u1, + /// OSPI2EN memory interface clock enable + OCTOSPI2EN: u1, + padding: u22, + }), + reserved88: [4]u8, + /// APB1ENR1 + APB1ENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clock enable + TIM2EN: u1, + /// TIM3 timer clock enable + TIM3EN: u1, + /// TIM4 timer clock enable + TIM4EN: u1, + /// TIM5 timer clock enable + TIM5EN: u1, + /// TIM6 timer clock enable + TIM6EN: u1, + /// TIM7 timer clock enable + TIM7EN: u1, + reserved10: u4, + /// RTC APB clock enable + RTCAPBEN: u1, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI2 clock enable + SPI2EN: u1, + /// SPI3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// I2C3 clock enable + I2C3EN: u1, + /// Clock Recovery System clock enable + CRSEN: u1, + /// CAN1 clock enable + CAN1EN: u1, + reserved28: u2, + /// Power interface clock enable + PWREN: u1, + /// DAC1 interface clock enable + DAC1EN: u1, + /// OPAMP interface clock enable + OPAMPEN: u1, + /// Low power timer 1 clock enable + LPTIM1EN: u1, + }), + /// APB1 peripheral clock enable register 2 + APB1ENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clock enable + LPUART1EN: u1, + /// I2C4 clock enable + I2C4EN: u1, + reserved5: u3, + /// LPTIM2EN + LPTIM2EN: u1, + padding: u26, + }), + /// APB2ENR + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved7: u6, + /// Firewall clock enable + FWEN: u1, + reserved11: u3, + /// TIM1 timer clock enable + TIM1EN: u1, + /// SPI1 clock enable + SPI1EN: u1, + /// TIM8 timer clock enable + TIM8EN: u1, + /// USART1clock enable + USART1EN: u1, + reserved16: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + reserved21: u2, + /// SAI1 clock enable + SAI1EN: u1, + /// SAI2 clock enable + SAI2EN: u1, + reserved24: u1, + /// DFSDM timer clock enable + DFSDM1EN: u1, + reserved26: u1, + /// LCD-TFT clock enable + LTDCEN: u1, + /// DSI clock enable + DSIEN: u1, + padding: u4, + }), + reserved104: [4]u8, + /// AHB1 peripheral clocks enable in Sleep and Stop modes register + AHB1SMENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clocks enable during Sleep and Stop modes + DMA1SMEN: u1, + /// DMA2 clocks enable during Sleep and Stop modes + DMA2SMEN: u1, + /// DMAMUX clock enable during Sleep and Stop modes + DMAMUX1SMEN: u1, + reserved8: u5, + /// Flash memory interface clocks enable during Sleep and Stop modes + FLASHSMEN: u1, + /// SRAM1 interface clocks enable during Sleep and Stop modes + SRAM1SMEN: u1, + reserved12: u2, + /// CRCSMEN + CRCSMEN: u1, + reserved16: u3, + /// Touch Sensing Controller clocks enable during Sleep and Stop modes + TSCSMEN: u1, + /// DMA2D clock enable during Sleep and Stop modes + DMA2DSMEN: u1, + /// GFXMMU clock enable during Sleep and Stop modes + GFXMMUSMEN: u1, + padding: u13, + }), + /// AHB2 peripheral clocks enable in Sleep and Stop modes register + AHB2SMENR: mmio.Mmio(packed struct(u32) { + /// IO port A clocks enable during Sleep and Stop modes + GPIOASMEN: u1, + /// IO port B clocks enable during Sleep and Stop modes + GPIOBSMEN: u1, + /// IO port C clocks enable during Sleep and Stop modes + GPIOCSMEN: u1, + /// IO port D clocks enable during Sleep and Stop modes + GPIODSMEN: u1, + /// IO port E clocks enable during Sleep and Stop modes + GPIOESMEN: u1, + /// IO port F clocks enable during Sleep and Stop modes + GPIOFSMEN: u1, + /// IO port G clocks enable during Sleep and Stop modes + GPIOGSMEN: u1, + /// IO port H clocks enable during Sleep and Stop modes + GPIOHSMEN: u1, + /// IO port I clocks enable during Sleep and Stop modes + GPIOISMEN: u1, + /// SRAM2 interface clocks enable during Sleep and Stop modes + SRAM2SMEN: u1, + /// SRAM2 interface clocks enable during Sleep and Stop modes + SRAM3SMEN: u1, + reserved12: u1, + /// OTG full speed clocks enable during Sleep and Stop modes + USB_OTG_FSSMEN: u1, + /// ADC clocks enable during Sleep and Stop modes + ADCFSSMEN: u1, + /// DCMI clock enable during Sleep and Stop modes + DCMISMEN: u1, + /// PKA clocks enable during Sleep and Stop modes + PKASMEN: u1, + /// AES accelerator clocks enable during Sleep and Stop modes + AESSMEN: u1, + /// HASH clock enable during Sleep and Stop modes + HASH1SMEN: u1, + /// Random Number Generator clocks enable during Sleep and Stop modes + RNGSMEN: u1, + reserved20: u1, + /// OctoSPI IO manager clocks enable during Sleep and Stop modes + OCTOSPIMSMEN: u1, + reserved22: u1, + /// SDMMC1 clocks enable during Sleep and Stop modes + SDMMC1SMEN: u1, + /// SDMMC2 clocks enable during Sleep and Stop modes + SDMMC2SMEN: u1, + padding: u8, + }), + /// AHB3 peripheral clocks enable in Sleep and Stop modes register + AHB3SMENR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller clocks enable during Sleep and Stop modes + FMCSMEN: u1, + reserved8: u7, + /// OctoSPI1 memory interface clocks enable during Sleep and Stop modes + OCTOSPI1SMEN: u1, + /// OctoSPI2 memory interface clocks enable during Sleep and Stop modes + OCTOSPI2SMEN: u1, + padding: u22, + }), + reserved120: [4]u8, + /// APB1SMENR1 + APB1SMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clocks enable during Sleep and Stop modes + TIM2SMEN: u1, + /// TIM3 timer clocks enable during Sleep and Stop modes + TIM3SMEN: u1, + /// TIM4 timer clocks enable during Sleep and Stop modes + TIM4SMEN: u1, + /// TIM5 timer clocks enable during Sleep and Stop modes + TIM5SMEN: u1, + /// TIM6 timer clocks enable during Sleep and Stop modes + TIM6SMEN: u1, + /// TIM7 timer clocks enable during Sleep and Stop modes + TIM7SMEN: u1, + reserved10: u4, + /// RTC APB clock enable during Sleep and Stop modes + RTCAPBSMEN: u1, + /// Window watchdog clocks enable during Sleep and Stop modes + WWDGSMEN: u1, + reserved14: u2, + /// SPI2 clocks enable during Sleep and Stop modes + SPI2SMEN: u1, + /// SPI3 clocks enable during Sleep and Stop modes + SP3SMEN: u1, + reserved17: u1, + /// USART2 clocks enable during Sleep and Stop modes + USART2SMEN: u1, + /// USART3 clocks enable during Sleep and Stop modes + USART3SMEN: u1, + /// UART4 clocks enable during Sleep and Stop modes + UART4SMEN: u1, + /// UART5 clocks enable during Sleep and Stop modes + UART5SMEN: u1, + /// I2C1 clocks enable during Sleep and Stop modes + I2C1SMEN: u1, + /// I2C2 clocks enable during Sleep and Stop modes + I2C2SMEN: u1, + /// I2C3 clocks enable during Sleep and Stop modes + I2C3SMEN: u1, + /// CRS clock enable during Sleep and Stop modes + CRSSMEN: u1, + /// CAN1 clocks enable during Sleep and Stop modes + CAN1SMEN: u1, + reserved28: u2, + /// Power interface clocks enable during Sleep and Stop modes + PWRSMEN: u1, + /// DAC1 interface clocks enable during Sleep and Stop modes + DAC1SMEN: u1, + /// OPAMP interface clocks enable during Sleep and Stop modes + OPAMPSMEN: u1, + /// Low power timer 1 clocks enable during Sleep and Stop modes + LPTIM1SMEN: u1, + }), + /// APB1 peripheral clocks enable in Sleep and Stop modes register 2 + APB1SMENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clocks enable during Sleep and Stop modes + LPUART1SMEN: u1, + /// I2C4 clocks enable during Sleep and Stop modes + I2C4SMEN: u1, + reserved5: u3, + /// LPTIM2SMEN + LPTIM2SMEN: u1, + padding: u26, + }), + /// APB2SMENR + APB2SMENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clocks enable during Sleep and Stop modes + SYSCFGSMEN: u1, + reserved11: u10, + /// TIM1 timer clocks enable during Sleep and Stop modes + TIM1SMEN: u1, + /// SPI1 clocks enable during Sleep and Stop modes + SPI1SMEN: u1, + /// TIM8 timer clocks enable during Sleep and Stop modes + TIM8SMEN: u1, + /// USART1clocks enable during Sleep and Stop modes + USART1SMEN: u1, + reserved16: u1, + /// TIM15 timer clocks enable during Sleep and Stop modes + TIM15SMEN: u1, + /// TIM16 timer clocks enable during Sleep and Stop modes + TIM16SMEN: u1, + /// TIM17 timer clocks enable during Sleep and Stop modes + TIM17SMEN: u1, + reserved21: u2, + /// SAI1 clocks enable during Sleep and Stop modes + SAI1SMEN: u1, + /// SAI2 clocks enable during Sleep and Stop modes + SAI2SMEN: u1, + reserved24: u1, + /// DFSDM timer clocks enable during Sleep and Stop modes + DFSDM1SMEN: u1, + reserved26: u1, + /// LCD-TFT timer clocks enable during Sleep and Stop modes + LTDCSMEN: u1, + /// DSI clocks enable during Sleep and Stop modes + DSISMEN: u1, + padding: u4, + }), + reserved136: [4]u8, + /// CCIPR + CCIPR: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SEL: packed union { + raw: u2, + value: USART1SEL, + }, + /// USART2 clock source selection + USART2SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// USART3 clock source selection + USART3SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// UART4 clock source selection + UART4SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// UART5 clock source selection + UART5SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// LPUART1 clock source selection + LPUART1SEL: packed union { + raw: u2, + value: LPUART1SEL, + }, + /// I2C1 clock source selection + I2C1SEL: packed union { + raw: u2, + value: I2C1SEL, + }, + /// I2C2 clock source selection + I2C2SEL: packed union { + raw: u2, + value: I2C2SEL, + }, + /// I2C3 clock source selection + I2C3SEL: packed union { + raw: u2, + value: I2C3SEL, + }, + /// Low power timer 1 clock source selection + LPTIM1SEL: packed union { + raw: u2, + value: LPTIM1SEL, + }, + /// Low power timer 2 clock source selection + LPTIM2SEL: packed union { + raw: u2, + value: LPTIM2SEL, + }, + reserved26: u4, + /// 48 MHz clock source selection + CLK48SEL: packed union { + raw: u2, + value: CLK48SEL, + }, + /// ADCs clock source selection + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, + padding: u2, + }), + reserved144: [4]u8, + /// BDCR + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enable + LSEON: u1, + /// LSE oscillator ready + LSERDY: u1, + /// LSE oscillator bypass + LSEBYP: u1, + /// SE oscillator drive capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// LSECSSON + LSECSSON: u1, + /// LSECSSD + LSECSSD: u1, + /// Disable the Clock LSE propagation to the system + LSESYSDIS: u1, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + reserved24: u7, + /// Low speed clock output enable + LSCOEN: u1, + /// Low speed clock output selection + LSCOSEL: packed union { + raw: u1, + value: LSCOSEL, + }, + padding: u6, + }), + /// CSR + CSR: mmio.Mmio(packed struct(u32) { + /// LSI oscillator enable + LSION: u1, + /// LSI oscillator ready + LSIRDY: u1, + reserved4: u2, + /// Internal low-speed oscillator predivided by 128. Note - This bit is available only on STM32L4P5xx and STM32L4Q5xx devices. + LSIPREDIV: u1, + reserved8: u3, + /// SI range after Standby mode + MSISRANGE: u4, + reserved23: u11, + /// Remove reset flag + RMVF: u1, + /// Firewall reset flag + FWRSTF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// Pin reset flag + PINRSTF: u1, + /// BOR flag + BORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent window watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + /// Clock recovery RC register + CRRCR: mmio.Mmio(packed struct(u32) { + /// HSI48 clock enable + HSI48ON: u1, + /// HSI48 clock ready flag + HSI48RDY: u1, + reserved7: u5, + /// HSI48 clock calibration + HSI48CAL: u9, + padding: u16, + }), + /// Peripherals independent clock configuration register + CCIPR2: mmio.Mmio(packed struct(u32) { + /// I2C4 clock source selection + I2C4SEL: packed union { + raw: u2, + value: I2C4SEL, + }, + /// Digital filter for sigma delta modulator kernel clock source selection + DFSDMSEL: packed union { + raw: u1, + value: DFSDMSEL, + }, + /// Digital filter for sigma delta modulator audio clock source selection + ADFSDMSEL: packed union { + raw: u2, + value: ADFSDMSEL, + }, + /// SAI1 clock source selection + SAI1SEL: packed union { + raw: u3, + value: SAI1SEL, + }, + /// SAI2 clock source selection + SAI2SEL: packed union { + raw: u3, + value: SAI2SEL, + }, + reserved12: u1, + /// clock selection + DSISEL: packed union { + raw: u1, + value: DSISEL, + }, + reserved14: u1, + /// SDMMC clock selection + SDMMCSEL: packed union { + raw: u1, + value: SDMMCSEL, + }, + reserved16: u1, + /// division factor for LTDC clock + LTDCDIV: u2, + reserved20: u2, + /// Octospi clock source selection + OCTOSPISEL: packed union { + raw: u2, + value: OCTOSPISEL, + }, + padding: u10, + }), + reserved164: [4]u8, + /// delay configuration register + DLYCFGR: mmio.Mmio(packed struct(u32) { + /// Delay sampling configuration on OCTOSPI1 to be used for internal sampling clock (called feedback clock) or for DQS data strobe + OCTOSPI1_DLY: u4, + /// Delay sampling configuration on OCTOSPI2 to be used for internal sampling clock (called feedback clock) or for DQS data strobe + OCTOSPI2_DLY: u4, + padding: u24, + }), + }; + }; + + pub const rcc_l5 = struct { + pub const ADCSEL = enum(u2) { + /// No clock selected + DISABLE = 0x0, + /// PLLADC1CLK clock selected + PLLSAI1_R = 0x1, + /// SYSCLK clock selected + SYS = 0x3, + _, + }; + + pub const CLK48SEL = enum(u2) { + /// HSI48 clock selected + HSI48 = 0x0, + /// PLLSAI1_Q aka PLL48M1CLK clock selected + PLLSAI1_Q = 0x1, + /// PLL_Q aka PLL48M2CLK clock selected + PLL1_Q = 0x2, + /// MSI clock selected + MSI = 0x3, + }; + + pub const FDCANSEL = enum(u2) { + /// HSE clock selected + HSE = 0x0, + /// PLL "Q" clock selected + PLL1_Q = 0x1, + /// PLLSAI "P" clock selected + PLLSAI1_P = 0x2, + _, + }; + + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, + _, + }; + + pub const LSCOSEL = enum(u1) { + /// LSI clock selected" + LSI = 0x0, + /// LSE clock selected + LSE = 0x1, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const MCOPRE = enum(u3) { + /// MCO divided by 1 + Div1 = 0x0, + /// MCO divided by 2 + Div2 = 0x1, + /// MCO divided by 4 + Div4 = 0x2, + /// MCO divided by 8 + Div8 = 0x3, + /// MCO divided by 16 + Div16 = 0x4, + _, + }; + + pub const MCOSEL = enum(u4) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// SYSCLK system clock selected + SYS = 0x1, + /// MSI clock selected + MSI = 0x2, + /// HSI clock selected + HSI = 0x3, + /// HSE clock selected + HSE = 0x4, + /// Main PLL clock selected + PLL = 0x5, + /// LSI clock selected + LSI = 0x6, + /// LSE clock selected + LSE = 0x7, + /// Internal HSI48 clock selected + HSI48 = 0x8, + _, + }; + + pub const MSIRANGE = enum(u4) { + /// range 0 around 100 kHz + Range100K = 0x0, + /// range 1 around 200 kHz + Range200K = 0x1, + /// range 2 around 400 kHz + Range400K = 0x2, + /// range 3 around 800 kHz + Range800K = 0x3, + /// range 4 around 1 MHz + Range1M = 0x4, + /// range 5 around 2 MHz + Range2M = 0x5, + /// range 6 around 4 MHz + Range4M = 0x6, + /// range 7 around 8 MHz + Range8M = 0x7, + /// range 8 around 16 MHz + Range16M = 0x8, + /// range 9 around 24 MHz + Range24M = 0x9, + /// range 10 around 32 MHz + Range32M = 0xa, + /// range 11 around 48 MHz + Range48M = 0xb, + _, + }; + + pub const MSIRGSEL = enum(u1) { + /// MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register + CSR = 0x0, + /// MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register + CR = 0x1, + }; + + pub const PLLM = enum(u4) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + }; + + pub const PLLN = enum(u7) { + Mul8 = 0x8, + Mul9 = 0x9, + Mul10 = 0xa, + Mul11 = 0xb, + Mul12 = 0xc, + Mul13 = 0xd, + Mul14 = 0xe, + Mul15 = 0xf, + Mul16 = 0x10, + Mul17 = 0x11, + Mul18 = 0x12, + Mul19 = 0x13, + Mul20 = 0x14, + Mul21 = 0x15, + Mul22 = 0x16, + Mul23 = 0x17, + Mul24 = 0x18, + Mul25 = 0x19, + Mul26 = 0x1a, + Mul27 = 0x1b, + Mul28 = 0x1c, + Mul29 = 0x1d, + Mul30 = 0x1e, + Mul31 = 0x1f, + Mul32 = 0x20, + Mul33 = 0x21, + Mul34 = 0x22, + Mul35 = 0x23, + Mul36 = 0x24, + Mul37 = 0x25, + Mul38 = 0x26, + Mul39 = 0x27, + Mul40 = 0x28, + Mul41 = 0x29, + Mul42 = 0x2a, + Mul43 = 0x2b, + Mul44 = 0x2c, + Mul45 = 0x2d, + Mul46 = 0x2e, + Mul47 = 0x2f, + Mul48 = 0x30, + Mul49 = 0x31, + Mul50 = 0x32, + Mul51 = 0x33, + Mul52 = 0x34, + Mul53 = 0x35, + Mul54 = 0x36, + Mul55 = 0x37, + Mul56 = 0x38, + Mul57 = 0x39, + Mul58 = 0x3a, + Mul59 = 0x3b, + Mul60 = 0x3c, + Mul61 = 0x3d, + Mul62 = 0x3e, + Mul63 = 0x3f, + Mul64 = 0x40, + Mul65 = 0x41, + Mul66 = 0x42, + Mul67 = 0x43, + Mul68 = 0x44, + Mul69 = 0x45, + Mul70 = 0x46, + Mul71 = 0x47, + Mul72 = 0x48, + Mul73 = 0x49, + Mul74 = 0x4a, + Mul75 = 0x4b, + Mul76 = 0x4c, + Mul77 = 0x4d, + Mul78 = 0x4e, + Mul79 = 0x4f, + Mul80 = 0x50, + Mul81 = 0x51, + Mul82 = 0x52, + Mul83 = 0x53, + Mul84 = 0x54, + Mul85 = 0x55, + Mul86 = 0x56, + Mul87 = 0x57, + Mul88 = 0x58, + Mul89 = 0x59, + Mul90 = 0x5a, + Mul91 = 0x5b, + Mul92 = 0x5c, + Mul93 = 0x5d, + Mul94 = 0x5e, + Mul95 = 0x5f, + Mul96 = 0x60, + Mul97 = 0x61, + Mul98 = 0x62, + Mul99 = 0x63, + Mul100 = 0x64, + Mul101 = 0x65, + Mul102 = 0x66, + Mul103 = 0x67, + Mul104 = 0x68, + Mul105 = 0x69, + Mul106 = 0x6a, + Mul107 = 0x6b, + Mul108 = 0x6c, + Mul109 = 0x6d, + Mul110 = 0x6e, + Mul111 = 0x6f, + Mul112 = 0x70, + Mul113 = 0x71, + Mul114 = 0x72, + Mul115 = 0x73, + Mul116 = 0x74, + Mul117 = 0x75, + Mul118 = 0x76, + Mul119 = 0x77, + Mul120 = 0x78, + Mul121 = 0x79, + Mul122 = 0x7a, + Mul123 = 0x7b, + Mul124 = 0x7c, + Mul125 = 0x7d, + Mul126 = 0x7e, + Mul127 = 0x7f, + _, + }; + + pub const PLLP = enum(u5) { + Div2 = 0x2, + Div3 = 0x3, + Div4 = 0x4, + Div5 = 0x5, + Div6 = 0x6, + Div7 = 0x7, + Div8 = 0x8, + Div9 = 0x9, + Div10 = 0xa, + Div11 = 0xb, + Div12 = 0xc, + Div13 = 0xd, + Div14 = 0xe, + Div15 = 0xf, + Div16 = 0x10, + Div17 = 0x11, + Div18 = 0x12, + Div19 = 0x13, + Div20 = 0x14, + Div21 = 0x15, + Div22 = 0x16, + Div23 = 0x17, + Div24 = 0x18, + Div25 = 0x19, + Div26 = 0x1a, + Div27 = 0x1b, + Div28 = 0x1c, + Div29 = 0x1d, + Div30 = 0x1e, + Div31 = 0x1f, + _, + }; + + pub const PLLPBIT = enum(u1) { + Div7 = 0x0, + Div17 = 0x1, + }; + + pub const PLLQ = enum(u2) { + Div2 = 0x0, + Div4 = 0x1, + Div6 = 0x2, + Div8 = 0x3, + }; + + pub const PLLR = enum(u2) { + Div2 = 0x0, + Div4 = 0x1, + Div6 = 0x2, + Div8 = 0x3, + }; + + pub const PLLSRC = enum(u2) { + /// No clock sent to PLL + DISABLE = 0x0, + /// MSI selected as PLL input clock + MSI = 0x1, + /// HSI selected as PLL input clock + HSI = 0x2, + /// HSE selected as PLL input clock + HSE = 0x3, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const RTCSEL = enum(u2) { + /// No clock + DISABLE = 0x0, + /// LSE oscillator clock used as RTC clock + LSE = 0x1, + /// LSI oscillator clock used as RTC clock + LSI = 0x2, + /// HSE oscillator clock divided by a prescaler used as RTC clock + HSE = 0x3, + }; + + pub const STOPWUCK = enum(u1) { + /// MSI oscillator selected as wake-up from Stop clock and CSS backup clock + MSI = 0x0, + /// HSI oscillator selected as wake-up from stop clock and CSS backup clock + HSI = 0x1, + }; + + pub const SW = enum(u2) { + /// MSI selected as system clock + MSI = 0x0, + /// HSI selected as system clock + HSI = 0x1, + /// HSE selected as system clock + HSE = 0x2, + /// PLL selected as system clock + PLL1_R = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// MSI clock enable + MSION: u1, + /// MSI clock ready flag + MSIRDY: u1, + /// MSI clock PLL enable + MSIPLLEN: u1, + /// MSI clock range selection + MSIRGSEL: packed union { + raw: u1, + value: MSIRGSEL, + }, + /// MSI clock ranges + MSIRANGE: packed union { + raw: u4, + value: MSIRANGE, + }, + /// HSI clock enable + HSION: u1, + /// HSI always enable for peripheral kernels + HSIKERON: u1, + /// HSI clock ready flag + HSIRDY: u1, + /// HSI automatic start from Stop + HSIASFS: u1, + reserved16: u4, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE crystal oscillator bypass + HSEBYP: u1, + /// Clock security system enable + CSSON: u1, + reserved24: u4, + /// Main PLL enable + PLLON: u1, + /// Main PLL clock ready flag + PLLRDY: u1, + /// SAI1 PLL enable + PLLSAI1ON: u1, + /// SAI1 PLL clock ready flag + PLLSAI1RDY: u1, + /// SAI2 PLL enable + PLLSAI2ON: u1, + /// SAI2 PLL clock ready flag + PLLSAI2RDY: u1, + reserved31: u1, + /// PRIV + PRIV: u1, + }), + /// Internal clock sources calibration register + ICSCR: mmio.Mmio(packed struct(u32) { + /// MSI clock calibration + MSICAL: u8, + /// MSI clock trimming + MSITRIM: u8, + /// HSI clock calibration + HSICAL: u8, + /// HSI clock trimming + HSITRIM: u7, + padding: u1, + }), + /// Clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u2, + value: SW, + }, + /// System clock switch status + SWS: packed union { + raw: u2, + value: SW, + }, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// APB low-speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + /// APB high-speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + reserved15: u1, + /// Wakeup from Stop and CSS backup clock selection + STOPWUCK: packed union { + raw: u1, + value: STOPWUCK, + }, + reserved24: u8, + /// Microcontroller clock output selection + MCOSEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// Microcontroller clock output prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, + }, + padding: u1, + }), + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// PLL clock source + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + reserved4: u2, + /// Division factor for the PLL input clock + PLLM: packed union { + raw: u4, + value: PLLM, + }, + /// PLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, + }, + reserved16: u1, + /// PLL PLLSAI3CLK output enable + PLLPEN: u1, + /// PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + PLLPBIT: packed union { + raw: u1, + value: PLLPBIT, + }, + reserved20: u2, + /// PLL PLLUSB1CLK output enable + PLLQEN: u1, + /// PLL division factor for PLLUSB1CLK(48 MHz clock) + PLLQ: packed union { + raw: u2, + value: PLLQ, + }, + reserved24: u1, + /// PLL PLLCLK output enable + PLLREN: u1, + /// PLL division factor for PLLCLK (system clock) + PLLR: packed union { + raw: u2, + value: PLLR, + }, + /// PLL division factor for PLLSAI2CLK + PLLP: packed union { + raw: u5, + value: PLLP, + }, + }), + /// PLLSAI1 configuration register + PLLSAI1CFGR: mmio.Mmio(packed struct(u32) { + /// PLL clock source + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + reserved4: u2, + /// Division factor for the PLL input clock + PLLM: packed union { + raw: u4, + value: PLLM, + }, + /// PLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, + }, + reserved16: u1, + /// PLL PLLSAI3CLK output enable + PLLPEN: u1, + /// PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + PLLPBIT: packed union { + raw: u1, + value: PLLPBIT, + }, + reserved20: u2, + /// PLL PLLUSB1CLK output enable + PLLQEN: u1, + /// PLL division factor for PLLUSB1CLK(48 MHz clock) + PLLQ: packed union { + raw: u2, + value: PLLQ, + }, + reserved24: u1, + /// PLL PLLCLK output enable + PLLREN: u1, + /// PLL division factor for PLLCLK (system clock) + PLLR: packed union { + raw: u2, + value: PLLR, + }, + /// PLL division factor for PLLSAI2CLK + PLLP: packed union { + raw: u5, + value: PLLP, + }, + }), + /// PLLSAI2 configuration register + PLLSAI2CFGR: mmio.Mmio(packed struct(u32) { + /// PLL clock source + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + reserved4: u2, + /// Division factor for the PLL input clock + PLLM: packed union { + raw: u4, + value: PLLM, + }, + /// PLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, + }, + reserved16: u1, + /// PLL PLLSAI3CLK output enable + PLLPEN: u1, + /// PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + PLLPBIT: packed union { + raw: u1, + value: PLLPBIT, + }, + reserved20: u2, + /// PLL PLLUSB1CLK output enable + PLLQEN: u1, + /// PLL division factor for PLLUSB1CLK(48 MHz clock) + PLLQ: packed union { + raw: u2, + value: PLLQ, + }, + reserved24: u1, + /// PLL PLLCLK output enable + PLLREN: u1, + /// PLL division factor for PLLCLK (system clock) + PLLR: packed union { + raw: u2, + value: PLLR, + }, + /// PLL division factor for PLLSAI2CLK + PLLP: packed union { + raw: u5, + value: PLLP, + }, + }), + /// Clock interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// MSI ready interrupt enable + MSIRDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// PLL ready interrupt enable + PLLRDYIE: u1, + /// PLLSAI1 ready interrupt enable + PLLSAI1RDYIE: u1, + /// PLLSAI2 ready interrupt enable + PLLSAI2RDYIE: u1, + reserved9: u1, + /// LSE clock security system interrupt enable + LSECSSIE: u1, + /// HSI48 ready interrupt enable + HSI48RDYIE: u1, + padding: u21, + }), + /// Clock interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// MSI ready interrupt flag + MSIRDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// PLL ready interrupt flag + PLLRDYF: u1, + /// PLLSAI1 ready interrupt flag + PLLSAI1RDYF: u1, + /// PLLSAI2 ready interrupt flag + PLLSAI2RDYF: u1, + /// Clock security system interrupt flag + CSSF: u1, + /// LSE Clock security system interrupt flag + LSECSSF: u1, + /// HSI48 ready interrupt flag + HSI48RDYF: u1, + padding: u21, + }), + /// Clock interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// MSI ready interrupt clear + MSIRDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// PLL ready interrupt clear + PLLRDYC: u1, + /// PLLSAI1 ready interrupt clear + PLLSAI1RDYC: u1, + /// PLLSAI2 ready interrupt clear + PLLSAI2RDYC: u1, + /// Clock security system interrupt clear + CSSC: u1, + /// LSE Clock security system interrupt clear + LSECSSC: u1, + /// HSI48 oscillator ready interrupt clear + HSI48RDYC: u1, + padding: u21, + }), + reserved40: [4]u8, + /// AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// DMA1 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + /// DMAMUX1RST + DMAMUX1RST: u1, + reserved8: u5, + /// Flash memory interface reset + FLASHRST: u1, + reserved12: u3, + /// CRC reset + CRCRST: u1, + reserved16: u3, + /// Touch Sensing Controller reset + TSCRST: u1, + reserved22: u5, + /// GTZC reset + GTZCRST: u1, + padding: u9, + }), + /// AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// IO port H reset + GPIOHRST: u1, + reserved13: u5, + /// ADC reset + ADCRST: u1, + reserved16: u2, + /// AES hardware accelerator reset + AESRST: u1, + /// Hash reset + HASHRST: u1, + /// Random number generator reset + RNGRST: u1, + /// PKARST + PKARST: u1, + reserved21: u1, + /// OTFDEC1RST + OTFDEC1RST: u1, + /// SDMMC1 reset + SDMMC1RST: u1, + padding: u9, + }), + /// AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller reset + FMCRST: u1, + reserved8: u7, + /// OCTOSPI1RST + OCTOSPI1RST: u1, + padding: u23, + }), + reserved56: [4]u8, + /// APB1 peripheral reset register 1 + APB1RSTR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer reset + TIM2RST: u1, + /// TIM3 timer reset + TIM3RST: u1, + /// TIM3 timer reset + TIM4RST: u1, + /// TIM5 timer reset + TIM5RST: u1, + /// TIM6 timer reset + TIM6RST: u1, + /// TIM7 timer reset + TIM7RST: u1, + reserved14: u8, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved17: u1, + /// USART2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// UART4 reset + UART4RST: u1, + /// UART5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// I2C3 reset + I2C3RST: u1, + /// CRS reset + CRSRST: u1, + reserved28: u3, + /// Power interface reset + PWRRST: u1, + /// DAC1 interface reset + DAC1RST: u1, + /// OPAMP interface reset + OPAMPRST: u1, + /// Low Power Timer 1 reset + LPTIM1RST: u1, + }), + /// APB1 peripheral reset register 2 + APB1RSTR2: mmio.Mmio(packed struct(u32) { + /// Low-power UART 1 reset + LPUART1RST: u1, + /// I2C4 reset + I2C4RST: u1, + reserved5: u3, + /// Low-power timer 2 reset + LPTIM2RST: u1, + /// LPTIM3RST + LPTIM3RST: u1, + reserved9: u2, + /// FDCAN1RST + FDCAN1RST: u1, + reserved21: u11, + /// USBRST + USBRST: u1, + reserved23: u1, + /// UCPD1RST + UCPD1RST: u1, + padding: u8, + }), + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// System configuration (SYSCFG) reset + SYSCFGRST: u1, + reserved11: u10, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + reserved16: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + reserved21: u2, + /// Serial audio interface 1 (SAI1) reset + SAI1RST: u1, + /// Serial audio interface 2 (SAI2) reset + SAI2RST: u1, + reserved24: u1, + /// Digital filters for sigma-delata modulators (DFSDM) reset + DFSDM1RST: u1, + padding: u7, + }), + reserved72: [4]u8, + /// AHB1 peripheral clock enable register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// DMAMUX clock enable + DMAMUX1EN: u1, + reserved8: u5, + /// Flash memory interface clock enable + FLASHEN: u1, + reserved12: u3, + /// CRC clock enable + CRCEN: u1, + reserved16: u3, + /// Touch Sensing Controller clock enable + TSCEN: u1, + reserved22: u5, + /// GTZCEN + GTZCEN: u1, + padding: u9, + }), + /// AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// IO port H clock enable + GPIOHEN: u1, + reserved13: u5, + /// ADC clock enable + ADCEN: u1, + reserved16: u2, + /// AES accelerator clock enable + AESEN: u1, + /// HASH clock enable + HASHEN: u1, + /// Random Number Generator clock enable + RNGEN: u1, + /// PKAEN + PKAEN: u1, + reserved21: u1, + /// OTFDEC1EN + OTFDEC1EN: u1, + /// SDMMC1 clock enable + SDMMC1EN: u1, + padding: u9, + }), + /// AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller clock enable + FMCEN: u1, + reserved8: u7, + /// OCTOSPI1EN + OCTOSPI1EN: u1, + padding: u23, + }), + reserved88: [4]u8, + /// APB1ENR1 + APB1ENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clock enable + TIM2EN: u1, + /// TIM3 timer clock enable + TIM3EN: u1, + /// TIM4 timer clock enable + TIM4EN: u1, + /// TIM5 timer clock enable + TIM5EN: u1, + /// TIM6 timer clock enable + TIM6EN: u1, + /// TIM7 timer clock enable + TIM7EN: u1, + reserved10: u4, + /// RTC APB clock enable + RTCAPBEN: u1, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI2 clock enable + SPI2EN: u1, + /// SPI3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// I2C3 clock enable + I2C3EN: u1, + /// Clock Recovery System clock enable + CRSEN: u1, + reserved28: u3, + /// Power interface clock enable + PWREN: u1, + /// DAC1 interface clock enable + DAC1EN: u1, + /// OPAMP interface clock enable + OPAMPEN: u1, + /// Low power timer 1 clock enable + LPTIM1EN: u1, + }), + /// APB1 peripheral clock enable register 2 + APB1ENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clock enable + LPUART1EN: u1, + /// I2C4 clock enable + I2C4EN: u1, + reserved5: u3, + /// LPTIM2EN + LPTIM2EN: u1, + /// LPTIM3EN + LPTIM3EN: u1, + reserved9: u2, + /// FDCAN1EN + FDCAN1EN: u1, + reserved21: u11, + /// USBEN + USBEN: u1, + reserved23: u1, + /// UCPD1EN + UCPD1EN: u1, + padding: u8, + }), + /// APB2ENR + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved11: u10, + /// TIM1 timer clock enable + TIM1EN: u1, + /// SPI1 clock enable + SPI1EN: u1, + /// TIM8 timer clock enable + TIM8EN: u1, + /// USART1clock enable + USART1EN: u1, + reserved16: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + reserved21: u2, + /// SAI1 clock enable + SAI1EN: u1, + /// SAI2 clock enable + SAI2EN: u1, + reserved24: u1, + /// DFSDM timer clock enable + DFSDM1EN: u1, + padding: u7, + }), + reserved104: [4]u8, + /// AHB1 peripheral clocks enable in Sleep and Stop modes register + AHB1SMENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clocks enable during Sleep and Stop modes + DMA1SMEN: u1, + /// DMA2 clocks enable during Sleep and Stop modes + DMA2SMEN: u1, + /// DMAMUX clock enable during Sleep and Stop modes + DMAMUX1SMEN: u1, + reserved8: u5, + /// Flash memory interface clocks enable during Sleep and Stop modes + FLASHSMEN: u1, + /// SRAM1 interface clocks enable during Sleep and Stop modes + SRAM1SMEN: u1, + reserved12: u2, + /// CRCSMEN + CRCSMEN: u1, + reserved16: u3, + /// Touch Sensing Controller clocks enable during Sleep and Stop modes + TSCSMEN: u1, + reserved22: u5, + /// GTZCSMEN + GTZCSMEN: u1, + /// ICACHESMEN + ICACHESMEN: u1, + padding: u8, + }), + /// AHB2 peripheral clocks enable in Sleep and Stop modes register + AHB2SMENR: mmio.Mmio(packed struct(u32) { + /// IO port A clocks enable during Sleep and Stop modes + GPIOASMEN: u1, + /// IO port B clocks enable during Sleep and Stop modes + GPIOBSMEN: u1, + /// IO port C clocks enable during Sleep and Stop modes + GPIOCSMEN: u1, + /// IO port D clocks enable during Sleep and Stop modes + GPIODSMEN: u1, + /// IO port E clocks enable during Sleep and Stop modes + GPIOESMEN: u1, + /// IO port F clocks enable during Sleep and Stop modes + GPIOFSMEN: u1, + /// IO port G clocks enable during Sleep and Stop modes + GPIOGSMEN: u1, + /// IO port H clocks enable during Sleep and Stop modes + GPIOHSMEN: u1, + reserved9: u1, + /// SRAM2 interface clocks enable during Sleep and Stop modes + SRAM2SMEN: u1, + reserved13: u3, + /// ADC clocks enable during Sleep and Stop modes + ADCFSSMEN: u1, + reserved16: u2, + /// AES accelerator clocks enable during Sleep and Stop modes + AESSMEN: u1, + /// HASH clock enable during Sleep and Stop modes + HASHSMEN: u1, + /// Random Number Generator clocks enable during Sleep and Stop modes + RNGSMEN: u1, + /// PKASMEN + PKASMEN: u1, + reserved21: u1, + /// OTFDEC1SMEN + OTFDEC1SMEN: u1, + /// SDMMC1 clocks enable during Sleep and Stop modes + SDMMC1SMEN: u1, + padding: u9, + }), + /// AHB3 peripheral clocks enable in Sleep and Stop modes register + AHB3SMENR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller clocks enable during Sleep and Stop modes + FMCSMEN: u1, + reserved8: u7, + /// OCTOSPI1SMEN + OCTOSPI1SMEN: u1, + padding: u23, + }), + reserved120: [4]u8, + /// APB1SMENR1 + APB1SMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clocks enable during Sleep and Stop modes + TIM2SMEN: u1, + /// TIM3 timer clocks enable during Sleep and Stop modes + TIM3SMEN: u1, + /// TIM4 timer clocks enable during Sleep and Stop modes + TIM4SMEN: u1, + /// TIM5 timer clocks enable during Sleep and Stop modes + TIM5SMEN: u1, + /// TIM6 timer clocks enable during Sleep and Stop modes + TIM6SMEN: u1, + /// TIM7 timer clocks enable during Sleep and Stop modes + TIM7SMEN: u1, + reserved10: u4, + /// RTC APB clock enable during Sleep and Stop modes + RTCAPBSMEN: u1, + /// Window watchdog clocks enable during Sleep and Stop modes + WWDGSMEN: u1, + reserved14: u2, + /// SPI2 clocks enable during Sleep and Stop modes + SPI2SMEN: u1, + /// SPI3 clocks enable during Sleep and Stop modes + SP3SMEN: u1, + reserved17: u1, + /// USART2 clocks enable during Sleep and Stop modes + USART2SMEN: u1, + /// USART3 clocks enable during Sleep and Stop modes + USART3SMEN: u1, + /// UART4 clocks enable during Sleep and Stop modes + UART4SMEN: u1, + /// UART5 clocks enable during Sleep and Stop modes + UART5SMEN: u1, + /// I2C1 clocks enable during Sleep and Stop modes + I2C1SMEN: u1, + /// I2C2 clocks enable during Sleep and Stop modes + I2C2SMEN: u1, + /// I2C3 clocks enable during Sleep and Stop modes + I2C3SMEN: u1, + /// CRS clock enable during Sleep and Stop modes + CRSSMEN: u1, + reserved28: u3, + /// Power interface clocks enable during Sleep and Stop modes + PWRSMEN: u1, + /// DAC1 interface clocks enable during Sleep and Stop modes + DAC1SMEN: u1, + /// OPAMP interface clocks enable during Sleep and Stop modes + OPAMPSMEN: u1, + /// Low power timer 1 clocks enable during Sleep and Stop modes + LPTIM1SMEN: u1, + }), + /// APB1 peripheral clocks enable in Sleep and Stop modes register 2 + APB1SMENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clocks enable during Sleep and Stop modes + LPUART1SMEN: u1, + /// I2C4 clocks enable during Sleep and Stop modes + I2C4SMEN: u1, + reserved5: u3, + /// LPTIM2SMEN + LPTIM2SMEN: u1, + /// LPTIM3SMEN + LPTIM3SMEN: u1, + reserved9: u2, + /// FDCAN1SMEN + FDCAN1SMEN: u1, + reserved21: u11, + /// USBSMEN + USBSMEN: u1, + reserved23: u1, + /// UCPD1SMEN + UCPD1SMEN: u1, + padding: u8, + }), + /// APB2SMENR + APB2SMENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clocks enable during Sleep and Stop modes + SYSCFGSMEN: u1, + reserved11: u10, + /// TIM1 timer clocks enable during Sleep and Stop modes + TIM1SMEN: u1, + /// SPI1 clocks enable during Sleep and Stop modes + SPI1SMEN: u1, + /// TIM8 timer clocks enable during Sleep and Stop modes + TIM8SMEN: u1, + /// USART1clocks enable during Sleep and Stop modes + USART1SMEN: u1, + reserved16: u1, + /// TIM15 timer clocks enable during Sleep and Stop modes + TIM15SMEN: u1, + /// TIM16 timer clocks enable during Sleep and Stop modes + TIM16SMEN: u1, + /// TIM17 timer clocks enable during Sleep and Stop modes + TIM17SMEN: u1, + reserved21: u2, + /// SAI1 clocks enable during Sleep and Stop modes + SAI1SMEN: u1, + /// SAI2 clocks enable during Sleep and Stop modes + SAI2SMEN: u1, + reserved24: u1, + /// DFSDM timer clocks enable during Sleep and Stop modes + DFSDM1SMEN: u1, + padding: u7, + }), + reserved136: [4]u8, + /// CCIPR + CCIPR: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SEL: u2, + /// USART2 clock source selection + USART2SEL: u2, + /// USART3 clock source selection + USART3SEL: u2, + /// UART4 clock source selection + UART4SEL: u2, + /// UART5 clock source selection + UART5SEL: u2, + /// LPUART1 clock source selection + LPUART1SEL: u2, + /// I2C1 clock source selection + I2C1SEL: u2, + /// I2C2 clock source selection + I2C2SEL: u2, + /// I2C3 clock source selection + I2C3SEL: u2, + /// Low power timer 1 clock source selection + LPTIM1SEL: u2, + /// Low power timer 2 clock source selection + LPTIM2SEL: u2, + /// Low-power timer 3 clock source selection + LPTIM3SEL: u2, + /// FDCAN clock source selection + FDCANSEL: packed union { + raw: u2, + value: FDCANSEL, + }, + /// 48 MHz clock source selection + CLK48SEL: packed union { + raw: u2, + value: CLK48SEL, + }, + /// ADCs clock source selection + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, + padding: u2, + }), + reserved144: [4]u8, + /// BDCR + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enable + LSEON: u1, + /// LSE oscillator ready + LSERDY: u1, + /// LSE oscillator bypass + LSEBYP: u1, + /// SE oscillator drive capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// LSECSSON + LSECSSON: u1, + /// LSECSSD + LSECSSD: u1, + /// LSESYSEN + LSESYSEN: u1, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved11: u1, + /// LSESYSRDY + LSESYSRDY: u1, + reserved15: u3, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + reserved24: u7, + /// Low speed clock output enable + LSCOEN: u1, + /// Low speed clock output selection + LSCOSEL: packed union { + raw: u1, + value: LSCOSEL, + }, + padding: u6, + }), + /// CSR + CSR: mmio.Mmio(packed struct(u32) { + /// LSI oscillator enable + LSION: u1, + /// LSI oscillator ready + LSIRDY: u1, + reserved4: u2, + /// LSIPREDIV + LSIPREDIV: u1, + reserved8: u3, + /// SI range after Standby mode + MSISRANGE: u4, + reserved23: u11, + /// Remove reset flag + RMVF: u1, + reserved25: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// Pin reset flag + PINRSTF: u1, + /// BOR flag + BORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent window watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + /// Clock recovery RC register + CRRCR: mmio.Mmio(packed struct(u32) { + /// HSI48 clock enable + HSI48ON: u1, + /// HSI48 clock ready flag + HSI48RDY: u1, + reserved7: u5, + /// HSI48 clock calibration + HSI48CAL: u9, + padding: u16, + }), + /// Peripherals independent clock configuration register + CCIPR2: mmio.Mmio(packed struct(u32) { + /// I2C4 clock source selection + I2C4SEL: u2, + /// Digital filter for sigma delta modulator kernel clock source selection + DFSDMSEL: u1, + /// Digital filter for sigma delta modulator audio clock source selection + ADFSDMSEL: u2, + /// SAI1 clock source selection + SAI1SEL: u3, + /// SAI2 clock source selection + SAI2SEL: u3, + reserved14: u3, + /// SDMMC clock selection + SDMMCSEL: u1, + reserved20: u5, + /// Octospi clock source selection + OCTOSPISEL: u2, + padding: u10, + }), + reserved184: [24]u8, + /// RCC secure configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// HSISEC + HSISEC: u1, + /// HSESEC + HSESEC: u1, + /// MSISEC + MSISEC: u1, + /// LSISEC + LSISEC: u1, + /// LSESEC + LSESEC: u1, + /// SYSCLKSEC + SYSCLKSEC: u1, + /// PRESCSEC + PRESCSEC: u1, + /// PLLSEC + PLLSEC: u1, + /// PLLSAI1SEC + PLLSAI1SEC: u1, + /// PLLSAI2SEC + PLLSAI2SEC: u1, + /// CLK48SEC + CLK48SEC: u1, + /// HSI48SEC + HSI48SEC: u1, + /// RMVFSEC + RMVFSEC: u1, + padding: u19, + }), + /// RCC secure status register + SECSR: mmio.Mmio(packed struct(u32) { + /// HSISECF + HSISECF: u1, + /// HSESECF + HSESECF: u1, + /// MSISECF + MSISECF: u1, + /// LSISECF + LSISECF: u1, + /// LSESECF + LSESECF: u1, + /// SYSCLKSECF + SYSCLKSECF: u1, + /// PRESCSECF + PRESCSECF: u1, + /// PLLSECF + PLLSECF: u1, + /// PLLSAI1SECF + PLLSAI1SECF: u1, + /// PLLSAI2SECF + PLLSAI2SECF: u1, + /// CLK48SECF + CLK48SECF: u1, + /// HSI48SECF + HSI48SECF: u1, + /// RMVFSECF + RMVFSECF: u1, + padding: u19, + }), + reserved232: [40]u8, + /// RCC AHB1 security status register + AHB1SECSR: mmio.Mmio(packed struct(u32) { + /// DMA1SECF + DMA1SECF: u1, + /// DMA2SECF + DMA2SECF: u1, + /// DMAMUX1SECF + DMAMUX1SECF: u1, + reserved8: u5, + /// FLASHSECF + FLASHSECF: u1, + /// SRAM1SECF + SRAM1SECF: u1, + reserved12: u2, + /// CRCSECF + CRCSECF: u1, + reserved16: u3, + /// TSCSECF + TSCSECF: u1, + reserved22: u5, + /// GTZCSECF + GTZCSECF: u1, + /// ICACHESECF + ICACHESECF: u1, + padding: u8, + }), + /// RCC AHB2 security status register + AHB2SECSR: mmio.Mmio(packed struct(u32) { + /// GPIOASECF + GPIOASECF: u1, + /// GPIOBSECF + GPIOBSECF: u1, + /// GPIOCSECF + GPIOCSECF: u1, + /// GPIODSECF + GPIODSECF: u1, + /// GPIOESECF + GPIOESECF: u1, + /// GPIOFSECF + GPIOFSECF: u1, + /// GPIOGSECF + GPIOGSECF: u1, + /// GPIOHSECF + GPIOHSECF: u1, + reserved9: u1, + /// SRAM2SECF + SRAM2SECF: u1, + reserved21: u11, + /// OTFDEC1SECF + OTFDEC1SECF: u1, + /// SDMMC1SECF + SDMMC1SECF: u1, + padding: u9, + }), + /// RCC AHB3 security status register + AHB3SECSR: mmio.Mmio(packed struct(u32) { + /// FSMCSECF + FSMCSECF: u1, + reserved8: u7, + /// OCTOSPI1SECF + OCTOSPI1SECF: u1, + padding: u23, + }), + reserved248: [4]u8, + /// RCC APB1 security status register 1 + APB1SECSR1: mmio.Mmio(packed struct(u32) { + /// TIM2SECF + TIM2SECF: u1, + /// TIM3SECF + TIM3SECF: u1, + /// TIM4SECF + TIM4SECF: u1, + /// TIM5SECF + TIM5SECF: u1, + /// TIM6SECF + TIM6SECF: u1, + /// TIM7SECF + TIM7SECF: u1, + reserved10: u4, + /// RTCAPBSECF + RTCAPBSECF: u1, + /// WWDGSECF + WWDGSECF: u1, + reserved14: u2, + /// SPI2SECF + SPI2SECF: u1, + /// SPI3SECF + SPI3SECF: u1, + reserved17: u1, + /// UART2SECF + UART2SECF: u1, + /// UART3SECF + UART3SECF: u1, + /// UART4SECF + UART4SECF: u1, + /// UART5SECF + UART5SECF: u1, + /// I2C1SECF + I2C1SECF: u1, + /// I2C2SECF + I2C2SECF: u1, + /// I2C3SECF + I2C3SECF: u1, + /// CRSSECF + CRSSECF: u1, + reserved28: u3, + /// PWRSECF + PWRSECF: u1, + /// DACSECF + DACSECF: u1, + /// OPAMPSECF + OPAMPSECF: u1, + /// LPTIM1SECF + LPTIM1SECF: u1, + }), + /// RCC APB1 security status register 2 + APB1SECSR2: mmio.Mmio(packed struct(u32) { + /// LPUART1SECF + LPUART1SECF: u1, + /// I2C4SECF + I2C4SECF: u1, + reserved5: u3, + /// LPTIM2SECF + LPTIM2SECF: u1, + /// LPTIM3SECF + LPTIM3SECF: u1, + reserved9: u2, + /// FDCAN1SECF + FDCAN1SECF: u1, + reserved21: u11, + /// USBSECF + USBSECF: u1, + reserved23: u1, + /// UCPD1SECF + UCPD1SECF: u1, + padding: u8, + }), + /// RCC APB2 security status register + APB2SECSR: mmio.Mmio(packed struct(u32) { + /// SYSCFGSECF + SYSCFGSECF: u1, + reserved11: u10, + /// TIM1SECF + TIM1SECF: u1, + /// SPI1SECF + SPI1SECF: u1, + /// TIM8SECF + TIM8SECF: u1, + /// USART1SECF + USART1SECF: u1, + reserved16: u1, + /// TIM15SECF + TIM15SECF: u1, + /// TIM16SECF + TIM16SECF: u1, + /// TIM17SECF + TIM17SECF: u1, + reserved21: u2, + /// SAI1SECF + SAI1SECF: u1, + /// SAI2SECF + SAI2SECF: u1, + reserved24: u1, + /// DFSDM1SECF + DFSDM1SECF: u1, + padding: u7, + }), + }; + }; + + pub const rcc_u0 = struct { + pub const ADCSEL = enum(u2) { + SYS = 0x0, + PLL1_P = 0x1, + HSI = 0x2, + _, + }; + + pub const CLK48SEL = enum(u2) { + DISABLE = 0x0, + MSI = 0x1, + PLL1_Q = 0x2, + HSI48 = 0x3, + }; + + pub const HPRE = enum(u4) { + Div1 = 0x0, + Div2 = 0x8, + Div4 = 0x9, + Div8 = 0xa, + Div16 = 0xb, + Div64 = 0xc, + Div128 = 0xd, + Div256 = 0xe, + Div512 = 0xf, + _, + }; + + pub const I2C1SEL = enum(u2) { + PCLK1 = 0x0, + SYS = 0x1, + HSI = 0x2, + _, + }; + + pub const I2C3SEL = enum(u2) { + PCLK1 = 0x0, + SYS = 0x1, + HSI = 0x2, + _, + }; + + pub const LPTIM1SEL = enum(u2) { + PCLK1 = 0x0, + LSI = 0x1, + HSI = 0x2, + LSE = 0x3, + }; + + pub const LPTIM2SEL = enum(u2) { + PCLK1 = 0x0, + LSI = 0x1, + HSI = 0x2, + LSE = 0x3, + }; + + pub const LPTIM3SEL = enum(u2) { + PCLK1 = 0x0, + LSI = 0x1, + HSI = 0x2, + LSE = 0x3, + }; + + pub const LPUART1SEL = enum(u2) { + PCLK1 = 0x0, + SYS = 0x1, + HSI = 0x2, + LSE = 0x3, + }; + + pub const LPUART2SEL = enum(u2) { + PCLK1 = 0x0, + SYS = 0x1, + HSI = 0x2, + LSE = 0x3, + }; + + pub const LPUART3SEL = enum(u2) { + PCLK1 = 0x0, + SYS = 0x1, + HSI = 0x2, + LSE = 0x3, + }; + + pub const LSCOSEL = enum(u1) { + LSI = 0x0, + LSE = 0x1, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const LSIPREDIV = enum(u1) { + Div1 = 0x0, + Div128 = 0x1, + }; + + pub const MCOPRE = enum(u4) { + Div1 = 0x0, + Div2 = 0x1, + Div4 = 0x2, + Div8 = 0x3, + Div16 = 0x4, + Div32 = 0x5, + Div64 = 0x6, + Div128 = 0x7, + Div256 = 0x8, + Div512 = 0x9, + Div1024 = 0xa, + _, + }; + + pub const MCOSEL = enum(u4) { + DISABLE = 0x0, + SYS = 0x1, + MSI = 0x2, + HSI = 0x3, + HSE = 0x4, + PLL1_R = 0x5, + LSI = 0x6, + LSE = 0x7, + HSI48 = 0x8, + RTC = 0x9, + RTC_WKUP = 0xa, + _, + }; + + pub const MSIRANGE = enum(u4) { + /// range 0 around 100 kHz + Range100K = 0x0, + /// range 1 around 200 kHz + Range200K = 0x1, + /// range 2 around 400 kHz + Range400K = 0x2, + /// range 3 around 800 kHz + Range800K = 0x3, + /// range 4 around 1 MHz + Range1M = 0x4, + /// range 5 around 2 MHz + Range2M = 0x5, + /// range 6 around 4 MHz + Range4M = 0x6, + /// range 7 around 8 MHz + Range8M = 0x7, + /// range 8 around 16 MHz + Range16M = 0x8, + /// range 9 around 24 MHz + Range24M = 0x9, + /// range 10 around 32 MHz + Range32M = 0xa, + /// range 11 around 48 MHz + Range48M = 0xb, + _, + }; + + pub const MSIRGSEL = enum(u1) { + /// MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register + CSR = 0x0, + /// MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register + CR = 0x1, + }; + + pub const MSISRANGE = enum(u4) { + RANGE_81MHz = 0x4, + _, + }; + + pub const PLLM = enum(u3) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + }; + + pub const PLLN = enum(u7) { + Mul4 = 0x4, + Mul5 = 0x5, + Mul6 = 0x6, + Mul7 = 0x7, + Mul8 = 0x8, + Mul9 = 0x9, + Mul10 = 0xa, + Mul11 = 0xb, + Mul12 = 0xc, + Mul13 = 0xd, + Mul14 = 0xe, + Mul15 = 0xf, + Mul16 = 0x10, + Mul17 = 0x11, + Mul18 = 0x12, + Mul19 = 0x13, + Mul20 = 0x14, + Mul21 = 0x15, + Mul22 = 0x16, + Mul23 = 0x17, + Mul24 = 0x18, + Mul25 = 0x19, + Mul26 = 0x1a, + Mul27 = 0x1b, + Mul28 = 0x1c, + Mul29 = 0x1d, + Mul30 = 0x1e, + Mul31 = 0x1f, + Mul32 = 0x20, + Mul33 = 0x21, + Mul34 = 0x22, + Mul35 = 0x23, + Mul36 = 0x24, + Mul37 = 0x25, + Mul38 = 0x26, + Mul39 = 0x27, + Mul40 = 0x28, + Mul41 = 0x29, + Mul42 = 0x2a, + Mul43 = 0x2b, + Mul44 = 0x2c, + Mul45 = 0x2d, + Mul46 = 0x2e, + Mul47 = 0x2f, + Mul48 = 0x30, + Mul49 = 0x31, + Mul50 = 0x32, + Mul51 = 0x33, + Mul52 = 0x34, + Mul53 = 0x35, + Mul54 = 0x36, + Mul55 = 0x37, + Mul56 = 0x38, + Mul57 = 0x39, + Mul58 = 0x3a, + Mul59 = 0x3b, + Mul60 = 0x3c, + Mul61 = 0x3d, + Mul62 = 0x3e, + Mul63 = 0x3f, + Mul64 = 0x40, + Mul65 = 0x41, + Mul66 = 0x42, + Mul67 = 0x43, + Mul68 = 0x44, + Mul69 = 0x45, + Mul70 = 0x46, + Mul71 = 0x47, + Mul72 = 0x48, + Mul73 = 0x49, + Mul74 = 0x4a, + Mul75 = 0x4b, + Mul76 = 0x4c, + Mul77 = 0x4d, + Mul78 = 0x4e, + Mul79 = 0x4f, + Mul80 = 0x50, + Mul81 = 0x51, + Mul82 = 0x52, + Mul83 = 0x53, + Mul84 = 0x54, + Mul85 = 0x55, + Mul86 = 0x56, + Mul87 = 0x57, + Mul88 = 0x58, + Mul89 = 0x59, + Mul90 = 0x5a, + Mul91 = 0x5b, + Mul92 = 0x5c, + Mul93 = 0x5d, + Mul94 = 0x5e, + Mul95 = 0x5f, + Mul96 = 0x60, + Mul97 = 0x61, + Mul98 = 0x62, + Mul99 = 0x63, + Mul100 = 0x64, + Mul101 = 0x65, + Mul102 = 0x66, + Mul103 = 0x67, + Mul104 = 0x68, + Mul105 = 0x69, + Mul106 = 0x6a, + Mul107 = 0x6b, + Mul108 = 0x6c, + Mul109 = 0x6d, + Mul110 = 0x6e, + Mul111 = 0x6f, + Mul112 = 0x70, + Mul113 = 0x71, + Mul114 = 0x72, + Mul115 = 0x73, + Mul116 = 0x74, + Mul117 = 0x75, + Mul118 = 0x76, + Mul119 = 0x77, + Mul120 = 0x78, + Mul121 = 0x79, + Mul122 = 0x7a, + Mul123 = 0x7b, + Mul124 = 0x7c, + Mul125 = 0x7d, + Mul126 = 0x7e, + Mul127 = 0x7f, + _, + }; + + pub const PLLP = enum(u5) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + Div17 = 0x10, + Div18 = 0x11, + Div19 = 0x12, + Div20 = 0x13, + Div21 = 0x14, + Div22 = 0x15, + Div23 = 0x16, + Div24 = 0x17, + Div25 = 0x18, + Div26 = 0x19, + Div27 = 0x1a, + Div28 = 0x1b, + Div29 = 0x1c, + Div30 = 0x1d, + Div31 = 0x1e, + Div32 = 0x1f, + _, + }; + + pub const PLLQ = enum(u3) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + _, + }; + + pub const PLLR = enum(u3) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + _, + }; + + pub const PLLSRC = enum(u2) { + DISABLE = 0x0, + MSI = 0x1, + HSI = 0x2, + HSE = 0x3, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const RTCSEL = enum(u2) { + DISABLE = 0x0, + LSE = 0x1, + LSI = 0x2, + HSE = 0x3, + }; + + pub const SW = enum(u3) { + MSI = 0x0, + HSI = 0x1, + HSE = 0x2, + PLL1_R = 0x3, + LSI = 0x4, + LSE = 0x5, + _, + }; + + pub const TIM15SEL = enum(u1) { + PCLK1_TIM = 0x0, + PLL1_Q = 0x1, + }; + + pub const TIM1SEL = enum(u1) { + PCLK1_TIM = 0x0, + PLL1_Q = 0x1, + }; + + pub const USART1SEL = enum(u2) { + PCLK1 = 0x0, + SYS = 0x1, + HSI = 0x2, + LSE = 0x3, + }; + + pub const USART2SEL = enum(u2) { + PCLK1 = 0x0, + SYS = 0x1, + HSI = 0x2, + LSE = 0x3, + }; + + /// RCC address block description. + pub const RCC = extern struct { + /// Clock control register. + CR: mmio.Mmio(packed struct(u32) { + /// MSI clock enable This bit is set and cleared by software. Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator Set by hardware when used directly or indirectly as system clock. + MSION: u1, + /// MSI clock ready flag This bit is set by hardware to indicate that the MSI oscillator is stable. Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles. + MSIRDY: u1, + /// MSI clock PLL enable Set and cleared by software to enable/ disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure (refer to RCC_CSR register). + MSIPLLEN: u1, + /// MSI clock range selection Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect. After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by MSISRANGE in CSR register. + MSIRGSEL: packed union { + raw: u1, + value: MSIRGSEL, + }, + /// MSI clock ranges These bits are configured by software to choose the frequency range of MSI when MSIRGSEL is set.12 frequency ranges are available: others: not allowed (hardware write protection) Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT ready (MSION=1 and MSIRDY=0). + MSIRANGE: packed union { + raw: u4, + value: MSIRANGE, + }, + /// HSI clock enable Set and cleared by software. Cleared by hardware to stop the HSI oscillator when entering Stop, Standby, or Shutdown mode. Forced by hardware to keep the HSI oscillator ON when it is used directly or indirectly as system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of the HSE oscillator used for system clock). + HSION: u1, + /// HSI always enable for peripheral kernels. Set and cleared by software to force HSI ON even in Stop modes. The HSI can only feed USART1, USART2, CEC and I2C1 peripherals configured with HSI as kernel clock. Keeping the HSI ON in Stop mode allows avoiding to slow down the communication speed because of the HSI startup time. This bit has no effect on HSION value. + HSIKERON: u1, + /// HSI clock ready flag Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI clock cycles. + HSIRDY: u1, + /// HSI automatic start from Stop Set and cleared by software. When the system wake-up clock is MSI, this bit is used to wake up the HSI is parallel of the system wake-up. + HSIASFS: u1, + reserved16: u4, + /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. + HSEON: u1, + /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. + HSERDY: u1, + /// HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + HSEBYP: u1, + /// Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. + CSSON: u1, + reserved24: u4, + /// PLL enable Set and cleared by software to enable the PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. + PLLON: u1, + /// PLL clock ready flag Set by hardware to indicate that the PLL is locked. + PLLRDY: u1, + padding: u6, + }), + /// Internal clock sources calibration register. + ICSCR: mmio.Mmio(packed struct(u32) { + /// MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value. + MSICAL: u8, + /// MSI clock trimming These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI. + MSITRIM: u8, + /// HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. + HSICAL: u8, + /// HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI. The default value is 64 when added to the HSICAL value, trim the HSI to 161MHz 1 11%. + HSITRIM: u7, + padding: u1, + }), + /// Clock configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected. + SW: packed union { + raw: u3, + value: SW, + }, + /// System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved. + SWS: packed union { + raw: u3, + value: SW, + }, + reserved8: u2, + /// AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1 Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Section14.1.4: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1. + PPRE: packed union { + raw: u3, + value: PPRE, + }, + /// Wake-up from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=10) or a switch on HSE is requested (SW=10). + STOPWUCK: u1, + /// Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching. + MCO2SEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: ... Others: reserved It is highly recommended to set this field before the MCO2 output is enabled. + MCO2PRE: packed union { + raw: u4, + value: MCOPRE, + }, + /// Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. + MCOSEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: ... Others: reserved It is highly recommended to set this field before the MCO output is enabled. + MCOPRE: packed union { + raw: u4, + value: MCOPRE, + }, + }), + /// PLL configuration register. + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// PLL input clock source This bit is controlled by software to select PLL clock source, as follows: The bitfield can be written only when the PLL is disabled. When the PLL is not used, selecting 00 allows saving power. + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + reserved4: u2, + /// Division factor M of the PLL input clock divider This bit is controlled by software to divide the PLL input clock before the actual phase-locked loop, as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the PLL input frequency after the /M divider is between 2.66 and 161MHz. + PLLM: packed union { + raw: u3, + value: PLLM, + }, + reserved8: u1, + /// PLL frequency multiplication factor N This bit is controlled by software to set the division factor of the fVCO feedback divider (that determines the PLL multiplication ratio) as follows: ... ... The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the VCO output frequency is between 96 and 3441MHz. + PLLN: packed union { + raw: u7, + value: PLLN, + }, + reserved16: u1, + /// PLLPCLK clock output enable This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL: Disabling the PLLPCLK clock output, when not used, allows saving power. + PLLPEN: u1, + /// PLL VCO division factor P for PLLPCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor P as follows: ... The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock. + PLLP: packed union { + raw: u5, + value: PLLP, + }, + reserved24: u2, + /// PLLQCLK clock output enable This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL: Disabling the PLLQCLK clock output, when not used, allows saving power. + PLLQEN: u1, + /// PLL VCO division factor Q for PLLQCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock. + PLLQ: packed union { + raw: u3, + value: PLLQ, + }, + /// PLLRCLK clock output enable This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL: This bit cannot be written when PLLRCLK output of the PLL is selected for system clock. Disabling the PLLRCLK clock output, when not used, allows saving power. + PLLREN: u1, + /// PLL VCO division factor R for PLLRCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor R as follows: The bitfield can be written only when the PLL is disabled. The PLLRCLK clock can be selected as system clock. Caution: The software must set this bitfield so as not to exceed 122MHz on this clock. + PLLR: packed union { + raw: u3, + value: PLLR, + }, + }), + reserved24: [8]u8, + /// Clock interrupt enable register. + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:. + LSIRDYIE: u1, + /// LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:. + LSERDYIE: u1, + /// MSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. + MSIRDYIE: u1, + /// HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization:. + HSIRDYIE: u1, + /// HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:. + HSERDYIE: u1, + /// PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock:. + PLLRDYIE: u1, + reserved9: u3, + /// LSE clock security system interrupt enable Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. + LSECSSIE: u1, + /// HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. + HSI48RDYIE: u1, + padding: u21, + }), + /// Clock interrupt flag register. + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. + LSIRDYF: u1, + /// LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. + LSERDYF: u1, + /// MSI ready interrupt flag Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set. Cleared by software setting the MSIRDYC bit. + MSIRDYF: u1, + /// HSI ready interrupt flag Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. + HSIRDYF: u1, + /// HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit. + HSERDYF: u1, + /// PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYIE is set. Cleared by software setting the PLLRDYC bit. + PLLRDYF: u1, + reserved8: u2, + /// HSE clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. + CSSF: u1, + /// LSE clock security system interrupt flag Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit. + LSECSSF: u1, + /// HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to RCC clock recovery RC register (RCC_CRRCR)). Cleared by software setting the HSI48RDYC bit. + HSI48RDYF: u1, + padding: u21, + }), + /// Clock interrupt clear register. + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. + LSIRDYC: u1, + /// LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. + LSERDYC: u1, + /// MSI ready interrupt clear This bit is set by software to clear the MSIRDYF flag. + MSIRDYC: u1, + /// HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag. + HSIRDYC: u1, + /// HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. + HSERDYC: u1, + /// PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. + PLLRDYC: u1, + reserved8: u2, + /// Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag. + CSSC: u1, + /// LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag. + LSECSSC: u1, + /// HSI48 oscillator ready interrupt clear This bit is set by software to clear the HSI48RDYF flag. + HSI48RDYC: u1, + padding: u21, + }), + reserved40: [4]u8, + /// AHB peripheral reset register. + AHBRSTR: mmio.Mmio(packed struct(u32) { + /// DMA1 and DMAMUX reset Set and cleared by software. + DMA1RST: u1, + /// DMA2 and DMAMUX reset Set and cleared by software. + DMA2RST: u1, + reserved8: u6, + /// Flash memory interface reset Set and cleared by software. This bit can only be set when the flash memory is in power down mode. + FLASHRST: u1, + reserved12: u3, + /// CRC reset Set and cleared by software. + CRCRST: u1, + reserved16: u3, + /// AES hardware accelerator reset Set and cleared by software. + AESRST: u1, + reserved18: u1, + /// Random number generator reset Set and cleared by software. + RNGRST: u1, + reserved24: u5, + /// Touch sensing controller reset Set and cleared by software. + TSCRST: u1, + padding: u7, + }), + /// I/O port reset register. + GPIORSTR: mmio.Mmio(packed struct(u32) { + /// I/O port A reset This bit is set and cleared by software. + GPIOARST: u1, + /// I/O port B reset This bit is set and cleared by software. + GPIOBRST: u1, + /// I/O port C reset This bit is set and cleared by software. + GPIOCRST: u1, + /// I/O port D reset This bit is set and cleared by software. + GPIODRST: u1, + /// I/O port E reset This bit is set and cleared by software. + GPIOERST: u1, + /// I/O port F reset This bit is set and cleared by software. + GPIOFRST: u1, + padding: u26, + }), + reserved56: [8]u8, + /// APB peripheral reset register 1. + APBRSTR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer reset Set and cleared by software. + TIM2RST: u1, + /// TIM3 timer reset Set and cleared by software. + TIM3RST: u1, + reserved4: u2, + /// TIM6 timer reset Set and cleared by software. + TIM6RST: u1, + /// TIM7 timer reset Set and cleared by software. + TIM7RST: u1, + reserved7: u1, + /// LPUART2 reset Set and cleared by software. + LPUART2RST: u1, + reserved9: u1, + /// LCD reset(1) Set and cleared by software. + LCDRST: u1, + reserved12: u2, + /// LPUART3 reset(1) Set and cleared by software. + LPUART3RST: u1, + /// USB reset(1) Set and cleared by software. + USBRST: u1, + /// SPI2 reset Set and cleared by software. + SPI2RST: u1, + /// SPI3 reset(1) Set and cleared by software. + SPI3RST: u1, + /// CRS reset(1) Set and cleared by software. + CRSRST: u1, + /// USART2 reset Set and cleared by software. + USART2RST: u1, + /// USART3 reset Set and cleared by software. + USART3RST: u1, + /// USART4 reset Set and cleared by software. + USART4RST: u1, + /// LPUART1 reset Set and cleared by software. + LPUART1RST: u1, + /// I2C1 reset Set and cleared by software. + I2C1RST: u1, + /// I2C2 reset Set and cleared by software. + I2C2RST: u1, + /// I2C3 reset Set and cleared by software. + I2C3RST: u1, + /// OPAMP reset Set and cleared by software. + OPAMPRST: u1, + /// I2C4 reset(1) Set and cleared by software. + I2C4RST: u1, + /// LPTIM3 reset Set and cleared by software. + LPTIM3RST: u1, + reserved28: u1, + /// Power interface reset Set and cleared by software. + PWRRST: u1, + /// DAC1 interface reset Set and cleared by software. + DAC1RST: u1, + /// Low Power Timer 2 reset Set and cleared by software. + LPTIM2RST: u1, + /// Low Power Timer 1 reset Set and cleared by software. + LPTIM1RST: u1, + }), + reserved64: [4]u8, + /// APB peripheral reset register 2. + APBRSTR2: mmio.Mmio(packed struct(u32) { + /// SYSCFG, COMP and VREFBUF reset Set and cleared by software. + SYSCFGRST: u1, + reserved11: u10, + /// TIM1 timer reset Set and cleared by software. + TIM1RST: u1, + /// SPI1 reset Set and cleared by software. + SPI1RST: u1, + reserved14: u1, + /// USART1 reset Set and cleared by software. + USART1RST: u1, + reserved16: u1, + /// TIM15 timer reset Set and cleared by software. + TIM15RST: u1, + /// TIM16 timer reset Set and cleared by software. + TIM16RST: u1, + reserved20: u2, + /// ADC reset Set and cleared by software. + ADCRST: u1, + padding: u11, + }), + reserved72: [4]u8, + /// AHB peripheral clock enable register. + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled. + DMA1EN: u1, + /// DMA2 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled. + DMA2EN: u1, + reserved8: u6, + /// Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the flash memory is in power down mode. + FLASHEN: u1, + reserved12: u3, + /// CRC clock enable Set and cleared by software. + CRCEN: u1, + reserved16: u3, + /// AES hardware accelerator Set and cleared by software. + AESEN: u1, + reserved18: u1, + /// Random number generator clock enable Set and cleared by software. + RNGEN: u1, + reserved24: u5, + /// Touch sensing controller clock enable Set and cleared by software. + TSCEN: u1, + padding: u7, + }), + /// I/O port clock enable register. + GPIOENR: mmio.Mmio(packed struct(u32) { + /// I/O port A clock enable This bit is set and cleared by software. + GPIOAEN: u1, + /// I/O port B clock enable This bit is set and cleared by software. + GPIOBEN: u1, + /// I/O port C clock enable This bit is set and cleared by software. + GPIOCEN: u1, + /// I/O port D clock enable This bit is set and cleared by software. + GPIODEN: u1, + /// I/O port E clock enable(1) This bit is set and cleared by software. + GPIOEEN: u1, + /// I/O port F clock enable This bit is set and cleared by software. + GPIOFEN: u1, + padding: u26, + }), + /// Debug configuration register. + DBGCFGR: mmio.Mmio(packed struct(u32) { + /// Debug support clock enable Set and cleared by software. + DBGEN: u1, + /// Debug support reset Set and cleared by software. + DBGRST: u1, + padding: u30, + }), + reserved88: [4]u8, + /// APB peripheral clock enable register 1. + APBENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clock enable Set and cleared by software. + TIM2EN: u1, + /// TIM3 timer clock enable Set and cleared by software. + TIM3EN: u1, + reserved4: u2, + /// TIM6 timer clock enable Set and cleared by software. + TIM6EN: u1, + /// TIM7 timer clock enable Set and cleared by software. + TIM7EN: u1, + reserved7: u1, + /// LPUART2 clock enable Set and cleared by software. + LPUART2EN: u1, + reserved9: u1, + /// LCD clock enable(1) Set and cleared by software. + LCDEN: u1, + /// RTC APB clock enable Set and cleared by software. + RTCAPBEN: u1, + /// WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0. + WWDGEN: u1, + /// LPUART3 clock enable Set and cleared by software. + LPUART3EN: u1, + /// USB clock enable(1) Set and cleared by software. + USBEN: u1, + /// SPI2 clock enable Set and cleared by software. + SPI2EN: u1, + /// SPI3 clock enable(1) Set and cleared by software. + SPI3EN: u1, + /// CRS clock enable(1) Set and cleared by software. + CRSEN: u1, + /// USART2 clock enable Set and cleared by software. + USART2EN: u1, + /// USART3 clock enable Set and cleared by software. + USART3EN: u1, + /// USART4 clock enable Set and cleared by software. + USART4EN: u1, + /// LPUART1 clock enable Set and cleared by software. + LPUART1EN: u1, + /// I2C1 clock enable Set and cleared by software. + I2C1EN: u1, + /// I2C2 clock enable Set and cleared by software. + I2C2EN: u1, + /// I2C3 clock enable Set and cleared by software. + I2C3EN: u1, + /// OPAMP clock enable Set and cleared by software. + OPAMPEN: u1, + /// I2C4EN clock enable(1) Set and cleared by software. + I2C4EN: u1, + /// LPTIM3 clock enable Set and cleared by software. + LPTIM3EN: u1, + reserved28: u1, + /// Power interface clock enable Set and cleared by software. + PWREN: u1, + /// DAC1 interface clock enable Set and cleared by software. + DAC1EN: u1, + /// LPTIM2 clock enable Set and cleared by software. + LPTIM2EN: u1, + /// LPTIM1 clock enable Set and cleared by software. + LPTIM1EN: u1, + }), + reserved96: [4]u8, + /// APB peripheral clock enable register 2. + APBENR2: mmio.Mmio(packed struct(u32) { + /// SYSCFG, COMP and VREFBUF clock enable Set and cleared by software. + SYSCFGEN: u1, + reserved11: u10, + /// TIM1 timer clock enable Set and cleared by software. + TIM1EN: u1, + /// SPI1 clock enable Set and cleared by software. + SPI1EN: u1, + reserved14: u1, + /// USART1 clock enable Set and cleared by software. + USART1EN: u1, + reserved16: u1, + /// TIM15 timer clock enable Set and cleared by software. + TIM15EN: u1, + /// TIM16 timer clock enable Set and cleared by software. + TIM16EN: u1, + reserved20: u2, + /// ADC clock enable Set and cleared by software. + ADCEN: u1, + padding: u11, + }), + reserved104: [4]u8, + /// AHB peripheral clock enable in Sleep/Stop mode register. + AHBSMENR: mmio.Mmio(packed struct(u32) { + /// DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. + DMA1SMEN: u1, + /// DMA2 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. + DMA2SMEN: u1, + reserved8: u6, + /// Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the flash memory is in power down mode. + FLASHSMEN: u1, + /// SRAM clock enable during Sleep mode Set and cleared by software. + SRAMSMEN: u1, + reserved12: u2, + /// CRC clock enable during Sleep mode Set and cleared by software. + CRCSMEN: u1, + reserved16: u3, + /// AES hardware accelerator clock enable during Sleep mode Set and cleared by software. + AESSMEN: u1, + reserved18: u1, + /// RNG clock enable during Sleep and Stop mode Set and cleared by software. + RNGSMEN: u1, + reserved24: u5, + /// TSC clock enable during Sleep and Stop mode Set and cleared by software. + TSCSMEN: u1, + padding: u7, + }), + /// I/O port in Sleep mode clock enable register. + GPIOSMENR: mmio.Mmio(packed struct(u32) { + /// I/O port A clock enable during Sleep mode Set and cleared by software. + GPIOASMEN: u1, + /// I/O port B clock enable during Sleep mode Set and cleared by software. + GPIOBSMEN: u1, + /// I/O port C clock enable during Sleep mode Set and cleared by software. + GPIOCSMEN: u1, + /// I/O port D clock enable during Sleep mode(1) Set and cleared by software. + GPIODSMEN: u1, + /// I/O port E clock enable during Sleep mode Set and cleared by software. + GPIOESMEN: u1, + /// I/O port F clock enable during Sleep mode Set and cleared by software. + GPIOFSMEN: u1, + padding: u26, + }), + reserved120: [8]u8, + /// APB peripheral clock enable in Sleep/Stop mode register 1. + APBSMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clock enable during Sleep mode Set and cleared by software. + TIM2SMEN: u1, + /// TIM3 timer clock enable during Sleep mode Set and cleared by software. + TIM3SMEN: u1, + reserved4: u2, + /// TIM6 timer clock enable during Sleep mode Set and cleared by software. + TIM6SMEN: u1, + /// TIM7 timer clock enable during Sleep mode Set and cleared by software. + TIM7SMEN: u1, + reserved7: u1, + /// LPUART2 clock enable during Sleep and Stop modes Set and cleared by software. + LPUART2SMEN: u1, + reserved9: u1, + /// LCD clock enable during Sleep mode(1) Set and cleared by software. + LCDSMEN: u1, + /// RTC APB clock enable during Sleep mode Set and cleared by software. + RTCAPBSMEN: u1, + /// WWDG clock enable during Sleep and Stop modes Set and cleared by software. + WWDGSMEN: u1, + /// LPUART3 clock enable during Sleep and Stop modes Set and cleared by software. + LPUART3SMEN: u1, + /// USB clock enable during Sleep mode(1) Set and cleared by software. + USBSMEN: u1, + /// SPI2 clock enable during Sleep mode Set and cleared by software. + SPI2SMEN: u1, + /// SPI3 clock enable during Sleep mode(1) Set and cleared by software. + SPI3SMEN: u1, + /// CRS clock enable during Sleep and Stop modes(1) Set and cleared by software. + CRSSMEN: u1, + /// USART2 clock enable during Sleep and Stop modes Set and cleared by software. + USART2SMEN: u1, + /// USART3 clock enable during Sleep mode Set and cleared by software. + USART3SMEN: u1, + /// USART4 clock enable during Sleep mode Set and cleared by software. + USART4SMEN: u1, + /// LPUART1 clock enable during Sleep and Stop modes Set and cleared by software. + LPUART1SMEN: u1, + /// I2C1 clock enable during Sleep and Stop modes Set and cleared by software. + I2C1SMEN: u1, + /// I2C2 clock enable during Sleep mode Set and cleared by software. + I2C2SMEN: u1, + /// I2C3 clock enable during Sleep mode Set and cleared by software. + I2C3SMEN: u1, + /// OPAMP clock enable during Sleep and Stop modes Set and cleared by software. + OPAMPSMEN: u1, + /// I2C4 clock enable during Sleep mode(1) Set and cleared by software. + I2C4SMEN: u1, + /// Low power timer 3 clock enable during Sleep mode Set and cleared by software. + LPTIM3SMEN: u1, + reserved28: u1, + /// Power interface clock enable during Sleep mode Set and cleared by software. + PWRSMEN: u1, + /// DAC1 interface clock enable during Sleep and Stop modes Set and cleared by software. + DAC1SMEN: u1, + /// Low Power Timer 2 clock enable during Sleep and Stop modes Set and cleared by software. + LPTIM2SMEN: u1, + /// Low Power Timer 1 clock enable during Sleep and Stop modes Set and cleared by software. + LPTIM1SMEN: u1, + }), + reserved128: [4]u8, + /// APB peripheral clock enable in Sleep/Stop mode register 2. + APBSMENR2: mmio.Mmio(packed struct(u32) { + /// SYSCFG, COMP and VREFBUF clock enable during Sleep and Stop modes Set and cleared by software. + SYSCFGSMEN: u1, + reserved11: u10, + /// TIM1 timer clock enable during Sleep mode Set and cleared by software. + TIM1SMEN: u1, + /// SPI1 clock enable during Sleep mode Set and cleared by software. + SPI1SMEN: u1, + reserved14: u1, + /// USART1 clock enable during Sleep and Stop modes Set and cleared by software. + USART1SMEN: u1, + reserved16: u1, + /// TIM15 timer clock enable during Sleep mode Set and cleared by software. + TIM15SMEN: u1, + /// TIM16 timer clock enable during Sleep mode Set and cleared by software. + TIM16SMEN: u1, + reserved20: u2, + /// ADC clock enable during Sleep mode Set and cleared by software. + ADCSMEN: u1, + padding: u11, + }), + reserved136: [4]u8, + /// Peripherals independent clock configuration register. + CCIPR: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows:. + USART1SEL: packed union { + raw: u2, + value: USART1SEL, + }, + /// USART2 clock source selection This bitfield is controlled by software to select USART2 clock source as follows:. + USART2SEL: packed union { + raw: u2, + value: USART2SEL, + }, + reserved6: u2, + /// LPUART3 clock source selection(1) This bitfield is controlled by software to select LPUART3 clock source as follows:. + LPUART3SEL: packed union { + raw: u2, + value: LPUART3SEL, + }, + /// LPUART2 clock source selection This bitfield is controlled by software to select LPUART2 clock source as follows:. + LPUART2SEL: packed union { + raw: u2, + value: LPUART2SEL, + }, + /// LPUART1 clock source selection This bitfield is controlled by software to select LPUART1 clock source as follows:. + LPUART1SEL: packed union { + raw: u2, + value: LPUART1SEL, + }, + /// I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows:. + I2C1SEL: packed union { + raw: u2, + value: I2C1SEL, + }, + reserved16: u2, + /// I2C3 clock source selection This bitfield is controlled by software to select I2C3 clock source as follows:. + I2C3SEL: packed union { + raw: u2, + value: I2C3SEL, + }, + /// LPTIM1 clock source selection This bitfield is controlled by software to select LPTIM1 clock source as follows:. + LPTIM1SEL: packed union { + raw: u2, + value: LPTIM1SEL, + }, + /// LPTIM2 clock source selection This bitfield is controlled by software to select LPTIM2 clock source as follows:. + LPTIM2SEL: packed union { + raw: u2, + value: LPTIM2SEL, + }, + /// LPTIM3 clock source selection This bitfield is controlled by software to select LPTIM3 clock source as follows:. + LPTIM3SEL: packed union { + raw: u2, + value: LPTIM3SEL, + }, + /// TIM1 clock source selection This bit is set and cleared by software. It selects TIM1 clock source as follows:. + TIM1SEL: packed union { + raw: u1, + value: TIM1SEL, + }, + /// TIM15 clock source selection This bit is set and cleared by software. It selects TIM15 clock source as follows:. + TIM15SEL: packed union { + raw: u1, + value: TIM15SEL, + }, + /// 481MHz clock source selection This bitfield is controlled by software to select the 481MHz clock source used by the USB FS and the RNG:. + CLK48SEL: packed union { + raw: u2, + value: CLK48SEL, + }, + /// ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC:. + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, + padding: u2, + }), + reserved144: [4]u8, + /// RTC domain control register. + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enable Set and cleared by software to enable LSE oscillator:. + LSEON: u1, + /// LSE oscillator ready Set and cleared by hardware to indicate when the external 321kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. + LSERDY: u1, + /// LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 321kHz oscillator is disabled (LSEON=0 and LSERDY=0). + LSEBYP: u1, + /// LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode. + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// CSS on LSE enable Set by software to enable the clock security system on LSE (321kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit. + LSECSSON: u1, + /// CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 321kHz oscillator (LSE):. + LSECSSD: u1, + /// LSE clock enable for system usage This bit must be set by software to enable the LSE clock for a system usage. + LSESYSEN: u1, + /// RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset this bitfield to 00. + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved11: u1, + /// LSE clock ready for system usage This flag is set by hardware to indicate that the LSE clock is ready for being used by the system (see LSESYSEN bit). This flag is set when LSE clock is ready (LSEON1=11 and LSERDY1=11) and two LSE clock cycles after that LSESYSEN is set. Cleared by hardware to indicate that the LSE clock is not ready to be used by the system. + LSESYSRDY: u1, + reserved15: u3, + /// RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP. + RTCEN: u1, + /// RTC domain software reset Set and cleared by software to reset the RTC domain:. + BDRST: u1, + reserved24: u7, + /// Low-speed clock output (LSCO) enable Set and cleared by software. + LSCOEN: u1, + /// Low-speed clock output selection Set and cleared by software to select the low-speed output clock:. + LSCOSEL: packed union { + raw: u1, + value: LSCOSEL, + }, + padding: u6, + }), + /// Control/status register. + CSR: mmio.Mmio(packed struct(u32) { + /// LSI oscillator enable Set and cleared by software to enable/disable the LSI oscillator:. + LSION: u1, + /// LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. + LSIRDY: u1, + /// Internal low-speed oscillator pre-divided by 128 Set and reset by hardware to indicate when the low-speed internal RC oscillator has to be divided by 128. The software has to switch off the LSI before changing this bit. + LSIPREDIV: packed union { + raw: u1, + value: LSIPREDIV, + }, + reserved8: u5, + /// MSI range after Standby mode Set by software to chose the MSI frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always 41MHz. MSISRANGE[3:0] can be written only when MSIRGSEL1=11. Others: Reserved Note: Changing the MSISRANGE[3:0] does not change the current MSI frequency. + MSISRANGE: packed union { + raw: u4, + value: MSISRANGE, + }, + reserved23: u11, + /// Remove reset flags Set by software to clear the reset flags. + RMVF: u1, + reserved25: u1, + /// Option byte loader reset flag Set by hardware when a reset from the Option byte loading occurs. Cleared by setting the RMVF bit. + OBLRSTF: u1, + /// Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by setting the RMVF bit. + PINRSTF: u1, + /// BOR or POR/PDR flag Set by hardware when a BOR or POR/PDR occurs. Cleared by setting the RMVF bit. + PWRRSTF: u1, + /// Software reset flag Set by hardware when a software reset occurs. Cleared by setting the RMVF bit. + SFTRSTF: u1, + /// Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by setting the RMVF bit. + IWDGRSTF: u1, + /// Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by setting the RMVF bit. + WWDGRSTF: u1, + /// Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. This operates only if nRST_STOP, nRST_STDBY or nRST_SHDW option bits are cleared. + LPWRRSTF: u1, + }), + /// RCC clock recovery RC register. + CRRCR: mmio.Mmio(packed struct(u32) { + /// HSI48 RC oscillator enable(1). + HSI48ON: u1, + /// HSI48 clock ready flag(1) The flag is set when the HSI48 clock is ready for use. + HSI48RDY: u1, + reserved7: u5, + /// HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. + HSI48CAL: u9, + padding: u16, + }), + }; + }; + + pub const rcc_u5 = struct { + pub const ADCDACSEL = enum(u3) { + /// HCLK clock selected + HCLK1 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// PLL2 R (pll2_r_ck) selected + PLL2_R = 0x2, + /// HSE clock selected + HSE = 0x3, + /// HSI clock selected + HSI = 0x4, + /// MSIK clock selected + MSIK = 0x5, + _, + }; + + pub const ADFSEL = enum(u3) { + /// HCLK selected + HCLK3 = 0x0, + /// PLL1 P (pll1_p_ck) selected + PLL1_P = 0x1, + /// PLL3 Q (pll3_q_ck) selected + PLL3_Q = 0x2, + /// input pin AUDIOCLK selected + AUDIOCLK = 0x3, + /// MSIK clock selected + MSIK = 0x4, + _, + }; + + pub const DACSEL = enum(u1) { + /// LSE selected + LSE = 0x0, + /// LSI selected + LSI = 0x1, + }; + + pub const DPRE = enum(u3) { + /// DCLK not divided + Div1 = 0x0, + /// DCLK divided by 2 + Div2 = 0x4, + /// DCLK divided by 4 + Div4 = 0x5, + /// DCLK divided by 8 + Div8 = 0x6, + /// DCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const DSISEL = enum(u1) { + /// PLL3 “P” (pll3_p_ck) selected + PLL3_P = 0x0, + /// DSI PHY PLL output selected (formerly called DCLK, renamed to DSI_PHY to match other chip families) + DSI_PHY = 0x1, + }; + + pub const FDCANSEL = enum(u2) { + /// HSE clock selected + HSE = 0x0, + /// PLL1 Q (pll1_q_ck) selected + PLL1_Q = 0x1, + /// PLL2 P (pll2_p_ck) selected + PLL2_P = 0x2, + _, + }; + + pub const HPRE = enum(u4) { + /// SYSCLK not divided + Div1 = 0x0, + /// SYSCLK divided by 2 + Div2 = 0x8, + /// SYSCLK divided by 4 + Div4 = 0x9, + /// SYSCLK divided by 8 + Div8 = 0xa, + /// SYSCLK divided by 16 + Div16 = 0xb, + /// SYSCLK divided by 64 + Div64 = 0xc, + /// SYSCLK divided by 128 + Div128 = 0xd, + /// SYSCLK divided by 256 + Div256 = 0xe, + /// SYSCLK divided by 512 + Div512 = 0xf, + _, + }; + + pub const HSEEXT = enum(u1) { + /// external HSE clock analog mode + ANALOG = 0x0, + /// external HSE clock digital mode (through I/O Schmitt trigger) + DIGITAL = 0x1, + }; + + pub const HSPISEL = enum(u2) { + /// SYSCLK selected + SYS = 0x0, + /// PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz + PLL1_Q = 0x1, + /// PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz + PLL2_Q = 0x2, + /// PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz + PLL3_R = 0x3, + }; + + pub const I2C3SEL = enum(u2) { + /// PCLK3 selected + PCLK3 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + /// MSIK selected + MSIK = 0x3, + }; + + pub const I2CSEL = enum(u2) { + /// PCLK1 selected + PCLK1 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + /// MSIK selected + MSIK = 0x3, + }; + + pub const ICLKSEL = enum(u2) { + /// HSI48 clock selected + HSI48 = 0x0, + /// PLL2 Q (pll2_q_ck) selected + PLL2_Q = 0x1, + /// PLL1 Q (pll1_q_ck) selected + PLL1_Q = 0x2, + /// MSIK clock selected + MSIK = 0x3, + }; + + pub const LPTIM2SEL = enum(u2) { + /// PCLK1 selected + PCLK1 = 0x0, + /// LSI selected + LSI = 0x1, + /// HSI selected + HSI = 0x2, + /// LSE selected + LSE = 0x3, + }; + + pub const LPTIMSEL = enum(u2) { + /// PCLK3 selected + PCLK3 = 0x0, + /// LSI selected + LSI = 0x1, + /// HSI selected + HSI = 0x2, + /// LSE selected + LSE = 0x3, + }; + + pub const LPUSARTSEL = enum(u3) { + /// PCLK3 selected + PCLK3 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + /// LSE selected + LSE = 0x3, + /// MSIK selected + MSIK = 0x4, + _, + }; + + pub const LSCOSEL = enum(u1) { + /// LSI clock selected + LSI = 0x0, + /// LSE clock selected + LSE = 0x1, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const LSIPREDIV = enum(u1) { + /// LSI not divided + Div1 = 0x0, + /// LSI divided by 128 + Div128 = 0x1, + }; + + pub const LTDCSEL = enum(u1) { + /// PLL3 “R” (pll3_r_ck) selected + PLL3_R = 0x0, + /// PLL2 “R” (pll2_r_ck) selected + PLL2_R = 0x1, + }; + + pub const MCOPRE = enum(u3) { + /// MCO divided by 1 + Div1 = 0x0, + /// MCO divided by 2 + Div2 = 0x1, + /// MCO divided by 4 + Div4 = 0x2, + /// MCO divided by 8 + Div8 = 0x3, + /// MCO divided by 16 + Div16 = 0x4, + _, + }; + + pub const MCOSEL = enum(u4) { + /// MCO output disabled, no clock on MCO + DISABLE = 0x0, + /// SYSCLK system clock selected + SYS = 0x1, + /// MSIS clock selected + MSIS = 0x2, + /// HSI clock selected + HSI = 0x3, + /// HSE clock selected + HSE = 0x4, + /// Main PLL clock pll1_r_ck selected + PLL1_R = 0x5, + /// LSI clock selected + LSI = 0x6, + /// LSE clock selected + LSE = 0x7, + /// Internal HSI48 clock selected + HSI48 = 0x8, + /// MSIK clock selected + MSIK = 0x9, + _, + }; + + pub const MDFSEL = enum(u3) { + /// HCLK selected + HCLK1 = 0x0, + /// PLL1 P (pll1_p_ck) selected + PLL1_P = 0x1, + /// PLL3 Q (pll3_q_ck) selected + PLL3_Q = 0x2, + /// input pin AUDIOCLK selected + AUDIOCLK = 0x3, + /// MSIK clock selected + MSIK = 0x4, + _, + }; + + pub const MSIBIAS = enum(u1) { + /// MSI bias continuous mode (clock accuracy fast settling time) + CONTINUOUS = 0x0, + /// MSI bias sampling mode (ultra-low-power mode) + SAMPLING = 0x1, + }; + + pub const MSIPLLFAST = enum(u1) { + /// MSI PLL normal start-up + NORMAL = 0x0, + /// MSI PLL fast start-up + FAST = 0x1, + }; + + pub const MSIPLLSEL = enum(u1) { + /// PLL mode applied to MSIK (MSI kernel) clock output + MSIK = 0x0, + /// PLL mode applied to MSIS (MSI system) clock output + MSIS = 0x1, + }; + + pub const MSIRANGE = enum(u4) { + /// range 0 around 48 MHz + RANGE_48MHZ = 0x0, + /// range 1 around 24 MHz + RANGE_24MHZ = 0x1, + /// range 2 around 16 MHz + RANGE_16MHZ = 0x2, + /// range 3 around 12 MHz + RANGE_12MHZ = 0x3, + /// range 4 around 4 MHz (reset value) + RANGE_4MHZ = 0x4, + /// range 5 around 2 MHz + RANGE_2MHZ = 0x5, + /// range 6 around 1.33 MHz + RANGE_1_33MHZ = 0x6, + /// range 7 around 1 MHz + RANGE_1MHZ = 0x7, + /// range 8 around 3.072 MHz + RANGE_3_072MHZ = 0x8, + /// range 9 around 1.536 MHz + RANGE_1_536MHZ = 0x9, + /// range 10 around 1.024 MHz + RANGE_1_024MHZ = 0xa, + /// range 11 around 768 kHz + RANGE_768KHZ = 0xb, + /// range 12 around 400 kHz + RANGE_400KHZ = 0xc, + /// range 13 around 200 kHz + RANGE_200KHZ = 0xd, + /// range 14 around 133 kHz + RANGE_133KHZ = 0xe, + /// range 15 around 100 kHz + RANGE_100KHZ = 0xf, + }; + + pub const MSIRGSEL = enum(u1) { + /// MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR + CSR = 0x0, + /// MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1 + ICSCR1 = 0x1, + }; + + pub const MSIXSRANGE = enum(u4) { + /// range 4 around 4M Hz (reset value) + RANGE_4MHZ = 0x4, + /// range 5 around 2 MHz + RANGE_2MHZ = 0x5, + /// range 6 around 1.5 MHz + RANGE_1_5MHZ = 0x6, + /// range 7 around 1 MHz + RANGE_1MHZ = 0x7, + /// range 8 around 3.072 MHz + RANGE_3_072MHZ = 0x8, + _, + }; + + pub const OCTOSPISEL = enum(u2) { + /// SYSCLK selected + SYS = 0x0, + /// MSIK selected + MSIK = 0x1, + /// PLL1 Q (pll1_q_ck) selected, can be up to 200 MHz + PLL1_Q = 0x2, + /// PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz + PLL2_Q = 0x3, + }; + + pub const OTGHSSEL = enum(u2) { + /// HSE selected + HSE = 0x0, + /// PLL1 “P” (pll1_q_ck) selected, + PLL1_P = 0x1, + /// HSE/2 selected + HSE_DIV_2 = 0x2, + /// PLL1 “P” divided by 2 (pll1_p_ck/2) selected + PLL1_P_DIV_2 = 0x3, + }; + + pub const PLLDIV = enum(u7) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + Div17 = 0x10, + Div18 = 0x11, + Div19 = 0x12, + Div20 = 0x13, + Div21 = 0x14, + Div22 = 0x15, + Div23 = 0x16, + Div24 = 0x17, + Div25 = 0x18, + Div26 = 0x19, + Div27 = 0x1a, + Div28 = 0x1b, + Div29 = 0x1c, + Div30 = 0x1d, + Div31 = 0x1e, + Div32 = 0x1f, + Div33 = 0x20, + Div34 = 0x21, + Div35 = 0x22, + Div36 = 0x23, + Div37 = 0x24, + Div38 = 0x25, + Div39 = 0x26, + Div40 = 0x27, + Div41 = 0x28, + Div42 = 0x29, + Div43 = 0x2a, + Div44 = 0x2b, + Div45 = 0x2c, + Div46 = 0x2d, + Div47 = 0x2e, + Div48 = 0x2f, + Div49 = 0x30, + Div50 = 0x31, + Div51 = 0x32, + Div52 = 0x33, + Div53 = 0x34, + Div54 = 0x35, + Div55 = 0x36, + Div56 = 0x37, + Div57 = 0x38, + Div58 = 0x39, + Div59 = 0x3a, + Div60 = 0x3b, + Div61 = 0x3c, + Div62 = 0x3d, + Div63 = 0x3e, + Div64 = 0x3f, + Div65 = 0x40, + Div66 = 0x41, + Div67 = 0x42, + Div68 = 0x43, + Div69 = 0x44, + Div70 = 0x45, + Div71 = 0x46, + Div72 = 0x47, + Div73 = 0x48, + Div74 = 0x49, + Div75 = 0x4a, + Div76 = 0x4b, + Div77 = 0x4c, + Div78 = 0x4d, + Div79 = 0x4e, + Div80 = 0x4f, + Div81 = 0x50, + Div82 = 0x51, + Div83 = 0x52, + Div84 = 0x53, + Div85 = 0x54, + Div86 = 0x55, + Div87 = 0x56, + Div88 = 0x57, + Div89 = 0x58, + Div90 = 0x59, + Div91 = 0x5a, + Div92 = 0x5b, + Div93 = 0x5c, + Div94 = 0x5d, + Div95 = 0x5e, + Div96 = 0x5f, + Div97 = 0x60, + Div98 = 0x61, + Div99 = 0x62, + Div100 = 0x63, + Div101 = 0x64, + Div102 = 0x65, + Div103 = 0x66, + Div104 = 0x67, + Div105 = 0x68, + Div106 = 0x69, + Div107 = 0x6a, + Div108 = 0x6b, + Div109 = 0x6c, + Div110 = 0x6d, + Div111 = 0x6e, + Div112 = 0x6f, + Div113 = 0x70, + Div114 = 0x71, + Div115 = 0x72, + Div116 = 0x73, + Div117 = 0x74, + Div118 = 0x75, + Div119 = 0x76, + Div120 = 0x77, + Div121 = 0x78, + Div122 = 0x79, + Div123 = 0x7a, + Div124 = 0x7b, + Div125 = 0x7c, + Div126 = 0x7d, + Div127 = 0x7e, + Div128 = 0x7f, + }; + + pub const PLLM = enum(u4) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + }; + + pub const PLLMBOOST = enum(u4) { + /// division by 1 (bypass) + Div1 = 0x0, + /// division by 2 + Div2 = 0x1, + /// division by 4 + Div4 = 0x2, + /// division by 6 + Div6 = 0x3, + /// division by 8 + Div8 = 0x4, + /// division by 10 + Div10 = 0x5, + /// division by 12 + Div12 = 0x6, + /// division by 14 + Div14 = 0x7, + /// division by 16 + Div16 = 0x8, + _, + }; + + pub const PLLN = enum(u9) { + Mul4 = 0x3, + Mul5 = 0x4, + Mul6 = 0x5, + Mul7 = 0x6, + Mul8 = 0x7, + Mul9 = 0x8, + Mul10 = 0x9, + Mul11 = 0xa, + Mul12 = 0xb, + Mul13 = 0xc, + Mul14 = 0xd, + Mul15 = 0xe, + Mul16 = 0xf, + Mul17 = 0x10, + Mul18 = 0x11, + Mul19 = 0x12, + Mul20 = 0x13, + Mul21 = 0x14, + Mul22 = 0x15, + Mul23 = 0x16, + Mul24 = 0x17, + Mul25 = 0x18, + Mul26 = 0x19, + Mul27 = 0x1a, + Mul28 = 0x1b, + Mul29 = 0x1c, + Mul30 = 0x1d, + Mul31 = 0x1e, + Mul32 = 0x1f, + Mul33 = 0x20, + Mul34 = 0x21, + Mul35 = 0x22, + Mul36 = 0x23, + Mul37 = 0x24, + Mul38 = 0x25, + Mul39 = 0x26, + Mul40 = 0x27, + Mul41 = 0x28, + Mul42 = 0x29, + Mul43 = 0x2a, + Mul44 = 0x2b, + Mul45 = 0x2c, + Mul46 = 0x2d, + Mul47 = 0x2e, + Mul48 = 0x2f, + Mul49 = 0x30, + Mul50 = 0x31, + Mul51 = 0x32, + Mul52 = 0x33, + Mul53 = 0x34, + Mul54 = 0x35, + Mul55 = 0x36, + Mul56 = 0x37, + Mul57 = 0x38, + Mul58 = 0x39, + Mul59 = 0x3a, + Mul60 = 0x3b, + Mul61 = 0x3c, + Mul62 = 0x3d, + Mul63 = 0x3e, + Mul64 = 0x3f, + Mul65 = 0x40, + Mul66 = 0x41, + Mul67 = 0x42, + Mul68 = 0x43, + Mul69 = 0x44, + Mul70 = 0x45, + Mul71 = 0x46, + Mul72 = 0x47, + Mul73 = 0x48, + Mul74 = 0x49, + Mul75 = 0x4a, + Mul76 = 0x4b, + Mul77 = 0x4c, + Mul78 = 0x4d, + Mul79 = 0x4e, + Mul80 = 0x4f, + Mul81 = 0x50, + Mul82 = 0x51, + Mul83 = 0x52, + Mul84 = 0x53, + Mul85 = 0x54, + Mul86 = 0x55, + Mul87 = 0x56, + Mul88 = 0x57, + Mul89 = 0x58, + Mul90 = 0x59, + Mul91 = 0x5a, + Mul92 = 0x5b, + Mul93 = 0x5c, + Mul94 = 0x5d, + Mul95 = 0x5e, + Mul96 = 0x5f, + Mul97 = 0x60, + Mul98 = 0x61, + Mul99 = 0x62, + Mul100 = 0x63, + Mul101 = 0x64, + Mul102 = 0x65, + Mul103 = 0x66, + Mul104 = 0x67, + Mul105 = 0x68, + Mul106 = 0x69, + Mul107 = 0x6a, + Mul108 = 0x6b, + Mul109 = 0x6c, + Mul110 = 0x6d, + Mul111 = 0x6e, + Mul112 = 0x6f, + Mul113 = 0x70, + Mul114 = 0x71, + Mul115 = 0x72, + Mul116 = 0x73, + Mul117 = 0x74, + Mul118 = 0x75, + Mul119 = 0x76, + Mul120 = 0x77, + Mul121 = 0x78, + Mul122 = 0x79, + Mul123 = 0x7a, + Mul124 = 0x7b, + Mul125 = 0x7c, + Mul126 = 0x7d, + Mul127 = 0x7e, + Mul128 = 0x7f, + Mul129 = 0x80, + Mul130 = 0x81, + Mul131 = 0x82, + Mul132 = 0x83, + Mul133 = 0x84, + Mul134 = 0x85, + Mul135 = 0x86, + Mul136 = 0x87, + Mul137 = 0x88, + Mul138 = 0x89, + Mul139 = 0x8a, + Mul140 = 0x8b, + Mul141 = 0x8c, + Mul142 = 0x8d, + Mul143 = 0x8e, + Mul144 = 0x8f, + Mul145 = 0x90, + Mul146 = 0x91, + Mul147 = 0x92, + Mul148 = 0x93, + Mul149 = 0x94, + Mul150 = 0x95, + Mul151 = 0x96, + Mul152 = 0x97, + Mul153 = 0x98, + Mul154 = 0x99, + Mul155 = 0x9a, + Mul156 = 0x9b, + Mul157 = 0x9c, + Mul158 = 0x9d, + Mul159 = 0x9e, + Mul160 = 0x9f, + Mul161 = 0xa0, + Mul162 = 0xa1, + Mul163 = 0xa2, + Mul164 = 0xa3, + Mul165 = 0xa4, + Mul166 = 0xa5, + Mul167 = 0xa6, + Mul168 = 0xa7, + Mul169 = 0xa8, + Mul170 = 0xa9, + Mul171 = 0xaa, + Mul172 = 0xab, + Mul173 = 0xac, + Mul174 = 0xad, + Mul175 = 0xae, + Mul176 = 0xaf, + Mul177 = 0xb0, + Mul178 = 0xb1, + Mul179 = 0xb2, + Mul180 = 0xb3, + Mul181 = 0xb4, + Mul182 = 0xb5, + Mul183 = 0xb6, + Mul184 = 0xb7, + Mul185 = 0xb8, + Mul186 = 0xb9, + Mul187 = 0xba, + Mul188 = 0xbb, + Mul189 = 0xbc, + Mul190 = 0xbd, + Mul191 = 0xbe, + Mul192 = 0xbf, + Mul193 = 0xc0, + Mul194 = 0xc1, + Mul195 = 0xc2, + Mul196 = 0xc3, + Mul197 = 0xc4, + Mul198 = 0xc5, + Mul199 = 0xc6, + Mul200 = 0xc7, + Mul201 = 0xc8, + Mul202 = 0xc9, + Mul203 = 0xca, + Mul204 = 0xcb, + Mul205 = 0xcc, + Mul206 = 0xcd, + Mul207 = 0xce, + Mul208 = 0xcf, + Mul209 = 0xd0, + Mul210 = 0xd1, + Mul211 = 0xd2, + Mul212 = 0xd3, + Mul213 = 0xd4, + Mul214 = 0xd5, + Mul215 = 0xd6, + Mul216 = 0xd7, + Mul217 = 0xd8, + Mul218 = 0xd9, + Mul219 = 0xda, + Mul220 = 0xdb, + Mul221 = 0xdc, + Mul222 = 0xdd, + Mul223 = 0xde, + Mul224 = 0xdf, + Mul225 = 0xe0, + Mul226 = 0xe1, + Mul227 = 0xe2, + Mul228 = 0xe3, + Mul229 = 0xe4, + Mul230 = 0xe5, + Mul231 = 0xe6, + Mul232 = 0xe7, + Mul233 = 0xe8, + Mul234 = 0xe9, + Mul235 = 0xea, + Mul236 = 0xeb, + Mul237 = 0xec, + Mul238 = 0xed, + Mul239 = 0xee, + Mul240 = 0xef, + Mul241 = 0xf0, + Mul242 = 0xf1, + Mul243 = 0xf2, + Mul244 = 0xf3, + Mul245 = 0xf4, + Mul246 = 0xf5, + Mul247 = 0xf6, + Mul248 = 0xf7, + Mul249 = 0xf8, + Mul250 = 0xf9, + Mul251 = 0xfa, + Mul252 = 0xfb, + Mul253 = 0xfc, + Mul254 = 0xfd, + Mul255 = 0xfe, + Mul256 = 0xff, + Mul257 = 0x100, + Mul258 = 0x101, + Mul259 = 0x102, + Mul260 = 0x103, + Mul261 = 0x104, + Mul262 = 0x105, + Mul263 = 0x106, + Mul264 = 0x107, + Mul265 = 0x108, + Mul266 = 0x109, + Mul267 = 0x10a, + Mul268 = 0x10b, + Mul269 = 0x10c, + Mul270 = 0x10d, + Mul271 = 0x10e, + Mul272 = 0x10f, + Mul273 = 0x110, + Mul274 = 0x111, + Mul275 = 0x112, + Mul276 = 0x113, + Mul277 = 0x114, + Mul278 = 0x115, + Mul279 = 0x116, + Mul280 = 0x117, + Mul281 = 0x118, + Mul282 = 0x119, + Mul283 = 0x11a, + Mul284 = 0x11b, + Mul285 = 0x11c, + Mul286 = 0x11d, + Mul287 = 0x11e, + Mul288 = 0x11f, + Mul289 = 0x120, + Mul290 = 0x121, + Mul291 = 0x122, + Mul292 = 0x123, + Mul293 = 0x124, + Mul294 = 0x125, + Mul295 = 0x126, + Mul296 = 0x127, + Mul297 = 0x128, + Mul298 = 0x129, + Mul299 = 0x12a, + Mul300 = 0x12b, + Mul301 = 0x12c, + Mul302 = 0x12d, + Mul303 = 0x12e, + Mul304 = 0x12f, + Mul305 = 0x130, + Mul306 = 0x131, + Mul307 = 0x132, + Mul308 = 0x133, + Mul309 = 0x134, + Mul310 = 0x135, + Mul311 = 0x136, + Mul312 = 0x137, + Mul313 = 0x138, + Mul314 = 0x139, + Mul315 = 0x13a, + Mul316 = 0x13b, + Mul317 = 0x13c, + Mul318 = 0x13d, + Mul319 = 0x13e, + Mul320 = 0x13f, + Mul321 = 0x140, + Mul322 = 0x141, + Mul323 = 0x142, + Mul324 = 0x143, + Mul325 = 0x144, + Mul326 = 0x145, + Mul327 = 0x146, + Mul328 = 0x147, + Mul329 = 0x148, + Mul330 = 0x149, + Mul331 = 0x14a, + Mul332 = 0x14b, + Mul333 = 0x14c, + Mul334 = 0x14d, + Mul335 = 0x14e, + Mul336 = 0x14f, + Mul337 = 0x150, + Mul338 = 0x151, + Mul339 = 0x152, + Mul340 = 0x153, + Mul341 = 0x154, + Mul342 = 0x155, + Mul343 = 0x156, + Mul344 = 0x157, + Mul345 = 0x158, + Mul346 = 0x159, + Mul347 = 0x15a, + Mul348 = 0x15b, + Mul349 = 0x15c, + Mul350 = 0x15d, + Mul351 = 0x15e, + Mul352 = 0x15f, + Mul353 = 0x160, + Mul354 = 0x161, + Mul355 = 0x162, + Mul356 = 0x163, + Mul357 = 0x164, + Mul358 = 0x165, + Mul359 = 0x166, + Mul360 = 0x167, + Mul361 = 0x168, + Mul362 = 0x169, + Mul363 = 0x16a, + Mul364 = 0x16b, + Mul365 = 0x16c, + Mul366 = 0x16d, + Mul367 = 0x16e, + Mul368 = 0x16f, + Mul369 = 0x170, + Mul370 = 0x171, + Mul371 = 0x172, + Mul372 = 0x173, + Mul373 = 0x174, + Mul374 = 0x175, + Mul375 = 0x176, + Mul376 = 0x177, + Mul377 = 0x178, + Mul378 = 0x179, + Mul379 = 0x17a, + Mul380 = 0x17b, + Mul381 = 0x17c, + Mul382 = 0x17d, + Mul383 = 0x17e, + Mul384 = 0x17f, + Mul385 = 0x180, + Mul386 = 0x181, + Mul387 = 0x182, + Mul388 = 0x183, + Mul389 = 0x184, + Mul390 = 0x185, + Mul391 = 0x186, + Mul392 = 0x187, + Mul393 = 0x188, + Mul394 = 0x189, + Mul395 = 0x18a, + Mul396 = 0x18b, + Mul397 = 0x18c, + Mul398 = 0x18d, + Mul399 = 0x18e, + Mul400 = 0x18f, + Mul401 = 0x190, + Mul402 = 0x191, + Mul403 = 0x192, + Mul404 = 0x193, + Mul405 = 0x194, + Mul406 = 0x195, + Mul407 = 0x196, + Mul408 = 0x197, + Mul409 = 0x198, + Mul410 = 0x199, + Mul411 = 0x19a, + Mul412 = 0x19b, + Mul413 = 0x19c, + Mul414 = 0x19d, + Mul415 = 0x19e, + Mul416 = 0x19f, + Mul417 = 0x1a0, + Mul418 = 0x1a1, + Mul419 = 0x1a2, + Mul420 = 0x1a3, + Mul421 = 0x1a4, + Mul422 = 0x1a5, + Mul423 = 0x1a6, + Mul424 = 0x1a7, + Mul425 = 0x1a8, + Mul426 = 0x1a9, + Mul427 = 0x1aa, + Mul428 = 0x1ab, + Mul429 = 0x1ac, + Mul430 = 0x1ad, + Mul431 = 0x1ae, + Mul432 = 0x1af, + Mul433 = 0x1b0, + Mul434 = 0x1b1, + Mul435 = 0x1b2, + Mul436 = 0x1b3, + Mul437 = 0x1b4, + Mul438 = 0x1b5, + Mul439 = 0x1b6, + Mul440 = 0x1b7, + Mul441 = 0x1b8, + Mul442 = 0x1b9, + Mul443 = 0x1ba, + Mul444 = 0x1bb, + Mul445 = 0x1bc, + Mul446 = 0x1bd, + Mul447 = 0x1be, + Mul448 = 0x1bf, + Mul449 = 0x1c0, + Mul450 = 0x1c1, + Mul451 = 0x1c2, + Mul452 = 0x1c3, + Mul453 = 0x1c4, + Mul454 = 0x1c5, + Mul455 = 0x1c6, + Mul456 = 0x1c7, + Mul457 = 0x1c8, + Mul458 = 0x1c9, + Mul459 = 0x1ca, + Mul460 = 0x1cb, + Mul461 = 0x1cc, + Mul462 = 0x1cd, + Mul463 = 0x1ce, + Mul464 = 0x1cf, + Mul465 = 0x1d0, + Mul466 = 0x1d1, + Mul467 = 0x1d2, + Mul468 = 0x1d3, + Mul469 = 0x1d4, + Mul470 = 0x1d5, + Mul471 = 0x1d6, + Mul472 = 0x1d7, + Mul473 = 0x1d8, + Mul474 = 0x1d9, + Mul475 = 0x1da, + Mul476 = 0x1db, + Mul477 = 0x1dc, + Mul478 = 0x1dd, + Mul479 = 0x1de, + Mul480 = 0x1df, + Mul481 = 0x1e0, + Mul482 = 0x1e1, + Mul483 = 0x1e2, + Mul484 = 0x1e3, + Mul485 = 0x1e4, + Mul486 = 0x1e5, + Mul487 = 0x1e6, + Mul488 = 0x1e7, + Mul489 = 0x1e8, + Mul490 = 0x1e9, + Mul491 = 0x1ea, + Mul492 = 0x1eb, + Mul493 = 0x1ec, + Mul494 = 0x1ed, + Mul495 = 0x1ee, + Mul496 = 0x1ef, + Mul497 = 0x1f0, + Mul498 = 0x1f1, + Mul499 = 0x1f2, + Mul500 = 0x1f3, + Mul501 = 0x1f4, + Mul502 = 0x1f5, + Mul503 = 0x1f6, + Mul504 = 0x1f7, + Mul505 = 0x1f8, + Mul506 = 0x1f9, + Mul507 = 0x1fa, + Mul508 = 0x1fb, + Mul509 = 0x1fc, + Mul510 = 0x1fd, + Mul511 = 0x1fe, + Mul512 = 0x1ff, + _, + }; + + pub const PLLRGE = enum(u2) { + /// PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz + FREQ_4TO8MHZ = 0x0, + /// PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz + FREQ_8TO16MHZ = 0x3, + _, + }; + + pub const PLLSRC = enum(u2) { + /// No clock sent to PLL3 + DISABLE = 0x0, + /// MSIS clock selected as PLL3 clock entry + MSIS = 0x1, + /// HSI clock selected as PLL3 clock entry + HSI = 0x2, + /// HSE clock selected as PLL3 clock entry + HSE = 0x3, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const RNGSEL = enum(u2) { + /// HSI48 selected + HSI48 = 0x0, + /// HSI48 / 2 selected, can be used in Range 4 + HSI48_DIV_2 = 0x1, + /// HSI selected + HSI = 0x2, + _, + }; + + pub const RTCSEL = enum(u2) { + /// No clock selected + DISABLE = 0x0, + /// LSE oscillator clock selected + LSE = 0x1, + /// LSI oscillator clock selected + LSI = 0x2, + /// HSE oscillator clock divided by 32 selected + HSE = 0x3, + }; + + pub const SAESSEL = enum(u1) { + /// SHSI selected + SHSI = 0x0, + /// SHSI / 2 selected, can be used in Range 4 + SHSI_DIV_2 = 0x1, + }; + + pub const SAISEL = enum(u3) { + /// PLL2 P (pll2_p_ck) selected + PLL2_P = 0x0, + /// PLL3 P (pll3_p_ck) selected + PLL3_P = 0x1, + /// PLL1 P (pll1_p_ck) selected + PLL1_P = 0x2, + /// input pin AUDIOCLK selected + AUDIOCLK = 0x3, + /// HSI clock selected + HSI = 0x4, + _, + }; + + pub const SDMMCSEL = enum(u1) { + /// ICLK clock selected + ICLK = 0x0, + /// PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) + PLL1_P = 0x1, + }; + + pub const SECURITY = enum(u1) { + /// non secure + NON_SECURE = 0x0, + /// secure + SECURE = 0x1, + }; + + pub const SPI1SEL = enum(u2) { + /// PCLK2 selected + PCLK2 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + /// MSIK selected + MSIK = 0x3, + }; + + pub const SPI2SEL = enum(u2) { + /// PCLK2 selected + PCLK1 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + /// MSIK selected + MSIK = 0x3, + }; + + pub const SPI3SEL = enum(u2) { + /// PCLK2 selected + PCLK3 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + /// MSIK selected + MSIK = 0x3, + }; + + pub const STOPKERWUCK = enum(u1) { + /// MSIK oscillator automatically enabled when exiting Stop mode + MSIK = 0x0, + /// HSI oscillator automatically enabled when exiting Stop mode + HSI = 0x1, + }; + + pub const STOPWUCK = enum(u1) { + /// MSIS oscillator selected as wakeup from stop clock and CSS backup clock + MSIS = 0x0, + /// HSI oscillator selected as wakeup from stop clock and CSS backup clock + HSI = 0x1, + }; + + pub const SW = enum(u2) { + /// MSIS selected as system clock + MSIS = 0x0, + /// HSI selected as system clock + HSI = 0x1, + /// HSE selected as system clock + HSE = 0x2, + /// PLL pll1_r_ck selected as system clock + PLL1_R = 0x3, + }; + + pub const SYSTICKSEL = enum(u2) { + /// HCLK/8 selected + HCLK1_DIV_8 = 0x0, + /// LSI selected + LSI = 0x1, + /// LSE selected + LSE = 0x2, + _, + }; + + pub const TIMICSEL = enum(u3) { + /// No sources can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + DISABLE = 0x0, + /// HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + HSI256_MSIS1024_MSIS4 = 0x4, + /// HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + HSI256_MSIS1024_MSIK4 = 0x5, + /// HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + HSI256_MSIK1024_MSIS4 = 0x6, + /// HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + HSI256_MSIK1024_MSIK4 = 0x7, + _, + }; + + pub const USART1SEL = enum(u2) { + /// PCLK2 selected + PCLK2 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + /// LSE selected + LSE = 0x3, + }; + + pub const USARTSEL = enum(u2) { + /// PCLK1 selected + PCLK1 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + /// LSE selected + LSE = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// RCC clock control register + CR: mmio.Mmio(packed struct(u32) { + /// MSIS clock enable Set and cleared by software. Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator. Set by hardware when used directly or indirectly as system clock. + MSISON: u1, + /// MSI enable for some peripheral kernels Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details). The MSIKERON must be configured at 0 before entering Stop 3 mode. + MSIKERON: u1, + /// MSIS clock ready flag Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON. Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles. + MSISRDY: u1, + /// MSI clock PLL-mode enable Set and cleared by software to enable/disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR). + MSIPLLEN: u1, + /// MSIK clock enable Set and cleared by software. Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator. + MSIKON: u1, + /// MSIK clock ready flag Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON. Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles. + MSIKRDY: u1, + /// MSI clock with PLL mode selection Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0). Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs. + MSIPLLSEL: packed union { + raw: u1, + value: MSIPLLSEL, + }, + /// MSI PLL mode fast startup Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock source. This bit is used only if PLL mode is selected (MSIPLLEN = 1). The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off. + MSIPLLFAST: packed union { + raw: u1, + value: MSIPLLFAST, + }, + /// HSI clock enable Set and cleared by software. Cleared by hardware to stop the HSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI is used directly or indirectly as system clock. + HSION: u1, + /// HSI enable for some peripheral kernels Set and cleared by software to force HSI ON even in Stop modes. Keeping the HSI ON in Stop mode allows the communication speed not to be reduced by the HSI startup time. This bit has no effect on HSION value. Refer to for more details. The HSIKERON must be configured at 0 before entering Stop 3 mode. + HSIKERON: u1, + /// HSI clock ready flag Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI clock cycles. + HSIRDY: u1, + reserved12: u1, + /// HSI48 clock enable Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes. + HSI48ON: u1, + /// HSI48 clock ready flag Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON. + HSI48RDY: u1, + /// SHSI clock enable Set and cleared by software. Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes. + SHSION: u1, + /// SHSI clock ready flag Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION. Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles. + SHSIRDY: u1, + /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. + HSEON: u1, + /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles. + HSERDY: u1, + /// HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + HSEBYP: u1, + /// Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. + CSSON: u1, + /// HSE external clock bypass mode Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled. + HSEEXT: packed union { + raw: u1, + value: HSEEXT, + }, + reserved24: u3, + /// PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock. + PLLON: u1, + /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + PLLRDY: u1, + padding: u6, + }), + reserved8: [4]u8, + /// RCC internal clock sources calibration register 1 + ICSCR1: mmio.Mmio(packed struct(u32) { + /// MSIRC3 clock calibration for MSI ranges 12 to 15 These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. + MSICAL3: u5, + /// MSIRC2 clock calibration for MSI ranges 8 to 11 These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. + MSICAL2: u5, + /// MSIRC1 clock calibration for MSI ranges 4 to 7 These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. + MSICAL1: u5, + /// MSIRC0 clock calibration for MSI ranges 0 to 3 These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]. + MSICAL0: u5, + reserved22: u2, + /// MSI bias mode selection Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy. + MSIBIAS: packed union { + raw: u1, + value: MSIBIAS, + }, + /// MSI clock range selection Set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect. After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR. + MSIRGSEL: packed union { + raw: u1, + value: MSIRGSEL, + }, + /// MSIK clock ranges These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0) MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz). + MSIKRANGE: packed union { + raw: u4, + value: MSIRANGE, + }, + /// MSIS clock ranges These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0) MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz). + MSISRANGE: packed union { + raw: u4, + value: MSIRANGE, + }, + }), + /// RCC internal clock sources calibration register 2 + ICSCR2: mmio.Mmio(packed struct(u32) { + /// MSI clock trimming for ranges 12 to 15 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. + MSITRIM3: u5, + /// MSI clock trimming for ranges 8 to 11 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. + MSITRIM2: u5, + /// MSI clock trimming for ranges 4 to 7 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. + MSITRIM1: u5, + /// MSI clock trimming for ranges 0 to 3 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. + MSITRIM0: u5, + padding: u12, + }), + /// RCC internal clock sources calibration register 3 + ICSCR3: mmio.Mmio(packed struct(u32) { + /// HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. + HSICAL: u12, + reserved16: u4, + /// HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI. + HSITRIM: u5, + padding: u11, + }), + /// RCC clock recovery RC register + CRRCR: mmio.Mmio(packed struct(u32) { + /// HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. + HSI48CAL: u9, + padding: u23, + }), + reserved28: [4]u8, + /// RCC clock configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// system clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value. + SW: packed union { + raw: u2, + value: SW, + }, + /// system clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. + SWS: packed union { + raw: u2, + value: SW, + }, + /// wakeup from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW = 10). + STOPWUCK: packed union { + raw: u1, + value: STOPWUCK, + }, + /// wakeup from Stop kernel clock automatic enable selection Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals. + STOPKERWUCK: packed union { + raw: u1, + value: STOPKERWUCK, + }, + reserved24: u18, + /// microcontroller clock output Set and cleared by software. Others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. + MCOSEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// microcontroller clock output prescaler Set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed + MCOPRE: packed union { + raw: u3, + value: MCOPRE, + }, + padding: u1, + }), + /// RCC clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// AHB prescaler Set and cleared by software to control the division factor of the AHB clock (HCLK). Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xxx: SYSCLK not divided + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (PCLK1). 0xx: HCLK not divided + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + reserved8: u1, + /// APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (PCLK2). 0xx: HCLK not divided + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + reserved12: u1, + /// DSI PHY prescaler This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK). 0xx: DCLK not divided Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + DPRE: packed union { + raw: u3, + value: DPRE, + }, + reserved16: u1, + /// AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1. + AHB1DIS: u1, + /// AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3. + AHB2DIS1: u1, + /// AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off. + AHB2DIS2: u1, + /// APB1 clock disable This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. + APB1DIS: u1, + /// APB2 clock disable This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off. + APB2DIS: u1, + padding: u11, + }), + /// RCC clock configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// APB3 prescaler Set and cleared by software to control the division factor of the APB3 clock (PCLK3). 0xx: HCLK not divided + PPRE3: packed union { + raw: u3, + value: PPRE, + }, + reserved16: u9, + /// AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4. + AHB3DIS: u1, + /// APB3 clock disable This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. + APB3DIS: u1, + padding: u14, + }), + /// RCC PLL1 configuration register + PLL1CFGR: mmio.Mmio(packed struct(u32) { + /// PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC must be 0. + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + /// PLL input frequency range Set and reset by software to select the proper reference frequency range used for PLL. This bit must be written before enabling the PLL. 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz + PLLRGE: packed union { + raw: u2, + value: PLLRGE, + }, + /// PLL fractional latch enable Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator. In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details). + PLLFRACEN: u1, + reserved8: u3, + /// Prescaler for PLL Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). ... + PLLM: packed union { + raw: u4, + value: PLLM, + }, + /// Prescaler for EPOD booster input clock Set and cleared by software to configure the prescaler of the PLL, used for the EPOD booster. The EPOD booster input frequency is PLL input clock frequency/PLLMBOOST. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0) and EPOD Boost mode is disabled (see ). others: reserved + PLLMBOOST: packed union { + raw: u4, + value: PLLMBOOST, + }, + /// PLL DIVP divider output enable Set and reset by software to enable the PLL_p_ck output of the PLL. To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). + PLLPEN: u1, + /// PLL DIVQ divider output enable Set and reset by software to enable the PLL_q_ck output of the PLL. To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). + PLLQEN: u1, + /// PLL DIVR divider output enable Set and reset by software to enable the PLL_r_ck output of the PLL. To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). + PLLREN: u1, + padding: u13, + }), + /// RCC PLL2 configuration register + PLL2CFGR: mmio.Mmio(packed struct(u32) { + /// PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC must be 0. + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + /// PLL input frequency range Set and reset by software to select the proper reference frequency range used for PLL. This bit must be written before enabling the PLL. 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz + PLLRGE: packed union { + raw: u2, + value: PLLRGE, + }, + /// PLL fractional latch enable Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator. In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details). + PLLFRACEN: u1, + reserved8: u3, + /// Prescaler for PLL Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). ... + PLLM: packed union { + raw: u4, + value: PLLM, + }, + reserved16: u4, + /// PLL DIVP divider output enable Set and reset by software to enable the PLL_p_ck output of the PLL. To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). + PLLPEN: u1, + /// PLL DIVQ divider output enable Set and reset by software to enable the PLL_q_ck output of the PLL. To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). + PLLQEN: u1, + /// PLL DIVR divider output enable Set and reset by software to enable the PLL_r_ck output of the PLL. To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). + PLLREN: u1, + padding: u13, + }), + /// RCC PLL3 configuration register + PLL3CFGR: mmio.Mmio(packed struct(u32) { + /// PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC must be 0. + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + /// PLL input frequency range Set and reset by software to select the proper reference frequency range used for PLL. This bit must be written before enabling the PLL. 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz + PLLRGE: packed union { + raw: u2, + value: PLLRGE, + }, + /// PLL fractional latch enable Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator. In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details). + PLLFRACEN: u1, + reserved8: u3, + /// Prescaler for PLL Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). ... + PLLM: packed union { + raw: u4, + value: PLLM, + }, + reserved16: u4, + /// PLL DIVP divider output enable Set and reset by software to enable the PLL_p_ck output of the PLL. To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). + PLLPEN: u1, + /// PLL DIVQ divider output enable Set and reset by software to enable the PLL_q_ck output of the PLL. To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). + PLLQEN: u1, + /// PLL DIVR divider output enable Set and reset by software to enable the PLL_r_ck output of the PLL. To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). + PLLREN: u1, + padding: u13, + }), + /// RCC PLL1 dividers register + PLL1DIVR: mmio.Mmio(packed struct(u32) { + /// Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16 MHz + PLLN: packed union { + raw: u9, + value: PLLN, + }, + /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... + PLLP: packed union { + raw: u7, + value: PLLDIV, + }, + /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLQ: packed union { + raw: u7, + value: PLLDIV, + }, + reserved24: u1, + /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLR: packed union { + raw: u7, + value: PLLDIV, + }, + padding: u1, + }), + /// RCC PLL1 fractional divider register + PLL1FRACR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1. + PLLFRACN: u13, + padding: u16, + }), + /// RCC PLL2 dividers configuration register + PLL2DIVR: mmio.Mmio(packed struct(u32) { + /// Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16 MHz + PLLN: packed union { + raw: u9, + value: PLLN, + }, + /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... + PLLP: packed union { + raw: u7, + value: PLLDIV, + }, + /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLQ: packed union { + raw: u7, + value: PLLDIV, + }, + reserved24: u1, + /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLR: packed union { + raw: u7, + value: PLLDIV, + }, + padding: u1, + }), + /// RCC PLL2 fractional divider register + PLL2FRACR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1. + PLLFRACN: u13, + padding: u16, + }), + /// RCC PLL3 dividers configuration register + PLL3DIVR: mmio.Mmio(packed struct(u32) { + /// Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16 MHz + PLLN: packed union { + raw: u9, + value: PLLN, + }, + /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... + PLLP: packed union { + raw: u7, + value: PLLDIV, + }, + /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLQ: packed union { + raw: u7, + value: PLLDIV, + }, + reserved24: u1, + /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLR: packed union { + raw: u7, + value: PLLDIV, + }, + padding: u1, + }), + /// RCC PLL3 fractional divider register + PLL3FRACR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1. + PLLFRACN: u13, + padding: u16, + }), + reserved80: [4]u8, + /// RCC clock interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. + LSIRDYIE: u1, + /// LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. + LSERDYIE: u1, + /// MSIS ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization. + MSISRDYIE: u1, + /// HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization. + HSIRDYIE: u1, + /// HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. + HSERDYIE: u1, + /// HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. + HSI48RDYIE: u1, + /// PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock. + PLLRDYIE: u1, + reserved11: u4, + /// MSIK ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization. + MSIKRDYIE: u1, + /// SHSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization. + SHSIRDYIE: u1, + padding: u19, + }), + /// RCC clock interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. Cleared by software setting the LSIRDYC bit. + LSIRDYF: u1, + /// LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYIE is set. Cleared by software setting the LSERDYC bit. + LSERDYF: u1, + /// MSIS ready interrupt flag Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set. Cleared by software setting the MSISRDYC bit. + MSISRDYF: u1, + /// HSI ready interrupt flag Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. + HSIRDYF: u1, + /// HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit. + HSERDYF: u1, + /// HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. Cleared by software setting the HSI48RDYC bit. + HSI48RDYF: u1, + /// PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit. + PLLRDYF: u1, + reserved10: u3, + /// Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. + CSSF: u1, + /// MSIK ready interrupt flag Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. Cleared by software setting the MSIKRDYC bit. + MSIKRDYF: u1, + /// SHSI ready interrupt flag Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set. Cleared by software setting the SHSIRDYC bit. + SHSIRDYF: u1, + padding: u19, + }), + /// RCC clock interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt clear Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect. + LSIRDYC: u1, + /// LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect. + LSERDYC: u1, + /// MSIS ready interrupt clear Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect. + MSISRDYC: u1, + /// HSI ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect. + HSIRDYC: u1, + /// HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect. + HSERDYC: u1, + /// HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect. + HSI48RDYC: u1, + /// PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect. + PLLRDYC: u1, + reserved10: u3, + /// Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect. + CSSC: u1, + /// MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect. + MSIKRDYC: u1, + /// SHSI oscillator ready interrupt clear Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect. + SHSIRDYC: u1, + padding: u19, + }), + reserved96: [4]u8, + /// RCC AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 reset Set and cleared by software. + GPDMA1RST: u1, + /// CORDIC reset Set and cleared by software. + CORDICRST: u1, + /// FMAC reset Set and cleared by software. + FMACRST: u1, + /// MDF1 reset Set and cleared by software. + MDF1RST: u1, + reserved12: u8, + /// CRC reset Set and cleared by software. + CRCRST: u1, + reserved15: u2, + /// JPEG reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + JPEGRST: u1, + /// TSC reset Set and cleared by software. + TSCRST: u1, + /// RAMCFG reset Set and cleared by software. + RAMCFGRST: u1, + /// DMA2D reset Set and cleared by software. + DMA2DRST: u1, + /// GFXMMU reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + GFXMMURST: u1, + /// GPU2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + GPU2DRST: u1, + padding: u11, + }), + /// RCC AHB2 peripheral reset register 1 + AHB2RSTR1: mmio.Mmio(packed struct(u32) { + /// IO port A reset Set and cleared by software. + GPIOARST: u1, + /// IO port B reset Set and cleared by software. + GPIOBRST: u1, + /// IO port C reset Set and cleared by software. + GPIOCRST: u1, + /// IO port D reset Set and cleared by software. + GPIODRST: u1, + /// IO port E reset Set and cleared by software. + GPIOERST: u1, + /// IO port F reset Set and cleared by software. + GPIOFRST: u1, + /// IO port G reset Set and cleared by software. + GPIOGRST: u1, + /// IO port H reset Set and cleared by software. + GPIOHRST: u1, + /// IO port I reset Set and cleared by software. + GPIOIRST: u1, + /// I/O port J reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + GPIOJRST: u1, + /// ADC1 and ADC2 reset This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. + ADC12RST: u1, + reserved12: u1, + /// DCMI and PSSI reset Set and cleared by software. + DCMIRST: u1, + reserved14: u1, + /// OTG_FS reset Set and cleared by software. + USB_OTG_FSRST: u1, + reserved16: u1, + /// AES hardware accelerator reset Set and cleared by software. + AESRST: u1, + /// Hash reset Set and cleared by software. + HASHRST: u1, + /// Random number generator reset Set and cleared by software. + RNGRST: u1, + /// PKA reset Set and cleared by software. + PKARST: u1, + /// SAES hardware accelerator reset Set and cleared by software. + SAESRST: u1, + /// OCTOSPIM reset Set and cleared by software. + OCTOSPIMRST: u1, + reserved23: u1, + /// OTFDEC1 reset Set and cleared by software. + OTFDEC1RST: u1, + /// OTFDEC2 reset Set and cleared by software. + OTFDEC2RST: u1, + reserved27: u2, + /// SDMMC1 reset Set and cleared by software. + SDMMC1RST: u1, + /// SDMMC2 reset Set and cleared by software. + SDMMC2RST: u1, + padding: u3, + }), + /// RCC AHB2 peripheral reset register 2 + AHB2RSTR2: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller reset Set and cleared by software. + FSMCRST: u1, + reserved4: u3, + /// OCTOSPI1 reset Set and cleared by software. + OCTOSPI1RST: u1, + reserved8: u3, + /// OCTOSPI2 reset Set and cleared by software. + OCTOSPI2RST: u1, + reserved12: u3, + /// HSPI1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + HSPI1RST: u1, + padding: u19, + }), + /// RCC AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// LPGPIO1 reset Set and cleared by software. + LPGPIO1RST: u1, + reserved5: u4, + /// ADC4 reset Set and cleared by software. + ADC4RST: u1, + /// DAC1 reset Set and cleared by software. + DAC1RST: u1, + reserved9: u2, + /// LPDMA1 reset Set and cleared by software. + LPDMA1RST: u1, + /// ADF1 reset Set and cleared by software. + ADF1RST: u1, + padding: u21, + }), + reserved116: [4]u8, + /// RCC APB1 peripheral reset register 1 + APB1RSTR1: mmio.Mmio(packed struct(u32) { + /// TIM2 reset Set and cleared by software. + TIM2RST: u1, + /// TIM3 reset Set and cleared by software. + TIM3RST: u1, + /// TIM4 reset Set and cleared by software. + TIM4RST: u1, + /// TIM5 reset Set and cleared by software. + TIM5RST: u1, + /// TIM6 reset Set and cleared by software. + TIM6RST: u1, + /// TIM7 reset Set and cleared by software. + TIM7RST: u1, + reserved14: u8, + /// SPI2 reset Set and cleared by software. + SPI2RST: u1, + reserved17: u2, + /// USART2 reset Set and cleared by software. + USART2RST: u1, + /// USART3 reset Set and cleared by software. + USART3RST: u1, + /// UART4 reset Set and cleared by software. + UART4RST: u1, + /// UART5 reset Set and cleared by software. + UART5RST: u1, + /// I2C1 reset Set and cleared by software. + I2C1RST: u1, + /// I2C2 reset Set and cleared by software. + I2C2RST: u1, + reserved24: u1, + /// CRS reset Set and cleared by software. + CRSRST: u1, + /// USART6 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + USART6RST: u1, + padding: u6, + }), + /// RCC APB1 peripheral reset register 2 + APB1RSTR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// I2C4 reset Set and cleared by software + I2C4RST: u1, + reserved5: u3, + /// LPTIM2 reset Set and cleared by software. + LPTIM2RST: u1, + /// I2C5 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + I2C5RST: u1, + /// I2C6 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + I2C6RST: u1, + reserved9: u1, + /// FDCAN1 reset Set and cleared by software. + FDCAN1RST: u1, + reserved23: u13, + /// UCPD1 reset Set and cleared by software. + UCPD1RST: u1, + padding: u8, + }), + /// RCC APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 reset Set and cleared by software. + TIM1RST: u1, + /// SPI1 reset Set and cleared by software. + SPI1RST: u1, + /// TIM8 reset Set and cleared by software. + TIM8RST: u1, + /// USART1 reset Set and cleared by software. + USART1RST: u1, + reserved16: u1, + /// TIM15 reset Set and cleared by software. + TIM15RST: u1, + /// TIM16 reset Set and cleared by software. + TIM16RST: u1, + /// TIM17 reset Set and cleared by software. + TIM17RST: u1, + reserved21: u2, + /// SAI1 reset Set and cleared by software. + SAI1RST: u1, + /// SAI2 reset Set and cleared by software. + SAI2RST: u1, + reserved24: u1, + /// USB reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + USBRST: u1, + /// GFXTIM reset This bit is set and cleared by software. Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + GFXTIMRST: u1, + /// LTDC reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + LTDCRST: u1, + /// DSI reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + DSIRST: u1, + padding: u4, + }), + /// RCC APB3 peripheral reset register + APB3RSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG reset Set and cleared by software. + SYSCFGRST: u1, + reserved5: u3, + /// SPI3 reset Set and cleared by software. + SPI3RST: u1, + /// LPUART1 reset Set and cleared by software. + LPUART1RST: u1, + /// I2C3 reset Set and cleared by software. + I2C3RST: u1, + reserved11: u3, + /// LPTIM1 reset Set and cleared by software. + LPTIM1RST: u1, + /// LPTIM3 reset Set and cleared by software. + LPTIM3RST: u1, + /// LPTIM4 reset Set and cleared by software. + LPTIM4RST: u1, + /// OPAMP reset Set and cleared by software. + OPAMPRST: u1, + /// COMP reset Set and cleared by software. + COMPRST: u1, + reserved20: u4, + /// VREFBUF reset Set and cleared by software. + VREFRST: u1, + padding: u11, + }), + reserved136: [4]u8, + /// RCC AHB1 peripheral clock enable register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 clock enable Set and cleared by software. + GPDMA1EN: u1, + /// CORDIC clock enable Set and cleared by software. + CORDICEN: u1, + /// FMAC clock enable Set and reset by software. + FMACEN: u1, + /// MDF1 clock enable Set and reset by software. + MDF1EN: u1, + reserved8: u4, + /// FLASH clock enable Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode. + FLASHEN: u1, + reserved12: u3, + /// CRC clock enable Set and cleared by software. + CRCEN: u1, + reserved15: u2, + /// JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + JPEGEN: u1, + /// Touch sensing controller clock enable Set and cleared by software. + TSCEN: u1, + /// RAMCFG clock enable Set and cleared by software. + RAMCFGEN: u1, + /// DMA2D clock enable Set and cleared by software. + DMA2DEN: u1, + /// GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + GFXMMUEN: u1, + /// GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + GPU2DEN: u1, + /// DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + DCACHE2EN: u1, + reserved24: u2, + /// GTZC1 clock enable Set and reset by software. + GTZC1EN: u1, + reserved28: u3, + /// BKPSRAM clock enable Set and reset by software. + BKPSRAMEN: u1, + reserved30: u1, + /// DCACHE1 clock enable Set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed. + DCACHE1EN: u1, + /// SRAM1 clock enable Set and reset by software. + SRAM1EN: u1, + }), + /// RCC AHB2 peripheral clock enable register 1 + AHB2ENR1: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable Set and cleared by software. + GPIOAEN: u1, + /// IO port B clock enable Set and cleared by software. + GPIOBEN: u1, + /// IO port C clock enable Set and cleared by software. + GPIOCEN: u1, + /// IO port D clock enable Set and cleared by software. + GPIODEN: u1, + /// IO port E clock enable Set and cleared by software. + GPIOEEN: u1, + /// IO port F clock enable Set and cleared by software. + GPIOFEN: u1, + /// IO port G clock enable Set and cleared by software. + GPIOGEN: u1, + /// IO port H clock enable Set and cleared by software. + GPIOHEN: u1, + /// IO port I clock enable Set and cleared by software. + GPIOIEN: u1, + /// I/O port J clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + GPIOJEN: u1, + /// ADC1 and ADC2 clock enable This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. + ADC12EN: u1, + reserved12: u1, + /// DCMI and PSSI clock enable Set and cleared by software. + DCMIEN: u1, + reserved14: u1, + /// OTG_FS clock enable Set and cleared by software. + USB_OTG_FSEN: u1, + /// OTG_HS PHY clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + USB_OTG_HS_PHYEN: u1, + /// AES clock enable Set and cleared by software. + AESEN: u1, + /// HASH clock enable Set and cleared by software + HASHEN: u1, + /// RNG clock enable Set and cleared by software. + RNGEN: u1, + /// PKA clock enable Set and cleared by software. + PKAEN: u1, + /// SAES clock enable Set and cleared by software. + SAESEN: u1, + /// OCTOSPIM clock enable Set and cleared by software. + OCTOSPIMEN: u1, + reserved23: u1, + /// OTFDEC1 clock enable Set and cleared by software. + OTFDEC1EN: u1, + /// OTFDEC2 clock enable Set and cleared by software. + OTFDEC2EN: u1, + reserved27: u2, + /// SDMMC1 clock enable Set and cleared by software. + SDMMC1EN: u1, + /// SDMMC2 clock enable Set and cleared by software. + SDMMC2EN: u1, + reserved30: u1, + /// SRAM2 clock enable Set and reset by software. + SRAM2EN: u1, + /// SRAM3 clock enable Set and reset by software. + SRAM3EN: u1, + }), + /// RCC AHB2 peripheral clock enable register 2 + AHB2ENR2: mmio.Mmio(packed struct(u32) { + /// FSMC clock enable Set and cleared by software. + FSMCEN: u1, + reserved4: u3, + /// OCTOSPI1 clock enable Set and cleared by software. + OCTOSPI1EN: u1, + reserved8: u3, + /// OCTOSPI2 clock enable Set and cleared by software. + OCTOSPI2EN: u1, + reserved12: u3, + /// HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + HSPI1EN: u1, + reserved30: u17, + /// SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + SRAM6EN: u1, + /// SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + SRAM5EN: u1, + }), + /// RCC AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// LPGPIO1 enable Set and cleared by software. + LPGPIO1EN: u1, + reserved2: u1, + /// PWR clock enable Set and cleared by software. + PWREN: u1, + reserved5: u2, + /// ADC4 clock enable Set and cleared by software. + ADC4EN: u1, + /// DAC1 clock enable Set and cleared by software. + DAC1EN: u1, + reserved9: u2, + /// LPDMA1 clock enable Set and cleared by software. + LPDMA1EN: u1, + /// ADF1 clock enable Set and cleared by software. + ADF1EN: u1, + reserved12: u1, + /// GTZC2 clock enable Set and cleared by software. + GTZC2EN: u1, + reserved31: u18, + /// SRAM4 clock enable Set and reset by software. + SRAM4EN: u1, + }), + reserved156: [4]u8, + /// RCC APB1 peripheral clock enable register 1 + APB1ENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable Set and cleared by software. + TIM2EN: u1, + /// TIM3 clock enable Set and cleared by software. + TIM3EN: u1, + /// TIM4 clock enable Set and cleared by software. + TIM4EN: u1, + /// TIM5 clock enable Set and cleared by software. + TIM5EN: u1, + /// TIM6 clock enable Set and cleared by software. + TIM6EN: u1, + /// TIM7 clock enable Set and cleared by software. + TIM7EN: u1, + reserved11: u5, + /// WWDG clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. + WWDGEN: u1, + reserved14: u2, + /// SPI2 clock enable Set and cleared by software. + SPI2EN: u1, + reserved17: u2, + /// USART2 clock enable Set and cleared by software. + USART2EN: u1, + /// USART3 clock enable Set and cleared by software. + USART3EN: u1, + /// UART4 clock enable Set and cleared by software. + UART4EN: u1, + /// UART5 clock enable Set and cleared by software. + UART5EN: u1, + /// I2C1 clock enable Set and cleared by software. + I2C1EN: u1, + /// I2C2 clock enable Set and cleared by software. + I2C2EN: u1, + reserved24: u1, + /// CRS clock enable Set and cleared by software. + CRSEN: u1, + /// USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + USART6EN: u1, + padding: u6, + }), + /// RCC APB1 peripheral clock enable register 2 + APB1ENR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// I2C4 clock enable Set and cleared by software + I2C4EN: u1, + reserved5: u3, + /// LPTIM2 clock enable Set and cleared by software. + LPTIM2EN: u1, + /// I2C5 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + I2C5EN: u1, + /// I2C6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + I2C6EN: u1, + reserved9: u1, + /// FDCAN1 clock enable Set and cleared by software. + FDCAN1EN: u1, + reserved23: u13, + /// UCPD1 clock enable Set and cleared by software. + UCPD1EN: u1, + padding: u8, + }), + /// RCC APB2 peripheral clock enable register + APB2ENR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 clock enable Set and cleared by software. + TIM1EN: u1, + /// SPI1 clock enable Set and cleared by software. + SPI1EN: u1, + /// TIM8 clock enable Set and cleared by software. + TIM8EN: u1, + /// USART1clock enable Set and cleared by software. + USART1EN: u1, + reserved16: u1, + /// TIM15 clock enable Set and cleared by software. + TIM15EN: u1, + /// TIM16 clock enable Set and cleared by software. + TIM16EN: u1, + /// TIM17 clock enable Set and cleared by software. + TIM17EN: u1, + reserved21: u2, + /// SAI1 clock enable Set and cleared by software. + SAI1EN: u1, + /// SAI2 clock enable Set and cleared by software. + SAI2EN: u1, + reserved24: u1, + /// USB clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + USBEN: u1, + /// GFXTIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + GFXTIMEN: u1, + /// LTDC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + LTDCEN: u1, + /// DSI clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + DSIEN: u1, + padding: u4, + }), + /// RCC APB3 peripheral clock enable register + APB3ENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG clock enable Set and cleared by software. + SYSCFGEN: u1, + reserved5: u3, + /// SPI3 clock enable Set and cleared by software. + SPI3EN: u1, + /// LPUART1 clock enable Set and cleared by software. + LPUART1EN: u1, + /// I2C3 clock enable Set and cleared by software. + I2C3EN: u1, + reserved11: u3, + /// LPTIM1 clock enable Set and cleared by software. + LPTIM1EN: u1, + /// LPTIM3 clock enable Set and cleared by software. + LPTIM3EN: u1, + /// LPTIM4 clock enable Set and cleared by software. + LPTIM4EN: u1, + /// OPAMP clock enable Set and cleared by software. + OPAMPEN: u1, + /// COMP clock enable Set and cleared by software. + COMPEN: u1, + reserved20: u4, + /// VREFBUF clock enable Set and cleared by software. + VREFEN: u1, + /// RTC and TAMP APB clock enable Set and cleared by software. + RTCAPBEN: u1, + padding: u10, + }), + reserved176: [4]u8, + /// RCC AHB1 peripheral clocks enable in Sleep and Stop modes register + AHB1SMENR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + GPDMA1SMEN: u1, + /// CORDIC clocks enable during Sleep and Stop modes Set and cleared by software during Sleep mode. + CORDICSMEN: u1, + /// FMAC clocks enable during Sleep and Stop modes. Set and cleared by software. + FMACSMEN: u1, + /// MDF1 clocks enable during Sleep and Stop modes. Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + MDF1SMEN: u1, + reserved8: u4, + /// FLASH clocks enable during Sleep and Stop modes Set and cleared by software. + FLASHSMEN: u1, + reserved12: u3, + /// CRC clocks enable during Sleep and Stop modes Set and cleared by software. + CRCSMEN: u1, + reserved15: u2, + /// JPEG clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + JPEGSMEN: u1, + /// TSC clocks enable during Sleep and Stop modes Set and cleared by software. + TSCSMEN: u1, + /// RAMCFG clocks enable during Sleep and Stop modes Set and cleared by software. + RAMCFGSMEN: u1, + /// DMA2D clocks enable during Sleep and Stop modes Set and cleared by software. + DMA2DSMEN: u1, + /// GFXMMU clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + GFXMMUSMEN: u1, + /// GPU2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + GPU2DSMEN: u1, + /// DCACHE2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + DCACHE2SMEN: u1, + reserved24: u2, + /// GTZC1 clocks enable during Sleep and Stop modes Set and cleared by software. + GTZC1SMEN: u1, + reserved28: u3, + /// BKPSRAM clocks enable during Sleep and Stop modes Set and cleared by software + BKPSRAMSMEN: u1, + /// ICACHE clocks enable during Sleep and Stop modes Set and cleared by software. + ICACHESMEN: u1, + /// DCACHE1 clocks enable during Sleep and Stop modes Set and cleared by software. + DCACHE1SMEN: u1, + /// SRAM1 clocks enable during Sleep and Stop modes Set and cleared by software. + SRAM1SMEN: u1, + }), + /// RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 1 + AHB2SMENR1: mmio.Mmio(packed struct(u32) { + /// IO port A clocks enable during Sleep and Stop modes Set and cleared by software. + GPIOASMEN: u1, + /// IO port B clocks enable during Sleep and Stop modes Set and cleared by software. + GPIOBSMEN: u1, + /// IO port C clocks enable during Sleep and Stop modes Set and cleared by software. + GPIOCSMEN: u1, + /// IO port D clocks enable during Sleep and Stop modes Set and cleared by software. + GPIODSMEN: u1, + /// IO port E clocks enable during Sleep and Stop modes Set and cleared by software. + GPIOESMEN: u1, + /// IO port F clocks enable during Sleep and Stop modes Set and cleared by software. + GPIOFSMEN: u1, + /// IO port G clocks enable during Sleep and Stop modes Set and cleared by software. + GPIOGSMEN: u1, + /// IO port H clocks enable during Sleep and Stop modes Set and cleared by software. + GPIOHSMEN: u1, + /// IO port I clocks enable during Sleep and Stop modes Set and cleared by software. + GPIOISMEN: u1, + /// I/O port J clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + GPIOJSMEN: u1, + /// ADC1 and ADC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. + ADC12SMEN: u1, + reserved12: u1, + /// DCMI and PSSI clocks enable during Sleep and Stop modes Set and cleared by software. + DCMISMEN: u1, + reserved14: u1, + /// OTG_FS clocks enable during Sleep and Stop modes Set and cleared by software. + USB_OTG_FSSMEN: u1, + /// OTG_HS PHY clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + USB_OTG_HS_PHYSMEN: u1, + /// AES clock enable during Sleep and Stop modes Set and cleared by software + AESSMEN: u1, + /// HASH clock enable during Sleep and Stop modes Set and cleared by software + HASHSMEN: u1, + /// Random number generator (RNG) clocks enable during Sleep and Stop modes Set and cleared by software. + RNGSMEN: u1, + /// PKA clocks enable during Sleep and Stop modes Set and cleared by software. + PKASMEN: u1, + /// SAES accelerator clocks enable during Sleep and Stop modes Set and cleared by software. + SAESSMEN: u1, + /// OCTOSPIM clocks enable during Sleep and Stop modes Set and cleared by software. + OCTOSPIMSMEN: u1, + reserved23: u1, + /// OTFDEC1 clocks enable during Sleep and Stop modes Set and cleared by software. + OTFDEC1SMEN: u1, + /// OTFDEC2 clocks enable during Sleep and Stop modes Set and cleared by software. + OTFDEC2SMEN: u1, + reserved27: u2, + /// SDMMC1 clocks enable during Sleep and Stop modes Set and cleared by software. + SDMMC1SMEN: u1, + /// SDMMC2 clocks enable during Sleep and Stop modes Set and cleared by software. + SDMMC2SMEN: u1, + reserved30: u1, + /// SRAM2 clocks enable during Sleep and Stop modes Set and cleared by software. + SRAM2SMEN: u1, + /// SRAM3 clocks enable during Sleep and Stop modes Set and cleared by software. + SRAM3SMEN: u1, + }), + /// RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 2 + AHB2SMENR2: mmio.Mmio(packed struct(u32) { + /// FSMC clocks enable during Sleep and Stop modes Set and cleared by software. + FSMCSMEN: u1, + reserved4: u3, + /// OCTOSPI1 clocks enable during Sleep and Stop modes Set and cleared by software. + OCTOSPI1SMEN: u1, + reserved8: u3, + /// OCTOSPI2 clocks enable during Sleep and Stop modes Set and cleared by software. + OCTOSPI2SMEN: u1, + reserved12: u3, + /// HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + HSPI1SMEN: u1, + reserved30: u17, + /// SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + SRAM6SMEN: u1, + /// SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + SRAM5SMEN: u1, + }), + /// RCC AHB3 peripheral clocks enable in Sleep and Stop modes register + AHB3SMENR: mmio.Mmio(packed struct(u32) { + /// LPGPIO1 enable during Sleep and Stop modes Set and cleared by software. + LPGPIO1SMEN: u1, + reserved2: u1, + /// PWR clock enable during Sleep and Stop modes Set and cleared by software. + PWRSMEN: u1, + reserved5: u2, + /// ADC4 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + ADC4SMEN: u1, + /// DAC1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + DAC1SMEN: u1, + reserved9: u2, + /// LPDMA1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPDMA1SMEN: u1, + /// ADF1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + ADF1SMEN: u1, + reserved12: u1, + /// GTZC2 clock enable during Sleep and Stop modes Set and cleared by software. + GTZC2SMEN: u1, + reserved31: u18, + /// SRAM4 clocks enable during Sleep and Stop modes Set and cleared by software. + SRAM4SMEN: u1, + }), + reserved196: [4]u8, + /// RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1 + APB1SMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 clocks enable during Sleep and Stop modes Set and cleared by software. + TIM2SMEN: u1, + /// TIM3 clocks enable during Sleep and Stop modes Set and cleared by software. + TIM3SMEN: u1, + /// TIM4 clocks enable during Sleep and Stop modes Set and cleared by software. + TIM4SMEN: u1, + /// TIM5 clocks enable during Sleep and Stop modes Set and cleared by software. + TIM5SMEN: u1, + /// TIM6 clocks enable during Sleep and Stop modes Set and cleared by software. + TIM6SMEN: u1, + /// TIM7 clocks enable during Sleep and Stop modes Set and cleared by software. + TIM7SMEN: u1, + reserved11: u5, + /// Window watchdog clocks enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated. + WWDGSMEN: u1, + reserved14: u2, + /// SPI2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + SPI2SMEN: u1, + reserved17: u2, + /// USART2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + USART2SMEN: u1, + /// USART3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + USART3SMEN: u1, + /// UART4 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + UART4SMEN: u1, + /// UART5 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + UART5SMEN: u1, + /// I2C1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + I2C1SMEN: u1, + /// I2C2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + I2C2SMEN: u1, + reserved24: u1, + /// CRS clock enable during Sleep and Stop modes Set and cleared by software. + CRSSMEN: u1, + /// USART6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + USART6SMEN: u1, + padding: u6, + }), + /// RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 + APB1SMENR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// I2C4 clocks enable during Sleep and Stop modes Set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. + I2C4SMEN: u1, + reserved5: u3, + /// LPTIM2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPTIM2SMEN: u1, + /// I2C5 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + I2C5SMEN: u1, + /// I2C6 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + I2C6SMEN: u1, + reserved9: u1, + /// FDCAN1 clocks enable during Sleep and Stop modes Set and cleared by software. + FDCAN1SMEN: u1, + reserved23: u13, + /// UCPD1 clocks enable during Sleep and Stop modes Set and cleared by software. + UCPD1SMEN: u1, + padding: u8, + }), + /// RCC APB2 peripheral clocks enable in Sleep and Stop modes register + APB2SMENR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 clocks enable during Sleep and Stop modes Set and cleared by software. + TIM1SMEN: u1, + /// SPI1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + SPI1SMEN: u1, + /// TIM8 clocks enable during Sleep and Stop modes Set and cleared by software. + TIM8SMEN: u1, + /// USART1clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + USART1SMEN: u1, + reserved16: u1, + /// TIM15 clocks enable during Sleep and Stop modes Set and cleared by software. + TIM15SMEN: u1, + /// TIM16 clocks enable during Sleep and Stop modes Set and cleared by software. + TIM16SMEN: u1, + /// TIM17 clocks enable during Sleep and Stop modes Set and cleared by software. + TIM17SMEN: u1, + reserved21: u2, + /// SAI1 clocks enable during Sleep and Stop modes Set and cleared by software. + SAI1SMEN: u1, + /// SAI2 clocks enable during Sleep and Stop modes Set and cleared by software. + SAI2SMEN: u1, + reserved24: u1, + /// USB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + USBSMEN: u1, + /// GFXTIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + GFXTIMSMEN: u1, + /// LTDC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + LTDCSMEN: u1, + /// DSI clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + DSISMEN: u1, + padding: u4, + }), + /// RCC APB3 peripheral clock enable in Sleep and Stop modes register + APB3SMENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG clocks enable during Sleep and Stop modes Set and cleared by software. + SYSCFGSMEN: u1, + reserved5: u3, + /// SPI3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + SPI3SMEN: u1, + /// LPUART1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPUART1SMEN: u1, + /// I2C3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + I2C3SMEN: u1, + reserved11: u3, + /// LPTIM1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPTIM1SMEN: u1, + /// LPTIM3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPTIM3SMEN: u1, + /// LPTIM4 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPTIM4SMEN: u1, + /// OPAMP clocks enable during Sleep and Stop modes Set and cleared by software. + OPAMPSMEN: u1, + /// COMP clocks enable during Sleep and Stop modes Set and cleared by software. + COMPSMEN: u1, + reserved20: u4, + /// VREFBUF clocks enable during Sleep and Stop modes Set and cleared by software. + VREFSMEN: u1, + /// RTC and TAMP APB clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + RTCAPBSMEN: u1, + padding: u10, + }), + reserved216: [4]u8, + /// RCC SmartRun domain peripheral autonomous mode register + SRDAMR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// SPI3 autonomous mode enable in Stop 0,1, 2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + SPI3AMEN: u1, + /// LPUART1 autonomous mode enable in Stop 0,1, 2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPUART1AMEN: u1, + /// I2C3 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + I2C3AMEN: u1, + reserved11: u3, + /// LPTIM1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPTIM1AMEN: u1, + /// LPTIM3 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPTIM3AMEN: u1, + /// LPTIM4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPTIM4AMEN: u1, + /// OPAMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. + OPAMPAMEN: u1, + /// COMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. + COMPAMEN: u1, + reserved20: u4, + /// VREFBUF autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. + VREFAMEN: u1, + /// RTC and TAMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + RTCAPBAMEN: u1, + reserved25: u3, + /// ADC4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + ADC4AMEN: u1, + /// LPGPIO1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. + LPGPIO1AMEN: u1, + /// DAC1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + DAC1AMEN: u1, + /// LPDMA1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPDMA1AMEN: u1, + /// ADF1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + ADF1AMEN: u1, + reserved31: u1, + /// SRAM4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. + SRAM4AMEN: u1, + }), + reserved224: [4]u8, + /// RCC peripherals independent clock configuration register 1 + CCIPR1: mmio.Mmio(packed struct(u32) { + /// USART1 kernel clock source selection This bits are used to select the USART1 kernel clock source. Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. + USART1SEL: packed union { + raw: u2, + value: USART1SEL, + }, + /// USART2 kernel clock source selection This bits are used to select the USART2 kernel clock source. Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. + USART2SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// USART3 kernel clock source selection This bits are used to select the USART3 kernel clock source. Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. + USART3SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// UART4 kernel clock source selection This bits are used to select the UART4 kernel clock source. Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. + UART4SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. + UART5SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK. + I2C1SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK. + I2C2SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK. + I2C4SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK. + SPI2SEL: packed union { + raw: u2, + value: SPI2SEL, + }, + /// Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1. + LPTIM2SEL: packed union { + raw: u2, + value: LPTIM2SEL, + }, + /// SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK. + SPI1SEL: packed union { + raw: u2, + value: SPI1SEL, + }, + /// SysTick clock source selection These bits are used to select the SysTick clock source. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry. + SYSTICKSEL: packed union { + raw: u2, + value: SYSTICKSEL, + }, + /// FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source. + FDCAN1SEL: packed union { + raw: u2, + value: FDCANSEL, + }, + /// intermediate clock source selection These bits are used to select the clock source used by OTG_FS and SDMMC. + ICLKSEL: packed union { + raw: u2, + value: ICLKSEL, + }, + reserved29: u1, + /// Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS. When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture. 0xx: HSI, MSIK and MSIS dividers disabled Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division. + TIMICSEL: packed union { + raw: u3, + value: TIMICSEL, + }, + }), + /// RCC peripherals independent clock configuration register 2 + CCIPR2: mmio.Mmio(packed struct(u32) { + /// MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. others: reserved + MDF1SEL: packed union { + raw: u3, + value: MDFSEL, + }, + reserved5: u2, + /// SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. + SAI1SEL: packed union { + raw: u3, + value: SAISEL, + }, + /// SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. + SAI2SEL: packed union { + raw: u3, + value: SAISEL, + }, + /// SAES kernel clock source selection This bit is used to select the SAES kernel clock source. + SAESSEL: packed union { + raw: u1, + value: SAESSEL, + }, + /// RNGSEL kernel clock source selection These bits are used to select the RNG kernel clock source. + RNGSEL: packed union { + raw: u2, + value: RNGSEL, + }, + /// SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC. + SDMMCSEL: packed union { + raw: u1, + value: SDMMCSEL, + }, + /// DSI kernel clock source selection This bit is used to select the DSI kernel clock source. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value. + DSISEL: packed union { + raw: u1, + value: DSISEL, + }, + /// USART6 kernel clock source selection These bits are used to select the USART6 kernel clock source. The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + USART6SEL: packed union { + raw: u2, + value: USARTSEL, + }, + /// LTDC kernel clock source selection This bit is used to select the LTDC kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + LTDCSEL: packed union { + raw: u1, + value: LTDCSEL, + }, + reserved20: u1, + /// OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source. + OCTOSPISEL: packed union { + raw: u2, + value: OCTOSPISEL, + }, + /// HSPI1 kernel clock source selection These bits are used to select the HSPI1 kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + HSPI1SEL: packed union { + raw: u2, + value: HSPISEL, + }, + /// I2C5 kernel clock source selection These bits are used to select the I2C5 kernel clock source. The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + I2C5SEL: packed union { + raw: u2, + value: I2CSEL, + }, + /// I2C6 kernel clock source selection These bits are used to select the I2C6 kernel clock source. The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + I2C6SEL: packed union { + raw: u2, + value: I2CSEL, + }, + reserved30: u2, + /// OTG_HS PHY kernel clock source selection These bits are used to select the OTG_HS PHY kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + OTGHSSEL: packed union { + raw: u2, + value: OTGHSSEL, + }, + }), + /// RCC peripherals independent clock configuration register 3 + CCIPR3: mmio.Mmio(packed struct(u32) { + /// LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. others: reserved Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI, LSE or MSIK. + LPUART1SEL: packed union { + raw: u3, + value: LPUSARTSEL, + }, + /// SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK. + SPI3SEL: packed union { + raw: u2, + value: SPI3SEL, + }, + reserved6: u1, + /// I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK. + I2C3SEL: packed union { + raw: u2, + value: I2C3SEL, + }, + /// LPTIM3 and LPTIM4 kernel clock source selection These bits are used to select the LPTIM3 and LPTIM4 kernel clock source. Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1. + LPTIM34SEL: packed union { + raw: u2, + value: LPTIMSEL, + }, + /// LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1. + LPTIM1SEL: packed union { + raw: u2, + value: LPTIMSEL, + }, + /// ADC1, ADC4 and DAC1 kernel clock source selection These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source. others: reserved Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode). + ADCDACSEL: packed union { + raw: u3, + value: ADCDACSEL, + }, + /// DAC1 sample and hold clock source selection This bit is used to select the DAC1 sample and hold clock source. + DAC1SEL: packed union { + raw: u1, + value: DACSEL, + }, + /// ADF1 kernel clock source selection These bits are used to select the ADF1 kernel clock source. others: reserved Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK. + ADF1SEL: packed union { + raw: u3, + value: ADFSEL, + }, + padding: u13, + }), + reserved240: [4]u8, + /// RCC Backup domain control register + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enable Set and cleared by software. + LSEON: u1, + /// LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. + LSERDY: u1, + /// LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). + LSEBYP: u1, + /// LSE oscillator drive capability Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in 'Xtal mode when it is not in bypass mode. + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// CSS on LSE enable Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit. + LSECSSON: u1, + /// CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE). + LSECSSD: u1, + /// LSE system clock (LSESYS) enable Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE. + LSESYSEN: u1, + /// RTC and TAMP clock source selection Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them. + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved11: u1, + /// LSE system clock (LSESYS) ready Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. + LSESYSRDY: u1, + /// LSE clock glitch filter enable Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0) + LSEGFON: u1, + reserved15: u2, + /// RTC and TAMP clock enable Set and cleared by software. + RTCEN: u1, + /// Backup domain software reset Set and cleared by software. + BDRST: u1, + reserved24: u7, + /// Low-speed clock output (LSCO) enable Set and cleared by software. + LSCOEN: u1, + /// Low-speed clock output selection Set and cleared by software. + LSCOSEL: packed union { + raw: u1, + value: LSCOSEL, + }, + /// LSI oscillator enable Set and cleared by software. + LSION: u1, + /// LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0. + LSIRDY: u1, + /// Low-speed clock divider configuration Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. + LSIPREDIV: packed union { + raw: u1, + value: LSIPREDIV, + }, + padding: u3, + }), + /// RCC control/status register + CSR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// MSIK range after Standby mode Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing the MSIKSRANGE does not change the current MSIK frequency. + MSIKSRANGE: packed union { + raw: u4, + value: MSIXSRANGE, + }, + /// MSIS range after Standby mode Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing the MSISSRANGE does not change the current MSIS frequency. + MSISSRANGE: packed union { + raw: u4, + value: MSIXSRANGE, + }, + reserved23: u7, + /// Remove reset flag Set by software to clear the reset flags. + RMVF: u1, + reserved25: u1, + /// Option byte loader reset flag Set by hardware when a reset from the option byte loading occurs. Cleared by writing to the RMVF bit. + OBLRSTF: u1, + /// NRST pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. + PINRSTF: u1, + /// BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit. + BORRSTF: u1, + /// Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. + SFTRSTF: u1, + /// Independent watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit. + IWDGRSTF: u1, + /// Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. + WWDGRSTF: u1, + /// Low-power reset flag Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared. Cleared by writing to the RMVF bit. + LPWRRSTF: u1, + }), + reserved272: [24]u8, + /// RCC secure configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// HSI clock configuration and status bits security Set and reset by software. + HSISEC: packed union { + raw: u1, + value: SECURITY, + }, + /// HSE clock configuration bits, status bits and HSE_CSS security Set and reset by software. + HSESEC: packed union { + raw: u1, + value: SECURITY, + }, + /// MSI clock configuration and status bits security Set and reset by software. + MSISEC: packed union { + raw: u1, + value: SECURITY, + }, + /// LSI clock configuration and status bits security Set and reset by software. + LSISEC: packed union { + raw: u1, + value: SECURITY, + }, + /// LSE clock configuration and status bits security Set and reset by software. + LSESEC: packed union { + raw: u1, + value: SECURITY, + }, + /// SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security Set and reset by software. + SYSCLKSEC: packed union { + raw: u1, + value: SECURITY, + }, + /// AHBx/APBx prescaler configuration bits security Set and reset by software. + PRESCSEC: packed union { + raw: u1, + value: SECURITY, + }, + /// PLL1 clock configuration and status bits security Set and reset by software. + PLLSEC: packed union { + raw: u1, + value: SECURITY, + }, + reserved10: u2, + /// intermediate clock source selection security Set and reset by software. + ICLKSEC: packed union { + raw: u1, + value: SECURITY, + }, + /// HSI48 clock configuration and status bits security Set and reset by software. + HSI48SEC: packed union { + raw: u1, + value: SECURITY, + }, + /// Remove reset flag security Set and reset by software. + RMVFSEC: packed union { + raw: u1, + value: SECURITY, + }, + padding: u19, + }), + /// RCC privilege configuration register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access. + SPRIV: u1, + /// RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure. + NSPRIV: u1, + padding: u30, + }), + }; + }; + + pub const rcc_wb = struct { + pub const ADCSEL = enum(u2) { + /// No clock selected + DISABLE = 0x0, + PLLSAI1_R = 0x1, + PLL1_P = 0x2, + /// SYSCLK clock selected + SYS = 0x3, }; - pub const PLLSRC = enum(u2) { - /// HSI selected as PLL clock - HSI = 0x0, - /// CSI selected as PLL clock - CSI = 0x1, - /// HSE selected as PLL clock - HSE = 0x2, - /// No clock sent to DIVMx dividers and PLLs - DISABLE = 0x3, + pub const CLK48SEL = enum(u2) { + /// HSI48 clock selected + HSI48 = 0x0, + /// PLLSAI1_Q aka PLL48M1CLK clock selected + PLLSAI1_Q = 0x1, + /// PLL_Q aka PLL48M2CLK clock selected + PLL1_Q = 0x2, + /// MSI clock selected + MSI = 0x3, }; - pub const PLLVCOSEL = enum(u1) { - /// VCO frequency range 192 to 836 MHz - WideVCO = 0x0, - /// VCO frequency range 150 to 420 MHz - MediumVCO = 0x1, + pub const HPRE = enum(u4) { + /// DCLK not divided + Div1 = 0x0, + /// hclk = SYSCLK divided by 3 + Div3 = 0x1, + /// hclk = SYSCLK divided by 5 + Div5 = 0x2, + /// hclk = SYSCLK divided by 6 + Div6 = 0x5, + /// hclk = SYSCLK divided by 8 + Div10 = 0x6, + /// hclk = SYSCLK divided by 32 + Div32 = 0x7, + /// hclk = SYSCLK divided by 2 + Div2 = 0x8, + /// hclk = SYSCLK divided by 4 + Div4 = 0x9, + /// hclk = SYSCLK divided by 8 + Div8 = 0xa, + /// hclk = SYSCLK divided by 16 + Div16 = 0xb, + /// hclk = SYSCLK divided by 64 + Div64 = 0xc, + /// hclk = SYSCLK divided by 128 + Div128 = 0xd, + /// hclk = SYSCLK divided by 256 + Div256 = 0xe, + /// hclk = SYSCLK divided by 256 + Div512 = 0xf, + _, }; - pub const PPRE = enum(u3) { - /// rcc_hclk not divided + pub const HSEPRE = enum(u1) { Div1 = 0x0, - /// rcc_hclk divided by 2 - Div2 = 0x4, - /// rcc_hclk divided by 4 - Div4 = 0x5, - /// rcc_hclk divided by 8 - Div8 = 0x6, - /// rcc_hclk divided by 16 - Div16 = 0x7, + Div2 = 0x1, + }; + + pub const I2C1SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, _, }; - pub const RNGSEL = enum(u2) { - /// HSI48 selected as peripheral clock - HSI48 = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// LSE selected as peripheral clock - LSE = 0x2, - /// LSI selected as peripheral clock - LSI = 0x3, + pub const I2C3SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + _, }; - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, + pub const LPTIM1SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// LSI clock selected + LSI = 0x1, + /// HSI clock selected + HSI = 0x2, + /// LSE clock selected + LSE = 0x3, }; - pub const SAIASEL = enum(u3) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_p selected as peripheral clock - PLL3_P = 0x2, - /// i2s_ckin selected as peripheral clock - I2S_CKIN = 0x3, - /// PER selected as peripheral clock - PER = 0x4, - _, + pub const LPTIM2SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// LSI clock selected + LSI = 0x1, + /// HSI clock selected + HSI = 0x2, + /// LSE clock selected + LSE = 0x3, }; - pub const SAISEL = enum(u3) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_p selected as peripheral clock - PLL3_P = 0x2, - /// I2S_CKIN selected as peripheral clock - I2S_CKIN = 0x3, - /// PER selected as peripheral clock - PER = 0x4, - _, + pub const LPUART1SEL = enum(u2) { + /// PCLK clock selected + PCLK1 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + HSE = 0x3, }; - pub const SDMMCSEL = enum(u1) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_r selected as peripheral clock - PLL2_R = 0x1, + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, }; - pub const SPDIFRXSEL = enum(u2) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_r selected as peripheral clock - PLL2_R = 0x1, - /// pll3_r selected as peripheral clock - PLL3_R = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, + pub const MCOPRE = enum(u3) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x1, + /// Division by 4 + Div4 = 0x2, + /// Division by 8 + Div8 = 0x3, + /// Division by 16 + Div16 = 0x4, + _, }; - pub const SPI45SEL = enum(u3) { - /// APB2 clock selected as peripheral clock - PCLK2 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock + pub const MCOSEL = enum(u4) { + /// No clock + DISABLE = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// MSI oscillator clock selected + MSI = 0x2, + /// HSI oscillator clock selected HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// HSE selected as peripheral clock - HSE = 0x5, + /// HSE clock selected (after stabilization, after HSERDY = 1) + HSE = 0x4, + /// PLL clock selected + PLL_R = 0x5, + /// LSI1 oscillator clock selected + LSI1 = 0x6, + /// LSI2 oscillator clock selected + LSI2 = 0x7, + /// LSE oscillator clock selected + LSE = 0x8, + /// HSI48 oscillator clock selected + HSI48 = 0x9, + /// HSE clock selected (before stabilization, after HSEON = 1) + HSE_UNSTABLE = 0xc, _, }; - pub const SPI6SEL = enum(u3) { - /// rcc_pclk4 selected as peripheral clock - PCLK4 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// HSE selected as peripheral clock - HSE = 0x5, + pub const MSIRANGE = enum(u4) { + /// range 0 around 100 kHz + Range100K = 0x0, + /// range 1 around 200 kHz + Range200K = 0x1, + /// range 2 around 400 kHz + Range400K = 0x2, + /// range 3 around 800 kHz + Range800K = 0x3, + /// range 4 around 1 MHz + Range1M = 0x4, + /// range 5 around 2 MHz + Range2M = 0x5, + /// range 6 around 4 MHz + Range4M = 0x6, + /// range 7 around 8 MHz + Range8M = 0x7, + /// range 8 around 16 MHz + Range16M = 0x8, + /// range 9 around 24 MHz + Range24M = 0x9, + /// range 10 around 32 MHz + Range32M = 0xa, + /// range 11 around 48 MHz + Range48M = 0xb, _, }; - pub const STOPWUCK = enum(u1) { - /// HSI selected as wake up clock from system Stop - HSI = 0x0, - /// CSI selected as wake up clock from system Stop - CSI = 0x1, + pub const PLLM = enum(u3) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, }; - pub const SW = enum(u3) { - /// HSI selected as system clock - HSI = 0x0, - /// CSI selected as system clock - CSI = 0x1, - /// HSE selected as system clock - HSE = 0x2, - /// PLL1 selected as system clock - PLL1_P = 0x3, + pub const PLLN = enum(u7) { + Mul6 = 0x6, + Mul7 = 0x7, + Mul8 = 0x8, + Mul9 = 0x9, + Mul10 = 0xa, + Mul11 = 0xb, + Mul12 = 0xc, + Mul13 = 0xd, + Mul14 = 0xe, + Mul15 = 0xf, + Mul16 = 0x10, + Mul17 = 0x11, + Mul18 = 0x12, + Mul19 = 0x13, + Mul20 = 0x14, + Mul21 = 0x15, + Mul22 = 0x16, + Mul23 = 0x17, + Mul24 = 0x18, + Mul25 = 0x19, + Mul26 = 0x1a, + Mul27 = 0x1b, + Mul28 = 0x1c, + Mul29 = 0x1d, + Mul30 = 0x1e, + Mul31 = 0x1f, + Mul32 = 0x20, + Mul33 = 0x21, + Mul34 = 0x22, + Mul35 = 0x23, + Mul36 = 0x24, + Mul37 = 0x25, + Mul38 = 0x26, + Mul39 = 0x27, + Mul40 = 0x28, + Mul41 = 0x29, + Mul42 = 0x2a, + Mul43 = 0x2b, + Mul44 = 0x2c, + Mul45 = 0x2d, + Mul46 = 0x2e, + Mul47 = 0x2f, + Mul48 = 0x30, + Mul49 = 0x31, + Mul50 = 0x32, + Mul51 = 0x33, + Mul52 = 0x34, + Mul53 = 0x35, + Mul54 = 0x36, + Mul55 = 0x37, + Mul56 = 0x38, + Mul57 = 0x39, + Mul58 = 0x3a, + Mul59 = 0x3b, + Mul60 = 0x3c, + Mul61 = 0x3d, + Mul62 = 0x3e, + Mul63 = 0x3f, + Mul64 = 0x40, + Mul65 = 0x41, + Mul66 = 0x42, + Mul67 = 0x43, + Mul68 = 0x44, + Mul69 = 0x45, + Mul70 = 0x46, + Mul71 = 0x47, + Mul72 = 0x48, + Mul73 = 0x49, + Mul74 = 0x4a, + Mul75 = 0x4b, + Mul76 = 0x4c, + Mul77 = 0x4d, + Mul78 = 0x4e, + Mul79 = 0x4f, + Mul80 = 0x50, + Mul81 = 0x51, + Mul82 = 0x52, + Mul83 = 0x53, + Mul84 = 0x54, + Mul85 = 0x55, + Mul86 = 0x56, + Mul87 = 0x57, + Mul88 = 0x58, + Mul89 = 0x59, + Mul90 = 0x5a, + Mul91 = 0x5b, + Mul92 = 0x5c, + Mul93 = 0x5d, + Mul94 = 0x5e, + Mul95 = 0x5f, + Mul96 = 0x60, + Mul97 = 0x61, + Mul98 = 0x62, + Mul99 = 0x63, + Mul100 = 0x64, + Mul101 = 0x65, + Mul102 = 0x66, + Mul103 = 0x67, + Mul104 = 0x68, + Mul105 = 0x69, + Mul106 = 0x6a, + Mul107 = 0x6b, + Mul108 = 0x6c, + Mul109 = 0x6d, + Mul110 = 0x6e, + Mul111 = 0x6f, + Mul112 = 0x70, + Mul113 = 0x71, + Mul114 = 0x72, + Mul115 = 0x73, + Mul116 = 0x74, + Mul117 = 0x75, + Mul118 = 0x76, + Mul119 = 0x77, + Mul120 = 0x78, + Mul121 = 0x79, + Mul122 = 0x7a, + Mul123 = 0x7b, + Mul124 = 0x7c, + Mul125 = 0x7d, + Mul126 = 0x7e, + Mul127 = 0x7f, _, }; - pub const SWPMISEL = enum(u1) { - /// pclk selected as peripheral clock - PCLK1 = 0x0, - /// hsi_ker selected as peripheral clock - HSI = 0x1, + pub const PLLP = enum(u5) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + Div17 = 0x10, + Div18 = 0x11, + Div19 = 0x12, + Div20 = 0x13, + Div21 = 0x14, + Div22 = 0x15, + Div23 = 0x16, + Div24 = 0x17, + Div25 = 0x18, + Div26 = 0x19, + Div27 = 0x1a, + Div28 = 0x1b, + Div29 = 0x1c, + Div30 = 0x1d, + Div31 = 0x1e, + _, }; - pub const TIMPRE = enum(u1) { - /// Timer kernel clock equal to 2x pclk by default - DefaultX2 = 0x0, - /// Timer kernel clock equal to 4x pclk by default - DefaultX4 = 0x1, + pub const PLLQ = enum(u3) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + _, }; - pub const USART16910SEL = enum(u3) { - /// rcc_pclk2 selected as peripheral clock - PCLK2 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, + pub const PLLR = enum(u3) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, _, }; - pub const USART234578SEL = enum(u3) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, + pub const PLLSRC = enum(u2) { + /// No clock selected as PLL entry clock source + DISABLE = 0x0, + /// MSI selected as PLL entry clock source + MSI = 0x1, + /// HSI selected as PLL entry clock source + HSI = 0x2, + /// HSE selected as PLL entry clock source + HSE = 0x3, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, _, }; - pub const USBSEL = enum(u2) { - /// Disable the kernel clock + pub const RNGSEL = enum(u2) { + /// CLK48 + CLK48 = 0x0, + /// LSI clock selected + LSI = 0x1, + /// LSE clock selected + LSE = 0x2, + _, + }; + + pub const RTCSEL = enum(u2) { + /// No clock selected DISABLE = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// HSI48 selected as peripheral clock - HSI48 = 0x3, + /// LSE oscillator clock selected + LSE = 0x1, + /// LSI oscillator clock selected + LSI = 0x2, + /// HSE oscillator clock divided by 32 selected + HSE = 0x3, + }; + + pub const SAI1SEL = enum(u2) { + PLLSAI1_P = 0x0, + PLL1_P = 0x1, + HSI = 0x2, + SAI1_EXTCLK = 0x3, + }; + + pub const SW = enum(u2) { + MSI = 0x0, + HSI = 0x1, + HSE = 0x2, + PLL1_R = 0x3, + }; + + pub const USART1SEL = enum(u2) { + /// PCLK clock selected + PCLK2 = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// HSI clock selected + HSI = 0x2, + HSE = 0x3, }; /// Reset and clock control pub const RCC = extern struct { - /// clock control register + /// Clock control register CR: mmio.Mmio(packed struct(u32) { - /// Internal high-speed clock enable + /// MSI clock enable + MSION: u1, + /// MSI clock ready flag + MSIRDY: u1, + /// MSI clock PLL enable + MSIPLLEN: u1, + reserved4: u1, + /// MSI clock ranges + MSIRANGE: packed union { + raw: u4, + value: MSIRANGE, + }, + /// HSI clock enabled HSION: u1, - /// High Speed Internal clock enable in Stop mode + /// HSI always enable for peripheral kernels HSIKERON: u1, /// HSI clock ready flag HSIRDY: u1, - /// HSI clock divider - HSIDIV: packed union { - raw: u2, - value: HSIDIV, - }, - /// HSI divider flag - HSIDIVF: u1, - reserved7: u1, - /// CSI clock enable - CSION: u1, - /// CSI clock ready flag - CSIRDY: u1, - /// CSI clock enable in Stop mode - CSIKERON: u1, - reserved12: u2, - /// RC48 clock enable - HSI48ON: u1, - /// RC48 clock ready flag - HSI48RDY: u1, - /// D1 domain clocks ready flag - D1CKRDY: u1, - /// D2 domain clocks ready flag - D2CKRDY: u1, - /// HSE clock enable + /// HSI automatic start from Stop + HSIASFS: u1, + /// HSI kernel clock ready flag for peripherals requests + HSIKERDY: u1, + reserved16: u3, + /// HSE clock enabled HSEON: u1, /// HSE clock ready flag HSERDY: u1, - /// HSE clock bypass + /// HSE crystal oscillator bypass HSEBYP: u1, - /// HSE Clock Security System enable - HSECSSON: u1, - reserved24: u4, - /// PLL1 enable + /// HSE Clock security system enable + CSSON: u1, + /// HSE sysclk and PLL M divider prescaler + HSEPRE: packed union { + raw: u1, + value: HSEPRE, + }, + reserved24: u3, + /// Main PLL enable PLLON: u1, - /// PLL1 clock ready flag + /// Main PLL clock ready flag PLLRDY: u1, - padding: u6, + /// SAI1 PLL enable + PLLSAI1ON: u1, + /// SAI1 PLL clock ready flag + PLLSAI1RDY: u1, + padding: u4, }), - /// RCC HSI configuration register - HSICFGR: mmio.Mmio(packed struct(u32) { + /// Internal clock sources calibration register + ICSCR: mmio.Mmio(packed struct(u32) { + /// MSI clock calibration + MSICAL: u8, + /// MSI clock trimming + MSITRIM: u8, /// HSI clock calibration - HSICAL: u12, - reserved24: u12, + HSICAL: u8, /// HSI clock trimming HSITRIM: u7, padding: u1, }), - /// RCC Clock Recovery RC Register - CRRCR: mmio.Mmio(packed struct(u32) { - /// Internal RC 48 MHz clock calibration - HSI48CAL: u10, - padding: u22, - }), - /// RCC CSI configuration register - CSICFGR: mmio.Mmio(packed struct(u32) { - /// CSI clock calibration - CSICAL: u9, - reserved24: u15, - /// CSI clock trimming - CSITRIM: u6, - padding: u2, - }), - /// RCC Clock Configuration Register + /// Clock configuration register CFGR: mmio.Mmio(packed struct(u32) { /// System clock switch - SW: packed union { - raw: u3, - value: SW, - }, - /// System clock switch status - SWS: packed union { - raw: u3, - value: SW, - }, - /// System clock selection after a wake up from system Stop - STOPWUCK: packed union { - raw: u1, - value: STOPWUCK, - }, - /// Kernel clock selection after a wake up from system Stop - STOPKERWUCK: packed union { - raw: u1, - value: STOPWUCK, - }, - /// HSE division factor for RTC clock - RTCPRE: u6, - /// High Resolution Timer clock prescaler selection - HRTIMSEL: packed union { - raw: u1, - value: HRTIMSEL, - }, - /// Timers clocks prescaler selection - TIMPRE: packed union { - raw: u1, - value: TIMPRE, - }, - reserved18: u2, - /// MCO1 prescaler - MCO1PRE: packed union { - raw: u4, - value: MCOPRE, - }, - /// Micro-controller clock output 1 - MCO1SEL: packed union { - raw: u3, - value: MCO1SEL, - }, - /// MCO2 prescaler - MCO2PRE: packed union { - raw: u4, - value: MCOPRE, - }, - /// Micro-controller clock output 2 - MCO2SEL: packed union { - raw: u3, - value: MCO2SEL, - }, - }), - reserved24: [4]u8, - /// RCC Domain 1 Clock Configuration Register - D1CFGR: mmio.Mmio(packed struct(u32) { - /// D1 domain AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// D1 domain APB3 prescaler - D1PPRE: packed union { - raw: u3, - value: PPRE, - }, - reserved8: u1, - /// D1 domain Core prescaler - D1CPRE: packed union { - raw: u4, - value: HPRE, - }, - padding: u20, - }), - /// RCC Domain 2 Clock Configuration Register - D2CFGR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// D2 domain APB1 prescaler - D2PPRE1: packed union { - raw: u3, - value: PPRE, - }, - reserved8: u1, - /// D2 domain APB2 prescaler - D2PPRE2: packed union { - raw: u3, - value: PPRE, - }, - padding: u21, - }), - /// RCC Domain 3 Clock Configuration Register - D3CFGR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// D3 domain APB4 prescaler - D3PPRE: packed union { - raw: u3, - value: PPRE, - }, - padding: u25, - }), - reserved40: [4]u8, - /// RCC PLLs Clock Source Selection Register - PLLCKSELR: mmio.Mmio(packed struct(u32) { - /// DIVMx and PLLs clock source selection - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - reserved4: u2, - /// Prescaler for PLLx - DIVM: packed union { - raw: u6, - value: PLLM, - }, - padding: u22, - }), - /// RCC PLLs Configuration Register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// PLL1 fractional latch enable - PLLFRACEN: u1, - /// PLL1 VCO selection - PLLVCOSEL: packed union { - raw: u1, - value: PLLVCOSEL, - }, - /// PLL1 input frequency range - PLLRGE: packed union { - raw: u2, - value: PLLRGE, - }, - reserved16: u12, - /// PLL1 DIVP divider output enable - DIVPEN: u1, - /// PLL1 DIVQ divider output enable - DIVQEN: u1, - /// PLL1 DIVR divider output enable - DIVREN: u1, - padding: u13, - }), - /// RCC PLL1 Dividers Configuration Register - PLLDIVR: mmio.Mmio(packed struct(u32) { - /// Multiplication factor for PLL1 VCO - PLLN: packed union { - raw: u9, - value: PLLN, - }, - /// PLL DIVP division factor - PLLP: packed union { - raw: u7, - value: PLLDIV, - }, - /// PLL DIVQ division factor - PLLQ: packed union { - raw: u7, - value: PLLDIV, - }, - reserved24: u1, - /// PLL DIVR division factor - PLLR: packed union { - raw: u7, - value: PLLDIV, - }, - padding: u1, - }), - /// RCC PLL1 Fractional Divider Register - PLLFRACR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Fractional part of the multiplication factor for PLL VCO - FRACN: u13, - padding: u16, - }), - reserved76: [20]u8, - /// RCC Domain 1 Kernel Clock Configuration Register - D1CCIPR: mmio.Mmio(packed struct(u32) { - /// FMC kernel clock source selection - FMCSEL: packed union { - raw: u2, - value: FMCSEL, - }, - reserved4: u2, - /// QUADSPI kernel clock source selection - QUADSPISEL: packed union { - raw: u2, - value: FMCSEL, - }, - reserved16: u10, - /// SDMMC kernel clock source selection - SDMMCSEL: packed union { - raw: u1, - value: SDMMCSEL, - }, - reserved28: u11, - /// per_ck clock source selection - PERSEL: packed union { - raw: u2, - value: PERSEL, - }, - padding: u2, - }), - /// RCC Domain 2 Kernel Clock Configuration Register - D2CCIP1R: mmio.Mmio(packed struct(u32) { - /// SAI1 and DFSDM1 kernel Aclk clock source selection - SAI1SEL: packed union { - raw: u3, - value: SAISEL, - }, - reserved6: u3, - /// SAI2 and SAI3 kernel clock source selection - SAI23SEL: packed union { - raw: u3, - value: SAISEL, - }, - reserved12: u3, - /// SPI/I2S1,2 and 3 kernel clock source selection - SPI123SEL: packed union { - raw: u3, - value: SAISEL, - }, - reserved16: u1, - /// SPI4 and 5 kernel clock source selection - SPI45SEL: packed union { - raw: u3, - value: SPI45SEL, - }, - reserved20: u1, - /// SPDIFRX kernel clock source selection - SPDIFRXSEL: packed union { - raw: u2, - value: SPDIFRXSEL, - }, - reserved24: u2, - /// DFSDM1 kernel Clk clock source selection - DFSDM1SEL: packed union { - raw: u1, - value: DFSDMSEL, - }, - reserved28: u3, - /// FDCAN kernel clock source selection - FDCANSEL: packed union { - raw: u2, - value: FDCANSEL, - }, - reserved31: u1, - /// SWPMI kernel clock source selection - SWPMISEL: packed union { - raw: u1, - value: SWPMISEL, - }, - }), - /// RCC Domain 2 Kernel Clock Configuration Register - D2CCIP2R: mmio.Mmio(packed struct(u32) { - /// USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection - USART234578SEL: packed union { - raw: u3, - value: USART234578SEL, - }, - /// USART1, 6, 9 and 10 kernel clock source selection - USART16910SEL: packed union { - raw: u3, - value: USART16910SEL, - }, - reserved8: u2, - /// RNG kernel clock source selection - RNGSEL: packed union { + SW: packed union { raw: u2, - value: RNGSEL, + value: SW, }, - reserved12: u2, - /// I2C1,2,3 kernel clock source selection - I2C1235SEL: packed union { + /// System clock switch status + SWS: packed union { raw: u2, - value: I2C1235SEL, + value: SW, }, - reserved20: u6, - /// USBOTG 1 and 2 kernel clock source selection - USBSEL: packed union { - raw: u2, - value: USBSEL, + /// AHB prescaler + HPRE: packed union { + raw: u4, + value: HPRE, }, - /// HDMI-CEC kernel clock source selection - CECSEL: packed union { - raw: u2, - value: CECSEL, + /// PB low-speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, }, - reserved28: u4, - /// LPTIM1 kernel clock source selection - LPTIM1SEL: packed union { + /// APB high-speed prescaler (APB2) + PPRE2: packed union { raw: u3, - value: LPTIM1SEL, + value: PPRE, + }, + reserved15: u1, + /// Wakeup from Stop and CSS backup clock selection + STOPWUCK: u1, + /// AHB prescaler flag + HPREF: u1, + /// APB1 prescaler flag + PPRE1F: u1, + /// APB2 prescaler flag + PPRE2F: u1, + reserved24: u5, + /// Microcontroller clock output + MCOSEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// Microcontroller clock output prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, }, padding: u1, }), - /// RCC Domain 3 Kernel Clock Configuration Register - D3CCIPR: mmio.Mmio(packed struct(u32) { - /// LPUART1 kernel clock source selection - LPUART1SEL: packed union { + /// PLLSYS configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// Main PLL, PLLSAI1 and PLLSAI2 entry clock source + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + reserved4: u2, + /// Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + PLLM: packed union { raw: u3, - value: LPUARTSEL, + value: PLLM, }, - reserved8: u5, - /// I2C4 kernel clock source selection - I2C4SEL: packed union { - raw: u2, - value: I2C4SEL, + reserved8: u1, + /// Main PLLSYS multiplication factor N + PLLN: packed union { + raw: u7, + value: PLLN, }, - /// LPTIM2 kernel clock source selection - LPTIM2SEL: packed union { + reserved16: u1, + /// Main PLLSYSP output enable + PLLPEN: u1, + /// Main PLL division factor P for PPLSYSSAICLK + PLLP: packed union { + raw: u5, + value: PLLP, + }, + reserved24: u2, + /// Main PLLSYSQ output enable + PLLQEN: u1, + /// Main PLLSYS division factor Q for PLLSYSUSBCLK + PLLQ: packed union { raw: u3, - value: LPTIM2SEL, + value: PLLQ, }, - /// LPTIM3,4,5 kernel clock source selection - LPTIM345SEL: packed union { + /// Main PLLSYSR PLLCLK output enable + PLLREN: u1, + /// Main PLLSYS division factor R for SYSCLK (system clock) + PLLR: packed union { raw: u3, - value: LPTIM2SEL, + value: PLLR, }, - /// SAR ADC kernel clock source selection - ADCSEL: packed union { - raw: u2, - value: ADCSEL, + }), + /// PLLSAI1 configuration register + PLLSAI1CFGR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// SAIPLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, }, - reserved21: u3, - /// Sub-Block A of SAI4 kernel clock source selection - SAI4ASEL: packed union { - raw: u3, - value: SAIASEL, + reserved16: u1, + /// SAIPLL PLLSAI1CLK output enable + PLLPEN: u1, + /// SAI1PLL division factor P for PLLSAICLK (SAI1clock) + PLLP: packed union { + raw: u5, + value: PLLP, }, - /// Sub-Block B of SAI4 kernel clock source selection - SAI4BSEL: packed union { + reserved24: u2, + /// SAIPLL PLLSAIUSBCLK output enable + PLLQEN: u1, + /// SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock) + PLLQ: packed union { raw: u3, - value: SAIASEL, + value: PLLQ, }, - /// DFSDM2 kernel clock source selection - DFSDM2SEL: u1, - /// SPI6 kernel clock source selection - SPI6SEL: packed union { + /// PLLSAI PLLADC1CLK output enable + PLLREN: u1, + /// PLLSAI division factor R for PLLADC1CLK (ADC clock) + PLLR: packed union { raw: u3, - value: SPI6SEL, + value: PLLR, }, - padding: u1, }), - reserved96: [4]u8, - /// RCC Clock Source Interrupt Enable Register + reserved24: [4]u8, + /// Clock interrupt enable register CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready Interrupt Enable - LSIRDYIE: u1, - /// LSE ready Interrupt Enable + /// LSI1 ready interrupt enable + LSI1RDYIE: u1, + /// LSE ready interrupt enable LSERDYIE: u1, - /// HSI ready Interrupt Enable + /// MSI ready interrupt enable + MSIRDYIE: u1, + /// HSI ready interrupt enable HSIRDYIE: u1, - /// HSE ready Interrupt Enable + /// HSE ready interrupt enable HSERDYIE: u1, - /// CSI ready Interrupt Enable - CSIRDYIE: u1, - /// RC48 ready Interrupt Enable - HSI48RDYIE: u1, - /// PLL1 ready Interrupt Enable + /// PLLSYS ready interrupt enable PLLRDYIE: u1, + /// PLLSAI1 ready interrupt enable + PLLSAI1RDYIE: u1, reserved9: u2, - /// LSE clock security system Interrupt Enable + /// LSE clock security system interrupt enable LSECSSIE: u1, - padding: u22, + /// HSI48 ready interrupt enable + HSI48RDYIE: u1, + /// LSI2 ready interrupt enable + LSI2RDYIE: u1, + padding: u20, }), - /// RCC Clock Source Interrupt Flag Register + /// Clock interrupt flag register CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready Interrupt Flag - LSIRDYF: u1, - /// LSE ready Interrupt Flag + /// LSI1 ready interrupt flag + LSI1RDYF: u1, + /// LSE ready interrupt flag LSERDYF: u1, - /// HSI ready Interrupt Flag + /// MSI ready interrupt flag + MSIRDYF: u1, + /// HSI ready interrupt flag HSIRDYF: u1, - /// HSE ready Interrupt Flag + /// HSE ready interrupt flag HSERDYF: u1, - /// CSI ready Interrupt Flag - CSIRDY: u1, - /// RC48 ready Interrupt Flag - HSI48RDYF: u1, - /// PLL1 ready Interrupt Flag + /// PLL ready interrupt flag PLLRDYF: u1, - reserved9: u2, - /// LSE clock security system Interrupt Flag - LSECSSF: u1, - /// HSE clock security system Interrupt Flag + /// PLLSAI1 ready interrupt flag + PLLSAI1RDYF: u1, + reserved8: u1, + /// HSE Clock security system interrupt flag HSECSSF: u1, - padding: u21, + /// LSE Clock security system interrupt flag + LSECSSF: u1, + /// HSI48 ready interrupt flag + HSI48RDYF: u1, + /// LSI2 ready interrupt flag + LSI2RDYF: u1, + padding: u20, }), - /// RCC Clock Source Interrupt Clear Register + /// Clock interrupt clear register CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready Interrupt Clear - LSIRDYC: u1, - /// LSE ready Interrupt Clear + /// LSI1 ready interrupt clear + LSI1RDYC: u1, + /// LSE ready interrupt clear LSERDYC: u1, - /// HSI ready Interrupt Clear + /// MSI ready interrupt clear + MSIRDYC: u1, + /// HSI ready interrupt clear HSIRDYC: u1, - /// HSE ready Interrupt Clear + /// HSE ready interrupt clear HSERDYC: u1, - /// CSI ready Interrupt Clear - HSE_ready_Interrupt_Clear: u1, - /// RC48 ready Interrupt Clear - HSI48RDYC: u1, - /// PLL1 ready Interrupt Clear + /// PLL ready interrupt clear PLLRDYC: u1, - reserved9: u2, - /// LSE clock security system Interrupt Clear - LSECSSC: u1, - /// HSE clock security system Interrupt Clear - HSECSSC: u1, - padding: u21, - }), - reserved112: [4]u8, - /// RCC Backup Domain Control Register - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enabled - LSEON: u1, - /// LSE oscillator ready - LSERDY: u1, - /// LSE oscillator bypass - LSEBYP: u1, - /// LSE oscillator driving capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// LSE clock security system enable - LSECSSON: u1, - /// LSE clock security system failure detection - LSECSSD: u1, + /// PLLSAI1 ready interrupt clear + PLLSAI1RDYC: u1, reserved8: u1, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// VSwitch domain software reset - BDRST: u1, - padding: u15, - }), - /// RCC Clock Control and Status Register - CSR: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable - LSION: u1, - /// LSI oscillator ready - LSIRDY: u1, - padding: u30, + /// HSE Clock security system interrupt clear + HSECSSC: u1, + /// LSE Clock security system interrupt clear + LSECSSC: u1, + /// HSI48 ready interrupt clear + HSI48RDYC: u1, + /// LSI2 ready interrupt clear + LSI2RDYC: u1, + padding: u20, }), - reserved124: [4]u8, - /// RCC AHB3 Reset Register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - /// MDMA block reset - MDMARST: u1, - reserved4: u3, - /// DMA2D block reset - DMA2DRST: u1, - /// JPGDEC block reset - JPGDECRST: u1, - reserved12: u6, - /// FMC block reset - FMCRST: u1, - reserved14: u1, - /// QUADSPI and QUADSPI delay block reset - QUADSPIRST: u1, - reserved16: u1, - /// SDMMC1 and SDMMC1 delay block reset - SDMMC1RST: u1, - reserved19: u2, - /// OCTOSPI2 and OCTOSPI2 delay block reset - OCTOSPI2RST: u1, - reserved21: u1, - /// OCTOSPI IO manager reset - IOMNGRRST: u1, - /// OTFDEC1 reset - OTFD1RST: u1, - /// OTFDEC2 reset - OTFD2RST: u1, - reserved31: u7, - /// CPU reset - CPURST: u1, + /// Step Down converter control register + SMPSCR: mmio.Mmio(packed struct(u32) { + /// Step Down converter clock selection + SMPSSEL: u2, + reserved4: u2, + /// Step Down converter clock prescaler + SMPSDIV: u2, + reserved8: u2, + /// Step Down converter clock switch status + SMPSSWS: u2, + padding: u22, }), - /// RCC AHB1 Peripheral Reset Register + /// AHB1 peripheral reset register AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 block reset + /// DMA1 reset DMA1RST: u1, - /// DMA2 block reset + /// DMA2 reset DMA2RST: u1, - reserved5: u3, - /// ADC1&2 block reset - ADC12RST: u1, - reserved14: u8, - /// ART block reset - ARTRST: u1, - /// ETH block reset - ETHRST: u1, - reserved25: u9, - /// USB_OTG_HS block reset - USB_OTG_HSRST: u1, - reserved27: u1, - /// USB_OTG_FS block reset - USB_OTG_FSRST: u1, - padding: u4, + /// DMAMUX reset + DMAMUX1RST: u1, + reserved12: u9, + /// CRC reset + CRCRST: u1, + reserved16: u3, + /// Touch Sensing Controller reset + TSCRST: u1, + padding: u15, }), - /// RCC AHB2 Peripheral Reset Register + /// AHB2 peripheral reset register AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// DCMI block reset - DCMIRST: u1, - reserved4: u3, - /// CRYPography block reset - CRYPRST: u1, - /// Hash block reset - HASHRST: u1, - /// Random Number Generator block reset - RNGRST: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 Delay block reset - SDMMC2RST: u1, - reserved16: u6, - /// FMAC reset - FMACRST: u1, - /// CORDIC reset - CORDICRST: u1, - padding: u14, - }), - /// RCC AHB4 Peripheral Reset Register - AHB4RSTR: mmio.Mmio(packed struct(u32) { - /// GPIO block reset + /// IO port A reset GPIOARST: u1, - /// GPIO block reset + /// IO port B reset GPIOBRST: u1, - /// GPIO block reset + /// IO port C reset GPIOCRST: u1, - /// GPIO block reset + /// IO port D reset GPIODRST: u1, - /// GPIO block reset + /// IO port E reset GPIOERST: u1, - /// GPIO block reset - GPIOFRST: u1, - /// GPIO block reset - GPIOGRST: u1, - /// GPIO block reset + reserved7: u2, + /// IO port H reset GPIOHRST: u1, - /// GPIO block reset - GPIOIRST: u1, - /// GPIO block reset - GPIOJRST: u1, - /// GPIO block reset - GPIOKRST: u1, - reserved19: u8, - /// CRC block reset - CRCRST: u1, - reserved21: u1, - /// BDMA block reset - BDMARST: u1, - reserved24: u2, - /// ADC3 block reset - ADC3RST: u1, - /// HSEM block reset + reserved13: u5, + /// ADC reset + ADCRST: u1, + reserved16: u2, + /// AES1 hardware accelerator reset + AES1RST: u1, + padding: u15, + }), + /// AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// Quad SPI memory interface reset + QUADSPIRST: u1, + reserved16: u7, + /// PKA interface reset + PKARST: u1, + /// AES2 interface reset + AES2RST: u1, + /// RNG interface reset + RNGRST: u1, + /// HSEM interface reset HSEMRST: u1, + /// IPCC interface reset + IPCCRST: u1, + reserved25: u4, + /// Flash interface reset + FLASHRST: u1, padding: u6, }), - /// RCC APB3 Peripheral Reset Register - APB3RSTR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// LTDC block reset - LTDCRST: u1, - /// DSI block reset - DSIRST: u1, - padding: u27, - }), - /// RCC APB1 Peripheral Reset Register - APB1LRSTR: mmio.Mmio(packed struct(u32) { - /// TIM block reset + reserved56: [4]u8, + /// APB1 peripheral reset register 1 + APB1RSTR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer reset TIM2RST: u1, - /// TIM block reset - TIM3RST: u1, - /// TIM block reset - TIM4RST: u1, - /// TIM block reset - TIM5RST: u1, - /// TIM block reset - TIM6RST: u1, - /// TIM block reset - TIM7RST: u1, - /// TIM block reset - TIM12RST: u1, - /// TIM block reset - TIM13RST: u1, - /// TIM block reset - TIM14RST: u1, - /// TIM block reset - LPTIM1RST: u1, + reserved9: u8, + /// LCD interface reset + LCDRST: u1, reserved14: u4, - /// SPI2 block reset + /// SPI2 reset SPI2RST: u1, - /// SPI3 block reset - SPI3RST: u1, - /// SPDIFRX block reset - SPDIFRXRST: u1, - /// USART2 block reset - USART2RST: u1, - /// USART3 block reset - USART3RST: u1, - /// UART4 block reset - UART4RST: u1, - /// UART5 block reset - UART5RST: u1, - /// I2C1 block reset + reserved21: u6, + /// I2C1 reset I2C1RST: u1, - /// I2C2 block reset - I2C2RST: u1, - /// I2C3 block reset + reserved23: u1, + /// I2C3 reset I2C3RST: u1, - reserved25: u1, - /// I2C5 block reset - I2C5RST: u1, - reserved27: u1, - /// HDMI-CEC block reset - CECRST: u1, - reserved29: u1, - /// DAC1 and 2 Blocks Reset - DAC12RST: u1, - /// UART7 block reset - UART7RST: u1, - /// UART8 block reset - UART8RST: u1, - }), - /// RCC APB1 Peripheral Reset Register - APB1HRSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System reset + /// CRS reset CRSRST: u1, - /// SWPMI block reset - SWPMIRST: u1, - reserved4: u1, - /// OPAMP block reset - OPAMPRST: u1, - /// MDIOS block reset - MDIOSRST: u1, - reserved8: u2, - /// FDCAN block reset - FDCANRST: u1, - reserved24: u15, - /// TIM23 block reset - TIM23RST: u1, - /// TIM24 block reset - TIM24RST: u1, - padding: u6, + reserved26: u1, + /// USB FS reset + USBRST: u1, + reserved31: u4, + /// Low Power Timer 1 reset + LPTIM1RST: u1, }), - /// RCC APB2 Peripheral Reset Register + /// APB1 peripheral reset register 2 + APB1RSTR2: mmio.Mmio(packed struct(u32) { + /// Low-power UART 1 reset + LPUART1RST: u1, + reserved5: u4, + /// Low-power timer 2 reset + LPTIM2RST: u1, + padding: u26, + }), + /// APB2 peripheral reset register APB2RSTR: mmio.Mmio(packed struct(u32) { - /// TIM1 block reset + reserved11: u11, + /// TIM1 timer reset TIM1RST: u1, - /// TIM8 block reset - TIM8RST: u1, - reserved4: u2, - /// USART1 block reset - USART1RST: u1, - /// USART6 block reset - USART6RST: u1, - /// UART9 block reset - UART9RST: u1, - /// USART10 block reset - USART10RST: u1, - reserved12: u4, - /// SPI1 block reset + /// SPI1 reset SPI1RST: u1, - /// SPI4 block reset - SPI4RST: u1, - reserved16: u2, - /// TIM15 block reset - TIM15RST: u1, - /// TIM16 block reset + reserved14: u1, + /// USART1 reset + USART1RST: u1, + reserved17: u2, + /// TIM16 timer reset TIM16RST: u1, - /// TIM17 block reset + /// TIM17 timer reset TIM17RST: u1, - reserved20: u1, - /// SPI5 block reset - SPI5RST: u1, - reserved22: u1, - /// SAI1 block reset + reserved21: u2, + /// Serial audio interface 1 (SAI1) reset SAI1RST: u1, - /// SAI2 block reset - SAI2RST: u1, - /// SAI3 block reset - SAI3RST: u1, - reserved28: u3, - /// DFSDM1 block reset - DFSDM1RST: u1, - /// HRTIM block reset - HRTIMRST: u1, - padding: u2, + padding: u10, }), - /// RCC APB4 Peripheral Reset Register - APB4RSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG block reset - SYSCFGRST: u1, - reserved3: u1, - /// LPUART1 block reset - LPUART1RST: u1, - reserved5: u1, - /// SPI6 block reset - SPI6RST: u1, - reserved7: u1, - /// I2C4 block reset - I2C4RST: u1, - reserved9: u1, - /// LPTIM2 block reset - LPTIM2RST: u1, - /// LPTIM3 block reset - LPTIM3RST: u1, - /// LPTIM4 block reset - LPTIM4RST: u1, - /// LPTIM5 block reset - LPTIM5RST: u1, - /// DAC2 (containing one converter) reset - DAC2RST: u1, - /// COMP12 Blocks Reset - COMP12RST: u1, - /// VREF block reset - VREFRST: u1, - reserved21: u5, - /// SAI4 block reset - SAI4RST: u1, - reserved26: u4, - /// Digital temperature sensor block reset - DTSRST: u1, - padding: u5, + /// APB3 peripheral reset register + APB3RSTR: mmio.Mmio(packed struct(u32) { + /// Radio system BLE reset + RFRST: u1, + padding: u31, }), - /// Global Control Register - GCR: mmio.Mmio(packed struct(u32) { - /// WWDG1 reset scope control - WW1RSC: u1, - /// WWDG2 reset scope control - WW2RSC: u1, - /// Force allow CPU1 to boot - BOOT_C1: u1, - /// Force allow CPU2 to boot - BOOT_C2: u1, - padding: u28, + /// AHB1 peripheral clock enable register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// DMAMUX clock enable + DMAMUX1EN: u1, + reserved12: u9, + /// CPU1 CRC clock enable + CRCEN: u1, + reserved16: u3, + /// Touch Sensing Controller clock enable + TSCEN: u1, + padding: u15, }), - reserved168: [4]u8, - /// RCC D3 Autonomous mode Register - D3AMR: mmio.Mmio(packed struct(u32) { - /// BDMA and DMAMUX Autonomous mode enable - BDMAAMEN: u1, - reserved3: u2, - /// LPUART1 Autonomous mode enable - LPUART1AMEN: u1, - reserved5: u1, - /// SPI6 Autonomous mode enable - SPI6AMEN: u1, - reserved7: u1, - /// I2C4 Autonomous mode enable - I2C4AMEN: u1, - reserved9: u1, - /// LPTIM2 Autonomous mode enable - LPTIM2AMEN: u1, - /// LPTIM3 Autonomous mode enable - LPTIM3AMEN: u1, - /// LPTIM4 Autonomous mode enable - LPTIM4AMEN: u1, - /// LPTIM5 Autonomous mode enable - LPTIM5AMEN: u1, - /// DAC2 (containing one converter) Autonomous mode enable - DAC2AMEN: u1, - /// COMP12 Autonomous mode enable - COMP12AMEN: u1, - /// VREF Autonomous mode enable - VREFAMEN: u1, - /// RTC Autonomous mode enable - RTCAMEN: u1, - reserved19: u2, - /// CRC Autonomous mode enable - CRCAMEN: u1, - reserved21: u1, - /// SAI4 Autonomous mode enable - SAI4AMEN: u1, - reserved24: u2, - /// ADC3 Autonomous mode enable - ADC3AMEN: u1, + /// AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + reserved7: u2, + /// IO port H clock enable + GPIOHEN: u1, + reserved13: u5, + /// ADC clock enable + ADCEN: u1, + reserved16: u2, + /// AES1 accelerator clock enable + AES1EN: u1, + padding: u15, + }), + /// AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// QUADSPIEN + QUADSPIEN: u1, + reserved16: u7, + /// PKAEN + PKAEN: u1, + /// AES2EN + AES2EN: u1, + /// RNGEN + RNGEN: u1, + /// HSEMEN + HSEMEN: u1, + /// IPCCEN + IPCCEN: u1, + reserved25: u4, + /// FLASHEN + FLASHEN: u1, + padding: u6, + }), + reserved88: [4]u8, + /// APB1ENR1 + APB1ENR1: mmio.Mmio(packed struct(u32) { + /// CPU1 TIM2 timer clock enable + TIM2EN: u1, + reserved9: u8, + /// CPU1 LCD clock enable + LCDEN: u1, + /// CPU1 RTC APB clock enable + RTCAPBEN: u1, + /// CPU1 Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// CPU1 SPI2 clock enable + SPI2EN: u1, + reserved21: u6, + /// CPU1 I2C1 clock enable + I2C1EN: u1, + reserved23: u1, + /// CPU1 I2C3 clock enable + I2C3EN: u1, + /// CPU1 CRS clock enable + CRSEN: u1, reserved26: u1, - /// Digital temperature sensor Autonomous mode enable - DTSAMEN: u1, - reserved28: u1, - /// Backup RAM Autonomous mode enable - BKPSRAMAMEN: u1, - /// SRAM4 Autonomous mode enable - SRAM4AMEN: u1, - padding: u2, + /// CPU1 USB clock enable + USBEN: u1, + reserved31: u4, + /// CPU1 Low power timer 1 clock enable + LPTIM1EN: u1, + }), + /// APB1 peripheral clock enable register 2 + APB1ENR2: mmio.Mmio(packed struct(u32) { + /// CPU1 Low power UART 1 clock enable + LPUART1EN: u1, + reserved5: u4, + /// CPU1 LPTIM2EN + LPTIM2EN: u1, + padding: u26, + }), + /// APB2ENR + APB2ENR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// CPU1 TIM1 timer clock enable + TIM1EN: u1, + /// CPU1 SPI1 clock enable + SPI1EN: u1, + reserved14: u1, + /// CPU1 USART1clock enable + USART1EN: u1, + reserved17: u2, + /// CPU1 TIM16 timer clock enable + TIM16EN: u1, + /// CPU1 TIM17 timer clock enable + TIM17EN: u1, + reserved21: u2, + /// CPU1 SAI1 clock enable + SAI1EN: u1, + padding: u10, + }), + reserved104: [4]u8, + /// AHB1 peripheral clocks enable in Sleep and Stop modes register + AHB1SMENR: mmio.Mmio(packed struct(u32) { + /// CPU1 DMA1 clocks enable during Sleep and Stop modes + DMA1SMEN: u1, + /// CPU1 DMA2 clocks enable during Sleep and Stop modes + DMA2SMEN: u1, + /// CPU1 DMAMUX clocks enable during Sleep and Stop modes + DMAMUX1SMEN: u1, + reserved9: u6, + /// CPU1 SRAM1 interface clocks enable during Sleep and Stop modes + SRAM1SMEN: u1, + reserved12: u2, + /// CPU1 CRCSMEN + CRCSMEN: u1, + reserved16: u3, + /// CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes + TSCSMEN: u1, + padding: u15, + }), + /// AHB2 peripheral clocks enable in Sleep and Stop modes register + AHB2SMENR: mmio.Mmio(packed struct(u32) { + /// CPU1 IO port A clocks enable during Sleep and Stop modes + GPIOASMEN: u1, + /// CPU1 IO port B clocks enable during Sleep and Stop modes + GPIOBSMEN: u1, + /// CPU1 IO port C clocks enable during Sleep and Stop modes + GPIOCSMEN: u1, + /// CPU1 IO port D clocks enable during Sleep and Stop modes + GPIODSMEN: u1, + /// CPU1 IO port E clocks enable during Sleep and Stop modes + GPIOESMEN: u1, + reserved7: u2, + /// CPU1 IO port H clocks enable during Sleep and Stop modes + GPIOHSMEN: u1, + reserved13: u5, + /// CPU1 ADC clocks enable during Sleep and Stop modes + ADCFSSMEN: u1, + reserved16: u2, + /// CPU1 AES1 accelerator clocks enable during Sleep and Stop modes + AES1SMEN: u1, + padding: u15, + }), + /// AHB3 peripheral clocks enable in Sleep and Stop modes register + AHB3SMENR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// QUADSPISMEN + QUADSPISMEN: u1, + reserved16: u7, + /// PKA accelerator clocks enable during CPU1 sleep mode + PKASMEN: u1, + /// AES2 accelerator clocks enable during CPU1 sleep mode + AES2SMEN: u1, + /// True RNG clocks enable during CPU1 sleep mode + RNGSMEN: u1, + reserved24: u5, + /// SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode + SRAM2SMEN: u1, + /// Flash interface clocks enable during CPU1 sleep mode + FLASHSMEN: u1, + padding: u6, + }), + reserved120: [4]u8, + /// APB1SMENR1 + APB1SMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clocks enable during CPU1 Sleep mode + TIM2SMEN: u1, + reserved9: u8, + /// LCD clocks enable during CPU1 Sleep mode + LCDSMEN: u1, + /// RTC APB clocks enable during CPU1 Sleep mode + RTCAPBSMEN: u1, + /// Window watchdog clocks enable during CPU1 Sleep mode + WWDGSMEN: u1, + reserved14: u2, + /// SPI2 clocks enable during CPU1 Sleep mode + SPI2SMEN: u1, + reserved21: u6, + /// I2C1 clocks enable during CPU1 Sleep mode + I2C1SMEN: u1, + reserved23: u1, + /// I2C3 clocks enable during CPU1 Sleep mode + I2C3SMEN: u1, + /// CRS clocks enable during CPU1 Sleep mode + CRSMEN: u1, + reserved26: u1, + /// USB FS clocks enable during CPU1 Sleep mode + USBSMEN: u1, + reserved31: u4, + /// Low power timer 1 clocks enable during CPU1 Sleep mode + LPTIM1SMEN: u1, + }), + /// APB1 peripheral clocks enable in Sleep and Stop modes register 2 + APB1SMENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clocks enable during CPU1 Sleep mode + LPUART1SMEN: u1, + reserved5: u4, + /// Low power timer 2 clocks enable during CPU1 Sleep mode + LPTIM2SMEN: u1, + padding: u26, + }), + /// APB2SMENR + APB2SMENR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 timer clocks enable during CPU1 Sleep mode + TIM1SMEN: u1, + /// SPI1 clocks enable during CPU1 Sleep mode + SPI1SMEN: u1, + reserved14: u1, + /// USART1clocks enable during CPU1 Sleep mode + USART1SMEN: u1, + reserved17: u2, + /// TIM16 timer clocks enable during CPU1 Sleep mode + TIM16SMEN: u1, + /// TIM17 timer clocks enable during CPU1 Sleep mode + TIM17SMEN: u1, + reserved21: u2, + /// SAI1 clocks enable during CPU1 Sleep mode + SAI1SMEN: u1, + padding: u10, + }), + reserved136: [4]u8, + /// CCIPR + CCIPR: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SEL: packed union { + raw: u2, + value: USART1SEL, + }, + reserved10: u8, + /// LPUART1 clock source selection + LPUART1SEL: packed union { + raw: u2, + value: LPUART1SEL, + }, + /// I2C1 clock source selection + I2C1SEL: packed union { + raw: u2, + value: I2C1SEL, + }, + reserved16: u2, + /// I2C3 clock source selection + I2C3SEL: packed union { + raw: u2, + value: I2C3SEL, + }, + /// Low power timer 1 clock source selection + LPTIM1SEL: packed union { + raw: u2, + value: LPTIM1SEL, + }, + /// Low power timer 2 clock source selection + LPTIM2SEL: packed union { + raw: u2, + value: LPTIM2SEL, + }, + /// SAI1 clock source selection + SAI1SEL: packed union { + raw: u2, + value: SAI1SEL, + }, + reserved26: u2, + /// 48 MHz clock source selection + CLK48SEL: packed union { + raw: u2, + value: CLK48SEL, + }, + /// ADCs clock source selection + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, + /// RNG clock source selection + RNGSEL: packed union { + raw: u2, + value: RNGSEL, + }, + }), + reserved144: [4]u8, + /// BDCR + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enable + LSEON: u1, + /// LSE oscillator ready + LSERDY: u1, + /// LSE oscillator bypass + LSEBYP: u1, + /// SE oscillator drive capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// LSECSSON + LSECSSON: u1, + /// CSS on LSE failure detection + LSECSSD_: u1, + reserved8: u1, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + reserved24: u7, + /// Low speed clock output enable + LSCOEN: u1, + /// Low speed clock output selection + LSCOSEL: u2, + padding: u5, }), - reserved208: [36]u8, - /// RCC Reset Status Register - RSR: mmio.Mmio(packed struct(u32) { - reserved16: u16, + /// CSR + CSR: mmio.Mmio(packed struct(u32) { + /// LSI1 oscillator enabled + LSI1ON: u1, + /// LSI1 oscillator ready + LSI1RDY: u1, + /// LSI2 oscillator enabled + LSI2ON: u1, + /// LSI2 oscillator ready + LSI2RDY: u1, + /// LSI2 oscillator trimming enable + LSI2TRIMEN: u1, + /// LSI2 oscillator trim OK + LSI2TRIMOK: u1, + reserved8: u2, + /// LSI2 oscillator bias configuration + LSI2BW: u4, + reserved14: u2, + /// RF system wakeup clock source selection + RFWKPSEL: u2, + /// Radio system BLE and 802.15.4 reset status + RFRSTS: u1, + reserved23: u6, /// Remove reset flag RMVF: u1, - /// CPU reset flag - CPURSTF: u1, - reserved19: u1, - /// D1 domain power switch reset flag - D1RSTF: u1, - /// D2 domain power switch reset flag - D2RSTF: u1, - /// BOR reset flag - BORRSTF: u1, - /// Pin reset flag (NRST) + reserved25: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// Pin reset flag PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// System reset from CPU reset flag + /// BOR flag + BORRSTF: u1, + /// Software reset flag SFTRSTF: u1, - reserved26: u1, - /// Independent Watchdog reset flag - IWDG1RSTF: u1, - reserved28: u1, - /// Window Watchdog reset flag - WWDG1RSTF: u1, - reserved30: u1, - /// Reset due to illegal D1 DStandby or CPU CStop flag + /// Independent window watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag LPWRRSTF: u1, - padding: u1, }), - /// RCC AHB3 Clock Register - AHB3ENR: mmio.Mmio(packed struct(u32) { - /// MDMA Peripheral Clock Enable - MDMAEN: u1, - reserved4: u3, - /// DMA2D Peripheral Clock Enable - DMA2DEN: u1, - /// JPGDEC Peripheral Clock Enable - JPGDECEN: u1, - reserved12: u6, - /// FMC Peripheral Clocks Enable - FMCEN: u1, - reserved14: u1, - /// QUADSPI and QUADSPI Delay Clock Enable - QUADSPIEN: u1, - reserved16: u1, - /// SDMMC1 and SDMMC1 Delay Clock Enable - SDMMC1EN: u1, - reserved19: u2, - /// OCTOSPI2 and OCTOSPI2 delay block enable - OCTOSPI2EN: u1, - reserved21: u1, - /// OCTOSPI IO manager enable - IOMNGREN: u1, - /// OTFDEC1 enable - OTFD1EN: u1, - /// OTFDEC2 enable - OTFD2EN: u1, - reserved28: u4, - /// D1 DTCM1 block enable - DTCM1EN: u1, - /// D1 DTCM2 block enable - DTCM2EN: u1, - /// D1 ITCM block enable - ITCM1EN: u1, - /// AXISRAM block enable - AXISRAMEN: u1, + /// Clock recovery RC register + CRRCR: mmio.Mmio(packed struct(u32) { + /// HSI48 oscillator enabled + HSI48ON: u1, + /// HSI48 clock ready + HSI48RDY: u1, + reserved7: u5, + /// HSI48 clock calibration + HSI48CAL: u9, + padding: u16, }), - /// RCC AHB1 Clock Register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// DMA1 Clock Enable + /// Clock HSE register + HSECR: mmio.Mmio(packed struct(u32) { + /// Register lock system + UNLOCKED: u1, + reserved3: u2, + /// HSE Sense amplifier threshold + HSES: u1, + /// HSE current control + HSEGMC: u3, + reserved8: u1, + /// HSE capacitor tuning + HSETUNE: u6, + padding: u18, + }), + reserved264: [104]u8, + /// Extended clock recovery register + EXTCFGR: mmio.Mmio(packed struct(u32) { + /// Shared AHB prescaler + SHDHPRE: packed union { + raw: u4, + value: HPRE, + }, + /// CPU2 AHB prescaler + C2HPRE: packed union { + raw: u4, + value: HPRE, + }, + reserved16: u8, + /// Shared AHB prescaler flag + SHDHPREF: u1, + /// CPU2 AHB prescaler flag + C2HPREF: u1, + reserved20: u2, + /// RF clock source selected + RFCSS: u1, + padding: u11, + }), + reserved328: [60]u8, + /// CPU2 AHB1 peripheral clock enable register + C2AHB1ENR: mmio.Mmio(packed struct(u32) { + /// CPU2 DMA1 clock enable DMA1EN: u1, - /// DMA2 Clock Enable + /// CPU2 DMA2 clock enable DMA2EN: u1, - reserved5: u3, - /// ADC1/2 Peripheral Clocks Enable - ADC12EN: u1, - reserved14: u8, - /// ART Clock Enable - ARTEN: u1, - /// Ethernet MAC bus interface Clock Enable - ETHEN: u1, - /// Ethernet Transmission Clock Enable - ETHTXEN: u1, - /// Ethernet Reception Clock Enable - ETHRXEN: u1, - reserved25: u7, - /// USB_OTG_HS Peripheral Clocks Enable - USB_OTG_HSEN: u1, - /// USB_OTG_HS ULPI clock enable - USB_OTG_HS_ULPIEN: u1, - /// USB_OTG_FS Peripheral Clocks Enable - USB_OTG_FSEN: u1, - /// USB_OTG_FS ULPI clock enable - USB_OTG_FS_ULPIEN: u1, - padding: u3, - }), - /// RCC AHB2 Clock Register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// DCMI peripheral clock - DCMIEN: u1, - reserved4: u3, - /// CRYP peripheral clock enable - CRYPEN: u1, - /// HASH peripheral clock enable - HASHEN: u1, - /// RNG peripheral clocks enable - RNGEN: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 delay clock enable - SDMMC2EN: u1, - reserved16: u6, - /// FMAC enable - FMACEN: u1, - /// CORDIC enable - CORDICEN: u1, - reserved29: u11, - /// SRAM1 block enable + /// CPU2 DMAMUX clock enable + DMAMUX1EN: u1, + reserved9: u6, + /// CPU2 SRAM1 clock enable SRAM1EN: u1, - /// SRAM2 block enable - SRAM2EN: u1, - /// SRAM3 block enable - SRAM3EN: u1, + reserved12: u2, + /// CPU2 CRC clock enable + CRCEN: u1, + reserved16: u3, + /// CPU2 Touch Sensing Controller clock enable + TSCEN: u1, + padding: u15, }), - /// RCC AHB4 Clock Register - AHB4ENR: mmio.Mmio(packed struct(u32) { - /// 0GPIO peripheral clock enable + /// CPU2 AHB2 peripheral clock enable register + C2AHB2ENR: mmio.Mmio(packed struct(u32) { + /// CPU2 IO port A clock enable GPIOAEN: u1, - /// 0GPIO peripheral clock enable + /// CPU2 IO port B clock enable GPIOBEN: u1, - /// 0GPIO peripheral clock enable + /// CPU2 IO port C clock enable GPIOCEN: u1, - /// 0GPIO peripheral clock enable + /// CPU2 IO port D clock enable GPIODEN: u1, - /// 0GPIO peripheral clock enable + /// CPU2 IO port E clock enable GPIOEEN: u1, - /// 0GPIO peripheral clock enable - GPIOFEN: u1, - /// 0GPIO peripheral clock enable - GPIOGEN: u1, - /// 0GPIO peripheral clock enable + reserved7: u2, + /// CPU2 IO port H clock enable GPIOHEN: u1, - /// 0GPIO peripheral clock enable - GPIOIEN: u1, - /// 0GPIO peripheral clock enable - GPIOJEN: u1, - /// 0GPIO peripheral clock enable - GPIOKEN: u1, - reserved19: u8, - /// CRC peripheral clock enable - CRCEN: u1, - reserved21: u1, - /// BDMA and DMAMUX2 Clock Enable - BDMAEN: u1, - reserved24: u2, - /// ADC3 Peripheral Clocks Enable - ADC3EN: u1, - /// HSEM peripheral clock enable - HSEMEN: u1, - reserved28: u2, - /// Backup RAM Clock Enable - BKPSRAMEN: u1, - padding: u3, + reserved13: u5, + /// CPU2 ADC clock enable + ADCEN: u1, + reserved16: u2, + /// CPU2 AES1 accelerator clock enable + AES1EN: u1, + padding: u15, }), - /// RCC APB3 Clock Register - APB3ENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// LTDC peripheral clock enable - LTDCEN: u1, - /// DSI Peripheral clocks enable - DSIEN: u1, - reserved6: u1, - /// WWDG1 Clock Enable - WWDG1EN: u1, - padding: u25, + /// CPU2 AHB3 peripheral clock enable register + C2AHB3ENR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// CPU2 PKAEN + PKAEN: u1, + /// CPU2 AES2EN + AES2EN: u1, + /// CPU2 RNGEN + RNGEN: u1, + /// CPU2 HSEMEN + HSEMEN: u1, + /// CPU2 IPCCEN + IPCCEN: u1, + reserved25: u4, + /// CPU2 FLASHEN + FLASHEN: u1, + padding: u6, }), - /// RCC APB1 Clock Register - APB1LENR: mmio.Mmio(packed struct(u32) { - /// TIM peripheral clock enable + reserved344: [4]u8, + /// CPU2 APB1ENR1 + C2APB1ENR1: mmio.Mmio(packed struct(u32) { + /// CPU2 TIM2 timer clock enable TIM2EN: u1, - /// TIM peripheral clock enable - TIM3EN: u1, - /// TIM peripheral clock enable - TIM4EN: u1, - /// TIM peripheral clock enable - TIM5EN: u1, - /// TIM peripheral clock enable - TIM6EN: u1, - /// TIM peripheral clock enable - TIM7EN: u1, - /// TIM peripheral clock enable - TIM12EN: u1, - /// TIM peripheral clock enable - TIM13EN: u1, - /// TIM peripheral clock enable - TIM14EN: u1, - /// LPTIM1 Peripheral Clocks Enable - LPTIM1EN: u1, - reserved11: u1, - /// WWDG2 peripheral clock enable - WWDG2EN: u1, - reserved14: u2, - /// SPI2 Peripheral Clocks Enable + reserved9: u8, + /// CPU2 LCD clock enable + LCDEN: u1, + /// CPU2 RTC APB clock enable + RTCAPBEN: u1, + reserved14: u3, + /// CPU2 SPI2 clock enable SPI2EN: u1, - /// SPI3 Peripheral Clocks Enable - SPI3EN: u1, - /// SPDIFRX Peripheral Clocks Enable - SPDIFRXEN: u1, - /// USART2 Peripheral Clocks Enable - USART2EN: u1, - /// USART3 Peripheral Clocks Enable - USART3EN: u1, - /// UART4 Peripheral Clocks Enable - UART4EN: u1, - /// UART5 Peripheral Clocks Enable - UART5EN: u1, - /// I2C1 Peripheral Clocks Enable + reserved21: u6, + /// CPU2 I2C1 clock enable I2C1EN: u1, - /// I2C2 Peripheral Clocks Enable - I2C2EN: u1, - /// I2C3 Peripheral Clocks Enable + reserved23: u1, + /// CPU2 I2C3 clock enable I2C3EN: u1, - reserved25: u1, - /// I2C5 Peripheral Clocks Enable - I2C5EN: u1, - reserved27: u1, - /// HDMI-CEC peripheral clock enable - CECEN: u1, - reserved29: u1, - /// DAC1&2 peripheral clock enable - DAC12EN: u1, - /// UART7 Peripheral Clocks Enable - UART7EN: u1, - /// UART8 Peripheral Clocks Enable - UART8EN: u1, - }), - /// RCC APB1 Clock Register - APB1HENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System peripheral clock enable + /// CPU2 CRS clock enable CRSEN: u1, - /// SWPMI Peripheral Clocks Enable - SWPMIEN: u1, - reserved4: u1, - /// OPAMP peripheral clock enable - OPAMPEN: u1, - /// MDIOS peripheral clock enable - MDIOSEN: u1, - reserved8: u2, - /// FDCAN Peripheral Clocks Enable - FDCANEN: u1, - reserved24: u15, - /// TIM23 block enable - TIM23EN: u1, - /// TIM24 block enable - TIM24EN: u1, - padding: u6, + reserved26: u1, + /// CPU2 USB clock enable + USBEN: u1, + reserved31: u4, + /// CPU2 Low power timer 1 clock enable + LPTIM1EN: u1, }), - /// RCC APB2 Clock Register - APB2ENR: mmio.Mmio(packed struct(u32) { - /// TIM1 peripheral clock enable + /// CPU2 APB1 peripheral clock enable register 2 + C2APB1ENR2: mmio.Mmio(packed struct(u32) { + /// CPU2 Low power UART 1 clock enable + LPUART1EN: u1, + reserved5: u4, + /// CPU2 LPTIM2EN + LPTIM2EN: u1, + padding: u26, + }), + /// CPU2 APB2ENR + C2APB2ENR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// CPU2 TIM1 timer clock enable TIM1EN: u1, - /// TIM8 peripheral clock enable - TIM8EN: u1, - reserved4: u2, - /// USART1 Peripheral Clocks Enable - USART1EN: u1, - /// USART6 Peripheral Clocks Enable - USART6EN: u1, - /// UART9 Peripheral Clocks Enable - UART9EN: u1, - /// USART10 Peripheral Clocks Enable - USART10EN: u1, - reserved12: u4, - /// SPI1 Peripheral Clocks Enable + /// CPU2 SPI1 clock enable SPI1EN: u1, - /// SPI4 Peripheral Clocks Enable - SPI4EN: u1, - reserved16: u2, - /// TIM15 peripheral clock enable - TIM15EN: u1, - /// TIM16 peripheral clock enable + reserved14: u1, + /// CPU2 USART1clock enable + USART1EN: u1, + reserved17: u2, + /// CPU2 TIM16 timer clock enable TIM16EN: u1, - /// TIM17 peripheral clock enable + /// CPU2 TIM17 timer clock enable TIM17EN: u1, - reserved20: u1, - /// SPI5 Peripheral Clocks Enable - SPI5EN: u1, - reserved22: u1, - /// SAI1 Peripheral Clocks Enable + reserved21: u2, + /// CPU2 SAI1 clock enable SAI1EN: u1, - /// SAI2 Peripheral Clocks Enable - SAI2EN: u1, - /// SAI3 Peripheral Clocks Enable - SAI3EN: u1, - reserved28: u3, - /// DFSDM1 Peripheral Clocks Enable - DFSDM1EN: u1, - /// HRTIM peripheral clock enable - HRTIMEN: u1, - padding: u2, + padding: u10, }), - /// RCC APB4 Clock Register - APB4ENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG peripheral clock enable - SYSCFGEN: u1, - reserved3: u1, - /// LPUART1 Peripheral Clocks Enable - LPUART1EN: u1, - reserved5: u1, - /// SPI6 Peripheral Clocks Enable - SPI6EN: u1, - reserved7: u1, - /// I2C4 Peripheral Clocks Enable - I2C4EN: u1, - reserved9: u1, - /// LPTIM2 Peripheral Clocks Enable - LPTIM2EN: u1, - /// LPTIM3 Peripheral Clocks Enable - LPTIM3EN: u1, - /// LPTIM4 Peripheral Clocks Enable - LPTIM4EN: u1, - /// LPTIM5 Peripheral Clocks Enable - LPTIM5EN: u1, - /// DAC2 (containing one converter) peripheral clock enable - DAC2EN: u1, - /// COMP1/2 peripheral clock enable - COMP12EN: u1, - /// VREF peripheral clock enable - VREFEN: u1, - /// RTC APB Clock Enable - RTCAPBEN: u1, - reserved21: u4, - /// SAI4 Peripheral Clocks Enable - SAI4EN: u1, - reserved26: u4, - /// Digital temperature sensor block enable - DTSEN: u1, - padding: u5, + /// CPU2 APB3ENR + C2APB3ENR: mmio.Mmio(packed struct(u32) { + /// CPU2 BLE interface clock enable + BLEEN: u1, + /// CPU2 802.15.4 interface clock enable + EN802: u1, + padding: u30, + }), + /// CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register + C2AHB1SMENR: mmio.Mmio(packed struct(u32) { + /// CPU2 DMA1 clocks enable during Sleep and Stop modes + DMA1SMEN: u1, + /// CPU2 DMA2 clocks enable during Sleep and Stop modes + DMA2SMEN: u1, + /// CPU2 DMAMUX clocks enable during Sleep and Stop modes + DMAMUX1SMEN: u1, + reserved9: u6, + /// SRAM1 interface clock enable during CPU1 CSleep mode + SRAM1SMEN: u1, + reserved12: u2, + /// CPU2 CRCSMEN + CRCSMEN: u1, + reserved16: u3, + /// CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes + TSCSMEN: u1, + padding: u15, + }), + /// CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register + C2AHB2SMENR: mmio.Mmio(packed struct(u32) { + /// CPU2 IO port A clocks enable during Sleep and Stop modes + GPIOASMEN: u1, + /// CPU2 IO port B clocks enable during Sleep and Stop modes + GPIOBSMEN: u1, + /// CPU2 IO port C clocks enable during Sleep and Stop modes + GPIOCSMEN: u1, + /// CPU2 IO port D clocks enable during Sleep and Stop modes + GPIODSMEN: u1, + /// CPU2 IO port E clocks enable during Sleep and Stop modes + GPIOESMEN: u1, + reserved7: u2, + /// CPU2 IO port H clocks enable during Sleep and Stop modes + GPIOHSMEN: u1, + reserved13: u5, + /// CPU2 ADC clocks enable during Sleep and Stop modes + ADCFSSMEN: u1, + reserved16: u2, + /// CPU2 AES1 accelerator clocks enable during Sleep and Stop modes + AES1SMEN: u1, + padding: u15, + }), + /// CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register + C2AHB3SMENR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// PKA accelerator clocks enable during CPU2 sleep modes + PKASMEN: u1, + /// AES2 accelerator clocks enable during CPU2 sleep modes + AES2SMEN: u1, + /// True RNG clocks enable during CPU2 sleep modes + RNGSMEN: u1, + reserved24: u5, + /// SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes + SRAM2SMEN: u1, + /// Flash interface clocks enable during CPU2 sleep modes + FLASHSMEN: u1, + padding: u6, + }), + reserved376: [4]u8, + /// CPU2 APB1SMENR1 + C2APB1SMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clocks enable during CPU2 Sleep mode + TIM2SMEN: u1, + reserved9: u8, + /// LCD clocks enable during CPU2 Sleep mode + LCDSMEN: u1, + /// RTC APB clocks enable during CPU2 Sleep mode + RTCAPBSMEN: u1, + reserved14: u3, + /// SPI2 clocks enable during CPU2 Sleep mode + SPI2SMEN: u1, + reserved21: u6, + /// I2C1 clocks enable during CPU2 Sleep mode + I2C1SMEN: u1, + reserved23: u1, + /// I2C3 clocks enable during CPU2 Sleep mode + I2C3SMEN: u1, + /// CRS clocks enable during CPU2 Sleep mode + CRSMEN: u1, + reserved26: u1, + /// USB FS clocks enable during CPU2 Sleep mode + USBSMEN: u1, + reserved31: u4, + /// Low power timer 1 clocks enable during CPU2 Sleep mode + LPTIM1SMEN: u1, + }), + /// CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 + C2APB1SMENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clocks enable during CPU2 Sleep mode + LPUART1SMEN: u1, + reserved5: u4, + /// Low power timer 2 clocks enable during CPU2 Sleep mode + LPTIM2SMEN: u1, + padding: u26, + }), + /// CPU2 APB2SMENR + C2APB2SMENR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 timer clocks enable during CPU2 Sleep mode + TIM1SMEN: u1, + /// SPI1 clocks enable during CPU2 Sleep mode + SPI1SMEN: u1, + reserved14: u1, + /// USART1clocks enable during CPU2 Sleep mode + USART1SMEN: u1, + reserved17: u2, + /// TIM16 timer clocks enable during CPU2 Sleep mode + TIM16SMEN: u1, + /// TIM17 timer clocks enable during CPU2 Sleep mode + TIM17SMEN: u1, + reserved21: u2, + /// SAI1 clocks enable during CPU2 Sleep mode + SAI1SMEN: u1, + padding: u10, + }), + /// CPU2 APB3SMENR + C2APB3SMENR: mmio.Mmio(packed struct(u32) { + /// BLE interface clocks enable during CPU2 Sleep mode + BLESMEN: u1, + /// 802.15.4 interface clocks enable during CPU2 Sleep modes + SMEN802: u1, + padding: u30, + }), + }; + }; + + pub const rcc_wba = struct { + pub const ADCSEL = enum(u3) { + /// hclk4 clock selected + HCLK4 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// pll1pclk selected + PLL1_P = 0x2, + /// HSE clock selected + HSE = 0x3, + /// HSI clock selected + HSI = 0x4, + _, + }; + + pub const HDIV5 = enum(u1) { + /// hclk5 = SYSCLK not divided + Div1 = 0x0, + /// hclk5 = SYSCLK divided by 2 + Div2 = 0x1, + }; + + pub const HPRE = enum(u3) { + /// DCLK not divided + Div1 = 0x0, + /// hclk = SYSCLK divided by 2 + Div2 = 0x4, + /// hclk = SYSCLK divided by 4 + Div4 = 0x5, + /// hclk = SYSCLK divided by 8 + Div8 = 0x6, + /// hclk = SYSCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const HPRE5 = enum(u3) { + /// DCLK not divided + Div1 = 0x0, + /// hclk5 = SYSCLK divided by 2 + Div2 = 0x4, + /// hclk5 = SYSCLK divided by 3 + Div3 = 0x5, + /// hclk5 = SYSCLK divided by 4 + Div4 = 0x6, + /// hclk5 = SYSCLK divided by 6 + Div6 = 0x7, + _, + }; + + pub const HSEPRE = enum(u1) { + /// HSE not divided, SYSCLK = HSE + Div1 = 0x0, + /// HSE divided, SYSCLK = HSE/2 + Div2 = 0x1, + }; + + pub const I2C1SEL = enum(u2) { + /// pclk1 selected + PCLK1 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + _, + }; + + pub const I2C3SEL = enum(u2) { + /// pclk7 selected + PCLK7 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + _, + }; + + pub const LPTIM1SEL = enum(u2) { + /// pclk7 selected. + PCLK7 = 0x0, + /// LSI selected + LSI = 0x1, + /// HSI selected + HSI = 0x2, + /// LSE selected + LSE = 0x3, + }; + + pub const LPTIM2SEL = enum(u2) { + /// pclk7 selected. + PCLK1 = 0x0, + /// LSI selected + LSI = 0x1, + /// HSI selected + HSI = 0x2, + /// LSE selected + LSE = 0x3, + }; + + pub const LPUARTSEL = enum(u2) { + /// pclk7 selected + PCLK7 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + /// LSE selected + LSE = 0x3, + }; + + pub const LSCOSEL = enum(u1) { + /// LSI clock selected + LSI = 0x0, + /// LSE clock selected + LSE = 0x1, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const LSETRIM = enum(u2) { + /// current source resistance 5/4 x R + R5_4 = 0x0, + /// current source resistance R + R = 0x1, + /// current source resistance 3/4 x R + R3_4 = 0x2, + /// current source resistance 2/3 x R + R2_3 = 0x3, + }; + + pub const LSIPREDIV = enum(u1) { + /// LSI not divided + Div1 = 0x0, + /// LSI divided by 128 + Div128 = 0x1, + }; + + pub const MCOPRE = enum(u3) { + /// MCO divided by 1 + Div1 = 0x0, + /// MCO divided by 2 + Div2 = 0x1, + /// MCO divided by 4 + Div4 = 0x2, + /// MCO divided by 8 + Div8 = 0x3, + /// MCO divided by 16 + Div16 = 0x4, + _, + }; + + pub const MCOSEL = enum(u4) { + /// MCO output disabled, no clock on MCO + DISABLED = 0x0, + /// sysclkpre system clock after PLL1RCLKPRE division selected + SYSCLKPRE = 0x1, + /// HSI clock selected + HSI = 0x3, + /// HSE clock selected + HSE = 0x4, + /// pll1rclk clock selected + PLL1_R = 0x5, + /// LSI clock selected + LSI = 0x6, + /// LSE clock selected + LSE = 0x7, + /// pll1pclk clock selected + PLL1_P = 0x8, + /// pll1qclk clock selected + PLL1_Q = 0x9, + /// hclk5 clock selected + HCLK5 = 0xa, + _, + }; + + pub const PLLRCLKPRE = enum(u1) { + /// pll1rclk not divided, sysclkpre = pll1rclk + Div1 = 0x0, + /// pll1rclk divided, sysclkpre = pll1rclk divided + Divided = 0x1, + }; + + pub const PLLRCLKPRESTEP = enum(u1) { + /// pll1rclk 2-step division + STEP2 = 0x0, + /// pll1rclk 3-step division + STEP3 = 0x1, + }; + + pub const PLLRGE = enum(u2) { + /// PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz + FREQ_4TO8MHZ = 0x0, + /// PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz + FREQ_8TO16MHZ = 0x3, + _, + }; + + pub const PLLSRC = enum(u2) { + /// no clock sent to PLL1 + DISABLE = 0x0, + /// HSI clock selected as PLL1 clock entry + HSI = 0x2, + /// HSE clock after HSEPRE divider selected as PLL1 clock entry + HSE = 0x3, + _, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const RADIOSTSEL = enum(u2) { + /// no clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled + DISABLE = 0x0, + /// LSE oscillator clock selected + LSE = 0x1, + /// HSE oscillator clock divided by 1000 selected + HSE = 0x3, + _, + }; + + pub const RNGSEL = enum(u2) { + /// LSE selected + LSE = 0x0, + /// LSI selected + LSI = 0x1, + /// HSI selected + HSI = 0x2, + /// pll1qclk divide by 2 selected + PLL1_Q = 0x3, + }; + + pub const RTCSEL = enum(u2) { + /// no clock selected, RTC and TAMP kernel clock disabled + DISABLE = 0x0, + /// LSE oscillator clock selected, and enabled + LSE = 0x1, + /// LSI oscillator clock selected, and enabled + LSI = 0x2, + /// HSE oscillator clock divided by 32 selected, and enabled + HSE = 0x3, + }; + + pub const SPI1SEL = enum(u2) { + /// pclk2 selected + PCLK2 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + _, + }; + + pub const SPI3SEL = enum(u2) { + /// pclk2 selected + PCLK7 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + _, + }; + + pub const SW = enum(u2) { + /// HSI selected as system clock + HSI = 0x0, + /// HSE or HSE/2, as defined by HSEPRE, selected as system clock + HSE = 0x2, + /// pll1rclk selected as system clock + PLL1_R = 0x3, + _, + }; + + pub const SYSTICKSEL = enum(u2) { + /// hclk1 divided by 8 selected + HCLK1_DIV_8 = 0x0, + /// LSI selected + LSI = 0x1, + /// LSE selected + LSE = 0x2, + _, + }; + + pub const TIMICSEL = enum(u1) { + /// HSI divider disabled + HSI = 0x0, + /// HSI/256 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + HSI_DIV_256 = 0x1, + }; + + pub const USART1SEL = enum(u2) { + /// pclk2 selected + PCLK2 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + /// LSE selected + LSE = 0x3, + }; + + pub const USARTSEL = enum(u2) { + /// pclk1 selected + PCLK1 = 0x0, + /// SYSCLK selected + SYS = 0x1, + /// HSI selected + HSI = 0x2, + /// LSE selected + LSE = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// RCC clock control register + CR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// HSI clock enable Set and cleared by software. Cleared by hardware when entering Stop and Standby modes. Set by hardware to force the HSI oscillator on when exiting Stop and Standby modes. Set by hardware to force the HSI oscillator on in case of clock security failure of the HSE crystal oscillator. This bit is set by hardware if the HSI is used directly or indirectly as system clock. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSION: u1, + /// HSI enable for some peripheral kernels Set and cleared by software to force HSI oscillator on even in Stop modes. Keeping the HSI oscillator on in Stop modes allows the communication speed not to be reduced by the HSI oscillator startup time. This bit has no effect on register bit HSION value. Cleared by hardware when entering Standby modes. Refer to Peripherals clock gating and autonomous mode for more details. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSIKERON: u1, + /// HSI clock ready flag Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI clock cycles. + HSIRDY: u1, + reserved16: u5, + /// HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE clock for the CPU when entering Stop and Standby modes and on a HSECSS failure. When the HSE is used as 2.4 GHz RADIO kernel clock, enabled by RADIOEN and RADIOSMEN and the 2.4 GHz RADIO is active, HSEON is not be cleared when entering low power mode. In this case only Stop 0 mode is entered as low power mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSEON: u1, + /// HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. This bit is set both when HSE is enabled by software by setting HSEON and when requested as kernel clock by the 2.4 GHz RADIO. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSERDY: u1, + reserved19: u1, + /// HSE clock security system enable Set by software to enable the HSE clock security system. When HSECSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSECSSON: u1, + /// HSE clock for SYSCLK prescaler Set and cleared by software to control the division factor of the HSE clock for SYSCLK. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSEPRE: packed union { + raw: u1, + value: HSEPRE, + }, + reserved24: u3, + /// PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop or Standby modes and when PLL1 on HSE is selected as sysclk, on a HSECSS failure. This bit cannot be reset if the PLL1 clock is used as the system clock. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + PLLON: u1, + /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + PLLRDY: u1, + padding: u6, + }), + reserved16: [12]u8, + /// RCC internal clock sources calibration register 3 + ICSCR3: mmio.Mmio(packed struct(u32) { + /// HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration value. When HSITRIM[4:0] is written, HSICAL[11:0] is updated with the sum of HSITRIM[4:0] and the initial factory trim value. + HSICAL: u12, + reserved16: u4, + /// HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI. + HSITRIM: u5, + padding: u11, + }), + reserved28: [8]u8, + /// RCC clock configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// system clock switch Set and cleared by software to select system clock source (SYSCLK). Cleared by hardware when entering Stop and Standby modes When selecting HSE directly or indirectly as system clock and HSE oscillator clock security fails, cleared by hardware. + SW: packed union { + raw: u2, + value: SW, + }, + /// system clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. + SWS: packed union { + raw: u2, + value: SW, + }, + reserved24: u20, + /// microcontroller clock output Set and cleared by software. others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. + MCOSEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// microcontroller clock output prescaler Set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. others: not allowed + MCOPRE: packed union { + raw: u3, + value: MCOPRE, + }, + padding: u1, }), - reserved252: [4]u8, - /// RCC AHB3 Sleep Clock Register - AHB3LPENR: mmio.Mmio(packed struct(u32) { - /// MDMA Clock Enable During CSleep Mode - MDMALPEN: u1, - reserved4: u3, - /// DMA2D Clock Enable During CSleep Mode - DMA2DLPEN: u1, - /// JPGDEC Clock Enable During CSleep Mode - JPGDECLPEN: u1, - reserved8: u2, - /// FLASH Clock Enable During CSleep Mode - FLASHLPEN: u1, - reserved12: u3, - /// FMC Peripheral Clocks Enable During CSleep Mode - FMCLPEN: u1, - reserved14: u1, - /// QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - QUADSPILPEN: u1, - reserved16: u1, - /// SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - SDMMC1LPEN: u1, - reserved19: u2, - /// OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode - OCTOSPI2LPEN: u1, - reserved21: u1, - /// OCTOSPI IO manager enable during CSleep Mode - IOMNGRLPEN: u1, - /// OTFDEC1 enable during CSleep Mode - OTFD1LPEN: u1, - /// OTFDEC2 enable during CSleep Mode - OTFD2LPEN: u1, - reserved28: u4, - /// D1DTCM1 Block Clock Enable During CSleep mode - D1DTCM1LPEN: u1, - /// D1 DTCM2 Block Clock Enable During CSleep mode - DTCM2LPEN: u1, - /// D1ITCM Block Clock Enable During CSleep mode - ITCMLPEN: u1, - /// AXISRAM Block Clock Enable During CSleep mode - AXISRAMLPEN: u1, + /// RCC clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// AHB1, AHB2 and AHB4 prescaler Set and cleared by software to control the division factor of the AHB1, AHB2 and AHB4 clock (hclk1). The software must limit the incremental frequency step by setting these bits correctly to ensure that the hclk1 maximum incremental frequency step does not exceed the maximum allowed incremental frequency step (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xx: hclk1 = SYSCLK not divided + HPRE: packed union { + raw: u3, + value: HPRE, + }, + reserved4: u1, + /// APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (pclk1). 0xx: pclk1 = hclk1 not divided + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + reserved8: u1, + /// APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (pclk2). 0xx: pclk2 = hclk1 not divided + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + padding: u21, }), - /// RCC AHB1 Sleep Clock Register - AHB1LPENR: mmio.Mmio(packed struct(u32) { - /// DMA1 Clock Enable During CSleep Mode - DMA1LPEN: u1, - /// DMA2 Clock Enable During CSleep Mode - DMA2LPEN: u1, - reserved5: u3, - /// ADC1/2 Peripheral Clocks Enable During CSleep Mode - ADC12LPEN: u1, - reserved14: u8, - /// ART Clock Enable During CSleep Mode - ARTLPEN: u1, - /// Ethernet MAC bus interface Clock Enable During CSleep Mode - ETHLPEN: u1, - /// Ethernet Transmission Clock Enable During CSleep Mode - ETHTXLPEN: u1, - /// Ethernet Reception Clock Enable During CSleep Mode - ETHRXLPEN: u1, - reserved25: u7, - /// USB_OTG_HS peripheral clock enable during CSleep mode - USB_OTG_HSLPEN: u1, - /// USB_PHY1 clock enable during CSleep mode - USB_OTG_HS_ULPILPEN: u1, - /// USB_OTG_FS peripheral clock enable during CSleep mode - USB_OTG_FSLPEN: u1, - /// USB_PHY2 clocks enable during CSleep mode - USB_OTG_FS_ULPILPEN: u1, - padding: u3, + /// RCC clock configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// APB7 prescaler Set and cleared by software to control the division factor of the APB7 clock (pclk7). 0xx: hclk1 not divided + PPRE7: packed union { + raw: u3, + value: PPRE, + }, + padding: u25, }), - /// RCC AHB2 Sleep Clock Register - AHB2LPENR: mmio.Mmio(packed struct(u32) { - /// DCMI peripheral clock enable during csleep mode - DCMILPEN: u1, - reserved4: u3, - /// CRYP peripheral clock enable during CSleep mode - CRYPLPEN: u1, - /// HASH peripheral clock enable during CSleep mode - HASHLPEN: u1, - /// RNG peripheral clock enable during CSleep mode - RNGLPEN: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - SDMMC2LPEN: u1, - reserved16: u6, - /// FMAC enable during CSleep Mode - FMACLPEN: u1, - /// CORDIC enable during CSleep Mode - CORDICLPEN: u1, - reserved29: u11, - /// SRAM1 Clock Enable During CSleep Mode - SRAM1LPEN: u1, - /// SRAM2 Clock Enable During CSleep Mode - SRAM2LPEN: u1, - /// SRAM3 Clock Enable During CSleep Mode - SRAM3LPEN: u1, + /// RCC PLL1 configuration register + PLL1CFGR: mmio.Mmio(packed struct(u32) { + /// PLL1 entry clock source Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled. Cleared by hardware when entering Stop or Standby modes. Note: In order to save power, when no PLL1 clock is used, the value of PLL1SRC must be 0. + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + /// PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz + PLLRGE: packed union { + raw: u2, + value: PLLRGE, + }, + /// PLL1 fractional latch enable Set and reset by software to latch the content of PLL1FRACN into the ΣΔ modulator. In order to latch the PLL1FRACN value into the ΣΔ modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL1 initialization phase for details). + PLLFRACEN: u1, + reserved8: u3, + /// Prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLM: u3, + reserved16: u5, + /// PLL1 DIVP divider output enable Set and reset by software to enable the pll1pclk output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1pclk is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). + PLLPEN: u1, + /// PLL1 DIVQ divider output enable Set and reset by software to enable the pll1qclk output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1qclk is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). + PLLQEN: u1, + /// PLL1 DIVR divider output enable Set and cleared by software to enable the pll1rclk output of the PLL1. To save power, PLL1REN and PLL1R bits must be set to 0 when the pll1rclk is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). + PLLREN: u1, + reserved20: u1, + /// pll1rclk clock for SYSCLK prescaler division enable Set and cleared by software to control the division of the pll1rclk clock for SYSCLK. + PLLRCLKPRE: packed union { + raw: u1, + value: PLLRCLKPRE, + }, + /// pll1rclk clock for SYSCLK prescaler division step selection Set and cleared by software to control the division step of the pll1rclk clock for SYSCLK. + PLLRCLKPRESTEP: packed union { + raw: u1, + value: PLLRCLKPRESTEP, + }, + /// pll1rclkpre not divided ready. Set by hardware after PLL1RCLKPRE has been set from divided to not divide, to indicate that the pll1rclk not divided is available on sysclkpre. + PLLRCLKPRERDY: u1, + padding: u9, }), - /// RCC AHB4 Sleep Clock Register - AHB4LPENR: mmio.Mmio(packed struct(u32) { - /// GPIO peripheral clock enable during CSleep mode - GPIOALPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOBLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOCLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIODLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOELPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOFLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOGLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOHLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOILPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOJLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOKLPEN: u1, - reserved19: u8, - /// CRC peripheral clock enable during CSleep mode - CRCLPEN: u1, - reserved21: u1, - /// BDMA Clock Enable During CSleep Mode - BDMALPEN: u1, - reserved24: u2, - /// ADC3 Peripheral Clocks Enable During CSleep Mode - ADC3LPEN: u1, - reserved28: u3, - /// Backup RAM Clock Enable During CSleep Mode - BKPSRAMLPEN: u1, - /// SRAM4 Clock Enable During CSleep Mode - SRAM4LPEN: u1, - padding: u2, + reserved52: [8]u8, + /// RCC PLL1 dividers register + PLL1DIVR: mmio.Mmio(packed struct(u32) { + /// Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... others: reserved VCO output frequency = Fref1_ck x multiplication factor for PLL1 VCO, when fractional value 0 has been loaded into PLL1FRACN, with: Multiplication factor for PLL1 VCO between 4 and 512 input frequency Fref1_ck between 4 and 16�MHz + PLLN: u9, + /// PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1pclk clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... + PLLP: u7, + /// PLL1 DIVQ division factor Set and reset by software to control the frequency of the PLl1QCLK clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLQ: u7, + reserved24: u1, + /// PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1rclk clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... + PLLR: u7, + padding: u1, }), - /// RCC APB3 Sleep Clock Register - APB3LPENR: mmio.Mmio(packed struct(u32) { + /// RCC PLL1 fractional divider register + PLL1FRACR: mmio.Mmio(packed struct(u32) { reserved3: u3, - /// LTDC peripheral clock enable during CSleep mode - LTDCLPEN: u1, - /// DSI Peripheral Clock Enable During CSleep Mode - DSILPEN: u1, + /// Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x [multiplication factor for PLL1 VCO + (PLL1FRACN / 213)], with: Multiplication factor for PLL1 VCO must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the used fractional value on-the-fly even if the PLL1 is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1. + PLLFRACN: u13, + padding: u16, + }), + reserved80: [20]u8, + /// RCC clock interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI1 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI1 oscillator stabilization. Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSI1RDYIE: u1, + /// LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSERDYIE: u1, + reserved3: u1, + /// HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSIRDYIE: u1, + /// HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSERDYIE: u1, reserved6: u1, - /// WWDG1 Clock Enable During CSleep Mode - WWDG1LPEN: u1, + /// PLL1 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + PLLRDYIE: u1, padding: u25, }), - /// RCC APB1 Low Sleep Clock Register - APB1LLPENR: mmio.Mmio(packed struct(u32) { - /// TIM2 peripheral clock enable during CSleep mode - TIM2LPEN: u1, - /// TIM3 peripheral clock enable during CSleep mode - TIM3LPEN: u1, - /// TIM4 peripheral clock enable during CSleep mode - TIM4LPEN: u1, - /// TIM5 peripheral clock enable during CSleep mode - TIM5LPEN: u1, - /// TIM6 peripheral clock enable during CSleep mode - TIM6LPEN: u1, - /// TIM7 peripheral clock enable during CSleep mode - TIM7LPEN: u1, - /// TIM12 peripheral clock enable during CSleep mode - TIM12LPEN: u1, - /// TIM13 peripheral clock enable during CSleep mode - TIM13LPEN: u1, - /// TIM14 peripheral clock enable during CSleep mode - TIM14LPEN: u1, - /// LPTIM1 Peripheral Clocks Enable During CSleep Mode - LPTIM1LPEN: u1, - reserved11: u1, - /// WWDG2 peripheral Clocks Enable During CSleep Mode - WWDG2LPEN: u1, - reserved14: u2, - /// SPI2 Peripheral Clocks Enable During CSleep Mode - SPI2LPEN: u1, - /// SPI3 Peripheral Clocks Enable During CSleep Mode - SPI3LPEN: u1, - /// SPDIFRX Peripheral Clocks Enable During CSleep Mode - SPDIFRXLPEN: u1, - /// USART2 Peripheral Clocks Enable During CSleep Mode - USART2LPEN: u1, - /// USART3 Peripheral Clocks Enable During CSleep Mode - USART3LPEN: u1, - /// UART4 Peripheral Clocks Enable During CSleep Mode - UART4LPEN: u1, - /// UART5 Peripheral Clocks Enable During CSleep Mode - UART5LPEN: u1, - /// I2C1 Peripheral Clocks Enable During CSleep Mode - I2C1LPEN: u1, - /// I2C2 Peripheral Clocks Enable During CSleep Mode - I2C2LPEN: u1, - /// I2C3 Peripheral Clocks Enable During CSleep Mode - I2C3LPEN: u1, - reserved25: u1, - /// I2C5 block enable during CSleep Mode - I2C5LPEN: u1, - reserved27: u1, - /// HDMI-CEC Peripheral Clocks Enable During CSleep Mode - CECLPEN: u1, - reserved29: u1, - /// DAC1/2 peripheral clock enable during CSleep mode - DAC12LPEN: u1, - /// UART7 Peripheral Clocks Enable During CSleep Mode - UART7LPEN: u1, - /// UART8 Peripheral Clocks Enable During CSleep Mode - UART8LPEN: u1, + /// RCC clock interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI1 ready interrupt flag Set by hardware when the LSI1 clock becomes stable and LSI1RDYIE is set. Cleared by software setting the LSI1RDYC bit. Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSI1RDYF: u1, + /// LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYIE is set. Cleared by software setting the LSERDYC bit. Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSERDYF: u1, + reserved3: u1, + /// HSI ready interrupt flag Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see CR). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Cleared by software setting the HSIRDYC bit. + HSIRDYF: u1, + /// HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSERDYF: u1, + reserved6: u1, + /// PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + PLLRDYF: u1, + reserved10: u3, + /// HSE clock security system interrupt flag Set by hardware when a clock security failure is detected in the HSE oscillator. Cleared by software setting the HSECSSC bit. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSECSSF: u1, + padding: u21, }), - /// RCC APB1 High Sleep Clock Register - APB1HLPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System peripheral clock enable during CSleep mode - CRSLPEN: u1, - /// SWPMI Peripheral Clocks Enable During CSleep Mode - SWPMILPEN: u1, - reserved4: u1, - /// OPAMP peripheral clock enable during CSleep mode - OPAMPLPEN: u1, - /// MDIOS peripheral clock enable during CSleep mode - MDIOSLPEN: u1, - reserved8: u2, - /// FDCAN Peripheral Clocks Enable During CSleep Mode - FDCANLPEN: u1, - reserved24: u15, - /// TIM23 block enable during CSleep Mode - TIM23LPEN: u1, - /// TIM24 block enable during CSleep Mode - TIM24LPEN: u1, - padding: u6, + /// RCC clock interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI1 ready interrupt clear Writing this bit to 1 clears the LSI1RDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSI1RDYC: u1, + /// LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSERDYC: u1, + reserved3: u1, + /// HSI ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.\ Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSIRDYC: u1, + /// HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSERDYC: u1, + reserved6: u1, + /// PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + PLLRDYC: u1, + reserved10: u3, + /// High speed external clock security system interrupt clear Writing this bit to 1 clears the HSECSSF flag. Writing 0 has no effect. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSECSSC: u1, + padding: u21, }), - /// RCC APB2 Sleep Clock Register - APB2LPENR: mmio.Mmio(packed struct(u32) { - /// TIM1 peripheral clock enable during CSleep mode - TIM1LPEN: u1, - /// TIM8 peripheral clock enable during CSleep mode - TIM8LPEN: u1, - reserved4: u2, - /// USART1 Peripheral Clocks Enable During CSleep Mode - USART1LPEN: u1, - /// USART6 Peripheral Clocks Enable During CSleep Mode - USART6LPEN: u1, - reserved12: u6, - /// SPI1 Peripheral Clocks Enable During CSleep Mode - SPI1LPEN: u1, - /// SPI4 Peripheral Clocks Enable During CSleep Mode - SPI4LPEN: u1, - reserved16: u2, - /// TIM15 peripheral clock enable during CSleep mode - TIM15LPEN: u1, - /// TIM16 peripheral clock enable during CSleep mode - TIM16LPEN: u1, - /// TIM17 peripheral clock enable during CSleep mode - TIM17LPEN: u1, - reserved20: u1, - /// SPI5 Peripheral Clocks Enable During CSleep Mode - SPI5LPEN: u1, - reserved22: u1, - /// SAI1 Peripheral Clocks Enable During CSleep Mode - SAI1LPEN: u1, - /// SAI2 Peripheral Clocks Enable During CSleep Mode - SAI2LPEN: u1, - /// SAI3 Peripheral Clocks Enable During CSleep Mode - SAI3LPEN: u1, - reserved28: u3, - /// DFSDM1 Peripheral Clocks Enable During CSleep Mode - DFSDM1LPEN: u1, - /// HRTIM peripheral clock enable during CSleep mode - HRTIMLPEN: u1, - padding: u2, + reserved96: [4]u8, + /// RCC AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 reset Set and cleared by software. Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + GPDMA1RST: u1, + reserved12: u11, + /// CRC reset Set and cleared by software. Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + CRCRST: u1, + reserved16: u3, + /// TSC reset Set and cleared by software. Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + TSCRST: u1, + padding: u15, }), - /// RCC APB4 Sleep Clock Register - APB4LPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG peripheral clock enable during CSleep mode - SYSCFGLPEN: u1, - reserved3: u1, - /// LPUART1 Peripheral Clocks Enable During CSleep Mode - LPUART1LPEN: u1, - reserved5: u1, - /// SPI6 Peripheral Clocks Enable During CSleep Mode - SPI6LPEN: u1, - reserved7: u1, - /// I2C4 Peripheral Clocks Enable During CSleep Mode - I2C4LPEN: u1, - reserved9: u1, - /// LPTIM2 Peripheral Clocks Enable During CSleep Mode - LPTIM2LPEN: u1, - /// LPTIM3 Peripheral Clocks Enable During CSleep Mode - LPTIM3LPEN: u1, - /// LPTIM4 Peripheral Clocks Enable During CSleep Mode - LPTIM4LPEN: u1, - /// LPTIM5 Peripheral Clocks Enable During CSleep Mode - LPTIM5LPEN: u1, - /// DAC2 (containing one converter) peripheral clock enable during CSleep mode - DAC2LPEN: u1, - /// COMP1/2 peripheral clock enable during CSleep mode - COMP12LPEN: u1, - /// VREF peripheral clock enable during CSleep mode - VREFLPEN: u1, - /// RTC APB Clock Enable During CSleep Mode - RTCAPBLPEN: u1, - reserved21: u4, - /// SAI4 Peripheral Clocks Enable During CSleep Mode - SAI4LPEN: u1, - reserved26: u4, - /// Digital temperature sensor block enable during CSleep Mode - DTSLPEN: u1, - padding: u5, + /// RCC AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset Set and cleared by software. Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + GPIOARST: u1, + /// IO port B reset Set and cleared by software. Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + GPIOBRST: u1, + /// IO port C reset Set and cleared by software. Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + GPIOCRST: u1, + reserved7: u4, + /// IO port H reset Set and cleared by software. Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + GPIOHRST: u1, + reserved16: u8, + /// AES hardware accelerator reset Set and cleared by software. Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + AESRST: u1, + /// Hash reset Set and cleared by software. Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HASHRST: u1, + /// Random number generator reset Set and cleared by software. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + RNGRST: u1, + /// SAES hardware accelerator reset Set and cleared by software. Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + SAESRST: u1, + /// HSEM hardware accelerator reset Set and cleared by software. Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HSEMRST: u1, + /// PKA reset Set and cleared by software. Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + PKARST: u1, + padding: u10, }), - reserved304: [16]u8, - /// RCC Reset Status Register - C1_RSR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Remove reset flag - RMVF: u1, - /// CPU reset flag - CPURSTF: u1, - reserved19: u1, - /// D1 domain power switch reset flag - D1RSTF: u1, - /// D2 domain power switch reset flag - D2RSTF: u1, - /// BOR reset flag - BORRSTF: u1, - /// Pin reset flag (NRST) - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// System reset from CPU reset flag - SFTRSTF: u1, - reserved26: u1, - /// Independent Watchdog reset flag - IWDG1RSTF: u1, - reserved28: u1, - /// Window Watchdog reset flag - WWDG1RSTF: u1, - reserved30: u1, - /// Reset due to illegal D1 DStandby or CPU CStop flag - LPWRRSTF: u1, - padding: u1, + reserved108: [4]u8, + /// RCC AHB4 peripheral reset register + AHB4RSTR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// ADC4 reset Set and cleared by software. Access can be secred by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + ADC4RST: u1, + padding: u26, }), - /// RCC AHB3 Clock Register - C1_AHB3ENR: mmio.Mmio(packed struct(u32) { - /// MDMA Peripheral Clock Enable - MDMAEN: u1, - reserved4: u3, - /// DMA2D Peripheral Clock Enable - DMA2DEN: u1, - /// JPGDEC Peripheral Clock Enable - JPGDECEN: u1, - reserved12: u6, - /// FMC Peripheral Clocks Enable - FMCEN: u1, + /// RCC AHB5 peripheral reset register + AHB5RSTR: mmio.Mmio(packed struct(u32) { + /// 2.4 GHz RADIO reset Set and cleared by software. Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + RADIORST: u1, + padding: u31, + }), + /// RCC APB1 peripheral reset register 1 + APB1RSTR1: mmio.Mmio(packed struct(u32) { + /// TIM2 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + TIM2RST: u1, + /// TIM3 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + TIM3RST: u1, + reserved17: u15, + /// USART2 reset Set and cleared by software. Access can be secured by GTZC_TZSC UART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + USART2RST: u1, + reserved21: u3, + /// I2C1 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + I2C1RST: u1, + padding: u10, + }), + /// RCC APB1 peripheral reset register 2 + APB1RSTR2: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// LPTIM2 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LPTIM2RST: u1, + padding: u26, + }), + /// RCC APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + TIM1RST: u1, + /// SPI1 reset Set and cleared by software. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + SPI1RST: u1, reserved14: u1, - /// QUADSPI and QUADSPI Delay Clock Enable - QUADSPIEN: u1, - reserved16: u1, - /// SDMMC1 and SDMMC1 Delay Clock Enable - SDMMC1EN: u1, - padding: u15, + /// USART1 reset Set and cleared by software. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + USART1RST: u1, + reserved17: u2, + /// TIM16 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + TIM16RST: u1, + /// TIM17 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + TIM17RST: u1, + padding: u13, }), - /// RCC AHB1 Clock Register - C1_AHB1ENR: mmio.Mmio(packed struct(u32) { - /// DMA1 Clock Enable - DMA1EN: u1, - /// DMA2 Clock Enable - DMA2EN: u1, + /// RCC APB7 peripheral reset register + APB7RSTR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG reset Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + SYSCFGRST: u1, reserved5: u3, - /// ADC1/2 Peripheral Clocks Enable - ADC12EN: u1, - reserved14: u8, - /// ART Clock Enable - ARTEN: u1, - /// Ethernet MAC bus interface Clock Enable - ETHEN: u1, - /// Ethernet Transmission Clock Enable - ETHTXEN: u1, - /// Ethernet Reception Clock Enable - ETHRXEN: u1, - reserved25: u7, - /// USB_OTG_HS Peripheral Clocks Enable - USB_OTG_HSEN: u1, - /// USB_PHY1 Clocks Enable - USB_OTG_HS_ULPIEN: u1, - /// USB_OTG_FS Peripheral Clocks Enable - USB_OTG_FSEN: u1, - /// USB_PHY2 Clocks Enable - USB_OTG_FS_ULPIEN: u1, - padding: u3, + /// SPI3 reset Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + SPI3RST: u1, + /// LPUART1 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LPUART1RST: u1, + /// I2C3 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + I2C3RST: u1, + reserved11: u3, + /// LPTIM1 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LPTIM1RST: u1, + padding: u20, }), - /// RCC AHB2 Clock Register - C1_AHB2ENR: mmio.Mmio(packed struct(u32) { - /// DCMI peripheral clock - DCMIEN: u1, - reserved4: u3, - /// CRYP peripheral clock enable - CRYPEN: u1, - /// HASH peripheral clock enable - HASHEN: u1, - /// RNG peripheral clocks enable - RNGEN: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 delay clock enable - SDMMC2EN: u1, - reserved29: u19, - /// SRAM1 block enable + reserved136: [4]u8, + /// RCC AHB1 peripheral clock enable register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 bus clock enable Set and cleared by software. Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + GPDMA1EN: u1, + reserved8: u7, + /// FLASH bus clock enable Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode. Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + FLASHEN: u1, + reserved12: u3, + /// CRC bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + CRCEN: u1, + reserved16: u3, + /// Touch sensing controller bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + TSCEN: u1, + /// RAMCFG bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + RAMCFGEN: u1, + reserved24: u6, + /// GTZC1 bus clock enable Set and reset by software. Can only be accessed secure when device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + GTZC1EN: u1, + reserved31: u6, + /// SRAM1 bus clock enable Set and reset by software. Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. SRAM1EN: u1, - /// SRAM2 block enable - SRAM2EN: u1, - /// SRAM3 block enable - SRAM3EN: u1, }), - /// RCC AHB4 Clock Register - C1_AHB4ENR: mmio.Mmio(packed struct(u32) { - /// 0GPIO peripheral clock enable + /// RCC AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// IO port A bus clock enable Set and cleared by software. Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. GPIOAEN: u1, - /// 0GPIO peripheral clock enable + /// IO port B bus clock enable Set and cleared by software. Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. GPIOBEN: u1, - /// 0GPIO peripheral clock enable + /// IO port C bus clock enable Set and cleared by software. Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. GPIOCEN: u1, - /// 0GPIO peripheral clock enable - GPIODEN: u1, - /// 0GPIO peripheral clock enable - GPIOEEN: u1, - /// 0GPIO peripheral clock enable - GPIOFEN: u1, - /// 0GPIO peripheral clock enable - GPIOGEN: u1, - /// 0GPIO peripheral clock enable + reserved7: u4, + /// IO port H bus clock enable Set and cleared by software. Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. GPIOHEN: u1, - /// 0GPIO peripheral clock enable - GPIOIEN: u1, - /// 0GPIO peripheral clock enable - GPIOJEN: u1, - /// 0GPIO peripheral clock enable - GPIOKEN: u1, - reserved19: u8, - /// CRC peripheral clock enable - CRCEN: u1, - reserved21: u1, - /// BDMA and DMAMUX2 Clock Enable - BDMAEN: u1, - reserved24: u2, - /// ADC3 Peripheral Clocks Enable - ADC3EN: u1, - /// HSEM peripheral clock enable + reserved16: u8, + /// AES bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + AESEN: u1, + /// HASH bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HASHEN: u1, + /// RNG bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + RNGEN: u1, + /// SAES bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + SAESEN: u1, + /// HSEM bus clock enable Set and cleared by software. Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. HSEMEN: u1, - reserved28: u2, - /// Backup RAM Clock Enable - BKPSRAMEN: u1, - padding: u3, + /// PKA bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + PKAEN: u1, + reserved30: u8, + /// SRAM2 bus clock enable Set and cleared by software. Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + SRAM2EN: u1, + padding: u1, }), - /// RCC APB3 Clock Register - C1_APB3ENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// LTDC peripheral clock enable - LTDCEN: u1, - /// DSI Peripheral clocks enable - DSIEN: u1, - reserved6: u1, - /// WWDG1 Clock Enable - WWDG1EN: u1, - padding: u25, + reserved148: [4]u8, + /// RCC AHB4 peripheral clock enable register + AHB4ENR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// PWR bus clock enable Set and cleared by software. Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + PWREN: u1, + reserved5: u2, + /// ADC4 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + ADC4EN: u1, + padding: u26, }), - /// RCC APB1 Clock Register - C1_APB1LENR: mmio.Mmio(packed struct(u32) { - /// TIM peripheral clock enable + /// RCC AHB5 peripheral clock enable register + AHB5ENR: mmio.Mmio(packed struct(u32) { + /// 2.4 GHz RADIO bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Before accessing the 2.4 GHz RADIO sleep timers registers the RADIOCLKRDY bit must be checked. Note: When RADIOSMEN and STRADIOCLKON are both cleared, RADIOCLKRDY bit must be re-checked when exiting low-power modes (Sleep and Stop). + RADIOEN: u1, + padding: u31, + }), + /// RCC APB1 peripheral clock enable register 1 + APB1ENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. TIM2EN: u1, - /// TIM peripheral clock enable + /// TIM3 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. TIM3EN: u1, - /// TIM peripheral clock enable - TIM4EN: u1, - /// TIM peripheral clock enable - TIM5EN: u1, - /// TIM peripheral clock enable - TIM6EN: u1, - /// TIM peripheral clock enable - TIM7EN: u1, - /// TIM peripheral clock enable - TIM12EN: u1, - /// TIM peripheral clock enable - TIM13EN: u1, - /// TIM peripheral clock enable - TIM14EN: u1, - /// LPTIM1 Peripheral Clocks Enable - LPTIM1EN: u1, - reserved11: u1, - /// WWDG2 peripheral clock enable - WWDG2EN: u1, - reserved14: u2, - /// SPI2 Peripheral Clocks Enable - SPI2EN: u1, - /// SPI3 Peripheral Clocks Enable - SPI3EN: u1, - /// SPDIFRX Peripheral Clocks Enable - SPDIFRXEN: u1, - /// USART2 Peripheral Clocks Enable + reserved11: u9, + /// WWDG bus clock enable Set by software to enable the window watchdog bus clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + WWDGEN: u1, + reserved17: u5, + /// USART2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC USART2SEC When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.. USART2EN: u1, - /// USART3 Peripheral Clocks Enable - USART3EN: u1, - /// UART4 Peripheral Clocks Enable - UART4EN: u1, - /// UART5 Peripheral Clocks Enable - UART5EN: u1, - /// I2C1 Peripheral Clocks Enable + reserved21: u3, + /// I2C1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. I2C1EN: u1, - /// I2C2 Peripheral Clocks Enable - I2C2EN: u1, - /// I2C3 Peripheral Clocks Enable - I2C3EN: u1, - reserved25: u1, - /// I2C5 Peripheral Clocks Enable - I2C5EN: u1, - reserved27: u1, - /// HDMI-CEC peripheral clock enable - CECEN: u1, - reserved29: u1, - /// DAC1&2 peripheral clock enable - DAC12EN: u1, - /// UART7 Peripheral Clocks Enable - UART7EN: u1, - /// UART8 Peripheral Clocks Enable - UART8EN: u1, + padding: u10, }), - /// RCC APB1 Clock Register - C1_APB1HENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System peripheral clock enable - CRSEN: u1, - /// SWPMI Peripheral Clocks Enable - SWPMIEN: u1, - reserved4: u1, - /// OPAMP peripheral clock enable - OPAMPEN: u1, - /// MDIOS peripheral clock enable - MDIOSEN: u1, - reserved8: u2, - /// FDCAN Peripheral Clocks Enable - FDCANEN: u1, - padding: u23, + /// RCC APB1 peripheral clock enable register 2 + APB1ENR2: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// LPTIM2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LPTIM2EN: u1, + padding: u26, }), - /// RCC APB2 Clock Register - C1_APB2ENR: mmio.Mmio(packed struct(u32) { - /// TIM1 peripheral clock enable + /// RCC APB2 peripheral clock enable register + APB2ENR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. TIM1EN: u1, - /// TIM8 peripheral clock enable - TIM8EN: u1, - reserved4: u2, - /// USART1 Peripheral Clocks Enable - USART1EN: u1, - /// USART6 Peripheral Clocks Enable - USART6EN: u1, - /// UART9 Peripheral Clocks Enable - UART9EN: u1, - /// USART10 Peripheral Clocks Enable - USART10EN: u1, - reserved12: u4, - /// SPI1 Peripheral Clocks Enable + /// SPI1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. SPI1EN: u1, - /// SPI4 Peripheral Clocks Enable - SPI4EN: u1, - reserved16: u2, - /// TIM15 peripheral clock enable - TIM15EN: u1, - /// TIM16 peripheral clock enable + reserved14: u1, + /// USART1bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + USART1EN: u1, + reserved17: u2, + /// TIM16 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. TIM16EN: u1, - /// TIM17 peripheral clock enable + /// TIM17 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. TIM17EN: u1, - reserved20: u1, - /// SPI5 Peripheral Clocks Enable - SPI5EN: u1, - reserved22: u1, - /// SAI1 Peripheral Clocks Enable - SAI1EN: u1, - /// SAI2 Peripheral Clocks Enable - SAI2EN: u1, - /// SAI3 Peripheral Clocks Enable - SAI3EN: u1, - reserved28: u3, - /// DFSDM1 Peripheral Clocks Enable - DFSDM1EN: u1, - /// HRTIM peripheral clock enable - HRTIMEN: u1, - padding: u2, + padding: u13, }), - /// RCC APB4 Clock Register - C1_APB4ENR: mmio.Mmio(packed struct(u32) { + /// RCC APB7 peripheral clock enable register + APB7ENR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// SYSCFG peripheral clock enable + /// SYSCFG bus clock enable Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. SYSCFGEN: u1, - reserved3: u1, - /// LPUART1 Peripheral Clocks Enable + reserved5: u3, + /// SPI3 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + SPI3EN: u1, + /// LPUART1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. LPUART1EN: u1, - reserved5: u1, - /// SPI6 Peripheral Clocks Enable - SPI6EN: u1, - reserved7: u1, - /// I2C4 Peripheral Clocks Enable - I2C4EN: u1, - reserved9: u1, - /// LPTIM2 Peripheral Clocks Enable - LPTIM2EN: u1, - /// LPTIM3 Peripheral Clocks Enable - LPTIM3EN: u1, - /// LPTIM4 Peripheral Clocks Enable - LPTIM4EN: u1, - /// LPTIM5 Peripheral Clocks Enable - LPTIM5EN: u1, - reserved14: u1, - /// COMP1/2 peripheral clock enable - COMP12EN: u1, - /// VREF peripheral clock enable - VREFEN: u1, - /// RTC APB Clock Enable + /// I2C3 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + I2C3EN: u1, + reserved11: u3, + /// LPTIM1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LPTIM1EN: u1, + reserved21: u9, + /// RTC and TAMP bus clock enable Set and cleared by software. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. RTCAPBEN: u1, - reserved21: u4, - /// SAI4 Peripheral Clocks Enable - SAI4EN: u1, padding: u10, }), - reserved348: [4]u8, - /// RCC AHB3 Sleep Clock Register - C1_AHB3LPENR: mmio.Mmio(packed struct(u32) { - /// MDMA Clock Enable During CSleep Mode - MDMALPEN: u1, - reserved4: u3, - /// DMA2D Clock Enable During CSleep Mode - DMA2DLPEN: u1, - /// JPGDEC Clock Enable During CSleep Mode - JPGDECLPEN: u1, - reserved8: u2, - /// Flash interface clock enable during csleep mode - FLASHPREN: u1, - reserved12: u3, - /// FMC Peripheral Clocks Enable During CSleep Mode - FMCLPEN: u1, - reserved14: u1, - /// QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - QUADSPILPEN: u1, - reserved16: u1, - /// SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - SDMMC1LPEN: u1, - reserved19: u2, - /// OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode - OCTOSPI2LPEN: u1, - reserved21: u1, - /// OCTOSPI IO manager enable during CSleep Mode - IOMNGRLPEN: u1, - /// OTFDEC1 enable during CSleep Mode - OTFD1LPEN: u1, - /// OTFDEC2 enable during CSleep Mode - OTFD2LPEN: u1, - reserved28: u4, - /// D1DTCM1 Block Clock Enable During CSleep mode - D1DTCM1LPEN: u1, - /// D1 DTCM2 Block Clock Enable During CSleep mode - DTCM2LPEN: u1, - /// D1ITCM Block Clock Enable During CSleep mode - ITCMLPEN: u1, - /// AXISRAM Block Clock Enable During CSleep mode - AXISRAMLPEN: u1, - }), - /// RCC AHB1 Sleep Clock Register - C1_AHB1LPENR: mmio.Mmio(packed struct(u32) { - /// DMA1 Clock Enable During CSleep Mode - DMA1LPEN: u1, - /// DMA2 Clock Enable During CSleep Mode - DMA2LPEN: u1, - reserved5: u3, - /// ADC1/2 Peripheral Clocks Enable During CSleep Mode - ADC12LPEN: u1, - reserved14: u8, - /// ART Clock Enable During CSleep Mode - ARTLPEN: u1, - /// Ethernet MAC bus interface Clock Enable During CSleep Mode - ETHLPEN: u1, - /// Ethernet Transmission Clock Enable During CSleep Mode - ETHTXLPEN: u1, - /// Ethernet Reception Clock Enable During CSleep Mode - ETHRXLPEN: u1, - reserved25: u7, - /// USB_OTG_HS peripheral clock enable during CSleep mode - USB_OTG_HSLPEN: u1, - /// USB_PHY1 clock enable during CSleep mode - USB_OTG_HS_ULPILPEN: u1, - /// USB_OTG_FS peripheral clock enable during CSleep mode - USB_OTG_FSLPEN: u1, - /// USB_PHY2 clocks enable during CSleep mode - USB_OTG_FS_ULPILPEN: u1, - padding: u3, - }), - /// RCC AHB2 Sleep Clock Register - C1_AHB2LPENR: mmio.Mmio(packed struct(u32) { - /// DCMI peripheral clock enable during csleep mode - DCMILPEN: u1, - reserved4: u3, - /// CRYP peripheral clock enable during CSleep mode - CRYPLPEN: u1, - /// HASH peripheral clock enable during CSleep mode - HASHLPEN: u1, - /// RNG peripheral clock enable during CSleep mode - RNGLPEN: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - SDMMC2LPEN: u1, - reserved16: u6, - /// FMAC enable during CSleep Mode - FMACLPEN: u1, - /// CORDIC enable during CSleep Mode - CORDICLPEN: u1, - reserved29: u11, - /// SRAM1 Clock Enable During CSleep Mode - SRAM1LPEN: u1, - /// SRAM2 Clock Enable During CSleep Mode - SRAM2LPEN: u1, - /// SRAM3 Clock Enable During CSleep Mode - SRAM3LPEN: u1, - }), - /// RCC AHB4 Sleep Clock Register - C1_AHB4LPENR: mmio.Mmio(packed struct(u32) { - /// GPIO peripheral clock enable during CSleep mode - GPIOALPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOBLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOCLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIODLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOELPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOFLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOGLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOHLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOILPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOJLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOKLPEN: u1, - reserved19: u8, - /// CRC peripheral clock enable during CSleep mode - CRCLPEN: u1, + reserved176: [4]u8, + /// RCC AHB1 peripheral clocks enable in Sleep and Stop modes register + AHB1SMENR: mmio.Mmio(packed struct(u32) { + /// GPDMA1 bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + GPDMA1SMEN: u1, + reserved8: u7, + /// FLASH bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + FLASHSMEN: u1, + reserved12: u3, + /// CRC bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + CRCSMEN: u1, + reserved16: u3, + /// TSC bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.. + TSCSMEN: u1, + /// RAMCFG bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + RAMCFGSMEN: u1, + reserved24: u6, + /// GTZC1 bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + GTZC1SMEN: u1, + reserved29: u4, + /// ICACHE bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC ICACHE_REGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.. + ICACHESMEN: u1, + reserved31: u1, + /// SRAM1 bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + SRAM1SMEN: u1, + }), + /// RCC AHB2 peripheral clocks enable in Sleep and Stop modes register + AHB2SMENR: mmio.Mmio(packed struct(u32) { + /// IO port A bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + GPIOASMEN: u1, + /// IO port B bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + GPIOBSMEN: u1, + /// IO port C bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + GPIOCSMEN: u1, + reserved7: u4, + /// IO port H bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + GPIOHSMEN: u1, + reserved16: u8, + /// AES bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + AESSMEN: u1, + /// HASH bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + HASHSMEN: u1, + /// Random number generator (RNG) bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + RNGSMEN: u1, + /// SAES accelerator bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + SAESSMEN: u1, reserved21: u1, - /// BDMA Clock Enable During CSleep Mode - BDMALPEN: u1, - reserved24: u2, - /// ADC3 Peripheral Clocks Enable During CSleep Mode - ADC3LPEN: u1, - reserved28: u3, - /// Backup RAM Clock Enable During CSleep Mode - BKPSRAMLPEN: u1, - /// SRAM4 Clock Enable During CSleep Mode - SRAM4LPEN: u1, - padding: u2, + /// PKA bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + PKASMEN: u1, + reserved30: u8, + /// SRAM2 bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + SRAM2SMEN: u1, + padding: u1, }), - /// RCC APB3 Sleep Clock Register - C1_APB3LPENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// LTDC peripheral clock enable during CSleep mode - LTDCLPEN: u1, - /// DSI Peripheral Clock Enable During CSleep Mode - DSILPEN: u1, - reserved6: u1, - /// WWDG1 Clock Enable During CSleep Mode - WWDG1LPEN: u1, - padding: u25, + reserved188: [4]u8, + /// RCC AHB4 peripheral clocks enable in Sleep and Stop modes register + AHB4SMENR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// PWR bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + PWRSMEN: u1, + reserved5: u2, + /// ADC4 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + ADC4SMEN: u1, + padding: u26, }), - /// RCC APB1 Low Sleep Clock Register - C1_APB1LLPENR: mmio.Mmio(packed struct(u32) { - /// TIM2 peripheral clock enable during CSleep mode - TIM2LPEN: u1, - /// TIM3 peripheral clock enable during CSleep mode - TIM3LPEN: u1, - /// TIM4 peripheral clock enable during CSleep mode - TIM4LPEN: u1, - /// TIM5 peripheral clock enable during CSleep mode - TIM5LPEN: u1, - /// TIM6 peripheral clock enable during CSleep mode - TIM6LPEN: u1, - /// TIM7 peripheral clock enable during CSleep mode - TIM7LPEN: u1, - /// TIM12 peripheral clock enable during CSleep mode - TIM12LPEN: u1, - /// TIM13 peripheral clock enable during CSleep mode - TIM13LPEN: u1, - /// TIM14 peripheral clock enable during CSleep mode - TIM14LPEN: u1, - /// LPTIM1 Peripheral Clocks Enable During CSleep Mode - LPTIM1LPEN: u1, - reserved11: u1, - /// WWDG2 peripheral Clocks Enable During CSleep Mode - WWDG2LPEN: u1, - reserved14: u2, - /// SPI2 Peripheral Clocks Enable During CSleep Mode - SPI2LPEN: u1, - /// SPI3 Peripheral Clocks Enable During CSleep Mode - SPI3LPEN: u1, - /// SPDIFRX Peripheral Clocks Enable During CSleep Mode - SPDIFRXLPEN: u1, - /// USART2 Peripheral Clocks Enable During CSleep Mode - USART2LPEN: u1, - /// USART3 Peripheral Clocks Enable During CSleep Mode - USART3LPEN: u1, - /// UART4 Peripheral Clocks Enable During CSleep Mode - UART4LPEN: u1, - /// UART5 Peripheral Clocks Enable During CSleep Mode - UART5LPEN: u1, - /// I2C1 Peripheral Clocks Enable During CSleep Mode - I2C1LPEN: u1, - /// I2C2 Peripheral Clocks Enable During CSleep Mode - I2C2LPEN: u1, - /// I2C3 Peripheral Clocks Enable During CSleep Mode - I2C3LPEN: u1, - reserved25: u1, - /// I2C5 block enable during CSleep Mode - I2C5LPEN: u1, - reserved27: u1, - /// HDMI-CEC Peripheral Clocks Enable During CSleep Mode - CECLPEN: u1, - reserved29: u1, - /// DAC1/2 peripheral clock enable during CSleep mode - DAC12LPEN: u1, - /// UART7 Peripheral Clocks Enable During CSleep Mode - UART7LPEN: u1, - /// UART8 Peripheral Clocks Enable During CSleep Mode - UART8LPEN: u1, + /// RCC AHB5 peripheral clocks enable in Sleep and Stop modes register + AHB5SMENR: mmio.Mmio(packed struct(u32) { + /// 2.4 GHz RADIO bus clock enable during Sleep and Stop modes when the 2.4 GHz RADIO is active. Set and cleared by software. Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + RADIOSMEN: u1, + padding: u31, }), - /// RCC APB1 High Sleep Clock Register - C1_APB1HLPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System peripheral clock enable during CSleep mode - CRSLPEN: u1, - /// SWPMI Peripheral Clocks Enable During CSleep Mode - SWPMILPEN: u1, - reserved4: u1, - /// OPAMP peripheral clock enable during CSleep mode - OPAMPLPEN: u1, - /// MDIOS peripheral clock enable during CSleep mode - MDIOSLPEN: u1, - reserved8: u2, - /// FDCAN Peripheral Clocks Enable During CSleep Mode - FDCANLPEN: u1, - reserved24: u15, - /// TIM23 block enable during CSleep Mode - TIM23LPEN: u1, - /// TIM24 block enable during CSleep Mode - TIM24LPEN: u1, - padding: u6, + /// RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1 + APB1SMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + TIM2SMEN: u1, + /// TIM3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + TIM3SMEN: u1, + reserved11: u9, + /// Window watchdog bus clock enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated. Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + WWDGSMEN: u1, + reserved17: u5, + /// USART2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + USART2SMEN: u1, + reserved21: u3, + /// I2C1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + I2C1SMEN: u1, + padding: u10, }), - /// RCC APB2 Sleep Clock Register - C1_APB2LPENR: mmio.Mmio(packed struct(u32) { - /// TIM1 peripheral clock enable during CSleep mode - TIM1LPEN: u1, - /// TIM8 peripheral clock enable during CSleep mode - TIM8LPEN: u1, - reserved4: u2, - /// USART1 Peripheral Clocks Enable During CSleep Mode - USART1LPEN: u1, - /// USART6 Peripheral Clocks Enable During CSleep Mode - USART6LPEN: u1, - reserved12: u6, - /// SPI1 Peripheral Clocks Enable During CSleep Mode - SPI1LPEN: u1, - /// SPI4 Peripheral Clocks Enable During CSleep Mode - SPI4LPEN: u1, - reserved16: u2, - /// TIM15 peripheral clock enable during CSleep mode - TIM15LPEN: u1, - /// TIM16 peripheral clock enable during CSleep mode - TIM16LPEN: u1, - /// TIM17 peripheral clock enable during CSleep mode - TIM17LPEN: u1, - reserved20: u1, - /// SPI5 Peripheral Clocks Enable During CSleep Mode - SPI5LPEN: u1, - reserved22: u1, - /// SAI1 Peripheral Clocks Enable During CSleep Mode - SAI1LPEN: u1, - /// SAI2 Peripheral Clocks Enable During CSleep Mode - SAI2LPEN: u1, - /// SAI3 Peripheral Clocks Enable During CSleep Mode - SAI3LPEN: u1, - reserved28: u3, - /// DFSDM1 Peripheral Clocks Enable During CSleep Mode - DFSDM1LPEN: u1, - /// HRTIM peripheral clock enable during CSleep mode - HRTIMLPEN: u1, - padding: u2, + /// RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 + APB1SMENR2: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// LPTIM2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPTIM2SMEN: u1, + padding: u26, }), - /// RCC APB4 Sleep Clock Register - C1_APB4LPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG peripheral clock enable during CSleep mode - SYSCFGLPEN: u1, - reserved3: u1, - /// LPUART1 Peripheral Clocks Enable During CSleep Mode - LPUART1LPEN: u1, - reserved5: u1, - /// SPI6 Peripheral Clocks Enable During CSleep Mode - SPI6LPEN: u1, - reserved7: u1, - /// I2C4 Peripheral Clocks Enable During CSleep Mode - I2C4LPEN: u1, - reserved9: u1, - /// LPTIM2 Peripheral Clocks Enable During CSleep Mode - LPTIM2LPEN: u1, - /// LPTIM3 Peripheral Clocks Enable During CSleep Mode - LPTIM3LPEN: u1, - /// LPTIM4 Peripheral Clocks Enable During CSleep Mode - LPTIM4LPEN: u1, - /// LPTIM5 Peripheral Clocks Enable During CSleep Mode - LPTIM5LPEN: u1, + /// RCC APB2 peripheral clocks enable in Sleep and Stop modes register + APB2SMENR: mmio.Mmio(packed struct(u32) { + reserved11: u11, + /// TIM1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + TIM1SMEN: u1, + /// SPI1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + SPI1SMEN: u1, reserved14: u1, - /// COMP1/2 peripheral clock enable during CSleep mode - COMP12LPEN: u1, - /// VREF peripheral clock enable during CSleep mode - VREFLPEN: u1, - /// RTC APB Clock Enable During CSleep Mode - RTCAPBLPEN: u1, - reserved21: u4, - /// SAI4 Peripheral Clocks Enable During CSleep Mode - SAI4LPEN: u1, - reserved26: u4, - /// Digital temperature sensor block enable during CSleep Mode - DTSLPEN: u1, - padding: u5, - }), - }; - }; - - pub const dsihost_v1 = struct { - /// DSI Host. - pub const DSIHOST = extern struct { - /// DSI Host Version Register. - VR: mmio.Mmio(packed struct(u32) { - /// Version of the DSI Host. - VERSION: u32, + /// USART1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + USART1SMEN: u1, + reserved17: u2, + /// TIM16 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + TIM16SMEN: u1, + /// TIM17 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + TIM17SMEN: u1, + padding: u13, }), - /// DSI Host Control Register. - CR: mmio.Mmio(packed struct(u32) { - /// Enable. - EN: u1, - padding: u31, + /// RCC APB7 peripheral clock enable in Sleep and Stop modes register + APB7SMENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SYSCFG bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + SYSCFGSMEN: u1, + reserved5: u3, + /// SPI3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + SPI3SMEN: u1, + /// LPUART1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPUART1SMEN: u1, + /// I2C3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + I2C3SMEN: u1, + reserved11: u3, + /// LPTIM1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + LPTIM1SMEN: u1, + reserved21: u9, + /// RTC and TAMP APB clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. + RTCAPBSMEN: u1, + padding: u10, }), - /// DSI HOST Clock Control Register. - CCR: mmio.Mmio(packed struct(u32) { - /// TX Escape Clock Division. - TXECKDIV: u8, - /// Timeout Clock Division. - TOCKDIV: u8, - padding: u16, + reserved224: [12]u8, + /// RCC peripherals independent clock configuration register 1 + CCIPR1: mmio.Mmio(packed struct(u32) { + /// USART1 kernel clock source selection This bits are used to select the USART1 kernel clock source. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. + USART1SEL: packed union { + raw: u2, + value: USART1SEL, + }, + /// USART2 kernel clock source selection This bits are used to select the USART2 kernel clock source. Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE. + USART2SEL: packed union { + raw: u2, + value: USARTSEL, + }, + reserved10: u6, + /// I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI. + I2C1SEL: packed union { + raw: u2, + value: I2C1SEL, + }, + reserved18: u6, + /// Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1. + LPTIM2SEL: packed union { + raw: u2, + value: LPTIM2SEL, + }, + /// SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI. + SPI1SEL: packed union { + raw: u2, + value: SPI1SEL, + }, + /// SysTick clock source selection These bits are used to select the SysTick clock source. Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one hclk1 cycle is introduced, due to the LSE or LSI sampling with hclk1 in the SysTick circuitry. + SYSTICKSEL: packed union { + raw: u2, + value: SYSTICKSEL, + }, + reserved31: u7, + /// Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture When the TIMICSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI/256. When TIMICSEL is cleared, the HSI, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture. Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The clock division must be disabled (TIMICSEL configured to 0) before selecting or changing a clock sources division. + TIMICSEL: packed union { + raw: u1, + value: TIMICSEL, + }, }), - /// DSI Host LTDC VCID Register. - LVCIDR: mmio.Mmio(packed struct(u32) { - /// Virtual Channel ID. - VCID: u2, - padding: u30, + /// RCC peripherals independent clock configuration register 2 + CCIPR2: mmio.Mmio(packed struct(u32) { + reserved12: u12, + /// RNGSEL kernel clock source selection These bits allow to select the RNG kernel clock source. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + RNGSEL: packed union { + raw: u2, + value: RNGSEL, + }, + padding: u18, }), - /// DSI Host LTDC Color Coding Register. - LCOLCR: mmio.Mmio(packed struct(u32) { - /// Color Coding. - COLC: u4, - reserved8: u4, - /// Loosely Packet Enable. - LPE: u1, - padding: u23, + /// RCC peripherals independent clock configuration register 3 + CCIPR3: mmio.Mmio(packed struct(u32) { + /// LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The LPUART1 is functional in Stop modes only when the kernel clock is HSI or LSE. + LPUART1SEL: packed union { + raw: u2, + value: LPUARTSEL, + }, + reserved3: u1, + /// SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The SPI3 is functional in Stop modes only when the kernel clock is HSI. + SPI3SEL: packed union { + raw: u2, + value: SPI3SEL, + }, + reserved6: u1, + /// I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The I2C3 is functional in Stop modes only when the kernel clock is HSI + I2C3SEL: packed union { + raw: u2, + value: I2C3SEL, + }, + reserved10: u2, + /// LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The LPTIM1 is functional in Stop modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1. + LPTIM1SEL: packed union { + raw: u2, + value: LPTIM1SEL, + }, + /// ADC4 kernel clock source selection These bits are used to select the ADC4 kernel clock source. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. others: reserved Note: The ADC4 is functional in Stop modes only when the kernel clock is HSI. + ADCSEL: packed union { + raw: u3, + value: ADCSEL, + }, + padding: u17, }), - /// DSI Host LTDC Polarity Configuration Register. - LPCR: mmio.Mmio(packed struct(u32) { - /// Data Enable Polarity. - DEP: u1, - /// VSYNC Polarity. - VSP: u1, - /// HSYNC Polarity. - HSP: u1, - padding: u29, + reserved240: [4]u8, + /// RCC backup domain control register + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enable Set and cleared by software. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSEON: u1, + /// LSE oscillator ready Set and cleared by hardware to indicate when the external 32�kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSERDY: u1, + /// LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32�kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSEBYP: u1, + /// LSE oscillator drive capability Set by software to modulate the drive capability of the LSE oscillator. LSEDRV must be programmed to a different value than 0 before enabling the LSE oscillator in ‘Xtal’ mode. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The oscillator is in ‘Xtal mode’ when it is not in bypass mode. + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// Low speed external clock security enable Set by software to enable the LSECSS. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware) and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD�=�1). In that case, the software must disable the LSECSSON bit. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSECSSON: u1, + /// Low speed external clock security, LSE failure Detection Set by hardware to indicate when a failure is detected by the LSECCS on the external 32�kHz oscillator. Reset when LSCSSON bit is cleared. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSECSSD: u1, + /// LSE system clock (LSESYS) enable Set by software to enable the LSE system clock generated by RCC. The lsesys clock is used for peripherals (USART, LPUART, LPTIM, RNG, 2.4 GHz RADIO) and functions (LSCO, MCO, TIM triggers, LPTIM trigger) excluding the RTC, TAMP and LSECSS. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSESYSEN: u1, + /// RTC and TAMP kernel clock source enable and selection Set by software to enable and select the clock source for the RTC. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved11: u1, + /// LSE system clock (LSESYS) ready Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSESYSRDY: u1, + /// LSE clock glitch filter enable Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0). Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSEGFON: u1, + /// LSE trimming These bits are initialized at startup and after OBL_LAUNCH with SBF cleared with the factory-programmed LSE calibration value. Set and cleared by software. These bits must be modified only once after a BOR reset or an OBL_LAUNCH and before enabling LSE with LSEON (when both LSEON = 0 and LSERDY�= 0). Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: OBL_LAUNCH of this field occurs only when SBF is cleared and must then only be started by software when LSE oscillator is disabled, LSEON = 0 and LSERDY = 0. + LSETRIM: packed union { + raw: u2, + value: LSETRIM, + }, + reserved16: u1, + /// Backup domain software reset Set and cleared by software. Can only be accessed secure when one or more features in the RTC or TAMP is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + BDRST: u1, + reserved18: u1, + /// 2.4 GHz RADIO sleep timer kernel clock enable and selection Set and cleared by software. Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + RADIOSTSEL: packed union { + raw: u2, + value: RADIOSTSEL, + }, + reserved24: u4, + /// Low-speed clock output (LSCO) enable Set and cleared by software. Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSCOEN: u1, + /// Low-speed clock output selection Set and cleared by software. Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSCOSEL: packed union { + raw: u1, + value: LSCOSEL, + }, + /// LSI1 oscillator enable Set and cleared by software. Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSI1ON: u1, + /// LSI1 oscillator ready Set and cleared by hardware to indicate when the LSI1 oscillator is stable. After the LSI1ON bit is cleared, LSI1RDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI1 is used by IWDG or RTC, even if LSI1ON = 0. Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSI1RDY: u1, + /// LSI1 Low-speed clock divider configuration Set and cleared by software to enable the LSI1 division. This bit can be written only when the LSI1 is disabled (LSI1ON = 0 and LSI1RDY = 0). The LSI1PREDIV cannot be changed if the LSI1 is used by the IWDG or by the RTC. Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + LSI1PREDIV: packed union { + raw: u1, + value: LSIPREDIV, + }, + padding: u3, }), - /// DSI Host Low-Power mode Configuration Register. - LPMCR: mmio.Mmio(packed struct(u32) { - /// VACT Largest Packet Size. - VLPSIZE: u8, - reserved16: u8, - /// Largest Packet Size. - LPSIZE: u8, - padding: u8, + /// RCC control/status register + CSR: mmio.Mmio(packed struct(u32) { + reserved23: u23, + /// Remove reset flag Set by software to clear the reset flags. Access can be secured by RCC RMVFSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. + RMVF: u1, + reserved25: u1, + /// Option byte loader reset flag Set by hardware when a reset from the option byte loading occurs. Cleared by writing to the RMVF bit. + OBLRSTF: u1, + /// NRST pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. + PINRSTF: u1, + /// BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit. + BORRSTF: u1, + /// Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. + SFTRSTF: u1, + /// Independent watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit. + IWDGRSTF: u1, + /// Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. + WWDGRSTF: u1, + /// Low-power reset flag Set by hardware when a reset occurs due to illegal Stop and Standby modes entry. Cleared by writing to the RMVF bit. + LPWRRSTF: u1, }), - reserved44: [16]u8, - /// DSI Host Protocol Configuration Register. - PCR: mmio.Mmio(packed struct(u32) { - /// EoTp Transmission Enable. - ETTXE: u1, - /// EoTp Reception Enable. - ETRXE: u1, - /// Bus Turn Around Enable. - BTAE: u1, - /// ECC Reception Enable. - ECCRXE: u1, - /// CRC Reception Enable. - CRCRXE: u1, - padding: u27, + reserved272: [24]u8, + /// RCC secure configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// HSI clock configuration and status bits security Set and reset by software. + HSISEC: u1, + /// HSE clock configuration bits, status bits and HSECSS security Set and reset by software. + HSESEC: u1, + reserved3: u1, + /// LSI clock configuration and status bits security Set and reset by software. + LSISEC: u1, + /// LSE clock configuration and status bits security Set and reset by software. + LSESEC: u1, + /// SYSCLK selection, clock output on MCO configuration security Set and reset by software. + SYSCLKSEC: u1, + /// AHBx/APBx prescaler configuration bits security Set and reset by software. + PRESCSEC: u1, + /// PLL1 clock configuration and status bits security Set and reset by software. + PLLSEC: u1, + reserved12: u4, + /// Remove reset flag security Set and reset by software. + RMVFSEC: u1, + padding: u19, }), - /// DSI Host Generic VCID Register. - GVCIDR: mmio.Mmio(packed struct(u32) { - /// Virtual Channel ID. - VCID: u2, + /// RCC privilege configuration register + PRIVCFGR: mmio.Mmio(packed struct(u32) { + /// RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access. + SPRIV: u1, + /// RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure. + NSPRIV: u1, padding: u30, }), - /// DSI Host mode Configuration Register. - MCR: mmio.Mmio(packed struct(u32) { - /// Command mode. - CMDM: u1, - padding: u31, - }), - /// DSI Host Video mode Configuration Register. - VMCR: mmio.Mmio(packed struct(u32) { - /// Video mode Type. - VMT: u2, - reserved8: u6, - /// Low-Power Vertical Sync Active Enable. - LPVSAE: u1, - /// Low-power Vertical Back-Porch Enable. - LPVBPE: u1, - /// Low-power Vertical Front-porch Enable. - LPVFPE: u1, - /// Low-Power Vertical Active Enable. - LPVAE: u1, - /// Low-Power Horizontal Back-Porch Enable. - LPHBPE: u1, - /// Low-Power Horizontal Front-Porch Enable. - LPHFPE: u1, - /// Frame Bus-Turn-Around Acknowledge Enable. - FBTAAE: u1, - /// Low-Power Command Enable. - LPCE: u1, - /// Pattern Generator Enable. - PGE: u1, - reserved20: u3, - /// Pattern Generator mode. - PGM: u1, - reserved24: u3, - /// Pattern Generator Orientation. - PGO: u1, - padding: u7, + reserved512: [232]u8, + /// RCC clock configuration register 2 + CFGR4: mmio.Mmio(packed struct(u32) { + /// AHB5 prescaler when SWS select PLL1 Set and cleared by software to control the division factor of the AHB5 clock (hclk5). Must not be changed when SYSCLK source indicated by SWS is PLL1. When SYSCLK source indicated by SWS is not PLL1: HPRE5 is not taken into account. When SYSCLK source indicated by SWS is PLL1: HPRE5 is taken into account, from the moment the system clock switch occurs Depending on the device voltage range, the software must set these bits correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xx: hclk5 = SYSCLK not divided + HPRE5: packed union { + raw: u3, + value: HPRE5, + }, + reserved4: u1, + /// AHB5 divider when SWS select HSI or HSE Set and reset by software. Set to 1 by hardware when entering Stop 1 mode. When SYSCLK source indicated by SWS is HSI or HSE: HDIV5 is taken into account When SYSCLK source indicated by SWS is PLL1: HDIV5 is taken not taken into account Depending on the device voltage range, the software must set this bit correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table�99). After a write operation to this bit and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. + HDIV5: packed union { + raw: u1, + value: HDIV5, + }, + padding: u27, }), - /// DSI Host Video Packet Configuration Register. - VPCR: mmio.Mmio(packed struct(u32) { - /// Video Packet Size. - VPSIZE: u14, - padding: u18, + reserved520: [4]u8, + /// RCC RADIO peripheral clock enable register + RADIOENR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// 2.4 GHz RADIO baseband kernel clock (aclk) enable Set and cleared by software. Note: The HSE oscillator needs to be enabled by either HSEON or STRADIOCLKON. + BBCLKEN: u1, + reserved16: u14, + /// 2.4 GHz RADIO bus clock enable and HSE oscillator enable by 2.4 GHz RADIO sleep timer wakeup event Set by hardware on a 2.4 GHz RADIO sleep timer wakeup event. Cleared by software writing zero to this bit. Note: Before accessing the 2.4 GHz RADIO registers the RADIOCLKRDY bit must be checked. + STRADIOCLKON: u1, + /// 2.4 GHz RADIO bus clock ready. Set and cleared by hardware to indicate that the 2.4 GHz RADIO bus clock is ready and the 2.4 GHz RADIO registers can be accessed. Note: Once both RADIOEN and STRADIOCLKON are cleared, RADIOCLKRDY goes low after three hclk5 clock cycles. + RADIOCLKRDY: u1, + padding: u14, }), - /// DSI Host Video Chunks Configuration Register. - VCCR: mmio.Mmio(packed struct(u32) { - /// Number of Chunks. - NUMC: u13, - padding: u19, + reserved528: [4]u8, + /// RCC external clock sources calibration register 1 + ECSCR1: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// HSE clock trimming These bits provide user-programmable capacitor trimming value. It can be programmed to adjust the HSE oscillator frequency. + HSETRIM: u6, + padding: u10, }), - /// DSI Host Video Null Packet Configuration Register. - VNPCR: mmio.Mmio(packed struct(u32) { - /// Null Packet Size. - NPSIZE: u13, - padding: u19, + }; + }; + + pub const rcc_wl5 = struct { + pub const ADCSEL = enum(u2) { + /// HSI used as ADC clock source + HSI = 0x1, + /// PLLPCLK used as ADC clock source + PLL1_P = 0x2, + /// SYSCLK used as ADC clock source + SYS = 0x3, + _, + }; + + pub const HPRE = enum(u4) { + /// DCLK not divided + Div1 = 0x0, + /// hclk = SYSCLK divided by 3 + Div3 = 0x1, + /// hclk = SYSCLK divided by 5 + Div5 = 0x2, + /// hclk = SYSCLK divided by 6 + Div6 = 0x5, + /// hclk = SYSCLK divided by 8 + Div10 = 0x6, + /// hclk = SYSCLK divided by 32 + Div32 = 0x7, + /// hclk = SYSCLK divided by 2 + Div2 = 0x8, + /// hclk = SYSCLK divided by 4 + Div4 = 0x9, + /// hclk = SYSCLK divided by 8 + Div8 = 0xa, + /// hclk = SYSCLK divided by 16 + Div16 = 0xb, + /// hclk = SYSCLK divided by 64 + Div64 = 0xc, + /// hclk = SYSCLK divided by 128 + Div128 = 0xd, + /// hclk = SYSCLK divided by 256 + Div256 = 0xe, + /// hclk = SYSCLK divided by 256 + Div512 = 0xf, + _, + }; + + pub const HSEPRE = enum(u1) { + Div1 = 0x0, + Div2 = 0x1, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const MCOPRE = enum(u3) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x1, + /// Division by 4 + Div4 = 0x2, + /// Division by 8 + Div8 = 0x3, + /// Division by 16 + Div16 = 0x4, + _, + }; + + pub const MCOSEL = enum(u4) { + /// No clock + DISABLE = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// MSI oscillator clock selected + MSI = 0x2, + /// HSI oscillator clock selected + HSI = 0x3, + /// HSE oscillator clock selected + HSE = 0x4, + /// Main PLLRCLK clock selected + PLL1_R = 0x5, + /// LSI oscillator clock selected + LSI = 0x6, + /// LSE oscillator clock selected + LSE = 0x8, + /// Main PLLCLK oscillator clock selected + PLL1_P = 0xd, + /// Main PLLQCLK oscillator clock selected + PLL1_Q = 0xe, + _, + }; + + pub const MSIRANGE = enum(u4) { + /// range 0 around 100 kHz + Range100K = 0x0, + /// range 1 around 200 kHz + Range200K = 0x1, + /// range 2 around 400 kHz + Range400K = 0x2, + /// range 3 around 800 kHz + Range800K = 0x3, + /// range 4 around 1 MHz + Range1M = 0x4, + /// range 5 around 2 MHz + Range2M = 0x5, + /// range 6 around 4 MHz + Range4M = 0x6, + /// range 7 around 8 MHz + Range8M = 0x7, + /// range 8 around 16 MHz + Range16M = 0x8, + /// range 9 around 24 MHz + Range24M = 0x9, + /// range 10 around 32 MHz + Range32M = 0xa, + /// range 11 around 48 MHz + Range48M = 0xb, + _, + }; + + pub const MSIRGSEL = enum(u1) { + /// MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register + CSR = 0x0, + /// MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register + CR = 0x1, + }; + + pub const PLLM = enum(u3) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + }; + + pub const PLLN = enum(u7) { + Mul6 = 0x6, + Mul7 = 0x7, + Mul8 = 0x8, + Mul9 = 0x9, + Mul10 = 0xa, + Mul11 = 0xb, + Mul12 = 0xc, + Mul13 = 0xd, + Mul14 = 0xe, + Mul15 = 0xf, + Mul16 = 0x10, + Mul17 = 0x11, + Mul18 = 0x12, + Mul19 = 0x13, + Mul20 = 0x14, + Mul21 = 0x15, + Mul22 = 0x16, + Mul23 = 0x17, + Mul24 = 0x18, + Mul25 = 0x19, + Mul26 = 0x1a, + Mul27 = 0x1b, + Mul28 = 0x1c, + Mul29 = 0x1d, + Mul30 = 0x1e, + Mul31 = 0x1f, + Mul32 = 0x20, + Mul33 = 0x21, + Mul34 = 0x22, + Mul35 = 0x23, + Mul36 = 0x24, + Mul37 = 0x25, + Mul38 = 0x26, + Mul39 = 0x27, + Mul40 = 0x28, + Mul41 = 0x29, + Mul42 = 0x2a, + Mul43 = 0x2b, + Mul44 = 0x2c, + Mul45 = 0x2d, + Mul46 = 0x2e, + Mul47 = 0x2f, + Mul48 = 0x30, + Mul49 = 0x31, + Mul50 = 0x32, + Mul51 = 0x33, + Mul52 = 0x34, + Mul53 = 0x35, + Mul54 = 0x36, + Mul55 = 0x37, + Mul56 = 0x38, + Mul57 = 0x39, + Mul58 = 0x3a, + Mul59 = 0x3b, + Mul60 = 0x3c, + Mul61 = 0x3d, + Mul62 = 0x3e, + Mul63 = 0x3f, + Mul64 = 0x40, + Mul65 = 0x41, + Mul66 = 0x42, + Mul67 = 0x43, + Mul68 = 0x44, + Mul69 = 0x45, + Mul70 = 0x46, + Mul71 = 0x47, + Mul72 = 0x48, + Mul73 = 0x49, + Mul74 = 0x4a, + Mul75 = 0x4b, + Mul76 = 0x4c, + Mul77 = 0x4d, + Mul78 = 0x4e, + Mul79 = 0x4f, + Mul80 = 0x50, + Mul81 = 0x51, + Mul82 = 0x52, + Mul83 = 0x53, + Mul84 = 0x54, + Mul85 = 0x55, + Mul86 = 0x56, + Mul87 = 0x57, + Mul88 = 0x58, + Mul89 = 0x59, + Mul90 = 0x5a, + Mul91 = 0x5b, + Mul92 = 0x5c, + Mul93 = 0x5d, + Mul94 = 0x5e, + Mul95 = 0x5f, + Mul96 = 0x60, + Mul97 = 0x61, + Mul98 = 0x62, + Mul99 = 0x63, + Mul100 = 0x64, + Mul101 = 0x65, + Mul102 = 0x66, + Mul103 = 0x67, + Mul104 = 0x68, + Mul105 = 0x69, + Mul106 = 0x6a, + Mul107 = 0x6b, + Mul108 = 0x6c, + Mul109 = 0x6d, + Mul110 = 0x6e, + Mul111 = 0x6f, + Mul112 = 0x70, + Mul113 = 0x71, + Mul114 = 0x72, + Mul115 = 0x73, + Mul116 = 0x74, + Mul117 = 0x75, + Mul118 = 0x76, + Mul119 = 0x77, + Mul120 = 0x78, + Mul121 = 0x79, + Mul122 = 0x7a, + Mul123 = 0x7b, + Mul124 = 0x7c, + Mul125 = 0x7d, + Mul126 = 0x7e, + Mul127 = 0x7f, + _, + }; + + pub const PLLP = enum(u5) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + Div17 = 0x10, + Div18 = 0x11, + Div19 = 0x12, + Div20 = 0x13, + Div21 = 0x14, + Div22 = 0x15, + Div23 = 0x16, + Div24 = 0x17, + Div25 = 0x18, + Div26 = 0x19, + Div27 = 0x1a, + Div28 = 0x1b, + Div29 = 0x1c, + Div30 = 0x1d, + Div31 = 0x1e, + _, + }; + + pub const PLLQ = enum(u3) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + _, + }; + + pub const PLLR = enum(u3) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + _, + }; + + pub const PLLSRC = enum(u2) { + /// No clock selected as PLL entry clock source + DISABLE = 0x0, + /// MSI selected as PLL entry clock source + MSI = 0x1, + /// HSI selected as PLL entry clock source + HSI = 0x2, + /// HSE selected as PLL entry clock source + HSE = 0x3, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const RNGSEL = enum(u2) { + PLL1_Q = 0x0, + LSI = 0x1, + LSE = 0x2, + MSI = 0x3, + }; + + pub const RTCSEL = enum(u2) { + /// No clock selected + DISABLE = 0x0, + /// LSE oscillator clock selected + LSE = 0x1, + /// LSI oscillator clock selected + LSI = 0x2, + /// HSE oscillator clock divided by 32 selected + HSE = 0x3, + }; + + pub const SW = enum(u2) { + MSI = 0x0, + HSI = 0x1, + HSE = 0x2, + PLL1_R = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// MSI clock enable + MSION: u1, + /// MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) + MSIRDY: u1, + /// MSI clock PLL enable + MSIPLLEN: u1, + /// MSI range control selection + MSIRGSEL: packed union { + raw: u1, + value: MSIRGSEL, + }, + /// MSI clock ranges + MSIRANGE: packed union { + raw: u4, + value: MSIRANGE, + }, + /// HSI clock enable + HSION: u1, + /// HSI always enable for peripheral kernel clocks. + HSIKERON: u1, + /// HSI clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI is ready) + HSIRDY: u1, + /// HSI automatic start from Stop + HSIASFS: u1, + /// HSI kernel clock ready flag for peripherals requests. + HSIKERDY: u1, + reserved16: u3, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + reserved19: u1, + /// HSE Clock security system enable + CSSON: u1, + /// HSE sysclk prescaler + HSEPRE: packed union { + raw: u1, + value: HSEPRE, + }, + /// Enable HSE VDDTCXO output on package pin PB0-VDDTCXO. + HSEBYPPWR: u1, + reserved24: u2, + /// Main PLL enable + PLLON: u1, + /// Main PLL clock ready flag + PLLRDY: u1, + padding: u6, }), - /// DSI Host Video HSA Configuration Register. - VHSACR: mmio.Mmio(packed struct(u32) { - /// Horizontal Synchronism Active duration. - HSA: u12, - padding: u20, + /// Internal clock sources calibration register + ICSCR: mmio.Mmio(packed struct(u32) { + /// MSI clock calibration + MSICAL: u8, + /// MSI clock trimming + MSITRIM: u8, + /// HSI clock calibration + HSICAL: u8, + /// HSI clock trimming + HSITRIM: u7, + padding: u1, }), - /// DSI Host Video HBP Configuration Register. - VHBPCR: mmio.Mmio(packed struct(u32) { - /// Horizontal Back-Porch duration. - HBP: u12, - padding: u20, + /// Clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u2, + value: SW, + }, + /// System clock switch status + SWS: packed union { + raw: u2, + value: SW, + }, + /// HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.) + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// PCLK1 low-speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + /// PCLK2 high-speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + reserved15: u1, + /// Wakeup from Stop and CSS backup clock selection + STOPWUCK: u1, + /// HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1) + HPREF: u1, + /// PCLK1 prescaler flag (APB1) + PPRE1F: u1, + /// PCLK2 prescaler flag (APB2) + PPRE2F: u1, + reserved24: u5, + /// Microcontroller clock output + MCOSEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// Microcontroller clock output prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, + }, + padding: u1, }), - /// DSI Host Video Line Configuration Register. - VLCR: mmio.Mmio(packed struct(u32) { - /// Horizontal Line duration. - HLINE: u15, - padding: u17, + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// Main PLL entry clock source + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + reserved4: u2, + /// Division factor for the main PLL input clock + PLLM: packed union { + raw: u3, + value: PLLM, + }, + reserved8: u1, + /// Main PLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, + }, + reserved16: u1, + /// Main PLL PLLPCLK output enable + PLLPEN: u1, + /// Main PLL division factor for PLLPCLK. + PLLP: packed union { + raw: u5, + value: PLLP, + }, + reserved24: u2, + /// Main PLL PLLQCLK output enable + PLLQEN: u1, + /// Main PLL division factor for PLLQCLK + PLLQ: packed union { + raw: u3, + value: PLLQ, + }, + /// Main PLL PLLRCLK output enable + PLLREN: u1, + /// Main PLL division factor for PLLRCLK + PLLR: packed union { + raw: u3, + value: PLLR, + }, }), - /// DSI Host Video VSA Configuration Register. - VVSACR: mmio.Mmio(packed struct(u32) { - /// Vertical Synchronism Active duration. - VSA: u10, + reserved24: [8]u8, + /// Clock interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// MSI ready interrupt enable + MSIRDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// PLL ready interrupt enable + PLLRDYIE: u1, + reserved9: u3, + /// LSE clock security system interrupt enable + LSECSSIE: u1, padding: u22, }), - /// DSI Host Video VBP Configuration Register. - VVBPCR: mmio.Mmio(packed struct(u32) { - /// Vertical Back-Porch duration. - VBP: u10, + /// Clock interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// MSI ready interrupt flag + MSIRDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// PLL ready interrupt flag + PLLRDYF: u1, + reserved8: u2, + /// HSE Clock security system interrupt flag + CSSF: u1, + /// LSE Clock security system interrupt flag + LSECSSF: u1, padding: u22, }), - /// DSI Host Video VFP Configuration Register. - VVFPCR: mmio.Mmio(packed struct(u32) { - /// Vertical Front-Porch duration. - VFP: u10, + /// Clock interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// MSI ready interrupt clear + MSIRDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// PLL ready interrupt clear + PLLRDYC: u1, + reserved8: u2, + /// HSE Clock security system interrupt clear + CSSC: u1, + /// LSE Clock security system interrupt clear + LSECSSC: u1, padding: u22, }), - /// DSI Host Video VA Configuration Register. - VVACR: mmio.Mmio(packed struct(u32) { - /// Vertical Active duration. - VA: u14, - padding: u18, - }), - /// DSI Host LTDC Command Configuration Register. - LCCR: mmio.Mmio(packed struct(u32) { - /// Command Size. - CMDSIZE: u16, - padding: u16, + reserved40: [4]u8, + /// AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// DMA1 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + /// DMAMUX1 reset + DMAMUX1RST: u1, + reserved12: u9, + /// CRC reset + CRCRST: u1, + padding: u19, }), - /// DSI Host Command mode Configuration Register. - CMCR: mmio.Mmio(packed struct(u32) { - /// Tearing Effect Acknowledge Request Enable. - TEARE: u1, - /// Acknowledge Request Enable. - ARE: u1, - reserved8: u6, - /// Generic Short Write Zero parameters Transmission. - GSW0TX: u1, - /// Generic Short Write One parameters Transmission. - GSW1TX: u1, - /// Generic Short Write Two parameters Transmission. - GSW2TX: u1, - /// Generic Short Read Zero parameters Transmission. - GSR0TX: u1, - /// Generic Short Read One parameters Transmission. - GSR1TX: u1, - /// Generic Short Read Two parameters Transmission. - GSR2TX: u1, - /// Generic Long Write Transmission. - GLWTX: u1, - reserved16: u1, - /// DCS Short Write Zero parameter Transmission. - DSW0TX: u1, - /// DCS Short Read One parameter Transmission. - DSW1TX: u1, - /// DCS Short Read Zero parameter Transmission. - DSR0TX: u1, - /// DCS Long Write Transmission. - DLWTX: u1, - reserved24: u4, - /// Maximum Read Packet Size. - MRDPS: u1, - padding: u7, + /// AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + reserved7: u4, + /// IO port H reset + GPIOHRST: u1, + padding: u24, }), - /// DSI Host Generic Header Configuration Register. - GHCR: mmio.Mmio(packed struct(u32) { - /// Type. - DT: u6, - /// Channel. - VCID: u2, - /// WordCount LSB. - WCLSB: u8, - /// WordCount MSB. - WCMSB: u8, - padding: u8, + /// AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// PKARST + PKARST: u1, + /// AESRST + AESRST: u1, + /// RNGRST + RNGRST: u1, + /// HSEMRST + HSEMRST: u1, + /// IPCCRST + IPCCRST: u1, + reserved25: u4, + /// Flash interface reset + FLASHRST: u1, + padding: u6, }), - /// DSI Host Generic Payload Data Register. - GPDR: mmio.Mmio(packed struct(u32) { - /// Payload Byte 1. - DATA1: u8, - /// Payload Byte 2. - DATA2: u8, - /// Payload Byte 3. - DATA3: u8, - /// Payload Byte 4. - DATA4: u8, + reserved56: [4]u8, + /// APB1 peripheral reset register 1 + APB1RSTR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer reset + TIM2RST: u1, + reserved14: u13, + /// SPI2 reset + SPI2RST: u1, + reserved17: u2, + /// USART2 reset + USART2RST: u1, + reserved21: u3, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// I2C3 reset + I2C3RST: u1, + reserved29: u5, + /// DAC reset + DACRST: u1, + reserved31: u1, + /// Low Power Timer 1 reset + LPTIM1RST: u1, }), - /// DSI Host Generic Packet Status Register. - GPSR: mmio.Mmio(packed struct(u32) { - /// Command FIFO Empty. - CMDFE: u1, - /// Command FIFO Full. - CMDFF: u1, - /// Payload Write FIFO Empty. - PWRFE: u1, - /// Payload Write FIFO Full. - PWRFF: u1, - /// Payload Read FIFO Empty. - PRDFE: u1, - /// Payload Read FIFO Full. - PRDFF: u1, - /// Read Command Busy. - RCB: u1, + /// APB1 peripheral reset register 2 + APB1RSTR2: mmio.Mmio(packed struct(u32) { + /// Low-power UART 1 reset + LPUART1RST: u1, + reserved5: u4, + /// Low-power timer 2 reset + LPTIM2RST: u1, + /// Low-power timer 3 reset + LPTIM3RST: u1, padding: u25, }), - /// DSI Host Timeout Counter Configuration Register 0. - TCCR0: mmio.Mmio(packed struct(u32) { - /// Low-power Reception Timeout Counter. - LPRX_TOCNT: u16, - /// High-Speed Transmission Timeout Counter. - HSTX_TOCNT: u16, - }), - /// DSI Host Timeout Counter Configuration Register 1. - TCCR1: mmio.Mmio(packed struct(u32) { - /// High-Speed Read Timeout Counter. - HSRD_TOCNT: u16, - padding: u16, - }), - /// DSI Host Timeout Counter Configuration Register 2. - TCCR2: mmio.Mmio(packed struct(u32) { - /// Low-Power Read Timeout Counter. - LPRD_TOCNT: u16, - padding: u16, - }), - /// DSI Host Timeout Counter Configuration Register 3. - TCCR3: mmio.Mmio(packed struct(u32) { - /// High-Speed Write Timeout Counter. - HSWR_TOCNT: u16, - reserved24: u8, - /// Presp mode. - PM: u1, - padding: u7, + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// ADC reset + ADCRST: u1, + reserved11: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI1 reset + SPI1RST: u1, + reserved14: u1, + /// USART1 reset + USART1RST: u1, + reserved17: u2, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + padding: u13, }), - /// DSI Host Timeout Counter Configuration Register 4. - TCCR4: mmio.Mmio(packed struct(u32) { - /// Low-Power Write Timeout Counter. - LSWR_TOCNT: u16, - padding: u16, + /// APB3 peripheral reset register + APB3RSTR: mmio.Mmio(packed struct(u32) { + /// Sub-GHz radio SPI reset + SUBGHZSPIRST: u1, + padding: u31, }), - /// DSI Host Timeout Counter Configuration Register 5. - TCCR5: mmio.Mmio(packed struct(u32) { - /// Bus-Turn-Around Timeout Counter. - BTA_TOCNT: u16, - padding: u16, + /// AHB1 peripheral clock enable register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// CPU1 DMA1 clock enable + DMA1EN: u1, + /// CPU1 DMA2 clock enable + DMA2EN: u1, + /// CPU1 DMAMUX1 clock enable + DMAMUX1EN: u1, + reserved12: u9, + /// CPU1 CRC clock enable + CRCEN: u1, + padding: u19, }), - reserved148: [4]u8, - /// DSI Host Clock Lane Configuration Register. - CLCR: mmio.Mmio(packed struct(u32) { - /// D-PHY Clock Control. - DPCC: u1, - /// Automatic Clock lane Control. - ACR: u1, - padding: u30, + /// AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// CPU1 IO port A clock enable + GPIOAEN: u1, + /// CPU1 IO port B clock enable + GPIOBEN: u1, + /// CPU1 IO port C clock enable + GPIOCEN: u1, + reserved7: u4, + /// CPU1 IO port H clock enable + GPIOHEN: u1, + padding: u24, }), - /// DSI Host Clock Lane Timer Configuration Register. - CLTCR: mmio.Mmio(packed struct(u32) { - /// Low-Power to High-Speed Time. - LP2HS_TIME: u10, - reserved16: u6, - /// High-Speed to Low-Power Time. - HS2LP_TIME: u10, + /// AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// PKAEN + PKAEN: u1, + /// AESEN + AESEN: u1, + /// RNGEN + RNGEN: u1, + /// HSEMEN + HSEMEN: u1, + /// IPCCEN + IPCCEN: u1, + reserved25: u4, + /// CPU1 Flash interface clock enable + FLASHEN: u1, padding: u6, }), - /// DSI Host Data Lane Timer Configuration Register. - DLTCR: mmio.Mmio(packed struct(u32) { - /// Maximum Read Time. - MRD_TIME: u15, - reserved16: u1, - /// Low-Power To High-Speed Time. - LP2HS_TIME: u8, - /// High-Speed To Low-Power Time. - HS2LP_TIME: u8, - }), - /// DSI Host PHY Control Register. - PCTLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Digital Enable. - DEN: u1, - /// Clock Enable. - CKE: u1, - padding: u29, + reserved88: [4]u8, + /// APB1 peripheral clock enable register 1 + APB1ENR1: mmio.Mmio(packed struct(u32) { + /// CPU1 TIM2 timer clock enable + TIM2EN: u1, + reserved10: u9, + /// CPU1 RTC APB clock enable + RTCAPBEN: u1, + /// CPU1 Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// CPU1 SPI2 clock enable + SPI2EN: u1, + reserved17: u2, + /// CPU1 USART2 clock enable + USART2EN: u1, + reserved21: u3, + /// CPU1 I2C1 clocks enable + I2C1EN: u1, + /// CPU1 I2C2 clocks enable + I2C2EN: u1, + /// CPU1 I2C3 clocks enable + I2C3EN: u1, + reserved29: u5, + /// CPU1 DAC clock enable + DACEN: u1, + reserved31: u1, + /// CPU1 Low power timer 1 clocks enable + LPTIM1EN: u1, }), - /// DSI Host PHY Configuration Register. - PCONFR: mmio.Mmio(packed struct(u32) { - /// Number of Lanes. - NL: u2, - reserved8: u6, - /// Stop Wait Time. - SW_TIME: u8, - padding: u16, + /// APB1 peripheral clock enable register 2 + APB1ENR2: mmio.Mmio(packed struct(u32) { + /// CPU1 Low power UART 1 clocks enable + LPUART1EN: u1, + reserved5: u4, + /// CPU1 Low power timer 2 clocks enable + LPTIM2EN: u1, + /// CPU1 Low power timer 3 clocks enable + LPTIM3EN: u1, + padding: u25, }), - /// DSI Host PHY ULPS Control Register. - PUCR: mmio.Mmio(packed struct(u32) { - /// ULPS Request on Clock Lane. - URCL: u1, - /// ULPS Exit on Clock Lane. - UECL: u1, - /// ULPS Request on Data Lane. - URDL: u1, - /// ULPS Exit on Data Lane. - UEDL: u1, - padding: u28, + /// APB2 peripheral clock enable register + APB2ENR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// CPU1 ADC clocks enable + ADCEN: u1, + reserved11: u1, + /// CPU1 TIM1 timer clock enable + TIM1EN: u1, + /// CPU1 SPI1 clock enable + SPI1EN: u1, + reserved14: u1, + /// CPU1 USART1clocks enable + USART1EN: u1, + reserved17: u2, + /// CPU1 TIM16 timer clock enable + TIM16EN: u1, + /// CPU1 TIM17 timer clock enable + TIM17EN: u1, + padding: u13, }), - /// DSI Host PHY TX Triggers Configuration Register. - PTTCR: mmio.Mmio(packed struct(u32) { - /// Transmission Trigger. - TX_TRIG: u4, - padding: u28, + /// APB3 peripheral clock enable register + APB3ENR: mmio.Mmio(packed struct(u32) { + /// sub-GHz radio SPI clock enable + SUBGHZSPIEN: u1, + padding: u31, }), - /// DSI Host PHY Status Register. - PSR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// PHY Direction. - PD: u1, - /// PHY Stop State Clock lane. - PSSC: u1, - /// ULPS Active Not Clock lane. - UANC: u1, - /// PHY Stop State lane 0. - PSS0: u1, - /// ULPS Active Not lane 1. - UAN0: u1, - /// RX ULPS Escape lane 0. - RUE0: u1, - /// PHY Stop State lane 1. - PSS1: u1, - /// ULPS Active Not lane 1. - UAN1: u1, - padding: u23, + /// AHB1 peripheral clocks enable in Sleep modes register + AHB1SMENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable during CPU1 CSleep mode. + DMA1SMEN: u1, + /// DMA2 clock enable during CPU1 CSleep mode + DMA2SMEN: u1, + /// DMAMUX1 clock enable during CPU1 CSleep mode. + DMAMUX1SMEN: u1, + reserved12: u9, + /// CRC clock enable during CPU1 CSleep mode. + CRCSMEN: u1, + padding: u19, }), - reserved188: [8]u8, - /// DSI Host Interrupt & Status Register 0. - ISR0: mmio.Mmio(packed struct(u32) { - /// Acknowledge Error 0. - AE0: u1, - /// Acknowledge Error 1. - AE1: u1, - /// Acknowledge Error 2. - AE2: u1, - /// Acknowledge Error 3. - AE3: u1, - /// Acknowledge Error 4. - AE4: u1, - /// Acknowledge Error 5. - AE5: u1, - /// Acknowledge Error 6. - AE6: u1, - /// Acknowledge Error 7. - AE7: u1, - /// Acknowledge Error 8. - AE8: u1, - /// Acknowledge Error 9. - AE9: u1, - /// Acknowledge Error 10. - AE10: u1, - /// Acknowledge Error 11. - AE11: u1, - /// Acknowledge Error 12. - AE12: u1, - /// Acknowledge Error 13. - AE13: u1, - /// Acknowledge Error 14. - AE14: u1, - /// Acknowledge Error 15. - AE15: u1, - /// PHY Error 0. - PE0: u1, - /// PHY Error 1. - PE1: u1, - /// PHY Error 2. - PE2: u1, - /// PHY Error 3. - PE3: u1, - /// PHY Error 4. - PE4: u1, - padding: u11, + /// AHB2 peripheral clocks enable in Sleep modes register + AHB2SMENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable during CPU1 CSleep mode. + GPIOASMEN: u1, + /// IO port B clock enable during CPU1 CSleep mode. + GPIOBSMEN: u1, + /// IO port C clock enable during CPU1 CSleep mode. + GPIOCSMEN: u1, + reserved7: u4, + /// IO port H clock enable during CPU1 CSleep mode. + GPIOHSMEN: u1, + padding: u24, }), - /// DSI Host Interrupt & Status Register 1. - ISR1: mmio.Mmio(packed struct(u32) { - /// Timeout High-Speed Transmission. - TOHSTX: u1, - /// Timeout Low-Power Reception. - TOLPRX: u1, - /// ECC Single-bit Error. - ECCSE: u1, - /// ECC Multi-bit Error. - ECCME: u1, - /// CRC Error. - CRCE: u1, - /// Packet Size Error. - PSE: u1, - /// EoTp Error. - EOTPE: u1, - /// LTDC Payload Write Error. - LPWRE: u1, - /// Generic Command Write Error. - GCWRE: u1, - /// Generic Payload Write Error. - GPWRE: u1, - /// Generic Payload Transmit Error. - GPTXE: u1, - /// Generic Payload Read Error. - GPRDE: u1, - /// Generic Payload Receive Error. - GPRXE: u1, - padding: u19, + /// AHB3 peripheral clocks enable in Sleep and Stop modes register + AHB3SMENR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// PKA accelerator clock enable during CPU1 CSleep mode. + PKASMEN: u1, + /// AES accelerator clock enable during CPU1 CSleep mode. + AESSMEN: u1, + /// True RNG clocks enable during CPU1 Csleep and CStop modes + RNGSMEN: u1, + reserved23: u4, + /// SRAM1 interface clock enable during CPU1 CSleep mode. + SRAM1SMEN: u1, + /// SRAM2 memory interface clock enable during CPU1 CSleep mode + SRAM2SMEN: u1, + /// Flash interface clock enable during CPU1 CSleep mode. + FLASHSMEN: u1, + padding: u6, }), - /// DSI Host Interrupt Enable Register 0. - IER0: mmio.Mmio(packed struct(u32) { - /// Acknowledge Error 0 Interrupt Enable. - AE0IE: u1, - /// Acknowledge Error 1 Interrupt Enable. - AE1IE: u1, - /// Acknowledge Error 2 Interrupt Enable. - AE2IE: u1, - /// Acknowledge Error 3 Interrupt Enable. - AE3IE: u1, - /// Acknowledge Error 4 Interrupt Enable. - AE4IE: u1, - /// Acknowledge Error 5 Interrupt Enable. - AE5IE: u1, - /// Acknowledge Error 6 Interrupt Enable. - AE6IE: u1, - /// Acknowledge Error 7 Interrupt Enable. - AE7IE: u1, - /// Acknowledge Error 8 Interrupt Enable. - AE8IE: u1, - /// Acknowledge Error 9 Interrupt Enable. - AE9IE: u1, - /// Acknowledge Error 10 Interrupt Enable. - AE10IE: u1, - /// Acknowledge Error 11 Interrupt Enable. - AE11IE: u1, - /// Acknowledge Error 12 Interrupt Enable. - AE12IE: u1, - /// Acknowledge Error 13 Interrupt Enable. - AE13IE: u1, - /// Acknowledge Error 14 Interrupt Enable. - AE14IE: u1, - /// Acknowledge Error 15 Interrupt Enable. - AE15IE: u1, - /// PHY Error 0 Interrupt Enable. - PE0IE: u1, - /// PHY Error 1 Interrupt Enable. - PE1IE: u1, - /// PHY Error 2 Interrupt Enable. - PE2IE: u1, - /// PHY Error 3 Interrupt Enable. - PE3IE: u1, - /// PHY Error 4 Interrupt Enable. - PE4IE: u1, - padding: u11, + reserved120: [4]u8, + /// APB1 peripheral clocks enable in Sleep mode register 1 + APB1SMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clock enable during CPU1 CSleep mode. + TIM2SMEN: u1, + reserved10: u9, + /// RTC bus clock enable during CPU1 CSleep mode. + RTCAPBSMEN: u1, + /// Window watchdog clocks enable during CPU1 CSleep mode. + WWDGSMEN: u1, + reserved14: u2, + /// SPI2 clock enable during CPU1 CSleep mode. + SPI2SMEN: u1, + reserved17: u2, + /// USART2 clock enable during CPU1 CSleep mode. + USART2SMEN: u1, + reserved21: u3, + /// I2C1 clock enable during CPU1 Csleep and CStop modes + I2C1SMEN: u1, + /// I2C2 clock enable during CPU1 Csleep and CStop modes + I2C2SMEN: u1, + /// I2C3 clock enable during CPU1 Csleep and CStop modes + I2C3SMEN: u1, + reserved29: u5, + /// DAC clock enable during CPU1 CSleep mode. + DACSMEN: u1, + reserved31: u1, + /// Low power timer 1 clock enable during CPU1 Csleep and CStop mode + LPTIM1SMEN: u1, }), - /// DSI Host Interrupt Enable Register 1. - IER1: mmio.Mmio(packed struct(u32) { - /// Timeout High-Speed Transmission Interrupt Enable. - TOHSTXIE: u1, - /// Timeout Low-Power Reception Interrupt Enable. - TOLPRXIE: u1, - /// ECC Single-bit Error Interrupt Enable. - ECCSEIE: u1, - /// ECC Multi-bit Error Interrupt Enable. - ECCMEIE: u1, - /// CRC Error Interrupt Enable. - CRCEIE: u1, - /// Packet Size Error Interrupt Enable. - PSEIE: u1, - /// EoTp Error Interrupt Enable. - EOTPEIE: u1, - /// LTDC Payload Write Error Interrupt Enable. - LPWREIE: u1, - /// Generic Command Write Error Interrupt Enable. - GCWREIE: u1, - /// Generic Payload Write Error Interrupt Enable. - GPWREIE: u1, - /// Generic Payload Transmit Error Interrupt Enable. - GPTXEIE: u1, - /// Generic Payload Read Error Interrupt Enable. - GPRDEIE: u1, - /// Generic Payload Receive Error Interrupt Enable. - GPRXEIE: u1, - padding: u19, + /// APB1 peripheral clocks enable in Sleep mode register 2 + APB1SMENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clock enable during CPU1 Csleep and CStop modes. + LPUART1SMEN: u1, + reserved5: u4, + /// Low power timer 2 clock enable during CPU1 Csleep and CStop modes + LPTIM2SMEN: u1, + /// Low power timer 3 clock enable during CPU1 Csleep and CStop modes + LPTIM3SMEN: u1, + padding: u25, }), - reserved216: [12]u8, - /// DSI Host Force Interrupt Register 0. - FIR0: mmio.Mmio(packed struct(u32) { - /// Force Acknowledge Error 0. - FAE0: u1, - /// Force Acknowledge Error 1. - FAE1: u1, - /// Force Acknowledge Error 2. - FAE2: u1, - /// Force Acknowledge Error 3. - FAE3: u1, - /// Force Acknowledge Error 4. - FAE4: u1, - /// Force Acknowledge Error 5. - FAE5: u1, - /// Force Acknowledge Error 6. - FAE6: u1, - /// Force Acknowledge Error 7. - FAE7: u1, - /// Force Acknowledge Error 8. - FAE8: u1, - /// Force Acknowledge Error 9. - FAE9: u1, - /// Force Acknowledge Error 10. - FAE10: u1, - /// Force Acknowledge Error 11. - FAE11: u1, - /// Force Acknowledge Error 12. - FAE12: u1, - /// Force Acknowledge Error 13. - FAE13: u1, - /// Force Acknowledge Error 14. - FAE14: u1, - /// Force Acknowledge Error 15. - FAE15: u1, - /// Force PHY Error 0. - FPE0: u1, - /// Force PHY Error 1. - FPE1: u1, - /// Force PHY Error 2. - FPE2: u1, - /// Force PHY Error 3. - FPE3: u1, - /// Force PHY Error 4. - FPE4: u1, - padding: u11, + /// APB2 peripheral clocks enable in Sleep mode register + APB2SMENR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// ADC clocks enable during CPU1 Csleep and CStop modes + ADCSMEN: u1, + reserved11: u1, + /// TIM1 timer clock enable during CPU1 CSleep mode. + TIM1SMEN: u1, + /// SPI1 clock enable during CPU1 CSleep mode. + SPI1SMEN: u1, + reserved14: u1, + /// USART1 clock enable during CPU1 Csleep and CStop modes. + USART1SMEN: u1, + reserved17: u2, + /// TIM16 timer clock enable during CPU1 CSleep mode. + TIM16SMEN: u1, + /// TIM17 timer clock enable during CPU1 CSleep mode. + TIM17SMEN: u1, + padding: u13, }), - /// DSI Host Force Interrupt Register 1. - FIR1: mmio.Mmio(packed struct(u32) { - /// Force Timeout High-Speed Transmission. - FTOHSTX: u1, - /// Force Timeout Low-Power Reception. - FTOLPRX: u1, - /// Force ECC Single-bit Error. - FECCSE: u1, - /// Force ECC Multi-bit Error. - FECCME: u1, - /// Force CRC Error. - FCRCE: u1, - /// Force Packet Size Error. - FPSE: u1, - /// Force EoTp Error. - FEOTPE: u1, - /// Force LTDC Payload Write Error. - FLPWRE: u1, - /// Force Generic Command Write Error. - FGCWRE: u1, - /// Force Generic Payload Write Error. - FGPWRE: u1, - /// Force Generic Payload Transmit Error. - FGPTXE: u1, - /// Force Generic Payload Read Error. - FGPRDE: u1, - /// Force Generic Payload Receive Error. - FGPRXE: u1, - padding: u19, + /// APB3 peripheral clock enable in Sleep mode register + APB3SMENR: mmio.Mmio(packed struct(u32) { + /// Sub-GHz radio SPI clock enable during Sleep and Stop modes + SUBGHZSPISMEN: u1, + padding: u31, }), - reserved256: [32]u8, - /// DSI Host Video Shadow Control Register. - VSCR: mmio.Mmio(packed struct(u32) { - /// Enable. - EN: u1, - reserved8: u7, - /// Update Register. - UR: u1, - padding: u23, + /// Peripherals independent clock configuration register + CCIPR: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SEL: u2, + /// USART2 clock source selection + USART2SEL: u2, + reserved8: u4, + /// SPI2 I2S clock source selection + SPI2SEL: u2, + /// LPUART1 clock source selection + LPUART1SEL: u2, + /// I2C1 clock source selection + I2C1SEL: u2, + /// I2C2 clock source selection + I2C2SEL: u2, + /// I2C3 clock source selection + I2C3SEL: u2, + /// Low power timer 1 clock source selection + LPTIM1SEL: u2, + /// Low power timer 2 clock source selection + LPTIM2SEL: u2, + /// Low power timer 3 clock source selection + LPTIM3SEL: u2, + reserved28: u4, + /// ADC clock source selection + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, + /// RNG clock source selection + RNGSEL: packed union { + raw: u2, + value: RNGSEL, + }, }), - reserved268: [8]u8, - /// DSI Host LTDC Current VCID Register. - LCVCIDR: mmio.Mmio(packed struct(u32) { - /// Virtual Channel ID. - VCID: u2, - padding: u30, + reserved144: [4]u8, + /// Backup domain control register + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enable + LSEON: u1, + /// LSE oscillator ready + LSERDY: u1, + /// LSE oscillator bypass + LSEBYP: u1, + /// LSE oscillator drive capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// CSS on LSE enable + LSECSSON: u1, + /// CSS on LSE failure Detection + LSECSSD: u1, + /// LSE system clock enable + LSESYSEN: u1, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved11: u1, + /// LSE system clock ready + LSESYSRDY: u1, + reserved15: u3, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + reserved24: u7, + /// Low speed clock output enable + LSCOEN: u1, + /// Low speed clock output selection + LSCOSEL: u1, + padding: u6, }), - /// DSI Host LTDC Current Color Coding Register. - LCCCR: mmio.Mmio(packed struct(u32) { - /// Color Coding. - COLC: u4, - reserved8: u4, - /// Loosely Packed Enable. - LPE: u1, - padding: u23, + /// Control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// LSI oscillator enable + LSION: u1, + /// LSI oscillator ready + LSIRDY: u1, + reserved4: u2, + /// LSI frequency prescaler + LSIPRE: u1, + reserved8: u3, + /// MSI clock ranges + MSISRANGE: u4, + reserved14: u2, + /// Radio in reset status flag + RFRSTF: u1, + /// Radio reset + RFRST: u1, + reserved23: u7, + /// Remove reset flag + RMVF: u1, + /// Radio illegal access flag + RFILARSTF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// Pin reset flag + PINRSTF: u1, + /// BOR flag + BORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent window watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, }), - reserved280: [4]u8, - /// DSI Host Low-Power mode Current Configuration Register. - LPMCCR: mmio.Mmio(packed struct(u32) { - /// VACT Largest Packet Size. - VLPSIZE: u8, + reserved264: [112]u8, + /// Extended clock recovery register + EXTCFGR: mmio.Mmio(packed struct(u32) { + /// HCLK3 shared prescaler (AHB3, Flash, and SRAM2) + SHDHPRE: packed union { + raw: u4, + value: HPRE, + }, + /// [dual core device only] HCLK2 prescaler (CPU2) + C2HPRE: packed union { + raw: u4, + value: HPRE, + }, reserved16: u8, - /// Largest Packet Size. - LPSIZE: u8, - padding: u8, - }), - reserved312: [28]u8, - /// DSI Host Video mode Current Configuration Register. - VMCCR: mmio.Mmio(packed struct(u32) { - /// Video mode Type. - VMT: u2, - /// Low-Power Vertical Sync time Enable. - LPVSAE: u1, - /// Low-power Vertical Back-Porch Enable. - LPVBPE: u1, - /// Low-power Vertical Front-Porch Enable. - LPVFPE: u1, - /// Low-Power Vertical Active Enable. - LPVAE: u1, - /// Low-power Horizontal Back-Porch Enable. - LPHBPE: u1, - /// Low-Power Horizontal Front-Porch Enable. - LPHFE: u1, - /// Frame BTA Acknowledge Enable. - FBTAAE: u1, - /// Low-Power Command Enable. - LPCE: u1, - padding: u22, - }), - /// DSI Host Video Packet Current Configuration Register. - VPCCR: mmio.Mmio(packed struct(u32) { - /// Video Packet Size. - VPSIZE: u14, - padding: u18, - }), - /// DSI Host Video Chunks Current Configuration Register. - VCCCR: mmio.Mmio(packed struct(u32) { - /// Number of Chunks. - NUMC: u13, - padding: u19, + /// HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2) + SHDHPREF: u1, + /// CLK2 prescaler flag (CPU2) + C2HPREF: u1, + padding: u14, }), - /// DSI Host Video Null Packet Current Configuration Register. - VNPCCR: mmio.Mmio(packed struct(u32) { - /// Null Packet Size. - NPSIZE: u13, + reserved328: [60]u8, + /// CPU2 AHB1 peripheral clock enable register + C2AHB1ENR: mmio.Mmio(packed struct(u32) { + /// CPU2 DMA1 clock enable + DMA1EN: u1, + /// CPU2 DMA2 clock enable + DMA2EN: u1, + /// CPU2 DMAMUX1 clock enable + DMAMUX1EN: u1, + reserved12: u9, + /// CPU2 CRC clock enable + CRCEN: u1, padding: u19, }), - /// DSI Host Video HSA Current Configuration Register. - VHSACCR: mmio.Mmio(packed struct(u32) { - /// Horizontal Synchronism Active duration. - HSA: u12, - padding: u20, + /// CPU2 AHB2 peripheral clock enable register + C2AHB2ENR: mmio.Mmio(packed struct(u32) { + /// CPU2 IO port A clock enable + GPIOAEN: u1, + /// CPU2 IO port B clock enable + GPIOBEN: u1, + /// CPU2 IO port C clock enable + GPIOCEN: u1, + reserved7: u4, + /// CPU2 IO port H clock enable + GPIOHEN: u1, + padding: u24, }), - /// DSI Host Video HBP Current Configuration Register. - VHBPCCR: mmio.Mmio(packed struct(u32) { - /// Horizontal Back-Porch duration. - HBP: u12, - padding: u20, + /// CPU2 AHB3 peripheral clock enable register [dual core device only] + C2AHB3ENR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// CPU2 PKA accelerator clock enable + PKAEN: u1, + /// CPU2 AES accelerator clock enable + AESEN: u1, + /// CPU2 True RNG clocks enable + RNGEN: u1, + /// CPU2 HSEM clock enable + HSEMEN: u1, + /// CPU2 IPCC interface clock enable + IPCCEN: u1, + reserved25: u4, + /// CPU2 Flash interface clock enable + FLASHEN: u1, + padding: u6, }), - /// DSI Host Video Line Current Configuration Register. - VLCCR: mmio.Mmio(packed struct(u32) { - /// Horizontal Line duration. - HLINE: u15, - padding: u17, + reserved344: [4]u8, + /// CPU2 APB1 peripheral clock enable register 1 [dual core device only] + C2APB1ENR1: mmio.Mmio(packed struct(u32) { + /// CPU2 TIM2 timer clock enable + TIM2EN: u1, + reserved10: u9, + /// CPU2 RTC APB clock enable + RTCAPBEN: u1, + reserved14: u3, + /// CPU2 SPI2 clock enable + SPI2EN: u1, + reserved17: u2, + /// CPU2 USART2 clock enable + USART2EN: u1, + reserved21: u3, + /// CPU2 I2C1 clocks enable + I2C1EN: u1, + /// CPU2 I2C2 clocks enable + I2C2EN: u1, + /// CPU2 I2C3 clocks enable + I2C3EN: u1, + reserved29: u5, + /// CPU2 DAC clock enable + DACEN: u1, + reserved31: u1, + /// CPU2 Low power timer 1 clocks enable + LPTIM1EN: u1, }), - /// DSI Host Video VSA Current Configuration Register. - VVSACCR: mmio.Mmio(packed struct(u32) { - /// Vertical Synchronism Active duration. - VSA: u10, - padding: u22, + /// CPU2 APB1 peripheral clock enable register 2 [dual core device only] + C2APB1ENR2: mmio.Mmio(packed struct(u32) { + /// CPU2 Low power UART 1 clocks enable + LPUART1EN: u1, + reserved5: u4, + /// CPU2 Low power timer 2 clocks enable + LPTIM2EN: u1, + /// CPU2 Low power timer 3 clocks enable + LPTIM3EN: u1, + padding: u25, }), - /// DSI Host Video VBP Current Configuration Register. - VVBPCCR: mmio.Mmio(packed struct(u32) { - /// Vertical Back-Porch duration. - VBP: u10, - padding: u22, + /// CPU2 APB2 peripheral clock enable register [dual core device only] + C2APB2ENR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// ADC clocks enable + ADCEN: u1, + reserved11: u1, + /// CPU2 TIM1 timer clock enable + TIM1EN: u1, + /// CPU2 SPI1 clock enable + SPI1EN: u1, + reserved14: u1, + /// CPU2 USART1clocks enable + USART1EN: u1, + reserved17: u2, + /// CPU2 TIM16 timer clock enable + TIM16EN: u1, + /// CPU2 TIM17 timer clock enable + TIM17EN: u1, + padding: u13, }), - /// DSI Host Video VFP Current Configuration Register. - VVFPCCR: mmio.Mmio(packed struct(u32) { - /// Vertical Front-Porch duration. - VFP: u10, - padding: u22, + /// CPU2 APB3 peripheral clock enable register [dual core device only] + C2APB3ENR: mmio.Mmio(packed struct(u32) { + /// CPU2 sub-GHz radio SPI clock enable + SUBGHZSPIEN: u1, + padding: u31, }), - /// DSI Host Video VA Current Configuration Register. - VVACCR: mmio.Mmio(packed struct(u32) { - /// Vertical Active duration. - VA: u14, - padding: u18, + /// CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only] + C2AHB1SMENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable during CPU2 CSleep mode. + DMA1SMEN: u1, + /// DMA2 clock enable during CPU2 CSleep mode. + DMA2SMEN: u1, + /// DMAMUX1 clock enable during CPU2 CSleep mode. + DMAMUX1SMEN: u1, + reserved12: u9, + /// CRC clock enable during CPU2 CSleep mode. + CRCSMEN: u1, + padding: u19, }), - reserved1024: [668]u8, - /// DSI Wrapper Configuration Register. - WCFGR: mmio.Mmio(packed struct(u32) { - /// DSI Mode. - DSIM: u1, - /// Color Multiplexing. - COLMUX: u3, - /// TE Source. - TESRC: u1, - /// TE Polarity. - TEPOL: u1, - /// Automatic Refresh. - AR: u1, - /// VSync Polarity. - VSPOL: u1, + /// CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only] + C2AHB2SMENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable during CPU2 CSleep mode. + GPIOASMEN: u1, + /// IO port B clock enable during CPU2 CSleep mode. + GPIOBSMEN: u1, + /// IO port C clock enable during CPU2 CSleep mode. + GPIOCSMEN: u1, + reserved7: u4, + /// IO port H clock enable during CPU2 CSleep mode. + GPIOHSMEN: u1, padding: u24, }), - /// DSI Wrapper Control Register. - WCR: mmio.Mmio(packed struct(u32) { - /// Color Mode. - COLM: u1, - /// Shutdown. - SHTDN: u1, - /// LTDC Enable. - LTDCEN: u1, - /// DSI Enable. - DSIEN: u1, - padding: u28, + /// CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only] + C2AHB3SMENR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// PKA accelerator clock enable during CPU2 CSleep mode. + PKASMEN: u1, + /// AES accelerator clock enable during CPU2 CSleep mode. + AESSMEN: u1, + /// True RNG clock enable during CPU2 CSleep and CStop mode. + RNGSMEN: u1, + reserved23: u4, + /// SRAM1 interface clock enable during CPU2 CSleep mode. + SRAM1SMEN: u1, + /// SRAM2 memory interface clock enable during CPU2 CSleep mode. + SRAM2SMEN: u1, + /// Flash interface clock enable during CPU2 CSleep mode. + FLASHSMEN: u1, + padding: u6, }), - /// DSI Wrapper Interrupt Enable Register. - WIER: mmio.Mmio(packed struct(u32) { - /// Tearing Effect Interrupt Enable. - TEIE: u1, - /// End of Refresh Interrupt Enable. - ERIE: u1, - reserved9: u7, - /// PLL Lock Interrupt Enable. - PLLLIE: u1, - /// PLL Unlock Interrupt Enable. - PLLUIE: u1, - reserved13: u2, - /// Regulator Ready Interrupt Enable. - RRIE: u1, - padding: u18, + reserved376: [4]u8, + /// CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only] + C2APB1SMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clock enable during CPU2 CSleep mode. + TIM2SMEN: u1, + reserved10: u9, + /// RTC bus clock enable during CPU2 CSleep mode. + RTCAPBSMEN: u1, + reserved14: u3, + /// SPI2 clock enable during CPU2 CSleep mode. + SPI2SMEN: u1, + reserved17: u2, + /// USART2 clock enable during CPU2 CSleep mode. + USART2SMEN: u1, + reserved21: u3, + /// I2C1 clock enable during CPU2 CSleep and CStop modes + I2C1SMEN: u1, + /// I2C2 clock enable during CPU2 CSleep and CStop modes + I2C2SMEN: u1, + /// I2C3 clock enable during CPU2 CSleep and CStop modes + I2C3SMEN: u1, + reserved29: u5, + /// DAC clock enable during CPU2 CSleep mode. + DACSMEN: u1, + reserved31: u1, + /// Low power timer 1 clock enable during CPU2 CSleep and CStop mode + LPTIM1SMEN: u1, }), - /// DSI Wrapper Interrupt & Status Register. - WISR: mmio.Mmio(packed struct(u32) { - /// Tearing Effect Interrupt Flag. - TEIF: u1, - /// End of Refresh Interrupt Flag. - ERIF: u1, - /// Busy Flag. - BUSY: u1, - reserved8: u5, - /// PLL Lock Status. - PLLLS: u1, - /// PLL Lock Interrupt Flag. - PLLLIF: u1, - /// PLL Unlock Interrupt Flag. - PLLUIF: u1, - reserved12: u1, - /// Regulator Ready Status. - RRS: u1, - /// Regulator Ready Interrupt Flag. - RRIF: u1, - padding: u18, + /// CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only] + C2APB1SMENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clock enable during CPU2 CSleep and CStop mode + LPUART1SMEN: u1, + reserved5: u4, + /// Low power timer 2 clocks enable during CPU2 CSleep and CStop modes. + LPTIM2SMEN: u1, + /// Low power timer 3 clocks enable during CPU2 CSleep and CStop modes. + LPTIM3SMEN: u1, + padding: u25, }), - /// DSI Wrapper Interrupt Flag Clear Register. - WIFCR: mmio.Mmio(packed struct(u32) { - /// Clear Tearing Effect Interrupt Flag. - CTEIF: u1, - /// Clear End of Refresh Interrupt Flag. - CERIF: u1, - reserved9: u7, - /// Clear PLL Lock Interrupt Flag. - CPLLLIF: u1, - /// Clear PLL Unlock Interrupt Flag. - CPLLUIF: u1, - reserved13: u2, - /// Clear Regulator Ready Interrupt Flag. - CRRIF: u1, - padding: u18, + /// CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only] + C2APB2SMENR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// ADC clocks enable during CPU2 Csleep and CStop modes + ADCSMEN: u1, + reserved11: u1, + /// TIM1 timer clock enable during CPU2 CSleep mode + TIM1SMEN: u1, + /// SPI1 clock enable during CPU2 CSleep mode + SPI1SMEN: u1, + reserved14: u1, + /// USART1clock enable during CPU2 CSleep and CStop mode + USART1SMEN: u1, + reserved17: u2, + /// TIM16 timer clock enable during CPU2 CSleep mode + TIM16SMEN: u1, + /// TIM17 timer clock enable during CPU2 CSleep mode + TIM17SMEN: u1, + padding: u13, }), - reserved1048: [4]u8, - /// DSI Wrapper PHY Configuration Register 0. - WPCR0: mmio.Mmio(packed struct(u32) { - /// Unit Interval multiplied by 4. - UIX4: u6, - /// Swap Clock Lane pins. - SWCL: u1, - /// Swap Data Lane 0 pins. - SWDL0: u1, - /// Swap Data Lane 1 pins. - SWDL1: u1, - /// Invert Hight-Speed data signal on Clock Lane. - HSICL: u1, - /// Invert the Hight-Speed data signal on Data Lane 0. - HSIDL0: u1, - /// Invert the High-Speed data signal on Data Lane 1. - HSIDL1: u1, - /// Force in TX Stop Mode the Clock Lane. - FTXSMCL: u1, - /// Force in TX Stop Mode the Data Lanes. - FTXSMDL: u1, - /// Contention Detection OFF on Data Lanes. - CDOFFDL: u1, - reserved16: u1, - /// Turn Disable Data Lanes. - TDDL: u1, - reserved18: u1, - /// Pull-Down Enable. - PDEN: u1, - /// custom time for tCLK-PREPARE Enable. - TCLKPREPEN: u1, - /// custom time for tCLK-ZERO Enable. - TCLKZEROEN: u1, - /// custom time for tHS-PREPARE Enable. - THSPREPEN: u1, - /// custom time for tHS-TRAIL Enable. - THSTRAILEN: u1, - /// custom time for tHS-ZERO Enable. - THSZEROEN: u1, - /// custom time for tLPX for Data lanes Enable. - TLPXDEN: u1, - /// custom time for tHS-EXIT Enable. - THSEXITEN: u1, - /// custom time for tLPX for Clock lane Enable. - TLPXCEN: u1, - /// custom time for tCLK-POST Enable. - TCLKPOSTEN: u1, - padding: u4, + /// CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only] + C2APB3SMENR: mmio.Mmio(packed struct(u32) { + /// sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes + SUBGHZSPISMEN: u1, + padding: u31, }), - /// DSI Wrapper PHY Configuration Register 1. - WPCR1: mmio.Mmio(packed struct(u32) { - /// High-Speed Transmission Delay on Clock Lane. - HSTXDCL: u2, - /// High-Speed Transmission Delay on Data Lanes. - HSTXDLL: u2, - reserved6: u2, - /// Low-Power transmission Slew Rate Compensation on Clock Lane. - LPSRCL: u2, - /// Low-Power transmission Slew Rate Compensation on Data Lanes. - LPSRDL: u2, - reserved12: u2, - /// SDD Control. - SDCC: u1, + }; + }; + + pub const rcc_wle = struct { + pub const ADCSEL = enum(u2) { + /// HSI used as ADC clock source + HSI = 0x1, + /// PLLPCLK used as ADC clock source + PLL1_P = 0x2, + /// SYSCLK used as ADC clock source + SYS = 0x3, + _, + }; + + pub const HPRE = enum(u4) { + /// DCLK not divided + Div1 = 0x0, + /// hclk = SYSCLK divided by 3 + Div3 = 0x1, + /// hclk = SYSCLK divided by 5 + Div5 = 0x2, + /// hclk = SYSCLK divided by 6 + Div6 = 0x5, + /// hclk = SYSCLK divided by 8 + Div10 = 0x6, + /// hclk = SYSCLK divided by 32 + Div32 = 0x7, + /// hclk = SYSCLK divided by 2 + Div2 = 0x8, + /// hclk = SYSCLK divided by 4 + Div4 = 0x9, + /// hclk = SYSCLK divided by 8 + Div8 = 0xa, + /// hclk = SYSCLK divided by 16 + Div16 = 0xb, + /// hclk = SYSCLK divided by 64 + Div64 = 0xc, + /// hclk = SYSCLK divided by 128 + Div128 = 0xd, + /// hclk = SYSCLK divided by 256 + Div256 = 0xe, + /// hclk = SYSCLK divided by 256 + Div512 = 0xf, + _, + }; + + pub const HSEPRE = enum(u1) { + Div1 = 0x0, + Div2 = 0x1, + }; + + pub const LSEDRV = enum(u2) { + /// Low driving capability + Low = 0x0, + /// Medium low driving capability + MediumLow = 0x1, + /// Medium high driving capability + MediumHigh = 0x2, + /// High driving capability + High = 0x3, + }; + + pub const MCOPRE = enum(u3) { + /// No division + Div1 = 0x0, + /// Division by 2 + Div2 = 0x1, + /// Division by 4 + Div4 = 0x2, + /// Division by 8 + Div8 = 0x3, + /// Division by 16 + Div16 = 0x4, + _, + }; + + pub const MCOSEL = enum(u4) { + /// No clock + DISABLE = 0x0, + /// SYSCLK clock selected + SYS = 0x1, + /// MSI oscillator clock selected + MSI = 0x2, + /// HSI oscillator clock selected + HSI = 0x3, + /// HSE oscillator clock selected + HSE = 0x4, + /// Main PLLRCLK clock selected + PLL1_R = 0x5, + /// LSI oscillator clock selected + LSI = 0x6, + /// LSE oscillator clock selected + LSE = 0x8, + /// Main PLLCLK oscillator clock selected + PLL1_P = 0xd, + /// Main PLLQCLK oscillator clock selected + PLL1_Q = 0xe, + _, + }; + + pub const MSIRANGE = enum(u4) { + /// range 0 around 100 kHz + Range100K = 0x0, + /// range 1 around 200 kHz + Range200K = 0x1, + /// range 2 around 400 kHz + Range400K = 0x2, + /// range 3 around 800 kHz + Range800K = 0x3, + /// range 4 around 1 MHz + Range1M = 0x4, + /// range 5 around 2 MHz + Range2M = 0x5, + /// range 6 around 4 MHz + Range4M = 0x6, + /// range 7 around 8 MHz + Range8M = 0x7, + /// range 8 around 16 MHz + Range16M = 0x8, + /// range 9 around 24 MHz + Range24M = 0x9, + /// range 10 around 32 MHz + Range32M = 0xa, + /// range 11 around 48 MHz + Range48M = 0xb, + _, + }; + + pub const MSIRGSEL = enum(u1) { + /// MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register + CSR = 0x0, + /// MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register + CR = 0x1, + }; + + pub const PLLM = enum(u3) { + Div1 = 0x0, + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + }; + + pub const PLLN = enum(u7) { + Mul6 = 0x6, + Mul7 = 0x7, + Mul8 = 0x8, + Mul9 = 0x9, + Mul10 = 0xa, + Mul11 = 0xb, + Mul12 = 0xc, + Mul13 = 0xd, + Mul14 = 0xe, + Mul15 = 0xf, + Mul16 = 0x10, + Mul17 = 0x11, + Mul18 = 0x12, + Mul19 = 0x13, + Mul20 = 0x14, + Mul21 = 0x15, + Mul22 = 0x16, + Mul23 = 0x17, + Mul24 = 0x18, + Mul25 = 0x19, + Mul26 = 0x1a, + Mul27 = 0x1b, + Mul28 = 0x1c, + Mul29 = 0x1d, + Mul30 = 0x1e, + Mul31 = 0x1f, + Mul32 = 0x20, + Mul33 = 0x21, + Mul34 = 0x22, + Mul35 = 0x23, + Mul36 = 0x24, + Mul37 = 0x25, + Mul38 = 0x26, + Mul39 = 0x27, + Mul40 = 0x28, + Mul41 = 0x29, + Mul42 = 0x2a, + Mul43 = 0x2b, + Mul44 = 0x2c, + Mul45 = 0x2d, + Mul46 = 0x2e, + Mul47 = 0x2f, + Mul48 = 0x30, + Mul49 = 0x31, + Mul50 = 0x32, + Mul51 = 0x33, + Mul52 = 0x34, + Mul53 = 0x35, + Mul54 = 0x36, + Mul55 = 0x37, + Mul56 = 0x38, + Mul57 = 0x39, + Mul58 = 0x3a, + Mul59 = 0x3b, + Mul60 = 0x3c, + Mul61 = 0x3d, + Mul62 = 0x3e, + Mul63 = 0x3f, + Mul64 = 0x40, + Mul65 = 0x41, + Mul66 = 0x42, + Mul67 = 0x43, + Mul68 = 0x44, + Mul69 = 0x45, + Mul70 = 0x46, + Mul71 = 0x47, + Mul72 = 0x48, + Mul73 = 0x49, + Mul74 = 0x4a, + Mul75 = 0x4b, + Mul76 = 0x4c, + Mul77 = 0x4d, + Mul78 = 0x4e, + Mul79 = 0x4f, + Mul80 = 0x50, + Mul81 = 0x51, + Mul82 = 0x52, + Mul83 = 0x53, + Mul84 = 0x54, + Mul85 = 0x55, + Mul86 = 0x56, + Mul87 = 0x57, + Mul88 = 0x58, + Mul89 = 0x59, + Mul90 = 0x5a, + Mul91 = 0x5b, + Mul92 = 0x5c, + Mul93 = 0x5d, + Mul94 = 0x5e, + Mul95 = 0x5f, + Mul96 = 0x60, + Mul97 = 0x61, + Mul98 = 0x62, + Mul99 = 0x63, + Mul100 = 0x64, + Mul101 = 0x65, + Mul102 = 0x66, + Mul103 = 0x67, + Mul104 = 0x68, + Mul105 = 0x69, + Mul106 = 0x6a, + Mul107 = 0x6b, + Mul108 = 0x6c, + Mul109 = 0x6d, + Mul110 = 0x6e, + Mul111 = 0x6f, + Mul112 = 0x70, + Mul113 = 0x71, + Mul114 = 0x72, + Mul115 = 0x73, + Mul116 = 0x74, + Mul117 = 0x75, + Mul118 = 0x76, + Mul119 = 0x77, + Mul120 = 0x78, + Mul121 = 0x79, + Mul122 = 0x7a, + Mul123 = 0x7b, + Mul124 = 0x7c, + Mul125 = 0x7d, + Mul126 = 0x7e, + Mul127 = 0x7f, + _, + }; + + pub const PLLP = enum(u5) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + Div8 = 0x7, + Div9 = 0x8, + Div10 = 0x9, + Div11 = 0xa, + Div12 = 0xb, + Div13 = 0xc, + Div14 = 0xd, + Div15 = 0xe, + Div16 = 0xf, + Div17 = 0x10, + Div18 = 0x11, + Div19 = 0x12, + Div20 = 0x13, + Div21 = 0x14, + Div22 = 0x15, + Div23 = 0x16, + Div24 = 0x17, + Div25 = 0x18, + Div26 = 0x19, + Div27 = 0x1a, + Div28 = 0x1b, + Div29 = 0x1c, + Div30 = 0x1d, + Div31 = 0x1e, + _, + }; + + pub const PLLQ = enum(u3) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + _, + }; + + pub const PLLR = enum(u3) { + Div2 = 0x1, + Div3 = 0x2, + Div4 = 0x3, + Div5 = 0x4, + Div6 = 0x5, + Div7 = 0x6, + _, + }; + + pub const PLLSRC = enum(u2) { + /// No clock selected as PLL entry clock source + DISABLE = 0x0, + /// MSI selected as PLL entry clock source + MSI = 0x1, + /// HSI selected as PLL entry clock source + HSI = 0x2, + /// HSE selected as PLL entry clock source + HSE = 0x3, + }; + + pub const PPRE = enum(u3) { + /// HCLK not divided + Div1 = 0x0, + /// HCLK divided by 2 + Div2 = 0x4, + /// HCLK divided by 4 + Div4 = 0x5, + /// HCLK divided by 8 + Div8 = 0x6, + /// HCLK divided by 16 + Div16 = 0x7, + _, + }; + + pub const RNGSEL = enum(u2) { + PLL1_Q = 0x0, + LSI = 0x1, + LSE = 0x2, + MSI = 0x3, + }; + + pub const RTCSEL = enum(u2) { + /// No clock selected + DISABLE = 0x0, + /// LSE oscillator clock selected + LSE = 0x1, + /// LSI oscillator clock selected + LSI = 0x2, + /// HSE oscillator clock divided by 32 selected + HSE = 0x3, + }; + + pub const SW = enum(u2) { + MSI = 0x0, + HSI = 0x1, + HSE = 0x2, + PLL1_R = 0x3, + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// MSI clock enable + MSION: u1, + /// MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) + MSIRDY: u1, + /// MSI clock PLL enable + MSIPLLEN: u1, + /// MSI range control selection + MSIRGSEL: packed union { + raw: u1, + value: MSIRGSEL, + }, + /// MSI clock ranges + MSIRANGE: packed union { + raw: u4, + value: MSIRANGE, + }, + /// HSI clock enable + HSION: u1, + /// HSI always enable for peripheral kernel clocks. + HSIKERON: u1, + /// HSI clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI is ready) + HSIRDY: u1, + /// HSI automatic start from Stop + HSIASFS: u1, + /// HSI kernel clock ready flag for peripherals requests. + HSIKERDY: u1, reserved16: u3, - /// High-Speed Transmission Slew Rate Control on Clock Lane. - HSTXSRCCL: u2, - /// High-Speed Transmission Slew Rate Control on Data Lanes. - HSTXSRCDL: u2, - reserved22: u2, - /// Forces LP Receiver in Low-Power Mode. - FLPRXLPM: u1, - reserved25: u2, - /// Low-Power RX low-pass Filtering Tuning. - LPRXFT: u2, - padding: u5, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + reserved19: u1, + /// HSE Clock security system enable + CSSON: u1, + /// HSE sysclk prescaler + HSEPRE: packed union { + raw: u1, + value: HSEPRE, + }, + /// Enable HSE VDDTCXO output on package pin PB0-VDDTCXO. + HSEBYPPWR: u1, + reserved24: u2, + /// Main PLL enable + PLLON: u1, + /// Main PLL clock ready flag + PLLRDY: u1, + padding: u6, }), - /// DSI Wrapper PHY Configuration Register 2. - WPCR2: mmio.Mmio(packed struct(u32) { - /// tCLK-PREPARE. - TCLKPREP: u8, - /// tCLK-ZERO. - TCLKZEO: u8, - /// tHS-PREPARE. - THSPREP: u8, - /// tHSTRAIL. - THSTRAIL: u8, + /// Internal clock sources calibration register + ICSCR: mmio.Mmio(packed struct(u32) { + /// MSI clock calibration + MSICAL: u8, + /// MSI clock trimming + MSITRIM: u8, + /// HSI clock calibration + HSICAL: u8, + /// HSI clock trimming + HSITRIM: u7, + padding: u1, + }), + /// Clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW: packed union { + raw: u2, + value: SW, + }, + /// System clock switch status + SWS: packed union { + raw: u2, + value: SW, + }, + /// HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.) + HPRE: packed union { + raw: u4, + value: HPRE, + }, + /// PCLK1 low-speed prescaler (APB1) + PPRE1: packed union { + raw: u3, + value: PPRE, + }, + /// PCLK2 high-speed prescaler (APB2) + PPRE2: packed union { + raw: u3, + value: PPRE, + }, + reserved15: u1, + /// Wakeup from Stop and CSS backup clock selection + STOPWUCK: u1, + /// HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1) + HPREF: u1, + /// PCLK1 prescaler flag (APB1) + PPRE1F: u1, + /// PCLK2 prescaler flag (APB2) + PPRE2F: u1, + reserved24: u5, + /// Microcontroller clock output + MCOSEL: packed union { + raw: u4, + value: MCOSEL, + }, + /// Microcontroller clock output prescaler + MCOPRE: packed union { + raw: u3, + value: MCOPRE, + }, + padding: u1, }), - /// DSI Wrapper PHY Configuration Register 3. - WPCR3: mmio.Mmio(packed struct(u32) { - /// tHS-ZERO. - THSZERO: u8, - /// tLPX for Data lanes. - TLPXD: u8, - /// tHSEXIT. - THSEXIT: u8, - /// tLPXC for Clock lane. - TLPXC: u8, + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// Main PLL entry clock source + PLLSRC: packed union { + raw: u2, + value: PLLSRC, + }, + reserved4: u2, + /// Division factor for the main PLL input clock + PLLM: packed union { + raw: u3, + value: PLLM, + }, + reserved8: u1, + /// Main PLL multiplication factor for VCO + PLLN: packed union { + raw: u7, + value: PLLN, + }, + reserved16: u1, + /// Main PLL PLLPCLK output enable + PLLPEN: u1, + /// Main PLL division factor for PLLPCLK. + PLLP: packed union { + raw: u5, + value: PLLP, + }, + reserved24: u2, + /// Main PLL PLLQCLK output enable + PLLQEN: u1, + /// Main PLL division factor for PLLQCLK + PLLQ: packed union { + raw: u3, + value: PLLQ, + }, + /// Main PLL PLLRCLK output enable + PLLREN: u1, + /// Main PLL division factor for PLLRCLK + PLLR: packed union { + raw: u3, + value: PLLR, + }, }), - /// DSI Wrapper PHY Configuration Register 4. - WPCR4: mmio.Mmio(packed struct(u32) { - /// tCLK-POST. - TCLKPOST: u8, - padding: u24, + reserved24: [8]u8, + /// Clock interrupt enable register + CIER: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// MSI ready interrupt enable + MSIRDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// PLL ready interrupt enable + PLLRDYIE: u1, + reserved9: u3, + /// LSE clock security system interrupt enable + LSECSSIE: u1, + padding: u22, }), - reserved1072: [4]u8, - /// DSI Wrapper Regulator and PLL Control Register. - WRPCR: mmio.Mmio(packed struct(u32) { - /// PLL Enable. - PLLEN: u1, - reserved2: u1, - /// PLL Loop Division Factor. - NDIV: u7, - reserved11: u2, - /// PLL Input Division Factor. - IDF: u4, - reserved16: u1, - /// PLL Output Division Factor. - ODF: u2, - reserved24: u6, - /// Regulator Enable. - REGEN: u1, - padding: u7, + /// Clock interrupt flag register + CIFR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// MSI ready interrupt flag + MSIRDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// PLL ready interrupt flag + PLLRDYF: u1, + reserved8: u2, + /// HSE Clock security system interrupt flag + CSSF: u1, + /// LSE Clock security system interrupt flag + LSECSSF: u1, + padding: u22, }), - }; - }; - - pub const pwr_wb55 = struct { - pub const VOS = enum(u2) { - /// Range 1 - Range1 = 0x1, - /// Range 2 - Range2 = 0x2, - _, - }; - - /// Power control - pub const PWR = extern struct { - /// Power control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection for CPU1 - LPMS: u3, - reserved4: u1, - /// Flash power down mode during LPRun for CPU1 - FPDR: u1, - /// Flash power down mode during LPsSleep for CPU1 - FPDS: u1, + /// Clock interrupt clear register + CICR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// MSI ready interrupt clear + MSIRDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// PLL ready interrupt clear + PLLRDYC: u1, reserved8: u2, - /// Disable backup domain write protection - DBP: u1, - /// Voltage scaling range selection - VOS: packed union { - raw: u2, - value: VOS, - }, - reserved14: u3, - /// Low-power run - LPR: u1, - padding: u17, + /// HSE Clock security system interrupt clear + CSSC: u1, + /// LSE Clock security system interrupt clear + LSECSSC: u1, + padding: u22, }), - /// Power control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Power voltage detector enable - PVDE: u1, - /// Power voltage detector level selection - PLS: u3, - /// Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V - PVME1: u1, - reserved6: u1, - /// Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V - PVME3: u1, - reserved10: u3, - /// VDDUSB USB supply valid - USV: u1, - padding: u21, + reserved40: [4]u8, + /// AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// DMA1 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + /// DMAMUX1 reset + DMAMUX1RST: u1, + reserved12: u9, + /// CRC reset + CRCRST: u1, + padding: u19, }), - /// Power control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin - EWUP: u1, - reserved8: u7, - /// Enable BORH and Step Down counverter forced in Bypass interrups for CPU1 - EBORHSDFB: u1, - /// SRAM2a retention in Standby mode - RRS: u1, - /// Apply pull-up and pull-down configuration - APC: u1, - /// Enable BLE end of activity interrupt for CPU1 - EBLEA: u1, - /// Enable critical radio phase end of activity interrupt for CPU1 - ECRPE: u1, - /// Enable end of activity interrupt for CPU1 - E802A: u1, - /// Enable CPU2 Hold interrupt for CPU1 - EC2H: u1, - /// Enable internal wakeup line for CPU1 - EIWUL: u1, - padding: u16, + /// AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + reserved7: u4, + /// IO port H reset + GPIOHRST: u1, + padding: u24, }), - /// Power control register 4 - CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity - WP1: u1, - reserved8: u7, - /// VBAT battery charging enable - VBE: u1, - /// VBAT battery charging resistor selection - VBRS: u1, - reserved15: u5, - /// BOOT CPU2 after reset or wakeup from Stop or Standby modes - C2BOOT: u1, - padding: u16, + /// AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// PKARST + PKARST: u1, + /// AESRST + AESRST: u1, + /// RNGRST + RNGRST: u1, + /// HSEMRST + HSEMRST: u1, + reserved25: u5, + /// Flash interface reset + FLASHRST: u1, + padding: u6, }), - /// Power status register 1 - SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag 1 - CWUF: u1, - reserved7: u6, - /// Step Down converter forced in Bypass interrupt flag - SDFBF: u1, - /// BORH interrupt flag - BORHF: u1, - /// BLE wakeup interrupt flag - BLEWUF: u1, - /// 802.15.4 wakeup interrupt flag - _802WUF: u1, - /// Enable critical radio phase end of activity interrupt flag - CRPEF: u1, - /// BLE end of activity interrupt flag - BLEAF: u1, - /// 802.15.4 end of activity interrupt flag - AF802: u1, - /// CPU2 Hold interrupt flag - C2HF: u1, - /// Internal Wakeup interrupt flag - WUFI: u1, - padding: u16, + reserved56: [4]u8, + /// APB1 peripheral reset register 1 + APB1RSTR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer reset + TIM2RST: u1, + reserved14: u13, + /// SPI2 reset + SPI2RST: u1, + reserved17: u2, + /// USART2 reset + USART2RST: u1, + reserved21: u3, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// I2C3 reset + I2C3RST: u1, + reserved29: u5, + /// DAC reset + DACRST: u1, + reserved31: u1, + /// Low Power Timer 1 reset + LPTIM1RST: u1, }), - /// Power status register 2 - SR2: mmio.Mmio(packed struct(u32) { - /// Step Down converter Bypass mode flag - SDBF: u1, - /// Step Down converter SMPS mode flag - SDSMPSF: u1, - reserved8: u6, - /// Low-power regulator started - REGLPS: u1, - /// Low-power regulator flag - REGLPF: u1, - /// Voltage scaling flag - VOSF: u1, - /// Power voltage detector output - PVDO: u1, - /// Peripheral voltage monitoring output: VDDUSB vs. 1.2 V - PVMO1: u1, + /// APB1 peripheral reset register 2 + APB1RSTR2: mmio.Mmio(packed struct(u32) { + /// Low-power UART 1 reset + LPUART1RST: u1, + reserved5: u4, + /// Low-power timer 2 reset + LPTIM2RST: u1, + /// Low-power timer 3 reset + LPTIM3RST: u1, + padding: u25, + }), + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// ADC reset + ADCRST: u1, + reserved11: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI1 reset + SPI1RST: u1, reserved14: u1, - /// Peripheral voltage monitoring output: VDDA vs. 1.62 V - PVMO3: u1, - padding: u17, + /// USART1 reset + USART1RST: u1, + reserved17: u2, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + padding: u13, }), - /// Power status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag 1 - CWUF: u1, - reserved7: u6, - /// Clear SMPS Step Down converter forced in Bypass interrupt flag - CSMPSFBF: u1, - /// Clear BORH interrupt flag - CBORHF: u1, - /// Clear BLE wakeup interrupt flag - CBLEWUF: u1, - /// Clear 802.15.4 wakeup interrupt flag - C802WUF: u1, - /// Clear critical radio phase end of activity interrupt flag - CCRPEF: u1, - /// Clear BLE end of activity interrupt flag - CBLEAF: u1, - /// Clear 802.15.4 end of activity interrupt flag - C802AF: u1, - /// Clear CPU2 Hold interrupt flag - CC2HF: u1, - padding: u17, + /// APB3 peripheral reset register + APB3RSTR: mmio.Mmio(packed struct(u32) { + /// Sub-GHz radio SPI reset + SUBGHZSPIRST: u1, + padding: u31, }), - /// Power control register 5 - CR5: mmio.Mmio(packed struct(u32) { - /// Step Down converter voltage output scaling - SDVOS: u4, - /// Step Down converter supplt startup current selection - SDSC: u3, - reserved8: u1, - /// BORH configuration selection - BORHC: u1, - /// VOS configuration selection (non user) - SMPSCFG: u1, - reserved14: u4, - /// Enable Step Down converter Bypass mode enabled - SDBEN: u1, - /// Enable Step Down converter SMPS mode enabled - SDEB: u1, - padding: u16, + /// AHB1 peripheral clock enable register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// CPU1 DMA1 clock enable + DMA1EN: u1, + /// CPU1 DMA2 clock enable + DMA2EN: u1, + /// CPU1 DMAMUX1 clock enable + DMAMUX1EN: u1, + reserved12: u9, + /// CPU1 CRC clock enable + CRCEN: u1, + padding: u19, }), - /// Power Port A pull-up control register - PUCRA: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// CPU1 IO port A clock enable + GPIOAEN: u1, + /// CPU1 IO port B clock enable + GPIOBEN: u1, + /// CPU1 IO port C clock enable + GPIOCEN: u1, + reserved7: u4, + /// CPU1 IO port H clock enable + GPIOHEN: u1, + padding: u24, }), - /// Power Port A pull-down control register - PDCRA: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// PKAEN + PKAEN: u1, + /// AESEN + AESEN: u1, + /// RNGEN + RNGEN: u1, + /// HSEMEN + HSEMEN: u1, + reserved25: u5, + /// CPU1 Flash interface clock enable + FLASHEN: u1, + padding: u6, }), - /// Power Port B pull-up control register - PUCRB: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + reserved88: [4]u8, + /// APB1 peripheral clock enable register 1 + APB1ENR1: mmio.Mmio(packed struct(u32) { + /// CPU1 TIM2 timer clock enable + TIM2EN: u1, + reserved10: u9, + /// CPU1 RTC APB clock enable + RTCAPBEN: u1, + /// CPU1 Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// CPU1 SPI2 clock enable + SPI2EN: u1, + reserved17: u2, + /// CPU1 USART2 clock enable + USART2EN: u1, + reserved21: u3, + /// CPU1 I2C1 clocks enable + I2C1EN: u1, + /// CPU1 I2C2 clocks enable + I2C2EN: u1, + /// CPU1 I2C3 clocks enable + I2C3EN: u1, + reserved29: u5, + /// CPU1 DAC clock enable + DACEN: u1, + reserved31: u1, + /// CPU1 Low power timer 1 clocks enable + LPTIM1EN: u1, }), - /// Power Port B pull-down control register - PDCRB: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// APB1 peripheral clock enable register 2 + APB1ENR2: mmio.Mmio(packed struct(u32) { + /// CPU1 Low power UART 1 clocks enable + LPUART1EN: u1, + reserved5: u4, + /// CPU1 Low power timer 2 clocks enable + LPTIM2EN: u1, + /// CPU1 Low power timer 3 clocks enable + LPTIM3EN: u1, + padding: u25, }), - /// Power Port C pull-up control register - PUCRC: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// APB2 peripheral clock enable register + APB2ENR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// CPU1 ADC clocks enable + ADCEN: u1, + reserved11: u1, + /// CPU1 TIM1 timer clock enable + TIM1EN: u1, + /// CPU1 SPI1 clock enable + SPI1EN: u1, + reserved14: u1, + /// CPU1 USART1clocks enable + USART1EN: u1, + reserved17: u2, + /// CPU1 TIM16 timer clock enable + TIM16EN: u1, + /// CPU1 TIM17 timer clock enable + TIM17EN: u1, + padding: u13, }), - /// Power Port C pull-down control register - PDCRC: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, + /// APB3 peripheral clock enable register + APB3ENR: mmio.Mmio(packed struct(u32) { + /// sub-GHz radio SPI clock enable + SUBGHZSPIEN: u1, padding: u31, }), - /// Power Port D pull-up control register - PUCRD: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// AHB1 peripheral clocks enable in Sleep modes register + AHB1SMENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable during CPU1 CSleep mode. + DMA1SMEN: u1, + /// DMA2 clock enable during CPU1 CSleep mode + DMA2SMEN: u1, + /// DMAMUX1 clock enable during CPU1 CSleep mode. + DMAMUX1SMEN: u1, + reserved12: u9, + /// CRC clock enable during CPU1 CSleep mode. + CRCSMEN: u1, + padding: u19, }), - /// Power Port D pull-down control register - PDCRD: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// AHB2 peripheral clocks enable in Sleep modes register + AHB2SMENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable during CPU1 CSleep mode. + GPIOASMEN: u1, + /// IO port B clock enable during CPU1 CSleep mode. + GPIOBSMEN: u1, + /// IO port C clock enable during CPU1 CSleep mode. + GPIOCSMEN: u1, + reserved7: u4, + /// IO port H clock enable during CPU1 CSleep mode. + GPIOHSMEN: u1, + padding: u24, }), - /// Power Port E pull-up control register - PUCRE: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// AHB3 peripheral clocks enable in Sleep and Stop modes register + AHB3SMENR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// PKA accelerator clock enable during CPU1 CSleep mode. + PKASMEN: u1, + /// AES accelerator clock enable during CPU1 CSleep mode. + AESSMEN: u1, + /// True RNG clocks enable during CPU1 Csleep and CStop modes + RNGSMEN: u1, + reserved23: u4, + /// SRAM1 interface clock enable during CPU1 CSleep mode. + SRAM1SMEN: u1, + /// SRAM2 memory interface clock enable during CPU1 CSleep mode + SRAM2SMEN: u1, + /// Flash interface clock enable during CPU1 CSleep mode. + FLASHSMEN: u1, + padding: u6, }), - /// Power Port E pull-down control register - PDCRE: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + reserved120: [4]u8, + /// APB1 peripheral clocks enable in Sleep mode register 1 + APB1SMENR1: mmio.Mmio(packed struct(u32) { + /// TIM2 timer clock enable during CPU1 CSleep mode. + TIM2SMEN: u1, + reserved10: u9, + /// RTC bus clock enable during CPU1 CSleep mode. + RTCAPBSMEN: u1, + /// Window watchdog clocks enable during CPU1 CSleep mode. + WWDGSMEN: u1, + reserved14: u2, + /// SPI2 clock enable during CPU1 CSleep mode. + SPI2SMEN: u1, + reserved17: u2, + /// USART2 clock enable during CPU1 CSleep mode. + USART2SMEN: u1, + reserved21: u3, + /// I2C1 clock enable during CPU1 Csleep and CStop modes + I2C1SMEN: u1, + /// I2C2 clock enable during CPU1 Csleep and CStop modes + I2C2SMEN: u1, + /// I2C3 clock enable during CPU1 Csleep and CStop modes + I2C3SMEN: u1, + reserved29: u5, + /// DAC clock enable during CPU1 CSleep mode. + DACSMEN: u1, + reserved31: u1, + /// Low power timer 1 clock enable during CPU1 Csleep and CStop mode + LPTIM1SMEN: u1, }), - reserved88: [16]u8, - /// Power Port H pull-up control register - PUCRH: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// APB1 peripheral clocks enable in Sleep mode register 2 + APB1SMENR2: mmio.Mmio(packed struct(u32) { + /// Low power UART 1 clock enable during CPU1 Csleep and CStop modes. + LPUART1SMEN: u1, + reserved5: u4, + /// Low power timer 2 clock enable during CPU1 Csleep and CStop modes + LPTIM2SMEN: u1, + /// Low power timer 3 clock enable during CPU1 Csleep and CStop modes + LPTIM3SMEN: u1, + padding: u25, }), - /// Power Port H pull-down control register - PDCRH: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, + /// APB2 peripheral clocks enable in Sleep mode register + APB2SMENR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// ADC clocks enable during CPU1 Csleep and CStop modes + ADCSMEN: u1, + reserved11: u1, + /// TIM1 timer clock enable during CPU1 CSleep mode. + TIM1SMEN: u1, + /// SPI1 clock enable during CPU1 CSleep mode. + SPI1SMEN: u1, + reserved14: u1, + /// USART1 clock enable during CPU1 Csleep and CStop modes. + USART1SMEN: u1, + reserved17: u2, + /// TIM16 timer clock enable during CPU1 CSleep mode. + TIM16SMEN: u1, + /// TIM17 timer clock enable during CPU1 CSleep mode. + TIM17SMEN: u1, + padding: u13, + }), + /// APB3 peripheral clock enable in Sleep mode register + APB3SMENR: mmio.Mmio(packed struct(u32) { + /// Sub-GHz radio SPI clock enable during Sleep and Stop modes + SUBGHZSPISMEN: u1, padding: u31, }), - reserved128: [32]u8, - /// CPU2 Power control register 1 - C2CR1: mmio.Mmio(packed struct(u32) { - /// Low-power mode selection for CPU2 - LPMS: u3, - reserved4: u1, - /// Flash power down mode during LPRun for CPU2 - FPDR: u1, - /// Flash power down mode during LPSleep for CPU2 - FPDS: u1, - reserved14: u8, - /// BLE external wakeup signal - BLEEWKUP: u1, - /// 802.15.4 external wakeup signal - _802EWKUP: u1, - padding: u16, + /// Peripherals independent clock configuration register + CCIPR: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SEL: u2, + /// USART2 clock source selection + USART2SEL: u2, + reserved8: u4, + /// SPI2 I2S clock source selection + SPI2SEL: u2, + /// LPUART1 clock source selection + LPUART1SEL: u2, + /// I2C1 clock source selection + I2C1SEL: u2, + /// I2C2 clock source selection + I2C2SEL: u2, + /// I2C3 clock source selection + I2C3SEL: u2, + /// Low power timer 1 clock source selection + LPTIM1SEL: u2, + /// Low power timer 2 clock source selection + LPTIM2SEL: u2, + /// Low power timer 3 clock source selection + LPTIM3SEL: u2, + reserved28: u4, + /// ADC clock source selection + ADCSEL: packed union { + raw: u2, + value: ADCSEL, + }, + /// RNG clock source selection + RNGSEL: packed union { + raw: u2, + value: RNGSEL, + }, }), - /// CPU2 Power control register 3 - C2CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin - EWUP: u1, - reserved9: u8, - /// Enable BLE host wakeup interrupt for CPU2 - EBLEWUP: u1, - /// Enable 802.15.4 host wakeup interrupt for CPU2 - E802WUP: u1, - reserved12: u1, - /// Apply pull-up and pull-down configuration for CPU2 - APC: u1, - reserved15: u2, - /// Enable internal wakeup line for CPU2 - EIWUL: u1, - padding: u16, + reserved144: [4]u8, + /// Backup domain control register + BDCR: mmio.Mmio(packed struct(u32) { + /// LSE oscillator enable + LSEON: u1, + /// LSE oscillator ready + LSERDY: u1, + /// LSE oscillator bypass + LSEBYP: u1, + /// LSE oscillator drive capability + LSEDRV: packed union { + raw: u2, + value: LSEDRV, + }, + /// CSS on LSE enable + LSECSSON: u1, + /// CSS on LSE failure Detection + LSECSSD: u1, + /// LSE system clock enable + LSESYSEN: u1, + /// RTC clock source selection + RTCSEL: packed union { + raw: u2, + value: RTCSEL, + }, + reserved11: u1, + /// LSE system clock ready + LSESYSRDY: u1, + reserved15: u3, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + reserved24: u7, + /// Low speed clock output enable + LSCOEN: u1, + /// Low speed clock output selection + LSCOSEL: u1, + padding: u6, }), - /// Power status clear register - EXTSCR: mmio.Mmio(packed struct(u32) { - /// Clear CPU1 Stop Standby flags - C1CSSF: u1, - /// Clear CPU2 Stop Standby flags - C2CSSF: u1, - /// Clear Critical Radio system phase - CCRPF: u1, - reserved8: u5, - /// System Standby flag for CPU1 - C1SBF: u1, - /// System Stop flag for CPU1 - C1STOPF: u1, - /// System Standby flag for CPU2 - C2SBF: u1, - /// System Stop flag for CPU2 - C2STOPF: u1, - reserved13: u1, - /// Critical Radio system phase - CRPF: u1, - /// CPU1 deepsleep mode - C1DS: u1, - /// CPU2 deepsleep mode - C2DS: u1, - padding: u16, + /// Control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// LSI oscillator enable + LSION: u1, + /// LSI oscillator ready + LSIRDY: u1, + reserved4: u2, + /// LSI frequency prescaler + LSIPRE: u1, + reserved8: u3, + /// MSI clock ranges + MSISRANGE: u4, + reserved14: u2, + /// Radio in reset status flag + RFRSTF: u1, + /// Radio reset + RFRST: u1, + reserved23: u7, + /// Remove reset flag + RMVF: u1, + /// Radio illegal access flag + RFILARSTF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// Pin reset flag + PINRSTF: u1, + /// BOR flag + BORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent window watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + reserved264: [112]u8, + /// Extended clock recovery register + EXTCFGR: mmio.Mmio(packed struct(u32) { + /// HCLK3 shared prescaler (AHB3, Flash, and SRAM2) + SHDHPRE: packed union { + raw: u4, + value: HPRE, + }, + reserved16: u12, + /// HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2) + SHDHPREF: u1, + padding: u15, }), }; }; - pub const quadspi_v1 = struct { - /// QuadSPI interface - pub const QUADSPI = extern struct { + pub const rng_v1 = struct { + /// Random number generator + pub const RNG = extern struct { /// control register CR: mmio.Mmio(packed struct(u32) { - /// Enable - EN: u1, - /// Abort request - ABORT: u1, - /// DMA enable (not available on all chips!) - DMAEN: u1, - /// Timeout counter enable - TCEN: u1, - /// Sample shift - SSHIFT: u1, - reserved6: u1, - /// Dual-flash mode - DFM: u1, - /// FLASH memory selection - FSEL: u1, - /// IFO threshold level - FTHRES: u4, - reserved16: u4, - /// Transfer error interrupt enable - TEIE: u1, - /// Transfer complete interrupt enable - TCIE: u1, - /// FIFO threshold interrupt enable - FTIE: u1, - /// Status match interrupt enable - SMIE: u1, - /// TimeOut interrupt enable - TOIE: u1, - reserved22: u1, - /// Automatic poll mode stop - APMS: u1, - /// Polling match mode - PMM: u1, - /// Clock prescaler - PRESCALER: u8, - }), - /// device configuration register - DCR: mmio.Mmio(packed struct(u32) { - /// Mode 0 / mode 3 - CKMODE: u1, - reserved8: u7, - /// Chip select high time - CSHT: u3, - reserved16: u5, - /// FLASH memory size - FSIZE: u5, - padding: u11, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Transfer error flag - TEF: u1, - /// Transfer complete flag - TCF: u1, - /// FIFO threshold flag - FTF: u1, - /// Status match flag - SMF: u1, - /// Timeout flag - TOF: u1, - /// Busy - BUSY: u1, - reserved8: u2, - /// FIFO level - FLEVEL: u7, - padding: u17, - }), - /// flag clear register - FCR: mmio.Mmio(packed struct(u32) { - /// Clear transfer error flag - CTEF: u1, - /// Clear transfer complete flag - CTCF: u1, - reserved3: u1, - /// Clear status match flag - CSMF: u1, - /// Clear timeout flag - CTOF: u1, - padding: u27, - }), - /// data length register - DLR: mmio.Mmio(packed struct(u32) { - /// Data length - DL: u32, - }), - /// communication configuration register - CCR: mmio.Mmio(packed struct(u32) { - /// Instruction - INSTRUCTION: u8, - /// Instruction mode - IMODE: u2, - /// Address mode - ADMODE: u2, - /// Address size - ADSIZE: u2, - /// Alternate bytes mode - ABMODE: u2, - /// Alternate bytes size - ABSIZE: u2, - /// Number of dummy cycles - DCYC: u5, - reserved24: u1, - /// Data mode - DMODE: u2, - /// Functional mode - FMODE: u2, - /// Send instruction only once mode - SIOO: u1, - /// Free-running clock mode (not available on all chips!) - FRCM: u1, - /// DDR hold half cycle - DHHC: u1, - /// Double data rate mode - DDRM: u1, - }), - /// address register - AR: mmio.Mmio(packed struct(u32) { - /// Address - ADDRESS: u32, - }), - /// ABR - ABR: mmio.Mmio(packed struct(u32) { - /// ALTERNATE - ALTERNATE: u32, - }), - /// data register - DR: mmio.Mmio(packed struct(u32) { - /// Data - DATA: u32, - }), - /// polling status mask register - PSMKR: mmio.Mmio(packed struct(u32) { - /// Status mask - MASK: u32, - }), - /// polling status match register - PSMAR: mmio.Mmio(packed struct(u32) { - /// Status match - MATCH: u32, - }), - /// polling interval register - PIR: mmio.Mmio(packed struct(u32) { - /// Polling interval - INTERVAL: u16, - padding: u16, - }), - /// low-power timeout register - LPTR: mmio.Mmio(packed struct(u32) { - /// Timeout period - TIMEOUT: u16, - padding: u16, + reserved2: u2, + /// Random number generator enable + RNGEN: u1, + /// Interrupt enable + IE: u1, + reserved5: u1, + /// Clock error detection + CED: u1, + padding: u26, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Data ready + DRDY: u1, + /// Clock error current status + CECS: u1, + /// Seed error current status + SECS: u1, + reserved5: u2, + /// Clock error interrupt status + CEIS: u1, + /// Seed error interrupt status + SEIS: u1, + padding: u25, }), + /// data register + DR: u32, }; }; - pub const rng_v3 = struct { + pub const rng_v2 = struct { pub const CLKDIV = enum(u4) { /// Internal RNG clock after divider is similar to incoming RNG clock NoDiv = 0x0, @@ -411388,9 +414348,7 @@ pub const types = struct { reserved5: u1, /// Clock error detection CED: u1, - reserved7: u1, - /// Auto reset disable - ARDIS: u1, + reserved8: u2, /// RNG configuration 3 RNG_CONFIG3: packed union { raw: u4, @@ -411404,4303 +414362,3325 @@ pub const types = struct { /// RNG configuration 2 RNG_CONFIG2: packed union { raw: u3, - value: RNG_CONFIG2, - }, - /// Clock divider factor - CLKDIV: packed union { - raw: u4, - value: CLKDIV, - }, - /// RNG configuration 1 - RNG_CONFIG1: packed union { - raw: u6, - value: RNG_CONFIG1, - }, - reserved30: u4, - /// Conditioning soft reset - CONDRST: u1, - /// Config Lock - CONFIGLOCK: u1, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Data ready - DRDY: u1, - /// Clock error current status - CECS: u1, - /// Seed error current status - SECS: u1, - reserved5: u2, - /// Clock error interrupt status - CEIS: u1, - /// Seed error interrupt status - SEIS: u1, - padding: u25, - }), - /// data register - DR: u32, - reserved16: [4]u8, - /// health test control register - HTCR: mmio.Mmio(packed struct(u32) { - /// Health test configuration - HTCFG: packed union { - raw: u32, - value: HTCFG, - }, - }), - }; - }; - - pub const rcc_h7ab = struct { - pub const ADCSEL = enum(u2) { - /// pll2_p selected as peripheral clock - PLL2_P = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// PER selected as peripheral clock - PER = 0x2, - _, - }; - - pub const CECSEL = enum(u2) { - /// LSE selected as peripheral clock - LSE = 0x0, - /// LSI selected as peripheral clock - LSI = 0x1, - /// csi_ker selected as peripheral clock - CSI = 0x2, - _, - }; - - pub const DFSDMSEL = enum(u1) { - /// rcc_pclk2 selected as peripheral clock - PCLK2 = 0x0, - /// System clock selected as peripheral clock - SYS = 0x1, - }; - - pub const FDCANSEL = enum(u2) { - /// HSE selected as peripheral clock - HSE = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x2, - _, - }; - - pub const FMCSEL = enum(u2) { - /// rcc_hclk3 selected as peripheral clock - HCLK3 = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// pll2_r selected as peripheral clock - PLL2_R = 0x2, - /// PER selected as peripheral clock - PER = 0x3, - }; - - pub const HPRE = enum(u4) { - /// sys_ck not divided - Div1 = 0x0, - /// sys_ck divided by 2 - Div2 = 0x8, - /// sys_ck divided by 4 - Div4 = 0x9, - /// sys_ck divided by 8 - Div8 = 0xa, - /// sys_ck divided by 16 - Div16 = 0xb, - /// sys_ck divided by 64 - Div64 = 0xc, - /// sys_ck divided by 128 - Div128 = 0xd, - /// sys_ck divided by 256 - Div256 = 0xe, - /// sys_ck divided by 512 - Div512 = 0xf, - _, - }; - - pub const HRTIMSEL = enum(u1) { - /// The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) - TIMY_KER = 0x0, - /// The HRTIM prescaler clock source is the CPU clock (c_ck) - C_CK = 0x1, - }; - - pub const HSIDIV = enum(u2) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x1, - /// Division by 4 - Div4 = 0x2, - /// Division by 8 - Div8 = 0x3, - }; - - pub const I2C1235SEL = enum(u2) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// hsi_ker selected as peripheral clock - HSI = 0x2, - /// csi_ker selected as peripheral clock - CSI = 0x3, - }; - - pub const I2C4SEL = enum(u2) { - /// rcc_pclk4 selected as peripheral clock - PCLK4 = 0x0, - /// pll3_r selected as peripheral clock - PLL3_R = 0x1, - /// hsi_ker selected as peripheral clock - HSI = 0x2, - /// csi_ker selected as peripheral clock - CSI = 0x3, - }; - - pub const LPTIM1SEL = enum(u3) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_r selected as peripheral clock - PLL3_R = 0x2, - /// LSE selected as peripheral clock - LSE = 0x3, - /// LSI selected as peripheral clock - LSI = 0x4, - /// PER selected as peripheral clock - PER = 0x5, - _, - }; - - pub const LPTIM2SEL = enum(u3) { - /// rcc_pclk4 selected as peripheral clock - PCLK4 = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_r selected as peripheral clock - PLL3_R = 0x2, - /// LSE selected as peripheral clock - LSE = 0x3, - /// LSI selected as peripheral clock - LSI = 0x4, - /// PER selected as peripheral clock - PER = 0x5, - _, - }; - - pub const LPUARTSEL = enum(u3) { - /// rcc_pclk_d4 selected as peripheral clock - PCLK4 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, - _, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCO1SEL = enum(u3) { - /// HSI selected for micro-controller clock output - HSI = 0x0, - /// LSE selected for micro-controller clock output - LSE = 0x1, - /// HSE selected for micro-controller clock output - HSE = 0x2, - /// pll1_q selected for micro-controller clock output - PLL1_Q = 0x3, - /// HSI48 selected for micro-controller clock output - HSI48 = 0x4, - _, - }; - - pub const MCO2SEL = enum(u3) { - /// System clock selected for micro-controller clock output - SYS = 0x0, - /// pll2_p selected for micro-controller clock output - PLL2_P = 0x1, - /// HSE selected for micro-controller clock output - HSE = 0x2, - /// pll1_p selected for micro-controller clock output - PLL1_P = 0x3, - /// CSI selected for micro-controller clock output - CSI = 0x4, - /// LSI selected for micro-controller clock output - LSI = 0x5, - _, - }; - - pub const MCOPRE = enum(u4) { - /// Divide by 1 - Div1 = 0x1, - /// Divide by 2 - Div2 = 0x2, - /// Divide by 3 - Div3 = 0x3, - /// Divide by 4 - Div4 = 0x4, - /// Divide by 5 - Div5 = 0x5, - /// Divide by 6 - Div6 = 0x6, - /// Divide by 7 - Div7 = 0x7, - /// Divide by 8 - Div8 = 0x8, - /// Divide by 9 - Div9 = 0x9, - /// Divide by 10 - Div10 = 0xa, - /// Divide by 11 - Div11 = 0xb, - /// Divide by 12 - Div12 = 0xc, - /// Divide by 13 - Div13 = 0xd, - /// Divide by 14 - Div14 = 0xe, - /// Divide by 15 - Div15 = 0xf, - _, - }; - - pub const PERSEL = enum(u2) { - /// HSI selected as peripheral clock - HSI = 0x0, - /// CSI selected as peripheral clock - CSI = 0x1, - /// HSE selected as peripheral clock - HSE = 0x2, - _, - }; - - pub const PLLDIV = enum(u7) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, - Div17 = 0x10, - Div18 = 0x11, - Div19 = 0x12, - Div20 = 0x13, - Div21 = 0x14, - Div22 = 0x15, - Div23 = 0x16, - Div24 = 0x17, - Div25 = 0x18, - Div26 = 0x19, - Div27 = 0x1a, - Div28 = 0x1b, - Div29 = 0x1c, - Div30 = 0x1d, - Div31 = 0x1e, - Div32 = 0x1f, - Div33 = 0x20, - Div34 = 0x21, - Div35 = 0x22, - Div36 = 0x23, - Div37 = 0x24, - Div38 = 0x25, - Div39 = 0x26, - Div40 = 0x27, - Div41 = 0x28, - Div42 = 0x29, - Div43 = 0x2a, - Div44 = 0x2b, - Div45 = 0x2c, - Div46 = 0x2d, - Div47 = 0x2e, - Div48 = 0x2f, - Div49 = 0x30, - Div50 = 0x31, - Div51 = 0x32, - Div52 = 0x33, - Div53 = 0x34, - Div54 = 0x35, - Div55 = 0x36, - Div56 = 0x37, - Div57 = 0x38, - Div58 = 0x39, - Div59 = 0x3a, - Div60 = 0x3b, - Div61 = 0x3c, - Div62 = 0x3d, - Div63 = 0x3e, - Div64 = 0x3f, - Div65 = 0x40, - Div66 = 0x41, - Div67 = 0x42, - Div68 = 0x43, - Div69 = 0x44, - Div70 = 0x45, - Div71 = 0x46, - Div72 = 0x47, - Div73 = 0x48, - Div74 = 0x49, - Div75 = 0x4a, - Div76 = 0x4b, - Div77 = 0x4c, - Div78 = 0x4d, - Div79 = 0x4e, - Div80 = 0x4f, - Div81 = 0x50, - Div82 = 0x51, - Div83 = 0x52, - Div84 = 0x53, - Div85 = 0x54, - Div86 = 0x55, - Div87 = 0x56, - Div88 = 0x57, - Div89 = 0x58, - Div90 = 0x59, - Div91 = 0x5a, - Div92 = 0x5b, - Div93 = 0x5c, - Div94 = 0x5d, - Div95 = 0x5e, - Div96 = 0x5f, - Div97 = 0x60, - Div98 = 0x61, - Div99 = 0x62, - Div100 = 0x63, - Div101 = 0x64, - Div102 = 0x65, - Div103 = 0x66, - Div104 = 0x67, - Div105 = 0x68, - Div106 = 0x69, - Div107 = 0x6a, - Div108 = 0x6b, - Div109 = 0x6c, - Div110 = 0x6d, - Div111 = 0x6e, - Div112 = 0x6f, - Div113 = 0x70, - Div114 = 0x71, - Div115 = 0x72, - Div116 = 0x73, - Div117 = 0x74, - Div118 = 0x75, - Div119 = 0x76, - Div120 = 0x77, - Div121 = 0x78, - Div122 = 0x79, - Div123 = 0x7a, - Div124 = 0x7b, - Div125 = 0x7c, - Div126 = 0x7d, - Div127 = 0x7e, - Div128 = 0x7f, - }; - - pub const PLLM = enum(u6) { - Div1 = 0x1, - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - Div16 = 0x10, - Div17 = 0x11, - Div18 = 0x12, - Div19 = 0x13, - Div20 = 0x14, - Div21 = 0x15, - Div22 = 0x16, - Div23 = 0x17, - Div24 = 0x18, - Div25 = 0x19, - Div26 = 0x1a, - Div27 = 0x1b, - Div28 = 0x1c, - Div29 = 0x1d, - Div30 = 0x1e, - Div31 = 0x1f, - Div32 = 0x20, - Div33 = 0x21, - Div34 = 0x22, - Div35 = 0x23, - Div36 = 0x24, - Div37 = 0x25, - Div38 = 0x26, - Div39 = 0x27, - Div40 = 0x28, - Div41 = 0x29, - Div42 = 0x2a, - Div43 = 0x2b, - Div44 = 0x2c, - Div45 = 0x2d, - Div46 = 0x2e, - Div47 = 0x2f, - Div48 = 0x30, - Div49 = 0x31, - Div50 = 0x32, - Div51 = 0x33, - Div52 = 0x34, - Div53 = 0x35, - Div54 = 0x36, - Div55 = 0x37, - Div56 = 0x38, - Div57 = 0x39, - Div58 = 0x3a, - Div59 = 0x3b, - Div60 = 0x3c, - Div61 = 0x3d, - Div62 = 0x3e, - _, - }; - - pub const PLLN = enum(u9) { - Mul4 = 0x3, - Mul5 = 0x4, - Mul6 = 0x5, - Mul7 = 0x6, - Mul8 = 0x7, - Mul9 = 0x8, - Mul10 = 0x9, - Mul11 = 0xa, - Mul12 = 0xb, - Mul13 = 0xc, - Mul14 = 0xd, - Mul15 = 0xe, - Mul16 = 0xf, - Mul17 = 0x10, - Mul18 = 0x11, - Mul19 = 0x12, - Mul20 = 0x13, - Mul21 = 0x14, - Mul22 = 0x15, - Mul23 = 0x16, - Mul24 = 0x17, - Mul25 = 0x18, - Mul26 = 0x19, - Mul27 = 0x1a, - Mul28 = 0x1b, - Mul29 = 0x1c, - Mul30 = 0x1d, - Mul31 = 0x1e, - Mul32 = 0x1f, - Mul33 = 0x20, - Mul34 = 0x21, - Mul35 = 0x22, - Mul36 = 0x23, - Mul37 = 0x24, - Mul38 = 0x25, - Mul39 = 0x26, - Mul40 = 0x27, - Mul41 = 0x28, - Mul42 = 0x29, - Mul43 = 0x2a, - Mul44 = 0x2b, - Mul45 = 0x2c, - Mul46 = 0x2d, - Mul47 = 0x2e, - Mul48 = 0x2f, - Mul49 = 0x30, - Mul50 = 0x31, - Mul51 = 0x32, - Mul52 = 0x33, - Mul53 = 0x34, - Mul54 = 0x35, - Mul55 = 0x36, - Mul56 = 0x37, - Mul57 = 0x38, - Mul58 = 0x39, - Mul59 = 0x3a, - Mul60 = 0x3b, - Mul61 = 0x3c, - Mul62 = 0x3d, - Mul63 = 0x3e, - Mul64 = 0x3f, - Mul65 = 0x40, - Mul66 = 0x41, - Mul67 = 0x42, - Mul68 = 0x43, - Mul69 = 0x44, - Mul70 = 0x45, - Mul71 = 0x46, - Mul72 = 0x47, - Mul73 = 0x48, - Mul74 = 0x49, - Mul75 = 0x4a, - Mul76 = 0x4b, - Mul77 = 0x4c, - Mul78 = 0x4d, - Mul79 = 0x4e, - Mul80 = 0x4f, - Mul81 = 0x50, - Mul82 = 0x51, - Mul83 = 0x52, - Mul84 = 0x53, - Mul85 = 0x54, - Mul86 = 0x55, - Mul87 = 0x56, - Mul88 = 0x57, - Mul89 = 0x58, - Mul90 = 0x59, - Mul91 = 0x5a, - Mul92 = 0x5b, - Mul93 = 0x5c, - Mul94 = 0x5d, - Mul95 = 0x5e, - Mul96 = 0x5f, - Mul97 = 0x60, - Mul98 = 0x61, - Mul99 = 0x62, - Mul100 = 0x63, - Mul101 = 0x64, - Mul102 = 0x65, - Mul103 = 0x66, - Mul104 = 0x67, - Mul105 = 0x68, - Mul106 = 0x69, - Mul107 = 0x6a, - Mul108 = 0x6b, - Mul109 = 0x6c, - Mul110 = 0x6d, - Mul111 = 0x6e, - Mul112 = 0x6f, - Mul113 = 0x70, - Mul114 = 0x71, - Mul115 = 0x72, - Mul116 = 0x73, - Mul117 = 0x74, - Mul118 = 0x75, - Mul119 = 0x76, - Mul120 = 0x77, - Mul121 = 0x78, - Mul122 = 0x79, - Mul123 = 0x7a, - Mul124 = 0x7b, - Mul125 = 0x7c, - Mul126 = 0x7d, - Mul127 = 0x7e, - Mul128 = 0x7f, - Mul129 = 0x80, - Mul130 = 0x81, - Mul131 = 0x82, - Mul132 = 0x83, - Mul133 = 0x84, - Mul134 = 0x85, - Mul135 = 0x86, - Mul136 = 0x87, - Mul137 = 0x88, - Mul138 = 0x89, - Mul139 = 0x8a, - Mul140 = 0x8b, - Mul141 = 0x8c, - Mul142 = 0x8d, - Mul143 = 0x8e, - Mul144 = 0x8f, - Mul145 = 0x90, - Mul146 = 0x91, - Mul147 = 0x92, - Mul148 = 0x93, - Mul149 = 0x94, - Mul150 = 0x95, - Mul151 = 0x96, - Mul152 = 0x97, - Mul153 = 0x98, - Mul154 = 0x99, - Mul155 = 0x9a, - Mul156 = 0x9b, - Mul157 = 0x9c, - Mul158 = 0x9d, - Mul159 = 0x9e, - Mul160 = 0x9f, - Mul161 = 0xa0, - Mul162 = 0xa1, - Mul163 = 0xa2, - Mul164 = 0xa3, - Mul165 = 0xa4, - Mul166 = 0xa5, - Mul167 = 0xa6, - Mul168 = 0xa7, - Mul169 = 0xa8, - Mul170 = 0xa9, - Mul171 = 0xaa, - Mul172 = 0xab, - Mul173 = 0xac, - Mul174 = 0xad, - Mul175 = 0xae, - Mul176 = 0xaf, - Mul177 = 0xb0, - Mul178 = 0xb1, - Mul179 = 0xb2, - Mul180 = 0xb3, - Mul181 = 0xb4, - Mul182 = 0xb5, - Mul183 = 0xb6, - Mul184 = 0xb7, - Mul185 = 0xb8, - Mul186 = 0xb9, - Mul187 = 0xba, - Mul188 = 0xbb, - Mul189 = 0xbc, - Mul190 = 0xbd, - Mul191 = 0xbe, - Mul192 = 0xbf, - Mul193 = 0xc0, - Mul194 = 0xc1, - Mul195 = 0xc2, - Mul196 = 0xc3, - Mul197 = 0xc4, - Mul198 = 0xc5, - Mul199 = 0xc6, - Mul200 = 0xc7, - Mul201 = 0xc8, - Mul202 = 0xc9, - Mul203 = 0xca, - Mul204 = 0xcb, - Mul205 = 0xcc, - Mul206 = 0xcd, - Mul207 = 0xce, - Mul208 = 0xcf, - Mul209 = 0xd0, - Mul210 = 0xd1, - Mul211 = 0xd2, - Mul212 = 0xd3, - Mul213 = 0xd4, - Mul214 = 0xd5, - Mul215 = 0xd6, - Mul216 = 0xd7, - Mul217 = 0xd8, - Mul218 = 0xd9, - Mul219 = 0xda, - Mul220 = 0xdb, - Mul221 = 0xdc, - Mul222 = 0xdd, - Mul223 = 0xde, - Mul224 = 0xdf, - Mul225 = 0xe0, - Mul226 = 0xe1, - Mul227 = 0xe2, - Mul228 = 0xe3, - Mul229 = 0xe4, - Mul230 = 0xe5, - Mul231 = 0xe6, - Mul232 = 0xe7, - Mul233 = 0xe8, - Mul234 = 0xe9, - Mul235 = 0xea, - Mul236 = 0xeb, - Mul237 = 0xec, - Mul238 = 0xed, - Mul239 = 0xee, - Mul240 = 0xef, - Mul241 = 0xf0, - Mul242 = 0xf1, - Mul243 = 0xf2, - Mul244 = 0xf3, - Mul245 = 0xf4, - Mul246 = 0xf5, - Mul247 = 0xf6, - Mul248 = 0xf7, - Mul249 = 0xf8, - Mul250 = 0xf9, - Mul251 = 0xfa, - Mul252 = 0xfb, - Mul253 = 0xfc, - Mul254 = 0xfd, - Mul255 = 0xfe, - Mul256 = 0xff, - Mul257 = 0x100, - Mul258 = 0x101, - Mul259 = 0x102, - Mul260 = 0x103, - Mul261 = 0x104, - Mul262 = 0x105, - Mul263 = 0x106, - Mul264 = 0x107, - Mul265 = 0x108, - Mul266 = 0x109, - Mul267 = 0x10a, - Mul268 = 0x10b, - Mul269 = 0x10c, - Mul270 = 0x10d, - Mul271 = 0x10e, - Mul272 = 0x10f, - Mul273 = 0x110, - Mul274 = 0x111, - Mul275 = 0x112, - Mul276 = 0x113, - Mul277 = 0x114, - Mul278 = 0x115, - Mul279 = 0x116, - Mul280 = 0x117, - Mul281 = 0x118, - Mul282 = 0x119, - Mul283 = 0x11a, - Mul284 = 0x11b, - Mul285 = 0x11c, - Mul286 = 0x11d, - Mul287 = 0x11e, - Mul288 = 0x11f, - Mul289 = 0x120, - Mul290 = 0x121, - Mul291 = 0x122, - Mul292 = 0x123, - Mul293 = 0x124, - Mul294 = 0x125, - Mul295 = 0x126, - Mul296 = 0x127, - Mul297 = 0x128, - Mul298 = 0x129, - Mul299 = 0x12a, - Mul300 = 0x12b, - Mul301 = 0x12c, - Mul302 = 0x12d, - Mul303 = 0x12e, - Mul304 = 0x12f, - Mul305 = 0x130, - Mul306 = 0x131, - Mul307 = 0x132, - Mul308 = 0x133, - Mul309 = 0x134, - Mul310 = 0x135, - Mul311 = 0x136, - Mul312 = 0x137, - Mul313 = 0x138, - Mul314 = 0x139, - Mul315 = 0x13a, - Mul316 = 0x13b, - Mul317 = 0x13c, - Mul318 = 0x13d, - Mul319 = 0x13e, - Mul320 = 0x13f, - Mul321 = 0x140, - Mul322 = 0x141, - Mul323 = 0x142, - Mul324 = 0x143, - Mul325 = 0x144, - Mul326 = 0x145, - Mul327 = 0x146, - Mul328 = 0x147, - Mul329 = 0x148, - Mul330 = 0x149, - Mul331 = 0x14a, - Mul332 = 0x14b, - Mul333 = 0x14c, - Mul334 = 0x14d, - Mul335 = 0x14e, - Mul336 = 0x14f, - Mul337 = 0x150, - Mul338 = 0x151, - Mul339 = 0x152, - Mul340 = 0x153, - Mul341 = 0x154, - Mul342 = 0x155, - Mul343 = 0x156, - Mul344 = 0x157, - Mul345 = 0x158, - Mul346 = 0x159, - Mul347 = 0x15a, - Mul348 = 0x15b, - Mul349 = 0x15c, - Mul350 = 0x15d, - Mul351 = 0x15e, - Mul352 = 0x15f, - Mul353 = 0x160, - Mul354 = 0x161, - Mul355 = 0x162, - Mul356 = 0x163, - Mul357 = 0x164, - Mul358 = 0x165, - Mul359 = 0x166, - Mul360 = 0x167, - Mul361 = 0x168, - Mul362 = 0x169, - Mul363 = 0x16a, - Mul364 = 0x16b, - Mul365 = 0x16c, - Mul366 = 0x16d, - Mul367 = 0x16e, - Mul368 = 0x16f, - Mul369 = 0x170, - Mul370 = 0x171, - Mul371 = 0x172, - Mul372 = 0x173, - Mul373 = 0x174, - Mul374 = 0x175, - Mul375 = 0x176, - Mul376 = 0x177, - Mul377 = 0x178, - Mul378 = 0x179, - Mul379 = 0x17a, - Mul380 = 0x17b, - Mul381 = 0x17c, - Mul382 = 0x17d, - Mul383 = 0x17e, - Mul384 = 0x17f, - Mul385 = 0x180, - Mul386 = 0x181, - Mul387 = 0x182, - Mul388 = 0x183, - Mul389 = 0x184, - Mul390 = 0x185, - Mul391 = 0x186, - Mul392 = 0x187, - Mul393 = 0x188, - Mul394 = 0x189, - Mul395 = 0x18a, - Mul396 = 0x18b, - Mul397 = 0x18c, - Mul398 = 0x18d, - Mul399 = 0x18e, - Mul400 = 0x18f, - Mul401 = 0x190, - Mul402 = 0x191, - Mul403 = 0x192, - Mul404 = 0x193, - Mul405 = 0x194, - Mul406 = 0x195, - Mul407 = 0x196, - Mul408 = 0x197, - Mul409 = 0x198, - Mul410 = 0x199, - Mul411 = 0x19a, - Mul412 = 0x19b, - Mul413 = 0x19c, - Mul414 = 0x19d, - Mul415 = 0x19e, - Mul416 = 0x19f, - Mul417 = 0x1a0, - Mul418 = 0x1a1, - Mul419 = 0x1a2, - Mul420 = 0x1a3, - Mul421 = 0x1a4, - Mul422 = 0x1a5, - Mul423 = 0x1a6, - Mul424 = 0x1a7, - Mul425 = 0x1a8, - Mul426 = 0x1a9, - Mul427 = 0x1aa, - Mul428 = 0x1ab, - Mul429 = 0x1ac, - Mul430 = 0x1ad, - Mul431 = 0x1ae, - Mul432 = 0x1af, - Mul433 = 0x1b0, - Mul434 = 0x1b1, - Mul435 = 0x1b2, - Mul436 = 0x1b3, - Mul437 = 0x1b4, - Mul438 = 0x1b5, - Mul439 = 0x1b6, - Mul440 = 0x1b7, - Mul441 = 0x1b8, - Mul442 = 0x1b9, - Mul443 = 0x1ba, - Mul444 = 0x1bb, - Mul445 = 0x1bc, - Mul446 = 0x1bd, - Mul447 = 0x1be, - Mul448 = 0x1bf, - Mul449 = 0x1c0, - Mul450 = 0x1c1, - Mul451 = 0x1c2, - Mul452 = 0x1c3, - Mul453 = 0x1c4, - Mul454 = 0x1c5, - Mul455 = 0x1c6, - Mul456 = 0x1c7, - Mul457 = 0x1c8, - Mul458 = 0x1c9, - Mul459 = 0x1ca, - Mul460 = 0x1cb, - Mul461 = 0x1cc, - Mul462 = 0x1cd, - Mul463 = 0x1ce, - Mul464 = 0x1cf, - Mul465 = 0x1d0, - Mul466 = 0x1d1, - Mul467 = 0x1d2, - Mul468 = 0x1d3, - Mul469 = 0x1d4, - Mul470 = 0x1d5, - Mul471 = 0x1d6, - Mul472 = 0x1d7, - Mul473 = 0x1d8, - Mul474 = 0x1d9, - Mul475 = 0x1da, - Mul476 = 0x1db, - Mul477 = 0x1dc, - Mul478 = 0x1dd, - Mul479 = 0x1de, - Mul480 = 0x1df, - Mul481 = 0x1e0, - Mul482 = 0x1e1, - Mul483 = 0x1e2, - Mul484 = 0x1e3, - Mul485 = 0x1e4, - Mul486 = 0x1e5, - Mul487 = 0x1e6, - Mul488 = 0x1e7, - Mul489 = 0x1e8, - Mul490 = 0x1e9, - Mul491 = 0x1ea, - Mul492 = 0x1eb, - Mul493 = 0x1ec, - Mul494 = 0x1ed, - Mul495 = 0x1ee, - Mul496 = 0x1ef, - Mul497 = 0x1f0, - Mul498 = 0x1f1, - Mul499 = 0x1f2, - Mul500 = 0x1f3, - Mul501 = 0x1f4, - Mul502 = 0x1f5, - Mul503 = 0x1f6, - Mul504 = 0x1f7, - Mul505 = 0x1f8, - Mul506 = 0x1f9, - Mul507 = 0x1fa, - Mul508 = 0x1fb, - Mul509 = 0x1fc, - Mul510 = 0x1fd, - Mul511 = 0x1fe, - Mul512 = 0x1ff, + value: RNG_CONFIG2, + }, + /// Clock divider factor + CLKDIV: packed union { + raw: u4, + value: CLKDIV, + }, + /// RNG configuration 1 + RNG_CONFIG1: packed union { + raw: u6, + value: RNG_CONFIG1, + }, + reserved30: u4, + /// Conditioning soft reset + CONDRST: u1, + /// Config Lock + CONFIGLOCK: u1, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Data ready + DRDY: u1, + /// Clock error current status + CECS: u1, + /// Seed error current status + SECS: u1, + reserved5: u2, + /// Clock error interrupt status + CEIS: u1, + /// Seed error interrupt status + SEIS: u1, + padding: u25, + }), + /// data register + DR: u32, + reserved16: [4]u8, + /// health test control register + HTCR: mmio.Mmio(packed struct(u32) { + /// Health test configuration + HTCFG: packed union { + raw: u32, + value: HTCFG, + }, + }), + }; + }; + + pub const rng_v3 = struct { + pub const CLKDIV = enum(u4) { + /// Internal RNG clock after divider is similar to incoming RNG clock + NoDiv = 0x0, + /// Divide RNG clock by 2^1 + Div_2_1 = 0x1, + /// Divide RNG clock by 2^2 + Div_2_2 = 0x2, + /// Divide RNG clock by 2^3 + Div_2_3 = 0x3, + /// Divide RNG clock by 2^4 + Div_2_4 = 0x4, + /// Divide RNG clock by 2^5 + Div_2_5 = 0x5, + /// Divide RNG clock by 2^6 + Div_2_6 = 0x6, + /// Divide RNG clock by 2^7 + Div_2_7 = 0x7, + /// Divide RNG clock by 2^8 + Div_2_8 = 0x8, + /// Divide RNG clock by 2^9 + Div_2_9 = 0x9, + /// Divide RNG clock by 2^10 + Div_2_10 = 0xa, + /// Divide RNG clock by 2^11 + Div_2_11 = 0xb, + /// Divide RNG clock by 2^12 + Div_2_12 = 0xc, + /// Divide RNG clock by 2^13 + Div_2_13 = 0xd, + /// Divide RNG clock by 2^14 + Div_2_14 = 0xe, + /// Divide RNG clock by 2^15 + Div_2_15 = 0xf, + }; + + pub const HTCFG = enum(u32) { + /// Recommended value for RNG certification (0x0000_AA74) + Recommended = 0xaa74, + /// Magic number to be written before any write (0x1759_0ABC) + Magic = 0x17590abc, _, }; - pub const PLLRGE = enum(u2) { - /// Frequency is between 1 and 2 MHz - Range1 = 0x0, - /// Frequency is between 2 and 4 MHz - Range2 = 0x1, - /// Frequency is between 4 and 8 MHz - Range4 = 0x2, - /// Frequency is between 8 and 16 MHz - Range8 = 0x3, + pub const NISTC = enum(u1) { + /// Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used + Default = 0x0, + /// Custom values for NIST compliant RNG + Custom = 0x1, }; - pub const PLLSRC = enum(u2) { - /// HSI selected as PLL clock - HSI = 0x0, - /// CSI selected as PLL clock - CSI = 0x1, - /// HSE selected as PLL clock - HSE = 0x2, - /// No clock sent to DIVMx dividers and PLLs - DISABLE = 0x3, + pub const RNG_CONFIG1 = enum(u6) { + /// Recommended value for config A (NIST certifiable) + ConfigA = 0xf, + /// Recommended value for config B (not NIST certifiable) + ConfigB = 0x18, + _, }; - pub const PLLVCOSEL = enum(u1) { - /// VCO frequency range 192 to 836 MHz - WideVCO = 0x0, - /// VCO frequency range 150 to 420 MHz - MediumVCO = 0x1, + pub const RNG_CONFIG2 = enum(u3) { + /// Recommended value for config A and B + ConfigA_B = 0x0, + _, }; - pub const PPRE = enum(u3) { - /// rcc_hclk not divided - Div1 = 0x0, - /// rcc_hclk divided by 2 - Div2 = 0x4, - /// rcc_hclk divided by 4 - Div4 = 0x5, - /// rcc_hclk divided by 8 - Div8 = 0x6, - /// rcc_hclk divided by 16 - Div16 = 0x7, + pub const RNG_CONFIG3 = enum(u4) { + /// Recommended value for config B (not NIST certifiable) + ConfigB = 0x0, + /// Recommended value for config A (NIST certifiable) + ConfigA = 0xd, _, }; - pub const RNGSEL = enum(u2) { - /// HSI48 selected as peripheral clock - HSI48 = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// LSE selected as peripheral clock - LSE = 0x2, - /// LSI selected as peripheral clock - LSI = 0x3, + /// Random number generator + pub const RNG = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Random number generator enable + RNGEN: u1, + /// Interrupt enable + IE: u1, + reserved5: u1, + /// Clock error detection + CED: u1, + reserved7: u1, + /// Auto reset disable + ARDIS: u1, + /// RNG configuration 3 + RNG_CONFIG3: packed union { + raw: u4, + value: RNG_CONFIG3, + }, + /// Non NIST compliant + NISTC: packed union { + raw: u1, + value: NISTC, + }, + /// RNG configuration 2 + RNG_CONFIG2: packed union { + raw: u3, + value: RNG_CONFIG2, + }, + /// Clock divider factor + CLKDIV: packed union { + raw: u4, + value: CLKDIV, + }, + /// RNG configuration 1 + RNG_CONFIG1: packed union { + raw: u6, + value: RNG_CONFIG1, + }, + reserved30: u4, + /// Conditioning soft reset + CONDRST: u1, + /// Config Lock + CONFIGLOCK: u1, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Data ready + DRDY: u1, + /// Clock error current status + CECS: u1, + /// Seed error current status + SECS: u1, + reserved5: u2, + /// Clock error interrupt status + CEIS: u1, + /// Seed error interrupt status + SEIS: u1, + padding: u25, + }), + /// data register + DR: u32, + reserved16: [4]u8, + /// health test control register + HTCR: mmio.Mmio(packed struct(u32) { + /// Health test configuration + HTCFG: packed union { + raw: u32, + value: HTCFG, + }, + }), }; + }; - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, + pub const rtc_v1 = struct { + pub const RTOFF = enum(u1) { + /// Last write operation on RTC registers is still ongoing + Ongoing = 0x0, + /// Last write operation on RTC registers terminated + Terminated = 0x1, }; - pub const SAIASEL = enum(u3) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_p selected as peripheral clock - PLL3_P = 0x2, - /// i2s_ckin selected as peripheral clock - I2S_CKIN = 0x3, - /// PER selected as peripheral clock - PER = 0x4, - _, + /// Real-time clock + pub const RTC = extern struct { + /// Control Register High + CRH: mmio.Mmio(packed struct(u32) { + /// Second interrupt enable + SECIE: u1, + /// Alarm interrupt enable + ALRIE: u1, + /// Overflow interrupt enable + OWIE: u1, + padding: u29, + }), + /// Control Register Low + CRL: mmio.Mmio(packed struct(u32) { + /// Second flag + SECF: u1, + /// Alarm flag + ALRF: u1, + /// Overflow flag + OWF: u1, + /// Registers synchronized flag + RSF: u1, + /// Enter configuration mode + CNF: u1, + /// RTC operation OFF + RTOFF: packed union { + raw: u1, + value: RTOFF, + }, + padding: u26, + }), + /// Prescaler Load Register High + PRLH: mmio.Mmio(packed struct(u32) { + /// Prescaler load register high + PRLH: u4, + padding: u28, + }), + /// Prescaler Load Register Low + PRLL: mmio.Mmio(packed struct(u32) { + /// Prescaler divider register low + PRLL: u16, + padding: u16, + }), + /// Prescaler Divider Register High + DIVH: mmio.Mmio(packed struct(u32) { + /// Prescaler divider register high + DIVH: u4, + padding: u28, + }), + /// Prescaler Divider Register Low + DIVL: mmio.Mmio(packed struct(u32) { + /// Prescaler divider register low + DIVL: u16, + padding: u16, + }), + /// Counter Register High + CNTH: mmio.Mmio(packed struct(u32) { + /// Counter register high + CNTH: u16, + padding: u16, + }), + /// Counter Register Low + CNTL: mmio.Mmio(packed struct(u32) { + /// Counter register low + CNTL: u16, + padding: u16, + }), + /// Alarm Register High + ALRH: mmio.Mmio(packed struct(u32) { + /// Alarm register high + ALRH: u16, + padding: u16, + }), + /// Alarm Register Low + ALRL: mmio.Mmio(packed struct(u32) { + /// Alarm register low + ALRL: u16, + padding: u16, + }), }; + }; - pub const SAISEL = enum(u3) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_p selected as peripheral clock - PLL2_P = 0x1, - /// pll3_p selected as peripheral clock - PLL3_P = 0x2, - /// I2S_CKIN selected as peripheral clock - I2S_CKIN = 0x3, - /// PER selected as peripheral clock - PER = 0x4, - _, + pub const rtc_v2f0 = struct { + pub const ALRMR_MSK = enum(u1) { + /// Alarm set if the date/day match + ToMatch = 0x0, + /// Date/day don’t care in Alarm comparison + NotMatch = 0x1, }; - pub const SDMMCSEL = enum(u1) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_r selected as peripheral clock - PLL2_R = 0x1, + pub const ALRMR_PM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, }; - pub const SPDIFRXSEL = enum(u2) { - /// pll1_q selected as peripheral clock - PLL1_Q = 0x0, - /// pll2_r selected as peripheral clock - PLL2_R = 0x1, - /// pll3_r selected as peripheral clock - PLL3_R = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, + pub const ALRMR_WDSEL = enum(u1) { + /// DU[3:0] represents the date units + DateUnits = 0x0, + /// DU[3:0] represents the week day. DT[1:0] is don’t care + WeekDay = 0x1, }; - pub const SPI45SEL = enum(u3) { - /// APB2 clock selected as peripheral clock - PCLK2 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// HSE selected as peripheral clock - HSE = 0x5, + pub const AMPM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const CALP = enum(u1) { + /// No RTCCLK pulses are added + NoChange = 0x0, + /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + IncreaseFreq = 0x1, + }; + + pub const CALW16 = enum(u1) { + /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + Sixteen_Second = 0x1, _, }; - pub const SPI6SEL = enum(u3) { - /// rcc_pclk4 selected as peripheral clock - PCLK4 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// HSE selected as peripheral clock - HSE = 0x5, + pub const CALW8 = enum(u1) { + /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + Eight_Second = 0x1, _, }; - pub const STOPWUCK = enum(u1) { - /// HSI selected as wake up clock from system Stop - HSI = 0x0, - /// CSI selected as wake up clock from system Stop - CSI = 0x1, + pub const COSEL = enum(u1) { + /// Calibration output is 512 Hz (with default prescaler setting) + CalFreq_512Hz = 0x0, + /// Calibration output is 1 Hz (with default prescaler setting) + CalFreq_1Hz = 0x1, }; - pub const SW = enum(u3) { - /// HSI selected as system clock - HSI = 0x0, - /// CSI selected as system clock - CSI = 0x1, - /// HSE selected as system clock - HSE = 0x2, - /// PLL1 selected as system clock - PLL1_P = 0x3, + pub const FMT = enum(u1) { + /// 24 hour/day format + Twenty_Four_Hour = 0x0, + /// AM/PM hour format + AM_PM = 0x1, + }; + + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Wakeup output enabled + Wakeup = 0x3, _, }; - pub const SWPMISEL = enum(u1) { - /// pclk selected as peripheral clock - PCLK1 = 0x0, - /// hsi_ker selected as peripheral clock - HSI = 0x1, + pub const PCMODE = enum(u1) { + /// PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode + Floating = 0x0, + /// PCx is forced to push-pull output if LSE is disabled + PushPull = 0x1, }; - pub const TIMPRE = enum(u1) { - /// Timer kernel clock equal to 2x pclk by default - DefaultX2 = 0x0, - /// Timer kernel clock equal to 4x pclk by default - DefaultX4 = 0x1, + pub const PCVALUE = enum(u1) { + /// If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low + Low = 0x0, + /// If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high + High = 0x1, }; - pub const USART16910SEL = enum(u3) { - /// rcc_pclk2 selected as peripheral clock - PCLK2 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, - _, + pub const POL = enum(u1) { + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + Low = 0x1, }; - pub const USART234578SEL = enum(u3) { - /// rcc_pclk1 selected as peripheral clock - PCLK1 = 0x0, - /// pll2_q selected as peripheral clock - PLL2_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// hsi_ker selected as peripheral clock - HSI = 0x3, - /// csi_ker selected as peripheral clock - CSI = 0x4, - /// LSE selected as peripheral clock - LSE = 0x5, - _, + pub const TAMPFLT = enum(u2) { + /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + Immediate = 0x0, + /// Tamper event is activated after 2 consecutive samples at the active level + Samples2 = 0x1, + /// Tamper event is activated after 4 consecutive samples at the active level + Samples4 = 0x2, + /// Tamper event is activated after 8 consecutive samples at the active level + Samples8 = 0x3, }; - pub const USBSEL = enum(u2) { - /// Disable the kernel clock - DISABLE = 0x0, - /// pll1_q selected as peripheral clock - PLL1_Q = 0x1, - /// pll3_q selected as peripheral clock - PLL3_Q = 0x2, - /// HSI48 selected as peripheral clock - HSI48 = 0x3, + pub const TAMPFREQ = enum(u3) { + /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + Div32768 = 0x0, + /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + Div16384 = 0x1, + /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + Div8192 = 0x2, + /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + Div4096 = 0x3, + /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + Div2048 = 0x4, + /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + Div1024 = 0x5, + /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + Div512 = 0x6, + /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + Div256 = 0x7, }; - /// Reset and clock control - pub const RCC = extern struct { - /// clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal high-speed clock enable - HSION: u1, - /// High Speed Internal clock enable in Stop mode - HSIKERON: u1, - /// HSI clock ready flag - HSIRDY: u1, - /// HSI clock divider - HSIDIV: packed union { - raw: u2, - value: HSIDIV, + pub const TAMPPRCH = enum(u2) { + /// 1 RTCCLK cycle + Cycles1 = 0x0, + /// 2 RTCCLK cycles + Cycles2 = 0x1, + /// 4 RTCCLK cycles + Cycles4 = 0x2, + /// 8 RTCCLK cycles + Cycles8 = 0x3, + }; + + pub const TAMPPUDIS = enum(u1) { + /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + Enabled = 0x0, + /// Disable precharge of RTC_TAMPx pins + Disabled = 0x1, + }; + + pub const TAMPTRG = enum(u1) { + /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. + RisingEdge = 0x0, + /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event + FallingEdge = 0x1, + }; + + pub const TSEDGE = enum(u1) { + /// RTC_TS input rising edge generates a time-stamp event + RisingEdge = 0x0, + /// RTC_TS input falling edge generates a time-stamp event + FallingEdge = 0x1, + }; + + pub const WUCKSEL = enum(u3) { + /// RTC/16 clock is selected + Div16 = 0x0, + /// RTC/8 clock is selected + Div8 = 0x1, + /// RTC/4 clock is selected + Div4 = 0x2, + /// RTC/2 clock is selected + Div2 = 0x3, + /// ck_spre (usually 1 Hz) clock is selected + ClockSpare = 0x4, + /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + ClockSpareWithOffset = 0x6, + _, + }; + + /// Real-time clock + pub const RTC = extern struct { + /// Time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, }, - /// HSI divider flag - HSIDIVF: u1, - reserved7: u1, - /// CSI clock enable - CSION: u1, - /// CSI clock ready flag - CSIRDY: u1, - /// CSI clock enable in Stop mode - CSIKERON: u1, - reserved12: u2, - /// RC48 clock enable - HSI48ON: u1, - /// RC48 clock ready flag - HSI48RDY: u1, - /// D1 domain clocks ready flag - D1CKRDY: u1, - /// D2 domain clocks ready flag - D2CKRDY: u1, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE clock bypass - HSEBYP: u1, - /// HSE Clock Security System enable - HSECSSON: u1, - reserved24: u4, - /// PLL1 enable - PLLON: u1, - /// PLL1 clock ready flag - PLLRDY: u1, - padding: u6, - }), - /// RCC HSI configuration register - HSICFGR: mmio.Mmio(packed struct(u32) { - /// HSI clock calibration - HSICAL: u12, - reserved24: u12, - /// HSI clock trimming - HSITRIM: u7, - padding: u1, - }), - /// RCC Clock Recovery RC Register - CRRCR: mmio.Mmio(packed struct(u32) { - /// Internal RC 48 MHz clock calibration - HSI48CAL: u10, - padding: u22, + padding: u9, }), - /// RCC CSI configuration register - CSICFGR: mmio.Mmio(packed struct(u32) { - /// CSI clock calibration - CSICAL: u9, - reserved24: u15, - /// CSI clock trimming - CSITRIM: u6, - padding: u2, + /// Date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, }), - /// RCC Clock Configuration Register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u3, - value: SW, - }, - /// System clock switch status - SWS: packed union { + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WUCKSEL: packed union { raw: u3, - value: SW, + value: WUCKSEL, }, - /// System clock selection after a wake up from system Stop - STOPWUCK: packed union { + /// Timestamp event active edge + TSEDGE: packed union { raw: u1, - value: STOPWUCK, + value: TSEDGE, }, - /// Kernel clock selection after a wake up from system Stop - STOPKERWUCK: packed union { + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + /// Bypass the shadow registers + BYPSHAD: u1, + /// Hour format + FMT: packed union { raw: u1, - value: STOPWUCK, + value: FMT, }, - /// HSE division factor for RTC clock - RTCPRE: u6, - /// High Resolution Timer clock prescaler selection - HRTIMSEL: packed union { + reserved8: u1, + /// Alarm enable + ALRE: u1, + reserved10: u1, + /// Wakeup timer enable + WUTE: u1, + /// Timestamp enable + TSE: u1, + /// Alarm interrupt enable + ALRIE: u1, + reserved14: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Timestamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output selection + COSEL: packed union { raw: u1, - value: HRTIMSEL, + value: COSEL, }, - /// Timers clocks prescaler selection - TIMPRE: packed union { + /// Output polarity + POL: packed union { raw: u1, - value: TIMPRE, + value: POL, }, - reserved18: u2, - /// MCO1 prescaler - MCO1PRE: packed union { - raw: u4, - value: MCOPRE, + /// Output selection + OSEL: packed union { + raw: u2, + value: OSEL, }, - /// Micro-controller clock output 1 - MCO1SEL: packed union { - raw: u3, - value: MCO1SEL, + /// Calibration output enable + COE: u1, + padding: u8, + }), + /// Initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm write enabled + ALRWF: u1, + reserved2: u1, + /// Wakeup timer write enabled + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Enter Initialization mode + INIT: u1, + /// Alarm flag + ALRF: u1, + reserved10: u1, + /// Wakeup timer flag + WUTF: u1, + /// Timestamp flag + TSF: u1, + /// Timestamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMPF: u1, + reserved16: u2, + /// Recalibration pending flag + RECALPF: u1, + padding: u15, + }), + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, + }), + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + padding: u16, + }), + reserved28: [4]u8, + /// Alarm register + ALRMR: [1]mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm seconds mask + MSK1: packed union { + raw: u1, + value: ALRMR_MSK, }, - /// MCO2 prescaler - MCO2PRE: packed union { - raw: u4, - value: MCOPRE, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm minutes mask + MSK2: packed union { + raw: u1, + value: ALRMR_MSK, }, - /// Micro-controller clock output 2 - MCO2SEL: packed union { - raw: u3, - value: MCO2SEL, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: ALRMR_PM, }, - }), - reserved24: [4]u8, - /// RCC Domain 1 Clock Configuration Register - D1CFGR: mmio.Mmio(packed struct(u32) { - /// D1 domain AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, + /// Alarm hours mask + MSK3: packed union { + raw: u1, + value: ALRMR_MSK, }, - /// D1 domain APB3 prescaler - D1PPRE: packed union { - raw: u3, - value: PPRE, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { + raw: u1, + value: ALRMR_WDSEL, }, - reserved8: u1, - /// D1 domain Core prescaler - D1CPRE: packed union { - raw: u4, - value: HPRE, + /// Alarm date mask + MSK4: packed union { + raw: u1, + value: ALRMR_MSK, }, - padding: u20, }), - /// RCC Domain 2 Clock Configuration Register - D2CFGR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// D2 domain APB1 prescaler - D2PPRE1: packed union { - raw: u3, - value: PPRE, - }, - reserved8: u1, - /// D2 domain APB2 prescaler - D2PPRE2: packed union { - raw: u3, - value: PPRE, - }, - padding: u21, + reserved36: [4]u8, + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, + padding: u24, }), - /// RCC Domain 3 Clock Configuration Register - D3CFGR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// D3 domain APB4 prescaler - D3PPRE: packed union { - raw: u3, - value: PPRE, - }, - padding: u25, + /// Sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, }), - reserved40: [4]u8, - /// RCC PLLs Clock Source Selection Register - PLLCKSELR: mmio.Mmio(packed struct(u32) { - /// DIVMx and PLLs clock source selection - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - reserved4: u2, - /// Prescaler for PLL1 - DIVM: packed union { - raw: u6, - value: PLLM, - }, - padding: u22, + /// Shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, }), - /// RCC PLLs Configuration Register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// PLL1 fractional latch enable - PLLFRACEN: u1, - /// PLL1 VCO selection - PLLVCOSEL: packed union { + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { raw: u1, - value: PLLVCOSEL, - }, - /// PLL1 input frequency range - PLLRGE: packed union { - raw: u2, - value: PLLRGE, + value: AMPM, }, - reserved16: u12, - /// PLL1 DIVP divider output enable - DIVPEN: u1, - /// PLL1 DIVQ divider output enable - DIVQEN: u1, - /// PLL1 DIVR divider output enable - DIVREN: u1, - padding: u13, + padding: u9, }), - /// RCC PLL1 Dividers Configuration Register - PLLDIVR: mmio.Mmio(packed struct(u32) { - /// Multiplication factor for PLL1 VCO - PLLN: packed union { - raw: u9, - value: PLLN, - }, - /// PLL DIVP division factor - PLLP: packed union { - raw: u7, - value: PLLDIV, - }, - /// PLL DIVQ division factor - PLLQ: packed union { - raw: u7, - value: PLLDIV, - }, - reserved24: u1, - /// PLL DIVR division factor - PLLR: packed union { - raw: u7, - value: PLLDIV, - }, - padding: u1, + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding: u16, }), - /// RCC PLL1 Fractional Divider Register - PLLFRACR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Fractional part of the multiplication factor for PLL VCO - FRACN: u13, + /// Timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, padding: u16, }), - reserved76: [20]u8, - /// RCC Domain 1 Kernel Clock Configuration Register - D1CCIPR: mmio.Mmio(packed struct(u32) { - /// FMC kernel clock source selection - FMCSEL: packed union { - raw: u2, - value: FMCSEL, - }, - reserved4: u2, - /// OCTOSPI kernel clock source selection - OCTOSPISEL: packed union { - raw: u2, - value: FMCSEL, + /// Calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved13: u4, + /// Use a 16-second calibration cycle period + CALW16: packed union { + raw: u1, + value: CALW16, }, - reserved16: u10, - /// SDMMC kernel clock source selection - SDMMCSEL: packed union { + /// Use an 8-second calibration cycle period + CALW8: packed union { raw: u1, - value: SDMMCSEL, + value: CALW8, }, - reserved28: u11, - /// per_ck clock source selection - PERSEL: packed union { - raw: u2, - value: PERSEL, + /// Increase frequency of RTC by 488.5 ppm + CALP: packed union { + raw: u1, + value: CALP, }, - padding: u2, + padding: u16, }), - /// RCC Domain 2 Kernel Clock Configuration Register - D2CCIP1R: mmio.Mmio(packed struct(u32) { - /// SAI1 and DFSDM1 kernel Aclk clock source selection - SAI1SEL: packed union { - raw: u3, - value: SAISEL, - }, - reserved6: u3, - /// SAI2 kernel clock source A source selection - SAI2ASEL: packed union { - raw: u3, - value: SAIASEL, - }, - /// SAI2 kernel clock source B source selection - SAI2BSEL: packed union { - raw: u3, - value: SAIASEL, - }, - /// SPI/I2S1,2 and 3 kernel clock source selection - SPI123SEL: packed union { - raw: u3, - value: SAISEL, + /// Tamper and alternate function configuration register + TAFCR: mmio.Mmio(packed struct(u32) { + /// Tamper detection enable + TAMPE: u1, + /// Active level for tamper + TAMPTRG: packed union { + raw: u1, + value: TAMPTRG, }, - reserved16: u1, - /// SPI4 and 5 kernel clock source selection - SPI45SEL: packed union { + /// Tamper interrupt enable + TAMPIE: u1, + reserved7: u4, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: packed union { raw: u3, - value: SPI45SEL, + value: TAMPFREQ, }, - reserved20: u1, - /// SPDIFRX kernel clock source selection - SPDIFRXSEL: packed union { + /// Tamper filter count + TAMPFLT: packed union { raw: u2, - value: SPDIFRXSEL, - }, - reserved24: u2, - /// DFSDM1 kernel Clk clock source selection - DFSDM1SEL: packed union { - raw: u1, - value: DFSDMSEL, + value: TAMPFLT, }, - reserved28: u3, - /// FDCAN kernel clock source selection - FDCANSEL: packed union { + /// Tamper precharge duration + TAMPPRCH: packed union { raw: u2, - value: FDCANSEL, + value: TAMPPRCH, }, - reserved31: u1, - /// SWPMI kernel clock source selection - SWPMISEL: packed union { + /// Tamper pull-up disable + TAMPPUDIS: packed union { raw: u1, - value: SWPMISEL, + value: TAMPPUDIS, }, - }), - /// RCC Domain 2 Kernel Clock Configuration Register - D2CCIP2R: mmio.Mmio(packed struct(u32) { - /// USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection - USART234578SEL: packed union { - raw: u3, - value: USART234578SEL, + reserved18: u2, + /// PC13 value + PC13VALUE: packed union { + raw: u1, + value: PCVALUE, }, - /// USART1, 6, 9 and 10 kernel clock source selection - USART16910SEL: packed union { - raw: u3, - value: USART16910SEL, + /// PC13 mode + PC13MODE: packed union { + raw: u1, + value: PCMODE, }, - reserved8: u2, - /// RNG kernel clock source selection - RNGSEL: packed union { - raw: u2, - value: RNGSEL, + /// PC14 value + PC14VALUE: packed union { + raw: u1, + value: PCVALUE, }, - reserved12: u2, - /// I2C1,2,3 kernel clock source selection - I2C1235SEL: packed union { - raw: u2, - value: I2C1235SEL, + /// PC14 mode + PC14MODE: packed union { + raw: u1, + value: PCMODE, }, - reserved20: u6, - /// USBOTG 1 and 2 kernel clock source selection - USBSEL: packed union { - raw: u2, - value: USBSEL, + /// PC15 value + PC15VALUE: packed union { + raw: u1, + value: PCVALUE, }, - /// HDMI-CEC kernel clock source selection - CECSEL: packed union { - raw: u2, - value: CECSEL, + /// PC15 mode + PC15MODE: packed union { + raw: u1, + value: PCMODE, }, - reserved28: u4, - /// LPTIM1 kernel clock source selection - LPTIM1SEL: packed union { - raw: u3, - value: LPTIM1SEL, + padding: u8, + }), + /// Alarm sub second register + ALRMSSR: [1]mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, + }), + reserved80: [8]u8, + /// Backup register + BKPR: [5]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + }; + }; + + pub const rtc_v2f2 = struct { + pub const ALRMR_MSK = enum(u1) { + /// Alarm set if the date/day match + ToMatch = 0x0, + /// Date/day don’t care in Alarm comparison + NotMatch = 0x1, + }; + + pub const ALRMR_PM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const ALRMR_WDSEL = enum(u1) { + /// DU[3:0] represents the date units + DateUnits = 0x0, + /// DU[3:0] represents the week day. DT[1:0] is don’t care + WeekDay = 0x1, + }; + + pub const AMPM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Alarm B output enabled + AlarmB = 0x2, + /// Wakeup output enabled + Wakeup = 0x3, + }; + + pub const POL = enum(u1) { + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + Low = 0x1, + }; + + pub const TAMPTRG = enum(u1) { + /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. + RisingEdge = 0x0, + /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event + FallingEdge = 0x1, + }; + + pub const TSEDGE = enum(u1) { + /// RTC_TS input rising edge generates a time-stamp event + RisingEdge = 0x0, + /// RTC_TS input falling edge generates a time-stamp event + FallingEdge = 0x1, + }; + + pub const WUCKSEL = enum(u3) { + /// RTC/16 clock is selected + Div16 = 0x0, + /// RTC/8 clock is selected + Div8 = 0x1, + /// RTC/4 clock is selected + Div4 = 0x2, + /// RTC/2 clock is selected + Div2 = 0x3, + /// ck_spre (usually 1 Hz) clock is selected + ClockSpare = 0x4, + /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + ClockSpareWithOffset = 0x6, + _, + }; + + /// Real-time clock + pub const RTC = extern struct { + /// Time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, }, - padding: u1, + padding: u9, }), - /// RCC Domain 3 Kernel Clock Configuration Register - D3CCIPR: mmio.Mmio(packed struct(u32) { - /// LPUART1 kernel clock source selection - LPUART1SEL: packed union { + /// Date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WUCKSEL: packed union { raw: u3, - value: LPUARTSEL, - }, - reserved8: u5, - /// I2C4 kernel clock source selection - I2C4SEL: packed union { - raw: u2, - value: I2C4SEL, + value: WUCKSEL, }, - /// LPTIM2 kernel clock source selection - LPTIM2SEL: packed union { - raw: u3, - value: LPTIM2SEL, + /// Timestamp event active edge + TSEDGE: packed union { + raw: u1, + value: TSEDGE, }, - /// LPTIM3,4,5 kernel clock source selection - LPTIM345SEL: packed union { - raw: u3, - value: LPTIM2SEL, + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + reserved6: u1, + /// Hour format + FMT: u1, + /// Coarse digital calibration enable + DCE: u1, + /// Alarm enable + ALRE: u1, + reserved10: u1, + /// Wakeup timer enable + WUTE: u1, + /// Timestamp enable + TSE: u1, + /// Alarm interrupt enable + ALRIE: u1, + reserved14: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Timestamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + reserved20: u1, + /// Output polarity + POL: packed union { + raw: u1, + value: POL, }, - /// SAR ADC kernel clock source selection - ADCSEL: packed union { + /// Output selection + OSEL: packed union { raw: u2, - value: ADCSEL, - }, - reserved27: u9, - /// DFSDM2 kernel clock source selection - DFSDM2SEL: u1, - /// SPI6 kernel clock source selection - SPI6SEL: packed union { - raw: u3, - value: SPI6SEL, + value: OSEL, }, - padding: u1, + /// Calibration output enable + COE: u1, + padding: u8, }), - reserved96: [4]u8, - /// RCC Clock Source Interrupt Enable Register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready Interrupt Enable - LSIRDYIE: u1, - /// LSE ready Interrupt Enable - LSERDYIE: u1, - /// HSI ready Interrupt Enable - HSIRDYIE: u1, - /// HSE ready Interrupt Enable - HSERDYIE: u1, - /// CSI ready Interrupt Enable - CSIRDYIE: u1, - /// RC48 ready Interrupt Enable - HSI48RDYIE: u1, - /// PLL1 ready Interrupt Enable - PLLRDYIE: u1, - reserved9: u2, - /// LSE clock security system Interrupt Enable - LSECSSIE: u1, - padding: u22, + /// Initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm write enabled + ALRWF: u1, + reserved2: u1, + /// Wakeup timer write enabled + WUTWF: u1, + reserved4: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Enter Initialization mode + INIT: u1, + /// Alarm flag + ALRF: u1, + reserved10: u1, + /// Wakeup timer flag + WUTF: u1, + /// Timestamp flag + TSF: u1, + /// Timestamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMPF: u1, + padding: u18, }), - /// RCC Clock Source Interrupt Flag Register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready Interrupt Flag - LSIRDYF: u1, - /// LSE ready Interrupt Flag - LSERDYF: u1, - /// HSI ready Interrupt Flag - HSIRDYF: u1, - /// HSE ready Interrupt Flag - HSERDYF: u1, - /// CSI ready Interrupt Flag - CSIRDYF: u1, - /// RC48 ready Interrupt Flag - HSI48RDYF: u1, - /// PLL1 ready Interrupt Flag - PLLRDYF: u1, - reserved9: u2, - /// LSE clock security system Interrupt Flag - LSECSSF: u1, - /// HSE clock security system Interrupt Flag - HSECSSF: u1, - padding: u21, + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, }), - /// RCC Clock Source Interrupt Clear Register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready Interrupt Clear - LSIRDYC: u1, - /// LSE ready Interrupt Clear - LSERDYC: u1, - /// HSI ready Interrupt Clear - HSIRDYC: u1, - /// HSE ready Interrupt Clear - HSERDYC: u1, - /// CSI ready Interrupt Clear - HSE_ready_Interrupt_Clear: u1, - /// RC48 ready Interrupt Clear - HSI48RDYC: u1, - /// PLL1 ready Interrupt Clear - PLLRDYC: u1, - reserved9: u2, - /// LSE clock security system Interrupt Clear - LSECSSC: u1, - /// HSE clock security system Interrupt Clear - HSECSSC: u1, - padding: u21, + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + padding: u16, }), - reserved112: [4]u8, - /// RCC Backup Domain Control Register - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enabled - LSEON: u1, - /// LSE oscillator ready - LSERDY: u1, - /// LSE oscillator bypass - LSEBYP: u1, - /// LSE oscillator driving capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, + /// Calibration register + CALIBR: mmio.Mmio(packed struct(u32) { + /// Digital calibration + DC: u5, + reserved7: u2, + /// Digital calibration sign + DCS: u1, + padding: u24, + }), + /// Alarm register + ALRMR: [2]mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm seconds mask + MSK1: packed union { + raw: u1, + value: ALRMR_MSK, }, - /// LSE clock security system enable - LSECSSON: u1, - /// LSE clock security system failure detection - LSECSSD: u1, - reserved8: u1, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm minutes mask + MSK2: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: ALRMR_PM, + }, + /// Alarm hours mask + MSK3: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { + raw: u1, + value: ALRMR_WDSEL, + }, + /// Alarm date mask + MSK4: packed union { + raw: u1, + value: ALRMR_MSK, }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// VSwitch domain software reset - BDRST: u1, - padding: u15, }), - /// RCC Clock Control and Status Register - CSR: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable - LSION: u1, - /// LSI oscillator ready - LSIRDY: u1, - padding: u30, + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, + padding: u24, }), - reserved124: [4]u8, - /// RCC AHB3 Reset Register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - /// MDMA block reset - MDMARST: u1, - reserved4: u3, - /// DMA2D block reset - DMA2DRST: u1, - /// JPGDEC block reset - JPGDECRST: u1, - reserved12: u6, - /// FMC block reset - FMCRST: u1, - reserved14: u1, - /// OCTOSPI1 and OCTOSPI1 delay block reset - OCTOSPI1RST: u1, + reserved48: [8]u8, + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, reserved16: u1, - /// SDMMC1 and SDMMC1 delay block reset - SDMMC1RST: u1, - reserved19: u2, - /// OCTOSPI2 and OCTOSPI2 delay block reset - OCTOSPI2RST: u1, - reserved21: u1, - /// OCTOSPI IO manager reset - IOMNGRRST: u1, - /// OTFDEC1 reset - OTFD1RST: u1, - /// OTFDEC2 reset - OTFD2RST: u1, - reserved31: u7, - /// CPU reset - CPURST: u1, - }), - /// RCC AHB1 Peripheral Reset Register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 block reset - DMA1RST: u1, - /// DMA2 block reset - DMA2RST: u1, - reserved5: u3, - /// ADC1&2 block reset - ADC12RST: u1, - reserved14: u8, - /// ART block reset - ARTRST: u1, - /// ETH block reset - ETHRST: u1, - reserved25: u9, - /// USB_OTG_HS block reset - USB_OTG_HSRST: u1, - reserved27: u1, - /// USB_OTG_FS block reset - USB_OTG_FSRST: u1, - padding: u4, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, + }, + padding: u9, }), - /// RCC AHB2 Peripheral Reset Register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// DCMI block reset - DCMIRST: u1, - reserved4: u3, - /// CRYPography block reset - CRYPRST: u1, - /// Hash block reset - HASHRST: u1, - /// Random Number Generator block reset - RNGRST: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 Delay block reset - SDMMC2RST: u1, - reserved11: u1, - /// BDMA1 block reset - BDMA1RST: u1, - reserved16: u4, - /// FMAC reset - FMACRST: u1, - /// CORDIC reset - CORDICRST: u1, - padding: u14, + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding: u16, }), - /// RCC AHB4 Peripheral Reset Register - AHB4RSTR: mmio.Mmio(packed struct(u32) { - /// GPIO block reset - GPIOARST: u1, - /// GPIO block reset - GPIOBRST: u1, - /// GPIO block reset - GPIOCRST: u1, - /// GPIO block reset - GPIODRST: u1, - /// GPIO block reset - GPIOERST: u1, - /// GPIO block reset - GPIOFRST: u1, - /// GPIO block reset - GPIOGRST: u1, - /// GPIO block reset - GPIOHRST: u1, - /// GPIO block reset - GPIOIRST: u1, - /// GPIO block reset - GPIOJRST: u1, - /// GPIO block reset - GPIOKRST: u1, - reserved19: u8, - /// CRC block reset - CRCRST: u1, - reserved21: u1, - /// BDMA2 block reset - BDMA2RST: u1, - reserved24: u2, - /// ADC3 block reset - ADC3RST: u1, - /// HSEM block reset - HSEMRST: u1, - padding: u6, + reserved64: [8]u8, + /// Tamper and alternate function configuration register + TAFCR: mmio.Mmio(packed struct(u32) { + /// Tamper detection enable + TAMPE: u1, + /// Active level for tamper + TAMPTRG: packed union { + raw: u1, + value: TAMPTRG, + }, + /// Tamper interrupt enable + TAMPIE: u1, + reserved16: u13, + /// Tamper 1 mapping + TAMP1INSEL: u1, + /// Timestamp mapping + TSINSEL: u1, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding: u13, }), - /// RCC APB3 Peripheral Reset Register - APB3RSTR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// LTDC block reset - LTDCRST: u1, - /// DSI block reset - DSIRST: u1, - padding: u27, + reserved80: [12]u8, + /// Backup register + BKPR: [20]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, }), - /// RCC APB1 Peripheral Reset Register - APB1LRSTR: mmio.Mmio(packed struct(u32) { - /// TIM block reset - TIM2RST: u1, - /// TIM block reset - TIM3RST: u1, - /// TIM block reset - TIM4RST: u1, - /// TIM block reset - TIM5RST: u1, - /// TIM block reset - TIM6RST: u1, - /// TIM block reset - TIM7RST: u1, - /// TIM block reset - TIM12RST: u1, - /// TIM block reset - TIM13RST: u1, - /// TIM block reset - TIM14RST: u1, - /// TIM block reset - LPTIM1RST: u1, - reserved14: u4, - /// SPI2 block reset - SPI2RST: u1, - /// SPI3 block reset - SPI3RST: u1, - /// SPDIFRX block reset - SPDIFRXRST: u1, - /// USART2 block reset - USART2RST: u1, - /// USART3 block reset - USART3RST: u1, - /// UART4 block reset - UART4RST: u1, - /// UART5 block reset - UART5RST: u1, - /// I2C1 block reset - I2C1RST: u1, - /// I2C2 block reset - I2C2RST: u1, - /// I2C3 block reset - I2C3RST: u1, - reserved25: u1, - /// I2C5 block reset - I2C5RST: u1, - reserved27: u1, - /// HDMI-CEC block reset - CECRST: u1, - reserved29: u1, - /// DAC1 (containing two converters) reset - DAC1RST: u1, - /// UART7 block reset - UART7RST: u1, - /// UART8 block reset - UART8RST: u1, + }; + }; + + pub const rtc_v2f3 = struct { + pub const ALRMR_MSK = enum(u1) { + /// Alarm set if the date/day match + ToMatch = 0x0, + /// Date/day don’t care in Alarm comparison + NotMatch = 0x1, + }; + + pub const ALRMR_PM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const ALRMR_WDSEL = enum(u1) { + /// DU[3:0] represents the date units + DateUnits = 0x0, + /// DU[3:0] represents the week day. DT[1:0] is don’t care + WeekDay = 0x1, + }; + + pub const AMPM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const CALP = enum(u1) { + /// No RTCCLK pulses are added + NoChange = 0x0, + /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + IncreaseFreq = 0x1, + }; + + pub const CALW16 = enum(u1) { + /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + Sixteen_Second = 0x1, + _, + }; + + pub const CALW8 = enum(u1) { + /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + Eight_Second = 0x1, + _, + }; + + pub const COSEL = enum(u1) { + /// Calibration output is 512 Hz (with default prescaler setting) + CalFreq_512Hz = 0x0, + /// Calibration output is 1 Hz (with default prescaler setting) + CalFreq_1Hz = 0x1, + }; + + pub const FMT = enum(u1) { + /// 24 hour/day format + Twenty_Four_Hour = 0x0, + /// AM/PM hour format + AM_PM = 0x1, + }; + + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Alarm B output enabled + AlarmB = 0x2, + /// Wakeup output enabled + Wakeup = 0x3, + }; + + pub const PCMODE = enum(u1) { + /// PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode + Floating = 0x0, + /// PCx is forced to push-pull output if LSE is disabled + PushPull = 0x1, + }; + + pub const PCVALUE = enum(u1) { + /// If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low + Low = 0x0, + /// If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high + High = 0x1, + }; + + pub const POL = enum(u1) { + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + Low = 0x1, + }; + + pub const RECALPF = enum(u1) { + /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + Pending = 0x1, + _, + }; + + pub const TAMPFLT = enum(u2) { + /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + Immediate = 0x0, + /// Tamper event is activated after 2 consecutive samples at the active level + Samples2 = 0x1, + /// Tamper event is activated after 4 consecutive samples at the active level + Samples4 = 0x2, + /// Tamper event is activated after 8 consecutive samples at the active level + Samples8 = 0x3, + }; + + pub const TAMPFREQ = enum(u3) { + /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + Div32768 = 0x0, + /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + Div16384 = 0x1, + /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + Div8192 = 0x2, + /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + Div4096 = 0x3, + /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + Div2048 = 0x4, + /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + Div1024 = 0x5, + /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + Div512 = 0x6, + /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + Div256 = 0x7, + }; + + pub const TAMPPRCH = enum(u2) { + /// 1 RTCCLK cycle + Cycles1 = 0x0, + /// 2 RTCCLK cycles + Cycles2 = 0x1, + /// 4 RTCCLK cycles + Cycles4 = 0x2, + /// 8 RTCCLK cycles + Cycles8 = 0x3, + }; + + pub const TAMPPUDIS = enum(u1) { + /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + Enabled = 0x0, + /// Disable precharge of RTC_TAMPx pins + Disabled = 0x1, + }; + + pub const TAMPTRG = enum(u1) { + /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. + RisingEdge = 0x0, + /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event + FallingEdge = 0x1, + }; + + pub const TSEDGE = enum(u1) { + /// RTC_TS input rising edge generates a time-stamp event + RisingEdge = 0x0, + /// RTC_TS input falling edge generates a time-stamp event + FallingEdge = 0x1, + }; + + pub const WUCKSEL = enum(u3) { + /// RTC/16 clock is selected + Div16 = 0x0, + /// RTC/8 clock is selected + Div8 = 0x1, + /// RTC/4 clock is selected + Div4 = 0x2, + /// RTC/2 clock is selected + Div2 = 0x3, + /// ck_spre (usually 1 Hz) clock is selected + ClockSpare = 0x4, + /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + ClockSpareWithOffset = 0x6, + _, + }; + + /// Real-time clock + pub const RTC = extern struct { + /// Time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, + }, + padding: u9, }), - /// RCC APB1 Peripheral Reset Register - APB1HRSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System reset - CRSRST: u1, - /// SWPMI block reset - SWPMIRST: u1, - reserved4: u1, - /// OPAMP block reset - OPAMPRST: u1, - /// MDIOS block reset - MDIOSRST: u1, + /// Date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, reserved8: u2, - /// FDCAN block reset - FDCANRST: u1, - reserved24: u15, - /// TIM23 block reset - TIM23RST: u1, - /// TIM24 block reset - TIM24RST: u1, - padding: u6, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, }), - /// RCC APB2 Peripheral Reset Register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// TIM1 block reset - TIM1RST: u1, - /// TIM8 block reset - TIM8RST: u1, - reserved4: u2, - /// USART1 block reset - USART1RST: u1, - /// USART6 block reset - USART6RST: u1, - /// UART9 block reset - UART9RST: u1, - /// USART10 block reset - USART10RST: u1, - reserved12: u4, - /// SPI1 block reset - SPI1RST: u1, - /// SPI4 block reset - SPI4RST: u1, + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WUCKSEL: packed union { + raw: u3, + value: WUCKSEL, + }, + /// Timestamp event active edge + TSEDGE: packed union { + raw: u1, + value: TSEDGE, + }, + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + /// Bypass the shadow registers + BYPSHAD: u1, + /// Hour format + FMT: packed union { + raw: u1, + value: FMT, + }, + reserved8: u1, + /// Alarm enable + ALRE: u1, + reserved10: u1, + /// Wakeup timer enable + WUTE: u1, + /// Timestamp enable + TSE: u1, + /// Alarm interrupt enable + ALRIE: u1, + reserved14: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Timestamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output selection + COSEL: packed union { + raw: u1, + value: COSEL, + }, + /// Output polarity + POL: packed union { + raw: u1, + value: POL, + }, + /// Output selection + OSEL: packed union { + raw: u2, + value: OSEL, + }, + /// Calibration output enable + COE: u1, + padding: u8, + }), + /// Initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm write enabled + ALRWF: u1, + reserved2: u1, + /// Wakeup timer write enabled + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Enter Initialization mode + INIT: u1, + /// Alarm flag + ALRF: u1, + reserved10: u1, + /// Wakeup timer flag + WUTF: u1, + /// Timestamp flag + TSF: u1, + /// Timestamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMPF: u1, reserved16: u2, - /// TIM15 block reset - TIM15RST: u1, - /// TIM16 block reset - TIM16RST: u1, - /// TIM17 block reset - TIM17RST: u1, - reserved20: u1, - /// SPI5 block reset - SPI5RST: u1, - reserved22: u1, - /// SAI1 block reset - SAI1RST: u1, - /// SAI2 block reset - SAI2RST: u1, - /// SAI3 block reset - SAI3RST: u1, - reserved28: u3, - /// DFSDM1 block reset - DFSDM1RST: u1, - /// HRTIM block reset - HRTIMRST: u1, - padding: u2, + /// Recalibration pending flag + RECALPF: packed union { + raw: u1, + value: RECALPF, + }, + padding: u15, }), - /// RCC APB4 Peripheral Reset Register - APB4RSTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG block reset - SYSCFGRST: u1, - reserved3: u1, - /// LPUART1 block reset - LPUART1RST: u1, - reserved5: u1, - /// SPI6 block reset - SPI6RST: u1, - reserved7: u1, - /// I2C4 block reset - I2C4RST: u1, - reserved9: u1, - /// LPTIM2 block reset - LPTIM2RST: u1, - /// LPTIM3 block reset - LPTIM3RST: u1, - /// LPTIM4 block reset - LPTIM4RST: u1, - /// LPTIM5 block reset - LPTIM5RST: u1, - /// DAC2 (containing one converter) reset - DAC2RST: u1, - /// COMP12 Blocks Reset - COMP12RST: u1, - /// VREF block reset - VREFRST: u1, - reserved21: u5, - /// SAI4 block reset - SAI4RST: u1, - reserved26: u4, - /// Digital temperature sensor block reset - DTSRST: u1, - padding: u5, + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, }), - /// Global Control Register - GCR: mmio.Mmio(packed struct(u32) { - /// WWDG1 reset scope control - WW1RSC: u1, - padding: u31, + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + padding: u16, }), - reserved168: [4]u8, - /// RCC D3 Autonomous mode Register - D3AMR: mmio.Mmio(packed struct(u32) { - /// BDMA2 and DMAMUX Autonomous mode enable - BDMA2AMEN: u1, - reserved3: u2, - /// LPUART1 Autonomous mode enable - LPUART1AMEN: u1, - reserved5: u1, - /// SPI6 Autonomous mode enable - SPI6AMEN: u1, - reserved7: u1, - /// I2C4 Autonomous mode enable - I2C4AMEN: u1, - reserved9: u1, - /// LPTIM2 Autonomous mode enable - LPTIM2AMEN: u1, - /// LPTIM3 Autonomous mode enable - LPTIM3AMEN: u1, - /// LPTIM4 Autonomous mode enable - LPTIM4AMEN: u1, - /// LPTIM5 Autonomous mode enable - LPTIM5AMEN: u1, - /// DAC2 (containing one converter) Autonomous mode enable - DAC2AMEN: u1, - /// COMP12 Autonomous mode enable - COMP12AMEN: u1, - /// VREF Autonomous mode enable - VREFAMEN: u1, - /// RTC Autonomous mode enable - RTCAMEN: u1, - reserved19: u2, - /// CRC Autonomous mode enable - CRCAMEN: u1, - reserved21: u1, - /// SAI4 Autonomous mode enable - SAI4AMEN: u1, - reserved24: u2, - /// ADC3 Autonomous mode enable - ADC3AMEN: u1, - reserved26: u1, - /// Digital temperature sensor Autonomous mode enable - DTSAMEN: u1, - reserved28: u1, - /// Backup RAM Autonomous mode enable - BKPSRAMAMEN: u1, - /// SRAM4 Autonomous mode enable - SRAM4AMEN: u1, - padding: u2, + reserved28: [4]u8, + /// Alarm register + ALRMR: [2]mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm seconds mask + MSK1: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm minutes mask + MSK2: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: ALRMR_PM, + }, + /// Alarm hours mask + MSK3: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { + raw: u1, + value: ALRMR_WDSEL, + }, + /// Alarm date mask + MSK4: packed union { + raw: u1, + value: ALRMR_MSK, + }, }), - reserved304: [132]u8, - /// RCC Reset Status Register - RSR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Remove reset flag - RMVF: u1, - /// CPU reset flag - CPURSTF: u1, - reserved19: u1, - /// D1 domain power switch reset flag - D1RSTF: u1, - /// D2 domain power switch reset flag - D2RSTF: u1, - /// BOR reset flag - BORRSTF: u1, - /// Pin reset flag (NRST) - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// System reset from CPU reset flag - SFTRSTF: u1, - reserved26: u1, - /// Independent Watchdog reset flag - IWDG1RSTF: u1, - reserved28: u1, - /// Window Watchdog reset flag - WWDG1RSTF: u1, - reserved30: u1, - /// Reset due to illegal D1 DStandby or CPU CStop flag - LPWRRSTF: u1, - padding: u1, + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, + padding: u24, }), - /// RCC AHB3 Clock Register - AHB3ENR: mmio.Mmio(packed struct(u32) { - /// MDMA Peripheral Clock Enable - MDMAEN: u1, - reserved4: u3, - /// DMA2D Peripheral Clock Enable - DMA2DEN: u1, - /// JPGDEC Peripheral Clock Enable - JPGDECEN: u1, - reserved12: u6, - /// FMC Peripheral Clocks Enable - FMCEN: u1, - reserved14: u1, - /// OCTOSPI1 and OCTOSPI1 Delay Clock Enable - OCTOSPI1EN: u1, - reserved16: u1, - /// SDMMC1 and SDMMC1 Delay Clock Enable - SDMMC1EN: u1, - reserved19: u2, - /// OCTOSPI2 and OCTOSPI2 delay block enable - OCTOSPI2EN: u1, - reserved21: u1, - /// OCTOSPI IO manager enable - IOMNGREN: u1, - /// OTFDEC1 enable - OTFD1EN: u1, - /// OTFDEC2 enable - OTFD2EN: u1, - reserved28: u4, - /// D1 DTCM1 block enable - DTCM1EN: u1, - /// D1 DTCM2 block enable - DTCM2EN: u1, - /// D1 ITCM block enable - ITCM1EN: u1, - /// AXISRAM block enable - AXISRAMEN: u1, + /// Sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, }), - /// RCC AHB1 Clock Register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// DMA1 Clock Enable - DMA1EN: u1, - /// DMA2 Clock Enable - DMA2EN: u1, - reserved5: u3, - /// ADC1/2 Peripheral Clocks Enable - ADC12EN: u1, - reserved14: u8, - /// ART Clock Enable - ARTEN: u1, - /// Ethernet MAC bus interface Clock Enable - ETHEN: u1, - /// Ethernet Transmission Clock Enable - ETHTXEN: u1, - /// Ethernet Reception Clock Enable - ETHRXEN: u1, - reserved25: u7, - /// USB_OTG_HS Peripheral Clocks Enable - USB_OTG_HSEN: u1, - /// USB_OTG_HS ULPI clock enable - USB_OTG_HS_ULPIEN: u1, - /// USB_OTG_FS Peripheral Clocks Enable - USB_OTG_FSEN: u1, - /// USB_OTG_FS ULPI clock enable - USB_OTG_FS_ULPIEN: u1, - padding: u3, + /// Shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, }), - /// RCC AHB2 Clock Register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// DCMI peripheral clock - DCMIEN: u1, - reserved4: u3, - /// CRYP peripheral clock enable - CRYPEN: u1, - /// HASH peripheral clock enable - HASHEN: u1, - /// RNG peripheral clocks enable - RNGEN: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 delay clock enable - SDMMC2EN: u1, - reserved11: u1, - /// BDMA1 clock enable - BDMA1EN: u1, - reserved16: u4, - /// FMAC enable - FMACEN: u1, - /// CORDIC enable - CORDICEN: u1, - reserved29: u11, - /// SRAM1 block enable - SRAM1EN: u1, - /// SRAM2 block enable - SRAM2EN: u1, - /// SRAM3 block enable - SRAM3EN: u1, + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, + }, + padding: u9, }), - /// RCC AHB4 Clock Register - AHB4ENR: mmio.Mmio(packed struct(u32) { - /// 0GPIO peripheral clock enable - GPIOAEN: u1, - /// 0GPIO peripheral clock enable - GPIOBEN: u1, - /// 0GPIO peripheral clock enable - GPIOCEN: u1, - /// 0GPIO peripheral clock enable - GPIODEN: u1, - /// 0GPIO peripheral clock enable - GPIOEEN: u1, - /// 0GPIO peripheral clock enable - GPIOFEN: u1, - /// 0GPIO peripheral clock enable - GPIOGEN: u1, - /// 0GPIO peripheral clock enable - GPIOHEN: u1, - /// 0GPIO peripheral clock enable - GPIOIEN: u1, - /// 0GPIO peripheral clock enable - GPIOJEN: u1, - /// 0GPIO peripheral clock enable - GPIOKEN: u1, - reserved19: u8, - /// CRC peripheral clock enable - CRCEN: u1, - reserved21: u1, - /// BDMA2 and DMAMUX2 Clock Enable - BDMA2EN: u1, - reserved24: u2, - /// ADC3 Peripheral Clocks Enable - ADC3EN: u1, - /// HSEM peripheral clock enable - HSEMEN: u1, - reserved28: u2, - /// Backup RAM Clock Enable - BKPSRAMEN: u1, - padding: u3, + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding: u16, }), - /// RCC APB3 Clock Register - APB3ENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// LTDC peripheral clock enable - LTDCEN: u1, - /// DSI Peripheral clocks enable - DSIEN: u1, - reserved6: u1, - /// WWDG1 Clock Enable - WWDG1EN: u1, - padding: u25, + /// Timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, }), - /// RCC APB1 Clock Register - APB1LENR: mmio.Mmio(packed struct(u32) { - /// TIM peripheral clock enable - TIM2EN: u1, - /// TIM peripheral clock enable - TIM3EN: u1, - /// TIM peripheral clock enable - TIM4EN: u1, - /// TIM peripheral clock enable - TIM5EN: u1, - /// TIM peripheral clock enable - TIM6EN: u1, - /// TIM peripheral clock enable - TIM7EN: u1, - /// TIM peripheral clock enable - TIM12EN: u1, - /// TIM peripheral clock enable - TIM13EN: u1, - /// TIM peripheral clock enable - TIM14EN: u1, - /// LPTIM1 Peripheral Clocks Enable - LPTIM1EN: u1, - reserved11: u1, - /// WWDG2 peripheral clock enable - WWDG2EN: u1, - reserved14: u2, - /// SPI2 Peripheral Clocks Enable - SPI2EN: u1, - /// SPI3 Peripheral Clocks Enable - SPI3EN: u1, - /// SPDIFRX Peripheral Clocks Enable - SPDIFRXEN: u1, - /// USART2 Peripheral Clocks Enable - USART2EN: u1, - /// USART3 Peripheral Clocks Enable - USART3EN: u1, - /// UART4 Peripheral Clocks Enable - UART4EN: u1, - /// UART5 Peripheral Clocks Enable - UART5EN: u1, - /// I2C1 Peripheral Clocks Enable - I2C1EN: u1, - /// I2C2 Peripheral Clocks Enable - I2C2EN: u1, - /// I2C3 Peripheral Clocks Enable - I2C3EN: u1, - reserved25: u1, - /// I2C5 Peripheral Clocks Enable - I2C5EN: u1, - reserved27: u1, - /// HDMI-CEC peripheral clock enable - CECEN: u1, - reserved29: u1, - /// DAC1 (containing two converters) peripheral clock enable - DAC1EN: u1, - /// UART7 Peripheral Clocks Enable - UART7EN: u1, - /// UART8 Peripheral Clocks Enable - UART8EN: u1, + /// Calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved13: u4, + /// Use a 16-second calibration cycle period + CALW16: packed union { + raw: u1, + value: CALW16, + }, + /// Use an 8-second calibration cycle period + CALW8: packed union { + raw: u1, + value: CALW8, + }, + /// Increase frequency of RTC by 488.5 ppm + CALP: packed union { + raw: u1, + value: CALP, + }, + padding: u16, }), - /// RCC APB1 Clock Register - APB1HENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System peripheral clock enable - CRSEN: u1, - /// SWPMI Peripheral Clocks Enable - SWPMIEN: u1, - reserved4: u1, - /// OPAMP peripheral clock enable - OPAMPEN: u1, - /// MDIOS peripheral clock enable - MDIOSEN: u1, - reserved8: u2, - /// FDCAN Peripheral Clocks Enable - FDCANEN: u1, - reserved24: u15, - /// TIM23 block enable - TIM23EN: u1, - /// TIM24 block enable - TIM24EN: u1, - padding: u6, + /// Tamper and alternate function configuration register + TAFCR: mmio.Mmio(packed struct(u32) { + /// Tamper detection enable + TAMPE: u1, + /// Active level for tamper + TAMPTRG: packed union { + raw: u1, + value: TAMPTRG, + }, + /// Tamper interrupt enable + TAMPIE: u1, + reserved7: u4, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: packed union { + raw: u3, + value: TAMPFREQ, + }, + /// Tamper filter count + TAMPFLT: packed union { + raw: u2, + value: TAMPFLT, + }, + /// Tamper precharge duration + TAMPPRCH: packed union { + raw: u2, + value: TAMPPRCH, + }, + /// Tamper pull-up disable + TAMPPUDIS: packed union { + raw: u1, + value: TAMPPUDIS, + }, + reserved18: u2, + /// PC13 value + PC13VALUE: packed union { + raw: u1, + value: PCVALUE, + }, + /// PC13 mode + PC13MODE: packed union { + raw: u1, + value: PCMODE, + }, + /// PC14 value + PC14VALUE: packed union { + raw: u1, + value: PCVALUE, + }, + /// PC14 mode + PC14MODE: packed union { + raw: u1, + value: PCMODE, + }, + /// PC15 value + PC15VALUE: packed union { + raw: u1, + value: PCVALUE, + }, + /// PC15 mode + PC15MODE: packed union { + raw: u1, + value: PCMODE, + }, + padding: u8, }), - /// RCC APB2 Clock Register - APB2ENR: mmio.Mmio(packed struct(u32) { - /// TIM1 peripheral clock enable - TIM1EN: u1, - /// TIM8 peripheral clock enable - TIM8EN: u1, - reserved4: u2, - /// USART1 Peripheral Clocks Enable - USART1EN: u1, - /// USART6 Peripheral Clocks Enable - USART6EN: u1, - /// UART9 Peripheral Clocks Enable - UART9EN: u1, - /// USART10 Peripheral Clocks Enable - USART10EN: u1, - reserved12: u4, - /// SPI1 Peripheral Clocks Enable - SPI1EN: u1, - /// SPI4 Peripheral Clocks Enable - SPI4EN: u1, - reserved16: u2, - /// TIM15 peripheral clock enable - TIM15EN: u1, - /// TIM16 peripheral clock enable - TIM16EN: u1, - /// TIM17 peripheral clock enable - TIM17EN: u1, - reserved20: u1, - /// SPI5 Peripheral Clocks Enable - SPI5EN: u1, - reserved22: u1, - /// SAI1 Peripheral Clocks Enable - SAI1EN: u1, - /// SAI2 Peripheral Clocks Enable - SAI2EN: u1, - /// SAI3 Peripheral Clocks Enable - SAI3EN: u1, - reserved28: u3, - /// DFSDM1 Peripheral Clocks Enable - DFSDM1EN: u1, - /// HRTIM peripheral clock enable - HRTIMEN: u1, - padding: u2, + /// Alarm sub second register + ALRMSSR: [2]mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, }), - /// RCC APB4 Clock Register - APB4ENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG peripheral clock enable - SYSCFGEN: u1, - reserved3: u1, - /// LPUART1 Peripheral Clocks Enable - LPUART1EN: u1, - reserved5: u1, - /// SPI6 Peripheral Clocks Enable - SPI6EN: u1, - reserved7: u1, - /// I2C4 Peripheral Clocks Enable - I2C4EN: u1, - reserved9: u1, - /// LPTIM2 Peripheral Clocks Enable - LPTIM2EN: u1, - /// LPTIM3 Peripheral Clocks Enable - LPTIM3EN: u1, - /// LPTIM4 Peripheral Clocks Enable - LPTIM4EN: u1, - /// LPTIM5 Peripheral Clocks Enable - LPTIM5EN: u1, - /// DAC2 (containing one converter) peripheral clock enable - DAC2EN: u1, - /// COMP1/2 peripheral clock enable - COMP12EN: u1, - /// VREF peripheral clock enable - VREFEN: u1, - /// RTC APB Clock Enable - RTCAPBEN: u1, - reserved21: u4, - /// SAI4 Peripheral Clocks Enable - SAI4EN: u1, - reserved26: u4, - /// Digital temperature sensor block enable - DTSEN: u1, - padding: u5, + reserved80: [4]u8, + /// Backup register + BKPR: [32]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + }; + }; + + pub const rtc_v2f4 = struct { + pub const ALRMR_MSK = enum(u1) { + /// Alarm set if the date/day match + ToMatch = 0x0, + /// Date/day don’t care in Alarm comparison + NotMatch = 0x1, + }; + + pub const ALRMR_PM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const ALRMR_WDSEL = enum(u1) { + /// DU[3:0] represents the date units + DateUnits = 0x0, + /// DU[3:0] represents the week day. DT[1:0] is don’t care + WeekDay = 0x1, + }; + + pub const AMPM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const CALP = enum(u1) { + /// No RTCCLK pulses are added + NoChange = 0x0, + /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + IncreaseFreq = 0x1, + }; + + pub const CALW16 = enum(u1) { + /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + Sixteen_Second = 0x1, + _, + }; + + pub const CALW8 = enum(u1) { + /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + Eight_Second = 0x1, + _, + }; + + pub const COSEL = enum(u1) { + /// Calibration output is 512 Hz (with default prescaler setting) + CalFreq_512Hz = 0x0, + /// Calibration output is 1 Hz (with default prescaler setting) + CalFreq_1Hz = 0x1, + }; + + pub const FMT = enum(u1) { + /// 24 hour/day format + Twenty_Four_Hour = 0x0, + /// AM/PM hour format + AM_PM = 0x1, + }; + + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Alarm B output enabled + AlarmB = 0x2, + /// Wakeup output enabled + Wakeup = 0x3, + }; + + pub const POL = enum(u1) { + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + Low = 0x1, + }; + + pub const RECALPF = enum(u1) { + /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + Pending = 0x1, + _, + }; + + pub const TAMPFLT = enum(u2) { + /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + Immediate = 0x0, + /// Tamper event is activated after 2 consecutive samples at the active level + Samples2 = 0x1, + /// Tamper event is activated after 4 consecutive samples at the active level + Samples4 = 0x2, + /// Tamper event is activated after 8 consecutive samples at the active level + Samples8 = 0x3, + }; + + pub const TAMPFREQ = enum(u3) { + /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + Div32768 = 0x0, + /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + Div16384 = 0x1, + /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + Div8192 = 0x2, + /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + Div4096 = 0x3, + /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + Div2048 = 0x4, + /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + Div1024 = 0x5, + /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + Div512 = 0x6, + /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + Div256 = 0x7, + }; + + pub const TAMPPRCH = enum(u2) { + /// 1 RTCCLK cycle + Cycles1 = 0x0, + /// 2 RTCCLK cycles + Cycles2 = 0x1, + /// 4 RTCCLK cycles + Cycles4 = 0x2, + /// 8 RTCCLK cycles + Cycles8 = 0x3, + }; + + pub const TAMPPUDIS = enum(u1) { + /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + Enabled = 0x0, + /// Disable precharge of RTC_TAMPx pins + Disabled = 0x1, + }; + + pub const TAMPTRG = enum(u1) { + /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. + RisingEdge = 0x0, + /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event + FallingEdge = 0x1, + }; + + pub const TSEDGE = enum(u1) { + /// RTC_TS input rising edge generates a time-stamp event + RisingEdge = 0x0, + /// RTC_TS input falling edge generates a time-stamp event + FallingEdge = 0x1, + }; + + pub const WUCKSEL = enum(u3) { + /// RTC/16 clock is selected + Div16 = 0x0, + /// RTC/8 clock is selected + Div8 = 0x1, + /// RTC/4 clock is selected + Div4 = 0x2, + /// RTC/2 clock is selected + Div2 = 0x3, + /// ck_spre (usually 1 Hz) clock is selected + ClockSpare = 0x4, + /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + ClockSpareWithOffset = 0x6, + _, + }; + + /// Real-time clock + pub const RTC = extern struct { + /// Time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, + }, + padding: u9, }), - reserved348: [4]u8, - /// RCC AHB3 Sleep Clock Register - AHB3LPENR: mmio.Mmio(packed struct(u32) { - /// MDMA Clock Enable During CSleep Mode - MDMALPEN: u1, - reserved4: u3, - /// DMA2D Clock Enable During CSleep Mode - DMA2DLPEN: u1, - /// JPGDEC Clock Enable During CSleep Mode - JPGDECLPEN: u1, + /// Date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, reserved8: u2, - /// FLASH Clock Enable During CSleep Mode - FLASHLPEN: u1, - reserved12: u3, - /// FMC Peripheral Clocks Enable During CSleep Mode - FMCLPEN: u1, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WUCKSEL: packed union { + raw: u3, + value: WUCKSEL, + }, + /// Timestamp event active edge + TSEDGE: packed union { + raw: u1, + value: TSEDGE, + }, + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + /// Bypass the shadow registers + BYPSHAD: u1, + /// Hour format + FMT: packed union { + raw: u1, + value: FMT, + }, + /// Coarse digital calibration enable + DCE: u1, + /// Alarm enable + ALRE: u1, + reserved10: u1, + /// Wakeup timer enable + WUTE: u1, + /// Timestamp enable + TSE: u1, + /// Alarm interrupt enable + ALRIE: u1, reserved14: u1, - /// OCTOSPI1 and OCTOSPI1 Delay Clock Enable During CSleep Mode - OCTOSPI1LPEN: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Timestamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output selection + COSEL: packed union { + raw: u1, + value: COSEL, + }, + /// Output polarity + POL: packed union { + raw: u1, + value: POL, + }, + /// Output selection + OSEL: packed union { + raw: u2, + value: OSEL, + }, + /// Calibration output enable + COE: u1, + padding: u8, + }), + /// Initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm write allowed + ALRWF: u1, + reserved2: u1, + /// Wakeup timer write allowed + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Enter Initialization mode + INIT: u1, + /// Alarm flag + ALRF: u1, + reserved10: u1, + /// Wakeup timer flag + WUTF: u1, + /// Timestamp flag + TSF: u1, + /// Timestamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMPF: u1, + reserved16: u2, + /// Recalibration pending flag + RECALPF: packed union { + raw: u1, + value: RECALPF, + }, + padding: u15, + }), + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, reserved16: u1, - /// SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - SDMMC1LPEN: u1, - reserved19: u2, - /// OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode - OCTOSPI2LPEN: u1, - reserved21: u1, - /// OCTOSPI IO manager enable during CSleep Mode - IOMNGRLPEN: u1, - /// OTFDEC1 enable during CSleep Mode - OTFD1LPEN: u1, - /// OTFDEC2 enable during CSleep Mode - OTFD2LPEN: u1, - reserved28: u4, - /// D1DTCM1 Block Clock Enable During CSleep mode - D1DTCM1LPEN: u1, - /// D1 DTCM2 Block Clock Enable During CSleep mode - DTCM2LPEN: u1, - /// D1ITCM Block Clock Enable During CSleep mode - ITCMLPEN: u1, - /// AXISRAM Block Clock Enable During CSleep mode - AXISRAMLPEN: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, }), - /// RCC AHB1 Sleep Clock Register - AHB1LPENR: mmio.Mmio(packed struct(u32) { - /// DMA1 Clock Enable During CSleep Mode - DMA1LPEN: u1, - /// DMA2 Clock Enable During CSleep Mode - DMA2LPEN: u1, - reserved5: u3, - /// ADC1/2 Peripheral Clocks Enable During CSleep Mode - ADC12LPEN: u1, - reserved14: u8, - /// ART Clock Enable During CSleep Mode - ARTLPEN: u1, - /// Ethernet MAC bus interface Clock Enable During CSleep Mode - ETHLPEN: u1, - /// Ethernet Transmission Clock Enable During CSleep Mode - ETHTXLPEN: u1, - /// Ethernet Reception Clock Enable During CSleep Mode - ETHRXLPEN: u1, - reserved25: u7, - /// USB_OTG_HS peripheral clock enable during CSleep mode - USB_OTG_HSLPEN: u1, - /// USB_PHY1 clock enable during CSleep mode - USB_OTG_HS_ULPILPEN: u1, - /// USB_OTG_FS peripheral clock enable during CSleep mode - USB_OTG_FSLPEN: u1, - /// USB_PHY2 clocks enable during CSleep mode - USB_OTG_FS_ULPILPEN: u1, - padding: u3, + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + padding: u16, }), - /// RCC AHB2 Sleep Clock Register - AHB2LPENR: mmio.Mmio(packed struct(u32) { - /// DCMI peripheral clock enable during csleep mode - DCMILPEN: u1, - reserved4: u3, - /// CRYP peripheral clock enable during CSleep mode - CRYPLPEN: u1, - /// HASH peripheral clock enable during CSleep mode - HASHLPEN: u1, - /// RNG peripheral clock enable during CSleep mode - RNGLPEN: u1, - reserved9: u2, - /// SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - SDMMC2LPEN: u1, - reserved11: u1, - /// BDMA1 Clock Enable During CSleep Mode - BDMA1LPEN: u1, - reserved16: u4, - /// FMAC enable during CSleep Mode - FMACLPEN: u1, - /// CORDIC enable during CSleep Mode - CORDICLPEN: u1, - reserved29: u11, - /// SRAM1 Clock Enable During CSleep Mode - SRAM1LPEN: u1, - /// SRAM2 Clock Enable During CSleep Mode - SRAM2LPEN: u1, - /// SRAM3 Clock Enable During CSleep Mode - SRAM3LPEN: u1, + /// Calibration register + CALIBR: mmio.Mmio(packed struct(u32) { + /// Digital calibration + DC: u5, + reserved7: u2, + /// Digital calibration sign + DCS: u1, + padding: u24, }), - /// RCC AHB4 Sleep Clock Register - AHB4LPENR: mmio.Mmio(packed struct(u32) { - /// GPIO peripheral clock enable during CSleep mode - GPIOALPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOBLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOCLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIODLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOELPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOFLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOGLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOHLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOILPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOJLPEN: u1, - /// GPIO peripheral clock enable during CSleep mode - GPIOKLPEN: u1, - reserved19: u8, - /// CRC peripheral clock enable during CSleep mode - CRCLPEN: u1, - reserved21: u1, - /// BDMA2 Clock Enable During CSleep Mode - BDMA2LPEN: u1, - reserved24: u2, - /// ADC3 Peripheral Clocks Enable During CSleep Mode - ADC3LPEN: u1, - reserved28: u3, - /// Backup RAM Clock Enable During CSleep Mode - BKPSRAMLPEN: u1, - /// SRAM4 Clock Enable During CSleep Mode - SRAM4LPEN: u1, - padding: u2, + /// Alarm register + ALRMR: [2]mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm seconds mask + MSK1: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm minutes mask + MSK2: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: ALRMR_PM, + }, + /// Alarm hours mask + MSK3: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { + raw: u1, + value: ALRMR_WDSEL, + }, + /// Alarm date mask + MSK4: packed union { + raw: u1, + value: ALRMR_MSK, + }, }), - /// RCC APB3 Sleep Clock Register - APB3LPENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// LTDC peripheral clock enable during CSleep mode - LTDCLPEN: u1, - /// DSI Peripheral Clock Enable During CSleep Mode - DSILPEN: u1, - reserved6: u1, - /// WWDG1 Clock Enable During CSleep Mode - WWDG1LPEN: u1, - padding: u25, + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, + padding: u24, }), - /// RCC APB1 Low Sleep Clock Register - APB1LLPENR: mmio.Mmio(packed struct(u32) { - /// TIM2 peripheral clock enable during CSleep mode - TIM2LPEN: u1, - /// TIM3 peripheral clock enable during CSleep mode - TIM3LPEN: u1, - /// TIM4 peripheral clock enable during CSleep mode - TIM4LPEN: u1, - /// TIM5 peripheral clock enable during CSleep mode - TIM5LPEN: u1, - /// TIM6 peripheral clock enable during CSleep mode - TIM6LPEN: u1, - /// TIM7 peripheral clock enable during CSleep mode - TIM7LPEN: u1, - /// TIM12 peripheral clock enable during CSleep mode - TIM12LPEN: u1, - /// TIM13 peripheral clock enable during CSleep mode - TIM13LPEN: u1, - /// TIM14 peripheral clock enable during CSleep mode - TIM14LPEN: u1, - /// LPTIM1 Peripheral Clocks Enable During CSleep Mode - LPTIM1LPEN: u1, - reserved11: u1, - /// WWDG2 peripheral Clocks Enable During CSleep Mode - WWDG2LPEN: u1, - reserved14: u2, - /// SPI2 Peripheral Clocks Enable During CSleep Mode - SPI2LPEN: u1, - /// SPI3 Peripheral Clocks Enable During CSleep Mode - SPI3LPEN: u1, - /// SPDIFRX Peripheral Clocks Enable During CSleep Mode - SPDIFRXLPEN: u1, - /// USART2 Peripheral Clocks Enable During CSleep Mode - USART2LPEN: u1, - /// USART3 Peripheral Clocks Enable During CSleep Mode - USART3LPEN: u1, - /// UART4 Peripheral Clocks Enable During CSleep Mode - UART4LPEN: u1, - /// UART5 Peripheral Clocks Enable During CSleep Mode - UART5LPEN: u1, - /// I2C1 Peripheral Clocks Enable During CSleep Mode - I2C1LPEN: u1, - /// I2C2 Peripheral Clocks Enable During CSleep Mode - I2C2LPEN: u1, - /// I2C3 Peripheral Clocks Enable During CSleep Mode - I2C3LPEN: u1, - reserved25: u1, - /// I2C5 block enable during CSleep Mode - I2C5LPEN: u1, - reserved27: u1, - /// HDMI-CEC Peripheral Clocks Enable During CSleep Mode - CECLPEN: u1, - reserved29: u1, - /// DAC1 (containing two converters) peripheral clock enable during CSleep mode - DAC1LPEN: u1, - /// UART7 Peripheral Clocks Enable During CSleep Mode - UART7LPEN: u1, - /// UART8 Peripheral Clocks Enable During CSleep Mode - UART8LPEN: u1, + /// Sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, }), - /// RCC APB1 High Sleep Clock Register - APB1HLPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clock Recovery System peripheral clock enable during CSleep mode - CRSLPEN: u1, - /// SWPMI Peripheral Clocks Enable During CSleep Mode - SWPMILPEN: u1, - reserved4: u1, - /// OPAMP peripheral clock enable during CSleep mode - OPAMPLPEN: u1, - /// MDIOS peripheral clock enable during CSleep mode - MDIOSLPEN: u1, + /// Shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, + }), + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, + }, + padding: u9, + }), + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, reserved8: u2, - /// FDCAN Peripheral Clocks Enable During CSleep Mode - FDCANLPEN: u1, - reserved24: u15, - /// TIM23 block enable during CSleep Mode - TIM23LPEN: u1, - /// TIM24 block enable during CSleep Mode - TIM24LPEN: u1, - padding: u6, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding: u16, }), - /// RCC APB2 Sleep Clock Register - APB2LPENR: mmio.Mmio(packed struct(u32) { - /// TIM1 peripheral clock enable during CSleep mode - TIM1LPEN: u1, - /// TIM8 peripheral clock enable during CSleep mode - TIM8LPEN: u1, - reserved4: u2, - /// USART1 Peripheral Clocks Enable During CSleep Mode - USART1LPEN: u1, - /// USART6 Peripheral Clocks Enable During CSleep Mode - USART6LPEN: u1, - reserved12: u6, - /// SPI1 Peripheral Clocks Enable During CSleep Mode - SPI1LPEN: u1, - /// SPI4 Peripheral Clocks Enable During CSleep Mode - SPI4LPEN: u1, - reserved16: u2, - /// TIM15 peripheral clock enable during CSleep mode - TIM15LPEN: u1, - /// TIM16 peripheral clock enable during CSleep mode - TIM16LPEN: u1, - /// TIM17 peripheral clock enable during CSleep mode - TIM17LPEN: u1, - reserved20: u1, - /// SPI5 Peripheral Clocks Enable During CSleep Mode - SPI5LPEN: u1, - reserved22: u1, - /// SAI1 Peripheral Clocks Enable During CSleep Mode - SAI1LPEN: u1, - /// SAI2 Peripheral Clocks Enable During CSleep Mode - SAI2LPEN: u1, - /// SAI3 Peripheral Clocks Enable During CSleep Mode - SAI3LPEN: u1, - reserved28: u3, - /// DFSDM1 Peripheral Clocks Enable During CSleep Mode - DFSDM1LPEN: u1, - /// HRTIM peripheral clock enable during CSleep mode - HRTIMLPEN: u1, - padding: u2, + /// Timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, }), - /// RCC APB4 Sleep Clock Register - APB4LPENR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// SYSCFG peripheral clock enable during CSleep mode - SYSCFGLPEN: u1, - reserved3: u1, - /// LPUART1 Peripheral Clocks Enable During CSleep Mode - LPUART1LPEN: u1, - reserved5: u1, - /// SPI6 Peripheral Clocks Enable During CSleep Mode - SPI6LPEN: u1, - reserved7: u1, - /// I2C4 Peripheral Clocks Enable During CSleep Mode - I2C4LPEN: u1, - reserved9: u1, - /// LPTIM2 Peripheral Clocks Enable During CSleep Mode - LPTIM2LPEN: u1, - /// LPTIM3 Peripheral Clocks Enable During CSleep Mode - LPTIM3LPEN: u1, - /// LPTIM4 Peripheral Clocks Enable During CSleep Mode - LPTIM4LPEN: u1, - /// LPTIM5 Peripheral Clocks Enable During CSleep Mode - LPTIM5LPEN: u1, - /// DAC2 (containing one converter) peripheral clock enable during CSleep mode - DAC2LPEN: u1, - /// COMP1/2 peripheral clock enable during CSleep mode - COMP12LPEN: u1, - /// VREF peripheral clock enable during CSleep mode - VREFLPEN: u1, - /// RTC APB Clock Enable During CSleep Mode - RTCAPBLPEN: u1, - reserved21: u4, - /// SAI4 Peripheral Clocks Enable During CSleep Mode - SAI4LPEN: u1, - reserved26: u4, - /// Digital temperature sensor block enable during CSleep Mode - DTSLPEN: u1, - padding: u5, + /// Calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved13: u4, + /// Use a 16-second calibration cycle period + CALW16: packed union { + raw: u1, + value: CALW16, + }, + /// Use an 8-second calibration cycle period + CALW8: packed union { + raw: u1, + value: CALW8, + }, + /// Increase frequency of RTC by 488.5 ppm + CALP: packed union { + raw: u1, + value: CALP, + }, + padding: u16, + }), + /// Tamper and alternate function configuration register + TAFCR: mmio.Mmio(packed struct(u32) { + /// Tamper detection enable + TAMPE: u1, + /// Active level for tamper + TAMPTRG: packed union { + raw: u1, + value: TAMPTRG, + }, + /// Tamper interrupt enable + TAMPIE: u1, + reserved7: u4, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: packed union { + raw: u3, + value: TAMPFREQ, + }, + /// Tamper filter count + TAMPFLT: packed union { + raw: u2, + value: TAMPFLT, + }, + /// Tamper precharge duration + TAMPPRCH: packed union { + raw: u2, + value: TAMPPRCH, + }, + /// Tamper pull-up disable + TAMPPUDIS: packed union { + raw: u1, + value: TAMPPUDIS, + }, + /// Tamper 1 mapping + TAMP1INSEL: u1, + /// Timestamp mapping + TSINSEL: u1, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding: u13, + }), + /// Alarm sub second register + ALRMSSR: [2]mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, + }), + reserved80: [4]u8, + /// Backup register + BKPR: [20]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, }), }; }; - pub const rcc_f2 = struct { - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, - _, + pub const rtc_v2f7 = struct { + pub const ALRMR_MSK = enum(u1) { + /// Alarm set if the date/day match + ToMatch = 0x0, + /// Date/day don’t care in Alarm comparison + NotMatch = 0x1, }; - pub const ISSRC = enum(u1) { - /// PLLI2S clock used as I2S clock source - PLLI2S = 0x0, - /// External clock mapped on the I2S_CKIN pin used as I2S clock source - CKIN = 0x1, + pub const ALRMR_PM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, }; - pub const MCO1SEL = enum(u2) { - /// HSI clock selected - HSI = 0x0, - /// LSE oscillator selected - LSE = 0x1, - /// HSE oscillator clock selected - HSE = 0x2, - /// PLL clock selected - PLL = 0x3, + pub const ALRMR_WDSEL = enum(u1) { + /// DU[3:0] represents the date units + DateUnits = 0x0, + /// DU[3:0] represents the week day. DT[1:0] is don’t care + WeekDay = 0x1, }; - pub const MCO2SEL = enum(u2) { - /// System clock (SYSCLK) selected - SYS = 0x0, - /// PLLI2S clock selected - PLLI2S = 0x1, - /// HSE oscillator clock selected - HSE = 0x2, - /// PLL clock selected - PLL = 0x3, + pub const AMPM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, }; - pub const MCOPRE = enum(u3) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x4, - /// Division by 3 - Div3 = 0x5, - /// Division by 4 - Div4 = 0x6, - /// Division by 5 - Div5 = 0x7, - _, + pub const CALP = enum(u1) { + /// No RTCCLK pulses are added + NoChange = 0x0, + /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + IncreaseFreq = 0x1, }; - pub const PLLM = enum(u6) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - Div16 = 0x10, - Div17 = 0x11, - Div18 = 0x12, - Div19 = 0x13, - Div20 = 0x14, - Div21 = 0x15, - Div22 = 0x16, - Div23 = 0x17, - Div24 = 0x18, - Div25 = 0x19, - Div26 = 0x1a, - Div27 = 0x1b, - Div28 = 0x1c, - Div29 = 0x1d, - Div30 = 0x1e, - Div31 = 0x1f, - Div32 = 0x20, - Div33 = 0x21, - Div34 = 0x22, - Div35 = 0x23, - Div36 = 0x24, - Div37 = 0x25, - Div38 = 0x26, - Div39 = 0x27, - Div40 = 0x28, - Div41 = 0x29, - Div42 = 0x2a, - Div43 = 0x2b, - Div44 = 0x2c, - Div45 = 0x2d, - Div46 = 0x2e, - Div47 = 0x2f, - Div48 = 0x30, - Div49 = 0x31, - Div50 = 0x32, - Div51 = 0x33, - Div52 = 0x34, - Div53 = 0x35, - Div54 = 0x36, - Div55 = 0x37, - Div56 = 0x38, - Div57 = 0x39, - Div58 = 0x3a, - Div59 = 0x3b, - Div60 = 0x3c, - Div61 = 0x3d, - Div62 = 0x3e, - Div63 = 0x3f, + pub const CALW16 = enum(u1) { + /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + Sixteen_Second = 0x1, _, }; - pub const PLLN = enum(u9) { - Mul192 = 0xc0, - Mul193 = 0xc1, - Mul194 = 0xc2, - Mul195 = 0xc3, - Mul196 = 0xc4, - Mul197 = 0xc5, - Mul198 = 0xc6, - Mul199 = 0xc7, - Mul200 = 0xc8, - Mul201 = 0xc9, - Mul202 = 0xca, - Mul203 = 0xcb, - Mul204 = 0xcc, - Mul205 = 0xcd, - Mul206 = 0xce, - Mul207 = 0xcf, - Mul208 = 0xd0, - Mul209 = 0xd1, - Mul210 = 0xd2, - Mul211 = 0xd3, - Mul212 = 0xd4, - Mul213 = 0xd5, - Mul214 = 0xd6, - Mul215 = 0xd7, - Mul216 = 0xd8, - Mul217 = 0xd9, - Mul218 = 0xda, - Mul219 = 0xdb, - Mul220 = 0xdc, - Mul221 = 0xdd, - Mul222 = 0xde, - Mul223 = 0xdf, - Mul224 = 0xe0, - Mul225 = 0xe1, - Mul226 = 0xe2, - Mul227 = 0xe3, - Mul228 = 0xe4, - Mul229 = 0xe5, - Mul230 = 0xe6, - Mul231 = 0xe7, - Mul232 = 0xe8, - Mul233 = 0xe9, - Mul234 = 0xea, - Mul235 = 0xeb, - Mul236 = 0xec, - Mul237 = 0xed, - Mul238 = 0xee, - Mul239 = 0xef, - Mul240 = 0xf0, - Mul241 = 0xf1, - Mul242 = 0xf2, - Mul243 = 0xf3, - Mul244 = 0xf4, - Mul245 = 0xf5, - Mul246 = 0xf6, - Mul247 = 0xf7, - Mul248 = 0xf8, - Mul249 = 0xf9, - Mul250 = 0xfa, - Mul251 = 0xfb, - Mul252 = 0xfc, - Mul253 = 0xfd, - Mul254 = 0xfe, - Mul255 = 0xff, - Mul256 = 0x100, - Mul257 = 0x101, - Mul258 = 0x102, - Mul259 = 0x103, - Mul260 = 0x104, - Mul261 = 0x105, - Mul262 = 0x106, - Mul263 = 0x107, - Mul264 = 0x108, - Mul265 = 0x109, - Mul266 = 0x10a, - Mul267 = 0x10b, - Mul268 = 0x10c, - Mul269 = 0x10d, - Mul270 = 0x10e, - Mul271 = 0x10f, - Mul272 = 0x110, - Mul273 = 0x111, - Mul274 = 0x112, - Mul275 = 0x113, - Mul276 = 0x114, - Mul277 = 0x115, - Mul278 = 0x116, - Mul279 = 0x117, - Mul280 = 0x118, - Mul281 = 0x119, - Mul282 = 0x11a, - Mul283 = 0x11b, - Mul284 = 0x11c, - Mul285 = 0x11d, - Mul286 = 0x11e, - Mul287 = 0x11f, - Mul288 = 0x120, - Mul289 = 0x121, - Mul290 = 0x122, - Mul291 = 0x123, - Mul292 = 0x124, - Mul293 = 0x125, - Mul294 = 0x126, - Mul295 = 0x127, - Mul296 = 0x128, - Mul297 = 0x129, - Mul298 = 0x12a, - Mul299 = 0x12b, - Mul300 = 0x12c, - Mul301 = 0x12d, - Mul302 = 0x12e, - Mul303 = 0x12f, - Mul304 = 0x130, - Mul305 = 0x131, - Mul306 = 0x132, - Mul307 = 0x133, - Mul308 = 0x134, - Mul309 = 0x135, - Mul310 = 0x136, - Mul311 = 0x137, - Mul312 = 0x138, - Mul313 = 0x139, - Mul314 = 0x13a, - Mul315 = 0x13b, - Mul316 = 0x13c, - Mul317 = 0x13d, - Mul318 = 0x13e, - Mul319 = 0x13f, - Mul320 = 0x140, - Mul321 = 0x141, - Mul322 = 0x142, - Mul323 = 0x143, - Mul324 = 0x144, - Mul325 = 0x145, - Mul326 = 0x146, - Mul327 = 0x147, - Mul328 = 0x148, - Mul329 = 0x149, - Mul330 = 0x14a, - Mul331 = 0x14b, - Mul332 = 0x14c, - Mul333 = 0x14d, - Mul334 = 0x14e, - Mul335 = 0x14f, - Mul336 = 0x150, - Mul337 = 0x151, - Mul338 = 0x152, - Mul339 = 0x153, - Mul340 = 0x154, - Mul341 = 0x155, - Mul342 = 0x156, - Mul343 = 0x157, - Mul344 = 0x158, - Mul345 = 0x159, - Mul346 = 0x15a, - Mul347 = 0x15b, - Mul348 = 0x15c, - Mul349 = 0x15d, - Mul350 = 0x15e, - Mul351 = 0x15f, - Mul352 = 0x160, - Mul353 = 0x161, - Mul354 = 0x162, - Mul355 = 0x163, - Mul356 = 0x164, - Mul357 = 0x165, - Mul358 = 0x166, - Mul359 = 0x167, - Mul360 = 0x168, - Mul361 = 0x169, - Mul362 = 0x16a, - Mul363 = 0x16b, - Mul364 = 0x16c, - Mul365 = 0x16d, - Mul366 = 0x16e, - Mul367 = 0x16f, - Mul368 = 0x170, - Mul369 = 0x171, - Mul370 = 0x172, - Mul371 = 0x173, - Mul372 = 0x174, - Mul373 = 0x175, - Mul374 = 0x176, - Mul375 = 0x177, - Mul376 = 0x178, - Mul377 = 0x179, - Mul378 = 0x17a, - Mul379 = 0x17b, - Mul380 = 0x17c, - Mul381 = 0x17d, - Mul382 = 0x17e, - Mul383 = 0x17f, - Mul384 = 0x180, - Mul385 = 0x181, - Mul386 = 0x182, - Mul387 = 0x183, - Mul388 = 0x184, - Mul389 = 0x185, - Mul390 = 0x186, - Mul391 = 0x187, - Mul392 = 0x188, - Mul393 = 0x189, - Mul394 = 0x18a, - Mul395 = 0x18b, - Mul396 = 0x18c, - Mul397 = 0x18d, - Mul398 = 0x18e, - Mul399 = 0x18f, - Mul400 = 0x190, - Mul401 = 0x191, - Mul402 = 0x192, - Mul403 = 0x193, - Mul404 = 0x194, - Mul405 = 0x195, - Mul406 = 0x196, - Mul407 = 0x197, - Mul408 = 0x198, - Mul409 = 0x199, - Mul410 = 0x19a, - Mul411 = 0x19b, - Mul412 = 0x19c, - Mul413 = 0x19d, - Mul414 = 0x19e, - Mul415 = 0x19f, - Mul416 = 0x1a0, - Mul417 = 0x1a1, - Mul418 = 0x1a2, - Mul419 = 0x1a3, - Mul420 = 0x1a4, - Mul421 = 0x1a5, - Mul422 = 0x1a6, - Mul423 = 0x1a7, - Mul424 = 0x1a8, - Mul425 = 0x1a9, - Mul426 = 0x1aa, - Mul427 = 0x1ab, - Mul428 = 0x1ac, - Mul429 = 0x1ad, - Mul430 = 0x1ae, - Mul431 = 0x1af, - Mul432 = 0x1b0, + pub const CALW8 = enum(u1) { + /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + Eight_Second = 0x1, _, }; - pub const PLLP = enum(u2) { - /// PLLP=2 - Div2 = 0x0, - /// PLLP=4 - Div4 = 0x1, - /// PLLP=6 - Div6 = 0x2, - /// PLLP=8 - Div8 = 0x3, + pub const COSEL = enum(u1) { + /// Calibration output is 512 Hz (with default prescaler setting) + CalFreq_512Hz = 0x0, + /// Calibration output is 1 Hz (with default prescaler setting) + CalFreq_1Hz = 0x1, }; - pub const PLLQ = enum(u4) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - _, + pub const FMT = enum(u1) { + /// 24 hour/day format + Twenty_Four_Hour = 0x0, + /// AM/PM hour format + AM_PM = 0x1, }; - pub const PLLR = enum(u3) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - _, + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Alarm B output enabled + AlarmB = 0x2, + /// Wakeup output enabled + Wakeup = 0x3, }; - pub const PLLSRC = enum(u1) { - /// HSI clock selected as PLL and PLLI2S clock entry - HSI = 0x0, - /// HSE oscillator clock selected as PLL and PLLI2S clock entry - HSE = 0x1, + pub const POL = enum(u1) { + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + Low = 0x1, }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, + pub const RECALPF = enum(u1) { + /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + Pending = 0x1, _, }; - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, + pub const TAMPFLT = enum(u2) { + /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + Immediate = 0x0, + /// Tamper event is activated after 2 consecutive samples at the active level + Samples2 = 0x1, + /// Tamper event is activated after 4 consecutive samples at the active level + Samples4 = 0x2, + /// Tamper event is activated after 8 consecutive samples at the active level + Samples8 = 0x3, }; - pub const SPREADSEL = enum(u1) { - /// Center spread - Center = 0x0, - /// Down spread - Down = 0x1, + pub const TAMPFREQ = enum(u3) { + /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + Div32768 = 0x0, + /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + Div16384 = 0x1, + /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + Div8192 = 0x2, + /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + Div4096 = 0x3, + /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + Div2048 = 0x4, + /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + Div1024 = 0x5, + /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + Div512 = 0x6, + /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + Div256 = 0x7, }; - pub const SW = enum(u2) { - /// HSI selected as system clock - HSI = 0x0, - /// HSE selected as system clock - HSE = 0x1, - /// PLL selected as system clock - PLL1_P = 0x2, + pub const TAMPPRCH = enum(u2) { + /// 1 RTCCLK cycle + Cycles1 = 0x0, + /// 2 RTCCLK cycles + Cycles2 = 0x1, + /// 4 RTCCLK cycles + Cycles4 = 0x2, + /// 8 RTCCLK cycles + Cycles8 = 0x3, + }; + + pub const TAMPPUDIS = enum(u1) { + /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + Enabled = 0x0, + /// Disable precharge of RTC_TAMPx pins + Disabled = 0x1, + }; + + pub const TAMPTRG = enum(u1) { + /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. + RisingEdge = 0x0, + /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event + FallingEdge = 0x1, + }; + + pub const TSEDGE = enum(u1) { + /// RTC_TS input rising edge generates a time-stamp event + RisingEdge = 0x0, + /// RTC_TS input falling edge generates a time-stamp event + FallingEdge = 0x1, + }; + + pub const WUCKSEL = enum(u3) { + /// RTC/16 clock is selected + Div16 = 0x0, + /// RTC/8 clock is selected + Div8 = 0x1, + /// RTC/4 clock is selected + Div4 = 0x2, + /// RTC/2 clock is selected + Div2 = 0x3, + /// ck_spre (usually 1 Hz) clock is selected + ClockSpare = 0x4, + /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + ClockSpareWithOffset = 0x6, _, }; - /// Reset and clock control - pub const RCC = extern struct { - /// clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal high-speed clock enable - HSION: u1, - /// Internal high-speed clock ready flag - HSIRDY: u1, - reserved3: u1, - /// Internal high-speed clock trimming - HSITRIM: u5, - /// Internal high-speed clock calibration - HSICAL: u8, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE clock bypass - HSEBYP: u1, - /// Clock security system enable - CSSON: u1, - reserved24: u4, - /// Main PLL (PLL) enable - PLLON: u1, - /// Main PLL (PLL) clock ready flag - PLLRDY: u1, - /// PLLI2S enable - PLLI2SON: u1, - /// PLLI2S clock ready flag - PLLI2SRDY: u1, - padding: u4, - }), - /// PLL configuration register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - PLLM: packed union { - raw: u6, - value: PLLM, - }, - /// Main PLL (PLL) multiplication factor for VCO - PLLN: packed union { - raw: u9, - value: PLLN, - }, + /// Real-time clock + pub const RTC = extern struct { + /// Time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, reserved16: u1, - /// Main PLL (PLL) division factor for main system clock - PLLP: packed union { - raw: u2, - value: PLLP, - }, - reserved22: u4, - /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - PLLSRC: packed union { + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { raw: u1, - value: PLLSRC, - }, - reserved24: u1, - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - PLLQ: packed union { - raw: u4, - value: PLLQ, + value: AMPM, }, - padding: u4, + padding: u9, }), - /// clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u2, - value: SW, - }, - /// System clock switch status - SWS: packed union { - raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, - }, - reserved10: u2, - /// APB Low speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, - }, - /// APB high-speed prescaler (APB2) - PPRE2: packed union { + /// Date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WUCKSEL: packed union { raw: u3, - value: PPRE, + value: WUCKSEL, }, - /// HSE division factor for RTC clock - RTCPRE: u5, - /// Microcontroller clock output 1 - MCO1SEL: packed union { - raw: u2, - value: MCO1SEL, + /// Timestamp event active edge + TSEDGE: packed union { + raw: u1, + value: TSEDGE, }, - /// I2S clock selection - I2SSRC: packed union { + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + /// Bypass the shadow registers + BYPSHAD: u1, + /// Hour format + FMT: packed union { raw: u1, - value: ISSRC, + value: FMT, }, - /// MCO1 prescaler - MCO1PRE: packed union { - raw: u3, - value: MCOPRE, + reserved8: u1, + /// Alarm enable + ALRE: u1, + reserved10: u1, + /// Wakeup timer enable + WUTE: u1, + /// Timestamp enable + TSE: u1, + /// Alarm interrupt enable + ALRIE: u1, + reserved14: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Timestamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output selection + COSEL: packed union { + raw: u1, + value: COSEL, }, - /// MCO2 prescaler - MCO2PRE: packed union { - raw: u3, - value: MCOPRE, + /// Output polarity + POL: packed union { + raw: u1, + value: POL, }, - /// Microcontroller clock output 2 - MCO2SEL: packed union { + /// Output selection + OSEL: packed union { raw: u2, - value: MCO2SEL, + value: OSEL, }, + /// Calibration output enable + COE: u1, + /// Timestamp on internal event enable + ITSE: u1, + padding: u7, }), - /// clock interrupt register - CIR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// Main PLL (PLL) ready interrupt flag - PLLRDYF: u1, - /// PLLI2S ready interrupt flag - PLLI2SRDYF: u1, - reserved7: u1, - /// Clock security system interrupt flag - CSSF: u1, - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// Main PLL (PLL) ready interrupt enable - PLLRDYIE: u1, - /// PLLI2S ready interrupt enable - PLLI2SRDYIE: u1, + /// Initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm write enabled + ALRWF: u1, + reserved2: u1, + /// Wakeup timer write enabled + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Enter Initialization mode + INIT: u1, + /// Alarm flag + ALRF: u1, + reserved10: u1, + /// Wakeup timer flag + WUTF: u1, + /// Timestamp flag + TSF: u1, + /// Timestamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMPF: u1, reserved16: u2, - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// Main PLL(PLL) ready interrupt clear - PLLRDYC: u1, - /// PLLI2S ready interrupt clear - PLLI2SRDYC: u1, - reserved23: u1, - /// Clock security system interrupt clear - CSSC: u1, - padding: u8, - }), - /// AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - /// IO port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// IO port H reset - GPIOHRST: u1, - /// IO port I reset - GPIOIRST: u1, - reserved12: u3, - /// CRC reset - CRCRST: u1, - reserved21: u8, - /// DMA2 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - reserved25: u2, - /// Ethernet MAC reset - ETHRST: u1, - reserved29: u3, - /// USB OTG HS module reset - USB_OTG_HSRST: u1, - padding: u2, - }), - /// AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// Camera interface reset - DCMIRST: u1, - reserved4: u3, - /// Cryptographic module reset - CRYPRST: u1, - /// Hash module reset - HSAHRST: u1, - /// Random number generator module reset - RNGRST: u1, - /// USB OTG FS module reset - USB_OTG_FSRST: u1, - padding: u24, - }), - /// AHB3 peripheral reset register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - /// Flexible static memory controller module reset - FSMCRST: u1, - padding: u31, - }), - reserved32: [4]u8, - /// APB1 peripheral reset register - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// TIM2 reset - TIM2RST: u1, - /// TIM3 reset - TIM3RST: u1, - /// TIM4 reset - TIM4RST: u1, - /// TIM5 reset - TIM5RST: u1, - /// TIM6 reset - TIM6RST: u1, - /// TIM7 reset - TIM7RST: u1, - /// TIM12 reset - TIM12RST: u1, - /// TIM13 reset - TIM13RST: u1, - /// TIM14 reset - TIM14RST: u1, - reserved11: u2, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI 2 reset - SPI2RST: u1, - /// SPI 3 reset - SPI3RST: u1, - reserved17: u1, - /// USART 2 reset - UART2RST: u1, - /// USART 3 reset - UART3RST: u1, - /// USART 4 reset - UART4RST: u1, - /// USART 5 reset - UART5RST: u1, - /// I2C 1 reset - I2C1RST: u1, - /// I2C 2 reset - I2C2RST: u1, - /// I2C3 reset - I2C3RST: u1, - reserved25: u1, - /// CAN1 reset - CAN1RST: u1, - /// CAN2 reset - CAN2RST: u1, - reserved28: u1, - /// Power interface reset - PWRRST: u1, - /// DAC reset - DACRST: u1, - padding: u2, + /// Recalibration pending flag + RECALPF: packed union { + raw: u1, + value: RECALPF, + }, + /// Internal time-stamp flag + ITSF: u1, + padding: u14, }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// TIM1 reset - TIM1RST: u1, - /// TIM8 reset - TIM8RST: u1, - reserved4: u2, - /// USART1 reset - USART1RST: u1, - /// USART6 reset - USART6RST: u1, - reserved8: u2, - /// ADC interface reset (common to all ADCs) - ADCRST: u1, - reserved11: u2, - /// SDIO reset - SDIORST: u1, - /// SPI 1 reset - SPI1RST: u1, - reserved14: u1, - /// System configuration controller reset - SYSCFGRST: u1, + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, reserved16: u1, - /// TIM9 reset - TIM9RST: u1, - /// TIM10 reset - TIM10RST: u1, - /// TIM11 reset - TIM11RST: u1, - padding: u13, - }), - reserved48: [8]u8, - /// AHB1 peripheral clock register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port C clock enable - GPIOCEN: u1, - /// IO port D clock enable - GPIODEN: u1, - /// IO port E clock enable - GPIOEEN: u1, - /// IO port F clock enable - GPIOFEN: u1, - /// IO port G clock enable - GPIOGEN: u1, - /// IO port H clock enable - GPIOHEN: u1, - /// IO port I clock enable - GPIOIEN: u1, - reserved12: u3, - /// CRC clock enable - CRCEN: u1, - reserved18: u5, - /// Backup SRAM interface clock enable - BKPSRAMEN: u1, - reserved21: u2, - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - reserved25: u2, - /// Ethernet MAC clock enable - ETHEN: u1, - /// Ethernet Transmission clock enable - ETHTXEN: u1, - /// Ethernet Reception clock enable - ETHRXEN: u1, - /// Ethernet PTP clock enable - ETHPTPEN: u1, - /// USB OTG HS clock enable - USB_OTG_HSEN: u1, - /// USB OTG HSULPI clock enable - USB_OTG_HSULPIEN: u1, - padding: u1, - }), - /// AHB2 peripheral clock enable register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// Camera interface enable - DCMIEN: u1, - reserved4: u3, - /// Cryptographic modules clock enable - CRYPEN: u1, - /// Hash modules clock enable - HASHEN: u1, - /// Random number generator clock enable - RNGEN: u1, - /// USB OTG FS clock enable - USB_OTG_FSEN: u1, - padding: u24, - }), - /// AHB3 peripheral clock enable register - AHB3ENR: mmio.Mmio(packed struct(u32) { - /// Flexible static memory controller module clock enable - FSMCEN: u1, - padding: u31, - }), - reserved64: [4]u8, - /// APB1 peripheral clock enable register - APB1ENR: mmio.Mmio(packed struct(u32) { - /// TIM2 clock enable - TIM2EN: u1, - /// TIM3 clock enable - TIM3EN: u1, - /// TIM4 clock enable - TIM4EN: u1, - /// TIM5 clock enable - TIM5EN: u1, - /// TIM6 clock enable - TIM6EN: u1, - /// TIM7 clock enable - TIM7EN: u1, - /// TIM12 clock enable - TIM12EN: u1, - /// TIM13 clock enable - TIM13EN: u1, - /// TIM14 clock enable - TIM14EN: u1, - reserved11: u2, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI2 clock enable - SPI2EN: u1, - /// SPI3 clock enable - SPI3EN: u1, - reserved17: u1, - /// USART 2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// UART5 clock enable - UART5EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - /// I2C2 clock enable - I2C2EN: u1, - /// I2C3 clock enable - I2C3EN: u1, - reserved25: u1, - /// CAN 1 clock enable - CAN1EN: u1, - /// CAN 2 clock enable - CAN2EN: u1, - reserved28: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - padding: u2, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, }), - /// APB2 peripheral clock enable register - APB2ENR: mmio.Mmio(packed struct(u32) { - /// TIM1 clock enable - TIM1EN: u1, - /// TIM8 clock enable - TIM8EN: u1, - reserved4: u2, - /// USART1 clock enable - USART1EN: u1, - /// USART6 clock enable - USART6EN: u1, - reserved8: u2, - /// ADC1 clock enable - ADC1EN: u1, - /// ADC2 clock enable - ADC2EN: u1, - /// ADC3 clock enable - ADC3EN: u1, - /// SDIO clock enable - SDIOEN: u1, - /// SPI1 clock enable - SPI1EN: u1, - reserved14: u1, - /// System configuration controller clock enable - SYSCFGEN: u1, - reserved16: u1, - /// TIM9 clock enable - TIM9EN: u1, - /// TIM10 clock enable - TIM10EN: u1, - /// TIM11 clock enable - TIM11EN: u1, - padding: u13, + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + padding: u16, }), - reserved80: [8]u8, - /// AHB1 peripheral clock enable in low power mode register - AHB1LPENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable during sleep mode - GPIOALPEN: u1, - /// IO port B clock enable during Sleep mode - GPIOBLPEN: u1, - /// IO port C clock enable during Sleep mode - GPIOCLPEN: u1, - /// IO port D clock enable during Sleep mode - GPIODLPEN: u1, - /// IO port E clock enable during Sleep mode - GPIOELPEN: u1, - /// IO port F clock enable during Sleep mode - GPIOFLPEN: u1, - /// IO port G clock enable during Sleep mode - GPIOGLPEN: u1, - /// IO port H clock enable during Sleep mode - GPIOHLPEN: u1, - /// IO port I clock enable during Sleep mode - GPIOILPEN: u1, - reserved12: u3, - /// CRC clock enable during Sleep mode - CRCLPEN: u1, - reserved15: u2, - /// Flash interface clock enable during Sleep mode - FLASHLPEN: u1, - /// SRAM 1interface clock enable during Sleep mode - SRAM1LPEN: u1, - /// SRAM 2 interface clock enable during Sleep mode - SRAM2LPEN: u1, - /// Backup SRAM interface clock enable during Sleep mode - BKPSRAMLPEN: u1, - reserved21: u2, - /// DMA1 clock enable during Sleep mode - DMA1LPEN: u1, - /// DMA2 clock enable during Sleep mode - DMA2LPEN: u1, - reserved25: u2, - /// Ethernet MAC clock enable during Sleep mode - ETHLPEN: u1, - /// Ethernet transmission clock enable during Sleep mode - ETHTXLPEN: u1, - /// Ethernet reception clock enable during Sleep mode - ETHRXLPEN: u1, - /// Ethernet PTP clock enable during Sleep mode - ETHPTPLPEN: u1, - /// USB OTG HS clock enable during Sleep mode - USB_OTG_HSLPEN: u1, - /// USB OTG HS ULPI clock enable during Sleep mode - USB_OTG_HSULPILPEN: u1, - padding: u1, + reserved28: [4]u8, + /// Alarm register + ALRMR: [2]mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm seconds mask + MSK1: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm minutes mask + MSK2: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: ALRMR_PM, + }, + /// Alarm hours mask + MSK3: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { + raw: u1, + value: ALRMR_WDSEL, + }, + /// Alarm date mask + MSK4: packed union { + raw: u1, + value: ALRMR_MSK, + }, }), - /// AHB2 peripheral clock enable in low power mode register - AHB2LPENR: mmio.Mmio(packed struct(u32) { - /// Camera interface enable during Sleep mode - DCMILPEN: u1, - reserved4: u3, - /// Cryptography modules clock enable during Sleep mode - CRYPLPEN: u1, - /// Hash modules clock enable during Sleep mode - HASHLPEN: u1, - /// Random number generator clock enable during Sleep mode - RNGLPEN: u1, - /// USB OTG FS clock enable during Sleep mode - USB_OTG_FSLPEN: u1, + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, padding: u24, }), - /// AHB3 peripheral clock enable in low power mode register - AHB3LPENR: mmio.Mmio(packed struct(u32) { - /// Flexible static memory controller module clock enable during Sleep mode - FSMCLPEN: u1, - padding: u31, + /// Sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, }), - reserved96: [4]u8, - /// APB1 peripheral clock enable in low power mode register - APB1LPENR: mmio.Mmio(packed struct(u32) { - /// TIM2 clock enable during Sleep mode - TIM2LPEN: u1, - /// TIM3 clock enable during Sleep mode - TIM3LPEN: u1, - /// TIM4 clock enable during Sleep mode - TIM4LPEN: u1, - /// TIM5 clock enable during Sleep mode - TIM5LPEN: u1, - /// TIM6 clock enable during Sleep mode - TIM6LPEN: u1, - /// TIM7 clock enable during Sleep mode - TIM7LPEN: u1, - /// TIM12 clock enable during Sleep mode - TIM12LPEN: u1, - /// TIM13 clock enable during Sleep mode - TIM13LPEN: u1, - /// TIM14 clock enable during Sleep mode - TIM14LPEN: u1, - reserved11: u2, - /// Window watchdog clock enable during Sleep mode - WWDGLPEN: u1, - reserved14: u2, - /// SPI2 clock enable during Sleep mode - SPI2LPEN: u1, - /// SPI3 clock enable during Sleep mode - SPI3LPEN: u1, - reserved17: u1, - /// USART2 clock enable during Sleep mode - USART2LPEN: u1, - /// USART3 clock enable during Sleep mode - USART3LPEN: u1, - /// UART4 clock enable during Sleep mode - UART4LPEN: u1, - /// UART5 clock enable during Sleep mode - UART5LPEN: u1, - /// I2C1 clock enable during Sleep mode - I2C1LPEN: u1, - /// I2C2 clock enable during Sleep mode - I2C2LPEN: u1, - /// I2C3 clock enable during Sleep mode - I2C3LPEN: u1, - reserved25: u1, - /// CAN 1 clock enable during Sleep mode - CAN1LPEN: u1, - /// CAN 2 clock enable during Sleep mode - CAN2LPEN: u1, - reserved28: u1, - /// Power interface clock enable during Sleep mode - PWRLPEN: u1, - /// DAC interface clock enable during Sleep mode - DACLPEN: u1, - padding: u2, + /// Shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, }), - /// APB2 peripheral clock enabled in low power mode register - APB2LPENR: mmio.Mmio(packed struct(u32) { - /// TIM1 clock enable during Sleep mode - TIM1LPEN: u1, - /// TIM8 clock enable during Sleep mode - TIM8LPEN: u1, - reserved4: u2, - /// USART1 clock enable during Sleep mode - USART1LPEN: u1, - /// USART6 clock enable during Sleep mode - USART6LPEN: u1, - reserved8: u2, - /// ADC1 clock enable during Sleep mode - ADC1LPEN: u1, - /// ADC2 clock enable during Sleep mode - ADC2LPEN: u1, - /// ADC 3 clock enable during Sleep mode - ADC3LPEN: u1, - /// SDIO clock enable during Sleep mode - SDIOLPEN: u1, - /// SPI 1 clock enable during Sleep mode - SPI1LPEN: u1, - reserved14: u1, - /// System configuration controller clock enable during Sleep mode - SYSCFGLPEN: u1, + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, reserved16: u1, - /// TIM9 clock enable during sleep mode - TIM9LPEN: u1, - /// TIM10 clock enable during Sleep mode - TIM10LPEN: u1, - /// TIM11 clock enable during Sleep mode - TIM11LPEN: u1, - padding: u13, - }), - reserved112: [8]u8, - /// Backup domain control register - BDCR: mmio.Mmio(packed struct(u32) { - /// External low-speed oscillator enable - LSEON: u1, - /// External low-speed oscillator ready - LSERDY: u1, - /// External low-speed oscillator bypass - LSEBYP: u1, - reserved8: u5, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - padding: u15, + padding: u9, }), - /// clock control & status register - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low-speed oscillator enable - LSION: u1, - /// Internal low-speed oscillator ready - LSIRDY: u1, - reserved24: u22, - /// Remove reset flag - RMVF: u1, - /// BOR reset flag - BORRSTF: u1, - /// PIN reset flag - PADRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - WDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding: u16, }), - reserved128: [8]u8, - /// spread spectrum clock generation register - SSCGR: mmio.Mmio(packed struct(u32) { - /// Modulation period - MODPER: u13, - /// Incrementation step - INCSTEP: u15, - reserved30: u2, - /// Spread Select - SPREADSEL: packed union { + /// Timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// Calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved13: u4, + /// Use a 16-second calibration cycle period + CALW16: packed union { raw: u1, - value: SPREADSEL, + value: CALW16, }, - /// Spread spectrum modulation enable - SSCGEN: u1, + /// Use an 8-second calibration cycle period + CALW8: packed union { + raw: u1, + value: CALW8, + }, + /// Increase frequency of RTC by 488.5 ppm + CALP: packed union { + raw: u1, + value: CALP, + }, + padding: u16, }), - /// PLLI2S configuration register - PLLI2SCFGR: mmio.Mmio(packed struct(u32) { - reserved6: u6, - /// PLLI2S multiplication factor for VCO - PLLN: packed union { - raw: u9, - value: PLLN, + /// Tamper configuration register + TAMPCR: mmio.Mmio(packed struct(u32) { + /// Tamper detection enable + TAMPE: u1, + /// Active level for tamper + TAMPTRG: packed union { + raw: u1, + value: TAMPTRG, }, - reserved28: u13, - /// PLLI2S division factor for I2S clocks - PLLR: packed union { + /// Tamper interrupt enable + TAMPIE: u1, + reserved7: u4, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: packed union { raw: u3, - value: PLLR, + value: TAMPFREQ, }, - padding: u1, + /// Tamper filter count + TAMPFLT: packed union { + raw: u2, + value: TAMPFLT, + }, + /// Tamper precharge duration + TAMPPRCH: packed union { + raw: u2, + value: TAMPPRCH, + }, + /// Tamper pull-up disable + TAMPPUDIS: packed union { + raw: u1, + value: TAMPPUDIS, + }, + /// Tamper interrupt enable + TAMPXIE: u1, + /// Tamper no erase + TAMPXNOERASE: u1, + /// Tamper mask flag + TAMPXMF: u1, + padding: u13, + }), + /// Alarm sub second register + ALRMSSR: [2]mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, + }), + /// Option register + OR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Timestamp mapping + TSINSEL: u2, + /// RTC_ALARM on PC13 output type + RTC_ALARM_TYPE: u1, + padding: u28, + }), + /// Backup register + BKPR: [32]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, }), }; }; - pub const lptim_v2b = struct { - pub const CCP_Input = enum(u2) { - Rising = 0x0, - Falling = 0x1, - Both = 0x3, + pub const rtc_v2h7 = struct { + pub const ALRMR_MSK = enum(u1) { + /// Alarm set if the date/day match + ToMatch = 0x0, + /// Date/day don’t care in Alarm comparison + NotMatch = 0x1, + }; + + pub const ALRMR_PM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const ALRMR_WDSEL = enum(u1) { + /// DU[3:0] represents the date units + DateUnits = 0x0, + /// DU[3:0] represents the week day. DT[1:0] is don’t care + WeekDay = 0x1, + }; + + pub const AMPM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const CALP = enum(u1) { + /// No RTCCLK pulses are added + NoChange = 0x0, + /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + IncreaseFreq = 0x1, + }; + + pub const CALW16 = enum(u1) { + /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + Sixteen_Second = 0x1, _, }; - pub const CCP_Output = enum(u2) { - ActiveHigh = 0x0, - ActiveLow = 0x1, + pub const CALW8 = enum(u1) { + /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + Eight_Second = 0x1, _, }; - pub const CCSEL = enum(u1) { - /// channel is configured in output PWM mode - OutputCompare = 0x0, - /// channel is configured in input capture mode - InputCapture = 0x1, + pub const COSEL = enum(u1) { + /// Calibration output is 512 Hz (with default prescaler setting) + CalFreq_512Hz = 0x0, + /// Calibration output is 1 Hz (with default prescaler setting) + CalFreq_1Hz = 0x1, }; - pub const CKPOL = enum(u2) { - /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. - Rising = 0x0, - /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. - Falling = 0x1, - /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. - Both = 0x2, + pub const FMT = enum(u1) { + /// 24 hour/day format + Twenty_Four_Hour = 0x0, + /// AM/PM hour format + AM_PM = 0x1, + }; + + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Alarm B output enabled + AlarmB = 0x2, + /// Wakeup output enabled + Wakeup = 0x3, + }; + + pub const POL = enum(u1) { + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + Low = 0x1, + }; + + pub const RECALPF = enum(u1) { + /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + Pending = 0x1, _, }; - pub const ClockSource = enum(u1) { - /// clocked by internal clock source (APB clock or any of the embedded oscillators) - Internal = 0x0, - /// clocked by an external clock source through the LPTIM external Input1 - External = 0x1, + pub const TAMPFLT = enum(u2) { + /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + Immediate = 0x0, + /// Tamper event is activated after 2 consecutive samples at the active level + Samples2 = 0x1, + /// Tamper event is activated after 4 consecutive samples at the active level + Samples4 = 0x2, + /// Tamper event is activated after 8 consecutive samples at the active level + Samples8 = 0x3, }; - pub const Filter = enum(u2) { - Count1 = 0x0, - Count2 = 0x1, - Count4 = 0x2, - Count8 = 0x3, + pub const TAMPFREQ = enum(u3) { + /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + Div32768 = 0x0, + /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + Div16384 = 0x1, + /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + Div8192 = 0x2, + /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + Div4096 = 0x3, + /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + Div2048 = 0x4, + /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + Div1024 = 0x5, + /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + Div512 = 0x6, + /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + Div256 = 0x7, }; - pub const PRESC = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div4 = 0x2, - Div8 = 0x3, - Div16 = 0x4, - Div32 = 0x5, - Div64 = 0x6, - Div128 = 0x7, + pub const TAMPPRCH = enum(u2) { + /// 1 RTCCLK cycle + Cycles1 = 0x0, + /// 2 RTCCLK cycles + Cycles2 = 0x1, + /// 4 RTCCLK cycles + Cycles4 = 0x2, + /// 8 RTCCLK cycles + Cycles8 = 0x3, }; - pub const TRIGEN = enum(u2) { - /// software trigger (counting start is initiated by software) - Software = 0x0, - /// rising edge is the active edge - RisingEdge = 0x1, - /// falling edge is the active edge - FallingEdge = 0x2, - /// both edges are active edges - BothEdge = 0x3, + pub const TAMPPUDIS = enum(u1) { + /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + Enabled = 0x0, + /// Disable precharge of RTC_TAMPx pins + Disabled = 0x1, }; - /// Low power timer with Output Compare - pub const LPTIM = extern struct { - /// LPTIM interrupt and status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, - /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. - ARRM: u1, - /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. - EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, - /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. - ARROK: u1, - /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UP: u1, - /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWN: u1, - /// LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. - UE: u1, - /// Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. - REPOK: u1, - reserved12: u3, - /// Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCOF: u1, - reserved24: u11, - /// Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. - DIEROK: u1, - padding: u7, - }), - /// LPTIM interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, - /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. - ARRMCF: u1, - /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. - EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, - /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. - ARROKCF: u1, - /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPCF: u1, - /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNCF: u1, - /// Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. - UECF: u1, - /// Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. - REPOKCF: u1, - reserved12: u3, - /// Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCOCF: u1, - reserved24: u11, - /// Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. - DIEROKCF: u1, - padding: u7, + pub const TAMPTRG = enum(u1) { + /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. + RisingEdge = 0x0, + /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event + FallingEdge = 0x1, + }; + + pub const TSEDGE = enum(u1) { + /// RTC_TS input rising edge generates a time-stamp event + RisingEdge = 0x0, + /// RTC_TS input falling edge generates a time-stamp event + FallingEdge = 0x1, + }; + + pub const WUCKSEL = enum(u3) { + /// RTC/16 clock is selected + Div16 = 0x0, + /// RTC/8 clock is selected + Div8 = 0x1, + /// RTC/4 clock is selected + Div4 = 0x2, + /// RTC/2 clock is selected + Div2 = 0x3, + /// ck_spre (usually 1 Hz) clock is selected + ClockSpare = 0x4, + /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + ClockSpareWithOffset = 0x6, + _, + }; + + /// Real-time clock + pub const RTC = extern struct { + /// Time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, + }, + padding: u9, }), - /// LPTIM interrupt enable register. - DIER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, - /// Autoreload match Interrupt Enable. - ARRMIE: u1, - /// External trigger valid edge Interrupt Enable. - EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, - /// Autoreload register update OK Interrupt Enable. - ARROKIE: u1, - /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPIE: u1, - /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNIE: u1, - /// Update event interrupt enable. - UEIE: u1, - /// Repetition register update OK interrupt Enable. - REPOKIE: u1, - reserved12: u3, - /// Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCOIE: u1, - reserved16: u3, - /// Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCDE: u1, - padding: u15, + /// Date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, }), - /// LPTIM configuration register. - CFGR: mmio.Mmio(packed struct(u32) { - /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. - CKSEL: packed union { - raw: u1, - value: ClockSource, + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WUCKSEL: packed union { + raw: u3, + value: WUCKSEL, }, - /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. - CKPOL: packed union { - raw: u2, - value: CKPOL, + /// Timestamp event active edge + TSEDGE: packed union { + raw: u1, + value: TSEDGE, }, - /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - CKFLT: packed union { - raw: u2, - value: Filter, + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + /// Bypass the shadow registers + BYPSHAD: u1, + /// Hour format + FMT: packed union { + raw: u1, + value: FMT, }, - reserved6: u1, - /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. - TRGFLT: packed union { - raw: u2, - value: Filter, + reserved8: u1, + /// Alarm enable + ALRE: u1, + reserved10: u1, + /// Wakeup timer enable + WUTE: u1, + /// Timestamp enable + TSE: u1, + /// Alarm interrupt enable + ALRIE: u1, + reserved14: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Timestamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output selection + COSEL: packed union { + raw: u1, + value: COSEL, }, - reserved9: u1, - /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. - PRESC: packed union { - raw: u3, - value: PRESC, + /// Output polarity + POL: packed union { + raw: u1, + value: POL, }, - reserved13: u1, - /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. - TRIGSEL: u3, - reserved17: u1, - /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. - TRIGEN: packed union { + /// Output selection + OSEL: packed union { raw: u2, - value: TRIGEN, + value: OSEL, }, - /// Timeout enable The TIMOUT bit controls the Timeout feature. - TIMOUT: u1, - /// Waveform shape The WAVE bit controls the output shape. - WAVE: u1, - reserved22: u1, - /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. - PRELOAD: u1, - /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. - COUNTMODE: packed union { + /// Calibration output enable + COE: u1, + /// Timestamp on internal event enable + ITSE: u1, + padding: u7, + }), + /// Initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm write enabled + ALRWF: u1, + reserved2: u1, + /// Wakeup timer write enabled + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Enter Initialization mode + INIT: u1, + /// Alarm flag + ALRF: u1, + reserved10: u1, + /// Wakeup timer flag + WUTF: u1, + /// Timestamp flag + TSF: u1, + /// Timestamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMPF: u1, + reserved16: u2, + /// Recalibration pending flag + RECALPF: packed union { raw: u1, - value: ClockSource, + value: RECALPF, }, - /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - ENC: u1, - padding: u7, + /// Internal time-stamp flag + ITSF: u1, + padding: u14, }), - /// LPTIM control register. - CR: mmio.Mmio(packed struct(u32) { - /// LPTIM enable The ENABLE bit is set and cleared by software. - ENABLE: u1, - /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. - SNGSTRT: u1, - /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. - CNTSTRT: u1, - /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. - COUNTRST: u1, - /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. - RSTARE: u1, - padding: u27, + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, }), - /// LPTIM compare register 1. - CCR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. - CCR: u16, + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, padding: u16, }), - /// LPTIM autoreload register. - ARR: mmio.Mmio(packed struct(u32) { - /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. - ARR: u16, + reserved28: [4]u8, + /// Alarm register + ALRMR: [2]mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm seconds mask + MSK1: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm minutes mask + MSK2: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: ALRMR_PM, + }, + /// Alarm hours mask + MSK3: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { + raw: u1, + value: ALRMR_WDSEL, + }, + /// Alarm date mask + MSK4: packed union { + raw: u1, + value: ALRMR_MSK, + }, + }), + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, + padding: u24, + }), + /// Sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, padding: u16, }), - /// LPTIM counter register. - CNT: mmio.Mmio(packed struct(u32) { - /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. - CNT: u16, + /// Shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, + }), + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, + }, + padding: u9, + }), + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, padding: u16, }), - reserved36: [4]u8, - /// LPTIM configuration register 2. - CFGR2: mmio.Mmio(packed struct(u32) { - /// LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. - INSEL: u2, - reserved16: u14, - /// LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. - ICSEL: u2, - padding: u14, + /// Timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, }), - /// LPTIM repetition register. - RCR: mmio.Mmio(packed struct(u32) { - /// Repetition register value REP is the repetition value for the LPTIM. - REP: u8, - padding: u24, + /// Calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved13: u4, + /// Use a 16-second calibration cycle period + CALW16: packed union { + raw: u1, + value: CALW16, + }, + /// Use an 8-second calibration cycle period + CALW8: packed union { + raw: u1, + value: CALW8, + }, + /// Increase frequency of RTC by 488.5 ppm + CALP: packed union { + raw: u1, + value: CALP, + }, + padding: u16, }), - /// LPTIM capture/compare mode register. - CCMR: mmio.Mmio(packed struct(u32) { - /// Capture/compare selection. This bitfield defines the direction of the channel input (capture) or output mode. - CCSEL: packed union { + /// Tamper configuration register + TAMPCR: mmio.Mmio(packed struct(u32) { + /// Tamper detection enable + TAMPE: u1, + /// Active level for tamper + TAMPTRG: packed union { raw: u1, - value: CCSEL, + value: TAMPTRG, }, - /// Capture/compare output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. - CCE: u1, - /// Capture/compare output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. - CCP_Input: packed union { - raw: u2, - value: CCP_Input, + /// Tamper interrupt enable + TAMPIE: u1, + reserved7: u4, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: packed union { + raw: u3, + value: TAMPFREQ, }, - reserved8: u4, - /// Input capture prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). - ICPSC: packed union { + /// Tamper filter count + TAMPFLT: packed union { raw: u2, - value: Filter, + value: TAMPFLT, }, - reserved12: u2, - /// Input capture filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - ICF: packed union { + /// Tamper precharge duration + TAMPPRCH: packed union { raw: u2, - value: Filter, + value: TAMPPRCH, }, - padding: u18, - }), - }; - }; - - pub const dbgmcu_l5 = struct { - /// MCU debug component - pub const DBGMCU = extern struct { - /// DBGMCU_IDCODE - IDCODE: mmio.Mmio(packed struct(u32) { - /// Device identifier - DEV_ID: u12, - reserved16: u4, - /// Revision identifie - REV_ID: u16, - }), - /// Debug MCU configuration register - CR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Debug Stop mode - DBG_STOP: u1, - /// Debug Standby mode - DBG_STANDBY: u1, - reserved4: u1, - /// Trace pin assignment control - TRACE_IOEN: u1, - /// Trace port and clock enable - TRACE_EN: u1, - /// Trace pin assignment control - TRACE_MODE: u2, - padding: u24, + /// Tamper pull-up disable + TAMPPUDIS: packed union { + raw: u1, + value: TAMPPUDIS, + }, + /// Tamper interrupt enable + TAMPXIE: u1, + /// Tamper no erase + TAMPXNOERASE: u1, + /// Tamper mask flag + TAMPXMF: u1, + padding: u13, }), - /// Debug MCU APB1 freeze register1 - APB1FZR1: mmio.Mmio(packed struct(u32) { - /// TIM2 counter stopped when core is halted - TIM2: u1, - /// TIM3 counter stopped when core is halted - TIM3: u1, - /// TIM4 counter stopped when core is halted - TIM4: u1, - /// TIM5 counter stopped when core is halted - TIM5: u1, - /// TIM6 counter stopped when core is halted - TIM6: u1, - /// TIM7 counter stopped when core is halted - TIM7: u1, - reserved10: u4, - /// RTC counter stopped when core is halted - RTC: u1, - /// Window watchdog counter stopped when core is halted - WWDG: u1, - /// Independent watchdog counter stopped when core is halted - IWDG: u1, - reserved21: u8, - /// I2C1 SMBUS timeout counter stopped when core is halted - I2C1: u1, - /// I2C2 SMBUS timeout counter stopped when core is halted - I2C2: u1, - /// I2C3 SMBUS timeout counter stopped when core is halted - I2C3: u1, - reserved31: u7, - /// LPTIM1 counter stopped when core is halted - LPTIM1: u1, + /// Alarm sub second register + ALRMSSR: [2]mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, }), - /// Debug MCU APB1 freeze register 2 - APB1FZR2: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// I2C4 counter stopped when core is halted - I2C4: u1, - reserved5: u3, - /// LPTIM2 counter stopped when core is halted - LPTIM2: u1, - /// LPTIM3 counter stopped when core is halted - LPTIM3: u1, - padding: u25, + /// Option register + OR: mmio.Mmio(packed struct(u32) { + /// RTC_ALARM output type on PC13 + RTC_ALARM_TYPE: u1, + /// RTC_OUT remap + RTC_OUT_RMP: u1, + padding: u30, }), - /// Debug MCU APB2 freeze register - APB2FZR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 counter stopped when core is halted - TIM1: u1, - reserved13: u1, - /// TIM8 counter stopped when core is halted - TIM8: u1, - reserved16: u2, - /// TIM15 counter stopped when core is halted - TIM15: u1, - /// TIM16 counter stopped when core is halted - TIM16: u1, - /// TIM17 counter stopped when core is halted - TIM17: u1, - padding: u13, + /// Backup register + BKPR: [32]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, }), }; }; - pub const rtc_v2f2 = struct { + pub const rtc_v2l0 = struct { pub const ALRMR_MSK = enum(u1) { /// Alarm set if the date/day match ToMatch = 0x0, @@ -415729,22 +417709,109 @@ pub const types = struct { PM = 0x1, }; - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Alarm B output enabled - AlarmB = 0x2, - /// Wakeup output enabled - Wakeup = 0x3, + pub const CALP = enum(u1) { + /// No RTCCLK pulses are added + NoChange = 0x0, + /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + IncreaseFreq = 0x1, + }; + + pub const CALW16 = enum(u1) { + /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + Sixteen_Second = 0x1, + _, + }; + + pub const CALW8 = enum(u1) { + /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + Eight_Second = 0x1, + _, + }; + + pub const COSEL = enum(u1) { + /// Calibration output is 512 Hz (with default prescaler setting) + CalFreq_512Hz = 0x0, + /// Calibration output is 1 Hz (with default prescaler setting) + CalFreq_1Hz = 0x1, + }; + + pub const FMT = enum(u1) { + /// 24 hour/day format + Twenty_Four_Hour = 0x0, + /// AM/PM hour format + AM_PM = 0x1, + }; + + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Alarm B output enabled + AlarmB = 0x2, + /// Wakeup output enabled + Wakeup = 0x3, + }; + + pub const POL = enum(u1) { + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + Low = 0x1, + }; + + pub const RECALPF = enum(u1) { + /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + Pending = 0x1, + _, + }; + + pub const TAMPFLT = enum(u2) { + /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + Immediate = 0x0, + /// Tamper event is activated after 2 consecutive samples at the active level + Samples2 = 0x1, + /// Tamper event is activated after 4 consecutive samples at the active level + Samples4 = 0x2, + /// Tamper event is activated after 8 consecutive samples at the active level + Samples8 = 0x3, + }; + + pub const TAMPFREQ = enum(u3) { + /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + Div32768 = 0x0, + /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + Div16384 = 0x1, + /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + Div8192 = 0x2, + /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + Div4096 = 0x3, + /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + Div2048 = 0x4, + /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + Div1024 = 0x5, + /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + Div512 = 0x6, + /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + Div256 = 0x7, + }; + + pub const TAMPPRCH = enum(u2) { + /// 1 RTCCLK cycle + Cycles1 = 0x0, + /// 2 RTCCLK cycles + Cycles2 = 0x1, + /// 4 RTCCLK cycles + Cycles4 = 0x2, + /// 8 RTCCLK cycles + Cycles8 = 0x3, }; - pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - Low = 0x1, + pub const TAMPPUDIS = enum(u1) { + /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + Enabled = 0x0, + /// Disable precharge of RTC_TAMPx pins + Disabled = 0x1, }; pub const TAMPTRG = enum(u1) { @@ -415835,11 +417902,14 @@ pub const types = struct { }, /// Reference clock detection enable (50 or 60 Hz) REFCKON: u1, - reserved6: u1, + /// Bypass the shadow registers + BYPSHAD: u1, /// Hour format - FMT: u1, - /// Coarse digital calibration enable - DCE: u1, + FMT: packed union { + raw: u1, + value: FMT, + }, + reserved8: u1, /// Alarm enable ALRE: u1, reserved10: u1, @@ -415860,7 +417930,11 @@ pub const types = struct { SUB1H: u1, /// Backup BKP: u1, - reserved20: u1, + /// Calibration output selection + COSEL: packed union { + raw: u1, + value: COSEL, + }, /// Output polarity POL: packed union { raw: u1, @@ -415873,10991 +417947,9259 @@ pub const types = struct { }, /// Calibration output enable COE: u1, - padding: u8, - }), - /// Initialization and status register - ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, - /// Wakeup timer write enabled - WUTWF: u1, - reserved4: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Enter Initialization mode - INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, - /// Wakeup timer flag - WUTF: u1, - /// Timestamp flag - TSF: u1, - /// Timestamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - padding: u18, - }), - /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, - padding: u9, - }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, - padding: u16, - }), - /// Calibration register - CALIBR: mmio.Mmio(packed struct(u32) { - /// Digital calibration - DC: u5, - reserved7: u2, - /// Digital calibration sign - DCS: u1, - padding: u24, - }), - /// Alarm register - ALRMR: [2]mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm seconds mask - MSK1: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm minutes mask - MSK2: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: ALRMR_PM, - }, - /// Alarm hours mask - MSK3: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { - raw: u1, - value: ALRMR_WDSEL, - }, - /// Alarm date mask - MSK4: packed union { - raw: u1, - value: ALRMR_MSK, - }, - }), - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: u8, - padding: u24, - }), - reserved48: [8]u8, - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, - }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding: u16, - }), - reserved64: [8]u8, - /// Tamper and alternate function configuration register - TAFCR: mmio.Mmio(packed struct(u32) { - /// Tamper detection enable - TAMPE: u1, - /// Active level for tamper - TAMPTRG: packed union { - raw: u1, - value: TAMPTRG, - }, - /// Tamper interrupt enable - TAMPIE: u1, - reserved16: u13, - /// Tamper 1 mapping - TAMP1INSEL: u1, - /// Timestamp mapping - TSINSEL: u1, - /// AFO_ALARM output type - ALARMOUTTYPE: u1, - padding: u13, - }), - reserved80: [12]u8, - /// Backup register - BKPR: [20]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, - }), - }; - }; - - pub const comp_v3 = struct { - pub const BLANKING = enum(u3) { - /// No blanking. - NoBlanking = 0x0, - /// TIM1 OC5 selected as blanking source. - TIM1OC5 = 0x1, - /// TIM2 OC3 selected as blanking source. - TIM2OC3 = 0x2, - _, - }; - - pub const HYST = enum(u2) { - None = 0x0, - Low = 0x1, - Medium = 0x2, - High = 0x3, - }; - - pub const POLARITY = enum(u1) { - /// Output is not inverted. - NotInverted = 0x0, - /// Output is inverted. - Inverted = 0x1, - }; - - pub const PWRMODE = enum(u2) { - /// High speed / full power. - HighSpeed = 0x0, - /// Medium speed / medium power. - MediumSpeed = 0x1, - /// Low speed / low power. - LowSpeed = 0x2, - /// Very-low speed / ultra-low power. - VeryLowSpeed = 0x3, - }; - - /// Comparator. - pub const COMP = extern struct { - /// Comparator control and status register. - CSR: mmio.Mmio(packed struct(u32) { - /// Enable - EN: u1, - reserved2: u1, - /// Power Mode. - PWRMODE: packed union { - raw: u2, - value: PWRMODE, - }, - /// Input minus selection bits. - INMSEL: u3, - /// Input plus selection bit. - INPSEL: u2, - reserved15: u6, - /// Polarity selection bit. - POLARITY: packed union { - raw: u1, - value: POLARITY, - }, - /// Hysteresis selection bits. - HYST: packed union { - raw: u2, - value: HYST, - }, - /// Blanking source selection bits. - BLANKING: packed union { - raw: u3, - value: BLANKING, - }, - reserved22: u1, - /// Scaler bridge enable. - BRGEN: u1, - /// Voltage scaler enable bit. - SCALEN: u1, - reserved25: u1, - /// Input minus extended selection bits. - INMESEL: u2, - reserved30: u3, - /// Output status bit. - VALUE: u1, - /// Register lock bit. - LOCK: u1, - }), - }; - }; - - pub const rcc_g4 = struct { - pub const ADCSEL = enum(u2) { - /// No clock selected - DISABLE = 0x0, - /// PLL 'P' clock selected as ADC clock - PLL1_P = 0x1, - /// System clock selected as ADC clock - SYS = 0x2, - _, - }; - - pub const CLK48SEL = enum(u2) { - /// HSI48 oscillator clock selected as 48 MHz clock - HSI48 = 0x0, - /// PLLQCLK selected as 48 MHz clock - PLL1_Q = 0x2, - _, - }; - - pub const FDCANSEL = enum(u2) { - /// HSE used as FDCAN clock source - HSE = 0x0, - /// PLLQCLK used as FDCAN clock source - PLL1_Q = 0x1, - /// PCLK used as FDCAN clock source - PCLK1 = 0x2, - _, - }; - - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK is divided by 2 - Div2 = 0x8, - /// SYSCLK is divided by 4 - Div4 = 0x9, - /// SYSCLK is divided by 8 - Div8 = 0xa, - /// SYSCLK is divided by 16 - Div16 = 0xb, - /// SYSCLK is divided by 64 - Div64 = 0xc, - /// SYSCLK is divided by 128 - Div128 = 0xd, - /// SYSCLK is divided by 256 - Div256 = 0xe, - /// SYSCLK is divided by 512 - Div512 = 0xf, - _, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCOPRE = enum(u3) { - /// MCO1 not divided - Div1 = 0x0, - /// MCO clock is divided by 2 - Div2 = 0x1, - /// MCO clock is divided by 4 - Div4 = 0x2, - /// MCO clock is divided by 8 - Div8 = 0x3, - /// MCO clock is divided divided by 16 - Div16 = 0x4, - _, - }; - - pub const MCOSEL = enum(u4) { - /// No clock, MCO output disabled - DISABLE = 0x0, - /// SYSCLK selected as MCO source - SYS = 0x1, - /// HSI selected as MCO source - HSI = 0x3, - /// HSE selected as MCO source - HSE = 0x4, - /// Main PLLCLK selected as MCO source - PLLCLK = 0x5, - /// LSI selected as MCO source - LSI = 0x6, - /// LSE selected as MCO source - LSE = 0x7, - /// HSI48 selected as MCO source - HSI48 = 0x8, - _, - }; - - pub const PLLM = enum(u4) { - Div1 = 0x0, - Div2 = 0x1, - Div3 = 0x2, - Div4 = 0x3, - Div5 = 0x4, - Div6 = 0x5, - Div7 = 0x6, - Div8 = 0x7, - Div9 = 0x8, - Div10 = 0x9, - Div11 = 0xa, - Div12 = 0xb, - Div13 = 0xc, - Div14 = 0xd, - Div15 = 0xe, - Div16 = 0xf, - }; - - pub const PLLN = enum(u7) { - Mul8 = 0x8, - Mul9 = 0x9, - Mul10 = 0xa, - Mul11 = 0xb, - Mul12 = 0xc, - Mul13 = 0xd, - Mul14 = 0xe, - Mul15 = 0xf, - Mul16 = 0x10, - Mul17 = 0x11, - Mul18 = 0x12, - Mul19 = 0x13, - Mul20 = 0x14, - Mul21 = 0x15, - Mul22 = 0x16, - Mul23 = 0x17, - Mul24 = 0x18, - Mul25 = 0x19, - Mul26 = 0x1a, - Mul27 = 0x1b, - Mul28 = 0x1c, - Mul29 = 0x1d, - Mul30 = 0x1e, - Mul31 = 0x1f, - Mul32 = 0x20, - Mul33 = 0x21, - Mul34 = 0x22, - Mul35 = 0x23, - Mul36 = 0x24, - Mul37 = 0x25, - Mul38 = 0x26, - Mul39 = 0x27, - Mul40 = 0x28, - Mul41 = 0x29, - Mul42 = 0x2a, - Mul43 = 0x2b, - Mul44 = 0x2c, - Mul45 = 0x2d, - Mul46 = 0x2e, - Mul47 = 0x2f, - Mul48 = 0x30, - Mul49 = 0x31, - Mul50 = 0x32, - Mul51 = 0x33, - Mul52 = 0x34, - Mul53 = 0x35, - Mul54 = 0x36, - Mul55 = 0x37, - Mul56 = 0x38, - Mul57 = 0x39, - Mul58 = 0x3a, - Mul59 = 0x3b, - Mul60 = 0x3c, - Mul61 = 0x3d, - Mul62 = 0x3e, - Mul63 = 0x3f, - Mul64 = 0x40, - Mul65 = 0x41, - Mul66 = 0x42, - Mul67 = 0x43, - Mul68 = 0x44, - Mul69 = 0x45, - Mul70 = 0x46, - Mul71 = 0x47, - Mul72 = 0x48, - Mul73 = 0x49, - Mul74 = 0x4a, - Mul75 = 0x4b, - Mul76 = 0x4c, - Mul77 = 0x4d, - Mul78 = 0x4e, - Mul79 = 0x4f, - Mul80 = 0x50, - Mul81 = 0x51, - Mul82 = 0x52, - Mul83 = 0x53, - Mul84 = 0x54, - Mul85 = 0x55, - Mul86 = 0x56, - Mul87 = 0x57, - Mul88 = 0x58, - Mul89 = 0x59, - Mul90 = 0x5a, - Mul91 = 0x5b, - Mul92 = 0x5c, - Mul93 = 0x5d, - Mul94 = 0x5e, - Mul95 = 0x5f, - Mul96 = 0x60, - Mul97 = 0x61, - Mul98 = 0x62, - Mul99 = 0x63, - Mul100 = 0x64, - Mul101 = 0x65, - Mul102 = 0x66, - Mul103 = 0x67, - Mul104 = 0x68, - Mul105 = 0x69, - Mul106 = 0x6a, - Mul107 = 0x6b, - Mul108 = 0x6c, - Mul109 = 0x6d, - Mul110 = 0x6e, - Mul111 = 0x6f, - Mul112 = 0x70, - Mul113 = 0x71, - Mul114 = 0x72, - Mul115 = 0x73, - Mul116 = 0x74, - Mul117 = 0x75, - Mul118 = 0x76, - Mul119 = 0x77, - Mul120 = 0x78, - Mul121 = 0x79, - Mul122 = 0x7a, - Mul123 = 0x7b, - Mul124 = 0x7c, - Mul125 = 0x7d, - Mul126 = 0x7e, - Mul127 = 0x7f, - _, - }; - - pub const PLLP = enum(u5) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - Div16 = 0x10, - Div17 = 0x11, - Div18 = 0x12, - Div19 = 0x13, - Div20 = 0x14, - Div21 = 0x15, - Div22 = 0x16, - Div23 = 0x17, - Div24 = 0x18, - Div25 = 0x19, - Div26 = 0x1a, - Div27 = 0x1b, - Div28 = 0x1c, - Div29 = 0x1d, - Div30 = 0x1e, - Div31 = 0x1f, - _, - }; - - pub const PLLPBIT = enum(u1) { - Div7 = 0x0, - Div17 = 0x1, - }; - - pub const PLLQ = enum(u2) { - Div2 = 0x0, - Div4 = 0x1, - Div6 = 0x2, - Div8 = 0x3, - }; - - pub const PLLR = enum(u2) { - Div2 = 0x0, - Div4 = 0x1, - Div6 = 0x2, - Div8 = 0x3, - }; - - pub const PLLSRC = enum(u2) { - /// No clock selected as PLL entry clock source - DISABLE = 0x0, - /// HSI selected as PLL entry clock source - HSI = 0x2, - /// HSE selected as PLL entry clock source - HSE = 0x3, - _, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK is divided by 2 - Div2 = 0x4, - /// HCLK is divided by 4 - Div4 = 0x5, - /// HCLK is divided by 8 - Div8 = 0x6, - /// HCLK is divided by 16 - Div16 = 0x7, - _, - }; - - pub const RTCSEL = enum(u2) { - /// No clock used as RTC clock - DISABLE = 0x0, - /// LSE used as RTC clock - LSE = 0x1, - /// LSI used as RTC clock - LSI = 0x2, - /// HSE divided by 32 used as RTC clock - HSE_Div32 = 0x3, - }; - - pub const SW = enum(u2) { - /// HSI selected as system clock - HSI = 0x1, - /// HSE selected as system clock - HSE = 0x2, - /// PLLRCLK selected as system clock - PLL1_R = 0x3, - _, - }; - - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// HSI clock enable - HSION: u1, - /// HSI always enable for peripheral kernels - HSIKERON: u1, - /// HSI clock ready flag - HSIRDY: u1, - reserved16: u5, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE crystal oscillator bypass - HSEBYP: u1, - /// Clock security system enable - CSSON: u1, - reserved24: u4, - /// Main PLL enable - PLLON: u1, - /// Main PLL clock ready flag - PLLRDY: u1, - padding: u6, - }), - /// Internal clock sources calibration register - ICSCR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Internal High Speed clock Calibration - HSICAL0: u8, - /// Internal High Speed clock trimming - HSITRIM: u7, - padding: u1, - }), - /// Clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u2, - value: SW, - }, - /// System clock switch status - SWS: packed union { - raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// PB low-speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, - }, - /// APB high-speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, - }, - reserved24: u10, - /// Microcontroller clock output - MCOSEL: packed union { - raw: u4, - value: MCOSEL, - }, - /// Microcontroller clock output prescaler - MCOPRE: packed union { - raw: u3, - value: MCOPRE, - }, - padding: u1, - }), - /// PLL configuration register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// Main PLL, PLLSAI1 and PLLSAI2 entry clock source - PLLSRC: packed union { - raw: u2, - value: PLLSRC, - }, - reserved4: u2, - /// Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock - PLLM: packed union { - raw: u4, - value: PLLM, - }, - /// Main PLL multiplication factor for VCO - PLLN: packed union { - raw: u7, - value: PLLN, - }, - reserved16: u1, - /// Main PLL PLLSAI3CLK output enable - PLLPEN: u1, - /// Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) - PLLPBIT: packed union { - raw: u1, - value: PLLPBIT, - }, - reserved20: u2, - /// Main PLL PLLUSB1CLK output enable - PLLQEN: u1, - /// Main PLL division factor for PLLUSB1CLK(48 MHz clock) - PLLQ: packed union { - raw: u2, - value: PLLQ, - }, - reserved24: u1, - /// Main PLL PLLCLK output enable - PLLREN: u1, - /// Main PLL division factor for PLLCLK (system clock) - PLLR: packed union { - raw: u2, - value: PLLR, - }, - /// Main PLL division factor for PLLSAI2CLK - PLLP: packed union { - raw: u5, - value: PLLP, - }, - }), - reserved24: [8]u8, - /// Clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - reserved3: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// PLL ready interrupt enable - PLLRDYIE: u1, - reserved9: u3, - /// LSE clock security system interrupt enable - LSECSSIE: u1, - /// HSI48 ready interrupt enable - HSI48RDYIE: u1, - padding: u21, - }), - /// Clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - reserved3: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// PLL ready interrupt flag - PLLRDYF: u1, - reserved8: u2, - /// Clock security system interrupt flag - CSSF: u1, - /// LSE Clock security system interrupt flag - LSECSSF: u1, - /// HSI48 ready interrupt flag - HSI48RDYF: u1, - padding: u21, - }), - /// Clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - reserved3: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// PLL ready interrupt clear - PLLRDYC: u1, - reserved8: u2, - /// Clock security system interrupt clear - CSSC: u1, - /// LSE Clock security system interrupt clear - LSECSSC: u1, - /// HSI48 oscillator ready interrupt clear - HSI48RDYC: u1, - padding: u21, - }), - reserved40: [4]u8, - /// AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// DMA1 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - /// DMAMUX1RST - DMAMUX1RST: u1, - /// CORDIC reset - CORDICRST: u1, - /// FMAC reset - FMACRST: u1, - reserved8: u3, - /// Flash memory interface reset - FLASHRST: u1, - reserved12: u3, - /// CRC reset - CRCRST: u1, - padding: u19, - }), - /// AHB2 peripheral reset register - AHB2RSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - /// IO port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - reserved13: u6, - /// ADC reset - ADC12RST: u1, - /// SAR ADC345 interface reset - ADC345RST: u1, - reserved16: u1, - /// DAC1 interface reset - DAC1RST: u1, - /// DAC2 interface reset - DAC2RST: u1, - /// DAC3 interface reset - DAC3RST: u1, - /// DAC4 interface reset - DAC4RST: u1, - reserved24: u4, - /// Cryptography module reset - AESRST: u1, - reserved26: u1, - /// Random Number Generator module reset - RNGRST: u1, - padding: u5, - }), - /// AHB3 peripheral reset register - AHB3RSTR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller reset - FMCRST: u1, - reserved8: u7, - /// Quad SPI 1 module reset - QUADSPIRST: u1, - padding: u23, - }), - reserved56: [4]u8, - /// APB1 peripheral reset register 1 - APB1RSTR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer reset - TIM2RST: u1, - /// TIM3 timer reset - TIM3RST: u1, - /// TIM3 timer reset - TIM4RST: u1, - /// TIM5 timer reset - TIM5RST: u1, - /// TIM6 timer reset - TIM6RST: u1, - /// TIM7 timer reset - TIM7RST: u1, - reserved8: u2, - /// Clock recovery system reset - CRSRST: u1, - reserved14: u5, - /// SPI2 reset - SPI2RST: u1, - /// SPI3 reset - SPI3RST: u1, - reserved17: u1, - /// USART2 reset - USART2RST: u1, - /// USART3 reset - USART3RST: u1, - /// UART4 reset - UART4RST: u1, - /// UART5 reset - UART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// USBD reset - USBRST: u1, - reserved25: u1, - /// FDCAN reset - FDCANRST: u1, - reserved28: u2, - /// Power interface reset - PWRRST: u1, - reserved30: u1, - /// I2C3 interface reset - I2C3RST: u1, - /// Low Power Timer 1 reset - LPTIM1RST: u1, - }), - /// APB1 peripheral reset register 2 - APB1RSTR2: mmio.Mmio(packed struct(u32) { - /// Low-power UART 1 reset - LPUART1RST: u1, - /// I2C4 reset - I2C4RST: u1, - reserved8: u6, - /// UCPD1 reset - UCPD1RST: u1, - padding: u23, - }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// System configuration (SYSCFG) reset - SYSCFGRST: u1, - reserved11: u10, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI1 reset - SPI1RST: u1, - /// TIM8 timer reset - TIM8RST: u1, - /// USART1 reset - USART1RST: u1, - /// SPI 4 reset - SPI4RST: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - reserved20: u1, - /// Timer 20 reset - TIM20RST: u1, - /// Serial audio interface 1 (SAI1) reset - SAI1RST: u1, - reserved26: u4, - /// HRTIMER reset - HRTIM1RST: u1, - padding: u5, - }), - reserved72: [4]u8, - /// AHB1 peripheral clock enable register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// DMAMUX clock enable - DMAMUX1EN: u1, - /// CORDIC clock enable - CORDICEN: u1, - /// FMAC clock enable - FMACEN: u1, - reserved8: u3, - /// Flash memory interface clock enable - FLASHEN: u1, - reserved12: u3, - /// CRC clock enable - CRCEN: u1, - padding: u19, + padding: u8, }), - /// AHB2 peripheral clock enable register - AHB2ENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port C clock enable - GPIOCEN: u1, - /// IO port D clock enable - GPIODEN: u1, - /// IO port E clock enable - GPIOEEN: u1, - /// IO port F clock enable - GPIOFEN: u1, - /// IO port G clock enable - GPIOGEN: u1, - reserved13: u6, - /// ADC clock enable - ADC12EN: u1, - /// DCMI clock enable - ADC345EN: u1, + /// Initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm write enabled + ALRWF: u1, + reserved2: u1, + /// Wakeup timer write enabled + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Enter Initialization mode + INIT: u1, + /// Alarm flag + ALRF: u1, + reserved10: u1, + /// Wakeup timer flag + WUTF: u1, + /// Timestamp flag + TSF: u1, + /// Timestamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMPF: u1, + reserved16: u2, + /// Recalibration pending flag + RECALPF: packed union { + raw: u1, + value: RECALPF, + }, + padding: u15, + }), + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, reserved16: u1, - /// AES accelerator clock enable - DAC1EN: u1, - /// HASH clock enable - DAC2EN: u1, - /// Random Number Generator clock enable - DAC3EN: u1, - /// DAC4 clock enable - DAC4EN: u1, - reserved24: u4, - /// AES clock enable - AESEN: u1, - reserved26: u1, - /// Random Number Generator clock enable - RNGEN: u1, - padding: u5, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, }), - /// AHB3 peripheral clock enable register - AHB3ENR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller clock enable - FMCEN: u1, - reserved8: u7, - /// QUADSPI memory interface clock enable - QUADSPIEN: u1, - padding: u23, + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + padding: u16, }), - reserved88: [4]u8, - /// APB1ENR1 - APB1ENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clock enable - TIM2EN: u1, - /// TIM3 timer clock enable - TIM3EN: u1, - /// TIM4 timer clock enable - TIM4EN: u1, - /// TIM5 timer clock enable - TIM5EN: u1, - /// TIM6 timer clock enable - TIM6EN: u1, - /// TIM7 timer clock enable - TIM7EN: u1, - reserved8: u2, - /// CRSclock enable - CRSEN: u1, - reserved10: u1, - /// RTC APB clock enable - RTCAPBEN: u1, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI2 clock enable - SPI2EN: u1, - /// SPI3 clock enable - SPI3EN: u1, - reserved17: u1, - /// USART2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// UART5 clock enable - UART5EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - /// I2C2 clock enable - I2C2EN: u1, - /// USB device clock enable - USBEN: u1, - reserved25: u1, - /// FDCAN clock enable - FDCANEN: u1, - reserved28: u2, - /// Power interface clock enable - PWREN: u1, - reserved30: u1, - /// I2C3 clock enable - I2C3EN: u1, - /// Low power timer 1 clock enable - LPTIM1EN: u1, + reserved28: [4]u8, + /// Alarm register + ALRMR: [2]mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm seconds mask + MSK1: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm minutes mask + MSK2: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: ALRMR_PM, + }, + /// Alarm hours mask + MSK3: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { + raw: u1, + value: ALRMR_WDSEL, + }, + /// Alarm date mask + MSK4: packed union { + raw: u1, + value: ALRMR_MSK, + }, }), - /// APB1 peripheral clock enable register 2 - APB1ENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clock enable - LPUART1EN: u1, - /// I2C4 clock enable - I2C4EN: u1, - reserved8: u6, - /// UCPD1 clock enable - UCPD1EN: u1, - padding: u23, + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, + padding: u24, }), - /// APB2ENR - APB2ENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved11: u10, - /// TIM1 timer clock enable - TIM1EN: u1, - /// SPI1 clock enable - SPI1EN: u1, - /// TIM8 timer clock enable - TIM8EN: u1, - /// USART1clock enable - USART1EN: u1, - /// SPI 4 clock enable - SPI4EN: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - reserved20: u1, - /// Timer 20 clock enable - TIM20EN: u1, - /// SAI1 clock enable - SAI1EN: u1, - reserved26: u4, - /// HRTIMER clock enable - HRTIM1EN: u1, - padding: u5, + /// Sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, }), - reserved104: [4]u8, - /// AHB1 peripheral clocks enable in Sleep and Stop modes register - AHB1SMENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clocks enable during Sleep and Stop modes - DMA1SMEN: u1, - /// DMA2 clocks enable during Sleep and Stop modes - DMA2SMEN: u1, - /// DMAMUX clock enable during Sleep and Stop modes - DMAMUX1SMEN: u1, - /// CORDIC clock enable during sleep mode - CORDICSMEN: u1, - /// FMACSM clock enable - FMACSMEN: u1, - reserved8: u3, - /// Flash memory interface clocks enable during Sleep and Stop modes - FLASHSMEN: u1, - /// SRAM1 interface clocks enable during Sleep and Stop modes - SRAM1SMEN: u1, - reserved12: u2, - /// CRCSMEN - CRCSMEN: u1, - padding: u19, + /// Shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, }), - /// AHB2 peripheral clocks enable in Sleep and Stop modes register - AHB2SMENR: mmio.Mmio(packed struct(u32) { - /// IO port A clocks enable during Sleep and Stop modes - GPIOASMEN: u1, - /// IO port B clocks enable during Sleep and Stop modes - GPIOBSMEN: u1, - /// IO port C clocks enable during Sleep and Stop modes - GPIOCSMEN: u1, - /// IO port D clocks enable during Sleep and Stop modes - GPIODSMEN: u1, - /// IO port E clocks enable during Sleep and Stop modes - GPIOESMEN: u1, - /// IO port F clocks enable during Sleep and Stop modes - GPIOFSMEN: u1, - /// IO port G clocks enable during Sleep and Stop modes - GPIOGSMEN: u1, - reserved9: u2, - /// CCM SRAM interface clocks enable during Sleep and Stop modes - CCMSRAMSMEN: u1, - /// SRAM2 interface clocks enable during Sleep and Stop modes - SRAM2SMEN: u1, - reserved13: u2, - /// ADC clocks enable during Sleep and Stop modes - ADC12SMEN: u1, - /// DCMI clock enable during Sleep and Stop modes - ADC345SMEN: u1, + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, reserved16: u1, - /// AES accelerator clocks enable during Sleep and Stop modes - DAC1SMEN: u1, - /// HASH clock enable during Sleep and Stop modes - DAC2SMEN: u1, - /// DAC3 clock enable during sleep mode - DAC3SMEN: u1, - /// DAC4 clock enable during sleep mode - DAC4SMEN: u1, - reserved24: u4, - /// Cryptography clock enable during sleep mode - AESMEN: u1, - reserved26: u1, - /// Random Number Generator clock enable during sleep mode - RNGEN: u1, - padding: u5, - }), - /// AHB3 peripheral clocks enable in Sleep and Stop modes register - AHB3SMENR: mmio.Mmio(packed struct(u32) { - /// Flexible memory controller clocks enable during Sleep and Stop modes - FMCSMEN: u1, - reserved8: u7, - /// QUADSPI memory interface clock enable during Sleep and Stop modes - QUADSPISMEN: u1, - padding: u23, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, + }, + padding: u9, }), - reserved120: [4]u8, - /// APB1SMENR1 - APB1SMENR1: mmio.Mmio(packed struct(u32) { - /// TIM2 timer clocks enable during Sleep and Stop modes - TIM2SMEN: u1, - /// TIM3 timer clocks enable during Sleep and Stop modes - TIM3SMEN: u1, - /// TIM4 timer clocks enable during Sleep and Stop modes - TIM4SMEN: u1, - /// TIM5 timer clocks enable during Sleep and Stop modes - TIM5SMEN: u1, - /// TIM6 timer clocks enable during Sleep and Stop modes - TIM6SMEN: u1, - /// TIM7 timer clocks enable during Sleep and Stop modes - TIM7SMEN: u1, + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, reserved8: u2, - /// CRS clock enable during sleep mode - CRSSMEN: u1, - reserved10: u1, - /// RTC APB clock enable during Sleep and Stop modes - RTCAPBSMEN: u1, - /// Window watchdog clocks enable during Sleep and Stop modes - WWDGSMEN: u1, - reserved14: u2, - /// SPI2 clocks enable during Sleep and Stop modes - SPI2SMEN: u1, - /// SPI3 clocks enable during Sleep and Stop modes - SP3SMEN: u1, - reserved17: u1, - /// USART2 clocks enable during Sleep and Stop modes - USART2SMEN: u1, - /// USART3 clocks enable during Sleep and Stop modes - USART3SMEN: u1, - /// UART4 clocks enable during Sleep and Stop modes - UART4SMEN: u1, - /// UART5 clocks enable during Sleep and Stop modes - UART5SMEN: u1, - /// I2C1 clocks enable during Sleep and Stop modes - I2C1SMEN: u1, - /// I2C2 clocks enable during Sleep and Stop modes - I2C2SMEN: u1, - /// USB device clocks enable during Sleep and Stop modes - USBSMEN: u1, - reserved25: u1, - /// FDCAN clock enable during sleep mode - FDCANSMEN: u1, - reserved28: u2, - /// Power interface clocks enable during Sleep and Stop modes - PWRSMEN: u1, - reserved30: u1, - /// I2C3 clocks enable during Sleep and Stop modes - I2C3SMEN: u1, - /// Low Power Timer1 clock enable during sleep mode - LPTIM1SMEN: u1, - }), - /// APB1 peripheral clocks enable in Sleep and Stop modes register 2 - APB1SMENR2: mmio.Mmio(packed struct(u32) { - /// Low power UART 1 clocks enable during Sleep and Stop modes - LPUART1SMEN: u1, - /// I2C4 clocks enable during Sleep and Stop modes - I2C4SMEN: u1, - reserved8: u6, - /// UCPD1 clocks enable during Sleep and Stop modes - UCPD1SMEN: u1, - padding: u23, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding: u16, }), - /// APB2SMENR - APB2SMENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clocks enable during Sleep and Stop modes - SYSCFGSMEN: u1, - reserved11: u10, - /// TIM1 timer clocks enable during Sleep and Stop modes - TIM1SMEN: u1, - /// SPI1 clocks enable during Sleep and Stop modes - SPI1SMEN: u1, - /// TIM8 timer clocks enable during Sleep and Stop modes - TIM8SMEN: u1, - /// USART1clocks enable during Sleep and Stop modes - USART1SMEN: u1, - /// SPI4 timer clocks enable during Sleep and Stop modes - SPI4SMEN: u1, - /// TIM15 timer clocks enable during Sleep and Stop modes - TIM15SMEN: u1, - /// TIM16 timer clocks enable during Sleep and Stop modes - TIM16SMEN: u1, - /// TIM17 timer clocks enable during Sleep and Stop modes - TIM17SMEN: u1, - reserved20: u1, - /// Timer 20clock enable during sleep mode - TIM20SMEN: u1, - /// SAI1 clock enable during sleep mode - SAI1SMEN: u1, - reserved26: u4, - /// HRTIMER clock enable during sleep mode - HRTIM1SMEN: u1, - padding: u5, + /// Timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, }), - reserved136: [4]u8, - /// CCIPR - CCIPR: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SEL: u2, - /// USART2 clock source selection - USART2SEL: u2, - /// USART3 clock source selection - USART3SEL: u2, - /// UART4 clock source selection - UART4SEL: u2, - /// UART5 clock source selection - UART5SEL: u2, - /// LPUART1 clock source selection - LPUART1SEL: u2, - /// I2C1 clock source selection - I2C1SEL: u2, - /// I2C2 clock source selection - I2C2SEL: u2, - /// I2C3 clock source selection - I2C3SEL: u2, - /// Low power timer 1 clock source selection - LPTIM1SEL: u2, - /// SAI1 clock source selection - SAI1SEL: u2, - /// I2S23 clock source selection - I2S23SEL: u2, - /// FDCAN clock source selection - FDCANSEL: packed union { - raw: u2, - value: FDCANSEL, - }, - /// 48 MHz clock source selection - CLK48SEL: packed union { - raw: u2, - value: CLK48SEL, + /// Calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved13: u4, + /// Use a 16-second calibration cycle period + CALW16: packed union { + raw: u1, + value: CALW16, }, - /// ADCs clock source selection - ADC12SEL: packed union { - raw: u2, - value: ADCSEL, + /// Use an 8-second calibration cycle period + CALW8: packed union { + raw: u1, + value: CALW8, }, - /// ADC3/4/5 clock source selection - ADC345SEL: packed union { - raw: u2, - value: ADCSEL, + /// Increase frequency of RTC by 488.5 ppm + CALP: packed union { + raw: u1, + value: CALP, }, + padding: u16, }), - reserved144: [4]u8, - /// BDCR - BDCR: mmio.Mmio(packed struct(u32) { - /// LSE oscillator enable - LSEON: u1, - /// LSE oscillator ready - LSERDY: u1, - /// LSE oscillator bypass - LSEBYP: u1, - /// SE oscillator drive capability - LSEDRV: packed union { + /// Tamper configuration register + TAMPCR: mmio.Mmio(packed struct(u32) { + /// Tamper detection enable + TAMPE: u1, + /// Active level for tamper + TAMPTRG: packed union { + raw: u1, + value: TAMPTRG, + }, + /// Tamper interrupt enable + TAMPIE: u1, + reserved7: u4, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: packed union { + raw: u3, + value: TAMPFREQ, + }, + /// Tamper filter count + TAMPFLT: packed union { raw: u2, - value: LSEDRV, + value: TAMPFLT, }, - /// LSECSSON - LSECSSON: u1, - /// LSECSSD - LSECSSD: u1, - reserved8: u1, - /// RTC clock source selection - RTCSEL: packed union { + /// Tamper precharge duration + TAMPPRCH: packed union { raw: u2, - value: RTCSEL, + value: TAMPPRCH, }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// RTC domain software reset - BDRST: u1, - reserved24: u7, - /// Low speed clock output enable - LSCOEN: u1, - /// Low speed clock output selection - LSCOSEL: u1, - padding: u6, + /// Tamper pull-up disable + TAMPPUDIS: packed union { + raw: u1, + value: TAMPPUDIS, + }, + /// Tamper interrupt enable + TAMPXIE: u1, + /// Tamper no erase + TAMPXNOERASE: u1, + /// Tamper mask flag + TAMPXMF: u1, + padding: u13, }), - /// CSR - CSR: mmio.Mmio(packed struct(u32) { - /// LSI oscillator enable - LSION: u1, - /// LSI oscillator ready - LSIRDY: u1, - reserved23: u21, - /// Remove reset flag - RMVF: u1, - reserved25: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// Pad reset flag - PINRSTF: u1, - /// BOR flag - BORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent window watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// Alarm sub second register + ALRMSSR: [2]mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, }), - /// Clock recovery RC register - CRRCR: mmio.Mmio(packed struct(u32) { - /// HSI48 clock enable - HSI48ON: u1, - /// HSI48 clock ready flag - HSI48RDY: u1, - reserved7: u5, - /// HSI48 clock calibration - HSI48CAL: u9, - padding: u16, + /// Option register + OR: mmio.Mmio(packed struct(u32) { + /// RTC_ALARM on PC13 output type + RTC_ALARM_TYPE: u1, + /// RTC_ALARM on PC13 output type + RTC_OUT_RMP: u1, + padding: u30, }), - /// Peripherals independent clock configuration register - CCIPR2: mmio.Mmio(packed struct(u32) { - /// I2C4 clock source selection - I2C4SEL: u2, - reserved20: u18, - /// Octospi clock source selection - QUADSPISEL: u2, - padding: u10, + /// Backup register + BKPR: [5]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, }), }; }; - pub const dma_v1 = struct { - pub const BURST = enum(u2) { - /// Single transfer - Single = 0x0, - /// Incremental burst of 4 beats - INCR4 = 0x1, - /// Incremental burst of 8 beats - INCR8 = 0x2, - /// Incremental burst of 16 beats - INCR16 = 0x3, + pub const rtc_v2l1 = struct { + pub const ALRMR_MSK = enum(u1) { + /// Alarm set if the date/day match + ToMatch = 0x0, + /// Date/day don’t care in Alarm comparison + NotMatch = 0x1, }; - pub const CT = enum(u1) { - /// The current target memory is Memory 0 - Memory0 = 0x0, - /// The current target memory is Memory 1 - Memory1 = 0x1, + pub const ALRMR_PM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, }; - pub const DIR = enum(u2) { - /// Peripheral-to-memory - PeripheralToMemory = 0x0, - /// Memory-to-peripheral - MemoryToPeripheral = 0x1, - /// Memory-to-memory - MemoryToMemory = 0x2, + pub const ALRMR_WDSEL = enum(u1) { + /// DU[3:0] represents the date units + DateUnits = 0x0, + /// DU[3:0] represents the week day. DT[1:0] is don’t care + WeekDay = 0x1, + }; + + pub const AMPM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const CALP = enum(u1) { + /// No RTCCLK pulses are added + NoChange = 0x0, + /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + IncreaseFreq = 0x1, + }; + + pub const CALW16 = enum(u1) { + /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + Sixteen_Second = 0x1, _, }; - pub const DMDIS = enum(u1) { - /// Direct mode is enabled - Enabled = 0x0, - /// Direct mode is disabled - Disabled = 0x1, + pub const CALW8 = enum(u1) { + /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + Eight_Second = 0x1, + _, }; - pub const FS = enum(u3) { - /// 0 < fifo_level < 1/4 - Quarter1 = 0x0, - /// 1/4 <= fifo_level < 1/2 - Quarter2 = 0x1, - /// 1/2 <= fifo_level < 3/4 - Quarter3 = 0x2, - /// 3/4 <= fifo_level < full - Quarter4 = 0x3, - /// FIFO is empty - Empty = 0x4, - /// FIFO is full - Full = 0x5, + pub const COSEL = enum(u1) { + /// Calibration output is 512 Hz (with default prescaler setting) + CalFreq_512Hz = 0x0, + /// Calibration output is 1 Hz (with default prescaler setting) + CalFreq_1Hz = 0x1, + }; + + pub const FMT = enum(u1) { + /// 24 hour/day format + Twenty_Four_Hour = 0x0, + /// AM/PM hour format + AM_PM = 0x1, + }; + + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Alarm B output enabled + AlarmB = 0x2, + /// Wakeup output enabled + Wakeup = 0x3, + }; + + pub const POL = enum(u1) { + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + Low = 0x1, + }; + + pub const RECALPF = enum(u1) { + /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + Pending = 0x1, _, }; - pub const FTH = enum(u2) { - /// 1/4 full FIFO - Quarter = 0x0, - /// 1/2 full FIFO - Half = 0x1, - /// 3/4 full FIFO - ThreeQuarters = 0x2, - /// Full FIFO - Full = 0x3, + pub const TAMPFLT = enum(u2) { + /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + Immediate = 0x0, + /// Tamper event is activated after 2 consecutive samples at the active level + Samples2 = 0x1, + /// Tamper event is activated after 4 consecutive samples at the active level + Samples4 = 0x2, + /// Tamper event is activated after 8 consecutive samples at the active level + Samples8 = 0x3, }; - pub const PFCTRL = enum(u1) { - /// The DMA is the flow controller - DMA = 0x0, - /// The peripheral is the flow controller - Peripheral = 0x1, + pub const TAMPFREQ = enum(u3) { + /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + Div32768 = 0x0, + /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + Div16384 = 0x1, + /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + Div8192 = 0x2, + /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + Div4096 = 0x3, + /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + Div2048 = 0x4, + /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + Div1024 = 0x5, + /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + Div512 = 0x6, + /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + Div256 = 0x7, }; - pub const PINCOS = enum(u1) { - /// The offset size for the peripheral address calculation is linked to the PSIZE - PSIZE = 0x0, - /// The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) - Fixed4 = 0x1, + pub const TAMPPRCH = enum(u2) { + /// 1 RTCCLK cycle + Cycles1 = 0x0, + /// 2 RTCCLK cycles + Cycles2 = 0x1, + /// 4 RTCCLK cycles + Cycles4 = 0x2, + /// 8 RTCCLK cycles + Cycles8 = 0x3, }; - pub const PL = enum(u2) { - /// Low - Low = 0x0, - /// Medium - Medium = 0x1, - /// High - High = 0x2, - /// Very high - VeryHigh = 0x3, + pub const TAMPPUDIS = enum(u1) { + /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + Enabled = 0x0, + /// Disable precharge of RTC_TAMPx pins + Disabled = 0x1, }; - pub const SIZE = enum(u2) { - /// Byte (8-bit) - Bits8 = 0x0, - /// Half-word (16-bit) - Bits16 = 0x1, - /// Word (32-bit) - Bits32 = 0x2, + pub const TAMPTRG = enum(u1) { + /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. + RisingEdge = 0x0, + /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event + FallingEdge = 0x1, + }; + + pub const TSEDGE = enum(u1) { + /// RTC_TS input rising edge generates a time-stamp event + RisingEdge = 0x0, + /// RTC_TS input falling edge generates a time-stamp event + FallingEdge = 0x1, + }; + + pub const WUCKSEL = enum(u3) { + /// RTC/16 clock is selected + Div16 = 0x0, + /// RTC/8 clock is selected + Div8 = 0x1, + /// RTC/4 clock is selected + Div4 = 0x2, + /// RTC/2 clock is selected + Div2 = 0x3, + /// ck_spre (usually 1 Hz) clock is selected + ClockSpare = 0x4, + /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + ClockSpareWithOffset = 0x6, _, }; - /// DMA controller - pub const DMA = extern struct { - /// low interrupt status register - ISR: [2]mmio.Mmio(packed struct(u32) { - /// Stream x FIFO error interrupt flag (x=3..0) - FEIF: u1, + /// Real-time clock + pub const RTC = extern struct { + /// Time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, + }, + padding: u9, + }), + /// Date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WUCKSEL: packed union { + raw: u3, + value: WUCKSEL, + }, + /// Timestamp event active edge + TSEDGE: packed union { + raw: u1, + value: TSEDGE, + }, + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + /// Bypass the shadow registers + BYPSHAD: u1, + /// Hour format + FMT: packed union { + raw: u1, + value: FMT, + }, + /// Coarse digital calibration enable + DCE: u1, + /// Alarm enable + ALRE: u1, + reserved10: u1, + /// Wakeup timer enable + WUTE: u1, + /// Timestamp enable + TSE: u1, + /// Alarm interrupt enable + ALRIE: u1, + reserved14: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Timestamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output selection + COSEL: packed union { + raw: u1, + value: COSEL, + }, + /// Output polarity + POL: packed union { + raw: u1, + value: POL, + }, + /// Output selection + OSEL: packed union { + raw: u2, + value: OSEL, + }, + /// Calibration output enable + COE: u1, + padding: u8, + }), + /// Initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm write enabled + ALRWF: u1, reserved2: u1, - /// Stream x direct mode error interrupt flag (x=3..0) - DMEIF: u1, - /// Stream x transfer error interrupt flag (x=3..0) - TEIF: u1, - /// Stream x half transfer interrupt flag (x=3..0) - HTIF: u1, - /// Stream x transfer complete interrupt flag (x = 3..0) - TCIF: u1, - padding: u26, + /// Wakeup timer write enabled + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Enter Initialization mode + INIT: u1, + /// Alarm flag + ALRF: u1, + reserved10: u1, + /// Wakeup timer flag + WUTF: u1, + /// Timestamp flag + TSF: u1, + /// Timestamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMPF: u1, + reserved16: u2, + /// Recalibration pending flag + RECALPF: packed union { + raw: u1, + value: RECALPF, + }, + padding: u15, + }), + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, }), - /// low interrupt flag clear register - IFCR: [2]mmio.Mmio(packed struct(u32) { - /// Stream x FIFO error interrupt flag (x=3..0) - FEIF: u1, - reserved2: u1, - /// Stream x direct mode error interrupt flag (x=3..0) - DMEIF: u1, - /// Stream x transfer error interrupt flag (x=3..0) - TEIF: u1, - /// Stream x half transfer interrupt flag (x=3..0) - HTIF: u1, - /// Stream x transfer complete interrupt flag (x = 3..0) - TCIF: u1, - padding: u26, + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + padding: u16, }), - /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers - ST: u32, - }; - - /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers - pub const ST = extern struct { - /// stream x configuration register - CR: mmio.Mmio(packed struct(u32) { - /// Stream enable / flag stream ready when read low - EN: u1, - /// Direct mode error interrupt enable - DMEIE: u1, - /// Transfer error interrupt enable - TEIE: u1, - /// Half transfer interrupt enable - HTIE: u1, - /// Transfer complete interrupt enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: packed union { + /// Calibration register + CALIBR: mmio.Mmio(packed struct(u32) { + /// Digital calibration + DC: u5, + reserved7: u2, + /// Digital calibration sign + DCS: u1, + padding: u24, + }), + /// Alarm register + ALRMR: [2]mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm seconds mask + MSK1: packed union { raw: u1, - value: PFCTRL, - }, - /// Data transfer direction - DIR: packed union { - raw: u2, - value: DIR, - }, - /// Circular mode enabled - CIRC: u1, - /// Peripheral increment mode enabled - PINC: u1, - /// Memory increment mode enabled - MINC: u1, - /// Peripheral data size - PSIZE: packed union { - raw: u2, - value: SIZE, + value: ALRMR_MSK, }, - /// Memory data size - MSIZE: packed union { - raw: u2, - value: SIZE, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm minutes mask + MSK2: packed union { + raw: u1, + value: ALRMR_MSK, }, - /// Peripheral increment offset size - PINCOS: packed union { + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { raw: u1, - value: PINCOS, + value: ALRMR_PM, }, - /// Priority level - PL: packed union { - raw: u2, - value: PL, + /// Alarm hours mask + MSK3: packed union { + raw: u1, + value: ALRMR_MSK, }, - /// Double buffer mode enabled - DBM: u1, - /// Current target (only in double buffer mode) - CT: packed union { + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { raw: u1, - value: CT, + value: ALRMR_WDSEL, }, - /// Enable bufferable transfers - TRBUFF: u1, - /// Peripheral burst transfer configuration - PBURST: packed union { - raw: u2, - value: BURST, + /// Alarm date mask + MSK4: packed union { + raw: u1, + value: ALRMR_MSK, }, - /// Memory burst transfer configuration - MBURST: packed union { - raw: u2, - value: BURST, + }), + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, + padding: u24, + }), + /// Sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// Shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, + }), + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, }, - padding: u7, + padding: u9, }), - /// stream x number of data register - NDTR: mmio.Mmio(packed struct(u32) { - /// Number of data items to transfer - NDT: u16, + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, padding: u16, }), - /// stream x peripheral address register - PAR: u32, - /// stream x memory 0 address register - M0AR: u32, - /// stream x memory 1 address register - M1AR: u32, - /// stream x FIFO control register - FCR: mmio.Mmio(packed struct(u32) { - /// FIFO threshold selection - FTH: packed union { - raw: u2, - value: FTH, + /// Timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// Calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved13: u4, + /// Use a 16-second calibration cycle period + CALW16: packed union { + raw: u1, + value: CALW16, }, - /// Direct mode disable - DMDIS: packed union { + /// Use an 8-second calibration cycle period + CALW8: packed union { raw: u1, - value: DMDIS, + value: CALW8, }, - /// FIFO status - FS: packed union { + /// Increase frequency of RTC by 488.5 ppm + CALP: packed union { + raw: u1, + value: CALP, + }, + padding: u16, + }), + /// Tamper and alternate function configuration register + TAFCR: mmio.Mmio(packed struct(u32) { + /// Tamper detection enable + TAMPE: u1, + /// Active level for tamper + TAMPTRG: packed union { + raw: u1, + value: TAMPTRG, + }, + /// Tamper interrupt enable + TAMPIE: u1, + reserved7: u4, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: packed union { raw: u3, - value: FS, + value: TAMPFREQ, }, - reserved7: u1, - /// FIFO error interrupt enable - FEIE: u1, - padding: u24, + /// Tamper filter count + TAMPFLT: packed union { + raw: u2, + value: TAMPFLT, + }, + /// Tamper precharge duration + TAMPPRCH: packed union { + raw: u2, + value: TAMPPRCH, + }, + /// Tamper pull-up disable + TAMPPUDIS: packed union { + raw: u1, + value: TAMPPUDIS, + }, + reserved18: u2, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding: u13, + }), + /// Alarm sub second register + ALRMSSR: [2]mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, + }), + reserved80: [4]u8, + /// Backup register + BKPR: [32]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, }), }; }; - pub const flash_h50 = struct { - pub const BKSEL = enum(u1) { - /// Bank1 is selected for Bank erase / sector erase / interrupt enable - BANK1 = 0x0, - /// Bank1 is selected for Bank erase / sector erase / interrupt enable - BANK2 = 0x1, + pub const rtc_v2l4 = struct { + pub const ALRMR_MSK = enum(u1) { + /// Alarm set if the date/day match + ToMatch = 0x0, + /// Date/day don’t care in Alarm comparison + NotMatch = 0x1, }; - pub const CODE_OP = enum(u3) { - /// No Flash operation on going during previous reset - B_0x0 = 0x0, - /// Single write operation interrupted - B_0x1 = 0x1, - /// Sector erase operation interrupted - B_0x3 = 0x3, - /// Bank erase operation interrupted - B_0x4 = 0x4, - /// Mass erase operation interrupted - B_0x5 = 0x5, - /// Option change operation interrupted - B_0x6 = 0x6, - _, + pub const ALRMR_PM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, }; - pub const NSBOOTR_NSBOOT_LOCK = enum(u8) { - /// The NSBOOTADD and SWAP_BANK are frozen. - B_0xB4 = 0xb4, - /// The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. - B_0xC3 = 0xc3, - _, + pub const ALRMR_WDSEL = enum(u1) { + /// DU[3:0] represents the date units + DateUnits = 0x0, + /// DU[3:0] represents the week day. DT[1:0] is don’t care + WeekDay = 0x1, }; - pub const NSPRIV = enum(u1) { - /// access to non secure registers is always granted - B_0x0 = 0x0, - /// access to non secure registers is denied in case of non privileged access. - B_0x1 = 0x1, + pub const AMPM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, }; - pub const OPTSR_BKPRAM_ECC = enum(u1) { - /// BKPRAM ECC check enabled - B_0x0 = 0x0, - /// BKPRAM ECC check disabled - B_0x1 = 0x1, + pub const CALP = enum(u1) { + /// No RTCCLK pulses are added + NoChange = 0x0, + /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + IncreaseFreq = 0x1, }; - pub const OPTSR_BOR_LEV = enum(u2) { - /// BOR OFF, POR/PDR reset threshold level is applied - B_0x0 = 0x0, - /// BOR Level 1, the threshold level is low (around 2.1 V) - B_0x1 = 0x1, - /// BOR Level 2, the threshold level is medium (around 2.4 V) - B_0x2 = 0x2, - /// BOR Level 3, the threshold level is high (around 2.7 V) - B_0x3 = 0x3, + pub const CALW16 = enum(u1) { + /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + Sixteen_Second = 0x1, + _, }; - pub const OPTSR_IO_VDDIO_HSLV = enum(u1) { - /// High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) - B_0x0 = 0x0, - /// High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - B_0x1 = 0x1, + pub const CALW8 = enum(u1) { + /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + Eight_Second = 0x1, + _, }; - pub const OPTSR_IO_VDD_HSLV = enum(u1) { - /// High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) - B_0x0 = 0x0, - /// High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) - B_0x1 = 0x1, + pub const COSEL = enum(u1) { + /// Calibration output is 512 Hz (with default prescaler setting) + CalFreq_512Hz = 0x0, + /// Calibration output is 1 Hz (with default prescaler setting) + CalFreq_1Hz = 0x1, }; - pub const OPTSR_IWDG_STDBY = enum(u1) { - /// Independent watchdog frozen in Standby mode - B_0x0 = 0x0, - /// Independent watchdog keep running in Standby mode. - B_0x1 = 0x1, + pub const FMT = enum(u1) { + /// 24 hour/day format + Twenty_Four_Hour = 0x0, + /// AM/PM hour format + AM_PM = 0x1, }; - pub const OPTSR_IWDG_STOP = enum(u1) { - /// Independent watchdog frozen in system Stop mode - B_0x0 = 0x0, - /// Independent watchdog keep running in system Stop mode. - B_0x1 = 0x1, + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Alarm B output enabled + AlarmB = 0x2, + /// Wakeup output enabled + Wakeup = 0x3, }; - pub const OPTSR_IWDG_SW = enum(u1) { - /// IWDG watchdog is controlled by hardware - B_0x0 = 0x0, - /// IWDG watchdog is controlled by software - B_0x1 = 0x1, + pub const POL = enum(u1) { + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + Low = 0x1, }; - pub const OPTSR_NRST_SHDW = enum(u1) { - /// a reset is generated when entering Shutdown mode on core domain - B_0x0 = 0x0, - /// no reset generated when entering Shutdown mode on core domain. - B_0x1 = 0x1, + pub const RECALPF = enum(u1) { + /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + Pending = 0x1, + _, }; - pub const OPTSR_NRST_STDBY = enum(u1) { - /// a reset is generated when entering Standby mode on core domain - B_0x0 = 0x0, - /// no reset generated when entering Standby mode on core domain. - B_0x1 = 0x1, + pub const TAMPFLT = enum(u2) { + /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + Immediate = 0x0, + /// Tamper event is activated after 2 consecutive samples at the active level + Samples2 = 0x1, + /// Tamper event is activated after 4 consecutive samples at the active level + Samples4 = 0x2, + /// Tamper event is activated after 8 consecutive samples at the active level + Samples8 = 0x3, }; - pub const OPTSR_NRST_STOP = enum(u1) { - /// a reset is generated when entering Stop mode on core domain - B_0x0 = 0x0, - /// no reset generated when entering Stop mode on core domain. - B_0x1 = 0x1, + pub const TAMPFREQ = enum(u3) { + /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + Div32768 = 0x0, + /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + Div16384 = 0x1, + /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + Div8192 = 0x2, + /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + Div4096 = 0x3, + /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + Div2048 = 0x4, + /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + Div1024 = 0x5, + /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + Div512 = 0x6, + /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + Div256 = 0x7, }; - pub const OPTSR_SRAM_ECC = enum(u1) { - /// SRAM2 ECC check enabled - B_0x0 = 0x0, - /// SRAM2 ECC check disabled - B_0x1 = 0x1, + pub const TAMPPRCH = enum(u2) { + /// 1 RTCCLK cycle + Cycles1 = 0x0, + /// 2 RTCCLK cycles + Cycles2 = 0x1, + /// 4 RTCCLK cycles + Cycles4 = 0x2, + /// 8 RTCCLK cycles + Cycles8 = 0x3, }; - pub const OPTSR_WWDG_SW = enum(u1) { - /// WWDG watchdog is controlled by hardware - B_0x0 = 0x0, - /// WWDG watchdog is controlled by software - B_0x1 = 0x1, + pub const TAMPPUDIS = enum(u1) { + /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + Enabled = 0x0, + /// Disable precharge of RTC_TAMPx pins + Disabled = 0x1, }; - pub const PRIVBB = enum(u8) { - /// sectors y in bank 1 is non privileged - B_0x0 = 0x0, - /// sector y in bank 1 is privileged - B_0x1 = 0x1, - _, + pub const TAMPTRG = enum(u1) { + /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. + RisingEdge = 0x0, + /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event + FallingEdge = 0x1, }; - pub const PRODUCT_STATE = enum(u8) { - /// Provisioning - PROVISIONING = 0x17, - /// iROT-Provisioned - IROT_PROVISIONED = 0x2e, - /// Locked - LOCKED = 0x5c, - /// Closed - CLOSED = 0x72, - /// Regression - REGRESSION = 0x9a, - /// Open - OPEN = 0xed, + pub const TSEDGE = enum(u1) { + /// RTC_TS input rising edge generates a time-stamp event + RisingEdge = 0x0, + /// RTC_TS input falling edge generates a time-stamp event + FallingEdge = 0x1, + }; + + pub const WUCKSEL = enum(u3) { + /// RTC/16 clock is selected + Div16 = 0x0, + /// RTC/8 clock is selected + Div8 = 0x1, + /// RTC/4 clock is selected + Div4 = 0x2, + /// RTC/2 clock is selected + Div2 = 0x3, + /// ck_spre (usually 1 Hz) clock is selected + ClockSpare = 0x4, + /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + ClockSpareWithOffset = 0x6, _, }; - /// FLASH address block description - pub const FLASH = extern struct { - /// FLASH access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. ... Note: No check is performed by hardware to verify that the configuration is correct. - LATENCY: u4, - /// Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to for details. Note: No check is performed to verify that the configuration is correct. Two WRHIGHFREQ values can be selected for some frequencies. - WRHIGHFREQ: u2, - reserved8: u2, - /// Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account. Bits used to control the prefetch. - PRFTEN: u1, - /// Smart prefetch enable. When bit value is modified, user must read back ACR register to be sure S_PRFTEN has been taken into account. Bits used to control the prefetch functionality. - S_PRFTEN: u1, - padding: u22, - }), - /// FLASH key register - NSKEYR: u32, - reserved12: [4]u8, - /// FLASH option key register - OPTKEYR: u32, - reserved24: [8]u8, - /// FLASH operation status register - OPSR: mmio.Mmio(packed struct(u32) { - /// Interrupted operation address. - ADDR_OP: u20, - reserved22: u2, - /// Interrupted operation bank It indicates which bank was concerned by operation. - BK_OP: u1, - /// Operation in system Flash memory interrupted Indicates that reset interrupted an ongoing operation in System Flash. - SYSF_OP: u1, - /// OTP operation interrupted Indicates that reset interrupted an ongoing operation in OTP area. - OTP_OP: u1, - reserved29: u4, - /// Flash memory operation code - CODE_OP: packed union { - raw: u3, - value: CODE_OP, - }, - }), - /// FLASH option control register - OPTCR: mmio.Mmio(packed struct(u32) { - /// FLASH_OPTCR lock option configuration bit The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset. It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change. - OPTLOCK: u1, - /// Option byte start change option configuration bit OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It’s set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It’s reseted at the same time as BSY bit. The user application cannot modify any FLASH_XXX_PRG embedded Flash memory register until the option change operation has been completed. Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in non-volatile memory. - OPTSTRT: u1, - reserved31: u29, - /// Bank swapping option configuration bit SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR. - SWAP_BANK: u1, - }), - /// FLASH non-secure status register - NSSR: mmio.Mmio(packed struct(u32) { - /// busy flag BSY flag indicates that a Flash memory is busy by an operation (write, erase, option byte change). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs. - BSY: u1, - /// write buffer not empty flag WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_NSCR the embedded Flash memory detects an error that involves data loss This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. - WBNE: u1, - reserved3: u1, - /// data buffer not empty flag DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free. - DBNE: u1, - reserved16: u12, - /// end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register. - EOP: u1, - /// write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR. - WRPERR: u1, - /// programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR. - PGSERR: u1, - /// strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR. - STRBERR: u1, - /// inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears INCERR. - INCERR: u1, - reserved23: u2, - /// Option byte change error flag OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1. Writing 1 to CLR_OPTCHANGEERR of register FLASH_CCR clears OPTCHANGEERR. Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set. - OPTCHANGEERR: u1, - padding: u8, - }), - /// FLASH secure status register - SECSR: mmio.Mmio(packed struct(u32) { - /// busy flag BSY flag indicates that a FLASH memory is busy by an operation (write, erase, option byte change, OBK operations, PUF operation). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs. - SECBSY: u1, - /// write buffer not empty flag WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_SECCR the embedded Flash memory detects an error that involves data loss This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. - SECWBNE: u1, - reserved3: u1, - /// data buffer not empty flag DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free. - SECDBNE: u1, - reserved16: u12, - /// end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register. - SECEOP: u1, - /// write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR. - SECWRPERR: u1, - /// programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR. - SECPGSERR: u1, - /// strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR. - SECSTRBERR: u1, - /// inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR. - SECINCERR: u1, - padding: u11, - }), - /// FLASH Non Secure control register - NSCR: mmio.Mmio(packed struct(u32) { - /// configuration lock bit This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change. - LOCK: u1, - /// programming control bit PG can be programmed only when LOCK is cleared to 0. PG allows programming in Bank1 and Bank2. - PG: u1, - /// sector erase request Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. - SER: u1, - /// erase request Setting BER bit to 1 requests a bank erase operation (user Flash memory only). BER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. Note: Write protection error is triggered when a bank erase is required and some sectors are protected. - BER: u1, - /// write forcing control bit FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. The embedded Flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively). Since there is just one write buffer, FW can force a write in bank1 or bank2. - FW: u1, - /// erase start control bit STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software. - STRT: u1, - /// sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0. ... - SNB: u3, - reserved15: u6, - /// Mass erase request Setting MER bit to 1 requests a mass erase operation (user Flash memory only). MER can be programmed only when LOCK is cleared to 0. If BER or SER are both set, a PGSERR is raised. Error is triggered when a mass erase is required and some sectors are protected. - MER: u1, - /// end of operation interrupt control bit Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0. - EOPIE: u1, - /// write protection error interrupt enable bit When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0. - WRPERRIE: u1, - /// programming sequence error interrupt enable bit When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0. - PGSERRIE: u1, - /// strobe error interrupt enable bit When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0. - STRBERRIE: u1, - /// inconsistency error interrupt enable bit When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0. - INCERRIE: u1, - reserved23: u2, - /// Option byte change error interrupt enable bit OPTCHANGEERRIE bit controls if an interrupt has to be generated when an error occurs during an option byte change. This bit can be programmed only when LOCK bit is cleared to 0. - OPTCHANGEERRIE: u1, - reserved31: u7, - /// Bank selector bit BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored. - BKSEL: packed union { + /// Real-time clock + pub const RTC = extern struct { + /// Time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { raw: u1, - value: BKSEL, + value: AMPM, }, + padding: u9, }), - reserved48: [4]u8, - /// FLASH non-secure clear control register - NSCCR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// EOP flag clear bit Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register. - CLR_EOP: u1, - /// WRPERR flag clear bit Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register. - CLR_WRPERR: u1, - /// PGSERR flag clear bit Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register. - CLR_PGSERR: u1, - /// STRBERR flag clear bit Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register. - CLR_STRBERR: u1, - /// INCERR flag clear bit Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register. - CLR_INCERR: u1, - reserved23: u2, - /// Clear the flag corresponding flag in FLASH_NSSR by writing this bit. - CLR_OPTCHANGEERR: u1, + /// Date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, padding: u8, }), - reserved60: [8]u8, - /// FLASH privilege configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// privilege attribute for non secure registers - NSPRIV: packed union { - raw: u1, - value: NSPRIV, - }, - padding: u30, - }), - reserved72: [8]u8, - /// FLASH HDP extension register - HDPEXTR: mmio.Mmio(packed struct(u32) { - /// HDP area extension in 8 Kbytes sectors in Bank1. Extension is added after the HDP1_END sector. - HDP1_EXT: u3, - reserved16: u13, - /// HDP area extension in 8 Kbytes sectors in Bank2. Extension is added after the HDP2_END sector. - HDP2_EXT: u3, - padding: u13, - }), - reserved80: [4]u8, - /// FLASH option status register - OPTSR_CUR: mmio.Mmio(packed struct(u32) { - /// Brownout level option status bit These bits reflects the power level that generates a system reset. - BOR_LEV: packed union { - raw: u2, - value: OPTSR_BOR_LEV, - }, - /// Brownout high enable status bit - BORH_EN: u1, - /// IWDG control mode option status bit - IWDG_SW: packed union { - raw: u1, - value: OPTSR_IWDG_SW, - }, - /// WWDG control mode option status bit - WWDG_SW: packed union { - raw: u1, - value: OPTSR_WWDG_SW, - }, - /// Core domain Shutdown entry reset option status bit - NRST_SHDW: packed union { - raw: u1, - value: OPTSR_NRST_SHDW, - }, - /// Core domain Stop entry reset option status bit - NRST_STOP: packed union { - raw: u1, - value: OPTSR_NRST_STOP, - }, - /// Core domain Standby entry reset option status bit - NRST_STDBY: packed union { - raw: u1, - value: OPTSR_NRST_STDBY, - }, - /// Life state code (based on Hamming 8,4). - PRODUCT_STATE: packed union { - raw: u8, - value: PRODUCT_STATE, + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WUCKSEL: packed union { + raw: u3, + value: WUCKSEL, }, - /// High-speed IO at low VDD voltage status bit. This bit can be set only with VDD below 2.5 V. - IO_VDD_HSLV: packed union { + /// Timestamp event active edge + TSEDGE: packed union { raw: u1, - value: OPTSR_IO_VDD_HSLV, + value: TSEDGE, }, - /// High-speed IO at low VDDIO2 voltage status bit. This bit can be set only with VDDIO2 below 2.5 V. - IO_VDDIO2_HSLV: packed union { + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + /// Bypass the shadow registers + BYPSHAD: u1, + /// Hour format + FMT: packed union { raw: u1, - value: OPTSR_IO_VDDIO_HSLV, + value: FMT, }, - reserved20: u2, - /// IWDG Stop mode freeze option status bit When set the independent watchdog IWDG is in system Stop mode. - IWDG_STOP: packed union { + reserved8: u1, + /// Alarm enable + ALRE: u1, + reserved10: u1, + /// Wakeup timer enable + WUTE: u1, + /// Timestamp enable + TSE: u1, + /// Alarm interrupt enable + ALRIE: u1, + reserved14: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Timestamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output selection + COSEL: packed union { raw: u1, - value: OPTSR_IWDG_STOP, + value: COSEL, }, - /// IWDG Standby mode freeze option status bit When set the independent watchdog IWDG is frozen in system Standby mode. - IWDG_STDBY: packed union { + /// Output polarity + POL: packed union { raw: u1, - value: OPTSR_IWDG_STDBY, + value: POL, }, - reserved31: u9, - /// Bank swapping option status bit SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset. - SWAP_BANK: u1, - }), - /// FLASH option status register - OPTSR_PRG: mmio.Mmio(packed struct(u32) { - /// Brownout level option status bit These bits reflects the power level that generates a system reset. - BOR_LEV: packed union { + /// Output selection + OSEL: packed union { raw: u2, - value: OPTSR_BOR_LEV, - }, - /// Brownout high enable status bit - BORH_EN: u1, - /// IWDG control mode option status bit - IWDG_SW: packed union { - raw: u1, - value: OPTSR_IWDG_SW, - }, - /// WWDG control mode option status bit - WWDG_SW: packed union { - raw: u1, - value: OPTSR_WWDG_SW, + value: OSEL, }, - /// Core domain Shutdown entry reset option status bit - NRST_SHDW: packed union { + /// Calibration output enable + COE: u1, + /// Timestamp on internal event enable + ITSE: u1, + padding: u7, + }), + /// Initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm write enabled + ALRWF: u1, + reserved2: u1, + /// Wakeup timer write enabled + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Enter Initialization mode + INIT: u1, + /// Alarm flag + ALRF: u1, + reserved10: u1, + /// Wakeup timer flag + WUTF: u1, + /// Timestamp flag + TSF: u1, + /// Timestamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMPF: u1, + reserved16: u2, + /// Recalibration pending flag + RECALPF: packed union { raw: u1, - value: OPTSR_NRST_SHDW, + value: RECALPF, }, - /// Core domain Stop entry reset option status bit - NRST_STOP: packed union { + padding: u15, + }), + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, + }), + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + padding: u16, + }), + reserved28: [4]u8, + /// Alarm register + ALRMR: [2]mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm seconds mask + MSK1: packed union { raw: u1, - value: OPTSR_NRST_STOP, + value: ALRMR_MSK, }, - /// Core domain Standby entry reset option status bit - NRST_STDBY: packed union { + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm minutes mask + MSK2: packed union { raw: u1, - value: OPTSR_NRST_STDBY, - }, - /// Life state code (based on Hamming 8,4). - PRODUCT_STATE: packed union { - raw: u8, - value: PRODUCT_STATE, + value: ALRMR_MSK, }, - /// High-speed IO at low VDD voltage status bit. This bit can be set only with VDD below 2.5 V. - IO_VDD_HSLV: packed union { + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { raw: u1, - value: OPTSR_IO_VDD_HSLV, + value: ALRMR_PM, }, - /// High-speed IO at low VDDIO2 voltage status bit. This bit can be set only with VDDIO2 below 2.5 V. - IO_VDDIO2_HSLV: packed union { + /// Alarm hours mask + MSK3: packed union { raw: u1, - value: OPTSR_IO_VDDIO_HSLV, + value: ALRMR_MSK, }, - reserved20: u2, - /// IWDG Stop mode freeze option status bit When set the independent watchdog IWDG is in system Stop mode. - IWDG_STOP: packed union { + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { raw: u1, - value: OPTSR_IWDG_STOP, + value: ALRMR_WDSEL, }, - /// IWDG Standby mode freeze option status bit When set the independent watchdog IWDG is frozen in system Standby mode. - IWDG_STDBY: packed union { + /// Alarm date mask + MSK4: packed union { raw: u1, - value: OPTSR_IWDG_STDBY, + value: ALRMR_MSK, }, - reserved31: u9, - /// Bank swapping option status bit SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset. - SWAP_BANK: u1, }), - reserved112: [24]u8, - /// FLASH option status register 2 - OPTSR2_CUR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// SRAM2 erase when system reset - SRAM2_RST: u1, - /// Backup RAM ECC detection and correction disable - BKPRAM_ECC: packed union { + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, + padding: u24, + }), + /// Sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// Shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, + }), + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { raw: u1, - value: OPTSR_BKPRAM_ECC, + value: AMPM, }, - reserved6: u1, - /// SRAM2 ECC detection and correction disable - SRAM2_ECC: packed union { + padding: u9, + }), + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding: u16, + }), + /// Timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// Calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved13: u4, + /// Use a 16-second calibration cycle period + CALW16: packed union { raw: u1, - value: OPTSR_SRAM_ECC, + value: CALW16, }, - reserved9: u2, - /// SRAM1 erase upon system reset - SRAM1_RST: u1, - /// SRAM1 ECC detection and correction disable - SRAM1_ECC: packed union { + /// Use an 8-second calibration cycle period + CALW8: packed union { raw: u1, - value: OPTSR_SRAM_ECC, + value: CALW8, }, - padding: u21, - }), - /// FLASH option status register 2 - OPTSR2_PRG: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// SRAM2 erase when system reset - SRAM2_RST: u1, - /// Backup RAM ECC detection and correction disable - BKPRAM_ECC: packed union { + /// Increase frequency of RTC by 488.5 ppm + CALP: packed union { raw: u1, - value: OPTSR_BKPRAM_ECC, + value: CALP, }, - reserved6: u1, - /// SRAM2 ECC detection and correction disable - SRAM2_ECC: packed union { + padding: u16, + }), + /// Tamper configuration register + TAMPCR: mmio.Mmio(packed struct(u32) { + /// Tamper detection enable + TAMPE: u1, + /// Active level for tamper + TAMPTRG: packed union { raw: u1, - value: OPTSR_SRAM_ECC, + value: TAMPTRG, }, - reserved9: u2, - /// SRAM1 erase upon system reset - SRAM1_RST: u1, - /// SRAM1 ECC detection and correction disable - SRAM1_ECC: packed union { - raw: u1, - value: OPTSR_SRAM_ECC, + /// Tamper interrupt enable + TAMPIE: u1, + reserved7: u4, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: packed union { + raw: u3, + value: TAMPFREQ, }, - padding: u21, - }), - reserved128: [8]u8, - /// FLASH non-secure unique boot entry register - NSBOOTR_CUR: mmio.Mmio(packed struct(u32) { - /// A field locking the values of SWAP_BANK, and NSBOOTADD settings. - NSBOOT_LOCK: packed union { - raw: u8, - value: NSBOOTR_NSBOOT_LOCK, + /// Tamper filter count + TAMPFLT: packed union { + raw: u2, + value: TAMPFLT, }, - /// unique boot entry address These bits reflect the UBE address - NSBOOTADD: u24, - }), - /// FLASH non-secure unique boot entry address - NSBOOTR_PRG: mmio.Mmio(packed struct(u32) { - /// A field locking the values of SWAP_BANK, and NSBOOTADD settings. - NSBOOT_LOCK: packed union { - raw: u8, - value: NSBOOTR_NSBOOT_LOCK, + /// Tamper precharge duration + TAMPPRCH: packed union { + raw: u2, + value: TAMPPRCH, }, - /// unique boot entry address These bits reflect the UBE address - NSBOOTADD: u24, - }), - reserved144: [8]u8, - /// FLASH non-secure OTP block lock - OTPBLR_CUR: mmio.Mmio(packed struct(u32) { - /// OTP block lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR. LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked. When one block is locked, it is not possible to remove the write protection. LOCKBL bits can be set if the corresponding bit in FLASH_OTPBLR_CUR is cleared. - LOCKBL: u32, - }), - /// FLASH non-secure OTP block lock - OTPBLR_PRG: mmio.Mmio(packed struct(u32) { - /// OTP block lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR. LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked. When one block is locked, it is not possible to remove the write protection. LOCKBL bits can be set if the corresponding bit in FLASH_OTPBLR_CUR is cleared. - LOCKBL: u32, - }), - reserved192: [40]u8, - /// FLASH privilege register for bank 1 - PRIVBB1R: mmio.Mmio(packed struct(u32) { - /// Privileged / unprivileged 8 Kbytes Flash Bank1 sector attribute (y = 0 to 7) - PRIVBB: packed union { - raw: u8, - value: PRIVBB, + /// Tamper pull-up disable + TAMPPUDIS: packed union { + raw: u1, + value: TAMPPUDIS, }, - padding: u24, - }), - reserved232: [36]u8, - /// FLASH write sector protection for Bank1 - WRPSGN1R_CUR: mmio.Mmio(packed struct(u32) { - /// Bank2 sector protection option status byte Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected) - WRPSG: u8, - padding: u24, - }), - /// FLASH write sector protection for Bank1 - WRPSGN1R_PRG: mmio.Mmio(packed struct(u32) { - /// Bank2 sector protection option status byte Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected) - WRPSG: u8, - padding: u24, - }), - reserved248: [8]u8, - /// FLASH HDP Bank1 register - HDP1R_CUR: mmio.Mmio(packed struct(u32) { - /// HDPL barrier start set in number of 8 Kbytes sectors - HDP1_STRT: u3, - reserved16: u13, - /// HDPL barrier end set in number of 8 Kbytes sectors - HDP1_END: u3, - padding: u13, - }), - /// FLASH HDP Bank1 register - HDP1R_PRG: mmio.Mmio(packed struct(u32) { - /// HDPL barrier start set in number of 8 Kbytes sectors - HDP1_STRT: u3, - reserved16: u13, - /// HDPL barrier end set in number of 8 Kbytes sectors - HDP1_END: u3, + /// Tamper interrupt enable + TAMPXIE: u1, + /// Tamper no erase + TAMPXNOERASE: u1, + /// Tamper mask flag + TAMPXMF: u1, padding: u13, }), - /// FLASH Flash ECC correction register - ECCCORR: mmio.Mmio(packed struct(u32) { - /// ECC error address When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved. The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area). - ADDR_ECC: u16, - reserved22: u6, - /// ECC bank flag for corrected ECC error It indicates which bank is concerned by ECC error - BK_ECC: u1, - /// ECC flag for corrected ECC error in system FLASH It indicates if system Flash memory is concerned by ECC error. - SYSF_ECC: u1, - /// OTP ECC error bit This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield. - OTP_ECC: u1, - /// ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation. - ECCCIE: u1, - reserved30: u4, - /// ECC correction set by hardware when single ECC error has been detected and corrected. Cleared by writing 1. - ECCC: u1, - padding: u1, - }), - /// FLASH ECC detection register - ECCDETR: mmio.Mmio(packed struct(u32) { - /// ECC error address When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved. The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area). - ADDR_ECC: u16, - reserved22: u6, - /// ECC fail bank for double ECC Error It indicates which bank is concerned by ECC error - BK_ECC: u1, - /// ECC fail for double ECC error in system Flash memory It indicates if system Flash memory is concerned by ECC error. - SYSF_ECC: u1, - /// OTP ECC error bit This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bit field. - OTP_ECC: u1, - reserved31: u6, - /// ECC detection set by hardware when two ECC error has been detected. When this bit is set, a NMI is generated. Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors. - ECCD: u1, - }), - /// FLASH ECC data - ECCDR: mmio.Mmio(packed struct(u32) { - /// ECC error data When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit of data (data area, read-only/OTP area), the failing data is read to this register. By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory. - DATA_ECC: u16, - padding: u16, - }), - reserved488: [220]u8, - /// FLASH write sector protection for Bank2 - WRPSGN2R_CUR: mmio.Mmio(packed struct(u32) { - /// Bank2 sector protection option status byte Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected) - WRPSG: u8, - padding: u24, - }), - /// FLASH write sector protection for Bank2 - WRPSGN2R_PRG: mmio.Mmio(packed struct(u32) { - /// Bank2 sector protection option status byte Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected) - WRPSG: u8, - padding: u24, + /// Alarm sub second register + ALRMSSR: [2]mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, }), - reserved504: [8]u8, - /// FLASH HDP Bank2 register - HDP2R_CUR: mmio.Mmio(packed struct(u32) { - /// Bank 2 HDPL barrier start set in number of 8 Kbytes sectors - HDP2_STRT: u3, - reserved16: u13, - /// Bank 2 HDPL barrier end set in number of 8 Kbytes sectors - HDP2_END: u3, - padding: u13, + /// Option register + OR: mmio.Mmio(packed struct(u32) { + /// RTC_ALARM on PC13 output type + RTC_ALARM_TYPE: u1, + /// RTC_OUT remap + RTC_OUT_RMP: u1, + padding: u30, }), - /// FLASH HDP Bank2 register - HDP2R_PRG: mmio.Mmio(packed struct(u32) { - /// Bank 2 HDPL barrier start set in number of 8 Kbytes sectors - HDP2_STRT: u3, - reserved16: u13, - /// Bank 2 HDPL barrier end set in number of 8 Kbytes sectors - HDP2_END: u3, - padding: u13, + /// Backup register + BKPR: [32]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, }), }; }; - pub const syscfg_f4 = struct { - /// System configuration controller - pub const SYSCFG = extern struct { - /// memory remap register - MEMRM: mmio.Mmio(packed struct(u32) { - /// Memory mapping selection - MEM_MODE: u3, - reserved8: u5, - /// Flash bank mode selection - FB_MODE: u1, - reserved10: u1, - /// FMC memory mapping swap - SWP_FMC: u2, - padding: u20, - }), - /// peripheral mode configuration register - PMC: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// ADC1DC2 - ADC1DC2: u1, - /// ADC2DC2 - ADC2DC2: u1, - /// ADC3DC2 - ADC3DC2: u1, - reserved23: u4, - /// Ethernet PHY interface selection - MII_RMII_SEL: u1, - padding: u8, - }), - /// external interrupt configuration register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration - EXTI: u4, - padding: u28, - }), - reserved32: [8]u8, - /// Compensation cell control register - CMPCR: mmio.Mmio(packed struct(u32) { - /// Compensation cell power-down - CMP_PD: u1, - reserved8: u7, - /// READY - READY: u1, - padding: u23, - }), + pub const rtc_v2wb = struct { + pub const ALRMR_MSK = enum(u1) { + /// Alarm set if the date/day match + ToMatch = 0x0, + /// Date/day don’t care in Alarm comparison + NotMatch = 0x1, }; - }; - pub const dbgmcu_wba = struct { - /// Microcontroller debug unit - pub const DBGMCU = extern struct { - /// identity code register - IDCODE: mmio.Mmio(packed struct(u32) { - /// Device ID - DEV_ID: u12, - reserved16: u4, - /// Revision ID - REV_ID: u16, - }), - /// status and configuration register - CR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Allows debug in Stop mode Write access can be protected by PWR_SECCFGR.LPMSEC. The CPU debug and clocks remain active and the HSI oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state. - DBG_STOP: u1, - /// Allows debug in Standby mode Write access can be protected by PWR_SECCFGR.LPMSEC. The CPU debug and clocks remain active and the HSI oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed. - DBG_STANDBY: u1, - reserved16: u13, - /// Device low power mode selected 10x: Standby mode others reserved - LPMS: u3, - /// Device Stop flag - STOPF: u1, - /// Device Standby flag - SBF: u1, - reserved24: u3, - /// CPU Sleep - CS: u1, - /// CPU DeepSleep - CDS: u1, - padding: u6, - }), - /// APB1L peripheral freeze register - APB1LFZR: mmio.Mmio(packed struct(u32) { - /// TIM2 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM2SEC. - DBG_TIM2_STOP: u1, - /// TIM3 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM3SEC. - DBG_TIM3_STOP: u1, - reserved11: u9, - /// WWDG stop in CPU debug Write access can be protected by GTZC_TZSC.WWDGSEC - DBG_WWDG_STOP: u1, - /// IWDG stop in CPU debug Write access can be protected by GTZC_TZSC.IWDGSEC. - DBG_IWDG_STOP: u1, - reserved21: u8, - /// I2C1 SMBUS timeout stop in CPU debug Write access can be protected by GTZC_TZSC.I2C1SEC. - DBG_I2C1_STOP: u1, - padding: u10, - }), - /// APB1H peripheral freeze register - APB1HFZR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// LPTIM2 stop in CPU debug Write access can be protected by GTZC_TZSC.LPTIM2SEC. - DBG_LPTIM2_STOP: u1, - padding: u26, - }), - /// APB2 peripheral freeze register - APB2FZR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM1SEC. - DBG_TIM1_STOP: u1, - reserved17: u5, - /// TIM16 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM16SEC. - DBG_TIM16_STOP: u1, - /// TIM17 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM17SEC. - DBG_TIM17_STOP: u1, - padding: u13, - }), - reserved36: [16]u8, - /// APB7 peripheral freeze register - APB7FZR: mmio.Mmio(packed struct(u32) { - reserved10: u10, - /// I2C3 stop in CPU debug Access can be protected by GTZC_TZSC.I2C3SEC. - DBG_I2C3_STOP: u1, - reserved17: u6, - /// LPTIM1 stop in CPU debug Access can be protected by GTZC_TZSC.LPTIM1SEC. - DBG_LPTIM1_STOP: u1, - reserved30: u12, - /// RTC stop in CPU debug Access can be protected by GTZC_TZSC.TIM17SEC. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. - DBG_RTC_STOP: u1, - padding: u1, - }), - /// AHB1 peripheral freeze register - AHB1FZR: mmio.Mmio(packed struct(u32) { - /// GPDMA 1 channel 0 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC0. - DBG_GPDMA1_CH0_STOP: u1, - /// GPDMA 1 channel 1 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC1. - DBG_GPDMA1_CH1_STOP: u1, - /// GPDMA 1 channel 2 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC2. - DBG_GPDMA1_CH2_STOP: u1, - /// GPDMA 1 channel 3 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC3. - DBG_GPDMA1_CH3_STOP: u1, - /// GPDMA 1 channel 4 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC4. - DBG_GPDMA1_CH4_STOP: u1, - /// GPDMA 1 channel 5 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC5. - DBG_GPDMA1_CH5_STOP: u1, - /// GPDMA 1 channel 6 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC6. - DBG_GPDMA1_CH6_STOP: u1, - /// GPDMA 1 channel 7 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC7. - DBG_GPDMA1_CH7_STOP: u1, - padding: u24, - }), - reserved252: [208]u8, - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Bit n identifies whether access port APn is present in device Bit n�=�0: APn absent Bit n�=�1: APn present - AP_PRESENT: u16, - /// Bit n identifies whether access port APn is open (can be accessed via the debug port) or locked (debug access to the APn is blocked, except for access) Bit n�=�0: APn locked (except for access to DBGMCU) Bit n�=�1: APn enabled - AP_ENABLED: u16, - }), - /// debug host authentication register - DBG_AUTH_HOST: mmio.Mmio(packed struct(u32) { - /// Device authentication key The device specific 64-bit authentication key (OEMn key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory. - AUTH_KEY: u32, - }), - /// debug device authentication register - DBG_AUTH_DEVICE: mmio.Mmio(packed struct(u32) { - /// Device specific ID Device specific ID used for RDP regression. - AUTH_ID: u32, - }), - reserved2012: [1748]u8, - /// part number codification register - PNCR: mmio.Mmio(packed struct(u32) { - /// Part number codification - CODIFICATION: u32, - }), - reserved4048: [2032]u8, - /// CoreSight peripheral identity register 4 - PIDR4: mmio.Mmio(packed struct(u32) { - /// JEP106 continuation code - JEP106CON: u4, - /// Register file size - F4KCOUNT: u4, - padding: u24, - }), - reserved4064: [12]u8, - /// CoreSight peripheral identity register 0 - PIDR0: mmio.Mmio(packed struct(u32) { - /// Part number bits [7:0] - PARTNUM: u8, - padding: u24, - }), - /// CoreSight peripheral identity register 1 - PIDR1: mmio.Mmio(packed struct(u32) { - /// Part number bits [11:8] - PARTNUM: u4, - /// JEP106 identity code bits [3:0] - JEP106ID: u4, - padding: u24, - }), - /// CoreSight peripheral identity register 2 - PIDR2: mmio.Mmio(packed struct(u32) { - /// JEP106 identity code bits [6:4] - JEP106ID: u3, - /// JEDEC assigned value - JEDEC: u1, - /// Component revision number - REVISION: u4, - padding: u24, - }), - /// CoreSight peripheral identity register 3 - PIDR3: mmio.Mmio(packed struct(u32) { - /// Customer modified - CMOD: u4, - /// Metal fix version - REVAND: u4, - padding: u24, - }), - /// CoreSight component identity register 0 - CIDR0: mmio.Mmio(packed struct(u32) { - /// Component ID bits [7:0] - PREAMBLE: u8, - padding: u24, - }), - /// CoreSight peripheral identity register 1 - CIDR1: mmio.Mmio(packed struct(u32) { - /// Component ID bits [11:8] - PREAMBLE: u4, - /// Component ID bits [15:12] - component class - CLASS: u4, - padding: u24, - }), - /// CoreSight component identity register 2 - CIDR2: mmio.Mmio(packed struct(u32) { - /// Component ID bits [23:16] - PREAMBLE: u8, - padding: u24, - }), - /// CoreSight component identity register 3 - CIDR3: mmio.Mmio(packed struct(u32) { - /// Component ID bits [31:24] - PREAMBLE: u8, - padding: u24, - }), + pub const ALRMR_PM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, }; - }; - pub const eth_v1b = struct { - pub const APCS = enum(u1) { - /// MAC passes all incoming frames unmodified - Disabled = 0x0, - /// MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes - Strip = 0x1, + pub const ALRMR_WDSEL = enum(u1) { + /// DU[3:0] represents the date units + DateUnits = 0x0, + /// DU[3:0] represents the week day. DT[1:0] is don’t care + WeekDay = 0x1, }; - pub const BFD = enum(u1) { - /// Address filters pass all received broadcast frames - Enabled = 0x0, - /// Address filters filter all incoming broadcast frames - Disabled = 0x1, + pub const AMPM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, }; - pub const BL = enum(u2) { - /// For retransmission n, wait up to 2^min(n, 10) time slots - BL10 = 0x0, - /// For retransmission n, wait up to 2^min(n, 8) time slots - BL8 = 0x1, - /// For retransmission n, wait up to 2^min(n, 4) time slots - BL4 = 0x2, - /// For retransmission n, wait up to 2^min(n, 1) time slots - BL1 = 0x3, + pub const CALP = enum(u1) { + /// No RTCCLK pulses are added + NoChange = 0x0, + /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + IncreaseFreq = 0x1, }; - pub const CR = enum(u3) { - /// 60-100MHz HCLK/42 - CR_60_100 = 0x0, - /// 100-150 MHz HCLK/62 - CR_100_150 = 0x1, - /// 20-35MHz HCLK/16 - CR_20_35 = 0x2, - /// 35-60MHz HCLK/16 - CR_35_60 = 0x3, - /// 150-168MHz HCLK/102 - CR_150_168 = 0x4, + pub const CALW16 = enum(u1) { + /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + Sixteen_Second = 0x1, _, }; - pub const CSD = enum(u1) { - /// Errors generated due to loss of carrier - Enabled = 0x0, - /// No error generated due to loss of carrier - Disabled = 0x1, + pub const CALW8 = enum(u1) { + /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + Eight_Second = 0x1, + _, }; - pub const CSR = enum(u1) { - /// Counters roll over to zero after reaching the maximum value - Rollover = 0x0, - /// Counters do not roll over to zero after reaching the maximum value - NotRollover = 0x1, + pub const COSEL = enum(u1) { + /// Calibration output is 512 Hz (with default prescaler setting) + CalFreq_512Hz = 0x0, + /// Calibration output is 1 Hz (with default prescaler setting) + CalFreq_1Hz = 0x1, }; - pub const CounterReset = enum(u1) { - /// Reset all counters. Cleared automatically - Reset = 0x1, - _, + pub const FMT = enum(u1) { + /// 24 hour/day format + Twenty_Four_Hour = 0x0, + /// AM/PM hour format + AM_PM = 0x1, }; - pub const DA = enum(u1) { - /// Round-robin with Rx:Tx priority given by PM - RoundRobin = 0x0, - /// Rx has priority over Tx - RxPriority = 0x1, + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Alarm B output enabled + AlarmB = 0x2, + /// Wakeup output enabled + Wakeup = 0x3, }; - pub const DAIF = enum(u1) { - /// Normal filtering of frames - Normal = 0x0, - /// Address check block operates in inverse filtering mode for the DA address comparison - Invert = 0x1, + pub const POL = enum(u1) { + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + Low = 0x1, }; - pub const DM = enum(u1) { - /// MAC operates in half-duplex mode - HalfDuplex = 0x0, - /// MAC operates in full-duplex mode - FullDuplex = 0x1, + pub const RECALPF = enum(u1) { + /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + Pending = 0x1, + _, }; - pub const DMAOMR_SR = enum(u1) { - /// Reception is stopped after transfer of the current frame - Stopped = 0x0, - /// Reception is placed in the Running state - Started = 0x1, + pub const TAMPFLT = enum(u2) { + /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + Immediate = 0x0, + /// Tamper event is activated after 2 consecutive samples at the active level + Samples2 = 0x1, + /// Tamper event is activated after 4 consecutive samples at the active level + Samples4 = 0x2, + /// Tamper event is activated after 8 consecutive samples at the active level + Samples8 = 0x3, }; - pub const DTCEFD = enum(u1) { - /// Drop frames with errors only in the receive checksum offload engine - Enabled = 0x0, - /// Do not drop frames that only have errors in the receive checksum offload engine - Disabled = 0x1, + pub const TAMPFREQ = enum(u3) { + /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + Div32768 = 0x0, + /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + Div16384 = 0x1, + /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + Div8192 = 0x2, + /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + Div4096 = 0x3, + /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + Div2048 = 0x4, + /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + Div1024 = 0x5, + /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + Div512 = 0x6, + /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + Div256 = 0x7, }; - pub const FB = enum(u1) { - /// AHB uses SINGLE and INCR burst transfers - Variable = 0x0, - /// AHB uses only fixed burst transfers - Fixed = 0x1, + pub const TAMPPRCH = enum(u2) { + /// 1 RTCCLK cycle + Cycles1 = 0x0, + /// 2 RTCCLK cycles + Cycles2 = 0x1, + /// 4 RTCCLK cycles + Cycles4 = 0x2, + /// 8 RTCCLK cycles + Cycles8 = 0x3, }; - pub const FCB = enum(u1) { - /// In half duplex only, deasserts back pressure - DisableBackPressure = 0x0, - /// In full duplex, initiate a Pause control frame. In half duplex, assert back pressure - PauseOrBackPressure = 0x1, + pub const TAMPPUDIS = enum(u1) { + /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + Enabled = 0x0, + /// Disable precharge of RTC_TAMPx pins + Disabled = 0x1, }; - pub const FEF = enum(u1) { - /// Rx FIFO drops frames with error status - Drop = 0x0, - /// All frames except runt error frames are forwarded to the DMA - Forward = 0x1, + pub const TAMPTRG = enum(u1) { + /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. + RisingEdge = 0x0, + /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event + FallingEdge = 0x1, }; - pub const FES = enum(u1) { - /// 10 Mbit/s - FES10 = 0x0, - /// 100 Mbit/s - FES100 = 0x1, + pub const TSEDGE = enum(u1) { + /// RTC_TS input rising edge generates a time-stamp event + RisingEdge = 0x0, + /// RTC_TS input falling edge generates a time-stamp event + FallingEdge = 0x1, }; - pub const FPM = enum(u1) { - /// PBL values used as-is - x1 = 0x0, - /// PBL values multiplied by 4 - x4 = 0x1, + pub const WUCKSEL = enum(u3) { + /// RTC/16 clock is selected + Div16 = 0x0, + /// RTC/8 clock is selected + Div8 = 0x1, + /// RTC/4 clock is selected + Div4 = 0x2, + /// RTC/2 clock is selected + Div2 = 0x3, + /// ck_spre (usually 1 Hz) clock is selected + ClockSpare = 0x4, + /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + ClockSpareWithOffset = 0x6, + _, + }; + + /// Real-time clock + pub const RTC = extern struct { + /// Time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, + }, + padding: u9, + }), + /// Date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WUCKSEL: packed union { + raw: u3, + value: WUCKSEL, + }, + /// Timestamp event active edge + TSEDGE: packed union { + raw: u1, + value: TSEDGE, + }, + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + /// Bypass the shadow registers + BYPSHAD: u1, + /// Hour format + FMT: packed union { + raw: u1, + value: FMT, + }, + reserved8: u1, + /// Alarm enable + ALRE: u1, + reserved10: u1, + /// Wakeup timer enable + WUTE: u1, + /// Timestamp enable + TSE: u1, + /// Alarm interrupt enable + ALRIE: u1, + reserved14: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Timestamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output selection + COSEL: packed union { + raw: u1, + value: COSEL, + }, + /// Output polarity + POL: packed union { + raw: u1, + value: POL, + }, + /// Output selection + OSEL: packed union { + raw: u2, + value: OSEL, + }, + /// Calibration output enable + COE: u1, + /// Timestamp on internal event enable + ITSE: u1, + padding: u7, + }), + /// Initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm write enabled + ALRWF: u1, + reserved2: u1, + /// Wakeup timer write enabled + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Enter Initialization mode + INIT: u1, + /// Alarm flag + ALRF: u1, + reserved10: u1, + /// Wakeup timer flag + WUTF: u1, + /// Timestamp flag + TSF: u1, + /// Timestamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMPF: u1, + reserved16: u2, + /// Recalibration pending flag + RECALPF: packed union { + raw: u1, + value: RECALPF, + }, + /// Internal time-stamp flag + ITSF: u1, + padding: u14, + }), + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, + }), + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + padding: u16, + }), + reserved28: [4]u8, + /// Alarm register + ALRMR: [2]mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm seconds mask + MSK1: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm minutes mask + MSK2: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: ALRMR_PM, + }, + /// Alarm hours mask + MSK3: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { + raw: u1, + value: ALRMR_WDSEL, + }, + /// Alarm date mask + MSK4: packed union { + raw: u1, + value: ALRMR_MSK, + }, + }), + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, + padding: u24, + }), + /// Sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// Shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, + }), + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, + }, + padding: u9, + }), + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding: u16, + }), + /// Timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// Calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved13: u4, + /// Use a 16-second calibration cycle period + CALW16: packed union { + raw: u1, + value: CALW16, + }, + /// Use an 8-second calibration cycle period + CALW8: packed union { + raw: u1, + value: CALW8, + }, + /// Increase frequency of RTC by 488.5 ppm + CALP: packed union { + raw: u1, + value: CALP, + }, + padding: u16, + }), + /// Tamper configuration register + TAMPCR: mmio.Mmio(packed struct(u32) { + /// Tamper detection enable + TAMPE: u1, + /// Active level for tamper + TAMPTRG: packed union { + raw: u1, + value: TAMPTRG, + }, + /// Tamper interrupt enable + TAMPIE: u1, + reserved7: u4, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: packed union { + raw: u3, + value: TAMPFREQ, + }, + /// Tamper filter count + TAMPFLT: packed union { + raw: u2, + value: TAMPFLT, + }, + /// Tamper precharge duration + TAMPPRCH: packed union { + raw: u2, + value: TAMPPRCH, + }, + /// Tamper pull-up disable + TAMPPUDIS: packed union { + raw: u1, + value: TAMPPUDIS, + }, + /// Tamper interrupt enable + TAMPXIE: u1, + /// Tamper no erase + TAMPXNOERASE: u1, + /// Tamper mask flag + TAMPXMF: u1, + padding: u13, + }), + /// Alarm sub second register + ALRMSSR: [2]mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, + }), + /// Option register + OR: mmio.Mmio(packed struct(u32) { + /// RTC_ALARM on PC13 output type + RTC_ALARM_TYPE: u1, + /// RTC_OUT remap + RTC_OUT_RMP: u1, + padding: u30, + }), + /// Backup register + BKPR: [20]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), }; + }; - pub const FTF = enum(u1) { - /// Transmit FIFO controller logic is reset to its default values. Cleared automatically - Flush = 0x1, + pub const rtc_v3 = struct { + pub const ALRF = enum(u1) { + /// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + Match = 0x1, _, }; - pub const FUGF = enum(u1) { - /// Rx FIFO drops all frames of less than 64 bytes - Drop = 0x0, - /// Rx FIFO forwards undersized frames - Forward = 0x1, - }; - - pub const HM = enum(u1) { - /// MAC performs a perfect destination address filtering for multicast frames - Perfect = 0x0, - /// MAC performs destination address filtering of received multicast frames according to the hash table - Hash = 0x1, - }; - - pub const HPF = enum(u1) { - /// If HM or HU is set, only frames that match the Hash filter are passed - HashOnly = 0x0, - /// If HM or HU is set, frames that match either the perfect filter or the hash filter are passed - HashOrPerfect = 0x1, - }; - - pub const HU = enum(u1) { - /// MAC performs a perfect destination address filtering for unicast frames - Perfect = 0x0, - /// MAC performs destination address filtering of received unicast frames according to the hash table - Hash = 0x1, + pub const ALRMF = enum(u1) { + /// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + Match = 0x1, + _, }; - pub const IFG = enum(u3) { - /// 96 bit times - IFG96 = 0x0, - /// 88 bit times - IFG88 = 0x1, - /// 80 bit times - IFG80 = 0x2, - /// 72 bit times - IFG72 = 0x3, - /// 64 bit times - IFG64 = 0x4, - /// 56 bit times - IFG56 = 0x5, - /// 48 bit times - IFG48 = 0x6, - /// 40 bit times - IFG40 = 0x7, + pub const ALRMR_MSK = enum(u1) { + /// Alarm set if the date/day match + ToMatch = 0x0, + /// Date/day don’t care in Alarm comparison + NotMatch = 0x1, }; - pub const IPCO = enum(u1) { - /// IPv4 checksum offload disabled - Disabled = 0x0, - /// IPv4 checksums are checked in received frames - Offload = 0x1, + pub const ALRMR_PM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, }; - pub const JD = enum(u1) { - /// Jabber enabled, transmit frames up to 2048 bytes - Enabled = 0x0, - /// Jabber disabled, transmit frames up to 16384 bytes - Disabled = 0x1, + pub const ALRMR_WDSEL = enum(u1) { + /// DU[3:0] represents the date units + DateUnits = 0x0, + /// DU[3:0] represents the week day. DT[1:0] is don’t care. + WeekDay = 0x1, }; - pub const LM = enum(u1) { - /// Normal mode - Normal = 0x0, - /// MAC operates in loopback mode at the MII - Loopback = 0x1, + pub const ALRMSSR_SSCLR = enum(u1) { + /// The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running + FreeRunning = 0x0, + /// The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0] + ALRMBINR = 0x1, }; - pub const MACAHR_SA = enum(u1) { - /// This address is used for comparison with DA fields of the received frame - Destination = 0x0, - /// This address is used for comparison with SA fields of received frames - Source = 0x1, + pub const AMPM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, }; - pub const MB = enum(u1) { - /// Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below - Normal = 0x0, - /// If FB is low, start all bursts greater than 16 with INCR (undefined burst) - Mixed = 0x1, + pub const BCDU = enum(u3) { + /// 1s increment each time SS[7:0]=0 + Bit7 = 0x0, + /// 1s increment each time SS[8:0]=0 + Bit8 = 0x1, + /// 1s increment each time SS[9:0]=0 + Bit9 = 0x2, + /// 1s increment each time SS[10:0]=0 + Bit10 = 0x3, + /// 1s increment each time SS[11:0]=0 + Bit11 = 0x4, + /// 1s increment each time SS[12:0]=0 + Bit12 = 0x5, + /// 1s increment each time SS[13:0]=0 + Bit13 = 0x6, + /// 1s increment each time SS[14:0]=0 + Bit14 = 0x7, }; - pub const MB_progress = enum(u1) { - /// This bit is set to 1 by the application to indicate that a read or write access is in progress - Busy = 0x1, - _, + pub const BIN = enum(u2) { + /// Free running BCD calendar mode (Binary mode disabled) + BCD = 0x0, + /// Free running Binary mode (BCD mode disabled) + Binary = 0x1, + /// Free running BCD calendar and Binary modes + BinBCD = 0x2, + /// Free running BCD calendar and Binary modes + BinBCD2 = 0x3, }; - pub const MCFHP = enum(u1) { - /// When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0 - AlmostHalf = 0x0, - /// When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0 - AlmostFull = 0x1, + pub const CALP = enum(u1) { + /// No RTCCLK pulses are added + NoChange = 0x0, + /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + IncreaseFreq = 0x1, }; - pub const MCP = enum(u1) { - /// MMC counters will be preset to almost full or almost half. Cleared automatically - Preset = 0x1, + pub const CALRF = enum(u1) { + /// Clear interrupt flag by writing 1 + Clear = 0x1, _, }; - pub const MW = enum(u1) { - /// Read operation - Read = 0x0, - /// Write operation - Write = 0x1, - }; - - pub const PBL = enum(u6) { - /// Maximum of 1 beat per DMA transaction - PBL1 = 0x1, - /// Maximum of 2 beats per DMA transaction - PBL2 = 0x2, - /// Maximum of 4 beats per DMA transaction - PBL4 = 0x4, - /// Maximum of 8 beats per DMA transaction - PBL8 = 0x8, - /// Maximum of 16 beats per DMA transaction - PBL16 = 0x10, - /// Maximum of 32 beats per DMA transaction - PBL32 = 0x20, + pub const CALW16 = enum(u1) { + /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + SixteenSeconds = 0x1, _, }; - pub const PCF = enum(u2) { - /// MAC prevents all control frames from reaching the application - PreventAll = 0x0, - /// MAC forwards all control frames to application except Pause - ForwardAllExceptPause = 0x1, - /// MAC forwards all control frames to application even if they fail the address filter - ForwardAll = 0x2, - /// MAC forwards control frames that pass the address filter - ForwardAllFiltered = 0x3, - }; - - pub const PD = enum(u1) { - /// All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received - Enabled = 0x1, + pub const CALW8 = enum(u1) { + /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + EightSeconds = 0x1, _, }; - pub const PLT = enum(u2) { - /// Pause time minus 4 slot times - PLT4 = 0x0, - /// Pause time minus 28 slot times - PLT28 = 0x1, - /// Pause time minus 144 slot times - PLT144 = 0x2, - /// Pause time minus 256 slot times - PLT256 = 0x3, - }; - - pub const PMTIM = enum(u1) { - /// PMT Status interrupt generation enabled - Unmasked = 0x0, - /// PMT Status interrupt generation disabled - Masked = 0x1, - }; - - pub const PriorityRxOverTx = enum(u2) { - /// RxDMA priority over TxDMA is 1:1 - OneToOne = 0x0, - /// RxDMA priority over TxDMA is 2:1 - TwoToOne = 0x1, - /// RxDMA priority over TxDMA is 3:1 - ThreeToOne = 0x2, - /// RxDMA priority over TxDMA is 4:1 - FourToOne = 0x3, + pub const COSEL = enum(u1) { + /// Calibration output is 512 Hz (with default prescaler setting) + CalFreq_512Hz = 0x0, + /// Calibration output is 1 Hz (with default prescaler setting) + CalFreq_1Hz = 0x1, }; - pub const RD = enum(u1) { - /// MAC attempts retries based on the settings of BL - Enabled = 0x0, - /// MAC attempts only 1 transmission - Disabled = 0x1, + pub const FMT = enum(u1) { + /// 24 hour/day format + TwentyFourHour = 0x0, + /// AM/PM hour format + AmPm = 0x1, }; - pub const RDP = enum(u6) { - /// 1 beat per RxDMA transaction - RDP1 = 0x1, - /// 2 beats per RxDMA transaction - RDP2 = 0x2, - /// 4 beats per RxDMA transaction - RDP4 = 0x4, - /// 8 beats per RxDMA transaction - RDP8 = 0x8, - /// 16 beats per RxDMA transaction - RDP16 = 0x10, - /// 32 beats per RxDMA transaction - RDP32 = 0x20, + pub const ITSF = enum(u1) { + /// This flag is set by hardware when a timestamp on the internal event occurs + TimestampEvent = 0x1, _, }; - pub const RFAEM = enum(u1) { - /// Received-alignment-error counter half-full interrupt enabled - Unmasked = 0x0, - /// Received-alignment-error counter half-full interrupt disabled - Masked = 0x1, - }; - - pub const RFCEM = enum(u1) { - /// Received-crc-error counter half-full interrupt enabled - Unmasked = 0x0, - /// Received-crc-error counter half-full interrupt disabled - Masked = 0x1, - }; - - pub const RGUFM = enum(u1) { - /// Received-good-unicast counter half-full interrupt enabled - Unmasked = 0x0, - /// Received-good-unicast counter half-full interrupt disabled - Masked = 0x1, - }; - - pub const ROD = enum(u1) { - /// MAC receives all packets from PHY while transmitting - Enabled = 0x0, - /// MAC disables reception of frames in half-duplex mode - Disabled = 0x1, - }; - - pub const RPD = enum(u32) { - /// Poll the receive descriptor list - Poll = 0x0, + pub const ITSMF = enum(u1) { + /// This flag is set by hardware when a timestamp on the internal event occurs + TimestampEvent = 0x1, _, }; - pub const RPS = enum(u3) { - /// Stopped, reset or Stop Receive command issued - Stopped = 0x0, - /// Running, fetching receive transfer descriptor - RunningFetching = 0x1, - /// Running, waiting for receive packet - RunningWaiting = 0x3, - /// Suspended, receive descriptor unavailable - Suspended = 0x4, - /// Running, writing data to host memory buffer - RunningWriting = 0x7, + pub const KEY = enum(u8) { + /// Activate write protection (any value that is not the keys) + Activate = 0x0, + /// Key 2 + Deactivate2 = 0x53, + /// Key 1 + Deactivate1 = 0xca, _, }; - pub const RSF = enum(u1) { - /// Rx FIFO operates in cut-through mode, subject to RTC bits - CutThrough = 0x0, - /// Frames are read from Rx FIFO after complete frame has been written - StoreForward = 0x1, - }; - - pub const RTC = enum(u2) { - /// 64 bytes - RTC64 = 0x0, - /// 32 bytes - RTC32 = 0x1, - /// 96 bytes - RTC96 = 0x2, - /// 128 bytes - RTC128 = 0x3, - }; - - pub const SAIF = enum(u1) { - /// Source address filter operates normally - Normal = 0x0, - /// Source address filter operation inverted - Invert = 0x1, - }; - - pub const ST = enum(u1) { - /// Transmission is placed in the Stopped state - Stopped = 0x0, - /// Transmission is placed in Running state - Started = 0x1, + pub const LPCAL = enum(u1) { + /// Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required + RTCCLK = 0x0, + /// Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode + CkApre = 0x1, }; - pub const TGFM = enum(u1) { - /// Transmitted-good counter half-full interrupt enabled - Unmasked = 0x0, - /// Transmitted-good counter half-full interrupt disabled - Masked = 0x1, + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Alarm B output enabled + AlarmB = 0x2, + /// Wakeup output enabled + Wakeup = 0x3, }; - pub const TGFMSCM = enum(u1) { - /// Transmitted-good-multiple-collision half-full interrupt enabled - Unmasked = 0x0, - /// Transmitted-good-multiple-collision half-full interrupt disabled - Masked = 0x1, + pub const POL = enum(u1) { + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + Low = 0x1, }; - pub const TGFSCM = enum(u1) { - /// Transmitted-good-single-collision half-full interrupt enabled - Unmasked = 0x0, - /// Transmitted-good-single-collision half-full interrupt disabled - Masked = 0x1, + pub const RECALPF = enum(u1) { + /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + Pending = 0x1, + _, }; - pub const TPD = enum(u32) { - /// Poll the transmit descriptor list - Poll = 0x0, + pub const SSRUF = enum(u1) { + /// This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + Underflow = 0x1, _, }; - pub const TPS = enum(u3) { - /// Stopped, Reset or Stop Transmit command issued - Stopped = 0x0, - /// Running, fetching transmit transfer descriptor - RunningFetching = 0x1, - /// Running, waiting for status - RunningWaiting = 0x2, - /// Running, reading data from host memory buffer - RunningReading = 0x3, - /// Suspended, transmit descriptor unavailable or transmit buffer underflow - Suspended = 0x6, - /// Running, closing transmit descriptor - Running = 0x7, + pub const SSRUMF = enum(u1) { + /// This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + Underflow = 0x1, _, }; - pub const TSF = enum(u1) { - /// Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold - CutThrough = 0x0, - /// Transmission starts when a full frame is in the Tx FIFO - StoreForward = 0x1, + pub const TAMPALRM_TYPE = enum(u1) { + /// TAMPALRM is push-pull output + PushPull = 0x0, + /// TAMPALRM is open-drain output + OpenDrain = 0x1, }; - pub const TSTIM = enum(u1) { - /// Time stamp interrupt generation enabled - Unmasked = 0x0, - /// Time stamp interrupt generation disabled - Masked = 0x1, + pub const TSEDGE = enum(u1) { + /// RTC_TS input rising edge generates a time-stamp event + RisingEdge = 0x0, + /// RTC_TS input falling edge generates a time-stamp event + FallingEdge = 0x1, }; - pub const TTC = enum(u3) { - /// 64 bytes - TTC64 = 0x0, - /// 128 bytes - TTC128 = 0x1, - /// 192 bytes - TTC192 = 0x2, - /// 256 bytes - TTC256 = 0x3, - /// 40 bytes - TTC40 = 0x4, - /// 32 bytes - TTC32 = 0x5, - /// 24 bytes - TTC24 = 0x6, - /// 16 bytes - TTC16 = 0x7, + pub const TSF = enum(u1) { + /// This flag is set by hardware when a time-stamp event occurs + TimestampEvent = 0x1, + _, }; - pub const USP = enum(u1) { - /// PBL value used for both Rx and Tx DMA - Combined = 0x0, - /// RxDMA uses RDP value, TxDMA uses PBL value - Separate = 0x1, + pub const TSMF = enum(u1) { + /// This flag is set by hardware when a time-stamp event occurs + TimestampEvent = 0x1, + _, }; - pub const VLANTC = enum(u1) { - /// Full 16 bit VLAN identifiers are used for comparison and filtering - VLANTC16 = 0x0, - /// 12 bit VLAN identifies are used for comparison and filtering - VLANTC12 = 0x1, + pub const TSOVF = enum(u1) { + /// This flag is set by hardware when a time-stamp event occurs while TSF is already set + Overflow = 0x1, + _, }; - pub const WD = enum(u1) { - /// Watchdog enabled, receive frames limited to 2048 bytes - Enabled = 0x0, - /// Watchdog disabled, receive frames may be up to to 16384 bytes - Disabled = 0x1, + pub const TSOVMF = enum(u1) { + /// This flag is set by hardware when a time-stamp event occurs while TSF is already set + Overflow = 0x1, + _, }; - pub const WFFRPR = enum(u1) { - /// Reset wakeup frame filter register point to 0b000. Automatically cleared - Reset = 0x1, + pub const WUCKSEL = enum(u3) { + /// RTC/16 clock is selected + Div16 = 0x0, + /// RTC/8 clock is selected + Div8 = 0x1, + /// RTC/4 clock is selected + Div4 = 0x2, + /// RTC/2 clock is selected + Div2 = 0x3, + /// ck_spre (usually 1 Hz) clock is selected + ClockSpare = 0x4, + /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + ClockSpareWithOffset = 0x6, _, }; - pub const ZQPD = enum(u1) { - /// Normal operation with automatic zero-quanta pause control frame generation - Enabled = 0x0, - /// Automatic generation of zero-quanta pause control frames is disabled - Disabled = 0x1, + pub const WUTF = enum(u1) { + /// This flag is set by hardware when the wakeup auto-reload counter reaches 0 + Zero = 0x1, + _, }; - /// Ethernet Peripheral - pub const ETH = extern struct { - /// Ethernet: media access control (MAC) - ETHERNET_MAC: u32, - reserved1792: [1788]u8, - /// Ethernet: Precision Time Protocol (PTP) - ETHERNET_PTP: u32, - reserved4096: [2300]u8, - /// Ethernet: DMA mode register (DMA) - ETHERNET_DMA: u32, + pub const WUTMF = enum(u1) { + /// This flag is set by hardware when the wakeup auto-reload counter reaches 0 + Zero = 0x1, + _, }; - /// Ethernet: DMA controller operation - pub const ETHERNET_DMA = extern struct { - /// Ethernet DMA bus mode register - DMABMR: mmio.Mmio(packed struct(u32) { - /// Software reset - SR: u1, - /// DMA arbitration - DA: packed union { - raw: u1, - value: DA, - }, - /// Descriptor skip length - DSL: u5, - /// Enhanced descriptor format enable - EDFE: u1, - /// Programmable burst length - PBL: packed union { - raw: u6, - value: PBL, - }, - /// Rx-Tx priority ratio + /// Real-time clock + pub const RTC = extern struct { + /// Time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation PM: packed union { - raw: u2, - value: PriorityRxOverTx, - }, - /// Fixed burst - FB: packed union { - raw: u1, - value: FB, - }, - /// Rx DMA PBL - RDP: packed union { - raw: u6, - value: RDP, - }, - /// Use separate PBL - USP: packed union { - raw: u1, - value: USP, - }, - /// 4xPBL mode - FPM: packed union { - raw: u1, - value: FPM, - }, - /// Address-aligned beats - AAB: u1, - /// Mixed burst - MB: packed union { raw: u1, - value: MB, - }, - padding: u5, - }), - /// Ethernet DMA transmit poll demand register - DMATPDR: mmio.Mmio(packed struct(u32) { - /// Transmit poll demand - TPD: packed union { - raw: u32, - value: TPD, - }, - }), - /// EHERNET DMA receive poll demand register - DMARPDR: mmio.Mmio(packed struct(u32) { - /// Receive poll demand - RPD: packed union { - raw: u32, - value: RPD, + value: AMPM, }, + padding: u9, }), - /// Ethernet DMA receive descriptor list address register - DMARDLAR: mmio.Mmio(packed struct(u32) { - /// Start of receive list - SRL: u32, - }), - /// Ethernet DMA transmit descriptor list address register - DMATDLAR: mmio.Mmio(packed struct(u32) { - /// Start of transmit list - STL: u32, + /// Date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, }), - /// Ethernet DMA status register - DMASR: mmio.Mmio(packed struct(u32) { - /// Transmit status - TS: u1, - /// Transmit process stopped status - TPSS: u1, - /// Transmit buffer unavailable status - TBUS: u1, - /// Transmit jabber timeout status - TJTS: u1, - /// Receive overflow status - ROS: u1, - /// Transmit underflow status - TUS: u1, - /// Receive status - RS: u1, - /// Receive buffer unavailable status - RBUS: u1, - /// Receive process stopped status - RPSS: u1, - /// PWTS - PWTS: u1, - /// Early transmit status - ETS: u1, - reserved13: u2, - /// Fatal bus error status - FBES: u1, - /// Early receive status - ERS: u1, - /// Abnormal interrupt summary - AIS: u1, - /// Normal interrupt summary - NIS: u1, - /// Receive process state - RPS: packed union { - raw: u3, - value: RPS, - }, - /// Transmit process state - TPS: packed union { - raw: u3, - value: TPS, - }, - /// Error bits status - EBS: u3, - reserved27: u1, - /// MMC status - MMCS: u1, - /// PMT status - PMTS: u1, - /// Time stamp trigger status - TSTS: u1, - padding: u2, + /// Sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Synchronous binary counter + SS: u32, }), - /// Ethernet DMA operation mode register - DMAOMR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Start/stop receive - SR: packed union { - raw: u1, - value: DMAOMR_SR, - }, - /// Operate on second frame - OSF: u1, - /// Receive threshold control - RTC: packed union { + /// Initialization control and status register + ICSR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Wakeup timer write enabled + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Enter Initialization mode + INIT: u1, + /// Binary mode + BIN: packed union { raw: u2, - value: RTC, - }, - reserved6: u1, - /// Forward undersized good frames - FUGF: packed union { - raw: u1, - value: FUGF, - }, - /// Forward error frames - FEF: packed union { - raw: u1, - value: FEF, - }, - reserved13: u5, - /// Start/stop transmission - ST: packed union { - raw: u1, - value: ST, + value: BIN, }, - /// Transmit threshold control - TTC: packed union { + /// BCD update + BCDU: packed union { raw: u3, - value: TTC, - }, - reserved20: u3, - /// Flush transmit FIFO - FTF: packed union { - raw: u1, - value: FTF, - }, - /// Transmit store and forward - TSF: packed union { - raw: u1, - value: TSF, - }, - reserved24: u2, - /// Disable flushing of received frames - DFRF: u1, - /// Receive store and forward - RSF: packed union { - raw: u1, - value: RSF, + value: BCDU, }, - /// Dropping of TCP/IP checksum error frames disable - DTCEFD: packed union { + reserved16: u3, + /// Recalibration pending Flag + RECALPF: packed union { raw: u1, - value: DTCEFD, + value: RECALPF, }, - padding: u5, - }), - /// Ethernet DMA interrupt enable register - DMAIER: mmio.Mmio(packed struct(u32) { - /// Transmit interrupt enable - TIE: u1, - /// Transmit process stopped interrupt enable - TPSIE: u1, - /// Transmit buffer unavailable interrupt enable - TBUIE: u1, - /// Transmit jabber timeout interrupt enable - TJTIE: u1, - /// Receive overflow interrupt enable - ROIE: u1, - /// Transmit underflow interrupt enable - TUIE: u1, - /// Receive interrupt enable - RIE: u1, - /// Receive buffer unavailable interrupt enable - RBUIE: u1, - /// Receive process stopped interrupt enable - RPSIE: u1, - /// Receive watchdog timeout interrupt enable - RWTIE: u1, - /// Early transmit interrupt enable - ETIE: u1, - reserved13: u2, - /// Fatal bus error interrupt enable - FBEIE: u1, - /// Early receive interrupt enable - ERIE: u1, - /// Abnormal interrupt summary enable - AISE: u1, - /// Normal interrupt summary enable - NISE: u1, padding: u15, }), - /// Ethernet DMA missed frame and buffer overflow counter register - DMAMFBOCR: mmio.Mmio(packed struct(u32) { - /// Missed frames by the controller - MFC: u16, - /// Overflow bit for missed frame counter - OMFC: u1, - /// Missed frames by the application - MFA: u11, - /// Overflow bit for FIFO overflow counter - OFOC: u1, - padding: u3, - }), - /// Ethernet DMA receive status watchdog timer register - DMARSWTR: mmio.Mmio(packed struct(u32) { - /// Receive status watchdog timer count - RSWTC: u8, - padding: u24, - }), - reserved72: [32]u8, - /// Ethernet DMA current host transmit descriptor register - DMACHTDR: mmio.Mmio(packed struct(u32) { - /// Host transmit descriptor address pointer - HTDAP: u32, - }), - /// Ethernet DMA current host receive descriptor register - DMACHRDR: mmio.Mmio(packed struct(u32) { - /// Host receive descriptor address pointer - HRDAP: u32, - }), - /// Ethernet DMA current host transmit buffer address register - DMACHTBAR: mmio.Mmio(packed struct(u32) { - /// Host transmit buffer address pointer - HTBAP: u32, + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, }), - /// Ethernet DMA current host receive buffer address register - DMACHRBAR: mmio.Mmio(packed struct(u32) { - /// Host receive buffer address pointer - HRBAP: u32, + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + /// Wakeup auto-reload output clear value + WUTOCLR: u16, }), - }; - - /// Ethernet: media access control (MAC) - pub const ETHERNET_MAC = extern struct { - /// Ethernet MAC configuration register - MACCR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// Deferral check - DC: u1, - /// Back-off limit - BL: packed union { - raw: u2, - value: BL, - }, - /// Automatic pad/CRC stripping - APCS: packed union { - raw: u1, - value: APCS, - }, - reserved9: u1, - /// Retry disable - RD: packed union { - raw: u1, - value: RD, - }, - /// IPv4 checksum offload - IPCO: packed union { - raw: u1, - value: IPCO, - }, - /// Duplex mode - DM: packed union { - raw: u1, - value: DM, - }, - /// Loopback mode - LM: packed union { - raw: u1, - value: LM, - }, - /// Receive own disable - ROD: packed union { - raw: u1, - value: ROD, - }, - /// Fast Ethernet speed - FES: packed union { - raw: u1, - value: FES, - }, - reserved16: u1, - /// Carrier sense disable - CSD: packed union { - raw: u1, - value: CSD, - }, - /// Interframe gap - IFG: packed union { + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WUCKSEL: packed union { raw: u3, - value: IFG, - }, - reserved22: u2, - /// Jabber disable - JD: packed union { - raw: u1, - value: JD, - }, - /// Watchdog disable - WD: packed union { - raw: u1, - value: WD, + value: WUCKSEL, }, - reserved25: u1, - /// CRC stripping for type frames - CSTF: u1, - padding: u6, - }), - /// Ethernet MAC frame filter register - MACFFR: mmio.Mmio(packed struct(u32) { - /// Promiscuous mode - PM: u1, - /// Hash unicast - HU: packed union { + /// Timestamp event active edge + TSEDGE: packed union { raw: u1, - value: HU, + value: TSEDGE, }, - /// Hash multicast - HM: packed union { + /// RTC_REFIN reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + /// Bypass the shadow registers + BYPSHAD: u1, + /// Hour format + FMT: packed union { raw: u1, - value: HM, + value: FMT, }, - /// Destination address unique filtering - DAIF: packed union { + /// SSR underflow interrupt enable + SSRUIE: u1, + /// Alarm enable + ALRE: u1, + reserved10: u1, + /// Wakeup timer enable + WUTE: u1, + /// Timestamp enable + TSE: u1, + /// Alarm interrupt enable + ALRAIE: u1, + reserved14: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Timestamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output selection + COSEL: packed union { raw: u1, - value: DAIF, + value: COSEL, }, - /// Pass all multicast - PAM: u1, - /// Broadcast frames disable - BFD: packed union { + /// Output polarity + POL: packed union { raw: u1, - value: BFD, + value: POL, }, - /// Pass control frames - PCF: packed union { + /// Output selection + OSEL: packed union { raw: u2, - value: PCF, + value: OSEL, }, - /// Source address filter - SAF: u1, - /// Hash or perfect filter - HPF: packed union { + /// Calibration output enable + COE: u1, + /// Timestamp on internal event enable + ITSE: u1, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper detection output enable on TAMPALRM + TAMPOE: u1, + reserved29: u2, + /// TAMPALRM pull-up enable + TAMPALRM_PU: u1, + /// TAMPALRM output type + TAMPALRM_TYPE: packed union { raw: u1, - value: HPF, + value: TAMPALRM_TYPE, }, - reserved31: u21, - /// Receive all - RA: u1, - }), - /// Ethernet MAC hash table high register - MACHTHR: mmio.Mmio(packed struct(u32) { - /// Upper 32 bits of hash table - HTH: u32, + /// RTC_OUT2 output enable + OUT2EN: u1, }), - /// Ethernet MAC hash table low register - MACHTLR: mmio.Mmio(packed struct(u32) { - /// Lower 32 bits of hash table - HTL: u32, + reserved36: [8]u8, + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: packed union { + raw: u8, + value: KEY, + }, + padding: u24, }), - /// Ethernet MAC MII address register - MACMIIAR: mmio.Mmio(packed struct(u32) { - /// MII busy - MB: packed union { + /// Calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved12: u3, + /// Calibration low-power mode + LPCAL: packed union { raw: u1, - value: MB_progress, + value: LPCAL, }, - /// MII write - MW: packed union { + /// Use a 16-second calibration cycle period + CALW16: packed union { raw: u1, - value: MW, + value: CALW16, }, - /// Clock range - CR: packed union { - raw: u3, - value: CR, + /// Use an 8-second calibration cycle period + CALW8: packed union { + raw: u1, + value: CALW8, + }, + /// Increase frequency of RTC by 488.5 ppm + CALP: packed union { + raw: u1, + value: CALP, }, - reserved6: u1, - /// MII register - select the desired MII register in the PHY device - MR: u5, - /// PHY address - select which of possible 32 PHYs is being accessed - PA: u5, padding: u16, }), - /// Ethernet MAC MII data register - MACMIIDR: mmio.Mmio(packed struct(u32) { - /// MII data read from/written to the PHY - MD: u16, + /// Shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, + }), + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding: u9, + }), + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, padding: u16, }), - /// Ethernet MAC flow control register - MACFCR: mmio.Mmio(packed struct(u32) { - /// Flow control busy/back pressure activate - FCB: packed union { + /// Timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u32, + }), + reserved64: [4]u8, + /// Alarm register + ALRMR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm A seconds mask + MSK1: packed union { raw: u1, - value: FCB, + value: ALRMR_MSK, }, - /// Transmit flow control enable - TFCE: u1, - /// Receive flow control enable - RFCE: u1, - /// Unicast pause frame detect - UPFD: u1, - /// Pause low threshold - PLT: packed union { - raw: u2, - value: PLT, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm A minutes mask + MSK2: packed union { + raw: u1, + value: ALRMR_MSK, }, - reserved7: u1, - /// Zero-quanta pause disable - ZQPD: packed union { + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { raw: u1, - value: ZQPD, + value: ALRMR_PM, }, - reserved16: u8, - /// Pause time - PT: u16, - }), - /// Ethernet MAC VLAN tag register - MACVLANTR: mmio.Mmio(packed struct(u32) { - /// VLAN tag identifier (for receive frames) - VLANTI: u16, - /// 12-bit VLAN tag comparison - VLANTC: packed union { + /// Alarm A hours mask + MSK3: packed union { raw: u1, - value: VLANTC, + value: ALRMR_MSK, }, - padding: u15, - }), - reserved40: [8]u8, - /// Ethernet MAC remote wakeup frame filter register - MACRWUFFR: u32, - /// Ethernet MAC PMT control and status register - MACPMTCSR: mmio.Mmio(packed struct(u32) { - /// Power down - PD: packed union { + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { raw: u1, - value: PD, + value: ALRMR_WDSEL, }, - /// Magic packet enable - MPE: u1, - /// Wakeup frame enable - WFE: u1, - reserved5: u2, - /// Magic packet received - MPR: u1, - /// Wakeup frame received - WFR: u1, - reserved9: u2, - /// Global unicast - GU: u1, - reserved31: u21, - /// Wakeup frame filter register pointer reset - WFFRPR: packed union { + /// Alarm A date mask + MSK4: packed union { raw: u1, - value: WFFRPR, + value: ALRMR_MSK, }, }), - reserved52: [4]u8, - /// Ethernet MAC debug register - MACDBGR: mmio.Mmio(packed struct(u32) { - /// MAC MII receive protocol engine active - MMRPEA: u1, - /// MAC small FIFO read/write controllers status - MSFRWCS: u2, - reserved4: u1, - /// Rx FIFO write controller active - RFWRA: u1, - /// Rx FIFO read controller status - RFRCS: u2, - reserved8: u1, - /// Rx FIFO fill level - RFFL: u2, - reserved16: u6, - /// MAC MII transmit engine active - MMTEA: u1, - /// MAC transmit frame controller status - MTFCS: u2, - /// MAC transmitter in pause - MTP: u1, - /// Tx FIFO read status - TFRS: u2, - /// Tx FIFO write active - TFWA: u1, - reserved24: u1, - /// Tx FIFO not empty - TFNE: u1, - /// Tx FIFO full - TFF: u1, - padding: u6, - }), - /// Ethernet MAC interrupt status register - MACSR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// PMT status - PMTS: u1, - /// MMC status - MMCS: u1, - /// MMC receive status - MMCRS: u1, - /// MMC transmit status - MMCTS: u1, - reserved9: u2, - /// Time stamp trigger status - TSTS: u1, - padding: u22, - }), - /// Ethernet MAC interrupt mask register - MACIMR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// PMT interrupt mask - PMTIM: packed union { + /// Alarm sub second register + ALRMSSR: mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u6, + reserved31: u1, + /// Clear synchronous counter on alarm (Binary mode only) + SSCLR: packed union { raw: u1, - value: PMTIM, + value: ALRMSSR_SSCLR, }, - reserved9: u5, - /// Time stamp trigger interrupt mask - TSTIM: packed union { + }), + reserved80: [8]u8, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Alarm flag + ALRF: packed union { raw: u1, - value: TSTIM, + value: ALRF, }, - padding: u22, - }), - /// Ethernet MAC address 0 high register - MACA0HR: mmio.Mmio(packed struct(u32) { - /// Ethernet MAC address 0 high - MACA0H: u16, - reserved31: u15, - /// Always 1 - MO: u1, - }), - /// Ethernet MAC address 0 low register - MACA0LR: mmio.Mmio(packed struct(u32) { - /// Ethernet MAC address 0 low - MACA0L: u32, - }), - /// Ethernet MAC address 1/2/3 high register - MACAHR: mmio.Mmio(packed struct(u32) { - /// Ethernet MAC address 1/2/3 high - MACAH: u16, - reserved24: u8, - /// MBC - MBC: u6, - /// SA - SA: packed union { + reserved2: u1, + /// Wakeup timer flag + WUTF: packed union { raw: u1, - value: MACAHR_SA, + value: WUTF, }, - /// AE - AE: u1, - }), - /// Ethernet MAC address 1/2/3 low register - MACALR: mmio.Mmio(packed struct(u32) { - /// Ethernet MAC address 1/2/3 low - MACAL: u32, - }), - reserved256: [176]u8, - /// Ethernet MMC control register - MMCCR: mmio.Mmio(packed struct(u32) { - /// Counter reset - CR: packed union { + /// Timestamp flag + TSF: packed union { raw: u1, - value: CounterReset, + value: TSF, }, - /// Counter stop rollover - CSR: packed union { + /// Timestamp overflow flag + TSOVF: packed union { raw: u1, - value: CSR, + value: TSOVF, }, - /// Reset on read - ROR: u1, - /// MMC counter freeze - MCF: u1, - /// MMC counter preset - MCP: packed union { + /// Internal timestamp flag + ITSF: packed union { raw: u1, - value: MCP, + value: ITSF, }, - /// MMC counter Full-Half preset - MCFHP: packed union { + /// SSR underflow flag + SSRUF: packed union { raw: u1, - value: MCFHP, + value: SSRUF, }, - padding: u26, - }), - /// Ethernet MMC receive interrupt register - MMCRIR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// Received frames CRC error status - RFCES: u1, - /// Received frames alignment error status - RFAES: u1, - reserved17: u10, - /// Received good Unicast frames status - RGUFS: u1, - padding: u14, - }), - /// Ethernet MMC transmit interrupt register - MMCTIR: mmio.Mmio(packed struct(u32) { - reserved14: u14, - /// Transmitted good frames single collision status - TGFSCS: u1, - /// Transmitted good frames more than single collision status - TGFMSCS: u1, - reserved21: u5, - /// Transmitted good frames status - TGFS: u1, - padding: u10, + padding: u25, }), - /// Ethernet MMC receive interrupt mask register - MMCRIMR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// Received frame CRC error mask - RFCEM: packed union { + /// Masked interrupt status register + MISR: mmio.Mmio(packed struct(u32) { + /// Alarm masked flag + ALRMF: packed union { raw: u1, - value: RFCEM, + value: ALRMF, }, - /// Received frames alignment error mask - RFAEM: packed union { + reserved2: u1, + /// Wakeup timer masked flag + WUTMF: packed union { raw: u1, - value: RFAEM, + value: WUTMF, }, - reserved17: u10, - /// Received good Unicast frames mask - RGUFM: packed union { + /// Timestamp masked flag + TSMF: packed union { raw: u1, - value: RGUFM, + value: TSMF, }, - padding: u14, - }), - /// Ethernet MMC transmit interrupt mask register - MMCTIMR: mmio.Mmio(packed struct(u32) { - reserved14: u14, - /// Transmitted good frames single collision mask - TGFSCM: packed union { + /// Timestamp overflow masked flag + TSOVMF: packed union { raw: u1, - value: TGFSCM, + value: TSOVMF, }, - /// Transmitted good frames more than single collision mask - TGFMSCM: packed union { + /// Internal timestamp masked flag + ITSMF: packed union { raw: u1, - value: TGFMSCM, + value: ITSMF, }, - /// Transmitted good frames mask - TGFM: packed union { + /// SSR underflow masked flag + SSRUMF: packed union { raw: u1, - value: TGFM, - }, - padding: u15, - }), - reserved332: [56]u8, - /// Ethernet MMC transmitted good frames after a single collision counter - MMCTGFSCCR: mmio.Mmio(packed struct(u32) { - /// Transmitted good frames single collision counter - TGFSCC: u32, - }), - /// Ethernet MMC transmitted good frames after more than a single collision - MMCTGFMSCCR: mmio.Mmio(packed struct(u32) { - /// TGFMSCC - TGFMSCC: u32, - }), - reserved360: [20]u8, - /// Ethernet MMC transmitted good frames counter register - MMCTGFCR: mmio.Mmio(packed struct(u32) { - /// HTL - TGFC: u32, - }), - reserved404: [40]u8, - /// Ethernet MMC received frames with CRC error counter register - MMCRFCECR: mmio.Mmio(packed struct(u32) { - /// RFCFC - RFCFC: u32, - }), - /// Ethernet MMC received frames with alignment error counter register - MMCRFAECR: mmio.Mmio(packed struct(u32) { - /// RFAEC - RFAEC: u32, - }), - reserved452: [40]u8, - /// MMC received good unicast frames counter register - MMCRGUFCR: mmio.Mmio(packed struct(u32) { - /// RGUFC - RGUFC: u32, - }), - }; - - /// Ethernet: Precision time protocol - pub const ETHERNET_PTP = extern struct { - /// Ethernet PTP time stamp control register - PTPTSCR: mmio.Mmio(packed struct(u32) { - /// TSE - TSE: u1, - /// TSFCU - TSFCU: u1, - /// TSSTI - TSSTI: u1, - /// TSSTU - TSSTU: u1, - /// TSITE - TSITE: u1, - /// TTSARU - TTSARU: u1, - reserved8: u2, - /// TSSARFE - TSSARFE: u1, - /// TSSSR - TSSSR: u1, - /// TSPTPPSV2E - TSPTPPSV2E: u1, - /// TSSPTPOEFE - TSSPTPOEFE: u1, - /// TSSIPV6FE - TSSIPV6FE: u1, - /// TSSIPV4FE - TSSIPV4FE: u1, - /// TSSEME - TSSEME: u1, - /// TSSMRME - TSSMRME: u1, - /// TSCNT - TSCNT: u2, - /// TSPFFMAE - TSPFFMAE: u1, - padding: u13, - }), - /// Ethernet PTP subsecond increment register - PTPSSIR: mmio.Mmio(packed struct(u32) { - /// STSSI - STSSI: u8, - padding: u24, - }), - /// Ethernet PTP time stamp high register - PTPTSHR: mmio.Mmio(packed struct(u32) { - /// STS - STS: u32, - }), - /// Ethernet PTP time stamp low register - PTPTSLR: mmio.Mmio(packed struct(u32) { - /// STSS - STSS: u31, - /// STPNS - STPNS: u1, - }), - /// Ethernet PTP time stamp high update register - PTPTSHUR: mmio.Mmio(packed struct(u32) { - /// TSUS - TSUS: u32, - }), - /// Ethernet PTP time stamp low update register - PTPTSLUR: mmio.Mmio(packed struct(u32) { - /// TSUSS - TSUSS: u31, - /// TSUPNS - TSUPNS: u1, - }), - /// Ethernet PTP time stamp addend register - PTPTSAR: mmio.Mmio(packed struct(u32) { - /// TSA - TSA: u32, - }), - /// Ethernet PTP target time high register - PTPTTHR: mmio.Mmio(packed struct(u32) { - /// 0 - TTSH: u32, - }), - /// Ethernet PTP target time low register - PTPTTLR: mmio.Mmio(packed struct(u32) { - /// TTSL - TTSL: u32, - }), - reserved40: [4]u8, - /// Ethernet PTP time stamp status register - PTPTSSR: mmio.Mmio(packed struct(u32) { - /// TSSO - TSSO: u1, - /// TSSO - TSTTR: u1, - padding: u30, - }), - /// Ethernet PTP PPS control register - PTPPPSCR: mmio.Mmio(packed struct(u32) { - /// TSSO - TSSO: u1, - /// TSTTR - TSTTR: u1, - padding: u30, - }), - }; - }; - - pub const cryp_v1 = struct { - /// Cryptographic processor. - pub const CRYP = extern struct { - /// control register. - CR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Algorithm direction. - ALGODIR: u1, - /// Algorithm mode. - ALGOMODE: u3, - /// Data type selection. - DATATYPE: u2, - /// Key size selection (AES mode only). - KEYSIZE: u2, - reserved14: u4, - /// FIFO flush. - FFLUSH: u1, - /// Cryptographic processor enable. - CRYPEN: u1, - padding: u16, - }), - /// status register. - SR: mmio.Mmio(packed struct(u32) { - /// Input FIFO empty. - IFEM: u1, - /// Input FIFO not full. - IFNF: u1, - /// Output FIFO not empty. - OFNE: u1, - /// Output FIFO full. - OFFU: u1, - /// Busy bit. - BUSY: u1, - padding: u27, - }), - /// data input register. - DIN: u32, - /// data output register. - DOUT: u32, - /// DMA control register. - DMACR: mmio.Mmio(packed struct(u32) { - /// DMA input enable. - DIEN: u1, - /// DMA output enable. - DOEN: u1, - padding: u30, - }), - /// interrupt mask set/clear register. - IMSCR: mmio.Mmio(packed struct(u32) { - /// Input FIFO service interrupt mask. - INIM: u1, - /// Output FIFO service interrupt mask. - OUTIM: u1, - padding: u30, - }), - /// raw interrupt status register. - RISR: mmio.Mmio(packed struct(u32) { - /// Input FIFO service raw interrupt status. - INRIS: u1, - /// Output FIFO service raw interrupt status. - OUTRIS: u1, - padding: u30, - }), - /// masked interrupt status register. - MISR: mmio.Mmio(packed struct(u32) { - /// Input FIFO service masked interrupt status. - INMIS: u1, - /// Output FIFO service masked interrupt status. - OUTMIS: u1, - padding: u30, - }), - /// Cluster KEY%s, containing K?LR, K?RR. - KEY: u32, - reserved64: [28]u8, - /// Cluster INIT%s, containing IV?LR, IV?RR. - INIT: u32, - }; - - /// Cluster INIT%s, containing IV?LR, IV?RR. - pub const INIT = extern struct { - /// initialization vector registers. - IVLR: u32, - /// initialization vector registers. - IVRR: u32, - }; - - /// Cluster KEY%s, containing K?LR, K?RR. - pub const KEY = extern struct { - /// key registers. - KLR: u32, - /// key registers. - KRR: u32, - }; - }; - - pub const flash_g4c4 = struct { - pub const LATENCY = enum(u4) { - /// Zero wait states - WS0 = 0x0, - /// One wait state - WS1 = 0x1, - /// Two wait states - WS2 = 0x2, - /// Three wait states - WS3 = 0x3, - /// Four wait states - WS4 = 0x4, - _, - }; - - pub const NRST_MODE = enum(u2) { - /// Reset pin is in reset input mode only - INPUT_ONLY = 0x1, - /// Reset pin is in GPIO mode only - GPIO = 0x2, - /// Reset pin is in reset input and output mode - INPUT_OUTPUT = 0x3, - _, - }; - - pub const RDP = enum(u8) { - /// Read protection not active - LEVEL_0 = 0xaa, - /// Memories read protection active - LEVEL_1 = 0xbb, - /// Chip read protection active - LEVEL_2 = 0xcc, - _, - }; - - /// Flash - pub const FLASH = extern struct { - /// Access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: packed union { - raw: u4, - value: LATENCY, - }, - reserved8: u4, - /// Prefetch enable - PRFTEN: u1, - /// Instruction cache enable - ICEN: u1, - /// Data cache enable - DCEN: u1, - /// Instruction cache reset - ICRST: u1, - /// Data cache reset - DCRST: u1, - /// Flash Power-down mode during Low-power run mode - RUN_PD: u1, - /// Flash Power-down mode during Low-power sleep mode - SLEEP_PD: u1, - reserved18: u3, - /// Debug software enable - DBG_SWEN: u1, - padding: u13, - }), - /// Power down key register - PDKEYR: u32, - /// Flash key register - KEYR: u32, - /// Option byte key register - OPTKEYR: u32, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved3: u1, - /// Programming error - PROGERR: u1, - /// Write protected error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Size error - SIZERR: u1, - /// Programming sequence error - PGSERR: u1, - /// Fast programming data miss error - MISERR: u1, - /// Fast programming error - FASTERR: u1, - reserved14: u4, - /// PCROP read error - RDERR: u1, - /// Option validity error - OPTVERR: u1, - /// Busy - BSY: u1, - padding: u15, - }), - /// Flash control register - CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Page erase - PER: u1, - /// Bank 1 Mass erase - MER1: u1, - /// Page number - PNB: u7, - reserved16: u6, - /// Start - STRT: u1, - /// Options modification start - OPTSTRT: u1, - /// Fast programming - FSTPG: u1, - reserved24: u5, - /// End of operation interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// PCROP read error interrupt enable - RDERRIE: u1, - /// Force the option byte loading - OBL_LAUNCH: u1, - /// Securable memory area protection enable - SEC_PROT1: u1, - reserved30: u1, - /// Options Lock - OPTLOCK: u1, - /// FLASH_CR Lock - LOCK: u1, - }), - /// Flash ECC register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC fail address - ADDR_ECC: u19, - reserved21: u2, - /// ECC fail for Corrected ECC Error or Double ECC Error in info block - BK_ECC: u1, - /// ECC fail for Corrected ECC Error or Double ECC Error in info block - SYSF_ECC: u1, - reserved24: u1, - /// ECC correction interrupt enable - ECCIE: u1, - reserved28: u3, - /// ECC correction - ECCC2: u1, - /// ECC2 detection - ECCD2: u1, - /// ECC correction - ECCC: u1, - /// ECC detection - ECCD: u1, - }), - reserved32: [4]u8, - /// Flash option register - OPTR: mmio.Mmio(packed struct(u32) { - /// Read protection level - RDP: packed union { - raw: u8, - value: RDP, - }, - /// BOR reset Level - BOR_LEV: u3, - reserved12: u1, - /// nRST_STOP - nRST_STOP: u1, - /// nRST_STDBY - nRST_STDBY: u1, - /// nRST_SHDW - nRST_SHDW: u1, - reserved16: u1, - /// Independent watchdog selection - IDWG_SW: u1, - /// Independent watchdog counter freeze in Stop mode - IWDG_STOP: u1, - /// Independent watchdog counter freeze in Standby mode - IWDG_STDBY: u1, - /// Window watchdog selection - WWDG_SW: u1, - reserved22: u2, - /// PB4 pull-up enable - PB4_PUPEN: u1, - /// Boot configuration - nBOOT1: u1, - /// SRAM2 parity check enable - SRAM2_PE: u1, - /// SRAM2 Erase when system reset - SRAM2_RST: u1, - /// nSWBOOT0 - nSWBOOT0: u1, - /// nBOOT0 option bit - nBOOT0: u1, - /// NRST_MODE - NRST_MODE: packed union { - raw: u2, - value: NRST_MODE, + value: SSRUMF, }, - /// Internal reset holder enable bit - IRHEN: u1, - padding: u1, - }), - /// Flash Bank 1 PCROP Start address register - PCROP1SR: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area start offset - PCROP1_STRT: u15, - padding: u17, - }), - /// Flash Bank 1 PCROP End address register - PCROP1ER: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area end offset - PCROP1_END: u15, - reserved31: u16, - /// PCROP area preserved when RDP level decreased - PCROP_RDP: u1, - }), - /// Flash Bank 1 WRP area A address register - WRP1AR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP first area start offset - WRP1A_STRT: u7, - reserved16: u9, - /// Bank 1 WRP first area A end offset - WRP1A_END: u7, - padding: u9, - }), - /// Flash Bank 1 WRP area B address register - WRP1BR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP second area B end offset - WRP1B_STRT: u7, - reserved16: u9, - /// Bank 1 WRP second area B start offset - WRP1B_END: u7, - padding: u9, - }), - reserved112: [60]u8, - /// securable area bank1 register - SEC1R: mmio.Mmio(packed struct(u32) { - /// SEC_SIZE1 - SEC_SIZE1: u8, - reserved16: u8, - /// used to force boot from user area - BOOT_LOCK: u1, - padding: u15, - }), - }; - }; - - pub const mdios_v1 = struct { - /// Management data input/output slave - pub const MDIOS = extern struct { - /// MDIOS configuration register - CR: mmio.Mmio(packed struct(u32) { - /// Peripheral enable - EN: u1, - /// Register write interrupt enable - WRIE: u1, - /// Register Read Interrupt Enable - RDIE: u1, - /// Error interrupt enable - EIE: u1, - reserved7: u3, - /// Disable Preamble Check - DPC: u1, - /// Slaves's address - PORT_ADDRESS: u5, - padding: u19, - }), - /// MDIOS write flag register - WRFR: mmio.Mmio(packed struct(u32) { - /// Write flags for MDIO registers 0 to 31 - WRF: u32, - }), - /// MDIOS clear write flag register - CWRFR: mmio.Mmio(packed struct(u32) { - /// Clear the write flag - CWRF: u32, - }), - /// MDIOS read flag register - RDFR: mmio.Mmio(packed struct(u32) { - /// Read flags for MDIO registers 0 to 31 - RDF: u32, - }), - /// MDIOS clear read flag register - CRDFR: mmio.Mmio(packed struct(u32) { - /// Clear the read flag - CRDF: u32, - }), - /// MDIOS status register - SR: mmio.Mmio(packed struct(u32) { - /// Preamble error flag - PERF: u1, - /// Start error flag - SERF: u1, - /// Turnaround error flag - TERF: u1, - padding: u29, - }), - /// MDIOS clear flag register - CLRFR: mmio.Mmio(packed struct(u32) { - /// Clear the preamble error flag - CPERF: u1, - /// Clear the start error flag - CSERF: u1, - /// Clear the turnaround error flag - CTERF: u1, - padding: u29, + padding: u25, }), - reserved256: [228]u8, - /// MDIOS input data register %s - DINR: [32]mmio.Mmio(packed struct(u32) { - /// Input data received from MDIO Master during write frames - DIN: u16, - padding: u16, + reserved92: [4]u8, + /// Status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear alarm A flag + CALRF: packed union { + raw: u1, + value: CALRF, + }, + reserved2: u1, + /// Clear wakeup timer flag + CWUTF: packed union { + raw: u1, + value: CALRF, + }, + /// Clear timestamp flag + CTSF: packed union { + raw: u1, + value: CALRF, + }, + /// Clear timestamp overflow flag + CTSOVF: packed union { + raw: u1, + value: CALRF, + }, + /// Clear internal timestamp flag + CITSF: packed union { + raw: u1, + value: CALRF, + }, + /// Clear SSR underflow flag + CSSRUF: packed union { + raw: u1, + value: CALRF, + }, + padding: u25, }), - /// MDIOS output data register %s - DOUTR: [32]mmio.Mmio(packed struct(u32) { - /// Output data sent to MDIO Master during read frames - DOUT: u16, - padding: u16, + reserved112: [16]u8, + /// Alarm binary mode register + ALRBINR: [2]mmio.Mmio(packed struct(u32) { + /// Synchronous counter alarm value in Binary mode + SS: u32, }), }; }; - pub const comp_u5 = struct { - pub const Blanking = enum(u5) { - /// No blanking. - NoBlanking = 0x0, - /// Check data sheet for blanking options - Blank1 = 0x1, - /// Check data sheet for blanking options - Blank2 = 0x2, - /// Check data sheet for blanking options - Blank3 = 0x4, + pub const rtc_v3l5 = struct { + pub const ALRF = enum(u1) { + /// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + Match = 0x1, _, }; - pub const Hysteresis = enum(u2) { - None = 0x0, + pub const ALRMF = enum(u1) { + /// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + Match = 0x1, + _, + }; + + pub const ALRMR_MSK = enum(u1) { + /// Alarm set if the date/day match + ToMatch = 0x0, + /// Date/day don’t care in Alarm comparison + NotMatch = 0x1, + }; + + pub const ALRMR_PM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const ALRMR_WDSEL = enum(u1) { + /// DU[3:0] represents the date units + DateUnits = 0x0, + /// DU[3:0] represents the week day. DT[1:0] is don’t care. + WeekDay = 0x1, + }; + + pub const AMPM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const CALP = enum(u1) { + /// No RTCCLK pulses are added + NoChange = 0x0, + /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + IncreaseFreq = 0x1, + }; + + pub const CALRF = enum(u1) { + /// Clear interrupt flag by writing 1 + Clear = 0x1, + _, + }; + + pub const CALW16 = enum(u1) { + /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + SixteenSeconds = 0x1, + _, + }; + + pub const CALW8 = enum(u1) { + /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + EightSeconds = 0x1, + _, + }; + + pub const COSEL = enum(u1) { + /// Calibration output is 512 Hz (with default prescaler setting) + CalFreq_512Hz = 0x0, + /// Calibration output is 1 Hz (with default prescaler setting) + CalFreq_1Hz = 0x1, + }; + + pub const FMT = enum(u1) { + /// 24 hour/day format + TwentyFourHour = 0x0, + /// AM/PM hour format + AmPm = 0x1, + }; + + pub const ITSF = enum(u1) { + /// This flag is set by hardware when a timestamp on the internal event occurs + TimestampEvent = 0x1, + _, + }; + + pub const ITSMF = enum(u1) { + /// This flag is set by hardware when a timestamp on the internal event occurs + TimestampEvent = 0x1, + _, + }; + + pub const KEY = enum(u8) { + /// Activate write protection (any value that is not the keys) + Activate = 0x0, + /// Key 2 + Deactivate2 = 0x53, + /// Key 1 + Deactivate1 = 0xca, + _, + }; + + pub const LPCAL = enum(u1) { + /// Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required + RTCCLK = 0x0, + /// Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode + CkApre = 0x1, + }; + + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Alarm B output enabled + AlarmB = 0x2, + /// Wakeup output enabled + Wakeup = 0x3, + }; + + pub const POL = enum(u1) { + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) Low = 0x1, - Medium = 0x2, - High = 0x3, }; - pub const INM = enum(u4) { - /// Inverting input set to 1/4 VRef - QuarterVRef = 0x0, - /// Inverting input set to 1/2 VRef - HalfVRef = 0x1, - /// Inverting input set to 3/4 VRef - ThreeQuarterVRef = 0x2, - /// Inverting input set to VRef - VRef = 0x3, - /// Inverting input set to DAC1 output - DAC1 = 0x4, - /// Inverting input set to DAC2 output - DAC2 = 0x5, - /// Inverting input set to IO1 (PB7) - INM1 = 0x6, - /// Inverting input set to IO2 (PB3) - INM2 = 0x7, + pub const RECALPF = enum(u1) { + /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + Pending = 0x1, _, }; - pub const Polarity = enum(u1) { - /// Output is not inverted. - NotInverted = 0x0, - /// Output is inverted. - Inverted = 0x1, + pub const TAMPALRM_TYPE = enum(u1) { + /// TAMPALRM is push-pull output + PushPull = 0x0, + /// TAMPALRM is open-drain output + OpenDrain = 0x1, }; - pub const PowerMode = enum(u2) { - /// High speed / full power. - HighSpeed = 0x0, - /// Medium speed / medium power. - MediumSpeed = 0x1, - /// Very-low speed / ultra-low power. - UltraLow = 0x3, + pub const TSEDGE = enum(u1) { + /// RTC_TS input rising edge generates a time-stamp event + RisingEdge = 0x0, + /// RTC_TS input falling edge generates a time-stamp event + FallingEdge = 0x1, + }; + + pub const TSF = enum(u1) { + /// This flag is set by hardware when a time-stamp event occurs + TimestampEvent = 0x1, _, }; - pub const WindowMode = enum(u1) { - /// Signal selected with INPSEL[2:0] bitfield of this register. - ThisInpsel = 0x0, - /// Signal selected with INPSEL[2:0] bitfield of the other register (required for window mode). - OtherInpsel = 0x1, + pub const TSMF = enum(u1) { + /// This flag is set by hardware when a time-stamp event occurs + TimestampEvent = 0x1, + _, }; - pub const WindowOut = enum(u1) { - /// Comparator 1 value. - COMP1_VALUE = 0x0, - /// Comparator 1 value XOR comparator 2 value (required for window mode). - @"COMP1_VALUE XOR COMP2_VALUE" = 0x1, + pub const TSOVF = enum(u1) { + /// This flag is set by hardware when a time-stamp event occurs while TSF is already set + Overflow = 0x1, + _, }; - /// Comparator. - pub const COMP = extern struct { - /// Comparator control and status register. - CSR: mmio.Mmio(packed struct(u32) { - /// Enable - EN: u1, - reserved4: u3, - /// Input minus selection bits. - INMSEL: packed union { - raw: u4, - value: INM, + pub const TSOVMF = enum(u1) { + /// This flag is set by hardware when a time-stamp event occurs while TSF is already set + Overflow = 0x1, + _, + }; + + pub const WUCKSEL = enum(u3) { + /// RTC/16 clock is selected + Div16 = 0x0, + /// RTC/8 clock is selected + Div8 = 0x1, + /// RTC/4 clock is selected + Div4 = 0x2, + /// RTC/2 clock is selected + Div2 = 0x3, + /// ck_spre (usually 1 Hz) clock is selected + ClockSpare = 0x4, + /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + ClockSpareWithOffset = 0x6, + _, + }; + + pub const WUTF = enum(u1) { + /// This flag is set by hardware when the wakeup auto-reload counter reaches 0 + Zero = 0x1, + _, + }; + + pub const WUTMF = enum(u1) { + /// This flag is set by hardware when the wakeup auto-reload counter reaches 0 + Zero = 0x1, + _, + }; + + /// Real-time clock + pub const RTC = extern struct { + /// Time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, }, - /// Input plus selection bit. - INPSEL: u3, - /// Comparator 1 noninverting input selector for window mode. - WINMODE: packed union { + padding: u9, + }), + /// Date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, + }), + /// Sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Synchronous binary counter + SS: u16, + padding: u16, + }), + /// Initialization control and status register + ICSR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Wakeup timer write flag + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Initialization mode + INIT: u1, + reserved16: u8, + /// Recalibration pending Flag + RECALPF: packed union { raw: u1, - value: WindowMode, + value: RECALPF, }, - reserved14: u2, - /// Comparator 1 output selector. - WINOUT: packed union { + padding: u15, + }), + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, + }), + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + /// Wakeup auto-reload output clear value + WUTOCLR: u16, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WUCKSEL: packed union { + raw: u3, + value: WUCKSEL, + }, + /// Timestamp event active edge + TSEDGE: packed union { raw: u1, - value: WindowOut, + value: TSEDGE, }, - /// Polarity selection bit. - POLARITY: packed union { + /// RTC_REFIN reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + /// Bypass the shadow registers + BYPSHAD: u1, + /// Hour format + FMT: packed union { raw: u1, - value: Polarity, + value: FMT, }, - /// Hysteresis selection bits. - HYST: packed union { - raw: u2, - value: Hysteresis, + reserved8: u1, + /// Alarm enable + ALRE: u1, + reserved10: u1, + /// Wakeup timer enable + WUTE: u1, + /// Timestamp enable + TSE: u1, + /// Alarm interrupt enable + ALRIE: u1, + reserved14: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Timestamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output selection + COSEL: packed union { + raw: u1, + value: COSEL, }, - /// Power Mode. - PWRMODE: packed union { + /// Output polarity + POL: packed union { + raw: u1, + value: POL, + }, + /// Output selection + OSEL: packed union { raw: u2, - value: PowerMode, + value: OSEL, }, - /// Blanking source selection bits. - BLANKSEL: packed union { - raw: u5, - value: Blanking, + /// Calibration output enable + COE: u1, + /// Timestamp on internal event enable + ITSE: u1, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper detection output enable on TAMPALRM + TAMPOE: u1, + reserved29: u2, + /// TAMPALRM pull-up enable + TAMPALRM_PU: u1, + /// TAMPALRM output type + TAMPALRM_TYPE: packed union { + raw: u1, + value: TAMPALRM_TYPE, }, - reserved30: u5, - /// Output status bit. - VALUE: u1, - /// Register lock bit. - LOCK: u1, - }), - }; - }; - - pub const dbgmcu_u5 = struct { - /// MCU debug component - pub const DBGMCU = extern struct { - /// DBGMCU_IDCODE - IDCODE: mmio.Mmio(packed struct(u32) { - /// Device dentification - DEV_ID: u12, - reserved16: u4, - /// Revision - REV_ID: u16, - }), - /// Debug MCU configuration register - CR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Debug Stop mode - DBG_STOP: u1, - /// Debug Standby mode - DBG_STANDBY: u1, - reserved4: u1, - /// Trace pin assignment control - TRACE_IOEN: u1, - /// trace port and clock enable - TRACE_EN: u1, - /// Trace pin assignment control - TRACE_MODE: u2, - padding: u24, - }), - /// Debug MCU APB1L peripheral freeze register - APB1LFZR: mmio.Mmio(packed struct(u32) { - /// TIM2 stop in debug - DBG_TIM2_STOP: u1, - /// TIM3 stop in debug - DBG_TIM3_STOP: u1, - /// TIM4 stop in debug - DBG_TIM4_STOP: u1, - /// TIM5 stop in debug - DBG_TIM5_STOP: u1, - /// TIM6 stop in debug - DBG_TIM6_STOP: u1, - /// TIM7 stop in debug - DBG_TIM7_STOP: u1, - reserved11: u5, - /// Window watchdog counter stop in debug - DBG_WWDG_STOP: u1, - /// Independent watchdog counter stop in debug - DBG_IWDG_STOP: u1, - reserved21: u8, - /// I2C1 SMBUS timeout stop in debug - DBG_I2C1_STOP: u1, - /// I2C2 SMBUS timeout stop in debug - DBG_I2C2_STOP: u1, - padding: u9, - }), - /// Debug MCU APB1H peripheral freeze register - APB1HFZR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// I2C4 stop in debug - DBG_I2C4_STOP: u1, - reserved5: u3, - /// LPTIM2 stop in debug - DBG_LPTIM2_STOP: u1, - padding: u26, - }), - /// Debug MCU APB2 peripheral freeze register - APB2FZR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 counter stopped when core is halted - DBG_TIM1_STOP: u1, - reserved13: u1, - /// TIM8 stop in debug - DBG_TIM8_STOP: u1, - reserved16: u2, - /// TIM15 counter stopped when core is halted - DBG_TIM15_STOP: u1, - /// TIM16 counter stopped when core is halted - DBG_TIM16_STOP: u1, - /// DBG_TIM17_STOP - DBG_TIM17_STOP: u1, - padding: u13, + /// RTC_OUT2 output enable + OUT2EN: u1, }), - /// Debug MCU APB3 peripheral freeze register - APB3FZR: mmio.Mmio(packed struct(u32) { - reserved10: u10, - /// I2C3 stop in debug - DBG_I2C3_STOP: u1, - reserved17: u6, - /// LPTIM1 stop in debug - DBG_LPTIM1_STOP: u1, - /// LPTIM3 stop in debug - DBG_LPTIM3_STOP: u1, - /// LPTIM4 stop in debug - DBG_LPTIM4_STOP: u1, - reserved30: u10, - /// RTC stop in debug - DBG_RTC_STOP: u1, - padding: u1, + /// Privilege mode control register + PRIVCR: mmio.Mmio(packed struct(u32) { + /// ALRAPRIV + ALRPRIV: u1, + reserved2: u1, + /// WUTPRIV + WUTPRIV: u1, + /// TSPRIV + TSPRIV: u1, + reserved13: u9, + /// CALPRIV + CALPRIV: u1, + /// INITPRIV + INITPRIV: u1, + /// PRIV + PRIV: u1, + padding: u16, }), - reserved32: [8]u8, - /// Debug MCU AHB1 peripheral freeze register - AHB1FZR: mmio.Mmio(packed struct(u32) { - /// GPDMA channel 0 stop in debug - DBG_GPDMA0_STOP: u1, - /// GPDMA channel 1 stop in debug - DBG_GPDMA1_STOP: u1, - /// GPDMA channel 2 stop in debug - DBG_GPDMA2_STOP: u1, - /// GPDMA channel 3 stop in debug - DBG_GPDMA3_STOP: u1, - /// GPDMA channel 4 stop in debug - DBG_GPDMA4_STOP: u1, - /// GPDMA channel 5 stop in debug - DBG_GPDMA5_STOP: u1, - /// GPDMA channel 6 stop in debug - DBG_GPDMA6_STOP: u1, - /// GPDMA channel 7 stop in debug - DBG_GPDMA7_STOP: u1, - /// GPDMA channel 8 stop in debug - DBG_GPDMA8_STOP: u1, - /// GPDMA channel 9 stop in debug - DBG_GPDMA9_STOP: u1, - /// GPDMA channel 10 stop in debug - DBG_GPDMA10_STOP: u1, - /// GPDMA channel 11 stop in debug - DBG_GPDMA11_STOP: u1, - /// GPDMA channel 12 stop in debug - DBG_GPDMA12_STOP: u1, - /// GPDMA channel 13 stop in debug - DBG_GPDMA13_STOP: u1, - /// GPDMA channel 14 stop in debug - DBG_GPDMA14_STOP: u1, - /// GPDMA channel 15 stop in debug - DBG_GPDMA15_STOP: u1, + SMCR: mmio.Mmio(packed struct(u32) { + /// Alarm x protection + ALRDPROT: u1, + reserved2: u1, + /// Wakeup timer protection + WUTDPROT: u1, + /// Timestamp protection + TSDPROT: u1, + reserved13: u9, + /// Shift register, daylight saving, calibration and reference clock protection + CALDPROT: u1, + /// Initialization protection + INITDPROT: u1, + /// RTC global protection + DECPROT: u1, padding: u16, }), - reserved40: [4]u8, - /// Debug MCU AHB3 peripheral freeze register - AHB3FZR: mmio.Mmio(packed struct(u32) { - /// LPDMA channel 0 stop in debug - DBG_LPDMA0_STOP: u1, - /// LPDMA channel 1 stop in debug - DBG_LPDMA1_STOP: u1, - /// LPDMA channel 2 stop in debug - DBG_LPDMA2_STOP: u1, - /// LPDMA channel 3 stop in debug - DBG_LPDMA3_STOP: u1, - padding: u28, + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: packed union { + raw: u8, + value: KEY, + }, + padding: u24, }), - reserved252: [208]u8, - /// DBGMCU status register - DBGMCU_SR: mmio.Mmio(packed struct(u32) { - /// Bit n identifies whether access port AP n is present in device Bit n = 0: APn absent Bit n = 1: APn present - AP_PRESENT: u8, - /// DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) Bit n = 0: APn locked Bit n = 1: APn enabled - AP_LOCKED: u8, + /// Calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved12: u3, + /// Calibration low-power mode + LPCAL: packed union { + raw: u1, + value: LPCAL, + }, + /// Use a 16-second calibration cycle period + CALW16: packed union { + raw: u1, + value: CALW16, + }, + /// Use an 8-second calibration cycle period + CALW8: packed union { + raw: u1, + value: CALW8, + }, + /// Increase frequency of RTC by 488.5 ppm + CALP: packed union { + raw: u1, + value: CALP, + }, padding: u16, }), - /// DBGMCU debug host authentication register - DBGMCU_DBG_AUTH_HOST: mmio.Mmio(packed struct(u32) { - /// Device authentication key The device specific 64-bit authentication key (OEM key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory. - AUTH_KEY: u32, - }), - /// DBGMCU debug device authentication register - DBGMCU_DBG_AUTH_DEVICE: mmio.Mmio(packed struct(u32) { - /// Device specific ID Device specific ID used for RDP regression. - AUTH_ID: u32, + /// Shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, }), - reserved4048: [3784]u8, - /// Debug MCU CoreSight peripheral identity register 4 - PIDR4: mmio.Mmio(packed struct(u32) { - /// JEP106 continuation code - JEP106CON: u4, - /// register file size - KCOUNT_4: u4, - padding: u24, + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding: u9, }), - reserved4064: [12]u8, - /// Debug MCU CoreSight peripheral identity register 0 - PIDR0: mmio.Mmio(packed struct(u32) { - /// part number bits [7:0] - PARTNUM: u8, - padding: u24, + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding: u16, }), - /// Debug MCU CoreSight peripheral identity register 1 - PIDR1: mmio.Mmio(packed struct(u32) { - /// part number bits [11:8] - PARTNUM: u4, - /// JEP106 identity code bits [3:0] - JEP106ID: u4, - padding: u24, + /// Timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, }), - /// Debug MCU CoreSight peripheral identity register 2 - PIDR2: mmio.Mmio(packed struct(u32) { - /// JEP106 identity code bits [6:4] - JEP106ID: u3, - /// JEDEC assigned value - JEDEC: u1, - /// component revision number - REVISION: u4, - padding: u24, + reserved64: [4]u8, + /// Alarm register + ALRMR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm A seconds mask + MSK1: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm A minutes mask + MSK2: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: ALRMR_PM, + }, + /// Alarm A hours mask + MSK3: packed union { + raw: u1, + value: ALRMR_MSK, + }, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { + raw: u1, + value: ALRMR_WDSEL, + }, + /// Alarm A date mask + MSK4: packed union { + raw: u1, + value: ALRMR_MSK, + }, }), - /// Debug MCU CoreSight peripheral identity register 3 - PIDR3: mmio.Mmio(packed struct(u32) { - /// customer modified - CMOD: u4, - /// metal fix version - REVAND: u4, - padding: u24, + /// Alarm sub second register + ALRMSSR: mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, }), - /// Debug MCU CoreSight component identity register 0 - CIDR0: mmio.Mmio(packed struct(u32) { - /// component identification bits [7:0] - PREAMBLE: u8, - padding: u24, + reserved80: [8]u8, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Alarm flag + ALRF: packed union { + raw: u1, + value: ALRF, + }, + reserved2: u1, + /// Wakeup timer flag + WUTF: packed union { + raw: u1, + value: WUTF, + }, + /// Timestamp flag + TSF: packed union { + raw: u1, + value: TSF, + }, + /// Timestamp overflow flag + TSOVF: packed union { + raw: u1, + value: TSOVF, + }, + /// Internal timestamp flag + ITSF: packed union { + raw: u1, + value: ITSF, + }, + padding: u26, }), - /// Debug MCU CoreSight component identity register 1 - CIDR1: mmio.Mmio(packed struct(u32) { - /// component identification bits [11:8] - PREAMBLE: u4, - /// component identification bits [15:12] - component class - CLASS: u4, - padding: u24, + /// Masked interrupt status register + MISR: mmio.Mmio(packed struct(u32) { + /// Alarm masked flag + ALRMF: packed union { + raw: u1, + value: ALRMF, + }, + reserved2: u1, + /// Wakeup timer masked flag + WUTMF: packed union { + raw: u1, + value: WUTMF, + }, + /// Timestamp masked flag + TSMF: packed union { + raw: u1, + value: TSMF, + }, + /// Timestamp overflow masked flag + TSOVMF: packed union { + raw: u1, + value: TSOVMF, + }, + /// Internal timestamp masked flag + ITSMF: packed union { + raw: u1, + value: ITSMF, + }, + padding: u26, }), - /// Debug MCU CoreSight component identity register 2 - CIDR2: mmio.Mmio(packed struct(u32) { - /// component identification bits [23:16] - PREAMBLE: u8, - padding: u24, + /// Secure masked interrupt status register + SMISR: mmio.Mmio(packed struct(u32) { + /// Alarm x interrupt secure masked flag + ALRMF: u1, + reserved2: u1, + /// WUTMF + WUTMF: u1, + /// TSMF + TSMF: u1, + /// TSOVMF + TSOVMF: u1, + /// ITSMF + ITSMF: u1, + padding: u26, }), - /// Debug MCU CoreSight component identity register 3 - CIDR3: mmio.Mmio(packed struct(u32) { - /// component identification bits [31:24] - PREAMBLE: u8, - padding: u24, + /// Status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear alarm x flag + CALRF: packed union { + raw: u1, + value: CALRF, + }, + reserved2: u1, + /// Clear wakeup timer flag + CWUTF: packed union { + raw: u1, + value: CALRF, + }, + /// Clear timestamp flag + CTSF: packed union { + raw: u1, + value: CALRF, + }, + /// Clear timestamp overflow flag + CTSOVF: packed union { + raw: u1, + value: CALRF, + }, + /// Clear internal timestamp flag + CITSF: packed union { + raw: u1, + value: CALRF, + }, + padding: u26, }), }; }; - pub const exti_h7 = struct { - /// External interrupt/event controller - pub const EXTI = extern struct { - /// Rising Trigger selection register - RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Falling Trigger selection register - FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Software interrupt event register - SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - reserved128: [116]u8, - /// Interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Event mask register - EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), - /// Pending register - PR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, - }), + pub const rtc_v3u5 = struct { + pub const ALRF = enum(u1) { + /// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + Match = 0x1, + _, + }; + + pub const ALRMF = enum(u1) { + /// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + Match = 0x1, + _, + }; + + pub const ALRMR_MSK = enum(u1) { + /// Alarm set if the date/day match + ToMatch = 0x0, + /// Date/day don’t care in Alarm comparison + NotMatch = 0x1, + }; + + pub const ALRMR_PM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, + }; + + pub const ALRMR_WDSEL = enum(u1) { + /// DU[3:0] represents the date units + DateUnits = 0x0, + /// DU[3:0] represents the week day. DT[1:0] is don’t care. + WeekDay = 0x1, }; - }; - pub const hrtim_v2 = struct { - pub const ACTIVEEFFECT = enum(u1) { - /// Timer event has no effect - NoEffect = 0x0, - /// Timer event forces the output to its active state - SetActive = 0x1, + pub const ALRMSSR_SSCLR = enum(u1) { + /// The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running + FreeRunning = 0x0, + /// The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0] + ALRMBINR = 0x1, }; - pub const BRSTDMA = enum(u2) { - /// Update done independently from the DMA burst transfer completion - Independent = 0x0, - /// Update done when the DMA burst transfer is completed - Completion = 0x1, - /// Update done on master timer roll-over following a DMA burst transfer completion - Rollover = 0x2, - _, + pub const AMPM = enum(u1) { + /// AM or 24-hour format + AM = 0x0, + /// PM + PM = 0x1, }; - pub const CAPTUREEFFECT = enum(u1) { - /// Timer event has no effect - NoEffect = 0x0, - /// Timer event triggers capture - TriggerCapture = 0x1, + pub const BCDU = enum(u3) { + /// 1s increment each time SS[7:0]=0 + Bit7 = 0x0, + /// 1s increment each time SS[8:0]=0 + Bit8 = 0x1, + /// 1s increment each time SS[9:0]=0 + Bit9 = 0x2, + /// 1s increment each time SS[10:0]=0 + Bit10 = 0x3, + /// 1s increment each time SS[11:0]=0 + Bit11 = 0x4, + /// 1s increment each time SS[12:0]=0 + Bit12 = 0x5, + /// 1s increment each time SS[13:0]=0 + Bit13 = 0x6, + /// 1s increment each time SS[14:0]=0 + Bit14 = 0x7, }; - pub const CPPSTAT = enum(u1) { - /// Signal applied on output 1 and output 2 forced inactive - Output1Active = 0x0, - /// Signal applied on output 2 and output 1 forced inactive - Output2Active = 0x1, + pub const BIN = enum(u2) { + /// Free running BCD calendar mode (Binary mode disabled) + BCD = 0x0, + /// Free running Binary mode (BCD mode disabled) + Binary = 0x1, + /// Free running BCD calendar and Binary modes + BinBCD = 0x2, + /// Free running BCD calendar and Binary modes + BinBCD2 = 0x3, }; - pub const DACSYNC = enum(u2) { - /// No DAC trigger generated - Disabled = 0x0, - /// Trigger generated on DACSync1 - DACSync1 = 0x1, - /// Trigger generated on DACSync2 - DACSync2 = 0x2, - /// Trigger generated on DACSync3 - DACSync3 = 0x3, + pub const CALP = enum(u1) { + /// No RTCCLK pulses are added + NoChange = 0x0, + /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + IncreaseFreq = 0x1, }; - pub const DELCMP = enum(u2) { - /// CMP register is always active (standard compare mode) - Standard = 0x0, - /// CMP is recomputed and is active following a capture 1 event - Capture1 = 0x1, - /// CMP is recomputed and is active following a capture 1 event or a Compare 1 match - CaptureX_Compare1 = 0x2, - /// CMP is recomputed and is active following a capture 1 event or a Compare 3 match - CaptureX_Compare3 = 0x3, + pub const CALRF = enum(u1) { + /// Clear interrupt flag by writing 1 + Clear = 0x1, + _, }; - pub const DLYPRT = enum(u3) { - /// Output 1 delayed idle on external event 6 - Output1_EE6 = 0x0, - /// Output 2 delayed idle on external event 6 - Output2_EE6 = 0x1, - /// Output 1 and 2 delayed idle on external event 6 - Output1_2_EE6 = 0x2, - /// Balanced idle on external event 6 - Balanced_EE6 = 0x3, - /// Output 1 delayed idle on external event 7 - Output1_EE7 = 0x4, - /// Output 2 delayed idle on external event 7 - Output2_EE7 = 0x5, - /// Output 1 and 2 delayed idle on external event 7 - Output1_2_EE7 = 0x6, - /// Balanced idle on external event 7 - Balanced_EE7 = 0x7, + pub const CALW16 = enum(u1) { + /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + SixteenSeconds = 0x1, + _, }; - pub const EEFLTR = enum(u4) { - /// No filtering - Disabled = 0x0, - /// Blanking from counter reset/roll-over to Compare 1 - BlankResetToCompare1 = 0x1, - /// Blanking from counter reset/roll-over to Compare 2 - BlankResetToCompare2 = 0x2, - /// Blanking from counter reset/roll-over to Compare 3 - BlankResetToCompare3 = 0x3, - /// Blanking from counter reset/roll-over to Compare 4 - BlankResetToCompare4 = 0x4, - /// Blanking from another timing unit: TIMFLTR1 source - BlankTIMFLTR1 = 0x5, - /// Blanking from another timing unit: TIMFLTR2 source - BlankTIMFLTR2 = 0x6, - /// Blanking from another timing unit: TIMFLTR3 source - BlankTIMFLTR3 = 0x7, - /// Blanking from another timing unit: TIMFLTR4 source - BlankTIMFLTR4 = 0x8, - /// Blanking from another timing unit: TIMFLTR5 source - BlankTIMFLTR5 = 0x9, - /// Blanking from another timing unit: TIMFLTR6 source - BlankTIMFLTR6 = 0xa, - /// Blanking from another timing unit: TIMFLTR7 source - BlankTIMFLTR7 = 0xb, - /// Blanking from another timing unit: TIMFLTR8 source - BlankTIMFLTR8 = 0xc, - /// Windowing from counter reset/roll-over to compare 2 - WindowResetToCompare2 = 0xd, - /// Windowing from counter reset/roll-over to compare 3 - WindowResetToCompare3 = 0xe, - /// Windowing from another timing unit: TIMWIN source - WindowTIMWIN = 0xf, + pub const CALW8 = enum(u1) { + /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + EightSeconds = 0x1, + _, }; - pub const FAULT = enum(u2) { - /// No action: the output is not affected by the fault input and stays in run mode - Disabled = 0x0, - /// Output goes to active state after a fault event - SetActive = 0x1, - /// Output goes to inactive state after a fault event - SetInactive = 0x2, - /// Output goes to high-z state after a fault event - SetHighZ = 0x3, + pub const COSEL = enum(u1) { + /// Calibration output is 512 Hz (with default prescaler setting) + CalFreq_512Hz = 0x0, + /// Calibration output is 1 Hz (with default prescaler setting) + CalFreq_1Hz = 0x1, }; - pub const FLTEN = enum(u1) { - /// Fault input ignored - Ignored = 0x0, - /// Fault input is active and can disable HRTIM outputs - Active = 0x1, + pub const FMT = enum(u1) { + /// 24 hour/day format + TwentyFourHour = 0x0, + /// AM/PM hour format + AmPm = 0x1, }; - pub const INACTIVEEFFECT = enum(u1) { - /// Timer event has no effect - NoEffect = 0x0, - /// Timer event forces the output to its inactive state - SetInactive = 0x1, + pub const ITSF = enum(u1) { + /// This flag is set by hardware when a timestamp on the internal event occurs + TimestampEvent = 0x1, + _, }; - pub const IPPSTAT = enum(u1) { - /// Protection occurred when the output 1 was active and output 2 forced inactive - Output1Active = 0x0, - /// Protection occurred when the output 2 was active and output 1 forced inactive - Output2Active = 0x1, + pub const ITSMF = enum(u1) { + /// This flag is set by hardware when a timestamp on the internal event occurs + TimestampEvent = 0x1, + _, }; - pub const OUTPUTSTATE = enum(u1) { - /// Output is or was inactive - Inactive = 0x0, - /// Output is or was active - Active = 0x1, + pub const KEY = enum(u8) { + /// Activate write protection (any value that is not the keys) + Activate = 0x0, + /// Key 2 + Deactivate2 = 0x53, + /// Key 1 + Deactivate1 = 0xca, + _, + }; + + pub const LPCAL = enum(u1) { + /// Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required + RTCCLK = 0x0, + /// Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode + CkApre = 0x1, + }; + + pub const OSEL = enum(u2) { + /// Output disabled + Disabled = 0x0, + /// Alarm A output enabled + AlarmA = 0x1, + /// Alarm B output enabled + AlarmB = 0x2, + /// Wakeup output enabled + Wakeup = 0x3, }; pub const POL = enum(u1) { - /// Positive polarity (output active high) - ActiveHigh = 0x0, - /// Negative polarity (output active low) - ActiveLow = 0x1, + /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + High = 0x0, + /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + Low = 0x1, }; - pub const RESETEFFECT = enum(u1) { - /// Timer Y compare Z event has no effect - NoEffect = 0x0, - /// Timer X counter is reset upon timer Y compare Z event - ResetCounter = 0x1, + pub const RECALPF = enum(u1) { + /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + Pending = 0x1, + _, }; - pub const SDTF = enum(u1) { - /// Positive deadtime on falling edge - Positive = 0x0, - /// Negative deadtime on falling edge - Negative = 0x1, + pub const SSRUF = enum(u1) { + /// This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + Underflow = 0x1, + _, }; - pub const SDTR = enum(u1) { - /// Positive deadtime on rising edge - Positive = 0x0, - /// Negative deadtime on rising edge - Negative = 0x1, + pub const SSRUMF = enum(u1) { + /// This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + Underflow = 0x1, + _, }; - pub const SYNCIN = enum(u2) { - /// Disabled. HRTIM is not synchronized and runs in standalone mode - Disabled = 0x0, - /// Internal event: the HRTIM is synchronized with the on-chip timer - Internal = 0x2, - /// External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM - External = 0x3, + pub const TAMPALRM_TYPE = enum(u1) { + /// TAMPALRM is push-pull output + PushPull = 0x0, + /// TAMPALRM is open-drain output + OpenDrain = 0x1, + }; + + pub const TSEDGE = enum(u1) { + /// RTC_TS input rising edge generates a time-stamp event + RisingEdge = 0x0, + /// RTC_TS input falling edge generates a time-stamp event + FallingEdge = 0x1, + }; + + pub const TSF = enum(u1) { + /// This flag is set by hardware when a time-stamp event occurs + TimestampEvent = 0x1, _, }; - pub const SYNCOUT = enum(u2) { - /// Disabled - Disabled = 0x0, - /// Positive pulse on SCOUT output (16x f_HRTIM clock cycles) - PositivePulse = 0x2, - /// Negative pulse on SCOUT output (16x f_HRTIM clock cycles) - NegativePulse = 0x3, + pub const TSMF = enum(u1) { + /// This flag is set by hardware when a time-stamp event occurs + TimestampEvent = 0x1, _, }; - pub const SYNCRST = enum(u1) { - /// Synchronization event has no effect on Timer x - Disabled = 0x0, - /// Synchronization event resets Timer x - Reset = 0x1, + pub const TSOVF = enum(u1) { + /// This flag is set by hardware when a time-stamp event occurs while TSF is already set + Overflow = 0x1, + _, }; - pub const SYNCSRC = enum(u2) { - /// Master timer Start - MasterStart = 0x0, - /// Master timer Compare 1 event - MasterCompare1 = 0x1, - /// Timer A start/reset - TimerAStart = 0x2, - /// Timer A Compare 1 event - TimerACompare1 = 0x3, + pub const TSOVMF = enum(u1) { + /// This flag is set by hardware when a time-stamp event occurs while TSF is already set + Overflow = 0x1, + _, }; - pub const SYNCSTRT = enum(u1) { - /// Synchronization event has no effect on Timer x - Disabled = 0x0, - /// Synchronization event starts Timer x - Start = 0x1, + pub const WUCKSEL = enum(u3) { + /// RTC/16 clock is selected + Div16 = 0x0, + /// RTC/8 clock is selected + Div8 = 0x1, + /// RTC/4 clock is selected + Div4 = 0x2, + /// RTC/2 clock is selected + Div2 = 0x3, + /// ck_spre (usually 1 Hz) clock is selected + ClockSpare = 0x4, + /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + ClockSpareWithOffset = 0x6, + _, }; - pub const TIMAISR_DLYPRT = enum(u1) { - /// Not in delayed idle or balanced idle mode - Inactive = 0x0, - /// Delayed idle or balanced idle mode entry - Active = 0x1, + pub const WUTF = enum(u1) { + /// This flag is set by hardware when the wakeup auto-reload counter reaches 0 + Zero = 0x1, + _, }; - pub const UPDGAT = enum(u4) { - /// Update occurs independently from the DMA burst transfer - Independent = 0x0, - /// Update occurs when the DMA burst transfer is completed - DMABurst = 0x1, - /// Update occurs on the update event following DMA burst transfer completion - DMABurst_Update = 0x2, - /// Update occurs on a rising edge of HRTIM update enable input 1 - Input1 = 0x3, - /// Update occurs on a rising edge of HRTIM update enable input 2 - Input2 = 0x4, - /// Update occurs on a rising edge of HRTIM update enable input 3 - Input3 = 0x5, - /// Update occurs on the update event following a rising edge of HRTIM update enable input 1 - Input1_Update = 0x6, - /// Update occurs on the update event following a rising edge of HRTIM update enable input 2 - Input2_Update = 0x7, - /// Update occurs on the update event following a rising edge of HRTIM update enable input 3 - Input3_Update = 0x8, + pub const WUTMF = enum(u1) { + /// This flag is set by hardware when the wakeup auto-reload counter reaches 0 + Zero = 0x1, _, }; - /// High Resolution Timer - pub const HRTIM = extern struct { - /// Master Timer Control Register - MCR: mmio.Mmio(packed struct(u32) { - /// HRTIM Master Clock prescaler - CKPSC: u3, - /// Master Continuous mode - CONT: u1, - /// Master Re-triggerable mode - RETRIG: u1, - /// Half mode enable - HALF: u1, - reserved8: u2, - /// Synchronization input - SYNCIN: packed union { - raw: u2, - value: SYNCIN, - }, - /// Synchronization Resets Master - SYNCRSTM: u1, - /// Synchronization Starts Master - SYNCSTRTM: u1, - /// Synchronization output - SYNCOUT: packed union { - raw: u2, - value: SYNCOUT, - }, - /// Synchronization source - SYNCSRC: packed union { - raw: u2, - value: SYNCSRC, - }, - /// Master Counter enable - MCEN: u1, - /// Timer X counter enable - TCEN: u1, - reserved25: u7, - /// AC Synchronization - DACSYNC: packed union { - raw: u2, - value: DACSYNC, - }, - /// Preload enable - PREEN: u1, - reserved29: u1, - /// Master Timer Repetition update - MREPU: u1, - /// Burst DMA Update - BRSTDMA: packed union { - raw: u2, - value: BRSTDMA, + /// Real-time clock + pub const RTC = extern struct { + /// Time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { + raw: u1, + value: AMPM, }, - }), - /// Master Timer Interrupt Status Register - MISR: mmio.Mmio(packed struct(u32) { - /// Master Compare X Interrupt Flag - MCMP: u1, - reserved4: u3, - /// Master Repetition Interrupt Flag - MREP: u1, - /// Sync Input Interrupt Flag - SYNC: u1, - /// Master Update Interrupt Flag - MUPD: u1, - padding: u25, - }), - /// Master Timer Interrupt Clear Register - MICR: mmio.Mmio(packed struct(u32) { - /// Master Compare X Interrupt flag clear - MCMPC: u1, - reserved4: u3, - /// Repetition Interrupt flag clear - MREPC: u1, - /// Sync Input Interrupt flag clear - SYNCC: u1, - /// Master update Interrupt flag clear - MUPDC: u1, - padding: u25, - }), - /// Master Timer DMA / Interrupt Enable Register - MDIER: mmio.Mmio(packed struct(u32) { - /// Master Compare X Interrupt Enable - MCMPIE: u1, - reserved4: u3, - /// Master Repetition Interrupt Enable - MREPIE: u1, - /// Sync Input Interrupt Enable - SYNCIE: u1, - /// Master Update Interrupt Enable - MUPDIE: u1, - reserved16: u9, - /// Master Compare X DMA request Enable - MCMPDE: u1, - reserved20: u3, - /// Master Repetition DMA request Enable - MREPDE: u1, - /// Sync Input DMA request Enable - SYNCDE: u1, - /// Master Update DMA request Enable - MUPDDE: u1, padding: u9, }), - /// Master Timer Counter Register - MCNTR: mmio.Mmio(packed struct(u32) { - /// Counter value - MCNT: u16, - padding: u16, - }), - /// Master Timer Period Register - MPER: mmio.Mmio(packed struct(u32) { - /// Master Timer Period value - MPER: u16, - padding: u16, - }), - /// Master Timer Repetition Register - MREP: mmio.Mmio(packed struct(u32) { - /// Master Timer Repetition counter value - MREP: u8, - padding: u24, - }), - /// Master Timer Compare X Register - MCMP: mmio.Mmio(packed struct(u32) { - /// Master Timer Compare X value - MCMP: u16, - padding: u16, - }), - reserved128: [96]u8, - /// High Resolution Timer: Timing Unit - TIM: u32, - reserved896: [764]u8, - /// High Resolution Timer: Control Register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Master Update Disable - MUDIS: u1, - /// Timer X Update Disable - TUDIS: u1, - reserved16: u14, - /// ADC Trigger X Update Source - ADUSRC: u3, - padding: u13, - }), - /// High Resolution Timer: Control Register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// Master Timer Software Update - MSWU: u1, - /// Timer X Software Update - TSWU: u1, - reserved8: u6, - /// Master Counter Software Reset - MRST: u1, - /// Timer X Counter Software Reset - TRST: u1, - padding: u22, - }), - /// High Resolution Timer: Interrupt Status Register - ISR: mmio.Mmio(packed struct(u32) { - /// Fault X Interrupt Flag - FLT: u1, - reserved5: u4, - /// System Fault Interrupt Flag - SYSFLT: u1, - reserved16: u10, - /// DLL Ready Interrupt Flag - DLLRDY: u1, - /// Burst Mode Period Interrupt Flag - BMPER: u1, - padding: u14, - }), - /// High Resolution Timer: Interrupt Clear Register - ICR: mmio.Mmio(packed struct(u32) { - /// Fault X Interrupt Flag Clear - FLT: u1, - reserved5: u4, - /// System Fault Interrupt Flag Clear - SYSFLT: u1, - reserved16: u10, - /// DLL Ready Interrupt Flag Clear - DLLRDY: u1, - /// Burst Mode Period Interrupt Flag Clear - BMPER: u1, - padding: u14, - }), - /// High Resolution Timer: Interrupt Enable Register - IER: mmio.Mmio(packed struct(u32) { - /// Fault X Interrupt Flag Enable - FLT: u1, - reserved5: u4, - /// System Fault Interrupt Flag Enable - SYSFLT: u1, - reserved16: u10, - /// DLL Ready Interrupt Flag Enable - DLLRDY: u1, - /// Burst Mode Period Interrupt Flag Enable - BMPER: u1, - padding: u14, - }), - /// High Resolution Timer: Output Enable Register - OENR: mmio.Mmio(packed struct(u32) { - /// Timer X Output Enable - T1OEN: u1, - /// Timer X Complementary Output Enable - T2OEN: u1, - padding: u30, - }), - /// High Resolution Timer: Output Disable Register - ODISR: mmio.Mmio(packed struct(u32) { - /// Timer X Output Disable - T1ODIS: u1, - /// Timer X Complementary Output Disable - T2ODIS: u1, - padding: u30, - }), - /// High Resolution Timer: Output Disable Status Register - ODSR: mmio.Mmio(packed struct(u32) { - /// Timer X Output Disable Status - T1ODIS: u1, - /// Timer X Complementary Output Disable Status - T2ODIS: u1, - padding: u30, - }), - /// High Resolution Timer: Burst Mode Control Register - BMCR: mmio.Mmio(packed struct(u32) { - /// Burst Mode Enable - BME: u1, - /// Burst Mode Operating Mode - BMOM: u1, - /// Burst Mode Clock source - BMCLK: u3, - reserved6: u1, - /// Burst Mode Prescaler - BMPRSC: u3, - reserved10: u1, - /// Burst Mode Preload Enable - BMPREN: u1, - reserved16: u5, - /// Master Timer Burst Mode - MTBM: u1, - /// Timer X Burst Mode - TBM: u1, - reserved31: u13, - BMSTAT: u1, - }), - /// High Resolution Timer: Burst Mode Trigger Register - BMTRGR: mmio.Mmio(packed struct(u32) { - /// Software start - SW: u1, - /// Master reset or roll-over - MSTRST: u1, - /// Master repetition - MSTREP: u1, - /// Master Compare X - MSTCMP: u1, - reserved7: u3, - /// Timer X reset or roll-over - TRST: u1, - /// Timer X repetition - TREP: u1, - /// Timer X compare 1 event - TCMP1: u1, - /// Timer X compare 2 event - TCMP2: u1, - padding: u21, - }), - /// High Resolution Timer: Burst Mode Compare Register - BMCMPR: mmio.Mmio(packed struct(u32) { - /// Burst mode compare value - BMCMP: u16, - padding: u16, - }), - /// High Resolution Timer: Burst Mode Period Register - BMPER: mmio.Mmio(packed struct(u32) { - /// Burst mode period value - BMPER: u16, - padding: u16, - }), - /// High Resolution Timer: External Event Control Register 1 - EECR1: mmio.Mmio(packed struct(u32) { - /// External Event X Source - EESRC: u2, - /// External Event X Polarity - EEPOL: u1, - /// External Event X Sensitivity - EESNS: u2, - /// External Event X Fast Mode - EEFAST: u2, - padding: u25, - }), - /// High Resolution Timer: External Event Control Register 2 - EECR2: mmio.Mmio(packed struct(u32) { - /// External Event X Source - EESRC: u2, - /// External Event X Polarity - EEPOL: u1, - /// External Event X Sensitivity - EESNS: u2, - padding: u27, + /// Date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, }), - /// High Resolution Timer: External Event Control Register 3 - EECR3: mmio.Mmio(packed struct(u32) { - /// External Event X filter - EEF: u3, - reserved30: u27, - /// External Event Sampling Clock Division - EEVSD: u2, + /// Sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Synchronous binary counter + SS: u32, }), - /// High Resolution Timer: ADC Trigger [1, 3] Register - ADC1R: mmio.Mmio(packed struct(u32) { - /// ADC trigger X on Master Compare Y - ADCMC: u1, - reserved4: u3, - /// ADC trigger X on Master Period - ADCMPER: u1, - /// ADC trigger X on External Event Y - ADCEEV: u1, - reserved10: u4, - /// ADC trigger X on Timer Y Compare 2 - ADCTC2: u1, - /// ADC trigger X on Timer Y Compare 3 - ADCTC3: u1, - /// ADC trigger X on Timer Y Compare 3 - ADCTC4: u1, - /// ADC trigger X on Timer Y Period - ADCTPER: u1, - /// ADC trigger X on Timer Y Reset - ADCTRST: u1, - padding: u17, + /// Initialization control and status register + ICSR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Wakeup timer write enabled + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Enter Initialization mode + INIT: u1, + /// Binary mode + BIN: packed union { + raw: u2, + value: BIN, + }, + /// BCD update + BCDU: packed union { + raw: u3, + value: BCDU, + }, + reserved16: u3, + /// Recalibration pending Flag + RECALPF: packed union { + raw: u1, + value: RECALPF, + }, + padding: u15, }), - /// High Resolution Timer: ADC Trigger [2, 4] Register - ADC2R: mmio.Mmio(packed struct(u32) { - /// ADC trigger X on Master Compare Y - ADCMC: u1, - reserved4: u3, - /// ADC trigger X on Master Period - ADCMPER: u1, - /// ADC trigger X on External Event Y - ADCEEV: u1, - reserved10: u4, - /// ADC trigger X on Timer Y Compare 2 - ADCTC2: u1, - reserved12: u1, - /// ADC trigger X on Timer Y Compare 3 - ADCTC4: u1, - /// ADC trigger X on Timer Y Period - ADCTPER: u1, - reserved15: u1, - /// ADC trigger X on Timer Y Compare 3 - ADCTC3: u1, - reserved22: u6, - /// ADC trigger X on Timer Y Reset - ADCTRST: u1, + /// Prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, padding: u9, }), - reserved972: [8]u8, - /// High Resolution Timer: DLL Control Register - DLLCR: mmio.Mmio(packed struct(u32) { - /// DLL Calibration Start - CAL: u1, - /// DLL Calibration Enable - CALEN: u1, - /// DLL Calibration Rate - CALRTE: u2, - padding: u28, - }), - /// High Resolution Timer: Fault Input Register 1 - FLTINR1: mmio.Mmio(packed struct(u32) { - /// Fault X enable - FLTE: u1, - /// Fault X polarity - FLTP: u1, - /// Fault X source - FLTSRC: u1, - /// Fault X filter - FLTF: u4, - /// Fault X Lock - FLTLCK: u1, - padding: u24, - }), - reserved984: [4]u8, - /// High Resolution Timer: Burst DMA Master timer update Register - BDMUPR: mmio.Mmio(packed struct(u32) { - /// MCR register update enable - MCR: u1, - /// MICR register update enable - MICR: u1, - /// MDIER register update enable - MDIER: u1, - /// MCNT register update enable - MCNT: u1, - /// MPER register update enable - MPER: u1, - /// MREP register update enable - MREP: u1, - /// MCMP register X update enable - MCMP: u1, - padding: u25, - }), - /// High Resolution Timer: Burst DMA Timer X update Register - BDTUPR: [5]mmio.Mmio(packed struct(u32) { - /// CR register update enable - CR: u1, - /// ICR register update enable - ICR: u1, - /// DIER register update enable - DIER: u1, - /// CNT register update enable - CNT: u1, - /// PER register update enable - PER: u1, - /// REP register update enable - REP: u1, - /// CMP register X update enable - CMP: u1, - padding: u25, - }), - /// High Resolution Timer: Burst DMA Data Register - BDMADR: mmio.Mmio(packed struct(u32) { - /// Burst DMA Data register - BDMADR: u31, - padding: u1, + /// Wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + /// Wakeup auto-reload output clear value + WUTOCLR: u16, }), - }; - - /// High Resolution Timer: Timing Unit - pub const HRTIM_TIMX = extern struct { - /// Timer X Control Register + /// Control register CR: mmio.Mmio(packed struct(u32) { - /// HRTIM Timer x Clock prescaler - CKPSC: u3, - /// Continuous mode - CONT: u1, - /// Re-triggerable mode - RETRIG: u1, - /// Half mode enable - HALF: u1, - /// Push-Pull mode enable - PSHPLL: u1, - reserved10: u3, - /// Synchronization Resets Timer X - SYNCRST: packed union { + /// Wakeup clock selection + WUCKSEL: packed union { + raw: u3, + value: WUCKSEL, + }, + /// Timestamp event active edge + TSEDGE: packed union { raw: u1, - value: SYNCRST, + value: TSEDGE, }, - /// Synchronization Starts Timer X - SYNCSTRT: packed union { + /// RTC_REFIN reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + /// Bypass the shadow registers + BYPSHAD: u1, + /// Hour format + FMT: packed union { raw: u1, - value: SYNCSTRT, + value: FMT, }, - /// Delayed CMP2 mode - DELCMP2: packed union { - raw: u2, - value: DELCMP, + /// SSR underflow interrupt enable + SSRUIE: u1, + /// Alarm enable + ALRE: u1, + reserved10: u1, + /// Wakeup timer enable + WUTE: u1, + /// Timestamp enable + TSE: u1, + /// Alarm interrupt enable + ALRIE: u1, + reserved14: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Timestamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output selection + COSEL: packed union { + raw: u1, + value: COSEL, }, - /// Delayed CMP4 mode - DELCMP4: packed union { - raw: u2, - value: DELCMP, + /// Output polarity + POL: packed union { + raw: u1, + value: POL, }, - reserved17: u1, - /// Timer X Repetition update - REPU: u1, - /// Timer X reset update - RSTU: u1, - /// Timer A update - TAU: u1, - /// Timer B update - TBU: u1, - /// Timer C update - TCU: u1, - /// Timer D update - TDU: u1, - /// Timer E update - TEU: u1, - /// Master Timer update - MSTU: u1, - /// AC Synchronization - DACSYNC: packed union { + /// Output selection + OSEL: packed union { raw: u2, - value: DACSYNC, + value: OSEL, }, - /// Preload enable - PREEN: u1, - /// Update Gating - UPDGAT: packed union { - raw: u4, - value: UPDGAT, + /// Calibration output enable + COE: u1, + /// Timestamp on internal event enable + ITSE: u1, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper detection output enable on TAMPALRM + TAMPOE: u1, + /// ALRFCLR + ALRFCLR: u1, + reserved29: u1, + /// TAMPALRM pull-up enable + TAMPALRM_PU: u1, + /// TAMPALRM output type + TAMPALRM_TYPE: packed union { + raw: u1, + value: TAMPALRM_TYPE, }, + /// RTC_OUT2 output enable + OUT2EN: u1, + }), + /// Privilege mode control register + PRIVCR: mmio.Mmio(packed struct(u32) { + /// ALRPRIV + ALRPRIV: u1, + reserved2: u1, + /// WUTPRIV + WUTPRIV: u1, + /// TSPRIV + TSPRIV: u1, + reserved13: u9, + /// CALPRIV + CALPRIV: u1, + /// INITPRIV + INITPRIV: u1, + /// PRIV + PRIV: u1, + padding: u16, + }), + /// Secure mode control register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// ALRASEC + ALRASEC: u1, + /// ALRBSEC + ALRBSEC: u1, + /// WUTSEC + WUTSEC: u1, + /// TSSEC + TSSEC: u1, + reserved13: u9, + /// CALSEC + CALSEC: u1, + /// INITSEC + INITSEC: u1, + /// SEC + SEC: u1, + padding: u16, }), - /// Timer X Interrupt Status Register - ISR: mmio.Mmio(packed struct(u32) { - /// Compare X Interrupt Flag - CMP: u1, - reserved4: u3, - /// Repetition Interrupt Flag - REP: u1, - reserved6: u1, - /// Update Interrupt Flag - UPD: u1, - /// Capture X Interrupt Flag - CPT: u1, - reserved9: u1, - /// Output X Set Interrupt Flag - SETR: u1, - /// Output X Reset Interrupt Flag - RSTR: u1, - reserved13: u2, - /// Reset Interrupt Flag - RST: u1, - /// Delayed Protection Flag - DLYPRT: packed union { - raw: u1, - value: TIMAISR_DLYPRT, + /// Write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: packed union { + raw: u8, + value: KEY, }, - reserved16: u1, - /// Current Push Pull Status - CPPSTAT: packed union { + padding: u24, + }), + /// Calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved12: u3, + /// Calibration low-power mode + LPCAL: packed union { raw: u1, - value: CPPSTAT, + value: LPCAL, }, - /// Idle Push Pull Status - IPPSTAT: packed union { + /// Use a 16-second calibration cycle period + CALW16: packed union { raw: u1, - value: IPPSTAT, + value: CALW16, }, - /// Output X State - OSTAT: packed union { + /// Use an 8-second calibration cycle period + CALW8: packed union { raw: u1, - value: OUTPUTSTATE, + value: CALW8, }, - reserved20: u1, - /// Output X Copy - OCPY: packed union { + /// Increase frequency of RTC by 488.5 ppm + CALP: packed union { raw: u1, - value: OUTPUTSTATE, + value: CALP, }, - padding: u11, - }), - /// Timer X Interrupt Clear Register - ICR: mmio.Mmio(packed struct(u32) { - /// Compare X Interrupt flag Clear - CMPC: u1, - reserved4: u3, - /// Repetition Interrupt flag Clear - REPC: u1, - reserved6: u1, - /// Update Interrupt flag Clear - UPDC: u1, - /// Capture X Interrupt flag Clear - CPTC: u1, - reserved9: u1, - /// Output X Set flag Clear - SETRC: u1, - /// Output X Reset flag Clear - RSTRC: u1, - reserved13: u2, - /// Reset Interrupt flag Clear - RSTC: u1, - /// Delayed Protection Flag Clear - DLYPRTC: u1, - padding: u17, - }), - /// Timer X DMA / Interrupt Enable Register - DIER: mmio.Mmio(packed struct(u32) { - /// Compare X Interrupt Enable - CMPIE: u1, - reserved4: u3, - /// Repetition Interrupt Enable - REPIE: u1, - reserved6: u1, - /// Update Interrupt Enable - UPDIE: u1, - /// Capture Interrupt Enable - CPTIE: u1, - reserved9: u1, - /// Output X Set Interrupt Enable - SETRIE: u1, - /// Output X Reset Interrupt Enable - RSTRIE: u1, - reserved13: u2, - /// Reset/roll-over Interrupt Enable - RSTIE: u1, - /// Delayed Protection Interrupt Enable - DLYPRTIE: u1, - reserved16: u1, - /// Compare X DMA request Enable - CMPDE: u1, - reserved20: u3, - /// Repetition DMA request Enable - REPDE: u1, - reserved22: u1, - /// Update DMA request Enable - UPDDE: u1, - /// Capture X DMA request Enable - CPTDE: u1, - reserved25: u1, - /// Output X Set DMA request Enable - SETRDE: u1, - /// Output X Reset DMA request Enable - RSTRDE: u1, - reserved29: u2, - /// Reset/roll-over DMA request Enable - RSTDE: u1, - /// Delayed Protection DMA request Enable - DLYPRTDE: u1, - padding: u1, - }), - /// Timer X Counter Register - CNT: mmio.Mmio(packed struct(u32) { - /// Timerx Counter value - CNT: u16, padding: u16, }), - /// Timer X Period Register - PER: mmio.Mmio(packed struct(u32) { - /// Timerx Period value - PER: u16, - padding: u16, + /// Shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, }), - /// Timer X Repetition Register - REP: mmio.Mmio(packed struct(u32) { - /// Timerx Repetition counter value - REP: u8, - padding: u24, + /// Timestamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding: u9, }), - /// Timer X Compare X Register - CMP: mmio.Mmio(packed struct(u32) { - /// Timerx Compare X value - CMP: u16, + /// Timestamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, padding: u16, }), - /// Timer X Compare X Compound Register - CMPC: mmio.Mmio(packed struct(u32) { - /// Timerx Compare X value - CMP: u16, - /// Timerx Repetition value (aliased from HRTIM_REPx register) - REP: u8, - padding: u8, - }), - reserved48: [12]u8, - /// Timer X Capture X Register - CPT: [2]mmio.Mmio(packed struct(u32) { - /// Timerx Capture X value - CPT: u16, - padding: u16, + /// Timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u32, }), - /// Timer X Deadtime Register - DT: mmio.Mmio(packed struct(u32) { - /// Deadtime Rising value - DTR: u9, - /// Sign Deadtime Rising value - SDTR: packed union { - raw: u1, - value: SDTR, - }, - /// Deadtime Prescaler - DTPRSC: u3, - reserved14: u1, - /// Deadtime Rising Sign Lock - DTRSLK: u1, - /// Deadtime Rising Lock - DTRLK: u1, - /// Deadtime Falling value - DTF: u9, - /// Sign Deadtime Falling value - SDTF: packed union { + reserved64: [4]u8, + /// Alarm register + ALRMR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm A seconds mask + MSK1: packed union { raw: u1, - value: SDTF, + value: ALRMR_MSK, }, - reserved30: u4, - /// Deadtime Falling Sign Lock - DTFSLK: u1, - /// Deadtime Falling Lock - DTFLK: u1, - }), - /// Timer X Output X Set Register - SETR: mmio.Mmio(packed struct(u32) { - /// Software Set trigger - SST: packed union { + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm A minutes mask + MSK2: packed union { raw: u1, - value: ACTIVEEFFECT, + value: ALRMR_MSK, }, - /// Timer X resynchronizaton - RESYNC: packed union { + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: packed union { raw: u1, - value: ACTIVEEFFECT, + value: ALRMR_PM, }, - /// Timer X Period - PER: packed union { + /// Alarm A hours mask + MSK3: packed union { raw: u1, - value: ACTIVEEFFECT, + value: ALRMR_MSK, }, - /// Timer X compare X - CMP: packed union { + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: packed union { raw: u1, - value: ACTIVEEFFECT, + value: ALRMR_WDSEL, }, - reserved7: u3, - /// Master Period - MSTPER: packed union { + /// Alarm A date mask + MSK4: packed union { raw: u1, - value: ACTIVEEFFECT, + value: ALRMR_MSK, }, - /// Master Compare X - MSTCMPX: packed union { + }), + /// Alarm sub second register + ALRMSSR: mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u6, + reserved31: u1, + /// Clear synchronous counter on alarm (Binary mode only) + SSCLR: packed union { raw: u1, - value: ACTIVEEFFECT, + value: ALRMSSR_SSCLR, }, - reserved12: u3, - /// Timer Event X - TIMEVNT: packed union { + }), + reserved80: [8]u8, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Alarm flag + ALRF: packed union { raw: u1, - value: ACTIVEEFFECT, + value: ALRF, }, - reserved21: u8, - /// External Event X - EXTEVNT: packed union { + reserved2: u1, + /// Wakeup timer flag + WUTF: packed union { raw: u1, - value: ACTIVEEFFECT, + value: WUTF, }, - reserved31: u9, - /// Registers update (transfer preload to active) - UPDATE: packed union { + /// Timestamp flag + TSF: packed union { raw: u1, - value: ACTIVEEFFECT, + value: TSF, }, - }), - /// Timer X Output X Reset Register - RSTR: mmio.Mmio(packed struct(u32) { - /// Software Reset trigger - SRT: packed union { + /// Timestamp overflow flag + TSOVF: packed union { raw: u1, - value: INACTIVEEFFECT, + value: TSOVF, }, - /// Timer X resynchronizaton - RESYNC: packed union { + /// Internal timestamp flag + ITSF: packed union { raw: u1, - value: INACTIVEEFFECT, + value: ITSF, }, - /// Timer X Period - PER: packed union { + /// SSR underflow flag + SSRUF: packed union { raw: u1, - value: INACTIVEEFFECT, + value: SSRUF, }, - /// Timer X compare X - CMP: packed union { + padding: u25, + }), + /// Masked interrupt status register + MISR: mmio.Mmio(packed struct(u32) { + /// Alarm masked flag + ALRMF: packed union { raw: u1, - value: INACTIVEEFFECT, + value: ALRMF, }, - reserved7: u3, - /// Master Period - MSTPER: packed union { + reserved2: u1, + /// Wakeup timer masked flag + WUTMF: packed union { raw: u1, - value: INACTIVEEFFECT, + value: WUTMF, }, - /// Master Compare X - MSTCMP: packed union { + /// Timestamp masked flag + TSMF: packed union { raw: u1, - value: INACTIVEEFFECT, + value: TSMF, }, - reserved12: u3, - /// Timer Event X - TIMEVNT: packed union { + /// Timestamp overflow masked flag + TSOVMF: packed union { raw: u1, - value: INACTIVEEFFECT, + value: TSOVMF, }, - reserved21: u8, - /// External Event X - EXTEVNT: packed union { + /// Internal timestamp masked flag + ITSMF: packed union { raw: u1, - value: INACTIVEEFFECT, + value: ITSMF, }, - reserved31: u9, - /// Registers update (transfer preload to active) - UPDATE: packed union { + /// SSR underflow masked flag + SSRUMF: packed union { raw: u1, - value: INACTIVEEFFECT, + value: SSRUMF, }, + padding: u25, }), - reserved76: [8]u8, - /// Timer X External Event Filtering Register 1 - EEF: mmio.Mmio(packed struct(u32) { - /// External Event X latch - LTCH: u1, - /// External Event X filter - FLTR: packed union { - raw: u4, - value: EEFLTR, - }, - padding: u27, + /// Secure masked interrupt status register + SMISR: mmio.Mmio(packed struct(u32) { + /// Alarm x interrupt secure masked flag + ALRMF: u1, + reserved2: u1, + /// WUTMF + WUTMF: u1, + /// TSMF + TSMF: u1, + /// TSOVMF + TSOVMF: u1, + /// ITSMF + ITSMF: u1, + /// SSRUMF + SSRUMF: u1, + padding: u25, }), - reserved84: [4]u8, - /// Timer X Reset Register - RST: mmio.Mmio(packed struct(u32) { - /// Timer X compare 1 event - TCMP1: packed union { + /// Status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear alarm x flag + CALRF: packed union { raw: u1, - value: RESETEFFECT, + value: CALRF, }, - /// Timer X Update reset - UPDT: packed union { + reserved2: u1, + /// Clear wakeup timer flag + CWUTF: packed union { raw: u1, - value: RESETEFFECT, + value: CALRF, }, - /// Timer X compare X reset - CMP: packed union { + /// Clear timestamp flag + CTSF: packed union { raw: u1, - value: RESETEFFECT, + value: CALRF, }, - reserved4: u1, - /// Master timer Period - MSTPER: packed union { + /// Clear timestamp overflow flag + CTSOVF: packed union { raw: u1, - value: RESETEFFECT, + value: CALRF, }, - /// Master compare X - MSTCMP: packed union { + /// Clear internal timestamp flag + CITSF: packed union { raw: u1, - value: RESETEFFECT, + value: CALRF, }, - reserved9: u3, - /// External Event X - EXTEVNT: packed union { + /// Clear SSR underflow flag + CSSRUF: packed union { raw: u1, - value: RESETEFFECT, + value: CALRF, }, - reserved20: u10, - /// Timer X compare 2 event - TCMP2: packed union { - raw: u1, - value: RESETEFFECT, + padding: u25, + }), + reserved112: [16]u8, + /// Alarm binary mode register + ALRBINR: [2]mmio.Mmio(packed struct(u32) { + /// Synchronous counter alarm value in Binary mode + SS: u32, + }), + }; + }; + + pub const saes_v1a = struct { + pub const CHMOD = enum(u3) { + /// Electronic codebook + ECB = 0x0, + /// Cipher-block chaining + CBC = 0x1, + /// Counter mode + CTR = 0x2, + /// Galois counter mode and Galois message authentication code + GCM_GMAC = 0x3, + /// Counter with CBC-MAC + CCM = 0x4, + _, + }; + + pub const DATATYPE = enum(u2) { + /// No swapping (32-bit data). + None = 0x0, + /// Half-word swapping (16-bit data) + HalfWord = 0x1, + /// Byte swapping (8-bit data) + Byte = 0x2, + /// Bit-level swapping + Bit = 0x3, + }; + + pub const GCMPH = enum(u2) { + /// Initialization phase + InitPhase = 0x0, + /// Header phase + HeaderPhase = 0x1, + /// Payload phase + PayloadPhase = 0x2, + /// Final phase + FinalPhase = 0x3, + }; + + pub const KEYSEL = enum(u3) { + /// Software key, loaded in key registers SAES_KEYx + SoftwareKey = 0x0, + /// Derived hardware unique key + DHUK = 0x1, + /// Boot hardware key + BHK = 0x2, + /// XOR of DHUK and BHK + XOR_DHUK_BHK = 0x4, + _, + }; + + pub const KEYSIZE = enum(u1) { + /// 128-bit + Bits128 = 0x0, + /// 256-bit + Bits256 = 0x1, + }; + + pub const KMOD = enum(u2) { + /// AES peripheral + Normal = 0x0, + /// Wrapped key for SAES mode. Key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process. + WrappedKey = 0x1, + /// Shared key mode. After a successful decryption process (unwrapping), SAES key registers are shared with the peripheral described in KSHAREID[1:0] bitfield. This sharing is valid only while KMOD[1:0] at 0x2 and KEYVALID=1. When a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process. + SharedKey = 0x2, + _, + }; + + pub const KSHAREID = enum(u2) { + /// AES peripheral + AES = 0x0, + _, + }; + + pub const MODE = enum(u2) { + Encryption = 0x0, + /// Key derivation (or key preparation), for ECB/CBC decryption only + KeyDerivation = 0x1, + Decryption = 0x2, + _, + }; + + /// Secure advanced encryption standard hardware accelerator. + pub const SAES = extern struct { + /// SAES control register. + CR: mmio.Mmio(packed struct(u32) { + /// SAES enable This bit enables/disables the SAES peripheral: At any moment, clearing then setting the bit re-initializes the SAES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD = 01 + CHMOD = 011 and KMOD = 01 + CHMOD = 010 + MODE = 00. Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN. + EN: u1, + /// Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + DATATYPE: packed union { + raw: u2, + value: DATATYPE, }, - /// Timer X compare 4 event - TCMP4: packed union { - raw: u1, - value: RESETEFFECT, + /// SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + MODE: packed union { + raw: u2, + value: MODE, }, - padding: u10, + padding: u27, }), - /// Timer X Chopper Register - CHP: mmio.Mmio(packed struct(u32) { - /// Timerx carrier frequency value - CARFRQ: u4, - /// Timerx chopper duty cycle value - CARDTY: u3, - /// Timerx start pulsewidth - STRTPW: u4, - padding: u21, + /// SAES status register. + SR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero. + RDERR: u1, + /// Write error This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected write is ignored. + WRERR: u1, + /// Busy This flag indicates whether SAES is idle or busy during GCM payload encryption phase: The flag is set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase. + BUSY: u1, + reserved7: u3, + /// Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to. + KEYVALID: u1, + padding: u24, }), - /// Timer X Capture X Control Register - CCR: mmio.Mmio(packed struct(u32) { - /// Software Capture - SWCPT: packed union { - raw: u1, - value: CAPTUREEFFECT, + /// SAES data input register. + DINR: u32, + /// SAES data output register. + DOUTR: u32, + /// SAES key register 0. + KEYR: u32, + reserved32: [12]u8, + /// SAES initialization vector register 0. + IVR: [4]u32, + reserved64: [16]u8, + /// SAES suspend registers. + SUSPR: [8]u32, + reserved768: [672]u8, + /// SAES interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set. + CCFIE: u1, + /// Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set. + RWEIE: u1, + /// Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set. + KEIE: u1, + /// RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set. + RNGEIE: u1, + padding: u28, + }), + /// SAES interrupt status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1. + CCF: u1, + /// Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected. + RWEIF: u1, + /// Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. AES fails to load the key shared by SAES peripheral (KMOD=10). When KEYVALID = 1 and (KEYPROT = 1 or KEYSEL is not 0x0), the security context of the application that loads the key (secure or non-secure) does not match the security attribute of the access to SAES_CR or SAES_DOUT. In this case, KEYVALID and EN bits are cleared. SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set. + KEIF: u1, + /// RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral. + RNGEIF: u1, + padding: u28, + }), + /// SAES interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_SR and SAES_ISR registers. + CCF: u1, + /// Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and both RDERR and WRERR flags in the SAES_SR register. + RWEIF: u1, + /// Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register. + KEIF: u1, + /// RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register. + RNGEIF: u1, + padding: u28, + }), + }; + }; + + pub const saes_v1b = struct { + pub const CHMOD = enum(u3) { + /// Electronic codebook + ECB = 0x0, + /// Cipher-block chaining + CBC = 0x1, + /// Counter mode + CTR = 0x2, + /// Galois counter mode and Galois message authentication code + GCM_GMAC = 0x3, + /// Counter with CBC-MAC + CCM = 0x4, + _, + }; + + pub const DATATYPE = enum(u2) { + /// No swapping (32-bit data). + None = 0x0, + /// Half-word swapping (16-bit data) + HalfWord = 0x1, + /// Byte swapping (8-bit data) + Byte = 0x2, + /// Bit-level swapping + Bit = 0x3, + }; + + pub const KEYSEL = enum(u3) { + /// Software key, loaded in key registers SAES_KEYx + SoftwareKey = 0x0, + /// Derived hardware unique key + DHUK = 0x1, + /// Boot hardware key + BHK = 0x2, + /// XOR of DHUK and BHK + XOR_DHUK_BHK = 0x4, + _, + }; + + pub const KEYSIZE = enum(u1) { + /// 128-bit + Bits128 = 0x0, + /// 256-bit + Bits256 = 0x1, + }; + + pub const KMOD = enum(u2) { + /// AES peripheral + Normal = 0x0, + /// Wrapped key for SAES mode. Key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process. + WrappedKey = 0x1, + /// Shared key mode. After a successful decryption process (unwrapping), SAES key registers are shared with the peripheral described in KSHAREID[1:0] bitfield. This sharing is valid only while KMOD[1:0] at 0x2 and KEYVALID=1. When a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process. + SharedKey = 0x2, + _, + }; + + pub const KSHAREID = enum(u2) { + /// AES peripheral + AES = 0x0, + _, + }; + + pub const MODE = enum(u2) { + Encryption = 0x0, + /// Key derivation (or key preparation), for ECB/CBC decryption only + KeyDerivation = 0x1, + Decryption = 0x2, + _, + }; + + /// Secure advanced encryption standard hardware accelerator. + pub const SAES = extern struct { + /// SAES control register. + CR: mmio.Mmio(packed struct(u32) { + /// SAES enable This bit enables/disables the SAES peripheral: At any moment, clearing then setting the bit re-initializes the SAES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD = 01 + CHMOD = 011 and KMOD = 01 + CHMOD = 010 + MODE = 00. Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN. + EN: u1, + /// Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + DATATYPE: packed union { + raw: u2, + value: DATATYPE, }, - /// Update Capture - UPDCPT: packed union { - raw: u1, - value: CAPTUREEFFECT, + /// SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + MODE: packed union { + raw: u2, + value: MODE, }, - /// External Event X Capture - EXEVCPT: packed union { - raw: u1, - value: CAPTUREEFFECT, + padding: u27, + }), + /// SAES status register. + SR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Computation completed flag. This bit mirrors the CCF bit of the SAES_ISR register. + CCF: u1, + /// Write error This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected write is ignored. + WRERR: u1, + /// Busy This flag indicates whether SAES is idle or busy during GCM payload encryption phase: The flag is set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase. + BUSY: u1, + reserved7: u3, + /// Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to. + KEYVALID: u1, + padding: u24, + }), + /// SAES data input register. + DINR: u32, + /// SAES data output register. + DOUTR: u32, + /// SAES key register 0. + KEYR: u32, + reserved32: [12]u8, + /// SAES initialization vector register 0. + IVR: [4]u32, + reserved64: [16]u8, + /// SAES suspend registers. + SUSPR: [8]u32, + reserved768: [672]u8, + /// SAES interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set. + CCFIE: u1, + /// Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set. + RWEIE: u1, + /// Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set. + KEIE: u1, + /// RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set. + RNGEIE: u1, + padding: u28, + }), + /// SAES interrupt status register. + ISR: mmio.Mmio(packed struct(u32) { + /// Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1. + CCF: u1, + /// Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected. + RWEIF: u1, + /// Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. AES fails to load the key shared by SAES peripheral (KMOD=10). When KEYVALID = 1 and (KEYPROT = 1 or KEYSEL is not 0x0), the security context of the application that loads the key (secure or non-secure) does not match the security attribute of the access to SAES_CR or SAES_DOUT. In this case, KEYVALID and EN bits are cleared. SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set. + KEIF: u1, + /// RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral. + RNGEIF: u1, + padding: u28, + }), + /// SAES interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_SR and SAES_ISR registers. + CCF: u1, + /// Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and both RDERR and WRERR flags in the SAES_SR register. + RWEIF: u1, + /// Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register. + KEIF: u1, + /// RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register. + RNGEIF: u1, + padding: u28, + }), + }; + }; + + pub const sai_v1 = struct { + pub const CKSTR = enum(u1) { + /// Data strobing edge is falling edge of SCK + FallingEdge = 0x0, + /// Data strobing edge is rising edge of SCK + RisingEdge = 0x1, + }; + + pub const CNRDY = enum(u1) { + /// External AC’97 Codec is ready + Ready = 0x0, + /// External AC’97 Codec is not ready + NotReady = 0x1, + }; + + pub const COMP = enum(u2) { + /// No companding algorithm + NoCompanding = 0x0, + /// μ-Law algorithm + MuLaw = 0x2, + /// A-Law algorithm + ALaw = 0x3, + _, + }; + + pub const CPL = enum(u1) { + /// 1’s complement representation + OnesComplement = 0x0, + /// 2’s complement representation + TwosComplement = 0x1, + }; + + pub const DS = enum(u3) { + /// 8 bits + Bit8 = 0x2, + /// 10 bits + Bit10 = 0x3, + /// 16 bits + Bit16 = 0x4, + /// 20 bits + Bit20 = 0x5, + /// 24 bits + Bit24 = 0x6, + /// 32 bits + Bit32 = 0x7, + _, + }; + + pub const FLVL = enum(u3) { + /// FIFO empty + Empty = 0x0, + /// FIFO <= 1⁄4 but not empty + Quarter1 = 0x1, + /// 1⁄4 < FIFO <= 1⁄2 + Quarter2 = 0x2, + /// 1⁄2 < FIFO <= 3⁄4 + Quarter3 = 0x3, + /// 3⁄4 < FIFO but not full + Quarter4 = 0x4, + /// FIFO full + Full = 0x5, + _, + }; + + pub const FSOFF = enum(u1) { + /// FS is asserted on the first bit of the slot 0 + OnFirst = 0x0, + /// FS is asserted one bit before the first bit of the slot 0 + BeforeFirst = 0x1, + }; + + pub const FSPOL = enum(u1) { + /// FS is active low (falling edge) + FallingEdge = 0x0, + /// FS is active high (rising edge) + RisingEdge = 0x1, + }; + + pub const FTH = enum(u3) { + /// FIFO empty + Empty = 0x0, + /// 1⁄4 FIFO + Quarter1 = 0x1, + /// 1⁄2 FIFO + Quarter2 = 0x2, + /// 3⁄4 FIFO + Quarter3 = 0x3, + /// FIFO full + Full = 0x4, + _, + }; + + pub const LSBFIRST = enum(u1) { + /// Data are transferred with MSB first + MsbFirst = 0x0, + /// Data are transferred with LSB first + LsbFirst = 0x1, + }; + + pub const MODE = enum(u2) { + /// Master transmitter + MasterTx = 0x0, + /// Master receiver + MasterRx = 0x1, + /// Slave transmitter + SlaveTx = 0x2, + /// Slave receiver + SlaveRx = 0x3, + }; + + pub const MONO = enum(u1) { + /// Stereo mode + Stereo = 0x0, + /// Mono mode + Mono = 0x1, + }; + + pub const MUTEVAL = enum(u1) { + /// Bit value 0 is sent during the mute mode + SendZero = 0x0, + /// Last values are sent during the mute mode + SendLast = 0x1, + }; + + pub const NODIV = enum(u1) { + /// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + MasterClock = 0x0, + /// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + NoDiv = 0x1, + }; + + pub const OUTDRIV = enum(u1) { + /// Audio block output driven when SAIEN is set + OnStart = 0x0, + /// Audio block output driven immediately after the setting of this bit + Immediately = 0x1, + }; + + pub const PRTCFG = enum(u2) { + /// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + Free = 0x0, + /// SPDIF protocol + Spdif = 0x1, + /// AC’97 protocol + Ac97 = 0x2, + _, + }; + + pub const SLOTEN = enum(u16) { + /// Inactive slot + Inactive = 0x0, + /// Active slot + Active = 0x1, + _, + }; + + pub const SLOTSZ = enum(u2) { + /// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) + DataSize = 0x0, + /// 16-bit + Bit16 = 0x1, + /// 32-bit + Bit32 = 0x2, + _, + }; + + pub const SYNCEN = enum(u2) { + /// audio sub-block in asynchronous mode + Asynchronous = 0x0, + /// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode + Internal = 0x1, + /// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + External = 0x2, + _, + }; + + pub const WCKCFG = enum(u1) { + /// Clock configuration is correct + Correct = 0x0, + /// Clock configuration does not respect the rule concerning the frame length specification + Wrong = 0x1, + }; + + /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + pub const CH = extern struct { + /// Configuration register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// SAIx audio block mode immediately + MODE: packed union { + raw: u2, + value: MODE, + }, + /// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. + PRTCFG: packed union { + raw: u2, + value: PRTCFG, + }, + reserved5: u1, + /// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. + DS: packed union { + raw: u3, + value: DS, }, - reserved16: u13, - /// Timer X output Set - TXSET: packed union { + /// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. + LSBFIRST: packed union { raw: u1, - value: CAPTUREEFFECT, + value: LSBFIRST, }, - /// Timer X output Reset - TXRST: packed union { + /// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. + CKSTR: packed union { raw: u1, - value: CAPTUREEFFECT, + value: CKSTR, }, - /// Timer X Compare X - TXCMP: packed union { - raw: u1, - value: CAPTUREEFFECT, + /// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. + SYNCEN: packed union { + raw: u2, + value: SYNCEN, }, - reserved20: u1, - /// Timer Y output Set - TYSET: packed union { + /// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. + MONO: packed union { raw: u1, - value: CAPTUREEFFECT, + value: MONO, }, - /// Timer Y output Reset - TYRST: packed union { + /// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. + OUTDRIV: packed union { raw: u1, - value: CAPTUREEFFECT, + value: OUTDRIV, }, - /// Timer Y Compare X - TYCMP: packed union { + reserved16: u2, + /// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. + SAIEN: u1, + /// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. + DMAEN: u1, + reserved19: u1, + /// No fixed divider between MCLK and FS + NODIV: packed union { raw: u1, - value: CAPTUREEFFECT, + value: NODIV, }, - reserved24: u1, - /// Timer Z output Set - TZSET: packed union { - raw: u1, - value: CAPTUREEFFECT, + /// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: + MCKDIV: u4, + padding: u8, + }), + /// Configuration register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// FIFO threshold. This bit is set and cleared by software. + FTH: packed union { + raw: u3, + value: FTH, }, - /// Timer Z output Reset - TZRST: packed union { + /// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. + FFLUSH: u1, + /// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. + TRIS: u1, + /// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. + MUTE: u1, + /// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. + MUTEVAL: packed union { raw: u1, - value: CAPTUREEFFECT, + value: MUTEVAL, }, - /// Timer Z Compare X - TZCMP: packed union { + /// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. + MUTECNT: u6, + /// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. + CPL: packed union { raw: u1, - value: CAPTUREEFFECT, + value: CPL, }, - reserved28: u1, - /// Timer T output Set - TTSET: packed union { - raw: u1, - value: CAPTUREEFFECT, + /// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. + COMP: packed union { + raw: u2, + value: COMP, }, - /// Timer T output Reset - TTRST: packed union { + padding: u16, + }), + /// This register has no meaning in AC97 and SPDIF audio protocol + FRCR: mmio.Mmio(packed struct(u32) { + /// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. + FRL: u8, + /// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. + FSALL: u7, + reserved16: u1, + /// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. + FSDEF: u1, + /// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + FSPOL: packed union { raw: u1, - value: CAPTUREEFFECT, + value: FSPOL, }, - /// Timer T Compare X - TTCMP: packed union { + /// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + FSOFF: packed union { raw: u1, - value: CAPTUREEFFECT, + value: FSOFF, }, - padding: u1, + padding: u13, }), - reserved100: [4]u8, - /// Timer X Output Register - OUTR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Output 1 polarity - POL: packed union { - raw: u1, - value: POL, - }, - /// Output X Idle mode - IDLEM: u1, - /// Output X Idle State - IDLES: u1, - /// Output X Fault state - FAULTX: packed union { + /// This register has no meaning in AC97 and SPDIF audio protocol + SLOTR: mmio.Mmio(packed struct(u32) { + /// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + FBOFF: u5, + reserved6: u1, + /// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + SLOTSZ: packed union { raw: u2, - value: FAULT, - }, - /// Output X Chopper enable - CHP: u1, - /// Output X Deadtime upon burst mode Idle entry - DIDL: u1, - /// Deadtime enable - DTEN: u1, - /// Delayed Protection Enable - DLYPRTEN: u1, - /// Delayed Protection - DLYPRT: packed union { - raw: u3, - value: DLYPRT, + value: SLOTSZ, }, - padding: u19, - }), - /// Timer X Fault Register - FLT: mmio.Mmio(packed struct(u32) { - /// Fault X enable - FLTEN: packed union { - raw: u1, - value: FLTEN, + /// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + NBSLOT: u4, + reserved16: u4, + /// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + SLOTEN: packed union { + raw: u16, + value: SLOTEN, }, - reserved31: u30, - /// Fault sources Lock - FLTLCK: u1, }), - }; - }; - - pub const flash_wl = struct { - /// Flash - pub const FLASH = extern struct { - /// Access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: u3, - reserved8: u5, - /// Prefetch enable - PRFTEN: u1, - /// Instruction cache enable - ICEN: u1, - /// Data cache enable - DCEN: u1, - /// Instruction cache reset - ICRST: u1, - /// Data cache reset - DCRST: u1, - reserved15: u2, - /// CPU1 CortexM4 program erase suspend request - PES: u1, - /// Flash User area empty - EMPTY: u1, - padding: u15, + /// Interrupt mask register 2 + IM: mmio.Mmio(packed struct(u32) { + /// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. + OVRUDRIE: u1, + /// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. + MUTEDETIE: u1, + /// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. + WCKCFGIE: u1, + /// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, + FREQIE: u1, + /// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. + CNRDYIE: u1, + /// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + AFSDETIE: u1, + /// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + LFSDETIE: u1, + padding: u25, }), - reserved8: [4]u8, - /// Flash key register - KEYR: u32, - /// Option byte key register - OPTKEYR: u32, /// Status register SR: mmio.Mmio(packed struct(u32) { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved3: u1, - /// Programming error - PROGERR: u1, - /// Write protected error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Size error - SIZERR: u1, - /// Programming sequence error - PGSERR: u1, - /// Fast programming data miss error - MISERR: u1, - /// Fast programming error - FASTERR: u1, - reserved13: u3, - /// User Option OPTVAL indication - OPTNV: u1, - /// PCROP read error - RDERR: u1, - /// Option validity error - OPTVERR: u1, - /// Busy - BSY: u1, - reserved18: u1, - /// Programming or erase configuration busy - CFGBSY: u1, - /// Programming or erase operation suspended - PESD: u1, - padding: u12, - }), - /// Flash control register - CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Page erase - PER: u1, - /// This bit triggers the mass erase (all user pages) when set - MER: u1, - /// Page number selection - PNB: u8, - reserved16: u5, - /// Start - STRT: u1, - /// Options modification start - OPTSTRT: u1, - /// Fast programming - FSTPG: u1, - reserved24: u5, - /// End of operation interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// PCROP read error interrupt enable - RDERRIE: u1, - /// Force the option byte loading - OBL_LAUNCH: u1, - reserved30: u2, - /// Options Lock - OPTLOCK: u1, - /// FLASH_CR Lock - LOCK: u1, - }), - /// Flash ECC register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC fail address - ADDR_ECC: u17, - reserved20: u3, - /// System Flash ECC fail - SYSF_ECC: u1, - reserved24: u3, - /// ECC correction interrupt enable - ECCCIE: u1, - reserved26: u1, - /// CPU identification - CPUID: u3, - reserved30: u1, - /// ECC correction - ECCC: u1, - /// ECC detection - ECCD: u1, - }), - reserved32: [4]u8, - /// Flash option register - OPTR: mmio.Mmio(packed struct(u32) { - /// Read protection level - RDP: u8, - /// Security enabled - ESE: u1, - /// BOR reset Level - BOR_LEV: u3, - /// nRST_STOP - nRST_STOP: u1, - /// nRST_STDBY - nRST_STDBY: u1, - /// nRST_SHDW - nRST_SHDW: u1, - reserved16: u1, - /// Independent watchdog selection - IDWG_SW: u1, - /// Independent watchdog counter freeze in Stop mode - IWDG_STOP: u1, - /// Independent watchdog counter freeze in Standby mode - IWDG_STDBY: u1, - /// Window watchdog selection - WWDG_SW: u1, - reserved23: u3, - /// Boot configuration - nBOOT1: u1, - /// SRAM2 parity check enable - SRAM2_PE: u1, - /// SRAM2 Erase when system reset - SRAM2_RST: u1, - /// Software Boot0 - nSWBOOT0: u1, - /// nBoot0 option bit - nBOOT0: u1, - reserved29: u1, - /// Radio Automatic Gain Control Trimming - AGC_TRIM: u3, - }), - /// Flash Bank 1 PCROP Start address zone A register - PCROP1ASR: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROPQ area start offset - PCROP1A_STRT: u9, - padding: u23, - }), - /// Flash Bank 1 PCROP End address zone A register - PCROP1AER: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area end offset - PCROP1A_END: u9, - reserved31: u22, - /// PCROP area preserved when RDP level decreased - PCROP_RDP: u1, - }), - /// Flash Bank 1 WRP area A address register - WRP1AR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP first area A start offset - WRP1A_STRT: u8, - reserved16: u8, - /// Bank 1 WRP first area A end offset - WRP1A_END: u8, - padding: u8, - }), - /// Flash Bank 1 WRP area B address register - WRP1BR: mmio.Mmio(packed struct(u32) { - /// Bank 1 WRP second area B start offset - WRP1B_END: u8, - reserved16: u8, - /// Bank 1 WRP second area B end offset - WRP1B_STRT: u8, - padding: u8, - }), - /// Flash Bank 1 PCROP Start address area B register - PCROP1BSR: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area B start offset - PCROP1B_STRT: u9, - padding: u23, - }), - /// Flash Bank 1 PCROP End address area B register - PCROP1BER: mmio.Mmio(packed struct(u32) { - /// Bank 1 PCROP area end area B offset - PCROP1B_END: u9, - padding: u23, - }), - /// IPCC mailbox data buffer address register - IPCCBR: mmio.Mmio(packed struct(u32) { - /// PCC mailbox data buffer base address - IPCCDBA: u14, - padding: u18, - }), - reserved92: [28]u8, - /// CPU2 cortex M0 access control register - C2ACR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// CPU2 cortex M0 prefetch enable - PRFTEN: u1, - /// CPU2 cortex M0 instruction cache enable - ICEN: u1, - reserved11: u1, - /// CPU2 cortex M0 instruction cache reset - ICRST: u1, - reserved15: u3, - /// CPU2 cortex M0 program erase suspend request - PES: u1, - padding: u16, - }), - /// CPU2 cortex M0 status register - C2SR: mmio.Mmio(packed struct(u32) { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved3: u1, - /// Programming error - PROGERR: u1, - /// write protection error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Size error - SIZERR: u1, - /// Programming sequence error - PGSERR: u1, - /// Fast programming data miss error - MISSERR: u1, - /// Fast programming error - FASTERR: u1, - reserved14: u4, - /// PCROP read error - RDERR: u1, - reserved16: u1, - /// Busy - BSY: u1, - reserved18: u1, - /// Programming or erase configuration busy - CFGBSY: u1, - /// Programming or erase operation suspended - PESD: u1, - padding: u12, - }), - /// CPU2 cortex M0 control register - C2CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Page erase - PER: u1, - /// Masse erase - MER: u1, - /// Page Number selection - PNB: u8, - reserved16: u5, - /// Start - STRT: u1, - reserved18: u1, - /// Fast programming - FSTPG: u1, - reserved24: u5, - /// End of operation interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// PCROP read error interrupt enable - RDERRIE: u1, - padding: u5, + /// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. + OVRUDR: u1, + /// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. + MUTEDET: u1, + /// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. + WCKCFG: packed union { + raw: u1, + value: WCKCFG, + }, + /// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. + FREQ: u1, + /// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. + CNRDY: packed union { + raw: u1, + value: CNRDY, + }, + /// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. + AFSDET: u1, + /// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register + LFSDET: u1, + reserved16: u9, + /// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: + FLVL: packed union { + raw: u3, + value: FLVL, + }, + padding: u13, }), - reserved128: [24]u8, - /// Secure flash start address register - SFR: mmio.Mmio(packed struct(u32) { - /// Secure flash start address - SFSA: u8, - /// Flash security disable - FSD: u1, - reserved12: u3, - /// Disable Cortex M0 debug access - DDS: u1, - padding: u19, + /// Clear flag register + CLRFR: mmio.Mmio(packed struct(u32) { + /// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. + COVRUDR: u1, + /// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. + CMUTEDET: u1, + /// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. + CWCKCFG: u1, + reserved4: u1, + /// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. + CCNRDY: u1, + /// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. + CAFSDET: u1, + /// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. + CLFSDET: u1, + padding: u25, }), - /// Secure SRAM2 start address and cortex M0 reset vector register - SRRVR: mmio.Mmio(packed struct(u32) { - /// cortex M0 access control register - SBRV: u18, - /// Secure backup SRAM2a start address - SBRSA: u5, - /// backup SRAM2a security disable - BRSD: u1, - reserved25: u1, - /// Secure non backup SRAM2a start address - SNBRSA: u5, - /// non-backup SRAM2b security disable - NBRSD: u1, - /// CPU2 cortex M0 boot reset vector memory selection - C2OPT: u1, + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. + DATA: u32, }), }; + + /// Serial audio interface + pub const SAI = extern struct { + reserved4: [4]u8, + /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + CH: u32, + }; }; - pub const aes_f7 = struct { - pub const DATATYPE = enum(u2) { - /// Word - None = 0x0, - /// Half-word (16-bit) - HalfWord = 0x1, - /// Byte (8-bit) - Byte = 0x2, - /// Bit - Bit = 0x3, + pub const sai_v2 = struct { + pub const CKSTR = enum(u1) { + /// Data strobing edge is falling edge of SCK + FallingEdge = 0x0, + /// Data strobing edge is rising edge of SCK + RisingEdge = 0x1, }; - pub const GCMPH = enum(u2) { - /// Init phase - @"Init phase" = 0x0, - /// Header phase - @"Header phase" = 0x1, - /// Payload phase - @"Payload phase" = 0x2, - /// Final phase - @"Final phase" = 0x3, + pub const CNRDY = enum(u1) { + /// External AC’97 Codec is ready + Ready = 0x0, + /// External AC’97 Codec is not ready + NotReady = 0x1, + }; + + pub const COMP = enum(u2) { + /// No companding algorithm + NoCompanding = 0x0, + /// μ-Law algorithm + MuLaw = 0x2, + /// A-Law algorithm + ALaw = 0x3, + _, + }; + + pub const CPL = enum(u1) { + /// 1’s complement representation + OnesComplement = 0x0, + /// 2’s complement representation + TwosComplement = 0x1, + }; + + pub const DS = enum(u3) { + /// 8 bits + Bit8 = 0x2, + /// 10 bits + Bit10 = 0x3, + /// 16 bits + Bit16 = 0x4, + /// 20 bits + Bit20 = 0x5, + /// 24 bits + Bit24 = 0x6, + /// 32 bits + Bit32 = 0x7, + _, + }; + + pub const FLVL = enum(u3) { + /// FIFO empty + Empty = 0x0, + /// FIFO <= 1⁄4 but not empty + Quarter1 = 0x1, + /// 1⁄4 < FIFO <= 1⁄2 + Quarter2 = 0x2, + /// 1⁄2 < FIFO <= 3⁄4 + Quarter3 = 0x3, + /// 3⁄4 < FIFO but not full + Quarter4 = 0x4, + /// FIFO full + Full = 0x5, + _, + }; + + pub const FSOFF = enum(u1) { + /// FS is asserted on the first bit of the slot 0 + OnFirst = 0x0, + /// FS is asserted one bit before the first bit of the slot 0 + BeforeFirst = 0x1, + }; + + pub const FSPOL = enum(u1) { + /// FS is active low (falling edge) + FallingEdge = 0x0, + /// FS is active high (rising edge) + RisingEdge = 0x1, + }; + + pub const FTH = enum(u3) { + /// FIFO empty + Empty = 0x0, + /// 1⁄4 FIFO + Quarter1 = 0x1, + /// 1⁄2 FIFO + Quarter2 = 0x2, + /// 3⁄4 FIFO + Quarter3 = 0x3, + /// FIFO full + Full = 0x4, + _, + }; + + pub const LSBFIRST = enum(u1) { + /// Data are transferred with MSB first + MsbFirst = 0x0, + /// Data are transferred with LSB first + LsbFirst = 0x1, }; pub const MODE = enum(u2) { - /// Encryption - Mode1 = 0x0, - /// Key derivation (or key preparation for ECB/CBC decryption) - Mode2 = 0x1, - /// Decryption - Mode3 = 0x2, - /// Key derivation then single decryption - Mode4 = 0x3, + /// Master transmitter + MasterTx = 0x0, + /// Master receiver + MasterRx = 0x1, + /// Slave transmitter + SlaveTx = 0x2, + /// Slave receiver + SlaveRx = 0x3, }; - /// Advanced encryption standard hardware accelerator - pub const AES = extern struct { - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// AES enable - EN: u1, - /// Data type selection - DATATYPE: packed union { - raw: u2, - value: DATATYPE, - }, - /// Operating mode + pub const MONO = enum(u1) { + /// Stereo mode + Stereo = 0x0, + /// Mono mode + Mono = 0x1, + }; + + pub const MUTEVAL = enum(u1) { + /// Bit value 0 is sent during the mute mode + SendZero = 0x0, + /// Last values are sent during the mute mode + SendLast = 0x1, + }; + + pub const NODIV = enum(u1) { + /// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + MasterClock = 0x0, + /// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + NoDiv = 0x1, + }; + + pub const OUTDRIV = enum(u1) { + /// Audio block output driven when SAIEN is set + OnStart = 0x0, + /// Audio block output driven immediately after the setting of this bit + Immediately = 0x1, + }; + + pub const PRTCFG = enum(u2) { + /// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + Free = 0x0, + /// SPDIF protocol + Spdif = 0x1, + /// AC’97 protocol + Ac97 = 0x2, + _, + }; + + pub const SLOTEN = enum(u16) { + /// Inactive slot + Inactive = 0x0, + /// Active slot + Active = 0x1, + _, + }; + + pub const SLOTSZ = enum(u2) { + /// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) + DataSize = 0x0, + /// 16-bit + Bit16 = 0x1, + /// 32-bit + Bit32 = 0x2, + _, + }; + + pub const SYNCEN = enum(u2) { + /// audio sub-block in asynchronous mode + Asynchronous = 0x0, + /// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode + Internal = 0x1, + /// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + External = 0x2, + _, + }; + + pub const WCKCFG = enum(u1) { + /// Clock configuration is correct + Correct = 0x0, + /// Clock configuration does not respect the rule concerning the frame length specification + Wrong = 0x1, + }; + + /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + pub const CH = extern struct { + /// Configuration register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// SAIx audio block mode immediately MODE: packed union { raw: u2, value: MODE, }, - /// Chaining mode bit1 bit0 - CHMOD10: u2, - /// Computation Complete Flag Clear - CCFC: u1, - /// Error clear - ERRC: u1, - /// CCF flag interrupt enable - CCFIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// Enable DMA management of data input phase - DMAINEN: u1, - /// Enable DMA management of data output phase - DMAOUTEN: u1, - /// GCM or CCM phase selection - GCMPH: packed union { + /// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. + PRTCFG: packed union { raw: u2, - value: GCMPH, + value: PRTCFG, + }, + reserved5: u1, + /// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. + DS: packed union { + raw: u3, + value: DS, + }, + /// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. + LSBFIRST: packed union { + raw: u1, + value: LSBFIRST, + }, + /// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. + CKSTR: packed union { + raw: u1, + value: CKSTR, + }, + /// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. + SYNCEN: packed union { + raw: u2, + value: SYNCEN, + }, + /// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. + MONO: packed union { + raw: u1, + value: MONO, + }, + /// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. + OUTDRIV: packed union { + raw: u1, + value: OUTDRIV, + }, + reserved16: u2, + /// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. + SAIEN: u1, + /// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. + DMAEN: u1, + reserved19: u1, + /// No fixed divider between MCLK and FS + NODIV: packed union { + raw: u1, + value: NODIV, + }, + /// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: + MCKDIV: u4, + padding: u8, + }), + /// Configuration register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// FIFO threshold. This bit is set and cleared by software. + FTH: packed union { + raw: u3, + value: FTH, + }, + /// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. + FFLUSH: u1, + /// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. + TRIS: u1, + /// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. + MUTE: u1, + /// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. + MUTEVAL: packed union { + raw: u1, + value: MUTEVAL, + }, + /// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. + MUTECNT: u6, + /// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. + CPL: packed union { + raw: u1, + value: CPL, + }, + /// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. + COMP: packed union { + raw: u2, + value: COMP, }, + padding: u16, + }), + /// This register has no meaning in AC97 and SPDIF audio protocol + FRCR: mmio.Mmio(packed struct(u32) { + /// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. + FRL: u8, + /// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. + FSALL: u7, reserved16: u1, - /// Chaining mode bit2 - CHMOD2: u1, - reserved18: u1, - /// Key size selection - KEYSIZE: u1, + /// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. + FSDEF: u1, + /// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + FSPOL: packed union { + raw: u1, + value: FSPOL, + }, + /// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + FSOFF: packed union { + raw: u1, + value: FSOFF, + }, padding: u13, }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Computation complete flag - CCF: u1, - /// Read error flag - RDERR: u1, - /// Write error flag - WRERR: u1, - /// Busy flag - BUSY: u1, - padding: u28, + /// This register has no meaning in AC97 and SPDIF audio protocol + SLOTR: mmio.Mmio(packed struct(u32) { + /// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + FBOFF: u5, + reserved6: u1, + /// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + SLOTSZ: packed union { + raw: u2, + value: SLOTSZ, + }, + /// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + NBSLOT: u4, + reserved16: u4, + /// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + SLOTEN: packed union { + raw: u16, + value: SLOTEN, + }, }), - /// Data input register - DINR: mmio.Mmio(packed struct(u32) { - /// Input data word - DIN: u32, + /// Interrupt mask register 2 + IM: mmio.Mmio(packed struct(u32) { + /// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. + OVRUDRIE: u1, + /// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. + MUTEDETIE: u1, + /// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. + WCKCFGIE: u1, + /// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, + FREQIE: u1, + /// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. + CNRDYIE: u1, + /// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + AFSDETIE: u1, + /// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + LFSDETIE: u1, + padding: u25, }), - /// Data output register - DOUTR: mmio.Mmio(packed struct(u32) { - /// Output data word - DOUT: u32, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. + OVRUDR: u1, + /// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. + MUTEDET: u1, + /// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. + WCKCFG: packed union { + raw: u1, + value: WCKCFG, + }, + /// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. + FREQ: u1, + /// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. + CNRDY: packed union { + raw: u1, + value: CNRDY, + }, + /// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. + AFSDET: u1, + /// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register + LFSDET: u1, + reserved16: u9, + /// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: + FLVL: packed union { + raw: u3, + value: FLVL, + }, + padding: u13, }), - /// Key register - KEYR: mmio.Mmio(packed struct(u32) { - /// Cryptographic key - KEY: u32, + /// Clear flag register + CLRFR: mmio.Mmio(packed struct(u32) { + /// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. + COVRUDR: u1, + /// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. + CMUTEDET: u1, + /// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. + CWCKCFG: u1, + reserved4: u1, + /// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. + CCNRDY: u1, + /// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. + CAFSDET: u1, + /// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. + CLFSDET: u1, + padding: u25, }), - reserved32: [12]u8, - /// Initialization vector register - IVR: [4]mmio.Mmio(packed struct(u32) { - /// Initialization vector input - IVI: u32, + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. + DATA: u32, }), - reserved64: [16]u8, - /// Suspend register - SUSPR: [8]mmio.Mmio(packed struct(u32) { - /// AES suspend - SUSP: u32, + }; + + /// Serial audio interface + pub const SAI = extern struct { + /// Global configuration register + GCR: mmio.Mmio(packed struct(u32) { + /// Synchronization inputs + SYNCIN: u2, + reserved4: u2, + /// Synchronization outputs These bits are set and cleared by software. + SYNCOUT: u2, + padding: u26, }), + /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + CH: u32, }; }; - pub const saes_v1b = struct { - pub const CHMOD = enum(u3) { - /// Electronic codebook - ECB = 0x0, - /// Cipher-block chaining - CBC = 0x1, - /// Counter mode - CTR = 0x2, - /// Galois counter mode and Galois message authentication code - GCM_GMAC = 0x3, - /// Counter with CBC-MAC - CCM = 0x4, - _, + pub const sai_v3_2pdm = struct { + pub const CKSTR = enum(u1) { + /// Data strobing edge is falling edge of SCK + FallingEdge = 0x0, + /// Data strobing edge is rising edge of SCK + RisingEdge = 0x1, }; - pub const DATATYPE = enum(u2) { - /// No swapping (32-bit data). - None = 0x0, - /// Half-word swapping (16-bit data) - HalfWord = 0x1, - /// Byte swapping (8-bit data) - Byte = 0x2, - /// Bit-level swapping - Bit = 0x3, + pub const CNRDY = enum(u1) { + /// External AC’97 Codec is ready + Ready = 0x0, + /// External AC’97 Codec is not ready + NotReady = 0x1, }; - pub const KEYSEL = enum(u3) { - /// Software key, loaded in key registers SAES_KEYx - SoftwareKey = 0x0, - /// Derived hardware unique key - DHUK = 0x1, - /// Boot hardware key - BHK = 0x2, - /// XOR of DHUK and BHK - XOR_DHUK_BHK = 0x4, + pub const COMP = enum(u2) { + /// No companding algorithm + NoCompanding = 0x0, + /// μ-Law algorithm + MuLaw = 0x2, + /// A-Law algorithm + ALaw = 0x3, _, }; - pub const KEYSIZE = enum(u1) { - /// 128-bit - Bits128 = 0x0, - /// 256-bit - Bits256 = 0x1, - }; - - pub const KMOD = enum(u2) { - /// AES peripheral - Normal = 0x0, - /// Wrapped key for SAES mode. Key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process. - WrappedKey = 0x1, - /// Shared key mode. After a successful decryption process (unwrapping), SAES key registers are shared with the peripheral described in KSHAREID[1:0] bitfield. This sharing is valid only while KMOD[1:0] at 0x2 and KEYVALID=1. When a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process. - SharedKey = 0x2, - _, + pub const CPL = enum(u1) { + /// 1’s complement representation + OnesComplement = 0x0, + /// 2’s complement representation + TwosComplement = 0x1, }; - pub const KSHAREID = enum(u2) { - /// AES peripheral - AES = 0x0, + pub const DS = enum(u3) { + /// 8 bits + Bit8 = 0x2, + /// 10 bits + Bit10 = 0x3, + /// 16 bits + Bit16 = 0x4, + /// 20 bits + Bit20 = 0x5, + /// 24 bits + Bit24 = 0x6, + /// 32 bits + Bit32 = 0x7, _, }; - pub const MODE = enum(u2) { - Encryption = 0x0, - /// Key derivation (or key preparation), for ECB/CBC decryption only - KeyDerivation = 0x1, - Decryption = 0x2, + pub const FLVL = enum(u3) { + /// FIFO empty + Empty = 0x0, + /// FIFO <= 1⁄4 but not empty + Quarter1 = 0x1, + /// 1⁄4 < FIFO <= 1⁄2 + Quarter2 = 0x2, + /// 1⁄2 < FIFO <= 3⁄4 + Quarter3 = 0x3, + /// 3⁄4 < FIFO but not full + Quarter4 = 0x4, + /// FIFO full + Full = 0x5, _, }; - /// Secure advanced encryption standard hardware accelerator. - pub const SAES = extern struct { - /// SAES control register. - CR: mmio.Mmio(packed struct(u32) { - /// SAES enable This bit enables/disables the SAES peripheral: At any moment, clearing then setting the bit re-initializes the SAES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD = 01 + CHMOD = 011 and KMOD = 01 + CHMOD = 010 + MODE = 00. Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN. - EN: u1, - /// Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. - DATATYPE: packed union { - raw: u2, - value: DATATYPE, - }, - /// SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. - MODE: packed union { - raw: u2, - value: MODE, - }, - padding: u27, - }), - /// SAES status register. - SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Computation completed flag. This bit mirrors the CCF bit of the SAES_ISR register. - CCF: u1, - /// Write error This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected write is ignored. - WRERR: u1, - /// Busy This flag indicates whether SAES is idle or busy during GCM payload encryption phase: The flag is set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase. - BUSY: u1, - reserved7: u3, - /// Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to. - KEYVALID: u1, - padding: u24, - }), - /// SAES data input register. - DINR: u32, - /// SAES data output register. - DOUTR: u32, - /// SAES key register 0. - KEYR: u32, - reserved32: [12]u8, - /// SAES initialization vector register 0. - IVR: [4]u32, - reserved64: [16]u8, - /// SAES suspend registers. - SUSPR: [8]u32, - reserved768: [672]u8, - /// SAES interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set. - CCFIE: u1, - /// Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set. - RWEIE: u1, - /// Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set. - KEIE: u1, - /// RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set. - RNGEIE: u1, - padding: u28, - }), - /// SAES interrupt status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1. - CCF: u1, - /// Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected. - RWEIF: u1, - /// Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. AES fails to load the key shared by SAES peripheral (KMOD=10). When KEYVALID = 1 and (KEYPROT = 1 or KEYSEL is not 0x0), the security context of the application that loads the key (secure or non-secure) does not match the security attribute of the access to SAES_CR or SAES_DOUT. In this case, KEYVALID and EN bits are cleared. SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set. - KEIF: u1, - /// RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral. - RNGEIF: u1, - padding: u28, - }), - /// SAES interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_SR and SAES_ISR registers. - CCF: u1, - /// Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and both RDERR and WRERR flags in the SAES_SR register. - RWEIF: u1, - /// Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register. - KEIF: u1, - /// RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register. - RNGEIF: u1, - padding: u28, - }), + pub const FSOFF = enum(u1) { + /// FS is asserted on the first bit of the slot 0 + OnFirst = 0x0, + /// FS is asserted one bit before the first bit of the slot 0 + BeforeFirst = 0x1, }; - }; - pub const rcc_f1cl = struct { - pub const ADCPRE = enum(u2) { - /// PCLK2 divided by 2 - Div2 = 0x0, - /// PCLK2 divided by 4 - Div4 = 0x1, - /// PCLK2 divided by 6 - Div6 = 0x2, - /// PCLK2 divided by 8 - Div8 = 0x3, + pub const FSPOL = enum(u1) { + /// FS is active low (falling edge) + FallingEdge = 0x0, + /// FS is active high (rising edge) + RisingEdge = 0x1, }; - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, + pub const FTH = enum(u3) { + /// FIFO empty + Empty = 0x0, + /// 1⁄4 FIFO + Quarter1 = 0x1, + /// 1⁄2 FIFO + Quarter2 = 0x2, + /// 3⁄4 FIFO + Quarter3 = 0x3, + /// FIFO full + Full = 0x4, _, }; - pub const I2S2SRC = enum(u1) { - /// System clock (SYSCLK) selected as I2S clock entry - SYS = 0x0, - /// PLL3 VCO clock selected as I2S clock entry - PLL3 = 0x1, + pub const LSBFIRST = enum(u1) { + /// Data are transferred with MSB first + MsbFirst = 0x0, + /// Data are transferred with LSB first + LsbFirst = 0x1, }; - pub const MCOSEL = enum(u4) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// System clock selected - SYS = 0x4, - /// HSI oscillator clock selected - HSI = 0x5, - /// HSE oscillator clock selected - HSE = 0x6, - /// PLL clock divided by 2 selected - PLL = 0x7, - /// PLL2 clock selected - PLL2 = 0x8, - /// PLL3 clock divided by 2 selected - PLL3DIV2 = 0x9, - /// XT1 external oscillator selected - XT1 = 0xa, - /// PLL3 clock selected - PLL3 = 0xb, - _, + pub const MODE = enum(u2) { + /// Master transmitter + MasterTx = 0x0, + /// Master receiver + MasterRx = 0x1, + /// Slave transmitter + SlaveTx = 0x2, + /// Slave receiver + SlaveRx = 0x3, }; - pub const PLL2MUL = enum(u4) { - /// PLL clock entry x8 - Mul8 = 0x6, - /// PLL clock entry x9 - Mul9 = 0x7, - /// PLL clock entry x10 - Mul10 = 0x8, - /// PLL clock entry x11 - Mul11 = 0x9, - /// PLL clock entry x12 - Mul12 = 0xa, - /// PLL clock entry x13 - Mul13 = 0xb, - /// PLL clock entry x14 - Mul14 = 0xc, - /// PLL clock entry x16 - Mul16 = 0xe, - /// PLL clock entry x20 - Mul20 = 0xf, - _, + pub const MONO = enum(u1) { + /// Stereo mode + Stereo = 0x0, + /// Mono mode + Mono = 0x1, }; - pub const PLLMUL = enum(u4) { - /// PLL input clock x4 - Mul4 = 0x2, - /// PLL input clock x5 - Mul5 = 0x3, - /// PLL input clock x6 - Mul6 = 0x4, - /// PLL input clock x7 - Mul7 = 0x5, - /// PLL input clock x8 - Mul8 = 0x6, - /// PLL input clock x9 - Mul9 = 0x7, - /// PLL input clock x6.5 - Mul6_5 = 0xd, - _, + pub const MUTEVAL = enum(u1) { + /// Bit value 0 is sent during the mute mode + SendZero = 0x0, + /// Last values are sent during the mute mode + SendLast = 0x1, }; - pub const PLLSRC = enum(u1) { - /// HSI divided by 2 selected as PLL input clock - HSI_Div2 = 0x0, - /// HSE divided by PREDIV selected as PLL input clock - HSE_Div_PREDIV = 0x1, + pub const NODIV = enum(u1) { + /// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + MasterClock = 0x0, + /// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + NoDiv = 0x1, }; - pub const PLLXTPRE = enum(u1) { - /// HSE clock not divided - Div1 = 0x0, - /// HSE clock divided by 2 - Div2 = 0x1, + pub const OUTDRIV = enum(u1) { + /// Audio block output driven when SAIEN is set + OnStart = 0x0, + /// Audio block output driven immediately after the setting of this bit + Immediately = 0x1, }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, + pub const PRTCFG = enum(u2) { + /// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + Free = 0x0, + /// SPDIF protocol + Spdif = 0x1, + /// AC’97 protocol + Ac97 = 0x2, _, }; - pub const PREDIV1 = enum(u4) { - /// PREDIV input clock not divided - Div1 = 0x0, - /// PREDIV input clock divided by 2 - Div2 = 0x1, - /// PREDIV input clock divided by 3 - Div3 = 0x2, - /// PREDIV input clock divided by 4 - Div4 = 0x3, - /// PREDIV input clock divided by 5 - Div5 = 0x4, - /// PREDIV input clock divided by 6 - Div6 = 0x5, - /// PREDIV input clock divided by 7 - Div7 = 0x6, - /// PREDIV input clock divided by 8 - Div8 = 0x7, - /// PREDIV input clock divided by 9 - Div9 = 0x8, - /// PREDIV input clock divided by 10 - Div10 = 0x9, - /// PREDIV input clock divided by 11 - Div11 = 0xa, - /// PREDIV input clock divided by 12 - Div12 = 0xb, - /// PREDIV input clock divided by 13 - Div13 = 0xc, - /// PREDIV input clock divided by 14 - Div14 = 0xd, - /// PREDIV input clock divided by 15 - Div15 = 0xe, - /// PREDIV input clock divided by 16 - Div16 = 0xf, - }; - - pub const PREDIV1SRC = enum(u1) { - /// HSE oscillator clock selected as PREDIV1 clock entry - HSE = 0x0, - /// PLL2 selected as PREDIV1 clock entry - PLL2 = 0x1, + pub const SLOTEN = enum(u16) { + /// Inactive slot + Inactive = 0x0, + /// Active slot + Active = 0x1, + _, }; - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, + pub const SLOTSZ = enum(u2) { + /// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) + DataSize = 0x0, + /// 16-bit + Bit16 = 0x1, + /// 32-bit + Bit32 = 0x2, + _, }; - pub const SW = enum(u2) { - /// HSI oscillator used as system clock - HSI = 0x0, - /// HSE oscillator used as system clock - HSE = 0x1, - /// PLL used as system clock - PLL1_P = 0x2, + pub const SYNCEN = enum(u2) { + /// audio sub-block in asynchronous mode + Asynchronous = 0x0, + /// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode + Internal = 0x1, + /// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + External = 0x2, _, }; - pub const USBPRE = enum(u1) { - /// PLL clock is divided by 1.5 - Div1_5 = 0x0, - /// PLL clock is not divided - Div1 = 0x1, + pub const WCKCFG = enum(u1) { + /// Clock configuration is correct + Correct = 0x0, + /// Clock configuration does not respect the rule concerning the frame length specification + Wrong = 0x1, }; - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal High Speed clock enable - HSION: u1, - /// Internal High Speed clock ready flag - HSIRDY: u1, - reserved3: u1, - /// Internal High Speed clock trimming - HSITRIM: u5, - /// Internal High Speed clock Calibration - HSICAL: u8, - /// External High Speed clock enable - HSEON: u1, - /// External High Speed clock ready flag - HSERDY: u1, - /// External High Speed clock Bypass - HSEBYP: u1, - /// Clock Security System enable - CSSON: u1, - reserved24: u4, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - /// PLL2 enable - PLL2ON: u1, - /// PLL2 clock ready flag - PLL2RDY: u1, - /// PLL3 enable - PLL3ON: u1, - /// PLL3 clock ready flag - PLL3RDY: u1, - padding: u2, - }), - /// Clock configuration register (RCC_CFGR) - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock Switch - SW: packed union { + /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + pub const CH = extern struct { + /// Configuration register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// SAIx audio block mode immediately + MODE: packed union { raw: u2, - value: SW, + value: MODE, }, - /// System Clock Switch Status - SWS: packed union { + /// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. + PRTCFG: packed union { raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, + value: PRTCFG, }, - /// APB Low speed prescaler (APB1) - PPRE1: packed union { + reserved5: u1, + /// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. + DS: packed union { raw: u3, - value: PPRE, + value: DS, }, - /// APB High speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, + /// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. + LSBFIRST: packed union { + raw: u1, + value: LSBFIRST, }, - /// ADC prescaler - ADCPRE: packed union { + /// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. + CKSTR: packed union { + raw: u1, + value: CKSTR, + }, + /// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. + SYNCEN: packed union { raw: u2, - value: ADCPRE, + value: SYNCEN, }, - /// PLL entry clock source - PLLSRC: packed union { + /// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. + MONO: packed union { raw: u1, - value: PLLSRC, + value: MONO, }, - /// HSE divider for PLL entry - PLLXTPRE: packed union { + /// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. + OUTDRIV: packed union { raw: u1, - value: PLLXTPRE, + value: OUTDRIV, }, - /// PLL Multiplication Factor - PLLMUL: packed union { - raw: u4, - value: PLLMUL, + reserved16: u2, + /// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. + SAIEN: u1, + /// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. + DMAEN: u1, + reserved19: u1, + /// No fixed divider between MCLK and FS + NODIV: packed union { + raw: u1, + value: NODIV, }, - /// USB prescaler - USBPRE: packed union { + /// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: + MCKDIV: u6, + /// Oversampling ratio for master clock + OSR: u1, + padding: u5, + }), + /// Configuration register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// FIFO threshold. This bit is set and cleared by software. + FTH: packed union { + raw: u3, + value: FTH, + }, + /// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. + FFLUSH: u1, + /// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. + TRIS: u1, + /// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. + MUTE: u1, + /// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. + MUTEVAL: packed union { raw: u1, - value: USBPRE, + value: MUTEVAL, }, - reserved24: u1, - /// Microcontroller clock output - MCOSEL: packed union { - raw: u4, - value: MCOSEL, + /// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. + MUTECNT: u6, + /// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. + CPL: packed union { + raw: u1, + value: CPL, }, - padding: u4, + /// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. + COMP: packed union { + raw: u2, + value: COMP, + }, + padding: u16, }), - /// Clock interrupt register (RCC_CIR) - CIR: mmio.Mmio(packed struct(u32) { - /// LSI Ready Interrupt flag - LSIRDYF: u1, - /// LSE Ready Interrupt flag - LSERDYF: u1, - /// HSI Ready Interrupt flag - HSIRDYF: u1, - /// HSE Ready Interrupt flag - HSERDYF: u1, - /// PLL Ready Interrupt flag - PLLRDYF: u1, - /// PLL2 Ready Interrupt flag - PLL2RDYF: u1, - /// PLL3 Ready Interrupt flag - PLL3RDYF: u1, - /// Clock Security System Interrupt flag - CSSF: u1, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1, - /// LSE Ready Interrupt Enable - LSERDYIE: u1, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1, - /// HSE Ready Interrupt Enable - HSERDYIE: u1, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1, - /// PLL2 Ready Interrupt Enable - PLL2RDYIE: u1, - /// PLL3 Ready Interrupt Enable - PLL3RDYIE: u1, + /// This register has no meaning in AC97 and SPDIF audio protocol + FRCR: mmio.Mmio(packed struct(u32) { + /// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. + FRL: u8, + /// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. + FSALL: u7, reserved16: u1, - /// LSI Ready Interrupt Clear - LSIRDYC: u1, - /// LSE Ready Interrupt Clear - LSERDYC: u1, - /// HSI Ready Interrupt Clear - HSIRDYC: u1, - /// HSE Ready Interrupt Clear - HSERDYC: u1, - /// PLL Ready Interrupt Clear - PLLRDYC: u1, - /// PLL2 Ready Interrupt Clear - PLL2RDYC: u1, - /// PLL3 Ready Interrupt Clear - PLL3RDYC: u1, - /// Clock security system interrupt clear - CSSC: u1, - padding: u8, - }), - /// APB2 peripheral reset register (RCC_APB2RSTR) - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// Alternate function I/O reset - AFIORST: u1, - reserved2: u1, - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - reserved9: u2, - /// ADC 1 interface reset - ADC1RST: u1, - /// ADC 2 interface reset - ADC2RST: u1, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI 1 reset - SPI1RST: u1, - reserved14: u1, - /// USART1 reset - USART1RST: u1, - padding: u17, - }), - /// APB1 peripheral reset register (RCC_APB1RSTR) - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - /// Timer 4 reset - TIM4RST: u1, - /// Timer 5 reset - TIM5RST: u1, - /// Timer 6 reset - TIM6RST: u1, - /// Timer 7 reset - TIM7RST: u1, - reserved11: u5, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI2 reset - SPI2RST: u1, - /// SPI3 reset - SPI3RST: u1, - reserved17: u1, - /// USART 2 reset - USART2RST: u1, - /// USART 3 reset - USART3RST: u1, - /// USART 4 reset - UART4RST: u1, - /// USART 5 reset - UART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - reserved25: u2, - /// CAN1 reset - CAN1RST: u1, - /// CAN2 reset - CAN2RST: u1, - /// Backup interface reset - BKPRST: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - padding: u2, + /// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. + FSDEF: u1, + /// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + FSPOL: packed union { + raw: u1, + value: FSPOL, + }, + /// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + FSOFF: packed union { + raw: u1, + value: FSOFF, + }, + padding: u13, }), - /// AHB Peripheral Clock enable register (RCC_AHBENR) - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// SRAM interface clock enable - SRAMEN: u1, - reserved4: u1, - /// FLASH clock enable - FLASHEN: u1, + /// This register has no meaning in AC97 and SPDIF audio protocol + SLOTR: mmio.Mmio(packed struct(u32) { + /// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + FBOFF: u5, reserved6: u1, - /// CRC clock enable - CRCEN: u1, - reserved12: u5, - /// USB OTG FS clock enable - USB_OTG_FSEN: u1, - reserved14: u1, - /// Ethernet MAC clock enable - ETHEN: u1, - /// Ethernet MAC TX clock enable - ETHTXEN: u1, - /// Ethernet MAC RX clock enable - ETHRXEN: u1, - padding: u15, - }), - /// APB2 peripheral clock enable register (RCC_APB2ENR) - APB2ENR: mmio.Mmio(packed struct(u32) { - /// Alternate function I/O clock enable - AFIOEN: u1, - reserved2: u1, - /// I/O port A clock enable - GPIOAEN: u1, - /// I/O port B clock enable - GPIOBEN: u1, - /// I/O port C clock enable - GPIOCEN: u1, - /// I/O port D clock enable - GPIODEN: u1, - /// I/O port E clock enable - GPIOEEN: u1, - reserved9: u2, - /// ADC 1 interface clock enable - ADC1EN: u1, - /// ADC 2 interface clock enable - ADC2EN: u1, - /// TIM1 Timer clock enable - TIM1EN: u1, - /// SPI 1 clock enable - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable - USART1EN: u1, - padding: u17, - }), - /// APB1 peripheral clock enable register (RCC_APB1ENR) - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer 2 clock enable - TIM2EN: u1, - /// Timer 3 clock enable - TIM3EN: u1, - /// Timer 4 clock enable - TIM4EN: u1, - /// Timer 5 clock enable - TIM5EN: u1, - /// Timer 6 clock enable - TIM6EN: u1, - /// Timer 7 clock enable - TIM7EN: u1, - reserved11: u5, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI 2 clock enable - SPI2EN: u1, - /// SPI 3 clock enable - SPI3EN: u1, - reserved17: u1, - /// USART 2 clock enable - USART2EN: u1, - /// USART 3 clock enable - USART3EN: u1, - /// UART 4 clock enable - UART4EN: u1, - /// UART 5 clock enable - UART5EN: u1, - /// I2C 1 clock enable - I2C1EN: u1, - /// I2C 2 clock enable - I2C2EN: u1, - reserved25: u2, - /// CAN1 clock enable - CAN1EN: u1, - /// CAN2 clock enable - CAN2EN: u1, - /// Backup interface clock enable - BKPEN: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - padding: u2, - }), - /// Backup domain control register (RCC_BDCR) - BDCR: mmio.Mmio(packed struct(u32) { - /// External Low Speed oscillator enable - LSEON: u1, - /// External Low Speed oscillator ready - LSERDY: u1, - /// External Low Speed oscillator bypass - LSEBYP: u1, - reserved8: u5, - /// RTC clock source selection - RTCSEL: packed union { + /// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + SLOTSZ: packed union { raw: u2, - value: RTCSEL, + value: SLOTSZ, + }, + /// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + NBSLOT: u4, + reserved16: u4, + /// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + SLOTEN: packed union { + raw: u16, + value: SLOTEN, }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - padding: u15, - }), - /// Control/status register (RCC_CSR) - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low speed oscillator enable - LSION: u1, - /// Internal low speed oscillator ready - LSIRDY: u1, - reserved24: u22, - /// Remove reset flag - RMVF: u1, - reserved26: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, }), - /// AHB peripheral clock reset register (RCC_AHBRSTR) - AHBRSTR: mmio.Mmio(packed struct(u32) { - reserved12: u12, - /// USB OTG FS reset - USB_OTG_FSRST: u1, - reserved14: u1, - /// Ethernet MAC reset - ETHRST: u1, - padding: u17, + /// Interrupt mask register 2 + IM: mmio.Mmio(packed struct(u32) { + /// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. + OVRUDRIE: u1, + /// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. + MUTEDETIE: u1, + /// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. + WCKCFGIE: u1, + /// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, + FREQIE: u1, + /// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. + CNRDYIE: u1, + /// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + AFSDETIE: u1, + /// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + LFSDETIE: u1, + padding: u25, }), - /// Clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// PREDIV1 division factor - PREDIV1: packed union { - raw: u4, - value: PREDIV1, - }, - /// PREDIV2 division factor - PREDIV2: packed union { - raw: u4, - value: PREDIV1, - }, - /// PLL2 Multiplication Factor - PLL2MUL: packed union { - raw: u4, - value: PLL2MUL, - }, - /// PLL3 Multiplication Factor - PLL3MUL: packed union { - raw: u4, - value: PLL2MUL, - }, - /// PREDIV1 entry clock source - PREDIV1SRC: packed union { + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. + OVRUDR: u1, + /// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. + MUTEDET: u1, + /// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. + WCKCFG: packed union { raw: u1, - value: PREDIV1SRC, + value: WCKCFG, }, - /// I2S2 clock source - I2S2SRC: packed union { + /// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. + FREQ: u1, + /// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. + CNRDY: packed union { raw: u1, - value: I2S2SRC, + value: CNRDY, }, - /// I2S3 clock source - I2S3SRC: packed union { - raw: u1, - value: I2S2SRC, + /// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. + AFSDET: u1, + /// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register + LFSDET: u1, + reserved16: u9, + /// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: + FLVL: packed union { + raw: u3, + value: FLVL, }, padding: u13, }), + /// Clear flag register + CLRFR: mmio.Mmio(packed struct(u32) { + /// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. + COVRUDR: u1, + /// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. + CMUTEDET: u1, + /// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. + CWCKCFG: u1, + reserved4: u1, + /// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. + CCNRDY: u1, + /// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. + CAFSDET: u1, + /// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. + CLFSDET: u1, + padding: u25, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. + DATA: u32, + }), + }; + + /// Serial audio interface + pub const SAI = extern struct { + /// Global configuration register + GCR: mmio.Mmio(packed struct(u32) { + /// Synchronization inputs + SYNCIN: u2, + reserved4: u2, + /// Synchronization outputs These bits are set and cleared by software. + SYNCOUT: u2, + padding: u26, + }), + /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + CH: u32, + reserved68: [60]u8, + /// PDM control register + PDMCR: mmio.Mmio(packed struct(u32) { + /// PDM enable + PDMEN: u1, + reserved4: u3, + /// Number of microphones + MICNBR: u2, + reserved8: u2, + /// Clock enable of bitstream clock number 1 + CKEN: u1, + padding: u23, + }), + /// PDM delay register + PDMDLY: mmio.Mmio(packed struct(u32) { + /// Delay line adjust for first microphone of pair 1 + DLYML: u3, + reserved4: u1, + /// Delay line adjust for second microphone of pair 1 + DLYMR: u3, + padding: u25, + }), }; }; - pub const usb_v3 = struct { - pub const DIR = enum(u1) { - /// data transmitted by the USB peripheral to the host PC - To = 0x0, - /// data received by the USB peripheral from the host PC - From = 0x1, + pub const sai_v3_4pdm = struct { + pub const CKSTR = enum(u1) { + /// Data strobing edge is falling edge of SCK + FallingEdge = 0x0, + /// Data strobing edge is rising edge of SCK + RisingEdge = 0x1, }; - pub const EP_TYPE = enum(u2) { - /// Bulk endpoint - Bulk = 0x0, - /// Control endpoint - Control = 0x1, - /// Iso endpoint - Iso = 0x2, - /// Interrupt endpoint - Interrupt = 0x3, + pub const CNRDY = enum(u1) { + /// External AC’97 Codec is ready + Ready = 0x0, + /// External AC’97 Codec is not ready + NotReady = 0x1, }; - pub const LPMACK = enum(u1) { - /// the valid LPM Token will be NYET - Nyet = 0x0, - /// the valid LPM Token will be ACK - Ack = 0x1, + pub const COMP = enum(u2) { + /// No companding algorithm + NoCompanding = 0x0, + /// μ-Law algorithm + MuLaw = 0x2, + /// A-Law algorithm + ALaw = 0x3, + _, }; - pub const SDET = enum(u1) { - /// CDP detected - CDP = 0x0, - /// DCP detected - DCP = 0x1, + pub const CPL = enum(u1) { + /// 1’s complement representation + OnesComplement = 0x0, + /// 2’s complement representation + TwosComplement = 0x1, }; - pub const STAT = enum(u2) { - /// all requests addressed to this endpoint are ignored - Disabled = 0x0, - /// the endpoint is stalled and all requests result in a STALL handshake - Stall = 0x1, - /// the endpoint is naked and all requests result in a NAK handshake - Nak = 0x2, - /// this endpoint is enabled, requests are ACKed - Valid = 0x3, + pub const DS = enum(u3) { + /// 8 bits + Bit8 = 0x2, + /// 10 bits + Bit10 = 0x3, + /// 16 bits + Bit16 = 0x4, + /// 20 bits + Bit20 = 0x5, + /// 24 bits + Bit24 = 0x6, + /// 32 bits + Bit32 = 0x7, + _, }; - /// Universal serial bus full-speed device interface - pub const USB = extern struct { - /// endpoint register - EPR: [8]mmio.Mmio(packed struct(u32) { - /// EA - EA: u4, - /// STAT_TX - STAT_TX: packed union { + pub const FLVL = enum(u3) { + /// FIFO empty + Empty = 0x0, + /// FIFO <= 1⁄4 but not empty + Quarter1 = 0x1, + /// 1⁄4 < FIFO <= 1⁄2 + Quarter2 = 0x2, + /// 1⁄2 < FIFO <= 3⁄4 + Quarter3 = 0x3, + /// 3⁄4 < FIFO but not full + Quarter4 = 0x4, + /// FIFO full + Full = 0x5, + _, + }; + + pub const FSOFF = enum(u1) { + /// FS is asserted on the first bit of the slot 0 + OnFirst = 0x0, + /// FS is asserted one bit before the first bit of the slot 0 + BeforeFirst = 0x1, + }; + + pub const FSPOL = enum(u1) { + /// FS is active low (falling edge) + FallingEdge = 0x0, + /// FS is active high (rising edge) + RisingEdge = 0x1, + }; + + pub const FTH = enum(u3) { + /// FIFO empty + Empty = 0x0, + /// 1⁄4 FIFO + Quarter1 = 0x1, + /// 1⁄2 FIFO + Quarter2 = 0x2, + /// 3⁄4 FIFO + Quarter3 = 0x3, + /// FIFO full + Full = 0x4, + _, + }; + + pub const LSBFIRST = enum(u1) { + /// Data are transferred with MSB first + MsbFirst = 0x0, + /// Data are transferred with LSB first + LsbFirst = 0x1, + }; + + pub const MODE = enum(u2) { + /// Master transmitter + MasterTx = 0x0, + /// Master receiver + MasterRx = 0x1, + /// Slave transmitter + SlaveTx = 0x2, + /// Slave receiver + SlaveRx = 0x3, + }; + + pub const MONO = enum(u1) { + /// Stereo mode + Stereo = 0x0, + /// Mono mode + Mono = 0x1, + }; + + pub const MUTEVAL = enum(u1) { + /// Bit value 0 is sent during the mute mode + SendZero = 0x0, + /// Last values are sent during the mute mode + SendLast = 0x1, + }; + + pub const NODIV = enum(u1) { + /// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + MasterClock = 0x0, + /// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + NoDiv = 0x1, + }; + + pub const OUTDRIV = enum(u1) { + /// Audio block output driven when SAIEN is set + OnStart = 0x0, + /// Audio block output driven immediately after the setting of this bit + Immediately = 0x1, + }; + + pub const PRTCFG = enum(u2) { + /// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + Free = 0x0, + /// SPDIF protocol + Spdif = 0x1, + /// AC’97 protocol + Ac97 = 0x2, + _, + }; + + pub const SLOTEN = enum(u16) { + /// Inactive slot + Inactive = 0x0, + /// Active slot + Active = 0x1, + _, + }; + + pub const SLOTSZ = enum(u2) { + /// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) + DataSize = 0x0, + /// 16-bit + Bit16 = 0x1, + /// 32-bit + Bit32 = 0x2, + _, + }; + + pub const SYNCEN = enum(u2) { + /// audio sub-block in asynchronous mode + Asynchronous = 0x0, + /// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode + Internal = 0x1, + /// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + External = 0x2, + _, + }; + + pub const WCKCFG = enum(u1) { + /// Clock configuration is correct + Correct = 0x0, + /// Clock configuration does not respect the rule concerning the frame length specification + Wrong = 0x1, + }; + + /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + pub const CH = extern struct { + /// Configuration register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// SAIx audio block mode immediately + MODE: packed union { raw: u2, - value: STAT, + value: MODE, }, - /// DTOG_TX - DTOG_TX: u1, - /// CTR_TX - CTR_TX: u1, - /// EP_KIND - EP_KIND: u1, - /// EPTYPE - EP_TYPE: packed union { + /// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. + PRTCFG: packed union { raw: u2, - value: EP_TYPE, + value: PRTCFG, }, - /// SETUP - SETUP: u1, - /// STAT_RX - STAT_RX: packed union { + reserved5: u1, + /// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. + DS: packed union { + raw: u3, + value: DS, + }, + /// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. + LSBFIRST: packed union { + raw: u1, + value: LSBFIRST, + }, + /// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. + CKSTR: packed union { + raw: u1, + value: CKSTR, + }, + /// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. + SYNCEN: packed union { raw: u2, - value: STAT, + value: SYNCEN, }, - /// DTOG_RX - DTOG_RX: u1, - /// CTR_RX - CTR_RX: u1, - padding: u16, - }), - reserved64: [32]u8, - /// control register - CNTR: mmio.Mmio(packed struct(u32) { - /// Force a reset of the USB peripheral, exactly like a RESET signaling on the USB - FRES: u1, - /// Enter power down mode - PDWN: u1, - /// Enter low-power mode - LPMODE: u1, - /// Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected - FSUSP: u1, - /// Resume request - RESUME: u1, - /// LPM L1 request request - L1RESUME: u1, - reserved7: u1, - /// L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - L1REQM: u1, - /// ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - ESOFM: u1, - /// SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - SOFM: u1, - /// RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - RESETM: u1, - /// SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - SUSPM: u1, - /// WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - WKUPM: u1, - /// ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - ERRM: u1, - /// PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - PMAOVRM: u1, - /// CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - CTRM: u1, - padding: u16, - }), - /// interrupt status register - ISTR: mmio.Mmio(packed struct(u32) { - /// EP_ID - EP_ID: u4, - /// DIR - DIR: packed union { + /// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. + MONO: packed union { raw: u1, - value: DIR, + value: MONO, }, - reserved7: u2, - /// LPM command to enter the L1 state is successfully received and acknowledged - L1REQ: u1, - /// an SOF packet is expected but not received - ESOF: u1, - /// beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus - SOF: u1, - /// peripheral detects an active USB RESET signal at its inputs - RESET: u1, - /// no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus - SUSP: u1, - /// activity is detected that wakes up the USB peripheral - WKUP: u1, - /// One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred - ERR: u1, - /// microcontroller has not been able to respond in time to an USB memory request - PMAOVR: u1, - /// endpoint has successfully completed a transaction - CTR: u1, - padding: u16, - }), - /// frame number register - FNR: mmio.Mmio(packed struct(u32) { - /// FN - FN: u11, - /// LSOF - LSOF: u2, - /// the frame timer remains in this state until an USB reset or USB suspend event occurs - LCK: u1, - /// received data minus upstream port data line - RXDM: u1, - /// received data plus upstream port data line - RXDP: u1, - padding: u16, - }), - /// device address - DADDR: mmio.Mmio(packed struct(u32) { - /// device address - ADD: u7, - /// USB device enabled - EF: u1, - padding: u24, + /// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. + OUTDRIV: packed union { + raw: u1, + value: OUTDRIV, + }, + reserved16: u2, + /// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. + SAIEN: u1, + /// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. + DMAEN: u1, + reserved19: u1, + /// No fixed divider between MCLK and FS + NODIV: packed union { + raw: u1, + value: NODIV, + }, + /// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: + MCKDIV: u6, + /// Oversampling ratio for master clock + OSR: u1, + padding: u5, }), - /// Buffer table address - BTABLE: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// BTABLE - BTABLE: u13, + /// Configuration register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// FIFO threshold. This bit is set and cleared by software. + FTH: packed union { + raw: u3, + value: FTH, + }, + /// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. + FFLUSH: u1, + /// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. + TRIS: u1, + /// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. + MUTE: u1, + /// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. + MUTEVAL: packed union { + raw: u1, + value: MUTEVAL, + }, + /// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. + MUTECNT: u6, + /// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. + CPL: packed union { + raw: u1, + value: CPL, + }, + /// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. + COMP: packed union { + raw: u2, + value: COMP, + }, padding: u16, }), - /// LPM control and status register - LPMCSR: mmio.Mmio(packed struct(u32) { - /// enable the LPM support within the USB device - LPMEN: u1, - /// LPMACK - LPMACK: packed union { + /// This register has no meaning in AC97 and SPDIF audio protocol + FRCR: mmio.Mmio(packed struct(u32) { + /// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. + FRL: u8, + /// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. + FSALL: u7, + reserved16: u1, + /// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. + FSDEF: u1, + /// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + FSPOL: packed union { raw: u1, - value: LPMACK, + value: FSPOL, }, - reserved3: u1, - /// REMWAKE - REMWAKE: u1, - /// BESL - BESL: u4, - padding: u24, - }), - /// Battery Charging Detector - BCDR: mmio.Mmio(packed struct(u32) { - /// Battery charging detector mode enable - BCDEN: u1, - /// Data contact detection mode enable - DCDEN: u1, - /// Primary detection mode enable - PDEN: u1, - /// Secondary detection mode enable - SDEN: u1, - /// Data contact detection status - DCDET: u1, - /// Primary detection status - PDET: u1, - /// Secondary detection status - SDET: packed union { + /// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + FSOFF: packed union { raw: u1, - value: SDET, + value: FSOFF, }, - /// DM pull-up detection status - PS2DET: u1, - reserved15: u7, - /// DP pull-up control - DPPU: u1, - padding: u16, + padding: u13, }), - }; - }; - - pub const dbgmcu_wb = struct { - /// Debug support - pub const DBGMCU = extern struct { - /// MCU Device ID Code Register - IDCODE: mmio.Mmio(packed struct(u32) { - /// Device Identifier - DEV_ID: u12, + /// This register has no meaning in AC97 and SPDIF audio protocol + SLOTR: mmio.Mmio(packed struct(u32) { + /// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + FBOFF: u5, + reserved6: u1, + /// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + SLOTSZ: packed union { + raw: u2, + value: SLOTSZ, + }, + /// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + NBSLOT: u4, reserved16: u4, - /// Revision Identifier - REV_ID: u16, + /// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + SLOTEN: packed union { + raw: u16, + value: SLOTEN, + }, }), - /// Debug MCU Configuration Register - CR: mmio.Mmio(packed struct(u32) { - /// Debug Sleep Mode - DBG_SLEEP: u1, - /// Debug Stop Mode - DBG_STOP: u1, - /// Debug Standby Mode - DBG_STANDBY: u1, - reserved5: u2, - /// Trace port and clock enable - TRACE_IOEN: u1, - reserved28: u22, - /// External trigger output enable - TRGOEN: u1, - padding: u3, + /// Interrupt mask register 2 + IM: mmio.Mmio(packed struct(u32) { + /// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. + OVRUDRIE: u1, + /// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. + MUTEDETIE: u1, + /// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. + WCKCFGIE: u1, + /// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, + FREQIE: u1, + /// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. + CNRDYIE: u1, + /// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + AFSDETIE: u1, + /// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + LFSDETIE: u1, + padding: u25, }), - reserved60: [52]u8, - /// APB1 Low Freeze Register CPU1 - APB1FZR1: mmio.Mmio(packed struct(u32) { - /// Debug Timer 2 stopped when Core is halted - TIM2: u1, - reserved10: u9, - /// RTC counter stopped when core is halted - RTC: u1, - /// WWDG counter stopped when core is halted - WWDG: u1, - /// IWDG counter stopped when core is halted - IWDG: u1, - reserved21: u8, - /// Debug I2C1 SMBUS timeout stopped when Core is halted - I2C1: u1, - reserved23: u1, - /// Debug I2C3 SMBUS timeout stopped when core is halted - I2C3: u1, - reserved31: u7, - /// Debug LPTIM1 stopped when Core is halted - LPTIM1: u1, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. + OVRUDR: u1, + /// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. + MUTEDET: u1, + /// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. + WCKCFG: packed union { + raw: u1, + value: WCKCFG, + }, + /// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. + FREQ: u1, + /// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. + CNRDY: packed union { + raw: u1, + value: CNRDY, + }, + /// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. + AFSDET: u1, + /// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register + LFSDET: u1, + reserved16: u9, + /// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: + FLVL: packed union { + raw: u3, + value: FLVL, + }, + padding: u13, }), - /// APB1 Low Freeze Register CPU2 - C2AP_B1FZR1: mmio.Mmio(packed struct(u32) { - /// LPTIM2 counter stopped when core is halted - LPTIM2: u1, - reserved10: u9, - /// RTC counter stopped when core is halted - RTC: u1, - reserved12: u1, - /// IWDG stopped when core is halted - IWDG: u1, - reserved21: u8, - /// I2C1 SMBUS timeout stopped when core is halted - I2C1: u1, - reserved23: u1, - /// I2C3 SMBUS timeout stopped when core is halted - I2C3: u1, - reserved31: u7, - /// LPTIM1 counter stopped when core is halted - LPTIM1: u1, + /// Clear flag register + CLRFR: mmio.Mmio(packed struct(u32) { + /// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. + COVRUDR: u1, + /// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. + CMUTEDET: u1, + /// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. + CWCKCFG: u1, + reserved4: u1, + /// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. + CCNRDY: u1, + /// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. + CAFSDET: u1, + /// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. + CLFSDET: u1, + padding: u25, }), - /// APB1 High Freeze Register CPU1 - APB1FZR2: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// LPTIM2 counter stopped when core is halted - LPTIM2: u1, - padding: u26, + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. + DATA: u32, }), - /// APB1 High Freeze Register CPU2 - C2APB1FZR2: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// LPTIM2 counter stopped when core is halted - LPTIM2: u1, + }; + + /// Serial audio interface + pub const SAI = extern struct { + /// Global configuration register + GCR: mmio.Mmio(packed struct(u32) { + /// Synchronization inputs + SYNCIN: u2, + reserved4: u2, + /// Synchronization outputs These bits are set and cleared by software. + SYNCOUT: u2, padding: u26, }), - /// APB2 Freeze Register CPU1 - APB2FZR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 counter stopped when core is halted - TIM1: u1, - reserved17: u5, - /// TIM16 counter stopped when core is halted - TIM16: u1, - /// TIM17 counter stopped when core is halted - TIM17: u1, - padding: u13, + /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + CH: u32, + reserved68: [60]u8, + /// PDM control register + PDMCR: mmio.Mmio(packed struct(u32) { + /// PDM enable + PDMEN: u1, + reserved4: u3, + /// Number of microphones + MICNBR: u2, + reserved8: u2, + /// Clock enable of bitstream clock number 1 + CKEN: u1, + padding: u23, + }), + /// PDM delay register + PDMDLY: mmio.Mmio(packed struct(u32) { + /// Delay line adjust for first microphone of pair 1 + DLYML: u3, + reserved4: u1, + /// Delay line adjust for second microphone of pair 1 + DLYMR: u3, + padding: u25, }), }; }; - pub const rtc_v2l0 = struct { - pub const ALRMR_MSK = enum(u1) { - /// Alarm set if the date/day match - ToMatch = 0x0, - /// Date/day don’t care in Alarm comparison - NotMatch = 0x1, + pub const sai_v4_2pdm = struct { + pub const CKSTR = enum(u1) { + /// Data strobing edge is falling edge of SCK + FallingEdge = 0x0, + /// Data strobing edge is rising edge of SCK + RisingEdge = 0x1, }; - pub const ALRMR_PM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const CNRDY = enum(u1) { + /// External AC’97 Codec is ready + Ready = 0x0, + /// External AC’97 Codec is not ready + NotReady = 0x1, }; - pub const ALRMR_WDSEL = enum(u1) { - /// DU[3:0] represents the date units - DateUnits = 0x0, - /// DU[3:0] represents the week day. DT[1:0] is don’t care - WeekDay = 0x1, + pub const COMP = enum(u2) { + /// No companding algorithm + NoCompanding = 0x0, + /// μ-Law algorithm + MuLaw = 0x2, + /// A-Law algorithm + ALaw = 0x3, + _, }; - pub const AMPM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const CPL = enum(u1) { + /// 1’s complement representation + OnesComplement = 0x0, + /// 2’s complement representation + TwosComplement = 0x1, }; - pub const CALP = enum(u1) { - /// No RTCCLK pulses are added - NoChange = 0x0, - /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - IncreaseFreq = 0x1, + pub const DS = enum(u3) { + /// 8 bits + Bit8 = 0x2, + /// 10 bits + Bit10 = 0x3, + /// 16 bits + Bit16 = 0x4, + /// 20 bits + Bit20 = 0x5, + /// 24 bits + Bit24 = 0x6, + /// 32 bits + Bit32 = 0x7, + _, }; - pub const CALW16 = enum(u1) { - /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 - Sixteen_Second = 0x1, + pub const FLVL = enum(u3) { + /// FIFO empty + Empty = 0x0, + /// FIFO <= 1⁄4 but not empty + Quarter1 = 0x1, + /// 1⁄4 < FIFO <= 1⁄2 + Quarter2 = 0x2, + /// 1⁄2 < FIFO <= 3⁄4 + Quarter3 = 0x3, + /// 3⁄4 < FIFO but not full + Quarter4 = 0x4, + /// FIFO full + Full = 0x5, _, }; - pub const CALW8 = enum(u1) { - /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected - Eight_Second = 0x1, - _, + pub const FSOFF = enum(u1) { + /// FS is asserted on the first bit of the slot 0 + OnFirst = 0x0, + /// FS is asserted one bit before the first bit of the slot 0 + BeforeFirst = 0x1, }; - pub const COSEL = enum(u1) { - /// Calibration output is 512 Hz (with default prescaler setting) - CalFreq_512Hz = 0x0, - /// Calibration output is 1 Hz (with default prescaler setting) - CalFreq_1Hz = 0x1, + pub const FSPOL = enum(u1) { + /// FS is active low (falling edge) + FallingEdge = 0x0, + /// FS is active high (rising edge) + RisingEdge = 0x1, }; - pub const FMT = enum(u1) { - /// 24 hour/day format - Twenty_Four_Hour = 0x0, - /// AM/PM hour format - AM_PM = 0x1, + pub const FTH = enum(u3) { + /// FIFO empty + Empty = 0x0, + /// 1⁄4 FIFO + Quarter1 = 0x1, + /// 1⁄2 FIFO + Quarter2 = 0x2, + /// 3⁄4 FIFO + Quarter3 = 0x3, + /// FIFO full + Full = 0x4, + _, }; - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Alarm B output enabled - AlarmB = 0x2, - /// Wakeup output enabled - Wakeup = 0x3, + pub const LSBFIRST = enum(u1) { + /// Data are transferred with MSB first + MsbFirst = 0x0, + /// Data are transferred with LSB first + LsbFirst = 0x1, }; - pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - Low = 0x1, + pub const MODE = enum(u2) { + /// Master transmitter + MasterTx = 0x0, + /// Master receiver + MasterRx = 0x1, + /// Slave transmitter + SlaveTx = 0x2, + /// Slave receiver + SlaveRx = 0x3, }; - pub const RECALPF = enum(u1) { - /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 - Pending = 0x1, - _, + pub const MONO = enum(u1) { + /// Stereo mode + Stereo = 0x0, + /// Mono mode + Mono = 0x1, }; - pub const TAMPFLT = enum(u2) { - /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - Immediate = 0x0, - /// Tamper event is activated after 2 consecutive samples at the active level - Samples2 = 0x1, - /// Tamper event is activated after 4 consecutive samples at the active level - Samples4 = 0x2, - /// Tamper event is activated after 8 consecutive samples at the active level - Samples8 = 0x3, + pub const MUTEVAL = enum(u1) { + /// Bit value 0 is sent during the mute mode + SendZero = 0x0, + /// Last values are sent during the mute mode + SendLast = 0x1, }; - pub const TAMPFREQ = enum(u3) { - /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - Div32768 = 0x0, - /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - Div16384 = 0x1, - /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - Div8192 = 0x2, - /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - Div4096 = 0x3, - /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - Div2048 = 0x4, - /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - Div1024 = 0x5, - /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - Div512 = 0x6, - /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - Div256 = 0x7, + pub const NODIV = enum(u1) { + /// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + MasterClock = 0x0, + /// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + NoDiv = 0x1, }; - pub const TAMPPRCH = enum(u2) { - /// 1 RTCCLK cycle - Cycles1 = 0x0, - /// 2 RTCCLK cycles - Cycles2 = 0x1, - /// 4 RTCCLK cycles - Cycles4 = 0x2, - /// 8 RTCCLK cycles - Cycles8 = 0x3, + pub const OUTDRIV = enum(u1) { + /// Audio block output driven when SAIEN is set + OnStart = 0x0, + /// Audio block output driven immediately after the setting of this bit + Immediately = 0x1, }; - pub const TAMPPUDIS = enum(u1) { - /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - Enabled = 0x0, - /// Disable precharge of RTC_TAMPx pins - Disabled = 0x1, + pub const PRTCFG = enum(u2) { + /// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + Free = 0x0, + /// SPDIF protocol + Spdif = 0x1, + /// AC’97 protocol + Ac97 = 0x2, + _, }; - pub const TAMPTRG = enum(u1) { - /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. - RisingEdge = 0x0, - /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event - FallingEdge = 0x1, + pub const SLOTEN = enum(u16) { + /// Inactive slot + Inactive = 0x0, + /// Active slot + Active = 0x1, + _, }; - pub const TSEDGE = enum(u1) { - /// RTC_TS input rising edge generates a time-stamp event - RisingEdge = 0x0, - /// RTC_TS input falling edge generates a time-stamp event - FallingEdge = 0x1, + pub const SLOTSZ = enum(u2) { + /// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) + DataSize = 0x0, + /// 16-bit + Bit16 = 0x1, + /// 32-bit + Bit32 = 0x2, + _, }; - pub const WUCKSEL = enum(u3) { - /// RTC/16 clock is selected - Div16 = 0x0, - /// RTC/8 clock is selected - Div8 = 0x1, - /// RTC/4 clock is selected - Div4 = 0x2, - /// RTC/2 clock is selected - Div2 = 0x3, - /// ck_spre (usually 1 Hz) clock is selected - ClockSpare = 0x4, - /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - ClockSpareWithOffset = 0x6, + pub const SYNCEN = enum(u2) { + /// audio sub-block in asynchronous mode + Asynchronous = 0x0, + /// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode + Internal = 0x1, + /// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + External = 0x2, _, }; - /// Real-time clock - pub const RTC = extern struct { - /// Time register - TR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, - }), - /// Date register - DR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding: u8, - }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Wakeup clock selection - WUCKSEL: packed union { - raw: u3, - value: WUCKSEL, - }, - /// Timestamp event active edge - TSEDGE: packed union { - raw: u1, - value: TSEDGE, + pub const WCKCFG = enum(u1) { + /// Clock configuration is correct + Correct = 0x0, + /// Clock configuration does not respect the rule concerning the frame length specification + Wrong = 0x1, + }; + + /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + pub const CH = extern struct { + /// Configuration register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// SAIx audio block mode immediately + MODE: packed union { + raw: u2, + value: MODE, }, - /// Reference clock detection enable (50 or 60 Hz) - REFCKON: u1, - /// Bypass the shadow registers - BYPSHAD: u1, - /// Hour format - FMT: packed union { - raw: u1, - value: FMT, + /// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. + PRTCFG: packed union { + raw: u2, + value: PRTCFG, }, - reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, - /// Wakeup timer enable - WUTE: u1, - /// Timestamp enable - TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, - /// Wakeup timer interrupt enable - WUTIE: u1, - /// Timestamp interrupt enable - TSIE: u1, - /// Add 1 hour (summer time change) - ADD1H: u1, - /// Subtract 1 hour (winter time change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output selection - COSEL: packed union { + reserved5: u1, + /// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. + DS: packed union { + raw: u3, + value: DS, + }, + /// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. + LSBFIRST: packed union { raw: u1, - value: COSEL, + value: LSBFIRST, }, - /// Output polarity - POL: packed union { + /// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. + CKSTR: packed union { raw: u1, - value: POL, + value: CKSTR, }, - /// Output selection - OSEL: packed union { + /// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. + SYNCEN: packed union { raw: u2, - value: OSEL, + value: SYNCEN, }, - /// Calibration output enable - COE: u1, - padding: u8, - }), - /// Initialization and status register - ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, - /// Wakeup timer write enabled - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Enter Initialization mode - INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, - /// Wakeup timer flag - WUTF: u1, - /// Timestamp flag - TSF: u1, - /// Timestamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, - /// Recalibration pending flag - RECALPF: packed union { + /// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. + MONO: packed union { raw: u1, - value: RECALPF, + value: MONO, }, - padding: u15, - }), - /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, - padding: u9, - }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, - padding: u16, - }), - reserved28: [4]u8, - /// Alarm register - ALRMR: [2]mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm seconds mask - MSK1: packed union { + /// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. + OUTDRIV: packed union { raw: u1, - value: ALRMR_MSK, + value: OUTDRIV, }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm minutes mask - MSK2: packed union { + reserved16: u2, + /// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. + SAIEN: u1, + /// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. + DMAEN: u1, + reserved19: u1, + /// No fixed divider between MCLK and FS + NODIV: packed union { raw: u1, - value: ALRMR_MSK, + value: NODIV, }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: ALRMR_PM, + /// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: + MCKDIV: u6, + /// Oversampling ratio for master clock + OSR: u1, + /// Master clock generation enable + MCKEN: u1, + padding: u4, + }), + /// Configuration register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// FIFO threshold. This bit is set and cleared by software. + FTH: packed union { + raw: u3, + value: FTH, }, - /// Alarm hours mask - MSK3: packed union { + /// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. + FFLUSH: u1, + /// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. + TRIS: u1, + /// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. + MUTE: u1, + /// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. + MUTEVAL: packed union { raw: u1, - value: ALRMR_MSK, + value: MUTEVAL, }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { + /// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. + MUTECNT: u6, + /// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. + CPL: packed union { raw: u1, - value: ALRMR_WDSEL, + value: CPL, }, - /// Alarm date mask - MSK4: packed union { - raw: u1, - value: ALRMR_MSK, + /// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. + COMP: packed union { + raw: u2, + value: COMP, }, - }), - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: u8, - padding: u24, - }), - /// Sub second register - SSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, padding: u16, }), - /// Shift control register - SHIFTR: mmio.Mmio(packed struct(u32) { - /// Subtract a fraction of a second - SUBFS: u15, - reserved31: u16, - /// Add one second - ADD1S: u1, - }), - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, + /// This register has no meaning in AC97 and SPDIF audio protocol + FRCR: mmio.Mmio(packed struct(u32) { + /// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. + FRL: u8, + /// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. + FSALL: u7, reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { + /// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. + FSDEF: u1, + /// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + FSPOL: packed union { raw: u1, - value: AMPM, + value: FSPOL, }, - padding: u9, - }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding: u16, - }), - /// Timestamp sub second register - TSSSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, - }), - /// Calibration register - CALR: mmio.Mmio(packed struct(u32) { - /// Calibration minus - CALM: u9, - reserved13: u4, - /// Use a 16-second calibration cycle period - CALW16: packed union { + /// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + FSOFF: packed union { raw: u1, - value: CALW16, + value: FSOFF, }, - /// Use an 8-second calibration cycle period - CALW8: packed union { - raw: u1, - value: CALW8, + padding: u13, + }), + /// This register has no meaning in AC97 and SPDIF audio protocol + SLOTR: mmio.Mmio(packed struct(u32) { + /// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + FBOFF: u5, + reserved6: u1, + /// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + SLOTSZ: packed union { + raw: u2, + value: SLOTSZ, }, - /// Increase frequency of RTC by 488.5 ppm - CALP: packed union { - raw: u1, - value: CALP, + /// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + NBSLOT: u4, + reserved16: u4, + /// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + SLOTEN: packed union { + raw: u16, + value: SLOTEN, }, - padding: u16, }), - /// Tamper configuration register - TAMPCR: mmio.Mmio(packed struct(u32) { - /// Tamper detection enable - TAMPE: u1, - /// Active level for tamper - TAMPTRG: packed union { + /// Interrupt mask register 2 + IM: mmio.Mmio(packed struct(u32) { + /// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. + OVRUDRIE: u1, + /// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. + MUTEDETIE: u1, + /// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. + WCKCFGIE: u1, + /// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, + FREQIE: u1, + /// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. + CNRDYIE: u1, + /// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + AFSDETIE: u1, + /// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + LFSDETIE: u1, + padding: u25, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. + OVRUDR: u1, + /// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. + MUTEDET: u1, + /// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. + WCKCFG: packed union { raw: u1, - value: TAMPTRG, - }, - /// Tamper interrupt enable - TAMPIE: u1, - reserved7: u4, - /// Activate timestamp on tamper detection event - TAMPTS: u1, - /// Tamper sampling frequency - TAMPFREQ: packed union { - raw: u3, - value: TAMPFREQ, - }, - /// Tamper filter count - TAMPFLT: packed union { - raw: u2, - value: TAMPFLT, - }, - /// Tamper precharge duration - TAMPPRCH: packed union { - raw: u2, - value: TAMPPRCH, + value: WCKCFG, }, - /// Tamper pull-up disable - TAMPPUDIS: packed union { + /// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. + FREQ: u1, + /// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. + CNRDY: packed union { raw: u1, - value: TAMPPUDIS, + value: CNRDY, + }, + /// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. + AFSDET: u1, + /// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register + LFSDET: u1, + reserved16: u9, + /// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: + FLVL: packed union { + raw: u3, + value: FLVL, }, - /// Tamper interrupt enable - TAMPXIE: u1, - /// Tamper no erase - TAMPXNOERASE: u1, - /// Tamper mask flag - TAMPXMF: u1, padding: u13, }), - /// Alarm sub second register - ALRMSSR: [2]mmio.Mmio(packed struct(u32) { - /// Sub seconds value - SS: u15, - reserved24: u9, - /// Mask the most-significant bits starting at this bit - MASKSS: u4, - padding: u4, + /// Clear flag register + CLRFR: mmio.Mmio(packed struct(u32) { + /// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. + COVRUDR: u1, + /// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. + CMUTEDET: u1, + /// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. + CWCKCFG: u1, + reserved4: u1, + /// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. + CCNRDY: u1, + /// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. + CAFSDET: u1, + /// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. + CLFSDET: u1, + padding: u25, }), - /// Option register - OR: mmio.Mmio(packed struct(u32) { - /// RTC_ALARM on PC13 output type - RTC_ALARM_TYPE: u1, - /// RTC_ALARM on PC13 output type - RTC_OUT_RMP: u1, - padding: u30, + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. + DATA: u32, }), - /// Backup register - BKPR: [5]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, + }; + + /// Serial audio interface + pub const SAI = extern struct { + /// Global configuration register + GCR: mmio.Mmio(packed struct(u32) { + /// Synchronization inputs + SYNCIN: u2, + reserved4: u2, + /// Synchronization outputs These bits are set and cleared by software. + SYNCOUT: u2, + padding: u26, + }), + /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + CH: u32, + reserved68: [60]u8, + /// PDM control register + PDMCR: mmio.Mmio(packed struct(u32) { + /// PDM enable + PDMEN: u1, + reserved4: u3, + /// Number of microphones + MICNBR: u2, + reserved8: u2, + /// Clock enable of bitstream clock number 1 + CKEN: u1, + padding: u23, + }), + /// PDM delay register + PDMDLY: mmio.Mmio(packed struct(u32) { + /// Delay line adjust for first microphone of pair 1 + DLYML: u3, + reserved4: u1, + /// Delay line adjust for second microphone of pair 1 + DLYMR: u3, + padding: u25, }), }; }; - pub const rcc_l0 = struct { - pub const HPRE = enum(u4) { - /// system clock not divided - Div1 = 0x0, - /// system clock divided by 2 - Div2 = 0x8, - /// system clock divided by 4 - Div4 = 0x9, - /// system clock divided by 8 - Div8 = 0xa, - /// system clock divided by 16 - Div16 = 0xb, - /// system clock divided by 64 - Div64 = 0xc, - /// system clock divided by 128 - Div128 = 0xd, - /// system clock divided by 256 - Div256 = 0xe, - /// system clock divided by 512 - Div512 = 0xf, - _, + pub const sai_v4_4pdm = struct { + pub const CKSTR = enum(u1) { + /// Data strobing edge is falling edge of SCK + FallingEdge = 0x0, + /// Data strobing edge is rising edge of SCK + RisingEdge = 0x1, }; - pub const I2CSEL = enum(u2) { - /// APB clock selected as peripheral clock - PCLK1 = 0x0, - /// System clock selected as peripheral clock - SYS = 0x1, - /// HSI clock selected as peripheral clock - HSI = 0x2, - _, + pub const CNRDY = enum(u1) { + /// External AC’97 Codec is ready + Ready = 0x0, + /// External AC’97 Codec is not ready + NotReady = 0x1, }; - pub const LPTIMSEL = enum(u2) { - /// APB clock selected as Timer clock - PCLK1 = 0x0, - /// LSI clock selected as Timer clock - LSI = 0x1, - /// HSI clock selected as Timer clock - HSI = 0x2, - /// LSE clock selected as Timer clock - LSE = 0x3, + pub const COMP = enum(u2) { + /// No companding algorithm + NoCompanding = 0x0, + /// μ-Law algorithm + MuLaw = 0x2, + /// A-Law algorithm + ALaw = 0x3, + _, }; - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium low driving capability - MediumLow = 0x1, - /// Medium high driving capability - MediumHigh = 0x2, - /// High driving capability - High = 0x3, + pub const CPL = enum(u1) { + /// 1’s complement representation + OnesComplement = 0x0, + /// 2’s complement representation + TwosComplement = 0x1, }; - pub const MCOPRE = enum(u3) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x1, - /// Division by 4 - Div4 = 0x2, - /// Division by 8 - Div8 = 0x3, - /// Division by 16 - Div16 = 0x4, + pub const DS = enum(u3) { + /// 8 bits + Bit8 = 0x2, + /// 10 bits + Bit10 = 0x3, + /// 16 bits + Bit16 = 0x4, + /// 20 bits + Bit20 = 0x5, + /// 24 bits + Bit24 = 0x6, + /// 32 bits + Bit32 = 0x7, _, }; - pub const MCOSEL = enum(u4) { - /// No clock - DISABLE = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI oscillator clock selected - HSI = 0x2, - /// MSI oscillator clock selected - MSI = 0x3, - /// HSE oscillator clock selected - HSE = 0x4, - /// PLL clock selected - PLL = 0x5, - /// LSI oscillator clock selected - LSI = 0x6, - /// LSE oscillator clock selected - LSE = 0x7, + pub const FLVL = enum(u3) { + /// FIFO empty + Empty = 0x0, + /// FIFO <= 1⁄4 but not empty + Quarter1 = 0x1, + /// 1⁄4 < FIFO <= 1⁄2 + Quarter2 = 0x2, + /// 1⁄2 < FIFO <= 3⁄4 + Quarter3 = 0x3, + /// 3⁄4 < FIFO but not full + Quarter4 = 0x4, + /// FIFO full + Full = 0x5, _, }; - pub const MSIRANGE = enum(u3) { - /// range 0 around 65.536 kHz - Range66K = 0x0, - /// range 1 around 131.072 kHz - Range131K = 0x1, - /// range 2 around 262.144 kHz - Range262K = 0x2, - /// range 3 around 524.288 kHz - Range524K = 0x3, - /// range 4 around 1.048 MHz - Range1M = 0x4, - /// range 5 around 2.097 MHz (reset value) - Range2M = 0x5, - /// range 6 around 4.194 MHz - Range4M = 0x6, - _, + pub const FSOFF = enum(u1) { + /// FS is asserted on the first bit of the slot 0 + OnFirst = 0x0, + /// FS is asserted one bit before the first bit of the slot 0 + BeforeFirst = 0x1, }; - pub const PLLDIV = enum(u2) { - /// PLLVCO / 2 - Div2 = 0x1, - /// PLLVCO / 3 - Div3 = 0x2, - /// PLLVCO / 4 - Div4 = 0x3, - _, + pub const FSPOL = enum(u1) { + /// FS is active low (falling edge) + FallingEdge = 0x0, + /// FS is active high (rising edge) + RisingEdge = 0x1, }; - pub const PLLMUL = enum(u4) { - /// PLL clock entry x 3 - Mul3 = 0x0, - /// PLL clock entry x 4 - Mul4 = 0x1, - /// PLL clock entry x 6 - Mul6 = 0x2, - /// PLL clock entry x 8 - Mul8 = 0x3, - /// PLL clock entry x 12 - Mul12 = 0x4, - /// PLL clock entry x 16 - Mul16 = 0x5, - /// PLL clock entry x 24 - Mul24 = 0x6, - /// PLL clock entry x 32 - Mul32 = 0x7, - /// PLL clock entry x 48 - Mul48 = 0x8, + pub const FTH = enum(u3) { + /// FIFO empty + Empty = 0x0, + /// 1⁄4 FIFO + Quarter1 = 0x1, + /// 1⁄2 FIFO + Quarter2 = 0x2, + /// 3⁄4 FIFO + Quarter3 = 0x3, + /// FIFO full + Full = 0x4, _, }; - pub const PLLSRC = enum(u1) { - /// HSI selected as PLL input clock - HSI = 0x0, - /// HSE selected as PLL input clock - HSE = 0x1, + pub const LSBFIRST = enum(u1) { + /// Data are transferred with MSB first + MsbFirst = 0x0, + /// Data are transferred with LSB first + LsbFirst = 0x1, }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, + pub const MODE = enum(u2) { + /// Master transmitter + MasterTx = 0x0, + /// Master receiver + MasterRx = 0x1, + /// Slave transmitter + SlaveTx = 0x2, + /// Slave receiver + SlaveRx = 0x3, }; - pub const RTCPRE = enum(u2) { - /// HSE divided by 2 - Div2 = 0x0, - /// HSE divided by 4 - Div4 = 0x1, - /// HSE divided by 8 - Div8 = 0x2, - /// HSE divided by 16 - Div16 = 0x3, + pub const MONO = enum(u1) { + /// Stereo mode + Stereo = 0x0, + /// Mono mode + Mono = 0x1, }; - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock - HSE = 0x3, + pub const MUTEVAL = enum(u1) { + /// Bit value 0 is sent during the mute mode + SendZero = 0x0, + /// Last values are sent during the mute mode + SendLast = 0x1, }; - pub const STOPWUCK = enum(u1) { - /// Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock - MSI = 0x0, - /// Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI/4 if HSIDIVEN=1) - HSI = 0x1, + pub const NODIV = enum(u1) { + /// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + MasterClock = 0x0, + /// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + NoDiv = 0x1, }; - pub const SW = enum(u2) { - /// MSI oscillator used as system clock - MSI = 0x0, - /// HSI oscillator used as system clock - HSI = 0x1, - /// HSE oscillator used as system clock - HSE = 0x2, - /// PLL used as system clock - PLL1_R = 0x3, + pub const OUTDRIV = enum(u1) { + /// Audio block output driven when SAIEN is set + OnStart = 0x0, + /// Audio block output driven immediately after the setting of this bit + Immediately = 0x1, }; - pub const UARTSEL = enum(u2) { - /// APB clock selected as peripheral clock - PCLK1 = 0x0, - /// System clock selected as peripheral clock - SYS = 0x1, - /// HSI clock selected as peripheral clock - HSI = 0x2, - /// LSE clock selected as peripheral clock - LSE = 0x3, + pub const PRTCFG = enum(u2) { + /// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + Free = 0x0, + /// SPDIF protocol + Spdif = 0x1, + /// AC’97 protocol + Ac97 = 0x2, + _, }; - pub const USART1SEL = enum(u2) { - /// APB clock selected as peripheral clock - PCLK2 = 0x0, - /// System clock selected as peripheral clock - SYS = 0x1, - /// HSI clock selected as peripheral clock - HSI = 0x2, - /// LSE clock selected as peripheral clock - LSE = 0x3, + pub const SLOTEN = enum(u16) { + /// Inactive slot + Inactive = 0x0, + /// Active slot + Active = 0x1, + _, }; - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// 16 MHz high-speed internal clock enable - HSION: u1, - /// High-speed internal clock enable bit for some IP kernels - HSIKERON: u1, - /// Internal high-speed clock ready flag - HSIRDY: u1, - /// HSIDIVEN - HSIDIVEN: u1, - /// HSIDIVF - HSIDIVF: u1, - /// 16 MHz high-speed internal clock output enable - HSIOUTEN: u1, - reserved8: u2, - /// MSI clock enable - MSION: u1, - /// MSI clock ready flag - MSIRDY: u1, - reserved16: u6, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE clock bypass - HSEBYP: u1, - /// Clock security system on HSE enable - CSSHSEON: u1, - /// TC/LCD prescaler - RTCPRE: packed union { + pub const SLOTSZ = enum(u2) { + /// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) + DataSize = 0x0, + /// 16-bit + Bit16 = 0x1, + /// 32-bit + Bit32 = 0x2, + _, + }; + + pub const SYNCEN = enum(u2) { + /// audio sub-block in asynchronous mode + Asynchronous = 0x0, + /// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode + Internal = 0x1, + /// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + External = 0x2, + _, + }; + + pub const WCKCFG = enum(u1) { + /// Clock configuration is correct + Correct = 0x0, + /// Clock configuration does not respect the rule concerning the frame length specification + Wrong = 0x1, + }; + + /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + pub const CH = extern struct { + /// Configuration register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// SAIx audio block mode immediately + MODE: packed union { raw: u2, - value: RTCPRE, + value: MODE, }, - reserved24: u2, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding: u6, - }), - /// Internal clock sources calibration register - ICSCR: mmio.Mmio(packed struct(u32) { - /// nternal high speed clock calibration - HSICAL: u8, - /// High speed internal clock trimming - HSITRIM: u5, - /// MSI clock ranges - MSIRANGE: packed union { + /// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. + PRTCFG: packed union { + raw: u2, + value: PRTCFG, + }, + reserved5: u1, + /// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. + DS: packed union { raw: u3, - value: MSIRANGE, + value: DS, }, - /// MSI clock calibration - MSICAL: u8, - /// MSI clock trimming - MSITRIM: u8, - }), - reserved12: [4]u8, - /// Clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u2, - value: SW, + /// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. + LSBFIRST: packed union { + raw: u1, + value: LSBFIRST, }, - /// System clock switch status - SWS: packed union { + /// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. + CKSTR: packed union { + raw: u1, + value: CKSTR, + }, + /// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. + SYNCEN: packed union { raw: u2, - value: SW, + value: SYNCEN, }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, + /// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. + MONO: packed union { + raw: u1, + value: MONO, }, - /// APB low-speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, + /// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. + OUTDRIV: packed union { + raw: u1, + value: OUTDRIV, }, - /// APB high-speed prescaler (APB2) - PPRE2: packed union { + reserved16: u2, + /// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. + SAIEN: u1, + /// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. + DMAEN: u1, + reserved19: u1, + /// No fixed divider between MCLK and FS + NODIV: packed union { + raw: u1, + value: NODIV, + }, + /// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: + MCKDIV: u6, + /// Oversampling ratio for master clock + OSR: u1, + /// Master clock generation enable + MCKEN: u1, + padding: u4, + }), + /// Configuration register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// FIFO threshold. This bit is set and cleared by software. + FTH: packed union { raw: u3, - value: PPRE, + value: FTH, }, - reserved15: u1, - /// Wake-up from stop clock selection - STOPWUCK: packed union { + /// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. + FFLUSH: u1, + /// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. + TRIS: u1, + /// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. + MUTE: u1, + /// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. + MUTEVAL: packed union { raw: u1, - value: STOPWUCK, + value: MUTEVAL, }, - /// PLL entry clock source - PLLSRC: packed union { + /// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. + MUTECNT: u6, + /// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. + CPL: packed union { raw: u1, - value: PLLSRC, + value: CPL, }, - reserved18: u1, - /// PLL multiplication factor - PLLMUL: packed union { - raw: u4, - value: PLLMUL, + /// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. + COMP: packed union { + raw: u2, + value: COMP, }, - /// PLL output division - PLLDIV: packed union { + padding: u16, + }), + /// This register has no meaning in AC97 and SPDIF audio protocol + FRCR: mmio.Mmio(packed struct(u32) { + /// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. + FRL: u8, + /// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. + FSALL: u7, + reserved16: u1, + /// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. + FSDEF: u1, + /// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + FSPOL: packed union { + raw: u1, + value: FSPOL, + }, + /// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. + FSOFF: packed union { + raw: u1, + value: FSOFF, + }, + padding: u13, + }), + /// This register has no meaning in AC97 and SPDIF audio protocol + SLOTR: mmio.Mmio(packed struct(u32) { + /// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + FBOFF: u5, + reserved6: u1, + /// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + SLOTSZ: packed union { raw: u2, - value: PLLDIV, + value: SLOTSZ, }, - /// Microcontroller clock output selection - MCOSEL: packed union { - raw: u4, - value: MCOSEL, + /// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + NBSLOT: u4, + reserved16: u4, + /// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. + SLOTEN: packed union { + raw: u16, + value: SLOTEN, + }, + }), + /// Interrupt mask register 2 + IM: mmio.Mmio(packed struct(u32) { + /// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. + OVRUDRIE: u1, + /// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. + MUTEDETIE: u1, + /// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. + WCKCFGIE: u1, + /// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, + FREQIE: u1, + /// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. + CNRDYIE: u1, + /// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + AFSDETIE: u1, + /// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. + LFSDETIE: u1, + padding: u25, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. + OVRUDR: u1, + /// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. + MUTEDET: u1, + /// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. + WCKCFG: packed union { + raw: u1, + value: WCKCFG, + }, + /// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. + FREQ: u1, + /// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. + CNRDY: packed union { + raw: u1, + value: CNRDY, }, - /// Microcontroller clock output prescaler - MCOPRE: packed union { + /// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. + AFSDET: u1, + /// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register + LFSDET: u1, + reserved16: u9, + /// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: + FLVL: packed union { raw: u3, - value: MCOPRE, + value: FLVL, }, - padding: u1, + padding: u13, }), - /// Clock interrupt enable register - CIER: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYIE: u1, - /// LSE ready interrupt flag - LSERDYIE: u1, - /// HSI ready interrupt flag - HSIRDYIE: u1, - /// HSE ready interrupt flag - HSERDYIE: u1, - /// PLL ready interrupt flag - PLLRDYIE: u1, - /// MSI ready interrupt flag - MSIRDYIE: u1, - reserved7: u1, - /// LSE CSS interrupt flag - CSSLSE: u1, - padding: u24, + /// Clear flag register + CLRFR: mmio.Mmio(packed struct(u32) { + /// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. + COVRUDR: u1, + /// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. + CMUTEDET: u1, + /// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. + CWCKCFG: u1, + reserved4: u1, + /// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. + CCNRDY: u1, + /// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. + CAFSDET: u1, + /// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. + CLFSDET: u1, + padding: u25, }), - /// Clock interrupt flag register - CIFR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// PLL ready interrupt flag - PLLRDYF: u1, - /// MSI ready interrupt flag - MSIRDYF: u1, - reserved7: u1, - /// LSE Clock Security System Interrupt flag - CSSLSEF: u1, - /// Clock Security System Interrupt flag - CSSHSEF: u1, - padding: u23, + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. + DATA: u32, }), - /// Clock interrupt clear register - CICR: mmio.Mmio(packed struct(u32) { - /// LSI ready Interrupt clear - LSIRDYC: u1, - /// LSE ready Interrupt clear - LSERDYC: u1, - /// HSI ready Interrupt clear - HSIRDYC: u1, - /// HSE ready Interrupt clear - HSERDYC: u1, - /// PLL ready Interrupt clear - PLLRDYC: u1, - /// MSI ready Interrupt clear - MSIRDYC: u1, - reserved7: u1, - /// LSE Clock Security System Interrupt clear - CSSLSEC: u1, - /// Clock Security System Interrupt clear - CSSHSEC: u1, + }; + + /// Serial audio interface + pub const SAI = extern struct { + /// Global configuration register + GCR: mmio.Mmio(packed struct(u32) { + /// Synchronization inputs + SYNCIN: u2, + reserved4: u2, + /// Synchronization outputs These bits are set and cleared by software. + SYNCOUT: u2, + padding: u26, + }), + /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + CH: u32, + reserved68: [60]u8, + /// PDM control register + PDMCR: mmio.Mmio(packed struct(u32) { + /// PDM enable + PDMEN: u1, + reserved4: u3, + /// Number of microphones + MICNBR: u2, + reserved8: u2, + /// Clock enable of bitstream clock number 1 + CKEN: u1, padding: u23, }), - /// GPIO reset register - GPIORSTR: mmio.Mmio(packed struct(u32) { - /// I/O port A reset - GPIOARST: u1, - /// I/O port B reset - GPIOBRST: u1, - /// I/O port A reset - GPIOCRST: u1, - /// I/O port D reset - GPIODRST: u1, - /// I/O port E reset - GPIOERST: u1, - reserved7: u2, - /// I/O port H reset - GPIOHRST: u1, - padding: u24, + /// PDM delay register + PDMDLY: mmio.Mmio(packed struct(u32) { + /// Delay line adjust for first microphone of pair 1 + DLYML: u3, + reserved4: u1, + /// Delay line adjust for second microphone of pair 1 + DLYMR: u3, + padding: u25, }), - /// AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - /// DMA reset - DMA1RST: u1, - reserved8: u7, - /// Memory interface reset - MIFRST: u1, - reserved12: u3, - /// Test integration module reset - CRCRST: u1, - reserved16: u3, - /// Touch Sensing reset - TSCRST: u1, - reserved20: u3, - /// Random Number Generator module reset - RNGRST: u1, - reserved24: u3, - /// Crypto module reset - CRYPRST: u1, + }; + }; + + pub const sdadc_v1 = struct { + /// Sigma-delta analog-to-digital converter. + pub const SDADC = extern struct { + /// control register 1. + CR1: mmio.Mmio(packed struct(u32) { + /// End of calibration interrupt enable. + EOCALIE: u1, + /// Injected end of conversion interrupt enable. + JEOCIE: u1, + /// Injected data overrun interrupt enable. + JOVRIE: u1, + /// Regular end of conversion interrupt enable. + REOCIE: u1, + /// Regular data overrun interrupt enable. + ROVRIE: u1, + reserved8: u3, + /// Reference voltage selection. + REFV: u2, + /// Slow clock mode enable. + SLOWCK: u1, + /// Enter Standby mode when idle. + SBI: u1, + /// Enter power down mode when idle. + PDI: u1, + reserved14: u1, + /// Launch a injected conversion synchronously with SDADC1. + JSYNC: u1, + /// Launch regular conversion synchronously with SDADC1. + RSYNC: u1, + /// DMA channel enabled to read data for the injected channel group. + JDMAEN: u1, + /// DMA channel enabled to read data for the regular channel. + RDMAEN: u1, + reserved31: u13, + /// Initialization mode request. + INIT: u1, + }), + /// control register 2. + CR2: mmio.Mmio(packed struct(u32) { + /// SDADC enable. + ADON: u1, + /// Number of calibration sequences to be performed (number of valid configurations). + CALIBCNT: u2, + reserved4: u1, + /// Start calibration. + STARTCALIB: u1, + /// Continuous mode selection for injected conversions. + JCONT: u1, + /// Delay start of injected conversions. + JDS: u1, + reserved8: u1, + /// Trigger signal selection for launching injected conversions. + JEXTSEL: u4, + reserved13: u1, + /// Trigger enable and trigger edge selection for injected conversions. + JEXTEN: u2, + /// Start a conversion of the injected group of channels. + JSWSTART: u1, + /// Regular channel selection. + RCH: u4, + reserved22: u2, + /// Continuous mode selection for regular conversions. + RCONT: u1, + /// Software start of a conversion on the regular channel. + RSWSTART: u1, + /// Fast conversion mode selection. + FAST: u1, padding: u7, }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// System configuration controller reset - SYSCFGRST: u1, + /// interrupt and status register. + ISR: mmio.Mmio(packed struct(u32) { + /// End of calibration flag. + EOCALF: u1, + /// End of injected conversion flag. + JEOCF: u1, + /// Injected conversion overrun flag. + JOVRF: u1, + /// End of regular conversion flag. + REOCF: u1, + /// Regular conversion overrun flag. + ROVRF: u1, + reserved12: u7, + /// Calibration in progress status. + CALIBIP: u1, + /// Injected conversion in progress status. + JCIP: u1, + /// Regular conversion in progress status. + RCIP: u1, + /// Stabilization in progress status. + STABIP: u1, + reserved31: u15, + /// Initialization mode is ready. + INITRDY: u1, + }), + /// interrupt and status clear register. + CLRISR: mmio.Mmio(packed struct(u32) { + /// Clear the end of calibration flag. + CLREOCALF: u1, reserved2: u1, - /// TIM21 timer reset - TIM21RST: u1, - reserved5: u2, - /// TIM22 timer reset - TIM22RST: u1, - reserved9: u3, - /// ADC interface reset - ADCRST: u1, - reserved12: u2, - /// SPI 1 reset - SPI1RST: u1, - reserved14: u1, - /// USART1 reset - USART1RST: u1, - reserved22: u7, - /// DBG reset - DBGRST: u1, - padding: u9, + /// Clear the injected conversion overrun flag. + CLRJOVRF: u1, + reserved4: u1, + /// Clear the regular conversion overrun flag. + CLRROVRF: u1, + padding: u27, }), - /// APB1 peripheral reset register - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - reserved4: u2, - /// Timer 6 reset - TIM6RST: u1, - /// Timer 7 reset - TIM7RST: u1, - reserved11: u5, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI2 reset - SPI2RST: u1, - reserved17: u2, - /// USART2 reset - USART2RST: u1, - /// LPUART1 reset - LPUART1RST: u1, - /// USART4 reset - USART4RST: u1, - /// USART5 reset - USART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// USB reset - USBRST: u1, - reserved27: u3, - /// Clock recovery system reset - CRSRST: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - /// I2C3 reset - I2C3RST: u1, - /// Low power timer reset - LPTIM1RST: u1, + reserved20: [4]u8, + /// injected channel group selection register. + JCHGR: mmio.Mmio(packed struct(u32) { + /// Injected channel group selection. + JCHG: u9, + padding: u23, }), - /// GPIO clock enable register - GPIOENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port A clock enable - GPIOCEN: u1, - /// I/O port D clock enable - GPIODEN: u1, - /// IO port E clock enable - GPIOEEN: u1, - reserved7: u2, - /// I/O port H clock enable - GPIOHEN: u1, - padding: u24, + reserved32: [8]u8, + /// configuration 0 register. + CONFR: [3]mmio.Mmio(packed struct(u32) { + /// Twelve-bit calibration offset for configuration 0. + OFFSET: u12, + reserved20: u8, + /// Gain setting for configuration 0. + GAIN: u3, + reserved26: u3, + /// Single-ended mode for configuration 0. + SE: u2, + reserved30: u2, + /// Common mode for configuration 0. + COMMON: u2, }), - /// AHB peripheral clock enable register - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA clock enable - DMA1EN: u1, - reserved8: u7, - /// NVM interface clock enable - MIFEN: u1, - reserved12: u3, - /// CRC clock enable - CRCEN: u1, - reserved16: u3, - /// Touch Sensing clock enable - TSCEN: u1, - reserved20: u3, - /// Random Number Generator clock enable - RNGEN: u1, - reserved24: u3, - /// Crypto clock enable - CRYPEN: u1, + reserved64: [20]u8, + /// channel configuration register 1. + CONFCHR1: mmio.Mmio(packed struct(u32) { + /// CONFCH0. + CONFCH: u2, + padding: u30, + }), + /// channel configuration register 2. + CONFCHR2: mmio.Mmio(packed struct(u32) { + /// Channel 8 configuration. + CONFCH: u2, + padding: u30, + }), + reserved96: [24]u8, + /// data register for injected group. + JDATAR: mmio.Mmio(packed struct(u32) { + /// Injected group conversion data. + JDATA: u16, + reserved24: u8, + /// Injected channel most recently converted. + JDATACH: u4, + padding: u4, + }), + /// data register for the regular channel. + RDATAR: mmio.Mmio(packed struct(u32) { + /// Regular channel conversion data. + RDATA: u16, + padding: u16, + }), + reserved112: [8]u8, + /// SDADC1 and SDADC2 injected data register. + JDATA12R: u32, + /// SDADC1 and SDADC2 regular data register. + RDATA12R: u32, + /// SDADC1 and SDADC3 injected data register. + JDATA13R: u32, + /// SDADC1 and SDADC3 regular data register. + RDATA13R: u32, + }; + }; + + pub const sdmmc_v1 = struct { + /// Secure digital input/output interface + pub const SDMMC = extern struct { + /// power control register + POWER: mmio.Mmio(packed struct(u32) { + /// PWRCTRL + PWRCTRL: u2, + padding: u30, + }), + /// SDI clock control register + CLKCR: mmio.Mmio(packed struct(u32) { + /// Clock divide factor + CLKDIV: u8, + /// Clock enable bit + CLKEN: u1, + /// Power saving configuration bit + PWRSAV: u1, + /// Clock divider bypass enable bit + BYPASS: u1, + /// Wide bus mode enable bit + WIDBUS: u2, + /// SDIO_CK dephasing selection bit + NEGEDGE: u1, + /// HW Flow Control enable + HWFC_EN: u1, + padding: u17, + }), + /// argument register + ARGR: mmio.Mmio(packed struct(u32) { + /// Command argument + CMDARG: u32, + }), + /// command register + CMDR: mmio.Mmio(packed struct(u32) { + /// Command index + CMDINDEX: u6, + /// Wait for response bits + WAITRESP: u2, + /// CPSM waits for interrupt request + WAITINT: u1, + /// CPSM Waits for ends of data transfer (CmdPend internal signal) + WAITPEND: u1, + /// Command path state machine (CPSM) Enable bit + CPSMEN: u1, + /// SD I/O suspend command + SDIOSuspend: u1, + padding: u20, + }), + /// command response register + RESPCMDR: mmio.Mmio(packed struct(u32) { + /// Response command index + RESPCMD: u6, + padding: u26, + }), + /// response 1..4 register + RESPR: [4]mmio.Mmio(packed struct(u32) { + /// see Table 132 + CARDSTATUS: u32, + }), + /// data timer register + DTIMER: mmio.Mmio(packed struct(u32) { + /// Data timeout period + DATATIME: u32, + }), + /// data length register + DLENR: mmio.Mmio(packed struct(u32) { + /// Data length value + DATALENGTH: u25, padding: u7, }), - /// APB2 peripheral clock enable register - APB2ENR: mmio.Mmio(packed struct(u32) { - /// System configuration controller clock enable - SYSCFGEN: u1, - reserved2: u1, - /// TIM21 timer clock enable - TIM21EN: u1, - reserved5: u2, - /// TIM22 timer clock enable - TIM22EN: u1, - reserved7: u1, - /// Firewall clock enable - FWEN: u1, - reserved9: u1, - /// ADC clock enable - ADCEN: u1, + /// data control register + DCTRL: mmio.Mmio(packed struct(u32) { + /// DTEN + DTEN: u1, + /// Data transfer direction selection + DTDIR: u1, + /// Data transfer mode selection 1: Stream or SDIO multibyte data transfer + DTMODE: u1, + /// DMA enable bit + DMAEN: u1, + /// Data block size + DBLOCKSIZE: u4, + /// Read wait start + RWSTART: u1, + /// Read wait stop + RWSTOP: u1, + /// Read wait mode + RWMOD: u1, + /// SD I/O enable functions + SDIOEN: u1, + padding: u20, + }), + /// data counter register + DCNTR: mmio.Mmio(packed struct(u32) { + /// Data count value + DATACOUNT: u25, + padding: u7, + }), + /// status register + STAR: mmio.Mmio(packed struct(u32) { + /// Command response received (CRC check failed) + CCRCFAIL: u1, + /// Data block sent/received (CRC check failed) + DCRCFAIL: u1, + /// Command response timeout + CTIMEOUT: u1, + /// Data timeout + DTIMEOUT: u1, + /// Transmit FIFO underrun error + TXUNDERR: u1, + /// Received FIFO overrun error + RXOVERR: u1, + /// Command response received (CRC check passed) + CMDREND: u1, + /// Command sent (no response required) + CMDSENT: u1, + /// Data end (data counter, SDIDCOUNT, is zero) + DATAEND: u1, + /// Start bit not detected on all data signals in wide bus mode + STBITERR: u1, + /// Data block sent/received (CRC check passed) + DBCKEND: u1, + /// Command transfer in progress + CMDACT: u1, + /// Data transmit in progress + TXACT: u1, + /// Data receive in progress + RXACT: u1, + /// Transmit FIFO half empty: at least 8 words can be written into the FIFO + TXFIFOHE: u1, + /// Receive FIFO half full: there are at least 8 words in the FIFO + RXFIFOHF: u1, + /// Transmit FIFO full + TXFIFOF: u1, + /// Receive FIFO full + RXFIFOF: u1, + /// Transmit FIFO empty + TXFIFOE: u1, + /// Receive FIFO empty + RXFIFOE: u1, + /// Data available in transmit FIFO + TXDAVL: u1, + /// Data available in receive FIFO + RXDAVL: u1, + /// SDIO interrupt received + SDIOIT: u1, + padding: u9, + }), + /// interrupt clear register + ICR: mmio.Mmio(packed struct(u32) { + /// CCRCFAIL flag clear bit + CCRCFAILC: u1, + /// DCRCFAIL flag clear bit + DCRCFAILC: u1, + /// CTIMEOUT flag clear bit + CTIMEOUTC: u1, + /// DTIMEOUT flag clear bit + DTIMEOUTC: u1, + /// TXUNDERR flag clear bit + TXUNDERRC: u1, + /// RXOVERR flag clear bit + RXOVERRC: u1, + /// CMDREND flag clear bit + CMDRENDC: u1, + /// CMDSENT flag clear bit + CMDSENTC: u1, + /// DATAEND flag clear bit + DATAENDC: u1, + /// STBITERR flag clear bit + STBITERRC: u1, + /// DBCKEND flag clear bit + DBCKENDC: u1, + reserved22: u11, + /// SDIOIT flag clear bit + SDIOITC: u1, + padding: u9, + }), + /// mask register + MASKR: mmio.Mmio(packed struct(u32) { + /// Command CRC fail interrupt enable + CCRCFAILIE: u1, + /// Data CRC fail interrupt enable + DCRCFAILIE: u1, + /// Command timeout interrupt enable + CTIMEOUTIE: u1, + /// Data timeout interrupt enable + DTIMEOUTIE: u1, + /// Tx FIFO underrun error interrupt enable + TXUNDERRIE: u1, + /// Rx FIFO overrun error interrupt enable + RXOVERRIE: u1, + /// Command response received interrupt enable + CMDRENDIE: u1, + /// Command sent interrupt enable + CMDSENTIE: u1, + /// Data end interrupt enable + DATAENDIE: u1, + /// STBITERR interrupt enable + STBITERRE: u1, + /// Data block end interrupt enable + DBCKENDIE: u1, + /// Command acting interrupt enable + CMDACTIE: u1, + /// Data transmit acting interrupt enable + TXACTIE: u1, + /// Data receive acting interrupt enable + RXACTIE: u1, + /// Tx FIFO half empty interrupt enable + TXFIFOHEIE: u1, + /// Rx FIFO half full interrupt enable + RXFIFOHFIE: u1, + /// Tx FIFO full interrupt enable + TXFIFOFIE: u1, + /// Rx FIFO full interrupt enable + RXFIFOFIE: u1, + /// Tx FIFO empty interrupt enable + TXFIFOEIE: u1, + /// Rx FIFO empty interrupt enable + RXFIFOEIE: u1, + /// Data available in Tx FIFO interrupt enable + TXDAVLIE: u1, + /// Data available in Rx FIFO interrupt enable + RXDAVLIE: u1, + /// SDIO mode interrupt received interrupt enable + SDIOITIE: u1, + padding: u9, + }), + reserved72: [8]u8, + /// FIFO counter register + FIFOCNT: mmio.Mmio(packed struct(u32) { + /// Remaining number of words to be written to or read from the FIFO + FIFOCOUNT: u24, + padding: u8, + }), + reserved128: [52]u8, + /// data FIFO register + FIFOR: mmio.Mmio(packed struct(u32) { + /// Receive and transmit FIFO data + FIFOData: u32, + }), + }; + }; + + pub const sdmmc_v2 = struct { + /// SDMMC + pub const SDMMC = extern struct { + /// SDMMC power control register + POWER: mmio.Mmio(packed struct(u32) { + /// SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11. + PWRCTRL: u2, + /// Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence: + VSWITCH: u1, + /// Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response: + VSWITCHEN: u1, + /// Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). + DIRPOL: u1, + padding: u27, + }), + /// The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width. + CLKCR: mmio.Mmio(packed struct(u32) { + /// Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.. + CLKDIV: u10, reserved12: u2, - /// SPI1 clock enable - SPI1EN: u1, + /// Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: + PWRSAV: u1, reserved14: u1, - /// USART1 clock enable - USART1EN: u1, - reserved22: u7, - /// DBG clock enable - DBGEN: u1, - padding: u9, + /// Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) + WIDBUS: u2, + /// SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. + NEGEDGE: u1, + /// Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11. + HWFC_EN: u1, + /// Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0) + DDR: u1, + /// Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) + BUSSPEED: u1, + /// Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) + SELCLKRX: u2, + padding: u10, }), - /// APB1 peripheral clock enable register - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer2 clock enable - TIM2EN: u1, - /// Timer 3 clock enbale - TIM3EN: u1, - reserved4: u2, - /// Timer 6 clock enable - TIM6EN: u1, - /// Timer 7 clock enable - TIM7EN: u1, - reserved11: u5, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI2 clock enable - SPI2EN: u1, - reserved17: u2, - /// UART2 clock enable - USART2EN: u1, - /// LPUART1 clock enable - LPUART1EN: u1, - /// USART4 clock enable - USART4EN: u1, - /// USART5 clock enable - USART5EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - /// I2C2 clock enable - I2C2EN: u1, - /// USB clock enable - USBEN: u1, - reserved27: u3, - /// Clock recovery system clock enable - CRSEN: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - /// I2C3 clock enable - I2C3EN: u1, - /// Low power timer clock enable - LPTIM1EN: u1, + /// The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. + ARGR: mmio.Mmio(packed struct(u32) { + /// Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. + CMDARG: u32, }), - /// GPIO clock enable in sleep mode register - GPIOSMEN: mmio.Mmio(packed struct(u32) { - /// Port A clock enable during Sleep mode - GPIOASMEN: u1, - /// Port B clock enable during Sleep mode - GPIOBSMEN: u1, - /// Port C clock enable during Sleep mode - GPIOCSMEN: u1, - /// Port D clock enable during Sleep mode - GPIODSMEN: u1, - /// Port E clock enable during Sleep mode - GPIOESMEN: u1, - reserved7: u2, - /// Port H clock enable during Sleep mode - GPIOHSMEN: u1, - padding: u24, + /// The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). + CMDR: mmio.Mmio(packed struct(u32) { + /// Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. + CMDINDEX: u6, + /// The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent. + CMDTRANS: u1, + /// The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent. + CMDSTOP: u1, + /// Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. + WAITRESP: u2, + /// CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode. + WAITINT: u1, + /// CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card. + WAITPEND: u1, + /// Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0. + CPSMEN: u1, + /// Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state. + DTHOLD: u1, + /// Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) + BOOTMODE: u1, + /// Enable boot mode procedure. + BOOTEN: u1, + /// The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1. + CMDSUSPEND: u1, + padding: u15, + }), + /// SDMMC command response register + RESPCMDR: mmio.Mmio(packed struct(u32) { + /// Response command index + RESPCMD: u6, + padding: u26, + }), + /// The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. + RESPR: [4]mmio.Mmio(packed struct(u32) { + /// see Table 432 + CARDSTATUS: u32, + }), + /// The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. + DTIMER: mmio.Mmio(packed struct(u32) { + /// Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods. + DATATIME: u32, + }), + /// The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. + DLENR: mmio.Mmio(packed struct(u32) { + /// Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0. + DATALENGTH: u25, + padding: u7, + }), + /// The SDMMC_DCTRL register control the data path state machine (DPSM). + DCTRL: mmio.Mmio(packed struct(u32) { + /// Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards. + DTEN: u1, + /// Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + DTDIR: u1, + /// Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + DTMODE: u2, + /// Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered) + DBLOCKSIZE: u4, + /// Read wait start. If this bit is set, read wait operation starts. + RWSTART: u1, + /// Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state. + RWSTOP: u1, + /// Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + RWMOD: u1, + /// SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. + SDIOEN: u1, + /// Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + BOOTACKEN: u1, + /// FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs. + FIFORST: u1, + padding: u18, + }), + /// The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. + DCNTR: mmio.Mmio(packed struct(u32) { + /// Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect. + DATACOUNT: u25, + padding: u7, + }), + /// The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) + STAR: mmio.Mmio(packed struct(u32) { + /// Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + CCRCFAIL: u1, + /// Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + DCRCFAIL: u1, + /// Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. + CTIMEOUT: u1, + /// Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + DTIMEOUT: u1, + /// Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + TXUNDERR: u1, + /// Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + RXOVERR: u1, + /// Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + CMDREND: u1, + /// Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + CMDSENT: u1, + /// Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + DATAEND: u1, + /// Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + DHOLD: u1, + /// Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + DBCKEND: u1, + /// Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + DABORT: u1, + /// Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. + DPSMACT: u1, + /// Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. + CPSMACT: u1, + /// Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. + TXFIFOHE: u1, + /// Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. + RXFIFOHF: u1, + /// Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty. + TXFIFOF: u1, + /// Receive FIFO full This bit is cleared when one FIFO location becomes empty. + RXFIFOF: u1, + /// Transmit FIFO empty This bit is cleared when one FIFO location becomes full. + TXFIFOE: u1, + /// Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full. + RXFIFOE: u1, + /// Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt. + BUSYD0: u1, + /// end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + BUSYD0END: u1, + /// SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + SDIOIT: u1, + /// Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + ACKFAIL: u1, + /// Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + ACKTIMEOUT: u1, + /// Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + VSWEND: u1, + /// SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + CKSTOP: u1, + /// IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + IDMATE: u1, + /// IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. + IDMABTC: u1, + padding: u3, + }), + /// The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. + ICR: mmio.Mmio(packed struct(u32) { + /// CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. + CCRCFAILC: u1, + /// DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. + DCRCFAILC: u1, + /// CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. + CTIMEOUTC: u1, + /// DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. + DTIMEOUTC: u1, + /// TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. + TXUNDERRC: u1, + /// RXOVERR flag clear bit Set by software to clear the RXOVERR flag. + RXOVERRC: u1, + /// CMDREND flag clear bit Set by software to clear the CMDREND flag. + CMDRENDC: u1, + /// CMDSENT flag clear bit Set by software to clear the CMDSENT flag. + CMDSENTC: u1, + /// DATAEND flag clear bit Set by software to clear the DATAEND flag. + DATAENDC: u1, + /// DHOLD flag clear bit Set by software to clear the DHOLD flag. + DHOLDC: u1, + /// DBCKEND flag clear bit Set by software to clear the DBCKEND flag. + DBCKENDC: u1, + /// DABORT flag clear bit Set by software to clear the DABORT flag. + DABORTC: u1, + reserved21: u9, + /// BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag. + BUSYD0ENDC: u1, + /// SDIOIT flag clear bit Set by software to clear the SDIOIT flag. + SDIOITC: u1, + /// ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag. + ACKFAILC: u1, + /// ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag. + ACKTIMEOUTC: u1, + /// VSWEND flag clear bit Set by software to clear the VSWEND flag. + VSWENDC: u1, + /// CKSTOP flag clear bit Set by software to clear the CKSTOP flag. + CKSTOPC: u1, + /// IDMA transfer error clear bit Set by software to clear the IDMATE flag. + IDMATEC: u1, + /// IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag. + IDMABTCC: u1, + padding: u3, + }), + /// The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. + MASKR: mmio.Mmio(packed struct(u32) { + /// Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. + CCRCFAILIE: u1, + /// Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. + DCRCFAILIE: u1, + /// Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. + CTIMEOUTIE: u1, + /// Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. + DTIMEOUTIE: u1, + /// Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. + TXUNDERRIE: u1, + /// Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. + RXOVERRIE: u1, + /// Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. + CMDRENDIE: u1, + /// Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. + CMDSENTIE: u1, + /// Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. + DATAENDIE: u1, + /// Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. + DHOLDIE: u1, + /// Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. + DBCKENDIE: u1, + /// Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. + DABORTIE: u1, + reserved14: u2, + /// Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. + TXFIFOHEIE: u1, + /// Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. + RXFIFOHFIE: u1, + reserved17: u1, + /// Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. + RXFIFOFIE: u1, + /// Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. + TXFIFOEIE: u1, + reserved21: u2, + /// BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. + BUSYD0ENDIE: u1, + /// SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. + SDIOITIE: u1, + /// Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. + ACKFAILIE: u1, + /// Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. + ACKTIMEOUTIE: u1, + /// Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. + VSWENDIE: u1, + /// Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. + CKSTOPIE: u1, + reserved28: u1, + /// IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. + IDMABTCIE: u1, + padding: u3, }), - /// AHB peripheral clock enable in sleep mode register - AHBSMENR: mmio.Mmio(packed struct(u32) { - /// DMA clock enable during sleep mode - DMA1SMEN: u1, - reserved8: u7, - /// NVM interface clock enable during sleep mode - MIFSMEN: u1, - /// SRAM interface clock enable during sleep mode - SRAMSMEN: u1, - reserved12: u2, - /// CRC clock enable during sleep mode - CRCSMEN: u1, - reserved16: u3, - /// Touch Sensing clock enable during sleep mode - TSCSMEN: u1, - reserved20: u3, - /// Random Number Generator clock enable during sleep mode - RNGSMEN: u1, - reserved24: u3, - /// Crypto clock enable during sleep mode - CRYPSMEN: u1, + /// The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. + ACKTIMER: mmio.Mmio(packed struct(u32) { + /// Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods. + ACKTIME: u25, padding: u7, }), - /// APB2 peripheral clock enable in sleep mode register - APB2SMENR: mmio.Mmio(packed struct(u32) { - /// System configuration controller clock enable during sleep mode - SYSCFGSMEN: u1, - reserved2: u1, - /// TIM21 timer clock enable during sleep mode - TIM21SMEN: u1, - reserved5: u2, - /// TIM22 timer clock enable during sleep mode - TIM22SMEN: u1, - reserved9: u3, - /// ADC clock enable during sleep mode - ADCSMEN: u1, - reserved12: u2, - /// SPI1 clock enable during sleep mode - SPI1SMEN: u1, - reserved14: u1, - /// USART1 clock enable during sleep mode - USART1SMEN: u1, - reserved22: u7, - /// DBG clock enable during sleep mode - DBGSMEN: u1, - padding: u9, - }), - /// APB1 peripheral clock enable in sleep mode register - APB1SMENR: mmio.Mmio(packed struct(u32) { - /// Timer2 clock enable during sleep mode - TIM2SMEN: u1, - /// Timer 3 clock enable during sleep mode - TIM3SMEN: u1, - reserved4: u2, - /// Timer 6 clock enable during sleep mode - TIM6SMEN: u1, - /// Timer 7 clock enable during sleep mode - TIM7SMEN: u1, - reserved11: u5, - /// Window watchdog clock enable during sleep mode - WWDGSMEN: u1, - reserved14: u2, - /// SPI2 clock enable during sleep mode - SPI2SMEN: u1, - reserved17: u2, - /// UART2 clock enable during sleep mode - USART2SMEN: u1, - /// LPUART1 clock enable during sleep mode - LPUART1SMEN: u1, - /// USART4 clock enabe during sleep mode - USART4SMEN: u1, - /// USART5 clock enable during sleep mode - USART5SMEN: u1, - /// I2C1 clock enable during sleep mode - I2C1SMEN: u1, - /// I2C2 clock enable during sleep mode - I2C2SMEN: u1, - /// USB clock enable during sleep mode - USBSMEN: u1, - reserved27: u3, - /// Clock recovery system clock enable during sleep mode - CRSSMEN: u1, - /// Power interface clock enable during sleep mode - PWRSMEN: u1, - /// DAC interface clock enable during sleep mode - DACSMEN: u1, - /// I2C3 clock enable during sleep mode - I2C3SMEN: u1, - /// Low power timer clock enable during sleep mode - LPTIM1SMEN: u1, + reserved80: [12]u8, + /// The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. + IDMACTRLR: mmio.Mmio(packed struct(u32) { + /// IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + IDMAEN: u1, + /// Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + IDMABMODE: u1, + /// Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware. + IDMABACT: u1, + padding: u29, }), - /// Clock configuration register - CCIPR: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SEL: packed union { - raw: u2, - value: USART1SEL, - }, - /// USART2 clock source selection - USART2SEL: packed union { - raw: u2, - value: UARTSEL, - }, - reserved10: u6, - /// LPUART1 clock source selection - LPUART1SEL: packed union { - raw: u2, - value: UARTSEL, - }, - /// I2C1 clock source selection - I2C1SEL: packed union { - raw: u2, - value: I2CSEL, - }, - reserved16: u2, - /// I2C3 clock source selection - I2C3SEL: packed union { - raw: u2, - value: I2CSEL, - }, - /// Low Power Timer clock source selection - LPTIM1SEL: packed union { - raw: u2, - value: LPTIMSEL, - }, - padding: u12, + /// The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration. + IDMABSIZER: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). + IDMABNDT: u8, + padding: u19, }), - /// Control and status register - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low-speed oscillator enable - LSION: u1, - /// Internal low-speed oscillator ready - LSIRDY: u1, - reserved8: u6, - /// External low-speed oscillator enable - LSEON: u1, - /// External low-speed oscillator ready - LSERDY: u1, - /// External low-speed oscillator bypass - LSEBYP: u1, - /// LSEDRV - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - /// CSSLSEON - CSSLSEON: u1, - /// CSS on LSE failure detection flag - CSSLSED: u1, - reserved16: u1, - /// RTC and LCD clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - /// RTC clock enable - RTCEN: u1, - /// RTC software reset - RTCRST: u1, - reserved23: u3, - /// Remove reset flag - RMVF: u1, - /// Firewall reset flag - FWRSTF: u1, - /// OBLRSTF - OBLRSTF: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration. + IDMABASE0R: mmio.Mmio(packed struct(u32) { + /// Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1). + IDMABASE0: u32, }), - }; - }; - - pub const dbgmcu_c0 = struct { - /// Debug support - pub const DBGMCU = extern struct { - /// MCU Device ID Code Register - IDCODE: mmio.Mmio(packed struct(u32) { - /// Device Identifier - DEV_ID: u16, - /// Revision Identifier - REV_ID: u16, + /// The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address. + IDMABASE1R: mmio.Mmio(packed struct(u32) { + /// Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0). + IDMABASE1: u32, }), - /// Debug MCU Configuration Register - CR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Debug Stop Mode - DBG_STOP: u1, - /// Debug Standby Mode - DBG_STANDBY: u1, - padding: u29, + reserved128: [32]u8, + /// The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + FIFOR: mmio.Mmio(packed struct(u32) { + /// Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words. + FIFODATA: u32, }), - /// DBG APB freeze register 1 - APB1FZR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// TIM3 counter stopped when core is halted - TIM3: u1, - reserved10: u8, - /// Debug RTC stopped when Core is halted - RTC: u1, - /// Debug Window Wachdog stopped when Core is halted - WWDG: u1, - /// Debug Independent Wachdog stopped when Core is halted - IWDG: u1, - reserved21: u8, - /// I2C1 SMBUS timeout mode stopped when core is halted - I2C1: u1, - padding: u10, + reserved1012: [880]u8, + /// SDMMC IP version register + VER: mmio.Mmio(packed struct(u32) { + /// IP minor revision number. + MINREV: u4, + /// IP major revision number. + MAJREV: u4, + padding: u24, }), - /// DBG APB freeze register 2 - APB2FZR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 - TIM1: u1, - reserved15: u3, - /// TIM14 - TIM14: u1, - reserved17: u1, - /// TIM16 - TIM16: u1, - /// TIM17 - TIM17: u1, - padding: u13, + /// SDMMC IP identification register + ID: mmio.Mmio(packed struct(u32) { + /// SDMMC IP identification. + IP_ID: u32, }), }; }; - pub const gfxmmu_v2 = struct { - pub const BM192 = enum(u1) { - /// 256 blocks per line. - @"256BlocksPerLine" = 0x0, - /// 192 blocks per line. - @"192BlocksPerLine" = 0x1, - }; - - pub const CLB = enum(u2) { - /// Cache locked on buffer 0. - LockedOnBuffer0 = 0x0, - /// Cache locked on buffer 1. - LockedOnBuffer1 = 0x1, - /// Cache locked on buffer 2. - LockedOnBuffer2 = 0x2, - /// Cache locked on buffer 3. - LockedOnBuffer3 = 0x3, - }; - - /// GFXMMU. - pub const GFXMMU = extern struct { - /// GFXMMU configuration register. + pub const spdifrx_h7 = struct { + /// Receiver Interface + pub const SPDIFRX = extern struct { + /// Control register CR: mmio.Mmio(packed struct(u32) { - /// Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. - BOIE: u1, - reserved4: u3, - /// AHB master error interrupt enable. This bit enables the AHB master error interrupt. - AMEIE: u1, - reserved6: u1, - /// 192 Block mode. This bit defines the number of blocks per line. - BM: packed union { - raw: u1, - value: BM192, - }, - /// Cache enable. This bit enables the cache unit. - CE: u1, - /// Cache lock. This bit lock the cache onto the buffer defined in the CLB field. - CL: u1, - /// Cache lock buffer. This field select the buffer on which the cache is locked. - CLB: packed union { - raw: u2, - value: CLB, - }, - /// Force caching. This bit force the caching into the cache regardless of the MPU attributes. The cache must be enable (CE bit set). - FC: u1, - /// Prefetch disable. This bit disables the prefetch of the cache. - PD: u1, - reserved16: u3, - /// Outter cachability. This bit configure the cachability of an access generated by the GFXMMU cache. - OC: u1, - /// Outter bufferability. This bit configure the bufferability of an access generated by the GFXMMU cache. - OB: u1, - padding: u14, - }), - /// GFXMMU status register. - SR: mmio.Mmio(packed struct(u32) { - /// Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. - BOF: u1, - reserved4: u3, - /// AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF. - AMEF: u1, - padding: u27, + /// Peripheral Block Enable + SPDIFEN: u2, + /// Receiver DMA ENable for data flow + RXDMAEN: u1, + /// STerEO Mode + RXSTEO: u1, + /// RX Data format + DRFMT: u2, + /// Mask Parity error bit + PMSK: u1, + /// Mask of Validity bit + VMSK: u1, + /// Mask of channel status and user bits + CUMSK: u1, + /// Mask of Preamble Type bits + PTMSK: u1, + /// Control Buffer DMA ENable for control flow + CBDMAEN: u1, + /// Channel Selection + CHSEL: u1, + /// Maximum allowed re-tries during synchronization phase + NBTR: u2, + /// Wait For Activity + WFA: u1, + reserved16: u1, + /// input selection + INSEL: u3, + reserved20: u1, + /// Symbol Clock Enable + CKSEN: u1, + /// Backup Symbol Clock Enable + CKSBKPEN: u1, + padding: u10, }), - /// GFXMMU flag clear register. - FCR: mmio.Mmio(packed struct(u32) { - /// Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. - CBOF: u1, - reserved4: u3, - /// Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register. - CAMEF: u1, - padding: u27, + /// Interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// RXNE interrupt enable + RXNEIE: u1, + /// Control Buffer Ready Interrupt Enable + CSRNEIE: u1, + /// Parity error interrupt enable + PERRIE: u1, + /// Overrun error Interrupt Enable + OVRIE: u1, + /// Synchronization Block Detected Interrupt Enable + SBLKIE: u1, + /// Synchronization Done + SYNCDIE: u1, + /// Serial Interface Error Interrupt Enable + IFEIE: u1, + padding: u25, }), - /// GFXMMU cache control register. - CCR: mmio.Mmio(packed struct(u32) { - /// Force flush. When set, the cache entries are flushed. This bit is reset by hardware when the flushing is complete. Write 0 has no effect. - FF: u1, - /// Force invalidate. When set, the cache entries are invalidated. This bit is reset by hardware when the invalidation is complete. Write 0 has no effect. - FI: u1, - padding: u30, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Read data register not empty + RXNE: u1, + /// Control Buffer register is not empty + CSRNE: u1, + /// Parity error + PERR: u1, + /// Overrun error + OVR: u1, + /// Synchronization Block Detected + SBD: u1, + /// Synchronization Done + SYNCD: u1, + /// Framing error + FERR: u1, + /// Synchronization error + SERR: u1, + /// Time-out error + TERR: u1, + reserved16: u7, + /// Duration of 5 symbols counted with SPDIF_CLK + WIDTH: u15, + padding: u1, }), - /// GFXMMU default value register. - DVR: mmio.Mmio(packed struct(u32) { - /// Default value. This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped. - DV: u32, + /// Interrupt Flag Clear register + IFCR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Clears the Parity error flag + PERRCF: u1, + /// Clears the Overrun error flag + OVRCF: u1, + /// Clears the Synchronization Block Detected flag + SBDCF: u1, + /// Clears the Synchronization Done flag + SYNCDCF: u1, + padding: u26, }), - reserved32: [12]u8, - /// GFXMMU buffer 0 configuration register. - BCR: [4]mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Physical buffer offset. Offset of the physical buffer. - PBO: u19, - /// Physical buffer base address. Base address MSB of the physical buffer. - PBBA: u9, + /// Data input register + FMT0_DR: mmio.Mmio(packed struct(u32) { + /// Parity Error bit + DR: u24, + /// Parity Error bit + PE: u1, + /// Validity bit + V: u1, + /// User bit + U: u1, + /// Channel Status bit + C: u1, + /// Preamble Type + PT: u2, + padding: u2, }), - reserved4096: [4048]u8, - /// GFXMMU LUT entry 0 low. - LUTL: mmio.Mmio(packed struct(u32) { - /// Line enable. - EN: u1, - reserved8: u7, - /// First Valid Block. Number of the first valid block of line number x. - FVB: u8, - /// Last Valid Block. Number of the last valid block of line number X. - LVB: u8, - padding: u8, + /// Channel Status register + CSR: mmio.Mmio(packed struct(u32) { + /// User data information + USR: u16, + /// Channel A status information + CS: u8, + /// Start Of Block + SOB: u1, + padding: u7, }), - /// GFXMMU LUT entry 0 high. - LUTH: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Line offset. Line offset of line number x (i.e. offset of block 0 of line x). - LO: u18, - padding: u10, + /// Debug Information register + DIR: mmio.Mmio(packed struct(u32) { + /// Threshold HIGH + THI: u13, + reserved16: u3, + /// Threshold LOW + TLO: u13, + padding: u3, }), }; }; - pub const dbgmcu_f7 = struct { - /// Debug support - pub const DBGMCU = extern struct { - /// IDCODE - IDCODE: mmio.Mmio(packed struct(u32) { - /// DEV_ID - DEV_ID: u12, - reserved16: u4, - /// REV_ID - REV_ID: u16, - }), - /// Control Register + pub const spdifrx_v1 = struct { + /// Receiver Interface + pub const SPDIFRX = extern struct { + /// Control register CR: mmio.Mmio(packed struct(u32) { - /// DBG_SLEEP - DBG_SLEEP: u1, - /// DBG_STOP - DBG_STOP: u1, - /// DBG_STANDBY - DBG_STANDBY: u1, - reserved5: u2, - /// TRACE_IOEN - TRACE_IOEN: u1, - /// TRACE_MODE - TRACE_MODE: u2, - padding: u24, + /// Peripheral Block Enable + SPDIFEN: u2, + /// Receiver DMA ENable for data flow + RXDMAEN: u1, + /// STerEO Mode + RXSTEO: u1, + /// RX Data format + DRFMT: u2, + /// Mask Parity error bit + PMSK: u1, + /// Mask of Validity bit + VMSK: u1, + /// Mask of channel status and user bits + CUMSK: u1, + /// Mask of Preamble Type bits + PTMSK: u1, + /// Control Buffer DMA ENable for control flow + CBDMAEN: u1, + /// Channel Selection + CHSEL: u1, + /// Maximum allowed re-tries during synchronization phase + NBTR: u2, + /// Wait For Activity + WFA: u1, + reserved16: u1, + /// input selection + INSEL: u3, + padding: u13, }), - /// Debug MCU APB1 Freeze register - APB1FZR: mmio.Mmio(packed struct(u32) { - /// TIM2 - TIM2: u1, - /// TIM3 - TIM3: u1, - /// TIM4 - TIM4: u1, - /// TIM5 - TIM5: u1, - /// TIM6 - TIM6: u1, - /// TIM7 - TIM7: u1, - /// TIM12 - TIM12: u1, - /// TIM13 - TIM13: u1, - /// TIM14 - TIM14: u1, - /// LPTIM1 - LPTIM1: u1, - /// RTC - RTC: u1, - /// WWDG - WWDG: u1, - /// IWDG - IWDG: u1, - /// CAN3 - CAN3: u1, - reserved21: u7, - /// DBG_I2C1_SMBUS_TIMEOUT - DBG_I2C1_SMBUS_TIMEOUT: u1, - /// DBG_I2C2_SMBUS_TIMEOUT - DBG_I2C2_SMBUS_TIMEOUT: u1, - /// DBG_I2C3_SMBUS_TIMEOUT - DBG_I2C3_SMBUS_TIMEOUT: u1, - /// DBG_I2C4SMBUS_TIMEOUT - DBG_I2C4_SMBUS_TIMEOUT: u1, - /// CAN1 - CAN1: u1, - /// CAN2 - CAN2: u1, - padding: u5, + /// Interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// RXNE interrupt enable + RXNEIE: u1, + /// Control Buffer Ready Interrupt Enable + CSRNEIE: u1, + /// Parity error interrupt enable + PERRIE: u1, + /// Overrun error Interrupt Enable + OVRIE: u1, + /// Synchronization Block Detected Interrupt Enable + SBLKIE: u1, + /// Synchronization Done + SYNCDIE: u1, + /// Serial Interface Error Interrupt Enable + IFEIE: u1, + padding: u25, }), - /// Debug MCU APB2 Freeze register - APB2FZR: mmio.Mmio(packed struct(u32) { - /// TIM1 counter stopped when core is halted - TIM1: u1, - /// TIM8 counter stopped when core is halted - TIM8: u1, - reserved16: u14, - /// TIM9 counter stopped when core is halted - TIM9: u1, - /// TIM10 counter stopped when core is halted - TIM10: u1, - /// TIM11 counter stopped when core is halted - TIM11: u1, - padding: u13, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Read data register not empty + RXNE: u1, + /// Control Buffer register is not empty + CSRNE: u1, + /// Parity error + PERR: u1, + /// Overrun error + OVR: u1, + /// Synchronization Block Detected + SBD: u1, + /// Synchronization Done + SYNCD: u1, + /// Framing error + FERR: u1, + /// Synchronization error + SERR: u1, + /// Time-out error + TERR: u1, + reserved16: u7, + /// Duration of 5 symbols counted with SPDIF_CLK + WIDTH: u15, + padding: u1, + }), + /// Interrupt Flag Clear register + IFCR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Clears the Parity error flag + PERRCF: u1, + /// Clears the Overrun error flag + OVRCF: u1, + /// Clears the Synchronization Block Detected flag + SBDCF: u1, + /// Clears the Synchronization Done flag + SYNCDCF: u1, + padding: u26, + }), + /// Data input register + DR: mmio.Mmio(packed struct(u32) { + /// Parity Error bit + DR: u24, + /// Parity Error bit + PE: u1, + /// Validity bit + V: u1, + /// User bit + U: u1, + /// Channel Status bit + C: u1, + /// Preamble Type + PT: u2, + padding: u2, + }), + /// Channel Status register + CSR: mmio.Mmio(packed struct(u32) { + /// User data information + USR: u16, + /// Channel A status information + CS: u8, + /// Start Of Block + SOB: u1, + padding: u7, + }), + /// Debug Information register + DIR: mmio.Mmio(packed struct(u32) { + /// Threshold HIGH + THI: u13, + reserved16: u3, + /// Threshold LOW + TLO: u13, + padding: u3, }), }; }; - pub const rtc_v3l5 = struct { - pub const ALRF = enum(u1) { - /// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - Match = 0x1, - _, + pub const spi_f1 = struct { + pub const BIDIMODE = enum(u1) { + /// 2-line unidirectional data mode selected + Unidirectional = 0x0, + /// 1-line bidirectional data mode selected + Bidirectional = 0x1, }; - pub const ALRMF = enum(u1) { - /// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - Match = 0x1, - _, + pub const BIDIOE = enum(u1) { + /// Output disabled (receive-only mode) + Receive = 0x0, + /// Output enabled (transmit-only mode) + Transmit = 0x1, }; - pub const ALRMR_MSK = enum(u1) { - /// Alarm set if the date/day match - ToMatch = 0x0, - /// Date/day don’t care in Alarm comparison - NotMatch = 0x1, + pub const BR = enum(u3) { + /// f_PCLK / 2 + Div2 = 0x0, + /// f_PCLK / 4 + Div4 = 0x1, + /// f_PCLK / 8 + Div8 = 0x2, + /// f_PCLK / 16 + Div16 = 0x3, + /// f_PCLK / 32 + Div32 = 0x4, + /// f_PCLK / 64 + Div64 = 0x5, + /// f_PCLK / 128 + Div128 = 0x6, + /// f_PCLK / 256 + Div256 = 0x7, }; - pub const ALRMR_PM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const CHLEN = enum(u1) { + /// 16-bit wide + Bits16 = 0x0, + /// 32-bit wide + Bits32 = 0x1, }; - pub const ALRMR_WDSEL = enum(u1) { - /// DU[3:0] represents the date units - DateUnits = 0x0, - /// DU[3:0] represents the week day. DT[1:0] is don’t care. - WeekDay = 0x1, + pub const CHSIDE = enum(u1) { + /// Channel left has to be transmitted or has been received + Left = 0x0, + /// Channel right has to be transmitted or has been received + Right = 0x1, }; - pub const AMPM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const CKPOL = enum(u1) { + /// I2S clock inactive state is low level + IdleLow = 0x0, + /// I2S clock inactive state is high level + IdleHigh = 0x1, }; - pub const CALP = enum(u1) { - /// No RTCCLK pulses are added - NoChange = 0x0, - /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - IncreaseFreq = 0x1, + pub const CPHA = enum(u1) { + /// The first clock transition is the first data capture edge + FirstEdge = 0x0, + /// The second clock transition is the first data capture edge + SecondEdge = 0x1, }; - pub const CALRF = enum(u1) { - /// Clear interrupt flag by writing 1 - Clear = 0x1, - _, + pub const CPOL = enum(u1) { + /// CK to 0 when idle + IdleLow = 0x0, + /// CK to 1 when idle + IdleHigh = 0x1, }; - pub const CALW16 = enum(u1) { - /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 - SixteenSeconds = 0x1, + pub const CRCNEXT = enum(u1) { + /// Next transmit value is from Tx buffer + TxBuffer = 0x0, + /// Next transmit value is from Tx CRC register + CRC = 0x1, + }; + + pub const DATLEN = enum(u2) { + /// 16-bit data length + Bits16 = 0x0, + /// 24-bit data length + Bits24 = 0x1, + /// 32-bit data length + Bits32 = 0x2, _, }; - pub const CALW8 = enum(u1) { - /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected - EightSeconds = 0x1, - _, + pub const DFF = enum(u1) { + /// 8-bit data frame format is selected for transmission/reception + Bits8 = 0x0, + /// 16-bit data frame format is selected for transmission/reception + Bits16 = 0x1, + }; + + pub const I2SCFG = enum(u2) { + /// Slave - transmit + SlaveTx = 0x0, + /// Slave - receive + SlaveRx = 0x1, + /// Master - transmit + MasterTx = 0x2, + /// Master - receive + MasterRx = 0x3, + }; + + pub const I2SSTD = enum(u2) { + /// I2S Philips standard + Philips = 0x0, + /// MSB justified standard + MSB = 0x1, + /// LSB justified standard + LSB = 0x2, + /// PCM standard + PCM = 0x3, + }; + + pub const LSBFIRST = enum(u1) { + /// Data is transmitted/received with the MSB first + MSBFirst = 0x0, + /// Data is transmitted/received with the LSB first + LSBFirst = 0x1, + }; + + pub const MSTR = enum(u1) { + /// Slave configuration + Slave = 0x0, + /// Master configuration + Master = 0x1, + }; + + pub const ODD = enum(u1) { + /// Real divider value is I2SDIV * 2 + Even = 0x0, + /// Real divider value is (I2SDIV * 2) + 1 + Odd = 0x1, + }; + + pub const PCMSYNC = enum(u1) { + /// Short frame synchronisation + Short = 0x0, + /// Long frame synchronisation + Long = 0x1, + }; + + pub const RXONLY = enum(u1) { + /// Full duplex (Transmit and receive) + FullDuplex = 0x0, + /// Output disabled (Receive-only mode) + OutputDisabled = 0x1, + }; + + /// Serial peripheral interface + pub const SPI = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Clock phase + CPHA: packed union { + raw: u1, + value: CPHA, + }, + /// Clock polarity + CPOL: packed union { + raw: u1, + value: CPOL, + }, + /// Master selection + MSTR: packed union { + raw: u1, + value: MSTR, + }, + /// Baud rate control + BR: packed union { + raw: u3, + value: BR, + }, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: packed union { + raw: u1, + value: LSBFIRST, + }, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: packed union { + raw: u1, + value: RXONLY, + }, + /// Data frame format + DFF: packed union { + raw: u1, + value: DFF, + }, + /// CRC transfer next + CRCNEXT: packed union { + raw: u1, + value: CRCNEXT, + }, + /// Hardware CRC calculation enable + CRCEN: u1, + /// Select the direction of transfer in bidirectional mode + BIDIOE: packed union { + raw: u1, + value: BIDIOE, + }, + /// Bidirectional data mode enable + BIDIMODE: packed union { + raw: u1, + value: BIDIMODE, + }, + padding: u16, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved5: u2, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt enable + RXNEIE: u1, + /// Tx buffer empty interrupt enable + TXEIE: u1, + padding: u24, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: packed union { + raw: u1, + value: CHSIDE, + }, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + padding: u24, + }), + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Data register + DR: u16, + padding: u16, + }), + /// CRC polynomial register + CRCPR: mmio.Mmio(packed struct(u32) { + /// CRC polynomial register + CRCPOLY: u16, + padding: u16, + }), + /// RX CRC register + RXCRCR: mmio.Mmio(packed struct(u32) { + /// Rx CRC register + RxCRC: u16, + padding: u16, + }), + /// TX CRC register + TXCRCR: mmio.Mmio(packed struct(u32) { + /// Tx CRC register + TxCRC: u16, + padding: u16, + }), + /// I2S configuration register + I2SCFGR: mmio.Mmio(packed struct(u32) { + /// Channel length (number of bits per audio channel) + CHLEN: packed union { + raw: u1, + value: CHLEN, + }, + /// Data length to be transferred + DATLEN: packed union { + raw: u2, + value: DATLEN, + }, + /// Steady state clock polarity + CKPOL: packed union { + raw: u1, + value: CKPOL, + }, + /// I2S standard selection + I2SSTD: packed union { + raw: u2, + value: I2SSTD, + }, + reserved7: u1, + /// PCM frame synchronization + PCMSYNC: packed union { + raw: u1, + value: PCMSYNC, + }, + /// I2S configuration mode + I2SCFG: packed union { + raw: u2, + value: I2SCFG, + }, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding: u20, + }), + /// I2S prescaler register + I2SPR: mmio.Mmio(packed struct(u32) { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the prescaler + ODD: packed union { + raw: u1, + value: ODD, + }, + /// Master clock output enable + MCKOE: u1, + padding: u22, + }), + }; + }; + + pub const spi_v1 = struct { + pub const BIDIMODE = enum(u1) { + /// 2-line unidirectional data mode selected + Unidirectional = 0x0, + /// 1-line bidirectional data mode selected + Bidirectional = 0x1, }; - pub const COSEL = enum(u1) { - /// Calibration output is 512 Hz (with default prescaler setting) - CalFreq_512Hz = 0x0, - /// Calibration output is 1 Hz (with default prescaler setting) - CalFreq_1Hz = 0x1, + pub const BIDIOE = enum(u1) { + /// Output disabled (receive-only mode) + Receive = 0x0, + /// Output enabled (transmit-only mode) + Transmit = 0x1, }; - pub const FMT = enum(u1) { - /// 24 hour/day format - TwentyFourHour = 0x0, - /// AM/PM hour format - AmPm = 0x1, + pub const BR = enum(u3) { + /// f_PCLK / 2 + Div2 = 0x0, + /// f_PCLK / 4 + Div4 = 0x1, + /// f_PCLK / 8 + Div8 = 0x2, + /// f_PCLK / 16 + Div16 = 0x3, + /// f_PCLK / 32 + Div32 = 0x4, + /// f_PCLK / 64 + Div64 = 0x5, + /// f_PCLK / 128 + Div128 = 0x6, + /// f_PCLK / 256 + Div256 = 0x7, }; - pub const ITSF = enum(u1) { - /// This flag is set by hardware when a timestamp on the internal event occurs - TimestampEvent = 0x1, - _, + pub const CHLEN = enum(u1) { + /// 16-bit wide + Bits16 = 0x0, + /// 32-bit wide + Bits32 = 0x1, }; - pub const ITSMF = enum(u1) { - /// This flag is set by hardware when a timestamp on the internal event occurs - TimestampEvent = 0x1, - _, + pub const CHSIDE = enum(u1) { + /// Channel left has to be transmitted or has been received + Left = 0x0, + /// Channel right has to be transmitted or has been received + Right = 0x1, }; - pub const KEY = enum(u8) { - /// Activate write protection (any value that is not the keys) - Activate = 0x0, - /// Key 2 - Deactivate2 = 0x53, - /// Key 1 - Deactivate1 = 0xca, - _, + pub const CKPOL = enum(u1) { + /// I2S clock inactive state is low level + IdleLow = 0x0, + /// I2S clock inactive state is high level + IdleHigh = 0x1, }; - pub const LPCAL = enum(u1) { - /// Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required - RTCCLK = 0x0, - /// Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode - CkApre = 0x1, + pub const CPHA = enum(u1) { + /// The first clock transition is the first data capture edge + FirstEdge = 0x0, + /// The second clock transition is the first data capture edge + SecondEdge = 0x1, }; - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Alarm B output enabled - AlarmB = 0x2, - /// Wakeup output enabled - Wakeup = 0x3, + pub const CPOL = enum(u1) { + /// CK to 0 when idle + IdleLow = 0x0, + /// CK to 1 when idle + IdleHigh = 0x1, }; - pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - Low = 0x1, + pub const CRCNEXT = enum(u1) { + /// Next transmit value is from Tx buffer + TxBuffer = 0x0, + /// Next transmit value is from Tx CRC register + CRC = 0x1, }; - pub const RECALPF = enum(u1) { - /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 - Pending = 0x1, + pub const DATLEN = enum(u2) { + /// 16-bit data length + Bits16 = 0x0, + /// 24-bit data length + Bits24 = 0x1, + /// 32-bit data length + Bits32 = 0x2, _, }; - pub const TAMPALRM_TYPE = enum(u1) { - /// TAMPALRM is push-pull output - PushPull = 0x0, - /// TAMPALRM is open-drain output - OpenDrain = 0x1, + pub const DFF = enum(u1) { + /// 8-bit data frame format is selected for transmission/reception + Bits8 = 0x0, + /// 16-bit data frame format is selected for transmission/reception + Bits16 = 0x1, }; - pub const TSEDGE = enum(u1) { - /// RTC_TS input rising edge generates a time-stamp event - RisingEdge = 0x0, - /// RTC_TS input falling edge generates a time-stamp event - FallingEdge = 0x1, + pub const FRF = enum(u1) { + /// SPI Motorola mode + Motorola = 0x0, + /// SPI TI mode + TI = 0x1, }; - pub const TSF = enum(u1) { - /// This flag is set by hardware when a time-stamp event occurs - TimestampEvent = 0x1, - _, + pub const I2SCFG = enum(u2) { + /// Slave - transmit + SlaveTx = 0x0, + /// Slave - receive + SlaveRx = 0x1, + /// Master - transmit + MasterTx = 0x2, + /// Master - receive + MasterRx = 0x3, }; - pub const TSMF = enum(u1) { - /// This flag is set by hardware when a time-stamp event occurs - TimestampEvent = 0x1, - _, + pub const I2SSTD = enum(u2) { + /// I2S Philips standard + Philips = 0x0, + /// MSB justified standard + MSB = 0x1, + /// LSB justified standard + LSB = 0x2, + /// PCM standard + PCM = 0x3, }; - pub const TSOVF = enum(u1) { - /// This flag is set by hardware when a time-stamp event occurs while TSF is already set - Overflow = 0x1, - _, + pub const LSBFIRST = enum(u1) { + /// Data is transmitted/received with the MSB first + MSBFirst = 0x0, + /// Data is transmitted/received with the LSB first + LSBFirst = 0x1, }; - pub const TSOVMF = enum(u1) { - /// This flag is set by hardware when a time-stamp event occurs while TSF is already set - Overflow = 0x1, - _, + pub const MSTR = enum(u1) { + /// Slave configuration + Slave = 0x0, + /// Master configuration + Master = 0x1, }; - pub const WUCKSEL = enum(u3) { - /// RTC/16 clock is selected - Div16 = 0x0, - /// RTC/8 clock is selected - Div8 = 0x1, - /// RTC/4 clock is selected - Div4 = 0x2, - /// RTC/2 clock is selected - Div2 = 0x3, - /// ck_spre (usually 1 Hz) clock is selected - ClockSpare = 0x4, - /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - ClockSpareWithOffset = 0x6, - _, + pub const ODD = enum(u1) { + /// Real divider value is I2SDIV * 2 + Even = 0x0, + /// Real divider value is (I2SDIV * 2) + 1 + Odd = 0x1, }; - pub const WUTF = enum(u1) { - /// This flag is set by hardware when the wakeup auto-reload counter reaches 0 - Zero = 0x1, - _, + pub const PCMSYNC = enum(u1) { + /// Short frame synchronisation + Short = 0x0, + /// Long frame synchronisation + Long = 0x1, }; - pub const WUTMF = enum(u1) { - /// This flag is set by hardware when the wakeup auto-reload counter reaches 0 - Zero = 0x1, - _, + pub const RXONLY = enum(u1) { + /// Full duplex (Transmit and receive) + FullDuplex = 0x0, + /// Output disabled (Receive-only mode) + OutputDisabled = 0x1, }; - /// Real-time clock - pub const RTC = extern struct { - /// Time register - TR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { + /// Serial peripheral interface + pub const SPI = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Clock phase + CPHA: packed union { raw: u1, - value: AMPM, + value: CPHA, }, - padding: u9, - }), - /// Date register - DR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding: u8, - }), - /// Sub second register - SSR: mmio.Mmio(packed struct(u32) { - /// Synchronous binary counter - SS: u16, - padding: u16, - }), - /// Initialization control and status register - ICSR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Wakeup timer write flag - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Initialization mode - INIT: u1, - reserved16: u8, - /// Recalibration pending Flag - RECALPF: packed union { + /// Clock polarity + CPOL: packed union { raw: u1, - value: RECALPF, + value: CPOL, }, - padding: u15, - }), - /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, - padding: u9, - }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, - /// Wakeup auto-reload output clear value - WUTOCLR: u16, - }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Wakeup clock selection - WUCKSEL: packed union { + /// Master selection + MSTR: packed union { + raw: u1, + value: MSTR, + }, + /// Baud rate control + BR: packed union { raw: u3, - value: WUCKSEL, + value: BR, }, - /// Timestamp event active edge - TSEDGE: packed union { + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: packed union { raw: u1, - value: TSEDGE, + value: LSBFIRST, }, - /// RTC_REFIN reference clock detection enable (50 or 60 Hz) - REFCKON: u1, - /// Bypass the shadow registers - BYPSHAD: u1, - /// Hour format - FMT: packed union { + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: packed union { raw: u1, - value: FMT, + value: RXONLY, }, - reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, - /// Wakeup timer enable - WUTE: u1, - /// Timestamp enable - TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, - /// Wakeup timer interrupt enable - WUTIE: u1, - /// Timestamp interrupt enable - TSIE: u1, - /// Add 1 hour (summer time change) - ADD1H: u1, - /// Subtract 1 hour (winter time change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output selection - COSEL: packed union { + /// Data frame format + DFF: packed union { raw: u1, - value: COSEL, + value: DFF, }, - /// Output polarity - POL: packed union { + /// CRC transfer next + CRCNEXT: packed union { raw: u1, - value: POL, + value: CRCNEXT, }, - /// Output selection - OSEL: packed union { - raw: u2, - value: OSEL, + /// Hardware CRC calculation enable + CRCEN: u1, + /// Select the direction of transfer in bidirectional mode + BIDIOE: packed union { + raw: u1, + value: BIDIOE, }, - /// Calibration output enable - COE: u1, - /// Timestamp on internal event enable - ITSE: u1, - /// Activate timestamp on tamper detection event - TAMPTS: u1, - /// Tamper detection output enable on TAMPALRM - TAMPOE: u1, - reserved29: u2, - /// TAMPALRM pull-up enable - TAMPALRM_PU: u1, - /// TAMPALRM output type - TAMPALRM_TYPE: packed union { + /// Bidirectional data mode enable + BIDIMODE: packed union { raw: u1, - value: TAMPALRM_TYPE, + value: BIDIMODE, }, - /// RTC_OUT2 output enable - OUT2EN: u1, - }), - /// Privilege mode control register - PRIVCR: mmio.Mmio(packed struct(u32) { - /// ALRAPRIV - ALRPRIV: u1, - reserved2: u1, - /// WUTPRIV - WUTPRIV: u1, - /// TSPRIV - TSPRIV: u1, - reserved13: u9, - /// CALPRIV - CALPRIV: u1, - /// INITPRIV - INITPRIV: u1, - /// PRIV - PRIV: u1, - padding: u16, - }), - SMCR: mmio.Mmio(packed struct(u32) { - /// Alarm x protection - ALRDPROT: u1, - reserved2: u1, - /// Wakeup timer protection - WUTDPROT: u1, - /// Timestamp protection - TSDPROT: u1, - reserved13: u9, - /// Shift register, daylight saving, calibration and reference clock protection - CALDPROT: u1, - /// Initialization protection - INITDPROT: u1, - /// RTC global protection - DECPROT: u1, padding: u16, }), - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: packed union { - raw: u8, - value: KEY, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved4: u1, + /// Frame format + FRF: packed union { + raw: u1, + value: FRF, }, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt enable + RXNEIE: u1, + /// Tx buffer empty interrupt enable + TXEIE: u1, padding: u24, }), - /// Calibration register - CALR: mmio.Mmio(packed struct(u32) { - /// Calibration minus - CALM: u9, - reserved12: u3, - /// Calibration low-power mode - LPCAL: packed union { - raw: u1, - value: LPCAL, - }, - /// Use a 16-second calibration cycle period - CALW16: packed union { - raw: u1, - value: CALW16, - }, - /// Use an 8-second calibration cycle period - CALW8: packed union { - raw: u1, - value: CALW8, - }, - /// Increase frequency of RTC by 488.5 ppm - CALP: packed union { + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: packed union { raw: u1, - value: CALP, + value: CHSIDE, }, - padding: u16, - }), - /// Shift control register - SHIFTR: mmio.Mmio(packed struct(u32) { - /// Subtract a fraction of a second - SUBFS: u15, - reserved31: u16, - /// Add one second - ADD1S: u1, - }), - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - padding: u9, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + FRE: u1, + padding: u23, }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Data register + DR: u16, padding: u16, }), - /// Timestamp sub second register - TSSSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, + /// CRC polynomial register + CRCPR: mmio.Mmio(packed struct(u32) { + /// CRC polynomial register + CRCPOLY: u16, padding: u16, }), - reserved64: [4]u8, - /// Alarm register - ALRMR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm A seconds mask - MSK1: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm A minutes mask - MSK2: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: ALRMR_PM, - }, - /// Alarm A hours mask - MSK3: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { - raw: u1, - value: ALRMR_WDSEL, - }, - /// Alarm A date mask - MSK4: packed union { - raw: u1, - value: ALRMR_MSK, - }, + /// RX CRC register + RXCRCR: mmio.Mmio(packed struct(u32) { + /// Rx CRC register + RxCRC: u16, + padding: u16, }), - /// Alarm sub second register - ALRMSSR: mmio.Mmio(packed struct(u32) { - /// Sub seconds value - SS: u15, - reserved24: u9, - /// Mask the most-significant bits starting at this bit - MASKSS: u4, - padding: u4, + /// TX CRC register + TXCRCR: mmio.Mmio(packed struct(u32) { + /// Tx CRC register + TxCRC: u16, + padding: u16, }), - reserved80: [8]u8, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Alarm flag - ALRF: packed union { - raw: u1, - value: ALRF, - }, - reserved2: u1, - /// Wakeup timer flag - WUTF: packed union { - raw: u1, - value: WUTF, - }, - /// Timestamp flag - TSF: packed union { - raw: u1, - value: TSF, - }, - /// Timestamp overflow flag - TSOVF: packed union { - raw: u1, - value: TSOVF, - }, - /// Internal timestamp flag - ITSF: packed union { + /// I2S configuration register + I2SCFGR: mmio.Mmio(packed struct(u32) { + /// Channel length (number of bits per audio channel) + CHLEN: packed union { raw: u1, - value: ITSF, + value: CHLEN, }, - padding: u26, - }), - /// Masked interrupt status register - MISR: mmio.Mmio(packed struct(u32) { - /// Alarm masked flag - ALRMF: packed union { - raw: u1, - value: ALRMF, + /// Data length to be transferred + DATLEN: packed union { + raw: u2, + value: DATLEN, }, - reserved2: u1, - /// Wakeup timer masked flag - WUTMF: packed union { + /// Steady state clock polarity + CKPOL: packed union { raw: u1, - value: WUTMF, + value: CKPOL, }, - /// Timestamp masked flag - TSMF: packed union { - raw: u1, - value: TSMF, + /// I2S standard selection + I2SSTD: packed union { + raw: u2, + value: I2SSTD, }, - /// Timestamp overflow masked flag - TSOVMF: packed union { + reserved7: u1, + /// PCM frame synchronization + PCMSYNC: packed union { raw: u1, - value: TSOVMF, + value: PCMSYNC, }, - /// Internal timestamp masked flag - ITSMF: packed union { - raw: u1, - value: ITSMF, + /// I2S configuration mode + I2SCFG: packed union { + raw: u2, + value: I2SCFG, }, - padding: u26, - }), - /// Secure masked interrupt status register - SMISR: mmio.Mmio(packed struct(u32) { - /// Alarm x interrupt secure masked flag - ALRMF: u1, - reserved2: u1, - /// WUTMF - WUTMF: u1, - /// TSMF - TSMF: u1, - /// TSOVMF - TSOVMF: u1, - /// ITSMF - ITSMF: u1, - padding: u26, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding: u20, }), - /// Status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear alarm x flag - CALRF: packed union { - raw: u1, - value: CALRF, - }, - reserved2: u1, - /// Clear wakeup timer flag - CWUTF: packed union { - raw: u1, - value: CALRF, - }, - /// Clear timestamp flag - CTSF: packed union { - raw: u1, - value: CALRF, - }, - /// Clear timestamp overflow flag - CTSOVF: packed union { - raw: u1, - value: CALRF, - }, - /// Clear internal timestamp flag - CITSF: packed union { + /// I2S prescaler register + I2SPR: mmio.Mmio(packed struct(u32) { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the prescaler + ODD: packed union { raw: u1, - value: CALRF, + value: ODD, }, - padding: u26, + /// Master clock output enable + MCKOE: u1, + padding: u22, }), }; }; - pub const afio_f1 = struct { - /// Alternate function I/O - pub const AFIO = extern struct { - /// Event Control Register (AFIO_EVCR) - EVCR: mmio.Mmio(packed struct(u32) { - /// Pin selection - PIN: u4, - /// Port selection - PORT: u3, - /// Event Output Enable - EVOE: u1, - padding: u24, - }), - /// AF remap and debug I/O configuration register (AFIO_MAPR) - MAPR: mmio.Mmio(packed struct(u32) { - /// SPI1 remapping - SPI1_REMAP: u1, - /// I2C1 remapping - I2C1_REMAP: u1, - /// USART1 remapping - USART1_REMAP: u1, - /// USART2 remapping - USART2_REMAP: u1, - /// USART3 remapping - USART3_REMAP: u2, - /// TIM1 remapping - TIM1_REMAP: u2, - /// TIM2 remapping - TIM2_REMAP: u2, - /// TIM3 remapping - TIM3_REMAP: u2, - /// TIM4 remapping - TIM4_REMAP: u1, - /// CAN1 remapping - CAN1_REMAP: u2, - /// Port D0/Port D1 mapping on OSCIN/OSCOUT - PD01_REMAP: u1, - /// Set and cleared by software - TIM5CH4_IREMAP: u1, - /// ADC 1 External trigger injected conversion remapping - ADC1_ETRGINJ_REMAP: u1, - /// ADC 1 external trigger regular conversion remapping - ADC1_ETRGREG_REMAP: u1, - /// ADC 2 external trigger injected conversion remapping - ADC2_ETRGINJ_REMAP: u1, - /// ADC 2 external trigger regular conversion remapping - ADC2_ETRGREG_REMAP: u1, - /// Ethernet MAC I/O remapping - ETH_REMAP: u1, - /// CAN2 I/O remapping - CAN2_REMAP: u1, - /// MII or RMII selection - MII_RMII_SEL: u1, - /// Serial wire JTAG configuration - SWJ_CFG: u3, - reserved28: u1, - /// SPI3/I2S3 remapping - SPI3_REMAP: u1, - /// TIM2 internal trigger 1 remapping - TIM2ITR1_IREMAP: u1, - /// Ethernet PTP PPS remapping - PTP_PPS_REMAP: u1, - padding: u1, - }), - /// External interrupt configuration register 1 (AFIO_EXTICR1) - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI12 configuration - EXTI: u4, - padding: u28, - }), - reserved28: [4]u8, - /// AF remap and debug I/O configuration register - MAPR2: mmio.Mmio(packed struct(u32) { - /// TIM15 remapping - TIM15_REMAP: u1, - /// TIM16 remapping - TIM16_REMAP: u1, - /// TIM17 remapping - TIM17_REMAP: u1, - /// CEC remapping - CEC_REMAP: u1, - /// TIM1 DMA remapping - TIM1_DMA_REMAP: u1, - /// TIM9 remapping - TIM9_REMAP: u1, - /// TIM10 remapping - TIM10_REMAP: u1, - /// TIM11 remapping - TIM11_REMAP: u1, - /// TIM13 remapping - TIM13_REMAP: u1, - /// TIM14 remapping - TIM14_REMAP: u1, - /// NADV connect/disconnect - FSMC_NADV: u1, - /// TIM67_DAC DMA remapping - TIM67_DAC_DMA_REMAP: u1, - /// TIM12 remapping - TIM12_REMAP: u1, - /// Miscellaneous features remapping - MISC_REMAP: u1, - padding: u18, - }), + pub const spi_v2 = struct { + pub const BIDIMODE = enum(u1) { + /// 2-line unidirectional data mode selected + Unidirectional = 0x0, + /// 1-line bidirectional data mode selected + Bidirectional = 0x1, + }; + + pub const BIDIOE = enum(u1) { + /// Output disabled (receive-only mode) + Receive = 0x0, + /// Output enabled (transmit-only mode) + Transmit = 0x1, + }; + + pub const BR = enum(u3) { + /// f_PCLK / 2 + Div2 = 0x0, + /// f_PCLK / 4 + Div4 = 0x1, + /// f_PCLK / 8 + Div8 = 0x2, + /// f_PCLK / 16 + Div16 = 0x3, + /// f_PCLK / 32 + Div32 = 0x4, + /// f_PCLK / 64 + Div64 = 0x5, + /// f_PCLK / 128 + Div128 = 0x6, + /// f_PCLK / 256 + Div256 = 0x7, + }; + + pub const CHLEN = enum(u1) { + /// 16-bit wide + Bits16 = 0x0, + /// 32-bit wide + Bits32 = 0x1, + }; + + pub const CHSIDE = enum(u1) { + /// Channel left has to be transmitted or has been received + Left = 0x0, + /// Channel right has to be transmitted or has been received + Right = 0x1, + }; + + pub const CKPOL = enum(u1) { + /// I2S clock inactive state is low level + IdleLow = 0x0, + /// I2S clock inactive state is high level + IdleHigh = 0x1, + }; + + pub const CPHA = enum(u1) { + /// The first clock transition is the first data capture edge + FirstEdge = 0x0, + /// The second clock transition is the first data capture edge + SecondEdge = 0x1, + }; + + pub const CPOL = enum(u1) { + /// CK to 0 when idle + IdleLow = 0x0, + /// CK to 1 when idle + IdleHigh = 0x1, + }; + + pub const CRCL = enum(u1) { + /// 8-bit CRC length + Bits8 = 0x0, + /// 16-bit CRC length + Bits16 = 0x1, + }; + + pub const CRCNEXT = enum(u1) { + /// Next transmit value is from Tx buffer + TxBuffer = 0x0, + /// Next transmit value is from Tx CRC register + CRC = 0x1, + }; + + pub const DATLEN = enum(u2) { + /// 16-bit data length + Bits16 = 0x0, + /// 24-bit data length + Bits24 = 0x1, + /// 32-bit data length + Bits32 = 0x2, + _, + }; + + pub const DS = enum(u4) { + /// 4-bit + Bits4 = 0x3, + /// 5-bit + Bits5 = 0x4, + /// 6-bit + Bits6 = 0x5, + /// 7-bit + Bits7 = 0x6, + /// 8-bit + Bits8 = 0x7, + /// 9-bit + Bits9 = 0x8, + /// 10-bit + Bits10 = 0x9, + /// 11-bit + Bits11 = 0xa, + /// 12-bit + Bits12 = 0xb, + /// 13-bit + Bits13 = 0xc, + /// 14-bit + Bits14 = 0xd, + /// 15-bit + Bits15 = 0xe, + /// 16-bit + Bits16 = 0xf, + _, }; - }; - pub const crc_v1 = struct { - /// Cyclic Redundancy Check calculation unit - pub const CRC = extern struct { - /// Data register - DR: u32, - /// Independent Data register - IDR: u32, - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// RESET bit - RESET: u1, - padding: u31, - }), + pub const FRF = enum(u1) { + /// SPI Motorola mode + Motorola = 0x0, + /// SPI TI mode + TI = 0x1, }; - }; - pub const rcc_l1 = struct { - pub const HPRE = enum(u4) { - /// system clock not divided - Div1 = 0x0, - /// system clock divided by 2 - Div2 = 0x8, - /// system clock divided by 4 - Div4 = 0x9, - /// system clock divided by 8 - Div8 = 0xa, - /// system clock divided by 16 - Div16 = 0xb, - /// system clock divided by 64 - Div64 = 0xc, - /// system clock divided by 128 - Div128 = 0xd, - /// system clock divided by 256 - Div256 = 0xe, - /// system clock divided by 512 - Div512 = 0xf, - _, + pub const FRLVL = enum(u2) { + /// Rx FIFO Empty + Empty = 0x0, + /// Rx 1/4 FIFO + Quarter = 0x1, + /// Rx 1/2 FIFO + Half = 0x2, + /// Rx FIFO full + Full = 0x3, }; - pub const MCOPRE = enum(u3) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x1, - /// Division by 4 - Div4 = 0x2, - /// Division by 8 - Div8 = 0x3, - /// Division by 16 - Div16 = 0x4, - _, + pub const FRXTH = enum(u1) { + /// RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + Half = 0x0, + /// RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + Quarter = 0x1, }; - pub const MCOSEL = enum(u3) { - /// No clock - DISABLE = 0x0, - /// SYSCLK clock selected - SYS = 0x1, - /// HSI oscillator clock selected - HSI = 0x2, - /// MSI oscillator clock selected - MSI = 0x3, - /// HSE oscillator clock selected - HSE = 0x4, - /// PLL clock selected - PLL = 0x5, - /// LSI oscillator clock selected - LSI = 0x6, - /// LSE oscillator clock selected - LSE = 0x7, + pub const FTLVL = enum(u2) { + /// Tx FIFO Empty + Empty = 0x0, + /// Tx 1/4 FIFO + Quarter = 0x1, + /// Tx 1/2 FIFO + Half = 0x2, + /// Tx FIFO full + Full = 0x3, }; - pub const MSIRANGE = enum(u3) { - /// range 0 around 65.536 kHz - Range66K = 0x0, - /// range 1 around 131.072 kHz - Range131K = 0x1, - /// range 2 around 262.144 kHz - Range262K = 0x2, - /// range 3 around 524.288 kHz - Range524K = 0x3, - /// range 4 around 1.048 MHz - Range1M = 0x4, - /// range 5 around 2.097 MHz (reset value) - Range2M = 0x5, - /// range 6 around 4.194 MHz - Range4M = 0x6, - _, + pub const ISCFG = enum(u2) { + /// Slave - transmit + SlaveTx = 0x0, + /// Slave - receive + SlaveRx = 0x1, + /// Master - transmit + MasterTx = 0x2, + /// Master - receive + MasterRx = 0x3, }; - pub const PLLDIV = enum(u2) { - /// PLLVCO / 2 - Div2 = 0x1, - /// PLLVCO / 3 - Div3 = 0x2, - /// PLLVCO / 4 - Div4 = 0x3, - _, + pub const ISMOD = enum(u1) { + /// SPI mode is selected + SPIMode = 0x0, + /// I2S mode is selected + I2SMode = 0x1, }; - pub const PLLMUL = enum(u4) { - /// PLL clock entry x 3 - Mul3 = 0x0, - /// PLL clock entry x 4 - Mul4 = 0x1, - /// PLL clock entry x 6 - Mul6 = 0x2, - /// PLL clock entry x 8 - Mul8 = 0x3, - /// PLL clock entry x 12 - Mul12 = 0x4, - /// PLL clock entry x 16 - Mul16 = 0x5, - /// PLL clock entry x 24 - Mul24 = 0x6, - /// PLL clock entry x 32 - Mul32 = 0x7, - /// PLL clock entry x 48 - Mul48 = 0x8, - _, + pub const ISSTD = enum(u2) { + /// I2S Philips standard + Philips = 0x0, + /// MSB justified standard + MSB = 0x1, + /// LSB justified standard + LSB = 0x2, + /// PCM standard + PCM = 0x3, }; - pub const PLLSRC = enum(u1) { - /// HSI selected as PLL input clock - HSI = 0x0, - /// HSE selected as PLL input clock - HSE = 0x1, + pub const LDMA_RX = enum(u1) { + /// Number of data to transfer for receive is even + Even = 0x0, + /// Number of data to transfer for receive is odd + Odd = 0x1, }; - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, + pub const LDMA_TX = enum(u1) { + /// Number of data to transfer for transmit is even + Even = 0x0, + /// Number of data to transfer for transmit is odd + Odd = 0x1, }; - pub const RTCPRE = enum(u2) { - /// HSE divided by 2 - Div2 = 0x0, - /// HSE divided by 4 - Div4 = 0x1, - /// HSE divided by 8 - Div8 = 0x2, - /// HSE divided by 16 - Div16 = 0x3, + pub const LSBFIRST = enum(u1) { + /// Data is transmitted/received with the MSB first + MSBFirst = 0x0, + /// Data is transmitted/received with the LSB first + LSBFirst = 0x1, }; - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock - HSE = 0x3, + pub const MSTR = enum(u1) { + /// Slave configuration + Slave = 0x0, + /// Master configuration + Master = 0x1, }; - pub const SW = enum(u2) { - /// MSI oscillator used as system clock - MSI = 0x0, - /// HSI oscillator used as system clock - HSI = 0x1, - /// HSE oscillator used as system clock - HSE = 0x2, - /// PLL used as system clock - PLL1_R = 0x3, + pub const ODD = enum(u1) { + /// Real divider value is I2SDIV * 2 + Even = 0x0, + /// Real divider value is (I2SDIV * 2) + 1 + Odd = 0x1, }; - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal high-speed clock enable - HSION: u1, - /// Internal high-speed clock ready flag - HSIRDY: u1, - reserved8: u6, - /// MSI clock enable - MSION: u1, - /// MSI clock ready flag - MSIRDY: u1, - reserved16: u6, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE clock bypass - HSEBYP: u1, - reserved24: u5, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - reserved28: u2, - /// Clock security system enable - CSSON: u1, - /// RTC/LCD prescaler - RTCPRE: packed union { - raw: u2, - value: RTCPRE, + pub const PCMSYNC = enum(u1) { + /// Short frame synchronisation + Short = 0x0, + /// Long frame synchronisation + Long = 0x1, + }; + + pub const RXONLY = enum(u1) { + /// Full duplex (Transmit and receive) + FullDuplex = 0x0, + /// Output disabled (Receive-only mode) + OutputDisabled = 0x1, + }; + + /// Serial peripheral interface + pub const SPI = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Clock phase + CPHA: packed union { + raw: u1, + value: CPHA, }, - padding: u1, - }), - /// Internal clock sources calibration register - ICSCR: mmio.Mmio(packed struct(u32) { - /// nternal high speed clock calibration - HSICAL: u8, - /// High speed internal clock trimming - HSITRIM: u5, - /// MSI clock ranges - MSIRANGE: packed union { + /// Clock polarity + CPOL: packed union { + raw: u1, + value: CPOL, + }, + /// Master selection + MSTR: packed union { + raw: u1, + value: MSTR, + }, + /// Baud rate control + BR: packed union { raw: u3, - value: MSIRANGE, + value: BR, }, - /// MSI clock calibration - MSICAL: u8, - /// MSI clock trimming - MSITRIM: u8, - }), - /// Clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u2, - value: SW, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: packed union { + raw: u1, + value: LSBFIRST, }, - /// System clock switch status - SWS: packed union { - raw: u2, - value: SW, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: packed union { + raw: u1, + value: RXONLY, }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, + /// CRC length + CRCL: packed union { + raw: u1, + value: CRCL, }, - /// APB low-speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, + /// CRC transfer next + CRCNEXT: packed union { + raw: u1, + value: CRCNEXT, }, - /// APB high-speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, + /// Hardware CRC calculation enable + CRCEN: u1, + /// Select the direction of transfer in bidirectional mode + BIDIOE: packed union { + raw: u1, + value: BIDIOE, }, - reserved16: u2, - /// PLL entry clock source - PLLSRC: packed union { + /// Bidirectional data mode enable + BIDIMODE: packed union { raw: u1, - value: PLLSRC, + value: BIDIMODE, }, - reserved18: u1, - /// PLL multiplication factor - PLLMUL: packed union { + padding: u16, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: packed union { + raw: u1, + value: FRF, + }, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt enable + RXNEIE: u1, + /// Tx buffer empty interrupt enable + TXEIE: u1, + /// Data size + DS: packed union { raw: u4, - value: PLLMUL, + value: DS, }, - /// PLL output division - PLLDIV: packed union { - raw: u2, - value: PLLDIV, + /// FIFO reception threshold + FRXTH: packed union { + raw: u1, + value: FRXTH, }, - /// Microcontroller clock output selection - MCOSEL: packed union { - raw: u3, - value: MCOSEL, + /// Last DMA transfer for reception + LDMA_RX: packed union { + raw: u1, + value: LDMA_RX, }, - reserved28: u1, - /// Microcontroller clock output prescaler - MCOPRE: packed union { - raw: u3, - value: MCOPRE, + /// Last DMA transfer for transmission + LDMA_TX: packed union { + raw: u1, + value: LDMA_TX, }, - padding: u1, - }), - /// Clock interrupt register - CIR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// PLL ready interrupt flag - PLLRDYF: u1, - /// MSI ready interrupt flag - MSIRDYF: u1, - reserved7: u1, - /// Clock security system interrupt flag - CSSF: u1, - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// PLL ready interrupt enable - PLLRDYIE: u1, - /// MSI ready interrupt enable - MSIRDYIE: u1, - reserved16: u2, - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// PLL ready interrupt clear - PLLRDYC: u1, - /// MSI ready interrupt clear - MSIRDYC: u1, - reserved23: u1, - /// Clock security system interrupt clear - CSSC: u1, - padding: u8, - }), - /// AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - /// IO port H reset - GPIOHRST: u1, - /// IO port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - reserved12: u4, - /// CRC reset - CRCRST: u1, - reserved15: u2, - /// FLASH reset - FLASHRST: u1, - reserved24: u8, - /// DMA1 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - reserved30: u4, - /// FSMC reset - FSMCRST: u1, - padding: u1, - }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// SYSCFGRST - SYSCFGRST: u1, - reserved2: u1, - /// TIM9RST - TIM9RST: u1, - /// TM10RST - TM10RST: u1, - /// TM11RST - TM11RST: u1, - reserved9: u4, - /// ADC1RST - ADC1RST: u1, - reserved11: u1, - /// SDIORST - SDIORST: u1, - /// SPI1RST - SPI1RST: u1, - reserved14: u1, - /// USART1RST - USART1RST: u1, - padding: u17, - }), - /// APB1 peripheral reset register - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - /// Timer 4 reset - TIM4RST: u1, - /// Timer 5 reset - TIM5RST: u1, - /// Timer 6reset - TIM6RST: u1, - /// Timer 7 reset - TIM7RST: u1, - reserved9: u3, - /// LCD reset - LCDRST: u1, - reserved11: u1, - /// Window watchdog reset - WWDRST: u1, - reserved14: u2, - /// SPI 2 reset - SPI2RST: u1, - /// SPI 3 reset - SPI3RST: u1, - reserved17: u1, - /// USART 2 reset - USART2RST: u1, - /// USART 3 reset - USART3RST: u1, - /// UART 4 reset - UART4RST: u1, - /// UART 5 reset - UART5RST: u1, - /// I2C 1 reset - I2C1RST: u1, - /// I2C 2 reset - I2C2RST: u1, - /// USB reset - USBRST: u1, - reserved28: u4, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - reserved31: u1, - /// COMP interface reset - COMPRST: u1, - }), - /// AHB peripheral clock enable register - AHBENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port C clock enable - GPIOCEN: u1, - /// IO port D clock enable - GPIODEN: u1, - /// IO port E clock enable - GPIOEEN: u1, - /// IO port H clock enable - GPIOHEN: u1, - /// IO port F clock enable - GPIOFEN: u1, - /// IO port G clock enable - GPIOGEN: u1, - reserved12: u4, - /// CRC clock enable - CRCEN: u1, - reserved15: u2, - /// FLASH clock enable - FLASHEN: u1, - reserved24: u8, - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - reserved30: u4, - /// FSMCEN - FSMCEN: u1, - padding: u1, - }), - /// APB2 peripheral clock enable register - APB2ENR: mmio.Mmio(packed struct(u32) { - /// System configuration controller clock enable - SYSCFGEN: u1, - reserved2: u1, - /// TIM9 timer clock enable - TIM9EN: u1, - /// TIM10 timer clock enable - TIM10EN: u1, - /// TIM11 timer clock enable - TIM11EN: u1, - reserved9: u4, - /// ADC1 interface clock enable - ADC1EN: u1, - reserved11: u1, - /// SDIO clock enable - SDIOEN: u1, - /// SPI 1 clock enable - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable - USART1EN: u1, - padding: u17, - }), - /// APB1 peripheral clock enable register - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer 2 clock enable - TIM2EN: u1, - /// Timer 3 clock enable - TIM3EN: u1, - /// Timer 4 clock enable - TIM4EN: u1, - /// Timer 5 clock enable - TIM5EN: u1, - /// Timer 6 clock enable - TIM6EN: u1, - /// Timer 7 clock enable - TIM7EN: u1, - reserved9: u3, - /// LCD clock enable - LCDEN: u1, - reserved11: u1, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI 2 clock enable - SPI2EN: u1, - /// SPI 3 clock enable - SPI3EN: u1, - reserved17: u1, - /// USART 2 clock enable - USART2EN: u1, - /// USART 3 clock enable - USART3EN: u1, - /// UART 4 clock enable - USART4EN: u1, - /// UART 5 clock enable - USART5EN: u1, - /// I2C 1 clock enable - I2C1EN: u1, - /// I2C 2 clock enable - I2C2EN: u1, - /// USB clock enable - USBEN: u1, - reserved28: u4, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - reserved31: u1, - /// COMP interface clock enable - COMPEN: u1, - }), - /// AHB peripheral clock enable in low power mode register - AHBLPENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable during Sleep mode - GPIOALPEN: u1, - /// IO port B clock enable during Sleep mode - GPIOBLPEN: u1, - /// IO port C clock enable during Sleep mode - GPIOCLPEN: u1, - /// IO port D clock enable during Sleep mode - GPIODLPEN: u1, - /// IO port E clock enable during Sleep mode - GPIOELPEN: u1, - /// IO port H clock enable during Sleep mode - GPIOHLPEN: u1, - /// IO port F clock enable during Sleep mode - GPIOFLPEN: u1, - /// IO port G clock enable during Sleep mode - GPIOGLPEN: u1, - reserved12: u4, - /// CRC clock enable during Sleep mode - CRCLPEN: u1, - reserved15: u2, - /// FLASH clock enable during Sleep mode - FLASHLPEN: u1, - /// SRAM clock enable during Sleep mode - SRAMLPEN: u1, - reserved24: u7, - /// DMA1 clock enable during Sleep mode - DMA1LPEN: u1, - /// DMA2 clock enable during Sleep mode - DMA2LPEN: u1, - padding: u6, - }), - /// APB2 peripheral clock enable in low power mode register - APB2LPENR: mmio.Mmio(packed struct(u32) { - /// System configuration controller clock enable during Sleep mode - SYSCFGLPEN: u1, - reserved2: u1, - /// TIM9 timer clock enable during Sleep mode - TIM9LPEN: u1, - /// TIM10 timer clock enable during Sleep mode - TIM10LPEN: u1, - /// TIM11 timer clock enable during Sleep mode - TIM11LPEN: u1, - reserved9: u4, - /// ADC1 interface clock enable during Sleep mode - ADC1LPEN: u1, - reserved11: u1, - /// SDIO clock enable during Sleep mode - SDIOLPEN: u1, - /// SPI 1 clock enable during Sleep mode - SPI1LPEN: u1, - reserved14: u1, - /// USART1 clock enable during Sleep mode - USART1LPEN: u1, padding: u17, }), - /// APB1 peripheral clock enable in low power mode register - APB1LPENR: mmio.Mmio(packed struct(u32) { - /// Timer 2 clock enable during Sleep mode - TIM2LPEN: u1, - /// Timer 3 clock enable during Sleep mode - TIM3LPEN: u1, - /// Timer 4 clock enable during Sleep mode - TIM4LPEN: u1, - reserved4: u1, - /// Timer 6 clock enable during Sleep mode - TIM6LPEN: u1, - /// Timer 7 clock enable during Sleep mode - TIM7LPEN: u1, - reserved9: u3, - /// LCD clock enable during Sleep mode - LCDLPEN: u1, - reserved11: u1, - /// Window watchdog clock enable during Sleep mode - WWDGLPEN: u1, - reserved14: u2, - /// SPI 2 clock enable during Sleep mode - SPI2LPEN: u1, - reserved17: u2, - /// USART 2 clock enable during Sleep mode - USART2LPEN: u1, - /// USART 3 clock enable during Sleep mode - USART3LPEN: u1, - reserved21: u2, - /// I2C 1 clock enable during Sleep mode - I2C1LPEN: u1, - /// I2C 2 clock enable during Sleep mode - I2C2LPEN: u1, - /// USB clock enable during Sleep mode - USBLPEN: u1, - reserved28: u4, - /// Power interface clock enable during Sleep mode - PWRLPEN: u1, - /// DAC interface clock enable during Sleep mode - DACLPEN: u1, - reserved31: u1, - /// COMP interface clock enable during Sleep mode - COMPLPEN: u1, - }), - /// Control/status register - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low-speed oscillator enable - LSION: u1, - /// Internal low-speed oscillator ready - LSIRDY: u1, - reserved8: u6, - /// External low-speed oscillator enable - LSEON: u1, - /// External low-speed oscillator ready - LSERDY: u1, - /// External low-speed oscillator bypass - LSEBYP: u1, - reserved16: u5, - /// RTC and LCD clock source selection - RTCSEL: packed union { + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: packed union { + raw: u1, + value: CHSIDE, + }, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// frame format error + FRE: u1, + /// FIFO reception level + FRLVL: packed union { raw: u2, - value: RTCSEL, + value: FRLVL, }, - reserved22: u4, - /// RTC clock enable - RTCEN: u1, - /// RTC software reset - RTCRST: u1, - /// Remove reset flag - RMVF: u1, - reserved26: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// FIFO Transmission Level + FTLVL: packed union { + raw: u2, + value: FTLVL, + }, + padding: u19, }), - }; - }; - - pub const lptim_v1 = struct { - pub const CKPOL = enum(u2) { - /// the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. - Rising = 0x0, - /// the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. - Falling = 0x1, - /// both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. - Both = 0x2, - _, - }; - - pub const ClockSource = enum(u1) { - /// clocked by internal clock source (APB clock or any of the embedded oscillators) - Internal = 0x0, - /// clocked by an external clock source through the LPTIM external Input1 - External = 0x1, - }; - - pub const Filter = enum(u2) { - Count1 = 0x0, - Count2 = 0x1, - Count4 = 0x2, - Count8 = 0x3, - }; - - pub const PRESC = enum(u3) { - Div1 = 0x0, - Div2 = 0x1, - Div4 = 0x2, - Div8 = 0x3, - Div16 = 0x4, - Div32 = 0x5, - Div64 = 0x6, - Div128 = 0x7, - }; - - pub const TRIGEN = enum(u2) { - /// software trigger (counting start is initiated by software) - Software = 0x0, - /// rising edge is the active edge - RisingEdge = 0x1, - /// falling edge is the active edge - FallingEdge = 0x2, - /// both edges are active edges - BothEdge = 0x3, - }; - - pub const WAVPOL = enum(u1) { - /// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. - Positive = 0x0, - /// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. - Negative = 0x1, - }; - - /// Low power timer with Output Compare - pub const LPTIM = extern struct { - /// LPTIM interrupt and status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, - /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. - ARRM: u1, - /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. - EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, - /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. - ARROK: u1, - /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UP: u1, - /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWN: u1, - padding: u25, + /// data register - half-word sized + DR16: u32, + /// CRC polynomial register + CRCPR: mmio.Mmio(packed struct(u32) { + /// CRC polynomial register + CRCPOLY: u16, + padding: u16, }), - /// LPTIM interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, - /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. - ARRMCF: u1, - /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. - EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, - /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. - ARROKCF: u1, - /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPCF: u1, - /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNCF: u1, - padding: u25, + /// RX CRC register + RXCRCR: mmio.Mmio(packed struct(u32) { + /// Rx CRC register + RxCRC: u16, + padding: u16, }), - /// LPTIM interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, - /// Autoreload match Interrupt Enable. - ARRMIE: u1, - /// External trigger valid edge Interrupt Enable. - EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, - /// Autoreload register update OK Interrupt Enable. - ARROKIE: u1, - /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - UPIE: u1, - /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - DOWNIE: u1, - padding: u25, + /// TX CRC register + TXCRCR: mmio.Mmio(packed struct(u32) { + /// Tx CRC register + TxCRC: u16, + padding: u16, }), - /// LPTIM configuration register. - CFGR: mmio.Mmio(packed struct(u32) { - /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. - CKSEL: packed union { + /// I2S configuration register + I2SCFGR: mmio.Mmio(packed struct(u32) { + /// Channel length (number of bits per audio channel) + CHLEN: packed union { raw: u1, - value: ClockSource, + value: CHLEN, }, - /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. - CKPOL: packed union { + /// Data length to be transferred + DATLEN: packed union { raw: u2, - value: CKPOL, + value: DATLEN, }, - /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - CKFLT: packed union { - raw: u2, - value: Filter, + /// Steady state clock polarity + CKPOL: packed union { + raw: u1, + value: CKPOL, }, - reserved6: u1, - /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. - TRGFLT: packed union { + /// I2S standard selection + I2SSTD: packed union { raw: u2, - value: Filter, + value: ISSTD, }, - reserved9: u1, - /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. - PRESC: packed union { - raw: u3, - value: PRESC, + reserved7: u1, + /// PCM frame synchronization + PCMSYNC: packed union { + raw: u1, + value: PCMSYNC, }, - reserved13: u1, - /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. - TRIGSEL: u3, - reserved17: u1, - /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. - TRIGEN: packed union { + /// I2S configuration mode + I2SCFG: packed union { raw: u2, - value: TRIGEN, + value: ISCFG, }, - /// Timeout enable The TIMOUT bit controls the Timeout feature. - TIMOUT: u1, - /// Waveform shape The WAVE bit controls the output shape. - WAVE: u1, - /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. - WAVPOL: packed union { + /// I2S Enabled + I2SE: u1, + /// I2S mode selection + I2SMOD: packed union { raw: u1, - value: WAVPOL, + value: ISMOD, }, - /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. - PRELOAD: u1, - /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. - COUNTMODE: packed union { + /// Asynchronous start enable + ASTRTEN: u1, + padding: u19, + }), + /// I2S prescaler register + I2SPR: mmio.Mmio(packed struct(u32) { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the prescaler + ODD: packed union { raw: u1, - value: ClockSource, + value: ODD, }, - /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. - ENC: u1, - padding: u7, - }), - /// LPTIM control register. - CR: mmio.Mmio(packed struct(u32) { - /// LPTIM enable The ENABLE bit is set and cleared by software. - ENABLE: u1, - /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. - SNGSTRT: u1, - /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. - CNTSTRT: u1, - padding: u29, - }), - /// LPTIM compare register 1. - CMP: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. - CMP: u16, - padding: u16, - }), - /// LPTIM autoreload register. - ARR: mmio.Mmio(packed struct(u32) { - /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. - ARR: u16, - padding: u16, - }), - /// LPTIM counter register. - CNT: mmio.Mmio(packed struct(u32) { - /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. - CNT: u16, - padding: u16, + /// Master clock output enable + MCKOE: u1, + padding: u22, }), }; }; - pub const usart_v4 = struct { - pub const ABRMOD = enum(u2) { - /// Measurement of the start bit is used to detect the baud rate - Start = 0x0, - /// Falling edge to falling edge measurement - Edge = 0x1, - /// 0x7F frame detection - Frame7F = 0x2, - /// 0x55 frame detection - Frame55 = 0x3, + pub const spi_v3 = struct { + pub const CHLEN = enum(u1) { + /// 16 bits per channel + Bits16 = 0x0, + /// 32 bits per channel + Bits32 = 0x1, }; - pub const ADDM = enum(u1) { - /// 4-bit address detection - Bit4 = 0x0, - /// 7-bit address detection - Bit7 = 0x1, + pub const CKPOL = enum(u1) { + /// CK idle Level is Low. Signals are sampled on rising and changed on falling clock edges + IdleLow = 0x0, + /// CK idle level is High. Signals are sampled on falling and changed on rising clock edges + IdleHigh = 0x1, + }; + + pub const COMM = enum(u2) { + /// Full duplex + FullDuplex = 0x0, + /// Simplex transmitter only + Transmitter = 0x1, + /// Simplex receiver only + Receiver = 0x2, + /// Half duplex + HalfDuplex = 0x3, }; pub const CPHA = enum(u1) { /// The first clock transition is the first data capture edge - First = 0x0, + FirstEdge = 0x0, /// The second clock transition is the first data capture edge - Second = 0x1, + SecondEdge = 0x1, }; pub const CPOL = enum(u1) { - /// Steady low value on CK pin outside transmission window - Low = 0x0, - /// Steady high value on CK pin outside transmission window - High = 0x1, + /// SCK to 0 when idle + IdleLow = 0x0, + /// SCK to 1 when idle + IdleHigh = 0x1, }; - pub const DEP = enum(u1) { - /// DE signal is active high - High = 0x0, - /// DE signal is active low - Low = 0x1, + pub const DATFMT = enum(u1) { + /// The data inside RXDR and TXDR are right aligned + RightAligned = 0x0, + /// The data inside RXDR and TXDR are left aligned + LeftAligned = 0x1, }; - pub const IRLP = enum(u1) { - /// Normal mode - Normal = 0x0, - /// Low-power mode - LowPower = 0x1, + pub const DATLEN = enum(u2) { + /// 16-bit data length + Bits16 = 0x0, + /// 24-bit data length + Bits24 = 0x1, + /// 32-bit data length + Bits32 = 0x2, + _, }; - pub const LBDL = enum(u1) { - /// 10-bit break detection - Bit10 = 0x0, - /// 11-bit break detection - Bit11 = 0x1, + pub const FIXCH = enum(u1) { + /// The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account) + NotFixed = 0x0, + /// The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN) + Fixed = 0x1, }; - pub const M0 = enum(u1) { - /// 1 start bit, 8 data bits, n stop bits - Bit8 = 0x0, - /// 1 start bit, 9 data bits, n stop bits - Bit9 = 0x1, + pub const FTHLV = enum(u4) { + /// 1 frame + OneFrame = 0x0, + /// 2 frames + TwoFrames = 0x1, + /// 3 frames + ThreeFrames = 0x2, + /// 4 frames + FourFrames = 0x3, + /// 5 frames + FiveFrames = 0x4, + /// 6 frames + SixFrames = 0x5, + /// 7 frames + SevenFrames = 0x6, + /// 8 frames + EightFrames = 0x7, + /// 9 frames + NineFrames = 0x8, + /// 10 frames + TenFrames = 0x9, + /// 11 frames + ElevenFrames = 0xa, + /// 12 frames + TwelveFrames = 0xb, + /// 13 frames + ThirteenFrames = 0xc, + /// 14 frames + FourteenFrames = 0xd, + /// 15 frames + FifteenFrames = 0xe, + /// 16 frames + SixteenFrames = 0xf, }; - pub const M1 = enum(u1) { - /// Use M0 to set the data bits - M0 = 0x0, - /// 1 start bit, 7 data bits, n stop bits - Bit7 = 0x1, + pub const HDDIR = enum(u1) { + /// Receiver in half duplex mode + Receiver = 0x0, + /// Transmitter in half duplex mode + Transmitter = 0x1, }; - pub const MSBFIRST = enum(u1) { - /// data is transmitted/received with data bit 0 first, following the start bit - LSB = 0x0, - /// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit + pub const I2SCFG = enum(u3) { + /// Slave, transmit + SlaveTx = 0x0, + /// Slave, receive + SlaveRx = 0x1, + /// Master, transmit + MasterTx = 0x2, + /// Master, receive + MasterRx = 0x3, + /// Slave, full duplex + SlaveFullDuplex = 0x4, + /// Master, full duplex + MasterFullDuplex = 0x5, + _, + }; + + pub const I2SSTD = enum(u2) { + /// I2S Philips standard + Philips = 0x0, + /// MSB/left justified standard MSB = 0x1, + /// LSB/right justified standard + LSB = 0x2, + /// PCM standard + PCM = 0x3, }; - pub const OVER8 = enum(u1) { - /// Oversampling by 16 - Oversampling16 = 0x0, - /// Oversampling by 8 - Oversampling8 = 0x1, + pub const LSBFIRST = enum(u1) { + /// Data is transmitted/received with the MSB first + MSBFirst = 0x0, + /// Data is transmitted/received with the LSB first + LSBFirst = 0x1, }; - pub const PRESC = enum(u4) { - /// input clock not divided - Div1 = 0x0, - /// input clock divided by 2 - Div2 = 0x1, - /// input clock divided by 4 - Div4 = 0x2, - /// input clock divided by 6 - Div6 = 0x3, - /// input clock divided by 8 - Div8 = 0x4, - /// input clock divided by 10 - Div10 = 0x5, - /// input clock divided by 12 - Div12 = 0x6, - /// input clock divided by 16 - Div16 = 0x7, - /// input clock divided by 32 - Div32 = 0x8, - /// input clock divided by 64 - Div64 = 0x9, - /// input clock divided by 128 - Div128 = 0xa, - /// input clock divided by 256 - Div256 = 0xb, - _, + pub const MASTER = enum(u1) { + /// Slave configuration + Slave = 0x0, + /// Master configuration + Master = 0x1, }; - pub const PS = enum(u1) { - /// Even parity + pub const MBR = enum(u3) { + /// f_spi_ker_ck / 2 + Div2 = 0x0, + /// f_spi_ker_ck / 4 + Div4 = 0x1, + /// f_spi_ker_ck / 8 + Div8 = 0x2, + /// f_spi_ker_ck / 16 + Div16 = 0x3, + /// f_spi_ker_ck / 32 + Div32 = 0x4, + /// f_spi_ker_ck / 64 + Div64 = 0x5, + /// f_spi_ker_ck / 128 + Div128 = 0x6, + /// f_spi_ker_ck / 256 + Div256 = 0x7, + }; + + pub const ODD = enum(u1) { + /// Real divider value is I2SDIV*2 Even = 0x0, - /// Odd parity + /// Real divider value is I2SDIV*2 + 1 Odd = 0x1, }; - pub const RWU = enum(u1) { - /// Receiver in active mode - Active = 0x0, - /// Receiver in mute mode - Mute = 0x1, + pub const PCMSYNC = enum(u1) { + /// Short PCM frame synchronization + Short = 0x0, + /// Long PCM frame synchronization + Long = 0x1, }; - pub const STOP = enum(u2) { - /// 1 stop bit - Stop1 = 0x0, - /// 0.5 stop bits - Stop0p5 = 0x1, - /// 2 stop bits - Stop2 = 0x2, - /// 1.5 stop bits - Stop1p5 = 0x3, + pub const RCRCINI = enum(u1) { + /// All zeros RX CRC initialization pattern + AllZeros = 0x0, + /// All ones RX CRC initialization pattern + AllOnes = 0x1, }; - pub const WAKE = enum(u1) { - /// USART wakeup on idle line - IdleLine = 0x0, - /// USART wakeup on address mark - AddressMark = 0x1, + pub const RXPLVL = enum(u2) { + /// Zero frames beyond packing ratio available + ZeroFrames = 0x0, + /// One frame beyond packing ratio available + OneFrame = 0x1, + /// Two frame beyond packing ratio available + TwoFrames = 0x2, + /// Three frame beyond packing ratio available + ThreeFrames = 0x3, }; - pub const WUS = enum(u2) { - /// WUF active on address match - Address = 0x0, - /// WuF active on Start bit detection - Start = 0x2, - /// WUF active on RXNE - RXNE = 0x3, + pub const RXWNE = enum(u1) { + /// Less than 32-bit data frame received + LessThan32 = 0x0, + /// At least 32-bit data frame received + AtLeast32 = 0x1, + }; + + pub const SP = enum(u3) { + /// Motorola SPI protocol + Motorola = 0x0, + /// TI SPI protocol + TI = 0x1, _, }; - /// Low-power Universal synchronous asynchronous receiver transmitter - pub const LPUART = extern struct { - /// Control register 1 + pub const SSIOP = enum(u1) { + /// Low level is active for SS signal + ActiveLow = 0x0, + /// High level is active for SS signal + ActiveHigh = 0x1, + }; + + pub const SSOM = enum(u1) { + /// SS is asserted until data transfer complete + Asserted = 0x0, + /// Data frames interleaved with SS not asserted during MIDI + NotAsserted = 0x1, + }; + + pub const TCRCINI = enum(u1) { + /// All zeros TX CRC initialization pattern + AllZeros = 0x0, + /// All ones TX CRC initialization pattern + AllOnes = 0x1, + }; + + pub const UDRCFG = enum(u2) { + /// Slave sends a constant underrun pattern + Constant = 0x0, + /// Slave repeats last received data frame from master + RepeatReceived = 0x1, + /// Slave repeats last transmitted data frame + RepeatTransmitted = 0x2, + _, + }; + + pub const UDRDET = enum(u2) { + /// Underrun is detected at begin of data frame + StartOfFrame = 0x0, + /// Underrun is detected at end of last data frame + EndOfFrame = 0x1, + /// Underrun is detected at begin of active SS signal + StartOfSlaveSelect = 0x2, + _, + }; + + /// Serial peripheral interface + pub const SPI = extern struct { + /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - /// USART enable - UE: u1, - /// USART enable in Stop mode - UESM: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: packed union { + /// Serial Peripheral Enable + SPE: u1, + reserved8: u7, + /// Master automatic SUSP in Receive mode + MASRX: u1, + /// Master transfer start + CSTART: u1, + /// Master SUSPend request + CSUSP: u1, + /// Rx/Tx direction at Half-duplex mode + HDDIR: packed union { raw: u1, - value: PS, + value: HDDIR, }, - /// Parity control enable - PCE: u1, - /// Receiver wakeup method - WAKE: packed union { + /// Internal SS signal input level + SSI: u1, + /// Full size (33-bit or 17-bit) CRC polynomial is used + CRC33_17: u1, + /// CRC calculation initialization pattern control for receiver + RCRCINI: packed union { raw: u1, - value: WAKE, + value: RCRCINI, }, - /// Word length - M0: packed union { + /// CRC calculation initialization pattern control for transmitter + TCRCINI: packed union { raw: u1, - value: M0, + value: TCRCINI, }, - /// Mute mode enable - MME: u1, - /// Character match interrupt enable - CMIE: u1, - /// Oversampling mode - OVER8: packed union { - raw: u1, - value: OVER8, + /// Locking the AF configuration of associated IOs + IOLOCK: u1, + padding: u15, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Number of data at current transfer + TSIZE: u16, + /// Number of data transfer extension to be reload into TSIZE just when a previous + TSER: u16, + }), + /// configuration register 1 + CFG1: mmio.Mmio(packed struct(u32) { + /// Number of bits in at single SPI data frame + DSIZE: u5, + /// threshold level + FTHLV: packed union { + raw: u4, + value: FTHLV, }, - /// Driver Enable deassertion time - DEDT: u5, - /// Driver Enable assertion time - DEAT: u5, - /// Receiver timeout interrupt enable - RTOIE: u1, - /// End of Block interrupt enable - EOBIE: u1, - /// Word length - M1: packed union { - raw: u1, - value: M1, + /// Behavior of slave transmitter at underrun condition + UDRCFG: packed union { + raw: u2, + value: UDRCFG, }, - /// FIFO mode enable - FIFOEN: u1, - /// TXFIFO empty interrupt enable - TXFEIE: u1, - /// RXFIFO Full interrupt enable - RXFFIE: u1, + /// Detection of underrun condition at slave transmitter + UDRDET: packed union { + raw: u2, + value: UDRDET, + }, + reserved14: u1, + /// Rx DMA stream enable + RXDMAEN: u1, + /// Tx DMA stream enable + TXDMAEN: u1, + /// Length of CRC frame to be transacted and compared + CRCSIZE: u5, + reserved22: u1, + /// Hardware CRC computation enable + CRCEN: u1, + reserved28: u5, + /// Master baud rate + MBR: packed union { + raw: u3, + value: MBR, + }, + padding: u1, }), - /// Control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// 7-bit Address Detection/4-bit Address Detection - ADDM: packed union { + /// configuration register 2 + CFG2: mmio.Mmio(packed struct(u32) { + /// Master SS Idleness + MSSI: u4, + /// Master Inter-Data Idleness + MIDI: u4, + reserved15: u7, + /// Swap functionality of MISO and MOSI pins + IOSWP: u1, + reserved17: u1, + /// SPI Communication Mode + COMM: packed union { + raw: u2, + value: COMM, + }, + /// Serial Protocol + SP: packed union { + raw: u3, + value: SP, + }, + /// SPI Master + MASTER: packed union { raw: u1, - value: ADDM, + value: MASTER, }, - /// Line break detection length - LBDL: packed union { + /// Data frame format + LSBFIRST: packed union { raw: u1, - value: LBDL, + value: LSBFIRST, }, - /// LIN break detection interrupt enable - LBDIE: u1, - reserved8: u1, - /// Last bit clock pulse - LBCL: u1, /// Clock phase CPHA: packed union { raw: u1, @@ -426868,8193 +427210,6163 @@ pub const types = struct { raw: u1, value: CPOL, }, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: packed union { - raw: u2, - value: STOP, - }, - /// LIN mode enable - LINEN: u1, - /// Swap TX/RX pins - SWAP: u1, - /// RX pin active level inversion - RXINV: u1, - /// TX pin active level inversion - TXINV: u1, - /// Binary data inversion - DATAINV: u1, - /// Most significant bit first - MSBFIRST: packed union { - raw: u1, - value: MSBFIRST, - }, - /// Auto baud rate enable - ABREN: u1, - /// Auto baud rate mode - ABRMOD: packed union { - raw: u2, - value: ABRMOD, - }, - /// Receiver timeout enable - RTOEN: u1, - /// Address of the USART node - ADD: u8, - }), - /// Control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: packed union { + /// Software management of SS signal input + SSM: u1, + reserved28: u1, + /// SS input/output polarity + SSIOP: packed union { raw: u1, - value: IRLP, + value: SSIOP, }, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method enable - ONEBIT: u1, - /// Overrun Disable - OVRDIS: u1, - /// DMA Disable on Reception Error - DDRE: u1, - /// Driver enable mode - DEM: u1, - /// Driver enable polarity selection - DEP: packed union { + /// SS output enable + SSOE: u1, + /// SS output management in master mode + SSOM: packed union { raw: u1, - value: DEP, - }, - reserved17: u1, - /// Smartcard auto-retry count - SCARCNT: u3, - /// Wakeup from Stop mode interrupt flag selection - WUS: packed union { - raw: u2, - value: WUS, + value: SSOM, }, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1, - /// TXFIFO threshold interrupt enable - TXFTIE: u1, - reserved25: u1, - /// Receive FIFO threshold configuration - RXFTCFG: u3, - /// RXFIFO threshold interrupt enable - RXFTIE: u1, - /// TXFIFO threshold configuration - TXFTCFG: u3, - }), - /// Baud rate register - BRR: mmio.Mmio(packed struct(u32) { - /// USARTDIV - BRR: u16, - padding: u16, + /// Alternate function always control GPIOs + AFCNTR: u1, }), - reserved24: [8]u8, - /// Request register - RQR: mmio.Mmio(packed struct(u32) { - /// Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. - ABRRQ: u1, - /// Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available - SBKRQ: u1, - /// Mute mode request. Puts the USART in mute mode and sets the RWU flag. - MMRQ: u1, - /// Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition - RXFRQ: u1, - /// Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data. - TXFRQ: u1, - padding: u27, + /// Interrupt Enable Register + IER: mmio.Mmio(packed struct(u32) { + /// RXP Interrupt Enable + RXPIE: u1, + /// TXP interrupt enable + TXPIE: u1, + /// DXP interrupt enabled + DXPIE: u1, + /// EOT, SUSP and TXC interrupt enable + EOTIE: u1, + /// TXTFIE interrupt enable + TXTFIE: u1, + /// UDR interrupt enable + UDRIE: u1, + /// OVR interrupt enable + OVRIE: u1, + /// CRC Interrupt enable + CRCEIE: u1, + /// TIFRE interrupt enable + TIFREIE: u1, + /// Mode Fault interrupt enable + MODFIE: u1, + /// Additional number of transactions reload interrupt enable + TSERFIE: u1, + padding: u21, }), - /// Interrupt & status register - ISR: mmio.Mmio(packed struct(u32) { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise error flag - NE: u1, - /// Overrun error - ORE: u1, - /// Idle line detected - IDLE: u1, - /// Read data register not empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS interrupt flag - CTSIF: u1, - /// CTS flag - CTS: u1, - /// Receiver timeout - RTOF: u1, - /// End of block flag - EOBF: u1, - reserved14: u1, - /// Auto baud rate error - ABRE: u1, - /// Auto baud rate flag - ABRF: u1, - /// Busy flag - BUSY: u1, - /// character match flag - CMF: u1, - /// Send break flag - SBKF: u1, - /// Receiver wakeup from Mute mode - RWU: packed union { + /// Status Register + SR: mmio.Mmio(packed struct(u32) { + /// Rx-Packet available + RXP: u1, + /// Tx-Packet space available + TXP: u1, + /// Duplex Packet + DXP: u1, + /// End Of Transfer + EOT: u1, + /// Transmission Transfer Filled + TXTF: u1, + /// Underrun at slave transmission mode + UDR: u1, + /// Overrun + OVR: u1, + /// CRC Error + CRCE: u1, + /// TI frame format error + TIFRE: u1, + /// Mode Fault + MODF: u1, + /// Additional number of SPI data to be transacted was reload + TSERF: u1, + /// SUSPend + SUSP: u1, + /// TxFIFO transmission complete + TXC: u1, + /// RxFIFO Packing LeVeL + RXPLVL: packed union { + raw: u2, + value: RXPLVL, + }, + /// RxFIFO Word Not Empty + RXWNE: packed union { raw: u1, - value: RWU, + value: RXWNE, }, - /// Wakeup from Stop mode flag - WUF: u1, - /// Transmit enable acknowledge flag - TEACK: u1, - /// Receive enable acknowledge flag - REACK: u1, - /// TXFIFO Empty - TXFE: u1, - /// RXFIFO Full - RXFF: u1, - reserved26: u1, - /// RXFIFO threshold flag - RXFT: u1, - /// TXFIFO threshold flag - TXFT: u1, - padding: u4, + /// Number of data frames remaining in current TSIZE session + CTSIZE: u16, }), - /// Interrupt flag clear register - ICR: mmio.Mmio(packed struct(u32) { - /// Parity error clear flag - PE: u1, - /// Framing error clear flag - FE: u1, - /// Noise error clear flag - NE: u1, - /// Overrun error clear flag - ORE: u1, - /// Idle line detected clear flag - IDLE: u1, - reserved6: u1, - /// Transmission complete clear flag - TC: u1, - reserved8: u1, - /// LIN break detection clear flag - LBD: u1, - /// CTS clear flag - CTS: u1, - reserved11: u1, - /// Receiver timeout clear flag - RTOF: u1, - /// End of block clear flag - EOBF: u1, - reserved17: u4, - /// Character match clear flag - CMF: u1, - reserved20: u2, - /// Wakeup from Stop mode clear flag - WUF: u1, - padding: u11, + /// Interrupt/Status Flags Clear Register + IFCR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// End Of Transfer flag clear + EOTC: u1, + /// Transmission Transfer Filled flag clear + TXTFC: u1, + /// Underrun flag clear + UDRC: u1, + /// Overrun flag clear + OVRC: u1, + /// CRC Error flag clear + CRCEC: u1, + /// TI frame format error flag clear + TIFREC: u1, + /// Mode Fault flag clear + MODFC: u1, + /// TSERFC flag clear + TSERFC: u1, + /// SUSPend flag clear + SUSPC: u1, + padding: u20, }), - /// Receive data register - RDR: mmio.Mmio(packed struct(u32) { - /// Data value - DR: u9, - padding: u23, + reserved32: [4]u8, + /// Transmit Data Register - half-word sized + TXDR16: u32, + reserved48: [12]u8, + /// Receive Data Register - half-word sized + RXDR16: u32, + reserved64: [12]u8, + /// Polynomial Register + CRCPOLY: mmio.Mmio(packed struct(u32) { + /// CRC polynomial register + CRCPOLY: u32, }), - /// Transmit data register - TDR: mmio.Mmio(packed struct(u32) { - /// Data value - DR: u9, - padding: u23, + /// Transmitter CRC Register + TXCRC: mmio.Mmio(packed struct(u32) { + /// CRC register for transmitter + TXCRC: u32, }), - /// Prescaler register - PRESC: mmio.Mmio(packed struct(u32) { - /// Clock prescaler - PRESCALER: packed union { - raw: u4, - value: PRESC, - }, - padding: u28, + /// Receiver CRC Register + RXCRC: mmio.Mmio(packed struct(u32) { + /// CRC register for receiver + RXCRC: u32, }), - }; - - /// Universal synchronous asynchronous receiver transmitter - pub const USART = extern struct { - /// Control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// USART enable - UE: u1, - /// USART enable in Stop mode - UESM: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: packed union { - raw: u1, - value: PS, - }, - /// Parity control enable - PCE: u1, - /// Receiver wakeup method - WAKE: packed union { - raw: u1, - value: WAKE, - }, - /// Word length - M0: packed union { - raw: u1, - value: M0, - }, - /// Mute mode enable - MME: u1, - /// Character match interrupt enable - CMIE: u1, - /// Oversampling mode - OVER8: packed union { - raw: u1, - value: OVER8, - }, - /// Driver Enable deassertion time - DEDT: u5, - /// Driver Enable assertion time - DEAT: u5, - /// Receiver timeout interrupt enable - RTOIE: u1, - /// End of Block interrupt enable - EOBIE: u1, - /// Word length - M1: packed union { - raw: u1, - value: M1, - }, - /// FIFO mode enable - FIFOEN: u1, - /// TXFIFO empty interrupt enable - TXFEIE: u1, - /// RXFIFO Full interrupt enable - RXFFIE: u1, + /// Underrun Data Register + UDRDR: mmio.Mmio(packed struct(u32) { + /// Data at slave underrun condition + UDRDR: u32, }), - /// Control register 2 - CR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// 7-bit Address Detection/4-bit Address Detection - ADDM: packed union { - raw: u1, - value: ADDM, - }, - /// Line break detection length - LBDL: packed union { - raw: u1, - value: LBDL, - }, - /// LIN break detection interrupt enable - LBDIE: u1, - reserved8: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: packed union { - raw: u1, - value: CPHA, - }, - /// Clock polarity - CPOL: packed union { - raw: u1, - value: CPOL, - }, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: packed union { - raw: u2, - value: STOP, + /// I2S Configuration Register + I2SCFGR: mmio.Mmio(packed struct(u32) { + /// I2S mode selection + I2SMOD: u1, + /// I2S configuration mode + I2SCFG: packed union { + raw: u3, + value: I2SCFG, }, - /// LIN mode enable - LINEN: u1, - /// Swap TX/RX pins - SWAP: u1, - /// RX pin active level inversion - RXINV: u1, - /// TX pin active level inversion - TXINV: u1, - /// Binary data inversion - DATAINV: u1, - /// Most significant bit first - MSBFIRST: packed union { + /// I2S standard selection + I2SSTD: packed union { + raw: u2, + value: I2SSTD, + }, + reserved7: u1, + /// PCM frame synchronization + PCMSYNC: packed union { raw: u1, - value: MSBFIRST, + value: PCMSYNC, }, - /// Auto baud rate enable - ABREN: u1, - /// Auto baud rate mode - ABRMOD: packed union { + /// Data length to be transferred + DATLEN: packed union { raw: u2, - value: ABRMOD, + value: DATLEN, }, - /// Receiver timeout enable - RTOEN: u1, - /// Address of the USART node - ADD: u8, - }), - /// Control register 3 - CR3: mmio.Mmio(packed struct(u32) { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: packed union { + /// Channel length (number of bits per audio channel) + CHLEN: packed union { raw: u1, - value: IRLP, + value: CHLEN, }, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method enable - ONEBIT: u1, - /// Overrun Disable - OVRDIS: u1, - /// DMA Disable on Reception Error - DDRE: u1, - /// Driver enable mode - DEM: u1, - /// Driver enable polarity selection - DEP: packed union { + /// Serial audio clock polarity + CKPOL: packed union { raw: u1, - value: DEP, + value: CKPOL, }, - reserved17: u1, - /// Smartcard auto-retry count - SCARCNT: u3, - /// Wakeup from Stop mode interrupt flag selection - WUS: packed union { - raw: u2, - value: WUS, + /// Fixed channel length in slave + FIXCH: packed union { + raw: u1, + value: FIXCH, }, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1, - /// TXFIFO threshold interrupt enable - TXFTIE: u1, - reserved25: u1, - /// Receive FIFO threshold configuration - RXFTCFG: u3, - /// RXFIFO threshold interrupt enable - RXFTIE: u1, - /// TXFIFO threshold configuration - TXFTCFG: u3, - }), - /// Baud rate register - BRR: mmio.Mmio(packed struct(u32) { - /// USARTDIV - BRR: u16, - padding: u16, - }), - /// Guard time and prescaler register - GTPR: mmio.Mmio(packed struct(u32) { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding: u16, - }), - /// Receiver timeout register - RTOR: mmio.Mmio(packed struct(u32) { - /// Receiver timeout value - RTO: u24, - /// Block Length - BLEN: u8, - }), - /// Request register - RQR: mmio.Mmio(packed struct(u32) { - /// Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. - ABRRQ: u1, - /// Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available - SBKRQ: u1, - /// Mute mode request. Puts the USART in mute mode and sets the RWU flag. - MMRQ: u1, - /// Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition - RXFRQ: u1, - /// Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data. - TXFRQ: u1, - padding: u27, - }), - /// Interrupt & status register - ISR: mmio.Mmio(packed struct(u32) { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise error flag - NE: u1, - /// Overrun error - ORE: u1, - /// Idle line detected - IDLE: u1, - /// Read data register not empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS interrupt flag - CTSIF: u1, - /// CTS flag - CTS: u1, - /// Receiver timeout - RTOF: u1, - /// End of block flag - EOBF: u1, - reserved14: u1, - /// Auto baud rate error - ABRE: u1, - /// Auto baud rate flag - ABRF: u1, - /// Busy flag - BUSY: u1, - /// character match flag - CMF: u1, - /// Send break flag - SBKF: u1, - /// Receiver wakeup from Mute mode - RWU: packed union { + /// Word select inversion + WSINV: u1, + /// Data format + DATFMT: packed union { raw: u1, - value: RWU, + value: DATFMT, }, - /// Wakeup from Stop mode flag - WUF: u1, - /// Transmit enable acknowledge flag - TEACK: u1, - /// Receive enable acknowledge flag - REACK: u1, - /// TXFIFO Empty - TXFE: u1, - /// RXFIFO Full - RXFF: u1, - reserved26: u1, - /// RXFIFO threshold flag - RXFT: u1, - /// TXFIFO threshold flag - TXFT: u1, - padding: u4, - }), - /// Interrupt flag clear register - ICR: mmio.Mmio(packed struct(u32) { - /// Parity error clear flag - PE: u1, - /// Framing error clear flag - FE: u1, - /// Noise error clear flag - NE: u1, - /// Overrun error clear flag - ORE: u1, - /// Idle line detected clear flag - IDLE: u1, - reserved6: u1, - /// Transmission complete clear flag - TC: u1, - reserved8: u1, - /// LIN break detection clear flag - LBD: u1, - /// CTS clear flag - CTS: u1, - reserved11: u1, - /// Receiver timeout clear flag - RTOF: u1, - /// End of block clear flag - EOBF: u1, - reserved17: u4, - /// Character match clear flag - CMF: u1, - reserved20: u2, - /// Wakeup from Stop mode clear flag - WUF: u1, - padding: u11, - }), - /// Receive data register - RDR: mmio.Mmio(packed struct(u32) { - /// Data value - DR: u9, - padding: u23, - }), - /// Transmit data register - TDR: mmio.Mmio(packed struct(u32) { - /// Data value - DR: u9, - padding: u23, - }), - /// Prescaler register - PRESC: mmio.Mmio(packed struct(u32) { - /// Clock prescaler - PRESCALER: packed union { - raw: u4, - value: PRESC, + reserved16: u1, + /// I2S linear prescaler + I2SDIV: u8, + /// Odd factor for the prescaler + ODD: packed union { + raw: u1, + value: ODD, }, - padding: u28, + /// Master clock output enable + MCKOE: u1, + padding: u6, }), }; }; - pub const rtc_v2l1 = struct { - pub const ALRMR_MSK = enum(u1) { - /// Alarm set if the date/day match - ToMatch = 0x0, - /// Date/day don’t care in Alarm comparison - NotMatch = 0x1, - }; - - pub const ALRMR_PM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const spi_v4 = struct { + pub const COMM = enum(u2) { + /// Full duplex + FullDuplex = 0x0, + /// Simplex transmitter only + Transmitter = 0x1, + /// Simplex receiver only + Receiver = 0x2, + /// Half duplex + HalfDuplex = 0x3, }; - pub const ALRMR_WDSEL = enum(u1) { - /// DU[3:0] represents the date units - DateUnits = 0x0, - /// DU[3:0] represents the week day. DT[1:0] is don’t care - WeekDay = 0x1, + pub const CPHA = enum(u1) { + /// The first clock transition is the first data capture edge + FirstEdge = 0x0, + /// The second clock transition is the first data capture edge + SecondEdge = 0x1, }; - pub const AMPM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + pub const CPOL = enum(u1) { + /// CK to 0 when idle + IdleLow = 0x0, + /// CK to 1 when idle + IdleHigh = 0x1, }; - pub const CALP = enum(u1) { - /// No RTCCLK pulses are added - NoChange = 0x0, - /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - IncreaseFreq = 0x1, + pub const FTHLV = enum(u4) { + /// 1 frame + OneFrame = 0x0, + /// 2 frames + TwoFrames = 0x1, + /// 3 frames + ThreeFrames = 0x2, + /// 4 frames + FourFrames = 0x3, + /// 5 frames + FiveFrames = 0x4, + /// 6 frames + SixFrames = 0x5, + /// 7 frames + SevenFrames = 0x6, + /// 8 frames + EightFrames = 0x7, + /// 9 frames + NineFrames = 0x8, + /// 10 frames + TenFrames = 0x9, + /// 11 frames + ElevenFrames = 0xa, + /// 12 frames + TwelveFrames = 0xb, + /// 13 frames + ThirteenFrames = 0xc, + /// 14 frames + FourteenFrames = 0xd, + /// 15 frames + FifteenFrames = 0xe, + /// 16 frames + SixteenFrames = 0xf, }; - pub const CALW16 = enum(u1) { - /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 - Sixteen_Second = 0x1, - _, + pub const HDDIR = enum(u1) { + /// Receiver in half duplex mode + Receiver = 0x0, + /// Transmitter in half duplex mode + Transmitter = 0x1, }; - pub const CALW8 = enum(u1) { - /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected - Eight_Second = 0x1, - _, + pub const LSBFIRST = enum(u1) { + /// Data is transmitted/received with the MSB first + MSBFirst = 0x0, + /// Data is transmitted/received with the LSB first + LSBFirst = 0x1, }; - pub const COSEL = enum(u1) { - /// Calibration output is 512 Hz (with default prescaler setting) - CalFreq_512Hz = 0x0, - /// Calibration output is 1 Hz (with default prescaler setting) - CalFreq_1Hz = 0x1, + pub const MASTER = enum(u1) { + /// Slave configuration + Slave = 0x0, + /// Master configuration + Master = 0x1, }; - pub const FMT = enum(u1) { - /// 24 hour/day format - Twenty_Four_Hour = 0x0, - /// AM/PM hour format - AM_PM = 0x1, + pub const MBR = enum(u3) { + /// f_spi_ker_ck / 2 + Div2 = 0x0, + /// f_spi_ker_ck / 4 + Div4 = 0x1, + /// f_spi_ker_ck / 8 + Div8 = 0x2, + /// f_spi_ker_ck / 16 + Div16 = 0x3, + /// f_spi_ker_ck / 32 + Div32 = 0x4, + /// f_spi_ker_ck / 64 + Div64 = 0x5, + /// f_spi_ker_ck / 128 + Div128 = 0x6, + /// f_spi_ker_ck / 256 + Div256 = 0x7, }; - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Alarm B output enabled - AlarmB = 0x2, - /// Wakeup output enabled - Wakeup = 0x3, + pub const RCRCINI = enum(u1) { + /// All zeros RX CRC initialization pattern + AllZeros = 0x0, + /// All ones RX CRC initialization pattern + AllOnes = 0x1, }; - pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - Low = 0x1, + pub const RDIOM = enum(u1) { + /// RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) + PermanentlyActive = 0x0, + /// RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) + FromInput = 0x1, }; - pub const RECALPF = enum(u1) { - /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 - Pending = 0x1, - _, + pub const RDIOP = enum(u1) { + /// high level of the signal means the slave is ready for communication + ReadyHigh = 0x0, + /// low level of the signal means the slave is ready for communication + ReadyLow = 0x1, }; - pub const TAMPFLT = enum(u2) { - /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - Immediate = 0x0, - /// Tamper event is activated after 2 consecutive samples at the active level - Samples2 = 0x1, - /// Tamper event is activated after 4 consecutive samples at the active level - Samples4 = 0x2, - /// Tamper event is activated after 8 consecutive samples at the active level - Samples8 = 0x3, + pub const RXPLVL = enum(u2) { + /// Zero frames beyond packing ratio available + ZeroFrames = 0x0, + /// One frame beyond packing ratio available + OneFrame = 0x1, + /// Two frame beyond packing ratio available + TwoFrames = 0x2, + /// Three frame beyond packing ratio available + ThreeFrames = 0x3, }; - pub const TAMPFREQ = enum(u3) { - /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - Div32768 = 0x0, - /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - Div16384 = 0x1, - /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - Div8192 = 0x2, - /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - Div4096 = 0x3, - /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - Div2048 = 0x4, - /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - Div1024 = 0x5, - /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - Div512 = 0x6, - /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - Div256 = 0x7, + pub const RXWNE = enum(u1) { + /// Less than 32-bit data frame received + LessThan32 = 0x0, + /// At least 32-bit data frame received + AtLeast32 = 0x1, }; - pub const TAMPPRCH = enum(u2) { - /// 1 RTCCLK cycle - Cycles1 = 0x0, - /// 2 RTCCLK cycles - Cycles2 = 0x1, - /// 4 RTCCLK cycles - Cycles4 = 0x2, - /// 8 RTCCLK cycles - Cycles8 = 0x3, + pub const SP = enum(u3) { + /// Motorola SPI protocol + Motorola = 0x0, + /// TI SPI protocol + TI = 0x1, + _, }; - pub const TAMPPUDIS = enum(u1) { - /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - Enabled = 0x0, - /// Disable precharge of RTC_TAMPx pins - Disabled = 0x1, + pub const SSIOP = enum(u1) { + /// Low level is active for SS signal + ActiveLow = 0x0, + /// High level is active for SS signal + ActiveHigh = 0x1, }; - pub const TAMPTRG = enum(u1) { - /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. - RisingEdge = 0x0, - /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event - FallingEdge = 0x1, + pub const SSOM = enum(u1) { + /// SS is asserted until data transfer complete + Asserted = 0x0, + /// Data frames interleaved with SS not asserted during MIDI + NotAsserted = 0x1, }; - pub const TSEDGE = enum(u1) { - /// RTC_TS input rising edge generates a time-stamp event - RisingEdge = 0x0, - /// RTC_TS input falling edge generates a time-stamp event - FallingEdge = 0x1, + pub const TCRCINI = enum(u1) { + /// All zeros TX CRC initialization pattern + AllZeros = 0x0, + /// All ones TX CRC initialization pattern + AllOnes = 0x1, }; - pub const WUCKSEL = enum(u3) { - /// RTC/16 clock is selected - Div16 = 0x0, - /// RTC/8 clock is selected - Div8 = 0x1, - /// RTC/4 clock is selected - Div4 = 0x2, - /// RTC/2 clock is selected - Div2 = 0x3, - /// ck_spre (usually 1 Hz) clock is selected - ClockSpare = 0x4, - /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - ClockSpareWithOffset = 0x6, + pub const UDRCFG = enum(u2) { + /// Slave sends a constant underrun pattern + Constant = 0x0, + /// Slave repeats last received data frame from master + RepeatReceived = 0x1, + /// Slave repeats last transmitted data frame + RepeatTransmitted = 0x2, _, }; - /// Real-time clock - pub const RTC = extern struct { - /// Time register - TR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, - }), - /// Date register - DR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding: u8, - }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Wakeup clock selection - WUCKSEL: packed union { - raw: u3, - value: WUCKSEL, - }, - /// Timestamp event active edge - TSEDGE: packed union { - raw: u1, - value: TSEDGE, - }, - /// Reference clock detection enable (50 or 60 Hz) - REFCKON: u1, - /// Bypass the shadow registers - BYPSHAD: u1, - /// Hour format - FMT: packed union { - raw: u1, - value: FMT, - }, - /// Coarse digital calibration enable - DCE: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, - /// Wakeup timer enable - WUTE: u1, - /// Timestamp enable - TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, - /// Wakeup timer interrupt enable - WUTIE: u1, - /// Timestamp interrupt enable - TSIE: u1, - /// Add 1 hour (summer time change) - ADD1H: u1, - /// Subtract 1 hour (winter time change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output selection - COSEL: packed union { + /// Serial peripheral interface + pub const SPI = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Serial Peripheral Enable + SPE: u1, + reserved8: u7, + /// Master automatic SUSP in Receive mode + MASRX: u1, + /// Master transfer start + CSTART: u1, + /// Master SUSPend request + CSUSP: u1, + /// Rx/Tx direction at Half-duplex mode + HDDIR: packed union { raw: u1, - value: COSEL, + value: HDDIR, }, - /// Output polarity - POL: packed union { + /// Internal SS signal input level + SSI: u1, + /// Full size (33-bit or 17-bit) CRC polynomial is used + CRC33_17: u1, + /// CRC calculation initialization pattern control for receiver + RCRCINI: packed union { raw: u1, - value: POL, - }, - /// Output selection - OSEL: packed union { - raw: u2, - value: OSEL, + value: RCRCINI, }, - /// Calibration output enable - COE: u1, - padding: u8, - }), - /// Initialization and status register - ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, - /// Wakeup timer write enabled - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Enter Initialization mode - INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, - /// Wakeup timer flag - WUTF: u1, - /// Timestamp flag - TSF: u1, - /// Timestamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, - /// Recalibration pending flag - RECALPF: packed union { + /// CRC calculation initialization pattern control for transmitter + TCRCINI: packed union { raw: u1, - value: RECALPF, + value: TCRCINI, }, + /// Locking the AF configuration of associated IOs + IOLOCK: u1, padding: u15, }), - /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, - padding: u9, - }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Number of data at current transfer + TSIZE: u16, padding: u16, }), - /// Calibration register - CALIBR: mmio.Mmio(packed struct(u32) { - /// Digital calibration - DC: u5, - reserved7: u2, - /// Digital calibration sign - DCS: u1, - padding: u24, + /// configuration register 1 + CFG1: mmio.Mmio(packed struct(u32) { + /// Number of bits in at single SPI data frame + DSIZE: u5, + /// threshold level + FTHLV: packed union { + raw: u4, + value: FTHLV, + }, + /// Behavior of slave transmitter at underrun condition + UDRCFG: packed union { + raw: u2, + value: UDRCFG, + }, + reserved14: u3, + /// Rx DMA stream enable + RXDMAEN: u1, + /// Tx DMA stream enable + TXDMAEN: u1, + /// Length of CRC frame to be transacted and compared + CRCSIZE: u5, + reserved22: u1, + /// Hardware CRC computation enable + CRCEN: u1, + reserved28: u5, + /// Master baud rate + MBR: packed union { + raw: u3, + value: MBR, + }, + /// bypass of the prescaler at master baud rate clock generator + BPASS: u1, }), - /// Alarm register - ALRMR: [2]mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm seconds mask - MSK1: packed union { + /// configuration register 2 + CFG2: mmio.Mmio(packed struct(u32) { + /// Master SS Idleness + MSSI: u4, + /// Master Inter-Data Idleness + MIDI: u4, + reserved13: u5, + /// RDY signal input/output management Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero. + RDIOM: packed union { raw: u1, - value: ALRMR_MSK, + value: RDIOM, }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm minutes mask - MSK2: packed union { + /// RDY signal input/output polarity + RDIOP: packed union { raw: u1, - value: ALRMR_MSK, + value: RDIOP, }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: ALRMR_PM, + /// Swap functionality of MISO and MOSI pins + IOSWP: u1, + reserved17: u1, + /// SPI Communication Mode + COMM: packed union { + raw: u2, + value: COMM, }, - /// Alarm hours mask - MSK3: packed union { - raw: u1, - value: ALRMR_MSK, + /// Serial Protocol + SP: packed union { + raw: u3, + value: SP, }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { + /// SPI Master + MASTER: packed union { raw: u1, - value: ALRMR_WDSEL, + value: MASTER, }, - /// Alarm date mask - MSK4: packed union { + /// Data frame format + LSBFIRST: packed union { raw: u1, - value: ALRMR_MSK, + value: LSBFIRST, }, - }), - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: u8, - padding: u24, - }), - /// Sub second register - SSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, - }), - /// Shift control register - SHIFTR: mmio.Mmio(packed struct(u32) { - /// Subtract a fraction of a second - SUBFS: u15, - reserved31: u16, - /// Add one second - ADD1S: u1, - }), - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { + /// Clock phase + CPHA: packed union { raw: u1, - value: AMPM, + value: CPHA, }, - padding: u9, - }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding: u16, - }), - /// Timestamp sub second register - TSSSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, - }), - /// Calibration register - CALR: mmio.Mmio(packed struct(u32) { - /// Calibration minus - CALM: u9, - reserved13: u4, - /// Use a 16-second calibration cycle period - CALW16: packed union { + /// Clock polarity + CPOL: packed union { raw: u1, - value: CALW16, + value: CPOL, }, - /// Use an 8-second calibration cycle period - CALW8: packed union { + /// Software management of SS signal input + SSM: u1, + reserved28: u1, + /// SS input/output polarity + SSIOP: packed union { raw: u1, - value: CALW8, + value: SSIOP, }, - /// Increase frequency of RTC by 488.5 ppm - CALP: packed union { + /// SS output enable + SSOE: u1, + /// SS output management in master mode + SSOM: packed union { raw: u1, - value: CALP, + value: SSOM, }, - padding: u16, + /// Alternate function always control GPIOs + AFCNTR: u1, }), - /// Tamper and alternate function configuration register - TAFCR: mmio.Mmio(packed struct(u32) { - /// Tamper detection enable - TAMPE: u1, - /// Active level for tamper - TAMPTRG: packed union { - raw: u1, - value: TAMPTRG, - }, - /// Tamper interrupt enable - TAMPIE: u1, - reserved7: u4, - /// Activate timestamp on tamper detection event - TAMPTS: u1, - /// Tamper sampling frequency - TAMPFREQ: packed union { - raw: u3, - value: TAMPFREQ, - }, - /// Tamper filter count - TAMPFLT: packed union { - raw: u2, - value: TAMPFLT, - }, - /// Tamper precharge duration - TAMPPRCH: packed union { + /// Interrupt Enable Register + IER: mmio.Mmio(packed struct(u32) { + /// RXP Interrupt Enable + RXPIE: u1, + /// TXP interrupt enable + TXPIE: u1, + /// DXP interrupt enabled + DXPIE: u1, + /// EOT, SUSP and TXC interrupt enable + EOTIE: u1, + /// TXTFIE interrupt enable + TXTFIE: u1, + /// UDR interrupt enable + UDRIE: u1, + /// OVR interrupt enable + OVRIE: u1, + /// CRC Interrupt enable + CRCEIE: u1, + /// TIFRE interrupt enable + TIFREIE: u1, + /// Mode Fault interrupt enable + MODFIE: u1, + padding: u22, + }), + /// Status Register + SR: mmio.Mmio(packed struct(u32) { + /// Rx-Packet available + RXP: u1, + /// Tx-Packet space available + TXP: u1, + /// Duplex Packet + DXP: u1, + /// End Of Transfer + EOT: u1, + /// Transmission Transfer Filled + TXTF: u1, + /// Underrun at slave transmission mode + UDR: u1, + /// Overrun + OVR: u1, + /// CRC Error + CRCE: u1, + /// TI frame format error + TIFRE: u1, + /// Mode Fault + MODF: u1, + reserved11: u1, + /// SUSPend + SUSP: u1, + /// TxFIFO transmission complete + TXC: u1, + /// RxFIFO Packing LeVeL + RXPLVL: packed union { raw: u2, - value: TAMPPRCH, + value: RXPLVL, }, - /// Tamper pull-up disable - TAMPPUDIS: packed union { + /// RxFIFO Word Not Empty + RXWNE: packed union { raw: u1, - value: TAMPPUDIS, + value: RXWNE, }, - reserved18: u2, - /// AFO_ALARM output type - ALARMOUTTYPE: u1, - padding: u13, + /// Number of data frames remaining in current TSIZE session + CTSIZE: u16, + }), + /// Interrupt/Status Flags Clear Register + IFCR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// End Of Transfer flag clear + EOTC: u1, + /// Transmission Transfer Filled flag clear + TXTFC: u1, + /// Underrun flag clear + UDRC: u1, + /// Overrun flag clear + OVRC: u1, + /// CRC Error flag clear + CRCEC: u1, + /// TI frame format error flag clear + TIFREC: u1, + /// Mode Fault flag clear + MODFC: u1, + reserved11: u1, + /// SUSPend flag clear + SUSPC: u1, + padding: u20, + }), + reserved32: [4]u8, + /// Transmit Data Register - half-word sized + TXDR16: u32, + reserved48: [12]u8, + /// Receive Data Register - half-word sized + RXDR16: u32, + reserved64: [12]u8, + /// Polynomial Register + CRCPOLY: mmio.Mmio(packed struct(u32) { + /// CRC polynomial register + CRCPOLY: u32, }), - /// Alarm sub second register - ALRMSSR: [2]mmio.Mmio(packed struct(u32) { - /// Sub seconds value - SS: u15, - reserved24: u9, - /// Mask the most-significant bits starting at this bit - MASKSS: u4, - padding: u4, + /// Transmitter CRC Register + TXCRC: mmio.Mmio(packed struct(u32) { + /// CRC register for transmitter + TXCRC: u32, }), - reserved80: [4]u8, - /// Backup register - BKPR: [32]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, + /// Receiver CRC Register + RXCRC: mmio.Mmio(packed struct(u32) { + /// CRC register for receiver + RXCRC: u32, + }), + /// Underrun Data Register + UDRDR: mmio.Mmio(packed struct(u32) { + /// Data at slave underrun condition + UDRDR: u32, }), }; }; - pub const gpdma_v1 = struct { - pub const AP = enum(u1) { - /// port 0 (AHB) allocated - Port0 = 0x0, - /// port 1 (AHB) allocated - Port1 = 0x1, + pub const spi_v5 = struct { + pub const COMM = enum(u2) { + /// Full duplex + FullDuplex = 0x0, + /// Simplex transmitter only + Transmitter = 0x1, + /// Simplex receiver only + Receiver = 0x2, + /// Half duplex + HalfDuplex = 0x3, }; - pub const BREQ = enum(u1) { - /// the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. - Burst = 0x0, - /// the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ). - Block = 0x1, + pub const CPHA = enum(u1) { + /// The first clock transition is the first data capture edge + FirstEdge = 0x0, + /// The second clock transition is the first data capture edge + SecondEdge = 0x1, }; - pub const DEC = enum(u1) { - /// The address is incremented by the programmed offset. - Add = 0x0, - /// The address is decremented by the programmed offset. - Subtract = 0x1, + pub const CPOL = enum(u1) { + /// CK to 0 when idle + IdleLow = 0x0, + /// CK to 1 when idle + IdleHigh = 0x1, }; - pub const DREQ = enum(u1) { - /// selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) - SourcePeripheral = 0x0, - /// selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) - DestinationPeripheral = 0x1, + pub const FTHLV = enum(u4) { + /// 1 frame + OneFrame = 0x0, + /// 2 frames + TwoFrames = 0x1, + /// 3 frames + ThreeFrames = 0x2, + /// 4 frames + FourFrames = 0x3, + /// 5 frames + FiveFrames = 0x4, + /// 6 frames + SixFrames = 0x5, + /// 7 frames + SevenFrames = 0x6, + /// 8 frames + EightFrames = 0x7, + /// 9 frames + NineFrames = 0x8, + /// 10 frames + TenFrames = 0x9, + /// 11 frames + ElevenFrames = 0xa, + /// 12 frames + TwelveFrames = 0xb, + /// 13 frames + ThirteenFrames = 0xc, + /// 14 frames + FourteenFrames = 0xd, + /// 15 frames + FifteenFrames = 0xe, + /// 16 frames + SixteenFrames = 0xf, }; - pub const DW = enum(u2) { - /// byte - Byte = 0x0, - /// half-word (2 bytes) - HalfWord = 0x1, - /// word (4 bytes) - Word = 0x2, - _, + pub const HDDIR = enum(u1) { + /// Receiver in half duplex mode + Receiver = 0x0, + /// Transmitter in half duplex mode + Transmitter = 0x1, }; - pub const LSM = enum(u1) { - /// channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. - RunToCompletion = 0x0, - /// channel executed once for the current LLI - LinkStep = 0x1, + pub const LSBFIRST = enum(u1) { + /// Data is transmitted/received with the MSB first + MSBFirst = 0x0, + /// Data is transmitted/received with the LSB first + LSBFirst = 0x1, }; - pub const PAM = enum(u2) { - /// If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width If source is wider: source data is transferred as right aligned, left-truncated down to the destination data width - ZeroExtendOrLeftTruncate = 0x0, - /// If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width If source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width - SignExtendOrRightTruncate = 0x1, - /// source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination - Pack = 0x2, + pub const MASTER = enum(u1) { + /// Slave configuration + Slave = 0x0, + /// Master configuration + Master = 0x1, + }; + + pub const MBR = enum(u3) { + /// f_spi_ker_ck / 2 + Div2 = 0x0, + /// f_spi_ker_ck / 4 + Div4 = 0x1, + /// f_spi_ker_ck / 8 + Div8 = 0x2, + /// f_spi_ker_ck / 16 + Div16 = 0x3, + /// f_spi_ker_ck / 32 + Div32 = 0x4, + /// f_spi_ker_ck / 64 + Div64 = 0x5, + /// f_spi_ker_ck / 128 + Div128 = 0x6, + /// f_spi_ker_ck / 256 + Div256 = 0x7, + }; + + pub const RCRCINI = enum(u1) { + /// All zeros RX CRC initialization pattern + AllZeros = 0x0, + /// All ones RX CRC initialization pattern + AllOnes = 0x1, + }; + + pub const RDIOM = enum(u1) { + /// RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) + PermanentlyActive = 0x0, + /// RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) + FromInput = 0x1, + }; + + pub const RDIOP = enum(u1) { + /// high level of the signal means the slave is ready for communication + ReadyHigh = 0x0, + /// low level of the signal means the slave is ready for communication + ReadyLow = 0x1, + }; + + pub const RXPLVL = enum(u2) { + /// Zero frames beyond packing ratio available + ZeroFrames = 0x0, + /// One frame beyond packing ratio available + OneFrame = 0x1, + /// Two frame beyond packing ratio available + TwoFrames = 0x2, + /// Three frame beyond packing ratio available + ThreeFrames = 0x3, + }; + + pub const RXWNE = enum(u1) { + /// Less than 32-bit data frame received + LessThan32 = 0x0, + /// At least 32-bit data frame received + AtLeast32 = 0x1, + }; + + pub const SP = enum(u3) { + /// Motorola SPI protocol + Motorola = 0x0, + /// TI SPI protocol + TI = 0x1, _, }; - pub const PRIO = enum(u2) { - /// low priority, low weight - LowWithLowhWeight = 0x0, - /// low priority, mid weight - LowWithMidWeight = 0x1, - /// low priority, high weight - LowWithHighWeight = 0x2, - /// high priority - High = 0x3, + pub const SSIOP = enum(u1) { + /// Low level is active for SS signal + ActiveLow = 0x0, + /// High level is active for SS signal + ActiveHigh = 0x1, }; - pub const SWREQ = enum(u1) { - /// no software request. The selected hardware request REQSEL[6:0] is taken into account. - Hardware = 0x0, - /// software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored. - Software = 0x1, + pub const SSOM = enum(u1) { + /// SS is asserted until data transfer complete + Asserted = 0x0, + /// Data frames interleaved with SS not asserted during MIDI + NotAsserted = 0x1, }; - pub const TCEM = enum(u2) { - /// at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. - EachBlock = 0x0, - /// channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block. - Each2DBlock = 0x1, - /// at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer. - EachLinkedListItem = 0x2, - /// at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated. - LastLinkedListItem = 0x3, + pub const TCRCINI = enum(u1) { + /// All zeros TX CRC initialization pattern + AllZeros = 0x0, + /// All ones TX CRC initialization pattern + AllOnes = 0x1, }; - pub const TRIGM = enum(u2) { - /// at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0). - Block = 0x0, - /// channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the - @"2DBlock" = 0x1, - /// at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned. - LinkedListItem = 0x2, - /// at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger. - Burst = 0x3, + pub const TRIGPOL = enum(u1) { + /// trigger is active on raising edge + RisingEdge = 0x0, + /// trigger is active on falling edge + FallingEdge = 0x1, }; - pub const TRIGPOL = enum(u2) { - /// no trigger (masked trigger event) - None = 0x0, - /// trigger on the rising edge - RisingEdge = 0x1, - /// trigger on the falling edge - FallingEdge = 0x2, - /// same as 00 - NoneAlt = 0x3, + pub const UDRCFG = enum(u2) { + /// Slave sends a constant underrun pattern + Constant = 0x0, + /// Slave repeats last received data frame from master + RepeatReceived = 0x1, + /// Slave repeats last transmitted data frame + RepeatTransmitted = 0x2, + _, }; - pub const Channel = extern struct { - /// GPDMA channel 15 linked-list base address register - LBAR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// linked-list base address of GPDMA channel x - LBA: u16, - }), - reserved12: [8]u8, - /// GPDMA channel 15 flag clear register - FCR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// transfer complete flag clear - TCF: u1, - /// half transfer flag clear - HTF: u1, - /// data transfer error flag clear - DTEF: u1, - /// update link transfer error flag clear - ULEF: u1, - /// user setting error flag clear - USEF: u1, - /// completed suspension flag clear - SUSPF: u1, - /// trigger overrun flag clear - TOF: u1, - padding: u17, - }), - /// GPDMA channel 15 status register - SR: mmio.Mmio(packed struct(u32) { - /// idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state). - IDLEF: u1, + /// Serial peripheral interface + pub const SPI = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Serial Peripheral Enable + SPE: u1, reserved8: u7, - /// transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). - TCF: u1, - /// half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination. - HTF: u1, - /// data transfer error flag - DTEF: u1, - /// update link transfer error flag - ULEF: u1, - /// user setting error flag - USEF: u1, - /// completed suspension flag - SUSPF: u1, - /// trigger overrun flag - TOF: u1, - reserved16: u1, - /// monitored FIFO level. Number of available write beats in the FIFO, in units of the programmed destination data width (see CH[x].TR1.DDW[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to CH[x].BR1.BDNT[15:0] and CH[x].BR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (CH[x].SR.SUSPF = 1). - FIFOL: u8, - padding: u8, - }), - /// GPDMA channel 15 control register - CR: mmio.Mmio(packed struct(u32) { - /// enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. - EN: u1, - /// reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in ). - RESET: u1, - /// suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in . - SUSP: u1, - reserved8: u5, - /// transfer complete interrupt enable - TCIE: u1, - /// half transfer complete interrupt enable - HTIE: u1, - /// data transfer error interrupt enable - DTEIE: u1, - /// update link transfer error interrupt enable - ULEIE: u1, - /// user setting error interrupt enable - USEIE: u1, - /// completed suspension interrupt enable - SUSPIE: u1, - /// trigger overrun interrupt enable - TOIE: u1, - reserved16: u1, - /// Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1. - LSM: packed union { + /// Master automatic SUSP in Receive mode + MASRX: u1, + /// Master transfer start + CSTART: u1, + /// Master SUSPend request + CSUSP: u1, + /// Rx/Tx direction at Half-duplex mode + HDDIR: packed union { raw: u1, - value: LSM, + value: HDDIR, }, - /// linked-list allocated port. This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1. - LAP: packed union { + /// Internal SS signal input level + SSI: u1, + /// Full size (33-bit or 17-bit) CRC polynomial is used + CRC33_17: u1, + /// CRC calculation initialization pattern control for receiver + RCRCINI: packed union { raw: u1, - value: AP, + value: RCRCINI, }, - reserved22: u4, - /// priority level of the channel x GPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. - PRIO: packed union { - raw: u2, - value: PRIO, + /// CRC calculation initialization pattern control for transmitter + TCRCINI: packed union { + raw: u1, + value: TCRCINI, }, - padding: u8, + /// Locking the AF configuration of associated IOs + IOLOCK: u1, + padding: u15, }), - reserved64: [40]u8, - /// GPDMA channel 15 transfer register 1 - TR1: mmio.Mmio(packed struct(u32) { - /// binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued. - SDW: packed union { - raw: u2, - value: DW, - }, - reserved3: u1, - /// source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. - SINC: u1, - /// source burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed. - SBL_1: u6, - reserved11: u1, - /// padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note: - PAM: packed union { - raw: u2, - value: PAM, - }, - /// source byte exchange within the unaligned half-word of each source word. If set, the two consecutive bytes within the unaligned half-word of each source word are exchanged. If the source data width is shorter than a word, this bit is ignored. - SBX: u1, - /// source allocated port. This bit is used to allocate the master port for the source transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. - SAP: packed union { - raw: u1, - value: AP, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Number of data at current transfer + TSIZE: u16, + padding: u16, + }), + /// configuration register 1 + CFG1: mmio.Mmio(packed struct(u32) { + /// Number of bits in at single SPI data frame + DSIZE: u5, + /// threshold level + FTHLV: packed union { + raw: u4, + value: FTHLV, }, - /// security attribute of the GPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure. - SSEC: u1, - /// binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued. - DDW: packed union { + /// Behavior of slave transmitter at underrun condition + UDRCFG: packed union { raw: u2, - value: DW, + value: UDRCFG, }, - reserved19: u1, - /// destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. - DINC: u1, - /// destination burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed. - DBL_1: u6, - /// destination byte exchange. IF set, the two consecutive (post PAM) bytes are exchanged in each destination half-word. If the destination data size is a byte, this bit is ignored. - DBX: u1, - /// destination half-word exchange. If set, e two consecutive (post PAM) half-words are exchanged in each destination word. If the destination data size is shorter than a word, this bit is ignored. - DHX: u1, - reserved30: u2, - /// destination allocated port. This bit is used to allocate the master port for the destination transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. - DAP: packed union { - raw: u1, - value: AP, + reserved14: u3, + /// Rx DMA stream enable + RXDMAEN: u1, + /// Tx DMA stream enable + TXDMAEN: u1, + /// Length of CRC frame to be transacted and compared + CRCSIZE: u5, + reserved22: u1, + /// Hardware CRC computation enable + CRCEN: u1, + reserved28: u5, + /// Master baud rate + MBR: packed union { + raw: u3, + value: MBR, }, - /// security attribute of the GPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure. - DSEC: u1, + /// bypass of the prescaler at master baud rate clock generator + BPASS: u1, }), - /// GPDMA channel 15 transfer register 2 - TR2: mmio.Mmio(packed struct(u32) { - /// GPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. - REQSEL: u7, - reserved9: u2, - /// software request. This bit is internally taken into account when CH[x].CR.EN is asserted. - SWREQ: packed union { - raw: u1, - value: SWREQ, - }, - /// destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note: - DREQ: packed union { + /// configuration register 2 + CFG2: mmio.Mmio(packed struct(u32) { + /// Master SS Idleness + MSSI: u4, + /// Master Inter-Data Idleness + MIDI: u4, + reserved13: u5, + /// RDY signal input/output management Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero. + RDIOM: packed union { raw: u1, - value: DREQ, + value: RDIOM, }, - /// Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: - BREQ: packed union { + /// RDY signal input/output polarity + RDIOP: packed union { raw: u1, - value: BREQ, + value: RDIOP, }, - reserved14: u2, - /// trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger. - TRIGM: packed union { + /// Swap functionality of MISO and MOSI pins + IOSWP: u1, + reserved17: u1, + /// SPI Communication Mode + COMM: packed union { raw: u2, - value: TRIGM, + value: COMM, }, - /// trigger event input selection. These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00. - TRIGSEL: u6, - reserved24: u2, - /// trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - TRIGPOL: packed union { - raw: u2, - value: TRIGPOL, + /// Serial Protocol + SP: packed union { + raw: u3, + value: SP, }, - reserved30: u4, - /// transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - TCEM: packed union { - raw: u2, - value: TCEM, + /// SPI Master + MASTER: packed union { + raw: u1, + value: MASTER, }, - }), - /// GPDMA channel 15 alternate block register 1 - BR1: mmio.Mmio(packed struct(u32) { - /// block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued. - BNDT: u16, - /// Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer. - BRC: u11, - reserved28: u1, - /// source address decrement - SDEC: packed union { + /// Data frame format + LSBFIRST: packed union { raw: u1, - value: DEC, + value: LSBFIRST, }, - /// destination address decrement - DDEC: packed union { + /// Clock phase + CPHA: packed union { raw: u1, - value: DEC, + value: CPHA, }, - /// Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer. - BRSDEC: packed union { + /// Clock polarity + CPOL: packed union { raw: u1, - value: DEC, + value: CPOL, }, - /// Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer. - BRDDEC: packed union { + /// Software management of SS signal input + SSM: u1, + reserved28: u1, + /// SS input/output polarity + SSIOP: packed union { raw: u1, - value: DEC, + value: SSIOP, + }, + /// SS output enable + SSOE: u1, + /// SS output management in master mode + SSOM: packed union { + raw: u1, + value: SSOM, }, + /// Alternate function always control GPIOs + AFCNTR: u1, }), - /// GPDMA channel 15 source address register - SAR: u32, - /// GPDMA channel 15 destination address register - DAR: u32, - /// GPDMA channel 15 transfer register 3 - TR3: mmio.Mmio(packed struct(u32) { - /// source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied. - SAO: u13, - reserved16: u3, - /// destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued. - DAO: u13, - padding: u3, + /// Interrupt Enable Register + IER: mmio.Mmio(packed struct(u32) { + /// RXP Interrupt Enable + RXPIE: u1, + /// TXP interrupt enable + TXPIE: u1, + /// DXP interrupt enabled + DXPIE: u1, + /// EOT, SUSP and TXC interrupt enable + EOTIE: u1, + /// TXTFIE interrupt enable + TXTFIE: u1, + /// UDR interrupt enable + UDRIE: u1, + /// OVR interrupt enable + OVRIE: u1, + /// CRC Interrupt enable + CRCEIE: u1, + /// TIFRE interrupt enable + TIFREIE: u1, + /// Mode Fault interrupt enable + MODFIE: u1, + padding: u22, }), - /// GPDMA channel 15 block register 2 - BR2: mmio.Mmio(packed struct(u32) { - /// Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. - BRSAO: u16, - /// Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued. - BRDAO: u16, + /// Status Register + SR: mmio.Mmio(packed struct(u32) { + /// Rx-Packet available + RXP: u1, + /// Tx-Packet space available + TXP: u1, + /// Duplex Packet + DXP: u1, + /// End Of Transfer + EOT: u1, + /// Transmission Transfer Filled + TXTF: u1, + /// Underrun at slave transmission mode + UDR: u1, + /// Overrun + OVR: u1, + /// CRC Error + CRCE: u1, + /// TI frame format error + TIFRE: u1, + /// Mode Fault + MODF: u1, + reserved11: u1, + /// SUSPend + SUSP: u1, + /// TxFIFO transmission complete + TXC: u1, + /// RxFIFO Packing LeVeL + RXPLVL: packed union { + raw: u2, + value: RXPLVL, + }, + /// RxFIFO Word Not Empty + RXWNE: packed union { + raw: u1, + value: RXWNE, + }, + /// Number of data frames remaining in current TSIZE session + CTSIZE: u16, }), - reserved124: [32]u8, - /// GPDMA channel 15 alternate linked-list address register - LLR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. - LA: u14, - /// Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer. - ULL: u1, - reserved25: u8, - /// Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer. - UB2: u1, - /// Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer. - UT3: u1, - /// Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer. - UDA: u1, - /// update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer. - USA: u1, - /// Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. - UB1: u1, - /// Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer. - UT2: u1, - /// Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer. - UT1: u1, + /// Interrupt/Status Flags Clear Register + IFCR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// End Of Transfer flag clear + EOTC: u1, + /// Transmission Transfer Filled flag clear + TXTFC: u1, + /// Underrun flag clear + UDRC: u1, + /// Overrun flag clear + OVRC: u1, + /// CRC Error flag clear + CRCEC: u1, + /// TI frame format error flag clear + TIFREC: u1, + /// Mode Fault flag clear + MODFC: u1, + reserved11: u1, + /// SUSPend flag clear + SUSPC: u1, + padding: u20, }), - }; - - /// GPDMA - pub const GPDMA = extern struct { - /// GPDMA secure configuration register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// SEC0 - SEC: u1, - padding: u31, + AUTOCR: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// trigger selection (refer ). ... Note: these bits can be written only when SPE = 0. + TRIGSEL: u4, + /// trigger polarity Note: This bit can be written only when SPE = 0. + TRIGPOL: packed union { + raw: u1, + value: TRIGPOL, + }, + /// trigger of CSTART control enable Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled + TRIGEN: u1, + padding: u10, }), - /// GPDMA privileged configuration register - PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// PRIV0 - PRIV: u1, - padding: u31, + /// Transmit Data Register - half-word sized + TXDR16: u32, + reserved48: [12]u8, + /// Receive Data Register - half-word sized + RXDR16: u32, + reserved64: [12]u8, + /// Polynomial Register + CRCPOLY: mmio.Mmio(packed struct(u32) { + /// CRC polynomial register + CRCPOLY: u32, }), - /// GPDMA configuration lock register - RCFGLOCKR: mmio.Mmio(packed struct(u32) { - /// LOCK0 - LOCK: u1, - padding: u31, + /// Transmitter CRC Register + TXCRC: mmio.Mmio(packed struct(u32) { + /// CRC register for transmitter + TXCRC: u32, }), - /// GPDMA non-secure masked interrupt status register - MISR: mmio.Mmio(packed struct(u32) { - /// MIS0 - MIS: u1, - padding: u31, + /// Receiver CRC Register + RXCRC: mmio.Mmio(packed struct(u32) { + /// CRC register for receiver + RXCRC: u32, }), - /// GPDMA secure masked interrupt status register - SMISR: mmio.Mmio(packed struct(u32) { - /// MIS0 - MIS: u1, - padding: u31, + /// Underrun Data Register + UDRDR: mmio.Mmio(packed struct(u32) { + /// Data at slave underrun condition + UDRDR: u32, }), - reserved80: [60]u8, - CH: u32, }; }; - pub const can_bxcan = struct { - pub const IDE = enum(u1) { - /// Standard identifier - Standard = 0x0, - /// Extended identifier - Extended = 0x1, + pub const syscfg_c0 = struct { + pub const IR_MOD = enum(u2) { + /// TIM16 + TIM16 = 0x0, + /// USART1 + USART1 = 0x1, + /// USART2 + USART2 = 0x2, + _, }; - pub const LEC = enum(u3) { - /// No Error - NoError = 0x0, - /// Stuff Error - Stuff = 0x1, - /// Form Error - Form = 0x2, - /// Acknowledgment Error - Ack = 0x3, - /// Bit recessive Error - BitRecessive = 0x4, - /// Bit dominant Error - BitDominant = 0x5, - /// CRC Error - Crc = 0x6, - /// Set by software - Custom = 0x7, + pub const MEM_MODE = enum(u2) { + /// Main Flash memory mapped at address 0 + MAIN_FLASH = 0x0, + /// System Flash memory mapped at address 0 + SYSTEM_FLASH = 0x1, + /// Main Flash memory mapped at address 0 (alternate encoding) + MAIN_FLASH_ALT = 0x2, + /// Embedded SRAM mapped at address 0 + SRAM = 0x3, }; - pub const RTR = enum(u1) { - /// Data frame - Data = 0x0, - /// Remote frame - Remote = 0x1, + pub const PINMUX0 = enum(u2) { + /// PB7 + PB7 = 0x0, + /// PC14 + PC14 = 0x1, + _, }; - pub const SILM = enum(u1) { - /// Normal operation - Normal = 0x0, - /// Silent Mode - Silent = 0x1, + pub const PINMUX1 = enum(u2) { + /// PF2 + PF2 = 0x0, + /// PA0 + PA0 = 0x1, + /// PA1 + PA1 = 0x2, + /// PA2 + PA2 = 0x3, }; - /// Controller area network - pub const CAN = extern struct { - /// master control register - MCR: mmio.Mmio(packed struct(u32) { - /// INRQ - INRQ: u1, - /// SLEEP - SLEEP: u1, - /// TXFP - TXFP: u1, - /// RFLM - RFLM: u1, - /// NART - NART: u1, - /// AWUM - AWUM: u1, - /// ABOM - ABOM: u1, - /// TTCM - TTCM: u1, - reserved15: u7, - /// RESET - RESET: u1, - /// DBF - DBF: u1, - padding: u15, - }), - /// master status register - MSR: mmio.Mmio(packed struct(u32) { - /// INAK - INAK: u1, - /// SLAK - SLAK: u1, - /// ERRI - ERRI: u1, - /// WKUI - WKUI: u1, - /// SLAKI - SLAKI: u1, - reserved8: u3, - /// TXM - TXM: u1, - /// RXM - RXM: u1, - /// SAMP - SAMP: u1, - /// RX - RX: u1, - padding: u20, + pub const PINMUX2 = enum(u2) { + /// PA8 + PA8 = 0x0, + /// PA11 + PA11 = 0x1, + _, + }; + + pub const PINMUX3 = enum(u2) { + /// PA14 + PA14 = 0x0, + /// PB6 + PB6 = 0x1, + /// PC15 + PC15 = 0x2, + _, + }; + + pub const PINMUX4 = enum(u2) { + /// PA7 + PA7 = 0x0, + /// PA12 + PA12 = 0x1, + _, + }; + + pub const PINMUX5 = enum(u2) { + /// PA3 + PA3 = 0x0, + /// PA4 + PA4 = 0x1, + /// PA5 + PA5 = 0x2, + /// PA6 + PA6 = 0x3, + }; + + /// register block + pub const SYSCFG = extern struct { + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details. + MEM_MODE: packed union { + raw: u2, + value: MEM_MODE, + }, + reserved3: u1, + /// PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. + PA11_RMP: u1, + /// PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. + PA12_RMP: u1, + /// IR output polarity selection + IR_POL: u1, + /// IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope: + IR_MOD: packed union { + raw: u2, + value: IR_MOD, + }, + reserved16: u8, + /// Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. + I2C_PB6_FMP: u1, + /// Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. + I2C_PB7_FMP: u1, + /// Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. + I2C_PB8_FMP: u1, + /// Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. + I2C_PB9_FMP: u1, + /// Fast Mode Plus (FM+) enable for I2C1 This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers. With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C1 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored. + I2C1_FMP: u1, + reserved22: u1, + /// Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. + I2C_PA9_FMP: u1, + /// Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. + I2C_PA10_FMP: u1, + /// Fast Mode Plus (FM+) enable for PC14 This bit is set and cleared by software. It enables I2C FM+ driving capability on PC14 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. + I2C_PC14_FMP: u1, + padding: u7, }), - /// transmit status register - TSR: mmio.Mmio(packed struct(u32) { - /// RQCP0 - RQCP: u1, - /// TXOK0 - TXOK: u1, - /// ALST0 - ALST: u1, - /// TERR0 - TERR: u1, - reserved7: u3, - /// ABRQ0 - ABRQ: u1, - reserved24: u16, - /// CODE - CODE: u2, - /// Lowest priority flag for mailbox 0 - TME: u1, - reserved29: u2, - /// Lowest priority flag for mailbox 0 - LOW: u1, - padding: u2, + reserved24: [20]u8, + /// configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Cortex�-M0+ LOCKUP enable This bit is set by software and cleared by system reset. When set, it enables the connection of Cortex�-M0+ LOCKUP (HardFault) output to the TIM1/16/17 Break input. + LOCKUP_LOCK: u1, + padding: u31, }), - /// receive FIFO 0 register - RFR: [2]mmio.Mmio(packed struct(u32) { - /// FMP0 - FMP: u2, - reserved3: u1, - /// FULL0 - FULL: u1, - /// FOVR0 - FOVR: u1, - /// RFOM0 - RFOM: u1, - padding: u26, + reserved60: [32]u8, + /// configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// Pin GPIO multiplexer 0 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved Pin F2 of WLCSP14 package GPIO assignment 1x: Reserved + PINMUX0: packed union { + raw: u2, + value: PINMUX0, + }, + /// Pin GPIO multiplexer 1 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved + PINMUX1: packed union { + raw: u2, + value: PINMUX1, + }, + /// Pin GPIO multiplexer 2 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 1x: Reserved + PINMUX2: packed union { + raw: u2, + value: PINMUX2, + }, + /// Pin GPIO multiplexer 3 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved + PINMUX3: packed union { + raw: u2, + value: PINMUX3, + }, + /// Pin GPIO multiplexer 4 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 1x: Reserved + PINMUX4: packed union { + raw: u2, + value: PINMUX4, + }, + /// Pin GPIO multiplexer 5 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved + PINMUX5: packed union { + raw: u2, + value: PINMUX5, + }, + padding: u20, }), - /// interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// TMEIE - TMEIE: u1, - /// FMPIE0 - FMPIE: u1, - /// FFIE0 - FFIE: u1, - /// FOVIE0 - FOVIE: u1, - reserved8: u4, - /// EWGIE - EWGIE: u1, - /// EPVIE - EPVIE: u1, - /// BOFIE - BOFIE: u1, - /// LECIE - LECIE: u1, - reserved15: u3, - /// ERRIE - ERRIE: u1, - /// WKUIE - WKUIE: u1, - /// SLKIE - SLKIE: u1, - padding: u14, + reserved128: [64]u8, + /// interrupt line 0 status register + ITLINE0: mmio.Mmio(packed struct(u32) { + /// Window watchdog interrupt pending flag + WWDG: u1, + padding: u31, }), - /// error status register - ESR: mmio.Mmio(packed struct(u32) { - /// EWGF - EWGF: u1, - /// EPVF - EPVF: u1, - /// BOFF - BOFF: u1, - reserved4: u1, - /// LEC - LEC: packed union { - raw: u3, - value: LEC, - }, - reserved16: u9, - /// TEC - TEC: u8, - /// REC - REC: u8, + reserved136: [4]u8, + /// interrupt line 2 status register + ITLINE2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// RTC interrupt request pending (EXTI line 19) + RTC: u1, + padding: u30, }), - /// bit timing register - BTR: mmio.Mmio(packed struct(u32) { - /// BRP - BRP: u10, - reserved16: u6, - /// TS1 - TS: u4, - reserved24: u4, - /// SJW - SJW: u2, - reserved30: u4, - /// Loop Back Mode enabled - LBKM: u1, - /// SILM - SILM: packed union { - raw: u1, - value: SILM, - }, + /// interrupt line 3 status register + ITLINE3: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Flash interface interrupt request pending + FLASH_ITF: u1, + padding: u30, }), - reserved384: [352]u8, - /// CAN Transmit cluster - TX: u32, - reserved432: [44]u8, - /// CAN Receive cluster - RX: u32, - reserved512: [76]u8, - /// filter master register - FMR: mmio.Mmio(packed struct(u32) { - /// FINIT - FINIT: u1, - reserved8: u7, - /// CAN2SB - CAN2SB: u6, - padding: u18, + /// interrupt line 4 status register + ITLINE4: mmio.Mmio(packed struct(u32) { + /// Reset and clock control interrupt request pending + RCC: u1, + padding: u31, }), - /// filter mode register - FM1R: mmio.Mmio(packed struct(u32) { - /// Filter mode - FBM: u1, + /// interrupt line 5 status register + ITLINE5: mmio.Mmio(packed struct(u32) { + /// EXTI + EXTI: u1, padding: u31, }), - reserved524: [4]u8, - /// filter scale register - FS1R: mmio.Mmio(packed struct(u32) { - /// Filter scale configuration - FSC: u1, + /// interrupt line 6 status register + ITLINE6: mmio.Mmio(packed struct(u32) { + /// EXTI + EXTI: u1, padding: u31, }), - reserved532: [4]u8, - /// filter FIFO assignment register - FFA1R: mmio.Mmio(packed struct(u32) { - /// Filter FIFO assignment for filter 0 - FFA: u1, + /// interrupt line 7 status register + ITLINE7: mmio.Mmio(packed struct(u32) { + /// EXTI + EXTI: u1, padding: u31, }), - reserved540: [4]u8, - /// filter activation register - FA1R: mmio.Mmio(packed struct(u32) { - /// Filter active - FACT: u1, + reserved164: [4]u8, + /// interrupt line 9 status register + ITLINE9: mmio.Mmio(packed struct(u32) { + /// DMA1 channel 1interrupt request pending + DMA1_CH1: u1, padding: u31, }), - reserved576: [32]u8, - /// CAN Filter Bank cluster - FB: u32, - }; - - /// CAN Filter Bank cluster - pub const FB = extern struct { - /// Filter bank 0 register 1 - FR1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FB: u1, + /// interrupt line 10 status register + ITLINE10: mmio.Mmio(packed struct(u32) { + /// DMA1 channel 2 interrupt request pending + DMA1_CH2: u1, + /// DMA1 channel 3 interrupt request pending + DMA1_CH3: u1, + padding: u30, + }), + /// interrupt line 11 status register + ITLINE11: mmio.Mmio(packed struct(u32) { + /// DMAMUX interrupt request pending + DMAMUX: u1, padding: u31, }), - /// Filter bank 0 register 2 - FR2: mmio.Mmio(packed struct(u32) { - /// Filter bits - FB: u1, + /// interrupt line 12 status register + ITLINE12: mmio.Mmio(packed struct(u32) { + /// ADC interrupt request pending + ADC: u1, padding: u31, }), - }; - - /// CAN Receive cluster - pub const RX = extern struct { - /// receive FIFO mailbox identifier register - RIR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// RTR - RTR: packed union { - raw: u1, - value: RTR, - }, - /// IDE - IDE: packed union { - raw: u1, - value: IDE, - }, - /// EXID - EXID: u18, - /// STID - STID: u11, + /// interrupt line 13 status register + ITLINE13: mmio.Mmio(packed struct(u32) { + /// Timer 1 commutation interrupt request pending + TIM1_CCU: u1, + /// Timer 1 trigger interrupt request pending + TIM1_TRG: u1, + /// Timer 1 update interrupt request pending + TIM1_UPD: u1, + /// Timer 1 break interrupt request pending + TIM1_BRK: u1, + padding: u28, }), - /// mailbox data high register - RDTR: mmio.Mmio(packed struct(u32) { - /// DLC - DLC: u4, - reserved8: u4, - /// FMI - FMI: u8, - /// TIME - TIME: u16, + /// interrupt line 14 status register + ITLINE14: mmio.Mmio(packed struct(u32) { + /// Timer 1 capture compare interrupt request pending + TIM1_CC: u1, + padding: u31, }), - /// mailbox data high register - RDLR: mmio.Mmio(packed struct(u32) { - /// DATA0 - DATA: u8, - padding: u24, + reserved192: [4]u8, + /// interrupt line 16 status register + ITLINE16: mmio.Mmio(packed struct(u32) { + /// Timer 3 interrupt request pending + TIM3: u1, + padding: u31, }), - /// receive FIFO mailbox data high register - RDHR: mmio.Mmio(packed struct(u32) { - /// DATA4 - DATA: u8, - padding: u24, + reserved204: [8]u8, + /// interrupt line 19 status register + ITLINE19: mmio.Mmio(packed struct(u32) { + /// Timer 14 interrupt request pending + TIM14: u1, + padding: u31, }), - }; - - /// CAN Transmit cluster - pub const TX = extern struct { - /// TX mailbox identifier register - TIR: mmio.Mmio(packed struct(u32) { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: packed union { - raw: u1, - value: RTR, - }, - /// IDE - IDE: packed union { - raw: u1, - value: IDE, - }, - /// EXID - EXID: u18, - /// STID - STID: u11, + reserved212: [4]u8, + /// interrupt line 21 status register + ITLINE21: mmio.Mmio(packed struct(u32) { + /// Timer 16 interrupt request pending + TIM16: u1, + padding: u31, }), - /// mailbox data length control and time stamp register - TDTR: mmio.Mmio(packed struct(u32) { - /// DLC - DLC: u4, - reserved8: u4, - /// TGT - TGT: u1, - reserved16: u7, - /// TIME - TIME: u16, + /// interrupt line 22 status register + ITLINE22: mmio.Mmio(packed struct(u32) { + /// Timer 17 interrupt request pending + TIM17: u1, + padding: u31, }), - /// mailbox data low register - TDLR: mmio.Mmio(packed struct(u32) { - /// DATA0 - DATA: u8, - padding: u24, + /// interrupt line 23 status register + ITLINE23: mmio.Mmio(packed struct(u32) { + /// I2C1 interrupt request pending, combined with EXTI line 23 + I2C1: u1, + padding: u31, }), - /// mailbox data high register - TDHR: mmio.Mmio(packed struct(u32) { - /// DATA4 - DATA: u8, - padding: u24, + reserved228: [4]u8, + /// interrupt line 25 status register + ITLINE25: mmio.Mmio(packed struct(u32) { + /// SPI1 interrupt request pending + SPI1: u1, + padding: u31, + }), + reserved236: [4]u8, + /// interrupt line 27 status register + ITLINE27: mmio.Mmio(packed struct(u32) { + /// USART1 interrupt request pending, combined with EXTI line 25 + USART1: u1, + padding: u31, + }), + /// interrupt line 28 status register + ITLINE28: mmio.Mmio(packed struct(u32) { + /// USART2 interrupt request pending (EXTI line 26) + USART2: u1, + padding: u31, }), }; }; - pub const rtc_v3 = struct { - pub const ALRF = enum(u1) { - /// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - Match = 0x1, - _, + pub const syscfg_f0 = struct { + pub const FMP = enum(u1) { + /// Standard + Standard = 0x0, + /// FM+ + FMP = 0x1, }; - pub const ALRMF = enum(u1) { - /// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - Match = 0x1, + pub const IR_MOD = enum(u2) { + /// TIM16 selected + TIM16 = 0x0, + /// USART1 selected + USART1 = 0x1, + /// USART4 selected + USART4 = 0x2, _, }; - pub const ALRMR_MSK = enum(u1) { - /// Alarm set if the date/day match - ToMatch = 0x0, - /// Date/day don’t care in Alarm comparison - NotMatch = 0x1, - }; - - pub const ALRMR_PM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, - }; - - pub const ALRMR_WDSEL = enum(u1) { - /// DU[3:0] represents the date units - DateUnits = 0x0, - /// DU[3:0] represents the week day. DT[1:0] is don’t care. - WeekDay = 0x1, - }; - - pub const ALRMSSR_SSCLR = enum(u1) { - /// The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running - FreeRunning = 0x0, - /// The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0] - ALRMBINR = 0x1, + pub const MEM_MODE = enum(u2) { + /// Main Flash memory mapped at 0x0000_0000 + MainFlash = 0x0, + /// System Flash memory mapped at 0x0000_0000 + SystemFlash = 0x1, + /// Main Flash memory mapped at 0x0000_0000 + MainFlash2 = 0x2, + /// Embedded SRAM mapped at 0x0000_0000 + SRAM = 0x3, }; - pub const AMPM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, + /// System configuration controller + pub const SYSCFG = extern struct { + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection bits + MEM_MODE: packed union { + raw: u2, + value: MEM_MODE, + }, + reserved4: u2, + /// PA11 and PA12 remapping bit for small packages (28 and 20 pins) 0: Pin pair PA9/PA10 mapped on the pins 1: Pin pair PA11/PA12 mapped instead of PA9/PA10 + PA11_PA12_RMP: u1, + reserved6: u1, + /// IR Modulation Envelope signal selection + IR_MOD: packed union { + raw: u2, + value: IR_MOD, + }, + /// ADC DMA remapping bit 0: ADC DMA request mapped on DMA channel 1 1: ADC DMA request mapped on DMA channel 2 + ADC_DMA_RMP: u1, + /// USART1_TX DMA remapping bit 0: USART1_TX DMA request mapped on DMA channel 2 1: USART1_TX DMA request mapped on DMA channel 4 + USART1_TX_DMA_RMP: u1, + /// USART1_RX DMA request remapping bit 0: USART1_RX DMA request mapped on DMA channel 3 1: USART1_RX DMA request mapped on DMA channel 5 + USART1_RX_DMA_RMP: u1, + /// TIM16 DMA request remapping bit 0: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3 1: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4 + TIM16_DMA_RMP: u1, + /// TIM17 DMA request remapping bit 0: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1 1: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2 + TIM17_DMA_RMP: u1, + /// TIM16 alternate DMA request remapping bit 0: TIM16 DMA request mapped according to TIM16_DMA_RMP bit 1: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6 + TIM16_DMA_RMP2: u1, + /// TIM17 alternate DMA request remapping bit 0: TIM17 DMA request mapped according to TIM16_DMA_RMP bit 1: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7 + TIM17_DMA_RMP2: u1, + reserved16: u1, + /// Fast Mode Plus (FM plus) driving capability activation bits. 0: PB6 pin operate in standard mode 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed + I2C_PB6_FMP: packed union { + raw: u1, + value: FMP, + }, + /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB7 pin operate in standard mode 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed + I2C_PB7_FMP: packed union { + raw: u1, + value: FMP, + }, + /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB8 pin operate in standard mode 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed + I2C_PB8_FMP: packed union { + raw: u1, + value: FMP, + }, + /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB9 pin operate in standard mode 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed + I2C_PB9_FMP: packed union { + raw: u1, + value: FMP, + }, + /// FM+ driving capability activation for I2C1 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers + I2C1_FMP: packed union { + raw: u1, + value: FMP, + }, + /// FM+ driving capability activation for I2C2 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers + I2C2_FMP: packed union { + raw: u1, + value: FMP, + }, + /// Fast Mode Plus (FM+) driving capability activation bits 0: PA9 pin operate in standard mode 1: I2C FM+ mode enabled on PA9 and the Speed control is bypassed + I2C_PA9_FMP: packed union { + raw: u1, + value: FMP, + }, + /// Fast Mode Plus (FM+) driving capability activation bits 0: PA10 pin operate in standard mode 1: I2C FM+ mode enabled on PA10 and the Speed control is bypassed + I2C_PA10_FMP: packed union { + raw: u1, + value: FMP, + }, + /// SPI2 DMA request remapping bit 0: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively 1: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively + SPI2_DMA_RMP: u1, + /// USART2 DMA request remapping bit 0: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively 1: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively + USART2_DMA_RMP: u1, + /// USART3 DMA request remapping bit 0: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0) 1: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively + USART3_DMA_RMP: u1, + /// I2C1 DMA request remapping bit 0: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively 1: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively + I2C1_DMA_RMP: u1, + /// TIM1 DMA request remapping bit 0: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively 1: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 + TIM1_DMA_RMP: u1, + /// TIM2 DMA request remapping bit 0: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively 1: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 + TIM2_DMA_RMP: u1, + /// TIM3 DMA request remapping bit 0: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 1: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 + TIM3_DMA_RMP: u1, + padding: u1, + }), + reserved8: [4]u8, + /// external interrupt configuration register 1 + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI configuration bits + EXTI: u4, + padding: u28, + }), + /// configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Cortex-M0 LOCKUP bit enable bit + LOCKUP_LOCK: u1, + /// SRAM parity lock bit + SRAM_PARITY_LOCK: u1, + /// PVD lock enable bit + PVD_LOCK: u1, + reserved8: u5, + /// SRAM parity flag + SRAM_PEF: u1, + padding: u23, + }), }; + }; - pub const BCDU = enum(u3) { - /// 1s increment each time SS[7:0]=0 - Bit7 = 0x0, - /// 1s increment each time SS[8:0]=0 - Bit8 = 0x1, - /// 1s increment each time SS[9:0]=0 - Bit9 = 0x2, - /// 1s increment each time SS[10:0]=0 - Bit10 = 0x3, - /// 1s increment each time SS[11:0]=0 - Bit11 = 0x4, - /// 1s increment each time SS[12:0]=0 - Bit12 = 0x5, - /// 1s increment each time SS[13:0]=0 - Bit13 = 0x6, - /// 1s increment each time SS[14:0]=0 - Bit14 = 0x7, + pub const syscfg_f2 = struct { + pub const MEM_MODE = enum(u2) { + /// Main Flash memory mapped at 0x0000_0000 + MainFlash = 0x0, + /// System Flash memory mapped at 0x0000_0000 + SystemFlash = 0x1, + /// FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000_0000 + FSMC = 0x2, + /// Embedded SRAM mapped at 0x0000_0000 + SRAM = 0x3, }; - pub const BIN = enum(u2) { - /// Free running BCD calendar mode (Binary mode disabled) - BCD = 0x0, - /// Free running Binary mode (BCD mode disabled) - Binary = 0x1, - /// Free running BCD calendar and Binary modes - BinBCD = 0x2, - /// Free running BCD calendar and Binary modes - BinBCD2 = 0x3, + /// System configuration controller + pub const SYSCFG = extern struct { + /// memory remap register + MEMRMP: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection + MEM_MODE: packed union { + raw: u2, + value: MEM_MODE, + }, + padding: u30, + }), + /// peripheral mode configuration register + PMC: mmio.Mmio(packed struct(u32) { + reserved23: u23, + /// Ethernet PHY interface selection + MII_RMII_SEL: u1, + padding: u8, + }), + /// external interrupt configuration register 1 + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 0 to 3) + EXTI: u4, + padding: u28, + }), + reserved32: [8]u8, + /// Compensation cell control register + CMPCR: mmio.Mmio(packed struct(u32) { + /// Compensation cell power-down + CMP_PD: u1, + reserved8: u7, + /// Compensation cell ready flag + READY: u1, + padding: u23, + }), }; + }; - pub const CALP = enum(u1) { - /// No RTCCLK pulses are added - NoChange = 0x0, - /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - IncreaseFreq = 0x1, + pub const syscfg_f3 = struct { + pub const ADC12_EXT13_RMP = enum(u1) { + /// Trigger source is TIM6_TRGO + Tim6 = 0x0, + /// Trigger source is TIM20_CC2 + Tim20 = 0x1, }; - pub const CALRF = enum(u1) { - /// Clear interrupt flag by writing 1 - Clear = 0x1, - _, + pub const ADC12_EXT15_RMP = enum(u1) { + /// Trigger source is TIM3_CC4 + Tim3 = 0x0, + /// Trigger source is TIM20_CC3 + Tim20 = 0x1, }; - pub const CALW16 = enum(u1) { - /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 - SixteenSeconds = 0x1, - _, + pub const ADC12_EXT2_RMP = enum(u1) { + /// Trigger source is TIM3_CC3 + Tim1 = 0x0, + /// rigger source is TIM20_TRGO + Tim20 = 0x1, }; - pub const CALW8 = enum(u1) { - /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected - EightSeconds = 0x1, - _, + pub const ADC12_EXT3_RMP = enum(u1) { + /// Trigger source is TIM2_CC2 + Tim2 = 0x0, + /// rigger source is TIM20_TRGO2 + Tim20 = 0x1, }; - pub const COSEL = enum(u1) { - /// Calibration output is 512 Hz (with default prescaler setting) - CalFreq_512Hz = 0x0, - /// Calibration output is 1 Hz (with default prescaler setting) - CalFreq_1Hz = 0x1, + pub const ADC12_EXT5_RMP = enum(u1) { + /// Trigger source is TIM4_CC4 + Tim4 = 0x0, + /// Trigger source is TIM20_CC1 + Tim20 = 0x1, }; - pub const FMT = enum(u1) { - /// 24 hour/day format - TwentyFourHour = 0x0, - /// AM/PM hour format - AmPm = 0x1, + pub const ADC12_JEXT13_RMP = enum(u1) { + /// Trigger source is TIM3_CC1 + Tim3 = 0x0, + /// Trigger source is TIM20_CC4 + Tim20 = 0x1, }; - pub const ITSF = enum(u1) { - /// This flag is set by hardware when a timestamp on the internal event occurs - TimestampEvent = 0x1, - _, + pub const ADC12_JEXT3_RMP = enum(u1) { + /// Trigger source is TIM2_CC1 + Tim2 = 0x0, + /// Trigger source is TIM20_TRGO + Tim20 = 0x1, }; - pub const ITSMF = enum(u1) { - /// This flag is set by hardware when a timestamp on the internal event occurs - TimestampEvent = 0x1, - _, + pub const ADC12_JEXT6_RMP = enum(u1) { + /// Trigger source is EXTI line 15 + Exti15 = 0x0, + /// Trigger source is TIM20_TRGO2 + Tim20 = 0x1, }; - pub const KEY = enum(u8) { - /// Activate write protection (any value that is not the keys) - Activate = 0x0, - /// Key 2 - Deactivate2 = 0x53, - /// Key 1 - Deactivate1 = 0xca, + pub const ADC2_DMA_RMP_CFGR3 = enum(u2) { + /// ADC2 mapped on DMA1 channel 2 + MapDma1Ch2 = 0x2, + /// ADC2 mapped on DMA1 channel 4 + MapDma1Ch4 = 0x3, _, }; - pub const LPCAL = enum(u1) { - /// Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required - RTCCLK = 0x0, - /// Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode - CkApre = 0x1, - }; - - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Alarm B output enabled - AlarmB = 0x2, - /// Wakeup output enabled - Wakeup = 0x3, + pub const ADC34_EXT15_RMP = enum(u1) { + /// Trigger source is TIM2_CC1 + Tim2 = 0x0, + /// Trigger source is TIM20_CC1 + Tim20 = 0x1, }; - pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - Low = 0x1, + pub const ADC34_EXT5_RMP = enum(u1) { + /// Trigger source is EXTI line 2 when reset at 0 + Exti2 = 0x0, + /// Trigger source is TIM20_TRGO + Tim20 = 0x1, }; - pub const RECALPF = enum(u1) { - /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 - Pending = 0x1, - _, + pub const ADC34_EXT6_RMP = enum(u1) { + /// Trigger source is TIM4_CC1 + Tim4 = 0x0, + /// Trigger source is TIM20_TRGO2 + Tim20 = 0x1, }; - pub const SSRUF = enum(u1) { - /// This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 - Underflow = 0x1, - _, + pub const ADC34_JEXT11_RMP = enum(u1) { + /// Trigger source is TIM1_CC3 + Tim1 = 0x0, + /// Trigger source is TIM20_TRGO2 + Tim20 = 0x1, }; - pub const SSRUMF = enum(u1) { - /// This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 - Underflow = 0x1, - _, + pub const ADC34_JEXT14_RMP = enum(u1) { + /// Trigger source is TIM7_TRGO + Tim7 = 0x0, + /// Trigger source is TIM20_CC2 + Tim20 = 0x1, }; - pub const TAMPALRM_TYPE = enum(u1) { - /// TAMPALRM is push-pull output - PushPull = 0x0, - /// TAMPALRM is open-drain output - OpenDrain = 0x1, + pub const ADC34_JEXT5_RMP = enum(u1) { + /// Trigger source is TIM4_CC3 + Tim4 = 0x0, + /// Trigger source is TIM20_TRGO + Tim20 = 0x1, }; - pub const TSEDGE = enum(u1) { - /// RTC_TS input rising edge generates a time-stamp event - RisingEdge = 0x0, - /// RTC_TS input falling edge generates a time-stamp event - FallingEdge = 0x1, + pub const DAC1_TRIG3_RMP = enum(u1) { + /// DAC trigger is TIM15_TRGO + Tim15 = 0x0, + /// DAC trigger is HRTIM1_DAC1_TRIG1 + HrTim1 = 0x1, }; - pub const TSF = enum(u1) { - /// This flag is set by hardware when a time-stamp event occurs - TimestampEvent = 0x1, + pub const ENCODER_MODE = enum(u2) { + /// No redirection + NoRedirection = 0x0, + /// TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively + MapTim2Tim15 = 0x1, + /// TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively + MapTim3Tim15 = 0x2, _, }; - pub const TSMF = enum(u1) { - /// This flag is set by hardware when a time-stamp event occurs - TimestampEvent = 0x1, - _, + pub const FMP = enum(u1) { + /// Standard + Standard = 0x0, + /// FM+ + FMP = 0x1, }; - pub const TSOVF = enum(u1) { - /// This flag is set by hardware when a time-stamp event occurs while TSF is already set - Overflow = 0x1, + pub const I2C1_RX_DMA_RMP = enum(u2) { + /// I2C1_RX mapped on DMA1 CH7 + MapDma1Ch7 = 0x0, + /// I2C1_RX mapped on DMA1 CH3 + MapDma1Ch3 = 0x1, + /// I2C1_RX mapped on DMA1 CH5 + MapDma1Ch5 = 0x2, _, }; - pub const TSOVMF = enum(u1) { - /// This flag is set by hardware when a time-stamp event occurs while TSF is already set - Overflow = 0x1, + pub const I2C1_TX_DMA_RMP = enum(u2) { + /// I2C1_TX mapped on DMA1 CH6 + MapDma1Ch6 = 0x0, + /// I2C1_TX mapped on DMA1 CH2 + MapDma1Ch2 = 0x1, + /// I2C1_TX mapped on DMA1 CH4 + MapDma1Ch4 = 0x2, _, }; - pub const WUCKSEL = enum(u3) { - /// RTC/16 clock is selected - Div16 = 0x0, - /// RTC/8 clock is selected - Div8 = 0x1, - /// RTC/4 clock is selected - Div4 = 0x2, - /// RTC/2 clock is selected - Div2 = 0x3, - /// ck_spre (usually 1 Hz) clock is selected - ClockSpare = 0x4, - /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - ClockSpareWithOffset = 0x6, - _, + pub const MEM_MODE = enum(u2) { + /// Main Flash memory mapped at 0x0000_0000 + MainFlash = 0x0, + /// System Flash memory mapped at 0x0000_0000 + SystemFlash = 0x1, + /// Main Flash memory mapped at 0x0000_0000 + MainFlash2 = 0x2, + /// Embedded SRAM mapped at 0x0000_0000 + SRAM = 0x3, }; - pub const WUTF = enum(u1) { - /// This flag is set by hardware when the wakeup auto-reload counter reaches 0 - Zero = 0x1, + pub const SPI1_RX_DMA_RMP = enum(u2) { + /// SPI1_RX mapped on DMA1 CH2 + MapDma1Ch3 = 0x0, + /// SPI1_RX mapped on DMA1 CH4 + MapDma1Ch5 = 0x1, + /// SPI1_RX mapped on DMA1 CH6 + MapDma1Ch7 = 0x2, _, }; - pub const WUTMF = enum(u1) { - /// This flag is set by hardware when the wakeup auto-reload counter reaches 0 - Zero = 0x1, + pub const SPI1_TX_DMA_RMP = enum(u2) { + /// SPI1_TX mapped on DMA1 CH3 + MapDma1Ch3 = 0x0, + /// SPI1_TX mapped on DMA1 CH5 + MapDma1Ch5 = 0x1, + /// SPI1_TX mapped on DMA1 CH7 + MapDma1Ch7 = 0x2, _, }; - /// Real-time clock - pub const RTC = extern struct { - /// Time register - TR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, - }), - /// Date register - DR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding: u8, - }), - /// Sub second register - SSR: mmio.Mmio(packed struct(u32) { - /// Synchronous binary counter - SS: u32, - }), - /// Initialization control and status register - ICSR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Wakeup timer write enabled - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Enter Initialization mode - INIT: u1, - /// Binary mode - BIN: packed union { - raw: u2, - value: BIN, - }, - /// BCD update - BCDU: packed union { - raw: u3, - value: BCDU, - }, - reserved16: u3, - /// Recalibration pending Flag - RECALPF: packed union { - raw: u1, - value: RECALPF, - }, - padding: u15, - }), - /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, - padding: u9, - }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, - /// Wakeup auto-reload output clear value - WUTOCLR: u16, - }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Wakeup clock selection - WUCKSEL: packed union { - raw: u3, - value: WUCKSEL, - }, - /// Timestamp event active edge - TSEDGE: packed union { - raw: u1, - value: TSEDGE, - }, - /// RTC_REFIN reference clock detection enable (50 or 60 Hz) - REFCKON: u1, - /// Bypass the shadow registers - BYPSHAD: u1, - /// Hour format - FMT: packed union { - raw: u1, - value: FMT, - }, - /// SSR underflow interrupt enable - SSRUIE: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, - /// Wakeup timer enable - WUTE: u1, - /// Timestamp enable - TSE: u1, - /// Alarm interrupt enable - ALRAIE: u1, - reserved14: u1, - /// Wakeup timer interrupt enable - WUTIE: u1, - /// Timestamp interrupt enable - TSIE: u1, - /// Add 1 hour (summer time change) - ADD1H: u1, - /// Subtract 1 hour (winter time change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output selection - COSEL: packed union { - raw: u1, - value: COSEL, - }, - /// Output polarity - POL: packed union { - raw: u1, - value: POL, - }, - /// Output selection - OSEL: packed union { + /// System configuration controller + pub const SYSCFG = extern struct { + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection bits + MEM_MODE: packed union { raw: u2, - value: OSEL, - }, - /// Calibration output enable - COE: u1, - /// Timestamp on internal event enable - ITSE: u1, - /// Activate timestamp on tamper detection event - TAMPTS: u1, - /// Tamper detection output enable on TAMPALRM - TAMPOE: u1, - reserved29: u2, - /// TAMPALRM pull-up enable - TAMPALRM_PU: u1, - /// TAMPALRM output type - TAMPALRM_TYPE: packed union { - raw: u1, - value: TAMPALRM_TYPE, - }, - /// RTC_OUT2 output enable - OUT2EN: u1, - }), - reserved36: [8]u8, - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: packed union { - raw: u8, - value: KEY, - }, - padding: u24, - }), - /// Calibration register - CALR: mmio.Mmio(packed struct(u32) { - /// Calibration minus - CALM: u9, - reserved12: u3, - /// Calibration low-power mode - LPCAL: packed union { - raw: u1, - value: LPCAL, + value: MEM_MODE, }, - /// Use a 16-second calibration cycle period - CALW16: packed union { + reserved5: u3, + /// USB interrupt remap 0: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively 1: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively + USB_IT_RMP: u1, + /// Timer 1 ITR3 selection 0: Not remapped 1: TIM1_ITR3 = TIM17_OC + TIM1_ITR3_RMP: u1, + /// DAC trigger remap (when TSEL = 001) 0: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices 1: DAC trigger is TIM3_TRGO + DAC1_TRIG_RMP: u1, + /// ADC24 DMA remapping bit 0: ADC24 DMA requests mapped on DMA2 channels 1 and 2 1: ADC24 DMA requests mapped on DMA2 channels 3 and 4 + ADC2_DMA_RMP: u1, + reserved11: u2, + /// TIM16 DMA request remapping bit 0: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 1: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 + TIM16_DMA_RMP: u1, + /// TIM17 DMA request remapping bit 0: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 1: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 + TIM17_DMA_RMP: u1, + /// TIM6 and DAC1 DMA request remapping bit 0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 + TIM6_DAC1_CH1_DMA_RMP: u1, + /// TIM7 and DAC2 DMA request remapping bit 0: Not remapped 1: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4 + TIM7_DAC1_CH2_DMA_RMP: u1, + /// DAC2 channel1 DMA remap 0: Not remapped 1: DAC2_CH1 DMA requests mapped on DMA1 channel 5 + DAC2_CH1_DMA_RMP: u1, + /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB6 pin operate in standard mode 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed + I2C_PB6_FMP: packed union { raw: u1, - value: CALW16, + value: FMP, }, - /// Use an 8-second calibration cycle period - CALW8: packed union { + /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB7 pin operate in standard mode 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed + I2C_PB7_FMP: packed union { raw: u1, - value: CALW8, + value: FMP, }, - /// Increase frequency of RTC by 488.5 ppm - CALP: packed union { + /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB8 pin operate in standard mode 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed + I2C_PB8_FMP: packed union { raw: u1, - value: CALP, + value: FMP, }, - padding: u16, - }), - /// Shift control register - SHIFTR: mmio.Mmio(packed struct(u32) { - /// Subtract a fraction of a second - SUBFS: u15, - reserved31: u16, - /// Add one second - ADD1S: u1, - }), - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - padding: u9, - }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding: u16, - }), - /// Timestamp sub second register - TSSSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u32, - }), - reserved64: [4]u8, - /// Alarm register - ALRMR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm A seconds mask - MSK1: packed union { + /// Fast Mode Plus (FM+) driving capability activation bits. 0: PB9 pin operate in standard mode 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed + I2C_PB9_FMP: packed union { raw: u1, - value: ALRMR_MSK, + value: FMP, }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm A minutes mask - MSK2: packed union { + /// I2C1 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits + I2C1_FMP: packed union { raw: u1, - value: ALRMR_MSK, + value: FMP, }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { + /// I2C2 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits + I2C2_FMP: packed union { raw: u1, - value: ALRMR_PM, + value: FMP, }, - /// Alarm A hours mask - MSK3: packed union { - raw: u1, - value: ALRMR_MSK, + /// Encoder mode + ENCODER_MODE: packed union { + raw: u2, + value: ENCODER_MODE, }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { + /// I2C3 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits + I2C3_FMP: packed union { raw: u1, - value: ALRMR_WDSEL, + value: FMP, }, - /// Alarm A date mask - MSK4: packed union { + reserved26: u1, + /// Idx 0: Invalid operation interrupt enable; Idx 1: Devide-by-zero interrupt enable; Idx 2: Underflow interrupt enable; Idx 3: Overflow interrupt enable; Idx 4: Input denormal interrupt enable; Idx 5: Inexact interrupt enable + FPU_IE: u1, + padding: u5, + }), + /// CCM SRAM protection register + RCR: mmio.Mmio(packed struct(u32) { + /// CCM SRAM page x write protection enabled + PAGE_WP: u1, + padding: u31, + }), + /// external interrupt configuration register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI x configuration + EXTI: u4, + padding: u28, + }), + /// configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Cortex-M0 LOCKUP bit enable bit + LOCKUP_LOCK: u1, + /// SRAM parity lock bit + SRAM_PARITY_LOCK: u1, + /// PVD lock enable bit + PVD_LOCK: u1, + reserved4: u1, + /// Bypass address bit 29 in parity calculation + BYP_ADDR_PAR: u1, + reserved8: u3, + /// SRAM parity flag + SRAM_PEF: u1, + padding: u23, + }), + reserved72: [44]u8, + /// configuration register 4 + CFGR4: mmio.Mmio(packed struct(u32) { + /// Controls the Input trigger of ADC12 regular channel EXT2 + ADC12_EXT2_RMP: packed union { raw: u1, - value: ALRMR_MSK, + value: ADC12_EXT2_RMP, }, - }), - /// Alarm sub second register - ALRMSSR: mmio.Mmio(packed struct(u32) { - /// Sub seconds value - SS: u15, - reserved24: u9, - /// Mask the most-significant bits starting at this bit - MASKSS: u6, - reserved31: u1, - /// Clear synchronous counter on alarm (Binary mode only) - SSCLR: packed union { + /// Controls the Input trigger of ADC12 regular channel EXT3 + ADC12_EXT3_RMP: packed union { raw: u1, - value: ALRMSSR_SSCLR, + value: ADC12_EXT3_RMP, }, - }), - reserved80: [8]u8, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Alarm flag - ALRF: packed union { + /// Controls the Input trigger of ADC12 regular channel EXT5 + ADC12_EXT5_RMP: packed union { raw: u1, - value: ALRF, + value: ADC12_EXT5_RMP, }, - reserved2: u1, - /// Wakeup timer flag - WUTF: packed union { + /// Controls the Input trigger of ADC12 regular channel EXT13 + ADC12_EXT13_RMP: packed union { raw: u1, - value: WUTF, + value: ADC12_EXT13_RMP, }, - /// Timestamp flag - TSF: packed union { + /// Controls the Input trigger of ADC12 regular channel EXT15 + ADC12_EXT15_RMP: packed union { raw: u1, - value: TSF, + value: ADC12_EXT15_RMP, }, - /// Timestamp overflow flag - TSOVF: packed union { + /// Controls the Input trigger of ADC12 injected channel JEXT3 + ADC12_JEXT3_RMP: packed union { raw: u1, - value: TSOVF, + value: ADC12_JEXT3_RMP, }, - /// Internal timestamp flag - ITSF: packed union { + /// Controls the Input trigger of ADC12 injected channel JEXT6 + ADC12_JEXT6_RMP: packed union { raw: u1, - value: ITSF, + value: ADC12_JEXT6_RMP, }, - /// SSR underflow flag - SSRUF: packed union { + /// Controls the Input trigger of ADC12 injected channel JEXT13 + ADC12_JEXT13_RMP: packed union { raw: u1, - value: SSRUF, + value: ADC12_JEXT13_RMP, }, - padding: u25, - }), - /// Masked interrupt status register - MISR: mmio.Mmio(packed struct(u32) { - /// Alarm masked flag - ALRMF: packed union { + /// Controls the Input trigger of ADC34 regular channel EXT5 + ADC34_EXT5_RMP: packed union { raw: u1, - value: ALRMF, + value: ADC34_EXT5_RMP, }, - reserved2: u1, - /// Wakeup timer masked flag - WUTMF: packed union { + /// Controls the Input trigger of ADC34 regular channel EXT6 + ADC34_EXT6_RMP: packed union { raw: u1, - value: WUTMF, + value: ADC34_EXT6_RMP, }, - /// Timestamp masked flag - TSMF: packed union { + /// Controls the Input trigger of ADC34 regular channel EXT15 + ADC34_EXT15_RMP: packed union { raw: u1, - value: TSMF, + value: ADC34_EXT15_RMP, }, - /// Timestamp overflow masked flag - TSOVMF: packed union { + /// Controls the Input trigger of ADC34 injected channel JEXT5 + ADC34_JEXT5_RMP: packed union { raw: u1, - value: TSOVMF, + value: ADC34_JEXT5_RMP, }, - /// Internal timestamp masked flag - ITSMF: packed union { + /// Controls the Input trigger of ADC34 injected channel JEXT11 + ADC34_JEXT11_RMP: packed union { raw: u1, - value: ITSMF, + value: ADC34_JEXT11_RMP, }, - /// SSR underflow masked flag - SSRUMF: packed union { + /// Controls the Input trigger of ADC34 injected channel JEXT14 + ADC34_JEXT14_RMP: packed union { raw: u1, - value: SSRUMF, + value: ADC34_JEXT14_RMP, }, - padding: u25, + padding: u18, }), - reserved92: [4]u8, - /// Status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear alarm A flag - CALRF: packed union { - raw: u1, - value: CALRF, + reserved80: [4]u8, + /// configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// SPI1_RX DMA remapping bit + SPI1_RX_DMA_RMP: packed union { + raw: u2, + value: SPI1_RX_DMA_RMP, }, - reserved2: u1, - /// Clear wakeup timer flag - CWUTF: packed union { - raw: u1, - value: CALRF, + /// SPI1_TX DMA remapping bit + SPI1_TX_DMA_RMP: packed union { + raw: u2, + value: SPI1_TX_DMA_RMP, }, - /// Clear timestamp flag - CTSF: packed union { - raw: u1, - value: CALRF, + /// I2C1_RX DMA remapping bit + I2C1_RX_DMA_RMP: packed union { + raw: u2, + value: I2C1_RX_DMA_RMP, }, - /// Clear timestamp overflow flag - CTSOVF: packed union { - raw: u1, - value: CALRF, + /// I2C1_TX DMA remapping bit + I2C1_TX_DMA_RMP: packed union { + raw: u2, + value: I2C1_TX_DMA_RMP, }, - /// Clear internal timestamp flag - CITSF: packed union { - raw: u1, - value: CALRF, + /// ADC2 DMA remapping bit + ADC2_DMA_RMP: packed union { + raw: u2, + value: ADC2_DMA_RMP_CFGR3, }, - /// Clear SSR underflow flag - CSSRUF: packed union { + reserved16: u6, + /// DAC1_CH1 / DAC1_CH2 Trigger remap + DAC1_TRIG3_RMP: packed union { raw: u1, - value: CALRF, + value: DAC1_TRIG3_RMP, }, - padding: u25, - }), - reserved112: [16]u8, - /// Alarm binary mode register - ALRBINR: [2]mmio.Mmio(packed struct(u32) { - /// Synchronous counter alarm value in Binary mode - SS: u32, + /// DAC1_CH1 / DAC1_CH2 Trigger remap 0: Not remapped 1: DAC trigger is HRTIM1_DAC1_TRIG2 + DAC1_TRIG5_RMP: u1, + padding: u14, }), }; }; - pub const dbgmcu_g0 = struct { - /// Debug support - pub const DBGMCU = extern struct { - /// MCU Device ID Code Register - IDCODE: mmio.Mmio(packed struct(u32) { - /// Device Identifier - DEV_ID: u16, - /// Revision Identifier - REV_ID: u16, + pub const syscfg_f4 = struct { + /// System configuration controller + pub const SYSCFG = extern struct { + /// memory remap register + MEMRM: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection + MEM_MODE: u3, + reserved8: u5, + /// Flash bank mode selection + FB_MODE: u1, + reserved10: u1, + /// FMC memory mapping swap + SWP_FMC: u2, + padding: u20, }), - /// Debug MCU Configuration Register - CR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Debug Stop Mode - DBG_STOP: u1, - /// Debug Standby Mode - DBG_STANDBY: u1, - padding: u29, + /// peripheral mode configuration register + PMC: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// ADC1DC2 + ADC1DC2: u1, + /// ADC2DC2 + ADC2DC2: u1, + /// ADC3DC2 + ADC3DC2: u1, + reserved23: u4, + /// Ethernet PHY interface selection + MII_RMII_SEL: u1, + padding: u8, }), - /// DBG APB freeze register 1 - APB1FZR: mmio.Mmio(packed struct(u32) { - /// Debug Timer 2 stopped when Core is halted - TIM2: u1, - /// TIM3 counter stopped when core is halted - TIM3: u1, - reserved4: u2, - /// Debug Timer 6 stopped when Core is halted - TIM6: u1, - /// TIM7 counter stopped when core is halted - TIM7: u1, - reserved10: u4, - /// Debug RTC stopped when Core is halted - RTC: u1, - /// Debug Window Wachdog stopped when Core is halted - WWDG: u1, - /// Debug Independent Wachdog stopped when Core is halted - IWDG: u1, - reserved21: u8, - /// I2C1 SMBUS timeout mode stopped when core is halted - I2C1: u1, - reserved30: u8, - /// Clocking of LPTIMER2 counter when the core is halted - LPTIM2: u1, - /// Clocking of LPTIMER1 counter when the core is halted - LPTIM1: u1, + /// external interrupt configuration register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI x configuration + EXTI: u4, + padding: u28, }), - /// DBG APB freeze register 2 - APB2FZR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 - TIM1: u1, - reserved15: u3, - /// TIM14 - TIM14: u1, - /// TIM15 - TIM15: u1, - /// TIM16 - TIM16: u1, - /// TIM17 - TIM17: u1, - padding: u13, + reserved32: [8]u8, + /// Compensation cell control register + CMPCR: mmio.Mmio(packed struct(u32) { + /// Compensation cell power-down + CMP_PD: u1, + reserved8: u7, + /// READY + READY: u1, + padding: u23, }), }; }; - pub const usb_v2 = struct { - pub const DIR = enum(u1) { - /// data transmitted by the USB peripheral to the host PC - To = 0x0, - /// data received by the USB peripheral from the host PC - From = 0x1, - }; - - pub const EP_TYPE = enum(u2) { - /// Bulk endpoint - Bulk = 0x0, - /// Control endpoint - Control = 0x1, - /// Iso endpoint - Iso = 0x2, - /// Interrupt endpoint - Interrupt = 0x3, - }; - - pub const LPMACK = enum(u1) { - /// the valid LPM Token will be NYET - Nyet = 0x0, - /// the valid LPM Token will be ACK - Ack = 0x1, + pub const syscfg_f7 = struct { + /// System configuration controller + pub const SYSCFG = extern struct { + /// memory remap register + MEMRMP: mmio.Mmio(packed struct(u32) { + /// Memory boot mapping + MEM_BOOT: u1, + reserved8: u7, + /// Flash bank mode selection + FB_MODE: u1, + reserved10: u1, + /// FMC memory mapping swap + SWP_FMC: u2, + padding: u20, + }), + /// peripheral mode configuration register + PMC: mmio.Mmio(packed struct(u32) { + /// I2C1_FMP I2C1 Fast Mode + Enable + I2C1_FMP: u1, + /// I2C2_FMP I2C2 Fast Mode + Enable + I2C2_FMP: u1, + /// I2C3_FMP I2C3 Fast Mode + Enable + I2C3_FMP: u1, + /// I2C4 Fast Mode + Enable + I2C4_FMP: u1, + /// PB6_FMP Fast Mode + PB6_FMP: u1, + /// PB7_FMP Fast Mode + Enable + PB7_FMP: u1, + /// PB8_FMP Fast Mode + Enable + PB8_FMP: u1, + /// Fast Mode + Enable + PB9_FMP: u1, + reserved16: u8, + /// ADC3DC2 + ADC1DC2: u1, + /// ADC2DC2 + ADC2DC2: u1, + /// ADC3DC2 + ADC3DC2: u1, + reserved23: u4, + /// Ethernet PHY interface selection + MII_RMII_SEL: u1, + padding: u8, + }), + /// external interrupt configuration register 1 + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 0 to 3) + EXTI: u4, + padding: u28, + }), + reserved32: [8]u8, + /// Compensation cell control register + CMPCR: mmio.Mmio(packed struct(u32) { + /// Compensation cell power-down + CMP_PD: u1, + reserved8: u7, + /// READY + READY: u1, + padding: u23, + }), }; + }; - pub const STAT = enum(u2) { - /// all requests addressed to this endpoint are ignored - Disabled = 0x0, - /// the endpoint is stalled and all requests result in a STALL handshake - Stall = 0x1, - /// the endpoint is naked and all requests result in a NAK handshake - Nak = 0x2, - /// this endpoint is enabled, requests are ACKed - Valid = 0x3, + pub const syscfg_g0 = struct { + pub const MEM_MODE = enum(u2) { + /// Main Flash memory mapped at address 0 + MAIN_FLASH = 0x0, + /// System Flash memory mapped at address 0 + SYSTEM_FLASH = 0x1, + /// Main Flash memory mapped at address 0 (alternate encoding) + MAIN_FLASH_ALT = 0x2, + /// Embedded SRAM mapped at address 0 + SRAM = 0x3, }; - /// Universal serial bus full-speed device interface - pub const USB = extern struct { - /// endpoint register - EPR: [8]mmio.Mmio(packed struct(u32) { - /// EA - EA: u4, - /// STAT_TX - STAT_TX: packed union { - raw: u2, - value: STAT, - }, - /// DTOG_TX - DTOG_TX: u1, - /// CTR_TX - CTR_TX: u1, - /// EP_KIND - EP_KIND: u1, - /// EPTYPE - EP_TYPE: packed union { - raw: u2, - value: EP_TYPE, - }, - /// SETUP - SETUP: u1, - /// STAT_RX - STAT_RX: packed union { + /// System configuration controller + pub const SYSCFG = extern struct { + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details. + MEM_MODE: packed union { raw: u2, - value: STAT, - }, - /// DTOG_RX - DTOG_RX: u1, - /// CTR_RX - CTR_RX: u1, - padding: u16, - }), - reserved64: [32]u8, - /// control register - CNTR: mmio.Mmio(packed struct(u32) { - /// Force a reset of the USB peripheral, exactly like a RESET signaling on the USB - FRES: u1, - /// Enter power down mode - PDWN: u1, - /// Enter low-power mode - LPMODE: u1, - /// Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected - FSUSP: u1, - /// Resume request - RESUME: u1, - /// LPM L1 request request - L1RESUME: u1, - reserved7: u1, - /// L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - L1REQM: u1, - /// ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - ESOFM: u1, - /// SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - SOFM: u1, - /// RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - RESETM: u1, - /// SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - SUSPM: u1, - /// WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - WKUPM: u1, - /// ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - ERRM: u1, - /// PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - PMAOVRM: u1, - /// CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set - CTRM: u1, - padding: u16, - }), - /// interrupt status register - ISTR: mmio.Mmio(packed struct(u32) { - /// EP_ID - EP_ID: u4, - /// DIR - DIR: packed union { - raw: u1, - value: DIR, + value: MEM_MODE, }, - reserved7: u2, - /// LPM command to enter the L1 state is successfully received and acknowledged - L1REQ: u1, - /// an SOF packet is expected but not received - ESOF: u1, - /// beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus - SOF: u1, - /// peripheral detects an active USB RESET signal at its inputs - RESET: u1, - /// no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus - SUSP: u1, - /// activity is detected that wakes up the USB peripheral - WKUP: u1, - /// One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred - ERR: u1, - /// microcontroller has not been able to respond in time to an USB memory request - PMAOVR: u1, - /// endpoint has successfully completed a transaction - CTR: u1, - padding: u16, - }), - /// frame number register - FNR: mmio.Mmio(packed struct(u32) { - /// FN - FN: u11, - /// LSOF - LSOF: u2, - /// the frame timer remains in this state until an USB reset or USB suspend event occurs - LCK: u1, - /// received data minus upstream port data line - RXDM: u1, - /// received data plus upstream port data line - RXDP: u1, - padding: u16, - }), - /// device address - DADDR: mmio.Mmio(packed struct(u32) { - /// device address - ADD: u7, - /// USB device enabled - EF: u1, - padding: u24, + reserved3: u1, + /// PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. + PA11_RMP: u1, + /// PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. + PA12_RMP: u1, + /// IR output polarity selection + IR_POL: u1, + /// IR Modulation Envelope signal selection. + IR_MOD: u2, + /// I/O analog switch voltage booster enable + BOOSTEN: u1, + /// Strobe signal bit for UCPD1 + UCPD1_STROBE: u1, + /// Strobe signal bit for UCPD2 + UCPD2_STROBE: u1, + reserved16: u5, + /// Fast Mode Plus (FM+) driving capability activation bits + I2C_PBx_FMP: u4, + /// FM+ driving capability activation for I2C1 + I2C1_FMP: u1, + /// FM+ driving capability activation for I2C2 + I2C2_FMP: u1, + /// Fast Mode Plus (FM+) driving capability activation bits + I2C_PAx_FMP: u2, + padding: u8, }), - /// Buffer table address - BTABLE: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// BTABLE - BTABLE: u13, - padding: u16, + reserved24: [20]u8, + /// configuration register 1 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Cortex-M0+ LOCKUP bit enable bit + LOCKUP_LOCK: u1, + /// SRAM parity lock bit + SRAM_PARITY_LOCK: u1, + /// PVD lock enable bit + PVD_LOCK: u1, + /// ECC error lock bit + ECC_LOCK: u1, + reserved8: u4, + /// SRAM parity error flag + SRAM_PEF: u1, + reserved16: u7, + /// PA1_CDEN + PA1_CDEN: u1, + /// PA3_CDEN + PA3_CDEN: u1, + /// PA5_CDEN + PA5_CDEN: u1, + /// PA6_CDEN + PA6_CDEN: u1, + /// PA13_CDEN + PA13_CDEN: u1, + /// PB0_CDEN + PB0_CDEN: u1, + /// PB1_CDEN + PB1_CDEN: u1, + /// PB2_CDEN + PB2_CDEN: u1, + padding: u8, }), - /// LPM control and status register - LPMCSR: mmio.Mmio(packed struct(u32) { - /// enable the LPM support within the USB device - LPMEN: u1, - /// LPMACK - LPMACK: packed union { - raw: u1, - value: LPMACK, - }, + reserved48: [20]u8, + /// VREFBUF control and status register + VREFBUF_CSR: mmio.Mmio(packed struct(u32) { + /// Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. + ENVR: u1, + /// High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration. + HIZ: u1, reserved3: u1, - /// REMWAKE - REMWAKE: u1, - /// BESL - BESL: u4, - padding: u24, + /// Voltage reference buffer ready + VRR: u1, + /// Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved + VRS: u3, + padding: u25, }), - }; - }; - - pub const exti_v1 = struct { - /// External interrupt/event controller - pub const EXTI = extern struct { - /// Interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// VREFBUF calibration control register + VREFBUF_CCR: mmio.Mmio(packed struct(u32) { + /// Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage. + TRIM: u6, + padding: u26, }), - /// Interrupt mask register - EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, + reserved128: [72]u8, + /// interrupt line 0 status register + ITLINE0: mmio.Mmio(packed struct(u32) { + /// Window watchdog interrupt pending flag + WWDG: u1, padding: u31, }), - /// Rising Trigger selection register - RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, + /// interrupt line 1 status register + ITLINE1: mmio.Mmio(packed struct(u32) { + /// PVD supply monitoring interrupt request pending (EXTI line 16). + PVDOUT: u1, padding: u31, }), - /// Falling Trigger selection register - FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// interrupt line 2 status register + ITLINE2: mmio.Mmio(packed struct(u32) { + /// TAMP + TAMP: u1, + /// RTC + RTC: u1, + padding: u30, }), - /// Software interrupt event register - SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// interrupt line 3 status register + ITLINE3: mmio.Mmio(packed struct(u32) { + /// FLASH_ITF + FLASH_ITF: u1, + /// FLASH_ECC + FLASH_ECC: u1, + padding: u30, }), - /// Pending register - PR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, + /// interrupt line 4 status register + ITLINE4: mmio.Mmio(packed struct(u32) { + /// RCC + RCC: u1, padding: u31, }), - }; - }; - - pub const usbram_32_2048 = struct { - /// USB Endpoint memory - pub const USBRAM = extern struct { - /// USB Endpoint memory - MEM: [512]u32, - }; - }; - - pub const lcd_v2 = struct { - /// Liquid crystal display controller - pub const LCD = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// LCD controller enable - LCDEN: u1, - /// Voltage source selection - VSEL: u1, - /// Duty selection - DUTY: u3, - /// Bias selector - BIAS: u2, - /// Mux segment enable - MUX_SEG: u1, - /// Voltage output buffer enable - BUFEN: u1, - padding: u23, + /// interrupt line 5 status register + ITLINE5: mmio.Mmio(packed struct(u32) { + /// EXTI0 + EXTI0: u1, + /// EXTI1 + EXTI1: u1, + padding: u30, }), - /// frame control register - FCR: mmio.Mmio(packed struct(u32) { - /// High drive enable - HD: u1, - /// Start of frame interrupt enable - SOFIE: u1, - reserved3: u1, - /// Update display done interrupt enable - UDDIE: u1, - /// Pulse ON duration - PON: u3, - /// Dead time duration - DEAD: u3, - /// Contrast control - CC: u3, - /// Blink frequency selection - BLINKF: u3, - /// Blink mode selection - BLINK: u2, - /// DIV clock divider - DIV: u4, - /// PS 16-bit prescaler - PS: u4, - padding: u6, + /// interrupt line 6 status register + ITLINE6: mmio.Mmio(packed struct(u32) { + /// EXTI2 + EXTI2: u1, + /// EXTI3 + EXTI3: u1, + padding: u30, }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// LCD enabled status - ENS: u1, - /// Start of frame flag - SOF: u1, - /// Update display request - UDR: u1, - /// Update Display Done - UDD: u1, - /// Ready flag - RDY: u1, - /// LCD Frame Control Register Synchronization flag - FCRSF: u1, - padding: u26, + /// interrupt line 7 status register + ITLINE7: mmio.Mmio(packed struct(u32) { + /// EXTI4 + EXTI4: u1, + /// EXTI5 + EXTI5: u1, + /// EXTI6 + EXTI6: u1, + /// EXTI7 + EXTI7: u1, + /// EXTI8 + EXTI8: u1, + /// EXTI9 + EXTI9: u1, + /// EXTI10 + EXTI10: u1, + /// EXTI11 + EXTI11: u1, + /// EXTI12 + EXTI12: u1, + /// EXTI13 + EXTI13: u1, + /// EXTI14 + EXTI14: u1, + /// EXTI15 + EXTI15: u1, + padding: u20, }), - /// clear register - CLR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Start of frame flag clear - SOFC: u1, - reserved3: u1, - /// Update display done clear - UDDC: u1, - padding: u28, + /// interrupt line 8 status register + ITLINE8: mmio.Mmio(packed struct(u32) { + /// UCPD1 + UCPD1: u1, + /// UCPD2 + UCPD2: u1, + /// USB + USB: u1, + padding: u29, }), - reserved20: [4]u8, - /// display memory - RAM_COM: u32, - }; - - /// display memory - pub const RAM_COM = extern struct { - /// display memory low word - LOW: u32, - /// display memory high word - HIGH: u32, - }; - }; - - pub const icache_v1_0crr = struct { - pub const WAYSEL = enum(u1) { - /// direct mapped cache (1-way cache) - DirectMapped = 0x0, - /// n-way set associative cache (reset value) - NWaySetAssociative = 0x1, - }; - - /// Instruction Cache Control Registers. - pub const ICACHE = extern struct { - /// ICACHE control register. - CR: mmio.Mmio(packed struct(u32) { - /// EN. - EN: u1, - /// Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. - CACHEINV: u1, - /// This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). - WAYSEL: packed union { - raw: u1, - value: WAYSEL, - }, - reserved16: u13, - /// Hit monitor enable. - HITMEN: u1, - /// Miss monitor enable. - MISSMEN: u1, - /// Hit monitor reset. - HITMRST: u1, - /// Miss monitor reset. - MISSMRST: u1, - padding: u12, + /// interrupt line 9 status register + ITLINE9: mmio.Mmio(packed struct(u32) { + /// DMA1_CH1 + DMA1_CH1: u1, + padding: u31, }), - /// ICACHE status register. - SR: mmio.Mmio(packed struct(u32) { - /// cache busy executing a full invalidate CACHEINV operation. - BUSYF: u1, - /// full invalidate CACHEINV operation finished. - BSYENDF: u1, - /// an error occurred during the operation. - ERRF: u1, + /// interrupt line 10 status register + ITLINE10: mmio.Mmio(packed struct(u32) { + /// DMA1_CH1 + DMA1_CH2: u1, + /// DMA1_CH3 + DMA1_CH3: u1, + padding: u30, + }), + /// interrupt line 11 status register + ITLINE11: mmio.Mmio(packed struct(u32) { + /// DMAMUX + DMAMUX: u1, + /// DMA1_CH4 + DMA1_CH4: u1, + /// DMA1_CH5 + DMA1_CH5: u1, + /// DMA1_CH6 + DMA1_CH6: u1, + /// DMA1_CH7 + DMA1_CH7: u1, + padding: u27, + }), + /// interrupt line 12 status register + ITLINE12: mmio.Mmio(packed struct(u32) { + /// ADC + ADC: u1, + /// COMP1 + COMP1: u1, + /// COMP2 + COMP2: u1, padding: u29, }), - /// ICACHE interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Interrupt enable on busy end. - BSYENDIE: u1, - /// Error interrupt on cache error. - ERRIE: u1, - padding: u29, + /// interrupt line 13 status register + ITLINE13: mmio.Mmio(packed struct(u32) { + /// TIM1_CCU + TIM1_CCU: u1, + /// TIM1_TRG + TIM1_TRG: u1, + /// TIM1_UPD + TIM1_UPD: u1, + /// TIM1_BRK + TIM1_BRK: u1, + padding: u28, }), - /// ICACHE flag clear register. - FCR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Clear busy end flag. - CBSYENDF: u1, - /// Clear ERRF flag in SR. - CERRF: u1, - padding: u29, + /// interrupt line 14 status register + ITLINE14: mmio.Mmio(packed struct(u32) { + /// TIM1_CC + TIM1_CC: u1, + padding: u31, }), - /// ICACHE hit monitor register. - HMONR: u32, - /// ICACHE miss monitor register. - MMONR: mmio.Mmio(packed struct(u32) { - /// Miss monitor register. - MISSMON: u16, - padding: u16, + /// interrupt line 15 status register + ITLINE15: mmio.Mmio(packed struct(u32) { + /// TIM2 + TIM2: u1, + padding: u31, }), - }; - }; - - pub const pwr_h50 = struct { - pub const ALS = enum(u2) { - /// AVD level0 (VAVD0 ~ 1.7 V) - Level0 = 0x0, - /// AVD level1 (VAVD1 ~ 2.1 V) - Level1 = 0x1, - /// AVD level2 (VAVD2 ~ 2.5 V) - Level2 = 0x2, - /// AVD level3 (VAVD3 ~ 2.8 V) - Level3 = 0x3, - }; - - pub const LPMS = enum(u1) { - /// Keeps Stop mode when entering DeepSleep. - Stop = 0x0, - /// Allows Standby mode when entering DeepSleep. - Standby = 0x1, - }; - - pub const PLS = enum(u3) { - /// PVD level0 (VPVD0 ~ 1.95 V) - Level0 = 0x0, - /// PVD level1 (VPVD1 ~ 2.10 V) - Level1 = 0x1, - /// PVD level2 (VPVD2 ~ 2.25 V) - Level2 = 0x2, - /// PVD level3 (VPVD3 ~ 2.40 V) - Level3 = 0x3, - /// PVD level4 (VPVD4 ~ 2.55 V) - Level4 = 0x4, - /// PVD level5 (VPVD5 ~ 2.70 V) - Level5 = 0x5, - /// PVD level6 (VPVD6 ~ 2.85 V) - Level6 = 0x6, - /// PVD_IN pin - PVDInPin = 0x7, - }; - - pub const PowerModeInStopMode = enum(u1) { - /// Remains in normal mode when the system enters Stop mode (quick restart time). - Normal = 0x0, - /// Enters low-power mode when the system enters Stop mode (low-power consumption). - LowPower = 0x1, - }; - - pub const Retention = enum(u1) { - /// Content is lost. - Lost = 0x0, - /// Content is preserved. - Preserved = 0x1, - }; - - pub const SVOS = enum(u2) { - /// SVOS5 scale 5 - Scale5 = 0x1, - /// SVOS4 scale 4 - Scale4 = 0x2, - /// SVOS3 scale 3 (default) - Scale3 = 0x3, - _, - }; - - pub const ShutOff = enum(u1) { - /// Content is kept. - Kept = 0x0, - /// Content is lost. - Lost = 0x1, - }; - - pub const VBRS = enum(u1) { - /// Charge VBAT through a 5 kΩ resistor. - R5kOhm = 0x0, - /// Charge VBAT through a 1.5 kΩ resistor. - R1_5kOhm = 0x1, - }; - - pub const VOS = enum(u2) { - Scale3 = 0x0, - Scale2 = 0x1, - Scale1 = 0x2, - Scale0 = 0x3, - }; - - pub const WUPP = enum(u1) { - /// detection on high level (rising edge) - High = 0x0, - /// detection on low level (falling edge) - Low = 0x1, - }; - - pub const WUPPUPD = enum(u2) { - NoPullUp = 0x0, - PullUp = 0x1, - PullDown = 0x2, - _, - }; - - /// Power control. - pub const PWR = extern struct { - /// PWR power mode control register. - PMCR: mmio.Mmio(packed struct(u32) { - /// low-power mode selection This bit defines the Deepsleep mode. - LPMS: packed union { - raw: u1, - value: LPMS, - }, - reserved2: u1, - /// system Stop mode voltage scaling selection These bits control the V_CORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. - SVOS: packed union { - raw: u2, - value: SVOS, - }, - reserved7: u3, - /// clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware. - CSSF: u1, - reserved9: u1, - /// Flash memory low-power mode in Stop mode This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode. Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode. - FLPS: packed union { - raw: u1, - value: PowerModeInStopMode, - }, - reserved12: u2, - /// analog switch V_BOOST control This bit enables the booster to guarantee the analog switch AC performance when the V_DD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V_DD supply voltage can be monitored through the PVD and the PLS bits. - BOOSTE: u1, - /// analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected V_DDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored. (ALS bits). - AVD_READY: u1, - reserved25: u11, - /// AHB SRAM2 shut-off in Stop mode. - SRAM2SO: packed union { - raw: u1, - value: ShutOff, - }, - /// AHB SRAM1 shut-off in Stop mode. - SRAM1SO: packed union { - raw: u1, - value: ShutOff, - }, - padding: u5, + /// interrupt line 16 status register + ITLINE16: mmio.Mmio(packed struct(u32) { + /// TIM3 + TIM3: u1, + padding: u31, }), - /// PWR status register. - PMSR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// Stop flag This bit is set by hardware and cleared only by any reset or by setting the CSSF bit. - STOPF: u1, - /// System standby flag This bit is set by hardware and cleared only by a POR or by setting the CSSF bit. - SBF: u1, - padding: u25, + /// interrupt line 17 status register + ITLINE17: mmio.Mmio(packed struct(u32) { + /// TIM6 + TIM6: u1, + /// DAC + DAC: u1, + /// LPTIM1 + LPTIM1: u1, + padding: u29, }), - reserved16: [8]u8, - /// PWR voltage scaling control register. - VOSCR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// voltage scaling selection according to performance These bits control the V_CORE voltage level and allow to obtain the best trade-off between power consumption and performance: - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance. - When increasing the performance, the voltage scaling must be changed before increasing the system frequency. - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling. - VOS: packed union { - raw: u2, - value: VOS, - }, - padding: u26, + /// interrupt line 18 status register + ITLINE18: mmio.Mmio(packed struct(u32) { + /// TIM7 + TIM7: u1, + /// LPTIM2 + LPTIM2: u1, + padding: u30, }), - /// PWR voltage scaling status register. - VOSSR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// Ready bit for V_CORE voltage scaling output selection. - VOSRDY: u1, - reserved13: u9, - /// Voltage level ready for currently used VOS. - ACTVOSRDY: u1, - /// voltage output scaling currently applied to V_CORE This field provides the last VOS value. - ACTVOS: packed union { - raw: u2, - value: VOS, - }, - padding: u16, + /// interrupt line 19 status register + ITLINE19: mmio.Mmio(packed struct(u32) { + /// TIM14 + TIM14: u1, + padding: u31, }), - reserved32: [8]u8, - /// PWR Backup domain control register. - BDCR: mmio.Mmio(packed struct(u32) { - /// Backup RAM retention in Standby and V_BAT modes When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and V_BAT modes) is enabled. If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in. Run and Stop modes. However its content is lost in Standby and V_BAT modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and V_BAT modes. - BREN: packed union { - raw: u1, - value: Retention, - }, - /// Backup domain voltage and temperature monitoring enable. - MONEN: u1, - reserved8: u6, - /// V_BAT charging enable Note: Reset only by POR,. - VBE: u1, - /// V_BAT charging resistor selection. - VBRS: packed union { - raw: u1, - value: VBRS, - }, - padding: u22, + /// interrupt line 20 status register + ITLINE20: mmio.Mmio(packed struct(u32) { + /// TIM15 + TIM15: u1, + padding: u31, }), - /// PWR Backup domain control register. - DBPCR: mmio.Mmio(packed struct(u32) { - /// Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write. access. This bit must be set to enable write access to these registers. - DBP: u1, + /// interrupt line 21 status register + ITLINE21: mmio.Mmio(packed struct(u32) { + /// TIM16 + TIM16: u1, padding: u31, }), - /// PWR Backup domain status register. - BDSR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready. - BRRDY: u1, - reserved20: u3, - /// V_BAT level monitoring versus low threshold. - VBATL: u1, - /// V_BAT level monitoring versus high threshold. - VBATH: u1, - /// temperature level monitoring versus low threshold. - TEMPL: u1, - /// temperature level monitoring versus high threshold. - TEMPH: u1, - padding: u8, + /// interrupt line 22 status register + ITLINE22: mmio.Mmio(packed struct(u32) { + /// TIM17 + TIM17: u1, + padding: u31, }), - reserved48: [4]u8, - /// PWR supply configuration control register. - SCCR: mmio.Mmio(packed struct(u32) { - /// power management unit bypass. - BYPASS: u1, - reserved8: u7, - /// LDO enable The value is set by hardware when the package uses the LDO regulator. - LDOEN: u1, - padding: u23, + /// interrupt line 23 status register + ITLINE23: mmio.Mmio(packed struct(u32) { + /// I2C1 + I2C1: u1, + padding: u31, }), - /// PWR voltage monitor control register. - VMCR: mmio.Mmio(packed struct(u32) { - /// PVD enable. - PVDE: u1, - /// programmable voltage detector (PVD) level selection These bits select the voltage threshold detected by the PVD. - PLS: packed union { - raw: u3, - value: PLS, - }, - reserved8: u4, - /// peripheral voltage monitor on V_DDA enable. - AVDEN: u1, - /// analog voltage detector (AVD) level selection These bits select the voltage threshold detected by the AVD. - ALS: packed union { - raw: u2, - value: ALS, - }, - padding: u21, + /// interrupt line 24 status register + ITLINE24: mmio.Mmio(packed struct(u32) { + /// I2C2 + I2C2: u1, + padding: u31, }), - reserved60: [4]u8, - /// PWR voltage monitor status register. - VMSR: mmio.Mmio(packed struct(u32) { - reserved19: u19, - /// analog voltage detector output on V_DDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set. - AVDO: u1, - /// voltage detector output on V_DDIO2 This bit is set and cleared by hardware. - VDDIO2RDY: u1, - reserved22: u1, - /// programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. - PVDO: u1, - padding: u9, + /// interrupt line 25 status register + ITLINE25: mmio.Mmio(packed struct(u32) { + /// SPI1 + SPI1: u1, + padding: u31, }), - /// PWR wakeup status clear register. - WUSCR: mmio.Mmio(packed struct(u32) { - /// clear wakeup pin flag for WUFx These bits are always read as 0. - CWUF: u1, + /// interrupt line 26 status register + ITLINE26: mmio.Mmio(packed struct(u32) { + /// SPI2 + SPI2: u1, padding: u31, }), - /// PWR wakeup status register. - WUSR: mmio.Mmio(packed struct(u32) { - /// wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. - WUF: u1, + /// interrupt line 27 status register + ITLINE27: mmio.Mmio(packed struct(u32) { + /// USART1 + USART1: u1, padding: u31, }), - /// PWR wakeup configuration register. - WUCR: mmio.Mmio(packed struct(u32) { - /// enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. - WUPEN: u1, - reserved8: u7, - /// wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. - WUPP: packed union { - raw: u1, - value: WUPP, - }, - reserved16: u7, - /// wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. - WUPPUPD: packed union { - raw: u2, - value: WUPPUPD, - }, - padding: u14, + /// interrupt line 28 status register + ITLINE28: mmio.Mmio(packed struct(u32) { + /// USART2 + USART2: u1, + padding: u31, }), - reserved80: [4]u8, - /// PWR I/O retention register. - IORETR: mmio.Mmio(packed struct(u32) { - /// IO retention enable: When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register. - IORETEN: u1, - reserved16: u15, - /// IO retention enable for JTAG IOs when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. - JTAGIORETEN: u1, - padding: u15, + /// interrupt line 29 status register + ITLINE29: mmio.Mmio(packed struct(u32) { + USART3: u1, + USART4: u1, + reserved3: u1, + USART5: u1, + USART6: u1, + padding: u27, }), - reserved260: [176]u8, - /// PWR privilege configuration register. - PRIVCFGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// PWR non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure. - NSPRIV: u1, + /// interrupt line 30 status register + ITLINE30: mmio.Mmio(packed struct(u32) { + /// CEC + CEC: u1, + padding: u31, + }), + /// interrupt line 31 status register + ITLINE31: mmio.Mmio(packed struct(u32) { + /// RNG + RNG: u1, + /// AES + AES: u1, padding: u30, }), }; }; - pub const rcc_f410 = struct { - pub const FMPI2CSEL = enum(u2) { - /// APB clock selected as I2C clock - PCLK1 = 0x0, - /// System clock selected as I2C clock - SYS = 0x1, - /// HSI clock selected as I2C clock - HSI = 0x2, - _, - }; - - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, - _, - }; - - pub const ISSRC = enum(u2) { - /// I2Sx clock frequency = f(PLLCLK_R) - PLLCLKR = 0x0, - /// I2Sx clock frequency = I2S_CKIN Alternate function input frequency - I2S_CKIN = 0x1, - /// I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) - HSI_HSE = 0x3, - _, - }; - - pub const LPTIMSEL = enum(u2) { - /// APB1 clock (PCLK1) selected as LPTILM1 clock - PCLK1 = 0x0, - /// LSI clock is selected as LPTILM1 clock - LSI = 0x1, - /// HSI clock is selected as LPTILM1 clock - HSI = 0x2, - /// LSE clock is selected as LPTILM1 clock - LSE = 0x3, - }; - - pub const MCO1SEL = enum(u2) { - /// HSI clock selected - HSI = 0x0, - /// LSE oscillator selected - LSE = 0x1, - /// HSE oscillator clock selected - HSE = 0x2, - /// PLL clock selected - PLL = 0x3, - }; - - pub const MCO2SEL = enum(u2) { - /// System clock (SYSCLK) selected - SYS = 0x0, - /// PLLI2S clock selected - PLLI2S = 0x1, - /// HSE oscillator clock selected - HSE = 0x2, - /// PLL clock selected - PLL = 0x3, - }; - - pub const MCOPRE = enum(u3) { - /// No division - Div1 = 0x0, - /// Division by 2 - Div2 = 0x4, - /// Division by 3 - Div3 = 0x5, - /// Division by 4 - Div4 = 0x6, - /// Division by 5 - Div5 = 0x7, - _, - }; - - pub const PLLM = enum(u6) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, - Div16 = 0x10, - Div17 = 0x11, - Div18 = 0x12, - Div19 = 0x13, - Div20 = 0x14, - Div21 = 0x15, - Div22 = 0x16, - Div23 = 0x17, - Div24 = 0x18, - Div25 = 0x19, - Div26 = 0x1a, - Div27 = 0x1b, - Div28 = 0x1c, - Div29 = 0x1d, - Div30 = 0x1e, - Div31 = 0x1f, - Div32 = 0x20, - Div33 = 0x21, - Div34 = 0x22, - Div35 = 0x23, - Div36 = 0x24, - Div37 = 0x25, - Div38 = 0x26, - Div39 = 0x27, - Div40 = 0x28, - Div41 = 0x29, - Div42 = 0x2a, - Div43 = 0x2b, - Div44 = 0x2c, - Div45 = 0x2d, - Div46 = 0x2e, - Div47 = 0x2f, - Div48 = 0x30, - Div49 = 0x31, - Div50 = 0x32, - Div51 = 0x33, - Div52 = 0x34, - Div53 = 0x35, - Div54 = 0x36, - Div55 = 0x37, - Div56 = 0x38, - Div57 = 0x39, - Div58 = 0x3a, - Div59 = 0x3b, - Div60 = 0x3c, - Div61 = 0x3d, - Div62 = 0x3e, - Div63 = 0x3f, - _, - }; - - pub const PLLN = enum(u9) { - Mul50 = 0x32, - Mul51 = 0x33, - Mul52 = 0x34, - Mul53 = 0x35, - Mul54 = 0x36, - Mul55 = 0x37, - Mul56 = 0x38, - Mul57 = 0x39, - Mul58 = 0x3a, - Mul59 = 0x3b, - Mul60 = 0x3c, - Mul61 = 0x3d, - Mul62 = 0x3e, - Mul63 = 0x3f, - Mul64 = 0x40, - Mul65 = 0x41, - Mul66 = 0x42, - Mul67 = 0x43, - Mul68 = 0x44, - Mul69 = 0x45, - Mul70 = 0x46, - Mul71 = 0x47, - Mul72 = 0x48, - Mul73 = 0x49, - Mul74 = 0x4a, - Mul75 = 0x4b, - Mul76 = 0x4c, - Mul77 = 0x4d, - Mul78 = 0x4e, - Mul79 = 0x4f, - Mul80 = 0x50, - Mul81 = 0x51, - Mul82 = 0x52, - Mul83 = 0x53, - Mul84 = 0x54, - Mul85 = 0x55, - Mul86 = 0x56, - Mul87 = 0x57, - Mul88 = 0x58, - Mul89 = 0x59, - Mul90 = 0x5a, - Mul91 = 0x5b, - Mul92 = 0x5c, - Mul93 = 0x5d, - Mul94 = 0x5e, - Mul95 = 0x5f, - Mul96 = 0x60, - Mul97 = 0x61, - Mul98 = 0x62, - Mul99 = 0x63, - Mul100 = 0x64, - Mul101 = 0x65, - Mul102 = 0x66, - Mul103 = 0x67, - Mul104 = 0x68, - Mul105 = 0x69, - Mul106 = 0x6a, - Mul107 = 0x6b, - Mul108 = 0x6c, - Mul109 = 0x6d, - Mul110 = 0x6e, - Mul111 = 0x6f, - Mul112 = 0x70, - Mul113 = 0x71, - Mul114 = 0x72, - Mul115 = 0x73, - Mul116 = 0x74, - Mul117 = 0x75, - Mul118 = 0x76, - Mul119 = 0x77, - Mul120 = 0x78, - Mul121 = 0x79, - Mul122 = 0x7a, - Mul123 = 0x7b, - Mul124 = 0x7c, - Mul125 = 0x7d, - Mul126 = 0x7e, - Mul127 = 0x7f, - Mul128 = 0x80, - Mul129 = 0x81, - Mul130 = 0x82, - Mul131 = 0x83, - Mul132 = 0x84, - Mul133 = 0x85, - Mul134 = 0x86, - Mul135 = 0x87, - Mul136 = 0x88, - Mul137 = 0x89, - Mul138 = 0x8a, - Mul139 = 0x8b, - Mul140 = 0x8c, - Mul141 = 0x8d, - Mul142 = 0x8e, - Mul143 = 0x8f, - Mul144 = 0x90, - Mul145 = 0x91, - Mul146 = 0x92, - Mul147 = 0x93, - Mul148 = 0x94, - Mul149 = 0x95, - Mul150 = 0x96, - Mul151 = 0x97, - Mul152 = 0x98, - Mul153 = 0x99, - Mul154 = 0x9a, - Mul155 = 0x9b, - Mul156 = 0x9c, - Mul157 = 0x9d, - Mul158 = 0x9e, - Mul159 = 0x9f, - Mul160 = 0xa0, - Mul161 = 0xa1, - Mul162 = 0xa2, - Mul163 = 0xa3, - Mul164 = 0xa4, - Mul165 = 0xa5, - Mul166 = 0xa6, - Mul167 = 0xa7, - Mul168 = 0xa8, - Mul169 = 0xa9, - Mul170 = 0xaa, - Mul171 = 0xab, - Mul172 = 0xac, - Mul173 = 0xad, - Mul174 = 0xae, - Mul175 = 0xaf, - Mul176 = 0xb0, - Mul177 = 0xb1, - Mul178 = 0xb2, - Mul179 = 0xb3, - Mul180 = 0xb4, - Mul181 = 0xb5, - Mul182 = 0xb6, - Mul183 = 0xb7, - Mul184 = 0xb8, - Mul185 = 0xb9, - Mul186 = 0xba, - Mul187 = 0xbb, - Mul188 = 0xbc, - Mul189 = 0xbd, - Mul190 = 0xbe, - Mul191 = 0xbf, - Mul192 = 0xc0, - Mul193 = 0xc1, - Mul194 = 0xc2, - Mul195 = 0xc3, - Mul196 = 0xc4, - Mul197 = 0xc5, - Mul198 = 0xc6, - Mul199 = 0xc7, - Mul200 = 0xc8, - Mul201 = 0xc9, - Mul202 = 0xca, - Mul203 = 0xcb, - Mul204 = 0xcc, - Mul205 = 0xcd, - Mul206 = 0xce, - Mul207 = 0xcf, - Mul208 = 0xd0, - Mul209 = 0xd1, - Mul210 = 0xd2, - Mul211 = 0xd3, - Mul212 = 0xd4, - Mul213 = 0xd5, - Mul214 = 0xd6, - Mul215 = 0xd7, - Mul216 = 0xd8, - Mul217 = 0xd9, - Mul218 = 0xda, - Mul219 = 0xdb, - Mul220 = 0xdc, - Mul221 = 0xdd, - Mul222 = 0xde, - Mul223 = 0xdf, - Mul224 = 0xe0, - Mul225 = 0xe1, - Mul226 = 0xe2, - Mul227 = 0xe3, - Mul228 = 0xe4, - Mul229 = 0xe5, - Mul230 = 0xe6, - Mul231 = 0xe7, - Mul232 = 0xe8, - Mul233 = 0xe9, - Mul234 = 0xea, - Mul235 = 0xeb, - Mul236 = 0xec, - Mul237 = 0xed, - Mul238 = 0xee, - Mul239 = 0xef, - Mul240 = 0xf0, - Mul241 = 0xf1, - Mul242 = 0xf2, - Mul243 = 0xf3, - Mul244 = 0xf4, - Mul245 = 0xf5, - Mul246 = 0xf6, - Mul247 = 0xf7, - Mul248 = 0xf8, - Mul249 = 0xf9, - Mul250 = 0xfa, - Mul251 = 0xfb, - Mul252 = 0xfc, - Mul253 = 0xfd, - Mul254 = 0xfe, - Mul255 = 0xff, - Mul256 = 0x100, - Mul257 = 0x101, - Mul258 = 0x102, - Mul259 = 0x103, - Mul260 = 0x104, - Mul261 = 0x105, - Mul262 = 0x106, - Mul263 = 0x107, - Mul264 = 0x108, - Mul265 = 0x109, - Mul266 = 0x10a, - Mul267 = 0x10b, - Mul268 = 0x10c, - Mul269 = 0x10d, - Mul270 = 0x10e, - Mul271 = 0x10f, - Mul272 = 0x110, - Mul273 = 0x111, - Mul274 = 0x112, - Mul275 = 0x113, - Mul276 = 0x114, - Mul277 = 0x115, - Mul278 = 0x116, - Mul279 = 0x117, - Mul280 = 0x118, - Mul281 = 0x119, - Mul282 = 0x11a, - Mul283 = 0x11b, - Mul284 = 0x11c, - Mul285 = 0x11d, - Mul286 = 0x11e, - Mul287 = 0x11f, - Mul288 = 0x120, - Mul289 = 0x121, - Mul290 = 0x122, - Mul291 = 0x123, - Mul292 = 0x124, - Mul293 = 0x125, - Mul294 = 0x126, - Mul295 = 0x127, - Mul296 = 0x128, - Mul297 = 0x129, - Mul298 = 0x12a, - Mul299 = 0x12b, - Mul300 = 0x12c, - Mul301 = 0x12d, - Mul302 = 0x12e, - Mul303 = 0x12f, - Mul304 = 0x130, - Mul305 = 0x131, - Mul306 = 0x132, - Mul307 = 0x133, - Mul308 = 0x134, - Mul309 = 0x135, - Mul310 = 0x136, - Mul311 = 0x137, - Mul312 = 0x138, - Mul313 = 0x139, - Mul314 = 0x13a, - Mul315 = 0x13b, - Mul316 = 0x13c, - Mul317 = 0x13d, - Mul318 = 0x13e, - Mul319 = 0x13f, - Mul320 = 0x140, - Mul321 = 0x141, - Mul322 = 0x142, - Mul323 = 0x143, - Mul324 = 0x144, - Mul325 = 0x145, - Mul326 = 0x146, - Mul327 = 0x147, - Mul328 = 0x148, - Mul329 = 0x149, - Mul330 = 0x14a, - Mul331 = 0x14b, - Mul332 = 0x14c, - Mul333 = 0x14d, - Mul334 = 0x14e, - Mul335 = 0x14f, - Mul336 = 0x150, - Mul337 = 0x151, - Mul338 = 0x152, - Mul339 = 0x153, - Mul340 = 0x154, - Mul341 = 0x155, - Mul342 = 0x156, - Mul343 = 0x157, - Mul344 = 0x158, - Mul345 = 0x159, - Mul346 = 0x15a, - Mul347 = 0x15b, - Mul348 = 0x15c, - Mul349 = 0x15d, - Mul350 = 0x15e, - Mul351 = 0x15f, - Mul352 = 0x160, - Mul353 = 0x161, - Mul354 = 0x162, - Mul355 = 0x163, - Mul356 = 0x164, - Mul357 = 0x165, - Mul358 = 0x166, - Mul359 = 0x167, - Mul360 = 0x168, - Mul361 = 0x169, - Mul362 = 0x16a, - Mul363 = 0x16b, - Mul364 = 0x16c, - Mul365 = 0x16d, - Mul366 = 0x16e, - Mul367 = 0x16f, - Mul368 = 0x170, - Mul369 = 0x171, - Mul370 = 0x172, - Mul371 = 0x173, - Mul372 = 0x174, - Mul373 = 0x175, - Mul374 = 0x176, - Mul375 = 0x177, - Mul376 = 0x178, - Mul377 = 0x179, - Mul378 = 0x17a, - Mul379 = 0x17b, - Mul380 = 0x17c, - Mul381 = 0x17d, - Mul382 = 0x17e, - Mul383 = 0x17f, - Mul384 = 0x180, - Mul385 = 0x181, - Mul386 = 0x182, - Mul387 = 0x183, - Mul388 = 0x184, - Mul389 = 0x185, - Mul390 = 0x186, - Mul391 = 0x187, - Mul392 = 0x188, - Mul393 = 0x189, - Mul394 = 0x18a, - Mul395 = 0x18b, - Mul396 = 0x18c, - Mul397 = 0x18d, - Mul398 = 0x18e, - Mul399 = 0x18f, - Mul400 = 0x190, - Mul401 = 0x191, - Mul402 = 0x192, - Mul403 = 0x193, - Mul404 = 0x194, - Mul405 = 0x195, - Mul406 = 0x196, - Mul407 = 0x197, - Mul408 = 0x198, - Mul409 = 0x199, - Mul410 = 0x19a, - Mul411 = 0x19b, - Mul412 = 0x19c, - Mul413 = 0x19d, - Mul414 = 0x19e, - Mul415 = 0x19f, - Mul416 = 0x1a0, - Mul417 = 0x1a1, - Mul418 = 0x1a2, - Mul419 = 0x1a3, - Mul420 = 0x1a4, - Mul421 = 0x1a5, - Mul422 = 0x1a6, - Mul423 = 0x1a7, - Mul424 = 0x1a8, - Mul425 = 0x1a9, - Mul426 = 0x1aa, - Mul427 = 0x1ab, - Mul428 = 0x1ac, - Mul429 = 0x1ad, - Mul430 = 0x1ae, - Mul431 = 0x1af, - Mul432 = 0x1b0, - _, + pub const syscfg_g4 = struct { + /// System configuration controller + pub const SYSCFG = extern struct { + /// Remap Memory register + MEMRMP: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection + MEM_MODE: u3, + reserved8: u5, + /// User Flash Bank mode + FB_mode: u1, + padding: u23, + }), + /// peripheral mode configuration register + CFGR1: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// BOOSTEN + BOOSTEN: u1, + /// GPIO analog switch control voltage selection + ANASWVDD: u1, + reserved16: u6, + /// FM+ drive capability on PB6 + I2C_PB6_FMP: u1, + /// FM+ drive capability on PB6 + I2C_PB7_FMP: u1, + /// FM+ drive capability on PB6 + I2C_PB8_FMP: u1, + /// FM+ drive capability on PB6 + I2C_PB9_FMP: u1, + /// I2C1 FM+ drive capability enable + I2C1_FMP: u1, + /// I2C1 FM+ drive capability enable + I2C2_FMP: u1, + /// I2C1 FM+ drive capability enable + I2C3_FMP: u1, + /// I2C1 FM+ drive capability enable + I2C4_FMP: u1, + reserved26: u2, + /// FPU Interrupts Enable + FPU_IE: u6, + }), + /// external interrupt configuration register 1 + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI x configuration + EXTI: u4, + padding: u28, + }), + /// CCM SRAM control and status register + SCSR: mmio.Mmio(packed struct(u32) { + /// CCM SRAM Erase + CCMER: u1, + /// CCM SRAM busy by erase operation + CCMBSY: u1, + padding: u30, + }), + /// configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Core Lockup Lock + CLL: u1, + /// SRAM Parity Lock + SPL: u1, + /// PVD Lock + PVDL: u1, + /// ECC Lock + ECCL: u1, + reserved8: u4, + /// SRAM Parity Flag + SPF: u1, + padding: u23, + }), + /// SRAM Write protection register 1 + SWPR: mmio.Mmio(packed struct(u32) { + /// Write protection + Page_WP: u1, + padding: u31, + }), + /// SRAM2 Key Register + SKR: mmio.Mmio(packed struct(u32) { + /// SRAM2 Key for software erase + KEY: u8, + padding: u24, + }), }; + }; - pub const PLLP = enum(u2) { - /// PLLP=2 - Div2 = 0x0, - /// PLLP=4 - Div4 = 0x1, - /// PLLP=6 - Div6 = 0x2, - /// PLLP=8 - Div8 = 0x3, + pub const syscfg_h5 = struct { + pub const CS = enum(u1) { + /// Code from the cell (available in the SBS_CCVR) + Cell = 0x0, + /// Code from SBS_CCCR + Software = 0x1, }; - pub const PLLQ = enum(u4) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, - Div8 = 0x8, - Div9 = 0x9, - Div10 = 0xa, - Div11 = 0xb, - Div12 = 0xc, - Div13 = 0xd, - Div14 = 0xe, - Div15 = 0xf, + pub const DBGCFG_LOCK = enum(u8) { + /// Writes to SBS_DBGCR allowed (default) + B_0xB4 = 0xb4, _, }; - pub const PLLR = enum(u3) { - Div2 = 0x2, - Div3 = 0x3, - Div4 = 0x4, - Div5 = 0x5, - Div6 = 0x6, - Div7 = 0x7, + pub const DBG_AUTH_HDPL = enum(u8) { + /// HDPL1 + B_0x51 = 0x51, + /// HDPL3 + B_0x6F = 0x6f, + /// HDPL2 + B_0x8A = 0x8a, _, }; - pub const PLLSRC = enum(u1) { - /// HSI clock selected as PLL and PLLI2S clock entry - HSI = 0x0, - /// HSE oscillator clock selected as PLL and PLLI2S clock entry - HSE = 0x1, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, + pub const EPOCH_SEL = enum(u2) { + /// SEC_EPOCH counter input selected + B_0x0 = 0x0, + /// NS_EPOCH (non-secure) input selected + B_0x1 = 0x1, _, }; - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, + pub const ETH_SEL_PHY = enum(u3) { + /// GMII or MII + MII_GMII = 0x0, + /// reserved (RGMII) + ReservedRGMII = 0x1, + /// RMII + RMII = 0x4, + _, }; - pub const SPREADSEL = enum(u1) { - /// Center spread - Center = 0x0, - /// Down spread - Down = 0x1, + pub const HDPL = enum(u8) { + /// HDPL1, iRoT + B_0x51 = 0x51, + /// HDPL3, application (secure/non-secure) + B_0x6F = 0x6f, + /// HDPL2, uRoT + B_0x8A = 0x8a, + /// HDPL0, RSS + B_0xB4 = 0xb4, + _, }; - pub const SW = enum(u2) { - /// HSI oscillator used as system clock - HSI = 0x0, - /// HSE oscillator used as system clock - HSE = 0x1, - /// PLL used as system clock - PLL1_P = 0x2, + pub const INCR_HDPL = enum(u8) { + /// recommended value to increment HDPL level by one + B_0x6A = 0x6a, + /// no increment + B_0xB4 = 0xb4, _, }; - pub const TIMPRE = enum(u1) { - /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx - Mul2 = 0x0, - /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx - Mul4 = 0x1, + pub const SEC = enum(u1) { + /// SBS_CFGR2 register accessible through secure or non-secure transaction + B_0x0 = 0x0, + /// SBS_CFGR2 register only accessible through secure transaction + B_0x1 = 0x1, }; - /// Reset and clock control - pub const RCC = extern struct { - /// clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal high-speed clock enable - HSION: u1, - /// Internal high-speed clock ready flag - HSIRDY: u1, - reserved3: u1, - /// Internal high-speed clock trimming - HSITRIM: u5, - /// Internal high-speed clock calibration - HSICAL: u8, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE clock bypass - HSEBYP: u1, - /// Clock security system enable - CSSON: u1, - reserved24: u4, - /// Main PLL (PLL) enable - PLLON: u1, - /// Main PLL (PLL) clock ready flag - PLLRDY: u1, - padding: u6, - }), - /// PLL configuration register - PLLCFGR: mmio.Mmio(packed struct(u32) { - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - PLLM: packed union { - raw: u6, - value: PLLM, - }, - /// Main PLL (PLL) multiplication factor for VCO - PLLN: packed union { - raw: u9, - value: PLLN, - }, - reserved16: u1, - /// Main PLL (PLL) division factor for main system clock - PLLP: packed union { - raw: u2, - value: PLLP, - }, - reserved22: u4, - /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - PLLSRC: packed union { - raw: u1, - value: PLLSRC, + /// SBS register block + pub const SYSCFG = extern struct { + reserved16: [16]u8, + /// SBS temporal isolation control register + HDPLCR: mmio.Mmio(packed struct(u32) { + /// increment HDPL value Other: all other values allow a HDPL level increment. + INCR_HDPL: packed union { + raw: u8, + value: INCR_HDPL, }, - reserved24: u1, - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - PLLQ: packed union { - raw: u4, - value: PLLQ, + padding: u24, + }), + /// SBS temporal isolation status register + HDPLSR: mmio.Mmio(packed struct(u32) { + /// temporal isolation level This bitfield returns the current temporal isolation level. + HDPL: packed union { + raw: u8, + value: HDPL, }, - /// PLL division factor for I2S and System clocks - PLLR: packed union { - raw: u3, - value: PLLR, + padding: u24, + }), + /// SBS next HDPL control register + NEXTHDPLCR: mmio.Mmio(packed struct(u32) { + /// index to point to a higher HDPL than the current one Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas (OBK-HDPL = HDPL + NEXTHDPL). See for more details. + NEXTHDPL: u2, + padding: u30, + }), + reserved32: [4]u8, + /// SBS debug control register + DBGCR: mmio.Mmio(packed struct(u32) { + /// access port unlock Write 0xB4 to this bitfield to open the device access port. + AP_UNLOCK: u8, + /// debug unlock when DBG_AUTH_HDPL is reached Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register. + DBG_UNLOCK: u8, + /// authenticated debug temporal isolation level Writing to this bitfield defines at which HDPL the authenticated debug opens. Note: Writing any other values is ignored. Reading any other value means the debug never opens. + DBG_AUTH_HDPL: packed union { + raw: u8, + value: DBG_AUTH_HDPL, }, - padding: u1, + /// control debug opening secure/non-secure Write 0xB4 to this bitfield to open debug for secure and non-secure. Writing any other values only open non-secure. + DBG_AUTH_SEC: u8, }), - /// clock configuration register - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock switch - SW: packed union { - raw: u2, - value: SW, + /// SBS debug lock register + DBGLOCKR: mmio.Mmio(packed struct(u32) { + /// debug configuration lock Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4. 0xC3 is the recommended value to lock the debug configuration using this bitfield. Other: Writes to SBS_DBGCR ignored + DBGCFG_LOCK: packed union { + raw: u8, + value: DBGCFG_LOCK, }, - /// System clock switch status - SWS: packed union { + padding: u24, + }), + reserved52: [12]u8, + /// SBS RSS command register + RSSCMDR: mmio.Mmio(packed struct(u32) { + /// RSS command The application can use this bitfield to pass on a command to the RSS, executed at the next reset. When RSSCMD ≠ 0 and PRODUCT_STATE is in Open, then the system always boots on RSS whatever is the boot pin value. + RSSCMD: u16, + padding: u16, + }), + reserved160: [104]u8, + /// SBS EPOCH selection control register + EPOCHSELCR: mmio.Mmio(packed struct(u32) { + /// select EPOCH value to be sent to the SAES 1x: EPOCH forced to zero (value used to retrieve PUF reference value at boot time) + EPOCH_SEL: packed union { raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// MCO output enable - MCO1EN: u1, - /// MCO output enable - MCO2EN: u1, - /// APB Low speed prescaler (APB1) - PPRE1: packed union { - raw: u3, - value: PPRE, + value: EPOCH_SEL, }, - /// APB high-speed prescaler (APB2) - PPRE2: packed union { - raw: u3, - value: PPRE, + padding: u30, + }), + reserved192: [28]u8, + /// SBS security mode configuration control register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// SBS clock control, memory-erase status register and compensation cell register security enable + SBSSEC: packed union { + raw: u1, + value: SEC, }, - /// HSE division factor for RTC clock - RTCPRE: u5, - /// Microcontroller clock output 1 - MCO1SEL: packed union { - raw: u2, - value: MCO1SEL, + /// ClassB security enable + CLASSBSEC: packed union { + raw: u1, + value: SEC, }, - reserved24: u1, - /// MCO1 prescaler - MCO1PRE: packed union { - raw: u3, - value: MCOPRE, + reserved3: u1, + /// FPU security enable Note: This bit can only be written through privilege transaction. + FPUSEC: packed union { + raw: u1, + value: SEC, }, - /// MCO2 prescaler - MCO2PRE: packed union { + reserved31: u27, + /// control accessibility of SMPS_DIV_CLOCK _EN in SBS_PMCR + SDCE_SEC_EN: u1, + }), + reserved256: [60]u8, + /// SBS product mode and configuration register + PMCR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// booster enable Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range. + BOOSTEN: u1, + /// booster VDD selection Note: Booster must not be used when VDDA < 2.7 V, but VDD > 2.7 V (add current consumption). When both VDD < 2.7 V and VDDA < 2.7 V, booster is needed to get full AC performances from I/O analog switches. + BOOSTVDDSEL: u1, + reserved16: u6, + /// Fast-mode Plus command on PB(6) + PB6_FMPLUS: u1, + /// Fast-mode Plus command on PB(7) + PB7_FMPLUS: u1, + /// Fast-mode Plus command on PB(8) + PB8_FMPLUS: u1, + /// Fast-mode Plus command on PB(9) + PB9_FMPLUS: u1, + reserved21: u1, + /// Ethernet PHY interface selection Other: reserved + ETH_SEL_PHY: packed union { raw: u3, - value: MCOPRE, - }, - /// Microcontroller clock output 2 - MCO2SEL: packed union { - raw: u2, - value: MCO2SEL, + value: ETH_SEL_PHY, }, - }), - /// clock interrupt register - CIR: mmio.Mmio(packed struct(u32) { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// Main PLL (PLL) ready interrupt flag - PLLRDYF: u1, - reserved7: u2, - /// Clock security system interrupt flag - CSSF: u1, - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// Main PLL (PLL) ready interrupt enable - PLLRDYIE: u1, - reserved16: u3, - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// Main PLL(PLL) ready interrupt clear - PLLRDYC: u1, - /// PLLI2S ready interrupt clear - PLLI2SRDYC: u1, - reserved23: u1, - /// Clock security system interrupt clear - CSSC: u1, padding: u8, }), - /// AHB1 peripheral reset register - AHB1RSTR: mmio.Mmio(packed struct(u32) { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - reserved7: u4, - /// IO port H reset - GPIOHRST: u1, - reserved12: u4, - /// CRC reset - CRCRST: u1, - reserved21: u8, - /// DMA2 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - reserved31: u8, - /// RNGRST - RNGRST: u1, - }), - reserved32: [12]u8, - /// APB1 peripheral reset register - APB1RSTR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// TIM5 reset - TIM5RST: u1, - /// TIM6 reset - TIM6RST: u1, - reserved9: u4, - /// LPTIM1 reset - LPTIM1RST: u1, - reserved11: u1, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI 2 reset - SPI2RST: u1, - reserved17: u2, - /// USART 2 reset - USART2RST: u1, - reserved21: u3, - /// I2C 1 reset - I2C1RST: u1, - /// I2C 2 reset - I2C2RST: u1, - reserved24: u1, - /// FMPI2C1 reset - FMPI2C1RST: u1, - reserved28: u3, - /// Power interface reset - PWRRST: u1, - /// DAC reset - DACRST: u1, - padding: u2, - }), - /// APB2 peripheral reset register - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// TIM1 reset - TIM1RST: u1, - reserved4: u3, - /// USART1 reset - USART1RST: u1, - /// USART6 reset - USART6RST: u1, - reserved8: u2, - /// ADC interface reset (common to all ADCs) - ADCRST: u1, - reserved12: u3, - /// SPI 1 reset - SPI1RST: u1, - reserved14: u1, - /// System configuration controller reset - SYSCFGRST: u1, - reserved16: u1, - /// TIM9 reset - TIM9RST: u1, - reserved18: u1, - /// TIM11 reset - TIM11RST: u1, - reserved20: u1, - /// SPI5 reset - SPI5RST: u1, - padding: u11, - }), - reserved48: [8]u8, - /// AHB1 peripheral clock register - AHB1ENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port C clock enable - GPIOCEN: u1, - reserved7: u4, - /// IO port H clock enable - GPIOHEN: u1, - reserved12: u4, - /// CRC clock enable - CRCEN: u1, - reserved21: u8, - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - reserved31: u8, - /// RNG clock enable - RNGEN: u1, - }), - reserved64: [12]u8, - /// APB1 peripheral clock enable register - APB1ENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// TIM5 clock enable - TIM5EN: u1, - /// TIM6 clock enable - TIM6EN: u1, - reserved9: u4, - /// LPTIM1 clock enable - LPTIM1EN: u1, - /// RTC APB clock enable - RTCAPBEN: u1, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI2 clock enable - SPI2EN: u1, - reserved17: u2, - /// USART 2 clock enable - USART2EN: u1, - reserved21: u3, - /// I2C1 clock enable - I2C1EN: u1, - /// I2C2 clock enable - I2C2EN: u1, - reserved24: u1, - /// FMPI2C1 clock enable - FMPI2C1EN: u1, - reserved28: u3, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - padding: u2, - }), - /// APB2 peripheral clock enable register - APB2ENR: mmio.Mmio(packed struct(u32) { - /// TIM1 clock enable - TIM1EN: u1, - reserved4: u3, - /// USART1 clock enable - USART1EN: u1, - /// USART6 clock enable - USART6EN: u1, - reserved8: u2, - /// ADC1 clock enable - ADC1EN: u1, - reserved12: u3, - /// SPI1 clock enable - SPI1EN: u1, - reserved14: u1, - /// System configuration controller clock enable - SYSCFGEN: u1, - /// EXTI ans external IT clock enable - EXTITEN: u1, - /// TIM9 clock enable - TIM9EN: u1, - reserved18: u1, - /// TIM11 clock enable - TIM11EN: u1, - reserved20: u1, - /// SPI5 clock enable - SPI5EN: u1, - padding: u11, - }), - reserved80: [8]u8, - /// AHB1 peripheral clock enable in low power mode register - AHB1LPENR: mmio.Mmio(packed struct(u32) { - /// IO port A clock enable during sleep mode - GPIOALPEN: u1, - /// IO port B clock enable during Sleep mode - GPIOBLPEN: u1, - /// IO port C clock enable during Sleep mode - GPIOCLPEN: u1, - reserved7: u4, - /// IO port H clock enable during Sleep mode - GPIOHLPEN: u1, - reserved12: u4, - /// CRC clock enable during Sleep mode - CRCLPEN: u1, - reserved15: u2, - /// Flash interface clock enable during Sleep mode - FLASHLPEN: u1, - /// SRAM 1interface clock enable during Sleep mode - SRAM1LPEN: u1, - reserved21: u4, - /// DMA1 clock enable during Sleep mode - DMA1LPEN: u1, - /// DMA2 clock enable during Sleep mode - DMA2LPEN: u1, - reserved31: u8, - /// RNG clock enable during sleep mode - RNGLPEN: u1, - }), - reserved96: [12]u8, - /// APB1 peripheral clock enable in low power mode register - APB1LPENR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// TIM5 clock enable during Sleep mode - TIM5LPEN: u1, - /// TIM6 clock enable during Sleep mode - TIM6LPEN: u1, - reserved9: u4, - /// LPTIM1 clock enable during sleep mode - LPTIM1LPEN: u1, - /// RTC APB clock enable during sleep mode - RTCAPBLPEN: u1, - /// Window watchdog clock enable during Sleep mode - WWDGLPEN: u1, - reserved14: u2, - /// SPI2 clock enable during Sleep mode - SPI2LPEN: u1, - reserved17: u2, - /// USART2 clock enable during Sleep mode - USART2LPEN: u1, - reserved21: u3, - /// I2C1 clock enable during Sleep mode - I2C1LPEN: u1, - /// I2C2 clock enable during Sleep mode - I2C2LPEN: u1, - reserved24: u1, - /// FMPI2C1 clock enable during Sleep - FMPI2C1LPEN: u1, - reserved28: u3, - /// Power interface clock enable during Sleep mode - PWRLPEN: u1, - /// DAC interface clock enable during sleep mode - DACLPEN: u1, - padding: u2, - }), - /// APB2 peripheral clock enabled in low power mode register - APB2LPENR: mmio.Mmio(packed struct(u32) { - /// TIM1 clock enable during Sleep mode - TIM1LPEN: u1, - reserved4: u3, - /// USART1 clock enable during Sleep mode - USART1LPEN: u1, - /// USART6 clock enable during Sleep mode - USART6LPEN: u1, - reserved8: u2, - /// ADC1 clock enable during Sleep mode - ADC1LPEN: u1, - reserved11: u2, - /// SDIO clock enable during Sleep mode - SDIOLPEN: u1, - /// SPI 1 clock enable during Sleep mode - SPI1LPEN: u1, - reserved14: u1, - /// System configuration controller clock enable during Sleep mode - SYSCFGLPEN: u1, - /// EXTI and External IT clock enable during sleep mode - EXTITLPEN: u1, - /// TIM9 clock enable during sleep mode - TIM9LPEN: u1, - reserved18: u1, - /// TIM11 clock enable during Sleep mode - TIM11LPEN: u1, - reserved20: u1, - /// SPI5 clock enable during Sleep mode - SPI5LPEN: u1, - padding: u11, + /// SBS FPU interrupt mask register + FPUIMR: mmio.Mmio(packed struct(u32) { + /// FPU interrupt enable Set and cleared by software to enable the Cortex-M33 FPU interrupts FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset) FPU_IE[4]: input abnormal interrupt enable FPU_IE[3]: overflow interrupt enable FPU_IE[2]: underflow interrupt enable FPU_IE[1]: divide-by-zero interrupt enable FPU_IE[0]: invalid operation interrupt enable + FPU_IE: u6, + padding: u26, }), - reserved112: [8]u8, - /// Backup domain control register - BDCR: mmio.Mmio(packed struct(u32) { - /// External low-speed oscillator enable - LSEON: u1, - /// External low-speed oscillator ready - LSERDY: u1, - /// External low-speed oscillator bypass - LSEBYP: u1, - reserved8: u5, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, + /// SBS memory erase status register + MESR: mmio.Mmio(packed struct(u32) { + /// erase after reset status This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, DCACHE, ICACHE and PKA. It is set by hardware and reset by software + MCLR: u1, + reserved16: u15, + /// end-of-erase status for ICACHE and PKA RAM This bit shows the status of the protection for ICACHE and PKA. It is set by hardware and reset by software. + IPMEE: u1, padding: u15, }), - /// clock control & status register - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low-speed oscillator enable - LSION: u1, - /// Internal low-speed oscillator ready - LSIRDY: u1, - reserved24: u22, - /// Remove reset flag - RMVF: u1, - /// BOR reset flag - BORRSTF: u1, - /// PIN reset flag - PADRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - WDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, - }), - reserved128: [8]u8, - /// spread spectrum clock generation register - SSCGR: mmio.Mmio(packed struct(u32) { - /// Modulation period - MODPER: u13, - /// Incrementation step - INCSTEP: u15, - reserved30: u2, - /// Spread Select - SPREADSEL: packed union { - raw: u1, - value: SPREADSEL, - }, - /// Spread spectrum modulation enable - SSCGEN: u1, - }), - reserved140: [8]u8, - /// DCKCFGR register - DCKCFGR: mmio.Mmio(packed struct(u32) { - reserved24: u24, - /// TIMPRE - TIMPRE: packed union { + reserved272: [4]u8, + /// SBS compensation cell for I/Os control and status register + CCCSR: mmio.Mmio(packed struct(u32) { + /// enable compensation cell for VDDIO power rail This bit enables the I/O compensation cell. + EN: u1, + /// code selection for VDDIO power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. + CS: packed union { raw: u1, - value: TIMPRE, - }, - /// I2SSRC - I2SSRC: packed union { - raw: u2, - value: ISSRC, + value: CS, }, - padding: u5, + reserved8: u6, + /// VDDIO compensation cell ready flag This bit provides the status of the compensation cell. + RDY: u1, + padding: u23, }), - reserved148: [4]u8, - /// DCKCFGR2 register - DCKCFGR2: mmio.Mmio(packed struct(u32) { - reserved22: u22, - /// FMPI2C1 kernel clock source selection - FMPI2C1SEL: packed union { - raw: u2, - value: FMPI2CSEL, - }, - reserved30: u6, - /// LPTIM1SEL - LPTIM1SEL: packed union { - raw: u2, - value: LPTIMSEL, - }, + /// SBS compensation cell for I/Os value register + CCVALR: mmio.Mmio(packed struct(u32) { + /// compensation value for the NMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. + ANSRC1: u4, + /// compensation value for the PMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. + APSRC1: u4, + /// Compensation value for the NMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. + ANSRC2: u4, + /// compensation value for the PMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. + APSRC2: u4, + padding: u16, + }), + /// SBS compensation cell for I/Os software code register + CCSWCR: mmio.Mmio(packed struct(u32) { + /// NMOS compensation code for VDD power rails This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR. + SW_ANSRC1: u4, + /// PMOS compensation code for the VDD power rails This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR. + SW_APSRC1: u4, + /// NMOS compensation code for VDDIO power rails This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR. + SW_ANSRC2: u4, + /// PMOS compensation code for the VDDIO power rails This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR. + SW_APSRC2: u4, + padding: u16, + }), + reserved288: [4]u8, + /// SBS Class B register + CFGR2: mmio.Mmio(packed struct(u32) { + /// core lockup lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1/8/15/16/17 break inputs. + CLL: u1, + /// SRAM ECC error lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1/8/15/16/17. + SEL: u1, + /// PVD lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1/8/15/16/17 break inputs. + PVDL: u1, + /// ECC lock This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1/8/15/6/17. + ECCL: u1, + padding: u28, + }), + reserved324: [32]u8, + /// SBS CPU non-secure lock register + CNSLCKR: mmio.Mmio(packed struct(u32) { + /// VTOR_NS register lock This bit is set by software and cleared only by a system reset. + LOCKNSVTOR: u1, + /// non-secure MPU register lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers. + LOCKNSMPU: u1, + padding: u30, + }), + /// SBS CPU secure lock register + CSLCKR: mmio.Mmio(packed struct(u32) { + /// VTOR_S and AIRCR register lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register. + LOCKSVTAIRCR: u1, + /// secure MPU registers lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers. + LOCKSMPU: u1, + /// SAU registers lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers. + LOCKSAU: u1, + padding: u29, + }), + /// SBS flift ECC NMI mask register + ECCNMIR: mmio.Mmio(packed struct(u32) { + /// NMI behavior setup when a double ECC error occurs on flitf data part + ECCNMI_MASK_EN: u1, + padding: u31, }), }; - }; - - pub const eth_v1c = struct { - pub const APCS = enum(u1) { - /// MAC passes all incoming frames unmodified - Disabled = 0x0, - /// MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes - Strip = 0x1, - }; - - pub const BFD = enum(u1) { - /// Address filters pass all received broadcast frames - Enabled = 0x0, - /// Address filters filter all incoming broadcast frames - Disabled = 0x1, - }; - - pub const BL = enum(u2) { - /// For retransmission n, wait up to 2^min(n, 10) time slots - BL10 = 0x0, - /// For retransmission n, wait up to 2^min(n, 8) time slots - BL8 = 0x1, - /// For retransmission n, wait up to 2^min(n, 4) time slots - BL4 = 0x2, - /// For retransmission n, wait up to 2^min(n, 1) time slots - BL1 = 0x3, - }; - - pub const CR = enum(u3) { - /// 60-100MHz HCLK/42 - CR_60_100 = 0x0, - /// 100-150 MHz HCLK/62 - CR_100_150 = 0x1, - /// 20-35MHz HCLK/16 - CR_20_35 = 0x2, - /// 35-60MHz HCLK/16 - CR_35_60 = 0x3, - /// 150-168MHz HCLK/102 - CR_150_168 = 0x4, - _, - }; - - pub const CSD = enum(u1) { - /// Errors generated due to loss of carrier - Enabled = 0x0, - /// No error generated due to loss of carrier - Disabled = 0x1, - }; - - pub const CSR = enum(u1) { - /// Counters roll over to zero after reaching the maximum value - Rollover = 0x0, - /// Counters do not roll over to zero after reaching the maximum value - NotRollover = 0x1, - }; - - pub const CounterReset = enum(u1) { - /// Reset all counters. Cleared automatically - Reset = 0x1, - _, - }; - - pub const DA = enum(u1) { - /// Round-robin with Rx:Tx priority given by PM - RoundRobin = 0x0, - /// Rx has priority over Tx - RxPriority = 0x1, - }; - - pub const DAIF = enum(u1) { - /// Normal filtering of frames - Normal = 0x0, - /// Address check block operates in inverse filtering mode for the DA address comparison - Invert = 0x1, - }; - - pub const DM = enum(u1) { - /// MAC operates in half-duplex mode - HalfDuplex = 0x0, - /// MAC operates in full-duplex mode - FullDuplex = 0x1, - }; - - pub const DMAOMR_SR = enum(u1) { - /// Reception is stopped after transfer of the current frame - Stopped = 0x0, - /// Reception is placed in the Running state - Started = 0x1, - }; - - pub const DTCEFD = enum(u1) { - /// Drop frames with errors only in the receive checksum offload engine - Enabled = 0x0, - /// Do not drop frames that only have errors in the receive checksum offload engine - Disabled = 0x1, - }; - - pub const FB = enum(u1) { - /// AHB uses SINGLE and INCR burst transfers - Variable = 0x0, - /// AHB uses only fixed burst transfers - Fixed = 0x1, - }; - - pub const FCB = enum(u1) { - /// In half duplex only, deasserts back pressure - DisableBackPressure = 0x0, - /// In full duplex, initiate a Pause control frame. In half duplex, assert back pressure - PauseOrBackPressure = 0x1, - }; - - pub const FEF = enum(u1) { - /// Rx FIFO drops frames with error status - Drop = 0x0, - /// All frames except runt error frames are forwarded to the DMA - Forward = 0x1, - }; - - pub const FES = enum(u1) { - /// 10 Mbit/s - FES10 = 0x0, - /// 100 Mbit/s - FES100 = 0x1, - }; - - pub const FPM = enum(u1) { - /// PBL values used as-is - x1 = 0x0, - /// PBL values multiplied by 4 - x4 = 0x1, - }; - - pub const FTF = enum(u1) { - /// Transmit FIFO controller logic is reset to its default values. Cleared automatically - Flush = 0x1, - _, - }; - - pub const FUGF = enum(u1) { - /// Rx FIFO drops all frames of less than 64 bytes - Drop = 0x0, - /// Rx FIFO forwards undersized frames - Forward = 0x1, - }; - - pub const HM = enum(u1) { - /// MAC performs a perfect destination address filtering for multicast frames - Perfect = 0x0, - /// MAC performs destination address filtering of received multicast frames according to the hash table - Hash = 0x1, - }; - - pub const HPF = enum(u1) { - /// If HM or HU is set, only frames that match the Hash filter are passed - HashOnly = 0x0, - /// If HM or HU is set, frames that match either the perfect filter or the hash filter are passed - HashOrPerfect = 0x1, - }; - - pub const HU = enum(u1) { - /// MAC performs a perfect destination address filtering for unicast frames - Perfect = 0x0, - /// MAC performs destination address filtering of received unicast frames according to the hash table - Hash = 0x1, - }; - - pub const IFG = enum(u3) { - /// 96 bit times - IFG96 = 0x0, - /// 88 bit times - IFG88 = 0x1, - /// 80 bit times - IFG80 = 0x2, - /// 72 bit times - IFG72 = 0x3, - /// 64 bit times - IFG64 = 0x4, - /// 56 bit times - IFG56 = 0x5, - /// 48 bit times - IFG48 = 0x6, - /// 40 bit times - IFG40 = 0x7, - }; - - pub const IPCO = enum(u1) { - /// IPv4 checksum offload disabled - Disabled = 0x0, - /// IPv4 checksums are checked in received frames - Offload = 0x1, - }; - - pub const JD = enum(u1) { - /// Jabber enabled, transmit frames up to 2048 bytes - Enabled = 0x0, - /// Jabber disabled, transmit frames up to 16384 bytes - Disabled = 0x1, - }; - - pub const LM = enum(u1) { - /// Normal mode - Normal = 0x0, - /// MAC operates in loopback mode at the MII - Loopback = 0x1, - }; - - pub const MACAHR_SA = enum(u1) { - /// This address is used for comparison with DA fields of the received frame - Destination = 0x0, - /// This address is used for comparison with SA fields of received frames - Source = 0x1, - }; - - pub const MB = enum(u1) { - /// Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below - Normal = 0x0, - /// If FB is low, start all bursts greater than 16 with INCR (undefined burst) - Mixed = 0x1, - }; - - pub const MB_progress = enum(u1) { - /// This bit is set to 1 by the application to indicate that a read or write access is in progress - Busy = 0x1, - _, - }; + }; - pub const MCFHP = enum(u1) { - /// When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0 - AlmostHalf = 0x0, - /// When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0 - AlmostFull = 0x1, + pub const syscfg_h50 = struct { + pub const CS = enum(u1) { + /// Code from the cell (available in SBS_CCVR) + Cell = 0x0, + /// Code from SBS_CCCR + Software = 0x1, }; - pub const MCP = enum(u1) { - /// MMC counters will be preset to almost full or almost half. Cleared automatically - Preset = 0x1, + pub const DBGCFG_LOCK = enum(u8) { + /// Writes to SBS_DBGCR allowed (default) + B_0xB4 = 0xb4, _, }; - pub const MW = enum(u1) { - /// Read operation - Read = 0x0, - /// Write operation - Write = 0x1, - }; - - pub const PBL = enum(u6) { - /// Maximum of 1 beat per DMA transaction - PBL1 = 0x1, - /// Maximum of 2 beats per DMA transaction - PBL2 = 0x2, - /// Maximum of 4 beats per DMA transaction - PBL4 = 0x4, - /// Maximum of 8 beats per DMA transaction - PBL8 = 0x8, - /// Maximum of 16 beats per DMA transaction - PBL16 = 0x10, - /// Maximum of 32 beats per DMA transaction - PBL32 = 0x20, + pub const DBG_AUTH_HDPL = enum(u8) { + /// HDPL1 + B_0x51 = 0x51, + /// HDPL3 + B_0x6F = 0x6f, + /// HDPL2 + B_0x8A = 0x8a, _, }; - pub const PCF = enum(u2) { - /// MAC prevents all control frames from reaching the application - PreventAll = 0x0, - /// MAC forwards all control frames to application except Pause - ForwardAllExceptPause = 0x1, - /// MAC forwards all control frames to application even if they fail the address filter - ForwardAll = 0x2, - /// MAC forwards control frames that pass the address filter - ForwardAllFiltered = 0x3, - }; - - pub const PD = enum(u1) { - /// All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received - Enabled = 0x1, + pub const HDPL = enum(u8) { + /// HDPL1, iRoT + B_0x51 = 0x51, + /// HDPL3, application + B_0x6F = 0x6f, + /// HDPL2, uRoT + B_0x8A = 0x8a, + /// HDPL0, RSS + B_0xB4 = 0xb4, _, }; - pub const PLT = enum(u2) { - /// Pause time minus 4 slot times - PLT4 = 0x0, - /// Pause time minus 28 slot times - PLT28 = 0x1, - /// Pause time minus 144 slot times - PLT144 = 0x2, - /// Pause time minus 256 slot times - PLT256 = 0x3, - }; - - pub const PMTIM = enum(u1) { - /// PMT Status interrupt generation enabled - Unmasked = 0x0, - /// PMT Status interrupt generation disabled - Masked = 0x1, - }; - - pub const PriorityRxOverTx = enum(u2) { - /// RxDMA priority over TxDMA is 1:1 - OneToOne = 0x0, - /// RxDMA priority over TxDMA is 2:1 - TwoToOne = 0x1, - /// RxDMA priority over TxDMA is 3:1 - ThreeToOne = 0x2, - /// RxDMA priority over TxDMA is 4:1 - FourToOne = 0x3, - }; - - pub const RD = enum(u1) { - /// MAC attempts retries based on the settings of BL - Enabled = 0x0, - /// MAC attempts only 1 transmission - Disabled = 0x1, - }; - - pub const RDP = enum(u6) { - /// 1 beat per RxDMA transaction - RDP1 = 0x1, - /// 2 beats per RxDMA transaction - RDP2 = 0x2, - /// 4 beats per RxDMA transaction - RDP4 = 0x4, - /// 8 beats per RxDMA transaction - RDP8 = 0x8, - /// 16 beats per RxDMA transaction - RDP16 = 0x10, - /// 32 beats per RxDMA transaction - RDP32 = 0x20, + pub const INCR_HDPL = enum(u8) { + /// recommended value to increment HDPL level by one + B_0x6A = 0x6a, + /// no increment + B_0xB4 = 0xb4, _, }; - pub const RFAEM = enum(u1) { - /// Received-alignment-error counter half-full interrupt enabled - Unmasked = 0x0, - /// Received-alignment-error counter half-full interrupt disabled - Masked = 0x1, - }; - - pub const RFCEM = enum(u1) { - /// Received-crc-error counter half-full interrupt enabled - Unmasked = 0x0, - /// Received-crc-error counter half-full interrupt disabled - Masked = 0x1, - }; - - pub const RGUFM = enum(u1) { - /// Received-good-unicast counter half-full interrupt enabled - Unmasked = 0x0, - /// Received-good-unicast counter half-full interrupt disabled - Masked = 0x1, - }; - - pub const ROD = enum(u1) { - /// MAC receives all packets from PHY while transmitting - Enabled = 0x0, - /// MAC disables reception of frames in half-duplex mode - Disabled = 0x1, - }; - - pub const RPD = enum(u32) { - /// Poll the receive descriptor list - Poll = 0x0, - _, + /// System configuration, boot and security + pub const SYSCFG = extern struct { + reserved16: [16]u8, + /// SBS temporal isolation control register + HDPLCR: mmio.Mmio(packed struct(u32) { + /// increment HDPL value Other: all other values allow a HDPL level increment. + INCR_HDPL: packed union { + raw: u8, + value: INCR_HDPL, + }, + padding: u24, + }), + /// SBS temporal isolation status register + HDPLSR: mmio.Mmio(packed struct(u32) { + /// temporal isolation level This bitfield returns the current temporal isolation level. + HDPL: packed union { + raw: u8, + value: HDPL, + }, + padding: u24, + }), + reserved32: [8]u8, + /// SBS debug control register + DBGCR: mmio.Mmio(packed struct(u32) { + /// access port unlock Write 0xB4 to this bitfield to open the device access port. + AP_UNLOCK: u8, + /// debug unlock when DBG_AUTH_HDPL is reached Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register. + DBG_UNLOCK: u8, + /// authenticated debug temporal isolation level Writing to this bitfield defines at which HDPL the authenticated debug opens. Note: Writing any other values is ignored. Reading any other value means the debug never opens. + DBG_AUTH_HDPL: packed union { + raw: u8, + value: DBG_AUTH_HDPL, + }, + padding: u8, + }), + /// SBS debug lock register + DBGLOCKR: mmio.Mmio(packed struct(u32) { + /// debug configuration lock Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4. 0xC3 is the recommended value to lock the debug configuration using this bitfield. Other: Writes to SBS_DBGCR ignored + DBGCFG_LOCK: packed union { + raw: u8, + value: DBGCFG_LOCK, + }, + padding: u24, + }), + reserved256: [216]u8, + /// SBS product mode and configuration register + PMCR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// booster enable Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range. + BOOSTEN: u1, + /// booster VDD selection Note: Booster must not be used when VDDA < 2.7 V, but VDD > 2.7 V (add current consumption). Note: When both VDD < 2.7 V and VDDA < 2.7 V, booster is needed to get full AC performances from I/O analog switches. + BOOSTVDDSEL: u1, + reserved16: u6, + /// Fast-mode Plus command on PB(6) + PB6_FMPLUS: u1, + /// Fast-mode Plus command on PB(7) + PB7_FMPLUS: u1, + /// Fast-mode Plus command on PB(8) + PB8_FMPLUS: u1, + padding: u13, + }), + /// SBS FPU interrupt mask register + FPUIMR: mmio.Mmio(packed struct(u32) { + /// FPU interrupt enable Set and cleared by software to enable the Cortex-M33 FPU interrupts FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset) FPU_IE[4]: input abnormal interrupt enable FPU_IE[3]: overflow interrupt enable FPU_IE[2]: underflow interrupt enable FPU_IE[1]: divide-by-zero interrupt enable FPU_IE[0]: invalid operation interrupt enable + FPU_IE: u6, + padding: u26, + }), + /// SBS memory erase status register + MESR: mmio.Mmio(packed struct(u32) { + /// erase after reset status This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, ICACHE. It is set by hardware and reset by software + MCLR: u1, + reserved16: u15, + /// end-of-erase status for ICACHE This bit shows the status of the protection for ICACHE. It is set by hardware and reset by software. + IPMEE: u1, + padding: u15, + }), + reserved272: [4]u8, + /// SBS compensation cell for I/Os control and status register + CCCSR: mmio.Mmio(packed struct(u32) { + /// enable compensation cell for VDDIO power rail This bit enables the I/O compensation cell. + EN: u1, + /// code selection for VDDIO power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. + CS: packed union { + raw: u1, + value: CS, + }, + reserved8: u6, + /// VDDIO compensation cell ready flag This bit provides the status of the compensation cell. + RDY: u1, + padding: u23, + }), + /// SBS compensation cell for I/Os value register + CCVALR: mmio.Mmio(packed struct(u32) { + /// compensation value for the NMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. + ANSRC1: u4, + /// compensation value for the PMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. + APSRC1: u4, + /// Compensation value for the NMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. + ANSRC2: u4, + /// compensation value for the PMOS transistor This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range. + APSRC2: u4, + padding: u16, + }), + /// SBS compensation cell for I/Os software code register + CCSWCR: mmio.Mmio(packed struct(u32) { + /// NMOS compensation code for VDD power rails This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR. + SW_ANSRC1: u4, + /// PMOS compensation code for the VDD power rails This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR. + SW_APSRC1: u4, + /// NMOS compensation code for VDDIO power rails This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR. + SW_ANSRC2: u4, + /// PMOS compensation code for the VDDIO power rails This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR. + SW_APSRC2: u4, + padding: u16, + }), + reserved288: [4]u8, + /// SBS Class B register + CFGR2: mmio.Mmio(packed struct(u32) { + /// core lockup lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1 break inputs. + CLL: u1, + /// SRAM ECC error lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1. + SEL: u1, + /// PVD lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1 break inputs. + PVDL: u1, + /// ECC lock This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1. + ECCL: u1, + padding: u28, + }), + reserved324: [32]u8, + /// SBS CPU lock register + CNSLCKR: mmio.Mmio(packed struct(u32) { + /// VTOR_NS register lock This bit is set by software and cleared only by a system reset. + LOCKNSVTOR: u1, + /// MPU register lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers. + LOCKNSMPU: u1, + padding: u30, + }), + reserved332: [4]u8, + /// SBS flift ECC NMI mask register + ECCNMIR: mmio.Mmio(packed struct(u32) { + /// NMI behavior setup when a double ECC error occurs on flitf data part + ECCNMI_MASK_EN: u1, + padding: u31, + }), }; + }; - pub const RPS = enum(u3) { - /// Stopped, reset or Stop Receive command issued - Stopped = 0x0, - /// Running, fetching receive transfer descriptor - RunningFetching = 0x1, - /// Running, waiting for receive packet - RunningWaiting = 0x3, - /// Suspended, receive descriptor unavailable - Suspended = 0x4, - /// Running, writing data to host memory buffer - RunningWriting = 0x7, + pub const syscfg_h7 = struct { + pub const ETH_SEL_PHY = enum(u3) { + /// GMII or MII + MII_GMII = 0x0, + /// RMII + RMII = 0x4, _, }; - pub const RSF = enum(u1) { - /// Rx FIFO operates in cut-through mode, subject to RTC bits - CutThrough = 0x0, - /// Frames are read from Rx FIFO after complete frame has been written - StoreForward = 0x1, - }; - - pub const RTC = enum(u2) { - /// 64 bytes - RTC64 = 0x0, - /// 32 bytes - RTC32 = 0x1, - /// 96 bytes - RTC96 = 0x2, - /// 128 bytes - RTC128 = 0x3, - }; - - pub const SAIF = enum(u1) { - /// Source address filter operates normally - Normal = 0x0, - /// Source address filter operation inverted - Invert = 0x1, - }; - - pub const ST = enum(u1) { - /// Transmission is placed in the Stopped state - Stopped = 0x0, - /// Transmission is placed in Running state - Started = 0x1, - }; - - pub const TGFM = enum(u1) { - /// Transmitted-good counter half-full interrupt enabled - Unmasked = 0x0, - /// Transmitted-good counter half-full interrupt disabled - Masked = 0x1, - }; - - pub const TGFMSCM = enum(u1) { - /// Transmitted-good-multiple-collision half-full interrupt enabled - Unmasked = 0x0, - /// Transmitted-good-multiple-collision half-full interrupt disabled - Masked = 0x1, - }; - - pub const TGFSCM = enum(u1) { - /// Transmitted-good-single-collision half-full interrupt enabled - Unmasked = 0x0, - /// Transmitted-good-single-collision half-full interrupt disabled - Masked = 0x1, + pub const ITCM_AXI_RAM_SIZE = enum(u2) { + /// 64 Kbyte ITCM-RAM / 320 Kbyte AXI-SRAM + Itcm64Axi320 = 0x0, + /// 128 Kbyte ITCM-RAM / 256 Kbyte AXI-SRAM + Itcm128Axi256 = 0x1, + /// 192 Kbyte ITCM-RAM / 192 Kbyte AXI-SRAM + Itcm192Axi192 = 0x2, + /// 256 Kbyte ITCM-RAM / 128 Kbyte AXI-SRAM + Itcm256Axi128 = 0x3, }; - pub const TPD = enum(u32) { - /// Poll the transmit descriptor list - Poll = 0x0, - _, + /// System configuration controller + pub const SYSCFG = extern struct { + reserved4: [4]u8, + /// peripheral mode configuration register + PMCR: mmio.Mmio(packed struct(u32) { + /// I2C1 Fm+ + I2C1FMP: u1, + /// I2C2 Fm+ + I2C2FMP: u1, + /// I2C3 Fm+ + I2C3FMP: u1, + /// I2C4 Fm+ + I2C4FMP: u1, + /// PB(6) Fm+ + PB6FMP: u1, + /// PB(7) Fast Mode Plus + PB7FMP: u1, + /// PB(8) Fast Mode Plus + PB8FMP: u1, + /// PB(9) Fm+ + PB9FMP: u1, + /// Booster Enable + BOOSTE: u1, + /// Analog switch supply voltage selection + BOOSTVDDSEL: u1, + reserved21: u11, + /// Ethernet PHY interface selection. + ETH_SEL_PHY: packed union { + raw: u3, + value: ETH_SEL_PHY, + }, + /// PA0 Switch Open + PA0SO: u1, + /// PA1 Switch Open + PA1SO: u1, + /// PC2 Switch Open + PC2SO: u1, + /// PC3 Switch Open + PC3SO: u1, + padding: u4, + }), + /// external interrupt configuration register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 4 to 7) + EXTI: u4, + padding: u28, + }), + reserved32: [8]u8, + /// compensation cell control/status register + CCCSR: mmio.Mmio(packed struct(u32) { + /// enable + EN: u1, + /// Code selection + CS: u1, + reserved8: u6, + /// Compensation cell ready flag + RDY: u1, + reserved16: u7, + /// High-speed at low-voltage + HSLV: u1, + padding: u15, + }), + /// SYSCFG compensation cell value register + CCVR: mmio.Mmio(packed struct(u32) { + /// NMOS compensation value + NCV: u4, + /// PMOS compensation value + PCV: u4, + padding: u24, + }), + /// SYSCFG compensation cell code register + CCCR: mmio.Mmio(packed struct(u32) { + /// NMOS compensation code + NCC: u4, + /// PMOS compensation code + PCC: u4, + padding: u24, + }), + reserved292: [248]u8, + /// SYSCFG package register + PKGR: mmio.Mmio(packed struct(u32) { + /// Package + PKG: u4, + padding: u28, + }), + reserved768: [472]u8, + /// SYSCFG user register 0 + UR0: mmio.Mmio(packed struct(u32) { + /// Bank Swap + BKS: u1, + reserved16: u15, + /// Readout protection + RDP: u8, + padding: u8, + }), + reserved776: [4]u8, + /// SYSCFG user register 2 + UR2: mmio.Mmio(packed struct(u32) { + /// BOR_LVL Brownout Reset Threshold Level + BORH: u2, + reserved16: u14, + /// Boot Address 0 + BOOT_ADD0: u16, + }), + /// SYSCFG user register 3 + UR3: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Boot Address 1 + BOOT_ADD1: u16, + }), + /// SYSCFG user register 4 + UR4: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Mass Erase Protected Area Disabled for bank 1 + MEPAD_1: u1, + padding: u15, + }), + /// SYSCFG user register 5 + UR5: mmio.Mmio(packed struct(u32) { + /// Mass erase secured area disabled for bank 1 + MESAD_1: u1, + reserved16: u15, + /// Write protection for flash bank 1 + WRPN_1: u8, + padding: u8, + }), + /// SYSCFG user register 6 + UR6: mmio.Mmio(packed struct(u32) { + /// Protected area start address for bank 1 + PA_BEG_1: u12, + reserved16: u4, + /// Protected area end address for bank 1 + PA_END_1: u12, + padding: u4, + }), + /// SYSCFG user register 7 + UR7: mmio.Mmio(packed struct(u32) { + /// Secured area start address for bank 1 + SA_BEG_1: u12, + reserved16: u4, + /// Secured area end address for bank 1 + SA_END_1: u12, + padding: u4, + }), + /// SYSCFG user register 8 + UR8: mmio.Mmio(packed struct(u32) { + /// Mass erase protected area disabled for bank 2 + MEPAD_2: u1, + reserved16: u15, + /// Mass erase secured area disabled for bank 2 + MESAD_2: u1, + padding: u15, + }), + /// SYSCFG user register 9 + UR9: mmio.Mmio(packed struct(u32) { + /// Write protection for flash bank 2 + WRPN_2: u8, + reserved16: u8, + /// Protected area start address for bank 2 + PA_BEG_2: u12, + padding: u4, + }), + /// SYSCFG user register 10 + UR10: mmio.Mmio(packed struct(u32) { + /// Protected area end address for bank 2 + PA_END_2: u12, + reserved16: u4, + /// Secured area start address for bank 2 + SA_BEG_2: u12, + padding: u4, + }), + /// SYSCFG user register 11 + UR11: mmio.Mmio(packed struct(u32) { + /// Secured area end address for bank 2 + SA_END_2: u12, + reserved16: u4, + /// Independent Watchdog 1 mode + IWDG1M: u1, + padding: u15, + }), + /// SYSCFG user register 12 + UR12: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Secure mode + SECURE: u1, + padding: u15, + }), + /// SYSCFG user register 13 + UR13: mmio.Mmio(packed struct(u32) { + /// Secured DTCM RAM Size + SDRS: u2, + reserved16: u14, + /// D1 Standby reset + D1SBRST: u1, + padding: u15, + }), + /// SYSCFG user register 14 + UR14: mmio.Mmio(packed struct(u32) { + /// D1 Stop Reset + D1STPRST: u1, + padding: u31, + }), + /// SYSCFG user register 15 + UR15: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Freeze independent watchdog in Standby mode + FZIWDGSTB: u1, + padding: u15, + }), + /// SYSCFG user register 16 + UR16: mmio.Mmio(packed struct(u32) { + /// Freeze independent watchdog in Stop mode + FZIWDGSTP: u1, + reserved16: u15, + /// Private key programmed + PKP: u1, + padding: u15, + }), + /// SYSCFG user register 17 + UR17: mmio.Mmio(packed struct(u32) { + /// I/O high speed / low voltage + IO_HSLV: u1, + reserved16: u15, + /// ITCM-RAM / AXI-SRAM size + TCM_AXI_SHARED_CFG: packed union { + raw: u2, + value: ITCM_AXI_RAM_SIZE, + }, + padding: u14, + }), + /// SYSCFG user register 18 + UR18: mmio.Mmio(packed struct(u32) { + /// CPU maximum frequency boost enable + CPU_FREQ_BOOST: u1, + padding: u31, + }), }; + }; - pub const TPS = enum(u3) { - /// Stopped, Reset or Stop Transmit command issued - Stopped = 0x0, - /// Running, fetching transmit transfer descriptor - RunningFetching = 0x1, - /// Running, waiting for status - RunningWaiting = 0x2, - /// Running, reading data from host memory buffer - RunningReading = 0x3, - /// Suspended, transmit descriptor unavailable or transmit buffer underflow - Suspended = 0x6, - /// Running, closing transmit descriptor - Running = 0x7, + pub const syscfg_h7od = struct { + pub const ETH_SEL_PHY = enum(u3) { + /// GMII or MII + MII_GMII = 0x0, + /// RMII + RMII = 0x4, _, }; - pub const TSF = enum(u1) { - /// Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold - CutThrough = 0x0, - /// Transmission starts when a full frame is in the Tx FIFO - StoreForward = 0x1, - }; - - pub const TSTIM = enum(u1) { - /// Time stamp interrupt generation enabled - Unmasked = 0x0, - /// Time stamp interrupt generation disabled - Masked = 0x1, - }; - - pub const TTC = enum(u3) { - /// 64 bytes - TTC64 = 0x0, - /// 128 bytes - TTC128 = 0x1, - /// 192 bytes - TTC192 = 0x2, - /// 256 bytes - TTC256 = 0x3, - /// 40 bytes - TTC40 = 0x4, - /// 32 bytes - TTC32 = 0x5, - /// 24 bytes - TTC24 = 0x6, - /// 16 bytes - TTC16 = 0x7, - }; - - pub const USP = enum(u1) { - /// PBL value used for both Rx and Tx DMA - Combined = 0x0, - /// RxDMA uses RDP value, TxDMA uses PBL value - Separate = 0x1, - }; - - pub const VLANTC = enum(u1) { - /// Full 16 bit VLAN identifiers are used for comparison and filtering - VLANTC16 = 0x0, - /// 12 bit VLAN identifies are used for comparison and filtering - VLANTC12 = 0x1, + /// System configuration controller + pub const SYSCFG = extern struct { + reserved4: [4]u8, + /// peripheral mode configuration register + PMCR: mmio.Mmio(packed struct(u32) { + /// I2C1 Fm+ + I2C1FMP: u1, + /// I2C2 Fm+ + I2C2FMP: u1, + /// I2C3 Fm+ + I2C3FMP: u1, + /// I2C4 Fm+ + I2C4FMP: u1, + /// PB(6) Fm+ + PB6FMP: u1, + /// PB(7) Fast Mode Plus + PB7FMP: u1, + /// PB(8) Fast Mode Plus + PB8FMP: u1, + /// PB(9) Fm+ + PB9FMP: u1, + /// Booster Enable + BOOSTE: u1, + /// Analog switch supply voltage selection + BOOSTVDDSEL: u1, + reserved21: u11, + /// Ethernet PHY interface selection. + ETH_SEL_PHY: packed union { + raw: u3, + value: ETH_SEL_PHY, + }, + /// PA0 Switch Open + PA0SO: u1, + /// PA1 Switch Open + PA1SO: u1, + /// PC2 Switch Open + PC2SO: u1, + /// PC3 Switch Open + PC3SO: u1, + padding: u4, + }), + /// external interrupt configuration register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 4 to 7) + EXTI: u4, + padding: u28, + }), + reserved32: [8]u8, + /// compensation cell control/status register + CCCSR: mmio.Mmio(packed struct(u32) { + /// enable + EN: u1, + /// Code selection + CS: u1, + reserved8: u6, + /// Compensation cell ready flag + RDY: u1, + reserved16: u7, + /// High-speed at low-voltage + HSLV: u1, + padding: u15, + }), + /// SYSCFG compensation cell value register + CCVR: mmio.Mmio(packed struct(u32) { + /// NMOS compensation value + NCV: u4, + /// PMOS compensation value + PCV: u4, + padding: u24, + }), + /// SYSCFG compensation cell code register + CCCR: mmio.Mmio(packed struct(u32) { + /// NMOS compensation code + NCC: u4, + /// PMOS compensation code + PCC: u4, + padding: u24, + }), + /// SYSCFG power control register + PWRCR: mmio.Mmio(packed struct(u32) { + /// Overdrive enable + ODEN: u4, + padding: u28, + }), + reserved292: [244]u8, + /// SYSCFG package register + PKGR: mmio.Mmio(packed struct(u32) { + /// Package + PKG: u4, + padding: u28, + }), + reserved768: [472]u8, + /// SYSCFG user register 0 + UR0: mmio.Mmio(packed struct(u32) { + /// Bank Swap + BKS: u1, + reserved16: u15, + /// Readout protection + RDP: u8, + padding: u8, + }), + reserved776: [4]u8, + /// SYSCFG user register 2 + UR2: mmio.Mmio(packed struct(u32) { + /// BOR_LVL Brownout Reset Threshold Level + BORH: u2, + reserved16: u14, + /// Boot Address 0 + BOOT_ADD0: u16, + }), + /// SYSCFG user register 3 + UR3: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Boot Address 1 + BOOT_ADD1: u16, + }), + /// SYSCFG user register 4 + UR4: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Mass Erase Protected Area Disabled for bank 1 + MEPAD_1: u1, + padding: u15, + }), + /// SYSCFG user register 5 + UR5: mmio.Mmio(packed struct(u32) { + /// Mass erase secured area disabled for bank 1 + MESAD_1: u1, + reserved16: u15, + /// Write protection for flash bank 1 + WRPN_1: u8, + padding: u8, + }), + /// SYSCFG user register 6 + UR6: mmio.Mmio(packed struct(u32) { + /// Protected area start address for bank 1 + PA_BEG_1: u12, + reserved16: u4, + /// Protected area end address for bank 1 + PA_END_1: u12, + padding: u4, + }), + /// SYSCFG user register 7 + UR7: mmio.Mmio(packed struct(u32) { + /// Secured area start address for bank 1 + SA_BEG_1: u12, + reserved16: u4, + /// Secured area end address for bank 1 + SA_END_1: u12, + padding: u4, + }), + /// SYSCFG user register 8 + UR8: mmio.Mmio(packed struct(u32) { + /// Mass erase protected area disabled for bank 2 + MEPAD_2: u1, + reserved16: u15, + /// Mass erase secured area disabled for bank 2 + MESAD_2: u1, + padding: u15, + }), + /// SYSCFG user register 9 + UR9: mmio.Mmio(packed struct(u32) { + /// Write protection for flash bank 2 + WRPN_2: u8, + reserved16: u8, + /// Protected area start address for bank 2 + PA_BEG_2: u12, + padding: u4, + }), + /// SYSCFG user register 10 + UR10: mmio.Mmio(packed struct(u32) { + /// Protected area end address for bank 2 + PA_END_2: u12, + reserved16: u4, + /// Secured area start address for bank 2 + SA_BEG_2: u12, + padding: u4, + }), + /// SYSCFG user register 11 + UR11: mmio.Mmio(packed struct(u32) { + /// Secured area end address for bank 2 + SA_END_2: u12, + reserved16: u4, + /// Independent Watchdog 1 mode + IWDG1M: u1, + padding: u15, + }), + /// SYSCFG user register 12 + UR12: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Secure mode + SECURE: u1, + padding: u15, + }), + /// SYSCFG user register 13 + UR13: mmio.Mmio(packed struct(u32) { + /// Secured DTCM RAM Size + SDRS: u2, + reserved16: u14, + /// D1 Standby reset + D1SBRST: u1, + padding: u15, + }), + /// SYSCFG user register 14 + UR14: mmio.Mmio(packed struct(u32) { + /// D1 Stop Reset + D1STPRST: u1, + padding: u31, + }), + /// SYSCFG user register 15 + UR15: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Freeze independent watchdog in Standby mode + FZIWDGSTB: u1, + padding: u15, + }), + /// SYSCFG user register 16 + UR16: mmio.Mmio(packed struct(u32) { + /// Freeze independent watchdog in Stop mode + FZIWDGSTP: u1, + reserved16: u15, + /// Private key programmed + PKP: u1, + padding: u15, + }), + /// SYSCFG user register 17 + UR17: mmio.Mmio(packed struct(u32) { + /// I/O high speed / low voltage + IO_HSLV: u1, + padding: u31, + }), }; + }; - pub const WD = enum(u1) { - /// Watchdog enabled, receive frames limited to 2048 bytes - Enabled = 0x0, - /// Watchdog disabled, receive frames may be up to to 16384 bytes - Disabled = 0x1, + pub const syscfg_h7rs = struct { + pub const AXIRAM_WS = enum(u1) { + /// No wait state added when accessing any AXIRAM with ECC = 0. + Ws0 = 0x0, + /// One wait state added when accessing any AXIRAM with ECC = 0. In this case, Fmax = 500 MHz is not guaranteed. (TBC). + Ws1 = 0x1, }; - pub const WFFRPR = enum(u1) { - /// Reset wakeup frame filter register point to 0b000. Automatically cleared - Reset = 0x1, + pub const DBGCFG_LOCK = enum(u8) { + /// Writes to SBS_DBGCR allowed (default). + Unlock = 0xb4, _, }; - pub const ZQPD = enum(u1) { - /// Normal operation with automatic zero-quanta pause control frame generation - Enabled = 0x0, - /// Automatic generation of zero-quanta pause control frames is disabled - Disabled = 0x1, - }; - - /// Ethernet Peripheral - pub const ETH = extern struct { - /// Ethernet: media access control (MAC) - ETHERNET_MAC: u32, - reserved1792: [1788]u8, - /// Ethernet: Precision Time Protocol (PTP) - ETHERNET_PTP: u32, - reserved4096: [2300]u8, - /// Ethernet: DMA mode register (DMA) - ETHERNET_DMA: u32, - }; - - /// Ethernet: DMA controller operation - pub const ETHERNET_DMA = extern struct { - /// Ethernet DMA bus mode register - DMABMR: mmio.Mmio(packed struct(u32) { - /// Software reset - SR: u1, - /// DMA arbitration - DA: packed union { - raw: u1, - value: DA, - }, - /// Descriptor skip length - DSL: u5, - /// Enhanced descriptor format enable - EDFE: u1, - /// Programmable burst length - PBL: packed union { - raw: u6, - value: PBL, - }, - /// Rx-Tx priority ratio - PM: packed union { - raw: u2, - value: PriorityRxOverTx, - }, - /// Fixed burst - FB: packed union { - raw: u1, - value: FB, + pub const DBG_AUTH_HDPL = enum(u8) { + /// HDPL1. + HDPL1 = 0x51, + /// HDPL3. + HDPL3 = 0x6f, + /// HDPL2. + HDPL2 = 0x8a, + _, + }; + + pub const ETH_SEL_PHY = enum(u3) { + /// GMII or MII + MII_GMII = 0x0, + /// RMII + RMII = 0x4, + _, + }; + + pub const HDPL = enum(u8) { + /// HDPL1. + HDPL1 = 0x51, + /// HDPL2. + HDPL2 = 0x8a, + /// HDPL0, corresponding to ST-RSS (default when device is close). + HDPL0 = 0xb4, + _, + }; + + /// System configuration, boot and security. + pub const SYSCFG = extern struct { + /// SBS boot status register. + BOOTSR: mmio.Mmio(packed struct(u32) { + /// initial vector for Cortex-M7 This register includes the physical boot address used by the Cortex-M7 after reset. + INITVTOR: u32, + }), + reserved16: [12]u8, + /// SBS hide protection control register. + HDPLCR: mmio.Mmio(packed struct(u32) { + /// increment HDPL Write 0x6A to increment device HDPL by one. After a write, the register value reverts to its default value (0xB4). + INCR_HDPL: u8, + padding: u24, + }), + /// SBS hide protection status register. + HDPLSR: mmio.Mmio(packed struct(u32) { + /// hide protection level This bitfield returns the current HDPL of the device. 0x6F and other codes: HDPL3, corresponding to non-boot application. Note: The device state (open/close) is defined in FLASH_NVSTATER register of the embedded Flash memory. + HDPL: packed union { + raw: u8, + value: HDPL, }, - /// Rx DMA PBL - RDP: packed union { - raw: u6, - value: RDP, + padding: u24, + }), + reserved32: [8]u8, + /// SBS debug control register. + DBGCR: mmio.Mmio(packed struct(u32) { + /// access port unlock Write 0xB4 to this bitfield to open the device access port. + AP_UNLOCK: u8, + /// debug unlock Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register. + DBG_UNLOCK: u8, + /// authenticated debug hide protection level Writing to this bitfield defines at which HDPL the authenticated debug opens. Note: Writing any other values is ignored. Reading any other value means the authenticated debug always fails. + DBG_AUTH_HDPL: packed union { + raw: u8, + value: DBG_AUTH_HDPL, }, - /// Use separate PBL - USP: packed union { - raw: u1, - value: USP, + padding: u8, + }), + /// SBS debug lock register. + DBGLOCKR: mmio.Mmio(packed struct(u32) { + /// debug configuration lock Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4. Other: Writes to SBS_DBGCR ignored Note: 0xC3 is the recommended value to lock the debug configuration using this bitfield. + DBGCFG_LOCK: packed union { + raw: u8, + value: DBGCFG_LOCK, }, - /// 4xPBL mode - FPM: packed union { - raw: u1, - value: FPM, + padding: u24, + }), + reserved52: [12]u8, + /// SBS RSS command register. + RSSCMDR: mmio.Mmio(packed struct(u32) { + /// RSS command The application can use this bitfield to pass on a command to the RSS, executed at the next reset. + RSSCMD: u16, + padding: u16, + }), + reserved256: [200]u8, + /// SBS product mode and configuration register. + PMCR: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Fast-mode Plus on PB(6). + FMPLUS_PB6: u1, + /// Fast-mode Plus on PB(7). + FMPLUS_PB7: u1, + /// Fast-mode Plus on PB(8). + FMPLUS_PB8: u1, + /// Fast-mode Plus on PB(9). + FMPLUS_PB9: u1, + /// booster enable Set this bit to reduce the THD of the analog switches when the supply voltage is below 2.7 V. guaranteeing the same performance as with the full voltage range. To avoid current consumption due to booster activation when VDDA < 2.7 V and VDD > 2.7 V, VDD can be selected as supply voltage for analog switches by setting BOOSTVDDSEL bit in SBS_PMCR. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption. + BOOSTEN: u1, + /// booster VDD selection This bit selects the analog switch supply voltage, between VDD, VDDA and booster. To avoid current consumption due to booster activation when VDDA < 2.7 V and VDD > 2.7 V, VDD can be selected as supply voltage for analog switches. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption. When both VDD and VDDA are below 2.7 V, the booster is still needed to obtain full AC performances from the I/O analog switches. + BOOSTVDDSEL: u1, + reserved21: u11, + /// Ethernet PHY interface selection. + ETH_SEL_PHY: packed union { + raw: u3, + value: ETH_SEL_PHY, }, - /// Address-aligned beats - AAB: u1, - /// Mixed burst - MB: packed union { + reserved28: u4, + /// AXIRAM wait state Set this bit to add one wait state to all AXIRAMs when ECC = 0. When ECC = 1 there is one wait state by default. + AXIRAM_WS: packed union { raw: u1, - value: MB, + value: AXIRAM_WS, }, - padding: u5, + padding: u3, }), - /// Ethernet DMA transmit poll demand register - DMATPDR: mmio.Mmio(packed struct(u32) { - /// Transmit poll demand - TPD: packed union { - raw: u32, - value: TPD, - }, + /// SBS FPU interrupt mask register. + FPUIMR: mmio.Mmio(packed struct(u32) { + /// FPU interrupt enable Set and cleared by software to enable the Cortex-M7 FPU interrupts xxxxx1: Invalid operation interrupt enabled (xxxxx0 to disable) xxxx1x: Divide-by-zero interrupt enabled (xxxx0x to disable) xxx1xx: Underflow interrupt enabled (xxx0xx to disable) xx1xxx: Overflow interrupt enabled (xx0xxx to disable) x1xxxx: Input denormal interrupt enabled (x0xxxx to disable) 1xxxxx: Inexact interrupt enabled (0xxxxx to disable), disabled by default. + FPU_IE: u6, + padding: u26, }), - /// EHERNET DMA receive poll demand register - DMARPDR: mmio.Mmio(packed struct(u32) { - /// Receive poll demand - RPD: packed union { - raw: u32, - value: RPD, - }, + /// SBS memory erase status register. + MESR: mmio.Mmio(packed struct(u32) { + /// memory erase flag This bit is set by hardware when BKPRAM and PKA SRAM erase is ongoing after a POWER ON reset or one tamper event (see Section 50: Tamper and backup registers (TAMP) for details). This bit is cleared when the erase is done. + MEF: u1, + padding: u31, }), - /// Ethernet DMA receive descriptor list address register - DMARDLAR: mmio.Mmio(packed struct(u32) { - /// Start of receive list - SRL: u32, + reserved272: [4]u8, + /// SBS I/O compensation cell control and status register. + CCCSR: mmio.Mmio(packed struct(u32) { + /// Compensation cell enable Set this bit to enable the compensation cell. + COMP_EN: u1, + /// Compensation cell code selection This bit selects the code to be applied for the I/O compensation cell. + COMP_CODESEL: u1, + /// XSPIM_P1 compensation cell enable Set this bit to enable the XSPIM_P1 compensation cell. + OCTO1_COMP_EN: u1, + /// XSPIM_P1 compensation cell code selection This bit selects the code to be applied for the XSPIM_P1 I/O compensation cell. + OCTO1_COMP_CODESEL: u1, + /// XSPIM_P2 compensation cell enable Set this bit to enable the XSPIM_P2 compensation cell. + OCTO2_COMP_EN: u1, + /// XSPIM_P2 compensation cell code selection This bit selects the code to be applied for the XSPIM_P2 I/O compensation cell. + OCTO2_COMP_CODESEL: u1, + reserved8: u2, + /// Compensation cell ready This bit provides the status of the compensation cell. + COMP_RDY: u1, + /// XSPIM_P1 compensation cell ready This bit provides the status of the XSPIM_P1 compensation cell. + OCTO1_COMP_RDY: u1, + /// XSPIM_P2 compensation cell ready This bit provides the status of the XSPIM_P2 compensation cell. + OCTO2_COMP_RDY: u1, + reserved16: u5, + /// I/O high speed at low voltage When this bit is set, the speed of the I/Os is optimized when the device voltage is low. This bit is active only if VDDIO_HSLV user option bit is set in FLASH. It must be used only if the device supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V may be destructive. + IOHSLV: u1, + /// XSPIM_P1 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P1 I/Os is optimized when the device voltage is low. This bit is active only if OCTO1_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V may be destructive. + OCTO1_IOHSLV: u1, + /// XSPIM_P2 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P2 I/Os is optimized when the device voltage is low. This bit is active only if OCTO2_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V may be destructive. + OCTO2_IOHSLV: u1, + padding: u13, }), - /// Ethernet DMA transmit descriptor list address register - DMATDLAR: mmio.Mmio(packed struct(u32) { - /// Start of transmit list - STL: u32, + /// SBS compensation cell for I/Os value register. + CCVALR: mmio.Mmio(packed struct(u32) { + /// NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register. + NSRC: u4, + /// PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register. + PSRC: u4, + /// XSPIM_P1 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register. + OCTO1_NSRC: u4, + /// XSPIM_P1 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register. + OCTO1_PSRC: u4, + /// XSPIM_P2 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register. + OCTO2_NSRC: u4, + /// XSPIM_P2 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register. + OCTO2_PSRC: u4, + padding: u8, }), - /// Ethernet DMA status register - DMASR: mmio.Mmio(packed struct(u32) { - /// Transmit status - TS: u1, - /// Transmit process stopped status - TPSS: u1, - /// Transmit buffer unavailable status - TBUS: u1, - /// Transmit jabber timeout status - TJTS: u1, - /// Receive overflow status - ROS: u1, - /// Transmit underflow status - TUS: u1, - /// Receive status - RS: u1, - /// Receive buffer unavailable status - RBUS: u1, - /// Receive process stopped status - RPSS: u1, - /// PWTS - PWTS: u1, - /// Early transmit status - ETS: u1, - reserved13: u2, - /// Fatal bus error status - FBES: u1, - /// Early receive status - ERS: u1, - /// Abnormal interrupt summary - AIS: u1, - /// Normal interrupt summary - NIS: u1, - /// Receive process state - RPS: packed union { - raw: u3, - value: RPS, - }, - /// Transmit process state - TPS: packed union { - raw: u3, - value: TPS, - }, - /// Error bits status - EBS: u3, - reserved27: u1, - /// MMC status - MMCS: u1, - /// PMT status - PMTS: u1, - /// Time stamp trigger status - TSTS: u1, - padding: u2, + /// SBS compensation cell for I/Os software value register. + CCSWVALR: mmio.Mmio(packed struct(u32) { + /// Software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register. + SW_NSRC: u4, + /// Software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register. + SW_PSRC: u4, + /// XSPIM_P1 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew -ate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register. + OCTO1_SW_NSRC: u4, + /// XSPIM_P1 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register. + OCTO1_SW_PSRC: u4, + /// XSPIM_P2 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register. + OCTO2_SW_NSRC: u4, + /// XSPIM_P2 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register. + OCTO2_SW_PSRC: u4, + padding: u8, }), - /// Ethernet DMA operation mode register - DMAOMR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Start/stop receive - SR: packed union { - raw: u1, - value: DMAOMR_SR, - }, - /// Operate on second frame - OSF: u1, - /// Receive threshold control - RTC: packed union { - raw: u2, - value: RTC, - }, - reserved6: u1, - /// Forward undersized good frames - FUGF: packed union { - raw: u1, - value: FUGF, - }, - /// Forward error frames - FEF: packed union { - raw: u1, - value: FEF, - }, + reserved288: [4]u8, + /// SBS break lockup register. + BKLOCKR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// PVD break lock This bit is set by SW and cleared only by a system reset. it can be used to enable and lock the connection to TIM1/8/15/16/17Break input as well as the PVDE and PLS[2:0] bitfields in the PWR_CR1 register. Once set, this bit is cleared only by a system reset. + PVD_BL: u1, + /// Flash ECC error break lock Set this bit to enable and lock the connection between embedded flash memory ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. + FLASHECC_BL: u1, + reserved6: u2, + /// Cortex-M7 lockup break lock Set this bit to enable and lock the connection between the Cortex-M7 lockup (HardFault) output and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. + CM7LCKUP_BL: u1, + /// Backup RAM ECC error break lock Set this bit to enable and lock the connection between backup RAM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. + BKRAMECC_BL: u1, reserved13: u5, - /// Start/stop transmission - ST: packed union { - raw: u1, - value: ST, - }, - /// Transmit threshold control - TTC: packed union { - raw: u3, - value: TTC, - }, - reserved20: u3, - /// Flush transmit FIFO - FTF: packed union { - raw: u1, - value: FTF, - }, - /// Transmit store and forward - TSF: packed union { - raw: u1, - value: TSF, - }, - reserved24: u2, - /// Disable flushing of received frames - DFRF: u1, - /// Receive store and forward - RSF: packed union { - raw: u1, - value: RSF, - }, - /// Dropping of TCP/IP checksum error frames disable - DTCEFD: packed union { - raw: u1, - value: DTCEFD, - }, - padding: u5, + /// DTCM ECC error break lock Set this bit to enable and lock the connection between DTCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. Note: The DTCM0 and DTCM1 are Ored to give DTCMECC. + DTCMECC_BL: u1, + /// ITCM ECC error break lock Set this bit to enable and lock the connection between ITCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. + ITCMECC_BL: u1, + reserved21: u6, + /// AXIRAM3 ECC error break lock Set this bit to enable and lock the connection between AXIRAM3 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set this bit is cleared only by a system reset. + ARAM3ECC_BL: u1, + reserved23: u1, + /// AXIRAM1 ECC error break lock Set this bit to enable and lock the connection between AXIRAM1 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. + ARAM1ECC_BL: u1, + padding: u8, }), - /// Ethernet DMA interrupt enable register - DMAIER: mmio.Mmio(packed struct(u32) { - /// Transmit interrupt enable - TIE: u1, - /// Transmit process stopped interrupt enable - TPSIE: u1, - /// Transmit buffer unavailable interrupt enable - TBUIE: u1, - /// Transmit jabber timeout interrupt enable - TJTIE: u1, - /// Receive overflow interrupt enable - ROIE: u1, - /// Transmit underflow interrupt enable - TUIE: u1, - /// Receive interrupt enable - RIE: u1, - /// Receive buffer unavailable interrupt enable - RBUIE: u1, - /// Receive process stopped interrupt enable - RPSIE: u1, - /// Receive watchdog timeout interrupt enable - RWTIE: u1, - /// Early transmit interrupt enable - ETIE: u1, - reserved13: u2, - /// Fatal bus error interrupt enable - FBEIE: u1, - /// Early receive interrupt enable - ERIE: u1, - /// Abnormal interrupt summary enable - AISE: u1, - /// Normal interrupt summary enable - NISE: u1, - padding: u15, + reserved304: [12]u8, + /// external interrupt configuration register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 4 to 7) + EXTI: u4, + padding: u28, }), - /// Ethernet DMA missed frame and buffer overflow counter register - DMAMFBOCR: mmio.Mmio(packed struct(u32) { - /// Missed frames by the controller - MFC: u16, - /// Overflow bit for missed frame counter - OMFC: u1, - /// Missed frames by the application - MFA: u11, - /// Overflow bit for FIFO overflow counter - OFOC: u1, - padding: u3, + }; + }; + + pub const syscfg_l0 = struct { + /// System configuration controller + pub const SYSCFG = extern struct { + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection bits + MEM_MODE: u2, + reserved3: u1, + /// User bank swapping + UFB: u1, + reserved8: u4, + /// Boot mode selected by the boot pins status bits + BOOT_MODE: u2, + padding: u22, }), - /// Ethernet DMA receive status watchdog timer register - DMARSWTR: mmio.Mmio(packed struct(u32) { - /// Receive status watchdog timer count - RSWTC: u8, + /// CFGR2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Firewall disable bit + FWDIS: u1, + reserved8: u7, + /// Fm+ drive capability on PB6 enable bit + I2C_PB6_FMP: u1, + /// Fm+ drive capability on PB7 enable bit + I2C_PB7_FMP: u1, + /// Fm+ drive capability on PB8 enable bit + I2C_PB8_FMP: u1, + /// Fm+ drive capability on PB9 enable bit + I2C_PB9_FMP: u1, + /// I2C1 Fm+ drive capability enable bit + I2C1_FMP: u1, + /// I2C2 Fm+ drive capability enable bit + I2C2_FMP: u1, + /// I2C3 Fm+ drive capability enable bit + I2C3_FMP: u1, + padding: u17, + }), + /// external interrupt configuration register + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI configuration bits + EXTI: u4, + padding: u28, + }), + reserved32: [8]u8, + /// CFGR3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// VREFINT enable and scaler control for COMP2 enable bit + EN_VREFINT: u1, + reserved4: u3, + /// VREFINT_ADC connection bit + SEL_VREF_OUT: u2, + reserved8: u2, + /// VREFINT reference for ADC enable bit + ENBUF_VREFINT_ADC: u1, + /// Temperature sensor reference for ADC enable bit + ENBUF_SENSOR_ADC: u1, + reserved12: u2, + /// VREFINT reference for COMP2 scaler enable bit + ENBUF_VREFINT_COMP2: u1, + /// VREFINT reference for HSI48 oscillator enable bit + ENREF_HSI48: u1, + reserved30: u16, + /// VREFINT ready flag + VREFINT_RDYF: u1, + /// SYSCFG_CFGR3 lock bit + REF_LOCK: u1, + }), + }; + }; + + pub const syscfg_l1 = struct { + /// System configuration controller + pub const SYSCFG = extern struct { + /// memory remap register + MEMRMP: mmio.Mmio(packed struct(u32) { + /// MEM_MODE + MEM_MODE: u2, + reserved8: u6, + /// BOOT_MODE + BOOT_MODE: u2, + padding: u22, + }), + /// peripheral mode configuration register + PMC: mmio.Mmio(packed struct(u32) { + /// USB pull-up + USB_PU: u1, + /// USB pull-up enable on DP line + LCD_CAPA: u5, + padding: u26, + }), + /// external interrupt configuration register 1 + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 8 to 11) + EXTI: u4, + padding: u28, + }), + }; + }; + + pub const syscfg_l4 = struct { + /// System configuration controller + pub const SYSCFG = extern struct { + /// memory remap register + MEMRMP: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection + MEM_MODE: u3, + /// QUADSPI memory mapping swap + QFS: u1, + reserved8: u4, + /// Flash Bank mode selection + FB_MODE: u1, + padding: u23, + }), + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// Firewall disable + FWDIS: u1, + reserved8: u7, + /// I/O analog switch voltage booster enable + BOOSTEN: u1, + reserved16: u7, + /// Fast-mode Plus (Fm+) driving capability activation on PB6 + I2C_PB6_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB7 + I2C_PB7_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB8 + I2C_PB8_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB9 + I2C_PB9_FMP: u1, + /// I2C1 Fast-mode Plus driving capability activation + I2C1_FMP: u1, + /// I2C2 Fast-mode Plus driving capability activation + I2C2_FMP: u1, + /// I2C3 Fast-mode Plus driving capability activation + I2C3_FMP: u1, + reserved26: u3, + /// Floating Point Unit interrupts enable bits + FPU_IE: u6, + }), + /// external interrupt configuration register 1 + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI12 configuration bits + EXTI: u4, + padding: u28, + }), + /// SCSR + SCSR: mmio.Mmio(packed struct(u32) { + /// SRAM2 Erase + SRAM2ER: u1, + /// SRAM2 busy by erase operation + SRAM2BSY: u1, + padding: u30, + }), + /// CFGR2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Cortex LOCKUP (Hardfault) output enable bit + CLL: u1, + /// SRAM2 parity lock bit + SPL: u1, + /// PVD lock enable bit + PVDL: u1, + /// ECC Lock + ECCL: u1, + reserved8: u4, + /// SRAM2 parity error flag + SPF: u1, + padding: u23, + }), + /// SWPR + SWPR: mmio.Mmio(packed struct(u32) { + /// SRAWM2 write protection. + PWP: u1, + padding: u31, + }), + /// SKR + SKR: mmio.Mmio(packed struct(u32) { + /// SRAM2 write protection key for software erase + KEY: u8, padding: u24, }), - reserved72: [32]u8, - /// Ethernet DMA current host transmit descriptor register - DMACHTDR: mmio.Mmio(packed struct(u32) { - /// Host transmit descriptor address pointer - HTDAP: u32, + }; + }; + + pub const syscfg_l5 = struct { + /// System configuration controller + pub const SYSCFG = extern struct { + /// SYSCFG secure configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock control security + SYSCFGSEC: u1, + /// ClassB security + CLASSBSEC: u1, + /// SRAM2 security + SRAM2SEC: u1, + /// FPUSEC + FPUSEC: u1, + padding: u28, }), - /// Ethernet DMA current host receive descriptor register - DMACHRDR: mmio.Mmio(packed struct(u32) { - /// Host receive descriptor address pointer - HRDAP: u32, + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// I/O analog switch voltage booster enable + BOOSTEN: u1, + /// GPIO analog switch control voltage selection + ANASWVDD: u1, + reserved16: u6, + /// Fast-mode Plus (Fm+) driving capability activation on PB6 + I2C_PB6_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB7 + I2C_PB7_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB8 + I2C_PB8_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB9 + I2C_PB9_FMP: u1, + /// I2C1 Fast-mode Plus driving capability activation + I2C1_FMP: u1, + /// I2C2 Fast-mode Plus driving capability activation + I2C2_FMP: u1, + /// I2C3 Fast-mode Plus driving capability activation + I2C3_FMP: u1, + /// I2C4_FMP + I2C4_FMP: u1, + padding: u8, }), - /// Ethernet DMA current host transmit buffer address register - DMACHTBAR: mmio.Mmio(packed struct(u32) { - /// Host transmit buffer address pointer - HTBAP: u32, + /// FPU interrupt mask register + FPUIMR: mmio.Mmio(packed struct(u32) { + /// Floating point unit interrupts enable bits + FPU_IE: u6, + padding: u26, }), - /// Ethernet DMA current host receive buffer address register - DMACHRBAR: mmio.Mmio(packed struct(u32) { - /// Host receive buffer address pointer - HRBAP: u32, + /// SYSCFG CPU non-secure lock register + CNSLCKR: mmio.Mmio(packed struct(u32) { + /// VTOR_NS register lock + LOCKNSVTOR: u1, + /// Non-secure MPU registers lock + LOCKNSMPU: u1, + padding: u30, + }), + /// SYSCFG CPU secure lock register + CSLOCKR: mmio.Mmio(packed struct(u32) { + /// LOCKSVTAIRCR + LOCKSVTAIRCR: u1, + /// LOCKSMPU + LOCKSMPU: u1, + /// LOCKSAU + LOCKSAU: u1, + padding: u29, + }), + /// CFGR2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// LOCKUP (hardfault) output enable bit + CLL: u1, + /// SRAM2 parity lock bit + SPL: u1, + /// PVD lock enable bit + PVDL: u1, + /// ECC Lock + ECCL: u1, + reserved8: u4, + /// SRAM2 parity error flag + SPF: u1, + padding: u23, + }), + /// SCSR + SCSR: mmio.Mmio(packed struct(u32) { + /// SRAM2 Erase + SRAM2ER: u1, + /// SRAM2 busy by erase operation + SRAM2BSY: u1, + padding: u30, + }), + /// SKR + SKR: mmio.Mmio(packed struct(u32) { + /// SRAM2 write protection key for software erase + KEY: u8, + padding: u24, + }), + /// SWPR + SWPR: mmio.Mmio(packed struct(u32) { + /// P0WP + P0WP: u1, + /// P1WP + P1WP: u1, + /// P2WP + P2WP: u1, + /// P3WP + P3WP: u1, + /// P4WP + P4WP: u1, + /// P5WP + P5WP: u1, + /// P6WP + P6WP: u1, + /// P7WP + P7WP: u1, + /// P8WP + P8WP: u1, + /// P9WP + P9WP: u1, + /// P10WP + P10WP: u1, + /// P11WP + P11WP: u1, + /// P12WP + P12WP: u1, + /// P13WP + P13WP: u1, + /// P14WP + P14WP: u1, + /// P15WP + P15WP: u1, + /// P16WP + P16WP: u1, + /// P17WP + P17WP: u1, + /// P18WP + P18WP: u1, + /// P19WP + P19WP: u1, + /// P20WP + P20WP: u1, + /// P21WP + P21WP: u1, + /// P22WP + P22WP: u1, + /// P23WP + P23WP: u1, + /// P24WP + P24WP: u1, + /// P25WP + P25WP: u1, + /// P26WP + P26WP: u1, + /// P27WP + P27WP: u1, + /// P28WP + P28WP: u1, + /// P29WP + P29WP: u1, + /// P30WP + P30WP: u1, + /// SRAM2 page 31 write protection + P31WP: u1, + }), + /// SWPR2 + SWPR2: mmio.Mmio(packed struct(u32) { + /// P32WP + P32WP: u1, + /// P33WP + P33WP: u1, + /// P34WP + P34WP: u1, + /// P35WP + P35WP: u1, + /// P36WP + P36WP: u1, + /// P37WP + P37WP: u1, + /// P38WP + P38WP: u1, + /// P39WP + P39WP: u1, + /// P40WP + P40WP: u1, + /// P41WP + P41WP: u1, + /// P42WP + P42WP: u1, + /// P43WP + P43WP: u1, + /// P44WP + P44WP: u1, + /// P45WP + P45WP: u1, + /// P46WP + P46WP: u1, + /// P47WP + P47WP: u1, + /// P48WP + P48WP: u1, + /// P49WP + P49WP: u1, + /// P50WP + P50WP: u1, + /// P51WP + P51WP: u1, + /// P52WP + P52WP: u1, + /// P53WP + P53WP: u1, + /// P54WP + P54WP: u1, + /// P55WP + P55WP: u1, + /// P56WP + P56WP: u1, + /// P57WP + P57WP: u1, + /// P58WP + P58WP: u1, + /// P59WP + P59WP: u1, + /// P60WP + P60WP: u1, + /// P61WP + P61WP: u1, + /// P62WP + P62WP: u1, + /// P63WP + P63WP: u1, + }), + reserved44: [4]u8, + /// RSSCMDR + RSSCMDR: mmio.Mmio(packed struct(u32) { + /// RSS commands + RSSCMD: u8, + padding: u24, }), }; + }; - /// Ethernet: media access control (MAC) - pub const ETHERNET_MAC = extern struct { - /// Ethernet MAC configuration register - MACCR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// Deferral check - DC: u1, - /// Back-off limit - BL: packed union { + pub const syscfg_u0 = struct { + pub const IR_MOD = enum(u2) { + /// TIM16 + TIM16 = 0x0, + /// USART1 + USART1 = 0x1, + /// USART2 + USART2 = 0x2, + _, + }; + + pub const MEM_MODE = enum(u2) { + /// System flash memory mapped at 0x000010000 + System_Flash = 0x1, + /// Embedded SRAM mapped at 0x000010000 + SRAM = 0x3, + _, + }; + + /// SYSCFG register block + pub const SYSCFG = extern struct { + /// SYSCFG configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection bits These bits are set and cleared by software. They control the memory internal mapping at address 0x000010000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section12.5: Boot configuration for more details. X0: Main flash memory mapped at 0x000010000 + MEM_MODE: packed union { raw: u2, - value: BL, - }, - /// Automatic pad/CRC stripping - APCS: packed union { - raw: u1, - value: APCS, - }, - reserved9: u1, - /// Retry disable - RD: packed union { - raw: u1, - value: RD, - }, - /// IPv4 checksum offload - IPCO: packed union { - raw: u1, - value: IPCO, - }, - /// Duplex mode - DM: packed union { - raw: u1, - value: DM, - }, - /// Loopback mode - LM: packed union { - raw: u1, - value: LM, - }, - /// Receive own disable - ROD: packed union { - raw: u1, - value: ROD, - }, - /// Fast Ethernet speed - FES: packed union { - raw: u1, - value: FES, - }, - reserved16: u1, - /// Carrier sense disable - CSD: packed union { - raw: u1, - value: CSD, - }, - /// Interframe gap - IFG: packed union { - raw: u3, - value: IFG, - }, - reserved22: u2, - /// Jabber disable - JD: packed union { - raw: u1, - value: JD, - }, - /// Watchdog disable - WD: packed union { - raw: u1, - value: WD, - }, - reserved25: u1, - /// CRC stripping for type frames - CSTF: u1, - padding: u6, - }), - /// Ethernet MAC frame filter register - MACFFR: mmio.Mmio(packed struct(u32) { - /// Promiscuous mode - PM: u1, - /// Hash unicast - HU: packed union { - raw: u1, - value: HU, - }, - /// Hash multicast - HM: packed union { - raw: u1, - value: HM, - }, - /// Destination address unique filtering - DAIF: packed union { - raw: u1, - value: DAIF, - }, - /// Pass all multicast - PAM: u1, - /// Broadcast frames disable - BFD: packed union { - raw: u1, - value: BFD, + value: MEM_MODE, }, - /// Pass control frames - PCF: packed union { + reserved3: u1, + /// PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. 0: No remap (PA11) 1: Remap (PA9) + PA11_RMP: u1, + /// PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. 0: No remap (PA12) 1: Remap (PA10) + PA12_RMP: u1, + /// IR output polarity selection + IR_POL: u1, + /// IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope: + IR_MOD: packed union { raw: u2, - value: PCF, - }, - /// Source address filter - SAF: u1, - /// Hash or perfect filter - HPF: packed union { - raw: u1, - value: HPF, + value: IR_MOD, }, - reserved31: u21, - /// Receive all - RA: u1, + /// I/O analog switch voltage booster enable This bit selects the way of supplying I/O analog switches: When using the analog inputs , setting to 0 is recommended for high VDD, setting to 1 for low VDD (less than 2.4 V). + BOOSTEN: u1, + reserved16: u7, + /// Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable + I2C_PB6_FMP: u1, + /// Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable + I2C_PB7_FMP: u1, + /// Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable + I2C_PB8_FMP: u1, + /// Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable + I2C_PB9_FMP: u1, + reserved22: u2, + /// Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable + I2C_PA9_FMP: u1, + /// Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable + I2C_PA10_FMP: u1, + /// Fast Mode Plus (FM+) enable for I2C3 This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers. With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C3 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable + I2C3_FMP: u1, + padding: u7, }), - /// Ethernet MAC hash table high register - MACHTHR: mmio.Mmio(packed struct(u32) { - /// Upper 32 bits of hash table - HTH: u32, + reserved24: [20]u8, + /// SYSCFG configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Cortex1-M0+ LOCKUP bit enable bit This bit is set by software and cleared by a system reset. It can be use to enable and lock the connection of Cortex1-M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input. + CCL: u1, + /// SRAM1 parity lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM1 parity error signal connection to TIM1/15/16 Break input. + SPL: u1, + /// PVD lock enable bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register. + PVDL: u1, + /// ECC error lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash ECC 2-bit error detection signal connection to TIM1/15/16 Break input. + ECCL: u1, + /// Backup SRAM2 parity lock This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break input. + BKPL: u1, + reserved7: u2, + /// Backup SRAM2 parity error flag This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1. + BKPF: u1, + /// SRAM1 parity error flag This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software by writing 1. + SPF: u1, + padding: u23, }), - /// Ethernet MAC hash table low register - MACHTLR: mmio.Mmio(packed struct(u32) { - /// Lower 32 bits of hash table - HTL: u32, + /// SYSCFG SRAM2 control and status register + SCSR: mmio.Mmio(packed struct(u32) { + /// SRAM2 erase Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation. Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register. + SRAM2ER: u1, + /// SRAM2 busy by erase operation + SRAM2BSY: u1, + padding: u30, }), - /// Ethernet MAC MII address register - MACMIIAR: mmio.Mmio(packed struct(u32) { - /// MII busy - MB: packed union { - raw: u1, - value: MB_progress, - }, - /// MII write - MW: packed union { - raw: u1, - value: MW, - }, - /// Clock range - CR: packed union { - raw: u3, - value: CR, - }, - reserved6: u1, - /// MII register - select the desired MII register in the PHY device - MR: u5, - /// PHY address - select which of possible 32 PHYs is being accessed - PA: u5, - padding: u16, + /// SYSCFG SRAM2 key register + SKR: mmio.Mmio(packed struct(u32) { + /// SRAM2 write protection key for software erase The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register: Write 0xCA into KEY[7:0] Write 0x53 into KEY[7:0] Writing a wrong key reactivates the write protection. + KEY: u8, + padding: u24, }), - /// Ethernet MAC MII data register - MACMIIDR: mmio.Mmio(packed struct(u32) { - /// MII data read from/written to the PHY - MD: u16, - padding: u16, + /// SYSCFG TSC comparator register + TSCCR: mmio.Mmio(packed struct(u32) { + /// Comparator mode for group 2 on I/O 1 + G2_IO1: u1, + /// Comparator mode for group 2 on I/O 3 + G2_IO3: u1, + /// Comparator mode for group 4 on I/O 3 + G4_IO3: u1, + /// Comparator mode for group 6 on I/O 1 + G6_IO1: u1, + /// Comparator mode for group 7 on I/O 1 + G7_IO1: u1, + /// I/O control in comparator mode The I/O control in comparator mode can be overwritten by hardware. + TSC_IOCTRL: u1, + padding: u26, }), - /// Ethernet MAC flow control register - MACFCR: mmio.Mmio(packed struct(u32) { - /// Flow control busy/back pressure activate - FCB: packed union { - raw: u1, - value: FCB, - }, - /// Transmit flow control enable - TFCE: u1, - /// Receive flow control enable - RFCE: u1, - /// Unicast pause frame detect - UPFD: u1, - /// Pause low threshold - PLT: packed union { - raw: u2, - value: PLT, - }, - reserved7: u1, - /// Zero-quanta pause disable - ZQPD: packed union { - raw: u1, - value: ZQPD, - }, - reserved16: u8, - /// Pause time - PT: u16, + reserved128: [88]u8, + /// SYSCFG interrupt line 0 status register + ITLINE0: mmio.Mmio(packed struct(u32) { + /// Window watchdog interrupt pending flag + WWDG: u1, + padding: u31, }), - /// Ethernet MAC VLAN tag register - MACVLANTR: mmio.Mmio(packed struct(u32) { - /// VLAN tag identifier (for receive frames) - VLANTI: u16, - /// 12-bit VLAN tag comparison - VLANTC: packed union { - raw: u1, - value: VLANTC, - }, - padding: u15, + /// SYSCFG interrupt line 1 status register + ITLINE1: mmio.Mmio(packed struct(u32) { + /// PVD supply monitoring interrupt request pending (EXTI line 16). + PVDOUT: u1, + /// VDDUSB supply monitoring interrupt request pending (EXTI line 19) + PVMOUT1: u1, + /// ADC supply monitoring interrupt request pending (EXTI line 20) + PVMOUT3: u1, + /// DAC supply monitoring interrupt request pending (EXTI line 21) + PVMOUT4: u1, + padding: u28, }), - reserved40: [8]u8, - /// Ethernet MAC remote wakeup frame filter register - MACRWUFFR: u32, - /// Ethernet MAC PMT control and status register - MACPMTCSR: mmio.Mmio(packed struct(u32) { - /// Power down - PD: packed union { - raw: u1, - value: PD, - }, - /// Magic packet enable - MPE: u1, - /// Wakeup frame enable - WFE: u1, - reserved5: u2, - /// Magic packet received - MPR: u1, - /// Wakeup frame received - WFR: u1, - reserved9: u2, - /// Global unicast - GU: u1, - reserved31: u21, - /// Wakeup frame filter register pointer reset - WFFRPR: packed union { - raw: u1, - value: WFFRPR, - }, + /// SYSCFG interrupt line 2 status register + ITLINE2: mmio.Mmio(packed struct(u32) { + /// Tamper interrupt request pending (EXTI line 21) + TAMP: u1, + /// RTC interrupt request pending (EXTI line 19) + RTC: u1, + padding: u30, }), - reserved52: [4]u8, - /// Ethernet MAC debug register - MACDBGR: mmio.Mmio(packed struct(u32) { - /// MAC MII receive protocol engine active - MMRPEA: u1, - /// MAC small FIFO read/write controllers status - MSFRWCS: u2, - reserved4: u1, - /// Rx FIFO write controller active - RFWRA: u1, - /// Rx FIFO read controller status - RFRCS: u2, - reserved8: u1, - /// Rx FIFO fill level - RFFL: u2, - reserved16: u6, - /// MAC MII transmit engine active - MMTEA: u1, - /// MAC transmit frame controller status - MTFCS: u2, - /// MAC transmitter in pause - MTP: u1, - /// Tx FIFO read status - TFRS: u2, - /// Tx FIFO write active - TFWA: u1, - reserved24: u1, - /// Tx FIFO not empty - TFNE: u1, - /// Tx FIFO full - TFF: u1, - padding: u6, + /// SYSCFG interrupt line 3 status register + ITLINE3: mmio.Mmio(packed struct(u32) { + /// Flash interface interrupt request pending + FLASH_ITF: u1, + /// Flash interface ECC interrupt request pending + FLASH_ECC: u1, + padding: u30, }), - /// Ethernet MAC interrupt status register - MACSR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// PMT status - PMTS: u1, - /// MMC status - MMCS: u1, - /// MMC receive status - MMCRS: u1, - /// MMC transmit status - MMCTS: u1, - reserved9: u2, - /// Time stamp trigger status - TSTS: u1, - padding: u22, + /// SYSCFG interrupt line 4 status register + ITLINE4: mmio.Mmio(packed struct(u32) { + /// Reset and clock control interrupt request pending + RCC: u1, + /// CRS interrupt request pending + CRS: u1, + padding: u30, }), - /// Ethernet MAC interrupt mask register - MACIMR: mmio.Mmio(packed struct(u32) { - reserved3: u3, - /// PMT interrupt mask - PMTIM: packed union { - raw: u1, - value: PMTIM, - }, - reserved9: u5, - /// Time stamp trigger interrupt mask - TSTIM: packed union { - raw: u1, - value: TSTIM, - }, - padding: u22, + /// SYSCFG interrupt line 5 status register + ITLINE5: mmio.Mmio(packed struct(u32) { + /// EXTI line 0 interrupt request pending + EXTI0: u1, + /// EXTI line 1 interrupt request pending + EXTI1: u1, + padding: u30, }), - /// Ethernet MAC address 0 high register - MACA0HR: mmio.Mmio(packed struct(u32) { - /// Ethernet MAC address 0 high - MACA0H: u16, - reserved31: u15, - /// Always 1 - MO: u1, + /// SYSCFG interrupt line 6 status register + ITLINE6: mmio.Mmio(packed struct(u32) { + /// EXTI line 2 interrupt request pending + EXTI2: u1, + /// EXTI line 3 interrupt request pending + EXTI3: u1, + padding: u30, }), - /// Ethernet MAC address 0 low register - MACA0LR: mmio.Mmio(packed struct(u32) { - /// Ethernet MAC address 0 low - MACA0L: u32, + /// SYSCFG interrupt line 7 status register + ITLINE7: mmio.Mmio(packed struct(u32) { + /// EXTI line 4 interrupt request pending + EXTI4: u1, + /// EXTI line 5 interrupt request pending + EXTI5: u1, + /// EXTI line 6 interrupt request pending + EXTI6: u1, + /// EXTI line 7 interrupt request pending + EXTI7: u1, + /// EXTI line 8 interrupt request pending + EXTI8: u1, + /// EXTI line 9 interrupt request pending + EXTI9: u1, + /// EXTI line 10 interrupt request pending + EXTI10: u1, + /// EXTI line 11 interrupt request pending + EXTI11: u1, + /// EXTI line 12 interrupt request pending + EXTI12: u1, + /// EXTI line 13 interrupt request pending + EXTI13: u1, + /// EXTI line 14 interrupt request pending + EXTI14: u1, + /// EXTI line 15 interrupt request pending + EXTI15: u1, + padding: u20, }), - /// Ethernet MAC address 1/2/3 high register - MACAHR: mmio.Mmio(packed struct(u32) { - /// Ethernet MAC address 1/2/3 high - MACAH: u16, - reserved24: u8, - /// MBC - MBC: u6, - /// SA - SA: packed union { - raw: u1, - value: MACAHR_SA, - }, - /// AE - AE: u1, + /// SYSCFG interrupt line 8 status register + ITLINE8: mmio.Mmio(packed struct(u32) { + /// USB interrupt request pending + USB: u1, + padding: u31, }), - /// Ethernet MAC address 1/2/3 low register - MACALR: mmio.Mmio(packed struct(u32) { - /// thernet MAC address 1/2/3 low - MACAL: u32, + /// SYSCFG interrupt line 9 status register + ITLINE9: mmio.Mmio(packed struct(u32) { + /// DMA1 channel 1 interrupt request pending + DMA1_CH1: u1, + padding: u31, }), - reserved256: [176]u8, - /// Ethernet MMC control register - MMCCR: mmio.Mmio(packed struct(u32) { - /// Counter reset - CR: packed union { - raw: u1, - value: CounterReset, - }, - /// Counter stop rollover - CSR: packed union { - raw: u1, - value: CSR, - }, - /// Reset on read - ROR: u1, - /// MMC counter freeze - MCF: u1, - /// MMC counter preset - MCP: packed union { - raw: u1, - value: MCP, - }, - /// MMC counter Full-Half preset - MCFHP: packed union { - raw: u1, - value: MCFHP, - }, - padding: u26, + /// SYSCFG interrupt line 10 status register + ITLINE10: mmio.Mmio(packed struct(u32) { + /// DMA1 channel 2 interrupt request pending + DMA1_CH2: u1, + /// DMA1 channel 3 interrupt request pending + DMA1_CH3: u1, + padding: u30, }), - /// Ethernet MMC receive interrupt register - MMCRIR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// Received frames CRC error status - RFCES: u1, - /// Received frames alignment error status - RFAES: u1, - reserved17: u10, - /// Received good Unicast frames status - RGUFS: u1, - padding: u14, + /// SYSCFG interrupt line 11 status register + ITLINE11: mmio.Mmio(packed struct(u32) { + /// DMAMUX interrupt request pending + DMAMUX: u1, + /// DMA1 channel 4 interrupt request pending + DMA1_CH4: u1, + /// DMA1 channel 5 interrupt request pending + DMA1_CH5: u1, + /// DMA1 channel 6 interrupt request pending + DMA1_CH6: u1, + /// DMA1 channel 7 interrupt request pending + DMA1_CH7: u1, + /// DMA2 channel 1 interrupt request pending + DMA2_CH1: u1, + /// DMA2 channel 2 interrupt request pending + DMA2_CH2: u1, + /// DMA2 channel 3 interrupt request pending + DMA2_CH3: u1, + /// DMA2 channel 4 interrupt request pending + DMA2_CH4: u1, + /// DMA2 channel 5 interrupt request pending + DMA2_CH5: u1, + padding: u22, }), - /// Ethernet MMC transmit interrupt register - MMCTIR: mmio.Mmio(packed struct(u32) { - reserved14: u14, - /// Transmitted good frames single collision status - TGFSCS: u1, - /// Transmitted good frames more than single collision status - TGFMSCS: u1, - reserved21: u5, - /// Transmitted good frames status - TGFS: u1, - padding: u10, + /// SYSCFG interrupt line 12 status register + ITLINE12: mmio.Mmio(packed struct(u32) { + /// ADC interrupt request pending + ADC: u1, + /// Comparator 1 interrupt request pending (EXTI line 17) + COMP1: u1, + /// Comparator 2 interrupt request pending (EXTI line 18) + COMP2: u1, + padding: u29, }), - /// Ethernet MMC receive interrupt mask register - MMCRIMR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// Received frame CRC error mask - RFCEM: packed union { - raw: u1, - value: RFCEM, - }, - /// Received frames alignment error mask - RFAEM: packed union { - raw: u1, - value: RFAEM, - }, - reserved17: u10, - /// Received good Unicast frames mask - RGUFM: packed union { - raw: u1, - value: RGUFM, - }, - padding: u14, + /// SYSCFG interrupt line 13 status register + ITLINE13: mmio.Mmio(packed struct(u32) { + /// Timer 1 commutation interrupt request pending + TIM1_CCU: u1, + /// Timer 1 trigger interrupt request pending + TIM1_TRG: u1, + /// Timer 1 update interrupt request pending + TIM1_UPD: u1, + /// Timer 1 break interrupt request pending + TIM1_BRK: u1, + padding: u28, }), - /// Ethernet MMC transmit interrupt mask register - MMCTIMR: mmio.Mmio(packed struct(u32) { - reserved14: u14, - /// Transmitted good frames single collision mask - TGFSCM: packed union { - raw: u1, - value: TGFSCM, - }, - /// Transmitted good frames more than single collision mask - TGFMSCM: packed union { - raw: u1, - value: TGFMSCM, - }, - /// Transmitted good frames mask - TGFM: packed union { - raw: u1, - value: TGFM, - }, - padding: u15, + /// SYSCFG interrupt line 14 status register + ITLINE14: mmio.Mmio(packed struct(u32) { + /// Timer 1 capture compare 1 interrupt request pending + TIM1_CC1: u1, + /// Timer 1 capture compare 2 interrupt request pending + TIM1_CC2: u1, + /// Timer 1 capture compare 3 interrupt request pending + TIM1_CC3: u1, + /// Timer 1 capture compare 4 interrupt request pending + TIM1_CC4: u1, + padding: u28, }), - reserved332: [56]u8, - /// Ethernet MMC transmitted good frames after a single collision counter - MMCTGFSCCR: mmio.Mmio(packed struct(u32) { - /// Transmitted good frames single collision counter - TGFSCC: u32, + /// SYSCFG interrupt line 15 status register + ITLINE15: mmio.Mmio(packed struct(u32) { + /// Timer 2 interrupt request pending + TIM2: u1, + padding: u31, }), - /// Ethernet MMC transmitted good frames after more than a single collision - MMCTGFMSCCR: mmio.Mmio(packed struct(u32) { - /// TGFMSCC - TGFMSCC: u32, + /// SYSCFG interrupt line 16 status register + ITLINE16: mmio.Mmio(packed struct(u32) { + /// Timer 3 interrupt request pending + TIM3: u1, + padding: u31, }), - reserved360: [20]u8, - /// Ethernet MMC transmitted good frames counter register - MMCTGFCR: mmio.Mmio(packed struct(u32) { - /// HTL - TGFC: u32, + /// SYSCFG interrupt line 17 status register + ITLINE17: mmio.Mmio(packed struct(u32) { + /// Timer 6 interrupt request pending + TIM6: u1, + /// DAC underrun interrupt request pending + DAC: u1, + /// Low-power timer 1 interrupt request pending (EXTI line 29) + LPTIM1: u1, + padding: u29, }), - reserved404: [40]u8, - /// Ethernet MMC received frames with CRC error counter register - MMCRFCECR: mmio.Mmio(packed struct(u32) { - /// RFCFC - RFCFC: u32, + /// SYSCFG interrupt line 18 status register + ITLINE18: mmio.Mmio(packed struct(u32) { + /// Timer 7 interrupt request pending + TIM7: u1, + /// Low-power timer 2 interrupt request pending (EXTI line 30) + LPTIM2: u1, + padding: u30, }), - /// Ethernet MMC received frames with alignment error counter register - MMCRFAECR: mmio.Mmio(packed struct(u32) { - /// RFAEC - RFAEC: u32, + /// SYSCFG interrupt line 19 status register + ITLINE19: mmio.Mmio(packed struct(u32) { + /// Timer 15 interrupt request pending + TIM15: u1, + /// Low-power timer 3 interrupt request pending + LPTIM3: u1, + padding: u30, }), - reserved452: [40]u8, - /// MMC received good unicast frames counter register - MMCRGUFCR: mmio.Mmio(packed struct(u32) { - /// RGUFC - RGUFC: u32, + /// SYSCFG interrupt line 20 status register + ITLINE20: mmio.Mmio(packed struct(u32) { + /// Timer 16 interrupt request pending + TIM16: u1, + padding: u31, }), - }; - - /// Ethernet: Precision time protocol - pub const ETHERNET_PTP = extern struct { - /// Ethernet PTP time stamp control register - PTPTSCR: mmio.Mmio(packed struct(u32) { - /// TSE - TSE: u1, - /// TSFCU - TSFCU: u1, - /// TSSTI - TSSTI: u1, - /// TSSTU - TSSTU: u1, - /// TSITE - TSITE: u1, - /// TTSARU - TTSARU: u1, - reserved8: u2, - /// TSSARFE - TSSARFE: u1, - /// TSSSR - TSSSR: u1, - /// TSPTPPSV2E - TSPTPPSV2E: u1, - /// TSSPTPOEFE - TSSPTPOEFE: u1, - /// TSSIPV6FE - TSSIPV6FE: u1, - /// TSSIPV4FE - TSSIPV4FE: u1, - /// TSSEME - TSSEME: u1, - /// TSSMRME - TSSMRME: u1, - /// TSCNT - TSCNT: u2, - /// TSPFFMAE - TSPFFMAE: u1, - padding: u13, + /// SYSCFG interrupt line 21 status register + ITLINE21: mmio.Mmio(packed struct(u32) { + /// TSC max count error interrupt request pending + TSC_MCE: u1, + /// TSC end of acquisition interrupt request pending + TSC_EOA: u1, + padding: u30, }), - /// Ethernet PTP subsecond increment register - PTPSSIR: mmio.Mmio(packed struct(u32) { - /// STSSI - STSSI: u8, - padding: u24, + /// SYSCFG interrupt line 22 status register + ITLINE22: mmio.Mmio(packed struct(u32) { + /// LCD interrupt request pending + LCD: u1, + padding: u31, }), - /// Ethernet PTP time stamp high register - PTPTSHR: mmio.Mmio(packed struct(u32) { - /// STS - STS: u32, + /// SYSCFG interrupt line 23 status register + ITLINE23: mmio.Mmio(packed struct(u32) { + /// I2C1 interrupt request pending (EXTI line 33) + I2C1: u1, + padding: u31, }), - /// Ethernet PTP time stamp low register - PTPTSLR: mmio.Mmio(packed struct(u32) { - /// STSS - STSS: u31, - /// STPNS - STPNS: u1, + /// SYSCFG interrupt line 24 status register + ITLINE24: mmio.Mmio(packed struct(u32) { + /// I2C2 interrupt request pending + I2C2: u1, + /// I2C4 interrupt request pending + I2C4: u1, + /// I2C3 interrupt request pending (EXTI line 23) + I2C3: u1, + padding: u29, }), - /// Ethernet PTP time stamp high update register - PTPTSHUR: mmio.Mmio(packed struct(u32) { - /// TSUS - TSUS: u32, + /// SYSCFG interrupt line 25 status register + ITLINE25: mmio.Mmio(packed struct(u32) { + /// SPI1 interrupt request pending + SPI1: u1, + padding: u31, }), - /// Ethernet PTP time stamp low update register - PTPTSLUR: mmio.Mmio(packed struct(u32) { - /// TSUSS - TSUSS: u31, - /// TSUPNS - TSUPNS: u1, + /// SYSCFG interrupt line 26 status register + ITLINE26: mmio.Mmio(packed struct(u32) { + /// SPI2 interrupt request pending + SPI2: u1, + /// SPI3 interrupt request pending + SPI3: u1, + padding: u30, }), - /// Ethernet PTP time stamp addend register - PTPTSAR: mmio.Mmio(packed struct(u32) { - /// TSA - TSA: u32, + /// SYSCFG interrupt line 27 status register + ITLINE27: mmio.Mmio(packed struct(u32) { + /// USART1 interrupt request pending, combined with EXTI line 25 + USART1: u1, + padding: u31, }), - /// Ethernet PTP target time high register - PTPTTHR: mmio.Mmio(packed struct(u32) { - /// 0 - TTSH: u32, + /// SYSCFG interrupt line 28 status register + ITLINE28: mmio.Mmio(packed struct(u32) { + /// USART2 interrupt request pending (EXTI line 35) + USART2: u1, + /// LPUART2 interrupt request pending (EXTI line 31) + LPUART2: u1, + padding: u30, }), - /// Ethernet PTP target time low register - PTPTTLR: mmio.Mmio(packed struct(u32) { - /// TTSL - TTSL: u32, + /// SYSCFG interrupt line 29 status register + ITLINE29: mmio.Mmio(packed struct(u32) { + /// USART3 interrupt request pending + USART3: u1, + /// LPUART1 interrupt request pending (EXTI line 30) + LPUART1: u1, + padding: u30, }), - reserved40: [4]u8, - /// Ethernet PTP time stamp status register - PTPTSSR: mmio.Mmio(packed struct(u32) { - /// TSSO - TSSO: u1, - /// TSSO - TSTTR: u1, + /// SYSCFG interrupt line 30 status register + ITLINE30: mmio.Mmio(packed struct(u32) { + /// USART4 interrupt request pending + USART4: u1, + /// LPUART3 interrupt request pending (EXTI line 32) + LPUART3: u1, padding: u30, }), - /// Ethernet PTP PPS control register - PTPPPSCR: mmio.Mmio(packed struct(u32) { - /// TSSO - TSSO: u1, - /// TSTTR - TSTTR: u1, + /// SYSCFG interrupt line 31 status register + ITLINE31: mmio.Mmio(packed struct(u32) { + /// RNG interrupt request pending + RNG: u1, + /// AES interrupt request pending + AES: u1, padding: u30, }), }; }; - pub const aes_v3a = struct { - pub const CHMOD = enum(u3) { - /// Electronic codebook - ECB = 0x0, - /// Cipher-block chaining - CBC = 0x1, - /// Counter mode - CTR = 0x2, - /// Galois counter mode and Galois message authentication code - GCM_GMAC = 0x3, - /// Counter with CBC-MAC - CCM = 0x4, - _, - }; - - pub const DATATYPE = enum(u2) { - /// Word - None = 0x0, - /// Half-word (16-bit) - HalfWord = 0x1, - /// Byte (8-bit) - Byte = 0x2, - /// Bit - Bit = 0x3, - }; - - pub const GCMPH = enum(u2) { - /// Init phase - @"Init phase" = 0x0, - /// Header phase - @"Header phase" = 0x1, - /// Payload phase - @"Payload phase" = 0x2, - /// Final phase - @"Final phase" = 0x3, - }; - - pub const MODE = enum(u2) { - /// Encryption - Mode1 = 0x0, - /// Key derivation (or key preparation for ECB/CBC decryption) - Mode2 = 0x1, - /// Decryption - Mode3 = 0x2, - _, - }; - - /// Advanced encryption standard hardware accelerator - pub const AES = extern struct { - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// AES enable - EN: u1, - /// Data type selection - DATATYPE: packed union { - raw: u2, - value: DATATYPE, - }, - /// Operating mode - MODE: packed union { - raw: u2, - value: MODE, - }, - padding: u27, + pub const syscfg_u5 = struct { + /// System configuration controller + pub const SYSCFG = extern struct { + /// SYSCFG secure configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock control security + SYSCFGSEC: u1, + /// CLASSBSEC + CLASSBSEC: u1, + reserved3: u1, + /// FPUSEC + FPUSEC: u1, + padding: u28, }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Computation complete flag - CCF: u1, - /// Read error flag - RDERR: u1, - /// Write error flag - WRERR: u1, - /// Busy flag - BUSY: u1, - reserved7: u3, - /// Key valid flag - KEYVALID: u1, - padding: u24, + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// I/O analog switch voltage booster enable + BOOSTEN: u1, + /// GPIO analog switch control voltage selection + ANASWVDD: u1, + reserved16: u6, + /// PB6_FMP + PB6_FMP: u1, + /// PB7_FMP + PB7_FMP: u1, + /// PB8_FMP + PB8_FMP: u1, + /// PB9_FMP + PB9_FMP: u1, + padding: u12, }), - /// Data input register - DINR: u32, - /// Data output register - DOUTR: u32, - /// Key register - KEYR: u32, - reserved32: [12]u8, - /// Initialization vector register - IVR: [4]u32, - reserved64: [16]u8, - /// Suspend register - SUSPR: [8]u32, - reserved768: [672]u8, - /// interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// Computation complete flag interrupt enable - CCFIE: u1, - /// Read or write error interrupt enable - RWEIE: u1, - /// Key error interrupt enable - KEIE: u1, - padding: u29, + /// FPU interrupt mask register + FPUIMR: mmio.Mmio(packed struct(u32) { + /// Floating point unit interrupts enable bits + FPU_IE: u6, + padding: u26, }), - /// interrupt status register - ISR: mmio.Mmio(packed struct(u32) { - /// Computation complete flag - CCF: u1, - /// Read or write error interrupt flag - RWEIF: u1, - /// Key error interrupt flag - KEIF: u1, - padding: u29, + /// SYSCFG CPU non-secure lock register + CNSLCKR: mmio.Mmio(packed struct(u32) { + /// VTOR_NS register lock + LOCKNSVTOR: u1, + /// Non-secure MPU registers lock + LOCKNSMPU: u1, + padding: u30, }), - /// interrupt clear register - ICR: mmio.Mmio(packed struct(u32) { - /// Computation complete flag clear - CCF: u1, - /// Read or write error interrupt flag clear - RWEIF: u1, - /// Key error interrupt flag clear - KEIF: u1, + /// SYSCFG CPU secure lock register + CSLOCKR: mmio.Mmio(packed struct(u32) { + /// LOCKSVTAIRCR + LOCKSVTAIRCR: u1, + /// LOCKSMPU + LOCKSMPU: u1, + /// LOCKSAU + LOCKSAU: u1, padding: u29, }), + /// configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// LOCKUP (hardfault) output enable bit + CLL: u1, + /// SRAM ECC lock bit + SPL: u1, + /// PVD lock enable bit + PVDL: u1, + /// ECC Lock + ECCL: u1, + padding: u28, + }), + /// memory erase status register + MESR: mmio.Mmio(packed struct(u32) { + /// MCLR + MCLR: u1, + reserved16: u15, + /// IPMEE + IPMEE: u1, + padding: u15, + }), + /// compensation cell control/status register + CCCSR: mmio.Mmio(packed struct(u32) { + /// EN1 + EN1: u1, + /// CS1 + CS1: u1, + /// EN2 + EN2: u1, + /// CS2 + CS2: u1, + reserved8: u4, + /// RDY1 + RDY1: u1, + /// RDY2 + RDY2: u1, + padding: u22, + }), + /// compensation cell value register + CCVR: mmio.Mmio(packed struct(u32) { + /// NCV1 + NCV1: u4, + /// PCV1 + PCV1: u4, + /// NCV2 + NCV2: u4, + /// PCV2 + PCV2: u4, + padding: u16, + }), + /// compensation cell code register + CCCR: mmio.Mmio(packed struct(u32) { + /// NCC1 + NCC1: u4, + /// PCC1 + PCC1: u4, + /// NCC2 + NCC2: u4, + /// PCC2 + PCC2: u4, + padding: u16, + }), + reserved44: [4]u8, + /// RSS command register + RSSCMDR: mmio.Mmio(packed struct(u32) { + /// RSS commands + RSSCMD: u16, + padding: u16, + }), + reserved112: [64]u8, + /// USB Type C and Power Delivery register + UCPDR: mmio.Mmio(packed struct(u32) { + /// CC1ENRXFILTER + CC1ENRXFILTER: u1, + /// CC2ENRXFILTER + CC2ENRXFILTER: u1, + padding: u30, + }), }; }; - pub const flash_h7 = struct { - /// Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R - pub const BANK = extern struct { - /// FLASH key register for bank 1 - KEYR: u32, - reserved8: [4]u8, - /// FLASH control register for bank 1 - CR: mmio.Mmio(packed struct(u32) { - /// Bank 1 configuration lock bit - LOCK: u1, - /// Bank 1 program enable bit - PG: u1, - /// Bank 1 sector erase request - SER: u1, - /// Bank 1 erase request - BER: u1, - /// Bank 1 program size - PSIZE: u2, - /// Bank 1 write forcing control bit - FW: u1, - /// Bank 1 bank or sector erase start control bit - START: u1, - /// Bank 1 sector erase selection number - SNB: u3, - reserved15: u4, - /// Bank 1 CRC control bit - CRC_EN: u1, - /// Bank 1 end-of-program interrupt control bit - EOPIE: u1, - /// Bank 1 write protection error interrupt enable bit - WRPERRIE: u1, - /// Bank 1 programming sequence error interrupt enable bit - PGSERRIE: u1, - /// Bank 1 strobe error interrupt enable bit - STRBERRIE: u1, - reserved21: u1, - /// Bank 1 inconsistency error interrupt enable bit - INCERRIE: u1, - /// Bank 1 write/erase error interrupt enable bit - OPERRIE: u1, - /// Bank 1 read protection error interrupt enable bit - RDPERRIE: u1, - /// Bank 1 secure error interrupt enable bit - RDSERRIE: u1, - /// Bank 1 ECC single correction error interrupt enable bit - SNECCERRIE: u1, - /// Bank 1 ECC double detection error interrupt enable bit - DBECCERRIE: u1, - /// Bank 1 end of CRC calculation interrupt enable bit - CRCENDIE: u1, - /// Bank 1 CRC read error interrupt enable bit - CRCRDERRIE: u1, - padding: u3, - }), - /// FLASH status register for bank 1 - SR: mmio.Mmio(packed struct(u32) { - /// Bank 1 ongoing program flag - BSY: u1, - /// Bank 1 write buffer not empty flag - WBNE: u1, - /// Bank 1 wait queue flag - QW: u1, - /// Bank 1 CRC busy flag - CRC_BUSY: u1, - reserved16: u12, - /// Bank 1 end-of-program flag - EOP: u1, - /// Bank 1 write protection error flag - WRPERR: u1, - /// Bank 1 programming sequence error flag - PGSERR: u1, - /// Bank 1 strobe error flag - STRBERR: u1, - reserved21: u1, - /// Bank 1 inconsistency error flag - INCERR: u1, - /// Bank 1 write/erase error flag - OPERR: u1, - /// Bank 1 read protection error flag - RDPERR: u1, - /// Bank 1 secure error flag - RDSERR: u1, - /// Bank 1 single correction error flag - SNECCERR1: u1, - /// Bank 1 ECC double detection error flag - DBECCERR: u1, - /// Bank 1 CRC-complete flag - CRCEND: u1, - /// Bank 1 CRC read error flag - CRCRDERR: u1, - padding: u3, + pub const syscfg_wb = struct { + /// System configuration controller + pub const SYSCFG = extern struct { + /// memory remap register + MEMRMP: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection + MEM_MODE: u3, + padding: u29, }), - /// FLASH clear control register for bank 1 - CCR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Bank 1 EOP1 flag clear bit - CLR_EOP: u1, - /// Bank 1 WRPERR1 flag clear bit - CLR_WRPERR: u1, - /// Bank 1 PGSERR1 flag clear bi - CLR_PGSERR: u1, - /// Bank 1 STRBERR1 flag clear bit - CLR_STRBERR: u1, - reserved21: u1, - /// Bank 1 INCERR1 flag clear bit - CLR_INCERR: u1, - /// Bank 1 OPERR1 flag clear bit - CLR_OPERR: u1, - /// Bank 1 RDPERR1 flag clear bit - CLR_RDPERR: u1, - /// Bank 1 RDSERR1 flag clear bit - CLR_RDSERR: u1, - /// Bank 1 SNECCERR1 flag clear bit - CLR_SNECCERR: u1, - /// Bank 1 DBECCERR1 flag clear bit - CLR_DBECCERR: u1, - /// Bank 1 CRCEND1 flag clear bit - CLR_CRCEND: u1, - /// Bank 1 CRC read error clear bit - CLR_CRCRDERR: u1, - padding: u3, + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// I/O analog switch voltage booster enable + BOOSTEN: u1, + reserved16: u7, + /// Fast-mode Plus (Fm+) driving capability activation on PB6 + I2C_PB6_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB7 + I2C_PB7_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB8 + I2C_PB8_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB9 + I2C_PB9_FMP: u1, + /// I2C1 Fast-mode Plus driving capability activation + I2C1_FMP: u1, + reserved22: u1, + /// I2C3 Fast-mode Plus driving capability activation + I2C3_FMP: u1, + reserved26: u3, + /// Floating Point Unit interrupts enable bits + FPU_IE: u6, }), - reserved36: [16]u8, - /// FLASH protection address for bank 1 - PRAR_CUR: mmio.Mmio(packed struct(u32) { - /// Bank 1 lowest PCROP protected address - PROT_AREA_START: u12, - reserved16: u4, - /// Bank 1 highest PCROP protected address - PROT_AREA_END: u12, - reserved31: u3, - /// Bank 1 PCROP protected erase enable option status bit - DMEP: u1, + /// external interrupt configuration register 1 + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI 0 configuration bits + EXTI: u3, + padding: u29, }), - /// FLASH protection address for bank 1 - PRAR_PRG: mmio.Mmio(packed struct(u32) { - /// Bank 1 lowest PCROP protected address configuration - PROT_AREA_START: u12, - reserved16: u4, - /// Bank 1 highest PCROP protected address configuration - PROT_AREA_END: u12, - reserved31: u3, - /// Bank 1 PCROP protected erase enable option configuration bit - DMEP: u1, + /// SCSR + SCSR: mmio.Mmio(packed struct(u32) { + /// SRAM2 Erase + SRAM2ER: u1, + /// SRAM2 busy by erase operation + SRAM2BSY: u1, + reserved31: u29, + /// CPU2 SRAM fetch (execution) disable. + C2RFD: u1, }), - /// FLASH secure address for bank 1 - SCAR_CUR: mmio.Mmio(packed struct(u32) { - /// Bank 1 lowest secure protected address - SEC_AREA_START: u12, - reserved16: u4, - /// Bank 1 highest secure protected address - SEC_AREA_END: u12, - reserved31: u3, - /// Bank 1 secure protected erase enable option status bit - DMES: u1, + /// CFGR2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Cortex-M4 LOCKUP (Hardfault) output enable bit + CLL: u1, + /// SRAM2 parity lock bit + SPL: u1, + /// PVD lock enable bit + PVDL: u1, + /// ECC Lock + ECCL: u1, + reserved8: u4, + /// SRAM2 parity error flag + SPF: u1, + padding: u23, }), - /// FLASH secure address for bank 1 - SCAR_PRG: mmio.Mmio(packed struct(u32) { - /// Bank 1 lowest secure protected address configuration - SEC_AREA_START: u12, - reserved16: u4, - /// Bank 1 highest secure protected address configuration - SEC_AREA_END: u12, - reserved31: u3, - /// Bank 1 secure protected erase enable option configuration bit - DMES: u1, + /// SRAM2 write protection register + SWPR: mmio.Mmio(packed struct(u32) { + /// P0WP + PWP: u1, + padding: u31, }), - /// FLASH write sector protection for bank 1 - WPSN_CURR: mmio.Mmio(packed struct(u32) { - /// Bank 1 sector write protection option status byte - WRPSn: u8, + /// SKR + SKR: mmio.Mmio(packed struct(u32) { + /// SRAM2 write protection key for software erase + KEY: u8, padding: u24, }), - /// FLASH write sector protection for bank 1 - WPSN_PRGR: mmio.Mmio(packed struct(u32) { - /// Bank 1 sector write protection configuration byte - WRPSn: u8, - padding: u24, + /// SRAM2 write protection register 2 + SWPR2: mmio.Mmio(packed struct(u32) { + /// P32WP + PWP: u1, + padding: u31, }), - reserved76: [16]u8, - /// FLASH CRC control register for bank 1 - CRCCR: mmio.Mmio(packed struct(u32) { - /// Bank 1 CRC sector number - CRC_SECT: u3, - reserved7: u4, - /// Bank 1 CRC select bit - ALL_BANK: u1, - /// Bank 1 CRC sector mode select bit - CRC_BY_SECT: u1, - /// Bank 1 CRC sector select bit - ADD_SECT: u1, - /// Bank 1 CRC sector list clear bit - CLEAN_SECT: u1, - reserved16: u5, - /// Bank 1 CRC start bit - START_CRC: u1, - /// Bank 1 CRC clear bit - CLEAN_CRC: u1, - reserved20: u2, - /// Bank 1 CRC burst size - CRC_BURST: u2, - padding: u10, + reserved256: [212]u8, + /// CPU1 interrupt mask register 1 + IMR1: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// Peripheral TIM1 interrupt mask to CPU1 + TIM1IM: u1, + /// Peripheral TIM16 interrupt mask to CPU1 + TIM16IM: u1, + /// Peripheral TIM17 interrupt mask to CPU1 + TIM17IM: u1, + reserved21: u5, + /// Peripheral EXIT5 interrupt mask to CPU1 + EXIT5IM: u1, + /// Peripheral EXIT6 interrupt mask to CPU1 + EXIT6IM: u1, + /// Peripheral EXIT7 interrupt mask to CPU1 + EXIT7IM: u1, + /// Peripheral EXIT8 interrupt mask to CPU1 + EXIT8IM: u1, + /// Peripheral EXIT9 interrupt mask to CPU1 + EXIT9IM: u1, + /// Peripheral EXIT10 interrupt mask to CPU1 + EXIT10IM: u1, + /// Peripheral EXIT11 interrupt mask to CPU1 + EXIT11IM: u1, + /// Peripheral EXIT12 interrupt mask to CPU1 + EXIT12IM: u1, + /// Peripheral EXIT13 interrupt mask to CPU1 + EXIT13IM: u1, + /// Peripheral EXIT14 interrupt mask to CPU1 + EXIT14IM: u1, + /// Peripheral EXIT15 interrupt mask to CPU1 + EXIT15IM: u1, }), - /// FLASH CRC start address register for bank 1 - CRCSADDR: mmio.Mmio(packed struct(u32) { - /// CRC start address on bank 1 - CRC_START_ADDR: u32, + /// CPU1 interrupt mask register 2 + IMR2: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Peripheral PVM1 interrupt mask to CPU1 + PVM1IM: u1, + reserved18: u1, + /// Peripheral PVM3 interrupt mask to CPU1 + PVM3IM: u1, + reserved20: u1, + /// Peripheral PVD interrupt mask to CPU1 + PVDIM: u1, + padding: u11, }), - /// FLASH CRC end address register for bank 1 - CRCEADDR: mmio.Mmio(packed struct(u32) { - /// CRC end address on bank 1 - CRC_END_ADDR: u32, + /// CPU2 interrupt mask register 1 + C2IMR1: mmio.Mmio(packed struct(u32) { + /// Peripheral RTCSTAMP interrupt mask to CPU2 + RTCSTAMP: u1, + reserved3: u2, + /// Peripheral RTCWKUP interrupt mask to CPU2 + RTCWKUP: u1, + /// Peripheral RTCALARM interrupt mask to CPU2 + RTCALARM: u1, + /// Peripheral RCC interrupt mask to CPU2 + RCC: u1, + /// Peripheral FLASH interrupt mask to CPU2 + FLASH: u1, + reserved8: u1, + /// Peripheral PKA interrupt mask to CPU2 + PKA: u1, + /// Peripheral RNG interrupt mask to CPU2 + RNG: u1, + /// Peripheral AES1 interrupt mask to CPU2 + AES1: u1, + /// Peripheral COMP interrupt mask to CPU2 + COMP: u1, + /// Peripheral ADC interrupt mask to CPU2 + ADC: u1, + padding: u19, }), - reserved92: [4]u8, - /// FLASH ECC fail address for bank 1 - FAR: mmio.Mmio(packed struct(u32) { - /// Bank 1 ECC error address - FAIL_ECC_ADDR: u15, - padding: u17, + /// CPU2 interrupt mask register 1 + C2IMR2: mmio.Mmio(packed struct(u32) { + /// Peripheral DMA1 CH1 interrupt mask to CPU2 + DMA1_CH1_IM: u1, + /// Peripheral DMA1 CH2 interrupt mask to CPU2 + DMA1_CH2_IM: u1, + /// Peripheral DMA1 CH3 interrupt mask to CPU2 + DMA1_CH3_IM: u1, + /// Peripheral DMA1 CH4 interrupt mask to CPU2 + DMA1_CH4_IM: u1, + /// Peripheral DMA1 CH5 interrupt mask to CPU2 + DMA1_CH5_IM: u1, + /// Peripheral DMA1 CH6 interrupt mask to CPU2 + DMA1_CH6_IM: u1, + /// Peripheral DMA1 CH7 interrupt mask to CPU2 + DMA1_CH7_IM: u1, + reserved8: u1, + /// Peripheral DMA2 CH1 interrupt mask to CPU1 + DMA2_CH1_IM: u1, + /// Peripheral DMA2 CH2 interrupt mask to CPU1 + DMA2_CH2_IM: u1, + /// Peripheral DMA2 CH3 interrupt mask to CPU1 + DMA2_CH3_IM: u1, + /// Peripheral DMA2 CH4 interrupt mask to CPU1 + DMA2_CH4_IM: u1, + /// Peripheral DMA2 CH5 interrupt mask to CPU1 + DMA2_CH5_IM: u1, + /// Peripheral DMA2 CH6 interrupt mask to CPU1 + DMA2_CH6_IM: u1, + /// Peripheral DMA2 CH7 interrupt mask to CPU1 + DMA2_CH7_IM: u1, + /// Peripheral DMAM UX1 interrupt mask to CPU1 + DMAM_UX1_IM: u1, + /// Peripheral PVM1IM interrupt mask to CPU1 + PVM1IM: u1, + reserved18: u1, + /// Peripheral PVM3IM interrupt mask to CPU1 + PVM3IM: u1, + reserved20: u1, + /// Peripheral PVDIM interrupt mask to CPU1 + PVDIM: u1, + /// Peripheral TSCIM interrupt mask to CPU1 + TSCIM: u1, + /// Peripheral LCDIM interrupt mask to CPU1 + LCDIM: u1, + padding: u9, + }), + /// secure IP control register + SIPCR: mmio.Mmio(packed struct(u32) { + /// Enable AES1 KEY[7:0] security. + SAES: u1, + reserved2: u1, + /// Enable PKA security + SPKA: u1, + /// Enable True RNG security + SRNG: u1, + padding: u28, }), }; + }; - /// Flash - pub const FLASH = extern struct { - /// Access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Read latency - LATENCY: u3, - reserved4: u1, - /// Flash signal delay - WRHIGHFREQ: u2, + pub const syscfg_wba = struct { + /// System configuration controller + pub const SYSCFG = extern struct { + /// secure configuration register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// clock control, memory erase status and compensation cell registers security + SYSCFGSEC: u1, + /// Class B security + CLASSBSEC: u1, + reserved3: u1, + /// FPU security + FPUSEC: u1, + padding: u28, + }), + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// I/O analog switch voltage booster enable Access can be protected by GTZC_TZSC ADC4SEC. Note: Refer to Table�121 for setting. + BOOSTEN: u1, + /// GPIO analog switch control voltage selection Access can be protected by GTZC_TZSC ADC4SEC. Note: Refer to Table�121 for setting. + ANASWVDD: u1, + reserved16: u6, + /// Fast-mode Plus drive capability activation on PA6 This bit can be read and written only with secure access if PA6 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA6 when PA6 is not used by I2C peripheral. This can be used to dive a LED for instance. Access can be protected by GPIOA SEC6. + PA6_FMP: u1, + /// Fast-mode Plus drive capability activation on PA7 This bit can be read and written only with secure access if PA7 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA7 when PA7 is not used by I2C peripheral. This can be used to dive a LED for instance. Access can be protected by GPIOA SEC7. + PA7_FMP: u1, + /// Fast-mode Plus drive capability activation on PA15 This bit can be read and written only with secure access if PA15 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA15 when PA15 is not used by I2C peripheral. This can be used to dive a LED for instance. Access can be protected by GPIOA SEC15. + PA15_FMP: u1, + /// Fast-mode Plus drive capability activation on PB3 This bit can be read and written only with secure access if PB3 is secure in GPIOB. This bit enables the Fast-mode Plus drive mode for PB3 when PB3 is not used by I2C peripheral. This can be used to dive a LED for instance. Access can be protected by GPIOB SEC3. + PB3_FMP: u1, + padding: u12, + }), + /// FPU interrupt mask register + FPUIMR: mmio.Mmio(packed struct(u32) { + /// Floating point unit interrupts enable bits FPU_IE[5]: Inexact interrupt enable (interrupt disable at reset) FPU_IE[4]: Input abnormal interrupt enable FPU_IE[3]: Overflow interrupt enable FPU_IE[2]: Underflow interrupt enable FPU_IE[1]: Divide-by-zero interrupt enable FPU_IE[0]: Invalid operation Interrupt enable + FPU_IE: u6, padding: u26, }), - /// Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R - BANK: u32, - /// FLASH option key register - OPTKEYR: u32, - reserved24: [12]u8, - /// FLASH option control register - OPTCR: mmio.Mmio(packed struct(u32) { - /// FLASH_OPTCR lock option configuration bit - OPTLOCK: u1, - /// Option byte start change option configuration bit - OPTSTART: u1, - reserved4: u2, - /// Flash mass erase enable bit - MER: u1, - reserved30: u25, - /// Option byte change error interrupt enable bit - OPTCHANGEERRIE: u1, - /// Bank swapping configuration bit - SWAP_BANK: u1, + /// CPU non-secure lock register + CNSLCKR: mmio.Mmio(packed struct(u32) { + /// VTOR_NS register lock This bit is set by software and cleared only by a system reset. + LOCKNSVTOR: u1, + /// Non-secure MPU registers lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers. + LOCKNSMPU: u1, + padding: u30, }), - /// FLASH option status register - OPTSR_CUR: mmio.Mmio(packed struct(u32) { - /// Option byte change ongoing flag - OPT_BUSY: u1, - reserved2: u1, - /// Brownout level option status bit - BOR_LEV: u2, - /// IWDG1 control option status bit - IWDG1_HW: u1, - reserved6: u1, - /// D1 DStop entry reset option status bit - nRST_STOP_D1: u1, - /// D1 DStandby entry reset option status bit - nRST_STBY_D1: u1, - /// Readout protection level option status byte - RDP: u8, - reserved17: u1, - /// IWDG Stop mode freeze option status bit - FZ_IWDG_STOP: u1, - /// IWDG Standby mode freeze option status bit - FZ_IWDG_SDBY: u1, - /// DTCM RAM size option status - ST_RAM_SIZE: u2, - /// Security enable option status bit - SECURITY: u1, - reserved26: u4, - /// User option bit 1 - RSS1: u1, - reserved28: u1, - /// Device personalization status bit - PERSO_OK: u1, - /// I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V) - IO_HSLV: u1, - /// Option byte change error flag - OPTCHANGEERR: u1, - /// Bank swapping option status bit - SWAP_BANK_OPT: u1, + /// CPU secure lock register + CSLOCKR: mmio.Mmio(packed struct(u32) { + /// VTOR_S register and AIRCR register bits lock This bit is set by software and cleared only by a system reset. When set, it disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register. + LOCKSVTAIRCR: u1, + /// Secure MPU registers lock This bit is set by software and cleared only by a system reset. When set, it disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers. + LOCKSMPU: u1, + /// SAU registers lock This bit is set by software and cleared only by a system reset. When set, it disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers. + LOCKSAU: u1, + padding: u29, }), - /// FLASH option status register - OPTSR_PRG: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// BOR reset level option configuration bits - BOR_LEV: u2, - /// IWDG1 option configuration bit - IWDG1_HW: u1, - reserved6: u1, - /// Option byte erase after D1 DStop option configuration bit - nRST_STOP_D1: u1, - /// Option byte erase after D1 DStandby option configuration bit - nRST_STBY_D1: u1, - /// Readout protection level option configuration byte - RDP: u8, - reserved17: u1, - /// IWDG Stop mode freeze option configuration bit - FZ_IWDG_STOP: u1, - /// IWDG Standby mode freeze option configuration bit - FZ_IWDG_SDBY: u1, - /// DTCM size select option configuration bits - ST_RAM_SIZE: u2, - /// Security option configuration bit - SECURITY: u1, - reserved26: u4, - /// User option configuration bit 1 - RSS1: u1, - /// User option configuration bit 2 - RSS2: u1, - reserved29: u1, - /// I/O high-speed at low-voltage (PRODUCT_BELOW_25V) - IO_HSLV: u1, - reserved31: u1, - /// Bank swapping option configuration bit - SWAP_BANK_OPT: u1, + /// configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// Cortex-M33 LOCKUP (hardfault) output enable This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex-M33 LOCKUP (hardfault) output to TIM1/16/17 break input. + CLL: u1, + /// SRAM2 parity lock bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs. + SPL: u1, + /// PVD lock enable bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PVDLS[2:0] in the PWR register. + PVDL: u1, + /// ECC lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC double error signal connection to TIM1/16/17 break input. + ECCL: u1, + padding: u28, }), - /// FLASH option clear control register - OPTCCR: mmio.Mmio(packed struct(u32) { - reserved30: u30, - /// OPTCHANGEERR reset bit - CLR_OPTCHANGEERR: u1, - padding: u1, + /// memory erase status register + MESR: mmio.Mmio(packed struct(u32) { + /// Device memories erase status This bit is set by hardware when SRAM2, ICACHE, PKA SRAM erase is completed after power-on reset or tamper detection (refer to Section�75: Tamper and backup registers (TAMP) for more details). This bit is not reset by system reset and is cleared by software by writing 1 to it. + MCLR: u1, + reserved16: u15, + /// ICACHE and PKA SRAM erase status This bit is set by hardware when ICACHE and PKA SRAM erase is completed after potential tamper detection (refer to Section�75: Tamper and backup registers (TAMP) for more details). This bit is cleared by software by writing 1 to it. + IPMEE: u1, + padding: u15, }), - reserved64: [24]u8, - /// FLASH register with boot address - BOOT_CURR: mmio.Mmio(packed struct(u32) { - /// Boot address 0 - BOOT_ADD0: u16, - /// Boot address 1 - BOOT_ADD1: u16, + /// compensation cell control/status register + CCCSR: mmio.Mmio(packed struct(u32) { + /// VDD I/Os compensation cell enable This bit enables the compensation cell of the I/Os supplied by VDD. + EN1: u1, + /// VDD I/Os code selection This bit selects the code to be applied for the compensation cell of the I/Os supplied by VDD. + CS1: u1, + reserved8: u6, + /// VDD I/Os compensation cell ready flag This bit provides the compensation cell status of the I/Os supplied by VDD. Note: The HSI clock is required for the compensation cell to work properly. The compensation cell ready bit (RDY1) is not set if the HSI clock is not enabled (HSION). + RDY1: u1, + padding: u23, }), - /// FLASH register with boot address - BOOT_PRGR: mmio.Mmio(packed struct(u32) { - /// Boot address 0 - BOOT_ADD0: u16, - /// Boot address 1 - BOOT_ADD1: u16, + /// compensation cell value register + CCVR: mmio.Mmio(packed struct(u32) { + /// NMOS compensation value of the I/Os supplied by VDD This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is reset. + NCV1: u4, + /// PMOS compensation value of the I/Os supplied by VDD This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is reset. + PCV1: u4, + padding: u24, }), - reserved92: [20]u8, - /// FLASH CRC data register - CRCDATAR: mmio.Mmio(packed struct(u32) { - /// CRC result - CRC_DATA: u32, + /// compensation cell code register + CCCR: mmio.Mmio(packed struct(u32) { + /// NMOS compensation code of the I/Os supplied by VDD These bits are written by software to define an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is set. + NCC1: u4, + /// PMOS compensation code of the I/Os supplied by VDD These bits are written by software to define an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is set. + PCC1: u4, + padding: u24, + }), + reserved44: [4]u8, + /// RSS command register + RSSCMDR: mmio.Mmio(packed struct(u32) { + /// RSS commands This field defines a command to be executed by the RSS. + RSSCMD: u16, + padding: u16, }), }; }; - pub const pwr_h7rm0433 = struct { - pub const VOS = enum(u2) { - Scale3 = 0x1, - Scale2 = 0x2, - Scale1 = 0x3, - _, - }; - - pub const WKUPPUPD = enum(u2) { - /// No pull-up. - NoPull = 0x0, - /// Pull-up. - PullUp = 0x1, - /// Pull-down. - PullDown = 0x2, - _, - }; - - /// PWR - pub const PWR = extern struct { - /// PWR control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) - LPDS: u1, - reserved4: u3, - /// Programmable voltage detector enable - PVDE: u1, - /// Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. - PLS: u3, - /// Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. - DBP: u1, - /// Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. - FLPS: u1, - reserved14: u4, - /// System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. - SVOS: u2, - /// Peripheral voltage monitor on VDDA enable - AVDEN: u1, - /// Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. - ALS: u2, - padding: u13, + pub const syscfg_wl5 = struct { + /// System configuration controller + pub const SYSCFG = extern struct { + /// memory remap register + MEMRMP: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection + MEM_MODE: u3, + padding: u29, }), - /// PWR control status register 1 - CSR1: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. - PVDO: u1, - reserved13: u8, - /// Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). - ACTVOSRDY: u1, - /// VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. - ACTVOS: u2, - /// Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set. - AVDO: u1, - padding: u15, + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// I/O analog switch voltage booster enable + BOOSTEN: u1, + reserved16: u7, + /// Fast-mode Plus (Fm+) driving capability activation on PB6 + I2C_PB6_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB7 + I2C_PB7_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB8 + I2C_PB8_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB9 + I2C_PB9_FMP: u1, + /// I2C1 Fast-mode Plus driving capability activation + I2C1_FMP: u1, + /// I2C2 Fast-mode Plus driving capability activation + I2C2_FMP: u1, + /// I2C3 Fast-mode Plus driving capability activation + I2C3_FMP: u1, + padding: u9, }), - /// This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. - CR2: mmio.Mmio(packed struct(u32) { - /// Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. - BREN: u1, - reserved4: u3, - /// VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. - MONEN: u1, - reserved16: u11, - /// Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. - BRRDY: u1, - reserved20: u3, - /// VBAT level monitoring versus low threshold - VBATL: u1, - /// VBAT level monitoring versus high threshold - VBATH: u1, - /// Temperature level monitoring versus low threshold - TEMPL: u1, - /// Temperature level monitoring versus high threshold - TEMPH: u1, - padding: u8, + /// external interrupt configuration register 1 + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI12 configuration bits + EXTI: u3, + padding: u29, }), - /// Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value. - CR3: mmio.Mmio(packed struct(u32) { - /// Power management unit bypass - BYPASS: u1, - /// Low drop-out regulator enable - LDOEN: u1, - /// Supply configuration update enable - SCUEN: u1, - reserved8: u5, - /// VBAT charging enable - VBE: u1, - /// VBAT charging resistor selection - VBRS: u1, - reserved24: u14, - /// VDD33USB voltage level detector enable. - USB33DEN: u1, - /// USB regulator enable. - USBREGEN: u1, - /// USB supply ready. - USB33RDY: u1, - padding: u5, + /// SCSR + SCSR: mmio.Mmio(packed struct(u32) { + /// SRAM2 erase + SRAM2ER: u1, + /// SRAM1, SRAM2 and PKA SRAM busy by erase operation + SRAMBSY: u1, + reserved8: u6, + /// PKA SRAM busy by erase operation + PKASRAMBSY: u1, + padding: u23, }), - /// This register allows controlling CPU1 power. - CPUCR: mmio.Mmio(packed struct(u32) { - /// D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. - PDDS_D1: u1, - /// D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. - PDDS_D2: u1, - /// System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. - PDDS_D3: u1, - reserved5: u2, - /// STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. - STOPF: u1, - /// System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit - SBF: u1, - /// D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. - SBF_D1: u1, - /// D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. - SBF_D2: u1, - /// Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. - CSSF: u1, - reserved11: u1, - /// Keep system D3 domain in Run mode regardless of the CPU sub-systems modes - RUN_D3: u1, - padding: u20, + /// CFGR2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// CPU1 LOCKUP (Hardfault) output enable bit + CLL: u1, + /// SRAM2 parity lock bit + SPL: u1, + /// PVD lock enable bit + PVDL: u1, + /// ECC Lock + ECCL: u1, + reserved8: u4, + /// SRAM2 parity error flag + SPF: u1, + padding: u23, }), - reserved24: [4]u8, - /// This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software - D3CR: mmio.Mmio(packed struct(u32) { - reserved13: u13, - /// VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). - VOSRDY: u1, - /// Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling. - VOS: packed union { - raw: u2, - value: VOS, - }, - padding: u16, + /// SWPR + SWPR: mmio.Mmio(packed struct(u32) { + /// SRAM2 1Kbyte page 0 write protection + PWP: u1, + padding: u31, }), - reserved32: [4]u8, - /// reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). - WKUPCR: mmio.Mmio(packed struct(u32) { - /// Clear Wakeup pin flag for WKUP. These bits are always read as 0. - WKUPC: u6, - padding: u26, + /// SKR + SKR: mmio.Mmio(packed struct(u32) { + /// SRAM2 write protection key for software erase + KEY: u8, + padding: u24, }), - /// reset only by system reset, not reset by wakeup from Standby mode - WKUPFR: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). - WKUPF: u1, - padding: u31, + reserved256: [216]u8, + /// SYSCFG CPU1 interrupt mask register 1 + IMR1: mmio.Mmio(packed struct(u32) { + /// RTCSTAMPTAMPLSECSSIM + RTCSTAMPTAMPLSECSSIM: u1, + reserved2: u1, + /// RTCSSRUIM + RTCSSRUIM: u1, + reserved21: u18, + /// EXTI5IM + EXTI5IM: u1, + /// EXTI6IM + EXTI6IM: u1, + /// EXTI7IM + EXTI7IM: u1, + /// EXTI8IM + EXTI8IM: u1, + /// EXTI9IM + EXTI9IM: u1, + /// EXTI10IM + EXTI10IM: u1, + /// EXTI11IM + EXTI11IM: u1, + /// EXTI12IM + EXTI12IM: u1, + /// EXTI13IM + EXTI13IM: u1, + /// EXTI14IM + EXTI14IM: u1, + /// EXTI15IM + EXTI15IM: u1, }), - /// Reset only by system reset, not reset by wakeup from Standby mode - WKUPEPR: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. - WKUPEN: u1, - reserved8: u7, - /// Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. - WKUPP: u1, - reserved16: u7, - /// Wakeup pin pull configuration - WKUPPUPD: packed union { - raw: u2, - value: WKUPPUPD, - }, - padding: u14, + /// SYSCFG CPU1 interrupt mask register 2 + IMR2: mmio.Mmio(packed struct(u32) { + reserved18: u18, + /// PVM3IM + PVM3IM: u1, + reserved20: u1, + /// PVDIM + PVDIM: u1, + padding: u11, + }), + /// SYSCFG CPU2 interrupt mask register 1 + C2IMR1: mmio.Mmio(packed struct(u32) { + /// RTCSTAMPTAMPLSECSSIM + RTCSTAMPTAMPLSECSSIM: u1, + /// RTCALARMIM + RTCALARMIM: u1, + /// RTCSSRUIM + RTCSSRUIM: u1, + /// RTCWKUPIM + RTCWKUPIM: u1, + reserved5: u1, + /// RCCIM + RCCIM: u1, + /// FLASHIM + FLASHIM: u1, + reserved8: u1, + /// PKAIM + PKAIM: u1, + reserved10: u1, + /// AESIM + AESIM: u1, + /// COMPIM + COMPIM: u1, + /// ADCIM + ADCIM: u1, + /// DACIM + DACIM: u1, + reserved16: u2, + /// EXTI0IM + EXTI0IM: u1, + /// EXTI1IM + EXTI1IM: u1, + /// EXTI2IM + EXTI2IM: u1, + /// EXTI3IM + EXTI3IM: u1, + /// EXTI4IM + EXTI4IM: u1, + /// EXTI5IM + EXTI5IM: u1, + /// EXTI6IM + EXTI6IM: u1, + /// EXTI7IM + EXTI7IM: u1, + /// EXTI8IM + EXTI8IM: u1, + /// EXTI9IM + EXTI9IM: u1, + /// EXTI10IM + EXTI10IM: u1, + /// EXTI11IM + EXTI11IM: u1, + /// EXTI12IM + EXTI12IM: u1, + /// EXTI13IM + EXTI13IM: u1, + /// EXTI14IM + EXTI14IM: u1, + /// EXTI15IM + EXTI15IM: u1, + }), + /// SYSCFG CPU2 interrupt mask register 2 + C2IMR2: mmio.Mmio(packed struct(u32) { + /// DMA1CH1IM + DMA1CH1IM: u1, + /// DMA1CH2IM + DMA1CH2IM: u1, + /// DMA1CH3IM + DMA1CH3IM: u1, + /// DMA1CH4IM + DMA1CH4IM: u1, + /// DMA1CH5IM + DMA1CH5IM: u1, + /// DMA1CH6IM + DMA1CH6IM: u1, + /// DMA1CH7IM + DMA1CH7IM: u1, + reserved8: u1, + /// DMA2CH1IM + DMA2CH1IM: u1, + /// DMA2CH2IM + DMA2CH2IM: u1, + /// DMA2CH3IM + DMA2CH3IM: u1, + /// DMA2CH4IM + DMA2CH4IM: u1, + /// DMA2CH5IM + DMA2CH5IM: u1, + /// DMA2CH6IM + DMA2CH6IM: u1, + /// DMA2CH7IM + DMA2CH7IM: u1, + /// DMAMUX1IM + DMAMUX1IM: u1, + reserved18: u2, + /// PVM3IM + PVM3IM: u1, + reserved20: u1, + /// PVDIM + PVDIM: u1, + padding: u11, + }), + reserved520: [248]u8, + /// radio debug control register + RFDCR: mmio.Mmio(packed struct(u32) { + /// radio debug test bus selection + RFTBSEL: u1, + padding: u31, }), }; }; - pub const comp_h5 = struct { - pub const BLANKING = enum(u4) { - NoBlanking = 0x0, - Tim1Oc5 = 0x1, - Tim2Oc3 = 0x2, - Tim3Oc3 = 0x3, - Tim3Oc4 = 0x4, - Lptim1Ch2 = 0x5, - Lptim2Ch2 = 0x6, - _, - }; - - pub const HYST = enum(u2) { - None = 0x0, - Low = 0x1, - Medium = 0x2, - High = 0x3, - }; - - pub const INMSEL = enum(u4) { - VRef_1over4 = 0x0, - VRef_1over2 = 0x1, - VRef_3over4 = 0x2, - VRef = 0x3, - Dac1Out1 = 0x4, - Inm1 = 0x5, - Inm2 = 0x6, - Inm3 = 0x7, - VSense = 0x8, - VBat_1over4 = 0x9, - _, - }; - - pub const PWRMODE = enum(u2) { - /// High speed / full power - High = 0x0, - /// Medium speed / medium power - Medium = 0x1, - /// Medium speed / medium power - MediumEither = 0x2, - /// Ultra low power / ultra-low-power - Low = 0x3, - }; - - /// Comparator. - pub const COMP = extern struct { - /// Comparator status register. - SR: mmio.Mmio(packed struct(u32) { - /// COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect. - CVAL: u1, - reserved16: u15, - /// COMP Channel1 interrupt flag This bit is set by hardware when the COMP Channel1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register. - CIF: u1, - padding: u15, + pub const syscfg_wle = struct { + /// System configuration controller + pub const SYSCFG = extern struct { + /// memory remap register + MEMRMP: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection + MEM_MODE: u3, + padding: u29, + }), + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// I/O analog switch voltage booster enable + BOOSTEN: u1, + reserved16: u7, + /// Fast-mode Plus (Fm+) driving capability activation on PB6 + I2C_PB6_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB7 + I2C_PB7_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB8 + I2C_PB8_FMP: u1, + /// Fast-mode Plus (Fm+) driving capability activation on PB9 + I2C_PB9_FMP: u1, + /// I2C1 Fast-mode Plus driving capability activation + I2C1_FMP: u1, + /// I2C2 Fast-mode Plus driving capability activation + I2C2_FMP: u1, + /// I2C3 Fast-mode Plus driving capability activation + I2C3_FMP: u1, + padding: u9, + }), + /// external interrupt configuration register 1 + EXTICR: [4]mmio.Mmio(packed struct(u32) { + /// EXTI12 configuration bits + EXTI: u3, + padding: u29, + }), + /// SCSR + SCSR: mmio.Mmio(packed struct(u32) { + /// SRAM2 erase + SRAM2ER: u1, + /// SRAM1, SRAM2 and PKA SRAM busy by erase operation + SRAMBSY: u1, + reserved8: u6, + /// PKA SRAM busy by erase operation + PKASRAMBSY: u1, + padding: u23, + }), + /// CFGR2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// CPU1 LOCKUP (Hardfault) output enable bit + CLL: u1, + /// SRAM2 parity lock bit + SPL: u1, + /// PVD lock enable bit + PVDL: u1, + /// ECC Lock + ECCL: u1, + reserved8: u4, + /// SRAM2 parity error flag + SPF: u1, + padding: u23, }), - /// Comparator interrupt clear flag register. - ICFR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Clear COMP Channel1 interrupt flag Writing 1 clears the C1IF flag in the COMP_SR register. - CCIF: u1, - padding: u15, + /// SWPR + SWPR: mmio.Mmio(packed struct(u32) { + /// SRAM2 1Kbyte page 0 write protection + PWP: u1, + padding: u31, }), - reserved12: [4]u8, - /// Comparator configuration register 1. - CFGR1: mmio.Mmio(packed struct(u32) { - /// COMP Channel1 enable This bit is set and cleared by software (only if LOCK not set). It enables the COMP-Channel1. - EN: u1, - /// Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler. If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level VREF_COMP (similar to VREFINT). If SCALEN and BRGEN are set, the four scaler outputs provide VREF_COMP, 3/4-VREF_COMP, 1/2-VREF_COMP and 1/4-VREF_COMP levels, respectively. - BRGEN: u1, - /// Voltage scaler enable This bit is set and cleared by software (only if LOCK not set). This bit enables the VREFINT scaler for the COMP channels. - SCALEN: u1, - /// COMP channel1 polarity selection This bit is set and cleared by software (only if LOCK not set). It inverts COMP channel1 polarity. - POLARITY: u1, - reserved6: u2, - /// COMP channel1 interrupt enable This bit is set and cleared by software (only if LOCK not set). This bit enable the interrupt generation of the COMP channel1. - ITEN: u1, - reserved8: u1, - /// COMP channel1 hysteresis selection These bits are set and cleared by software (only if LOCK not set). They select the hysteresis voltage of the COMP channel1. - HYST: packed union { - raw: u2, - value: HYST, - }, - reserved12: u2, - /// Power mode of the COMP channel1 These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the COMP channel1. - PWRMODE: packed union { - raw: u2, - value: PWRMODE, - }, - reserved16: u2, - /// COMP channel1 inverting input selection These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of the COMP channel. Note: See Table-146: COMP1 inverting input assignment for more details. - INMSEL: packed union { - raw: u4, - value: INMSEL, - }, - /// COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. Note: See Table-145: COMP1 noninverting input assignment for more details. - INPSEL1: u1, - reserved22: u1, - /// COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of the COMP channel. See Table-145: COMP1 noninverting input assignment for more details. - INPSEL2: u1, - reserved24: u1, - /// COMP Channel1 blanking source selection Bits of this field are set and cleared by software (only if LOCK not set). The field selects the input source for COMP Channel1 output blanking: All other values: reserved. - BLANKING: packed union { - raw: u4, - value: BLANKING, - }, - reserved31: u3, - /// Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR1[31:0]. - LOCK: u1, + /// SKR + SKR: mmio.Mmio(packed struct(u32) { + /// SRAM2 write protection key for software erase + KEY: u8, + padding: u24, }), - /// Comparator configuration register 2. - CFGR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// COMP non-inverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. See Table-145: COMP1 noninverting input assignment for more details. - INPSEL0: u1, - reserved31: u26, - /// Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR2[31:0]. - LOCK: u1, + reserved520: [480]u8, + /// radio debug control register + RFDCR: mmio.Mmio(packed struct(u32) { + /// radio debug test bus selection + RFTBSEL: u1, + padding: u31, }), }; }; - pub const dbgmcu_h5 = struct { - /// Microcontroller debug unit. - pub const DBGMCU = extern struct { - /// DBGMCU identity code register. - IDCODE: mmio.Mmio(packed struct(u32) { - /// device identification. - DEV_ID: u12, - reserved16: u4, - /// revision. - REV_ID: u16, - }), - /// DBGMCU configuration register. - CR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Allows debug in Stop mode All clocks are disabled automatically in Stop mode. All active clocks and oscillators continue to run during Stop mode, allowing full debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state. - STOP: u1, - /// Allows debug in Standby mode All clocks are disabled and the core powered down automatically in Standby mode. All active clocks and oscillators continue to run during Standby mode, and the core supply is maintained, allowing full debug capability. On exit from Standby mode, a system reset is performed. - STANDBY: u1, - reserved4: u1, - /// trace pin enable. - TRACE_IOEN: u1, - /// trace port and clock enable. This bit enables the trace port clock, TRACECK. - TRACE_EN: u1, - /// trace pin assignment. - TRACE_MODE: u2, - reserved16: u8, - /// Debug credentials reset type This bit selects which type of reset is used to revoke the debug authentication credentials. - DCRT: u1, + pub const tamp_g0 = struct { + /// Tamper and backup registers + pub const TAMP = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Tamper detection on IN X enable + TAMPE: u1, + reserved16: u15, + /// Internal tamper X enable + ITAMPE: u1, padding: u15, }), - /// DBGMCU APB1L peripheral freeze register. - APB1LFZR: mmio.Mmio(packed struct(u32) { - /// TIM2 stop in debug. - TIM2_STOP: u1, - /// TIM3 stop in debug. - TIM3_STOP: u1, - /// TIM4 stop in debug. - TIM4_STOP: u1, - /// TIM5 stop in debug. - TIM5_STOP: u1, - /// TIM6 stop in debug. - TIM6_STOP: u1, - /// TIM7 stop in debug. - TIM7_STOP: u1, - /// TIM12 stop in debug. - TIM12_STOP: u1, - /// TIM13 stop in debug. - TIM13_STOP: u1, - /// TIM14 stop in debug. - TIM14_STOP: u1, - reserved11: u2, - /// WWDG stop in debug. - WWDG_STOP: u1, - /// IWDG stop in debug. - IWDG_STOP: u1, - reserved21: u8, - /// I2C1 SMBUS timeout stop in debug. - I2C1_STOP: u1, - /// I2C2 SMBUS timeout stop in debug. - I2C2_STOP: u1, - /// I3C1 SCL stall counter stop in debug. - I3C1_STOP: u1, - padding: u8, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Tamper X no erase + TAMPNOER: u1, + reserved16: u15, + /// Tamper X mask + TAMPMSK: u1, + reserved24: u7, + /// Active level for tamper X input + TAMPTRG: u1, + padding: u7, }), - /// DBGMCU APB1H peripheral freeze register. - APB1HFZR: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// LPTIM2 stop in debug. - LPTIM2_STOP: u1, - padding: u26, + reserved12: [4]u8, + /// TAMP filter control register + FLTCR: mmio.Mmio(packed struct(u32) { + /// Tamper sampling frequency. Determines the frequency at which each of the INx inputs are sampled. + TAMPFREQ: u3, + /// INx filter count. These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the INx inputs. + TAMPFLT: u2, + /// INx precharge duration. These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the INx inputs. + TAMPPRCH: u2, + /// INx pull-up disable. This bit determines if each of the TAMPx pins are precharged before each sample. + TAMPPUDIS: u1, + padding: u24, }), - /// DBGMCU APB2 peripheral freeze register. - APB2FZR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 stop in debug. - TIM1_STOP: u1, - reserved13: u1, - /// TIM8 stop in debug. - TIM8_STOP: u1, - reserved16: u2, - /// TIM15 stop in debug. - TIM15_STOP: u1, - /// TIM16 stop in debug. - TIM16_STOP: u1, - /// TIM17 stop in debug. - TIM17_STOP: u1, - padding: u13, + reserved44: [28]u8, + /// TAMP interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// Tamper X interrupt enable + TAMPIE: u1, + reserved16: u15, + /// Internal tamper X interrupt enable + ITAMPIE: u1, + padding: u15, }), - /// DBGMCU APB3 peripheral freeze register. - APB3FZR: mmio.Mmio(packed struct(u32) { - reserved10: u10, - /// I2C3 SMBUS timeout stop in debug. - I2C3_STOP: u1, - /// I2C4 SMBUS timeout stop in debug. - I2C4_STOP: u1, - reserved17: u5, - /// LPTIM1 stop in debug. - LPTIM1_STOP: u1, - /// LPTIM3 stop in debug. - LPTIM3_STOP: u1, - /// LPTIM4 stop in debug. - LPTIM4_STOP: u1, - /// LPTIM5 stop in debug. - LPTIM5_STOP: u1, - /// LPTIM6 stop in debug. - LPTIM6_STOP: u1, - reserved30: u8, - /// RTC stop in debug. - RTC_STOP: u1, - padding: u1, + /// TAMP status register + SR: mmio.Mmio(packed struct(u32) { + /// Tamper X detection flag + TAMPF: u1, + reserved16: u15, + /// Internal tamper X detection flag + ITAMPF: u1, + padding: u15, }), - reserved32: [8]u8, - /// DBGMCU AHB1 peripheral freeze register. - AHB1FZR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 channel 0 stop in debug. - GPDMA1_STOP: u1, + /// TAMP masked interrupt status register + MISR: mmio.Mmio(packed struct(u32) { + /// Tamper X interrupt masked flag + TAMPMF: u1, reserved16: u15, - /// GPDMA2 channel 0 stop in debug. - GPDMA2_STOP: u1, + /// Internal tamper X interrupt masked flag + ITAMPMF: u1, padding: u15, }), - reserved252: [216]u8, - /// DBGMCU status register. - SR: mmio.Mmio(packed struct(u32) { - /// Bit n identifies whether access port AP n is present in device Bit n = 0: APn absent Bit n = 1: APn present. - AP_PRESENT: u16, - /// Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) Bit n = 0: APn locked Bit n = 1: APn enabled. - AP_ENABLED: u16, + reserved60: [4]u8, + /// TAMP status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear tamper X detection flag + CTAMPF: u1, + reserved16: u15, + /// Clear internal tamper X detection flag + CITAMPF: u1, + padding: u15, }), - /// DBGMCU debug authentication mailbox host register. - AUTH_HOST: u32, - /// DBGMCU debug authentication mailbox device register. - AUTH_DEVICE: u32, - /// DBGMCU debug authentication mailbox acknowledge register. - AUTH_ACK: mmio.Mmio(packed struct(u32) { - /// Host to device acknowledge. The device sets this bit to indicate that it has placed a message in the DBGMCU_DBG_AUTH_DEVICE register. It should be reset by the host after reading the message. - HOST_ACK: u1, - /// Device to device acknowledge. The host sets this bit to indicate that it has placed a message in the DBGMCU_DBG_AUTH_HOST register. It is reset by the device after reading the message. - DEV_ACK: u1, - padding: u30, + reserved256: [192]u8, + /// TAMP backup register + BKPR: [5]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, }), - reserved4048: [3780]u8, - /// DBGMCU CoreSight peripheral identity register 4. - PIDR4: mmio.Mmio(packed struct(u32) { - /// JEP106 continuation code. - JEP106CON: u4, - /// register file size. - SIZE: u4, - padding: u24, + reserved1004: [728]u8, + /// TAMP hardware configuration register 2 + HWCFGR2: mmio.Mmio(packed struct(u32) { + /// PTIONREG_OUT + PTIONREG_OUT: u8, + /// TRUST_ZONE + TRUST_ZONE: u4, + padding: u20, }), - reserved4064: [12]u8, - /// DBGMCU CoreSight peripheral identity register 0. - PIDR0: mmio.Mmio(packed struct(u32) { - /// part number bits [7:0]. - PARTNUM: u8, - padding: u24, + /// TAMP hardware configuration register 1 + HWCFGR1: mmio.Mmio(packed struct(u32) { + /// BACKUP_REGS + BACKUP_REGS: u8, + /// TAMPER + TAMPER: u4, + /// ACTIVE_TAMPER + ACTIVE_TAMPER: u4, + /// INT_TAMPER + INT_TAMPER: u16, }), - /// DBGMCU CoreSight peripheral identity register 1. - PIDR1: mmio.Mmio(packed struct(u32) { - /// part number bits [11:8]. - PARTNUM: u4, - /// JEP106 identity code bits [3:0]. - JEP106ID: u4, + /// EXTI IP Version register + VERR: mmio.Mmio(packed struct(u32) { + /// Minor Revision number + MINREV: u4, + /// Major Revision number + MAJREV: u4, padding: u24, }), - /// DBGMCU CoreSight peripheral identity register 2. - PIDR2: mmio.Mmio(packed struct(u32) { - /// JEP106 identity code bits [6:4]. - JEP106ID: u3, - /// JEDEC assigned value. - JEDEC: u1, - /// component revision number. - REVISION: u4, - padding: u24, + /// EXTI Identification register + IPIDR: mmio.Mmio(packed struct(u32) { + /// IP Identification + IPID: u32, }), - /// DBGMCU CoreSight peripheral identity register 3. - PIDR3: mmio.Mmio(packed struct(u32) { - /// customer modified. - CMOD: u4, - /// metal fix version. - REVAND: u4, - padding: u24, + /// EXTI Size ID register + SIDR: mmio.Mmio(packed struct(u32) { + /// Size Identification + SID: u32, }), - /// DBGMCU CoreSight component identity register 0. - CIDR0: mmio.Mmio(packed struct(u32) { - /// component identification bits [7:0]. - PREAMBLE: u8, - padding: u24, + }; + }; + + pub const tamp_g4 = struct { + /// Tamper and backup registers + pub const TAMP = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Tamper detection on IN X enable + TAMPE: u1, + reserved16: u15, + /// Internal tamper X enable + ITAMPE: u1, + padding: u15, }), - /// DBGMCU CoreSight component identity register 1. - CIDR1: mmio.Mmio(packed struct(u32) { - /// component identification bits [11:8]. - PREAMBLE: u4, - /// component identification bits [15:12] - component class. - CLASS: u4, - padding: u24, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Tamper X no erase + TAMPNOER: u1, + reserved16: u15, + /// Tamper X mask. + TAMPMSK: u1, + reserved24: u7, + /// Active level for tamper X input. + TAMPTRG: u1, + padding: u7, }), - /// DBGMCU CoreSight component identity register 2. - CIDR2: mmio.Mmio(packed struct(u32) { - /// component identification bits [23:16]. - PREAMBLE: u8, + reserved12: [4]u8, + /// TAMP filter control register + FLTCR: mmio.Mmio(packed struct(u32) { + /// Tamper sampling frequency. Determines the frequency at which each of the INx inputs are sampled. + TAMPFREQ: u3, + /// INx filter count. These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the INx inputs. + TAMPFLT: u2, + /// INx precharge duration. These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the INx inputs. + TAMPPRCH: u2, + /// INx pull-up disable. This bit determines if each of the TAMPx pins are precharged before each sample. + TAMPPUDIS: u1, padding: u24, }), - /// DBGMCU CoreSight component identity register 3. - CIDR3: mmio.Mmio(packed struct(u32) { - /// component identification bits [31:24]. - PREAMBLE: u8, - padding: u24, + reserved44: [28]u8, + /// TAMP interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// Tamper X interrupt enable + TAMPIE: u1, + reserved16: u15, + /// Internal tamper X interrupt enable + ITAMPIE: u1, + padding: u15, + }), + /// TAMP status register + SR: mmio.Mmio(packed struct(u32) { + /// Tamper X detection flag + TAMPF: u1, + reserved16: u15, + /// Internal tamper X detection flag + ITAMPF: u1, + padding: u15, + }), + /// TAMP masked interrupt status register + MISR: mmio.Mmio(packed struct(u32) { + /// Tamper X interrupt masked flag + TAMPMF: u1, + reserved16: u15, + /// Internal tamper X interrupt masked flag + ITAMPMF: u1, + padding: u15, + }), + reserved60: [4]u8, + /// TAMP status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear tamper X detection flag + CTAMPF: u1, + reserved16: u15, + /// Clear internal tamper X detection flag + CITAMPF: u1, + padding: u15, + }), + reserved256: [192]u8, + /// TAMP backup register + BKPR: [32]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, }), }; }; - pub const rcc_f0v1 = struct { - pub const CECSW = enum(u1) { - /// HSI clock divided by 244 selected as CEC clock source - HSI_DIV_244 = 0x0, - /// LSE clock selected as CEC clock source - LSE = 0x1, - }; - - pub const HPRE = enum(u4) { - /// SYSCLK not divided - Div1 = 0x0, - /// SYSCLK divided by 2 - Div2 = 0x8, - /// SYSCLK divided by 4 - Div4 = 0x9, - /// SYSCLK divided by 8 - Div8 = 0xa, - /// SYSCLK divided by 16 - Div16 = 0xb, - /// SYSCLK divided by 64 - Div64 = 0xc, - /// SYSCLK divided by 128 - Div128 = 0xd, - /// SYSCLK divided by 256 - Div256 = 0xe, - /// SYSCLK divided by 512 - Div512 = 0xf, - _, - }; - - pub const ICSW = enum(u1) { - /// HSI clock selected as I2C clock source - HSI = 0x0, - /// SYSCLK clock selected as I2C clock source - SYS = 0x1, - }; - - pub const LSEDRV = enum(u2) { - /// Low driving capability - Low = 0x0, - /// Medium high driving capability - MediumHigh = 0x1, - /// Medium low driving capability - MediumLow = 0x2, - /// High driving capability - High = 0x3, - }; - - pub const MCOSEL = enum(u4) { - /// MCO output disabled, no clock on MCO - DISABLE = 0x0, - /// Internal RC 14 MHz (HSI14) oscillator clock selected - HSI14 = 0x1, - /// Internal low speed (LSI) oscillator clock selected - LSI = 0x2, - /// External low speed (LSE) oscillator clock selected - LSE = 0x3, - /// System clock selected - SYS = 0x4, - /// Internal RC 8 MHz (HSI) oscillator clock selected - HSI = 0x5, - /// External 4-32 MHz (HSE) oscillator clock selected - HSE = 0x6, - /// PLL clock selected divided by 2 - PLL = 0x7, - _, - }; - - pub const PLLMUL = enum(u4) { - /// PLL input clock x2 - Mul2 = 0x0, - /// PLL input clock x3 - Mul3 = 0x1, - /// PLL input clock x4 - Mul4 = 0x2, - /// PLL input clock x5 - Mul5 = 0x3, - /// PLL input clock x6 - Mul6 = 0x4, - /// PLL input clock x7 - Mul7 = 0x5, - /// PLL input clock x8 - Mul8 = 0x6, - /// PLL input clock x9 - Mul9 = 0x7, - /// PLL input clock x10 - Mul10 = 0x8, - /// PLL input clock x11 - Mul11 = 0x9, - /// PLL input clock x12 - Mul12 = 0xa, - /// PLL input clock x13 - Mul13 = 0xb, - /// PLL input clock x14 - Mul14 = 0xc, - /// PLL input clock x15 - Mul15 = 0xd, - /// PLL input clock x16 - Mul16 = 0xe, - _, - }; - - pub const PLLSRC = enum(u1) { - /// HSI divided by 2 selected as PLL input clock - HSI_Div2 = 0x0, - /// HSE divided by PREDIV selected as PLL input clock - HSE_Div_PREDIV = 0x1, - }; - - pub const PLLXTPRE = enum(u1) { - /// HSE clock not divided - Div1 = 0x0, - /// HSE clock divided by 2 - Div2 = 0x1, - }; - - pub const PPRE = enum(u3) { - /// HCLK not divided - Div1 = 0x0, - /// HCLK divided by 2 - Div2 = 0x4, - /// HCLK divided by 4 - Div4 = 0x5, - /// HCLK divided by 8 - Div8 = 0x6, - /// HCLK divided by 16 - Div16 = 0x7, - _, - }; - - pub const PREDIV = enum(u4) { - /// PREDIV input clock not divided - Div1 = 0x0, - /// PREDIV input clock divided by 2 - Div2 = 0x1, - /// PREDIV input clock divided by 3 - Div3 = 0x2, - /// PREDIV input clock divided by 4 - Div4 = 0x3, - /// PREDIV input clock divided by 5 - Div5 = 0x4, - /// PREDIV input clock divided by 6 - Div6 = 0x5, - /// PREDIV input clock divided by 7 - Div7 = 0x6, - /// PREDIV input clock divided by 8 - Div8 = 0x7, - /// PREDIV input clock divided by 9 - Div9 = 0x8, - /// PREDIV input clock divided by 10 - Div10 = 0x9, - /// PREDIV input clock divided by 11 - Div11 = 0xa, - /// PREDIV input clock divided by 12 - Div12 = 0xb, - /// PREDIV input clock divided by 13 - Div13 = 0xc, - /// PREDIV input clock divided by 14 - Div14 = 0xd, - /// PREDIV input clock divided by 15 - Div15 = 0xe, - /// PREDIV input clock divided by 16 - Div16 = 0xf, - }; - - pub const RTCSEL = enum(u2) { - /// No clock - DISABLE = 0x0, - /// LSE oscillator clock used as RTC clock - LSE = 0x1, - /// LSI oscillator clock used as RTC clock - LSI = 0x2, - /// HSE oscillator clock divided by a prescaler used as RTC clock - HSE = 0x3, - }; - - pub const SW = enum(u2) { - /// HSI oscillator used as system clock - HSI = 0x0, - /// HSE oscillator used as system clock - HSE = 0x1, - /// PLL used as system clock - PLL1_P = 0x2, - _, - }; - - pub const USART1SW = enum(u2) { - /// PCLK selected as USART clock source - PCLK2 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, - }; - - pub const USARTSW = enum(u2) { - /// PCLK selected as USART clock source - PCLK1 = 0x0, - /// SYSCLK selected as USART clock source - SYS = 0x1, - /// LSE selected as USART clock source - LSE = 0x2, - /// HSI selected as USART clock source - HSI = 0x3, - }; - - pub const USBSW = enum(u1) { - /// PLL clock selected as USB clock source - PLL1_P = 0x1, - _, - }; - - /// Reset and clock control - pub const RCC = extern struct { - /// Clock control register - CR: mmio.Mmio(packed struct(u32) { - /// Internal High Speed clock enable - HSION: u1, - /// Internal High Speed clock ready flag - HSIRDY: u1, - reserved3: u1, - /// Internal High Speed clock trimming - HSITRIM: u5, - /// Internal High Speed clock Calibration - HSICAL: u8, - /// External High Speed clock enable - HSEON: u1, - /// External High Speed clock ready flag - HSERDY: u1, - /// External High Speed clock Bypass - HSEBYP: u1, - /// Clock Security System enable - CSSON: u1, - reserved24: u4, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding: u6, - }), - /// Clock configuration register (RCC_CFGR) - CFGR: mmio.Mmio(packed struct(u32) { - /// System clock Switch - SW: packed union { - raw: u2, - value: SW, - }, - /// System Clock Switch Status - SWS: packed union { - raw: u2, - value: SW, - }, - /// AHB prescaler - HPRE: packed union { - raw: u4, - value: HPRE, - }, - /// APB Low speed prescaler (APB1) - PPRE: packed union { - raw: u3, - value: PPRE, - }, - reserved14: u3, - /// APCPRE is deprecated. See ADC field in CFGR2 register. - ADCPRE: u1, - reserved16: u1, - /// PLL input clock source - PLLSRC: packed union { - raw: u1, - value: PLLSRC, - }, - /// HSE divider for PLL entry. Same bit as PREDIV[0] from CFGR2 register. Refer to it for its meaning - PLLXTPRE: packed union { - raw: u1, - value: PLLXTPRE, - }, - /// PLL Multiplication Factor - PLLMUL: packed union { - raw: u4, - value: PLLMUL, - }, - reserved24: u2, - /// Microcontroller clock output - MCOSEL: packed union { - raw: u4, - value: MCOSEL, - }, - padding: u4, + pub const tamp_h5 = struct { + /// Tamper and backup. + pub const TAMP = extern struct { + /// TAMP control register 1. + CR1: mmio.Mmio(packed struct(u32) { + /// Tamper detection on TAMP_INx enable. (x=1-8) + TAMPE: u1, + reserved16: u15, + /// Internal tamper 1 enable. + ITAMP1E: u1, + /// Internal tamper 2 enable. + ITAMP2E: u1, + /// Internal tamper 3 enable. + ITAMP3E: u1, + /// Internal tamper 4 enable. + ITAMP4E: u1, + /// Internal tamper 5 enable. + ITAMP5E: u1, + /// Internal tamper 6 enable. + ITAMP6E: u1, + /// Internal tamper 7 enable. + ITAMP7E: u1, + /// Internal tamper 8 enable. + ITAMP8E: u1, + /// Internal tamper 9 enable. + ITAMP9E: u1, + reserved26: u1, + /// Internal tamper 11 enable. + ITAMP11E: u1, + /// Internal tamper 12 enable. + ITAMP12E: u1, + /// Internal tamper 13 enable. + ITAMP13E: u1, + reserved30: u1, + /// Internal tamper 15 enable. + ITAMP15E: u1, + padding: u1, }), - /// Clock interrupt register (RCC_CIR) - CIR: mmio.Mmio(packed struct(u32) { - /// LSI Ready Interrupt flag - LSIRDYF: u1, - /// LSE Ready Interrupt flag - LSERDYF: u1, - /// HSI Ready Interrupt flag - HSIRDYF: u1, - /// HSE Ready Interrupt flag - HSERDYF: u1, - /// PLL Ready Interrupt flag - PLLRDYF: u1, - /// HSI14 ready interrupt flag - HSI14RDYF: u1, - reserved7: u1, - /// Clock Security System Interrupt flag - CSSF: u1, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1, - /// LSE Ready Interrupt Enable - LSERDYIE: u1, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1, - /// HSE Ready Interrupt Enable - HSERDYIE: u1, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1, - /// HSI14 ready interrupt enable - HSI14RDYIE: u1, - reserved16: u2, - /// LSI Ready Interrupt Clear - LSIRDYC: u1, - /// LSE Ready Interrupt Clear - LSERDYC: u1, - /// HSI Ready Interrupt Clear - HSIRDYC: u1, - /// HSE Ready Interrupt Clear - HSERDYC: u1, - /// PLL Ready Interrupt Clear - PLLRDYC: u1, - /// HSI 14 MHz Ready Interrupt Clear - HSI14RDYC: u1, - reserved23: u1, - /// Clock security system interrupt clear - CSSC: u1, - padding: u8, + /// TAMP control register 2. + CR2: mmio.Mmio(packed struct(u32) { + /// Tamper x potential mode. (x=1-8) + TAMPPOM: u1, + reserved16: u15, + /// Tamper x mask. The tamper x interrupt must not be enabled when TAMPxMSK is set. (x=1-3) + TAMPMSK: u1, + reserved22: u5, + /// Backup registers and device secrets access blocked. + BKBLOCK: u1, + /// Backup registers and device secrets erase Writing ‘1’ to this bit reset the backup registers and device secrets(1). Writing 0 has no effect. This bit is always read as 0. + BKERASE: u1, + /// Active level for tamper x input If TAMPFLT = 00 Tamper x input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge triggers a tamper detection event. (x=1-8) + TAMPTRG: u1, + padding: u7, }), - /// APB2 peripheral reset register (RCC_APB2RSTR) - APB2RSTR: mmio.Mmio(packed struct(u32) { - /// SYSCFG and COMP reset - SYSCFGRST: u1, - reserved5: u4, - /// USART6 reset - USART6RST: u1, - /// USART7 reset - USART7RST: u1, - /// USART8 reset - USART8RST: u1, - reserved9: u1, - /// ADC interface reset - ADCRST: u1, - reserved11: u1, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI 1 reset - SPI1RST: u1, + /// TAMP control register 3. + CR3: mmio.Mmio(packed struct(u32) { + /// Internal tamper 1 potential mode. + ITAMP1POM: u1, + /// Internal tamper 2 potential mode. + ITAMP2POM: u1, + /// Internal tamper 3 potential mode. + ITAMP3POM: u1, + /// Internal tamper 4 potential mode. + ITAMP4POM: u1, + /// Internal tamper 5 potential mode. + ITAMP5POM: u1, + /// Internal tamper 6 potential mode. + ITAMP6POM: u1, + /// Internal tamper 7 potential mode. + ITAMP7POM: u1, + /// Internal tamper 8 potential mode. + ITAMP8POM: u1, + /// Internal tamper 9 potential mode. + ITAMP9POM: u1, + reserved10: u1, + /// Internal tamper 11 potential mode. + ITAMP11POM: u1, + /// Internal tamper 12 potential mode. + ITAMP12POM: u1, + /// Internal tamper 13 potential mode. + ITAMP13POM: u1, reserved14: u1, - /// USART1 reset - USART1RST: u1, - reserved16: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - reserved22: u3, - /// Debug MCU reset - DBGMCURST: u1, - padding: u9, + /// Internal tamper 15 potential mode. + ITAMP15POM: u1, + padding: u17, }), - /// APB1 peripheral reset register (RCC_APB1RSTR) - APB1RSTR: mmio.Mmio(packed struct(u32) { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - reserved4: u2, - /// Timer 6 reset - TIM6RST: u1, - /// TIM7 timer reset - TIM7RST: u1, - reserved8: u2, - /// Timer 14 reset - TIM14RST: u1, - reserved11: u2, - /// Window watchdog reset - WWDGRST: u1, - reserved14: u2, - /// SPI2 reset - SPI2RST: u1, - reserved17: u2, - /// USART 2 reset - USART2RST: u1, - /// USART3 reset - USART3RST: u1, - /// USART4 reset - USART4RST: u1, - /// USART5 reset - USART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// USB interface reset - USBRST: u1, - reserved25: u1, - /// CAN interface reset - CANRST: u1, - reserved27: u1, - /// Clock Recovery System interface reset - CRSRST: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - /// HDMI CEC reset - CECRST: u1, - padding: u1, + /// TAMP filter control register. + FLTCR: mmio.Mmio(packed struct(u32) { + /// Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled. + TAMPFREQ: u3, + /// TAMP_INx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs. + TAMPFLT: u2, + /// TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs. + TAMPPRCH: u2, + /// TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each sample. + TAMPPUDIS: u1, + padding: u24, }), - /// AHB Peripheral Clock enable register (RCC_AHBENR) - AHBENR: mmio.Mmio(packed struct(u32) { - /// DMA clock enable - DMAEN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// SRAM interface clock enable - SRAMEN: u1, - reserved4: u1, - /// FLASH clock enable - FLASHEN: u1, - reserved6: u1, - /// CRC clock enable - CRCEN: u1, - reserved17: u10, - /// I/O port A clock enable - GPIOAEN: u1, - /// I/O port B clock enable - GPIOBEN: u1, - /// I/O port C clock enable - GPIOCEN: u1, - /// I/O port D clock enable - GPIODEN: u1, - /// I/O port E clock enable - GPIOEEN: u1, - /// I/O port F clock enable - GPIOFEN: u1, - reserved24: u1, - /// Touch sensing controller clock enable - TSCEN: u1, - padding: u7, + /// TAMP active tamper control register 1. + ATCR1: mmio.Mmio(packed struct(u32) { + /// Tamper x active mode. (x=1-8) + TAMPAM: u1, + reserved8: u7, + /// Active tamper shared output x selection The selected output must be available in the package pinout. (x=1-4) + ATOSEL: u2, + reserved16: u6, + /// Active tamper RTC asynchronous prescaler clock selection These bits selects the RTC asynchronous prescaler stage output.The selected clock is CK_ATPRE. fCK_ATPRE = fRTCCLK / 2ATCKSEL when (PREDIV_A+1) = 128. ... These bits can be written only when all active tampers are disabled. The write protection remains for up to 1.5 ck_atpre cycles after all the active tampers are disable. + ATCKSEL: u3, + reserved24: u5, + /// Active tamper output change period The tamper output is changed every CK_ATPER = (2ATPER x CK_ATPRE) cycles. Refer to. + ATPER: u3, + reserved30: u3, + /// Active tamper output sharing TAMP_IN1 is compared with TAMPOUTSEL1 TAMP_IN2 is compared with TAMPOUTSEL2 TAMP_IN3 is compared with TAMPOUTSEL3 TAMP_IN4 is compared with TAMPOUTSEL4 TAMP_IN5 is compared with TAMPOUTSEL5 TAMP_IN6 is compared with TAMPOUTSEL6 TAMP_IN7 is compared with TAMPOUTSEL7 TAMP_IN8 is compared with TAMPOUTSEL8. + ATOSHARE: u1, + /// Active tamper filter enable. + FLTEN: u1, + }), + /// TAMP active tamper seed register. + ATSEEDR: u32, + /// TAMP active tamper output register. + ATOR: mmio.Mmio(packed struct(u32) { + /// Pseudo-random generator value This field provides the values of the PRNG output. Because of potential inconsistencies due to synchronization delays, PRNG must be read at least twice. The read value is correct if it is equal to previous read value. This field can only be read when the APB is in secure mode. + PRNG: u8, + reserved14: u6, + /// Seed running flag This flag is set by hardware when a new seed is written in the TAMP_ATSEEDR. It is cleared by hardware when the PRNG has absorbed this new seed, and by system reset. The TAMP APB cock must not be switched off as long as SEEDF is set. + SEEDF: u1, + /// Active tamper initialization status This flag is set by hardware when the PRNG has absorbed the first 128-bit seed, meaning that the enabled active tampers are functional. This flag is cleared when the active tampers are disabled. + INITS: u1, + padding: u16, + }), + /// TAMP active tamper control register 2. + ATCR2: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// Active tamper shared output x selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSELx[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. (x=1-8) + ATOSEL: u3, + padding: u21, }), - /// APB2 peripheral clock enable register (RCC_APB2ENR) - APB2ENR: mmio.Mmio(packed struct(u32) { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved5: u4, - /// USART6 clock enable - USART6EN: u1, - /// USART7 clock enable - USART7EN: u1, - /// USART8 clock enable - USART8EN: u1, - reserved9: u1, - /// ADC 1 interface clock enable - ADCEN: u1, - reserved11: u1, - /// TIM1 Timer clock enable - TIM1EN: u1, - /// SPI 1 clock enable - SPI1EN: u1, - reserved14: u1, - /// USART1 clock enable - USART1EN: u1, - reserved16: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - reserved22: u3, - /// MCU debug module clock enable - DBGMCUEN: u1, - padding: u9, + /// TAMP secure mode register. + SECCFGR: mmio.Mmio(packed struct(u32) { + /// Backup registers read/write protection offset Protection zone 1 is defined for backup registers from TAMP_BKP0R to TAMP_BKPxR (x = BKPRWSEC-1, from 0 to 128). if TZEN=1, these backup registers can be read and written only with secure access. If TZEN=0: the protection zone 1 can be read and written with non-secure access. If BKPRWSEC = 0: there is no protection zone 1. If BKPRWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode. + BKPRWSEC: u8, + reserved15: u7, + /// Monotonic counter 1 secure protection. + CNT1SEC: u1, + /// Backup registers write protection offset Protection zone 2 is defined for backup registers from TAMP_BKPyR (y = BKPRWSEC, from 0 to 128) to TAMP_BKPzR (z = BKPWSEC-1, from 0 to 128, BKPWSEC ≥ BKPRWSEC): if TZEN=1, these backup registers can be written only with secure access. They can be read with secure or non-secure access. Protection zone 3 defined for backup registers from TAMP_BKPtR (t = BKPWSEC, from 0 to 127). They can be read or written with secure or non-secure access. If TZEN=0: the protection zone 2 can be read and written with non-secure access. If BKPWSEC = 0 or if BKPWSEC ≤ BKPRWSEC: there is no protection zone 2. If BKPWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode. + BKPWSEC: u8, + reserved30: u6, + /// Boot hardware key lock This bit can be read and can only be written to 1 by software. It is cleared by hardware together with the backup registers following a tamper detection event or when the readout protection (RDP) is disabled. + BHKLOCK: u1, + /// Tamper protection (excluding monotonic counters and backup registers) Note: Refer to for details on the read protection. + TAMPSEC: u1, }), - /// APB1 peripheral clock enable register (RCC_APB1ENR) - APB1ENR: mmio.Mmio(packed struct(u32) { - /// Timer 2 clock enable - TIM2EN: u1, - /// Timer 3 clock enable - TIM3EN: u1, - reserved4: u2, - /// Timer 6 clock enable - TIM6EN: u1, - /// TIM7 timer clock enable - TIM7EN: u1, - reserved8: u2, - /// Timer 14 clock enable - TIM14EN: u1, - reserved11: u2, - /// Window watchdog clock enable - WWDGEN: u1, - reserved14: u2, - /// SPI 2 clock enable - SPI2EN: u1, - reserved17: u2, - /// USART 2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// USART4 clock enable - USART4EN: u1, - /// USART5 clock enable - USART5EN: u1, - /// I2C 1 clock enable - I2C1EN: u1, - /// I2C 2 clock enable - I2C2EN: u1, - /// USB interface clock enable - USBEN: u1, - reserved25: u1, - /// CAN interface clock enable - CANEN: u1, - reserved27: u1, - /// Clock Recovery System interface clock enable - CRSEN: u1, - /// Power interface clock enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - /// HDMI CEC interface clock enable - CECEN: u1, + /// TAMP privilege mode control register. + PRIVCFGR: mmio.Mmio(packed struct(u32) { + reserved15: u15, + /// Monotonic counter 1 privilege protection. + CNT1PRIV: u1, + reserved29: u13, + /// Backup registers zone 1 privilege protection. + BKPRWPRIV: u1, + /// Backup registers zone 2 privilege protection. + BKPWPRIV: u1, + /// Tamper privilege protection (excluding backup registers) Note: Refer to for details on the read protection. + TAMPPRIV: u1, + }), + reserved44: [4]u8, + /// TAMP interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// Tamper x interrupt enable. (x=1-8) + TAMPIE: u1, + reserved16: u15, + /// Internal tamper 1 interrupt enable. + ITAMP1IE: u1, + /// Internal tamper 2 interrupt enable. + ITAMP2IE: u1, + /// Internal tamper 3 interrupt enable. + ITAMP3IE: u1, + /// Internal tamper 4 interrupt enable. + ITAMP4IE: u1, + /// Internal tamper 5 interrupt enable. + ITAMP5IE: u1, + /// Internal tamper 6 interrupt enable. + ITAMP6IE: u1, + /// Internal tamper 7 interrupt enable. + ITAMP7IE: u1, + /// Internal tamper 8 interrupt enable. + ITAMP8IE: u1, + /// Internal tamper 9 interrupt enable. + ITAMP9IE: u1, + reserved26: u1, + /// Internal tamper 11 interrupt enable. + ITAMP11IE: u1, + /// Internal tamper 12 interrupt enable. + ITAMP12IE: u1, + /// Internal tamper 13 interrupt enable. + ITAMP13IE: u1, + reserved30: u1, + /// Internal tamper 15 interrupt enable. + ITAMP15IE: u1, padding: u1, }), - /// Backup domain control register (RCC_BDCR) - BDCR: mmio.Mmio(packed struct(u32) { - /// External Low Speed oscillator enable - LSEON: u1, - /// External Low Speed oscillator ready - LSERDY: u1, - /// External Low Speed oscillator bypass - LSEBYP: u1, - /// LSE oscillator drive capability - LSEDRV: packed union { - raw: u2, - value: LSEDRV, - }, - reserved8: u3, - /// RTC clock source selection - RTCSEL: packed union { - raw: u2, - value: RTCSEL, - }, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software reset - BDRST: u1, - padding: u15, + /// TAMP status register. + SR: mmio.Mmio(packed struct(u32) { + /// TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. (x=1-8) + TAMPF: u1, + reserved16: u15, + /// Internal tamper 1 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 1. + ITAMP1F: u1, + /// Internal tamper 2 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 2. + ITAMP2F: u1, + /// Internal tamper 3 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 3. + ITAMP3F: u1, + /// Internal tamper 4 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 4. + ITAMP4F: u1, + /// Internal tamper 5 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 5. + ITAMP5F: u1, + /// Internal tamper 6 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6. + ITAMP6F: u1, + /// Internal tamper 7 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 7. + ITAMP7F: u1, + /// Internal tamper 8 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 8. + ITAMP8F: u1, + /// Internal tamper 9 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 9. + ITAMP9F: u1, + reserved26: u1, + /// Internal tamper 11 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 11. + ITAMP11F: u1, + /// Internal tamper 12 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 12. + ITAMP12F: u1, + /// Internal tamper 13 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 13. + ITAMP13F: u1, + reserved30: u1, + /// Internal tamper 15 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 15. + ITAMP15F: u1, + padding: u1, }), - /// Control/status register (RCC_CSR) - CSR: mmio.Mmio(packed struct(u32) { - /// Internal low speed oscillator enable - LSION: u1, - /// Internal low speed oscillator ready - LSIRDY: u1, - reserved23: u21, - /// 1.8 V domain reset flag - V18PWRRSTF: u1, - /// Remove reset flag - RMVF: u1, - /// Option byte loader reset flag - OBLRSTF: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, + /// TAMP non-secure masked interrupt status register. + MISR: mmio.Mmio(packed struct(u32) { + /// TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised. + TAMPMF: u1, + reserved16: u15, + /// Internal tamper 1 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 1 non-secure interrupt is raised. + ITAMP1MF: u1, + /// Internal tamper 2 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 2 non-secure interrupt is raised. + ITAMP2MF: u1, + /// Internal tamper 3 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 3 non-secure interrupt is raised. + ITAMP3MF: u1, + /// Internal tamper 4 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 4 non-secure interrupt is raised. + ITAMP4MF: u1, + /// Internal tamper 5 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 5 non-secure interrupt is raised. + ITAMP5MF: u1, + /// Internal tamper 6 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 6 non-secure interrupt is raised. + ITAMP6MF: u1, + /// Internal tamper 7 tamper non-secure interrupt masked flag This flag is set by hardware when the internal tamper 7 non-secure interrupt is raised. + ITAMP7MF: u1, + /// Internal tamper 8 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 8 non-secure interrupt is raised. + ITAMP8MF: u1, + /// internal tamper 9 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 9 non-secure interrupt is raised. + ITAMP9MF: u1, + reserved26: u1, + /// internal tamper 11 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 11 non-secure interrupt is raised. + ITAMP11MF: u1, + /// internal tamper 12 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 12 non-secure interrupt is raised. + ITAMP12MF: u1, + /// internal tamper 13 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 13 non-secure interrupt is raised. + ITAMP13MF: u1, + reserved30: u1, + /// internal tamper 15 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 15 non-secure interrupt is raised. + ITAMP15MF: u1, + padding: u1, }), - /// AHB peripheral reset register - AHBRSTR: mmio.Mmio(packed struct(u32) { - reserved17: u17, - /// I/O port A reset - GPIOARST: u1, - /// I/O port B reset - GPIOBRST: u1, - /// I/O port C reset - GPIOCRST: u1, - /// I/O port D reset - GPIODRST: u1, - /// I/O port E reset - GPIOERST: u1, - /// I/O port F reset - GPIOFRST: u1, - reserved24: u1, - /// Touch sensing controller reset - TSCRST: u1, - padding: u7, + /// TAMP secure masked interrupt status register. + SMISR: mmio.Mmio(packed struct(u32) { + /// TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper x secure interrupt is raised. (x=1-8) + TAMPMF: u1, + reserved16: u15, + /// Internal tamper 1 secure interrupt masked flag This flag is set by hardware when the internal tamper 1 secure interrupt is raised. + ITAMP1MF: u1, + /// Internal tamper 2 secure interrupt masked flag This flag is set by hardware when the internal tamper 2 secure interrupt is raised. + ITAMP2MF: u1, + /// Internal tamper 3 secure interrupt masked flag This flag is set by hardware when the internal tamper 3 secure interrupt is raised. + ITAMP3MF: u1, + /// Internal tamper 4 secure interrupt masked flag This flag is set by hardware when the internal tamper 4 secure interrupt is raised. + ITAMP4MF: u1, + /// Internal tamper 5 secure interrupt masked flag This flag is set by hardware when the internal tamper 5 secure interrupt is raised. + ITAMP5MF: u1, + /// Internal tamper 6 secure interrupt masked flag This flag is set by hardware when the internal tamper 6 secure interrupt is raised. + ITAMP6MF: u1, + /// Internal tamper 7 secure interrupt masked flag This flag is set by hardware when the internal tamper 7 secure interrupt is raised. + ITAMP7MF: u1, + /// Internal tamper 8 secure interrupt masked flag This flag is set by hardware when the internal tamper 8 secure interrupt is raised. + ITAMP8MF: u1, + /// internal tamper 9 secure interrupt masked flag This flag is set by hardware when the internal tamper 9 secure interrupt is raised. + ITAMP9MF: u1, + reserved26: u1, + /// internal tamper 11 secure interrupt masked flag This flag is set by hardware when the internal tamper 11 secure interrupt is raised. + ITAMP11MF: u1, + /// internal tamper 12 secure interrupt masked flag This flag is set by hardware when the internal tamper 12 secure interrupt is raised. + ITAMP12MF: u1, + /// internal tamper 13 secure interrupt masked flag This flag is set by hardware when the internal tamper 13 secure interrupt is raised. + ITAMP13MF: u1, + reserved30: u1, + /// internal tamper 15 secure interrupt masked flag This flag is set by hardware when the internal tamper 15 secure interrupt is raised. + ITAMP15MF: u1, + padding: u1, }), - /// Clock configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - /// PREDIV division factor - PREDIV: packed union { - raw: u4, - value: PREDIV, - }, - padding: u28, + /// TAMP status clear register. + SCR: mmio.Mmio(packed struct(u32) { + /// Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the TAMP_SR register. (x=1-8) + CTAMPF: u1, + reserved16: u15, + /// Clear ITAMP1 detection flag Writing 1 in this bit clears the ITAMP1F bit in the TAMP_SR register. + CITAMP1F: u1, + /// Clear ITAMP2 detection flag Writing 1 in this bit clears the ITAMP2F bit in the TAMP_SR register. + CITAMP2F: u1, + /// Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register. + CITAMP3F: u1, + /// Clear ITAMP4 detection flag Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register. + CITAMP4F: u1, + /// Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register. + CITAMP5F: u1, + /// Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register. + CITAMP6F: u1, + /// Clear ITAMP7 detection flag Writing 1 in this bit clears the ITAMP7F bit in the TAMP_SR register. + CITAMP7F: u1, + /// Clear ITAMP8 detection flag Writing 1 in this bit clears the ITAMP8F bit in the TAMP_SR register. + CITAMP8F: u1, + /// Clear ITAMP9 detection flag Writing 1 in this bit clears the ITAMP9F bit in the TAMP_SR register. + CITAMP9F: u1, + reserved26: u1, + /// Clear ITAMP11 detection flag Writing 1 in this bit clears the ITAMP11F bit in the TAMP_SR register. + CITAMP11F: u1, + /// Clear ITAMP12 detection flag Writing 1 in this bit clears the ITAMP12F bit in the TAMP_SR register. + CITAMP12F: u1, + /// Clear ITAMP13 detection flag Writing 1 in this bit clears the ITAMP13F bit in the TAMP_SR register. + CITAMP13F: u1, + reserved30: u1, + /// Clear ITAMP15 detection flag Writing 1 in this bit clears the ITAMP15F bit in the TAMP_SR register. + CITAMP15F: u1, + padding: u1, }), - /// Clock configuration register 3 - CFGR3: mmio.Mmio(packed struct(u32) { - /// USART1 clock source selection - USART1SW: packed union { - raw: u2, - value: USART1SW, - }, - reserved4: u2, - /// I2C1 clock source selection - I2C1SW: packed union { - raw: u1, - value: ICSW, - }, - reserved6: u1, - /// HDMI CEC clock source selection - CECSW: packed union { - raw: u1, - value: CECSW, - }, - /// USB clock source selection - USBSW: packed union { - raw: u1, - value: USBSW, - }, - /// ADCSW is deprecated. See ADC field in CFGR2 register. - ADCSW: u1, - reserved16: u7, - /// USART2 clock source selection - USART2SW: packed union { - raw: u2, - value: USARTSW, - }, - /// USART3 clock source - USART3SW: packed union { - raw: u2, - value: USARTSW, - }, - padding: u12, + /// TAMP monotonic counter 1 register. + COUNT1R: u32, + reserved80: [12]u8, + /// TAMP option register. + OR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// TAMP_OUT3 mapping. + OUT3_RMP: u2, + /// TAMP_OUT5 mapping. + OUT5_RMP: u1, + reserved8: u4, + /// TAMP_IN2 mapping. + IN2_RMP: u1, + /// TAMP_IN3 mapping. + IN3_RMP: u1, + /// TAMP_IN4 mapping. + IN4_RMP: u1, + padding: u21, }), - /// Clock control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// HSI14 clock enable - HSI14ON: u1, - /// HR14 clock ready flag - HSI14RDY: u1, - /// HSI14 clock request from ADC disable - HSI14DIS: u1, - /// HSI14 clock trimming - HSI14TRIM: u5, - /// HSI14 clock calibration - HSI14CAL: u8, - padding: u16, + /// TAMP resources protection configuration register. + RPCFGR: mmio.Mmio(packed struct(u32) { + /// Configurable resource 0 protection. + RPCFG0: u1, + padding: u31, }), + reserved256: [168]u8, + /// TAMP backup x register. (x=0-31) + BKPR: [32]u32, }; }; - pub const sai_v2 = struct { - pub const CKSTR = enum(u1) { - /// Data strobing edge is falling edge of SCK - FallingEdge = 0x0, - /// Data strobing edge is rising edge of SCK - RisingEdge = 0x1, - }; - - pub const CNRDY = enum(u1) { - /// External AC’97 Codec is ready - Ready = 0x0, - /// External AC’97 Codec is not ready - NotReady = 0x1, - }; - - pub const COMP = enum(u2) { - /// No companding algorithm - NoCompanding = 0x0, - /// μ-Law algorithm - MuLaw = 0x2, - /// A-Law algorithm - ALaw = 0x3, - _, - }; - - pub const CPL = enum(u1) { - /// 1’s complement representation - OnesComplement = 0x0, - /// 2’s complement representation - TwosComplement = 0x1, - }; - - pub const DS = enum(u3) { - /// 8 bits - Bit8 = 0x2, - /// 10 bits - Bit10 = 0x3, - /// 16 bits - Bit16 = 0x4, - /// 20 bits - Bit20 = 0x5, - /// 24 bits - Bit24 = 0x6, - /// 32 bits - Bit32 = 0x7, - _, - }; - - pub const FLVL = enum(u3) { - /// FIFO empty - Empty = 0x0, - /// FIFO <= 1⁄4 but not empty - Quarter1 = 0x1, - /// 1⁄4 < FIFO <= 1⁄2 - Quarter2 = 0x2, - /// 1⁄2 < FIFO <= 3⁄4 - Quarter3 = 0x3, - /// 3⁄4 < FIFO but not full - Quarter4 = 0x4, - /// FIFO full - Full = 0x5, - _, - }; - - pub const FSOFF = enum(u1) { - /// FS is asserted on the first bit of the slot 0 - OnFirst = 0x0, - /// FS is asserted one bit before the first bit of the slot 0 - BeforeFirst = 0x1, - }; - - pub const FSPOL = enum(u1) { - /// FS is active low (falling edge) - FallingEdge = 0x0, - /// FS is active high (rising edge) - RisingEdge = 0x1, - }; - - pub const FTH = enum(u3) { - /// FIFO empty - Empty = 0x0, - /// 1⁄4 FIFO - Quarter1 = 0x1, - /// 1⁄2 FIFO - Quarter2 = 0x2, - /// 3⁄4 FIFO - Quarter3 = 0x3, - /// FIFO full - Full = 0x4, - _, - }; - - pub const LSBFIRST = enum(u1) { - /// Data are transferred with MSB first - MsbFirst = 0x0, - /// Data are transferred with LSB first - LsbFirst = 0x1, - }; - - pub const MODE = enum(u2) { - /// Master transmitter - MasterTx = 0x0, - /// Master receiver - MasterRx = 0x1, - /// Slave transmitter - SlaveTx = 0x2, - /// Slave receiver - SlaveRx = 0x3, - }; - - pub const MONO = enum(u1) { - /// Stereo mode - Stereo = 0x0, - /// Mono mode - Mono = 0x1, - }; - - pub const MUTEVAL = enum(u1) { - /// Bit value 0 is sent during the mute mode - SendZero = 0x0, - /// Last values are sent during the mute mode - SendLast = 0x1, - }; - - pub const NODIV = enum(u1) { - /// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value - MasterClock = 0x0, - /// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. - NoDiv = 0x1, - }; - - pub const OUTDRIV = enum(u1) { - /// Audio block output driven when SAIEN is set - OnStart = 0x0, - /// Audio block output driven immediately after the setting of this bit - Immediately = 0x1, - }; - - pub const PRTCFG = enum(u2) { - /// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol - Free = 0x0, - /// SPDIF protocol - Spdif = 0x1, - /// AC’97 protocol - Ac97 = 0x2, - _, - }; - - pub const SLOTEN = enum(u16) { - /// Inactive slot - Inactive = 0x0, - /// Active slot - Active = 0x1, - _, - }; - - pub const SLOTSZ = enum(u2) { - /// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) - DataSize = 0x0, - /// 16-bit - Bit16 = 0x1, - /// 32-bit - Bit32 = 0x2, - _, - }; - - pub const SYNCEN = enum(u2) { - /// audio sub-block in asynchronous mode - Asynchronous = 0x0, - /// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode - Internal = 0x1, - /// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode - External = 0x2, - _, - }; - - pub const WCKCFG = enum(u1) { - /// Clock configuration is correct - Correct = 0x0, - /// Clock configuration does not respect the rule concerning the frame length specification - Wrong = 0x1, - }; - - /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - pub const CH = extern struct { - /// Configuration register 1 + pub const tamp_l5 = struct { + /// Tamper and backup registers + pub const TAMP = extern struct { + /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - /// SAIx audio block mode immediately - MODE: packed union { - raw: u2, - value: MODE, - }, - /// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. - PRTCFG: packed union { - raw: u2, - value: PRTCFG, - }, - reserved5: u1, - /// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. - DS: packed union { - raw: u3, - value: DS, - }, - /// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. - LSBFIRST: packed union { - raw: u1, - value: LSBFIRST, - }, - /// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. - CKSTR: packed union { - raw: u1, - value: CKSTR, - }, - /// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. - SYNCEN: packed union { - raw: u2, - value: SYNCEN, - }, - /// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. - MONO: packed union { - raw: u1, - value: MONO, - }, - /// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. - OUTDRIV: packed union { - raw: u1, - value: OUTDRIV, - }, - reserved16: u2, - /// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. - SAIEN: u1, - /// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. - DMAEN: u1, - reserved19: u1, - /// No fixed divider between MCLK and FS - NODIV: packed union { - raw: u1, - value: NODIV, - }, - /// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: - MCKDIV: u4, - padding: u8, + /// TAMPE + TAMPE: u1, + reserved16: u15, + /// ITAMPE + ITAMPE: u1, + padding: u15, }), - /// Configuration register 2 + /// control register 2 CR2: mmio.Mmio(packed struct(u32) { - /// FIFO threshold. This bit is set and cleared by software. - FTH: packed union { - raw: u3, - value: FTH, - }, - /// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. - FFLUSH: u1, - /// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. - TRIS: u1, - /// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. - MUTE: u1, - /// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. - MUTEVAL: packed union { - raw: u1, - value: MUTEVAL, - }, - /// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. - MUTECNT: u6, - /// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. - CPL: packed union { - raw: u1, - value: CPL, - }, - /// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. - COMP: packed union { - raw: u2, - value: COMP, - }, - padding: u16, + /// Tamper X no erase + TAMPNOER: u1, + reserved16: u15, + /// Tamper X mask + TAMPMSK: u1, + reserved23: u6, + /// BKERASE + BKERASE: u1, + /// Active level for tamper X input + TAMPTRG: u1, + padding: u7, }), - /// This register has no meaning in AC97 and SPDIF audio protocol - FRCR: mmio.Mmio(packed struct(u32) { - /// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. - FRL: u8, - /// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. - FSALL: u7, - reserved16: u1, - /// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. - FSDEF: u1, - /// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - FSPOL: packed union { - raw: u1, - value: FSPOL, - }, - /// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - FSOFF: packed union { - raw: u1, - value: FSOFF, - }, - padding: u13, + /// control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Internal Tamper X no erase + ITAMPNOER: u1, + padding: u31, }), - /// This register has no meaning in AC97 and SPDIF audio protocol - SLOTR: mmio.Mmio(packed struct(u32) { - /// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - FBOFF: u5, - reserved6: u1, - /// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - SLOTSZ: packed union { - raw: u2, - value: SLOTSZ, - }, - /// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - NBSLOT: u4, - reserved16: u4, - /// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - SLOTEN: packed union { - raw: u16, - value: SLOTEN, - }, + /// TAMP filter control register + FLTCR: mmio.Mmio(packed struct(u32) { + /// TAMPFREQ + TAMPFREQ: u3, + /// TAMPFLT + TAMPFLT: u2, + /// TAMPPRCH + TAMPPRCH: u2, + /// TAMPPUDIS + TAMPPUDIS: u1, + padding: u24, }), - /// Interrupt mask register 2 - IM: mmio.Mmio(packed struct(u32) { - /// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. - OVRUDRIE: u1, - /// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. - MUTEDETIE: u1, - /// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. - WCKCFGIE: u1, - /// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, - FREQIE: u1, - /// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. - CNRDYIE: u1, - /// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. - AFSDETIE: u1, - /// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. - LFSDETIE: u1, - padding: u25, + /// TAMP active tamper control register 1 + ATCR1: mmio.Mmio(packed struct(u32) { + /// TAMPAM + TAMPAM: u1, + reserved8: u7, + /// ATOSEL + ATOSEL: u2, + reserved16: u6, + /// ATCKSEL + ATCKSEL: u2, + reserved24: u6, + /// ATPER + ATPER: u2, + reserved30: u4, + /// ATOSHARE + ATOSHARE: u1, + /// FLTEN + FLTEN: u1, }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. - OVRUDR: u1, - /// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. - MUTEDET: u1, - /// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. - WCKCFG: packed union { - raw: u1, - value: WCKCFG, - }, - /// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. - FREQ: u1, - /// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. - CNRDY: packed union { - raw: u1, - value: CNRDY, - }, - /// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. - AFSDET: u1, - /// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register - LFSDET: u1, - reserved16: u9, - /// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: - FLVL: packed union { - raw: u3, - value: FLVL, - }, - padding: u13, + /// TAMP active tamper seed register + ATSEEDR: mmio.Mmio(packed struct(u32) { + /// Pseudo-random generator seed value + SEED: u32, }), - /// Clear flag register - CLRFR: mmio.Mmio(packed struct(u32) { - /// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. - COVRUDR: u1, - /// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. - CMUTEDET: u1, - /// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. - CWCKCFG: u1, - reserved4: u1, - /// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. - CCNRDY: u1, - /// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. - CAFSDET: u1, - /// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. - CLFSDET: u1, - padding: u25, + /// TAMP active tamper output register + ATOR: mmio.Mmio(packed struct(u32) { + /// Pseudo-random generator value + PRNG: u8, + reserved14: u6, + /// Seed running flag + SEEDF: u1, + /// Active tamper initialization status + INITS: u1, + padding: u16, }), - /// Data register - DR: mmio.Mmio(packed struct(u32) { - /// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. - DATA: u32, + /// TAMP active tamper control register 2 + ATCR2: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// ATOSEL + ATOSEL: u3, + padding: u21, }), - }; - - /// Serial audio interface - pub const SAI = extern struct { - /// Global configuration register - GCR: mmio.Mmio(packed struct(u32) { - /// Synchronization inputs - SYNCIN: u2, - reserved4: u2, - /// Synchronization outputs These bits are set and cleared by software. - SYNCOUT: u2, - padding: u26, + /// TAMP secure mode register + SMCR: mmio.Mmio(packed struct(u32) { + /// Backup registers read/write protection offset + BKPRWDPROT: u8, + reserved16: u8, + /// Backup registers write protection offset + BKPWDPROT: u8, + reserved31: u7, + /// Tamper protection + TAMPDPROT: u1, }), - /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - CH: u32, - }; - }; - - pub const pwr_f4 = struct { - pub const PDDS = enum(u1) { - /// Enter Stop mode when the CPU enters deepsleep - STOP_MODE = 0x0, - /// Enter Standby mode when the CPU enters deepsleep - STANDBY_MODE = 0x1, - }; - - pub const VOS = enum(u2) { - /// Scale 3 mode (STM32F4[23] ONLY) - SCALE3 = 0x1, - /// Scale 2 mode - SCALE2 = 0x2, - /// Scale 1 mode (reset value) - SCALE1 = 0x3, - _, - }; - - /// Power control - pub const PWR = extern struct { - /// power control register - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power deep sleep - LPDS: u1, - /// Power down deepsleep - PDDS: packed union { - raw: u1, - value: PDDS, - }, - /// Clear wakeup flag - CWUF: u1, - /// Clear standby flag - CSBF: u1, - /// Power voltage detector enable - PVDE: u1, - /// PVD level selection - PLS: u3, - /// Disable backup domain write protection - DBP: u1, - /// Flash power down in Stop mode - FPDS: u1, - /// Low-Power Regulator Low Voltage in deepsleep - LPLVDS: u1, - /// Main regulator low voltage in deepsleep mode - MRLVDS: u1, - reserved13: u1, - /// ADCDC1 - ADCDC1: u1, - /// Regulator voltage scaling output selection - VOS: packed union { - raw: u2, - value: VOS, - }, - /// Over-drive enable (STM32F4[23] ONLY) - ODEN: u1, - /// Over-drive switching enabled (STM32F4[23] ONLY) - ODSWEN: u1, - /// Under-drive enable in stop mode (STM32F4[23] ONLY) - UDEN: u2, - /// Flash Memory Stop while System Run - FMSSR: u1, - /// Flash Interface Stop while System Run - FISSR: u1, - padding: u10, + /// TAMP privilege mode control register + PRIVCR: mmio.Mmio(packed struct(u32) { + reserved29: u29, + /// Backup registers zone 1 privilege protection + BKPRWPRIV: u1, + /// Backup registers zone 2 privilege protection + BKPWPRIV: u1, + /// Tamper privilege protection + TAMPPRIV: u1, }), - /// power control/status register - CSR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag - WUF: u1, - /// Standby flag - SBF: u1, - /// PVD output - PVDO: u1, - /// Backup regulator ready - BRR: u1, - reserved7: u3, - /// Enable WKUP2 pin - EWUP2: u1, - /// Enable WKUP pin - EWUP: u1, - /// Backup regulator enable - BRE: u1, - reserved14: u4, - /// Regulator voltage scaling output selection ready bit (STM32F4[23] ONLY) - VOSRDY: u1, - reserved16: u1, - /// Over-drive mode ready (STM32F4[23] ONLY) - ODRDY: u1, - /// Over-drive mode switching ready (STM32F4[23] ONLY) - ODSWRDY: u1, - /// Under-drive ready flag - UDRDY: u2, - padding: u12, + reserved44: [4]u8, + /// TAMP interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// Tamper X interrupt enable + TAMPIE: u1, + reserved16: u15, + /// Internal tamper X interrupt enable + ITAMPIE: u1, + padding: u15, + }), + /// TAMP status register + SR: mmio.Mmio(packed struct(u32) { + /// Tamper X detection flag + TAMPF: u1, + reserved16: u15, + /// Internal tamper X detection flag + ITAMPF: u1, + padding: u15, }), - }; - }; - - pub const hash_v1 = struct { - /// Hash processor. - pub const HASH = extern struct { - /// control register. - CR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Initialize message digest calculation. - INIT: u1, - /// DMA enable. - DMAE: u1, - /// Data type selection. - DATATYPE: u2, - /// Mode selection. - MODE: u1, - /// Algorithm selection. - ALGO: u1, - /// Number of words already pushed. - NBW: u4, - /// DIN not empty. - DINNE: u1, - reserved16: u3, - /// Long key selection. - LKEY: u1, + /// TAMP masked interrupt status register + MISR: mmio.Mmio(packed struct(u32) { + /// Tamper X interrupt masked flag + TAMPMF: u1, + reserved16: u15, + /// Internal tamper X interrupt masked flag + ITAMPMF: u1, padding: u15, }), - /// data input register. - DIN: u32, - /// start register. - STR: mmio.Mmio(packed struct(u32) { - /// Number of valid bits in the last word of the message. - NBLW: u5, - reserved8: u3, - /// Digest calculation. - DCAL: u1, - padding: u23, + /// TAMP secure masked interrupt status register + SMISR: mmio.Mmio(packed struct(u32) { + /// Tamper X interrupt masked flag + TAMPMF: u1, + reserved16: u15, + /// Internal tamper X interrupt masked flag + ITAMPMF: u1, + padding: u15, }), - /// digest registers. - HR: [5]u32, - /// interrupt enable register. - IMR: mmio.Mmio(packed struct(u32) { - /// Data input interrupt enable. - DINIE: u1, - /// Digest calculation completion interrupt enable. - DCIE: u1, - padding: u30, + /// TAMP status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear tamper X detection flag + CTAMPF: u1, + reserved16: u15, + /// Clear internal tamper X detection flag + CITAMPF: u1, + padding: u15, }), - /// status register. - SR: mmio.Mmio(packed struct(u32) { - /// Data input interrupt status. - DINIS: u1, - /// Digest calculation completion interrupt status. - DCIS: u1, - /// DMA Status. - DMAS: u1, - /// Busy bit. - BUSY: u1, + /// TAMP monotonic counter register + COUNTR: mmio.Mmio(packed struct(u32) { + /// COUNT + COUNT: u32, + }), + reserved80: [12]u8, + /// TAMP configuration register + CFGR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// TMONEN + TMONEN: u1, + /// VMONEN + VMONEN: u1, + /// WUTMONEN + WUTMONEN: u1, padding: u28, }), - reserved248: [208]u8, - /// context swap registers. - CSR: [51]u32, + reserved256: [172]u8, + /// TAMP backup register + BKPR: [32]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), }; }; - pub const rtc_v2f3 = struct { - pub const ALRMR_MSK = enum(u1) { - /// Alarm set if the date/day match - ToMatch = 0x0, - /// Date/day don’t care in Alarm comparison - NotMatch = 0x1, - }; - - pub const ALRMR_PM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, - }; - - pub const ALRMR_WDSEL = enum(u1) { - /// DU[3:0] represents the date units - DateUnits = 0x0, - /// DU[3:0] represents the week day. DT[1:0] is don’t care - WeekDay = 0x1, - }; - - pub const AMPM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, - }; - - pub const CALP = enum(u1) { - /// No RTCCLK pulses are added - NoChange = 0x0, - /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - IncreaseFreq = 0x1, - }; - - pub const CALW16 = enum(u1) { - /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 - Sixteen_Second = 0x1, - _, - }; - - pub const CALW8 = enum(u1) { - /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected - Eight_Second = 0x1, - _, - }; - - pub const COSEL = enum(u1) { - /// Calibration output is 512 Hz (with default prescaler setting) - CalFreq_512Hz = 0x0, - /// Calibration output is 1 Hz (with default prescaler setting) - CalFreq_1Hz = 0x1, - }; - - pub const FMT = enum(u1) { - /// 24 hour/day format - Twenty_Four_Hour = 0x0, - /// AM/PM hour format - AM_PM = 0x1, - }; - - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Alarm B output enabled - AlarmB = 0x2, - /// Wakeup output enabled - Wakeup = 0x3, - }; - - pub const PCMODE = enum(u1) { - /// PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode - Floating = 0x0, - /// PCx is forced to push-pull output if LSE is disabled - PushPull = 0x1, - }; - - pub const PCVALUE = enum(u1) { - /// If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low - Low = 0x0, - /// If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high - High = 0x1, - }; - - pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - Low = 0x1, - }; - - pub const RECALPF = enum(u1) { - /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 - Pending = 0x1, + pub const tamp_u5 = struct { + pub const ATCKSEL = enum(u3) { + /// RTCCLK is selected + Div1 = 0x0, + /// RTCCLK/2 is selected when (PREDIV_A+1) = 128 (actually selects 1st flip flop output) + Div2 = 0x1, + /// RTCCLK/4 is selected when (PREDIV_A+1) = 128 (actually selects 2nd flip flop output) + Div4 = 0x2, + /// RTCCLK/128 is selected when (PREDIV_A+1) = 128 (actually selects 7th flip flop output) + Div128 = 0x7, _, }; pub const TAMPFLT = enum(u2) { - /// Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) - Immediate = 0x0, - /// Tamper event is activated after 2 consecutive samples at the active level - Samples2 = 0x1, - /// Tamper event is activated after 4 consecutive samples at the active level - Samples4 = 0x2, - /// Tamper event is activated after 8 consecutive samples at the active level - Samples8 = 0x3, + /// Tamper event is activated on edge of INx input transitions to the active level (no internal pull-up on INx input). + NoFilter = 0x0, + /// Tamper event is activated after 2 consecutive samples at the active level. + Filter2 = 0x1, + /// Tamper event is activated after 4 consecutive samples at the active level. + Filter4 = 0x2, + /// Tamper event is activated after 8 consecutive samples at the active level. + Filter8 = 0x3, }; pub const TAMPFREQ = enum(u3) { /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) - Div32768 = 0x0, + Hz_1 = 0x0, /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) - Div16384 = 0x1, + Hz_2 = 0x1, /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) - Div8192 = 0x2, + Hz_4 = 0x2, /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) - Div4096 = 0x3, + Hz_8 = 0x3, /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) - Div2048 = 0x4, + Hz_16 = 0x4, /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) - Div1024 = 0x5, + Hz_32 = 0x5, /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) - Div512 = 0x6, + Hz_64 = 0x6, /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) - Div256 = 0x7, + Hz_128 = 0x7, }; pub const TAMPPRCH = enum(u2) { @@ -435068,2102 +433380,2295 @@ pub const types = struct { Cycles8 = 0x3, }; - pub const TAMPPUDIS = enum(u1) { - /// Precharge RTC_TAMPx pins before sampling (enable internal pull-up) - Enabled = 0x0, - /// Disable precharge of RTC_TAMPx pins - Disabled = 0x1, - }; - pub const TAMPTRG = enum(u1) { - /// If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. - RisingEdge = 0x0, - /// If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event - FallingEdge = 0x1, - }; - - pub const TSEDGE = enum(u1) { - /// RTC_TS input rising edge generates a time-stamp event - RisingEdge = 0x0, - /// RTC_TS input falling edge generates a time-stamp event - FallingEdge = 0x1, - }; - - pub const WUCKSEL = enum(u3) { - /// RTC/16 clock is selected - Div16 = 0x0, - /// RTC/8 clock is selected - Div8 = 0x1, - /// RTC/4 clock is selected - Div4 = 0x2, - /// RTC/2 clock is selected - Div2 = 0x3, - /// ck_spre (usually 1 Hz) clock is selected - ClockSpare = 0x4, - /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - ClockSpareWithOffset = 0x6, - _, + /// If TAMPFLT 00 Tamper 2 input staying low triggers a tamper detection event. + FilteredLowOrUnfilteredHigh = 0x0, + /// If TAMPFLT 00 Tamper 2 input staying high triggers a tamper detection event. + FilteredHighOrUnfilteredLow = 0x1, }; - /// Real-time clock - pub const RTC = extern struct { - /// Time register - TR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, - }), - /// Date register - DR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding: u8, - }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Wakeup clock selection - WUCKSEL: packed union { - raw: u3, - value: WUCKSEL, - }, - /// Timestamp event active edge - TSEDGE: packed union { - raw: u1, - value: TSEDGE, - }, - /// Reference clock detection enable (50 or 60 Hz) - REFCKON: u1, - /// Bypass the shadow registers - BYPSHAD: u1, - /// Hour format - FMT: packed union { - raw: u1, - value: FMT, - }, - reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, - /// Wakeup timer enable - WUTE: u1, - /// Timestamp enable - TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, - /// Wakeup timer interrupt enable - WUTIE: u1, - /// Timestamp interrupt enable - TSIE: u1, - /// Add 1 hour (summer time change) - ADD1H: u1, - /// Subtract 1 hour (winter time change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output selection - COSEL: packed union { - raw: u1, - value: COSEL, - }, - /// Output polarity - POL: packed union { - raw: u1, - value: POL, - }, - /// Output selection - OSEL: packed union { - raw: u2, - value: OSEL, - }, - /// Calibration output enable - COE: u1, - padding: u8, - }), - /// Initialization and status register - ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, - /// Wakeup timer write enabled - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Enter Initialization mode - INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, - /// Wakeup timer flag - WUTF: u1, - /// Timestamp flag - TSF: u1, - /// Timestamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, - /// Recalibration pending flag - RECALPF: packed union { - raw: u1, - value: RECALPF, - }, + /// Tamper and backup registers + pub const TAMP = extern struct { + /// TAMP control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Tamper detection on INx enable + TAMPE: u1, + reserved16: u15, + /// Internal tamper X enable + ITAMPE: u1, padding: u15, }), - /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, - padding: u9, - }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, - padding: u16, - }), - reserved28: [4]u8, - /// Alarm register - ALRMR: [2]mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm seconds mask - MSK1: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm minutes mask - MSK2: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: ALRMR_PM, - }, - /// Alarm hours mask - MSK3: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { - raw: u1, - value: ALRMR_WDSEL, - }, - /// Alarm date mask - MSK4: packed union { - raw: u1, - value: ALRMR_MSK, - }, - }), - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: u8, - padding: u24, - }), - /// Sub second register - SSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, - }), - /// Shift control register - SHIFTR: mmio.Mmio(packed struct(u32) { - /// Subtract a fraction of a second - SUBFS: u15, - reserved31: u16, - /// Add one second - ADD1S: u1, - }), - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: AMPM, - }, - padding: u9, - }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding: u16, - }), - /// Timestamp sub second register - TSSSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u16, - padding: u16, - }), - /// Calibration register - CALR: mmio.Mmio(packed struct(u32) { - /// Calibration minus - CALM: u9, - reserved13: u4, - /// Use a 16-second calibration cycle period - CALW16: packed union { - raw: u1, - value: CALW16, - }, - /// Use an 8-second calibration cycle period - CALW8: packed union { - raw: u1, - value: CALW8, - }, - /// Increase frequency of RTC by 488.5 ppm - CALP: packed union { - raw: u1, - value: CALP, - }, - padding: u16, - }), - /// Tamper and alternate function configuration register - TAFCR: mmio.Mmio(packed struct(u32) { - /// Tamper detection enable - TAMPE: u1, - /// Active level for tamper + /// TAMP control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Tamper X no erase + TAMPNOER: u1, + reserved16: u15, + /// Tamper X mask. The tamper 1 interrupt must not be enabled when TAMP1MSK is set. + TAMPMSK: u1, + reserved22: u5, + /// Backup registers and device secrets access blocked + BKBLOCK: u1, + /// Backup registers and device secrets erase. Writing '1 to this bit reset the backup registers and device secrets(1). Writing 0 has no effect. This bit is always read as 0. + BKERASE: u1, + /// Active level for tamper 1 input. TAMPTRG: packed union { raw: u1, value: TAMPTRG, }, - /// Tamper interrupt enable - TAMPIE: u1, - reserved7: u4, - /// Activate timestamp on tamper detection event - TAMPTS: u1, - /// Tamper sampling frequency + padding: u7, + }), + /// TAMP control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Internal Tamper X no erase + ITAMPNOER: u1, + padding: u31, + }), + /// TAMP filter control register + FLTCR: mmio.Mmio(packed struct(u32) { + /// Tamper sampling frequency. Determines the frequency at which each of the INx inputs are sampled. TAMPFREQ: packed union { raw: u3, value: TAMPFREQ, }, - /// Tamper filter count + /// INx filter count. These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the INx inputs. TAMPFLT: packed union { raw: u2, value: TAMPFLT, }, - /// Tamper precharge duration + /// INx precharge duration. These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the INx inputs. TAMPPRCH: packed union { raw: u2, value: TAMPPRCH, }, - /// Tamper pull-up disable - TAMPPUDIS: packed union { - raw: u1, - value: TAMPPUDIS, - }, - reserved18: u2, - /// PC13 value - PC13VALUE: packed union { - raw: u1, - value: PCVALUE, - }, - /// PC13 mode - PC13MODE: packed union { - raw: u1, - value: PCMODE, - }, - /// PC14 value - PC14VALUE: packed union { - raw: u1, - value: PCVALUE, - }, - /// PC14 mode - PC14MODE: packed union { - raw: u1, - value: PCMODE, - }, - /// PC15 value - PC15VALUE: packed union { - raw: u1, - value: PCVALUE, - }, - /// PC15 mode - PC15MODE: packed union { - raw: u1, - value: PCMODE, - }, - padding: u8, - }), - /// Alarm sub second register - ALRMSSR: [2]mmio.Mmio(packed struct(u32) { - /// Sub seconds value - SS: u15, - reserved24: u9, - /// Mask the most-significant bits starting at this bit - MASKSS: u4, - padding: u4, - }), - reserved80: [4]u8, - /// Backup register - BKPR: [32]mmio.Mmio(packed struct(u32) { - /// BKP - BKP: u32, + /// INx pull-up disable. This bit determines if each of the TAMPx pins are precharged before each sample. + TAMPPUDIS: u1, + padding: u24, }), - }; - }; - - pub const comp_v2 = struct { - pub const HYST = enum(u3) { - None = 0x0, - /// 10mV hysteresis - Hyst10m = 0x1, - /// 20mV hysteresis - Hyst20m = 0x2, - /// 30mV hysteresis - Hyst30m = 0x3, - /// 40mV hysteresis - Hyst40m = 0x4, - /// 50mV hysteresis - Hyst50m = 0x5, - /// 60mV hysteresis - Hyst60m = 0x6, - /// 70mV hysteresis - Hyst70m = 0x7, - }; - - pub const POLARITY = enum(u1) { - /// Non-inverted polarity - NonInverted = 0x0, - /// Inverted polarity - Inverted = 0x1, - }; - - /// Comparator v2. (RM0440 24) - pub const COMP = extern struct { - /// Comparator control and status register. - CSR: mmio.Mmio(packed struct(u32) { - /// COMP enable bit. - EN: u1, - reserved4: u3, - /// Comparator signal selector for inverting input INM. (RM0440 24.3.2 Table 197) - INMSEL: u3, - reserved8: u1, - /// Comparator signal selector for non-inverting input INP. (RM0440 24.3.2 Table 196) - INPSEL: u1, - reserved15: u6, - /// Comparator polarity selector. - POLARITY: packed union { - raw: u1, - value: POLARITY, - }, - /// Comparator hysteresis selector. - HYST: packed union { + /// TAMP active tamper control register 1 + ATCR1: mmio.Mmio(packed struct(u32) { + /// Tamper X active mode + TAMPAM: u1, + reserved8: u7, + /// Active tamper shared output X selection. The selected output must be available in the package pinout + ATOSEL: u2, + reserved16: u6, + /// Active tamper RTC asynchronous prescaler clock selection. These bits selects the RTC asynchronous prescaler stage output.The selected clock is CK_ATPRE.. fCK_ATPRE = fRTCCLK / 2ATCKSEL when (PREDIV_A+1) = 128.. .... These bits can be written only when all active tampers are disabled. The write protection remains for up to 1.5 ck_atpre cycles after all the active tampers are disable. + ATCKSEL: packed union { raw: u3, - value: HYST, + value: ATCKSEL, }, - /// Comparator blanking source selector. (RM0440 24.3.6 Table 198) - BLANKSEL: u3, - /// Vrefint resistor bridge enable. (RM0440 24.6) - BRGEN: u1, - /// Vrefint scaled input enable. (RM0440 24.6) - SCALEN: u1, - reserved30: u6, - /// Comparator output status. (READ ONLY) - VALUE_DO_NOT_SET: u1, - /// CSR register lock. - LOCK: u1, - }), - }; - }; - - pub const flash_h7ab = struct { - /// Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R - pub const BANK = extern struct { - /// FLASH key register for bank 1 - KEYR: u32, - reserved8: [4]u8, - /// FLASH control register for bank 1 - CR: mmio.Mmio(packed struct(u32) { - /// Bank 1 configuration lock bit - LOCK: u1, - /// Bank 1 program enable bit - PG: u1, - /// Bank 1 sector erase request - SER: u1, - /// Bank 1 erase request - BER: u1, - /// Bank 1 write forcing control bit - FW: u1, - /// Bank 1 bank or sector erase start control bit - START: u1, - /// Bank 1 sector erase selection number - SSN: u7, - reserved15: u2, - /// Bank 1 CRC control bit - CRC_EN: u1, - /// Bank 1 end-of-program interrupt control bit - EOPIE: u1, - /// Bank 1 write protection error interrupt enable bit - WRPERRIE: u1, - /// Bank 1 programming sequence error interrupt enable bit - PGSERRIE: u1, - /// Bank 1 strobe error interrupt enable bit - STRBERRIE: u1, - reserved21: u1, - /// Bank 1 inconsistency error interrupt enable bit - INCERRIE: u1, - /// Bank 1 write/erase error interrupt enable bit - OPERRIE: u1, - /// Bank 1 read protection error interrupt enable bit - RDPERRIE: u1, - /// Bank 1 secure error interrupt enable bit - RDSERRIE: u1, - /// Bank 1 ECC single correction error interrupt enable bit - SNECCERRIE: u1, - /// Bank 1 ECC double detection error interrupt enable bit - DBECCERRIE: u1, - /// Bank 1 end of CRC calculation interrupt enable bit - CRCENDIE: u1, - /// Bank 1 CRC read error interrupt enable bit - CRCRDERRIE: u1, - padding: u3, + reserved24: u5, + /// Active tamper output change period. The tamper output is changed every CK_ATPER = (2ATPER x CK_ATPRE) cycles. Refer to . + ATPER: u3, + reserved30: u3, + /// Active tamper output sharing. IN1 is compared with TAMPOUTSEL1. IN2 is compared with TAMPOUTSEL2. IN3 is compared with TAMPOUTSEL3. IN4 is compared with TAMPOUTSEL4. IN5 is compared with TAMPOUTSEL5. IN6 is compared with TAMPOUTSEL6. IN7 is compared with TAMPOUTSEL7. IN8 is compared with TAMPOUTSEL8 + ATOSHARE: u1, + /// Active tamper filter enable + FLTEN: u1, }), - /// FLASH status register for bank 1 - SR: mmio.Mmio(packed struct(u32) { - /// Bank 1 ongoing program flag - BSY: u1, - /// Bank 1 write buffer not empty flag - WBNE: u1, - /// Bank 1 wait queue flag - QW: u1, - /// Bank 1 CRC busy flag - CRC_BUSY: u1, - reserved16: u12, - /// Bank 1 end-of-program flag - EOP: u1, - /// Bank 1 write protection error flag - WRPERR: u1, - /// Bank 1 programming sequence error flag - PGSERR: u1, - /// Bank 1 strobe error flag - STRBERR: u1, - reserved21: u1, - /// Bank 1 inconsistency error flag - INCERR: u1, - /// Bank 1 write/erase error flag - OPERR: u1, - /// Bank 1 read protection error flag - RDPERR: u1, - /// Bank 1 secure error flag - RDSERR: u1, - /// Bank 1 single correction error flag - SNECCERR1: u1, - /// Bank 1 ECC double detection error flag - DBECCERR: u1, - /// Bank 1 CRC-complete flag - CRCEND: u1, - /// Bank 1 CRC read error flag - CRCRDERR: u1, - padding: u3, + /// TAMP active tamper seed register + ATSEEDR: mmio.Mmio(packed struct(u32) { + /// Pseudo-random generator seed value. This register must be written four times with 32-bit values to provide the 128-bit seed to the PRNG. Writing to this register automatically sends the seed value to the PRNG. + SEED: u32, }), - /// FLASH clear control register for bank 1 - CCR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Bank 1 EOP1 flag clear bit - CLR_EOP: u1, - /// Bank 1 WRPERR1 flag clear bit - CLR_WRPERR: u1, - /// Bank 1 PGSERR1 flag clear bi - CLR_PGSERR: u1, - /// Bank 1 STRBERR1 flag clear bit - CLR_STRBERR: u1, - reserved21: u1, - /// Bank 1 INCERR1 flag clear bit - CLR_INCERR: u1, - /// Bank 1 OPERR1 flag clear bit - CLR_OPERR: u1, - /// Bank 1 RDPERR1 flag clear bit - CLR_RDPERR: u1, - /// Bank 1 RDSERR1 flag clear bit - CLR_RDSERR: u1, - /// Bank 1 SNECCERR1 flag clear bit - CLR_SNECCERR: u1, - /// Bank 1 DBECCERR1 flag clear bit - CLR_DBECCERR: u1, - /// Bank 1 CRCEND1 flag clear bit - CLR_CRCEND: u1, - /// Bank 1 CRC read error clear bit - CLR_CRCRDERR: u1, - padding: u3, + /// TAMP active tamper output register + ATOR: mmio.Mmio(packed struct(u32) { + /// Pseudo-random generator value. This field provides the values of the PRNG output. Because of potential inconsistencies due to synchronization delays, PRNG must be read at least twice. The read value is correct if it is equal to previous read value. This field can only be read when the APB is in secure mode. + PRNG: u8, + reserved14: u6, + /// Seed running flag. This flag is set by hardware when a new seed is written in the ATSEEDR. It is cleared by hardware when the PRNG has absorbed this new seed, and by system reset. The TAMP APB cock must not be switched off as long as SEEDF is set. + SEEDF: u1, + /// Active tamper initialization status. This flag is set by hardware when the PRNG has absorbed the first 128-bit seed, meaning that the enabled active tampers are functional. This flag is cleared when the active tampers are disabled. + INITS: u1, + padding: u16, }), - reserved36: [16]u8, - /// FLASH protection address for bank 1 - PRAR_CUR: mmio.Mmio(packed struct(u32) { - /// Bank 1 lowest PCROP protected address - PROT_AREA_START: u12, - reserved16: u4, - /// Bank 1 highest PCROP protected address - PROT_AREA_END: u12, - reserved31: u3, - /// Bank 1 PCROP protected erase enable option status bit - DMEP: u1, + /// TAMP active tamper control register 2 + ATCR2: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// Active tamper shared output X selection. The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the ATCR1, and so can also be read or. written through ATCR1. + ATOSEL: u3, + padding: u21, }), - /// FLASH protection address for bank 1 - PRAR_PRG: mmio.Mmio(packed struct(u32) { - /// Bank 1 lowest PCROP protected address configuration - PROT_AREA_START: u12, - reserved16: u4, - /// Bank 1 highest PCROP protected address configuration - PROT_AREA_END: u12, - reserved31: u3, - /// Bank 1 PCROP protected erase enable option configuration bit - DMEP: u1, + /// TAMP secure mode register + SECCFGR: mmio.Mmio(packed struct(u32) { + /// Backup registers read/write protection offset. Protection zone 1 is defined for backup registers from BKP0R to BKPxR (x = BKPRWSEC-1, from 0 to 128). if TZEN=1, these backup registers can be read and written only with secure access. If TZEN=0: the protection zone 1 can be read and written with non-secure access. If BKPRWSEC = 0: there is no protection zone 1. If BKPRWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode. + BKPRWSEC: u8, + reserved15: u7, + /// Monotonic counter 1 secure protection + CNT1SEC: u1, + /// Backup registers write protection offset. Protection zone 2 is defined for backup registers from BKPyR (y = BKPRWSEC, from 0 to 128) to BKPzR (z = BKPWSEC-1, from 0 to 128, BKPWSECBKPRWSEC): if TZEN=1, these backup registers can be written only with secure access. They can be read with secure or non-secure access. Protection zone 3 defined for backup registers from BKPtR (t = BKPWSEC, from 0 to 127). They can be read or written with secure or non-secure access. If TZEN=0: the protection zone 2 can be read and written with non-secure access. If BKPWSEC = 0 or if BKPWSEC BKPRWSEC: there is no protection zone 2. If BKPWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode. + BKPWSEC: u8, + reserved30: u6, + /// Boot hardware key lock. This bit can be read and can only be written to 1 by software. It is cleared by hardware together with the backup registers following a tamper detection event or when the readout protection (RDP) is disabled. + BHKLOCK: u1, + /// Tamper protection (excluding monotonic counters and backup registers). Note: Refer to for details on the read protection. + TAMPSEC: u1, }), - /// FLASH secure address for bank 1 - SCAR_CUR: mmio.Mmio(packed struct(u32) { - /// Bank 1 lowest secure protected address - SEC_AREA_START: u12, - reserved16: u4, - /// Bank 1 highest secure protected address - SEC_AREA_END: u12, - reserved31: u3, - /// Bank 1 secure protected erase enable option status bit - DMES: u1, + /// TAMP privilege mode control register + PRIVCR: mmio.Mmio(packed struct(u32) { + reserved15: u15, + /// Monotonic counter 1 privilege protection + CNT1PRIV: u1, + reserved29: u13, + /// Backup registers zone 1 privilege protection + BKPRWPRIV: u1, + /// Backup registers zone 2 privilege protection + BKPWPRIV: u1, + /// Tamper privilege protection (excluding backup registers). Note: Refer to for details on the read protection. + TAMPPRIV: u1, }), - /// FLASH secure address for bank 1 - SCAR_PRG: mmio.Mmio(packed struct(u32) { - /// Bank 1 lowest secure protected address configuration - SEC_AREA_START: u12, - reserved16: u4, - /// Bank 1 highest secure protected address configuration - SEC_AREA_END: u12, - reserved31: u3, - /// Bank 1 secure protected erase enable option configuration bit - DMES: u1, + reserved44: [4]u8, + /// TAMP interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// Tamper X interrupt enable + TAMPIE: u1, + reserved16: u15, + /// Internal tamper X interrupt enable + ITAMPIE: u1, + padding: u15, }), - /// FLASH write sector protection for bank 1 - WPSN_CURR: mmio.Mmio(packed struct(u32) { - /// Bank 1 sector write protection option status byte - WRPSn: u8, - padding: u24, + /// TAMP status register + SR: mmio.Mmio(packed struct(u32) { + /// TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. + TAMPF: u1, + reserved16: u15, + /// Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + ITAMPF: u1, + padding: u15, }), - /// FLASH write sector protection for bank 1 - WPSN_PRGR: mmio.Mmio(packed struct(u32) { - /// Bank 1 sector write protection configuration byte - WRPSn: u8, - padding: u24, + /// TAMP non-secure masked interrupt status register + MISR: mmio.Mmio(packed struct(u32) { + /// TAMPx non-secure interrupt masked flag. This flag is set by hardware when the tamper X non-secure interrupt is raised. + TAMPMF: u1, + reserved16: u15, + /// Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + ITAMPMF: u1, + padding: u15, }), - reserved76: [16]u8, - /// FLASH CRC control register for bank 1 - CRCCR: mmio.Mmio(packed struct(u32) { - /// Bank 1 CRC sector number - CRC_SECT: u3, - reserved7: u4, - /// Bank 1 CRC select bit - ALL_BANK: u1, - /// Bank 1 CRC sector mode select bit - CRC_BY_SECT: u1, - /// Bank 1 CRC sector select bit - ADD_SECT: u1, - /// Bank 1 CRC sector list clear bit - CLEAN_SECT: u1, - reserved16: u5, - /// Bank 1 CRC start bit - START_CRC: u1, - /// Bank 1 CRC clear bit - CLEAN_CRC: u1, - reserved20: u2, - /// Bank 1 CRC burst size - CRC_BURST: u2, - padding: u10, + /// TAMP secure masked interrupt status register + SMISR: mmio.Mmio(packed struct(u32) { + /// TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper X secure interrupt is raised. + TAMPMF: u1, + reserved16: u15, + /// Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + ITAMPMF: u1, + padding: u15, }), - /// FLASH CRC start address register for bank 1 - CRCSADDR: mmio.Mmio(packed struct(u32) { - /// CRC start address on bank 1 - CRC_START_ADDR: u32, + /// TAMP status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the SR register. + CTAMPF: u1, + reserved16: u15, + /// Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + CITAMPF: u1, + padding: u15, }), - /// FLASH CRC end address register for bank 1 - CRCEADDR: mmio.Mmio(packed struct(u32) { - /// CRC end address on bank 1 - CRC_END_ADDR: u32, + /// TAMP monotonic counter 1 register + COUNTR: mmio.Mmio(packed struct(u32) { + /// This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value. + COUNT: u32, }), - reserved92: [4]u8, - /// FLASH ECC fail address for bank 1 - FAR: mmio.Mmio(packed struct(u32) { - /// Bank 1 ECC error address - FAIL_ECC_ADDR: u15, - padding: u17, + reserved84: [16]u8, + /// TAMP erase configuration register + ERCFGR: mmio.Mmio(packed struct(u32) { + /// Configurable device secrets configuration + ERCFG0: u1, + padding: u31, + }), + reserved256: [168]u8, + /// TAMP backup X register + BKPR: [32]mmio.Mmio(packed struct(u32) { + /// The application can write or read data to and from these registers. In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + BKP: u32, }), }; + }; - /// Flash - pub const FLASH = extern struct { - /// Access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Read latency - LATENCY: u3, - reserved4: u1, - /// Flash signal delay - WRHIGHFREQ: u2, - padding: u26, + pub const tamp_wl = struct { + pub const BKERASE = enum(u1) { + /// Reset backup registers + Reset = 0x1, + _, + }; + + pub const TAMPFLT = enum(u2) { + /// Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input)" + NoFilter = 0x0, + /// Tamper event is activated after 2 consecutive samples at the active level" + Filter2 = 0x1, + /// Tamper event is activated after 4 consecutive samples at the active level" + Filter4 = 0x2, + /// Tamper event is activated after 8 consecutive samples at the active level" + Filter8 = 0x3, + }; + + pub const TAMPFREQ = enum(u3) { + /// RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + Hz_1 = 0x0, + /// RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + Hz_2 = 0x1, + /// RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + Hz_4 = 0x2, + /// RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + Hz_8 = 0x3, + /// RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + Hz_16 = 0x4, + /// RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + Hz_32 = 0x5, + /// RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + Hz_64 = 0x6, + /// RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + Hz_128 = 0x7, + }; + + pub const TAMPMSK = enum(u1) { + /// Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection + ResetBySoftware = 0x0, + /// Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased. The tamper x interrupt must not be enabled when TAMP3MSK is set + ResetByHardware = 0x1, + }; + + pub const TAMPPRCH = enum(u2) { + /// 1 RTCCLK cycle + Cycles1 = 0x0, + /// 2 RTCCLK cycles + Cycles2 = 0x1, + /// 4 RTCCLK cycles + Cycles4 = 0x2, + /// 8 RTCCLK cycles + Cycles8 = 0x3, + }; + + pub const TAMPTRG = enum(u1) { + /// If TAMPFLT != 00 Tamper x input staying low triggers a tamper detection event. If TAMPFLT = 00 Tamper x input rising edge and high level triggers a tamper detection event + FilteredLowOrUnfilteredHigh = 0x0, + /// If TAMPFLT != 00 Tamper x input staying high triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge and low level triggers a tamper detection event + FilteredHighOrUnfilteredLow = 0x1, + }; + + /// Tamper and backup registers + pub const TAMP = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Tamper detection on IN X enable + TAMPE: u1, + reserved16: u15, + /// Internal tamper X enable + ITAMPE: u1, + padding: u15, }), - /// Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R - BANK: u32, - /// FLASH option key register - OPTKEYR: u32, - reserved24: [12]u8, - /// FLASH option control register - OPTCR: mmio.Mmio(packed struct(u32) { - /// FLASH_OPTCR lock option configuration bit - OPTLOCK: u1, - /// Option byte start change option configuration bit - OPTSTART: u1, - reserved4: u2, - /// Flash mass erase enable bit - MER: u1, - /// OTP program control bit - PG_OTP: u1, - reserved30: u24, - /// Option byte change error interrupt enable bit - OPTCHANGEERRIE: u1, - /// Bank swapping configuration bit - SWAP_BANK: u1, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Tamper X no erase + TAMPNOER: u1, + reserved16: u15, + /// Tamper X mask. The tamper X interrupt must not be enabled when TAMPMSK is set. + TAMPMSK: packed union { + raw: u1, + value: TAMPMSK, + }, + reserved23: u6, + /// Backup registers erase + BKERASE: packed union { + raw: u1, + value: BKERASE, + }, + /// Active level for tamper X input + TAMPTRG: packed union { + raw: u1, + value: TAMPTRG, + }, + padding: u7, }), - /// FLASH option status register - OPTSR_CUR: mmio.Mmio(packed struct(u32) { - /// Option byte change ongoing flag - OPT_BUSY: u1, - reserved2: u1, - /// Brownout level option status bit - BOR_LEV: u2, - /// IWDG1 control option status bit - IWDG1_HW: u1, - reserved6: u1, - /// D1 DStop entry reset option status bit - nRST_STOP_D1: u1, - /// D1 DStandby entry reset option status bit - nRST_STBY_D1: u1, - /// Readout protection level option status byte - RDP: u8, - reserved17: u1, - /// IWDG Stop mode freeze option status bit - FZ_IWDG_STOP: u1, - /// IWDG Standby mode freeze option status bit - FZ_IWDG_SDBY: u1, - /// DTCM RAM size option status - ST_RAM_SIZE: u2, - /// Security enable option status bit - SECURITY: u1, - reserved26: u4, - /// User option bit 1 - RSS1: u1, - reserved28: u1, - /// Device personalization status bit - PERSO_OK: u1, - /// I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V) - IO_HSLV: u1, - /// Option byte change error flag - OPTCHANGEERR: u1, - /// Bank swapping option status bit - SWAP_BANK_OPT: u1, + /// TAMP control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Internal Tamper X no erase + ITAMPNOER: u1, + padding: u31, }), - /// FLASH option status register - OPTSR_PRG: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// BOR reset level option configuration bits - BOR_LEV: u2, - /// IWDG1 option configuration bit - IWDG1_HW: u1, - reserved6: u1, - /// Option byte erase after D1 DStop option configuration bit - nRST_STOP_D1: u1, - /// Option byte erase after D1 DStandby option configuration bit - nRST_STBY_D1: u1, - /// Readout protection level option configuration byte - RDP: u8, - reserved17: u1, - /// IWDG Stop mode freeze option configuration bit - FZ_IWDG_STOP: u1, - /// IWDG Standby mode freeze option configuration bit - FZ_IWDG_SDBY: u1, - /// DTCM size select option configuration bits - ST_RAM_SIZE: u2, - /// Security option configuration bit - SECURITY: u1, - reserved26: u4, - /// User option configuration bit 1 - RSS1: u1, - /// User option configuration bit 2 - RSS2: u1, - reserved29: u1, - /// I/O high-speed at low-voltage (PRODUCT_BELOW_25V) - IO_HSLV: u1, - reserved31: u1, - /// Bank swapping option configuration bit - SWAP_BANK_OPT: u1, + /// TAMP filter control register + FLTCR: mmio.Mmio(packed struct(u32) { + /// Tamper sampling frequency. Determines the frequency at which each of the INx inputs are sampled. + TAMPFREQ: packed union { + raw: u3, + value: TAMPFREQ, + }, + /// INx filter count. These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the INx inputs. + TAMPFLT: packed union { + raw: u2, + value: TAMPFLT, + }, + /// INx precharge duration. These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the INx inputs. + TAMPPRCH: packed union { + raw: u2, + value: TAMPPRCH, + }, + /// INx pull-up disable. This bit determines if each of the TAMPx pins are precharged before each sample. + TAMPPUDIS: u1, + padding: u24, }), - /// FLASH option clear control register - OPTCCR: mmio.Mmio(packed struct(u32) { - reserved30: u30, - /// OPTCHANGEERR reset bit - CLR_OPTCHANGEERR: u1, - padding: u1, + reserved44: [28]u8, + /// TAMP interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// Tamper X interrupt enable + TAMPIE: u1, + reserved16: u15, + /// Internal tamper X interrupt enable + ITAMPIE: u1, + padding: u15, }), - reserved64: [24]u8, - /// FLASH register with boot address - BOOT_CURR: mmio.Mmio(packed struct(u32) { - /// Boot address 0 - BOOT_ADD0: u16, - /// Boot address 1 - BOOT_ADD1: u16, + /// TAMP status register + SR: mmio.Mmio(packed struct(u32) { + /// Tamper X detection flag + TAMPF: u1, + reserved16: u15, + /// Internal tamper X detection flag + ITAMPF: u1, + padding: u15, }), - /// FLASH register with boot address - BOOT_PRGR: mmio.Mmio(packed struct(u32) { - /// Boot address 0 - BOOT_ADD0: u16, - /// Boot address 1 - BOOT_ADD1: u16, + /// TAMP masked interrupt status register + MISR: mmio.Mmio(packed struct(u32) { + /// Tamper X interrupt masked flag + TAMPMF: u1, + reserved16: u15, + /// Internal tamper X interrupt masked flag + ITAMPMF: u1, + padding: u15, }), - reserved92: [20]u8, - /// FLASH CRC data register - CRCDATAR: mmio.Mmio(packed struct(u32) { - /// CRC result - CRC_DATA: u32, + reserved60: [4]u8, + /// TAMP status clear register + SCR: mmio.Mmio(packed struct(u32) { + /// Clear tamper X detection flag + CTAMPF: u1, + reserved16: u15, + /// Clear internal tamper X detection flag + CITAMPF: u1, + padding: u15, + }), + /// monotonic counter register + COUNTR: mmio.Mmio(packed struct(u32) { + /// COUNT + COUNT: u32, + }), + reserved256: [188]u8, + /// TAMP backup register + BKPR: [20]mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, }), }; }; - pub const adccommon_f3 = struct { - /// ADC clock mode - pub const CKMODE = enum(u2) { - /// Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous mode - Asynchronous = 0x0, - /// Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck. - SyncDiv1 = 0x1, - /// Use AHB clock rcc_hclk3 divided by 2. - SyncDiv2 = 0x2, - /// Use AHB clock rcc_hclk3 divided by 4. - SyncDiv4 = 0x3, + pub const timer_l0 = struct { + pub const CCDS = enum(u1) { + /// CCx DMA request sent when CCx event occurs + OnCompare = 0x0, + /// CCx DMA request sent when update event occurs + OnUpdate = 0x1, }; - pub const DMACFG = enum(u1) { - /// DMA One Shot mode selected - OneShot = 0x0, - /// DMA Circular mode selected - Circulator = 0x1, + pub const CCMR_Input_CCS = enum(u2) { + /// CCx channel is configured as input, normal mapping: ICx mapped to TIx + TI4 = 0x1, + /// CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + TI3 = 0x2, + /// CCx channel is configured as input, ICx is mapped on TRC + TRC = 0x3, + _, }; - /// Dual ADC mode selection - pub const DUAL = enum(u5) { - /// Independent mode - Independent = 0x0, - /// Dual, combined regular simultaneous + injected simultaneous mode - DualRJ = 0x1, - /// Dual, combined regular simultaneous + alternate trigger mode - DualRA = 0x2, - /// Dual, combined injected simultaneous + fast interleaved mode - DualIJ = 0x3, - /// Dual, injected simultaneous mode only - DualJ = 0x5, - /// Dual, regular simultaneous mode only - DualR = 0x6, - /// dual, interleaved mode only - DualI = 0x7, - /// Dual, alternate trigger mode only - DualA = 0x9, + pub const CCMR_Output_CCS = enum(u2) { + /// CCx channel is configured as output + Output = 0x0, _, }; - /// Direct memory access mode for multi ADC mode - pub const MDMA = enum(u2) { - /// MDMA mode disabled - Disabled = 0x0, - /// MDMA mode enabled for 12 and 10-bit resolution - Bits12_10 = 0x2, - /// MDMA mode enabled for 8 and 6-bit resolution - Bits8_6 = 0x3, + pub const CKD = enum(u2) { + /// t_DTS = t_CK_INT + Div1 = 0x0, + /// t_DTS = 2 × t_CK_INT + Div2 = 0x1, + /// t_DTS = 4 × t_CK_INT + Div4 = 0x2, _, }; - /// ADC common registers - pub const ADC_COMMON = extern struct { - /// ADC Common status register - CSR: mmio.Mmio(packed struct(u32) { - /// Master ADC ready - ADRDY_MST: u1, - /// End of sampling phase flag of the master ADC - EOSMP_MST: u1, - /// End of regular conversion of the master ADC - EOC_MST: u1, - /// End of regular sequence flag of the master ADC - EOS_MST: u1, - /// Overrun flag of the master ADC - OVR_MST: u1, - /// End of injected conversion of the master ADC - JEOC_MST: u1, - /// End of injected sequence flag of the master ADC - JEOS: u1, - /// Analog watchdog flag of the master ADC - AWD_MST: u1, - reserved10: u2, - /// Injected context queue overflow flag of the master ADC - JQOVF_MST: u1, - reserved16: u5, - /// Slave ADC ready - ADRDY_SLV: u1, - /// End of sampling phase flag of the slave ADC - EOSMP_SLV: u1, - /// End of regular conversion of the slave ADC - EOC_SLV: u1, - /// End of regular sequence flag of the slave ADC - EOS_SLV: u1, - /// Overrun flag of the slave ADC - OVR_SLV: u1, - /// End of injected conversion of the slave ADC - JEOC_SLV: u1, - /// End of injected sequence flag of the slave ADC - JEOS_SLV: u1, - /// Analog watchdog flag of the slave ADC - AWD_SLV: u1, - reserved26: u2, - /// Injected context queue overflow flag of the slave ADC - JQOVF_SLV: u1, - padding: u5, + pub const CMS = enum(u2) { + /// The counter counts up or down depending on the direction bit + EdgeAligned = 0x0, + /// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + CenterAligned1 = 0x1, + /// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + CenterAligned2 = 0x2, + /// The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + CenterAligned3 = 0x3, + }; + + pub const DIR = enum(u1) { + /// Counter used as upcounter + Up = 0x0, + /// Counter used as downcounter + Down = 0x1, + }; + + pub const ETP = enum(u1) { + /// ETR is noninverted, active at high level or rising edge + NotInverted = 0x0, + /// ETR is inverted, active at low level or falling edge + Inverted = 0x1, + }; + + pub const ETPS = enum(u2) { + /// Prescaler OFF + Div1 = 0x0, + /// ETRP frequency divided by 2 + Div2 = 0x1, + /// ETRP frequency divided by 4 + Div4 = 0x2, + /// ETRP frequency divided by 8 + Div8 = 0x3, + }; + + pub const FilterValue = enum(u4) { + /// No filter, sampling is done at fDTS + NoFilter = 0x0, + /// fSAMPLING=fCK_INT, N=2 + FCK_INT_N2 = 0x1, + /// fSAMPLING=fCK_INT, N=4 + FCK_INT_N4 = 0x2, + /// fSAMPLING=fCK_INT, N=8 + FCK_INT_N8 = 0x3, + /// fSAMPLING=fDTS/2, N=6 + FDTS_Div2_N6 = 0x4, + /// fSAMPLING=fDTS/2, N=8 + FDTS_Div2_N8 = 0x5, + /// fSAMPLING=fDTS/4, N=6 + FDTS_Div4_N6 = 0x6, + /// fSAMPLING=fDTS/4, N=8 + FDTS_Div4_N8 = 0x7, + /// fSAMPLING=fDTS/8, N=6 + FDTS_Div8_N6 = 0x8, + /// fSAMPLING=fDTS/8, N=8 + FDTS_Div8_N8 = 0x9, + /// fSAMPLING=fDTS/16, N=5 + FDTS_Div16_N5 = 0xa, + /// fSAMPLING=fDTS/16, N=6 + FDTS_Div16_N6 = 0xb, + /// fSAMPLING=fDTS/16, N=8 + FDTS_Div16_N8 = 0xc, + /// fSAMPLING=fDTS/32, N=5 + FDTS_Div32_N5 = 0xd, + /// fSAMPLING=fDTS/32, N=6 + FDTS_Div32_N6 = 0xe, + /// fSAMPLING=fDTS/32, N=8 + FDTS_Div32_N8 = 0xf, + }; + + pub const MMS = enum(u3) { + /// The UG bit from the TIMx_EGR register is used as trigger output + Reset = 0x0, + /// The counter enable signal, CNT_EN, is used as trigger output + Enable = 0x1, + /// The update event is selected as trigger output + Update = 0x2, + /// The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + ComparePulse = 0x3, + /// OC1REF signal is used as trigger output + CompareOC1 = 0x4, + /// OC2REF signal is used as trigger output + CompareOC2 = 0x5, + /// OC3REF signal is used as trigger output + CompareOC3 = 0x6, + /// OC4REF signal is used as trigger output + CompareOC4 = 0x7, + }; + + pub const MSM = enum(u1) { + /// No action + NoSync = 0x0, + /// The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + Sync = 0x1, + }; + + pub const OCM = enum(u3) { + /// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + Frozen = 0x0, + /// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + ActiveOnMatch = 0x1, + /// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + InactiveOnMatch = 0x2, + /// OCyREF toggles when TIMx_CNT=TIMx_CCRy + Toggle = 0x3, + /// OCyREF is forced low + ForceInactive = 0x4, + /// OCyREF is forced high + ForceActive = 0x5, + /// In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + PwmMode1 = 0x6, + /// Inversely to PwmMode1 + PwmMode2 = 0x7, + }; + + pub const SMS = enum(u3) { + /// Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock. + Disabled = 0x0, + /// Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + Encoder_Mode_1 = 0x1, + /// Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + Encoder_Mode_2 = 0x2, + /// Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + Encoder_Mode_3 = 0x3, + /// Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + Reset_Mode = 0x4, + /// Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + Gated_Mode = 0x5, + /// Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + Trigger_Mode = 0x6, + /// External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + Ext_Clock_Mode = 0x7, + }; + + pub const TI1S = enum(u1) { + /// The TIMx_CH1 pin is connected to TI1 input + Normal = 0x0, + /// The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + XOR = 0x1, + }; + + pub const TS = enum(u3) { + /// Internal Trigger 0 (ITR0) + ITR0 = 0x0, + /// Internal Trigger 1 (ITR1) + ITR1 = 0x1, + /// Internal Trigger 2 (ITR2) + ITR2 = 0x2, + /// Internal Trigger 3 (ITR3) + ITR3 = 0x3, + /// TI1 Edge Detector (TI1F_ED) + TI1F_ED = 0x4, + /// Filtered Timer Input 1 (TI1FP1) + TI1FP1 = 0x5, + /// Filtered Timer Input 2 (TI2FP2) + TI2FP2 = 0x6, + /// External Trigger input (ETRF) + ETRF = 0x7, + }; + + pub const URS = enum(u1) { + /// Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + AnyEvent = 0x0, + /// Only counter overflow/underflow generates an update interrupt or DMA request + CounterOnly = 0x1, + }; + + /// Virtual 1-channel timers + pub const TIM_1CH = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// Clock division + CKD: packed union { + raw: u2, + value: CKD, + }, + padding: u22, }), - reserved8: [4]u8, - /// ADC common control register - CCR: mmio.Mmio(packed struct(u32) { - /// Dual ADC mode selection - DUAL: packed union { - raw: u5, - value: DUAL, + reserved12: [8]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/Compare x (x=1) interrupt enable + CCIE: u1, + padding: u30, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1) interrupt flag + CCIF: u1, + reserved9: u7, + /// Capture/Compare x (x=1) overcapture flag + CCOF: u1, + padding: u22, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1) generation + CCG: u1, + padding: u30, + }), + /// capture/compare mode register 1 (input mode) + CCMR_Input: [1]mmio.Mmio(packed struct(u32) { + /// Capture/Compare y selection + CCS: packed union { + raw: u2, + value: CCMR_Input_CCS, }, - reserved8: u3, - /// Delay between 2 sampling phases - DELAY: u4, - reserved13: u1, - /// Direct memory access configuration - DMACFG: packed union { + /// Input capture y prescaler + ICPSC: u2, + /// Input capture y filter + ICF: packed union { + raw: u4, + value: FilterValue, + }, + padding: u24, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare x (x=1) output enable + CCE: u1, + /// Capture/Compare x (x=1) output Polarity + CCP: u1, + reserved3: u1, + /// Capture/Compare x (x=1) output Polarity + CCNP: u1, + padding: u28, + }), + reserved52: [16]u8, + /// capture/compare register x (x=1) + CCR: [1]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, + }), + reserved80: [24]u8, + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, + }; + + /// 2-channel timers + pub const TIM_2CH = extern struct { + reserved4: [4]u8, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: packed union { + raw: u3, + value: MMS, + }, + /// TI1 selection + TI1S: packed union { raw: u1, - value: DMACFG, + value: TI1S, }, - /// Direct memory access mode for multi ADC mode - MDMA: packed union { + padding: u24, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: packed union { + raw: u3, + value: SMS, + }, + reserved4: u1, + /// Trigger selection + TS: packed union { + raw: u3, + value: TS, + }, + /// Master/Slave mode + MSM: packed union { + raw: u1, + value: MSM, + }, + /// External trigger filter + ETF: packed union { + raw: u4, + value: FilterValue, + }, + /// External trigger prescaler + ETPS: packed union { raw: u2, - value: MDMA, + value: ETPS, }, - /// ADC clock mode - CKMODE: packed union { + /// External clock mode 2 enable + ECE: u1, + /// External trigger polarity + ETP: packed union { + raw: u1, + value: ETP, + }, + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/Compare x (x=1-2) interrupt enable + CCIE: u1, + reserved6: u4, + /// Trigger interrupt enable + TIE: u1, + padding: u25, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1-2) interrupt flag + CCIF: u1, + reserved6: u4, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare x (x=1-2) overcapture flag + CCOF: u1, + padding: u22, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1-2) generation + CCG: u1, + reserved6: u4, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (input mode) + CCMR_Input: [1]mmio.Mmio(packed struct(u32) { + /// Capture/Compare y selection + CCS: packed union { raw: u2, - value: CKMODE, + value: CCMR_Input_CCS, }, - reserved22: u4, - /// VREFINT enable - VREFEN: u1, - /// Temperature sensor enable - TSEN: u1, - /// VBAT enable - VBATEN: u1, - padding: u7, + /// Input capture y prescaler + ICPSC: u2, + /// Input capture y filter + ICF: packed union { + raw: u4, + value: FilterValue, + }, + padding: u24, }), - /// ADC common regular data register for dual and triple modes - CDR: mmio.Mmio(packed struct(u32) { - /// Regular data of the master ADC - RDATA_MST: u16, - /// Regular data of the master ADC - RDATA_SLV: u16, + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare x (x=1-2) output enable + CCE: u1, + /// Capture/Compare x (x=1-2) output Polarity + CCP: u1, + reserved3: u1, + /// Capture/Compare x (x=1-2) output Polarity + CCNP: u1, + padding: u28, + }), + reserved52: [16]u8, + /// capture/compare register x (x=1-2) + CCR: [2]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, }), }; - }; - pub const exti_w = struct { - /// CPU-specific registers - pub const CPU = extern struct { - /// CPU x interrupt mask register - IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// Basic timers + pub const TIM_BASIC = extern struct { + reserved4: [4]u8, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: packed union { + raw: u3, + value: MMS, + }, + padding: u25, }), - /// CPU x event mask register - EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + }; + + /// Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP + pub const TIM_BASIC_NO_CR2 = extern struct { + reserved12: [12]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// Update DMA request enable + UDE: u1, + padding: u23, }), }; - /// External interrupt/event controller - pub const EXTI = extern struct { - /// rising trigger selection register - RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// Virtual timer for common part of TIM_BASIC and TIM_1CH + pub const TIM_CORE = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: packed union { + raw: u1, + value: URS, + }, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + reserved11: u3, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, }), - /// falling trigger selection register - FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, + reserved12: [8]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, padding: u31, }), - /// software interrupt event register - SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, padding: u31, }), - /// EXTI pending register - PR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, padding: u31, }), - reserved128: [112]u8, - /// CPU specific registers - CPU: u32, - }; - }; - - pub const hsem_v1 = struct { - /// Hardware semaphore (HSEM). - pub const HSEM = extern struct { - /// HSEM register HSEM_R%s HSEM_R31. - R: [32]mmio.Mmio(packed struct(u32) { - /// Semaphore ProcessID. - PROCID: u8, - /// Semaphore COREID. - COREID: u4, - reserved31: u19, - /// Lock indication. - LOCK: u1, - }), - /// HSEM Read lock register. - RLR: [32]mmio.Mmio(packed struct(u32) { - /// Semaphore ProcessID. - PROCID: u8, - /// Semaphore COREID. - COREID: u4, - reserved31: u19, - /// Lock indication. - LOCK: u1, + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, }), - /// HSEM Interrupt enable register. - IER: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x enable bit. - ISE: u1, - padding: u31, + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, }), - /// HSEM Interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x clear bit. - ISC: u1, - padding: u31, + }; + + /// General purpose 16-bit timers + pub const TIM_GP16 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Direction + DIR: packed union { + raw: u1, + value: DIR, + }, + /// Center-aligned mode selection + CMS: packed union { + raw: u2, + value: CMS, + }, + reserved8: u1, + /// Clock division + CKD: packed union { + raw: u2, + value: CKD, + }, + padding: u22, }), - /// HSEM Interrupt status register. - ISR: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x status bit before enable (mask). - ISF: u1, - padding: u31, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Capture/compare DMA selection + CCDS: packed union { + raw: u1, + value: CCDS, + }, + reserved7: u3, + /// TI1 selection + TI1S: packed union { + raw: u1, + value: TI1S, + }, + padding: u24, }), - /// HSEM Masked interrupt status register. - MISR: mmio.Mmio(packed struct(u32) { - /// masked interrupt semaphore x status bit after enable (mask). - MISF: u1, - padding: u31, + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: packed union { + raw: u3, + value: SMS, + }, + reserved4: u1, + /// Trigger selection + TS: packed union { + raw: u3, + value: TS, + }, + /// Master/Slave mode + MSM: packed union { + raw: u1, + value: MSM, + }, + /// External trigger filter + ETF: packed union { + raw: u4, + value: FilterValue, + }, + /// External trigger prescaler + ETPS: packed union { + raw: u2, + value: ETPS, + }, + /// External clock mode 2 enable + ECE: u1, + /// External trigger polarity + ETP: packed union { + raw: u1, + value: ETP, + }, + padding: u16, }), - reserved320: [48]u8, - /// HSEM Clear register. - CR: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// COREID of semaphores to be cleared. - COREID: u4, - reserved16: u4, - /// Semaphore clear Key. - KEY: u16, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/Compare x (x=1-4) interrupt enable + CCIE: u1, + reserved6: u4, + /// Trigger interrupt enable + TIE: u1, + reserved9: u2, + /// Capture/Compare x (x=1-4) DMA request enable + CCDE: u1, + reserved14: u4, + /// Trigger DMA request enable + TDE: u1, + padding: u17, }), - /// HSEM Interrupt clear register. - KEYR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Semaphore Clear Key. - KEY: u16, + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1-4) interrupt flag + CCIF: u1, + reserved6: u4, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare x (x=1-4) overcapture flag + CCOF: u1, + padding: u22, }), - }; - }; - - pub const dbgmcu_l4 = struct { - /// MCU debug component - pub const DBGMCU = extern struct { - /// DBGMCU_IDCODE - IDCODE: mmio.Mmio(packed struct(u32) { - /// Device identifier - DEV_ID: u16, - /// Revision identifie - REV_ID: u16, + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1-4) generation + CCG: u1, + reserved6: u4, + /// Trigger generation + TG: u1, + padding: u25, }), - /// Debug MCU configuration register - CR: mmio.Mmio(packed struct(u32) { - /// Debug Sleep mode - DBG_SLEEP: u1, - /// Debug Stop mode - DBG_STOP: u1, - /// Debug Standby mode - DBG_STANDBY: u1, - reserved5: u2, - /// Trace pin assignment control - TRACE_IOEN: u1, - /// Trace pin assignment control - TRACE_MODE: u2, + /// capture/compare mode register 1-2 (input mode) + CCMR_Input: [2]mmio.Mmio(packed struct(u32) { + /// Capture/Compare y selection + CCS: packed union { + raw: u2, + value: CCMR_Input_CCS, + }, + /// Input capture y prescaler + ICPSC: u2, + /// Input capture y filter + ICF: packed union { + raw: u4, + value: FilterValue, + }, padding: u24, }), - /// Debug MCU APB1 freeze register1 - APB1FZR1: mmio.Mmio(packed struct(u32) { - /// TIM2 counter stopped when core is halted - TIM2: u1, - /// TIM3 counter stopped when core is halted - TIM3: u1, - /// TIM4 counter stopped when core is halted - TIM4: u1, - /// TIM5 counter stopped when core is halted - TIM5: u1, - /// TIM6 counter stopped when core is halted - TIM6: u1, - /// TIM7 counter stopped when core is halted - TIM7: u1, - reserved10: u4, - /// RTC counter stopped when core is halted - RTC: u1, - /// Window watchdog counter stopped when core is halted - WWDG: u1, - /// Independent watchdog counter stopped when core is halted - IWDG: u1, - reserved21: u8, - /// I2C1 SMBUS timeout counter stopped when core is halted - I2C1: u1, - /// I2C2 SMBUS timeout counter stopped when core is halted - I2C2: u1, - /// I2C3 SMBUS timeout counter stopped when core is halted - I2C3: u1, - reserved25: u1, - /// bxCAN stopped when core is halted - CAN: u1, - reserved31: u5, - /// LPTIM1 counter stopped when core is halted - LPTIM1: u1, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare x (x=1-4) output enable + CCE: u1, + /// Capture/Compare x (x=1-4) output Polarity + CCP: u1, + reserved3: u1, + /// Capture/Compare x (x=1-4) output Polarity + CCNP: u1, + padding: u28, }), - /// Debug MCU APB1 freeze register 2 - APB1FZR2: mmio.Mmio(packed struct(u32) { - reserved5: u5, - /// LPTIM2 counter stopped when core is halted - LPTIM2: u1, - padding: u26, + reserved52: [16]u8, + /// capture/compare register x (x=1-4) + CCR: [4]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, }), - /// Debug MCU APB2 freeze register - APB2FZR: mmio.Mmio(packed struct(u32) { - reserved11: u11, - /// TIM1 counter stopped when core is halted - TIM1: u1, - reserved13: u1, - /// TIM8 counter stopped when core is halted - TIM8: u1, - reserved16: u2, - /// TIM15 counter stopped when core is halted - TIM15: u1, - /// TIM16 counter stopped when core is halted - TIM16: u1, - /// TIM17 counter stopped when core is halted - TIM17: u1, - padding: u13, + reserved72: [4]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, }), }; }; - pub const sai_v4_2pdm = struct { - pub const CKSTR = enum(u1) { - /// Data strobing edge is falling edge of SCK - FallingEdge = 0x0, - /// Data strobing edge is rising edge of SCK - RisingEdge = 0x1, + pub const timer_v1 = struct { + pub const BKINP = enum(u1) { + /// input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) + NotInverted = 0x0, + /// input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) + Inverted = 0x1, }; - pub const CNRDY = enum(u1) { - /// External AC’97 Codec is ready - Ready = 0x0, - /// External AC’97 Codec is not ready - NotReady = 0x1, + pub const BKP = enum(u1) { + /// Break input tim_brk is active low + ActiveLow = 0x0, + /// Break input tim_brk is active high + ActiveHigh = 0x1, }; - pub const COMP = enum(u2) { - /// No companding algorithm - NoCompanding = 0x0, - /// μ-Law algorithm - MuLaw = 0x2, - /// A-Law algorithm - ALaw = 0x3, - _, + pub const CCDS = enum(u1) { + /// CCx DMA request sent when CCx event occurs + OnCompare = 0x0, + /// CCx DMA request sent when update event occurs + OnUpdate = 0x1, }; - pub const CPL = enum(u1) { - /// 1’s complement representation - OnesComplement = 0x0, - /// 2’s complement representation - TwosComplement = 0x1, + pub const CCMR_Input_CCS = enum(u2) { + /// CCx channel is configured as input, normal mapping: ICx mapped to TIx + TI4 = 0x1, + /// CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + TI3 = 0x2, + /// CCx channel is configured as input, ICx is mapped on TRC + TRC = 0x3, + _, }; - pub const DS = enum(u3) { - /// 8 bits - Bit8 = 0x2, - /// 10 bits - Bit10 = 0x3, - /// 16 bits - Bit16 = 0x4, - /// 20 bits - Bit20 = 0x5, - /// 24 bits - Bit24 = 0x6, - /// 32 bits - Bit32 = 0x7, + pub const CCMR_Output_CCS = enum(u2) { + /// CCx channel is configured as output + Output = 0x0, _, }; - pub const FLVL = enum(u3) { - /// FIFO empty - Empty = 0x0, - /// FIFO <= 1⁄4 but not empty - Quarter1 = 0x1, - /// 1⁄4 < FIFO <= 1⁄2 - Quarter2 = 0x2, - /// 1⁄2 < FIFO <= 3⁄4 - Quarter3 = 0x3, - /// 3⁄4 < FIFO but not full - Quarter4 = 0x4, - /// FIFO full - Full = 0x5, + pub const CKD = enum(u2) { + /// t_DTS = t_CK_INT + Div1 = 0x0, + /// t_DTS = 2 × t_CK_INT + Div2 = 0x1, + /// t_DTS = 4 × t_CK_INT + Div4 = 0x2, _, }; - pub const FSOFF = enum(u1) { - /// FS is asserted on the first bit of the slot 0 - OnFirst = 0x0, - /// FS is asserted one bit before the first bit of the slot 0 - BeforeFirst = 0x1, + pub const CMS = enum(u2) { + /// The counter counts up or down depending on the direction bit + EdgeAligned = 0x0, + /// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + CenterAligned1 = 0x1, + /// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + CenterAligned2 = 0x2, + /// The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + CenterAligned3 = 0x3, }; - pub const FSPOL = enum(u1) { - /// FS is active low (falling edge) - FallingEdge = 0x0, - /// FS is active high (rising edge) - RisingEdge = 0x1, + pub const DIR = enum(u1) { + /// Counter used as upcounter + Up = 0x0, + /// Counter used as downcounter + Down = 0x1, }; - pub const FTH = enum(u3) { - /// FIFO empty - Empty = 0x0, - /// 1⁄4 FIFO - Quarter1 = 0x1, - /// 1⁄2 FIFO - Quarter2 = 0x2, - /// 3⁄4 FIFO - Quarter3 = 0x3, - /// FIFO full - Full = 0x4, - _, + pub const ETP = enum(u1) { + /// ETR is noninverted, active at high level or rising edge + NotInverted = 0x0, + /// ETR is inverted, active at low level or falling edge + Inverted = 0x1, }; - pub const LSBFIRST = enum(u1) { - /// Data are transferred with MSB first - MsbFirst = 0x0, - /// Data are transferred with LSB first - LsbFirst = 0x1, + pub const ETPS = enum(u2) { + /// Prescaler OFF + Div1 = 0x0, + /// ETRP frequency divided by 2 + Div2 = 0x1, + /// ETRP frequency divided by 4 + Div4 = 0x2, + /// ETRP frequency divided by 8 + Div8 = 0x3, }; - pub const MODE = enum(u2) { - /// Master transmitter - MasterTx = 0x0, - /// Master receiver - MasterRx = 0x1, - /// Slave transmitter - SlaveTx = 0x2, - /// Slave receiver - SlaveRx = 0x3, + pub const FilterValue = enum(u4) { + /// No filter, sampling is done at fDTS + NoFilter = 0x0, + /// fSAMPLING=fCK_INT, N=2 + FCK_INT_N2 = 0x1, + /// fSAMPLING=fCK_INT, N=4 + FCK_INT_N4 = 0x2, + /// fSAMPLING=fCK_INT, N=8 + FCK_INT_N8 = 0x3, + /// fSAMPLING=fDTS/2, N=6 + FDTS_Div2_N6 = 0x4, + /// fSAMPLING=fDTS/2, N=8 + FDTS_Div2_N8 = 0x5, + /// fSAMPLING=fDTS/4, N=6 + FDTS_Div4_N6 = 0x6, + /// fSAMPLING=fDTS/4, N=8 + FDTS_Div4_N8 = 0x7, + /// fSAMPLING=fDTS/8, N=6 + FDTS_Div8_N6 = 0x8, + /// fSAMPLING=fDTS/8, N=8 + FDTS_Div8_N8 = 0x9, + /// fSAMPLING=fDTS/16, N=5 + FDTS_Div16_N5 = 0xa, + /// fSAMPLING=fDTS/16, N=6 + FDTS_Div16_N6 = 0xb, + /// fSAMPLING=fDTS/16, N=8 + FDTS_Div16_N8 = 0xc, + /// fSAMPLING=fDTS/32, N=5 + FDTS_Div32_N5 = 0xd, + /// fSAMPLING=fDTS/32, N=6 + FDTS_Div32_N6 = 0xe, + /// fSAMPLING=fDTS/32, N=8 + FDTS_Div32_N8 = 0xf, }; - pub const MONO = enum(u1) { - /// Stereo mode - Stereo = 0x0, - /// Mono mode - Mono = 0x1, + pub const GC5C = enum(u1) { + /// No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3) + NoEffect = 0x0, + /// TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF + LogicalAND = 0x1, }; - pub const MUTEVAL = enum(u1) { - /// Bit value 0 is sent during the mute mode - SendZero = 0x0, - /// Last values are sent during the mute mode - SendLast = 0x1, + pub const LOCK = enum(u2) { + /// No bit is write protected + Disabled = 0x0, + /// DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written + Level1 = 0x1, + /// LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + Level2 = 0x2, + /// LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + Level3 = 0x3, }; - pub const NODIV = enum(u1) { - /// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value - MasterClock = 0x0, - /// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. - NoDiv = 0x1, + pub const MMS = enum(u3) { + /// The UG bit from the TIMx_EGR register is used as trigger output + Reset = 0x0, + /// The counter enable signal, CNT_EN, is used as trigger output + Enable = 0x1, + /// The update event is selected as trigger output + Update = 0x2, + /// The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + ComparePulse = 0x3, + /// OC1REF signal is used as trigger output + CompareOC1 = 0x4, + /// OC2REF signal is used as trigger output + CompareOC2 = 0x5, + /// OC3REF signal is used as trigger output + CompareOC3 = 0x6, + /// OC4REF signal is used as trigger output + CompareOC4 = 0x7, }; - pub const OUTDRIV = enum(u1) { - /// Audio block output driven when SAIEN is set - OnStart = 0x0, - /// Audio block output driven immediately after the setting of this bit - Immediately = 0x1, + pub const MMS2 = enum(u4) { + /// The UG bit from the TIMx_EGR register is used as TRGO2 + Reset = 0x0, + /// The counter enable signal, CNT_EN, is used as TRGO2 + Enable = 0x1, + /// The update event is selected as TRGO2 + Update = 0x2, + /// TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + ComparePulse = 0x3, + /// OC1REF signal is used as TRGO2 + CompareOC1 = 0x4, + /// OC2REF signal is used as TRGO2 + CompareOC2 = 0x5, + /// OC3REF signal is used as TRGO2 + CompareOC3 = 0x6, + /// OC4REF signal is used as TRGO2 + CompareOC4 = 0x7, + /// OC5REF signal is used as TRGO2 + CompareOC5 = 0x8, + /// OC6REF signal is used as TRGO2 + CompareOC6 = 0x9, + /// OC4REF rising or falling edges generate pulses on TRGO2 + ComparePulse_OC4 = 0xa, + /// OC6REF rising or falling edges generate pulses on TRGO2 + ComparePulse_OC6 = 0xb, + /// OC4REF or OC6REF rising edges generate pulses on TRGO2 + ComparePulse_OC4_Or_OC6_Rising = 0xc, + /// OC4REF rising or OC6REF falling edges generate pulses on TRGO2 + ComparePulse_OC4_Rising_Or_OC6_Falling = 0xd, + /// OC5REF or OC6REF rising edges generate pulses on TRGO2 + ComparePulse_OC5_Or_OC6_Rising = 0xe, + /// OC5REF rising or OC6REF falling edges generate pulses on TRGO2 + ComparePulse_OC5_Rising_Or_OC6_Falling = 0xf, }; - pub const PRTCFG = enum(u2) { - /// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol - Free = 0x0, - /// SPDIF protocol - Spdif = 0x1, - /// AC’97 protocol - Ac97 = 0x2, - _, + pub const MSM = enum(u1) { + /// No action + NoSync = 0x0, + /// The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + Sync = 0x1, }; - pub const SLOTEN = enum(u16) { - /// Inactive slot - Inactive = 0x0, - /// Active slot - Active = 0x1, - _, + pub const OCM = enum(u3) { + /// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + Frozen = 0x0, + /// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + ActiveOnMatch = 0x1, + /// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + InactiveOnMatch = 0x2, + /// OCyREF toggles when TIMx_CNT=TIMx_CCRy + Toggle = 0x3, + /// OCyREF is forced low + ForceInactive = 0x4, + /// OCyREF is forced high + ForceActive = 0x5, + /// In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + PwmMode1 = 0x6, + /// Inversely to PwmMode1 + PwmMode2 = 0x7, }; - pub const SLOTSZ = enum(u2) { - /// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) - DataSize = 0x0, - /// 16-bit - Bit16 = 0x1, - /// 32-bit - Bit32 = 0x2, + pub const OSSI = enum(u1) { + /// When inactive, OC/OCN outputs are disabled + Disabled = 0x0, + /// When inactive, OC/OCN outputs are forced to idle level + IdleLevel = 0x1, + }; + + pub const OSSR = enum(u1) { + /// When inactive, OC/OCN outputs are disabled + Disabled = 0x0, + /// When inactive, OC/OCN outputs are enabled with their inactive level + IdleLevel = 0x1, + }; + + pub const SMS = enum(u4) { + /// Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock. + Disabled = 0x0, + /// Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + Encoder_Mode_1 = 0x1, + /// Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + Encoder_Mode_2 = 0x2, + /// Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + Encoder_Mode_3 = 0x3, + /// Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + Reset_Mode = 0x4, + /// Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + Gated_Mode = 0x5, + /// Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + Trigger_Mode = 0x6, + /// External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + Ext_Clock_Mode = 0x7, + /// Rising edge of the selected trigger input (tim_trgi) reinitializes the counter, generates an update of the registers and starts the counter. + Combined_Reset_Trigger = 0x8, _, }; - pub const SYNCEN = enum(u2) { - /// audio sub-block in asynchronous mode - Asynchronous = 0x0, - /// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode - Internal = 0x1, - /// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode - External = 0x2, + pub const TI1S = enum(u1) { + /// The TIMx_CH1 pin is connected to TI1 input + Normal = 0x0, + /// The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + XOR = 0x1, + }; + + pub const TS = enum(u5) { + /// Internal Trigger 0 + ITR0 = 0x0, + /// Internal Trigger 1 + ITR1 = 0x1, + /// Internal Trigger 2 + ITR2 = 0x2, + /// Internal Trigger 3 + ITR3 = 0x3, + /// TI1 Edge Detector + TI1F_ED = 0x4, + /// Filtered Timer Input 1 + TI1FP1 = 0x5, + /// Filtered Timer Input 2 + TI2FP2 = 0x6, + /// External Trigger input + ETRF = 0x7, _, }; - pub const WCKCFG = enum(u1) { - /// Clock configuration is correct - Correct = 0x0, - /// Clock configuration does not respect the rule concerning the frame length specification - Wrong = 0x1, + pub const URS = enum(u1) { + /// Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + AnyEvent = 0x0, + /// Only counter overflow/underflow generates an update interrupt or DMA request + CounterOnly = 0x1, }; - /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - pub const CH = extern struct { - /// Configuration register 1 + /// 1-channel timers + pub const TIM_1CH = extern struct { + /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - /// SAIx audio block mode immediately - MODE: packed union { + reserved8: u8, + /// Clock division + CKD: packed union { raw: u2, - value: MODE, + value: CKD, }, - /// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. - PRTCFG: packed union { + padding: u22, + }), + reserved12: [8]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/Compare x (x=1) interrupt enable + CCIE: u1, + padding: u30, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1) interrupt flag + CCIF: u1, + reserved9: u7, + /// Capture/Compare x (x=1) overcapture flag + CCOF: u1, + padding: u22, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1) generation + CCG: u1, + padding: u30, + }), + /// capture/compare mode register 1 (input mode) + CCMR_Input: [1]mmio.Mmio(packed struct(u32) { + /// Capture/Compare y selection + CCS: packed union { + raw: u2, + value: CCMR_Input_CCS, + }, + /// Input capture y prescaler + ICPSC: u2, + /// Input capture y filter + ICF: packed union { + raw: u4, + value: FilterValue, + }, + padding: u24, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare x (x=1) output enable + CCE: u1, + /// Capture/Compare x (x=1) output Polarity + CCP: u1, + reserved3: u1, + /// Capture/Compare x (x=1) output Polarity + CCNP: u1, + padding: u28, + }), + reserved52: [16]u8, + /// capture/compare register x (x=1) + CCR: [1]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, + }), + reserved80: [24]u8, + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, + reserved104: [20]u8, + /// input selection register + TISEL: mmio.Mmio(packed struct(u32) { + /// Selects TIM_TIx (x=1) input + TISEL: u4, + padding: u28, + }), + }; + + /// 1-channel with one complementary output timers + pub const TIM_1CH_CMP = extern struct { + reserved4: [4]u8, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: packed union { + raw: u1, + value: CCDS, + }, + reserved8: u4, + /// Output Idle state x (x=1) + OIS: u1, + /// Output Idle state x (x=1) + OISN: u1, + padding: u22, + }), + reserved12: [4]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// COM interrupt enable + COMIE: u1, + reserved7: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare x (x=1) DMA request enable + CCDE: u1, + padding: u22, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// COM interrupt flag + COMIF: u1, + reserved7: u1, + /// Break x (x=1) interrupt flag + BIF: u1, + padding: u24, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Capture/Compare control update generation + COMG: u1, + reserved7: u1, + /// Break x (x=1) generation + BG: u1, + padding: u24, + }), + reserved32: [8]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Capture/Compare x (x=1) complementary output enable + CCNE: u1, + padding: u29, + }), + reserved48: [12]u8, + /// repetition counter register + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition counter value + REP: u8, + padding: u24, + }), + reserved68: [16]u8, + /// break and dead-time register + BDTR: mmio.Mmio(packed struct(u32) { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: packed union { + raw: u2, + value: LOCK, + }, + /// Off-state selection for Idle mode + OSSI: packed union { + raw: u1, + value: OSSI, + }, + /// Off-state selection for Run mode + OSSR: packed union { + raw: u1, + value: OSSR, + }, + /// Break x (x=1) enable + BKE: u1, + /// Break x (x=1) polarity + BKP: packed union { + raw: u1, + value: BKP, + }, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break x (x=1) filter + BKF: packed union { + raw: u4, + value: FilterValue, + }, + padding: u12, + }), + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + reserved96: [16]u8, + /// alternate function register 1 + AF1: mmio.Mmio(packed struct(u32) { + /// TIMx_BKIN input enable + BKINE: u1, + /// TIM_BRK_CMPx (x=1-2) enable + BKCMPE: u1, + reserved8: u6, + /// BRK DFSDM1_BREAKx enable (x=0 if TIM15, x=1 if TIM16, x=2 if TIM17) + BKDF1BKE: u1, + /// TIMx_BKIN input polarity + BKINP: packed union { + raw: u1, + value: BKINP, + }, + /// TIM_BRK_CMPx (x=1-2) input polarity + BKCMPP: packed union { + raw: u1, + value: BKINP, + }, + padding: u21, + }), + }; + + /// 2-channel timers + pub const TIM_2CH = extern struct { + reserved4: [4]u8, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: packed union { + raw: u3, + value: MMS, + }, + /// TI1 selection + TI1S: packed union { + raw: u1, + value: TI1S, + }, + padding: u24, + }), + /// slave mode control register + SMCR: u32, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/Compare x (x=1-2) interrupt enable + CCIE: u1, + reserved6: u4, + /// Trigger interrupt enable + TIE: u1, + padding: u25, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1-2) interrupt flag + CCIF: u1, + reserved6: u4, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare x (x=1-2) overcapture flag + CCOF: u1, + padding: u22, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1-2) generation + CCG: u1, + reserved6: u4, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (input mode) + CCMR_Input: [1]mmio.Mmio(packed struct(u32) { + /// Capture/Compare y selection + CCS: packed union { + raw: u2, + value: CCMR_Input_CCS, + }, + /// Input capture y prescaler + ICPSC: u2, + /// Input capture y filter + ICF: packed union { + raw: u4, + value: FilterValue, + }, + padding: u24, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare x (x=1-2) output enable + CCE: u1, + /// Capture/Compare x (x=1-2) output Polarity + CCP: u1, + reserved3: u1, + /// Capture/Compare x (x=1-2) output Polarity + CCNP: u1, + padding: u28, + }), + reserved52: [16]u8, + /// capture/compare register x (x=1-2) + CCR: [2]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, + }), + reserved104: [44]u8, + /// input selection register + TISEL: mmio.Mmio(packed struct(u32) { + /// Selects TIM_TIx (x=1-2) input + TISEL: u4, + padding: u28, + }), + }; + + /// 2-channel with one complementary output timers + pub const TIM_2CH_CMP = extern struct { + reserved4: [4]u8, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: packed union { + raw: u3, + value: MMS, + }, + /// TI1 selection + TI1S: packed union { + raw: u1, + value: TI1S, + }, + /// Output Idle state x (x=1,2) + OIS: u1, + padding: u23, + }), + /// slave mode control register + SMCR: u32, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// Trigger interrupt enable + TIE: u1, + reserved13: u6, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1,2) interrupt flag + CCIF: u1, + reserved6: u4, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare x (x=1,2) overcapture flag + CCOF: u1, + padding: u22, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1,2) generation + CCG: u1, + reserved6: u4, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (input mode) + CCMR_Input: [2]mmio.Mmio(packed struct(u32) { + /// Capture/Compare y selection + CCS: packed union { + raw: u2, + value: CCMR_Input_CCS, + }, + /// Input capture y prescaler + ICPSC: u2, + /// Input capture y filter + ICF: packed union { + raw: u4, + value: FilterValue, + }, + padding: u24, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Capture/Compare x (x=1) complementary output enable + CCNE: u1, + padding: u29, + }), + reserved52: [16]u8, + /// capture/compare register x (x=1-2) + CCR: [2]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, + }), + reserved68: [8]u8, + /// break and dead-time register + BDTR: mmio.Mmio(packed struct(u32) { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: packed union { raw: u2, - value: PRTCFG, + value: LOCK, }, - reserved5: u1, - /// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. - DS: packed union { - raw: u3, - value: DS, + /// Off-state selection for Idle mode + OSSI: packed union { + raw: u1, + value: OSSI, }, - /// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. - LSBFIRST: packed union { + /// Off-state selection for Run mode + OSSR: packed union { raw: u1, - value: LSBFIRST, + value: OSSR, }, - /// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. - CKSTR: packed union { + /// Break x (x=1) enable + BKE: u1, + /// Break x (x=1) polarity + BKP: packed union { raw: u1, - value: CKSTR, + value: BKP, }, - /// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. - SYNCEN: packed union { - raw: u2, - value: SYNCEN, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break x (x=1) filter + BKF: packed union { + raw: u4, + value: FilterValue, }, - /// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. - MONO: packed union { + padding: u12, + }), + reserved104: [32]u8, + /// input selection register + TISEL: mmio.Mmio(packed struct(u32) { + /// Selects TIM_TIx (x=1-2) input + TISEL: u4, + padding: u28, + }), + }; + + /// Advanced Control timers + pub const TIM_ADV = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Direction + DIR: packed union { raw: u1, - value: MONO, + value: DIR, }, - /// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. - OUTDRIV: packed union { - raw: u1, - value: OUTDRIV, + /// Center-aligned mode selection + CMS: packed union { + raw: u2, + value: CMS, }, - reserved16: u2, - /// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. - SAIEN: u1, - /// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. - DMAEN: u1, - reserved19: u1, - /// No fixed divider between MCLK and FS - NODIV: packed union { - raw: u1, - value: NODIV, + reserved8: u1, + /// Clock division + CKD: packed union { + raw: u2, + value: CKD, }, - /// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: - MCKDIV: u6, - /// Oversampling ratio for master clock - OSR: u1, - /// Master clock generation enable - MCKEN: u1, - padding: u4, + padding: u22, }), - /// Configuration register 2 + /// control register 2 CR2: mmio.Mmio(packed struct(u32) { - /// FIFO threshold. This bit is set and cleared by software. - FTH: packed union { - raw: u3, - value: FTH, + reserved8: u8, + /// Output Idle state x (x=1-6) + OIS: u1, + /// Output Idle state x N x (x=1-4) + OISN: u1, + reserved20: u10, + /// Master mode selection 2 + MMS2: packed union { + raw: u4, + value: MMS2, }, - /// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. - FFLUSH: u1, - /// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. - TRIS: u1, - /// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. - MUTE: u1, - /// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. - MUTEVAL: packed union { - raw: u1, - value: MUTEVAL, + padding: u8, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// External trigger filter + ETF: packed union { + raw: u4, + value: FilterValue, }, - /// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. - MUTECNT: u6, - /// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. - CPL: packed union { + /// External trigger prescaler + ETPS: packed union { + raw: u2, + value: ETPS, + }, + /// External clock mode 2 enable + ECE: u1, + /// External trigger polarity + ETP: packed union { raw: u1, - value: CPL, + value: ETP, }, - /// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. - COMP: packed union { + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/Compare x (x=1-4) interrupt enable + CCIE: u1, + reserved9: u7, + /// Capture/Compare x (x=1-4) DMA request enable + CCDE: u1, + padding: u22, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1-4) interrupt flag + CCIF: u1, + reserved7: u5, + /// Break x (x=1,2) interrupt flag + BIF: u1, + reserved9: u1, + /// Capture/Compare x (x=1-4) overcapture flag + CCOF: u1, + reserved13: u3, + /// System break interrupt flag + SBIF: u1, + reserved16: u2, + /// Capture/compare 5 interrupt flag + CCIF5: u1, + /// Capture/compare 6 interrupt flag + CCIF6: u1, + padding: u14, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1-4) generation + CCG: u1, + reserved7: u5, + /// Break x (x=1-2) generation + BG: u1, + padding: u24, + }), + /// capture/compare mode register 1-2 (input mode) + CCMR_Input: [2]mmio.Mmio(packed struct(u32) { + /// Capture/Compare y selection + CCS: packed union { raw: u2, - value: COMP, + value: CCMR_Input_CCS, + }, + /// Input capture y prescaler + ICPSC: u2, + /// Input capture y filter + ICF: packed union { + raw: u4, + value: FilterValue, }, + padding: u24, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare x (x=1-6) output enable + CCE: u1, + /// Capture/Compare x (x=1-6) output Polarity + CCP: u1, + /// Capture/Compare x (x=1-3) complementary output enable + CCNE: u1, + /// Capture/Compare x (x=1-4) output Polarity + CCNP: u1, + padding: u28, + }), + reserved48: [12]u8, + /// repetition counter register + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition counter value + REP: u16, padding: u16, }), - /// This register has no meaning in AC97 and SPDIF audio protocol - FRCR: mmio.Mmio(packed struct(u32) { - /// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. - FRL: u8, - /// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. - FSALL: u7, - reserved16: u1, - /// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. - FSDEF: u1, - /// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - FSPOL: packed union { + /// capture/compare register x (x=1-4) + CCR: [4]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, + }), + /// break and dead-time register + BDTR: mmio.Mmio(packed struct(u32) { + reserved12: u12, + /// Break x (x=1,2) enable + BKE: u1, + /// Break x (x=1,2) polarity + BKP: packed union { raw: u1, - value: FSPOL, + value: BKP, }, - /// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. - FSOFF: packed union { - raw: u1, - value: FSOFF, + reserved16: u2, + /// Break x (x=1,2) filter + BKF: packed union { + raw: u4, + value: FilterValue, }, - padding: u13, + padding: u12, }), - /// This register has no meaning in AC97 and SPDIF audio protocol - SLOTR: mmio.Mmio(packed struct(u32) { - /// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - FBOFF: u5, - reserved6: u1, - /// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - SLOTSZ: packed union { - raw: u2, - value: SLOTSZ, + reserved76: [4]u8, + /// DMA address for full transfer + DMAR: u32, + reserved84: [4]u8, + /// capture/compare mode register 3 + CCMR3: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Output compare x (x=5,6) fast enable + OCFE: u1, + /// Output compare x (x=5,6) preload enable + OCPE: u1, + /// Output compare x (x=5,6) mode + OCM: packed union { + raw: u3, + value: OCM, }, - /// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - NBSLOT: u4, - reserved16: u4, - /// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. - SLOTEN: packed union { - raw: u16, - value: SLOTEN, + /// Output compare x (x=5,6) clear enable + OCCE: u1, + padding: u24, + }), + /// capture/compare register 5 + CCR5: mmio.Mmio(packed struct(u32) { + reserved29: u29, + /// Group channel 5 and channel x (x=1-3) + GC5C: packed union { + raw: u1, + value: GC5C, }, + padding: u2, }), - /// Interrupt mask register 2 - IM: mmio.Mmio(packed struct(u32) { - /// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. - OVRUDRIE: u1, - /// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. - MUTEDETIE: u1, - /// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. - WCKCFGIE: u1, - /// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, - FREQIE: u1, - /// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. - CNRDYIE: u1, - /// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. - AFSDETIE: u1, - /// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. - LFSDETIE: u1, - padding: u25, + /// capture/compare register 6 + CCR6: mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. - OVRUDR: u1, - /// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. - MUTEDET: u1, - /// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. - WCKCFG: packed union { + /// alternate function register 1 + AF1: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// etr_in source selection + ETRSEL: u4, + padding: u14, + }), + /// alternate function register 2 + AF2: mmio.Mmio(packed struct(u32) { + /// TIMx_BKIN2 input enable + BK2INE: u1, + /// TIM_BRK2_CMPx (x=1-8) enable + BK2CMPE: u1, + reserved8: u6, + /// BRK2 DFSDM1_BREAK1 enable + BK2DF1BK1E: u1, + /// TIMx_BK2IN input polarity + BK2INP: packed union { raw: u1, - value: WCKCFG, + value: BKINP, }, - /// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. - FREQ: u1, - /// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. - CNRDY: packed union { + /// TIM_BRK2_CMPx (x=1-4) input polarity + BK2CMPP: packed union { raw: u1, - value: CNRDY, - }, - /// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. - AFSDET: u1, - /// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register - LFSDET: u1, - reserved16: u9, - /// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: - FLVL: packed union { - raw: u3, - value: FLVL, + value: BKINP, }, - padding: u13, - }), - /// Clear flag register - CLRFR: mmio.Mmio(packed struct(u32) { - /// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. - COVRUDR: u1, - /// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. - CMUTEDET: u1, - /// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. - CWCKCFG: u1, - reserved4: u1, - /// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. - CCNRDY: u1, - /// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. - CAFSDET: u1, - /// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. - CLFSDET: u1, - padding: u25, + padding: u21, }), - /// Data register - DR: mmio.Mmio(packed struct(u32) { - /// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. - DATA: u32, + /// input selection register + TISEL: mmio.Mmio(packed struct(u32) { + /// Selects TIM_TIx (x=1-4) input + TISEL: u4, + padding: u28, }), }; - /// Serial audio interface - pub const SAI = extern struct { - /// Global configuration register - GCR: mmio.Mmio(packed struct(u32) { - /// Synchronization inputs - SYNCIN: u2, - reserved4: u2, - /// Synchronization outputs These bits are set and cleared by software. - SYNCOUT: u2, - padding: u26, - }), - /// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR - CH: u32, - reserved68: [60]u8, - /// PDM control register - PDMCR: mmio.Mmio(packed struct(u32) { - /// PDM enable - PDMEN: u1, - reserved4: u3, - /// Number of microphones - MICNBR: u2, - reserved8: u2, - /// Clock enable of bitstream clock number 1 - CKEN: u1, - padding: u23, - }), - /// PDM delay register - PDMDLY: mmio.Mmio(packed struct(u32) { - /// Delay line adjust for first microphone of pair 1 - DLYML: u3, - reserved4: u1, - /// Delay line adjust for second microphone of pair 1 - DLYMR: u3, + /// Basic timers + pub const TIM_BASIC = extern struct { + reserved4: [4]u8, + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: packed union { + raw: u3, + value: MMS, + }, padding: u25, }), }; - }; - - pub const adc_v1 = struct { - pub const ALIGN = enum(u1) { - /// Right alignment - Right = 0x0, - /// Left alignment - Left = 0x1, - }; - - pub const AWDSGL = enum(u1) { - /// Analog watchdog enabled on all channels - AllChannels = 0x0, - /// Analog watchdog enabled on a single channel - SingleChannel = 0x1, - }; - - pub const CKMODE = enum(u2) { - /// Asynchronous clock mode - ADCCLK = 0x0, - /// Synchronous clock mode (PCLK/2) - PCLK_Div2 = 0x1, - /// Sychronous clock mode (PCLK/4) - PCLK_Div4 = 0x2, - _, - }; - - pub const DMACFG = enum(u1) { - /// DMA One Shot mode selected - OneShot = 0x0, - /// DMA Circular mode selected - Circular = 0x1, - }; - - pub const EXTEN = enum(u2) { - /// Trigger detection disabled - Disabled = 0x0, - /// Trigger detection on the rising edge - RisingEdge = 0x1, - /// Trigger detection on the falling edge - FallingEdge = 0x2, - /// Trigger detection on both the rising and falling edges - BothEdges = 0x3, - }; - - pub const OVRMOD = enum(u1) { - /// ADC_DR register is preserved with the old data when an overrun is detected - Preserved = 0x0, - /// ADC_DR register is overwritten with the last conversion result when an overrun is detected - Overwritten = 0x1, - }; - - pub const RES = enum(u2) { - /// 12-bit (14 ADCCLK cycles) - Bits12 = 0x0, - /// 10-bit (13 ADCCLK cycles) - Bits10 = 0x1, - /// 8-bit (11 ADCCLK cycles) - Bits8 = 0x2, - /// 6-bit (9 ADCCLK cycles) - Bits6 = 0x3, - }; - - pub const SAMPLE_TIME = enum(u3) { - /// 1.5 cycles - Cycles1_5 = 0x0, - /// 7.5 cycles - Cycles7_5 = 0x1, - /// 13.5 cycles - Cycles13_5 = 0x2, - /// 28.5 cycles - Cycles28_5 = 0x3, - /// 41.5 cycles - Cycles41_5 = 0x4, - /// 55.5 cycles - Cycles55_5 = 0x5, - /// 71.5 cycles - Cycles71_5 = 0x6, - /// 239.5 cycles - Cycles239_5 = 0x7, - }; - pub const SCANDIR = enum(u1) { - /// Upward scan (from CHSEL0 to CHSEL18) - Upward = 0x0, - /// Backward scan (from CHSEL18 to CHSEL0) - Backward = 0x1, + /// Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP + pub const TIM_BASIC_NO_CR2 = extern struct { + reserved12: [12]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// Update DMA request enable + UDE: u1, + padding: u23, + }), }; - /// Analog-to-digital converter - pub const ADC = extern struct { - /// interrupt and status register - ISR: mmio.Mmio(packed struct(u32) { - /// ADC ready - ADRDY: u1, - /// End of sampling flag - EOSMP: u1, - /// End of conversion flag - EOC: u1, - /// End of sequence flag - EOSEQ: u1, - /// ADC overrun - OVR: u1, - reserved7: u2, - /// Analog watchdog flag - AWD: u1, - padding: u24, + /// Virtual timer for common part of TIM_BASIC and TIM_1CH + pub const TIM_CORE = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: packed union { + raw: u1, + value: URS, + }, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + reserved11: u3, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, }), - /// interrupt enable register - IER: mmio.Mmio(packed struct(u32) { - /// ADC ready interrupt enable - ADRDYIE: u1, - /// End of sampling flag interrupt enable - EOSMPIE: u1, - /// End of conversion interrupt enable - EOCIE: u1, - /// End of conversion sequence interrupt enable - EOSEQIE: u1, - /// Overrun interrupt enable - OVRIE: u1, - reserved7: u2, - /// Analog watchdog interrupt enable - AWDIE: u1, - padding: u24, + reserved12: [8]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + padding: u31, }), - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// ADC enable command - ADEN: u1, - /// ADC disable command - ADDIS: u1, - /// ADC start conversion command - ADSTART: u1, - reserved4: u1, - /// ADC stop conversion command - ADSTP: u1, - reserved31: u26, - /// ADC calibration - ADCAL: u1, + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + padding: u31, }), - /// configuration register 1 - CFGR1: mmio.Mmio(packed struct(u32) { - /// Direct memory access enable - DMAEN: u1, - /// Direct memory access configuration - DMACFG: packed union { - raw: u1, - value: DMACFG, - }, - /// Scan sequence direction - SCANDIR: packed union { + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + padding: u31, + }), + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + }; + + /// General purpose 16-bit timers + pub const TIM_GP16 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Direction + DIR: packed union { raw: u1, - value: SCANDIR, + value: DIR, }, - /// Data resolution - RES: packed union { + /// Center-aligned mode selection + CMS: packed union { raw: u2, - value: RES, - }, - /// Data alignment - ALIGN: packed union { - raw: u1, - value: ALIGN, + value: CMS, }, - /// External trigger selection - EXTSEL: u3, - reserved10: u1, - /// External trigger enable and polarity selection - EXTEN: packed union { + reserved8: u1, + /// Clock division + CKD: packed union { raw: u2, - value: EXTEN, + value: CKD, }, - /// Overrun management mode - OVRMOD: packed union { + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Capture/compare DMA selection + CCDS: packed union { raw: u1, - value: OVRMOD, + value: CCDS, }, - /// Continuous conversion - CONT: u1, - /// Wait conversion mode - WAIT: u1, - /// Auto-off mode - AUTOFF: u1, - /// Discontinuous mode - DISCEN: u1, - reserved22: u5, - /// Enable the watchdog on a single channel or on all channels - AWDSGL: packed union { + reserved7: u3, + /// TI1 selection + TI1S: packed union { raw: u1, - value: AWDSGL, + value: TI1S, }, - /// Analog watchdog enable - AWDEN: u1, - reserved26: u2, - /// Analog watchdog channel selection - AWDCH: u5, - padding: u1, + padding: u24, }), - /// configuration register 2 - CFGR2: mmio.Mmio(packed struct(u32) { - reserved30: u30, - /// ADC clock mode - CKMODE: packed union { + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// External trigger filter + ETF: packed union { + raw: u4, + value: FilterValue, + }, + /// External trigger prescaler + ETPS: packed union { raw: u2, - value: CKMODE, + value: ETPS, }, - }), - /// sampling time register - SMPR: mmio.Mmio(packed struct(u32) { - /// Sampling time selection - SMP: packed union { - raw: u3, - value: SAMPLE_TIME, + /// External clock mode 2 enable + ECE: u1, + /// External trigger polarity + ETP: packed union { + raw: u1, + value: ETP, }, - padding: u29, - }), - reserved32: [8]u8, - /// watchdog threshold register - TR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog lower threshold - LT: u12, - reserved16: u4, - /// Analog watchdog higher threshold - HT: u12, - padding: u4, - }), - reserved40: [4]u8, - /// channel selection register - CHSELR: mmio.Mmio(packed struct(u32) { - /// Channel-x selection - @"CHSEL x": u1, - padding: u31, - }), - reserved64: [20]u8, - /// data register - DR: mmio.Mmio(packed struct(u32) { - /// Converted data - DATA: u16, padding: u16, }), - reserved776: [708]u8, - /// common configuration register - CCR: mmio.Mmio(packed struct(u32) { - reserved22: u22, - /// Temperature sensor and VREFINT enable - VREFEN: u1, - /// Temperature sensor enable - TSEN: u1, - /// VBAT enable - VBATEN: u1, - padding: u7, - }), - }; - }; - - pub const syscfg_h7rs = struct { - pub const AXIRAM_WS = enum(u1) { - /// No wait state added when accessing any AXIRAM with ECC = 0. - Ws0 = 0x0, - /// One wait state added when accessing any AXIRAM with ECC = 0. In this case, Fmax = 500 MHz is not guaranteed. (TBC). - Ws1 = 0x1, - }; - - pub const DBGCFG_LOCK = enum(u8) { - /// Writes to SBS_DBGCR allowed (default). - Unlock = 0xb4, - _, - }; - - pub const DBG_AUTH_HDPL = enum(u8) { - /// HDPL1. - HDPL1 = 0x51, - /// HDPL3. - HDPL3 = 0x6f, - /// HDPL2. - HDPL2 = 0x8a, - _, - }; - - pub const ETH_SEL_PHY = enum(u3) { - /// GMII or MII - MII_GMII = 0x0, - /// RMII - RMII = 0x4, - _, - }; - - pub const HDPL = enum(u8) { - /// HDPL1. - HDPL1 = 0x51, - /// HDPL2. - HDPL2 = 0x8a, - /// HDPL0, corresponding to ST-RSS (default when device is close). - HDPL0 = 0xb4, - _, - }; - - /// System configuration, boot and security. - pub const SYSCFG = extern struct { - /// SBS boot status register. - BOOTSR: mmio.Mmio(packed struct(u32) { - /// initial vector for Cortex-M7 This register includes the physical boot address used by the Cortex-M7 after reset. - INITVTOR: u32, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/Compare x (x=1-4) interrupt enable + CCIE: u1, + reserved6: u4, + /// Trigger interrupt enable + TIE: u1, + reserved9: u2, + /// Capture/Compare x (x=1-4) DMA request enable + CCDE: u1, + reserved14: u4, + /// Trigger DMA request enable + TDE: u1, + padding: u17, }), - reserved16: [12]u8, - /// SBS hide protection control register. - HDPLCR: mmio.Mmio(packed struct(u32) { - /// increment HDPL Write 0x6A to increment device HDPL by one. After a write, the register value reverts to its default value (0xB4). - INCR_HDPL: u8, - padding: u24, + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1-4) interrupt flag + CCIF: u1, + reserved6: u4, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare x (x=1-4) overcapture flag + CCOF: u1, + padding: u22, }), - /// SBS hide protection status register. - HDPLSR: mmio.Mmio(packed struct(u32) { - /// hide protection level This bitfield returns the current HDPL of the device. 0x6F and other codes: HDPL3, corresponding to non-boot application. Note: The device state (open/close) is defined in FLASH_NVSTATER register of the embedded Flash memory. - HDPL: packed union { - raw: u8, - value: HDPL, - }, - padding: u24, + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Capture/compare x (x=1-4) generation + CCG: u1, + reserved6: u4, + /// Trigger generation + TG: u1, + padding: u25, }), - reserved32: [8]u8, - /// SBS debug control register. - DBGCR: mmio.Mmio(packed struct(u32) { - /// access port unlock Write 0xB4 to this bitfield to open the device access port. - AP_UNLOCK: u8, - /// debug unlock Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register. - DBG_UNLOCK: u8, - /// authenticated debug hide protection level Writing to this bitfield defines at which HDPL the authenticated debug opens. Note: Writing any other values is ignored. Reading any other value means the authenticated debug always fails. - DBG_AUTH_HDPL: packed union { - raw: u8, - value: DBG_AUTH_HDPL, + /// capture/compare mode register 1-2 (input mode) + CCMR_Input: [2]mmio.Mmio(packed struct(u32) { + /// Capture/Compare y selection + CCS: packed union { + raw: u2, + value: CCMR_Input_CCS, }, - padding: u8, - }), - /// SBS debug lock register. - DBGLOCKR: mmio.Mmio(packed struct(u32) { - /// debug configuration lock Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4. Other: Writes to SBS_DBGCR ignored Note: 0xC3 is the recommended value to lock the debug configuration using this bitfield. - DBGCFG_LOCK: packed union { - raw: u8, - value: DBGCFG_LOCK, + /// Input capture y prescaler + ICPSC: u2, + /// Input capture y filter + ICF: packed union { + raw: u4, + value: FilterValue, }, padding: u24, }), - reserved52: [12]u8, - /// SBS RSS command register. - RSSCMDR: mmio.Mmio(packed struct(u32) { - /// RSS command The application can use this bitfield to pass on a command to the RSS, executed at the next reset. - RSSCMD: u16, - padding: u16, - }), - reserved256: [200]u8, - /// SBS product mode and configuration register. - PMCR: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Fast-mode Plus on PB(6). - FMPLUS_PB6: u1, - /// Fast-mode Plus on PB(7). - FMPLUS_PB7: u1, - /// Fast-mode Plus on PB(8). - FMPLUS_PB8: u1, - /// Fast-mode Plus on PB(9). - FMPLUS_PB9: u1, - /// booster enable Set this bit to reduce the THD of the analog switches when the supply voltage is below 2.7 V. guaranteeing the same performance as with the full voltage range. To avoid current consumption due to booster activation when VDDA < 2.7 V and VDD > 2.7 V, VDD can be selected as supply voltage for analog switches by setting BOOSTVDDSEL bit in SBS_PMCR. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption. - BOOSTEN: u1, - /// booster VDD selection This bit selects the analog switch supply voltage, between VDD, VDDA and booster. To avoid current consumption due to booster activation when VDDA < 2.7 V and VDD > 2.7 V, VDD can be selected as supply voltage for analog switches. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption. When both VDD and VDDA are below 2.7 V, the booster is still needed to obtain full AC performances from the I/O analog switches. - BOOSTVDDSEL: u1, - reserved21: u11, - /// Ethernet PHY interface selection. - ETH_SEL_PHY: packed union { - raw: u3, - value: ETH_SEL_PHY, - }, - reserved28: u4, - /// AXIRAM wait state Set this bit to add one wait state to all AXIRAMs when ECC = 0. When ECC = 1 there is one wait state by default. - AXIRAM_WS: packed union { - raw: u1, - value: AXIRAM_WS, - }, - padding: u3, - }), - /// SBS FPU interrupt mask register. - FPUIMR: mmio.Mmio(packed struct(u32) { - /// FPU interrupt enable Set and cleared by software to enable the Cortex-M7 FPU interrupts xxxxx1: Invalid operation interrupt enabled (xxxxx0 to disable) xxxx1x: Divide-by-zero interrupt enabled (xxxx0x to disable) xxx1xx: Underflow interrupt enabled (xxx0xx to disable) xx1xxx: Overflow interrupt enabled (xx0xxx to disable) x1xxxx: Input denormal interrupt enabled (x0xxxx to disable) 1xxxxx: Inexact interrupt enabled (0xxxxx to disable), disabled by default. - FPU_IE: u6, - padding: u26, - }), - /// SBS memory erase status register. - MESR: mmio.Mmio(packed struct(u32) { - /// memory erase flag This bit is set by hardware when BKPRAM and PKA SRAM erase is ongoing after a POWER ON reset or one tamper event (see Section 50: Tamper and backup registers (TAMP) for details). This bit is cleared when the erase is done. - MEF: u1, - padding: u31, - }), - reserved272: [4]u8, - /// SBS I/O compensation cell control and status register. - CCCSR: mmio.Mmio(packed struct(u32) { - /// Compensation cell enable Set this bit to enable the compensation cell. - COMP_EN: u1, - /// Compensation cell code selection This bit selects the code to be applied for the I/O compensation cell. - COMP_CODESEL: u1, - /// XSPIM_P1 compensation cell enable Set this bit to enable the XSPIM_P1 compensation cell. - OCTO1_COMP_EN: u1, - /// XSPIM_P1 compensation cell code selection This bit selects the code to be applied for the XSPIM_P1 I/O compensation cell. - OCTO1_COMP_CODESEL: u1, - /// XSPIM_P2 compensation cell enable Set this bit to enable the XSPIM_P2 compensation cell. - OCTO2_COMP_EN: u1, - /// XSPIM_P2 compensation cell code selection This bit selects the code to be applied for the XSPIM_P2 I/O compensation cell. - OCTO2_COMP_CODESEL: u1, - reserved8: u2, - /// Compensation cell ready This bit provides the status of the compensation cell. - COMP_RDY: u1, - /// XSPIM_P1 compensation cell ready This bit provides the status of the XSPIM_P1 compensation cell. - OCTO1_COMP_RDY: u1, - /// XSPIM_P2 compensation cell ready This bit provides the status of the XSPIM_P2 compensation cell. - OCTO2_COMP_RDY: u1, - reserved16: u5, - /// I/O high speed at low voltage When this bit is set, the speed of the I/Os is optimized when the device voltage is low. This bit is active only if VDDIO_HSLV user option bit is set in FLASH. It must be used only if the device supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V may be destructive. - IOHSLV: u1, - /// XSPIM_P1 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P1 I/Os is optimized when the device voltage is low. This bit is active only if OCTO1_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V may be destructive. - OCTO1_IOHSLV: u1, - /// XSPIM_P2 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P2 I/Os is optimized when the device voltage is low. This bit is active only if OCTO2_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V may be destructive. - OCTO2_IOHSLV: u1, - padding: u13, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare x (x=1-4) output enable + CCE: u1, + /// Capture/Compare x (x=1-4) output Polarity + CCP: u1, + reserved3: u1, + /// Capture/Compare x (x=1-4) output Polarity + CCNP: u1, + padding: u28, }), - /// SBS compensation cell for I/Os value register. - CCVALR: mmio.Mmio(packed struct(u32) { - /// NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register. - NSRC: u4, - /// PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register. - PSRC: u4, - /// XSPIM_P1 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register. - OCTO1_NSRC: u4, - /// XSPIM_P1 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register. - OCTO1_PSRC: u4, - /// XSPIM_P2 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register. - OCTO2_NSRC: u4, - /// XSPIM_P2 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register. - OCTO2_PSRC: u4, - padding: u8, + reserved52: [16]u8, + /// capture/compare register x (x=1-4) + CCR: [4]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, }), - /// SBS compensation cell for I/Os software value register. - CCSWVALR: mmio.Mmio(packed struct(u32) { - /// Software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register. - SW_NSRC: u4, - /// Software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register. - SW_PSRC: u4, - /// XSPIM_P1 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew -ate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register. - OCTO1_SW_NSRC: u4, - /// XSPIM_P1 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register. - OCTO1_SW_PSRC: u4, - /// XSPIM_P2 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register. - OCTO2_SW_NSRC: u4, - /// XSPIM_P2 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register. - OCTO2_SW_PSRC: u4, - padding: u8, + reserved72: [4]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, }), - reserved288: [4]u8, - /// SBS break lockup register. - BKLOCKR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// PVD break lock This bit is set by SW and cleared only by a system reset. it can be used to enable and lock the connection to TIM1/8/15/16/17Break input as well as the PVDE and PLS[2:0] bitfields in the PWR_CR1 register. Once set, this bit is cleared only by a system reset. - PVD_BL: u1, - /// Flash ECC error break lock Set this bit to enable and lock the connection between embedded flash memory ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. - FLASHECC_BL: u1, - reserved6: u2, - /// Cortex-M7 lockup break lock Set this bit to enable and lock the connection between the Cortex-M7 lockup (HardFault) output and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. - CM7LCKUP_BL: u1, - /// Backup RAM ECC error break lock Set this bit to enable and lock the connection between backup RAM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. - BKRAMECC_BL: u1, - reserved13: u5, - /// DTCM ECC error break lock Set this bit to enable and lock the connection between DTCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. Note: The DTCM0 and DTCM1 are Ored to give DTCMECC. - DTCMECC_BL: u1, - /// ITCM ECC error break lock Set this bit to enable and lock the connection between ITCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. - ITCMECC_BL: u1, - reserved21: u6, - /// AXIRAM3 ECC error break lock Set this bit to enable and lock the connection between AXIRAM3 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set this bit is cleared only by a system reset. - ARAM3ECC_BL: u1, - reserved23: u1, - /// AXIRAM1 ECC error break lock Set this bit to enable and lock the connection between AXIRAM1 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. - ARAM1ECC_BL: u1, - padding: u8, + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, }), - reserved304: [12]u8, - /// external interrupt configuration register - EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration (x = 4 to 7) - EXTI: u4, + reserved96: [16]u8, + /// alternate function register 1 + AF1: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// etr_in source selection + ETRSEL: u4, + padding: u14, + }), + reserved104: [4]u8, + /// input selection register + TISEL: mmio.Mmio(packed struct(u32) { + /// Selects TIM_TIx (x=1-4) input + TISEL: u4, padding: u28, }), }; + + /// General purpose 32-bit timers + pub const TIM_GP32 = extern struct { + reserved36: [36]u8, + /// counter + CNT: u32, + reserved44: [4]u8, + /// auto-reload register + ARR: u32, + reserved52: [4]u8, + /// capture/compare register x (x=1-4) + CCR: [4]u32, + }; }; pub const timer_v2 = struct { @@ -438647,3169 +437152,4664 @@ pub const types = struct { TISEL: u4, padding: u28, }), - /// alternate function register 1 - AF1: mmio.Mmio(packed struct(u32) { - reserved14: u14, - /// etr_in source selection - ETRSEL: u4, - padding: u14, + /// alternate function register 1 + AF1: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// etr_in source selection + ETRSEL: u4, + padding: u14, + }), + /// alternate function register 2 + AF2: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// ocref_clr source selection + OCRSEL: u3, + padding: u13, + }), + reserved988: [884]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + reserved16: u3, + /// DMA burst source selection + DBSS: packed union { + raw: u4, + value: DBSS, + }, + padding: u12, + }), + /// DMA address for full transfer + DMAR: u32, + }; + + /// General purpose 32-bit timers + pub const TIM_GP32 = extern struct { + reserved36: [36]u8, + /// counter (Dither mode disabled) + CNT: u32, + reserved44: [4]u8, + /// auto-reload register (Dither mode disabled) + ARR: u32, + reserved52: [4]u8, + /// capture/compare register x (x=1-4) (Dither mode disabled) + CCR: [4]u32, + }; + }; + + pub const tsc_v1 = struct { + /// Touch sensing controller. + pub const TSC = extern struct { + /// control register. + CR: mmio.Mmio(packed struct(u32) { + /// Touch sensing controller enable. + TSCE: u1, + /// Start a new acquisition. + START: u1, + /// Acquisition mode. + AM: u1, + /// Synchronization pin polarity. + SYNCPOL: u1, + /// I/O Default mode. + IODEF: u1, + /// Max count value. + MCV: u3, + reserved12: u4, + /// pulse generator prescaler. + PGPSC: u3, + /// Spread spectrum prescaler. + SSPSC: u1, + /// Spread spectrum enable. + SSE: u1, + /// Spread spectrum deviation. + SSD: u7, + /// Charge transfer pulse low. + CTPL: u4, + /// Charge transfer pulse high. + CTPH: u4, + }), + /// interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// End of acquisition interrupt enable. + EOAIE: u1, + /// Max count error interrupt enable. + MCEIE: u1, + padding: u30, + }), + /// interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// End of acquisition interrupt clear. + EOAIC: u1, + /// Max count error interrupt clear. + MCEIC: u1, + padding: u30, + }), + /// interrupt status register. + ISR: mmio.Mmio(packed struct(u32) { + /// End of acquisition flag. + EOAF: u1, + /// Max count error flag. + MCEF: u1, + padding: u30, + }), + /// I/O hysteresis control register. + IOHCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 Schmitt trigger hysteresis mode. + G1_IO1: u1, + /// G1_IO2 Schmitt trigger hysteresis mode. + G1_IO2: u1, + /// G1_IO3 Schmitt trigger hysteresis mode. + G1_IO3: u1, + /// G1_IO4 Schmitt trigger hysteresis mode. + G1_IO4: u1, + /// G2_IO1 Schmitt trigger hysteresis mode. + G2_IO1: u1, + /// G2_IO2 Schmitt trigger hysteresis mode. + G2_IO2: u1, + /// G2_IO3 Schmitt trigger hysteresis mode. + G2_IO3: u1, + /// G2_IO4 Schmitt trigger hysteresis mode. + G2_IO4: u1, + /// G3_IO1 Schmitt trigger hysteresis mode. + G3_IO1: u1, + /// G3_IO2 Schmitt trigger hysteresis mode. + G3_IO2: u1, + /// G3_IO3 Schmitt trigger hysteresis mode. + G3_IO3: u1, + /// G3_IO4 Schmitt trigger hysteresis mode. + G3_IO4: u1, + /// G4_IO1 Schmitt trigger hysteresis mode. + G4_IO1: u1, + /// G4_IO2 Schmitt trigger hysteresis mode. + G4_IO2: u1, + /// G4_IO3 Schmitt trigger hysteresis mode. + G4_IO3: u1, + /// G4_IO4 Schmitt trigger hysteresis mode. + G4_IO4: u1, + /// G5_IO1 Schmitt trigger hysteresis mode. + G5_IO1: u1, + /// G5_IO2 Schmitt trigger hysteresis mode. + G5_IO2: u1, + /// G5_IO3 Schmitt trigger hysteresis mode. + G5_IO3: u1, + /// G5_IO4 Schmitt trigger hysteresis mode. + G5_IO4: u1, + /// G6_IO1 Schmitt trigger hysteresis mode. + G6_IO1: u1, + /// G6_IO2 Schmitt trigger hysteresis mode. + G6_IO2: u1, + /// G6_IO3 Schmitt trigger hysteresis mode. + G6_IO3: u1, + /// G6_IO4 Schmitt trigger hysteresis mode. + G6_IO4: u1, + padding: u8, + }), + reserved24: [4]u8, + /// I/O analog switch control register. + IOASCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 analog switch enable. + G1_IO1: u1, + /// G1_IO2 analog switch enable. + G1_IO2: u1, + /// G1_IO3 analog switch enable. + G1_IO3: u1, + /// G1_IO4 analog switch enable. + G1_IO4: u1, + /// G2_IO1 analog switch enable. + G2_IO1: u1, + /// G2_IO2 analog switch enable. + G2_IO2: u1, + /// G2_IO3 analog switch enable. + G2_IO3: u1, + /// G2_IO4 analog switch enable. + G2_IO4: u1, + /// G3_IO1 analog switch enable. + G3_IO1: u1, + /// G3_IO2 analog switch enable. + G3_IO2: u1, + /// G3_IO3 analog switch enable. + G3_IO3: u1, + /// G3_IO4 analog switch enable. + G3_IO4: u1, + /// G4_IO1 analog switch enable. + G4_IO1: u1, + /// G4_IO2 analog switch enable. + G4_IO2: u1, + /// G4_IO3 analog switch enable. + G4_IO3: u1, + /// G4_IO4 analog switch enable. + G4_IO4: u1, + /// G5_IO1 analog switch enable. + G5_IO1: u1, + /// G5_IO2 analog switch enable. + G5_IO2: u1, + /// G5_IO3 analog switch enable. + G5_IO3: u1, + /// G5_IO4 analog switch enable. + G5_IO4: u1, + /// G6_IO1 analog switch enable. + G6_IO1: u1, + /// G6_IO2 analog switch enable. + G6_IO2: u1, + /// G6_IO3 analog switch enable. + G6_IO3: u1, + /// G6_IO4 analog switch enable. + G6_IO4: u1, + padding: u8, + }), + reserved32: [4]u8, + /// I/O sampling control register. + IOSCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 sampling mode. + G1_IO1: u1, + /// G1_IO2 sampling mode. + G1_IO2: u1, + /// G1_IO3 sampling mode. + G1_IO3: u1, + /// G1_IO4 sampling mode. + G1_IO4: u1, + /// G2_IO1 sampling mode. + G2_IO1: u1, + /// G2_IO2 sampling mode. + G2_IO2: u1, + /// G2_IO3 sampling mode. + G2_IO3: u1, + /// G2_IO4 sampling mode. + G2_IO4: u1, + /// G3_IO1 sampling mode. + G3_IO1: u1, + /// G3_IO2 sampling mode. + G3_IO2: u1, + /// G3_IO3 sampling mode. + G3_IO3: u1, + /// G3_IO4 sampling mode. + G3_IO4: u1, + /// G4_IO1 sampling mode. + G4_IO1: u1, + /// G4_IO2 sampling mode. + G4_IO2: u1, + /// G4_IO3 sampling mode. + G4_IO3: u1, + /// G4_IO4 sampling mode. + G4_IO4: u1, + /// G5_IO1 sampling mode. + G5_IO1: u1, + /// G5_IO2 sampling mode. + G5_IO2: u1, + /// G5_IO3 sampling mode. + G5_IO3: u1, + /// G5_IO4 sampling mode. + G5_IO4: u1, + /// G6_IO1 sampling mode. + G6_IO1: u1, + /// G6_IO2 sampling mode. + G6_IO2: u1, + /// G6_IO3 sampling mode. + G6_IO3: u1, + /// G6_IO4 sampling mode. + G6_IO4: u1, + padding: u8, + }), + reserved40: [4]u8, + /// I/O channel control register. + IOCCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 channel mode. + G1_IO1: u1, + /// G1_IO2 channel mode. + G1_IO2: u1, + /// G1_IO3 channel mode. + G1_IO3: u1, + /// G1_IO4 channel mode. + G1_IO4: u1, + /// G2_IO1 channel mode. + G2_IO1: u1, + /// G2_IO2 channel mode. + G2_IO2: u1, + /// G2_IO3 channel mode. + G2_IO3: u1, + /// G2_IO4 channel mode. + G2_IO4: u1, + /// G3_IO1 channel mode. + G3_IO1: u1, + /// G3_IO2 channel mode. + G3_IO2: u1, + /// G3_IO3 channel mode. + G3_IO3: u1, + /// G3_IO4 channel mode. + G3_IO4: u1, + /// G4_IO1 channel mode. + G4_IO1: u1, + /// G4_IO2 channel mode. + G4_IO2: u1, + /// G4_IO3 channel mode. + G4_IO3: u1, + /// G4_IO4 channel mode. + G4_IO4: u1, + /// G5_IO1 channel mode. + G5_IO1: u1, + /// G5_IO2 channel mode. + G5_IO2: u1, + /// G5_IO3 channel mode. + G5_IO3: u1, + /// G5_IO4 channel mode. + G5_IO4: u1, + /// G6_IO1 channel mode. + G6_IO1: u1, + /// G6_IO2 channel mode. + G6_IO2: u1, + /// G6_IO3 channel mode. + G6_IO3: u1, + /// G6_IO4 channel mode. + G6_IO4: u1, + padding: u8, + }), + reserved48: [4]u8, + /// I/O group control status register. + IOGCSR: mmio.Mmio(packed struct(u32) { + /// Analog I/O group x enable. + G1E: u1, + /// Analog I/O group x enable. + G2E: u1, + /// Analog I/O group x enable. + G3E: u1, + /// Analog I/O group x enable. + G4E: u1, + /// Analog I/O group x enable. + G5E: u1, + /// Analog I/O group x enable. + G6E: u1, + /// Analog I/O group x enable. + G7E: u1, + /// Analog I/O group x enable. + G8E: u1, + reserved16: u8, + /// Analog I/O group x status. + G1S: u1, + /// Analog I/O group x status. + G2S: u1, + /// Analog I/O group x status. + G3S: u1, + /// Analog I/O group x status. + G4S: u1, + /// Analog I/O group x status. + G5S: u1, + /// Analog I/O group x status. + G6S: u1, + /// Analog I/O group x status. + G7S: u1, + /// Analog I/O group x status. + G8S: u1, + padding: u8, + }), + /// I/O group x counter register. + IOGCR: [6]mmio.Mmio(packed struct(u32) { + /// Counter value. + CNT: u14, + padding: u18, + }), + }; + }; + + pub const tsc_v2 = struct { + /// Touch sensing controller. + pub const TSC = extern struct { + /// control register. + CR: mmio.Mmio(packed struct(u32) { + /// Touch sensing controller enable. + TSCE: u1, + /// Start a new acquisition. + START: u1, + /// Acquisition mode. + AM: u1, + /// Synchronization pin polarity. + SYNCPOL: u1, + /// I/O Default mode. + IODEF: u1, + /// Max count value. + MCV: u3, + reserved12: u4, + /// pulse generator prescaler. + PGPSC: u3, + /// Spread spectrum prescaler. + SSPSC: u1, + /// Spread spectrum enable. + SSE: u1, + /// Spread spectrum deviation. + SSD: u7, + /// Charge transfer pulse low. + CTPL: u4, + /// Charge transfer pulse high. + CTPH: u4, + }), + /// interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// End of acquisition interrupt enable. + EOAIE: u1, + /// Max count error interrupt enable. + MCEIE: u1, + padding: u30, + }), + /// interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// End of acquisition interrupt clear. + EOAIC: u1, + /// Max count error interrupt clear. + MCEIC: u1, + padding: u30, + }), + /// interrupt status register. + ISR: mmio.Mmio(packed struct(u32) { + /// End of acquisition flag. + EOAF: u1, + /// Max count error flag. + MCEF: u1, + padding: u30, + }), + /// I/O hysteresis control register. + IOHCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 Schmitt trigger hysteresis mode. + G1_IO1: u1, + /// G1_IO2 Schmitt trigger hysteresis mode. + G1_IO2: u1, + /// G1_IO3 Schmitt trigger hysteresis mode. + G1_IO3: u1, + /// G1_IO4 Schmitt trigger hysteresis mode. + G1_IO4: u1, + /// G2_IO1 Schmitt trigger hysteresis mode. + G2_IO1: u1, + /// G2_IO2 Schmitt trigger hysteresis mode. + G2_IO2: u1, + /// G2_IO3 Schmitt trigger hysteresis mode. + G2_IO3: u1, + /// G2_IO4 Schmitt trigger hysteresis mode. + G2_IO4: u1, + /// G3_IO1 Schmitt trigger hysteresis mode. + G3_IO1: u1, + /// G3_IO2 Schmitt trigger hysteresis mode. + G3_IO2: u1, + /// G3_IO3 Schmitt trigger hysteresis mode. + G3_IO3: u1, + /// G3_IO4 Schmitt trigger hysteresis mode. + G3_IO4: u1, + /// G4_IO1 Schmitt trigger hysteresis mode. + G4_IO1: u1, + /// G4_IO2 Schmitt trigger hysteresis mode. + G4_IO2: u1, + /// G4_IO3 Schmitt trigger hysteresis mode. + G4_IO3: u1, + /// G4_IO4 Schmitt trigger hysteresis mode. + G4_IO4: u1, + /// G5_IO1 Schmitt trigger hysteresis mode. + G5_IO1: u1, + /// G5_IO2 Schmitt trigger hysteresis mode. + G5_IO2: u1, + /// G5_IO3 Schmitt trigger hysteresis mode. + G5_IO3: u1, + /// G5_IO4 Schmitt trigger hysteresis mode. + G5_IO4: u1, + /// G6_IO1 Schmitt trigger hysteresis mode. + G6_IO1: u1, + /// G6_IO2 Schmitt trigger hysteresis mode. + G6_IO2: u1, + /// G6_IO3 Schmitt trigger hysteresis mode. + G6_IO3: u1, + /// G6_IO4 Schmitt trigger hysteresis mode. + G6_IO4: u1, + /// G7_IO1 Schmitt trigger hysteresis mode. + G7_IO1: u1, + /// G7_IO2 Schmitt trigger hysteresis mode. + G7_IO2: u1, + /// G7_IO3 Schmitt trigger hysteresis mode. + G7_IO3: u1, + /// G7_IO4 Schmitt trigger hysteresis mode. + G7_IO4: u1, + padding: u4, + }), + reserved24: [4]u8, + /// I/O analog switch control register. + IOASCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 analog switch enable. + G1_IO1: u1, + /// G1_IO2 analog switch enable. + G1_IO2: u1, + /// G1_IO3 analog switch enable. + G1_IO3: u1, + /// G1_IO4 analog switch enable. + G1_IO4: u1, + /// G2_IO1 analog switch enable. + G2_IO1: u1, + /// G2_IO2 analog switch enable. + G2_IO2: u1, + /// G2_IO3 analog switch enable. + G2_IO3: u1, + /// G2_IO4 analog switch enable. + G2_IO4: u1, + /// G3_IO1 analog switch enable. + G3_IO1: u1, + /// G3_IO2 analog switch enable. + G3_IO2: u1, + /// G3_IO3 analog switch enable. + G3_IO3: u1, + /// G3_IO4 analog switch enable. + G3_IO4: u1, + /// G4_IO1 analog switch enable. + G4_IO1: u1, + /// G4_IO2 analog switch enable. + G4_IO2: u1, + /// G4_IO3 analog switch enable. + G4_IO3: u1, + /// G4_IO4 analog switch enable. + G4_IO4: u1, + /// G5_IO1 analog switch enable. + G5_IO1: u1, + /// G5_IO2 analog switch enable. + G5_IO2: u1, + /// G5_IO3 analog switch enable. + G5_IO3: u1, + /// G5_IO4 analog switch enable. + G5_IO4: u1, + /// G6_IO1 analog switch enable. + G6_IO1: u1, + /// G6_IO2 analog switch enable. + G6_IO2: u1, + /// G6_IO3 analog switch enable. + G6_IO3: u1, + /// G6_IO4 analog switch enable. + G6_IO4: u1, + /// G7_IO1 analog switch enable. + G7_IO1: u1, + /// G7_IO2 analog switch enable. + G7_IO2: u1, + /// G7_IO3 analog switch enable. + G7_IO3: u1, + /// G7_IO4 analog switch enable. + G7_IO4: u1, + padding: u4, + }), + reserved32: [4]u8, + /// I/O sampling control register. + IOSCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 sampling mode. + G1_IO1: u1, + /// G1_IO2 sampling mode. + G1_IO2: u1, + /// G1_IO3 sampling mode. + G1_IO3: u1, + /// G1_IO4 sampling mode. + G1_IO4: u1, + /// G2_IO1 sampling mode. + G2_IO1: u1, + /// G2_IO2 sampling mode. + G2_IO2: u1, + /// G2_IO3 sampling mode. + G2_IO3: u1, + /// G2_IO4 sampling mode. + G2_IO4: u1, + /// G3_IO1 sampling mode. + G3_IO1: u1, + /// G3_IO2 sampling mode. + G3_IO2: u1, + /// G3_IO3 sampling mode. + G3_IO3: u1, + /// G3_IO4 sampling mode. + G3_IO4: u1, + /// G4_IO1 sampling mode. + G4_IO1: u1, + /// G4_IO2 sampling mode. + G4_IO2: u1, + /// G4_IO3 sampling mode. + G4_IO3: u1, + /// G4_IO4 sampling mode. + G4_IO4: u1, + /// G5_IO1 sampling mode. + G5_IO1: u1, + /// G5_IO2 sampling mode. + G5_IO2: u1, + /// G5_IO3 sampling mode. + G5_IO3: u1, + /// G5_IO4 sampling mode. + G5_IO4: u1, + /// G6_IO1 sampling mode. + G6_IO1: u1, + /// G6_IO2 sampling mode. + G6_IO2: u1, + /// G6_IO3 sampling mode. + G6_IO3: u1, + /// G6_IO4 sampling mode. + G6_IO4: u1, + /// G7_IO1 sampling mode. + G7_IO1: u1, + /// G7_IO2 sampling mode. + G7_IO2: u1, + /// G7_IO3 sampling mode. + G7_IO3: u1, + /// G7_IO4 sampling mode. + G7_IO4: u1, + padding: u4, + }), + reserved40: [4]u8, + /// I/O channel control register. + IOCCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 channel mode. + G1_IO1: u1, + /// G1_IO2 channel mode. + G1_IO2: u1, + /// G1_IO3 channel mode. + G1_IO3: u1, + /// G1_IO4 channel mode. + G1_IO4: u1, + /// G2_IO1 channel mode. + G2_IO1: u1, + /// G2_IO2 channel mode. + G2_IO2: u1, + /// G2_IO3 channel mode. + G2_IO3: u1, + /// G2_IO4 channel mode. + G2_IO4: u1, + /// G3_IO1 channel mode. + G3_IO1: u1, + /// G3_IO2 channel mode. + G3_IO2: u1, + /// G3_IO3 channel mode. + G3_IO3: u1, + /// G3_IO4 channel mode. + G3_IO4: u1, + /// G4_IO1 channel mode. + G4_IO1: u1, + /// G4_IO2 channel mode. + G4_IO2: u1, + /// G4_IO3 channel mode. + G4_IO3: u1, + /// G4_IO4 channel mode. + G4_IO4: u1, + /// G5_IO1 channel mode. + G5_IO1: u1, + /// G5_IO2 channel mode. + G5_IO2: u1, + /// G5_IO3 channel mode. + G5_IO3: u1, + /// G5_IO4 channel mode. + G5_IO4: u1, + /// G6_IO1 channel mode. + G6_IO1: u1, + /// G6_IO2 channel mode. + G6_IO2: u1, + /// G6_IO3 channel mode. + G6_IO3: u1, + /// G6_IO4 channel mode. + G6_IO4: u1, + /// G7_IO1 channel mode. + G7_IO1: u1, + /// G7_IO2 channel mode. + G7_IO2: u1, + /// G7_IO3 channel mode. + G7_IO3: u1, + /// G7_IO4 channel mode. + G7_IO4: u1, + padding: u4, + }), + reserved48: [4]u8, + /// I/O group control status register. + IOGCSR: mmio.Mmio(packed struct(u32) { + /// Analog I/O group x enable. + G1E: u1, + /// Analog I/O group x enable. + G2E: u1, + /// Analog I/O group x enable. + G3E: u1, + /// Analog I/O group x enable. + G4E: u1, + /// Analog I/O group x enable. + G5E: u1, + /// Analog I/O group x enable. + G6E: u1, + /// Analog I/O group x enable. + G7E: u1, + reserved16: u9, + /// Analog I/O group x status. + G1S: u1, + /// Analog I/O group x status. + G2S: u1, + /// Analog I/O group x status. + G3S: u1, + /// Analog I/O group x status. + G4S: u1, + /// Analog I/O group x status. + G5S: u1, + /// Analog I/O group x status. + G6S: u1, + /// Analog I/O group x status. + G7S: u1, + padding: u9, + }), + /// I/O group x counter register. + IOGCR: [7]mmio.Mmio(packed struct(u32) { + /// Counter value. + CNT: u14, + padding: u18, + }), + }; + }; + + pub const tsc_v3 = struct { + /// Touch sensing controller. + pub const TSC = extern struct { + /// control register. + CR: mmio.Mmio(packed struct(u32) { + /// Touch sensing controller enable. + TSCE: u1, + /// Start a new acquisition. + START: u1, + /// Acquisition mode. + AM: u1, + /// Synchronization pin polarity. + SYNCPOL: u1, + /// I/O Default mode. + IODEF: u1, + /// Max count value. + MCV: u3, + reserved12: u4, + /// pulse generator prescaler. + PGPSC: u3, + /// Spread spectrum prescaler. + SSPSC: u1, + /// Spread spectrum enable. + SSE: u1, + /// Spread spectrum deviation. + SSD: u7, + /// Charge transfer pulse low. + CTPL: u4, + /// Charge transfer pulse high. + CTPH: u4, + }), + /// interrupt enable register. + IER: mmio.Mmio(packed struct(u32) { + /// End of acquisition interrupt enable. + EOAIE: u1, + /// Max count error interrupt enable. + MCEIE: u1, + padding: u30, + }), + /// interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// End of acquisition interrupt clear. + EOAIC: u1, + /// Max count error interrupt clear. + MCEIC: u1, + padding: u30, + }), + /// interrupt status register. + ISR: mmio.Mmio(packed struct(u32) { + /// End of acquisition flag. + EOAF: u1, + /// Max count error flag. + MCEF: u1, + padding: u30, + }), + /// I/O hysteresis control register. + IOHCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 Schmitt trigger hysteresis mode. + G1_IO1: u1, + /// G1_IO2 Schmitt trigger hysteresis mode. + G1_IO2: u1, + /// G1_IO3 Schmitt trigger hysteresis mode. + G1_IO3: u1, + /// G1_IO4 Schmitt trigger hysteresis mode. + G1_IO4: u1, + /// G2_IO1 Schmitt trigger hysteresis mode. + G2_IO1: u1, + /// G2_IO2 Schmitt trigger hysteresis mode. + G2_IO2: u1, + /// G2_IO3 Schmitt trigger hysteresis mode. + G2_IO3: u1, + /// G2_IO4 Schmitt trigger hysteresis mode. + G2_IO4: u1, + /// G3_IO1 Schmitt trigger hysteresis mode. + G3_IO1: u1, + /// G3_IO2 Schmitt trigger hysteresis mode. + G3_IO2: u1, + /// G3_IO3 Schmitt trigger hysteresis mode. + G3_IO3: u1, + /// G3_IO4 Schmitt trigger hysteresis mode. + G3_IO4: u1, + /// G4_IO1 Schmitt trigger hysteresis mode. + G4_IO1: u1, + /// G4_IO2 Schmitt trigger hysteresis mode. + G4_IO2: u1, + /// G4_IO3 Schmitt trigger hysteresis mode. + G4_IO3: u1, + /// G4_IO4 Schmitt trigger hysteresis mode. + G4_IO4: u1, + /// G5_IO1 Schmitt trigger hysteresis mode. + G5_IO1: u1, + /// G5_IO2 Schmitt trigger hysteresis mode. + G5_IO2: u1, + /// G5_IO3 Schmitt trigger hysteresis mode. + G5_IO3: u1, + /// G5_IO4 Schmitt trigger hysteresis mode. + G5_IO4: u1, + /// G6_IO1 Schmitt trigger hysteresis mode. + G6_IO1: u1, + /// G6_IO2 Schmitt trigger hysteresis mode. + G6_IO2: u1, + /// G6_IO3 Schmitt trigger hysteresis mode. + G6_IO3: u1, + /// G6_IO4 Schmitt trigger hysteresis mode. + G6_IO4: u1, + /// G7_IO1 Schmitt trigger hysteresis mode. + G7_IO1: u1, + /// G7_IO2 Schmitt trigger hysteresis mode. + G7_IO2: u1, + /// G7_IO3 Schmitt trigger hysteresis mode. + G7_IO3: u1, + /// G7_IO4 Schmitt trigger hysteresis mode. + G7_IO4: u1, + /// G8_IO1 Schmitt trigger hysteresis mode. + G8_IO1: u1, + /// G8_IO2 Schmitt trigger hysteresis mode. + G8_IO2: u1, + /// G8_IO3 Schmitt trigger hysteresis mode. + G8_IO3: u1, + /// G8_IO4 Schmitt trigger hysteresis mode. + G8_IO4: u1, + }), + reserved24: [4]u8, + /// I/O analog switch control register. + IOASCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 analog switch enable. + G1_IO1: u1, + /// G1_IO2 analog switch enable. + G1_IO2: u1, + /// G1_IO3 analog switch enable. + G1_IO3: u1, + /// G1_IO4 analog switch enable. + G1_IO4: u1, + /// G2_IO1 analog switch enable. + G2_IO1: u1, + /// G2_IO2 analog switch enable. + G2_IO2: u1, + /// G2_IO3 analog switch enable. + G2_IO3: u1, + /// G2_IO4 analog switch enable. + G2_IO4: u1, + /// G3_IO1 analog switch enable. + G3_IO1: u1, + /// G3_IO2 analog switch enable. + G3_IO2: u1, + /// G3_IO3 analog switch enable. + G3_IO3: u1, + /// G3_IO4 analog switch enable. + G3_IO4: u1, + /// G4_IO1 analog switch enable. + G4_IO1: u1, + /// G4_IO2 analog switch enable. + G4_IO2: u1, + /// G4_IO3 analog switch enable. + G4_IO3: u1, + /// G4_IO4 analog switch enable. + G4_IO4: u1, + /// G5_IO1 analog switch enable. + G5_IO1: u1, + /// G5_IO2 analog switch enable. + G5_IO2: u1, + /// G5_IO3 analog switch enable. + G5_IO3: u1, + /// G5_IO4 analog switch enable. + G5_IO4: u1, + /// G6_IO1 analog switch enable. + G6_IO1: u1, + /// G6_IO2 analog switch enable. + G6_IO2: u1, + /// G6_IO3 analog switch enable. + G6_IO3: u1, + /// G6_IO4 analog switch enable. + G6_IO4: u1, + /// G7_IO1 analog switch enable. + G7_IO1: u1, + /// G7_IO2 analog switch enable. + G7_IO2: u1, + /// G7_IO3 analog switch enable. + G7_IO3: u1, + /// G7_IO4 analog switch enable. + G7_IO4: u1, + /// G8_IO1 analog switch enable. + G8_IO1: u1, + /// G8_IO2 analog switch enable. + G8_IO2: u1, + /// G8_IO3 analog switch enable. + G8_IO3: u1, + /// G8_IO4 analog switch enable. + G8_IO4: u1, + }), + reserved32: [4]u8, + /// I/O sampling control register. + IOSCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 sampling mode. + G1_IO1: u1, + /// G1_IO2 sampling mode. + G1_IO2: u1, + /// G1_IO3 sampling mode. + G1_IO3: u1, + /// G1_IO4 sampling mode. + G1_IO4: u1, + /// G2_IO1 sampling mode. + G2_IO1: u1, + /// G2_IO2 sampling mode. + G2_IO2: u1, + /// G2_IO3 sampling mode. + G2_IO3: u1, + /// G2_IO4 sampling mode. + G2_IO4: u1, + /// G3_IO1 sampling mode. + G3_IO1: u1, + /// G3_IO2 sampling mode. + G3_IO2: u1, + /// G3_IO3 sampling mode. + G3_IO3: u1, + /// G3_IO4 sampling mode. + G3_IO4: u1, + /// G4_IO1 sampling mode. + G4_IO1: u1, + /// G4_IO2 sampling mode. + G4_IO2: u1, + /// G4_IO3 sampling mode. + G4_IO3: u1, + /// G4_IO4 sampling mode. + G4_IO4: u1, + /// G5_IO1 sampling mode. + G5_IO1: u1, + /// G5_IO2 sampling mode. + G5_IO2: u1, + /// G5_IO3 sampling mode. + G5_IO3: u1, + /// G5_IO4 sampling mode. + G5_IO4: u1, + /// G6_IO1 sampling mode. + G6_IO1: u1, + /// G6_IO2 sampling mode. + G6_IO2: u1, + /// G6_IO3 sampling mode. + G6_IO3: u1, + /// G6_IO4 sampling mode. + G6_IO4: u1, + /// G7_IO1 sampling mode. + G7_IO1: u1, + /// G7_IO2 sampling mode. + G7_IO2: u1, + /// G7_IO3 sampling mode. + G7_IO3: u1, + /// G7_IO4 sampling mode. + G7_IO4: u1, + /// G8_IO1 sampling mode. + G8_IO1: u1, + /// G8_IO2 sampling mode. + G8_IO2: u1, + /// G8_IO3 sampling mode. + G8_IO3: u1, + /// G8_IO4 sampling mode. + G8_IO4: u1, + }), + reserved40: [4]u8, + /// I/O channel control register. + IOCCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 channel mode. + G1_IO1: u1, + /// G1_IO2 channel mode. + G1_IO2: u1, + /// G1_IO3 channel mode. + G1_IO3: u1, + /// G1_IO4 channel mode. + G1_IO4: u1, + /// G2_IO1 channel mode. + G2_IO1: u1, + /// G2_IO2 channel mode. + G2_IO2: u1, + /// G2_IO3 channel mode. + G2_IO3: u1, + /// G2_IO4 channel mode. + G2_IO4: u1, + /// G3_IO1 channel mode. + G3_IO1: u1, + /// G3_IO2 channel mode. + G3_IO2: u1, + /// G3_IO3 channel mode. + G3_IO3: u1, + /// G3_IO4 channel mode. + G3_IO4: u1, + /// G4_IO1 channel mode. + G4_IO1: u1, + /// G4_IO2 channel mode. + G4_IO2: u1, + /// G4_IO3 channel mode. + G4_IO3: u1, + /// G4_IO4 channel mode. + G4_IO4: u1, + /// G5_IO1 channel mode. + G5_IO1: u1, + /// G5_IO2 channel mode. + G5_IO2: u1, + /// G5_IO3 channel mode. + G5_IO3: u1, + /// G5_IO4 channel mode. + G5_IO4: u1, + /// G6_IO1 channel mode. + G6_IO1: u1, + /// G6_IO2 channel mode. + G6_IO2: u1, + /// G6_IO3 channel mode. + G6_IO3: u1, + /// G6_IO4 channel mode. + G6_IO4: u1, + /// G7_IO1 channel mode. + G7_IO1: u1, + /// G7_IO2 channel mode. + G7_IO2: u1, + /// G7_IO3 channel mode. + G7_IO3: u1, + /// G7_IO4 channel mode. + G7_IO4: u1, + /// G8_IO1 channel mode. + G8_IO1: u1, + /// G8_IO2 channel mode. + G8_IO2: u1, + /// G8_IO3 channel mode. + G8_IO3: u1, + /// G8_IO4 channel mode. + G8_IO4: u1, }), - /// alternate function register 2 - AF2: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// ocref_clr source selection - OCRSEL: u3, - padding: u13, + reserved48: [4]u8, + /// I/O group control status register. + IOGCSR: mmio.Mmio(packed struct(u32) { + /// Analog I/O group x enable. + G1E: u1, + /// Analog I/O group x enable. + G2E: u1, + /// Analog I/O group x enable. + G3E: u1, + /// Analog I/O group x enable. + G4E: u1, + /// Analog I/O group x enable. + G5E: u1, + /// Analog I/O group x enable. + G6E: u1, + /// Analog I/O group x enable. + G7E: u1, + /// Analog I/O group x enable. + G8E: u1, + reserved16: u8, + /// Analog I/O group x status. + G1S: u1, + /// Analog I/O group x status. + G2S: u1, + /// Analog I/O group x status. + G3S: u1, + /// Analog I/O group x status. + G4S: u1, + /// Analog I/O group x status. + G5S: u1, + /// Analog I/O group x status. + G6S: u1, + /// Analog I/O group x status. + G7S: u1, + /// Analog I/O group x status. + G8S: u1, + padding: u8, }), - reserved988: [884]u8, - /// DMA control register - DCR: mmio.Mmio(packed struct(u32) { - /// DMA base address - DBA: u5, - reserved8: u3, - /// DMA burst length - DBL: u5, - reserved16: u3, - /// DMA burst source selection - DBSS: packed union { - raw: u4, - value: DBSS, - }, - padding: u12, + /// I/O group x counter register. + IOGCR: [8]mmio.Mmio(packed struct(u32) { + /// Counter value. + CNT: u14, + padding: u18, }), - /// DMA address for full transfer - DMAR: u32, - }; - - /// General purpose 32-bit timers - pub const TIM_GP32 = extern struct { - reserved36: [36]u8, - /// counter (Dither mode disabled) - CNT: u32, - reserved44: [4]u8, - /// auto-reload register (Dither mode disabled) - ARR: u32, - reserved52: [4]u8, - /// capture/compare register x (x=1-4) (Dither mode disabled) - CCR: [4]u32, }; }; - pub const fsmc_v1x0 = struct { - pub const ACCMOD = enum(u2) { - /// Access mode A - A = 0x0, - /// Access mode B - B = 0x1, - /// Access mode C - C = 0x2, - /// Access mode D - D = 0x3, - }; - - pub const CPSIZE = enum(u3) { - /// No burst split when crossing page boundary - NoBurstSplit = 0x0, - /// 128 bytes CRAM page size - Bytes128 = 0x1, - /// 256 bytes CRAM page size - Bytes256 = 0x2, - /// 512 bytes CRAM page size - Bytes512 = 0x3, - /// 1024 bytes CRAM page size - Bytes1024 = 0x4, - _, - }; - - pub const MTYP = enum(u2) { - /// SRAM memory type - SRAM = 0x0, - /// PSRAM (CRAM) memory type - PSRAM = 0x1, - /// NOR Flash/OneNAND Flash - Flash = 0x2, - _, - }; - - pub const MWID = enum(u2) { - /// Memory data bus width 8 bits - Bits8 = 0x0, - /// Memory data bus width 16 bits - Bits16 = 0x1, - /// Memory data bus width 32 bits - Bits32 = 0x2, - _, - }; - - pub const WAITCFG = enum(u1) { - /// NWAIT signal is active one data cycle before wait state - BeforeWaitState = 0x0, - /// NWAIT signal is active during wait state - DuringWaitState = 0x1, - }; - - pub const WAITPOL = enum(u1) { - /// NWAIT active low - ActiveLow = 0x0, - /// NWAIT active high - ActiveHigh = 0x1, + pub const ucpd_v1 = struct { + pub const ANAMODE = enum(u1) { + /// Source + Source = 0x0, + /// Sink + Sink = 0x1, }; - /// Flexible static memory controller - pub const FSMC = extern struct { - /// SRAM/NOR-Flash chip-select control register 1-4 - BCR: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { - raw: u2, - value: MTYP, - }, - /// Memory data bus width - MWID: packed union { - raw: u2, - value: MWID, - }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { - raw: u1, - value: WAITPOL, - }, - /// WRAPMOD - WRAPMOD: u1, - /// Wait timing configuration - WAITCFG: packed union { - raw: u1, - value: WAITCFG, - }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - /// CRAM page size - CPSIZE: packed union { - raw: u3, - value: CPSIZE, - }, - /// Write burst enable - CBURSTRW: u1, - padding: u12, - }), - /// SRAM/NOR-Flash chip-select timing register 1-4 - BTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - /// Clock divide ratio (for FMC_CLK signal) - CLKDIV: u4, - /// Data latency for synchronous memory - DATLAT: u4, - /// Access mode - ACCMOD: packed union { - raw: u2, - value: ACCMOD, - }, - padding: u2, - }), - reserved260: [252]u8, - /// SRAM/NOR-Flash write timing registers 1-4 - BWTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - reserved28: u8, - /// Access mode - ACCMOD: packed union { - raw: u2, - value: ACCMOD, - }, - padding: u2, - }), + pub const CCENABLE = enum(u2) { + /// Disable both PHYs + Disabled = 0x0, + /// Enable CC1 PHY + Cc1 = 0x1, + /// Enable CC2 PHY + Cc2 = 0x2, + /// Enable CC1 and CC2 PHY + Both = 0x3, }; - }; - pub const rng_v2 = struct { - pub const CLKDIV = enum(u4) { - /// Internal RNG clock after divider is similar to incoming RNG clock - NoDiv = 0x0, - /// Divide RNG clock by 2^1 - Div_2_1 = 0x1, - /// Divide RNG clock by 2^2 - Div_2_2 = 0x2, - /// Divide RNG clock by 2^3 - Div_2_3 = 0x3, - /// Divide RNG clock by 2^4 - Div_2_4 = 0x4, - /// Divide RNG clock by 2^5 - Div_2_5 = 0x5, - /// Divide RNG clock by 2^6 - Div_2_6 = 0x6, - /// Divide RNG clock by 2^7 - Div_2_7 = 0x7, - /// Divide RNG clock by 2^8 - Div_2_8 = 0x8, - /// Divide RNG clock by 2^9 - Div_2_9 = 0x9, - /// Divide RNG clock by 2^10 - Div_2_10 = 0xa, - /// Divide RNG clock by 2^11 - Div_2_11 = 0xb, - /// Divide RNG clock by 2^12 - Div_2_12 = 0xc, - /// Divide RNG clock by 2^13 - Div_2_13 = 0xd, - /// Divide RNG clock by 2^14 - Div_2_14 = 0xe, - /// Divide RNG clock by 2^15 - Div_2_15 = 0xf, + pub const PHYCCSEL = enum(u1) { + /// Use CC1 IO for Power Delivery communication + Cc1 = 0x0, + /// Use CC2 IO for Power Delivery communication + Cc2 = 0x1, }; - pub const HTCFG = enum(u32) { - /// Recommended value for RNG certification (0x0000_AA74) - Recommended = 0xaa74, - /// Magic number to be written before any write (0x1759_0ABC) - Magic = 0x17590abc, + pub const PSC_USBPDCLK = enum(u3) { + /// 1 (bypass) + Div1 = 0x0, + /// 2 + Div2 = 0x1, + /// 4 + Div4 = 0x2, + /// 8 + Div8 = 0x3, + /// 16 + Div16 = 0x4, _, }; - pub const NISTC = enum(u1) { - /// Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used - Default = 0x0, - /// Custom values for NIST compliant RNG - Custom = 0x1, + pub const RXORDSET = enum(u3) { + /// SOP code detected in receiver + Sop = 0x0, + /// SOP' code detected in receiver + SopPrime = 0x1, + /// SOP'' code detected in receiver + SopDoublePrime = 0x2, + /// SOP'_Debug detected in receiver + SopPrimeDebug = 0x3, + /// SOP''_Debug detected in receiver + SopDoublePrimeDebug = 0x4, + /// Cable Reset detected in receiver + CableReset = 0x5, + /// SOP extension#1 detected in receiver + Ext1 = 0x6, + /// SOP extension#2 detected in receiver + Ext2 = 0x7, }; - pub const RNG_CONFIG1 = enum(u6) { - /// Recommended value for config A (NIST certifiable) - ConfigA = 0xf, - /// Recommended value for config B (not NIST certifiable) - ConfigB = 0x18, + pub const RXSOPKINVALID = enum(u3) { + /// No K‑code corrupted + None = 0x0, + /// First K‑code corrupted + First = 0x1, + /// Second K‑code corrupted + Second = 0x2, + /// Third K‑code corrupted + Third = 0x3, + /// Fourth K‑code corrupted + Fourth = 0x4, _, }; - pub const RNG_CONFIG2 = enum(u3) { - /// Recommended value for config A and B - ConfigA_B = 0x0, + pub const TXMODE = enum(u2) { + /// Transmission of Tx packet previously defined in other registers + Packet = 0x0, + /// Cable Reset sequence + CableReset = 0x1, + /// BIST test sequence (BIST Carrier Mode 2) + Bist = 0x2, _, }; - pub const RNG_CONFIG3 = enum(u4) { - /// Recommended value for config B (not NIST certifiable) - ConfigB = 0x0, - /// Recommended value for config A (NIST certifiable) - ConfigA = 0xd, - _, + pub const TYPEC_VSTATE_CC = enum(u2) { + /// Lowest + Lowest = 0x0, + /// Low + Low = 0x1, + /// High + High = 0x2, + /// Highest + Highest = 0x3, }; - /// Random number generator - pub const RNG = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Random number generator enable - RNGEN: u1, - /// Interrupt enable - IE: u1, - reserved5: u1, - /// Clock error detection - CED: u1, - reserved8: u2, - /// RNG configuration 3 - RNG_CONFIG3: packed union { - raw: u4, - value: RNG_CONFIG3, - }, - /// Non NIST compliant - NISTC: packed union { - raw: u1, - value: NISTC, - }, - /// RNG configuration 2 - RNG_CONFIG2: packed union { + /// USB Power Delivery interface + pub const UCPD = extern struct { + /// configuration register 1 + CFGR1: mmio.Mmio(packed struct(u32) { + /// Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfield value plus one) of a clk divider producing half-bit clock (hbit_clk). + HBITCLKDIV: u6, + /// Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal. + IFRGAP: u5, + /// Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the clk frequency and the HBITCLKDIV[5:0] bitfield setting. + TRANSWIN: u5, + reserved17: u1, + /// Pre-scaler division ratio for generating clk The bitfield determines the division ratio of a kernel clock pre-scaler producing peripheral clock (clk). It is recommended to use the pre-scaler so as to set the clk frequency in the range from 6 to 9 MHz. + PSC_USBPDCLK: packed union { raw: u3, - value: RNG_CONFIG2, - }, - /// Clock divider factor - CLKDIV: packed union { - raw: u4, - value: CLKDIV, - }, - /// RNG configuration 1 - RNG_CONFIG1: packed union { - raw: u6, - value: RNG_CONFIG1, + value: PSC_USBPDCLK, }, - reserved30: u4, - /// Conditioning soft reset - CONDRST: u1, - /// Config Lock - CONFIGLOCK: u1, + /// Receiver ordered set enable The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function: 0bxxxxxxxx1: SOP detect enabled 0bxxxxxxx1x: SOP' detect enabled 0bxxxxxx1xx: SOP'' detect enabled 0bxxxxx1xxx: Hard Reset detect enabled 0bxxxx1xxxx: Cable Detect reset enabled 0bxxx1xxxxx: SOP'_Debug enabled 0bxx1xxxxxx: SOP''_Debug enabled 0bx1xxxxxxx: SOP extension#1 enabled 0b1xxxxxxxx: SOP extension#2 enabled + RXORDSETEN: u9, + /// Transmission DMA mode enable When set, the bit enables DMA mode for transmission. + TXDMAEN: u1, + /// Reception DMA mode enable When set, the bit enables DMA mode for reception. + RXDMAEN: u1, + /// peripheral enable General enable of the peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state. + UCPDEN: u1, }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Data ready - DRDY: u1, - /// Clock error current status - CECS: u1, - /// Seed error current status - SECS: u1, - reserved5: u2, - /// Clock error interrupt status - CEIS: u1, - /// Seed error interrupt status - SEIS: u1, - padding: u25, + /// configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler). + RXFILTDIS: u1, + /// BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value. + RXFILT2N3: u1, + /// Force ClkReq clock request + FORCECLK: u1, + /// Wakeup from Stop mode enable Setting the bit enables the ASYNC_INT signal. + WUPEN: u1, + padding: u28, }), - /// data register - DR: u32, - reserved16: [4]u8, - /// health test control register - HTCR: mmio.Mmio(packed struct(u32) { - /// Health test configuration - HTCFG: packed union { - raw: u32, - value: HTCFG, - }, + /// configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// SW trim value for Rd resistor on the CC1 line + TRIM_CC1_RD: u4, + reserved9: u5, + /// SW trim value for Rp current sources on the CC1 line + TRIM_CC1_RP: u4, + reserved16: u3, + /// SW trim value for Rd resistor on the CC2 line + TRIM_CC2_RD: u4, + reserved25: u5, + /// SW trim value for Rp current sources on the CC2 line + TRIM_CC2_RP: u4, + padding: u3, }), - }; - }; - - pub const aes_v2 = struct { - pub const DATATYPE = enum(u2) { - /// Word - None = 0x0, - /// Half-word (16-bit) - HalfWord = 0x1, - /// Byte (8-bit) - Byte = 0x2, - /// Bit - Bit = 0x3, - }; - - pub const GCMPH = enum(u2) { - /// Init phase - @"Init phase" = 0x0, - /// Header phase - @"Header phase" = 0x1, - /// Payload phase - @"Payload phase" = 0x2, - /// Final phase - @"Final phase" = 0x3, - }; - - pub const MODE = enum(u2) { - /// Encryption - Mode1 = 0x0, - /// Key derivation (or key preparation for ECB/CBC decryption) - Mode2 = 0x1, - /// Decryption - Mode3 = 0x2, - /// Key derivation then single decryption - Mode4 = 0x3, - }; - - /// Advanced encryption standard hardware accelerator - pub const AES = extern struct { - /// Control register + /// control register CR: mmio.Mmio(packed struct(u32) { - /// AES enable - EN: u1, - /// Data type selection - DATATYPE: packed union { + /// Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the "tBISTContMode" delay), disable the peripheral (UCPDEN = 0). + TXMODE: packed union { raw: u2, - value: DATATYPE, + value: TXMODE, }, - /// Operating mode - MODE: packed union { - raw: u2, - value: MODE, + /// Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded. + TXSEND: u1, + /// Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded. + TXHRST: u1, + /// Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message. + RXMODE: u1, + /// USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set. + PHYRXEN: u1, + /// CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach. + PHYCCSEL: packed union { + raw: u1, + value: PHYCCSEL, }, - /// Chaining mode bit1 bit0 - CHMOD10: u2, - /// Computation Complete Flag Clear - CCFC: u1, - /// Error clear - ERRC: u1, - /// CCF flag interrupt enable - CCFIE: u1, - /// Error interrupt enable - ERRIE: u1, - /// Enable DMA management of data input phase - DMAINEN: u1, - /// Enable DMA management of data output phase - DMAOUTEN: u1, - /// GCM or CCM phase selection - GCMPH: packed union { + /// Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield. + ANASUBMODE: u2, + /// Analog PHY operating mode The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0]. + ANAMODE: packed union { + raw: u1, + value: ANAMODE, + }, + /// CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source. + CCENABLE: packed union { raw: u2, - value: GCMPH, + value: CCENABLE, }, - reserved16: u1, - /// Chaining mode bit2 - CHMOD2: u1, - reserved18: u1, - /// Key size selection - KEYSIZE: u1, + reserved13: u1, + /// VCONN switch enable for CC1 + CC1VCONNEN: u1, + /// VCONN switch enable for CC2 + CC2VCONNEN: u1, + /// Dead battery function enable The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register. Dead battery function only operates if the external circuit is appropriately configured. + DBATTEN: u1, + /// FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink. + FRSRXEN: u1, + /// FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0. + FRSTX: u1, + /// Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to "USB Type-C ECN for Source VCONN Discharge". The CCENABLE[1:0] bitfield must be set accordingly, too. + RDCH: u1, reserved20: u1, - /// Number of padding bytes in last block of payload - NPBLB: u4, - padding: u8, - }), - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Computation complete flag - CCF: u1, - /// Read error flag - RDERR: u1, - /// Write error flag - WRERR: u1, - /// Busy flag - BUSY: u1, - padding: u28, - }), - /// Data input register - DINR: mmio.Mmio(packed struct(u32) { - /// Input data word - DIN: u32, - }), - /// Data output register - DOUTR: mmio.Mmio(packed struct(u32) { - /// Output data word - DOUT: u32, - }), - /// Key register - KEYR: mmio.Mmio(packed struct(u32) { - /// Cryptographic key - KEY: u32, - }), - reserved32: [12]u8, - /// Initialization vector register - IVR: [4]mmio.Mmio(packed struct(u32) { - /// Initialization vector input - IVI: u32, + /// CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE[1:0]. + CC1TCDIS: u1, + /// CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE[1:0]. + CC2TCDIS: u1, + padding: u10, }), - reserved64: [16]u8, - /// Suspend register - SUSPR: [8]mmio.Mmio(packed struct(u32) { - /// AES suspend - SUSP: u32, + /// interrupt mask register + IMR: mmio.Mmio(packed struct(u32) { + /// TXIS interrupt enable + TXISIE: u1, + /// TXMSGDISC interrupt enable + TXMSGDISCIE: u1, + /// TXMSGSENT interrupt enable + TXMSGSENTIE: u1, + /// TXMSGABT interrupt enable + TXMSGABTIE: u1, + /// HRSTDISC interrupt enable + HRSTDISCIE: u1, + /// HRSTSENT interrupt enable + HRSTSENTIE: u1, + /// TXUND interrupt enable + TXUNDIE: u1, + reserved8: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// RXORDDET interrupt enable + RXORDDETIE: u1, + /// RXHRSTDET interrupt enable + RXHRSTDETIE: u1, + /// RXOVR interrupt enable + RXOVRIE: u1, + /// RXMSGEND interrupt enable + RXMSGENDIE: u1, + reserved14: u1, + /// TYPECEVT1 interrupt enable + TYPECEVT1IE: u1, + /// TYPECEVT2 interrupt enable + TYPECEVT2IE: u1, + reserved20: u4, + /// FRSEVT interrupt enable + FRSEVTIE: u1, + padding: u11, }), - }; - }; - - pub const vrefbuf_v1 = struct { - pub const HIZ = enum(u1) { - /// VREF+ pin is internally connected to the voltage reference buffer output. - Connected = 0x0, - /// VREF+ pin is high impedance. - HighZ = 0x1, - }; - - pub const VRS = enum(u1) { - /// Voltage reference set to VREF_OUT1 (around 2.048 V). - Vref0 = 0x0, - /// Voltage reference set to VREF_OUT2 (around 2.5 V). - Vref1 = 0x1, - }; - - /// Voltage reference buffer. - pub const VREFBUF = extern struct { - /// control and status register. - CSR: mmio.Mmio(packed struct(u32) { - /// Voltage reference buffer mode enable. - ENVR: u1, - /// High impedance mode. - HIZ: packed union { - raw: u1, - value: HIZ, - }, - /// Voltage reference scale. - VRS: packed union { - raw: u1, - value: VRS, + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Transmit interrupt status The flag indicates that the TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the TXDR register. + TXIS: u1, + /// Message transmission discarded The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit. Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle. + TXMSGDISC: u1, + /// Message transmission completed The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit. In the event of a message transmission interrupted by a Hard Reset, the flag is not raised. + TXMSGSENT: u1, + /// Transmit message abort The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit. + TXMSGABT: u1, + /// Hard Reset discarded The flag indicates that the Hard Reset message is discarded. The flag is cleared by setting the HRSTDISCCF bit. + HRSTDISC: u1, + /// Hard Reset message sent The flag indicates that the Hard Reset message is sent. The flag is cleared by setting the HRSTSENTCF bit. + HRSTSENT: u1, + /// Tx data underrun detection The flag indicates that the Tx data register (TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit. + TXUND: u1, + reserved8: u1, + /// Receive data register not empty detection The flag indicates that the RXDR register is not empty. It is automatically cleared upon reading RXDR. + RXNE: u1, + /// Rx ordered set (4 K-codes) detection The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET[2:0] bitfield of the RX_ORDSET register. It is cleared by setting the RXORDDETCF bit. + RXORDDET: u1, + /// Rx Hard Reset receipt detection The flag indicates the receipt of valid Hard Reset message. It is cleared by setting the RXHRSTDETCF bit. + RXHRSTDET: u1, + /// Rx data overflow detection The flag indicates Rx data buffer overflow. It is cleared by setting the RXOVRCF bit. The buffer overflow can occur if the received data are not read fast enough. + RXOVR: u1, + /// Rx message received The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit. The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message. + RXMSGEND: u1, + /// Receive message error The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set. + RXERR: u1, + /// Type-C voltage level event on CC1 line The flag indicates a change of the TYPEC_VSTATE_CC1[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit. + TYPECEVT1: u1, + /// Type-C voltage level event on CC2 line The flag indicates a change of the TYPEC_VSTATE_CC2[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit. + TYPECEVT2: u1, + /// The status bitfield indicates the voltage level on the CC1 line in its steady state. The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value. + TYPEC_VSTATE_CC1: packed union { + raw: u2, + value: TYPEC_VSTATE_CC, }, - /// Voltage reference buffer ready. - VRR: u1, - padding: u28, - }), - /// calibration control register. - CCR: mmio.Mmio(packed struct(u32) { - /// Trimming code. - TRIM: u6, - padding: u26, - }), - }; - }; - - pub const pwr_h7rm0468 = struct { - pub const SDLEVEL = enum(u2) { - Reset = 0x0, - V1_8 = 0x1, - V2_5 = 0x2, - V2_5_ALT = 0x3, - }; - - pub const VOS = enum(u2) { - Scale0 = 0x0, - Scale3 = 0x1, - Scale2 = 0x2, - Scale1 = 0x3, - }; - - pub const WKUPPUPD = enum(u2) { - /// No pull-up. - NoPull = 0x0, - /// Pull-up. - PullUp = 0x1, - /// Pull-down. - PullDown = 0x2, - _, - }; - - /// PWR - pub const PWR = extern struct { - /// PWR control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) - LPDS: u1, - reserved4: u3, - /// Programmable voltage detector enable - PVDE: u1, - /// Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. - PLS: u3, - /// Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. - DBP: u1, - /// Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. - FLPS: u1, - reserved14: u4, - /// System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. - SVOS: u2, - /// Peripheral voltage monitor on VDDA enable - AVDEN: u1, - /// Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. - ALS: u2, - padding: u13, - }), - /// PWR control status register 1 - CSR1: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. - PVDO: u1, - reserved13: u8, - /// Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). - ACTVOSRDY: u1, - /// VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. - ACTVOS: u2, - /// Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set. - AVDO: u1, - padding: u15, - }), - /// This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. - CR2: mmio.Mmio(packed struct(u32) { - /// Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. - BREN: u1, - reserved4: u3, - /// VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. - MONEN: u1, - reserved16: u11, - /// Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. - BRRDY: u1, - reserved20: u3, - /// VBAT level monitoring versus low threshold - VBATL: u1, - /// VBAT level monitoring versus high threshold - VBATH: u1, - /// Temperature level monitoring versus low threshold - TEMPL: u1, - /// Temperature level monitoring versus high threshold - TEMPH: u1, - padding: u8, - }), - /// Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value. - CR3: mmio.Mmio(packed struct(u32) { - /// Power management unit bypass - BYPASS: u1, - /// Low drop-out regulator enable - LDOEN: u1, - /// SD converter Enable - SDEN: u1, - /// Step-down converter forced ON and in High Power MR mode - SDEXTHP: u1, - /// Step-down converter voltage output level selection - SDLEVEL: packed union { + /// CC2 line voltage level The status bitfield indicates the voltage level on the CC2 line in its steady state. The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value. + TYPEC_VSTATE_CC2: packed union { raw: u2, - value: SDLEVEL, + value: TYPEC_VSTATE_CC, }, - reserved8: u2, - /// VBAT charging enable - VBE: u1, - /// VBAT charging resistor selection - VBRS: u1, - reserved16: u6, - /// SMPS step-down converter external supply ready - SDEXTRDY: u1, - reserved24: u7, - /// VDD33USB voltage level detector enable. - USB33DEN: u1, - /// USB regulator enable. - USBREGEN: u1, - /// USB supply ready. - USB33RDY: u1, - padding: u5, + /// FRS detection event The flag is cleared by setting the FRSEVTCF bit. + FRSEVT: u1, + padding: u11, }), - /// This register allows controlling CPU1 power. - CPUCR: mmio.Mmio(packed struct(u32) { - /// D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. - PDDS_D1: u1, - /// D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. - PDDS_D2: u1, - /// System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. - PDDS_D3: u1, - reserved5: u2, - /// STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. - STOPF: u1, - /// System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit - SBF: u1, - /// D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. - SBF_D1: u1, - /// D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. - SBF_D2: u1, - /// Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. - CSSF: u1, - reserved11: u1, - /// Keep system D3 domain in Run mode regardless of the CPU sub-systems modes - RUN_D3: u1, - padding: u20, + /// interrupt clear register + ICR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Tx message discard flag (TXMSGDISC) clear Setting the bit clears the TXMSGDISC flag in the SR register. + TXMSGDISCCF: u1, + /// Tx message send flag (TXMSGSENT) clear Setting the bit clears the TXMSGSENT flag in the SR register. + TXMSGSENTCF: u1, + /// Tx message abort flag (TXMSGABT) clear Setting the bit clears the TXMSGABT flag in the SR register. + TXMSGABTCF: u1, + /// Hard reset discard flag (HRSTDISC) clear Setting the bit clears the HRSTDISC flag in the SR register. + HRSTDISCCF: u1, + /// Hard reset send flag (HRSTSENT) clear Setting the bit clears the HRSTSENT flag in the SR register. + HRSTSENTCF: u1, + /// Tx underflow flag (TXUND) clear Setting the bit clears the TXUND flag in the SR register. + TXUNDCF: u1, + reserved9: u2, + /// Rx ordered set detect flag (RXORDDET) clear Setting the bit clears the RXORDDET flag in the SR register. + RXORDDETCF: u1, + /// Rx Hard Reset detect flag (RXHRSTDET) clear Setting the bit clears the RXHRSTDET flag in the SR register. + RXHRSTDETCF: u1, + /// Rx overflow flag (RXOVR) clear Setting the bit clears the RXOVR flag in the SR register. + RXOVRCF: u1, + /// Rx message received flag (RXMSGEND) clear Setting the bit clears the RXMSGEND flag in the SR register. + RXMSGENDCF: u1, + reserved14: u1, + /// Type-C CC1 event flag (TYPECEVT1) clear Setting the bit clears the TYPECEVT1 flag in the SR register + TYPECEVT1CF: u1, + /// Type-C CC2 line event flag (TYPECEVT2) clear Setting the bit clears the TYPECEVT2 flag in the SR register + TYPECEVT2CF: u1, + reserved20: u4, + /// FRS event flag (FRSEVT) clear Setting the bit clears the FRSEVT flag in the SR register. + FRSEVTCF: u1, + padding: u11, + }), + /// Tx ordered set type register + TX_ORDSETR: mmio.Mmio(packed struct(u32) { + /// Ordered set to transmit The bitfield determines a full 20-bit sequence to transmit, consisting of four K-codes, each of five bits, defining the packet to transmit. The bit 0 (bit 0 of K-code1) is the first, the bit 19 (bit 4 of K‑code4) the last. + TXORDSET: u20, + padding: u12, }), - reserved24: [4]u8, - /// This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software - D3CR: mmio.Mmio(packed struct(u32) { - reserved13: u13, - /// VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). - VOSRDY: u1, - /// Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling. - VOS: packed union { - raw: u2, - value: VOS, + /// Tx payload size register + TX_PAYSZR: mmio.Mmio(packed struct(u32) { + /// Payload size yet to transmit The bitfield is modified by software and by hardware. It contains the number of bytes of a payload (including header but excluding CRC) yet to transmit: each time a data byte is written into the TXDR register, the bitfield value decrements and the TXIS bit is set, except when the bitfield value reaches zero. The enumerated values are standard payload sizes before the start of transmission. + TXPAYSZ: u10, + padding: u22, + }), + /// Tx data register + TXDR: mmio.Mmio(packed struct(u32) { + /// Data byte to transmit + TXDATA: u8, + padding: u24, + }), + RX_ORDSETR: mmio.Mmio(packed struct(u32) { + /// Rx ordered set code detected + RXORDSET: packed union { + raw: u3, + value: RXORDSET, }, - padding: u16, + /// The bit indicates the number of correct K‑codes. For debug purposes only. + RXSOP3OF4: u1, + /// The bitfield is for debug purposes only. Others: Invalid + RXSOPKINVALID: packed union { + raw: u3, + value: RXSOPKINVALID, + }, + padding: u25, }), - reserved32: [4]u8, - /// reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). - WKUPCR: mmio.Mmio(packed struct(u32) { - /// Clear Wakeup pin flag for WKUP. These bits are always read as 0. - WKUPC: u6, - padding: u26, + RX_PAYSZR: mmio.Mmio(packed struct(u32) { + /// Rx payload size received This bitfield contains the number of bytes of a payload (including header but excluding CRC) received: each time a new data byte is received in the RXDR register, the bitfield value increments and the RXMSGEND flag is set (and an interrupt generated if enabled). The bitfield may return a spurious value when a byte reception is ongoing (the RXMSGEND flag is low). + RXPAYSZ: u10, + padding: u22, }), - /// reset only by system reset, not reset by wakeup from Standby mode - WKUPFR: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). - WKUPF: u1, - padding: u31, + RXDR: mmio.Mmio(packed struct(u32) { + /// Data byte received + RXDATA: u8, + padding: u24, }), - /// Reset only by system reset, not reset by wakeup from Standby mode - WKUPEPR: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. - WKUPEN: u1, - reserved8: u7, - /// Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. - WKUPP: u1, - reserved16: u7, - /// Wakeup pin pull configuration - WKUPPUPD: packed union { - raw: u2, - value: WKUPPUPD, - }, - padding: u14, + /// Rx ordered set extension register 1 + RX_ORDEXTR1: mmio.Mmio(packed struct(u32) { + /// Ordered set 1 received The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last. + RXSOPX1: u20, + padding: u12, }), - }; - }; - - pub const pka_v1c = struct { - /// Public key accelerator. - pub const PKA = extern struct { - /// PKA control register. - CR: mmio.Mmio(packed struct(u32) { - /// PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application. - EN: u1, - /// start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy. - START: u1, - reserved8: u6, - /// PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. - MODE: u6, - reserved17: u3, - /// End of operation interrupt enable. - PROCENDIE: u1, - reserved19: u1, - /// RAM error interrupt enable. - RAMERRIE: u1, - /// Address error interrupt enable. - ADDRERRIE: u1, - padding: u11, + /// Rx ordered set extension register 2 + RX_ORDEXTR2: mmio.Mmio(packed struct(u32) { + /// Ordered set 2 received The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last. + RXSOPX2: u20, + padding: u12, }), - /// PKA status register. - SR: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). - BUSY: u1, - /// PKA End of Operation flag. - PROCENDF: u1, - reserved19: u1, - /// PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. - RAMERRF: u1, - /// Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. - ADDRERRF: u1, - padding: u11, + reserved1012: [952]u8, + /// UCPD IP ID register + IPVER: mmio.Mmio(packed struct(u32) { + /// IPVER + IPVER: u32, }), - /// PKA clear flag register. - CLRFR: mmio.Mmio(packed struct(u32) { - reserved17: u17, - /// Clear PKA End of Operation flag. - PROCENDFC: u1, - reserved19: u1, - /// Clear PKA RAM error flag. - RAMERRFC: u1, - /// Clear address error flag. - ADDRERRFC: u1, - padding: u11, + /// UCPD IP ID register + IPID: mmio.Mmio(packed struct(u32) { + /// IPID + IPID: u32, + }), + /// UCPD IP ID register + MID: mmio.Mmio(packed struct(u32) { + /// IPID + IPID: u32, }), - reserved1024: [1012]u8, - /// PKA internal memeory. - RAM: [894]u32, }; }; - pub const spi_v1 = struct { - pub const BIDIMODE = enum(u1) { - /// 2-line unidirectional data mode selected - Unidirectional = 0x0, - /// 1-line bidirectional data mode selected - Bidirectional = 0x1, + pub const uid_v1 = struct { + /// Device Factory programmed 96-bit unique device identifier + pub const UID = extern struct { + /// Factory programmed 96-bit unique device identifier word 0 + UID: [3]u32, }; + }; - pub const BIDIOE = enum(u1) { - /// Output disabled (receive-only mode) - Receive = 0x0, - /// Output enabled (transmit-only mode) - Transmit = 0x1, + pub const usart_v1 = struct { + pub const CPHA = enum(u1) { + /// The first clock transition is the first data capture edge + First = 0x0, + /// The second clock transition is the first data capture edge + Second = 0x1, }; - pub const BR = enum(u3) { - /// f_PCLK / 2 - Div2 = 0x0, - /// f_PCLK / 4 - Div4 = 0x1, - /// f_PCLK / 8 - Div8 = 0x2, - /// f_PCLK / 16 - Div16 = 0x3, - /// f_PCLK / 32 - Div32 = 0x4, - /// f_PCLK / 64 - Div64 = 0x5, - /// f_PCLK / 128 - Div128 = 0x6, - /// f_PCLK / 256 - Div256 = 0x7, + pub const CPOL = enum(u1) { + /// Steady low value on CK pin outside transmission window + Low = 0x0, + /// Steady high value on CK pin outside transmission window + High = 0x1, }; - pub const CHLEN = enum(u1) { - /// 16-bit wide - Bits16 = 0x0, - /// 32-bit wide - Bits32 = 0x1, + pub const IRLP = enum(u1) { + /// Normal mode + Normal = 0x0, + /// Low-power mode + LowPower = 0x1, }; - pub const CHSIDE = enum(u1) { - /// Channel left has to be transmitted or has been received - Left = 0x0, - /// Channel right has to be transmitted or has been received - Right = 0x1, + pub const LBDL = enum(u1) { + /// 10-bit break detection + Bit10 = 0x0, + /// 11-bit break detection + Bit11 = 0x1, }; - pub const CKPOL = enum(u1) { - /// I2S clock inactive state is low level - IdleLow = 0x0, - /// I2S clock inactive state is high level - IdleHigh = 0x1, + pub const M0 = enum(u1) { + /// 1 start bit, 8 data bits, n stop bits + Bit8 = 0x0, + /// 1 start bit, 9 data bits, n stop bits + Bit9 = 0x1, }; - pub const CPHA = enum(u1) { - /// The first clock transition is the first data capture edge - FirstEdge = 0x0, - /// The second clock transition is the first data capture edge - SecondEdge = 0x1, + pub const PS = enum(u1) { + /// Even parity + Even = 0x0, + /// Odd parity + Odd = 0x1, }; - pub const CPOL = enum(u1) { - /// CK to 0 when idle - IdleLow = 0x0, - /// CK to 1 when idle - IdleHigh = 0x1, + pub const RWU = enum(u1) { + /// Receiver in active mode + Active = 0x0, + /// Receiver in mute mode + Mute = 0x1, }; - pub const CRCNEXT = enum(u1) { - /// Next transmit value is from Tx buffer - TxBuffer = 0x0, - /// Next transmit value is from Tx CRC register - CRC = 0x1, + pub const STOP = enum(u2) { + /// 1 stop bit + Stop1 = 0x0, + /// 0.5 stop bits + Stop0p5 = 0x1, + /// 2 stop bits + Stop2 = 0x2, + /// 1.5 stop bits + Stop1p5 = 0x3, }; - pub const DATLEN = enum(u2) { - /// 16-bit data length - Bits16 = 0x0, - /// 24-bit data length - Bits24 = 0x1, - /// 32-bit data length - Bits32 = 0x2, - _, + pub const WAKE = enum(u1) { + /// USART wakeup on idle line + IdleLine = 0x0, + /// USART wakeup on address mark + AddressMark = 0x1, }; - pub const DFF = enum(u1) { - /// 8-bit data frame format is selected for transmission/reception - Bits8 = 0x0, - /// 16-bit data frame format is selected for transmission/reception - Bits16 = 0x1, + /// Universal asynchronous receiver transmitter + pub const UART = extern struct { + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding: u22, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// USARTDIV + BRR: u16, + padding: u16, + }), + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: packed union { + raw: u1, + value: RWU, + }, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: packed union { + raw: u1, + value: PS, + }, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: packed union { + raw: u1, + value: WAKE, + }, + /// Word length + M0: packed union { + raw: u1, + value: M0, + }, + /// USART enable + UE: u1, + padding: u18, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Address of the USART node + ADD: u4, + reserved5: u1, + /// Line break detection length + LBDL: packed union { + raw: u1, + value: LBDL, + }, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved12: u5, + /// STOP bits + STOP: packed union { + raw: u2, + value: STOP, + }, + /// LIN mode enable + LINEN: u1, + padding: u17, + }), + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: packed union { + raw: u1, + value: IRLP, + }, + /// Half-duplex selection + HDSEL: u1, + reserved6: u2, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + padding: u24, + }), }; - pub const FRF = enum(u1) { - /// SPI Motorola mode - Motorola = 0x0, - /// SPI TI mode - TI = 0x1, + /// Universal synchronous asynchronous receiver transmitter + pub const USART = extern struct { + reserved16: [16]u8, + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: packed union { + raw: u1, + value: CPHA, + }, + /// Clock polarity + CPOL: packed union { + raw: u1, + value: CPOL, + }, + /// Clock enable + CLKEN: u1, + padding: u20, + }), + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + reserved8: u2, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + padding: u21, + }), + /// Guard time and prescaler register + GTPR: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding: u16, + }), }; + }; - pub const I2SCFG = enum(u2) { - /// Slave - transmit - SlaveTx = 0x0, - /// Slave - receive - SlaveRx = 0x1, - /// Master - transmit - MasterTx = 0x2, - /// Master - receive - MasterRx = 0x3, + pub const usart_v2 = struct { + pub const CPHA = enum(u1) { + /// The first clock transition is the first data capture edge + First = 0x0, + /// The second clock transition is the first data capture edge + Second = 0x1, }; - pub const I2SSTD = enum(u2) { - /// I2S Philips standard - Philips = 0x0, - /// MSB justified standard - MSB = 0x1, - /// LSB justified standard - LSB = 0x2, - /// PCM standard - PCM = 0x3, + pub const CPOL = enum(u1) { + /// Steady low value on CK pin outside transmission window + Low = 0x0, + /// Steady high value on CK pin outside transmission window + High = 0x1, }; - pub const LSBFIRST = enum(u1) { - /// Data is transmitted/received with the MSB first - MSBFirst = 0x0, - /// Data is transmitted/received with the LSB first - LSBFirst = 0x1, + pub const IRLP = enum(u1) { + /// Normal mode + Normal = 0x0, + /// Low-power mode + LowPower = 0x1, }; - pub const MSTR = enum(u1) { - /// Slave configuration - Slave = 0x0, - /// Master configuration - Master = 0x1, + pub const LBDL = enum(u1) { + /// 10-bit break detection + Bit10 = 0x0, + /// 11-bit break detection + Bit11 = 0x1, }; - pub const ODD = enum(u1) { - /// Real divider value is I2SDIV * 2 + pub const M0 = enum(u1) { + /// 1 start bit, 8 data bits, n stop bits + Bit8 = 0x0, + /// 1 start bit, 9 data bits, n stop bits + Bit9 = 0x1, + }; + + pub const OVER8 = enum(u1) { + /// Oversampling by 16 + Oversampling16 = 0x0, + /// Oversampling by 8 + Oversampling8 = 0x1, + }; + + pub const PS = enum(u1) { + /// Even parity Even = 0x0, - /// Real divider value is (I2SDIV * 2) + 1 + /// Odd parity Odd = 0x1, }; - pub const PCMSYNC = enum(u1) { - /// Short frame synchronisation - Short = 0x0, - /// Long frame synchronisation - Long = 0x1, + pub const RWU = enum(u1) { + /// Receiver in active mode + Active = 0x0, + /// Receiver in mute mode + Mute = 0x1, }; - pub const RXONLY = enum(u1) { - /// Full duplex (Transmit and receive) - FullDuplex = 0x0, - /// Output disabled (Receive-only mode) - OutputDisabled = 0x1, + pub const STOP = enum(u2) { + /// 1 stop bit + Stop1 = 0x0, + /// 0.5 stop bits + Stop0p5 = 0x1, + /// 2 stop bits + Stop2 = 0x2, + /// 1.5 stop bits + Stop1p5 = 0x3, }; - /// Serial peripheral interface - pub const SPI = extern struct { - /// control register 1 + pub const WAKE = enum(u1) { + /// USART wakeup on idle line + IdleLine = 0x0, + /// USART wakeup on address mark + AddressMark = 0x1, + }; + + /// Universal asynchronous receiver transmitter + pub const UART = extern struct { + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding: u22, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// USARTDIV + BRR: u16, + padding: u16, + }), + /// Control register 1 CR1: mmio.Mmio(packed struct(u32) { - /// Clock phase - CPHA: packed union { - raw: u1, - value: CPHA, - }, - /// Clock polarity - CPOL: packed union { - raw: u1, - value: CPOL, - }, - /// Master selection - MSTR: packed union { - raw: u1, - value: MSTR, - }, - /// Baud rate control - BR: packed union { - raw: u3, - value: BR, - }, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: packed union { - raw: u1, - value: LSBFIRST, - }, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: packed union { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: packed union { raw: u1, - value: RXONLY, + value: RWU, }, - /// Data frame format - DFF: packed union { + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: packed union { raw: u1, - value: DFF, + value: PS, }, - /// CRC transfer next - CRCNEXT: packed union { + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: packed union { raw: u1, - value: CRCNEXT, + value: WAKE, }, - /// Hardware CRC calculation enable - CRCEN: u1, - /// Select the direction of transfer in bidirectional mode - BIDIOE: packed union { + /// Word length + M0: packed union { raw: u1, - value: BIDIOE, + value: M0, }, - /// Bidirectional data mode enable - BIDIMODE: packed union { + /// USART enable + UE: u1, + reserved15: u1, + /// Oversampling mode + OVER8: packed union { raw: u1, - value: BIDIMODE, + value: OVER8, }, padding: u16, }), - /// control register 2 + /// Control register 2 CR2: mmio.Mmio(packed struct(u32) { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved4: u1, - /// Frame format - FRF: packed union { + /// Address of the USART node + ADD: u4, + reserved5: u1, + /// Line break detection length + LBDL: packed union { raw: u1, - value: FRF, + value: LBDL, }, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt enable - RXNEIE: u1, - /// Tx buffer empty interrupt enable - TXEIE: u1, - padding: u24, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: packed union { - raw: u1, - value: CHSIDE, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved12: u5, + /// STOP bits + STOP: packed union { + raw: u2, + value: STOP, }, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - FRE: u1, - padding: u23, - }), - /// data register - DR: mmio.Mmio(packed struct(u32) { - /// Data register - DR: u16, - padding: u16, - }), - /// CRC polynomial register - CRCPR: mmio.Mmio(packed struct(u32) { - /// CRC polynomial register - CRCPOLY: u16, - padding: u16, - }), - /// RX CRC register - RXCRCR: mmio.Mmio(packed struct(u32) { - /// Rx CRC register - RxCRC: u16, - padding: u16, - }), - /// TX CRC register - TXCRCR: mmio.Mmio(packed struct(u32) { - /// Tx CRC register - TxCRC: u16, - padding: u16, + /// LIN mode enable + LINEN: u1, + padding: u17, }), - /// I2S configuration register - I2SCFGR: mmio.Mmio(packed struct(u32) { - /// Channel length (number of bits per audio channel) - CHLEN: packed union { + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: packed union { raw: u1, - value: CHLEN, - }, - /// Data length to be transferred - DATLEN: packed union { - raw: u2, - value: DATLEN, + value: IRLP, }, - /// Steady state clock polarity - CKPOL: packed union { + /// Half-duplex selection + HDSEL: u1, + reserved6: u2, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + padding: u24, + }), + }; + + /// Universal synchronous asynchronous receiver transmitter + pub const USART = extern struct { + reserved16: [16]u8, + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: packed union { raw: u1, - value: CKPOL, - }, - /// I2S standard selection - I2SSTD: packed union { - raw: u2, - value: I2SSTD, + value: CPHA, }, - reserved7: u1, - /// PCM frame synchronization - PCMSYNC: packed union { + /// Clock polarity + CPOL: packed union { raw: u1, - value: PCMSYNC, - }, - /// I2S configuration mode - I2SCFG: packed union { - raw: u2, - value: I2SCFG, + value: CPOL, }, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, + /// Clock enable + CLKEN: u1, padding: u20, }), - /// I2S prescaler register - I2SPR: mmio.Mmio(packed struct(u32) { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the prescaler - ODD: packed union { - raw: u1, - value: ODD, - }, - /// Master clock output enable - MCKOE: u1, - padding: u22, + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + reserved8: u2, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method enable + ONEBIT: u1, + padding: u20, + }), + /// Guard time and prescaler register + GTPR: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding: u16, }), }; }; - pub const fmc_v2x1 = struct { - pub const ACCMOD = enum(u2) { - /// Access mode A - A = 0x0, - /// Access mode B - B = 0x1, - /// Access mode C - C = 0x2, - /// Access mode D - D = 0x3, + pub const usart_v3 = struct { + pub const ABRMOD = enum(u2) { + /// Measurement of the start bit is used to detect the baud rate + Start = 0x0, + /// Falling edge to falling edge measurement + Edge = 0x1, + /// 0x7F frame detection + Frame7F = 0x2, + /// 0x55 frame detection + Frame55 = 0x3, }; - pub const CAS = enum(u2) { - /// 1 cycle - Clocks1 = 0x1, - /// 2 cycles - Clocks2 = 0x2, - /// 3 cycles - Clocks3 = 0x3, - _, + pub const ADDM = enum(u1) { + /// 4-bit address detection + Bit4 = 0x0, + /// 7-bit address detection + Bit7 = 0x1, }; - pub const CPSIZE = enum(u3) { - /// No burst split when crossing page boundary - NoBurstSplit = 0x0, - /// 128 bytes CRAM page size - Bytes128 = 0x1, - /// 256 bytes CRAM page size - Bytes256 = 0x2, - /// 512 bytes CRAM page size - Bytes512 = 0x3, - /// 1024 bytes CRAM page size - Bytes1024 = 0x4, - _, + pub const CPHA = enum(u1) { + /// The first clock transition is the first data capture edge + First = 0x0, + /// The second clock transition is the first data capture edge + Second = 0x1, }; - pub const ECCPS = enum(u3) { - /// ECC page size 256 bytes - Bytes256 = 0x0, - /// ECC page size 512 bytes - Bytes512 = 0x1, - /// ECC page size 1024 bytes - Bytes1024 = 0x2, - /// ECC page size 2048 bytes - Bytes2048 = 0x3, - /// ECC page size 4096 bytes - Bytes4096 = 0x4, - /// ECC page size 8192 bytes - Bytes8192 = 0x5, - _, + pub const CPOL = enum(u1) { + /// Steady low value on CK pin outside transmission window + Low = 0x0, + /// Steady high value on CK pin outside transmission window + High = 0x1, }; - pub const MODE = enum(u3) { - /// Normal Mode - Normal = 0x0, - /// Clock Configuration Enable - ClockConfigurationEnable = 0x1, - /// PALL (All Bank Precharge) command - PALL = 0x2, - /// Auto-refresh command - AutoRefreshCommand = 0x3, - /// Load Mode Resgier - LoadModeRegister = 0x4, - /// Self-refresh command - SelfRefreshCommand = 0x5, - /// Power-down command - PowerDownCommand = 0x6, - _, + pub const DEP = enum(u1) { + /// DE signal is active high + High = 0x0, + /// DE signal is active low + Low = 0x1, }; - pub const MODES = enum(u2) { - /// Normal Mode + pub const IRLP = enum(u1) { + /// Normal mode Normal = 0x0, - /// Self-refresh mode - SelfRefresh = 0x1, - /// Power-down mode - PowerDown = 0x2, - _, - }; - - pub const MTYP = enum(u2) { - /// SRAM memory type - SRAM = 0x0, - /// PSRAM (CRAM) memory type - PSRAM = 0x1, - /// NOR Flash/OneNAND Flash - Flash = 0x2, - _, + /// Low-power mode + LowPower = 0x1, }; - pub const MWID = enum(u2) { - /// Memory data bus width 8 bits - Bits8 = 0x0, - /// Memory data bus width 16 bits - Bits16 = 0x1, - /// Memory data bus width 32 bits - Bits32 = 0x2, - _, + pub const LBDL = enum(u1) { + /// 10-bit break detection + Bit10 = 0x0, + /// 11-bit break detection + Bit11 = 0x1, }; - pub const NB = enum(u1) { - /// Two internal Banks - NB2 = 0x0, - /// Four internal Banks - NB4 = 0x1, + pub const M0 = enum(u1) { + /// 1 start bit, 8 data bits, n stop bits + Bit8 = 0x0, + /// 1 start bit, 9 data bits, n stop bits + Bit9 = 0x1, }; - pub const NC = enum(u2) { - /// 8 bits - Bits8 = 0x0, - /// 9 bits - Bits9 = 0x1, - /// 10 bits - Bits10 = 0x2, - /// 11 bits - Bits11 = 0x3, + pub const M1 = enum(u1) { + /// Use M0 to set the data bits + M0 = 0x0, + /// 1 start bit, 7 data bits, n stop bits + Bit7 = 0x1, }; - pub const NR = enum(u2) { - /// 11 bits - Bits11 = 0x0, - /// 12 bits - Bits12 = 0x1, - /// 13 bits - Bits13 = 0x2, - _, + pub const MSBFIRST = enum(u1) { + /// data is transmitted/received with data bit 0 first, following the start bit + LSB = 0x0, + /// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit + MSB = 0x1, }; - pub const PTYP = enum(u1) { - /// NAND Flash - NANDFlash = 0x1, - _, + pub const OVER8 = enum(u1) { + /// Oversampling by 16 + Oversampling16 = 0x0, + /// Oversampling by 8 + Oversampling8 = 0x1, }; - pub const PWID = enum(u2) { - /// External memory device width 8 bits - Bits8 = 0x0, - /// External memory device width 16 bits - Bits16 = 0x1, - _, + pub const PS = enum(u1) { + /// Even parity + Even = 0x0, + /// Odd parity + Odd = 0x1, }; - pub const RPIPE = enum(u2) { - /// No clock cycle delay - NoDelay = 0x0, - /// One clock cycle delay - Clocks1 = 0x1, - /// Two clock cycles delay - Clocks2 = 0x2, - _, + pub const RWU = enum(u1) { + /// Receiver in active mode + Active = 0x0, + /// Receiver in mute mode + Mute = 0x1, }; - pub const SDCLK = enum(u2) { - /// SDCLK clock disabled - Disabled = 0x0, - /// SDCLK period = 2 x HCLK period - Div2 = 0x2, - /// SDCLK period = 3 x HCLK period - Div3 = 0x3, - _, + pub const STOP = enum(u2) { + /// 1 stop bit + Stop1 = 0x0, + /// 0.5 stop bits + Stop0p5 = 0x1, + /// 2 stop bits + Stop2 = 0x2, + /// 1.5 stop bits + Stop1p5 = 0x3, }; - pub const WAITCFG = enum(u1) { - /// NWAIT signal is active one data cycle before wait state - BeforeWaitState = 0x0, - /// NWAIT signal is active during wait state - DuringWaitState = 0x1, + pub const WAKE = enum(u1) { + /// USART wakeup on idle line + IdleLine = 0x0, + /// USART wakeup on address mark + AddressMark = 0x1, }; - pub const WAITPOL = enum(u1) { - /// NWAIT active low - ActiveLow = 0x0, - /// NWAIT active high - ActiveHigh = 0x1, + pub const WUS = enum(u2) { + /// WUF active on address match + Address = 0x0, + /// WuF active on Start bit detection + Start = 0x2, + /// WUF active on RXNE + RXNE = 0x3, + _, }; - /// Flexible memory controller - pub const FMC = extern struct { - /// SRAM/NOR-Flash chip-select control register 1 - BCR1: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { - raw: u2, - value: MTYP, - }, - /// Memory data bus width - MWID: packed union { - raw: u2, - value: MWID, + /// Low-power Universal synchronous asynchronous receiver transmitter + pub const LPUART = extern struct { + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: packed union { + raw: u1, + value: PS, }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: packed union { raw: u1, - value: WAITPOL, + value: WAKE, }, - reserved11: u1, - /// Wait timing configuration - WAITCFG: packed union { + /// Word length + M0: packed union { raw: u1, - value: WAITCFG, + value: M0, }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - /// CRAM page size - CPSIZE: packed union { - raw: u3, - value: CPSIZE, + /// Mute mode enable + MME: u1, + /// Character match interrupt enable + CMIE: u1, + /// Oversampling mode + OVER8: packed union { + raw: u1, + value: OVER8, }, - /// Write burst enable - CBURSTRW: u1, - /// Continuous clock enable - CCLKEN: u1, - /// Write FIFO disable - WFDIS: u1, - padding: u10, - }), - /// SRAM/NOR-Flash chip-select timing register 1-4 - BTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - /// Clock divide ratio (for FMC_CLK signal) - CLKDIV: u4, - /// Data latency for synchronous memory - DATLAT: u4, - /// Access mode - ACCMOD: packed union { - raw: u2, - value: ACCMOD, + /// Driver Enable deassertion time + DEDT: u5, + /// Driver Enable assertion time + DEAT: u5, + /// Receiver timeout interrupt enable + RTOIE: u1, + /// End of Block interrupt enable + EOBIE: u1, + /// Word length + M1: packed union { + raw: u1, + value: M1, }, - padding: u2, + padding: u3, }), - /// SRAM/NOR-Flash chip-select control register 2-4 - BCR: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { - raw: u2, - value: MTYP, + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// 7-bit Address Detection/4-bit Address Detection + ADDM: packed union { + raw: u1, + value: ADDM, }, - /// Memory data bus width - MWID: packed union { - raw: u2, - value: MWID, + /// Line break detection length + LBDL: packed union { + raw: u1, + value: LBDL, }, - /// Flash access enable - FACCEN: u1, + /// LIN break detection interrupt enable + LBDIE: u1, reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: packed union { raw: u1, - value: WAITPOL, + value: CPHA, }, - reserved11: u1, - /// Wait timing configuration - WAITCFG: packed union { + /// Clock polarity + CPOL: packed union { raw: u1, - value: WAITCFG, + value: CPOL, }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - /// CRAM page size - CPSIZE: packed union { - raw: u3, - value: CPSIZE, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: packed union { + raw: u2, + value: STOP, }, - /// Write burst enable - CBURSTRW: u1, - padding: u12, - }), - reserved128: [116]u8, - /// PC Card/NAND Flash control register - PCR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Wait feature enable bit - PWAITEN: u1, - /// NAND Flash memory bank enable bit - PBKEN: u1, - /// Memory type - PTYP: packed union { + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level inversion + RXINV: u1, + /// TX pin active level inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: packed union { raw: u1, - value: PTYP, + value: MSBFIRST, }, - /// Data bus width - PWID: packed union { + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: packed union { raw: u2, - value: PWID, - }, - /// ECC computation logic enable bit - ECCEN: u1, - reserved9: u2, - /// CLE to RE delay - TCLR: u4, - /// ALE to RE delay - TAR: u4, - /// ECC page size - ECCPS: packed union { - raw: u3, - value: ECCPS, + value: ABRMOD, }, - padding: u12, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD: u8, }), - /// FIFO status and interrupt register - SR: mmio.Mmio(packed struct(u32) { - /// Interrupt rising edge status - IRS: u1, - /// Interrupt high-level status - ILS: u1, - /// Interrupt falling edge status - IFS: u1, - /// Interrupt rising edge detection enable bit + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable IREN: u1, - /// Interrupt high-level detection enable bit - ILEN: u1, - /// Interrupt falling edge detection enable bit - IFEN: u1, - /// FIFO empty status - FEMPT: u1, - padding: u25, + /// IrDA low-power + IRLP: packed union { + raw: u1, + value: IRLP, + }, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity selection + DEP: packed union { + raw: u1, + value: DEP, + }, + reserved17: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag selection + WUS: packed union { + raw: u2, + value: WUS, + }, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1, + padding: u9, }), - /// Common memory space timing register - PMEM: mmio.Mmio(packed struct(u32) { - /// Common memory x setup time - MEMSET: u8, - /// Common memory wait time - MEMWAIT: u8, - /// Common memory hold time - MEMHOLD: u8, - /// Common memory x data bus Hi-Z time - MEMHIZ: u8, + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// USARTDIV + BRR: u16, + padding: u16, }), - /// Attribute memory space timing register - PATT: mmio.Mmio(packed struct(u32) { - /// Attribute memory setup time - ATTSET: u8, - /// Attribute memory wait time - ATTWAIT: u8, - /// Attribute memory hold time - ATTHOLD: u8, - /// Attribute memory data bus Hi-Z time - ATTHIZ: u8, + reserved24: [8]u8, + /// Request register + RQR: mmio.Mmio(packed struct(u32) { + /// Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. + ABRRQ: u1, + /// Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available + SBKRQ: u1, + /// Mute mode request. Puts the USART in mute mode and sets the RWU flag. + MMRQ: u1, + /// Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition + RXFRQ: u1, + /// Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data. + TXFRQ: u1, + padding: u27, }), - reserved148: [4]u8, - /// ECC result register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC computation result value - ECC: u32, + /// Interrupt & status register + ISR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved14: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute mode + RWU: packed union { + raw: u1, + value: RWU, + }, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge flag + TEACK: u1, + /// Receive enable acknowledge flag + REACK: u1, + padding: u9, }), - reserved260: [108]u8, - /// SRAM/NOR-Flash write timing registers 1-4 - BWTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - reserved28: u8, - /// Access mode - ACCMOD: packed union { - raw: u2, - value: ACCMOD, + /// Interrupt flag clear register + ICR: mmio.Mmio(packed struct(u32) { + /// Parity error clear flag + PE: u1, + /// Framing error clear flag + FE: u1, + /// Noise error clear flag + NE: u1, + /// Overrun error clear flag + ORE: u1, + /// Idle line detected clear flag + IDLE: u1, + reserved6: u1, + /// Transmission complete clear flag + TC: u1, + reserved8: u1, + /// LIN break detection clear flag + LBD: u1, + /// CTS clear flag + CTS: u1, + reserved11: u1, + /// Receiver timeout clear flag + RTOF: u1, + /// End of block clear flag + EOBF: u1, + reserved17: u4, + /// Character match clear flag + CMF: u1, + reserved20: u2, + /// Wakeup from Stop mode clear flag + WUF: u1, + padding: u11, + }), + /// Receive data register + RDR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Transmit data register + TDR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + }; + + /// Universal synchronous asynchronous receiver transmitter + pub const USART = extern struct { + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: packed union { + raw: u1, + value: PS, }, - padding: u2, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: packed union { + raw: u1, + value: WAKE, + }, + /// Word length + M0: packed union { + raw: u1, + value: M0, + }, + /// Mute mode enable + MME: u1, + /// Character match interrupt enable + CMIE: u1, + /// Oversampling mode + OVER8: packed union { + raw: u1, + value: OVER8, + }, + /// Driver Enable deassertion time + DEDT: u5, + /// Driver Enable assertion time + DEAT: u5, + /// Receiver timeout interrupt enable + RTOIE: u1, + /// End of Block interrupt enable + EOBIE: u1, + /// Word length + M1: packed union { + raw: u1, + value: M1, + }, + padding: u3, }), - reserved320: [56]u8, - /// SDRAM Control Register 1-2 - SDCR: [2]mmio.Mmio(packed struct(u32) { - /// Number of column address bits - NC: packed union { - raw: u2, - value: NC, + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// 7-bit Address Detection/4-bit Address Detection + ADDM: packed union { + raw: u1, + value: ADDM, }, - /// Number of row address bits - NR: packed union { - raw: u2, - value: NR, + /// Line break detection length + LBDL: packed union { + raw: u1, + value: LBDL, }, - /// Memory data bus width - MWID: packed union { - raw: u2, - value: MWID, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved8: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: packed union { + raw: u1, + value: CPHA, }, - /// Number of internal banks - NB: packed union { + /// Clock polarity + CPOL: packed union { raw: u1, - value: NB, + value: CPOL, }, - /// CAS latency - CAS: packed union { + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: packed union { raw: u2, - value: CAS, + value: STOP, }, - /// Write protection - WP: u1, - /// SDRAM clock configuration - SDCLK: packed union { - raw: u2, - value: SDCLK, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level inversion + RXINV: u1, + /// TX pin active level inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: packed union { + raw: u1, + value: MSBFIRST, }, - /// Burst read - RBURST: u1, - /// Read pipe - RPIPE: packed union { + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: packed union { raw: u2, - value: RPIPE, + value: ABRMOD, }, - padding: u17, - }), - /// SDRAM Timing register 1-2 - SDTR: [2]mmio.Mmio(packed struct(u32) { - /// Load Mode Register to Active - TMRD: u4, - /// Exit self-refresh delay - TXSR: u4, - /// Self refresh time - TRAS: u4, - /// Row cycle delay - TRC: u4, - /// Recovery delay - TWR: u4, - /// Row precharge delay - TRP: u4, - /// Row to column delay - TRCD: u4, - padding: u4, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD: u8, }), - /// SDRAM Command Mode register - SDCMR: mmio.Mmio(packed struct(u32) { - /// Command mode - MODE: packed union { - raw: u3, - value: MODE, + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: packed union { + raw: u1, + value: IRLP, }, - /// Command target bank 2 - CTB2: u1, - /// Command target bank 1 - CTB1: u1, - /// Number of Auto-refresh - NRFS: u4, - /// Mode Register definition - MRD: u13, - padding: u10, - }), - /// SDRAM Refresh Timer register - SDRTR: mmio.Mmio(packed struct(u32) { - /// Clear Refresh error flag - CRE: u1, - /// Refresh Timer Count - COUNT: u13, - /// RES Interrupt Enable - REIE: u1, - padding: u17, - }), - /// SDRAM Status register - SDSR: mmio.Mmio(packed struct(u32) { - /// Refresh error flag - RE: u1, - /// Status Mode for Bank 1 - MODES1: packed union { - raw: u2, - value: MODES, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity selection + DEP: packed union { + raw: u1, + value: DEP, }, - /// Status Mode for Bank 2 - MODES2: packed union { + reserved17: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag selection + WUS: packed union { raw: u2, - value: MODES, + value: WUS, }, - /// Busy status + /// Wakeup from Stop mode interrupt enable + WUFIE: u1, + padding: u9, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// USARTDIV + BRR: u16, + padding: u16, + }), + /// Guard time and prescaler register + GTPR: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding: u16, + }), + /// Receiver timeout register + RTOR: mmio.Mmio(packed struct(u32) { + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), + /// Request register + RQR: mmio.Mmio(packed struct(u32) { + /// Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. + ABRRQ: u1, + /// Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available + SBKRQ: u1, + /// Mute mode request. Puts the USART in mute mode and sets the RWU flag. + MMRQ: u1, + /// Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition + RXFRQ: u1, + /// Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data. + TXFRQ: u1, + padding: u27, + }), + /// Interrupt & status register + ISR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved14: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag BUSY: u1, - padding: u26, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute mode + RWU: packed union { + raw: u1, + value: RWU, + }, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge flag + TEACK: u1, + /// Receive enable acknowledge flag + REACK: u1, + padding: u9, + }), + /// Interrupt flag clear register + ICR: mmio.Mmio(packed struct(u32) { + /// Parity error clear flag + PE: u1, + /// Framing error clear flag + FE: u1, + /// Noise error clear flag + NE: u1, + /// Overrun error clear flag + ORE: u1, + /// Idle line detected clear flag + IDLE: u1, + reserved6: u1, + /// Transmission complete clear flag + TC: u1, + reserved8: u1, + /// LIN break detection clear flag + LBD: u1, + /// CTS clear flag + CTS: u1, + reserved11: u1, + /// Receiver timeout clear flag + RTOF: u1, + /// End of block clear flag + EOBF: u1, + reserved17: u4, + /// Character match clear flag + CMF: u1, + reserved20: u2, + /// Wakeup from Stop mode clear flag + WUF: u1, + padding: u11, + }), + /// Receive data register + RDR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Transmit data register + TDR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, }), }; - }; - - pub const rtc_v3u5 = struct { - pub const ALRF = enum(u1) { - /// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - Match = 0x1, - _, - }; - - pub const ALRMF = enum(u1) { - /// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - Match = 0x1, - _, - }; - - pub const ALRMR_MSK = enum(u1) { - /// Alarm set if the date/day match - ToMatch = 0x0, - /// Date/day don’t care in Alarm comparison - NotMatch = 0x1, - }; - - pub const ALRMR_PM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, - }; - - pub const ALRMR_WDSEL = enum(u1) { - /// DU[3:0] represents the date units - DateUnits = 0x0, - /// DU[3:0] represents the week day. DT[1:0] is don’t care. - WeekDay = 0x1, - }; - - pub const ALRMSSR_SSCLR = enum(u1) { - /// The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running - FreeRunning = 0x0, - /// The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0] - ALRMBINR = 0x1, - }; - - pub const AMPM = enum(u1) { - /// AM or 24-hour format - AM = 0x0, - /// PM - PM = 0x1, - }; - - pub const BCDU = enum(u3) { - /// 1s increment each time SS[7:0]=0 - Bit7 = 0x0, - /// 1s increment each time SS[8:0]=0 - Bit8 = 0x1, - /// 1s increment each time SS[9:0]=0 - Bit9 = 0x2, - /// 1s increment each time SS[10:0]=0 - Bit10 = 0x3, - /// 1s increment each time SS[11:0]=0 - Bit11 = 0x4, - /// 1s increment each time SS[12:0]=0 - Bit12 = 0x5, - /// 1s increment each time SS[13:0]=0 - Bit13 = 0x6, - /// 1s increment each time SS[14:0]=0 - Bit14 = 0x7, - }; - - pub const BIN = enum(u2) { - /// Free running BCD calendar mode (Binary mode disabled) - BCD = 0x0, - /// Free running Binary mode (BCD mode disabled) - Binary = 0x1, - /// Free running BCD calendar and Binary modes - BinBCD = 0x2, - /// Free running BCD calendar and Binary modes - BinBCD2 = 0x3, - }; - - pub const CALP = enum(u1) { - /// No RTCCLK pulses are added - NoChange = 0x0, - /// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - IncreaseFreq = 0x1, - }; - - pub const CALRF = enum(u1) { - /// Clear interrupt flag by writing 1 - Clear = 0x1, - _, - }; - - pub const CALW16 = enum(u1) { - /// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 - SixteenSeconds = 0x1, - _, - }; - - pub const CALW8 = enum(u1) { - /// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected - EightSeconds = 0x1, - _, - }; - - pub const COSEL = enum(u1) { - /// Calibration output is 512 Hz (with default prescaler setting) - CalFreq_512Hz = 0x0, - /// Calibration output is 1 Hz (with default prescaler setting) - CalFreq_1Hz = 0x1, - }; - - pub const FMT = enum(u1) { - /// 24 hour/day format - TwentyFourHour = 0x0, - /// AM/PM hour format - AmPm = 0x1, - }; - - pub const ITSF = enum(u1) { - /// This flag is set by hardware when a timestamp on the internal event occurs - TimestampEvent = 0x1, - _, - }; + }; - pub const ITSMF = enum(u1) { - /// This flag is set by hardware when a timestamp on the internal event occurs - TimestampEvent = 0x1, - _, + pub const usart_v4 = struct { + pub const ABRMOD = enum(u2) { + /// Measurement of the start bit is used to detect the baud rate + Start = 0x0, + /// Falling edge to falling edge measurement + Edge = 0x1, + /// 0x7F frame detection + Frame7F = 0x2, + /// 0x55 frame detection + Frame55 = 0x3, }; - pub const KEY = enum(u8) { - /// Activate write protection (any value that is not the keys) - Activate = 0x0, - /// Key 2 - Deactivate2 = 0x53, - /// Key 1 - Deactivate1 = 0xca, - _, + pub const ADDM = enum(u1) { + /// 4-bit address detection + Bit4 = 0x0, + /// 7-bit address detection + Bit7 = 0x1, }; - pub const LPCAL = enum(u1) { - /// Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required - RTCCLK = 0x0, - /// Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode - CkApre = 0x1, + pub const CPHA = enum(u1) { + /// The first clock transition is the first data capture edge + First = 0x0, + /// The second clock transition is the first data capture edge + Second = 0x1, }; - pub const OSEL = enum(u2) { - /// Output disabled - Disabled = 0x0, - /// Alarm A output enabled - AlarmA = 0x1, - /// Alarm B output enabled - AlarmB = 0x2, - /// Wakeup output enabled - Wakeup = 0x3, + pub const CPOL = enum(u1) { + /// Steady low value on CK pin outside transmission window + Low = 0x0, + /// Steady high value on CK pin outside transmission window + High = 0x1, }; - pub const POL = enum(u1) { - /// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + pub const DEP = enum(u1) { + /// DE signal is active high High = 0x0, - /// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + /// DE signal is active low Low = 0x1, }; - pub const RECALPF = enum(u1) { - /// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 - Pending = 0x1, - _, + pub const IRLP = enum(u1) { + /// Normal mode + Normal = 0x0, + /// Low-power mode + LowPower = 0x1, }; - pub const SSRUF = enum(u1) { - /// This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 - Underflow = 0x1, - _, + pub const LBDL = enum(u1) { + /// 10-bit break detection + Bit10 = 0x0, + /// 11-bit break detection + Bit11 = 0x1, }; - pub const SSRUMF = enum(u1) { - /// This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 - Underflow = 0x1, - _, + pub const M0 = enum(u1) { + /// 1 start bit, 8 data bits, n stop bits + Bit8 = 0x0, + /// 1 start bit, 9 data bits, n stop bits + Bit9 = 0x1, }; - pub const TAMPALRM_TYPE = enum(u1) { - /// TAMPALRM is push-pull output - PushPull = 0x0, - /// TAMPALRM is open-drain output - OpenDrain = 0x1, + pub const M1 = enum(u1) { + /// Use M0 to set the data bits + M0 = 0x0, + /// 1 start bit, 7 data bits, n stop bits + Bit7 = 0x1, }; - pub const TSEDGE = enum(u1) { - /// RTC_TS input rising edge generates a time-stamp event - RisingEdge = 0x0, - /// RTC_TS input falling edge generates a time-stamp event - FallingEdge = 0x1, + pub const MSBFIRST = enum(u1) { + /// data is transmitted/received with data bit 0 first, following the start bit + LSB = 0x0, + /// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit + MSB = 0x1, }; - pub const TSF = enum(u1) { - /// This flag is set by hardware when a time-stamp event occurs - TimestampEvent = 0x1, - _, + pub const OVER8 = enum(u1) { + /// Oversampling by 16 + Oversampling16 = 0x0, + /// Oversampling by 8 + Oversampling8 = 0x1, }; - pub const TSMF = enum(u1) { - /// This flag is set by hardware when a time-stamp event occurs - TimestampEvent = 0x1, + pub const PRESC = enum(u4) { + /// input clock not divided + Div1 = 0x0, + /// input clock divided by 2 + Div2 = 0x1, + /// input clock divided by 4 + Div4 = 0x2, + /// input clock divided by 6 + Div6 = 0x3, + /// input clock divided by 8 + Div8 = 0x4, + /// input clock divided by 10 + Div10 = 0x5, + /// input clock divided by 12 + Div12 = 0x6, + /// input clock divided by 16 + Div16 = 0x7, + /// input clock divided by 32 + Div32 = 0x8, + /// input clock divided by 64 + Div64 = 0x9, + /// input clock divided by 128 + Div128 = 0xa, + /// input clock divided by 256 + Div256 = 0xb, _, }; - pub const TSOVF = enum(u1) { - /// This flag is set by hardware when a time-stamp event occurs while TSF is already set - Overflow = 0x1, - _, + pub const PS = enum(u1) { + /// Even parity + Even = 0x0, + /// Odd parity + Odd = 0x1, }; - pub const TSOVMF = enum(u1) { - /// This flag is set by hardware when a time-stamp event occurs while TSF is already set - Overflow = 0x1, - _, + pub const RWU = enum(u1) { + /// Receiver in active mode + Active = 0x0, + /// Receiver in mute mode + Mute = 0x1, }; - pub const WUCKSEL = enum(u3) { - /// RTC/16 clock is selected - Div16 = 0x0, - /// RTC/8 clock is selected - Div8 = 0x1, - /// RTC/4 clock is selected - Div4 = 0x2, - /// RTC/2 clock is selected - Div2 = 0x3, - /// ck_spre (usually 1 Hz) clock is selected - ClockSpare = 0x4, - /// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - ClockSpareWithOffset = 0x6, - _, + pub const STOP = enum(u2) { + /// 1 stop bit + Stop1 = 0x0, + /// 0.5 stop bits + Stop0p5 = 0x1, + /// 2 stop bits + Stop2 = 0x2, + /// 1.5 stop bits + Stop1p5 = 0x3, }; - pub const WUTF = enum(u1) { - /// This flag is set by hardware when the wakeup auto-reload counter reaches 0 - Zero = 0x1, - _, + pub const WAKE = enum(u1) { + /// USART wakeup on idle line + IdleLine = 0x0, + /// USART wakeup on address mark + AddressMark = 0x1, }; - pub const WUTMF = enum(u1) { - /// This flag is set by hardware when the wakeup auto-reload counter reaches 0 - Zero = 0x1, + pub const WUS = enum(u2) { + /// WUF active on address match + Address = 0x0, + /// WuF active on Start bit detection + Start = 0x2, + /// WUF active on RXNE + RXNE = 0x3, _, }; - /// Real-time clock - pub const RTC = extern struct { - /// Time register - TR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { + /// Low-power Universal synchronous asynchronous receiver transmitter + pub const LPUART = extern struct { + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: packed union { raw: u1, - value: AMPM, + value: PS, }, - padding: u9, - }), - /// Date register - DR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding: u8, - }), - /// Sub second register - SSR: mmio.Mmio(packed struct(u32) { - /// Synchronous binary counter - SS: u32, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: packed union { + raw: u1, + value: WAKE, + }, + /// Word length + M0: packed union { + raw: u1, + value: M0, + }, + /// Mute mode enable + MME: u1, + /// Character match interrupt enable + CMIE: u1, + /// Oversampling mode + OVER8: packed union { + raw: u1, + value: OVER8, + }, + /// Driver Enable deassertion time + DEDT: u5, + /// Driver Enable assertion time + DEAT: u5, + /// Receiver timeout interrupt enable + RTOIE: u1, + /// End of Block interrupt enable + EOBIE: u1, + /// Word length + M1: packed union { + raw: u1, + value: M1, + }, + /// FIFO mode enable + FIFOEN: u1, + /// TXFIFO empty interrupt enable + TXFEIE: u1, + /// RXFIFO Full interrupt enable + RXFFIE: u1, }), - /// Initialization control and status register - ICSR: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Wakeup timer write enabled - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Enter Initialization mode - INIT: u1, - /// Binary mode - BIN: packed union { + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// 7-bit Address Detection/4-bit Address Detection + ADDM: packed union { + raw: u1, + value: ADDM, + }, + /// Line break detection length + LBDL: packed union { + raw: u1, + value: LBDL, + }, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved8: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: packed union { + raw: u1, + value: CPHA, + }, + /// Clock polarity + CPOL: packed union { + raw: u1, + value: CPOL, + }, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: packed union { raw: u2, - value: BIN, + value: STOP, }, - /// BCD update - BCDU: packed union { - raw: u3, - value: BCDU, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level inversion + RXINV: u1, + /// TX pin active level inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: packed union { + raw: u1, + value: MSBFIRST, }, - reserved16: u3, - /// Recalibration pending Flag - RECALPF: packed union { + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: packed union { + raw: u2, + value: ABRMOD, + }, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD: u8, + }), + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: packed union { raw: u1, - value: RECALPF, + value: IRLP, }, - padding: u15, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity selection + DEP: packed union { + raw: u1, + value: DEP, + }, + reserved17: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag selection + WUS: packed union { + raw: u2, + value: WUS, + }, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1, + /// TXFIFO threshold interrupt enable + TXFTIE: u1, + reserved25: u1, + /// Receive FIFO threshold configuration + RXFTCFG: u3, + /// RXFIFO threshold interrupt enable + RXFTIE: u1, + /// TXFIFO threshold configuration + TXFTCFG: u3, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// USARTDIV + BRR: u16, + padding: u16, + }), + reserved24: [8]u8, + /// Request register + RQR: mmio.Mmio(packed struct(u32) { + /// Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. + ABRRQ: u1, + /// Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available + SBKRQ: u1, + /// Mute mode request. Puts the USART in mute mode and sets the RWU flag. + MMRQ: u1, + /// Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition + RXFRQ: u1, + /// Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data. + TXFRQ: u1, + padding: u27, + }), + /// Interrupt & status register + ISR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved14: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute mode + RWU: packed union { + raw: u1, + value: RWU, + }, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge flag + TEACK: u1, + /// Receive enable acknowledge flag + REACK: u1, + /// TXFIFO Empty + TXFE: u1, + /// RXFIFO Full + RXFF: u1, + reserved26: u1, + /// RXFIFO threshold flag + RXFT: u1, + /// TXFIFO threshold flag + TXFT: u1, + padding: u4, + }), + /// Interrupt flag clear register + ICR: mmio.Mmio(packed struct(u32) { + /// Parity error clear flag + PE: u1, + /// Framing error clear flag + FE: u1, + /// Noise error clear flag + NE: u1, + /// Overrun error clear flag + ORE: u1, + /// Idle line detected clear flag + IDLE: u1, + reserved6: u1, + /// Transmission complete clear flag + TC: u1, + reserved8: u1, + /// LIN break detection clear flag + LBD: u1, + /// CTS clear flag + CTS: u1, + reserved11: u1, + /// Receiver timeout clear flag + RTOF: u1, + /// End of block clear flag + EOBF: u1, + reserved17: u4, + /// Character match clear flag + CMF: u1, + reserved20: u2, + /// Wakeup from Stop mode clear flag + WUF: u1, + padding: u11, + }), + /// Receive data register + RDR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Transmit data register + TDR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, }), /// Prescaler register - PRER: mmio.Mmio(packed struct(u32) { - /// Synchronous prescaler factor - PREDIV_S: u15, - reserved16: u1, - /// Asynchronous prescaler factor - PREDIV_A: u7, - padding: u9, + PRESC: mmio.Mmio(packed struct(u32) { + /// Clock prescaler + PRESCALER: packed union { + raw: u4, + value: PRESC, + }, + padding: u28, }), - /// Wakeup timer register - WUTR: mmio.Mmio(packed struct(u32) { - /// Wakeup auto-reload value bits - WUT: u16, - /// Wakeup auto-reload output clear value - WUTOCLR: u16, + }; + + /// Universal synchronous asynchronous receiver transmitter + pub const USART = extern struct { + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: packed union { + raw: u1, + value: PS, + }, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: packed union { + raw: u1, + value: WAKE, + }, + /// Word length + M0: packed union { + raw: u1, + value: M0, + }, + /// Mute mode enable + MME: u1, + /// Character match interrupt enable + CMIE: u1, + /// Oversampling mode + OVER8: packed union { + raw: u1, + value: OVER8, + }, + /// Driver Enable deassertion time + DEDT: u5, + /// Driver Enable assertion time + DEAT: u5, + /// Receiver timeout interrupt enable + RTOIE: u1, + /// End of Block interrupt enable + EOBIE: u1, + /// Word length + M1: packed union { + raw: u1, + value: M1, + }, + /// FIFO mode enable + FIFOEN: u1, + /// TXFIFO empty interrupt enable + TXFEIE: u1, + /// RXFIFO Full interrupt enable + RXFFIE: u1, }), - /// Control register - CR: mmio.Mmio(packed struct(u32) { - /// Wakeup clock selection - WUCKSEL: packed union { - raw: u3, - value: WUCKSEL, + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// 7-bit Address Detection/4-bit Address Detection + ADDM: packed union { + raw: u1, + value: ADDM, }, - /// Timestamp event active edge - TSEDGE: packed union { + /// Line break detection length + LBDL: packed union { raw: u1, - value: TSEDGE, + value: LBDL, }, - /// RTC_REFIN reference clock detection enable (50 or 60 Hz) - REFCKON: u1, - /// Bypass the shadow registers - BYPSHAD: u1, - /// Hour format - FMT: packed union { + /// LIN break detection interrupt enable + LBDIE: u1, + reserved8: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: packed union { raw: u1, - value: FMT, + value: CPHA, }, - /// SSR underflow interrupt enable - SSRUIE: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, - /// Wakeup timer enable - WUTE: u1, - /// Timestamp enable - TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, - /// Wakeup timer interrupt enable - WUTIE: u1, - /// Timestamp interrupt enable - TSIE: u1, - /// Add 1 hour (summer time change) - ADD1H: u1, - /// Subtract 1 hour (winter time change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output selection - COSEL: packed union { + /// Clock polarity + CPOL: packed union { raw: u1, - value: COSEL, + value: CPOL, }, - /// Output polarity - POL: packed union { + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: packed union { + raw: u2, + value: STOP, + }, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level inversion + RXINV: u1, + /// TX pin active level inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: packed union { raw: u1, - value: POL, + value: MSBFIRST, + }, + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: packed union { + raw: u2, + value: ABRMOD, + }, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD: u8, + }), + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: packed union { + raw: u1, + value: IRLP, + }, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity selection + DEP: packed union { + raw: u1, + value: DEP, + }, + reserved17: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag selection + WUS: packed union { + raw: u2, + value: WUS, + }, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1, + /// TXFIFO threshold interrupt enable + TXFTIE: u1, + reserved25: u1, + /// Receive FIFO threshold configuration + RXFTCFG: u3, + /// RXFIFO threshold interrupt enable + RXFTIE: u1, + /// TXFIFO threshold configuration + TXFTCFG: u3, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// USARTDIV + BRR: u16, + padding: u16, + }), + /// Guard time and prescaler register + GTPR: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding: u16, + }), + /// Receiver timeout register + RTOR: mmio.Mmio(packed struct(u32) { + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), + /// Request register + RQR: mmio.Mmio(packed struct(u32) { + /// Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. + ABRRQ: u1, + /// Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available + SBKRQ: u1, + /// Mute mode request. Puts the USART in mute mode and sets the RWU flag. + MMRQ: u1, + /// Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition + RXFRQ: u1, + /// Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data. + TXFRQ: u1, + padding: u27, + }), + /// Interrupt & status register + ISR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved14: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute mode + RWU: packed union { + raw: u1, + value: RWU, + }, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge flag + TEACK: u1, + /// Receive enable acknowledge flag + REACK: u1, + /// TXFIFO Empty + TXFE: u1, + /// RXFIFO Full + RXFF: u1, + reserved26: u1, + /// RXFIFO threshold flag + RXFT: u1, + /// TXFIFO threshold flag + TXFT: u1, + padding: u4, + }), + /// Interrupt flag clear register + ICR: mmio.Mmio(packed struct(u32) { + /// Parity error clear flag + PE: u1, + /// Framing error clear flag + FE: u1, + /// Noise error clear flag + NE: u1, + /// Overrun error clear flag + ORE: u1, + /// Idle line detected clear flag + IDLE: u1, + reserved6: u1, + /// Transmission complete clear flag + TC: u1, + reserved8: u1, + /// LIN break detection clear flag + LBD: u1, + /// CTS clear flag + CTS: u1, + reserved11: u1, + /// Receiver timeout clear flag + RTOF: u1, + /// End of block clear flag + EOBF: u1, + reserved17: u4, + /// Character match clear flag + CMF: u1, + reserved20: u2, + /// Wakeup from Stop mode clear flag + WUF: u1, + padding: u11, + }), + /// Receive data register + RDR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Transmit data register + TDR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Prescaler register + PRESC: mmio.Mmio(packed struct(u32) { + /// Clock prescaler + PRESCALER: packed union { + raw: u4, + value: PRESC, + }, + padding: u28, + }), + }; + }; + + pub const usb_v1 = struct { + pub const DIR = enum(u1) { + /// data transmitted by the USB peripheral to the host PC + To = 0x0, + /// data received by the USB peripheral from the host PC + From = 0x1, + }; + + pub const EP_TYPE = enum(u2) { + /// Bulk endpoint + Bulk = 0x0, + /// Control endpoint + Control = 0x1, + /// Iso endpoint + Iso = 0x2, + /// Interrupt endpoint + Interrupt = 0x3, + }; + + pub const STAT = enum(u2) { + /// all requests addressed to this endpoint are ignored + Disabled = 0x0, + /// the endpoint is stalled and all requests result in a STALL handshake + Stall = 0x1, + /// the endpoint is naked and all requests result in a NAK handshake + Nak = 0x2, + /// this endpoint is enabled, requests are ACKed + Valid = 0x3, + }; + + /// Universal serial bus full-speed device interface + pub const USB = extern struct { + /// endpoint register + EPR: [8]mmio.Mmio(packed struct(u32) { + /// EA + EA: u4, + /// STAT_TX + STAT_TX: packed union { + raw: u2, + value: STAT, }, - /// Output selection - OSEL: packed union { + /// DTOG_TX + DTOG_TX: u1, + /// CTR_TX + CTR_TX: u1, + /// EP_KIND + EP_KIND: u1, + /// EPTYPE + EP_TYPE: packed union { raw: u2, - value: OSEL, + value: EP_TYPE, }, - /// Calibration output enable - COE: u1, - /// Timestamp on internal event enable - ITSE: u1, - /// Activate timestamp on tamper detection event - TAMPTS: u1, - /// Tamper detection output enable on TAMPALRM - TAMPOE: u1, - /// ALRFCLR - ALRFCLR: u1, - reserved29: u1, - /// TAMPALRM pull-up enable - TAMPALRM_PU: u1, - /// TAMPALRM output type - TAMPALRM_TYPE: packed union { - raw: u1, - value: TAMPALRM_TYPE, + /// SETUP + SETUP: u1, + /// STAT_RX + STAT_RX: packed union { + raw: u2, + value: STAT, }, - /// RTC_OUT2 output enable - OUT2EN: u1, - }), - /// Privilege mode control register - PRIVCR: mmio.Mmio(packed struct(u32) { - /// ALRPRIV - ALRPRIV: u1, - reserved2: u1, - /// WUTPRIV - WUTPRIV: u1, - /// TSPRIV - TSPRIV: u1, - reserved13: u9, - /// CALPRIV - CALPRIV: u1, - /// INITPRIV - INITPRIV: u1, - /// PRIV - PRIV: u1, + /// DTOG_RX + DTOG_RX: u1, + /// CTR_RX + CTR_RX: u1, padding: u16, }), - /// Secure mode control register - SECCFGR: mmio.Mmio(packed struct(u32) { - /// ALRASEC - ALRASEC: u1, - /// ALRBSEC - ALRBSEC: u1, - /// WUTSEC - WUTSEC: u1, - /// TSSEC - TSSEC: u1, - reserved13: u9, - /// CALSEC - CALSEC: u1, - /// INITSEC - INITSEC: u1, - /// SEC - SEC: u1, + reserved64: [32]u8, + /// control register + CNTR: mmio.Mmio(packed struct(u32) { + /// Force a reset of the USB peripheral, exactly like a RESET signaling on the USB + FRES: u1, + /// Enter power down mode + PDWN: u1, + /// Enter low-power mode + LPMODE: u1, + /// Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected + FSUSP: u1, + /// Resume request + RESUME: u1, + reserved8: u3, + /// ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + ESOFM: u1, + /// SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + SOFM: u1, + /// RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + RESETM: u1, + /// SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + SUSPM: u1, + /// WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + WKUPM: u1, + /// ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + ERRM: u1, + /// PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + PMAOVRM: u1, + /// CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + CTRM: u1, padding: u16, }), - /// Write protection register - WPR: mmio.Mmio(packed struct(u32) { - /// Write protection key - KEY: packed union { - raw: u8, - value: KEY, - }, - padding: u24, - }), - /// Calibration register - CALR: mmio.Mmio(packed struct(u32) { - /// Calibration minus - CALM: u9, - reserved12: u3, - /// Calibration low-power mode - LPCAL: packed union { - raw: u1, - value: LPCAL, - }, - /// Use a 16-second calibration cycle period - CALW16: packed union { - raw: u1, - value: CALW16, - }, - /// Use an 8-second calibration cycle period - CALW8: packed union { - raw: u1, - value: CALW8, - }, - /// Increase frequency of RTC by 488.5 ppm - CALP: packed union { + /// interrupt status register + ISTR: mmio.Mmio(packed struct(u32) { + /// EP_ID + EP_ID: u4, + /// DIR + DIR: packed union { raw: u1, - value: CALP, + value: DIR, }, + reserved8: u3, + /// an SOF packet is expected but not received + ESOF: u1, + /// beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus + SOF: u1, + /// peripheral detects an active USB RESET signal at its inputs + RESET: u1, + /// no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus + SUSP: u1, + /// activity is detected that wakes up the USB peripheral + WKUP: u1, + /// One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred + ERR: u1, + /// microcontroller has not been able to respond in time to an USB memory request + PMAOVR: u1, + /// endpoint has successfully completed a transaction + CTR: u1, padding: u16, }), - /// Shift control register - SHIFTR: mmio.Mmio(packed struct(u32) { - /// Subtract a fraction of a second - SUBFS: u15, - reserved31: u16, - /// Add one second - ADD1S: u1, + /// frame number register + FNR: mmio.Mmio(packed struct(u32) { + /// FN + FN: u11, + /// LSOF + LSOF: u2, + /// the frame timer remains in this state until an USB reset or USB suspend event occurs + LCK: u1, + /// received data minus upstream port data line + RXDM: u1, + /// received data plus upstream port data line + RXDP: u1, + padding: u16, }), - /// Timestamp time register - TSTR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved8: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved16: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - padding: u9, + /// device address + DADDR: mmio.Mmio(packed struct(u32) { + /// device address + ADD: u7, + /// USB device enabled + EF: u1, + padding: u24, }), - /// Timestamp date register - TSDR: mmio.Mmio(packed struct(u32) { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved8: u2, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, + /// Buffer table address + BTABLE: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// BTABLE + BTABLE: u13, padding: u16, }), - /// Timestamp sub second register - TSSSR: mmio.Mmio(packed struct(u32) { - /// Sub second value - SS: u32, - }), - reserved64: [4]u8, - /// Alarm register - ALRMR: mmio.Mmio(packed struct(u32) { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm A seconds mask - MSK1: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm A minutes mask - MSK2: packed union { - raw: u1, - value: ALRMR_MSK, - }, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: packed union { - raw: u1, - value: ALRMR_PM, - }, - /// Alarm A hours mask - MSK3: packed union { - raw: u1, - value: ALRMR_MSK, + }; + }; + + pub const usb_v2 = struct { + pub const DIR = enum(u1) { + /// data transmitted by the USB peripheral to the host PC + To = 0x0, + /// data received by the USB peripheral from the host PC + From = 0x1, + }; + + pub const EP_TYPE = enum(u2) { + /// Bulk endpoint + Bulk = 0x0, + /// Control endpoint + Control = 0x1, + /// Iso endpoint + Iso = 0x2, + /// Interrupt endpoint + Interrupt = 0x3, + }; + + pub const LPMACK = enum(u1) { + /// the valid LPM Token will be NYET + Nyet = 0x0, + /// the valid LPM Token will be ACK + Ack = 0x1, + }; + + pub const STAT = enum(u2) { + /// all requests addressed to this endpoint are ignored + Disabled = 0x0, + /// the endpoint is stalled and all requests result in a STALL handshake + Stall = 0x1, + /// the endpoint is naked and all requests result in a NAK handshake + Nak = 0x2, + /// this endpoint is enabled, requests are ACKed + Valid = 0x3, + }; + + /// Universal serial bus full-speed device interface + pub const USB = extern struct { + /// endpoint register + EPR: [8]mmio.Mmio(packed struct(u32) { + /// EA + EA: u4, + /// STAT_TX + STAT_TX: packed union { + raw: u2, + value: STAT, }, - /// Date units or day in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: packed union { - raw: u1, - value: ALRMR_WDSEL, + /// DTOG_TX + DTOG_TX: u1, + /// CTR_TX + CTR_TX: u1, + /// EP_KIND + EP_KIND: u1, + /// EPTYPE + EP_TYPE: packed union { + raw: u2, + value: EP_TYPE, }, - /// Alarm A date mask - MSK4: packed union { - raw: u1, - value: ALRMR_MSK, + /// SETUP + SETUP: u1, + /// STAT_RX + STAT_RX: packed union { + raw: u2, + value: STAT, }, + /// DTOG_RX + DTOG_RX: u1, + /// CTR_RX + CTR_RX: u1, + padding: u16, }), - /// Alarm sub second register - ALRMSSR: mmio.Mmio(packed struct(u32) { - /// Sub seconds value - SS: u15, - reserved24: u9, - /// Mask the most-significant bits starting at this bit - MASKSS: u6, - reserved31: u1, - /// Clear synchronous counter on alarm (Binary mode only) - SSCLR: packed union { - raw: u1, - value: ALRMSSR_SSCLR, - }, + reserved64: [32]u8, + /// control register + CNTR: mmio.Mmio(packed struct(u32) { + /// Force a reset of the USB peripheral, exactly like a RESET signaling on the USB + FRES: u1, + /// Enter power down mode + PDWN: u1, + /// Enter low-power mode + LPMODE: u1, + /// Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected + FSUSP: u1, + /// Resume request + RESUME: u1, + /// LPM L1 request request + L1RESUME: u1, + reserved7: u1, + /// L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + L1REQM: u1, + /// ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + ESOFM: u1, + /// SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + SOFM: u1, + /// RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + RESETM: u1, + /// SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + SUSPM: u1, + /// WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + WKUPM: u1, + /// ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + ERRM: u1, + /// PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + PMAOVRM: u1, + /// CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + CTRM: u1, + padding: u16, }), - reserved80: [8]u8, - /// Status register - SR: mmio.Mmio(packed struct(u32) { - /// Alarm flag - ALRF: packed union { - raw: u1, - value: ALRF, - }, - reserved2: u1, - /// Wakeup timer flag - WUTF: packed union { - raw: u1, - value: WUTF, - }, - /// Timestamp flag - TSF: packed union { - raw: u1, - value: TSF, - }, - /// Timestamp overflow flag - TSOVF: packed union { - raw: u1, - value: TSOVF, - }, - /// Internal timestamp flag - ITSF: packed union { - raw: u1, - value: ITSF, - }, - /// SSR underflow flag - SSRUF: packed union { + /// interrupt status register + ISTR: mmio.Mmio(packed struct(u32) { + /// EP_ID + EP_ID: u4, + /// DIR + DIR: packed union { raw: u1, - value: SSRUF, + value: DIR, }, - padding: u25, + reserved7: u2, + /// LPM command to enter the L1 state is successfully received and acknowledged + L1REQ: u1, + /// an SOF packet is expected but not received + ESOF: u1, + /// beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus + SOF: u1, + /// peripheral detects an active USB RESET signal at its inputs + RESET: u1, + /// no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus + SUSP: u1, + /// activity is detected that wakes up the USB peripheral + WKUP: u1, + /// One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred + ERR: u1, + /// microcontroller has not been able to respond in time to an USB memory request + PMAOVR: u1, + /// endpoint has successfully completed a transaction + CTR: u1, + padding: u16, }), - /// Masked interrupt status register - MISR: mmio.Mmio(packed struct(u32) { - /// Alarm masked flag - ALRMF: packed union { - raw: u1, - value: ALRMF, - }, - reserved2: u1, - /// Wakeup timer masked flag - WUTMF: packed union { - raw: u1, - value: WUTMF, - }, - /// Timestamp masked flag - TSMF: packed union { - raw: u1, - value: TSMF, - }, - /// Timestamp overflow masked flag - TSOVMF: packed union { - raw: u1, - value: TSOVMF, - }, - /// Internal timestamp masked flag - ITSMF: packed union { - raw: u1, - value: ITSMF, - }, - /// SSR underflow masked flag - SSRUMF: packed union { - raw: u1, - value: SSRUMF, - }, - padding: u25, + /// frame number register + FNR: mmio.Mmio(packed struct(u32) { + /// FN + FN: u11, + /// LSOF + LSOF: u2, + /// the frame timer remains in this state until an USB reset or USB suspend event occurs + LCK: u1, + /// received data minus upstream port data line + RXDM: u1, + /// received data plus upstream port data line + RXDP: u1, + padding: u16, }), - /// Secure masked interrupt status register - SMISR: mmio.Mmio(packed struct(u32) { - /// Alarm x interrupt secure masked flag - ALRMF: u1, - reserved2: u1, - /// WUTMF - WUTMF: u1, - /// TSMF - TSMF: u1, - /// TSOVMF - TSOVMF: u1, - /// ITSMF - ITSMF: u1, - /// SSRUMF - SSRUMF: u1, - padding: u25, + /// device address + DADDR: mmio.Mmio(packed struct(u32) { + /// device address + ADD: u7, + /// USB device enabled + EF: u1, + padding: u24, }), - /// Status clear register - SCR: mmio.Mmio(packed struct(u32) { - /// Clear alarm x flag - CALRF: packed union { - raw: u1, - value: CALRF, - }, - reserved2: u1, - /// Clear wakeup timer flag - CWUTF: packed union { - raw: u1, - value: CALRF, - }, - /// Clear timestamp flag - CTSF: packed union { - raw: u1, - value: CALRF, - }, - /// Clear timestamp overflow flag - CTSOVF: packed union { - raw: u1, - value: CALRF, - }, - /// Clear internal timestamp flag - CITSF: packed union { - raw: u1, - value: CALRF, - }, - /// Clear SSR underflow flag - CSSRUF: packed union { + /// Buffer table address + BTABLE: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// BTABLE + BTABLE: u13, + padding: u16, + }), + /// LPM control and status register + LPMCSR: mmio.Mmio(packed struct(u32) { + /// enable the LPM support within the USB device + LPMEN: u1, + /// LPMACK + LPMACK: packed union { raw: u1, - value: CALRF, + value: LPMACK, }, - padding: u25, - }), - reserved112: [16]u8, - /// Alarm binary mode register - ALRBINR: [2]mmio.Mmio(packed struct(u32) { - /// Synchronous counter alarm value in Binary mode - SS: u32, + reserved3: u1, + /// REMWAKE + REMWAKE: u1, + /// BESL + BESL: u4, + padding: u24, }), }; }; - pub const adc_f3_v2 = struct { - pub const DISCNUM = enum(u3) { - /// 1 conversions are discontinued and the conversion is carried out on one channel - DISCNUM_1 = 0x0, - /// 2 conversion is discontinued and the conversions are carried out on 2 channels - DISCNUM_2 = 0x1, - /// 3 conversions are discontinued and the conversions are carried out on 3 channels - DISCNUM_3 = 0x2, - /// 4 conversions are discontinued and the conversions are carried out on 4 channels - DISCNUM_4 = 0x3, - /// 5 conversions are discontinued and the conversions are carried out on 5 channels - DISCNUM_5 = 0x4, - /// 6 conversions are discontinued and the conversions are carried out on 6 channels - DISCNUM_6 = 0x5, - /// 7 conversions are discontinued and the conversions are carried out on 7 channels - DISCNUM_7 = 0x6, - /// 8 conversions are discontinued and the conversions are carried out on 8 channels - DISCNUM_8 = 0x7, + pub const usb_v3 = struct { + pub const DIR = enum(u1) { + /// data transmitted by the USB peripheral to the host PC + To = 0x0, + /// data received by the USB peripheral from the host PC + From = 0x1, }; - pub const SAMPLE_TIME = enum(u3) { - /// 1.5 ADC clock cycles - Cycles1_5 = 0x0, - /// 7.5 ADC clock cycles - Cycles7_5 = 0x1, - /// 13.5 ADC clock cycles - Cycles13_5 = 0x2, - /// 28.5 ADC clock cycles - Cycles28_5 = 0x3, - /// 41.5 ADC clock cycles - Cycles41_5 = 0x4, - /// 55.5 ADC clock cycles - Cycles55_5 = 0x5, - /// 71.5 ADC clock cycles - Cycles71_5 = 0x6, - /// 239.5 ADC clock cycles - Cycles239_5 = 0x7, + pub const EP_TYPE = enum(u2) { + /// Bulk endpoint + Bulk = 0x0, + /// Control endpoint + Control = 0x1, + /// Iso endpoint + Iso = 0x2, + /// Interrupt endpoint + Interrupt = 0x3, }; - /// Analog-to-Digital Converter - pub const ADC = extern struct { - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// analog watchdog flag - AWD: u1, - /// end of conversion - EOC: u1, - /// injected channel end of conversion - JEOC: u1, - /// injected channel start flag - JSTRT: u1, - /// regular channel start flag - STRT: u1, - /// overrun - OVR: u1, - padding: u26, - }), - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - /// analog watchdog channel select bits - AWDCH: u5, - /// interrupt enable for EOC - EOCIE: u1, - /// analog watchdog interrupt enable - AWDIE: u1, - /// interrupt enable for injected channels - JEOCIE: u1, - /// scan mode - SCAN: u1, - /// enable the watchdog on a single channel in scan mode - AWDSGL: u1, - /// automatic injected group conversion - JAUTO: u1, - /// discontinuous mode on regular channels - DISCEN: u1, - /// discontinuous mode on injected channels - JDISCEN: u1, - /// discontinuous mode channel count - DISCNUM: packed union { - raw: u3, - value: DISCNUM, - }, - reserved22: u6, - /// analog watchdog enable on injected channels - JAWDEN: u1, - /// analog watchdog enable on regular channels - AWDEN: u1, - padding: u8, - }), - /// control register 2 - CR2: mmio.Mmio(packed struct(u32) { - /// A/D converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - /// A/D calibration - CAL: u1, - /// reset calibration - RSTCAL: u1, - reserved8: u4, - /// DMA disable selection (for single ADC mode) - DMA: u1, - reserved11: u2, - /// data alignment - ALIGN: u1, - /// external event select for injected group - JEXTSEL: u3, - /// external trigger conversion mode for injected channels - JEXTTRIG: u1, - reserved17: u1, - /// external event select for regular group - EXTSEL: u3, - /// external trigger conversion mode for regular channels - EXTTRIG: u1, - /// start conversion of injected channels - JSWSTART: u1, - /// start conversion of regular channels - SWSTART: u1, - /// temperature sensor and VREFINT enable - TSVREFE: u1, - padding: u8, - }), - /// sample time register 1 - SMPR1: mmio.Mmio(packed struct(u32) { - /// channel 10 sampling time selection - SMP10: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 11 sampling time selection - SMP11: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 12 sampling time selection - SMP12: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 13 sampling time selection - SMP13: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 14 sampling time selection - SMP14: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 15 sampling time selection - SMP15: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 16 sampling time selection - SMP16: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 17 sampling time selection - SMP17: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 18 sampling time selection - SMP18: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - padding: u5, - }), - /// sample time register 2 - SMPR2: mmio.Mmio(packed struct(u32) { - /// channel 0 sampling time selection - SMP0: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 1 sampling time selection - SMP1: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 2 sampling time selection - SMP2: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 3 sampling time selection - SMP3: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 4 sampling time selection - SMP4: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 5 sampling time selection - SMP5: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 6 sampling time selection - SMP6: packed union { - raw: u3, - value: SAMPLE_TIME, - }, - /// channel 7 sampling time selection - SMP7: packed union { - raw: u3, - value: SAMPLE_TIME, + pub const LPMACK = enum(u1) { + /// the valid LPM Token will be NYET + Nyet = 0x0, + /// the valid LPM Token will be ACK + Ack = 0x1, + }; + + pub const SDET = enum(u1) { + /// CDP detected + CDP = 0x0, + /// DCP detected + DCP = 0x1, + }; + + pub const STAT = enum(u2) { + /// all requests addressed to this endpoint are ignored + Disabled = 0x0, + /// the endpoint is stalled and all requests result in a STALL handshake + Stall = 0x1, + /// the endpoint is naked and all requests result in a NAK handshake + Nak = 0x2, + /// this endpoint is enabled, requests are ACKed + Valid = 0x3, + }; + + /// Universal serial bus full-speed device interface + pub const USB = extern struct { + /// endpoint register + EPR: [8]mmio.Mmio(packed struct(u32) { + /// EA + EA: u4, + /// STAT_TX + STAT_TX: packed union { + raw: u2, + value: STAT, }, - /// channel 8 sampling time selection - SMP8: packed union { - raw: u3, - value: SAMPLE_TIME, + /// DTOG_TX + DTOG_TX: u1, + /// CTR_TX + CTR_TX: u1, + /// EP_KIND + EP_KIND: u1, + /// EPTYPE + EP_TYPE: packed union { + raw: u2, + value: EP_TYPE, }, - /// channel 9 sampling time selection - SMP9: packed union { - raw: u3, - value: SAMPLE_TIME, + /// SETUP + SETUP: u1, + /// STAT_RX + STAT_RX: packed union { + raw: u2, + value: STAT, }, - padding: u2, - }), - /// injected channel data offset register 1 - JOFR1: mmio.Mmio(packed struct(u32) { - /// data offset for injected channel 1 - JOFFSET1: u12, - padding: u20, - }), - /// injected channel data offset register 2 - JOFR2: mmio.Mmio(packed struct(u32) { - /// data offset for injected channel 2 - JOFFSET2: u12, - padding: u20, - }), - /// injected channel data offset register 3 - JOFR3: mmio.Mmio(packed struct(u32) { - /// data offset for injected channel 3 - JOFFSET3: u12, - padding: u20, - }), - /// injected channel data offset register 4 - JOFR4: mmio.Mmio(packed struct(u32) { - /// data offset for injected channel 4 - JOFFSET4: u12, - padding: u20, - }), - /// watchdog higher threshold register - HTR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog high threshold - HT: u12, - padding: u20, - }), - /// watchdog lower threshold register - LTR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog low threshold - LT: u12, - padding: u20, - }), - /// regular sequence register 1 - SQR1: mmio.Mmio(packed struct(u32) { - /// 13th conversion in regular sequence - SQ13: u5, - /// 14th conversion in regular sequence - SQ14: u5, - /// 15th conversion in regular sequence - SQ15: u5, - /// 16th conversion in regular sequence - SQ16: u5, - /// regular channel sequence length - L: u4, - padding: u8, - }), - /// regular sequence register 2 - SQR2: mmio.Mmio(packed struct(u32) { - /// 7th conversion in regular sequence - SQ7: u5, - /// 8th conversion in regular sequence - SQ8: u5, - /// 9th conversion in regular sequence - SQ9: u5, - /// 10th conversion in regular sequence - SQ10: u5, - /// 11th conversion in regular sequence - SQ11: u5, - /// 12th conversion in regular sequence - SQ12: u5, - padding: u2, - }), - /// regular sequence register 3 - SQR3: mmio.Mmio(packed struct(u32) { - /// 1st conversion in regular sequence - SQ1: u5, - /// 2nd conversion in regular sequence - SQ2: u5, - /// 3rd conversion in regular sequence - SQ3: u5, - /// 4th conversion in regular sequence - SQ4: u5, - /// 5th conversion in regular sequence - SQ5: u5, - /// 6th conversion in regular sequence - SQ6: u5, - padding: u2, - }), - /// injected sequence register - JSQR: mmio.Mmio(packed struct(u32) { - /// 1st conversion in injected sequence - JSQ1: u5, - /// 2nd conversion in injected sequence - JSQ2: u5, - /// 3rd conversion in injected sequence - JSQ3: u5, - /// 4th conversion in injected sequence - JSQ4: u5, - /// injected sequence length - JL: u2, - padding: u10, + /// DTOG_RX + DTOG_RX: u1, + /// CTR_RX + CTR_RX: u1, + padding: u16, }), - /// injected data register 1 - JDR1: mmio.Mmio(packed struct(u32) { - /// Injected data - JDATA1: u16, + reserved64: [32]u8, + /// control register + CNTR: mmio.Mmio(packed struct(u32) { + /// Force a reset of the USB peripheral, exactly like a RESET signaling on the USB + FRES: u1, + /// Enter power down mode + PDWN: u1, + /// Enter low-power mode + LPMODE: u1, + /// Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected + FSUSP: u1, + /// Resume request + RESUME: u1, + /// LPM L1 request request + L1RESUME: u1, + reserved7: u1, + /// L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + L1REQM: u1, + /// ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + ESOFM: u1, + /// SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + SOFM: u1, + /// RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + RESETM: u1, + /// SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + SUSPM: u1, + /// WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + WKUPM: u1, + /// ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + ERRM: u1, + /// PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + PMAOVRM: u1, + /// CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + CTRM: u1, padding: u16, }), - /// injected data register 2 - JDR2: mmio.Mmio(packed struct(u32) { - /// Injected data - JDATA2: u16, + /// interrupt status register + ISTR: mmio.Mmio(packed struct(u32) { + /// EP_ID + EP_ID: u4, + /// DIR + DIR: packed union { + raw: u1, + value: DIR, + }, + reserved7: u2, + /// LPM command to enter the L1 state is successfully received and acknowledged + L1REQ: u1, + /// an SOF packet is expected but not received + ESOF: u1, + /// beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus + SOF: u1, + /// peripheral detects an active USB RESET signal at its inputs + RESET: u1, + /// no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus + SUSP: u1, + /// activity is detected that wakes up the USB peripheral + WKUP: u1, + /// One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred + ERR: u1, + /// microcontroller has not been able to respond in time to an USB memory request + PMAOVR: u1, + /// endpoint has successfully completed a transaction + CTR: u1, padding: u16, }), - /// injected data register 3 - JDR3: mmio.Mmio(packed struct(u32) { - /// Injected data - JDATA3: u16, + /// frame number register + FNR: mmio.Mmio(packed struct(u32) { + /// FN + FN: u11, + /// LSOF + LSOF: u2, + /// the frame timer remains in this state until an USB reset or USB suspend event occurs + LCK: u1, + /// received data minus upstream port data line + RXDM: u1, + /// received data plus upstream port data line + RXDP: u1, padding: u16, }), - /// injected data register 4 - JDR4: mmio.Mmio(packed struct(u32) { - /// Injected data - JDATA4: u16, + /// device address + DADDR: mmio.Mmio(packed struct(u32) { + /// device address + ADD: u7, + /// USB device enabled + EF: u1, + padding: u24, + }), + /// Buffer table address + BTABLE: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// BTABLE + BTABLE: u13, padding: u16, }), - /// regular data register - DR: mmio.Mmio(packed struct(u32) { - /// Regular data - DATA: u16, + /// LPM control and status register + LPMCSR: mmio.Mmio(packed struct(u32) { + /// enable the LPM support within the USB device + LPMEN: u1, + /// LPMACK + LPMACK: packed union { + raw: u1, + value: LPMACK, + }, + reserved3: u1, + /// REMWAKE + REMWAKE: u1, + /// BESL + BESL: u4, + padding: u24, + }), + /// Battery Charging Detector + BCDR: mmio.Mmio(packed struct(u32) { + /// Battery charging detector mode enable + BCDEN: u1, + /// Data contact detection mode enable + DCDEN: u1, + /// Primary detection mode enable + PDEN: u1, + /// Secondary detection mode enable + SDEN: u1, + /// Data contact detection status + DCDET: u1, + /// Primary detection status + PDET: u1, + /// Secondary detection status + SDET: packed union { + raw: u1, + value: SDET, + }, + /// DM pull-up detection status + PS2DET: u1, + reserved15: u7, + /// DP pull-up control + DPPU: u1, padding: u16, }), }; }; - pub const fsmc_v3x1 = struct { - pub const ACCMOD = enum(u2) { - /// Access mode A - A = 0x0, - /// Access mode B - B = 0x1, - /// Access mode C - C = 0x2, - /// Access mode D - D = 0x3, - }; - - pub const CPSIZE = enum(u3) { - /// No burst split when crossing page boundary - NoBurstSplit = 0x0, - /// 128 bytes CRAM page size - Bytes128 = 0x1, - /// 256 bytes CRAM page size - Bytes256 = 0x2, - /// 512 bytes CRAM page size - Bytes512 = 0x3, - /// 1024 bytes CRAM page size - Bytes1024 = 0x4, - _, - }; - - pub const ECCPS = enum(u3) { - /// ECC page size 256 bytes - Bytes256 = 0x0, - /// ECC page size 512 bytes - Bytes512 = 0x1, - /// ECC page size 1024 bytes - Bytes1024 = 0x2, - /// ECC page size 2048 bytes - Bytes2048 = 0x3, - /// ECC page size 4096 bytes - Bytes4096 = 0x4, - /// ECC page size 8192 bytes - Bytes8192 = 0x5, - _, - }; - - pub const MTYP = enum(u2) { - /// SRAM memory type - SRAM = 0x0, - /// PSRAM (CRAM) memory type - PSRAM = 0x1, - /// NOR Flash/OneNAND Flash - Flash = 0x2, - _, - }; - - pub const MWID = enum(u2) { - /// Memory data bus width 8 bits - Bits8 = 0x0, - /// Memory data bus width 16 bits - Bits16 = 0x1, - /// Memory data bus width 32 bits - Bits32 = 0x2, - _, + pub const usb_v4 = struct { + pub const DIR = enum(u1) { + /// data transmitted by the USB peripheral to the host PC + To = 0x0, + /// data received by the USB peripheral from the host PC + From = 0x1, }; - pub const PTYP = enum(u1) { - /// NAND Flash - NANDFlash = 0x1, - _, + pub const EP_TYPE = enum(u2) { + /// Bulk endpoint + Bulk = 0x0, + /// Control endpoint + Control = 0x1, + /// Iso endpoint + Iso = 0x2, + /// Interrupt endpoint + Interrupt = 0x3, }; - pub const PWID = enum(u2) { - /// External memory device width 8 bits - Bits8 = 0x0, - /// External memory device width 16 bits - Bits16 = 0x1, - _, + pub const LPMACK = enum(u1) { + /// The valid LPM Token will be NYET / NYET answer + Nyet = 0x0, + /// The valid LPM Token will be ACK / ACK answer + Ack = 0x1, }; - pub const WAITCFG = enum(u1) { - /// NWAIT signal is active one data cycle before wait state - BeforeWaitState = 0x0, - /// NWAIT signal is active during wait state - DuringWaitState = 0x1, + pub const SDET = enum(u1) { + /// CDP detected + CDP = 0x0, + /// DCP detected + DCP = 0x1, }; - pub const WAITPOL = enum(u1) { - /// NWAIT active low - ActiveLow = 0x0, - /// NWAIT active high - ActiveHigh = 0x1, + pub const STAT = enum(u2) { + /// all requests addressed to this endpoint are ignored + Disabled = 0x0, + /// the endpoint is stalled and all requests result in a STALL handshake + Stall = 0x1, + /// the endpoint is naked and all requests result in a NAK handshake + Nak = 0x2, + /// this endpoint is enabled, requests are ACKed + Valid = 0x3, }; - /// Flexible static memory controller - pub const FSMC = extern struct { - /// SRAM/NOR-Flash chip-select control register 1 - BCR1: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { + /// Universal serial bus full-speed host/device interface + pub const USB = extern struct { + /// endpoint/channel + EPR: [8]mmio.Mmio(packed struct(u32) { + /// endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + EA: u4, + /// Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be VALID or DISABLED. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to STALL or NAK for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC) + STAT_TX: packed union { raw: u2, - value: MTYP, + value: STAT, }, - /// Memory data bus width - MWID: packed union { + /// Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1. + DTOG_TX: u1, + /// Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions. + CTR_TX: u1, + /// endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + EP_KIND: u1, + /// USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers + EP_TYPE: packed union { raw: u2, - value: MWID, + value: EP_TYPE, }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { - raw: u1, - value: WAITPOL, + /// Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + SETUP: u1, + /// Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALL or 'NAK for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate. + STAT_RX: packed union { + raw: u2, + value: STAT, }, - reserved11: u1, - /// Wait timing configuration - WAITCFG: packed union { + /// Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + DTOG_RX: u1, + /// USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect. + CTR_RX: u1, + /// Host mode Device address assigned to the endpoint during the enumeration process. + DEVADDR: u7, + /// Host mode This bit is set by the hardware when a device responds with a NAK. Software can be use this bit to monitoring the number of NAKs received from a device. + NAK: u1, + /// Low speed endpoint Host with HUB only Host mode This bit is set by the software to send an LS transaction to the corresponding endpoint. + LS_EP: u1, + /// Transmit error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. + ERR_TX: u1, + /// Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. + ERR_RX: u1, + padding: u5, + }), + reserved64: [32]u8, + /// control register + CNTR: mmio.Mmio(packed struct(u32) { + /// Force a reset of the USB peripheral, exactly like a RESET signaling on the USB + FRES: u1, + /// Power down This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used. + PDWN: u1, + /// Suspend state effective This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wakeup logic and single ended receiver is kept alive to detect remote wakeup or resume events. Software must poll this bit to confirm it to be set before any STOP mode entry. This bit is cleared by hardware simultaneously to the WAKEUP flag being set. + LPMODE: u1, + /// Suspend state enable Device mode Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3 ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to purse more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY=1 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Host mode Software can set this bit when Host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to purse more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. + FSUSP: u1, + /// L2 Remote Wakeup / Resume driver Device mode The microcontroller can set this bit to send remote wake-up signaling to the Host. It must be activated, according to USB specifications, for no less than 1ms and no more than 15ms after which the Host PC is ready to drive the resume sequence up to its end. Host mode Software sets this bit to send resume signaling to the device. Software clears this bit to send end of resume to device and restart SOF generation. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. + RESUME: u1, + /// L1 Remote Wakeup / Resume driver Device mode Software sets this bit to send a LPM L1 50us remote wakeup signaling to the host. After the signaling ends, this bit is cleared by hardware. Host mode Software sets this bit to send L1 resume signaling to device. Resume duration and next SOF generation is automatically driven to set the restart of USB activity timely aligned with the programmed BESL value. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. This bit is cleared by hardware at the end of resume. + L1RESUME: u1, + reserved7: u1, + /// LPM L1 state request interrupt mask + L1REQM: u1, + /// Expected start of frame interrupt mask + ESOFM: u1, + /// Start of frame interrupt mask + SOFM: u1, + /// reset interrupt mask + RESETM: u1, + /// Suspend mode interrupt mask + SUSPM: u1, + /// Wakeup interrupt mask + WKUPM: u1, + /// Error interrupt mask + ERRM: u1, + /// Packet memory area over / underrun interrupt mask + PMAOVRM: u1, + /// CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set + CTRM: u1, + /// 512 byte threshold interrupt mask + THR512M: u1, + reserved31: u14, + /// HOST mode HOST bit selects betweens Host or Device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit. + HOST: u1, + }), + /// interrupt status register + ISTR: mmio.Mmio(packed struct(u32) { + /// Device Endpoint / Host channel identification number These bits are written by the hardware according to the host channel or device endpoint number, which generated the interrupt request. If several endpoint/channel transactions are pending, the hardware writes the identification number related to the endpoint/channel having the highest priority defined in the following way: Two levels are defined, in order of priority: Isochronous and double-buffered bulk channels/endpoints are considered first and then the others are examined. If more than one endpoint/channel from the same set is requesting an interrupt, the IDN bits in USB_ISTR register are assigned according to the lowest requesting register, CHEP0R having the highest priority followed by CHEP1R and so on. The application software can assign a register to each endpoint/channel according to this priority scheme, so as to order the concurring endpoint/channel requests in a suitable way. These bits are read only. + EP_ID: u4, + /// Direction of transaction This bit is written by the hardware according to the direction of the successful transaction, which generated the interrupt request. If DIR bit=0, VTTX bit is set in the USB_EPnR register related to the interrupting endpoint. The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host PC). If DIR bit=1, VTRX bit or both VTTX/VTRX are set in the USB_EPnR register related to the interrupting endpoint. The interrupting transaction is of OUT type (data received by the USB peripheral from the host PC) or two pending transactions are waiting to be processed. This information can be used by the application software to access the USB_EPnR bits related to the triggering transaction since it represents the direction having the interrupt pending. This bit is read-only. + DIR: packed union { raw: u1, - value: WAITCFG, - }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - /// CRAM page size - CPSIZE: packed union { - raw: u3, - value: CPSIZE, + value: DIR, }, - /// Write burst enable - CBURSTRW: u1, - /// Continuous clock enable - CCLKEN: u1, - /// Write FIFO disable - WFDIS: u1, - padding: u10, + reserved7: u2, + /// LPM L1 state request This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. This bit is read/write but only '0 can be written and writing '1 has no effect. + L1REQ: u1, + /// Expected start of frame This bit is set by the hardware when an SOF packet is expected but not received. The host sends an SOF packet each 1 ms, but if the device does not receive it properly, the Suspend Timer issues this interrupt. If three consecutive ESOF interrupts are generated (i.e. three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the missing SOF packets occur while the Suspend Timer is not yet locked. This bit is read/write but only '0 can be written and writing '1 has no effect. + ESOF: u1, + /// Start of frame This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 1 ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this could be useful for isochronous applications). This bit is read/write but only '0 can be written and writing '1 has no effect. + SOF: u1, + /// reset request Device mode This bit is set by hardware when an USB reset is released by the host and the bus returns to idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles. Host mode This bit is set by hardware when device connection or device disconnection is detected. Device connection is signaled after J state is sampled for 22cycles consecutively from unconnected state. Device disconnection is signaled after SE0 state is sampled for 22cycles consecutively from connected state. + RESET: u1, + /// Suspend mode request This bit is set by the hardware when no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only '0 can be written and writing '1 has no effect. + SUSP: u1, + /// Wakeup This bit is set to 1 by the hardware when, during suspend mode, activity is detected that wakes up the USB peripheral. This event asynchronously clears the LP_MODE bit in the CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of the device (e.g. wakeup unit) about the start of the resume process. This bit is read/write but only '0 can be written and writing '1 has no effect. + WKUP: u1, + /// Error This flag is set whenever one of the errors listed below has occurred: NANS: No ANSwer. The timeout for a host response has expired. CRC: Cyclic Redundancy Check error. One of the received CRCs, either in the token or in the data, was wrong. BST: Bit Stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or CRC. FVIO: Framing format Violation. A non-standard frame was received (EOP not in the right place, wrong token sequence, etc.). The USB software can usually ignore errors, since the USB peripheral and the PC host manage retransmission in case of errors in a fully transparent way. This interrupt can be useful during the software development phase, or to monitor the quality of transmission over the USB bus, to flag possible problems to the user (e.g. loose connector, too noisy environment, broken conductor in the USB cable and so on). This bit is read/write but only '0 can be written and writing '1 has no effect. + ERR: u1, + /// Packet memory area over / underrun This bit is set if the microcontroller has not been able to respond in time to an USB memory request. The USB peripheral handles this event in the following way: During reception an ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the transmitted stream; in both cases the host will retry the transaction. The PMAOVR interrupt should never occur during normal operations. Since the failed transaction is retried by the host, the application software has the chance to speed-up device operations during this interrupt handling, to be ready for the next transaction retry; however this does not happen during Isochronous transfers (no isochronous transaction is anyway retried) leading to a loss of data in this case. This bit is read/write but only '0 can be written and writing '1 has no effect. + PMAOVR: u1, + /// Correct transfer This bit is set by the hardware to indicate that an endpoint/channel has successfully completed a transaction; using DIR and EP_ID bits software can determine which endpoint/channel requested the interrupt. This bit is read-only. + CTR: u1, + /// 512 byte threshold interrupt This bit is set to 1 by the hardware when 512 bytes have been transmitted or received during isochronous transfers. This bit is read/write but only 0 can be written and writing 1 has no effect. Note that no information is available to indicate the associated channel/endpoint, however in practice only one ISO endpoint/channel with such large packets can be supported, so that channel. + THR512: u1, + reserved29: u12, + /// Device connection status Host mode: This bit contains information about device connection status. It is set by hardware when a LS/FS device is attached to the host while it is reset when the device is disconnected. + DCON_STAT: u1, + /// Low Speed device connected Host mode: This bit is set by hardware when an LS device connection is detected. Device connection is signaled after LS J-state is sampled for 22 consecutive cycles of the USB clock (48 MHz) from the unconnected state. + LS_DCON: u1, + padding: u1, }), - /// SRAM/NOR-Flash chip-select timing register 1-4 - BTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - /// Clock divide ratio (for FMC_CLK signal) - CLKDIV: u4, - /// Data latency for synchronous memory - DATLAT: u4, - /// Access mode - ACCMOD: packed union { - raw: u2, - value: ACCMOD, + /// frame number register + FNR: mmio.Mmio(packed struct(u32) { + /// Frame number This bit field contains the 11-bits frame number contained in the last received SOF packet. The frame number is incremented for every frame sent by the host and it is useful for Isochronous transfers. This bit field is updated on the generation of an SOF interrupt. + FN: u11, + /// Lost SOF Device mode These bits are written by the hardware when an ESOF interrupt is generated, counting the number of consecutive SOF packets lost. At the reception of an SOF packet, these bits are cleared. + LSOF: u2, + /// Locked Device mode This bit is set by the hardware when at least two consecutive SOF packets have been received after the end of an USB reset condition or after the end of an USB resume sequence. Once locked, the frame timer remains in this state until an USB reset or USB suspend event occurs. + LCK: u1, + /// Receive data - line status This bit can be used to observe the status of received data minus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event. + RXDM: u1, + /// Receive data + line status This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event. + RXDP: u1, + padding: u16, + }), + /// device address + DADDR: mmio.Mmio(packed struct(u32) { + /// Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel Address (EA) field in the associated USB_EPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction + ADD: u7, + /// Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD[6:0] bits. If this bit is at '0 no transactions are handled, irrespective of the settings of USB_EPnR registers. + EF: u1, + padding: u24, + }), + reserved84: [4]u8, + /// LPM control and status register + LPMCSR: mmio.Mmio(packed struct(u32) { + /// LPM support enable Device mode This bit is set by the software to enable the LPM support within the USB device. If this bit is at '0 no LPM transactions are handled. Host mode Software sets this bit to transmit an LPM transaction to device. This bit is cleared by hardware, simultaneous with L1REQ flag set, when device answer is received + LPMEN: u1, + /// LPM Token acknowledge enable The NYET/ACK will be returned only on a successful LPM transaction: No errors in both the EXT token and the LPM token (else ERROR) A valid bLinkState = 0001B (L1) is received (else STALL) This bit contains the device answer to the LPM transaction. It mast be evaluated following the L1REQ interrupt. + LPMACK: packed union { + raw: u1, + value: LPMACK, }, - padding: u2, + reserved3: u1, + /// bRemoteWake value Device mode This bit contains the bRemoteWake value received with last ACKed LPM Token Host mode This bit contains the bRemoteWake value transmitted with the LPM transaction + REMWAKE: u1, + /// BESL value Device mode These bits contain the BESL value received with last ACKed LPM Token Host mode These bits contain the BESL value transmitted with the LPM transaction + BESL: u4, + padding: u24, }), - /// SRAM/NOR-Flash chip-select control register 2-4 - BCR: mmio.Mmio(packed struct(u32) { - /// Memory bank enable bit - MBKEN: u1, - /// Address/data multiplexing enable bit - MUXEN: u1, - /// Memory type - MTYP: packed union { - raw: u2, - value: MTYP, + /// Battery charging detector + BCDR: mmio.Mmio(packed struct(u32) { + /// Battery charging detector (BCD) enable Device mode This bit is set by the software to enable the BCD support within the USB device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD should be placed in OFF mode by clearing this bit to '0 in order to allow the normal USB operation. + BCDEN: u1, + /// Data contact detection (DCD) mode enable Device mode This bit is set by the software to put the BCD into DCD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. + DCDEN: u1, + /// Primary detection (PD) mode enable Device mode This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. + PDEN: u1, + /// Secondary detection (SD) mode enable Device mode This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. + SDEN: u1, + /// Data contact detection (DCD) status Device mode This bit gives the result of DCD. + DCDET: u1, + /// Primary detection (PD) status Device mode This bit gives the result of PD. + PDET: u1, + /// Secondary detection (SD) status Device mode This bit gives the result of SD. + SDET: packed union { + raw: u1, + value: SDET, }, - /// Memory data bus width - MWID: packed union { - raw: u2, - value: MWID, + /// DM pull-up detection status Device mode This bit is active only during PD and gives the result of comparison between DM voltage level and VLGC threshold. In normal situation, the DM level should be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification. + PS2DET: u1, + reserved15: u7, + /// DP pull-up / DPDM pull-down Device mode This bit is set by software to enable the embedded pull-up on DP line. Clearing it to '0 can be used to signal disconnect to the host when needed by the user software. Host mode This bit is set by software to enable the embedded pull-down on DP and DM lines. + DPPU: u1, + padding: u16, + }), + }; + }; + + pub const usbram_16x1_512 = struct { + /// USB Endpoint memory + pub const USBRAM = extern struct { + /// USB Endpoint memory + MEM: [256]u32, + }; + }; + + pub const usbram_16x2_1024 = struct { + /// USB Endpoint memory + pub const USBRAM = extern struct { + /// USB Endpoint memory + MEM: u32, + }; + }; + + pub const usbram_16x2_512 = struct { + /// USB Endpoint memory + pub const USBRAM = extern struct { + /// USB Endpoint memory + MEM: u32, + }; + }; + + pub const usbram_32_1024 = struct { + /// USB Endpoint memory + pub const USBRAM = extern struct { + /// USB Endpoint memory + MEM: [256]u32, + }; + }; + + pub const usbram_32_2048 = struct { + /// USB Endpoint memory + pub const USBRAM = extern struct { + /// USB Endpoint memory + MEM: [512]u32, + }; + }; + + pub const vrefbuf_v1 = struct { + pub const HIZ = enum(u1) { + /// VREF+ pin is internally connected to the voltage reference buffer output. + Connected = 0x0, + /// VREF+ pin is high impedance. + HighZ = 0x1, + }; + + pub const VRS = enum(u1) { + /// Voltage reference set to VREF_OUT1 (around 2.048 V). + Vref0 = 0x0, + /// Voltage reference set to VREF_OUT2 (around 2.5 V). + Vref1 = 0x1, + }; + + /// Voltage reference buffer. + pub const VREFBUF = extern struct { + /// control and status register. + CSR: mmio.Mmio(packed struct(u32) { + /// Voltage reference buffer mode enable. + ENVR: u1, + /// High impedance mode. + HIZ: packed union { + raw: u1, + value: HIZ, }, - /// Flash access enable - FACCEN: u1, - reserved8: u1, - /// Burst enable bit - BURSTEN: u1, - /// Wait signal polarity bit - WAITPOL: packed union { + /// Voltage reference scale. + VRS: packed union { raw: u1, - value: WAITPOL, + value: VRS, }, - reserved11: u1, - /// Wait timing configuration - WAITCFG: packed union { + /// Voltage reference buffer ready. + VRR: u1, + padding: u28, + }), + /// calibration control register. + CCR: mmio.Mmio(packed struct(u32) { + /// Trimming code. + TRIM: u6, + padding: u26, + }), + }; + }; + + pub const vrefbuf_v2a1 = struct { + pub const HIZ = enum(u1) { + /// VREF+ pin is internally connected to the voltage reference buffer output. + Connected = 0x0, + /// VREF+ pin is high impedance. + HighZ = 0x1, + }; + + pub const VRS = enum(u3) { + /// Voltage reference set to VREF_OUT1 (around 2.048 V). + Vref0 = 0x0, + /// Voltage reference set to VREF_OUT2 (around 2.5 V). + Vref1 = 0x1, + /// Voltage reference set to VREF_OUT2 (around 2.5 V). + Vref2 = 0x2, + /// Voltage reference set to VREF_OUT2 (around 2.5 V). + Vref3 = 0x3, + _, + }; + + /// Voltage reference buffer. + pub const VREFBUF = extern struct { + /// VREFBUF control and status register. + CSR: mmio.Mmio(packed struct(u32) { + /// Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. + ENVR: u1, + /// High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration. + HIZ: packed union { raw: u1, - value: WAITCFG, + value: HIZ, }, - /// Write enable bit - WREN: u1, - /// Wait enable bit - WAITEN: u1, - /// Extended mode enable - EXTMOD: u1, - /// Wait signal during asynchronous transfers - ASYNCWAIT: u1, - /// CRAM page size - CPSIZE: packed union { + reserved3: u1, + /// Voltage reference buffer ready. + VRR: u1, + /// Voltage reference scale These bits select the value generated by the voltage reference buffer. VRS = 000: VREFBUF0 voltage selected. VRS = 001: VREFBUF1 voltage selected. VRS = 010: VREFBUF2 voltage selected. VRS = 011: VREFBUF3 voltage selected. Others: Reserved Note: Refer to the product datasheet for each VREFBUFx voltage setting value. The software can program this bitfield only when the VREFBUF is disabled (ENVR=0). + VRS: packed union { raw: u3, - value: CPSIZE, + value: VRS, }, - /// Write burst enable - CBURSTRW: u1, - padding: u12, + padding: u25, }), - reserved128: [116]u8, - /// PC Card/NAND Flash control register - PCR: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Wait feature enable bit - PWAITEN: u1, - /// NAND Flash memory bank enable bit - PBKEN: u1, - /// Memory type - PTYP: packed union { + /// VREFBUF calibration control register. + CCR: mmio.Mmio(packed struct(u32) { + /// Trimming code The TRIM code is a 6-bit unsigned data (minimum 000000, maximum 111111) that is set and updated according the mechanism described below. Reset: TRIM[5:0] is automatically initialized with the VRS = 0 trimming value stored in the Flash memory during the production test. VRS change: TRIM[5:0] is automatically initialized with the trimming value (corresponding to VRS setting) stored in the Flash memory during the production test. Write in TRIM[5:0]: User can modify the TRIM[5:0] with an arbitrary value. This is permanently disabling the control of the trimming value with VRS (until the device is reset). Note: If the user application performs the trimming, the trimming code must start from 000000 to 111111 in ascending order. + TRIM: u6, + padding: u26, + }), + }; + }; + + pub const vrefbuf_v2a2 = struct { + pub const HIZ = enum(u1) { + /// VREF+ pin is internally connected to the voltage reference buffer output. + Connected = 0x0, + /// VREF+ pin is high impedance. + HighZ = 0x1, + }; + + pub const VRS = enum(u3) { + /// Voltage reference set to VREF_OUT1 (around 2.048 V). + Vref0 = 0x0, + /// Voltage reference set to VREF_OUT2 (around 2.5 V). + Vref1 = 0x1, + /// Voltage reference set to VREF_OUT2 (around 2.5 V). + Vref2 = 0x2, + _, + }; + + /// Voltage reference buffer. + pub const VREFBUF = extern struct { + /// VREFBUF control and status register. + CSR: mmio.Mmio(packed struct(u32) { + /// Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. + ENVR: u1, + /// High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration. + HIZ: packed union { raw: u1, - value: PTYP, - }, - /// Data bus width - PWID: packed union { - raw: u2, - value: PWID, + value: HIZ, }, - /// ECC computation logic enable bit - ECCEN: u1, - reserved9: u2, - /// CLE to RE delay - TCLR: u4, - /// ALE to RE delay - TAR: u4, - /// ECC page size - ECCPS: packed union { + reserved3: u1, + /// Voltage reference buffer ready. + VRR: u1, + /// Voltage reference scale These bits select the value generated by the voltage reference buffer. VRS = 000: VREFBUF0 voltage selected. VRS = 001: VREFBUF1 voltage selected. VRS = 010: VREFBUF2 voltage selected. VRS = 011: VREFBUF3 voltage selected. Others: Reserved Note: Refer to the product datasheet for each VREFBUFx voltage setting value. The software can program this bitfield only when the VREFBUF is disabled (ENVR=0). + VRS: packed union { raw: u3, - value: ECCPS, + value: VRS, }, - padding: u12, - }), - /// FIFO status and interrupt register - SR: mmio.Mmio(packed struct(u32) { - /// Interrupt rising edge status - IRS: u1, - /// Interrupt high-level status - ILS: u1, - /// Interrupt falling edge status - IFS: u1, - /// Interrupt rising edge detection enable bit - IREN: u1, - /// Interrupt high-level detection enable bit - ILEN: u1, - /// Interrupt falling edge detection enable bit - IFEN: u1, - /// FIFO empty status - FEMPT: u1, padding: u25, }), - /// Common memory space timing register - PMEM: mmio.Mmio(packed struct(u32) { - /// Common memory x setup time - MEMSET: u8, - /// Common memory wait time - MEMWAIT: u8, - /// Common memory hold time - MEMHOLD: u8, - /// Common memory x data bus Hi-Z time - MEMHIZ: u8, - }), - /// Attribute memory space timing register - PATT: mmio.Mmio(packed struct(u32) { - /// Attribute memory setup time - ATTSET: u8, - /// Attribute memory wait time - ATTWAIT: u8, - /// Attribute memory hold time - ATTHOLD: u8, - /// Attribute memory data bus Hi-Z time - ATTHIZ: u8, - }), - reserved148: [4]u8, - /// ECC result register - ECCR: mmio.Mmio(packed struct(u32) { - /// ECC computation result value - ECC: u32, + /// VREFBUF calibration control register. + CCR: mmio.Mmio(packed struct(u32) { + /// Trimming code The TRIM code is a 6-bit unsigned data (minimum 000000, maximum 111111) that is set and updated according the mechanism described below. Reset: TRIM[5:0] is automatically initialized with the VRS = 0 trimming value stored in the Flash memory during the production test. VRS change: TRIM[5:0] is automatically initialized with the trimming value (corresponding to VRS setting) stored in the Flash memory during the production test. Write in TRIM[5:0]: User can modify the TRIM[5:0] with an arbitrary value. This is permanently disabling the control of the trimming value with VRS (until the device is reset). Note: If the user application performs the trimming, the trimming code must start from 000000 to 111111 in ascending order. + TRIM: u6, + padding: u26, }), - reserved260: [108]u8, - /// SRAM/NOR-Flash write timing registers 1-4 - BWTR: mmio.Mmio(packed struct(u32) { - /// Address setup phase duration - ADDSET: u4, - /// Address-hold phase duration - ADDHLD: u4, - /// Data-phase duration - DATAST: u8, - /// Bus turnaround phase duration - BUSTURN: u4, - reserved28: u8, - /// Access mode - ACCMOD: packed union { + }; + }; + + pub const vrefbuf_v2b = struct { + pub const HIZ = enum(u1) { + /// VREF+ pin is internally connected to the voltage reference buffer output. + Connected = 0x0, + /// VREF+ pin is high impedance. + HighZ = 0x1, + }; + + pub const VRS = enum(u2) { + /// Voltage reference set to VREF_OUT1 (around 2.048 V). + Vref0 = 0x0, + /// Voltage reference set to VREF_OUT2 (around 2.5 V). + Vref1 = 0x1, + /// Voltage reference set to VREF_OUT2 (around 2.5 V). + Vref2 = 0x2, + _, + }; + + /// Voltage reference buffer. + pub const VREFBUF = extern struct { + /// VREF_BUF Control and Status Register. + CSR: mmio.Mmio(packed struct(u32) { + /// Enable Voltage Reference. + ENVR: u1, + /// High impedence mode for the VREF_BUF. + HIZ: packed union { + raw: u1, + value: HIZ, + }, + reserved3: u1, + /// Voltage reference buffer ready. + VRR: u1, + /// Voltage reference scale. + VRS: packed union { raw: u2, - value: ACCMOD, + value: VRS, }, - padding: u2, + padding: u26, + }), + /// VREF_BUF Calibration Control Register. + CCR: mmio.Mmio(packed struct(u32) { + /// Trimming code. + TRIM: u6, + padding: u26, }), }; }; - pub const flash_f4 = struct { - pub const LATENCY = enum(u4) { - /// 0 wait states - WS0 = 0x0, - /// 1 wait states - WS1 = 0x1, - /// 2 wait states - WS2 = 0x2, - /// 3 wait states - WS3 = 0x3, - /// 4 wait states - WS4 = 0x4, - /// 5 wait states - WS5 = 0x5, - /// 6 wait states - WS6 = 0x6, - /// 7 wait states - WS7 = 0x7, - /// 8 wait states - WS8 = 0x8, - /// 9 wait states - WS9 = 0x9, - /// 10 wait states - WS10 = 0xa, - /// 11 wait states - WS11 = 0xb, - /// 12 wait states - WS12 = 0xc, - /// 13 wait states - WS13 = 0xd, - /// 14 wait states - WS14 = 0xe, - /// 15 wait states - WS15 = 0xf, + pub const vrefintcal_v1 = struct { + /// VREFINT Factory Calibration + pub const VREFINTCAL = extern struct { + /// Factory calibration + DATA: u32, }; + }; - pub const PSIZE = enum(u2) { - /// Program x8 - PSIZE8 = 0x0, - /// Program x16 - PSIZE16 = 0x1, - /// Program x32 - PSIZE32 = 0x2, - /// Program x64 - PSIZE64 = 0x3, + pub const wwdg_v1 = struct { + pub const WDGTB = enum(u2) { + /// Counter clock (PCLK1 div 4096) div 1 + Div1 = 0x0, + /// Counter clock (PCLK1 div 4096) div 2 + Div2 = 0x1, + /// Counter clock (PCLK1 div 4096) div 4 + Div4 = 0x2, + /// Counter clock (PCLK1 div 4096) div 8 + Div8 = 0x3, }; - /// FLASH - pub const FLASH = extern struct { - /// Flash access control register - ACR: mmio.Mmio(packed struct(u32) { - /// Latency - LATENCY: packed union { - raw: u4, - value: LATENCY, + /// Window watchdog + pub const WWDG = extern struct { + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// 7-bit counter (MSB to LSB) + T: u7, + /// Watchdog activated + WDGA: u1, + padding: u24, + }), + /// Configuration register + CFR: mmio.Mmio(packed struct(u32) { + /// 7-bit window value + W: u7, + /// Timer base + WDGTB: packed union { + raw: u2, + value: WDGTB, }, - reserved8: u4, - /// Prefetch enable - PRFTEN: u1, - /// Instruction cache enable - ICEN: u1, - /// Data cache enable - DCEN: u1, - /// Instruction cache reset - ICRST: u1, - /// Data cache reset - DCRST: u1, - padding: u19, + /// Early wakeup interrupt + EWI: u1, + padding: u22, }), - /// Flash key register - KEYR: u32, - /// Flash option key register - OPTKEYR: u32, /// Status register SR: mmio.Mmio(packed struct(u32) { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved4: u2, - /// Write protection error - WRPERR: u1, - /// Programming alignment error - PGAERR: u1, - /// Programming parallelism error - PGPERR: u1, - /// Programming sequence error - PGSERR: u1, - reserved16: u8, - /// Busy - BSY: u1, - padding: u15, + /// Early wakeup interrupt flag + EWIF: u1, + padding: u31, }), + }; + }; + + pub const wwdg_v2 = struct { + pub const WDGTB = enum(u3) { + /// Counter clock (PCLK1 div 4096) div 1 + Div1 = 0x0, + /// Counter clock (PCLK1 div 4096) div 2 + Div2 = 0x1, + /// Counter clock (PCLK1 div 4096) div 4 + Div4 = 0x2, + /// Counter clock (PCLK1 div 4096) div 8 + Div8 = 0x3, + /// Counter clock (PCLK1 div 4096) div 16 + Div16 = 0x4, + /// Counter clock (PCLK1 div 4096) div 32 + Div32 = 0x5, + /// Counter clock (PCLK1 div 4096) div 64 + Div64 = 0x6, + /// Counter clock (PCLK1 div 4096) div 128 + Div128 = 0x7, + }; + + /// Window watchdog + pub const WWDG = extern struct { /// Control register CR: mmio.Mmio(packed struct(u32) { - /// Programming - PG: u1, - /// Sector Erase - SER: u1, - /// Mass Erase - MER: u1, - /// Sector number - SNB: u5, - /// Program size - PSIZE: packed union { - raw: u2, - value: PSIZE, + /// 7-bit counter (MSB to LSB) + T: u7, + /// Activation bit (true is enabled, false is disabled) + WDGA: u1, + padding: u24, + }), + /// Configuration register + CFR: mmio.Mmio(packed struct(u32) { + /// 7-bit window value + W: u7, + reserved9: u2, + /// Early wakeup interrupt + EWI: u1, + reserved11: u1, + /// Timer base + WDGTB: packed union { + raw: u3, + value: WDGTB, }, - reserved16: u6, - /// Start - STRT: u1, - reserved24: u7, - /// End of operation interrupt enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - reserved31: u5, - /// Lock - LOCK: u1, + padding: u18, }), - /// Flash option control register - OPTCR: mmio.Mmio(packed struct(u32) { - /// Option lock - OPTLOCK: u1, - /// Option start - OPTSTRT: u1, - /// BOR reset Level - BOR_LEV: u2, - reserved5: u1, - /// WDG_SW User option bytes - WDG_SW: u1, - /// nRST_STOP User option bytes - nRST_STOP: u1, - /// nRST_STDBY User option bytes - nRST_STDBY: u1, - /// Read protect - RDP: u8, - /// Not write protect - nWRP: u12, - reserved30: u2, - /// Dual-bank enable on 1 Mbyte Flash memory devices - DB1M: u1, - /// Selection of protection mode for nWPRi bits - SPRMOD: u1, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Early wakeup interrupt flag + EWIF: u1, + padding: u31, }), }; }; diff --git a/port/stmicro/stm32/src/generate.zig b/port/stmicro/stm32/src/generate.zig index 21edaf9f..d2db658f 100644 --- a/port/stmicro/stm32/src/generate.zig +++ b/port/stmicro/stm32/src/generate.zig @@ -357,7 +357,7 @@ pub fn main() !void { const device_id = try db.create_device(.{ .name = chip_file.value.name, // TODO - .arch = std.meta.stringToEnum(regz.Database.Arch, core_to_microzig_cpu.get(core.name).?).?, + .arch = std.meta.stringToEnum(regz.Database.Arch, core_to_cpu.get(core.name).?).?, }); try regz.arm.load_system_interrupts(&db, device_id); @@ -397,7 +397,7 @@ pub fn main() !void { } } - const chips_file = try std.fs.cwd().createFile("src/chips.zig", .{}); + const chips_file = try std.fs.cwd().createFile("src/Chips.zig", .{}); defer chips_file.close(); try generate_chips_file(chips_file.writer(), chip_files.items); @@ -411,7 +411,7 @@ pub fn main() !void { }; } -const core_to_microzig_cpu = std.StaticStringMap([]const u8).initComptime(&.{ +const core_to_cpu = std.StaticStringMap([]const u8).initComptime(&.{ .{ "cm0", "cortex_m0" }, .{ "cm0p", "cortex_m0plus" }, .{ "cm3", "cortex_m3" }, @@ -423,64 +423,94 @@ const core_to_microzig_cpu = std.StaticStringMap([]const u8).initComptime(&.{ fn generate_chips_file(writer: anytype, chip_files: []const std.json.Parsed(ChipFile)) !void { try writer.writeAll( \\const std = @import("std"); - \\const MicroZig = @import("microzig/build"); + \\const microzig = @import("microzig/build-internals"); + \\ + \\const Self = @This(); + \\ + \\ + ); + + for (chip_files) |json| { + const chip_file = json.value; + try writer.print("{}: *microzig.Target,\n", .{std.zig.fmtId(chip_file.name)}); + } + + try writer.writeAll( + \\ + \\pub fn init(dep: *std.Build.Dependency) Self { + \\ const b = dep.builder; + \\ const register_definition_path = b.path("src/chips/all.zig"); + \\ + \\ var ret: Self = undefined; \\ - \\fn root() []const u8 { - \\ return comptime (std.fs.path.dirname(@src().file) orelse "."); - \\} - \\const build_root = root(); - \\pub const register_definition_path = build_root ++ "/chips/all.zig"; \\ ); for (chip_files) |json| { const chip_file = json.value; const core = chip_file.cores[0]; - var microzig_core_name = core_to_microzig_cpu.get(chip_file.cores[0].name) orelse { - std.log.err("Unhandled core name: '{s}'", .{core.name}); - return error.UnhandledCoreName; - }; + + const fpu_feature = std.StaticStringMap([]const u8).initComptime(&.{ + .{ "cm4", "vfp4d16sp" }, + .{ "cm7", "fp_armv8d16sp" }, + .{ "cm33", "vfp4d16sp" }, + }); + + var with_fpu = false; for (core.interrupts) |item| { if (std.mem.indexOf(u8, item.name, "FPU")) |_| { - const Case = enum { cm4, cm7, cm33, none }; - const case = std.meta.stringToEnum(Case, core.name) orelse defaultblk: { - std.log.warn("Found core with FPU interrupt, but don't have a target with FPU", .{}); - break :defaultblk .none; - }; - switch (case) { - .cm4 => { - microzig_core_name = "cortex_m4f"; - }, - .cm7 => { - microzig_core_name = "cortex_m7f"; - }, - .cm33 => { - microzig_core_name = "cortex_m33f"; - }, - else => {}, - } + with_fpu = true; break; } } try writer.print( - \\ - \\pub const {} = MicroZig.Target{{ - \\ .preferred_format = .elf, - \\ .chip = .{{ - \\ .name = "{s}", - \\ .cpu = MicroZig.cpus.{s}, - \\ .memory_regions = &.{{ + \\ ret.{} = b.allocator.create(microzig.Target) catch @panic("out of memory"); + \\ ret.{}.* = .{{ + \\ .dep = dep, + \\ .preferred_binary_format = .elf, + \\ .chip = .{{ + \\ .name = "{s}", + \\ .cpu = .{{ + \\ .cpu_arch = .thumb, + \\ .cpu_model = .{{ .explicit = &std.Target.arm.cpu.{s} }}, + \\ .os_tag = .freestanding, \\ , .{ + std.zig.fmtId(chip_file.name), std.zig.fmtId(chip_file.name), chip_file.name, - microzig_core_name, + core_to_cpu.get(core.name).?, }); + if (with_fpu) { + try writer.print( + \\ .cpu_features_add = std.Target.arm.featureSet(&.{{.{s}}}), + \\ .abi = .eabihf, + \\ }}, + \\ + , .{ + fpu_feature.get(core.name).?, + }); + } else { + try writer.writeAll( + \\ .abi = .eabi, + \\ }, + \\ + ); + } + + try writer.writeAll( + \\ .register_definition = .{ + \\ .zig = register_definition_path, + \\ }, + \\ .memory_regions = &.{ + \\ + ); + for (chip_file.memory) |memory| { try writer.print( - \\ .{{ .offset = 0x{X}, .length = 0x{X}, .kind = .{s} }}, + \\ .{{ .offset = 0x{X}, .length = 0x{X}, .kind = .{s} }}, \\ , .{ memory.address, memory.size, switch (memory.kind) { .flash => "flash", @@ -489,30 +519,33 @@ fn generate_chips_file(writer: anytype, chip_files: []const std.json.Parsed(Chip } try writer.writeAll( + \\ }, \\ }, - \\ .register_definition = .{ - \\ .zig = .{ .cwd_relative = register_definition_path }, - \\ }, - \\ }, \\ ); - // For now + // TODO: Better system to detect if hal is present. if (std.mem.startsWith(u8, chip_file.name, "STM32F103")) { try writer.writeAll( - \\ .hal = .{ - \\ .root_source_file = .{ .cwd_relative = build_root ++ "/hals/STM32F103/hal.zig" }, - \\ }, + \\ .hal = .{ + \\ .root_source_file = b.path("src/hals/STM32F103/hal.zig"), + \\ }, \\ - , ); } try writer.writeAll( - \\}; + \\ }; + \\ \\ ); } + + try writer.writeAll( + \\ return ret; + \\} + \\ + ); } fn chip_file_less_than(_: void, lhs: std.json.Parsed(ChipFile), rhs: std.json.Parsed(ChipFile)) bool { diff --git a/build/src/generate_linkerscript.zig b/tools/generate_linker_script.zig similarity index 98% rename from build/src/generate_linkerscript.zig rename to tools/generate_linker_script.zig index 0652cf75..f2fe124a 100644 --- a/build/src/generate_linkerscript.zig +++ b/tools/generate_linker_script.zig @@ -1,6 +1,5 @@ const std = @import("std"); -const defs = @import("microzig/build/definitions"); -const MemoryRegion = defs.MemoryRegion; +const MemoryRegion = @import("build-internals").MemoryRegion; pub const Args = struct { cpu_name: []const u8,